This document, the "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer’s Manual (Order Number: EK–D3SYS–PM. B01)," serves as a comprehensive guide for design engineers and programmers developing system-level software, such as operating systems and drivers, for the DEC 3000 AXP family of workstations.
The manual provides detailed information on the hardware architecture and its behavior, covering a wide range of topics essential for low-level programming:
- System Overview: Describes the components and variations among the different DEC 3000 AXP models.
- Memory and I/O Addressing: Explains address maps (memory and I/O), methods for I/O space addressing (dense and sparse space), and critical CPU and TURBOchannel interface registers.
- Hardware Components & Registers: Details the functionality and programming of key ASICs like the Address ASIC (for memory configuration and caching), CXTurbo Graphics Subsystem (for 300/500 models), IOCTL ASIC (managing various I/O devices like Ethernet, serial ports, ISDN, RTC), and the TURBOchannel Dual SCSI ASIC.
- I/O Programming Considerations: Discusses restrictions, DMA capabilities (physical and virtual), interrupt handling, and system-specific TURBOchannel usage.
- Hardware Exceptions and Interrupts: Explains sources of errors and interrupts, system behavior under errors, error/interrupt matrices, and PALcode recovery algorithms.
- Power Up and Initialization: Outlines the processor and Bcache initialization sequences, firmware entry points, and the contents of various firmware ROMs (SROM, SYSROM).
- System Configuration: Describes the Main Configuration Table and Device Configuration Tables, which store information about system devices.
- Console: Provides extensive information on the console device, its commands, data structures, and service routines for system control and diagnostics.
- Nonvolatile RAM (NVR): Details the NVR's structure and its use for storing system settings like boot flags and security information.
The document is a critical resource for understanding the intricate hardware and firmware interactions required for robust system-level software development on these Alpha AXP-based systems.