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Document:	Firefox Bus Interface Chip Specification
Order Number:	MISC-683639F9
Revision:	0
Pages:	76
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OCR Text

Firefox Bus Interface Chip Specification
Revision 3.0

Tom Dewey (DECWSE::DEWEY)
Joe Minacapelli (DECWSE::M/NACAPELLI)
Michael Nielsen (DECWSE::NIELSEN)
Workstation Systems Engineering
Digital Equipment Corporation
100 Hamilton Avenue
Palo Alto, CA 94301

415 -853-6718

December 30, 1987

RESTRICTED DISTRIBUTION

Copyright 1986, 1987 by Digital Equipment Corporation
The infonnation in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for
any errors that may occur in this document. 1bis specification does not describe any program or product
which is currently available from Digital Equipment Corporation. Nor does Digital Equipment Corporation commit to implement this specification in any product or program. Digital Equipment Corporation
makes no commitment that this document accurately describes any product it might ever make.

Blank Page

Table of Contents

5. Firefox Bus Interface Chip

5.1. Architecture .....................................................................................................................

5 .1.1. FBI C Configurations . ... .. .. ... .... .. . ... .. .. .. .. .... .. ... .. .. ... .. .. .. ... ..... .. .. .... . ... .. .. .. ... .. . .. .. .. . .
5.1.2. Cache Consistency ..............................................................................................
5.1.3. On-Chip Single-Entry Snoopy Cache .................................................................
5.1.4. External Snoopy Cache .. .. ....... ... .. ... .. .. ............ ..... ....... ... ............ .. ... ....... .. ... .. ......

2
3
4
4

5.1.4.1. Cache Read ......................................................................................................
5.1.4.2. Cache Write .....................................................................................................
5.1.4.3. Victim Processing and Cache Fill ....................................................................
5.1.4.4. Shared Read .....................................................................................................
5.1.4.5. Shared Write ....................................................................................................

5
5
6
6

5.1.5. Interlocked Transactions .....................................................................................
5.1.6. S~ Processor Registers ....................................................................................
5.1.7. I/0-Interrupt Masking .......................................................... , , .........................
5 .1.8. Interprocessor/Device Interrupts ................................... ................................. ... .
5.1.9. M-bus 1/0-Space Range Decoder .......................................................................
5.1.10. Status-Indicator Outputs ...................................................................................
5.1.11. Manufacturing-Mode Inputs .............................................................................
5.1.12. FBIC Support for Diagnostic/Self-test ROM ...................................................
5.1.13. CV AX Pin-Bus Timeout Detection ..................................................................
5.1.14. M-bus Module-Type Identification ...................................................................
5.1.15. FBIC Error Detection and Logging ..................................................................
5.1.16. Diagnostic Function Testing .............................................................................
5.1.17. Firefox 1/0-Space Mapping ..............................................................................
5.1.18. FBIC I/0-Space Address Mapping ...................................................................
5.1.19. FBIC Registers ..................................................................................................

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6
7
7
7
7
8
8
8
8
8
9
9
13
14

5.1.19.1. MODTYPE Register ......................................................................................
5.1.19.2. BUSCSR Register ..........................................................................................
5.1.19.3. BUSCIL Register ..........................................................................................
5.1.19.4. BUSADR Register .........................................................................................
. 5.1.19.5. BUSDAT Register .........................................................................................
. ·5.1.19.6. FBICSR Register ...........................................................................................
5.1.19.7. RANGE Register ...........................................................................................
5.1.19.8. IPDVINT Register .........................................................................................
5.1.19.9. WHAMl Register ...........................................................................................
5.1.19.10. CPUID Register ...........................................................................................
5.1.19.11. IADRl Register ...........................................................................................
5.1.19.12. IADR2 Register ..................... .....................................................................
5.1.19.13. SAVGPR Register .......................................................................................

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31
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lll

5.2. Interface ...........................................................................................................................

5.2.0.1. CV AX Pin-Bus Pinout Group ..........................................................................

5.2.0.1.1. CDAL<31:0>--Data/Address Lines .............................................................
5.2.0.1.2. CCSDP<3:0>--Cycle Status/Data Parity ......................................................
5.2.0.1.3. CDPE<O>--Data-Parity Enable ....................................................................
5.2.0.1.4. CAS<O>--Add.ress Strobe .............................................................................
5.2.0.1.5. CDS<O>--Data Strobe ..................................................................................
5.2.0.1.6. CBM<3:0>--Byte Mask ................................................................................
5.2.0.1.7. CWR<O>--Write ...........................................................................................
5.2.0.1.8. CRDY<O>--Ready ........................................................................................
5.2.0.l.9. CERR<O>--Error ..........................................................................................
5.2.0.1.10. CCCTL<O>--Cache Control .......................................................................
5.2.0.1.11. CD?vfR.<0>--DMA Request ........................................................................
5.2.0.1.12. CDMG<O>--DMA Grailt ............................................................................
5.2.0.1.13. CRESET<O>--Synchronous RESET ..........................................................
5.2.0.1.14. SYSRESET<O>--Asynchronous RESET ...................................................
5.2.0.1.15. CHALT<O>--HALT ...................................................................................
5.2.0.1.16. CIRQ<3:0>--Interrupt Requests .................................................................
5 .2.0.1.17. CRD<O>--Corrected Read Data ............. ............... ............ ............ .............
5.2.0.1.18. ME~R<O>--Memory Error ...................................................................
5.2.0.1.19. CCLKA<O>, CCLKB<O>, CCLKC<O>--Oocks A. B, and C ...................

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43

5.2.0.2. M-Bus Pinout Group ........................................................................................

5.2.0.2.1 . .MBRM<6:0>--Request Monitor ...................................................................
5.2.0.2.2 . .MBRP<O>--Partner Request Monitor ...........................................................
5.2.0.2.3. MYMBRQ<O>--Request Output ..................................................................
5.2.0.2.4 . .MBUSYI<O>/MBUSYO«>>--.MBUSY Input/Output .................................
5.2.0.2.5. MC:MD<3:0>-Transaction Command .........................................................
5.2.0.2.6. MSTATUS<l:O>--Transaction Status ..........................................................
5.2.0.2.7. MDAL<31:0>--Transaction Data/Address ..................................................
5.2.0.2.8. MCPAR<O>--Transaction Command Parity ................................................
5.2.0.2.9. MSPAR<O>--Transaction Status Parity .......................................................
5.2.0.2.10. MDPAR<O>--Transaction Data/Address Parity .........................................
5.2.0.2.11. MCDRV<O>--TransactionCommandDrive ..............................................
5.2.0.2.12. MSDRV<O>--Transaction Status Drive .....................................................
5.2.0.2.13. MDDRV<O>--Transaction Data/Address Drive ........................................
5.2.0.2.14. MSHAREDI<O>/MSHAREDO<O>--MSHARED Input/Output ...............
5.2.0.2.15. MDATINVl<O>/MDATINVO<O>--MDATINV Input/Output .................
5.2.0.2.16. WD<2:0>--Module ID ...............................................................................
5.2.0.2.17. ~E"I'<O>--System Reset ......................................................................
, 5.2.0.2.18. MABORTI<O>/MABORTO<O>--MABORT Input/Output ......................
·5.2.0.2.19. MIRQI<3:0>/MIRQ0<3:0>--lnterrupt Requests .......................................
5.2.0.2.20. ~T<O>--Processor Halt .....................................................................
5.2.0.2.21. MCLK.A<O>--Clock-A Phase .....................................................................
5.2.0.2.22. MCLKB<O>--Clock-B Phase .....................................................................

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5.2.0.3. Cache-Control Pinout Group ...........................................................................

5.2.0.3.1. TCACHE<l2:0>--Tag Cache .......................................................................
5.2.0.3.2. TAGSH<O>--Tag Shared .............................................................................
5.2.0.3.3. TAGDR<O>--Tag Diny ................................................................................

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5.2.0.3 .4. T AGPAR <0>--Tag-Cache Parity ............................................................... ..

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5.2.0.3.5. T AGWE<O>--Tag-Cache Write Enable ...................................................... .
5.2.0.3.6. TAGCE<O>--Tag-Cache Chip Enable ........................................................ .
5.2.0.3.7. DATCE<3:0>--Data-Cache Chip Enable ................................................... ..
5.2.0.3.8. DATWE<O>--Data-Cache Write Enable ................................................... ..
5.2.0.3.9. XOE<O>--Data-Cache Transceiver Output Enable ..................................... .
5.2.0.3.10. ECL<O>--Data-Cache Counter Enable ...................................................... .
5.2.0.3.11. CTINDX_OE<O>--CV AX Pin-Bus Tag-Index Output Enable ................ .
5.2.0.3.12. MTINDX_LE<O>--M-Bus Tag-Index Latch Enable ................................ .
5.2.03.13. MTINDX_OE<O>--M-Bus Tag-Index Output Enable ............................. ..

..47,

5.2.0.4. Miscellaneous Pinout Group ........................................................................... .

5.2.0.4.1. MODCL<l:O>--Module Class ..................................................................... .
5.2.0.4.2. TYPDUAL<O>--Dual-FBIC Module .......................................................... .
5.2.0.4.3. TYPAGNTE<O>--A/B Processor or CVAX Pin-Bus Grantee ................... .
5.2.0.4.4. TYPRET<O>--CVAX Pin-Bus Retriable ................................................... ..
5.2.0.4.5. TYPSYNC<O>--CVAX Pin-Bus Synchronous .......................................... ..
5.2.0.4.6. DEVIRQ<3:0>--Device-Intenupt Requests ................................................ .
5.2.0.4.7. ROMOE<O>--Extemal-ROM Output Enable ............................................. .
5.2.0.4.8. ROMWID32<0>--Extemal-ROM Width .................................................... .
5.2.0.4.9. ROMWADDR<O>--Extemal-ROM Word Address .................................... .
5.2.0.4.10. MNFMOD--Manufacturing Mode
5.2.0.4.11. LEDS<O>--LEDs Value ............................................................................ .
5 .2.0.4.12. TESTOlJT<0>--Test Output ..................................................................... .
5.2.0.4.13. TRISTA TE<O>--Tristate All FBIC Pins ................................................... .

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5.3. FBIC Transactions .......................................................................................................... .

5.3.1. CVAX Pin-Bus Transactions ............................................................................. .

5.3.1.1. Read ................................................................................................................ .
5.3.1.2. Write ............................................................................................................... .
5.3.1.3. External-Cache Miss ....................................................................................... .
5.3.1.4. External-Cache Victim-Read Transaction ...................................................... .
5.3.1.5. External-Cache Fill ......................................................................................... .
5.3.1.6. External-Cache Shared-Read .......................................................................... .
5.3.1.7. External-Cache Data-Write-Through Update ................................................. .
5.3.1.8. 16-Bit-ROM Read Transaction ....................................................................... .
5.3.1.9. 32-Bit-ROM Read Transaction ....................................................................... .

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5.3.2. M-bus Transactions .......................................................................................... ..

5.4. FBIC Performance During System Use ......................................................................... ..

5.5. Testability and System Diagnostic Support .................................................................... .

5.6. DC Characteristics ......................................................................................................... ..

5.6.1. Absolute Maximum Ratings .............................................................................. .
5.6.2. Electrical Oiaracteristics ................................................................................... .

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5.7. AC Characteristics ........................................................................................................ ..

5.7.1. M-bus AC Characteristics ................................................................................. ..

A""I

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5.7.2. CVAX pin-bus AC Characteristics .....................................................................

5.8. Package Diagram and Pin Assignment ............................................................................

Revision History
I Date
: 2 Dec 87

Version
3.0

Content/Changes
Update to reflect final FBIC design
Changed CV AX target cycle time to 70ns
Changed ROM maximum access time to 200ns
Changed CV AX pin-bus miss to assert CDMR before CRDY and CERR
Removed assertion of COPE during ROM reads
Removed reference to M-bus access to tag store in I/O space
Reduced number status-indicator bits to 6 bits
Added SERR and DBLE error bits to BUSCTL
Removed Diagnostic Test Functions 12 and 13
Swapped IPUNIT and DEVUNIT bits in IPDVINT register
Added CCLKC pin
Added DATWE pin
Added XOE pin
Added ECL pin
Removed TYPNOMEM pin
Reduced CRD Y and CERR to single pin signals
Changed bidirectional MIRQ<3:0> to :MIRQl<3:0>/MIRQ0<3:0> pins
Added performance section
Added DC characteristics
Added AC characteristics for CV AX pin-bus
Added package pinout and pin assignment section

\ 30 Apr 87

2.0

Expanded functional description
Reorganized registers
Updated pinout and pin descriptions
Added CVAX pin-bus timing diagrams
Added local 1/0 space

: 30 Jan 87

1.1

Integrated with System Specifications
Added EPR access to WHAMI, CPUID, SAVGPR registers
Removed internal data cache parity
Added :MRESET to RESET synchronization
Added programmable RESET

) 10 Jan 87

1.0

Fust external release

! 20Dec 86

0.0

Preliminary draft

vii

Blank Page

viii

5. Firefox Bus Interface Chip

Tilis chapter, the design specification of the Firefox Bus Interface Chip (FBIC), describes the functionality
of that chip. The FBIC is an LSI Logic, "Sea Of Gates" 1.5-micron gate array, and is packaged in a 223pin PGA. The chip that is used in the Firefox Workstation to interface to the processor bus (CV AX pinbus), the system bus (M-bus), and the per-processor, level-2 cache. This specification describes the external
behavior and interface of the chip for designers and systems programmers; it does not describe internal
operation of the chip. The reader is assumed to be familiar with the Firefox M-Bus Specification, the CVAX
CPU Chip Engineering Specification, and the Firefox System Specification.
The FBIC is a niple-poned, multipurpose, bus-interface and cache controller. Figure 5-1 shows the FBIC
in a processor configuration with its CVAX pin-bus, M-bus, and level-2 snoopy cache tag-store pons. The
FBIC functions as both a CVAX pin-bus master and a CVAX pin-bus slave, depending on the needs of the
particular module on which it resides. It also supports the M-bus write-back cache protocol defined in the
Firefox System Specification. On modules that support external caches, the FBIC provides cache control.
On modules that communicate with main memory, but do not support level-2 caches, the FBIC contains an
on-chip, single-entry, level-2 snoopy cache.

CVAX

C-bus '-----~1 Data store

Tagston:

1Transceivers

~
M-bus
Figure 5-1:

Trtpa..Ported FBIC Diagram

There are· two separately clocked, synchronous state machines on the FBIC. The CVAX pin-bus synchronous machine monitors and initiates transactions on the local CVAX pin-bus. The M-bus synchronous
state machine monitors and initiates transactions on the system M-bus. 1be same level-2 cache is used during accesses from either bus port. CVAX pin-bus transactions requiring cache tag compares are timemultiplexed with higher-priority accesses to the M-bus synchronous state machine. This ensures systemwide data consistency. On-chip synchronization circuits allow the two state machines to communicate
across time domains.

5 .1. Firefox Bus Interface Chip

December 30, 1987

Firefox System Spccificat1on l

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5.1. Architecture
The FBIC is intended for use on all Firefox modules that require an interface between the CVAX pin-bus
and M-bus. An FBIC monitors local CV AX pin-bus accesses and M-bus memory and I/0-space accesses
and responds appropriately to requests from either bus. Support functions performed by the FBIC for the
module on which it resides include the following:

•

Snoopy-cache management

•
•
•
•
•
•
•
•
•
•
•
•

Interlocked transactions
Sl\1P processor registers
1/0-interrupt masking
Interprocessor/device interrupts
1/0-space range decoding
6-bit status-indicator output
2-bit manufacturing-mode input
16/32-bit ROM control
CVAX pin-bus timeout detection
M-bus module-type identification
M-bus error detection and error logging
Diagnostic function testing

The snoopy-cache-controller portion of the FBIC is used on CVAX processor modules that participate in
the Firefox S:MP architecture. For 1/0 modules that perlorm OMA in global memory space, the FBIC also
implements a single-entry, on-chip snoopy cache.
5.1.1. FBIC Configurations

The FBIC supports the following configurations when used as a CVAX pin-bus to M-bus interlace:
•

Single- or dual-processor module

•

Synchronous or asynchronous CVAX pin-bus based 1/0-module

•

Arbiter or auxiliary on CVAX pin-bus based I/0-module

•

Retriable or nonretriable CVAX pin-bus based 1/0-module

Table 5-1 lists the supported FBIC configurations as determined by the TYP pins.

2 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.l.l.

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Table 5-1:

Supported FBIC configurations

Typsync
0
0
0
0

Typdual

0
0
0
0

1
1
0
0
0
0
1

Typagnte
0
0

Typret
0
1
0

0
0

l
0
0

1
0
0
1
l

1
0
1
0
1
0
1
0
1
0
1

Configuration
Bus adapter class (CQBIC)
Bus adapter class (CQBIC)
Unsupported
Unsupported
Unsupported
Unsupported
Unsupported
Unsupported
I/O class
1/0 class
Graphics class
Graphics class
Unsupported
CPU class (B processor)
Unsupported
CPU class (A processor)

The FBIC can be used on single- or dual-processor modules. The FBIC TYPDUAL input pin detennines
whether the FBIC operates in single- or dual-processor mode. On dual-processor modules, the FBIC supports M-bus subarbitration between the two FBICs on the module and jointly manages a single set of Mbus transceivers and buffers. In addition, the two FBICs share the 32-Mbyte, slot-specific, I/0-space
region as two 16-Mbyte halves. The FBIC TYPAGNTE input pin determines whether a dual processor
operates as the A or B processor.
The FBIC can be used on synchronous or asynchronous CVAX pin-busses on 1/0 modules. The FBIC
TYPSYNC input pin specifies whether the FBIC is on a synchronous or an asynchronous CVAX pin-bus.
On a synchronous CVAX pin-bus, the FBIC synchronously samples/asserts CAS, COAL, and
CRDY/CERR but does not monitor CDS. On an asynchronous CVAX pin-bus, the FBIC treats CAS and
CDS as asynchronous strobes for COAL, with full handshake between CDS and CRDY/CERR. On an
asynchronous CV AX pin-bus, the FBIC requires external synchronizers for CRDY/CERR, such as the
CCLOCK implements. The FBIC supports only memory-space references from asynchronous CV AX
pin-bus masters.
The FBIC can be either the arbiter or an auxiliary on an 1/0-module CVAX pin-bus. The FBIC
TYPAGNTE input pin specifies whether the FBIC is the arbiter or an auxiliary. (The TYPAGNTE
specifies A/B processor for dual FBIC modules and grantor/grantee for single FBIC modules.) As arbiter,
the FBIC is the default CV AX pin-bus master, monitors CDMR, and drives CDMG. As auxiliary, it asserts
cnrvm when it requires use of the CVAX pin-bus, and it monitors CDMG.
The FBIC can retry either the CVAX pin-bus or the M-bus to break deadlocks between the two busses.
The FBIC TYPRET input pin specifies which bus to retry. If a CVAX pin-bus is nonretriable, 1/0-space
references from the M-bus that require use of the CVAX pin-bus of the module are retried when there is a
pending reference between the CVAX pin-bus and M-bus. If a CVAX pin-bus is retriable, pending references between the CVAX pin-bus and M-bus are retried when an 1/0-space reference from the M-bus
requires use of the CVAX pin-bus.
5.1.2. Cache Consistency

The FBIC implements the snoopy-cache protocol as defined by the Firefox System Specification. That is,
FBIC caches are write-back for unshared data and write-through for shared data. The FBIC guarantees
work.station-wide cache consistency for shared data written by a single processor, consistency of adjacent

5.1.2. Firefox Bus Interface Chip

December 30. 1987

Firefox System Specification 3

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bytes of shared data written simultaneously by different processors. and consistency of bytes of shared data
written simultaneously by different processors using interlocked instructions.
The FBIC does not guarantee consistency of bytes of shared data written simultaneously by different processors using noninterlocked instructions. Each cache affected will end up with the value which was written on the M-bus first. For example, if processor A writes 1 to location X, and processor B simultaneously
writes 2 to location X. and processor A perfonns the M-bus write first, both caches will will end up with 1
inX.
No explicit software-synchronization actions are required to maintain cache consistency. There is, of
course. a delay between the time a processor issues a write to its cache and the time all other caches in the
workstation complete the shared write of themselves. This delay is typically 2 to 3 microseconds.
5.1.3. On-Chip Single-Entry Snoopy Cache

The FBIC implements a single-entry on-chip snoopy-cache for 1/0 modules that participate in the M-bus
global memory space. The FBIC on-chip cache is also used on processor modules after power-up reset
until they initialize and enable the external cache.
The on-chip cache consists of a single octaword data store and a single tag-store entry. The on-chip cache
is not parity protected. The tag-store portion of the on-chip cache is accessible through CVAX pin-bus I/0
space for diagnostic/self-test purposes.
On powerup, the on-chip data store is not initialized, and the on-chip tag store is set to ls. That is, the onchip cache initializes to contain a shared, dirty copy of the last octaword in memory space.
5.1.4. External Snoopy Cache

The FBIC supports an external snoopy cache for CVAX processors. This cache is 64 Kbytes in size, is
direct-mapped. has octaword line size, and has longword access. The external-cache data store resides
directly on the COAL bus and has byte parity. The external-cache tag store resides on the tag port of the
FBIC and has word parity.
The FBICSR<EXCAEN> register bit determines whether or not the external cache is enabled. After
powerup, the external cache is off. Software must enable the cache and initialize the external tag store
through l/0-space writes. The external-cache tag store is accessible in the FBIC's slot-specific I/0-space
region for diagnostic/self-test purposes. The external-cache tag and data stores are inaccessible when the
external cache is off.
External cache hits complete in 2 CVAX cycles; there ue no wait states. Writes to shared lines are sent
through to the M-bus in a pseudo-write-behind fashion. 'This is so tenned because the CV AX receives
CRDY and CDMR immediately, and therefore, no additional CVAX pin-bus transactions are completed
until the ~te-tbrougb is completed.
The FBIC performs shared reads and write-through updates on behalf of the M-bus as required to maintain
cache consistency.
The implementation of the FBIC external cache supports use of the CVAX internal cache for both
instruction-stream and data-stream references. The CVAX internal cache is a subset of the external cache,
which means that, whenever the FBIC removes a line from the external cache, it also invalidates that line in
the CVAX internal cache, and whenever the FBIC does a write-through update of the external data store, it
also invalidates that line in the CV AX internal cache. This algorithm ensures consistency between all
caches in a Firefox workstation.
To maintain cache consistency, the CV AX internal cache must not be enabled while the FBIC external

4 Firefox: System Specification

December 30, 1987

Firefox: Bus Interface Chip 5.1.4.

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cache is off.
Once external caching has been turned on, it must be manually flushed before being turned off, otheIV1ise.
modified cache data will be lost. To manually flush the external data store. read all tags through I/O space
and force victim writes of any dirty lines by reading memory at a congruent address without generating any
memory writes in the process. Turning off the external cache is not recommended.
5.1.4.1. Cache Read

When the CV AX issues a memory-space read, the FBIC probes the tag store to determine whether the
requested location is present in the cache. In parallel with the tag probe, the FBIC enables the data store
onto the COAL in anticipation of a cache hit. If the tag probe results in a hit, the FBIC asserts CROY to
the CV AX to complete the transaction.
If the tag probe results in a miss, the FBIC immediately asserts CD:MR to the CVAX, and then, on the next
cycle. asserts CRDY and CERR. This causes the CV AX to retry the read after relinquishing the CV AX
pin-bus. The FBIC then performs victim processing on the data store, fills the data store with the requested
line, and releases the CVAX pin-bus.
5.1.4.2. Cache Write

When the CV AX issues a memory-space write, the FBIC probes the tag store to determine whether the
requ~sted location is presem in the cache. If the tag probe results m a tut, the FBIC enables wntes to the
data store and asserts CRD Y to the CVAX to complete the tramaction. In parallel with writing the data
store. the FBIC writes the tag store to set the dirty bit for the cache line_
If the tag has the shared bit asserted, the FBIC uses the data and byte masks it latched off the CVAX pinbus during the data-store write to generate a masked octaword write-through transaction on the M-bus.
When the write-through is completed, the FBIC updates the shared bit of the tag store from the value of
MSHAREO; that is, if the line is no longer in other caches. it reverts to being an unshared line.

If the tag probe results in a miss, the FBIC immediately asserts CD1\1R. to the CVAX and then, on the next
cycle, asserts CRDY and CERR. 1bis causes the CVAX to retry the write after relinquishing the CVAX
pin-bus. The FBIC then performs victim processing on the data store, fills the data store with the requested
line, and releases the CVAX pin-bus.
5.1.4.3. Victim Processing and Cache Fiii

When a read or write miss occurs, the FBIC initiates victim processing before filling the data store with the
requested line. To terminate the CVAX transaction, the FBIC issues a bus request, which is followed
immediately by a retry to ensure that the request will be honored.
If the vie~ line is clean, the FBIC immediately issues an M-bus memory read to obtain the requested line.
In parallel with the M-bus memory read, the FBIC waits for the CV AX to grant it the CVAX pin-bus and
then performs an octaword read and CVAX cache invalidate, possibly to remove the victim from the
CV AX internal cache. The FBIC then waits for the M-bus memory read to be completed, and when it has
the memory-read data, does a CV AX pin-bus octaword write to fill the data store with the requested line.
In parallel with the data-store fill, the FBIC updates the tag store with the new address, sets the shared bit
from the MS HARED signal, and clears the dirty bit. Fmally, it releases the CVAX pin-bus so the CVAX
can reissue the missed transaction.
If the victim line is dirty, the FBIC waits for the CV AX to grant it the CV AX pin-bus and then performs an
octaword read and CV AX cache invalidate, possibly to remove the victim from the CV AX internal cache.
The FBIC then issues an M-bus memory victim write to flush the dirty line back to memory. While the
M-bus memory victim write is being completed, the FBIC updates the tag store to clear the dirty bit. It

5.1.4.3. Firefox Bus Interface Chip

December 30, 1987

Firefox System Specification 5

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then issues an M-bus memory read to obtain the requested line, when it has the memory-read data, does a
CV AX pin-bus octaword write to fill the data store with the requested line. In parallel with the data-store
fill, the FBIC updates the tag store with the new address. sets the shared bit from the MSHARED signal,
and clears the dirty bit. Finally, it releases the CVAX pin-bus so the CV AX can reissue the missed transaction.
5.1.4.4. Shared Read

Whenever the FBIC observes the start of a memory read on the M-bus, it probes the tag store to determine
whether its data store contains the requested line. If a hit results, it asserts the MSHARED signal so the
module issuing the memory read can mark the cache line as being shared. The FBIC also updates its tag
store to set the shared bit. If the FBIC has a tag bit to a dirty line, it asserts its MBRQ signal and takes over
the role of M-bus slave from the memory module. The FBIC W AITs the M-bus until it can request the
CVAX pin-bus. read the requested line out of the external-cache data store, and supply the line to the Mbus. This ensures that modified data resident in caches is used in place of stale memory data.
5.1.4.5. Shared Write

Whenever the FBIC observes the start of a memory write-through (or write unlock) on the M-bus, it probes
the tag store to determine whether its data store contains the requested line. If a hit results, the FBIC
asserts the MSHARED signal so the module issuing the memory write cannot clear its shared bit. Because
the initiator of the write-through has set its dirty bit, the FBIC also clears its tag-store dirty bit. The FBIC
BUSYs the M-bus until it can request the CVAX pin-bus. write the specified bytes to the external-cache
data store, and invalidate the line in the CVAX internal cache.
5.1.5. Interlocked Transactions

The FBIC implements the M-bus interlocked-transaction mechanism as defined in the Firefox M-Bus
Specification. That is. the FBIC implements interlocking on bexaword addresses and up to two simultaneous interlocks of different hexaword regions. Interlocks are supported for both memory space and global
1/0 space.
When a CV AX pin-bus master issues an interlocked read in memory space, the FBIC forces a cache miss
and requests an M-bus memory-read interlock. To honor the interlock while the hexaword region is
already interlocked, or while two interlocks are already in progress, the FBIC suppresses arbitrating for the
M-bus. When a CV AX pin-bus master issues an unlock write in memory space, the FBIC forces a writethrough operation to generate an M-bus memory-write unlock.
When a CVAX pin-bus master issues an interlocked read in 1/0 space. the FBIC requests an M-bus 1/0read interlock. To honor the interlock while the bexaword region is already interlocked, or while two interlocks are already in progress, the FBIC suppresses arbitrating for the M-bus. When a CVAX pin-bus master issues an unlock write in 1/0 space, the FBIC generates an M-bus 1/0-write unlock.
The FBIC does not enforce interlocks for CVAX pin-bus references to its own 32-Mbyte, slot-specific,
I/0-space region.
5.1.6. SMP Processor Registers

The FBIC implements the Sl\1P CPUID and WHAMI processor registers. CPUID, a read-only register that
specifies the hardware CPU identifier, is accessible as IPR 14andthrough1/0 space. WHAMI (who am I)
is a read/write register that specifies the software CPU identifier, which is typically a pointer to a CPUspecific data structure. It is accessible as IPR 15andthrough1/0 space.

6 Firefox System Specification

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5.1. 7. 1/0-lnterrupt Masking

Tue FBIC allows software control of interrupt-request connections between the CVAX pin-bus and M-bus.
The interrupt request for each of the four interrupt priority levels (14, 15, 16, and 17) can be independently
isolated or connected between the CV AX pin-bus and M-bus. When CV AX pin-bus and M-bus interrupt
requests are connected, the signal flow can be either from the M-bus to the CVAX pin-bus (for processor
modules) or from the CV AX pin-bus to the M-bus (for I/0 modules).
5.1.8. Interprocessor/Device Interrupts

The FBIC implements a vectored interrupt unit that can be used for interprocessor interrupts onto the
CVAX pin-bus (for processor modules) or for device interrupts onto the M-bus (for 1/0 modules). The
vector for the interrupts is programmable, and interrupts can be generated under software control for any of
the four interrupt priority levels (14, 15, 16, or 17). When the unit is used for device interrupts, interrupts
can also be generated via the edge-triggered DEVIRQ input pins. To facilitate distinguishing among interrupts from an FBIC that generates multiple IPL interrupts, the interrupt unit automatically specifies the IPL
level in the vector when it acknowledges an interrupt.
5.1.9. M-bus 1/0-Space Range Decoder

The FBIC implements an M-bus I/0-space range decoder to allow access to UO module resources that do
not reside within the module's 32-Mbyte, slot-specific, 1/0-space region. This is necessary for modules
that have more than 32-Mbytes of local resources or local resources with hardwired 1/0-space addresses.
The range decoder specifies a match value for the high-order 16 bits of the M-bus address and a mask
value to make some of the match bits "don't cares":

InRange = ((Match XOR Adr<31:16>) and (not Mask) eql 0) and enable
The mask field allows regiom larger than 64 Kbytes to be specified and multiple discontiguous regions to
be matched.
The CV AX System Support chip (SSC) has registers in the CVAX address range 2014XXX. Setting the
range-decoder match field to 8014 and the mask field to 0000 will cause the FBIC to forward M-bus 1/0
transactions at addresses 8014XXXX onto the CVAX pin-bus.
The CVAX Q-Bus Interface chip (CQBIC) has registers in both the CVAX address ranges 2000XXXX and
2008XXXX. Setting the range-decoder match field to 8000 and the mask field to 0008 will cause the FBIC
to forward M-bus 1/0 transactions at addresses 8000XXXX and 8008XXXX onto the CV AX pin-bus.
A third example of the use of the M-bus 1/0 space range decoder is a graphics module that has a 16-Mbyte
frame buffer at M-bus addresses 88XXXXXX. In this case, setting the range-decoder match field to 8800,
and the mask field to OOFF, will cause the FBIC to forward M-bus 1/0 transactions at these addresses onto
the CVAX pin-bus.
The FBIC does not support local CVAX pin-bus access to the UO-space addresses specified by the range
decoder. Behavior is unpredictable if the hardware generates such references.
5.1.1 O. Status-Indicator Outputs

The FBIC drives the value of the six FBICSR<LEDS> register bits externally on the LEDS output pins.
These outputs (with buffering) can be used to drive light-emitting diodes or hex-digit displays with
diagnostic/self-test infonnation.

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5.1.11. Manufacturing-Mode Inputs

The FBIC makes the value of the two MNFMOD input pins available in the FBICSR<MF'?vID> register bits
for use by software. This may be used by ROM-based software to operate in special modes, such as continuous self-test or loopback of various forms.
5.1.12. FBIC Support for Of agnostic/Self.test ROM

The FBIC supports CV AX pin-bus access to an external. 16- or 32-bit. 512-Kbyte diagnostic/self-test
ROM. This ROM is mapped to both the VAX restart address range of 20040000#16 to 2007FFFF#l6 on
the CV AX pin-bus. and to the 32-Mbyte, slot-specific. I/0-space region on the CV AX pin-bus/M-bus.
The FBIC ROMWID32 input pin specifies whether the ROM is 16 or 32 bits. For 16-bit ROM, the FBIC
stalls the processor and performs two separate reads to the external ROM. using the ROMW ADDR signal
to select the upper and lower half of a longword. It loads these words into an internal latch and provides the
processor with the longword when it has been completely assembled in the latch. The ROM's data lines
should be attached to the local CDAL<l5:0> lines, its address lines should be connected to ROMW ADDR
and CDAL<l5:2> through an external address latch, and its output enable should be connected to the FBIC
ROMOE<O> line. For 32-bit ROM, the FBIC stalls the processor and performs a single read of the ROM.
The FBIC still loads the ROM into an internal latch, disables the ROM, and red.rives the data onto CDAL,
actions necessary because of timing constraints on the synchronous CVAX pin-bus.
To satisfy ti.ming constraints for a 70-ns CVAX pin-bus, the FBIC requires ROM with a maximum access
time of 200 ns.
5.1.13. CV AX Pin-Bus Timeout Detection

The FBIC implements a CVAX pin-bus timer that terminates a CVAX pin-bus transaction by asserting
CERR if the transaction continues for more than 2048 CV AX pin-bus clock cycles. This timeout function
aborts nonexistent I/0 references on the local CVAX pin-bus as well as system-level failures, such as hung
interlocks and synchronization failures between different bus interfaces.
5.1.14. M-bus Modul•Type Identification

The FBIC implements the MODTYPE register as required by the Firefox M-Bus Specification. The FBIC
MODCL input pins are used to generate the MODTYPE<CLASS> field as a CPU, I/0, graphics, or bus
adapter class. The MODTYPE<SUBCLASS> field reflects the value of the FBIC TYPOUAL input pin.
5.1.15. FBIC Error Detection and Logging

To allow precise error logging for diagnostic and Field Service analysis, the FBIC is designed to implement
extensive error detection and to save as much nonredundant state as is practical. Every FBIC will detect
several types of M-bus, CVAX pin-bus. and external-cache errors and take appropriate action to ensure
that the e.rror is recognized by a processor.
The types of M-bus, CVAX pin-bus, and external-cache errors detected by the FBIC are logged in the
BUSCSR register by the assertion of a status bit. For errors that require assertion of MABORT, a machine
check must always be initiated for every processor in the Firefox system. The FBIC accomplishes this by
asserting l\1EMERR to the local CV AX processor. For modules that do not contain a processor, MEMERR
can be used to generate a device interrupt by a loopback to the FBIC DEVIRQ<3> device-interrupt
request. If a CV AX l/0 cycle is in progress when MAB ORT is asserted, the FBIC can also terminate a
CVAX I/0 cycle with error status. Although the FBIC makes a best effort to detect all errors, it is not
intended that it catch 100 percent of M-bus. CVAX pin-bus, or external-cache faults.

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The FBIC detects the following M-bus errors:
•

MBRQ arbitration

•
•
•
•

Invalid MC1\1D encoding
Invalid data supplied
Cache tag parity
MC!'YID parity

•

MSTATUS parity

•
•
•
•

MDAL parity

•
•

Interlocked violation
No slave response
Slave wait/busy timeout
Error MSTATVS
M-bus double errors

The FBIC detects the following CVAX pin-bus errors:
•

CDAL parity when sinking data

•

Cache tag parity

•

Transaction umeout

When the FBIC detects M-bus errors. it freezes the BUSCTL, BUSADR, and BUSDAT log registers in
addition to asserting status bits in the BUSCSR register.
Continued system operation after an M-bus error or a cache tag-parity error is not recommended. Because
the FBIC is not designed to allow system recovery after M-bus errors and external-cache tag-parity errors,
the operating system should log all saved error information and then reboot. The FBIC does not guarantee
cache data consistency after an M-bus error or a cache tag-parity error, nor does it guarantee that memorywrite transactions in progress at the time of the M-bus error will be completed successfully.
A more detailed description of error conditions and their recommended resolution can be found in Chapter
15, "Firefox Error-Handling Specification."
5.1.16. Diagnostic Function Testing

The FBICSR<TSTFNC> bits allow diagnostic software to exercise various functions of the FBIC involving
error generation/checking and bus protocol. In addition, the BUSCTL, BUSADR, and BUSDAT errorlogging registers allow observation of M-bus control and data signals.
5.1.17. Firefox 1/0-Space Mapping

The M-bus supports a 2-Gbyte memory address space and a separate 2-Gbyte I/O address space. Each
module is assigned a 32-Mbyte region of 1/0 space as a function of its backplane slot. Address-space
assignments are listed in Table 5-2.

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Firefox. System Specification 9

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Table 5-2:

Address-Space Assignments for the M-Bus Module

M-Bus Address Range

00000000 ... lFFFFFFF
20000000 ... 7FFFFFFF
80000000 ... 87FFFFFF
88000000 ... 8FFFFFFF
90000000 ... 91FFFFFF
92000000 ... 93FFFFFF
94000000 ... 95FFFFFF
96000000 ... 97FFFFFF
98000000 ... 99FFFFFF
9AOOOOOO ... 9BFFFFFF
9C000000 ... 9DFFFFFF
9E000000 ... 9FFFFFFF
AOOOOOOO ... FFFFFFFF

VAX Address Range

Mbytes

00000000 ... lFFFFFFF

512
1536
128
128
32
32

NIA

20000000 ... 27FFFFFF
28000000 ... 2FFFFFFF
30000000 ... 31FFFFFF
32000000 ... 33FFFFFF
34000000 ... 35FFFFFF
36000000 ... 37FFFFFF
38000000 ... 39FFFFFF
3AOOOOOO ... 3BFFFFFF
3COOOOOO ... 3DFFFFFF
3E000000 ... 3FFFFFFF
NIA

32
32

32
1536

Function
Memory space
Reserved memory space
Global 110 space
Local 110 space
Slot 0 I/O space
Slot l I/O space
Slot 2 I/O space
Slot 3 1/0 space
Slot 4 I/O space
Slot 5 1/0 space
Slot 6 1/0 space
Slot 7 1/0 space
Reserved IIO space

The FBIC only supports a 30-bit physical address space on the CVAX pin-bus; it does not support M-bus
reserved memory space or M-bus reserved 1/0 space. Table 5-3 lists the connection of the CVAX pin-bus
address signals to MDAL signals for cycle P2 of M-bus transactions to convert from 30-bit physical
addresses to 32-bit physical addresses. For all other M-bus cycles, the VAX DAL<31 :00> is directly connected to MDAL<3 l :00>.
Table 5-3:

VAX 30-Blt Physical Addr•H to M-Bua 32-Blt Addreu

M-Bus Address
MDAL<31>
MDAL<30>
MDAL<29>
MDAL<28:00>

VAX Address

DAL<29>
0
0
DAL<28:00>

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Figure 5-2 shows the FBIC address space from the perspective of a CVAX pin-bus device. CVAX pin-bus
references to memory space access the memory through the FBIC cache. The FBIC forwards CVAX pinbus references to global M-bus 1/0 space and slot-specific 1/0 space for other slots onto the M-bus. It handles CV AX pin-bus references to its own registers, tag store, and ROM directly, without using the M-bus.
It does not participate in CV AX pin-bus references to the local I/O space and the first 30 Mbytes of the
slot-specific IiO space.
32-Mbyte slot 7

3EOOOOOO :

32-Mbyte slot 6

3COOOOOO I

32-Mbyte slot 5

3AOOOOOO i

Slot Specific I/0 Space

32-Mbyte slot 4

38000000 !

.. ····1
I
I

32-Mbyte slot 3

36000000
34000000
32000000

32-Mbyte slot 2

32-Mbyte slot 1

1·.

I 33F80000

Module ROM

I 33EOOOOO

I
30-Mbyte 1/0

32-Mbyte slot 0

30000000

FBIC registers
External tag store
Reserved

i 33FOOOOO
!

33E80000

·· .. j

32000000

128-Mbyte
C-bus local I/0

28000000 '
127.5-Mbyte
Global M-bus I/O
20080000
20040000
20000000

VAX boot ROM
Global M-bus I/0

256 Kbytes
256 Kbytes

512-Mbyte
M-bus memory

00000000

Figure 5-2:

FBIC C-Bus Address Space

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Figure 5-3 shows the FBIC address space from the perspective of an M-bus device. M-bus references to
memory-space access the FBIC cache as appropriate for shared data. The FBIC forwards M-bus references to global I/O space onto its CV AX pin-bus only if its range decoder matches the address. It handles
M-bus references to its registers directly, without using the CVAX pin-bus. but forwards M-bus references
to its 30 Mbytes of slot-specific 1/0 space and to its ROM onto the CV AX pin-bus. The FBIC does not
participate in other regions of M-bus I/0 space.

FFFFFFFFI
I
I

1536-Mbyte
reserved l/0

•

9EOOOOOO i

32-Mbyte slot 7

9COOOOOO I

32-Mbyte slot 6

9AOOOOOO I

32-Mbyte slot 5

98000000

32-Mbyte slot 4

96000000
94000000

32-Mbyte slot 3
32-Mbyte slot 2

92000000

32-Mbyte slot 1

90000000

32-Mbyte slot 0

l~~~~~.;...._~~----

128-Mbyte

88000000

80080000
80040000
80000000

127 .5-Mbyte
M-bus I/O
256-Kbyte local 1/0
256-Kbyte M-bus I/O

1536-Mbyte
Reserved memory
20000000

512-Mbyte
M-bus memory
00000000

Figure 5-3:

FBIC M-Bus Address Space

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5.1.18. FBIC 1/0-Space Address Mapping

By logically connecting the .MDAL<3 l> and CDAL<29> address lines, the FBIC directly maps into
CV AX pin-bus l/0-space accesses those M-bus JJO-space accesses that fall in the 32-Mbyte, slot-specific
region of the module on which the FBIC resides. In the same manner, the FBIC also directly maps into Mbus l/0-space accesses the CV AX pin-bus 1/0-space accesses to the global I/O space region (except those
that reference the bootstrap ROM region of 20040000 ... 2007FFFF) and to the 32-Mbyte. slot-specific
region of other modules. The FBIC does not participate in local 1/0-space accesses. CV AX pin-bus 1/0space accesses to the 32-Mbyte, slot-specific region of the module on which the FBIC resides are discussed
following Figure 5-4.
The FBIC determines the 32-Mbyte M-bus address range to which it must respond by concatenating the
MID (Module ID) input pins, as shown in Figure 5-4.
31

28 27

24 23

28 27

24 23

+--------+----------------------+--------+
High M-bus 3ddress
I
9
I MID2 MIDl MIDO
1
I FFFFFF I
+--------+----------------------+--------+
Low M-bus address

Figure 5-4:

+--------+----------------------+--------+
9
I MID2 MIDl MIDO
0
I 000000 I
+--------+----------------------+--------+

Construction of the Module-Specific M-Bus 1/0-Space Range

Because there are two separate CVAX pin-busses but only one 32-Mbyte, slot-specific address region on
the Firefox dual-CV AX processor module, the 32-Mbyte region is divided into two, 16-Mbyte regions (one
per CVAX pin-bus). This means that the FBIC will map into CVAX pin-bus 1/0-space accesses only those
M-bus 1/0-space accesses that fall both in the 32-Mbyte, slot-specific region of a processor module and
within the 16-Mbyte range specific to that particular processor. Moreover, the FBIC will not map into Mbus I/0-space accesses the CVAX pin-bus 1/0-space accesses to the 16-Mbyte, slot-specific region belonging to the local processor on a Firefox dual-CVAX processor module, although it will map into M-bus
1/0-space accesses the CVAX pin-bus 1/0-space accesses to the 16-Mbyte, slot-specific region belonging
to the other processor on a Firefox dual-CVAX processor module.
The FBIC determines the module type on which it resides from the TYPDUAL, TYPAGNfE, TYPSYNC,
and TYPRET input pins defined in Section 1.2, "Interface," later in this chapter. If the FBIC resides on a
Firefox dual-CV AX processor module, it determines the per-processor 16-Mbyte M-bus address range to
which it must respond by concatenating the MID and the TYPAGNTE input pins, as shown in Figure 5-5.
The CPUID register implemented on the FBIC uses these same signals to uniquely identify each processor
in the Firefox system.

28 27

24 23

28 27

24 23

+--------+-------------------------+--------+
High M-bus address
9
I MID2 MIDl MIDO TYPAGNTE I FFFFFF I
+--------+-------------------------+--------+
Low M-bus address

Figure 5-5:

+--------+-------------------------+--------+
I MID2 MIDl MIDO TYPAGNTE I 000000 l
9
+--------+-------------------------+--------+

Construction of the Processor-Specific M-Bus 1/0-Space Range

Within the 16- or 32-Mbyte M-bus 1/0-space address range that corresponds to a particular FBIC. the high
2-Mbyte region is reserved for access to FBIC registers. external-cache tag store. and module-specific

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ROM. The FBIC will map M-bus I/0-space accesses in this 2-Mbyte range into the appropriate FBIC
register and ROM accesses. CV AX pin-bus accesses outside the local 2-Mbyte range but within the 16Mbyte processor-specific region will not be mapped by the FBIC into corresponding M-bus accesses.
Software running on a particular CV AX processor can determine the 2-Mbyte I/0-space range at which to
access local resources by reading the processor's CPUID or \\'HAMI register with the VAX move from
processor register instruction.
Because all CV AX processors will expect to find diagnostic/self-test ROM starting at address
20040000#16 on the CV AX pin-bus. the ROM is also mapped by the FBIC to this CV AX pin-bus location.
CV AX pin-bus 1/0-space accesses to this ROM will never be mapped to M-bus accesses in the corresponding M-bus 1/0-space range.
Within the 2-Mbyte region, the top 512 Kbytes are reserved for FBIC registers, the next 512 Kbytes are
reserved for the external tag store, the next 512 are reserved for future use, and the bottom 512 Kbytes are
reserved forthe module's ROM.
The FBIC registers require only a 64-byte region of the 512-Kbyte register region; thus, they appear 8192
times within th~ region. For compatibility with possible future extensions, software must only access the
registers at their designated addresses.
Each external-cache tag appears in 1/0 space four times at each longwoni within the naturally aligned octawoni; that is. the tag for external-cache line 0 is accessible at offsets XXFOOOOO, XXF00004, XXF00008,
and XXFOOOOC. Software can access the tag for a cache line at any of the four addresses. The entire set of
tags reappear eight times within the 512-Kbyte tag space. For compatibility with larger external caches,
software must access the tags only in the XXFOOOOO ... XXFOFFFF region.
The ROM appears at both the VAX restart addresses of 20040000 and XXEOOOOO. The FBIC only
responds to addresses 20040000 ... 2007FFFF (a total of 256 Kbytes) because of the address-space assignments of the CQBIC. Modules with 512 Kbytes of ROM can access only the upper 256 Kbytes of the
ROM at XXE40000 ... XXE7FFFF. ROMs smaller than their assigned regions reappear multiple times
within their regions.
5.1.19. FBIC Registers

The FBIC supports a total of 13 internal registers that implement the following:

•
•

•
•
•
•
•

•
•

M-bus module-type identification
M-bus error detection and error status
M-bus enor-control signal log
M-bus error-address signal log
M-bus error data signal log
Con~l and status of the FBIC
I/0-interrupt masking
Diagnostic/self-test LEDs
I/0-space range decoding

•
•
•
•
•
•
•
•

Interprocessor-interrupt delivery
Interprocessor-interrupt vector
Device-interrupt delivery
Device-interrupt vector
Software processor identification
Hardware processor identification
Interlocked-transaction status
Scratch-register storage

Table 5-4 lists address offset, access, and function of the FBIC registers. each of which is described in
detail in the subsections that follow the table. The FBIC registers are at the top of a 512-Kbyte region;
references to unassigned addresses produces unpredictable results.

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Table 5-4:

FBIC Register Map

Address
XXFFFFFC# 16
XXFFFFF8# 16
XXFFFFF4# 16
XXFFFFFO#l6
XXFFFFEC# 16
XXFFFFE8#16
XXFFFFE4#16
XXFFFFEO#l6
XXFFFFDC#l 6
XXFFFFD8#16
XXFFFFD4#16
XXFFFFDO#l6
XXFFFFC4# 16

R/W*
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W

Register Description
Module type
M-bus error status
M-bus error-control signal log
M-bus error-address signal log
M-bus error-data signal log
FBIC control status
1/0-space-range decode
Interprocessor/device interrupt
Unique software ID
Unique hardware ID
Interlock 1 address
Interlock 2 address
Halt-code scratch

* R/W =Read/Write
In the FBIC register descriptions that follow, all fields labeled MBZ (must be zero) indicate reserved bits.
These bits should always be written with Os to provide for future enhancements; reading these bits will
return all Os. All register bits with write access are cleared bv MRESET. All registers with write access
support byte writes. Unless otherwise noted. all register bits are active-high.

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5.1.19.1. MODTYPE Register

The MODTYPE register is a read-only register that indicates the class of the module, infollllation specific
to the class, the interface chip, and the revision of the interface chip. Figure 5-6 shows the bit definitions
for the MODTYPE register.
Name: MODTYPE

Address: XXFFFFFC#l6

2 2

1 1

4 3

6 5

REVISION

INTERFACE

Access: R

8 7
SUBCLASS

0
CLASS

MODTYPE:

REVISION
INTERFACE ~~~~~~~~~~_.
SUBCLASS
CLASS
Figure 5-6:

MODTYPE Register

MODTYPE<7:0>

(R)

CLASS

Module Class

The CLASS field indicates the class of module on which the FBIC is physically situated. These bits
reflect the value of the FBIC MODCL<l :0> input pins. Table 5-5 shows the value of the
MODTYPE<7:0> as a function of the MODCL<l :0> pins.
Table 5-5:

MODCL Encoding for MODTYPEcCLASS>

MODCL<l:O>
0
1
2
3
MODTYPE<15:8>

MODTYPE<7:0>
01

Class
Bus adapter
Graphics

02
04
08
SUBCLASS

1/0
CPU
(R)

Module Subclass

The FBIC echos the state of the TYPDUAL input pin on MODTYPE<8>. MODTYPE<l5:9>
always reads as Os.

INTERFACE
(R)
Interface Chip
The FBIC specifies the FBIC code of 1 in this field.

MODTYPE<23:16>

MODTYP°E<31:24>

REVISION

(R)

Interface Revision

The FBIC specifies revision 1 in this field.

As an example of the contents of the MODTYPE register, an FBIC on a Firefox dual-CV AX processor
module has a MODTYPE value of01010108; the FBIC on an 1/0 module has MODTYPE of 01010004.

16 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip S. l.19. l.

DIGITAL EQCIPME~"T CORPORATION - RESTRlCTED DISTRlBCTIO~

5.1.19.2. BUSCSR Register

The BUSCSR register is a read/write register that maintains M-bus error status and controls M-bus error
logging. Figure 5-7 shows the bit definitions for the BUSCSR register. All bits of BUSCSR are active-low.
Whenever the FRZN bit is set, the FBIC logs errors in BUS CSR by clearing the corresponding status bit.
When the FBIC clears a status bit. it also clears the FRZN bit. When the FRZN bit is clear, the FBIC does
not alter the value of BUSCSR. This means that the BUSCSR saves the first error event. If errors occur
simultaneously and error logging is enabled, the FBIC clears multiple-status bits. To enable error logging,
write FFFFFFFF#l6 to BUSCSR. The result of simultaneous error events and I/0-space writes to
BUS CSR is unpredictable.
Address: XXFFFFF8#16

Access: RW

3 3 2 2 2 2 2 2 2 2 2 2 1 l 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5

Name: BUSCSR

rvmz

BUSCSR:

FRZN

ARB
ICMD
IDAT

i I

\ITPE

-----I

MDPE
MSPE

MCPE

ILCK

MTO

_ _II

NOS
CTO
CDPE
CTPE
SERR
DBLE
..

Figure 5-7:

BUSCSR Register

BUSCSR<16>

DBLE

(RW)

Double M-Bus Error

The FBIC clears DBLE when an M-bus error is detected and the FRZN (BUSCSR<31>) bit is
already cleared.
BUSCSR<l 7>

SERR

(RW)

Error on MST ATUS

The FB IC clears SERR when an M-bus slave supplies an MST ATVS value of error ( 11 #2).
BUSCSR<18>

CTPE

5. l.l 9.2. Firefox Bus Interface Chip

(RW)

CDAL Tag-Store Parity Error

December 30, 1987

Firefox System Specification 17

DIGITAL EQt.:IP~EST CORPORATIOS - RESTRlCTED DISTRIBCTIO~

The FBIC clears CI"PE when a CV AX pin-bus memory-space reference detects a tag-store parity
error. It also assens the CERR signal to tenninate the CV AX pin-bus transaction when it detects a
tag-store parity error.
BUSCSR<l9>

COPE

(RW)

COAL Parity Error

The FBIC clears CDPE when it reads data from the COAL bus. It also clears CDPE when it accepts
write data from the CDAL bus, if the CDAL and CSDP signals are inconsistent and the CDPE signal
is asserted.
B USCSR<20>

CTO

(RW)

COAL Timeout

The FBIC clears CTO when CAS is asserted for 2048 continuous CVAX pin-bus cycles. It also
assens the CERR signal to terminate the transaction
BUSCSR <21>

NOS

(RW)

M-Bus No-Slave Response

The FBIC clears NOS when no M-bus slave responds to an M-bus transaction initiated by this FBIC.
BUS CSR <22>

rvrro

(RW)

M-Bus Slave Timeout

The FBIC clears MTO when an M-bus slave either specifies WAIT status or asserts MBUSY for 256
continuous M-bus cycles. The FBIC also generates an MABORT sequence when it clears MTO.
BUSCSR<23>

Il..CK

(RW)

M-Bus Interlock Violation

The FBIC clears ILCK when an unexpected interlocked operation is issued on the M-bus. An unexpected interlocked operation would be an interlocked read to a hexaword address that is already
interlocked, a third interlocked read when two interlocks are already in progress, or an unlock write
to a hexaword address that is not interlocked. The FBIC also generates an MABORT sequence when
it clears ILCK.
BUSCSR<24>

MCPE

(RW)

M-Bus MC:MD Parity Error

The FBIC clears MCPE when it detects a parity error on the MCMD signals. It checks MCMD parity the cycle after the value is on the M-bus--that is, P3; memory write P4, P5. P6, first P7; 1/0 read
first P4; and I/0 write first P4. The FBIC also generates an MABORT sequence when it clears
MCPE.
BUSCSR<25>

MSPE

(RW)

M-Bus MSTATUS Parity Error

The FBIC clears MSPE when it detects a parity error on the MSTATUS signals. It checks

MSTATIJS parity the cycle after the value is on the M-bus--that is, memory read PS. P9, PIO, Pll;
I/0 read PS; 1/0 write PS; and interrupt acknowledge P6. The FBIC also generates an MABORT
se"~ence when it clears MSPE.
B USCSR<26>

MDPE

(RW)

M-Bus MDAL Parity Error

The FBIC clears .MDPE when it detects a parity error on the MDAL signals. It checks MDAL parity
the cycle after the value is on the M-bus--that is. P3; memory read PS, P9, PlO, Pll; memory write
P4. PS, P6. first P7; 1/0 read P5; I/0 write first P4; and interrupt acknowledge P6. The FBIC also
generates an MABORT sequence when it clears MDPE.
BUSCSR<27>

MTPE

(RW)

M-Bus Tag Parity Error

The FBIC clears ~ITPE when it does an M-bus memory-space tag probe and detects a tag-store parity error. It also generates an MABORT sequence when it clears MTPE.

18 Fircfo,cSystern Specitication

December 30, 1987

Firefox Bus Interface Chip 5.1.19.2.

DIGITAL EQCIPME'\1 CORPORATIO~ -RESTRICTED DISTR1BL1IO;>.;

B USCSR <28>

IDAT

(RW)

M-Bus Invalid Data Supplied

The FBIC clears IDAT when it supplies data onto :MDAL indicating that it detected a parity error on
obtaining read data from the COAL.
B USCSR<29>

IC!vID

(RW)

M-Bus Invalid MC!vID Encoding

The FBIC clears ICMD when it detects that an M-bus transaction has an undefined MC:MD encoding
during P2. It also generates a MABORT sequence when it clears IC:MD.
BUSCSR<30>

ARB

(RW)

M-Bus Arbitration Error

The FBIC clears ARB when it detects an M-bus arbitration error. Arbitration errors represent either
premature deassertion of an MBRQ signal when the FBIC is monitoring a transaction, or assertion of
another MBRQ signal when the FBIC has its MBRQ signal asserted as a master or slave of a transaction. The FBIC also generates an MABORT sequence when it clears ARB.
BUSCSR<31>

FR.ZN

(RW)

M-Bus Error Logging Frozen

The FBIC clears FRZN when it clears one or more of the BUSCSR<30:0> bits or when it detects
MABORT asserted.

5.1.19.2. Firefo)( Bus 1ntcrface Chip

December 30, 198 7

Fircfo)( System Specification 19

DIGITAL EQt:IPME.""lT CORPORATION - RESTRICTED DISTRlBL"TION

5.1.19.3. BUSCTL Register

The BUSCIL register is a read/write register that logs the value of M-bus control signals at the time the
FBIC detects an error. Write access to the BUSCTL register is only for diagnostic testing; the result of
I/0-space writes to the B USCTL register when error logging is enabled is unpredictable. Figure 5-8 shows
the bit definitions for the BUSCTL register.
Address: XXFFFFF4#16

Name: BUSCTL

Access: RW

2 2 2 2 1 1 1 1 1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2

2 2 2 2
8 7 6 5

9 8 7 6

i SMC jMISi PHZ !HiA!DjSJB!DIS! MS IC/ MCMD 1QIP!
ifl
~ I~ If "' ~
I~ ifl

BUSCTL:

_j Tj '"

SVDMC?vID

MASTER

T, .,

T , .,

PHASE

MBRM

'11

SLAVE

I
I

MHALT
MAB ORT

?vIDATINV

MS HARED
MBUSY

?vIDPAR
MSPAR

MSTATUS

MCPAR
MC?vID
MBRQ
MBRP
MBRM
Figure 5-8:

BUSCTL Reglater

BUSCTL<6:0>

MBRM

(RW)

M-Bus MBRM Signals

The FBIC continuously updates MBRM from the M-bus MBRM signals when BUSCSR<FRZN> is
set or MRESET is asserted. This provides module-present information on reset and M-bus MBRQ
status infonnation during M-bus errors.
BUSCTL<7>

MBRP

(RW)

M-Bus MBRP Signal

The FBIC continuously updates MBRP from the FBIC MBRP input pin when BUSCSR<F'RZN> is
set or MRESET is asserted. This provides module-present infonnati.on on reset and M-bus MBRQ
status infonnation during M-bus errors.

20 Firefox System Specification

December 30, 1987

Firefox Bus Interface OUp 5.1.19.3.

DIGITAL EQCIPME."<"T CORPORA TIO.S - RESTRICTED DISTR1Bl:Tro.s

BUSCTI..<8>

MBRQ

(RW)

The FBIC continuously updates
BUSCSR<FRZN> is set.
BUScrL<12:9> MCMD

(RW)

M-Bus l\.1BRQ Signal
MBRQ

from

the

FBIC MYMBRQ output pin when

M-Bus MCMD Signals

The FBIC updates MCMD from the M-bus MC:MD signals when it checks parity on the MCMD signals and BUSCSR<FRZN> is set.
BUSCT.1...<13>

MCPAR

(RW)

M-Bus MCPAR Signal

The FBIC updates MCPAR from the M-bus MCPAR signal when it checks parity on the MCMD signals and BliSCSR<FRZN> is set.
BUScrL<15:14> MSTATUS

(RW)

M-Bus MSTATUS Signals

The FBIC updates MSTATUS from the M-bus MSTATUS signals when it checks parity on the
MSTATUS signals and B USC SR <FRZN > is set.
BUSCTL<l6>

MSPAR

(RW)

M-Bus MSPAR Signal

The FBIC updates MSPAR from the M-bus MSPAR signal when it checks parity on the MSTATUS

signals and BUSCSR<FRZN> is set.
BUSCTL<l7>

MDPAR

(RW)

M-Bus MDPAR Signal

The FBIC updates :MDPAR from the M-bus MDPAR signal when it checks parity on the MDAL signals and BUSCSR<FRZN> is set.
BUSCTL<l8>

MBUSY

(RW)

M-Bus MBUSY Signal

The FIBC continuously updates MBUSY from the M-bus MBUSY signal when BUSCSR<FRZN> is
set.
BUSCTL<l9>

MSHARED

(RW)

M-Bus MSHARED Signal

The FBIC continuously updates MSHARED from
BUSCSR<FRZN> is set.
BUSCTL<20>

MDATINV

(RW)

M-Bus MDATINV Signal

The FBIC continuously updates MDATINV from
BUSCSR<FRZN> is set.
BUSCT'I:-41>

MABORT

(RW)

the M-bus MSHARED signal when

the

M-bus MDATINV signal when

M-Bus MABORT Signal

The FBIC updates MABORT from the M-bus MABORT signal when BUSCSR<FRZN> is set.
B USCTL<22>

:MHALT

(RW)

M-Bus rvt:HALT Signal

The FBIC updates rvt:HALT from the M-bus :MHALT signal when BUSCSR<FRZN> is set.
BUSCTL<25:23> PHASE

(RW)

M-Bus Transaction Phase

The FBIC continuously updates PHASE from the M-bus state-machine transaction phase when
B USCSR<FRZN> is set. Table 5-6 shows the encoding of PHASE as a function of the M-bus transaction phase.

5. l.19.3. Firefox. Bus Interface Chip

December 30, 1987

Firefox. System Specification 21

DIGITAL EQlJIPME.1'IT CORPORATION - RESTRICTED DISTRIBL"TION

Table 5-6:

Encoding of the BUSCTL M-Bus Transaction Phase

M-Bus

PHASE

1
2
3
4

P3
P4
P5
P6
P7

5
6

P9
PlO

7
7
7

BUSCTI..<26>

SLAVE

(RW)

M-Bus Slave

The FBIC continuously updates SLAVE from the M-bus state-machine slave mode when
B USCSR <FR.ZN> is set.
BUSCI'L<27>

MASTER

(RW)

M-Bus Master

The FBIC continuously updates MASTER from the M-bus state-machine master mode when
BUSCSR<FRZN> is set.
BUSCTI..<31 :28> SVDMCMD

(RW)

M-Bus Saved MCMD Signals

The FBIC updates SVDMCMD from the P2 value of the M-bus MCMD signals during P3 of every
transaction when BUSCSR<F'RZN> is set.

22 Fin:fox System Specification

December 30, 1987

Fin:fox Bus Interface Chip 5.1.19.3.

DIGITAL EQt:IPME.."\! CORPORA TIO:-.i - RESTRICTED OISTRlBLTIO:-.;

5.1.19.4. BUSADR Register

The BUSADR register is a readiwrite register that maintains the M-bus address of the last M-bus transaction. Write access to the BUSADR register is only for diagnostic testing; the result of 1/0-space writes to
the B USADR register when error logging is enabled is unpredictable. Figure 5-9 shows the bit definitions
for the BUSADR register.
Address: XXFFFFFO#l 6

Name: BlJSADR

Access: RW
0

ADDRESS
BUSADR:

ADR
Figure 5-9:

BUSADR Register

BUSADR<31:0> ADR

(RW)

M-Bus Error Address

The FBIC updates ADR from the P2 value of the M-bus :MDAL signals during P3 of every transaction when BUSCSR<FRZN> is set.

5. l.19.4. Firefox Bus Interface Chip

December 30, 1987

Firefox System Specification 23

DIGITAL EQt;IPMENT CORPORATION - RESTRICTED DISTRIBCTION

5.1.19.5. BUSDAT Register

The BUSDAT register is a read/write register that maintains the last M-bus MDAL value. Write access to
the BUSDAT register is only for diagnostic testing; the result of 1/0-space writes to the BUSCTL register
when error logging is enabled is unpredictable. Figure 5-10 shows the bit definitions for the BUSDAT
register.
Address: XXFFFFEC# 16

Name: BUSDAT
3
1

Access: RW
0

DATA
BUSDAT:

DATA
Figure 5-10:

BUSDAT Register

BUSDAT<31:0> DATA

(RW)

M-Bus Error Data

The FBIC updates DATA from the M-bus MDAL signals when the FBIC checks parity on the
MDAL signals and BUSCSR<FRZN> is set.

24 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5. l.19.5.

DIGIT AL EQUIPMENT CORPORA TIO~ - RESTRICTED DISTRlBCTION

5.1.19.6. FBICSR Register

The FBICSR register is a read/write control and status register for the FBIC itself. Figure 5-11 shows the
bit definitions for the FBI CSR register.
Name: FBICSR

Address: XXFFFFE8#16

3 3 2 2 2 2 2 2 2
1 0 9 8 7 6 5 4 3

2 1
0 9

Access: RW

1 1 1 1
6 5 4 3

i IRQD

;MB~

8 7 6 5
LEDS

FBICSR:

iH.Z!;

TSTFN

c~nss

EXCAEN
HALTCPU
RESET
IRQEN
IRQC2M

LEDS

HALTEN

TSTFNC
CDPE
Figure 5-11:

FBIC Control and Status Register

FBICSR<O>

CDPE

(RW)

CVAX Pin-Bus Parity-Check Enable

The CDPE bit enables checking on the CVAX pin-bus CDAL/CCSDP signals. The FBIC asserts the
CVAX pin-bus CDPE signal when it or the external-cache data store drives data onto the CVAX
pin-bus and FBICSR<CDPE> is asserted.
FBICSR-9:1>

TSTFNC

(RW)

FBIC Diagnostic Test Function

The TSTFNC bits select a test function for use by diagnostics to facilitate testing of various FBIC
functions. The TSTFNC bits are not cleared by MAB ORT. Table 5- 7 lists encodings for the test
function.

5. l. l 9.6. Firefox Bus Interface Chip

December 30, 1987

Fi.rcfox System Specification 25

DIGITAL EQClPME.1\'T CORPORATION - RESTRICTED DISTRIBl..'TION

Table 5-7:

Encodings for the FBICSR Diagnostic Test Function

TSTFNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 .. 30
31

FBICSR<7>

Diagnostic Test Function
Logically isolate FBIC from M-bus
Complement output of MCI\ID parity generator
Complement output of MST ATUS parity generator
Complement output of MDAL parity generator
Complement output of MC:MD valid decoder
Force all reads/writes interlocked. honor ISIP
Force all reads/write interlocked. ignore ISIP
Assert MBUSY
Assert .MDATINV
Assert MSHARED
Assert MABORT
Complement output of COAL parity generator
Unpredictable
U npred.ictable
Force cache hit
Unpred.ictable
Normal mode

HALTEN

(RW)

Enable CPU Halts

.MHALn

The FBIC asserts the CHALT signal when (FBICSR<HALTCPU> OR
AND HALTEN is
true. Qearing the HALTEN bit allows console software to suppress (additional) halts. The
HALTEN bit is automatically cleared by the FBIC when MHALT and HALTEN are asserted to provide a debouncing mechanism for the MHALT switch. However, the HALTEN bit is not cleared
when FBICSR<HALTCPU> and HALTEN are asserted.

FBICSR<13:8>

LEDS

(RW)

FBIC LED Outputs

The FBIC drives the module LEDS with the value of LEDS. Clearing a bit of LEDS illuminates the
corresponding module LED. Setting a bit of LEDS turns off the corresponding module LED.
Because MRESET clears the FBICSR register, the FBIC illuminates all module LEDS during

MRESET.
FBICSR<19:16> IRQC2M

(RW)

Interrupt-Request Direction

IRQC2M specifies the ftow direction of the MIRQ/CIRQ signals. If a bit of IRQC2M is 1, assertion
of the corresponding CIR.Q signal causes assertion of the corresponding MIRQ signal, provided that
the cor.responding FBICSR<IRQEN> bit is 1. This is used by modules that generate interrupts onto
the M-bus. If a bit of IRQC2M is 0, assertion of the corresponding MIRQ signal causes assertion of
the conespooding CIRQ signal. provided that the conesponding FBICSR<IRQEN> bit is 1. This is
used by modules that service interrupts from the M-bus.
FBICSR<23:20> IRQEN

(RW)

Interrupt-Request Enable

The IRQEN bits allow connection of the MIRQ/aRQ signals. If a bit of IRQEN is 1, the FBIC electrically connects the corresponding CIRQ/MIRQ signals. If a bit of IRQEN is 0, the FBIC electrically isolates the corresponding CIRQ/MIRQ signals. Table 5-8 lists the correspondence between
the IRQEN/IRQC2M bits and the CIRQ/MIRQ signals.

26 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.1.19.6.

DIGITAL EQC"IPME.~'T CORPORATION - RESTRlCTED DISTRIBL'TIO~

Table 5-8:

FBICSR IRQEN/IRQC2M and CIRQ/MIRQ Correspondence

IRQEN
FBICSR<20>
FBICSR<21>
FBICSR<22>
FBICSR<23>

FBICSR<24>

IRQC2M
FBICSR<l6>
FBICSR<17>
FBICSR<l8>
FBICSR<l9>

RESET

(RW)

CIRQ
CIRQO
CIRQl
CIRQ2
CIRQ3

MIRQ
MIRQO
MIRQl
MIRQ2
MIRQ3

CV AX Pin-Bus RESET Control

The FBIC asserts the CRESET signal when RESET is 1. The M-bus portion of the FBIC is not
affected by the state of the CRESET signal. The CVAX pin-bus portion of the FBIC returns to the
idle state. The RESET bit is not automatically cleared; a 0 must be explicitly written to clear it.
Software must guarantee a 500-ns minimum pulse width on CRESET. Software must also guarantee
that the M-bus is idle while asserting the RESET bit in a module, or unpredictable behavior will
result. Because the RESET bit is not automatically cleared, a module may not reset itself.
FBICSR<25>

HALTCPU (RW)

CVAX Pin-Bus HALT Control

The FBIC asserts the CHALT signal when HALTCPU is 1 and the FBICSR<HALTEN> bit is 1.
FBICSR<26>

EXCAEN

(RW)

External-Cache Enable

The FBIC enables its external cache when EXCAEN is 1.

FBICSR<27>

CMISS

(RW)

CVAX Pin-Bus Cache Miss Occurred

The FBIC clears CMISS independent of any diagnostic modes when a CVAX pin-bus memory-space
reference misses in the external cache. The CMISS bit is used in conjunction with the force-cachehit diagnostic mode to test operation of the tag comparators.
FBICSR<31 :30> MFMD

(R)

Manufacturing Mode

The MFMD bits reflect the value of the FBIC MANFMODE<l :0> input pins.

5. l.l 9.6. Firefox Bus Interface Oiip

December 30, 1987

Firefox System Specification 27

DIGITAL EQUIPMENT CORPORATION - RESTRICTED DISTRIBUTIO~

5.1.19.7. RANGE Register

The RANGE register is a read/write register that specifies an I/0-space address range that should be
decoded for a given module. Note that it is possible to program the same address range to FBICs in different slots. This will result in MBRQ errors whenever M-bus cycles in this address range are attempted.
Figure 5-12 shows the bit definitions for the RANGE register.
Name: RANGE

Access: RW

Address: XXFFFFE4#16

1 1 1

3
1

6 5 4

jEI

MATCH
RANGE:

0
MASK

MATCH
ENABLE
MASK
Figure 5-12:

RANGE Register

RANGE<l4:0>

MASK

(RW)

M-Bus 1/0-Space Address Range Mask

If a bit of the MASK field is 1, the corresponding bit of RANGE<MATCH> is a "don't care" bit. If
a bit of the MASK field is 0, the conesponding bit of RANGE<MATCH> must be the same as the
corresponding MDAL bit to generate a range match.
RANGE<l5>

ENABLE

(RW)

M-Bus 1/0-Space Address-Range Enable

If the ENABLE bit is 1, the matches of the range decoder cause the FBIC to respond as an M-bus
slave and forward the transaction into the CVAX pin-bus. If the ENABLE bit is 0, the range decoder
never matches.
RANGE<31:16> MATCH

(RW)

M-Bus 1/0-Space Address-Range Match

The MATCH bits specify the value of MDAL<31:16> to generate a range decoder hit for M-bus
transaction addresses. The range-decoder function is (((MDAL<31:16> XOR MATCH) AND (NOT
MASK)) EQL 0) AND ENABLE.

28 Firefox. System Specification

December 30, 1987

Firefox. Bus Interface Chip 5.1.19.7.

DIGITAL EQUIPME.'IT CORPORATION - RESTRICTED DISTRIBUTION

5.1.19.8. IPDVINT Register

The IPDVINT register is a read/write register that implements interprocessor and device intenupts. Interprocessor interrupts are into the local module, whereas device interrupts are onto the M-bus. The
IPDVINT register can be used either as an interprocessor-intermpt unit or a device-interrupt unit, but not as
both simultaneously. Figure 5-13 shows the bit definitions for the IPDVINT register.
Address: XXFFFFEO# 16

Name: IPDVINT

2 2 2 2 2 2
8 7 6 5 4 3

3
l
MBZ
IPDVINT:

7!6/5141

Access: RW

l 1 1 l

8 7 6 5
MBZ

I I D1

4 3 2 1 0

VECTOR

IPL MBZ

IPL17
IPL16
IPL15
IPL14

IPUN1T
DEVUNIT
VECTOR
IPL
Figure 5-13:

IPDVINT Reglater

IPDVINT<3:2>

IPL

(RW)

Interrupt Level

The IPL field specifies the low two bits of the interrupt vector that the FBIC supplies when it
responds to an interrupt acknowledge as an interprocessor or device-interrupt unit. When the FBIC
returns a vector, the IPL field is set to the IPL level bits <3:2>. Table 5-9 lists the encoding for each
IPL level.
Table 5-9:

IPL
14
15"
16
17

Encoding for the IPDVINT IPL Fleld

VECTOR<3:2>
0
1
2
3

When the FBIC returns the contents of the IPDVINT register during an I/0-space read, the IPL field
is set to bits <3 :2> of the register address (namely 00#2).
IPDVINT<15:4> VECTOR

(RW)

Interrupt Vector

The VECTOR field specifies the interrupt vector that the FBIC supplies when it responds to an interrupt acknowledge as an interprocessor or device-interrupt unit.
IPDVI~! <17>

DEYUNIT (RW)

5. l .19.8. Firefox Bus Interface Chip

Device-Interrupt Unit

December 30, 1987

Firefox System Specification 29

DIGITAL EQVIPME.~1 CORPORATION. RESTRICTED DISTRIBtmo:-.;

When the DEVUNIT bit is l, the IPDVINT register functions as a device-interrupt unit. This means
that interrupt requests are asserted on the .MIRQ signals. Operation of the IPDVINT register is
unpredictable if both IPUNIT and DEVUNIT are 1.
IPDVINT<l6>

IPUNIT

(RW)

Interprocessor-Interrupt Unit

When the IPUNIT bit is 1, the IPDVINT register functions as an interprocessor-interrupt unit. 1bis
means that intenupt requests are asserted on the CIRQ signals. Operation of the IPDVINT register is
unpredictable if both IPUNIT and DEVUNIT are 1.
IPDVINT<24>

IPL14

(RW)

Generate IPL 14 Interrupt

When the IPL14 bit is 1, the IPDVINT register generates an IPL 14 interrupt. As a result, it asserts
CIRQO/MIRQO. When the IPDVINT responds to an IPL 14 interrupt acknowledge, it clears the
IPL14 bit. When the FBIC is in diagnostic-isolate test mode, the IPL14 bit is read/write. Otherwise,
writing a 1 to IPL14 sets it and writing a 0 has no effect.
IPDVINT <25>

IPL15

(RW)

Generate IPL 15 Interrupt

When the IPL15 bit is 1. the IPDVINT register generates an IPL 15 interrupt. As a result, it asserts
CIRQl/MIRQl. When the IPDVINT responds to an IPL 15 interrupt acknowledge, it clears the
IPL15 bit. When the FBIC is in diagnostic-isolate-test mode, the IPL15 bit is read/write. Otherwise,
writing a 1 to IPL15 sets it and writing a 0 has no effect.
IPDVINT<26>

IPL16

(RW)

Generate IPL 16 Interrupt

When the IPL16 bit is 1, the IPDVINT register generates an IPL 16 interrupt. As a result, it asserts
CIRQ2/MIRQ2. When the IPDVINT responds to an IPL 16 interrupt acknowledge, it clears the
IPL16 bit. When the FBIC is in diagnostic-isolate-test mode, the IPL16 bit is read/write. Otherwise,
writing a 1 to IPL16 sets it and writing a 0 has no effect.
IPDVINT<27>

IPL17

(RW)

Generate IPL 17 Interrupt

When the IPL 17 bit is 1, the IPDVINT register generates an IPL 17 interrupt. As a result, it asserts
CIRQ3/MIRQ3. When the IPDVINT responds to an IPL 17 interrupt acknowledge, it clears the
IPLl 7 bit. When the FBIC is in diagnostic-isolate-test-mode, the IPLl 7 bit is read/write. Otherwise,
writing a 1 to IPL17 sets it and writing a 0 has no effect.

30 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.1.19.8.

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5.1.19.9. WHAMI Register

The WHAMI register is a read/write register for use by operating system software as a unique who-am-i
identifier. The WHAMI register is also accessible to the local CPU as EPR 15. Figure 5-14 shows the bit
definitions for the WHAMI register.
Name: WHAM1

Address: XXFFFFDC#l6

Access: RW
0

DATA
WHAMI:

DATA
Figure 5-14:

WHAMI Register

WHAMI<31:0>

DATA

(RW)

Pointer to Processor-Specific Data

DAT A interpretation is specific to the operating system.

5.1.19.9. Firefox Bus Interface Chip

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Firefox System Specification 31

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5.1.19.10. CPUID Register

The CPUID register is a read-only register that uniquely identifies each processor in a Firefox wotkstation.
It is also accessible to the local CPU as EPR 14. Figure 5-15 shows the bit definitions for the CPUID register.
Address: XXFFFFD8#16

Name: CPU1D

Access: R

5 4

.rvmz
CPUID:

2 l 0

MID' P

i
I
I

MID
PROC
Figure 5-15:

CPUID Register

CPUID<l :0>

PROC

(R)

Processor Identifier

The PROC field uniquely identifies each processor for multiple-processor modules. It reflects the
value of the FBIC TYPAGNTE input pin in both bits. If the TYPAGNTE pin is 0, the PROC field is
0; if the TYPAGNTE pin is 1, the PROC field is 3.
CPUID<4:2>

MID (R)

Module Slot Identifier

The MID field reflects the values of the FBIC MID input pins.

32 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.1.19.10.

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5. 1. 19. 11. IADR1 Reg later

The IADR 1 register is the first of the two units used for an interlocked sequence in progress. When one
interlock is in progress, IADRl is used to hold the hexaword interlock address. It is accessible as a register
only for diagnostic purposes. IADRl must not be written during normal system operation; if it is, system
behavior will be unpredictable. Figure 5-16 shows the format of the IADR 1 register.
Name: IADRl

Address: XXFFFFD4#16

Access: RW

5 4

1 0

ADDRESS
IADRl:

ADDRESS

VALID
Figure 5-16:

IADR1 Register

IADRl<O> VALID

(RW)

Interlock Register Valid

When VALID is 1, IADRl contams the hexaword address of a locked region. The FBIC sets
VALID when an interlocked read transaction is issued on the M-bus and VALID is not already set.
The FBIC clears VALID when an unlock-write transaction for the hex.award specified by
IADRI<.ADDRESS> is issued on the M-bus. The FBIC also clears VALID when MABORT is
asserted
IADR1<31:5>

ADDRESS (RW)

Interlock Register Address

The ADDRESS field records the hexaword address of the currently interlocked region specified by
IADRl.

5. l.19.11. Firefox Bus Interface Chip

December 30, 1987

Firefox System Specification 33

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5.1.19.12. IADR2 Register

The IADR2 register is the second of the two units used for an interlocked sequence in progress. When one
interlock is already in progress, IADR2 is used to hold the hexaword interlock address of the second interlock. It is accessible as a register only for diagnostic purposes. IADR2 must not be written during normal
system operation; if it is, system behavior will be unpredictable. Figure 5-17 shows the format of the
IADR2 register.
Address: XXFFFFDO#l 6

Name: IADR2

Access: RW

5 4

ADDRESS
IADR2:

0
MBZ

,v;I

ADDRESS

VALID
Figure 5-17:

IADR2 Register

IADR2<0> VALID

(RW) Interlock Register Valid

When VALID is 1, IADR2 contains the hexaword address of a locked region. The FBIC sets
VALID when an interlocked read transaction is issued on the M-bus and IADRl<VALID> is set.
The FBIC clears V AUD when an unlock-write transaction for the hexaword specified by
IADR2<ADDRESS> is issued on the M-bus. The FBIC also clears VALID when MABORT is
asserted.
IADR2<31 :5>

ADDRESS (RW)

Interlock Register Address

The ADDRESS field records the hexaword address of the currently interlocked region specified by
IADR2.

34 Firefox System Specification

December 30, 1987

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5.1.19.13. SAVGPR Register

The SA VGPR register is a read/write. temporary-storage register for use by console software during processor HALT handling. The SAVGPR register is also accessible to the local CPU as EPR 41. Figure 5-18
shows the bit definitions for the SAVGPR register.
Address: XXFFFFC4# 16

Name: SA VGPR
3
l

Access: RW
0

DATA
SAVGPR:

DATA
Figure 5-18:

SAVGPA Register

SAVGPR<31:0> DATA

(RW)

Save General-Purpose Register

DAT A use is specific to the console software.

5.2. Interface
The FBIC has four groups of signals that implement the CVAX pin-bus interface, the M-bus interface, the
external-cache interface. and miscellaneous external logic and datapath control. Table 5-10 lists the FBIC
pin signals and their functions. The signal type "I" refers to an input with respect to the FBIC. The signal
type do·· refers to an output with respect to the FBIC. The signal type "I/0" refers to both.

5.2. Firefox Bus Interface Chip

December 30, 1987

Firefox System Specification 35

DIGITAL EQCIPMENT CORPORATION - RESTRlCTED DISTRlBL'TIO~

TableS-10:

Group
CBUS

MBUS

FBIC Plnout

Signal
CDAL
CCSDP
COPE
CAS
CDS
CBM
CWR
CRDY
CERR
CCCTL
CDMR
CDMG
CRESET
SYS RESET
CHALT
CIRQ
CRD
MEMERR
CCLKA
CCLKB
CCLKC

MBRM
MBRP
MYMBRQ
MB US YI
MBUSYO
MCMD
MSTATIJS
MDAL
MCPAR
MSPAR
l\IDPAR
MCDRV
MSDRV
MDDRV
MSHAREDI
MSHAREDO
MDATINVI
MDATINVO
MID
MRESET
MABORTI
MAB ORTO
:MIR.QI
MIRQO
MHALT
MCLKA
MCLKB

36 Firefox System Specification

Assert
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H

L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H

Count
32
4
1
1
1
4
1
1
1

1
1

1
1
1
1
4

1
1
1

Type
1/0
1/0
I/0
I/0
I/0
I/0
I/0
I/0
1/0
0
1/0
1/0
I
0
0
I/O
0
0

I
I
I

Subtotal

I
I
0
I
0
1/0
1/0
I/O
I/O
I/0
1/0
0
0
0
I

1
1
1
4

2
32
1
1
1
1
1
1

1
1
1
1

0
I
0

3
1
1

I
I
I

1
4
4
1
l
l

0
I

0
I
I
I

Function
Data and address
Cycle status/data parity
Data-parity enable
Address strobe
Data strobe
Byte mask
Write/read
Ready
Error
Cache control
OMA request
OMA grant
Synchronous RESET
Asynchronous RESET
HALT
Interrupt request
Corrected read data
Memory error
Clock A
ClockB
ClockC

Module M-bus requests
Partner M-bus request
Local M-bus request
Slave-busy input
Slave-busy output
M-bus cycle command
M-bus cycle status
Data and address
MCMDparity
MSTATIJS parity
MDALparity
MCMD xcvr direction
MSTATIJS xcvr direction
MDAT xcvrdirection
Shared line input
Shared line output
Data-invalid input
Data-invalid output
Module ID
System reset
Transaction-abort input
Transaction-abort output
Interrupt requests input
Interrupt requests output
Halt CPU input
M-bus clock-A phase
M-bus clock-B phase

Subtotal

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Firefox Bus Interface Chip 5.2.

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Group

Signal

Assert

Count

Type

Function

CACHECTRL

TCACHE
TAGSH
TAG DR
TAGPAR
TAG\VE
TAGCE
DATCE
DATWE
XOE
ECL
CTINDX_OE
MTINDX_LE
MTINDX_OE

H
H
H
H
L
L
L
L

13
1
l
I

I/O
I/O
I/O
I/O

0
0

l
L
H
1
l
l

0
1
1
0
0
0

Tag cache
Tag shared signal
Tag dirty signal
Tag parity
Tag-cache write enable
Tag-cache chip enable
Data-cache chip enable
Data-cache write enable
0
0
CVAX pin-bus tag-index output enable
M-bus tag-index latch enable
M-bus tag-index output enable

Subtotal

2
1
l
1
l
4
1
1
1

I
I
I
I
I
I
0
I

MISC

MODCL
TYPDUAL
TYPAGNTE
TYPRET
TYPSYNC
DEVIRQ
ROMOE
ROMWID32
ROMWADDR
MNFMOD
LEDS
TESTOUT
TRISTATE

L
H
L

H
H
H
H
H
L
L
H
H
L
L
H
H

6
1

0
0
I

Subtotal

188

SIGNALS
RESERVED
VDD

vss

Signal pins
Spare pins
Supply pins
Ground pins

223

Total

Module class
Dual module
A processor/grantee
Retriable
Synchronous bus
Device-interrupt requests
External-ROM output enable
External-ROM width 16/32
External-ROM word address
Manufacturing mode
LED value
Test output
Tristate all FBIC pins

In the following pages, the four groups of FBIC pins are described in detail.
5.2.0.1. CVAX Pin-Bua Plnout Group

The CV AX pin-bus group consists of those FBIC pins that are connected to the local CVAX pin-bus. The
signal descriptions are from the perspective of the FBIC. Unless otherwise noted, signal descriptions apply
to FBIC operation as both a CVAX pin-bus master and a CVAX pin-bus slave. Unless otherwise noted,
signal descriptions apply to both synchronous and asynchronous CVAX pin-busses. The pins that make up
this group are described here.
5.2.0.1.1. CDALc31 :0>-Data/Address Lines

The CDAL is a 32-bit, time-multiplexed bus used to transfer all data and address information on the CV AX
pin-bus. The CV AX pin-bus master drives COAL with an address around the falling edge of CAS. The
CV AX pin-bus slave drives COAL with data for memory-space reads, 1/0-space reads, EPR reads, and
interrupt acknowledges until the rising edge of CDS. The CV AX pin-bus master drives CDAL with data

5.2.0. l. l. Firefox Bus Interface Chip

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for memory-space writes, I/0-space writes, and EPR writes until the rising edge of CDS.
For memory-space addresses, CDAL<31 :30> indicates the length of the transfer as shown in Table 5-11.
CDAL<29> is 0, CDAL<28:2> specifies the longword address of the operand, and CDAL<l:O> is
undefined. Quadword, hexword, and octaword transfers are all within the same naturally aligned region for
the transfer size. Table 5-12 shows the implied sequencing of CDAL<3 :2> for such references.
Table 5-11:

Transfer-Length Encoding

CDAL<31:30>
00
01
10
11

Table 5-12:

Length

3 longwords
l longword
2 longwords
4 longwords

Quad/Hex/Octaword Implied Address Sequencing

CDAL<3:2>

Second Address

Third Address

01
00

01
10
11

11
00

Fourth Address
11
10
01
00

For I/0-space addresses, CDAL<3 l :30> indicates the length of the transfer, which must be one longword
or behavior will be unpredictable. CDAL<29> is 1, CDAL<28:2> specifies the longword address of the
operand, and CDAL<l :0> is undefined.
For EPR addresses, CDAL<31:8> is undefine~ CDAL<7:2> specifies the register, and CDAL<l:O> is
undefined.
For intenupt-acknowledge addresses, CDAL<31 :7> is undefined, CDAL<6:2> specifies the IPL of the
intetrupt being acknowledged, and CDAL<l:O> is undefined.
For memory-space, 1/0-space, and EPR reads, CDAL<31:0> specifies the data. For interrupt acknowledges, CDAL<31:16> is undefined and CDAL<15:0> specifies the vector. For memory-space, I/0space, and EPR writes, CDAL<31:0> specifies the data

5.2.0.1.2. CCSDPc3:0>-Cycle Status/Data Parity

During the address portion of a CVAX pin-bus transaction, the cycle-status lines, in conjunction with the
CWR signal, characteri7.e the type of cycle occurring on the CVAX pin-bus. Table 5-13 shows the specific
encoding ~~ the pins around the falling edge of CAS.

38 Firefox System Specification

December 30, 1987

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Table 5-13:

Encoding for the CCSDP Cycle Type

CWR
1

CCSDP<2:0>

CV AX Pin-Bus Cycle Type

FDIC Cycle Type

000
001
010
011
100
101
110
111

Request D-stream read
Reserved
EPR read
Interrupt acknowledge
Request I-stream read
Demand D-strearn read (lock)
Demand D-strearn read with modify intent
Demand 0-strearn read (no lock or modify intent)

Read
UPREDICTABLE
EPR read
Interrupt acknowledge
Read
Read interlocked
Read
Read

0
0
0
0
0
0
0
0

000
001
010
011
100
101
110
111

Reserved
Reserved
EPR write
Reserved for OMA-device use
Reserved
Write unlock
Reserved
Write no unlock

UNPREDICTABLE
UNPREDICTABLE
EPR write
UNPREDICTABLE
UNPREDICTABLE
Write unlock
UNPREDICTABLE
Write

As a CVAX pin-bus master. the FBIC generates only transactions involving demand 0-stream read,
demand D-strearn read interlocked. write. write unlock, and interrupt acknowledge.
During the data portion of CV AX pin-bus transactions. CCSOP<3:0> specifies byte parity for COAL.
Even parity is checked/generated on even bytes; odd parity, on odd bytes. Even parity will drive a 0 when
there are an even number of ls in the byte's data; odd parity will drive a 0 for an odd number of ls. Table
5-14 lists the correspondence of CCSOP signals and COAL bytes. If COPE is asserted. the device that
sources data onto COAL is generating parity for all bytes and the device that sinks data from COAL can
check parity for the bytes specified by CBM<3:0>.
The FBIC always generates parity when it drives the COAL with data. If it is supplying data it obtained
from the M-bus with :MDATINV asserted, the FBIC intentionally generates invalid parity on the CVAX
pin-bus. Otherwise, it generates valid parity on the CVAX pin-bus. It checks parity when it receives data
from COAL and COPE is asserted
Table 5-14:

Byte Correspondence Between CCSDP and COAL

CCSDP

CDAL

<3>
<2>
<1>
<0>

<31:24>
<23:16>
<15:08>
<07:00>

5.2.0.1.3. CDPE<O>-Data-Parlty Enable

When COPE is asserted. the device that sinks data from COAL/CCSOP should check parity. When COPE
is deasserted, the device that sinks data from COAL/CCSDP must not check parity.
The FBIC asserts the COPE signal whenever the FBICSR<CDPE> bit is asserted and either it or the external data store is driving data onto the CVAX pin-bus. except during CV AX ROM reads.
The COPE signal requires an external pull-up resistor (nominally 600 ohms).

5 .2.0.1.4. Firefox Bus Interface Chip

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5.2.0.1.4. CAScO>-Address Strobe

A CV AX pin-bus master asserts CAS when the COAL. CCSDP, and CWR signals contain valid information during the address portion of a CV AX pin-bus transaction. A CVAX pin-bus slave latches these signals at that time, and it interprets them as an address and transaction specifier.
The CV AX pin-bus master continues to assert CAS until the transaction ends. The rising edge of CAS
always terminates a CV AX pin-bus transaction, whether CRDY/CERR has been asserted or not.
When the FBIC generates octaword reads and writes on the CV AX pin-bus to maintain the external-cache
data store, it does not assert the CRDY/CERR signals. Nor does it assert the CRDY/CERR signals when it
generates 1/0 reads on the CV AX pin-bus to access the ROM.
The CAS signal requires an external pull-up resistor (nominally 2K ohms).
5.2.0.1.5. CDScO>-Data Strobe

The CDS signal provides timing information for asynchronous data transfers on the CV AX pin-bus. During
a memory read (single or multiple transfer}, I/O read, EPR-read, or interrupt acknowledge, the CVAX pinbus master asserts CDS to indicate that CDAL<31 :0> and CCSDP<3 :0> are free to receive incoming data
and deasserts CDS to indicate that it has received and latched the incoming data During a memory write,
1/0 write, or EPR write, the CV AX pin-bus master asserts CDS to indicate that CDAL<31 :O> and
CS/DP<3:0> contain valid outgoing data and deasserts CDS to indicate that the data is about to be
removed.
When operating as a synchronous CVAX pin-bus slave, the FBIC does not monitor CDS; data transfers
always occur during successive CVAX pin-bus cycles.
The CDS signal requires an external pull-up resistor (nominally 2K ohms).
5.2.0.1.6. CBMc3:0>-Byte Mask

The CBM signals specify which bytes of the COAL bus contain valid information during the data portion
of a CV AX pin-bus cycle. The CVAX pin-bus master supplies byte masks for each longword of
quad/hex/octaword transfers. Table 5-15 lists the correspondence between CBM signals and CDAL bytes.
Table S-15:

Byte Correspondence Between CBM and COAL

CBM

CDAL

<3>
<2>
<1>
<0>

<31:24>
<23:16>
<15:08>

<07:00>

When th~ .FBIC is a CVAX pin-bus slave for memory writes, 1/0 writes, and EPR writes, it supports all
possible bYte maks. As a CVAX pin-bus slave for memory reads, 1/0 reads, EPR reads, and interrupt acknowledges. it ignores the byte masks.
To control which bytes are written with M-bus shared write-through data, the FBIC uses the CBM signals
during octaword writes to the external-cache data store.
5.2.0.1.7. CWRcO>-Wrlte

The CWR signal specifies the direction of data transfer on the CDAL bus. If CWR is asserted, the CV AX
pin-bus master is driving data onto the COAL. If it is deasserted. the CVAX pin-bus master is receiving
data from the COAL. CWR is valid around the falling edge of CAS.
CWR must be stable throughout the assertion of CAS or behavior is unpredictable.

40 Firefo:it System Specification

December 30, 1987

Firefo:it Bus Interface Chip 5.2.0.1.8.

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5.2.0.1.8. CROY cO>-Ready

The CV AX pin-bus slave asserts the CRDY signal to indicate normal tennination of the current CVAX
pin-bus tranSaction. During a CV AX pin-bus memory-read. 1/0-read. EPR read, or interrupt-acknowledge
transaction. CRDY indicates that the CV AX pin-bus slave has placed the requested data on the COAL bus
in time for the next sampling point. During a CV AX pin-bus memory-write, I/0-write, or EPR-write transaction. CROY indicates that the information on the COAL bus has been received and can be removed following the next sampling point. Upon assertion of CRDY, the CVAX pin-bus master terminates the current
CV AX pin-bus transaction. and the CV AX pin-bus slave deasserts CRDY.
The CROY signal requires an external pull-up resistor (nominally 600 ohms).
5.2.0.1.9. CERR<O>-Error

The CVAX pin-bus slave asserts the CERR signal to indicate abnormal termination of the current CV AX
pin-bus transaction. The interpretation of CERR depends on whether CROY is also asserted. When CERR
and CRDY are asserted simultaneously, the CVAX pin-bus master will retry the current bus cycle. When
CERR is asserted and CRDY deasserted, the CV AX pin-bus master will abort the current bus cycle. To
eliminate timing hazards associated with CERR and CRDY synchronizers, the CV AX pin-bus master interprets as a retry, assertion of CERR followed by assertion of CERR and CRDY.
If retries are specified for the second, third, or fourth longword of a quad/hex/octaword memory transaction, behavior is unpredictable.
The CERR signal requires an external pull-up resistor (nominally 600 ohms).
5.2.0.1.10. CCCTLcO>-Cache Control

The CCCTL signal can be used to generate CV AX cache invalidates and to suppress CVAX data caching.
The FBIC always drives the CCCTL signal, even if it is not the current CVAX pin-bus master. It uses
CCCTL only to generate the CV AX octaword cache invalidates as required to maintain the external-cache
data store.
The CCCTL signal requires an external pull-up resistor (nominally 600 ohms).
5.2.0.1.11. CDMRcO>-DMA Requ..t

The CO:MR signal is asserted by a CV AX pin-bus slave when it wishes to ta.lee control of the COAL bus
and related control signals for OMA or other purposes. When the CV AX pin-bus master observes CDMR
asserted, it completes the current CVAX pin-bus transaction, tristates the CVAX pin-bus control and data
signals, and asserts CDMG. When the CVAX pin-bus master observes CDMR dea,,serted, it deasserts
COMG and resumes driving the CVAX pin-bus control and data signals.

If the FBIC is the CVAX pin-bus grantor, it monitors CO:MR and asserts COMG when it relinquishes the
CVAX. pin-bus. As CVAX pin-bus grantee, it asserts CD:MR when it requires the CVAX pin-bus and
monitors COMO. It determines its grantor/grantee role from the TYPDUAL(TYPAGNTE input pins.
The CD:MR signal requires an external pull-up resistor (nominally 600 ohms).
5.2.0.1.12. COMG<O>·-OMA Grant

The CDMG signal is asserted by the CV AX pin-bus master to grant to a CV AX pin-bus slave control of
both the CDAL bus and related control signals. The CV AX pin-bus master tristates the COAL, CAS, CDS,
CBM, COPE, CCSDP, and CWR signals. When the CV AX pin-bus slave deasserts COMR., the CV AX
pin-bus master responds by deasserting CDMG and starting the next bus cycle.
If the FBIC is the CVAX pin-bus grantor. it monitors CD:MR and asserts COMG when it relinquishes the
CV AX pin-bus. As CV AX pin-bus grantee, it asserts CD'MR when it requires the CV AX pin-bus and

5.2.0.1.12. Firefoll Bus Interface Otip

December 30, 1987

Fircfoll System Specification 41

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monitors CDMG. The FBIC detennines its grantor/grantee role from the TYPDUALffYPAGNTE input
pins.
5.2.0.1.13. CRESET<0>-Synchronous RESET

\Vhen CRESET is asserted. all CV AX pin-bus devices initialize their internal logic and return to an idle
state. While CRESET is asserted, the CV AX pin-bus default master tristates the COAL, COPE, CBM,
CWR. CCSDP. CAS, and CDS signals.
5.2.0.1.14. SYSRESETcO>-Asynchronous RESET

When SYSRESET is asserted, module logic synchronizes it to generate the CRESET signal. The FBIC
asserts SYSRESETwhen FBICSR<RESET> or .MRESET is asserted.
The SYSRESET signal requires an external pull-up resistor (nominally 600 otuns).
5.2.0.1.15. CHALT c0>-HALT

\Vhen the CHALT signal makes a deasserted-to-asserted transaction, CV AX processors initiate a HALT.
The FBIC asserts CHALT when FBICSR<HALTEN> AND (FBICSR<HALTCPU> OR
is true.

MHALn

The CHALT signal requires an external pull-up resistor (nominally 600 ohms).
5.2.0.1.16. Cl RQ<3 :0>-lnterrupt Requests

The CIRQ signals specify an interrupt request. Table 5-16 lists the correspondence of CIRQ signals to
interrupt priority levels. The CIRQ signals are level-sensitive. The FBIC can be programmed to forward
assertions of CIRQ signals onto MIRQ signals (for non-CPU modules) or assertions of MIRQ signals onto
CIRQ signals (for CPU modules).
Table 5-16:

CIRQ
<3>
<2>
<1>
<0>

CIRQ Interrupt Priority Levels

IPL
17
16

15
14

The CIRQ signals requires external pull-up resistors (nominally 600 ohms).
5.2.0.1.17. CADcCb-Corrected Read Data

The CRD :signal allows a CVAX pin-bus slave to indicate that data supplied to the CVAX pin-bus had a
corrected single-bit ECC error. In the CVAX, CRD interrupts at IPL lA (SCB vector 54#16). A corrected
read-data interrupt is not acknowledged by the CVAX.
The FBIC asserts CRD when it obtains corrected data from an M-bus memory read.
The CRD signal requires an external pull-up resistor (nominally 600 otuns).
5.2.0.1.18. MEMERR<O>-Memory Error

The MENIBRR signal allows the CVAX pin-bus slave to signal a memory/M-bus error to the CV AX pinbus. In the CV AX • .ME:MER.R intenupts at IPLlD (SCB vector 60#16). A MEMERR intenupt is not acknowledged by the CV AX.

42 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.2.0. l.l 8.

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The FBIC asserts MEMERR when it supplies data with a parity error onto the M-bus or when a M-bus
abon occurs.
The r-.1EMERR signal requires an external pull-up resistor (nominally 600 ohms).
5.2.0.1.19. CCLKA<O>, CCLKB<O>, CCLKC<O>-Clocks A, B, and C

CCLKA, CCLKB. and CCLKC are the clocks for the CV AX pin-bus. CCLKA and CCLKB are squarewave signals that are phase-shifted 180 degrees. CCLKC is a square-wave signal that is inphase but half
the frequency of CCLKA. It is used to distinguish CVAX pin-bus phase Pl from CV AX pin-bus phase P3.
The FBIC supports a CV AX pin-bus cycle time of 70 to 100 ns for modules that do not have an external
cache and a CV AX pin-bus cycle time of 70 to 80 ns for modules that do have an external cache.
5.2.0.2. M-Bus Plnout Group
The M-bus pinout group consists of those FBIC pins that are connected to the M-bus, either directly or
through external transceivers/buffers. Operation of the M-bus interface is as defined by the Firefox M-Bus

Specification. A detailed description of the M-bus signals can be found in that document. The pins themselves are described here.
5.2.0.2.1. MBRMc6:0>-Request Monitor

1be M-bus MBRM signals are the M-bus requests from the other backplane sloes. 'The FBIC MBRM signals connect directly to the M-bus MBRM signals for the backplane slot.
5.2.0.2.2. MBRPcO>-Partner Request Monitor

The FBIC MBRP signal connects to the MYMBRQ output of the other FBIC on a dual-FBIC module. It is
used to resolve intramodule M-bus arbitration in the same fashion that the M-bus MBRQ signals resolve
intermodule M-bus arbitration.
5.2.0.2.3. MYMBRQcO>-Aequeat Output

The M-bus MBRQ signal indicates that a module is in arbitration for the M-bus, or that it is driving the Mbus as master/slave. The FBIC MYMBRQ signal drives the M-bus MBRQ signal for the backplane slot
through a 74F244-class buffer. To form the module :MBRQ signal on dual-FBIC modules, the two FBIC
MnvIBRQ signals must be logically ORed together with external logic.
5.2.0.2.4. MBUSYlc0>/MBUSY0c0>-MBUSY Input/Output

When assert~ the M-bus MBUSY signal stalls commencement of new M-bus transactions. The FBIC
MBUSYI signal connects directly to the M-bus :MBUSY signal. The FBIC MBUSYO signal drives the
M-bus ~USY signal through a 74AS760-class open-collector buffer.
5.2.0.2.5. MCMDc3:0>-Tranaactlon Command

The M-bus MC~ signals specify transaction type, memory-write byte masks, and I/0 byte masks from
M-bus masters. The FBIC MC:MD signals connect to the M-bus MC~ signals through an external
74F245 transceiver. By default, the FBIC MC~ signals are inputs so two FBICs can share an M-bus
transceiver.
5.2.0.2.6. MST ATUSc1 :0>-Transaction Status

The M-bus MST A TUS signals specify transaction status from M-bus slaves. The FBIC MST ATUS signals
connect to the M-bus MSTATUS signals through an external 74F245 transceiver. By default, the FBIC
MST ATIJS signals are inputs so two FBI Cs can share an M-bus transceiver.

5.2.0.2.7. Firdox Bus Interface Chip

December 30, 1987

Firefox System Specification 43

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5.2.0.2.7. MDAL<31 :0>-Transactlon Data/Address

The M-bus MDAL signals specify M-bus transaction addresses and data. The FBIC MDAL signals connect
to the M-bus MDAL signals through external 74F245 transceivers. By default, the FBIC MDAL signals
are inputs so two FBICs can share a set of M-bus transceivers.
5.2.0.2.8. MCPAR<O>-Transaction Command Parity

The M-bus MCPAR signal specifies even parity for the M-bus MCMD signals. The FBIC MCPAR signal
connects to the M-bus MCPAR signal through an external 74F245 transceiver. By default, the FBIC
MCPAR signal is an input so two FBICs can share an M-bus transceiver.
5.2.0.2.9. MSPAR<O>-Transactlon Status Parity

The M-bus MSPAR signal specifies even parity for the M-bus MSTATUS signals. The FBIC MSPAR signal connects to the M-bus MSPAR signal through an external 74F245 transceiver. By default, the FBIC
MSPAR signal is an input so two FBICs can share an M-bus transceiver.
5.2.0.2.10. MDPARc<»-Transaction Data/Address Parity

The M-bus MDPAR signal specifies even parity for the M-bus :MDAL signals. The FBIC MDPAR signal
connects to the M-bus :MDPAR signal through an external 74F245 transceiver. By default, the FBIC
:MDPAR signal is an input so two FBI Cs can share an M-bus transceiver.
5.2.0.2.11. MCDRVc0>-Transactlon Command Drive

The FBIC MCDRV signal controls the direction of the external 74F245 transceivers for the FBIC
MCMD/MCPAR signals. To form the module MCDRV signal on dual-FBIC modules, the two FBIC
MCDRV signals must be logically ORed together with external logic.
5.2.0.2.12. MSDRVcO>-Transactlon Status Drive

The FBIC MSDRV signal controls the direction of the external 74F245 transceivers for the FBIC
MSTATUS/MSPAR signals. To form the module MSDRV signal on dual-FBIC modules, the two FBIC
MSDRV signals must be logically ORed together with external logic.
5.2.0.2.13. MDDRVcO>-Transactlon Data/Addreu Drive

The FBIC :MDDRV signal controls the direction of the external 74F245 transceivers for the FBIC
MDAL/MDPAR signals. To fonn the module :MDDRV signal on dual-FBIC modules, the two FBIC
MDDRV signals must be logically ORed together with external logic.
5.2.0.2.14. MSHAAEDlcO>/MSHAAEDOcO>-MSHAAED Input/Output

The M.:.bus MSHARED signal indicates that the memory octaword referenced by the cunent tramaction is
shared. The FBIC MSHAREDI signal connects directly to the M-bus MSHARED signal. The FBIC
MSHAREDO signal drives the M-bus MSHARED signal through a 74AS760-class open-collector buffer.
5.2.0.2.15. MDATINVlcO>IMDATINVOcO>-MDATINV Input/Output

The M-bus MDATINV signal indicates that the data on :MDAL had an internal module-parity error. The
FBIC MDATINVI signal connects directly to the M-bus :MDATINV signal. The FBIC :MDATINVO signal drives the M-bus :MDATINV signal through a 74AS760-class open-collector buffer.

44 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.2.0.2.16.

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5.2.0.2.16. Ml0c2:0>-Module ID

The WD signals uniquely identify each M-bus backplane slot with a value from 0 to 7. The FBIC MID
signals connect to the module M-bus rvnD signals through 47-ohm series resistors.
5.2.0.2.17. MR ES ETc0>-System Reset

When the MRESET signal is asserted, the entire workstation is reinitialized. The FBIC MRESET signal
connects directly to the M-bus 'MRESET signal.
5.2.0.2.18. MABORTlcO>IMABORTOcO>-MABORT Input/Output

The M-bus MABORT signal indicates that an error has occurred on the M-bus. The FBIC MABORTI signal connects directly to the M-bus MABORT signal. The FBIC MABORTO signal drives the M-bus
MABORT signal through a 74AS760-class open-collector buffer.
5.2.0.2.19. MIRQlc3:0>/MIRQOc3:0>-lnterrupt Requests

The M-bus l\1IRQ signals are asserted to indicate a pending interrupt. The FBIC MIRQI signals connect
directly to the M-bus .MIRQ signals. The FBIC MIRQO signals drive the M-bus MIRQ signals through a
74AS760-class open-collector buffer.
5.2.0.2.20. MHALTcO>-Processor Halt

The M-bus .MHALT signal is asserted to halt all processors. The FBIC MHALT signal co1U1ects directly to
the M-bus .MHALT signal.
5.2.0.2.21. MCLKAcO>-Clock·A Phase

MCLKA is the master clock for the M-bus. The FBIC MCLKA signal connects directly to the M-bus
MCLKA signal for the backplane slot.
5.2.0.2.22. MCLKBcO>-Clock-B Phase

MCLKA is the slave clock for the M-bus. The FBIC _MCLKB signal connects directly to the M-bus
MCLKB signal for the backplane slot.
5.2.0.3. Cache-Control Plnout Group

The cache-control pinout group consists of those FBIC pins that control and tramfer data to the extemalcache tag and data stores. The pins that make up this group are described here.
5.2.0.3.1. TCACHEc12:0>-Tag Cache

The TCACHE signals transfer 13 bits of data between the FBIC and an external-cache tag store. The FBIC
has exclusive control over these pins and uses them to read and write the tag store in order to perfonn tag
compares and update the cache entry. The TCACHE signals are the high-order 13 bits of the CVAX pinbus physical address, namely CDAL<28: 16>.
5.2.0.3.2. T AGSHcO>-Tag Shared

The T AGSH signal transfers the shared bit between the FBIC and the external-cache tag store.

5.2.0.3.3. Firefox Bus [ntcrfacc Chip

December 30, 1987

Firefox System Specification 45

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5.2.0.3.3. TAGDRcO>-Tag Dirty

The T AGOR signal transfers the dirty bit between the FBIC and the external-cache tag store.
5.2.0.3.4. TAGPARcO>-Tag-Cache Parity

The TAGPAR signal transfers 1 bit of parity for the 15-bit external-cache tag-store entry. The tag entry is
composed of a 13-bit address, a shared bit, and a dirty bit, as described earlier. Even parity is
checked/generated for all 15 bits.
5.2.0.3.5. TAGWEcO>-Tag-Cache Write Enable

The TAGWE signal controls modification of the external-cache tag store. When TAGWE is a 0, the external tag-store RAMs are in write mode. When T AGWE is a 1, the external tag-store RAMs are in read
mode.
5.2.0.3.6. TAGCEcO>-Tag-Cache Chip Enable

The T AGCE signal controls access to the external-cache tag store. When T AGCE is a 0, the external tagstore RAMs are enabled. When T AGCE is a 1, the external tag-store RAMs are disabled.
5.2.0.3.7. DATCEc3:0>-Data-Cache Chip Enable

The DATCE signals control access of individual bytes in the longword external-cache data store. If
DATCE<3> is asserted, the RAMs transfer data to/from CDAL<31:24>. If DATCE<2> is asserted, the
RAMs transfer data to/from CDAL<23:16>. If DATCE<l> is asserted, the RAMs transfer data to/from
CDAL<15:8>. IfDATCE<O> is asserted, the RAMs transfer data to/from CDAL<7:0>.
5.2.0.3.8. DATWEcO>-Data-Cache Write Enable

The DATWE signal controls direction of the external-cache data-store transceivers and the write enable to
the RAMs. When DAT\VE is a 1, data is driven from the CVAX pin-bus into the RAMs. When DATWE
is a 0, data is driven from the RAMs onto the CVAX pin-bus.
5.2.0.3.9. XOEcO>-Data-Cache Transceiver Output Enable

The XOE signal controls the output enable of the external-cache data-store transceivers. When XOE is a 1,
the transceivers are ttistated. When XOE is a 0, the transceivers drive data onto the CVAX pin-bus or
toward the external-cache data store RAMs depending on the value of DATWE.
5.2.0.3.1 O. ECL.cO>-Dat.Cache Counter Enable

The ECL signal gates the clock signal to the two-bit, external-cache address latch fed by the external-cache
address c~. When ECL is a l, the clock signal should be enabled to the latch. When ECL is a 0, the
clock sigrial should be disabled from reaching the latch, and the transparent latch should remain closed.
This signal allows tag probes from the M-bus to preempt an ongoing CV AX pin-bus cycle that may need to
update the external-cache tag-store.
5.2.0.3.11. CTINDX_OEcO>-CV AX Pin-Bua Tag-Index Output Enable

The CTINDX_OE signal enables the CVAX pin-bus address latch for the external-cache tag store. The
latch captures the middle 12 bits of an octaword address, namely CDAL<l5:4>. The CTINDX_OE signal
connects directly to the CVAX pin-bus address-latch output-enable pin.

46 Firefo;11. System Specification

December 30, 1987

Firefox Bus Interface Cbip 5.2.0.3.12.

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5.2.0.3.12. MTINDX_LE<O>-M·Bus Tag-Index Latch Enable

The l\tfITNDX_LE signal is a iatch-enable signal for the external latch that indexes into the external tag
score from the M-bus. The latch captures the middle 12 bits of an M-bus octaword address, namely
MDAL<l5:4>. When MTINDX_LE and MCLKB are asserted, the latch should be transparent.
5.2.0.3.13. MTINOX_OE<O>··M-Bus Tag-Index Output Enable

The MTINDX_ OE signal enables the M-bus address latch for the external-cache tag store. The latch captures the middle 12 bits of an octaword address, namely rv1DAL<l5:4>. The MTINDX_OE signal connects directly to the M-bus address-latch output-enable pin
5.2.0.4. Miscellaneous Plnout Group

The miscellaneous pinout group consists of all FBIC pins that do not fall within one of the other three
groups. They are described here.
5.2.0.4.1. MOOCLc1 :0>-Module Class

These input-only signals indicate to the FBIC the class of module on which the chip is physically located.
To be able to identify the correct module to the FBIC, these signals must be tied to power and ground
through resistors in the manner shown in Table 5-17.
Table 5-17:

M-Bus Defined Module Classes

MODCL

Class
Bus adapter
Graphics
I/O
CPU

00
01
10
11

5.2.0.4.2. TYPDUALcO>-Dual-FBIC Module

The TYPDUAL input pin indicates whether the module bas one or two FBICs. If TYPDUAL is
deasserted, the FBIC is the only one on a module, and it responds to the full 32-Mbyte, slot-specific, M-bus
I/0-space region If TYPDUAL is asserted, the FBIC is one of two FBICs. and responds only to the upper
or lower 16 Mbytes of the slot-specific, M-bus 1/0-space region. If an FBIC is on a dual module, the FBIC
always functions as a CV AX pin-bus grantee.
5.2.0.4.3. TYPAGNTEcO>-AIB Proceuor or CVAX Pin-Bua Grantee

When the TYPDUAL pin is asserted, the TYPAGNTE input pin indicates whether the FBIC is associated
with the A or B processor of a dual-processor module. If TYPAGNTE is deasserted, the FBIC is the B
processor
responds to the lower 16 Mbytes of the 32-Mbyte, slot-specific, M-bus 1/0-space region. If
TYPAGNTE is asserted. the FBIC is the A processor and responds to the upper 16 Mbytes of the 32Mbyte, slot-specific, M-bus I/0-space region.

and

When the TYPDUAL pin is deasserted, the TYPAGNTE indicates whether the FBIC is the default CVAX
pin-bus master. If TYP AGNTE is deasserted, the FBIC is the CVAX pin-bus grantor and monitors CDMR
and drives CDMG. If TYPAGNTE is asserted, the FBIC is the CVAX pin-bus grantee and drives CDMR
and monitors CDMG.

5.2.0.4.4. Firefox Bus Interface Chip

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Firefox System Specification 47

DIGITAL EQUIPMENT CORPORATtor; - RESTRICTED DISTR1Btrno.;-.;

5.2.0.4.4. TYPRET<0>-CV AX Pin-Bus Retrtable

The TYPRET input pin indicates whether the FBIC can retry the CVAX pin-bus master to complete a
deadlocked M-bus transaction. If TYPRET is deasserted and the CVAX pin-bus has a pending M-bus transaction, the FBIC retries M-bus I/0-space and interrupt-acknowledge transactions that require the CV AX
pin-bus. If TYPRET is asserted, and the CVAX pin-bus has a pending M-bus transaction. the FBIC retries
the CV AX pin-bus when M-bus 1/0-space and interrupt-acknowledge transactions require the CV AX pinbus.
5.2.0.4.5. TYPSYNC<O>-CV AX Pin-Bus Synchronous

The TYPSYNC input pin indicates whether the CV AX pin-bus is synchronous or asynchronous. If TYPSYNC is deasserted, the CV AX pin-bus is asynchronous, and the FBIC performs a full handshake of the
CDS and CRDY/CERR signals. If TYPSYNC is asserted, the CVAX pin-bus is synchronous and the FBIC
initiates external cache tag-store probes before CAS is asserted; in addition, it does not monitor CDS with
respect to CRD Y/CERR assertion/deassertion.
5.2.0.4.6. DEVIRQc3:0>-Devlce-lnterrupt Requests

The DEVIRQ input pins are edge-sensitive equivalents of the IPDVINT<IPL17:IPL14> bits when the
IPDVINT register is operating as a device-interrupt unit.
5.2.0.4.7. ROMOEcO>-External-ROM Output Enable

When ROMOE is asserted, the external diagnostic/self-test ROM(s) drive CDAL. The FBIC asserts
ROMOE during ROM assembly.
5.2.0.4.8. ROMWID32c0>-External-ROM Width

If ROMWID32 is deasserted, the ROM is 16 bits wide and requires two word reads to assemble a
longword. If ROMWID32 is asserted, the ROM is 32 bits wide and does not require assembly. The
ROMWID32 input pin connects to power/ground through a 47-ohm series resistor, as appropriate.
5.2.0.4.9. ROMWADDRcO>-Extemal-ROM Word Addrna

The ROMWADDR signal specifies the LSB of the word address for 16-bit ROM. It connects directly to
the LSB address line of an external 16-bit ROM. For external 32-bit ROM, it is left unconnected
5.2.0.4.1 O. MNFMOD-Manufacturlng Mode

The :MNFMOD input pins specify the value of the FBICSR<MFMD> bits. These pins require an external
lK-ohm pull-up resistor.
5.2.0.4.tt;. L!DScCb-LEDa V•lue

The LEDS output pins drive the module LEDs through a 7 4LS244 buffer or equivalent. These LEDS pins
continually reflect the value of the FBICSR<LEDS> bits.
5.2.0.4.12. TESTOUT cO>-T•t Output

The TESTOUT pin is the end of the gate-array, I/0-pa~ NAND tree used during functional and parametric
testing of components.

48 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.2.0.4.13.

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5.2.0.4.13. TRISTATEcO>-Tristate All FBIC Pins

When the TRISTATE input pin is asserted, the FBIC tristates all of its output pins.

5.3. FBIC Transactions
This section describes the transactions involving the FBIC on both the CVAX pin-bus and the M-bus.
5.3.1. CV AX Pin-Bus Transactions
5.3.1.1. Read

Figure 5-19 shows the general format of synchronous CVAX pin-bus read transactions. The transaction
shown is a memory-space octaword read. Memory-space longword/quadword/hexword reads, I/0-space
reads, EPR reads, and interrupt acknowledges are of the same form but with the appropriate number of
data-transfer cycles. The CVAX pin-bus slave may stall data transfers in cycle increments by not asserting
CRDY. For an asynchronous CVAX pin-bus, additional dead cycles may occur before and after each longword transfer because of synchronirer delays in the CDS and CRD Y paths.
! P3 ! P4
CDAL

I Pl I P2 I P3 I P4 I Pl I P2 I P3 ! P4 ! Pl ! P2 I P3 I P4 I Pl ! P2 I P3
I

CCSDP

DATA

ADDRESS

STAr:s

DATA

r--·-, PAR11Y

DATA

PARITY

1-\

P4 ; Pl

I P2 I

DATA

PARITY.

r\
I

~
I

CBM

CWR
CAS

I I

\
\

CDS

CR.DY

I
I

I
I
I
I

\
\

I
I

r-:
I

CERR

cccn.
CDMR

CDMG

Figure 5-19:

Read Transaction

5.3.1.2. Wrtt.

Figure S-20 shows the general format of synchronous CVAX pin-bus write transactions. The transaction
shown is a memory-space octaword write. Memory-space longword/quadword/hexword writes, I/0-space
writes. and EPR writes are of the same form but with the appropriate number of data-transfer cycles. The
CV AX pin-bus slave can stall data transfers in cycle increments by not asserting CRDY. For an asynchronous CV AX pin-bus, additional dead cycles can occur before and after each longword transfer because of
synchronizer delays in the CDS and CRDY paths.

5.3. l.2. Fircfoll Bus Interface Chip

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Firefox System Specification 49

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I P3 I P4 I p 1 I P2 I P3 i P4 j Pl I P2 I P3 I P4 I Pl I P2 I P3 I P4 I p 1 I P2 i P3 I P4 I Pl I P2 i
DATA

COAL

DATA

CCSDP

, PARITY,

'PARITY I

DATA

'PARITY I

CBM
CWR

----,

CAS
CDS

CRDY

\
\

I
I

\I
\I

/1
/'

I ,

I :

CERR

cccn..
CDMR
CDMG

Figure 5-20:

Write Transaction

5.3.1.3. External-Cache Miss

Figure 5-21 shows an external-cache read miss transaction and the start of the victim-read and octaword
cache-invalidate transaction from the FBIC. An external-cache write miss t:ramaction has the same fonn.

I P3 I P4 I Pl I P2 I P3 I P4 I Pl
COAL

:-<

: ADDRESS'

~
I

STA.TUS

CCSDP

>-+-< :

D~'TA

: )--+--( : p~
I

I P4 I Pl I P2

(

: ADDRESS:

(

~
I

STA.TUS

CBM
CWR

(':-\

CAS

CDS

CRDY

CERR

\~~/

cccn..

CDMR

CDMG

Figure 5-21 :

External-Cache Read Miss

5.3.1.4. External-Cache Victim-Read Transaction

Figure 5-22 shows an external-cache data-store transaction involving victim read and octaword cache
invalidate. Whenever an external-cache miss occurs, the FBIC issues an external-cache victim-read transaction to remove the victim line from the external-cache data store and the CV AX internal cache.

50 Firefox System Specification

December 30, 1987

Firefox Bus Interface Cb ip 5 .3. 1.4.

DIGITAL EQCIPME.'i"'f CORPORATIO~ - RESTRlCTED DISTRlBCTIO.\"

jP3IP4iPl iP2/P3:P4:Pl !P2iP3:P4!Pl .P21P3JP4!Pl ,P2:P3·P4iPI P2~P3:P4iPl :P2iP3/P4!Pl :P2:P3'P4.Pl P2,
COAL

:-.@DRES5i7--< D~TA f-< DATA r(D~TA f-< DATA ) > - : - - - - - - - - - - 1

TA.ITS

CCSDP

RARITY

ARITY

,~ARITYHARITY)>-+-:~-~..,___ _ _ _ _..,..._.,
,

CBM

I_;_/

>+-<I

*-<;

>+-<:

)>--'- - - - - - - -

CWR

CAS

CDS

CRDY

CERR
CCCTL

CDMR
CDMG

Figure 5-22:

External-Cache Victim-Read Transaction

5.3.1.5. External-Cache Fiii

Figure 5-23 shows a data-store fill transaction in the external cache. The FBIC issues such a transaction to
load an external-cache line that missed.

I P3 I P4 I Pl I P2 I P3 I P4 l Pl I P2 I P3 I P4 I Pl I P2 I P3 I P4 I Pl I P2 I P3 I P4 i Pl
CDAL

CCSDP

P2 I

-< WORE~

STAiTI:S I

CBM
CWR

CAS

\._1__-JI I

CDS

\.__1_ __,/ I

\~~/1

'------'

CRDY

CERR
CCCTL
CDMR
CDMG

Figure 5-23:

External-Cache Fiii Transaction

5.3.1.6. External-Cache Shared-Read

Figure 5-24 shows an FBIC external-cache shared-read transaction that supplies read data to the M-bus.

5.3. l .6. Firefox Bus Interface Chip

December 30, 1987

Firefox System Specification 51

DIGITAL EQVIPME.~'T CORPORATION - RESTRlCTED DISTRIBCTIO~

P3 I P4 I p 1 I P2

P4 ~. Pl

COAL

ADDRESS

DA: A

CCSDP

, STAirus I

PARfrY,

P3 I P4 I Pl

P2 I, P3 I P4 i Pl

DA: A

PARfrY I

PARITY·

P2: P3

P4 ! Pl

DATA

,.....I

PARITY

)-1

r-<

Ti-<:

r-C

CBM

CWR

CAS
CDS

CROY

CERR
CCCTL
CDMR
CDMG

Figure 5-24:

External-Cache Shared-Read

5.3.1. 7. External-Cache Data-Write-Through Update

Figure 5-25 shows a transaction in the external-cache data store involving a write-through update and octaword cache invalidate transaction. Whenever it receives an M-bus write through, the FBIC issues such a
transaction, which updates the external-cache data store and invalidates the CV AX internal cache.

iP3 iP4 jP l IP2jP3jP4Jp11 P2jP3 IP4 jP I IP2 IP3jP4jPl jP2jP3 jP4 IPl IP2IP3 IP4IP l IP21 P3 IP4 !Pl !P21 P3IP4Ip11 P2j
COAL
CCSDP
CBM

CWR
CAS

:;--;-\'
J

CDS

CRDY
CERR
CCCTL
CDMR

/1I

CDMG

Figure 5-25:

External-Cache Write-Through Update Transaction

52 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.3.1.8.

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5.3.1.8. 16-Blt-ROM Read Transaction

Figure 5-26 shows a ROM read for a module with 16-bit ROMs. The FBIC reads the ROM twice. assembles the two words into a longword, and supplies the longword to the CVAX pin-bus master. Tue figure
does not accurately reflect the duration of the ROM read cycle because the ROM will drive data for two
additional CV AX pin-bus cycles for each half of the longword and there is insufficient room on the page to
correct the diagram.
P3P41P li'.P2PlP4P lf>P3P4i> IP3>lP41P IP2P'.3P41> IP'2P3P4P
1P2P3P4P liP'2P3P4Pll>~3P4P 1P2PP4P IP2PF4P IP~
i
•

CDAL

'-<:Af)R)-'.-:--<~:~--L_o_w~-~~'y~:-~-H_1_o_H~-~---'

CCSDP

l~~~:----.-,:--:--1--1-r--1-,·-,..:_,...:__ 1....,.....~1--1

)>--'._ _
, -'----:

1 __

~'--------------------->

__
1 __
, __
• -',..-.------'--'--'

CBM
CWR
I

CAS

I
I

~~----.....·,11111111111

CDS
CRDY

I \1

.L..J

I ,ri
\_J_J I I

II
I

CERR

CCCT1.
CDMR

I
I

CDMG
I

___.._.______.__._..._~--"'--'---_.._.._.__...__.__._...._,1

R0~10E

I
!

ROMWADDR

Figure S.26:

I
I

16-Blt-ROM Read Transaction

5.3.1.9. 32-Blt-ROM Read Transaction

Figure S-27 shows a ROM read for a module with 32-bit ROMs. The FBIC enables the ROM onto CDAL,
latches it, disables the ROM, redrives the data, and asserts CRDY. Because of timing restrictions, the
FBIC must red.rive the data.

5.3.1.9. Firefox. Bus Interface Chip

December 30, 1987

Firefox. System Specification 53

DIGITAL EQCIPME.Vf CORPORATIOI' - RESTRICTED DISTRlBl.,110~

IP3!P4JP lr4J>J!P~ I:n!P~P~ 1~3fP~ lP"~3fP~ 1~3fP4r l~~P41P l~~P4P I!P2!1'31P4tp llP'2lP31P4f l!P2j
COAL

:<:

CCSDP

111

DA:1°1
11

:):

I:'.

:~:

1111111

CBM

CWR
•

;

~\~1--1_._I_._I-l'--l'--'l'--1--'l--'1__.l__.l__t__..1__..__..l__._l_._1_1_._1_._l_l_._l_._l_.._l_.._1_._I_1......,-Jt'--l--'l-l__.l__.l__.1__1__._,1

CAS

'-----''---,I

CDS

CRDY

CDMG

I
l

'-----'~'-~-----, I

ROM OE

ROMWADDR
I

Figura 5-27:

CDMR

\L_UI

CCCTI..

I
I

Irr--!

CERR

I \1

I
I

32-Blt-ROM Raad Transaction

5.3.2. M·bus Transactions

FBIC M-bus transactions conform to the Firefox M-Bus Specification. Please refer to that document for a
detailed description of M-bus transactions.

5.4. FBIC Performance During System Use
The following tables contain examples of FBIC performance for external-cache hits, clean/dirty misses,
write-throughs, shared reads, shared writes; global 1/0 space reads; and M-bus interrupt acknowledges. In
all cases, the M-bus is otherwise idle and M-bus slaves respond in minimal time.
The data is from a DECSIM simulation run on 4 Dec 87 using the FBIC structural model. To guarantee
fixed-length synchronizer delay and to approximately model the expected M-bus/CVAX pin-bus clock
cycle relationship, the simulation was run with an M-bus to CV AX pin-bus clock cycle ratio of 3 to 2. This
implies that a cycle in the M-bus column is 1.5 times longer than a cycle in the CVAX pin-bus column.
Under each transaction analysis, an Mor a Cina column indicates that the cycle is counted in the overall
transaction duration or penalty calculation.
Table 5-18 shows the external-cache hit performance.
Table 5-18:

c
c

c
2

Emmal-Cacha Hit Performance

Cycles
Address
Data

Cycles

Table 5-19 shows the external-cache clean-miss penalty.

54 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.4.

DIGITAL EQCIPME."'\"T CORPORATION - RESTRICTED DISTRIBL"TIO.-...

Table 5-19:

c
c
c

c
c
c
c
c
~

'-'

c
c

External-Cache Clean-Miss Penalty

Cycles
Address
Data
Retry/DMR Asrt
Grant Delay
Grant
Pipe
Victim adr
Victim data 0
Victim data l
Victim data 2
Victim data 3
Inval Delay
Inval Delay
Inval Delay
Tag Write
Sync
Pipe
Fill data 0
Fill data 1
Fill data 2
Fill data 3/D :MR DeAsrt
Ungrant Delay
Ungrant

Cycles

M
M
M
M
M
M
M
M
M
M
M
M
Done

Sync
Request
Pl Arb
P2 Miss adr
P3 Wait 0
P4 Wait 1
P5 Wait 2
P6 Wait 3
P7 Data 0
P8 Data 1
P9 Data 2
PIO Data 3

·'

5.4. Firefox. Bus Interface Otip

December 30, 1987

Firdox System Specification 55

DIGITAL EQCIP~E."'<'T CORPORATION - RESTRICTED DISTRIBL'TION

Table 5-20 shows the external-cache dirty-miss penalty.
Table S-20:

c
c
c
c
c
c
c
c
c

c
c
c

c
c
c
c
c
c
c
c

Extemal-Cache Dirty-Miss Penalty

Cycles
Address
Data
Retry/DMR Asrt
Grant Delay
Grant
Pipe
Victim adr
Victim data 0
Victim data 1
Victim data 2
Victim data 3
Inval Delay
Inval Delay
lnval Delay
Wait
Wait
Sync
Pipe
Pipe(fag write
Wait

Sync
Tag Write
Wait
Wait
Sync
Pipe
Fill data 0
Fill data 1

Cycles

M
M
M
M
M
M
M
M

Sync
Request
Pl Arb
P2 Victim adr
P3 Data 0
P5 Data 1
P6 Data 2
P7 Data 3
Done

M
M
M
M
M
M
M
M
M
M
M
M

Sync
Request
Pl Arl>
P2 Miss adr
P3 WaitO
P4Wait1
PS Wait 2
P6Wait3
P7 DataO
P8Data1
P9Data2
PlO Data 3
Done

Fill~2

Fill data 3/DMR DeAsrt
Ungrant Delay
Ungrant

56 Firefox System Specification

December 30, 1987

Firefox Bu.s Interface Chip 5.4.

DIGITAL EQCIPME..'-.! CORPORATIO!'i -RESTRlCTED DISTRIBL!IO~

Table 5-21 shows the external-cache write-through penalty.
Table 5-21:

c
c

c
c
c
c
c
c

External-Cache Write-Through Penalty

Cycles
Address
Data
Drvffi. Asrt
Rdy/Grant Delay
Grant
Wait

Wait
Sync
Pipe
Tag Write
DMRDeAsrt
Ungrant Delay
Cngrant

Cycles

M
M
M
M
M
M
M
M

Sync
Request
Pl Arb
P2 Write adr
P3 Data 0
P4 Data 1
P5 Data 2
P6 Data 3
Done

Table 5-22 below shows the cache shared read penalty. The M-bus penalty for read from cache versus
read from memory is as follows:

17 C-cycles (Sync to Data 3 - request =>data ready)
2 M-cycles (Sync to Done - synch done=> fifo pipeline started)
4 M-cycles (Required 4 M-bus waits for probe)
17 C-2M

The CVAX pin-bus penalty for shared read from its cache during CVAX pin-bus read hit is as follows:

+
+

2 C-cycles (Tag Probe to Tag Write)
12 C-cycles (Sync to Data 2 - request=> data ready)
6 M-cycles (Sync to Data 3 - synch done => empty fifo)
4 C-cycles (Sync to Ungrant - synch fifo emptied=> bus idle)
18C+6M

The CVAX pin-bus penalty for shared read from its cache during CVAX pin-bus write hit is as follows:

+
+

6 C-cycles (Tag Probe to Tag Write, wait to do write thru)
12 C-cycles (Sync to Data 2 - request=> data ready)
6 M-cycles (Sync to Data 3 - synch done==> empty fifo)
4 C-cycles (Sync to Ungrant - synch tifo emptied==> bus idle)
22 C + 6 M

5.4. Firefox Bus Interface Chip

December 30, 1987

Firefox System Specification 57

DIGITAL EQUIPME~ CORPORATION -RESTRlCTED DISTR1BL1ION

Table 5-22:

External-Cache Shared-Read Penalty

Cycles

c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c

Sync
Tag Probe
Tag Write
Wait
Wait
Wait
Pipe/Sync
Pipe
DrvIR Asrt
Grant Delay
Grant
Pipe
Pipe
Pipe
Adr
Data 0
Data l
Data 2
Data 3
Wait

c
c
c
c

Wait
Sync
DMR DeAsrt
U ngrant Delay
Ungrant

Cycles
Pl Arb
P2Adr
P3 Wait 0
P4 Wait 1

M
M
M
M
M

PS Wait 2
P6 Wait 3/Shared
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
'P7 Data Wait
M
'P7 Data Wait/Done
'P7 Data 0
PS Data 1
P9 Data 2
PIO Data 3

Table 5-23 shows the external-cache shared-write penalty.
The M-bus penalty for write-through to cache is as follows:

+
+

15 C-cycles (Pipe/Sync to Inval Delay 3 - synch request==> inval done)
2 M.:.cycles (Sync to Done - synch done => delay pipeline started)
8 M-cycles (Required 8 Delay cycles to guarantee fair arl>itration)
4 M-cycles (Required 4 data transfer cycles)
15 C + 6 M

The CV AX pin-bus penalty for shared write to its cache during CVAX pin-bus read bit is as follows:
2 C-cycles (Tag Probe and Tag Write)
18 C-cycles (Data Invalidate cycle)
20 C-cycles

58 Firefox System Specification

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Firefox Bus Interface Chip 5.4.

DIGITAL EQCIP.\18'i! CORPORATION -RESTRICTED DISTRIBL!ION

The CV AX pin-bus penalty for shared write to its cache during CVAX pin-bus write hit is as follows:
6 C-cycles (Tag Probe, Tag Write, wait to do write thru)
18 C-cycles (Data Invalidate cycle)
24 C-cycles
Table 5-23:

External-Cache Shared-Write Penalty

Cycles

c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c

Sync
Tag Probe
Tag Write
Wait
Wait
Wait
Pipe/Sync
Pipe
DMR Asrt
Grant Delay
Grant
Pipe
Pipe
Pipe
Ad.r
DataO
Data 1
Data2
Data 3
Inval Delay
Inval Delay
Inval Delay
DMR DeAsrt
U ngrant Delay
Ungrant
Idle
Idle
Idle
Idle
Idle:
Idle
Idle
Idle

c
c
c
c
c
c

Cycles
Pl Arb
P2Adr
P3 Data 0
P4 Data 1

M
M
M
M
M
M
M
M
M
M
M

P5 Data2
P6 Data 3/Shared
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy/Sync
Busy/Done
Busy/Delay
Busy/Delay
Busy/Delay
Busy/Delay
Busy/Delay
Busy/Delay
Busy/Delay
Busy/Delay
Busy/Delay

Table 5-24 shows the global I/0 space performance.

5.4. Firefox. Bus Interface Chip

December 30, 1987

Firefox. System Specification 59

DIGITAL EQulPME."1 CORPORATION - RESTRICTED DISTRlBCTIO~

Table 5-24:

c
c
c

1/0 Transaction

Cycles

Address
Decode
Wait

Wait

c
c

Cycles

M
M
M
M
M
M
Sync
Pipe
RDY

Sync
Request
Pl Arb
P2 Address
P3 Mask
P4 Status

Table 5-25 shows the M-bus interrupt-acknowledge performance.
Table 5-25:

c
c
c

c
c
c
5

Interrupt-Acknowledge Transaction

Cycles
Address
Decode
Wait

Wait
Sync
Pipe
ROY

Cycles

M
M
M
M
M
M
M

Sync
Request
Pl Arb
P2 Address
P3 Decode
P4 Slave arb
PS Vector
Done

60 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.5.

DIGITAL EQUIPMS'ff CORPORATIO~ - RESTRICTED DISTRlBCTIOl'i

5.5. Testability and System Diagnostic Support
The FBIC provides a variety of diagnostic functions for both chip-level testability and system self-test
diagnostics. including the following:
•

M-bus error detection and error logging

•

M-bus module-type identification

•

General-purpose scratch register support

•

'Thirteen programmable diagnostic functions

•

Access to external and internal tags in I/0 space

•

External- and internal-cache miss detection

•

M-bus and CV AX pin-bus timeout detection

•

6-bit status-indicator output

•

16/32-bit ROM control

•

2-bit manufacturing-mode input
TBD.

5.6. DC Characteristics
The following section lists the FBIC steady-state DC characteristics as published by LSI Logic for the
L2000 ceramic chip package.
5.6.1. Absolute Maximum Ratings

Table 5-26 shows the absolute maximum ratings.
Table 5-26:

Absolute Maximum Ratings

Parameter
Storage temperature range
Active temperature range
Supply voltage range
Input or output voltage applied

5.6.2. Firefox Bus Interface Chip

Range

-40 to +125 C
0 to +70 C

-0.3 to +7 V
-0.1 to +7.3 V

December 30, 1987

Firefox System Specification 61

DIGITAL EQt:IPME.'41 CORPORATIO~ - RESTRlCTED DISTRIBlmO~

5.6.2. Electrical Characteristics

The DC characteristics of the FBIC appear in Table 5-27.
Table 5-27:

DC Characteristics

Minimum
2.0

Symbol
Vih

Parameter
High-level input
voltage (TI"L)

Vih

High-level input
voltage (CMOS)

Vil

Low-level input
voltage (TI"L)

0.8

Vil

Low-level input
voltage (CMOS)

1.5

Yoh

High-level output
voltage

Bl: Ioh=-lmA
B2: Ioh = -2mA
B4: lob = -4mA
BS: lob = -8mA
B 12: lob = -12mA

Low-level output
voltage

Bl: Iol = lmA

Vol

Condition

Maximum

v
v

3.5

2.4

v
v
v
v

2.4
2.4
2.4
2.4
0.4

B4: Iol =4mA
B8: Iol = 8mA
Bl2: Iol = 12mA
-10

v
0.4
0.4
0.4
0.4

B2: Iol = 2mA

Ioz

Three-state output
leakage current

Yoh= Vss orVdd

Cin

Input capacitance

Any input

Cout

Output capacitance

Any output

Specified temperature range
Specified supply voltage range

Units

0 to +70

+4.75 to +5.25

5.7. AC Characteristics
5. 7.1. M·bus AC Characteristic•

TBD.
5.7.2. CVAX pin-bus AC Characteristics

Table 5-28 outlines the FBIC CV AX pin-bus AC specification. This specification is subject to change
upon characterization of the actual device; moreover, the parameters appearing therein are biased to be
conservative estimates of the actual parameters.

62 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.7.2.

DIGITAL EQCIPME~'T CORPORATIO~ -RESTRJCTED DISTRJBL"TIO~

Table 5-28:

CV AX Pin-Bus AC Specification

Symbol
TDALD

Parameter
P3 rising to valid CDAL<3 l :00> (addr)

Minimum

Maximum

Load (pF)

100

TDALD

P3 rising to valid CDAL<3 l :00> (data)

100

TDALH

P2 rising to invalid CDAL<3 l :00>
(address/data hold time)

100

TDALHLZ

P2 rising to CDAL<3 l :00> tristate

100

TDS

Setup of CDAL<3 l :00> to Pl rising

TDH

Hold of CDAL<31:00> after Pl risen

TOPS

Setup of CCSDP<3 :0> to Pl rising
(data parity)

TDPH

Hold of CCSDP<3:0> (data parity)
after P 1 risen

TADDS

Setup of CDAL<3 l :00> (address) to
CAS_L assertion

TADDH

Hold of CDAL<31:00> (address) after
CAS_L assertion

TSD

P3 rising to valid CCSDP<3:0> (CS)

100

TASD

Pl rising to CAS_L assertion

100

TASID

P2 rising to CAS_L deassertion

100

TADRH

Hold of CDAL<31:00> (adr) after CAS_L
assertion (provided by FBIC)

+ (Pl-P2)

100

-TASD(max)
TADRS

Setup of CDAL<31:00> (adr) to CAS_L
assertion (provided by FBIC)

100

+ (P3-Pl)
- TDALD(max)

TDSD

P3 rising to CDS_L assertion

100

TD SID

Pl rising to CDS_L deasserion

100

TDATH

Hold of CDAL<31:00> (data) after CDS_L
deassertion (provided by FBIC)

+ (Pl-P2)

100

15
- TDSID(max)

TDATS

Set-up of CDAL<3 l :00> (data) to
CDS_L deassertion (provided by FBIC)

+ (P3-Pl)
- TDALD(max)
(continued)

5.7 .2. Firefox Bus Interface Chip

December 30, 1987

Firefox System Specification 63

DIGITAL EQlJIP~E.'\"f CORPORATION - RESTRICTED DISTRIBL!IO~

Symbol

Parameter

Minimum

Maximum

Load (pF)

TBWI

P3 rising to valid CBM<3:0>

100

TSD

P3 rising to CWR_L assertion

100

TSID

P2 rising to CWR_L deassertion

100

TSWS

Setup of CRDY_L or CERR_L asserted
to Pl rising

TSWH

Hold of CRD Y_L or CERR_L asserted
after P 1 risen

TDPD

P3 rising to valid CCSDP<3 :0> (DP)

100

TDPEDF

CClockC falling to CDPE_L assertion
(fast)

100

TDPEDS

P3 rising to CDPE_L assertion
(Slow; CClockC input pin tied to VDD)

100

TRMOED

P3 rising to ROMOE_L assertion or
de assertion

100

TRMWAD

P3 rising to ROMWADDR assertion or
de assertion

100

TD~

P2 rising to CD:MR_L assertion or
de assertion

100

TDMGS

Setup of CDMG_L asserted to P3 rising

TDMGH

Hold of CDMG_L asserted to P3 risen

TTWEDO

P3 rising to T AGWE_L assertion

TTWEDl

P 1 rising to T AGWE_L deassertion

TTCEDO

P3 rising to TAGCE_L assertion

TTCED_l ·:

Pl rising to TAGCE_L deassertion

TTAGD

P4 rising to valid TCACHE<l5 :0>

TTAGID...Z

P2 rising to TCACHE<15:0> tristate

TTAGS

Setup ofTCACHE<15:0> to TAGCE_L
deassertion (provided by FBIC)

TTAGH

Hold ofTCACHE<15:0> afterTAGCE_L
deassertion (provided by FBIC)

(continued)

64 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.7.2.

DIGITAL EQCIPME.Vf CORPORATION - RESTRICTED DISTRlBLTION

Symbol

Parameter

Minimum

Maximum

Load (pF)

TD WEDO

CAS_L assertion to DATWE_L assertion

TDWEDl

CAS_L deassertion to DATWE_L
de assertion

TD CE DO

CWR_L deassertion. or CWR_L asserted
and P3 rising to DA TCE_L assertion

TDCEDl

Pl rising, or CWR_L assertion to
DATCE_L deassertion

TXOEDO

CAS_L asserted and P2 rising to
XOE_L assertion

TXOEDl

P2 rising to XOE_L deassertion

TCTLDFO

CCiock falling to CDPE_L assertion
(fast)

TCTLDSO

P3 rising to CDPE_L assertion
(Slow; CClockC input pin tied to VDD)

.:t

~.i.

TRESETS

Setup of CRESET_L deasserted to
CCL.KA rising

TRESETH

Hold of CRESET_L asserted to-CCLKA
rising

TCNDXDO

P3 rising to Cl1NDXOE_L asserted

Tiv!NDXDO

P3 rising to MTINDXOE_L asserted

TCNDXDl

P3 rising to Cl1NDXOE_L deasserted

DtfNDXDl

P3 rising to MTINDXOE_L deasserted

5.8. Package Diagram and Pin Assignment
The FBIC package pinout is pictured in Figure 5-28.

5.8. Firefox. Bus Interface Chip

December 30, 198 7

Firefox. System Specification 65

DIGITAL EQt.;IP~E.~1 CORPORATIO~ - RESTRlCTED DISTRlBL'TIO~

View from Top
A

x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

c
D
E
F

G
H

J
K

L
M

N
p
R

u
v

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
DC7093
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8

View from Pin Side

v
u
T
R
p
N

0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0

0 0 0 0

K
J

0 0 0 0
0 0 0 0

0 0 0 0

G
F
E
D

0 0
0 0
0 0
0 0
0 0
0 0
X 0

B
A

0
0
0
0

0 0 0 0

0
0
0
0

0
0
0
0
0
0
0

0 0 0 0

DC7093

0
0
0
0

0
0
0
0
0
0
0
0
0
0

0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
Note: X is an index mark; there is no pin at this location.
Figure 5-28:

Package Plnout

66 Firefox System Specification

December 30, 1987

Firefox Bus Interface Chip 5.8.

DIGITAL EQlJIPM:E!.~T CORPORATION - RESTRICTED DISTRIBL"TIO~

Table 5-29 shows the FBIC signal, power, and ground pin assignments.
Table 5-29:

FBIC Signal, Power, and Ground Pin Assignments

CV AX Pin-Bus
B 11 - CCSDP<O>
ClO - CCSDP<l>
Al 1 - CCSDP<2>
BIO - CCSDP<3>
Gl7 - COPE
004- CAS
003 - CDS
Dll - CBM<O>
Cl 1 - CBM<l>
Al2 - CBM<2>
010- CBM<3>
COl - C\VR
002 - CROY
E04-CERR
FIS - cccn..
Jl6- CDMR
G18 - CD\1G

E02 - CRESET
F03 - S YSRESET
l'04- CHALT
V16 - CIRQ<O>
Ul5 - CIRQ<l>
T13 - CIRQ<2>
U14 - CIRQ<3>
TOI - CRD
P04-MEMERR
E03 - CCLKA
F04-CCLKB
Jl5 - CCLKC
B09 - CDAL<O>
C09- CDAL<l>
B08 - CDAL<2>
009- CDAL<3>
A07 - CDAL<4>
C08 - CDAL<5>
B07 - CDAL<6>

oos- ~AL<7>
A06 - CDAL<8>
B06 - CDAL<9>
007 - CDAL<l O>
A05 - CDAL<ll>
C06 - CDAL<12>
805 - CDAL<l3>
006 - CDAL<14>
COS - CDAL<15>
A04- CDAL<l6>
B04 - CDAL<l 7>
DOI - CDAL<18>
EOl - CDAL<l9>
G04 - COAL<20>

M-Bus
Pl5 - MBRM<O>
R16 - MBRM<l>
Tl8 - MBRM<2>
Tl7 - MBRM<3>
R15 - l'vIBRJ.\1<4>
Tl6- MBRM<5>
U16 - MBRM<6>
R17- MBRP
R 18 - MThffiRQ
N18 - MBUSYI
Ml5- MBUSYO
T 10 - MC1"1Ik0>
Vl2 - MC:MD<l>
Vl 1 - MCMD<2>
T09 - MCMD<3>
V13 - MSTATUS<O>
R ! 0 · \'fSTATl'S<i >
Ul2 -MCPAR
Tll -MSPAR
UIO-MDPAR
Ull - MCDRV
Rll - MSDRV
R03-MDDRV
N17 - MSHAREDI
N 16 - MSHAREDO
Ml6 - MDATINVI
Ml 8 - MDATINVO
Al5 - MID<O>
B 15 - :MID<l>
D 14 - 1vfiD<2>
T03 -MRESET
Pl8 - MABORTI
Nl5 - MABORTO
R14- 'MIRQl<O>
V15 - :MIRQl<l>
Tl4- MIRQ1<2>
T12 - MIRQ1<3>
Tl5 - MIRQO<O>
R13 - 'MIRQO<l>
R12 - 'MIRQ0<2>
V14 -1vfiRQ0<3>
T04-MHALT
P17 - MCLKA
P16- MCLKB
R09 - MDAL<O>
U09 - MDAL<l>
T08 - MD AL<2>
U08 - MDAL<3>
R08 - MDAL<4>
V07 - MDAL<5>

5.8. Fircfollt Bus Interface Chip

Cache Control
El7 -TCACHE<O>
G15 -TCACHE<l>
El6-TCACHE<2>
Fl6 - TCACHE<3>
Fl5 -TCACHE<4>
018 -TCACHE<5>
D 17 - TCACHE<6>
Dl6-TCACHE<7>
El5 -TCACHE<8>
Cl8 - TCACHE<9>
Cl7 - TCACHE<lO>
C16- TCACHE<ll>
015 -TCACHE<l2>
Bl6-TAGSH
A16-TAGDR
Cl5 -TAGPAR
Fl7 -TAG\VE
H16-TAGCE
C04 - DATCE<O>
D05 - DATCE<l>
A03 -DATCE<2>
B03 - DATCE<3>
C03-DATWE
C02-XOE
H17 -ECL
G16- CTINDX_OE
R02 - MTINDX_LE
H15 - MTINDX_OE

December 30, 1987

Miscellaneous
D 13 - MODCL<O>
C14 - MODCL<l>
B 14 - TYPDUAL
Cl3 - TYPAGNTE
A14-TYPRET
012 - TYPSYNC
R05 - DEVIRQ<O>
V03 - DEVIRQ<l>
U03 - DEVIRQ<2>
R04 - DEVIRQ<3>
H18-ROMOE
B 13 - ROMWID32
Kl6 - ROMWADDR
Cl2 - MNFMOD<O>
A13 - :MNFMOD<l>
L15 - LEDS<O>
Ll 7 - LEDS<l>
L 16 - LEDS<2>
Kl 7 - LEDS<3>
K15 - LEDS<4>
117 - LEDS<.5>
T02 - TESTOUT
ROI -TRISTATE

Power/Ground
V02 - VDD
V09- VDD
Vl8 - VDD
UOl - VDD
Ul7 - VDD
L18 - VDD
JOI - VDD
Jl8 - VDO
BOl - VDO
Bl8 - VDO
A02- VDD
A09- VDD
A17 - VDD
VOl - VSS
V08 - VSS
VlO - VSS
V17 - VSS

U02 - VSS
UI8 - VSS
KOl - VSS
Kl8 - VSS
HOl - VSS
B02- VSS
B17 - VSS
A08 - VSS
AlO - VSS
Al8 - VSS
El8 - VSS
Bl2 - VSS (Unused)
C07 - VSS (Unused)
Ml7 - VSS (Unused)
Ul3 - VSS (Unused)
T07 - VSS (Unused)
NOl - VSS (Unused)
H04 - VSS (Unused)

Firefox System Specification 67

DIGITAL EQliIPMENT CORPORATION - RESTRlCTED DISTRlBCTION

CV AX Pin-Bus
F02 - CDAL<21>
G03 - CDAL<22>
FOl - CDAL<23>
G02 - CDAL<24>
H03 - CDAL<25>
GO 1 - CDAL<26>
104 - CDAL<27>
H02 - CDAL<28>
J03 - CDAL<29>
102 - CDAL<30>
K02 - CDAL<31>

M-Bus

Cache Control

Miscellaneous

Power/Ground

U07 - MDAL<6>
R07 - MDAL<7>
V06 - MDAL<8>
T06 - MDAL<9>
U06 - MDAL<IO>
R06 - MDAL<ll>
V05 - MDAL<12>
U05 - MDAL<l3>
T05 - MDAL<14>
Y04 - MDAL<l5>
P03 - MDAL<l6>
N04 - MDAL<l7>
P02 - MDAL<l8>
N03 - MDAL<19>
POl - MDAL<20>
M04- MDAL<21>
N02 - MDAL<22>
M03 - MDAL<23>
L04 - MDAL<24>
M02 - MDAL<25>
L03 - MDAL<26>
MOl - MDAL<27>
K04 - MDAL<28>
L02 - MDAL<29>
K03 - MDAL<30>
LOl - MDAL<31>

68 Firefoll System Specification

December 30, 1987

Firefoll Bus Interface Chip 5.8.