Firefox Bus Interface Chip Specification

This document specifies the functionality of the Firefox Bus Interface Chip (FBIC), a 1.5-micron gate array developed by Digital Equipment Corporation in 1987. The FBIC serves as a triple-ported, multipurpose bus-interface and cache controller, primarily interfacing the CVAX pin-bus (processor bus), the M-bus (system bus), and a level-2 cache within the Firefox Workstation environment.

Key functionalities include:

• Bus Interfacing: Operates as both a master and a slave on the CVAX pin-bus and supports the M-bus write-back cache protocol.
• Cache Management: Provides cache control for external 64KB snoopy caches used by CVAX processors, and includes an on-chip single-entry snoopy cache for I/O modules. It enforces cache consistency across the system (write-back for unshared, write-through for shared data).
• Transaction Handling: Manages interlocked transactions across M-bus memory and I/O spaces.
• Interrupts: Supports I/O-interrupt masking and implements a vectored interrupt unit for interprocessor/device interrupts.
• Address Mapping: Features an M-bus I/O-space range decoder for flexible access to module resources.
• Diagnostics & Error Handling: Includes SMP processor registers (CPUID, WHAMI), status-indicator outputs, manufacturing mode inputs, support for diagnostic/self-test ROM, CVAX pin-bus timeout detection, M-bus module-type identification, and extensive error detection and logging for M-bus, CVAX pin-bus, and external-cache errors.

Architecturally, the FBIC contains two separately clocked, synchronous state machines (for CVAX and M-bus) that communicate to ensure system-wide data consistency. The specification details the chip's external behavior, interface, pinout, and electrical characteristics for designers and system programmers.