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Document:	CIBCA User Guide
Order Number:	EK-CIBCA-UG
Revision:	001
Pages:	86
Original Filename:

OCR Text

EK-CIBCA-UG-001

CIBCA

User Guide.

- D‘i.gfit;_a”-l: 'Eq;uii'pm'emf jC.‘c_‘_)*rpo'ration_ e

EK-CIBCAUG-00

CIBCA

Cl BUS

PORT

STAR -

COUPLER

ADAPTER

MKV87-1038

| Figure 1-1 Simplified]CIBCA Pdrt ,*A'dapter_Connectien"
1. 2 2

Features

_;-VAX Backplane Interconnect demgn

_ Dtagnosttc data loopback (1nternal/external) capablhty

'Data 1ntegnty via cychc redundancy checkmg -

'Round-robtn arbltratlon at heavy loadmg B » -Contentlon arbltratton at hght loadmg
data transmtssmn
o T‘Packet-ortented

Immedtate acknowledgment of packet receptton

| Operatlonal modes |

- Disabled
|

Enabled

- | Ummttahzed
Dual 51gna1 paths

1.3 SPECIFICATIONS
CI GENERAL SPECIFICATIONS
Priority arbitration

Light loading

Contention

Heavy 'loading

) ?Round-robm

Parity

| Cychc redundancy check

Manchester-encoded senal packet L |

Data format

'ENVIRONMENTAL SPECIFICATIONS
. .Temperature

Operating

10°C to 40°C (50°F to 104°F) amblent temperature w1th .|

a gradient of 10°C (18°F)/hr

Storage /shipping

| —40°C to 70°C (—40°F to 158°F) amblent temperature
~with a gradient of 2°C (36°F)/hr |
I

“Relative Humidity

* Operating

,10% to 90% w1th a maximum wet bulb temperature of .
28°C (82°F) and a minimum dew pomt of 2°C (36°F) |

with no condensatlon

- 5%-to'95% with no COndensation ) ‘

Storage/shipping
Altitude

Sea level to 2.4 km (8,000 ft)

Operating

Maxxmum operatmg temperatures decrease by a factor of B
1.8°C/ 1000 (1°F/ 1000 ft) for operatton above sea level |

Storage/shippiu_g

Up to 9.1 km (30,000 ft) above sea level (actual or effec-~ L
tive by means of cabin pressur1zat10n)

~ Shock
-

'ELECTRICAL SPECIFICATIONS
Power consumption

45.0 Vat8 A nominal
—5.2 V at 2 A nominal
—2.0 V at 1 A nominal

5 Gs peak at 7 to 13 ms )duratloni-n three axes | mutually e
perpendicular (maximum

-VAXBI BUS SPECIFICATIONS |

Bus Characterlstlcs |
Type f;

‘Synchronous

. Width

32 data'“bits

‘ Cycletime |
Pnonty arbitration

Paity

Distributed embedded |
Odd

N Data tranSfers o

Block mode (masked)

Longword
~ Quadword
Oeta-word

o 'Tran‘srhissi‘on Characteristics
-

Bandwidth

AMaster port

Slave port B

11.4 Mbytes/S

| »‘133Mbytes/s :

Length (maxxmum)

15m(5ft)

Bus loadmg (maxlmum)

16 logical nodes

* CI BUS SPECIFICATIONS )
Bus Characteristics -

| | Serlal
,Extemal lehgth'(ma’iimum)

| 45 m (147 64 ft) radxus from star coupler

| Datatransfer rate . r

B "417‘0 MbltS/S (maxxrnum)

Bus loadmg (max1mum)

16 logical nedes

: Cable type (BNCIA-XX)

Double shielded eoaxial

;- Cable 1mpedance

50 ohms

1.4 PHYSICAL HARDWARE DESCRIPT ION
|
Refer to Table 1-1 and Flgure 1-2 for an overview of the hardware components of the CIBCA._,

Table 1-1

Hardware COmponents ef the ’CIBCAJAdapter

‘Part Number

T1015

Port controller‘ module

T1025

Link/ packet buff.er | rnodule |

17-01504-01

2.0 inch cable (1 each)
0.7 inch .cable (1 each)

17-01473-01

e
|
Internal CI bulkhead cable assembly
-

12-27249-01

Dummy connector (Receive) "

12-27249-02

Dummy eennector (Transmit)

17-01504-02

12-22246-01

VAXBI

Component Type

. Transition connector assembly (2 each)

PORT

CONTROLLER

T1015
—

CILP

LINK/PACKET
| > TX PATH A

BUFFER

' 11025
3

~—

RX PATH A

~ TXPATHB
< RXPATHB

‘Figure 12

Simplified CIBCA Block Diagram

CIBCA HARDWARE

modules. The T—series modules are housed in
- Refer to Figure 1-3. The CIBCA consists of two T-series type
. These modules are used to interface the host
_two adjacent slots within an H9400-A VAXBI card.cage
system’s VAXBI bus to the CI bus.

~ PORT
~ CONTROLLER
T1015

INTERMODULE CABLES

LINK/PACKET
BUFFER

T1025

DUMM
UMMY Y

CONNECTORS
s

ClI INTERNAL
BULKH
BULKHEAD

CABLE ASSEMBLY

- 17-01473-01
|

12-27249-02

o®

12-272489-01

- 17-01504-01

TRANSITION CONNECTOR

~ ASSEMBLY -

12-22246-01
MKV87-1040

Figure 1-3 Hardware Components of the CIBCA

- The Port Controller Module

The port controller module, part number T1015, contains the VAXBI protocol the VAXBI control logxc

'mrcroprocessor and control store.

The Lmk/Packet Buffer Module

The link/packet buffer module, part number T1025 contains the CI bus protocol logrc and CI packet

~ buffer memory.

CIBCA Cables

The two CIBCA cables are used to electrrcally interconnect the T1015 and T1025 modules. Each cable

consists of two 30-pin female connectors and an interconnecting ribbon cable arrangedin a ground-signal- ground-fashion. The cables are mated to cable connectors located on the VAXBI card cage corresponding
- to Zone C of the modules. The short cable completes the innermost electrical connection whlle the longer
cable completes the outermost electrical connection betweenthe two modules.
|

The CI Bulkhead Connector Panel

‘The CIBCAis connected internally from the VAXBI backplane to the CI bulkhead connector panel via
two pairs of coaxial cables. The CI bulkhead connector panel provides the electrical isolation for the
system by creating an EMI/RFI shield without compromising signal integrity. The panelis mountedin the
cable connector openings located on the rear inside I/O panels of the cabinet. Two pairs of double-shielded
coaxial cables connect the CI paths of the node from the CI bulkhead connector panel to thestar coupler.
One cable of each pair is for transmlttmg data, the other for rece1v1ng data

1.5 REFERENCE DOCUMENTS

Title

»CI.BCA‘ Mal'nténance Print Set

' CIBCA Hardware Technical Description

| SC00'8'Star Coupler User's Guide

o | ‘ |
|

’

- EK-SC008 UG

AN
e

| Northboro MA 01532- 2597

Attn: Pnntmg and Clrculatron Servrces (NRO3 /W3)

Digital Equipment Corporation

Peripherals and Supplies Group
- Cotton Road
Nashua, NH 03063-1260 |

1-7

‘MP-01836-O'1
| EK-CIBCA TD

Digital Equipment Corporatlon
10 Forbes Road

Customers'may order hardware documents from:

|
| )

Order Processrng Section

| Document Number

| DIGITALper‘sonnel ,may order hardware documents from:

21 INTRODUCTION

CHAPTER 2

SITE PREPARATION
AND INSTALLATION

This chapter contams mformatlon on 51te preparatlon and mstallatlon mcludmg

Operating Envrronment - Venfymg that the CIBCA optlon meets all of the mmlmum physmal envuon—.
mental, and groundmg specrficauons

System Conf‘guratrons Configurmg the CIBCA optlonto various VAX systems w1th a VAXBI 1nstalled
Unpacking 'and I-nventory - Unpackm-g and v,erlfymg that the shipmentis complete and undamaged.

Installation and Coufiguratlon - Ihstallmg the modules intermodule cables,‘ and' internal CI bulkhead |
cable assembly; and configurmg the node address of the CIBCA adapter optlon and other jumper
selectable parameters

2. 2 OPERATING ENVIRONMENT
2.2.1 Physncal Elements
|
|
The CIBCA optron requlres two adJacent VAXBI slots

| There must be two available S. 1 cm X 10 2 cm (2in x 4 in) or one 10 2cm X 10.2 cm (4in X 4 in) I/O
connector panel opemng(s)in the cabinet for the CI bulkhead cable connector panel

yal'\\\

2.2.2
-

System Envnronment and Groundmg Elements

Consult the appllcable system mstallatron manual for mformatron regardmg system environment and
grounding requirements.

2.3 'SYSTEM,CONFIGURATIONS‘ ‘

Refer
to Figures 2-1, 2-2, and 2-3.

NOTE
)
Ensure that the CIBCA hardware and microcode
revision level is consistent with the revision level of

the cluster and vice versa. Consult the VAXcluster
System Revision Document for more information.

CIBCA

BULKHEAD

cABLES

//cctcuuuw"

| 5N

ér”

‘

/’“
QJ

Figure 2-1

CIBCA Adapter - VAX 8200/8300

2-2

MKV87-1041

VAX 8500

i oliltal
AIR

MOVER

POWER REGULATORS

BACKPLANE

INTERCONNECT

~ MEMORY

“CPU_

50 HZ

o
|

TRANSFORMER | |

SPC
SYSTEM

POWER

~ONTROLLER

MKV87-1042

‘Figure 2-2

CIBCA Adapter - VAX 8500

“MODULAR POWER SUPPLIES(MPS)

)

EXPANDER |

(H9652)

(OPTIONAL)

BLOWER ASSEMBLY

~
- BOX

(OPTIONAL

CPU CABINET (H9650) ~

(H9652)

FRONT END CABINET

EXPANSION CABINET EXPANSION CABINET

~ (H9652)

S >

EXPANDER BOX|| EXPANDER BOX
-

-2

HEEAHEREIE
-'

» S’é’:(ANDER
50 HZ

TRANSFORMER
(OPTIONAL)
AC INPUT
_

BOX | | EXPANDER BOX
' EXPANDER

B
]

NBOX
"MKV87-1043

2-4

" 2.4 UNPACKING
AND INVENTORY

| The customer 1s responsible for the actual movement of the equipment to the installation srte
For all VAXBI systems ensure that all equrpment for the CIBCA optron is moved to the desrgnated
installation site.
-

Verifying Shipment Inventory

PROCEDURE
1.

Inventory all equlpment agamst the shrppmg hst accompanymg the equipment.

2. | Notify the customer of any opened cartons or boxes and document this fact on the mstallatlon
report.

Notify the Field Service unit manager of any missing or incorrect items.

4. 'Reouestthatthe customer c0ntactthe shipping carrier to l'ocate'anymissing-items
5.

Request that the Field Service umt manager check ‘with the Digital Equlpment Corporation -

Traffic and Shipping Department if the shipping carner does not have the mrssmg items.

| 6 - Check all boxes for externa,l«damage v(dents, holes, or crushed corners)t

T Notify the customer of all damage an‘d list alldamage on the installation report.
| Unpacking the Shipping‘ Boxes
PROCEDURE

‘

-1~. | Locate and open the box marked “OPEN ME FIRST” It contains the shrppmg/accessory hst
2.

Open all remammg boxes and mventoryr the contents against the shlppmg/accessory list.

3.
4.

I-nspect the .equipment ‘for' damage. Report any damage and note it on the instailation report.
~

If damage is extensrve notify Digital Equipment Corporation for 1nstructions on how to
proceed

2.5 CIBCA INSTALLATION AND CONFIGURATION |

25.1 T1015 and T1025 Module Installation
CAUTION
Use an antistatic wrist ground strap (VelostatTM Klt
P/N 29-11762-00) while working on a VAXBI system with its covers removed or when handling any
VAXBI module. Do not remove any module from ltS
| antlstatlc packagmg until you are ready to install it.

Before 1nstallat10n of the CIBCA, perform the followmg steps.
For CIBCA add-ons, the CIBCA.BIN mlcrocode must be resident on the system console boot
device. Before shutting the system down, copy CIBCA BIN from the appropriate media (sup-

plied with the CIBCA) to the console boot device. Contents of the supplled media are hsted
|

below -

VAX CIBCA MICROCODE UPDATE FLOPPY

‘This floppy contains the latest version of the mlcrocode file, CIBCA BIN. It has the EEPROM
Programmmg and Update utility (EVGDA) whichis used to update the CIBCA EEPROM.

This floppyis also used to place and/or update the CIBCA microcode on the system console
boot dewce

i | Fldppy Directory

EVGDA;EXE

- EVGDAHLP
CIBCABIN
VMB.EXE

CIBCA EEPROM PROGRAM UTILITY |

HELP FILE FOR EVGDA
CIBCA MICROCODE FILE
VAX PRIMARY BOOT FILE (w1th CIBCA patch

‘Description
-

until VMS V4.6is released)

Turn OFF power to the system

| . Ground yourself
'Expose the VAXBI card cage
|

NOTE

Proceed directly to Section 2.5.2 if the CI bulkhead
~ cable assemblyis installed and the VAXBI card cage
~contains the T1015 module, T1025 module, and the

CIBCA intermodule cables

Velostat is a trademark of the Minnesota Mining and Manufacturing Co.
2-6

,PROCEDURE’
l.

Carefully insert the T1015 and T1025 modules into any two unoccupled but adjacent module

slots within the same VAXBI card cage (see Figure 2-4). The T1015 is insertedin the lower
numbered slot. If the present system cable configuration interferes with the installation of the
CIBCA, cables, and jumpers, then the T1015 and T1025 module slot positions (including
jumpers and cables) can be interchanged, however, thisi$ not recommended.
|

VAXBI
CARD CAGE
(FRONT)

T1025 MODULE —
R

T1.01 5 MODULE

COMPONENT SIDE

MKV87-1044

- Figure 2-4 . VAXBI Card Cage - Module Installation

If 'necessary, install the twof transition connector assemblies, DEC,.P/N 12-22246-01, onto the

- 'VAXBI backplane on the slots containing the T1015 and T1025 modules. Using the torque

- screwdriver supplied in the VAXBI tool kit, DEC P/N 29-25608 OO torque the transition

connector assemblies to 5 m/lbs +1 1n/lbs

Refer to Flgure2-5 while carefully connectmg the CIBCA mtermodule cables to the VAXBI
card cage connectors as follows

Attach a 0.7 inch cable at Zone C between the innermost connectors of the T1015 and T1025
modules.
Form the 2. 0 inch cable as shown and attach at Zone C between the outermost connectors of
the T1015 and T1025 modules
|

"ZONEC

ZONE D

|
ZONEE
|

" 2.0 INCH CABLE
17-01504-01

MKV87 1045

Figure 2-5 VAXBI Backplane - CIBCA Intermodule Cable Connectlons

Refer to Figure 2-6 while carefully connecting the internal CI bulkhead Cables.. |

5. "Route the 1nternal CI bulkhead cables and install the I/O bulkhead panel
6. | Install the RECEIVE dummy connector in Zone E of the slot contammg the T1025 (solder
side). Install the TRANSMIT dummy connector in Zone D of the slot contamlng the T1025
(solder side).

Install the RECEIVE cable connector intothe transition header in Zone E of the slot containing

- the T1025 (component side). Install the TRANSMIT cable connector into the transition header
in Zone D of the slot containing the T1025 (component side). Cables must exit toward Zone E.
Use tie-wraps to secure cables

)

DUMMY

" CONNECTORS

- eONEE

ZONE D

—

- 'ZONEE

T1015

)

-3

|1
T1025

—
|

VAX 8500/8550/8700/8800 VIEW

|
'_ MKV87- 1046 ' '_

'Frgure 2-6 CIBCA CI Intemal Bulkhead Cable Assembly Installatron

252 VAXBI Backplane Jumper Verificaton
on the user section of the VAXBI
Several jumpers and a VAXBI node ID encapsulated plug are usedThese
jumpers are configured at the
CIBCA.
the
for
backplane to control certain operating parameters
system. The configuration
the
in
d
installe
shipped
is
~ factory for normal operation when the CIBCA
in the other VAXcluster
selected
ers
paramet
the
settings of the CIBCA backplane jumpers must match
|

" nodes. Figure 2-7 illustrates a VAXBI backplane assembly.

VAXBI BACKPLANE

- ASSEMBLY

. MKV87-1047

VAXBI Stationary Backplane

'\Fi:gure 2-7

253 VAXBI Node
ID Plug

slot) provides an encoded 4-bit
An encapsulated plug on the VAXBI 'backpla'ne (on the T1015 module
ation number or VAXBI NODE, ID is
binary identification number. The decimal equivalent identific
|
|
|
- printed on the plug.

2.5.4 CI Node Address Jumpers

)

and its complement
The CI node addresiss obtained from the T1015 backplane slot. The CI node address
node address jumpers should be
must be configured exactly the same. Table 2-1 lists the way the CI
configured for a respective address. See Figure 2-8 for a detailed view of CIBCA jumper backplane
2-10

Table 2-1

CI Node Address Jumpers

D5-D35 D6-D36 D7-D37
E1-E31

<26>

- <2>

E4-E44

<24>

" ouT " ouT

OUT
OuUT
OUT

"IN

OUT

OUT
OUT

- OuT

IN
IN

OUT

"IN

<23

E6-E36

<22

- OUT

OUT

OouT

OUT

D10-D40 D11-D41 D12-D42

ES-E35

OUT
ouT

OouT
ouT

CIN

IN
IN

OUT

OuUT

CI NODE

E7-E37

E8-E38

<2l>

<20>

- OuUT
ouT

- ouT
IN

IN
OUT

223

ADDRESS
DECIMAL

ouT

IN
- OUT

224

IN
IN

DS8-D38 D9-D39

E3-E33

@®
® @
l®
®
@@
EXT HEADER

EXT ACK TO

® @
® 6

®
e

® @
1
CLUSSIZE
CLUSSIZE O

1® ©
©e

cNoDEA 2’

" CNODE A 2 6

| cnopE
A 2°

| cnopEA2

cNODEA

CNODE A 2 2

CNODEA

cNODEA2°0
BOOT TIME 3

| 8OOT TIME
2
BOOT TIME 1

SECTION D

NODEA
2

NODE A 2 6

® ©| NGDE A 2

® 8| NODEA 2

®®| “"NODE A 2

@ el

NODE A 2

|
@O

NODEA2

® O NoDE A 2°

DELTA TIME 2.

@
®| " DELTA TIME 1
oo

[

® 0|

POOOOOOOOOOOO O O
®O 006 PPRPOROOO®RER
OB

®®

BOOT TIME 0

PPEPPOEOOO®O®
O

Addresses above 223 decimal are illegal.

SXeXe
Yo xcxoxcxoxe
) G
POOOO
O

E2-E32

'DELTA TIME O
DIS ARB

@ @

SECTIONE

. MKV87-1048

Figure 2-8

CIBCA Backplane Jumper Pinning
2-11

2.5.5 Boot Time Jumpers

dapter waits after power up before exiting the CI
Boot time is the length of time the CIBCA adz

state. Table 2-2 identifies jumper positions to select the desired boot time.

UNINIT

Table 2-2 Boot Time Jumpers |
D13-D43

D14-Dd4

OUT

ouT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
IN
IN

OUT

IN
IN
OUT
OUT
IN

IN
IN
- OUT
OUT
IN
IN
- OUT

Time in Seconds

1500 (Default)

1400
1300
1200
1100
1000

OUT
IN
OouT
IN
oUT
IN
OUT

0900
0800
0700
0600
0500
0400
10300

OUT

0100

OUT

"IN

D16-D46

OUT
IN
CIN
OUT
OUT

IN
IN
OUT
OUT
OUT
OUT
IN

OUT
OUT
IN
IN
IN
IN
IN

DI15-D45

0200

0000

2.5.6 Disable Arbitration Jumpers

the normal
Jumper E12-E42 is the Disable Arbitration j umper. When inserted, this jumper defeats(Delta)
time.

and allows the T102 5 to transmit after waiting only one basic quiet slot
“arbitration sequence
This jumper is normally out.

2.5.7 Extend Header"Jlimper |

extend
Jumper D24-D54 is the Extend Header jumper. When inserted, this jumper allows the T1025 to
|
out.
normally
is
jumper
This
header.
the
in
the number of bit synchronous characters

2.5.8 Alter Delta Time 'Ju"mpers

These jumpers force the T1025 to incre

- the basic CI quiet slot Delta time. Table 2-3 identifies jumper

insertion to select the desired Delta time.

Table _2-_3 Alter Delta Time Jumpers
E09-E39

E10-E40

“E11-E41

OUT
OuUT
OuUT
OuT
IN
IN
IN
IN

- OUT
OUT
IN
IN
OUT
OUT
IN
IN

- OUT
IN
OUT
IN
OuT
'IN
OouT
IN
2-12

Quiet Slot Count
T
10
14
16
21
25
32
~ Illegal

2.5.9

Node Count Jumpers

These jjumpers force the CI arbitration loglc to arbltrate for more than 16 nodes Table 2-4 1dent1f1es the

jumper insertions to select the node count.

~ Table 2-4 Node Count Jumpers
D29-D59

ouTr
OUT
IN

Node Count

D30-D60

~(In Decimal)

our

IN
OUT

32
64

128

2.5.10 Extend ACK Timeout Jumper

Jumper D25-D55is the Extend ACK Txmeout_]umper When mstalled thlSjumper forces the T1025 to
increase the timeout perlod for a CI ACK return. This Jumper is normally out.

2-13

CHAPTER
3

ACCEPTANCE VERIFICATION

3.1 INTRODUCTION

‘Diagnostic Verification — Verifying the CIBCA hardware operation by running diagnostic tests with
the system in a standalone environment.

| Maintenance Verification - Facilitating VAXcluster maintenance by describing the tools that are
‘required and/or provided for individual nodes or options withina VAXcluster system.

3.2 POWER-ON PROCEDURE

Refer to the appropriate system user guide for power-on procedures.

3.3 DIAGNOSTIC VERIFICATION
|
|
e
SRR
To determine if the CIBCA adapter hardware is functioning properly, seven Level 3 diagnostic programs
must be executed. These diagnostic programs
and their applicable diagnostic supervisor program, are
contained on separate RX50 floppy diskettes.
|
|
|

Five of the seven Level 3 diagnostic programs are executed with the system operating in a standalone

environment (not connected to a VAXcluster and not running under the VMS operating system).

Two of the seven Level 3 diagnostic programs are then executed with the system operating in a
standalone environment (not running under the VMS operating system) but connected to the coupler in order to verify the functional CIBCA hardware operation within the system. This is referred
to as
functional level testing.
|
|
|
o
R

Table 3-1 lists the CIBCA dia‘gnoStic programs..lTable 3-2 »provides a summary of the CIBCA diaghOStic
testing hierarchy.‘Figure 3-1 describes the CIBCA acceptance testing flow.

Table 31 List of CIBCA Diagnostic Programs

Program
Title

Program
- Designation

EVGCA

EVGCB
EVGCC
- EVGCD
- EVGCE
EVGCK
- EVGCL

EVGCM

CIBCA T1015 Reparr Level Dlagnostlc 1

CIBCA T1015 Repair Level Diagnostic 2
CIBCA T1015 Repair Level Diagnostic 3
~ CIBCA T1015 Repair Level Diagnostic 4
- CIBCA T1025 Repair Level Diagnostic 1
CIBCA Repair Level Microcode 1
CIBCA Repair Level Microcode 2

EVGCN

EVGDA

EVGAA
EVGAB

EVXCI

- CIBCA Repair Level Microcode 3

CIBCA Repair Level Microcode 4

CIBCA EEPROM Programming and Update Ut111ty

CI Functional Diagnostic 1
'CI Functional Diagnostic 2
'CI Exerciser Diagnostic

Table 3—2 CIBCA Dlagnostrc Testmg Hlerarchy

| Dragnostrc | '.

Dlagnostrc

Program Level

Testmg Functlon

Tests the detalled hardware operatlon of the CIBCA adapter

Functional

'Tests the functronal hardware operat1on of the CIBCA

Exerciser

Tests the comrnunications hetween CI nodes.

Category

- Repair

adapter.

Detects a failing CI node.
Verifies repair of a failing CI node.

C START,) Y
POWER-UP SELF-TEST

REPAIR LEVEL DIAGNOSTIC
TESTING W/ATTENUATORS
ATTACHED TO Cl BULKHEAD

. P/‘\\

CONNECTORS

Cl BUS CABLE TESTING

“WITH REPAIR LEVEL

DIAGNOSTIC EXT__LOOP TEST
| AND ATTENUATORS ATTACHED
| TO ENDS OF CI BUS CABLES

PROGRAM/UPDATE THE
|

cIBCA MICROCODE EEPROM

USING EVGDA

'FUNCTIONAL DIAGNOSTIC
"TESTING OF CIBCA LOCALLY

THEN CONNECTED TO SC008

AND COMMUNICATING WITH
OTHER CI NODES.

MKV87-1049

Figure 3-1 CIBCA Acceptan'ce Te‘sting Flow Di‘agram

3-3

3.3.1

Prehmmary Setup

Before running the diagnostics, make the followmg CI bus loopback connections on the CI bulkhead

connector panel located at the back of the cabinet (see Figure 3-2).

PROCEDURE

Usmg one of the attenuator pads (P/N 12-19907-01) and two of the modulanty cables (P/ N
70-18530-00) supplied in the CIBCA Controlled Dlstrlbutton (CD) k1t DEC P/N

- A2-W1207- 10 connect TRANSMIT A to RECEIVE A.

Perform the same connectlon for path B‘usmg the other attenuator pad and two modularity

cables from the CIBCA CD kit. Connect TRANSMIT B to RECEIVE B.

MODULARITY

CABLE

P/N 70-18530-00

|-,—"\ ATTENUATOR
PAD

P/N 12-19907-01

~ MODULARITY
CABLE

P/N 70-18530-00

MKV87-1050

Figure 3-2 Diagnostic Loopback Cable Connections

3.3.2 Loading the Diagnostic Superv.i'sotProgram PROCEDURE

1.'

Insert the proper RX50 dlskette mto the console RX50 disk dl‘lVC unit 0.

Load the dlagnostlc supervisor program into physmal memory from the console load dev1ce

This procedure may vary depending -on the system type in which the CIBCA is installed.
Consult the applicable system installation manual for dxagnostxc supervisor load and run
procedures..

The following are examples to load the diagnostic supervisor.
VAX 8800 SYSTEMS

>>>@DIABOO (boots the diagnostic supervisor from the VAX console fixed disk)

3-4

VAX 8200 SYSTEMS

- Insert the dlagnostlc supervisor diskette into the left RXS50 drive, then
>>> B CSA1 (boots the dlagnostxc superv1sor from the o_onsole load deviee).
- Identify the CIBCA adapter and its node configuration parameters to the diagnostic supervisor
program. The ATTACH/SELECT sequence will once again vary depending upon the system
~type in which the CIBCA is installed. It is assumed that the installer is familiar with the
- diagnostic supervisor ATTACH and SELECT sequences for VAXBI devices on the processor
being used. Below are examples for attachlng the CIBCA hardware
im VAX 8800 and VAX

8200 series system env1ronments

" CIBCA ON A VAX 8800
- a.

All ATTACHes spec1fy1ng BI NODE numbers shouldbe documented to show that node |
numbers are to be in hexademmal

‘BI nodes instead of bemg attached to HUB should be attached to NBIBn, that is, the
following sequence should be added:
|
|

ATTACH NBIA HUB NBIAn

- LOGICAL ADAPTER #? N

!wherenOor 1

" ATTACH NBIB NBIAn
Device Name? NBIBn

BI#?n

'BI Node Number (HEX) 7’n

ATTACH

! where n 0 to 3

~!0orl

'n0to F

! Then attach UUT

Device name? CIBCA

! Device to test

- Device link? NBIBn

Device? PAAn

'BI Node (DEC) 7 n
BR Level? 4
CI address (DEC) ? n

! Specify the CI
!Bl node #
!
BR level 4

10-16

For example
ATTACH NBIA HUB NBIAO 0
ATTACH NBIB NBIAO NBIBO 1 0
ATTACH CIBCA NBIBO PAAO 2 4 0

| SELECT PAAO

! logical unit 0

! BI #1, Bl node 0
! BI node 2, BR level 4
' CI node O
! device to be run

CIBCA ON A VAX 8200

! Then attach UUT

,ATTACH
Device name? CIBCA
Device link? HUB
Device? PAAn
BI Node (DEC) 7 n
BR Level? n

! Device to test
'

' Specify the CI
! Bl node #
' BR level #
'0-16

- CI address (DEC) ? n

3-5

4. Select the CIBCA adapter as the unit under test, as follows: 4
|
DS> SELECT PAAO
5. : S»howp the tmit selected, as follows:
DS> SHOW SELECT
Repair Level Testmg

3.3.3

;

A minimum of five successful passes of each dlagnostlc program must be completed to satisfy acceptance

testing requirements. Examples 3-1 through 3 5 provrde trace printouts for dlagnostlcs EVGCA through
|

EVGCE respectively.

NOTE

HELP files are available under the dlagnostlc

supervisor for all the dlagnostlc programs mcludmg |

the supervisor program ltself

‘dPROCEDURE
1.
-

Whlle proceedmg through the dlagnostlc acceptance testmg, ensure that the dtagnostlcs are
accessible via the DEFAULT LOAD PATH. This may requlre changmg diagnostic medlain

the current load path device.

Load-the EVGCA dxagnostrc program, as folloWs:

. DS> LOAD'EVGCA (first -repairlevel diagnoStic) |
,' 3.

Set the de51red dxagnostlc supervrsor control flags to enable prmtmg of the number and title of

- each test before 1t is executed and to halt on a detected error.
DS> SET FLAGS TRACE, HALT

Start the diagnostic program. \
DS> START/ PASS 5

| 5.

Repeat Steps 1 through 4 to load and execute the remammg repalrlevel diagnostics (EVGCB
through EVGCE). Substltute the target filename in Step 2.

DS>
DS>

ATTACH CIBCA
SEL PAAQ

HUB PAAD

&4 O
12
|

SET TRACE, HALT
LOAD EVGCA DS> START

- PrOgram: EVGCA - T1015 CIBCA Repa1r Level D1agnost1c Part
1, Revision 1 0, 13 tests, at 11 45: 34 75. Test1ng _PAAQ
1:
Test
Test 2:
Test 3:

Device Type/BIIC Conf1gurat1on
BI Control and Status Register
BCA BI Required Register Test

Test

Test 4: BCA General Purpose Device Reg1ster Test
BCA User CSR Space Register Test
Test 5:
"Test 6: Port Status Register Test
~

Test
Test

7:
8:

"Test 9:

Test 10:
Test 11:

‘
BCA Specific Register Test
Local Store/VCDT Address Read/wr1te Test

Local Store/VCDT Data Read/Write Test

Local Store/VCDT Dynamic Memory Test
Control Store Address Test

Test 12: Control Store Read/Write Ram Test

Test 13: Control Store Ram Dynamic Memory Test

.. End of run, 0 errors detected pass count is*1,'time is

24OCT-1986 11:47: 09 98
Example 3-1

Trace Prmtout for Repair Level Dlagnostlc EVGCA

DS> LOAD
DS>

EVGCB

START

. Program: EVG(CB - T1B15 CIBCA Repa1r LeveL D1agnost1c Part

Revision 1.0,

17 tests,
at 11:49:36.98.

Testing: _PAAO

Test

"Test

Internal

Test
Test
Test
Test
Test

3:
4:
5:
6:
7:

Microprogram Controller UPC+1 Test
Microprogram Controller JSB/RSB Test
Microprogram Controller Pop Micro Stack
Single Operand Instruction -Test
Two Operand Instruction Test

Test

Rotate

EEPROM Integrity Verification Test

Test

11:

Set

Ram MIMUM Bit n Instruction Test

Test

12:

Set

ACC

Bus

Test 8: Single Bit

~ Test 10:

Branch/Sequencer Jump

Shift

Bit

Test

Instruction Test_

Instruct1on

Test

Set RAM Bit n Instruction Test
Minus

Test

Bit

Instruction Test

Test 13: Set DLATCH Bit
n Instruction Test
Test 14: Reset RAMBit n Instruction Test
Test 15: Reset ACC Bit n Instruct1on Test

‘Test 16: Reset DLATCH Bit n Instruction Test
Test 17: Test RAM Bit n Instruction Test
.
End of run, 0 errors detected, pass count
24 OCT
-1986 11: 50:00.02

e
time

Example 3- 2 Trace Prmtout for Repalr Level Dlagnostlc EVGCB

3-8

DS> LOAD EVGCC
'DS>

START

ic
Part
.. Program: EVGCC - T1015 CIBCA Repair Level Diagnost
_PAAQ
Testing:
11:50:13.17.
at
3, Revision 1.0, 18 tests,

Test ACC Bit n Instruction Test
Test 1:
n
Test
2: Test DLATCH Bit n Instructio
Test

Test

Test 5:

n Instruction Test
Load RAM Bit

Load RAM NOT Bit

Instruction Test

Load ACC Bit n Instruction Test

Test
6:
Test 7:
Test 8:

Load ACC NOT Bit n Instruction Test
Load YBUS Bit n Instruction Test
Load YBUS NOT Bit n Instruction Test

Test 10:
Test 11:

Add ACC Bit n Instruction Test:‘
on
Test
Add DLATCH Bit n Instructi

- Test 9: Add RAM Bit n Instruction Test

//\\

~Test 12:

Rotate and Merge by n Instruction Test

Rotate and Compare by n Instruct1on Test
Prioritize Instruction Test
|
|
Test 15: CRC Instruction Test
Test 16: No Operation Instruct1on Test
L
~ Test 17: AMD29116 Internal Register Address Test
'Test_18:_Local Store/VCDT Microcode Access Test
‘Test
Test

13:
14:

. End of

-0CT-1986
24

run, 0

errors detected, pass

11:50:59. 24

1is
count is 1, “time

Example 3 3 Trace Pnntout for Repan' Level Dlagnostlc EVGCC ‘

3-9

DS>

LOAD

DS>

START

EVGCD

e« Program:

EVGCD
-

T1015 CIBCA

1.0,

teSts, at

Revision

Test

Local

Repair

Level Diagnostic
Part

11:45:34., 75.

Testing:u_PAAO

DuaL Address Test

Store/V1rtuaL Circuit

Descr1ptor

Error Test
Test 3: Interrupt

Test

MTE

M1crouord

Test
Test

6:
7:

Control Store Parity Error (CSPE)
Condition Code Branch MUX Test

Test
Test

8:
9:

Maintenance
Tick Branch

Test
Test

10:
11:

IB Register Read/Write Loopback Test
BCAI Register Test

Test
Test

12:
13:

" Test

14:

Power

‘Test
Test

15: CBOR/CBIR Port Initiated Loopback Test
16: Command Address/Byte Count Reg1ster

Test

17:

Datamover

Test
Test

18:
19:

Datamover Read/Write
Page Overflow Test

Test
~Test
Test

20:
21:
22:

Write/Stop Command_Test
BI Slave Transaction
Test
Suspend and Release II Bus Test

Test

23:

Suspend and

End of

24-0CT-1986

run, O

~Test

Interrupt

Test

Verification

Test

Timer D1sabLe
Test

Fail

Table Parity

Test

Durina

Test with

Test
S

Branch Test

Power

,
Fa1t

D1sabLe

Set

Test

Loopback Test

Release

to Host Memory Test
|

CILP Bus

Test

errors detected pass count is

11:50:25.08

Example 3-4 Trace Printout for Repair ‘Levei Diagnostic EVGCD |

3-1{0

1, time

DS> LOAD EVGCE
DS>

START

.. Program: EVGCE- CIBCA T1025 Repair Level Diagnostic
Revision

Test

1.0,

1'—L1nk

15 tests,

Conf1gurat1on

11:51:52.34.

CILP Bus

Testing: _PAAO

Integr1ty

Test

'iContents of CONFIGURATION Reg1ster O

' True Node Address fi OE
Cluster

Size

: 00

Extended

ACK

.00

- Extended
~

Disable

Delta

Header
ARB

Time

: 00
: 00
: 01

vContents_ofCONFIGURATION.RegiSter 1
CompLement
Boot

Time

Node AddreSS‘:
-

Buffer

Data

Test

Packet

Test

Transmit

OF
Integr1ty Test

with External/Internal

Loopback

Set

Test'

Test 4: Transmit with Internal Loopback Set Test
Test
S: Transmit with External Loopback Set Test
Test 6: Force Transm1t Parity Error in InternaL Loopback
Test
7: Invalid

Test

9: Bad

Test
Test
~ Test

Test
Test

Test

Complement

True/Complement
CRC

Destination

Dest1nat1on

Test

Node

Number

Test

Swap

Test

10: MNegative (NAK) Acknowledgement Test
11: Transmit Abort Test
12: Extended Link Configuration Test

13: Valid CI Node Number Test,
14: Internal Interaction Test
15: Arbitration Time Test
|

e« End of
run,
0 errors
24-0CT-1986 11:57:21.16

detected,

AlL

Comb1nat1ons

e
pass

count
-

B
is
1,
o

'Example 3-5 Trace Printout for-'R_epair Level Diagnostic EVGCE

3-11

»
time

334 CI Bus Cable Testing

- After successfully completing five passes of each of the five repaxr level diagnostics, remove the attenuator pads and modularity cables from the CI bulkhead connectors (J 21-J24) and perform the followmg
steps.

PROCEDURE
1.

Venfy that this CIBCA port has a umque node address within the VAXcluster before connect-_
ing any cables

Locate the set of four CI bus coax1al cables (BNCIAXX) Label each end of the CI bus
coaxial cables with the CI node and CI path information using the labels provided with the
BNCIA-XX cables Connect one end of each cable to the approprlate CI bulkhead connector.
NOTE

The coaxnal CI bus cables may be connected to or
removed from the CI bulkhead connectors without
powering down the system. DO NOT unroll or

| 'route the CI bus cables at this time.

Connect the two attenuator pads to the free ends of the coaxial CI bus cables. Be sure to
connect TRANSMIT A to RECEIVE A and TRANSMIT B to RECEIVE B.

- Run five passes of the EXTERNAL__LOOP sectlon of the dlagnostlc program EVGCE to
test the CI bus cables.

DS> RUN EVGCE/SEC: EXTERNAL_.LOOP/PASS 5
3.3. 5

CIBCA EEPROM Programmmg and Update Utlhty

| PROCEDURE

Insert the RX50 floppy contammg EVGDA and the CIBCA mlcrocode f11e CIBCA BIN into
|

~ the console floppy drive being used as the diagnostic load path.

By default, tests 3 through 5are run. Tests 1,2, 6 and 7 are specral purpose tests these are not
normally executedin the field.

Load the EVGDA dlagnostlc program as follows

DS> LOAD EVGDA
Start the diagnostic program.

DS> START
Example 3-6 shows a trace printout when running the (default) update section .

3-12

| ..'Program:

EVGDA - CIBCA EEPROM Programming
and Update

Utjlity, Revision
PAAQ

1.1,

7 tests,
at 10:32:34.78.

Testing:

Summary of EEPROM data from File Header

" The EEPROM Version Number is: 0001
The EEPROM CRC Value is: 5012E01c
The
The

EEPROM
EEPROM

Starting Logical Block Number is: 1
Microcode S1ze, in Bytes,'1s' 8190

Summary of Functional data from File Header'
The Functional Version-number is: 0001
TN

"The

Functional

The

CRC

VaLue'iS:

SB9DGASBF

Functional
Starting Logical Block Number is:

The

Functional Microcode

Size,

in 16-Bit

NOrds,

is:

12288

Test 3: Update the EEPROM Microcode Started Update of the

~EEPROM

29-0CT1986

10:32:46.05

,CURRENT‘vaLue of EEPROM Update Counter-is-: 4
NEW value of EEPROM Update Counter
is : 5 Finished with
Update of the EEPROM at 29-0CT-1986 10:34:09.39

Test

4:"Ver1'.1‘y‘j “the

Verification
Finished

mth

the

Contents

»EEPROM

Stahted

EEPROM at 29-0CT-1986 10:34:10.29

Ver1f1cat1on

the

EEPROM

29~ OCT
-1986

10:34:10. 98

Test '5:
Selftest
Selftest

Execute and. Check

Setftest~'StatUSv'Started

Execution at
29-0CT-1986
10:34:11.99
Execution at 29-OCT-1986'10:34;11.99'

End of run; 0 errors

29-0CT-1986

detected pass

10:34:13.24

count is

Finished

Example 3-6 Trace Prmtout for Repaxr Level Dlagnostlc EVGDA

3-13

time

Functional Level Testing

' 3.3.6

With the CI bus cables and attenuator pads providing s1gnal loopback load and run the CI functlonal
diagnostics EVGAA and EVGAB. A minimum of five passes of each diagnostic must be completed to
satisfy acceptance testing requirements. Examples 3-7 and 3-8 show trace prmtouts for diagnostics
|

EVGAA and EVGAB respectlvely

PROCEDURE

Whlle proceedmg through the diagnostic acceptance testmg, ensure that the diagnostics are

accessible via the DEFAULT LOAD PATH. ThlS may requlre changmg dlagnostlc mediain

. the current load path device.

2. | Load the EVGAA dtagnostlc program
DS> LOAD EVGAA (first functlonal dragnostlc)

Set event flag 1 to load the CIBCA BIN nucrocode Thisis always requlred after running the

- repair level dlagnostlcs

DS> SET EVENT FLAG 1

Set the desired diagnostic supervisor cont-rolflags to enable printing of thenumber and title of
each test before it is executed and
to halt on a detected error.

DS> SET FLAGS TRACE, HALT
5 Start the EVGAA dlagnostlc program
|

DS> START/ PASS:5

6. B After five successful passes of EVGAA load and run EVGAB by typmg the followmg
-

DS> LOAD EVGAB

DS> CLEAR EVENT FLAG 1
DS> START/ PASS 5

.Dlsconnect the attenuators from the ends of the CI bus cablesin preparat1on for routmg and
connectmg the cables to the star coupler

- 8. Route and connect the CI bus coaxral cables to the coupler.
NOTE

For information and connecting of the coaxnal CI
bus cables to the star coupler, refer to the SC008
Star Coupler User’s Guide.

Run EVGAA and EVGAB

3-14

'DS>

LOAD

DS>

SET

EVENT FLAG

EVGAA

DS>

SET

FLAGS

DS>

START/PASS:5

TRACE,

HALT

.. Program: EVGAA - CI FUNCTIONAL
PART I, Revision

tests,

11:11:45.99.

Flag
2 SET
Flag 3 SET

Testing

Load-CI,Microcode

Event Flag 1 SET
Event
Event

Testing _PAAD

Queue

REQID

Loop Function

Entries

o
in

Test

Device _PAAQ

EEPROM‘Revision.= 0001

Functionat'Revision =‘O0D1

Test
1: Cluster Cdnfiguratidnf‘

Contents

the

PPR:COFFO010E(X)]

PORT

PARAMETER

;

CLUSTER_SIZE=16,
IBUF_LEN= OFFD(X)
MBZ=0(X),
DISABLE_ARB=0(X),
EXTENDED HEADER=0(X),
SLOT_COUNT=10,
PORT NUMBER=0E
(X

Cluster

~Configuration

for

’v********************************

CANNOT

Differentiate

CIBCI remotely.
= Receive

Node

CI780,

CI750,

(PSv=_Path.SeLect,»TP = Transmit Pafh,

Hard

Soft

CIXXX

0007

FFFFOFO0(X)

03
OE

HSCSO
CIBCA

0225
4F710200¢Xx)
0001 “0001.
FFFFOFOO(X)

OK
0K

A
A

" Type

Path)

.Devicé

Number

‘Rev.

Pcrt

Rev.

Functionality

’aPath'

Status

Cluster Configuration for Path B'
(PS

Path

Nofle

| Devicev

Number

03
OE

Select,

Type

CIXXX

HSCSO0
CIBCA

TP
= Transmit

Hard
|

Rev.

0007

Rev.

0007

‘

Path,
RP = Receive

Sdffv’f.

0225
‘_0001
0001

Port

Funct1onal1ty

FFFFOFOOCX)

4F710200(X)
'FFFFOFOO(X)~

Path)

»‘Path
-

Status

0K
0K

P
S

B
B

Example 3-7 Trace Pifilntout'fOr_F unctional Diagnostic EVGAA (Sheet 1 of 2) B |

3-15

DWW Vo

********************************

mow
i v

between

>>»>»| U
BB
> I DD

You

Path

Nodes NOT Listed do not exist on Cluster

SETCKT with‘Var{ous Masks and M Values

Test

SETCKT for Each Valid Port
SETCKT for Invalid Port

Test 3

Test

5:
6:
7:

Test
Test

Test 8:
9:

Test

REQID

Basic

REQID With 6 Packets on DGFQ

Datagram Discard
Response Queue Available
Send Datagram

Interrupt

1 0: - SNDMSG With No V1rtuaL C1rcu1t Open
11: ~Send Message Crossing Page Boundary

- Test

Test

12: Message Length Test
Test 13: Packet Size Violation
Test 14; Send Loopback (SNDLB)
Test 15: SNDLB Full Buffer On Path
Test 16:
SNDLB
Full Buffer On Path
Test

A
B

17: SMDLB Automatic Path Selection
e First pass done, 0 errors detected, time
11 12 55.07
Test

s 24+ocT—1986

Example 3-7 Trace Pnntout for Functional Dlagnostlc EVGAA (Sheet 2 of 2)
B

EVGAB

DS>

LOAD

DS>

CLEAR

DS>

SET

DS>

START/PASS:5

«..Program:

EVENT FLAG

1,
2

TRACE ,

HALT

FLAGS

EVGAB - CI FUNCTIONAL PART 1II, ReVision-4.0, 12 tests

00:00;00.00._ Testing:

ROM REVISION - 0001
Test

Test 2:
-~ Test
3:

Test

_PAAO

NCS REVISION

WITH OFFSET COMBINATIONS
|
SEND DATA TEST,
|
REQUEST DATA TEST, WITH OFFSET COMBINATIONS
INVALIDATE TRANSLATION CACHE TEST
SNDMDAT TEST, ENABLED/MAINTENANCE STATE

SNDMDAT

TEST,

ENABLED STATE

6:
7:
8:

REQMDAT

TEST,

ENABLED/MAINT

Test
Test

REQMDAT

TEST,

ENABLED

" Test

Test

" Test

11:

Test

12:

..«

End

-~ time

STATE

SEND RESET TEST IN ENABLED STATE
QUEUE CONTENTION TEST
|

10: BUFFER

Test

0001

BUFFER

READ

WRITE

ACCESS

TEST

ACCESS TEST

WRITE TO GLOBAL BUFFER TEST

of run, 0 errors detected,
is 15 JUuL-1985 00:00: 00 00

Example 3-8

pass

count

Trace Printout For Funcnonal Dlagnostlc EVGAB

3-16

3.4 REFERENCES

3 Table 3-3

Summary of the Functions of VAXcluster System Maintenance and Management Tools

Tool

Function

A Level 2R multipurpose exerciser that provides local CI interface functional

CI Exerciser
-

communicate using the CI bus.

as they are logged by the VMS operating system. It prowdes the user with a
warning mechanism that quickly identifies an option thatis either failed or has
degraded operationally. See Note 1.
-

SET HOST/HSC

A VAX system integri'ty monitor utility program that monitors and filters errors

VAXsim

SHOW Cluster

testing as well as a means to determine the ability of VAXcluster nodes to rehably

~ Allows the display of a large vanety of utlhty 1nformatlon relevant to the conflguration and operation of the VAXcluster of which the host system is a member See
Note 2.

Allows..a terminal. on a host VMS system to effectively become an HSCS50

. terminal. The user may thenissue any standard HSC50 commands and look at or
control the HSC50 just as if it were a terminal connected directly to one of the

HSC50 termmal ports See Note 3
NOTES:

For more information, consult the VAX System Integrity Monitor Manual.

2. For more _information, consult the VAX/ VMS Show Cluster Utility Manual.

For more information, consult the VAX/ VMS. DCL‘Dictionary under SET HOS'T/HSC.

3-17

CHAPTER 4

CIBCA TROUBLESHOOTING

4.1

INTRODUCT ION
|
This chapter prowdes mformat10n ‘that w1ll helpin troubleshootmg a CIBCA

4.2

CIBCA MICROCODE REVISIONS

- The loadable binary file CIBCA.BIN revision can be checked by using the VMS DUMP utrhty A dump
of the fileis 111ustrated
in Example 4-1.

After successful completlon of CIBCA self-test the mlcrocode CIBCA. BIN is loaded into the control

‘store. Control store location ‘bb+108C contains therevision number of the functional mlcrocode and
‘location bb+1090 contams the revision number of the EEPROM code.

Dump of file oxsxsaca LATEST:CBCA_LATEST.UCODEJICIBCA.BIN;2

File

(176,68192.0)

End

1110

block

Allocatod

ertual block number 1 (00000001), 512 (0200) bytes
00000000
00000000

00010000
00000000

1FFEQO000

E01C3130 3030204E
00000000 00C00000 00000000

5-DEC-1986

09:24222.37

EEPROM VERSION NUMBER

49422841

434626943

00000000

00300000

00000000

0001c aPeeee“cacacccee
ecececccccccaccccnces secccccoces
ccececccccscscscasecancccncccans

000000

00000000

00000000
00000030

00000000
00000000

000060

00000000
00000000

ececcccecocccascccccsccccncsconses

00000000
00000000

00000000

00003000
00000000_00000000

00000011

5835J648F

31303030

00000000 00000000

00000000

00000000 00000000

00000000
00000000

00000000

00000000
00000000

00000000 00000000 00000000
00000000 00000000 00000000
00000000

00000000

00000001

00000000

00015012

CIRCA.BIN

000020

Q00040

ececceccccceccucccsccacces eesessecas 000030
@cecssccscccsscscccnscssscnsscas - 0000A0

ecececcccceccss eesccsccscscccsnsase 00g00Co
cecceccccescacancacasesecsseccnce - 0000E0
0001lejelocccelecoccccscscncncncse 000100
« M eccecoceccnnns -"";‘9 ........ 000120

— _FUNCTIONAL VERSION NI'UMBER

Example
4-1 CIBCA.BIN
4.3 CIBCA FRU LIST
‘See Table l 1 for a list of the hardware FRUs used m
i the CIBCA
4.4 CIBCA SELF—TEST TEST DESCRIPTION
The CIBCA self-testis made up of a collection of tests. These tests, along with a brlef descrlptlon of what |
each test checks are listedin Table 4-1.

4.5 CIBCA SELF-TEST TEST/ FAILURE CODE REGISTER (STFCR) bb+1FFC
‘Figure 4-1 illustrates the STFCR register. At the begmnmg of each test, regxster STFCRis loaded with the
test number and O for a failure code. If test 1 is ready to run, the STFCR is loaded with 1000 (hex).
During each key failure point of the test, the failure codeis incrementedin case of a failure. If a failure
occurs, the STFCRis written to local store location 3FF (hex) or bb+lFFC (hex) so it can be accessed

from the host bus.

Table 4-1

CIBCA Self-Test

Test

Number

1
|

Name

Description

29116 Status|

Checks the Z, N, O, and C bits.

ALU RAM Test

Checks the 32 RAM locations.

Index Register,

Checks the dlfferent ways to WRITE and READ the control |

2
3

Literal Register,
Local Store, and

store

MUX Test

Packet- Buffer

WRITEs all four packet buffers w1th a data pattern and then -

WRITE/READ Test

reads/checks the data.

'Move Data Test

Performs a loopback of data from the BCAI DMA files

through the link/packet buffer module and back into the

BCAI DMA files.

(BIIC) STS Bit

Verrfies that the BIIC self-test passed

Set Test

Data Mover WRITE

_Checks the SEL logic.

Loopback to Local
Store Test

WRITE/READ

~and address lines.
|
|

- Toggle Register :

| Setsand olears the bits in the toggle regiSter. o

- Parity Bits Test

' Checks the different PE bits 1n the PMCSR register.

XBUS R’egister

Test

~ WRITE:s all the XBUS registers and then checks the data by

way of the index register. |

BI WRITE/READ

Test

-14

~ Checks the IB, II, BCALBIIC, local store, and the 29116 data

Loopback to
Local Store Test

TEST NUMBER

,11'

Performs a self-directed WRITE/READ to the BIIC GPR

number 0 (defined in CIBCA as the PQBBR) to ensure that
the CIBCA can accessitself over the BI bus.

7 6

4 3

2 1

FAILURE CODE
MKV87 1051

Flgure 4- Self-Test Farlure Code Reglster (STFCR)

4. 6

CIBCA SELF-TEST FAILURE CODES AND FRUs

The followingis a look-up chart for the STFCR register. If the CIBCA self-tcst fails, the contents of the

STFCR reglster bb+1FFC, in conjunction with this chart, can be used to identify the falhng FRU.

Probable FRU Failure

,STFCR Contents
100X
200X
IXXX
- 400X
5001
5002
5003
5004
5005
5006
15007
5008
5009
~ 500A
500B

T1015 PCM
T1015 PCM
‘T1015 PCM
T1015 PCM
T1015/T1025 PCM/CCI
T1015 PCM
|
T1015 PCM
T1015 PCM
T1015 PCM
T1015 PCM
T1025 CCI
T1025 CCI

500C

T1015 PCM |
T1025 CCI
T1025 CCT.

T1025 CCI

500D
500E

T1015 PCM
T1015 PCM

5020
5021
5022
5023
5024
5025
5026
5027

T1015 PCM

S00F
501X

T1015 PCM
T1015/T1025 PCM/CCI

|
T1015 PCM
T1015 PCM
T1015 PCM
T1015/T1025 PCM/CCI
T1025 CCI
T1015 PCM
T1015 PCM

5028

'T1025 CCI

5029
502A

T1025 CCI
'T1025 CCI

502B
502C
502B
502C
502D
502E
'502F
503X
600X
700X

T1015 PCM
T1015 PCM
T1015 PCM
" T1015 PCM
- T1015/T1025 PCM/CCI
T1015/T1025 PCM/CCI.
T1015 PCM

T1015 PCM

800X
- 90XX
AOXX
BOXX

coxx

T1015 PCM
T1015 PCM

T1015 PCM

T1015 PCM
T1015 PCM
T1015 PCM

T1015 PCM

APPENDIX A

CIBCA REGISTER SUMMARY

A.l

INTRODUCTION

This section presents the interface conventions Wthh allow programmer access to the CIBCA adapter

functions and access to the software registers that are used to control and monitor the operation within the
CIBCA adapter 1tself Entry to these reglsters is accomplished through the VAXBI address space area.

A.2 VAXBI PHYSICAL ADDRESS SPACE

The physical address on the VAXBIis 30 bits long, thereby, provrdmg a VAXBI physrcal address space of
one gigabyte. A program will access this physical address space whenever it makes reference to a CIBCA
adapter’s hardware or software reglsters

The VAXBI physrcal address space is dmded into two parts; memory space and I/O space Selectlonof
memory space and I/O space is determmed by address b1t <29> of a READ or WRITE VAXBI bus

transaction.

e | Physrcal Memory Space Addresses |
The first 512 Mbytes (addresses OOOO0000 through 1FFF FFFF hexadec1mal) are physwal
memory space addresses

I/O S’paCe Address’es'
The last 512 Mbytes of the VAXBI physical address space (addresses 2000 OOOO through 3FFF o
FFFF hexadecimal) are I/ O space addresses |
N

Figure A-l 111ustrates the physical partmomng of the VAXBI physical address space. As shownin Flgure
A-2, the 512 Mbyte VAXBI I/O address space is orgamzed into several categories: map window,

broadcast space, and node space. Only the VAXBI node space is used by the CIBCA adapter.
Node Space

The VAXBI node space (Figure A- 3) is organized into sixteen 8-Kbyte address blocks. The CIBCA

adapter hardwareis assigned to one of theseaddress blocks. This address blockis referred to as the CIBCA
adapter node Itis accessed whenever a CIBCA adapter hardware or software reglster is referenced

DURING THE C/A CYCLE ON VAXBI D<31:00>

LENGTH

‘”

‘

Cnsssusmsmnnd

7313029

30-BIT ADDRESS

0 = MEMORY SPACE
1 =1/0 SPACE

1 512 meyTe A 3FFF FFFF
1 512 MBYTE,l 1FFF FFFF
.,

MEMORY .

I SPACE_

T 0000 0000

1 GIGABYTE ADDR’-ESS SPACE
MKV86-2038

Figure A-1 VAXBI Physical Address Space

RESERVED
MAP WINDOW
:NODE PRIVATE
| MULTIBROADCAST

, SPACE
VAXBI NODE SPACE
- MKV85- 2552

Flgure A-2

VAXBI Physwal I/ O Address Space

f_rvAxslNODE

ReserveD

MAP WINDOW

NODE PRIVATE

“MULTIBROADCAST
SPACE

VAX8| ADDRESS SPACE

VAXBINODESPACE | <

]

ciBcA ADAPTER NODE

VAXBI NODE 0

MKVES-2550

IFigure A-3 VAXBI Node Space

‘A3 CIBCA ADAPTER NODE ‘
A3

Addressing

‘ 'DUR_ING THE C/A CYCLE ON VAXBI'D<31 :00>:

The address area of the CIBCA adapter nodeis calculated by takmg the base address representing the
VAXBI I/O address space (2000 0000 hex) and adding 8K times the node ID, plus the offset address of
the device register. For simplicity, this calculated addressis represented by “bb+" whenever a reference is
made to any of the following register bit maps. Figure A-4 illustrates the format structure of a 30-bit I/ 0)
address Table A 1 lists the startmg addresses of the 16 VAXBI nodespaces.
|

O E

313029

~ LENGTH

2028

|1|4

30-BIT ADDRESS

1/ ADDRESS SPACE -

1716

|noDEID|

1312

T ]

ADDRESS WITH 8 KBYTES OF NODE SPACE

MKV86-2039

'Figure A-4 30-.Bit I/0 Address Bit Map
A3

Table A-1 Node Space Address Assignments

erode 1)

)

Base Address

mmg(}m}ooo*\_lcsm.puw"—c

2000 0000
2000 2000

2000 4000
2000 6000
2000 8000
2000 AOO0

2000 C000
2000 E000

2001 0000
2001 2000
2001 4000
2001 6000
2001 8000
2001 A00O
2001 C000
2001 E000

NOTE:

T Offset address range OOOO to lFFF hex

'A 32 Partmomng

- As shownin Figure A-5, the CIBCA node space is d1v1ded 1nto two segments: VAXBI CSR space and

User CSR space. The VAXBI CSR space occupies the first 256 byte locations andis used by the VAXBI
protocol and VAXBI control logic of the CIBCA adapter hardware. The User CSR space occupies the
remaining locations of the address block. Only a portionof these addresses are used by the CIBCA
~ adapter. Reading or writing to an unused register address will produce unpredictable results such as,
unpredlctable data p0551ble panty errors, and p0531ble VAXBI NO ACK responses.
|

- | VAXBI NODE 15 |

RESERVED

| vaxsi NODE 14 '

FoPAVED

“MAP WINDOW

—

NODE PRIVATE

MULTIBROADCAST

~ VAXBI ADDRESS SPACE
SR

']v

_VAXBI NODE SPACE

USER CSR SPACE

| CIBCA NODE SPACE |

| SPACE

VAXBI CSR SPACE

! VAXBI NODE 1_ {
VAXBI NODE 0_

MK V85-25563

Figure A-5 CIBCA Address Node Space

A.3.3

Registers

Figure A-6 shows that the first 256 bytes of the CIBCA node space are reserved for the VAXBI CSR
registers. VAXBI required registers and specific device registers fall into the category of VAXBI CSR
registers. The VAXBI required registers are used by all VAXBI nodes including the CIBCA. The specific
~device registers are special-purpose VAXBI registers used to control the VAXBI device window area, and
VAXBI data transfer control and interrupt control. The remaining addresses of the CIBCA node space are
reserved for User CSR registers. The adapter registers fall into this category and are used for initializing
and controlling the CIBCA adapter hardware All these regrsters are accessed usmg longword addresses.

" Flgure A-7 111ustrates the VAXBI interface reglsters and adapter reglsters
NOTE

- The CIBCA adapter hardware onlyi ssues Iongword
or octaword VAXBI bus transactions.

-’

FFFF

| vaxeinooeo

R
|

—

CIBCANODESPACE
SRR

NOpRSTAE

—

_VAXBINODED

'CIBCA SPECIFIC

| 104C

__REGISTERS

[

USERINTERFACE

(s SPACE

|,000

200

L
100

T |

— I

USER CSR SPACE

Jicao

_ LOCALSTORE| 1050

__veor _

T GENERALPURPOSEilvOOFC
[

__REGISTERS

vaxsispeciric | 99%°
REGISTERS

VAXBI REQUIRED

|
-

| goF0

L_REGISTERS

| 0020

001C

[ ;000

VAXBICSR

SPACE
MKV86-2040

Figure A-6 CIBCA Adapter Register Address Space

| VAXBI REQUIRED REGISTERS

bb+00
bb+1C

bb+20

bb+FO

BIIC SPECIFIC DEVICE REGISTERS

L GENERAL PURPOSE REGISTERS
T

bb+FC

bb+100

| SLAVE- ONLY STATUS REGISTER

bb+200 IRECEIVE CONSOLE DATA‘REGISTER»" qi

bb+FFC

RESERVED/NOT ASSIGNED

" bb+1000

| PORT STATUS REGISTER

bb+1004

bb+1008

) §

bb+204 IRESERVED/NOT ASSIGNED

| PORT MAINTENANCE CONTROL/STATUS REGISTER
- MAINTENANCE ADDRESS REGISTER

=
bb+100C | 'MAINTENANCE DATA REGISTER
'PORT COMMAND QUEUE 0 CONTROL REGISTER |
bb+1010
bb+1014- " PORT COMMAND QUEUE 1 CONTROL REGISTER
PORT COMMAND QUEUE 2 CONTROL REGISTER
bb+1018

bb+101C | PORT COMMAND QUEUE 3 CONTROL REGISTER
PORT STATUS RELEASE CONTROL REGISTER
~ bb+1020

bb+1024

PORT ENABLE CONTROL REGISTER

bb+1028

~PORT DISABLE CONTROL REGISTER

bb+102C

- PORT INITIALIZE CONTROL REGISTER

PORT DATAGRAM FREE QUEUE CONTROL REG.

bb+1030

PORT MESSAGE FREE QUEUE CONTROL REG.

bb+1034

- PORT MAINTENANCE TIMER CONTROL REG.

- bb+1038

- PORT MAINT. TIMER EXPIRATION CONTROL REG.

bb+103C
bb+1040

RESERVED REGISTER 3

bb+1044

RESERVED REGISTER 4

bb+1048

RESERVED REGISTER 1

bb+104C |

bb+1050

bb+1BFC
bb+1C00

RESERVED REGISTER 2
-LOCALSTORE
LOCAL STORE
VIRTUAL CIRCUIT DESCRIPTOR TABLE

.bb+1FFC [ VIRTUAL CIRCUIT DESCRIPTOR TABLE
MKV86-2041

B Figure A-7

VAXBI Interface Registers and Adapter Registers

Ad VAXBI REQUIRED REGISTERS

Flgure A-8 illustrates a more detailed dlagram of the VAXBI requlred regxsters. B

bb+0000

DEVICE REGISTER

'bb+0004 | VAXBI CONTROL AND STATUS REGISTER
bb+0008 | BUS ERROR REGISTER

bb+000C

| ERROR INTERRUPT CONTROL REGISTER

bb+0010 | INTERRUPT DESTINATION REGISTER

bb+0024

bb+0028 | BCI CONTROL AND STATUS REGISTER
bb+002C | WRITE STATUS REGISTER

bb+0030

| RESERVED

bb+00FO

| PORT QUEUE BLOCK BASE REGISTER

bb+0040 | USER INTERFACE INTERRUPT CONTROL REG.
|

bb+00F4 | PORT FAILING ADDRESS REGISTER

bb+00F8

bb+OOFC

PORT PARAMETER REGISTER

| PORT ERROR STATUS REGISTER
MKV86-2042

Figure A-8 VAXBI CSR Space

= 0000
A.4.1 Device Reglster (DTYPE) (R/W,DMW DCLOL) OFFSET
The Device Register (Figure A-9) address offset
= 00 hex, field bits <15:00> identifies the type of node
for use by the VMS operating system’s devme drlver software The dev1ce type assigned to the CIBCA

N adapter1S 0108 (hex).

Field b1ts <23: 16> 1dent1fy the port revision level Fleld bxts <28 24> 1dent1fy the link revision level Bit

<29>is reserved. Bit <30> indicates packet buffer size (0=1K, 1=4K). If blt <3 1>is a0, it implies half-

duplex operatlon If b1t <31>is a 1, it implies full-duplex operatlon

313029282726252423
|

1615
.
TYPE = 0108 (HEX)
DEVICE
|
PORTREV

FULL-DUPLEX HA J

PACKET BUFFER SIZE 4K H

|
RESERVEDREV 244 |
"REV 234
|
REV 22
REV 214

REVZ204

PORT MODULE REVISION LEVEL=
NODE TYPEMKV86-2043

Figure A-9 Device Register. Bit Map

A.4.2 VAXBI Control and Status Register (VAXBICSR) OFFSET 0004

The VAXBI Control and Status Register, address offset 0004 (hex), contains control and status mformation bits. It also contains the BIIC type and the node ID, and spec1fles the mode of arbitration. Flgure A-10
'111ustrates the reglster format. The b1t a551gnments are descrlbedin Table A- 2
3

~
N

_2423; oLl

VAXBI|

vaxel

INTER REV.___

161514131211109 8

'QAINTERTYPE

HESJ J

|
Lt

0
b1t

6 5

lapg| vAXBI

4 3

{NODE D]

SES

INIT-

BROKE-

STS
-

“NRST-

UWP-

HEIEd |

SEIE-

MKV86-2044

Figure A-10 VAXBI Control and Status Register

- Table A-2 VAXBI Control and Status Reglster Bit Defimtlons

Bit
.

| Descnptnon |

<31:24>

VAXBI INTERFACE REVISION (RO) - Indlcates revision level of the BIIC chlp.'

<23:16>

VAXBI INTERFACE TYPE (RO)
- Indicates the type of devxce that prov1des the prlmary

interface to the VAXBI (always 00000001).

| <1’5>'
|

<14>
*

HARD ERROR SUMMARY (RO) - Indlcates that one or more of the hard error bitsin

the Bus Error Reglster are set.

SOFT ERROR SUMMARY (RO) Indicates that one or more of the soft error bitsiIn the

Bus Error Register are set.

<13>

INIT - This bit is not used.

<12>

S
_

<ll>

BROKE (WIC DCLOS) ~ Self-test failure. Adapterv will clear this bit when both the

BIIC’s internal self-test and the port S self-test passes. The port will do a self-test on power |
- up only
o
|
|
B
-

SELF TEST STATUS (R/W, DCLOC) This bit will be a “1” 1f the BIIC’s internal self-

- test passes. This bit enables thc BIIC’s BIdrivers, and, therefore, a chip that fails self-test
will be unable to drive the BI. If the node has a reset STS bit, then a WRITE that sets this
bit will receive a NOACK response. Because the node’s VAXBI driver is disabled, the
. WRITE must be either a loopback or a VAXBI mternode transactlon
|

) Table A-2

VAXBI Control and Status Reglster Blt Defimtlons (Cont)

Descnptlon |

Bit

o NODE RESET (SC) ertmg a “1” to this bit location forces the initiation ofa complete

<10>

‘node self-test. When this bitis written as a “1”, the self-test status (STS) bit must also be
- written as a ““1” to ensure proper operatlon of the WRITE-type transaction. READs to this
~ bit will always return a “0”. The BIIC asserts the BCI DC LO L line following the setting of
‘the NRST bit. When BCI DC LO L lineis deasserted, the BIIC begins its self-test. This will

also cause the CIBCA to reload self-test code from the EEPROM into the control store and
the CIBCA self-test will commence.

| <09>

Must be Zero.

UNLOCK WRITE PENDING (WlC DCLOC SC) - Indlcates that a successful IRCI

transaction has been completed by the master port interface at this node and there has not
been a subsequent UMWCI command. This bitis cleared by a UMWCI transaction thatis
- completed successfully by the master port interface. If a UWMCI transaction is attempted
by the master port interface when the UWP bit is not set, the ISE bit in the Bus Error
Register will be set.

<O7>

HARD ERROR INTERRUPT ENABLE (R/W DCLOC, STOPC) - Enables an error

interrupt to be generated by the VAXBI node when HESis asserted. This b1t should be “0”
for the CIBCA.

<06>

SOPT ERROR INTERRUPT ENABLE (R/W, DCLOC STOPC [VMSL)) - This 'bit

‘determines whether an error interrupt will be generated by this node when SESis asserted.

- VMS can set this bit to allow an 1nterruptto be generated by this node when a soft error is

o _fidetected VMS must load the vector in the Error Interrupt Control Register if it sets thlS bit.
<05:04>

ARBITRATION (R/ W DCLOC) -Two arbitration control bits determme the mode of

o arbltratlon to be used by the interface.

1 O

00
01

10
11

Arbitration Mode-

|
Dual Round Robm
" Fixed High Priority (Reserved)
Fixed Low Priority (Reserved)
Dlsable Arbitration (Reserved)

'VAXBI NODE ID (RO DMW, DCLOL) - Indlcates thlS node ID which is formed by
~ backplanejumpers on pins B9, B10, B11, and B12 on theBI backplane. This informationis

_loaded from BCI I <3:0> H lines durmg the last cyclein which BCI DC LOis asserted.

A-10

A.43 Bus Error Register (BER) (W1C, DCLOC) OFFSET 0008
The Bus Error Register provides bus error status information resulting from VAXBI bus or mternal
loopback transactlons Figure A-11 illustrates the reglster format. The bit a531gnments are describedin
”TableA3

NOTE

Unless otherwise noted, all BER bits can be set
~during VAXBI and loopback transactions. Bits
~

<30:16>-are hard error bits, and bits <2:0> are soft

- error bits. Bit <3>, user parity enable (UPEN), is
not an error bit. It indicates the BIIC parity mode.

HARD ERROR BITS

31302928272625242322 2120191817 1615

CTE
- MPE4

|
1|

|
TDF-

IVE-

|
N

SOFT ERROR BITS |
|

CRDNPE-

CPE-

SPEJ- g

RDSd

“RTO-

STOJ

BTONEX-

| ICEJ

Figure A-11

Bus Error Register

CA-11

MKV86-2045

Table A-3 Bus Error Register Bit Definitions
- Bit

o Description

<31>

Will be zero.

<30>

NO ACK to MULTI RESPONDER COMMAND RECEIVED (WIC, DCLOC) — This
bit will be set if the master receives a NO ACK command response for an INVAL, STOP,

~INTR, IPINTR, BDCST, or RESERVED COMMAND.

<29>

<28>

MASTER TRANSMIT CHECK, ERROR - Durlng cycles of ‘a transaction m which the

master is the only source of data on the BI D, I, and P lines, the BIIC verifies that the
master’s transmitted data matches the received data from the BI. If the transmitted data
does not match the received data, this bitis set. This checkis not performed for the master’s
assertion of its encoded ID on the I lines during the embedded ARB cycle. When this bit
sets, the MSEin the Port Status Reglster also sets, causmg the port to initiate an mterrupt
- CONTROL TRANSMIT ERROR

- Thrs b1tis not used by the CIBCA

MASTER PARITY ERROR This b1tis set if the master detects a parlty error on the bus

during a data cycle of a transaction that has an ACK confirmation on the CNF <2:0> lines.
-~ When this bit sets, the MSEin the Port Status Reglster also sets, causing the port to initiate
an mterrupt

<26>

| INTERLOCK SEQUENCE ERROR Not used by the CIBCA
| TRANSMITTER DURING FAULT - ‘Not used ’by the CIBCA

<24>

IDENT VECTOR ERROR
- This bitis set if an ACK response is not received from the
master. When this bit sets, the MSEin the Port Status Register also sets, causing the port to
| ‘Initiate an mterrupt

<23>

' COMMAND PARITY ERROR }- Not used by the CIBCA.

<22> |

| SLAVE PARITY ERROR
- This bit is set by the selected slave if the BIIC detects a parity

‘error during a data cycle of a WRITE-type transaction. The BIIC suppresses all parity error
checkmg during data cycles that do not have an ACK confirmation on the CNF lines. This
assures that the BIIC will not check parity during data cycles that have undefined data, such
as STALLed data cycles. When this bit sets, the MSEin the Port Status Register also sets,
causing the port to initiate an mterrupt

<21>

READ DATA SUBSTITUTE This bitis set 1f a read data substitute (RDS) or reserved
status code is received during a READ-type or IDENT (for vector status) transaction. In
order for this bit to be set the BIIC logic also requires a successful parity check for the data
cycle that contains the RDS code. This bit will be set even if the transaction is aborted some
time after the receipt of the RDS or reserved status code. When this bit sets, the MSEin the
Port Status Reglster also sets, causmg the port to 1mt1ate an interrupt.

<20>

- RETRY TIMEOUT This bit is set if the master receives 4096 consecutive RETRY |
responses from the selected slave for the same master port transaction. When this bit sets,
the MSE in the Port Status Register also sets, causing the port to initiate an interrupt.

A-12

Table A-3

Bit

Bus Error Register Bit Definitions (COnt)
‘ Descrlptlon

STALL TIMEOUT ThlS bit is set if the slave port asserts the STALL code on the

RS<1:0> lines for 128 consecutive cycles. When this bitis set, the MSEinthe Port Status
Register also sets, causing the port to initiate an interrupt.-

‘BUS TIMEOUT ‘This bit is set if the BIIC is unable to start at least one pending
transaction before 4096 cycles have elapsed. When this bit is set, the MSE in the Port

<]18>

Status Register also sets, causing the port to initiate an interrupt.

~ NON-EXISTENT ADDRESS — This bit is set whena NO ACK response is received for a

<17>

READ-type or WRITE-type command sent by the BIIC. This bit is set only if the master
- loopback and master parity check of the command/address cycle was successful. This bitis
not set for NO ACK responses to other commands. When this bitis set, the MSEin the
Port Status Register also sets, causing the port to 1mt1ate an 1nterrupt

- ILLEGAL CONFIRMATION ERROR - A reserved or 1llegal CNF code has been
received during a transaction in which_ the BIIC is involved. This bit can be set by either the
. master or slave node. NO ACKis not considered an illegal response for command confirma-

.' <16>

~ tion. When this bitis set, the MSEin the Port Status Register also sets, causing the port to
1n1t1ate an 1nterrupt
_<15:04’>
<03>

All zeros.

USER PARITY ENABLE (RO, DCLOC) - Thls b1t mdlcates the BIIC parity mode. A

“1” indicates the BIIC is configured for user-generated parity, while a “0” indicates the
BIIC will provide the parity generations. Thisis opposite to the polarity provided on the BCI
PO line during BI DC L, which indicates which device generates parity. On power-up, an
“H” (default) configures the BIIC for BIIC-generated parity, whereas, an “L” configures
the chip for user-generated parity. While UPEN is set, the user interface is required to

“provide parity on the BCI PO L line whenever BCI SDE L or BCI MDE L is asserted. The

CIBCA sets this bit at the end of a successful self-test but before it clears the BROKE bitin
the VAXBI Control and Status Reglster The port controller module provides parity for the

~ BIIC.

ID PARITY ERROR (WIC, DCLOC) This bitis set if a parity error is detected on the
BI I lines when the master’s encoded ID is asserted during embedded ARB cycles. All nodes
perform this parity check. This bitis not set during loopback request transactions. When
. this bitis set, it causes the BIIC to generate an mterrupt if the SEIE bit in the VAXBI
Control and Status Registeris set.

<01>

CORRECTED READ DATA (WI1C, DCLOC) ~ This bitis set if the master receives a
corrected read data status code. For this bit to be set, the BIIC logic requlres the receipt of
good parity for the data cycle that contains the CRD code. This bit is set even if the
transaction aborts after the CRD status code has been received. When this bit is set, it
causes the BIIC to generate an 1nterrupt if the SEIE b1tin the VAXBI Control andStatus
Reglsteris set.

<00>

| NULL BUS PARITY ERROR (WIC DCLOC) Odd parity is detected on the bus durmg

“the second cycle of a two-cycle sequence during which Bl NO ARB L and BI BSY L were
unasserted. When this bitis set, it causes the BIIC to generate an interrupt 1f the SEIE bitin
the BI Control and Status Registeris set.

A-13

A.4.4 Error Interrupt Control Register (EINTRCSR) OFFSET
= 000C

* The Error Interrupt Control Register controls the operation of the interrupts initiated by a BIIC detected

bus error (which sets a bitin the Bus Error Register) or by setting the FORCE bitin this register. An error
interrupt request is the logical OR of all the BER register bits with the FORCE bit and error interrupt
~enable bits set in the VAXBI Control and Status Regrster This reglster 1s set up by the software if the
SEIE bitin the VAXBI Control and Status Reglsteris set.
|

- Figure A-12 illustrates the reglster format. The bit ass-lgnments »ar“e described is Table A-4.
25242322212019

16151413

Lawzeros | | o] | | 555 lojo|]

wvector

210

|o|o

oINTRAB] | J
-

INTRC
-

SeENnT

FORCE-*'”’

~ MKV86-2046

Figure A-12 Error Interrupt Control Register |
~ Table A-4 Error Interrupt Control Reglster Blt Definitions

Bit

Descnptlon o

<31:25>

All zeros |

<24> o

INTERRUPT ABORT BIT Not used by the CIBCA

| INTERRUPT COMPLETE,BIT - Not_ used by the CIBCA.

| _ <23>

| |

‘

<22>

Zero.

21>

- Not used by the CIBCA.
PT
SENT
INTERRU

<20>

INTERRUPT FORCE
- Not used by the CIBCA.

<19:16>

LEVEL <7:4> (R/W, DCLOC) - Not used by the CIBCA.

<15:14>

- Zero.

<13:02>

,‘VECTOR (DCLOC R/W [VMSL)) - This field contains the vector used during error
|

<01:00>

’

interrupt sequences. It is transmitted when this node wins an IDENT ARB cycle on an
IDENT transactron that matches the conditionsin the Error Interrupt Control Register.

| Zero. |

A-l4

A.4.5 Interrupt Destlnatlon Register (INTRDES) (R/W,DCLOC,[VMSL]) OFFSET
= 0010

‘The Interrupt Destination Regrster indicates which nodes of the VAXBI are to be targeted by interrupt
commands. The destination is sent out during the INTR command and is monitored by all nodes to
determine whether to respond Figure A-13 1llustrates the register format. The bit a351gnments are
describedin Table A-5.

ALLZERO'S

1615

INTERRUPT DESTINATION
-

MKV86-2047

Figure A-13 .Interrupt DeStin‘ation Register

Table A-5 Interrui)t Destination 'Register Bit Definitions |
Bit

Description

- <31:16>

All zeros_.

<15:00>

INTERRUPT DESTINATION
- This field determines which node(s) on the VAXBI are
to be targeted by INTR commands sent by this node. This fieldis sent out durmg the INTR

command andis used by the destination to determine whether to respond.

Durmg an IDENT command the decoded master’s IDis compared to the destination fleld
If thereis no match, this node will not respond to the IDENT
|
|

If thereis a match the master’s decoded ID is set in the Interrupt Destination Register. The
'BIIC will then respond to the IDENT, provided that thereis an unserviced interrupt request
at that node that matches the level transmlttedin the IDENT command

A-15

A46 TP Interrupt Mask Register (IPINTRMSK) (R/ W DCLOC) OFFSET 0014

The CIBCA does not use thls reglster

1615

IP INTERRUPT MASK

]

'ALL ZERO'S

MKV86-2048

~
A. 4 7

Figure A-14 TP Interrupt Mask Register

Force Bit IPINTR/STOP Destination Reglster (IPIDR) (R/W DCLOC) OFFSET 0018

The CIBCA does not use this register.

1615

'ALL ZERO'S

< |P INTERRUPT DESTINATION
‘MKV86-2049

Figure A-15 Force Bit IPINTR‘/‘STOP; Destination Reg‘ister:,’
A48

IP Interrupt Source Reglster (IPNTRSRC) (WlC DCLOC) OFFSET 001C

- The CIBCA does not use this reglster

1615

_
ALLZERO'S

P INTERRUPT SOURCE

|
' MKV86-2050

Figure A-16 IP Interrupt Source_v-Regitster
A4, 9 ‘Starting Address Reglster

The Starting Address Reglsteris not used by the CIBCA
- A4.10

Endmg Address Register

The Ending Address Reglster is not used by the CIBCA

A-16

A4.11

BCI Control and Status Register (BCICSR) OFFSET
= 0028

The BCI Control and Status Register enables various functions between the BIIC chip and the user’s port
to occur. Figure A-17 illustrates the register format. The b1t assignments are describedin Table A-6.

1817161514131211109 876 54
32

ALLZERO'S

| |

B I

Y B

A [ 1 Fo] [0

BURSTENJ J 1
HNNTR

MSEN-

BDCSTEN-

- STOPENA
|
RSVDENIDENTEN
-

INVALEN
WINVALEN'UCSRENS |
BICSRENS

INTREN-

IPINTREN--

|
|

PNXTEN-

RTOEV
-

MKV86-2051

Figure A-17 BCI Control rand ;StatusRegvister

;Table A-6 BCI Control and Status Regrster Bit Defimtlons
Bit

| Descnptlon

<31:1_8>'

» <1‘7>

" All ZEr0S.
BURST ENABLE - When set, this bit causes BI NO ARB L to be asserted continuously

~ after the next successful ARB by this node, until the BURSTEN bitis reset or BCI MAB L

is asserted. The assertion of BI MAB L does not reset the BURSTEN bit. It merely clears
the burst mode state in the BIIC, which is holding BI NO ARB L. Unless a subsequent
transaction clears this bit, the next successful ARB by this node will cause the BIIC to once
again hold BI NO ARB L continuously. Only BI requests may be used in burst mode.
Loopback requests must not be used. The CIBCA clears thlS b1t If this bltis set, the action
of the CIBCAis undefined.

| <‘16>’

IP INTERRUPT/ STOP FORCE (R/ W DCLOC) When set, this brt causes the BIIC to
arbitrate for the bus and transmit an IPINTR or STOP command. The command transmitted depends on the command storedin the Force Bit IPINTR/STOP Command Register,
using the Force Bit IPINTR/STOP Destination Register for the destination field. The
IPINTR/STOP Force Bit is reset by the BIIC following the transmission of an IPINTR

~ transaction. If the transmission fails, the NICIPS (NO ACK or illegal CNF received for

Force Bit INTR/STOP command) EV codeis output and the NMR (NO ACK to Mul- |

tiresponder Command Received) bitis set. The CIBCA clears this b1t If this bitis set, the
actlon of the CIBCA1S undefined

A-17

Table A-6 BCI‘Control and Status Register. B’it Definitions (COflt)
Bit
,<_15>

Description
|

~ MULTICAST SPACE ENABLE (R/W DCLOC)- The CIBCA clears this bit. If this bit

SRR

set the actlon of the CIBCAis undefmed

BROADCAST ENABLE The BI BROADCAST command dlrected at the CIBCA is

<14>

"NO ACKED The CIBCA clears thls bit. If this bit is set, the actlon of the CIBCA is
|

undefined

STOP ENABLE When set, thlS bit causes the BIIC to assert SEL and the appropriate

<13>

- SC<2:0> code following the receipt of a STOP command directed at this node. The CIBCA
sets this bit at the end of' self-teSt and before the green light comes ON.

RESERVED ENABLE When set, the BIIC asserts SEL and the appropriate SC<2:0>

<l12>

code following the recelpt of a RESERVED command code. The CIBCA clears this bit.
The CIBCA NO ACKs RESERVED commands that are recerved even 1f the bitiis set.

IDENT ENABLE The CIBCA clears this bit. If this bitis set, the actlon of the CIBCA1S

T <]ll>

undefined
<10>

| INVALIDATE ENABLE The CIBCA clears this bit. The CIBCA NO ACKs INVALIDATE commands that are received. If this bitis set, the actlon of the CIBCAis undefined.

<09>' '~

WRITE INVALIDATE ENABLE The CIBCA clears this b1t 1If this b1t1S set, the action
of the CIBCAis undefined.

USER INTERFACE CSR SPACE ENABLE. When set, this bit causes the BIIC to

. <08>

assert SEL and the appropriate SC<2:0> code following the receipt of a READ or WRITE

type command directed at this node’s User CSR space. The CIBCA sets this bit at the end

of a successful self-test just after the green light comes ON to allow access to the port’s
User CSR space.

<07>

ASBIIC CSR SPACE ENABLE The CIBCA clears thlS bit.

"<06;.

| 'INTERRUPT ENABLE ‘The CIBCA clears this b1t If thls bitis set, the action of the
CIBCA is undefined The CIBCA returns NO ACKs to BI INTERRUPT commands

IP INTERRUPT ENABLE The CIBCA does not respond to IP INTR commands If thls

bitis set, the action of the CIBCAis undefmed

<0d>
__<o3>'

PIPELINE NEXT ENABLE The CIBCA clears th1s b1t If thlS bit iis set, the actlon of

'the CIBCA iis undefmed

RTO EV ENABLE The CIBCA sets this bit at the end ofa successful self-test, but before

it clears the BROKE bitin the VAXBI Control and Status Reglster If this b1tis cleared,

| theaction of the CIBCAis undefined

'<02:OO> - | Zero.

A-18

A.4.12 Write Status Reglster (WSTAT) OFFSET
= 002C

The CIBCA does not use this register.

|
|
. ALLZERO'S

_,3’1302928_27
I .
oo

| GPR3:l ; ’
GPR2-

GPR1-

- GPROMKV86-2052

| ‘Figure A-18 Write Status Register

A.4.13 User Interface Interrupt Control Register (UINTRCSR) OFFSET = 0040

" The User Interface Interrupt Control Register controls the operation of interrupts initiated by the user
" interface. Interrupts may be initiated by either the assertion of any of the BCI INT <7:4> L lines or by

setting any of the force bits in this reglster Figure A-19 1llustrates the reglster format The bit assignments

2827

2423

2019

wtRag ||

are descnbedin Table A-7

16151413
o] ~

210

VvecToR

|o]o|

INTR
CMPLT
<7:4> ~—

INTR
CSENT

<7:4>-

INTR
FORCE
<7:4>d

EXVEC—

|
MKV‘86-2053

Figure A-I9 Usér_' Interface ‘In‘terrl‘l\pt COntrol;, Register

A-19

~ »_ Table A-7
- Bit

<31:28>

<27:24>

User Interface Interrupt Control Register Bit Definitions
|

Descnptron

INTERRUPT ABORT <7:4> (WIC DCLOC) ~ There are four 1nterrupt abort bits
corresponding to the four tvnterrupt levels An interrupt abort bitis set if an INTR command
sent under the control of this register is aborted. INTRABis a status bit set by the BIIC and
- can be reset only by the user interface. The bit has no effect on the ability of the BIIC to
- send or respond to further INTR or IDENT transacttons
,.
INTERRUPT COMPLETE <7:4> (W1C, DCLOC)
- There are four mterrupt complete
bits corresponding to the four interrupt levels. An interrupt complete bit is set when the
vector for an interrupt has been successfully transmitted, or if an INTR command sent

under the control of this register is aborted. Removal of the interrupt request clears the
corresponding INTRC bit. While an INTR bitis set, no further interrupts at that level are
generated by this register. Further, no IDENTS will be responded to by this register when
the INTRC bitis set at the IDENT level.

| f '<23:2O>_.V

INTERRUPT SENT <7: 4> (W1C, DCLOC STOPC)There are four mterruptsent b1ts |
corresponding to the four interrupt levels. When asserted, an INTR SENT bit indicates that
~an INTR command for the corresponding level has been successfully transmitted. This bitis
cleared during an IDENT command following the detection of a level and master ID match.
Clearing the bit allows the interrupt to be resent if this node loses the IDENT arbitration, or
if the node wins but the vector transmission fails. Deassertion of an interrupt request causes
the appropriate INTR SENT bit to be cleared.

Itis not necessary for the INTR SENT bit at a glven level to be set in order for the BIIC to
respond to an IDENT at that level All that is required is that the mterrupt request be
posted at the IDENT level.
-

<19:16>

INTERRUPT FORCE <7: 4> (R/W, DCLOC STOPC) - There are four FORCE bits

- corresponding to the four interrupt levels. Setting a FORCE bitis equlvalent to asserting
the corresponding BCI INT<7 4> L input.
- When multlple mterrupt requests are asserted sxmultaneously, the BIIC transmlts INTR

commands for the highest priority requests first. Similarly, when an IDENT command

'solicits more than one level, the BIIC responds with the highest pending level.

CIBCA diagnostics may use the FORCE bits to cause the CIBCA to generate mterrupt‘
- commands onto the VAXBI.
.r
|
|
-

<15>

- EXTERNAL VECTOR (R/W, DCLOC) - The CIBCA does not support the external

vector mode. If the external vector bitis set, the action of the CIBCAis undefined.

Zero.
<13:02>

VECTOR (R/W DCLOC [VMSL]) - This field contains the vector used durmg user
interface mterrupt sequences (unless the external vector bitis set). The vector is transmitted
when this node wins an IDENT ARB that matches the conditions in the User Interface'
~ Interrupt Control Register.

The vector must be loaded by software prlor to enablmg mterrupts The interrupt level

utlllzed by the CIBCA iis Level 4.

<01:00>

Zero. .

A-20

A.4.14
|

Port Queue Block Base Register (PQBBR) (R/W,DCLOC,[SC]) OFFSET
= 00F0

The Port Queue Block Base Register contains the physical address of the base for the port queue blockin
b1ts <28:09>. All other bits must be zero.

.The PQBBRis READ/WRITE by the port drlver and ean be written only when'theport is in the dlsabled |
~

or disabled/maintenance state. Its value before being written is unpredictable. Figure A-20 1llustrates the
register format.

I-:Mez

PQB BASE <28:09>

MmBZ

]

MKV86-2054

|
- A4.15
-

Figure A-20 Port Queue Block Base Register |

Port Fallmg Address Regrster (PFAR) (R/W, DCLOC,[SC]) OF FSET 00F4

For DSE interrupts the PFAR contains the virtual address or structure. For MSE 1nterrupts and buffer

memory system errors, the PFAR contains a physical address

The PFAR is READ ONLY by the port dnver and vahd after a DSE or MSE interrupt, or after a
response wrth buffer memory system error status. Flgure A-21 1llustrates the reglster format.

FAILING ADDRESS

)

]

MKV86-2055 |
~ Figure A-21

Port Failing Address Register

A-21

,A 4.16

Port Parameter Register (PPR) (R/W DCLOC,[SC]) OFFSET 00F8

The Port Parameter Register contains port implementation parameters and the port number. The PPRis
set up by microcode during the port initialization process. It is validin any state except the uninitialized

state. The PPR is READ ONLY. Writing to this register destroys the port state with unpredictable
results Frgure A-22 1llustrates the reglster format The bit assignments are descrlbedin Table A-8.

_313029282726252423222120191817161514131211109 87654321 O,

| J

cszz]'
L12ERREE
"

XHDR

EEREE

| |
cszo-

4 | |
stot
SLOT

sLoT< |

L10-

o8-

PNO6B

PNos-

|
PNO3-

oad

PNO1

Ry
T

LO3 Lo2d

PNOO-

14 |
o<
A

Figure A-22 Port Parameter Register

A-22

MKV86-ZQ56

Table A-8 P_ort Parameter Register Bit Definitions
Bit

Descnptlon

. <31:29>

CLUSTER SIZE <02: 00> This f1eld 1nd1cates the maxrmum number of nodes allowed

on the CI as follows

csz

<28:16>

0
0

O
1

16 Max)
32Max)

0-15
0-31

64 (Max)

0-63

0
1

1
X

(decnmal)

128 (Max) - 0-127
Reserved
S

LENGTH <12: 00> Thrs fleld 1nd1cates the size of the internal buffers avallable for o

) FF8 (hex) or [4088 (dec)]

,Reserved and read as zero.

<11>

~ (decimal)

message and data transfers. 4 Kbyte buffers are utilized, therefore this fieldis preset to

- <15:13>

<12>

" Cluster Size Range

DISABLE ARBITRATION When this bit is set, defeats the normal arbitration |

sequence and allows the LINK to transmit after wa1t1ng only one basic quiet slot (Delta
time).
.
-

o ,'EXTENDED HEADER When this bitis set, allows the LINK to extend the number
~of bit synchronous charactersin the header

}<110:08_'> ~
o

slot Delta time as follows:

-0
1

<O7:OO>

ALTER DELTA TIME <01:00> - These three bits force the LINK to a specrfrc quiet

."ADT<2> ADT<1> ADT<‘0>I -

QUIET SLOT COUNT (in decimal)

32
Illegal

PORT NUMBER <07:00>- This f1eld indicates the CI node number of thlS port

A-23

A 4. 17 Port Error Status Reglster (PESR) (R/ W DCLOC [SC]) OFFSET 00FC

" The PESR indicates the type of error which resulted in a data structure error (PSR__DSE) interrupt.
PESRis READ ONLY by the port drlver and valid after a Port Status RCngtCl‘ DSE mterrupt Figure
A-23 illustrates the reglster format.

32 10
31302928 272625242322 2120191817161514 131211109 8 7 6 54

EC31 :]

EC30 -

—
EC29
ec28—

EC27 --,

—
EC26

—
EC25

EC24-

|
EC23“EC21 —

EC20
—

- EC19-

EC1 8 - EC17-—

EC16EC15—

EC14-

EC13ECc12" EC11—-

|
ecoo~ Ecos- ECO07 ECO6 —

ECO5
—

ECO3 —
EC02—
ECO1-

ECO0—
‘MKV86-2057

~ Figure A-23 Port Error Status Register

A-24

Port Status Regrster (PSR) OFFSET = 1000

A4IS

The PSR returns status to the port driver after an interrupt. When an mterrupt is requested by the port.

these bits are fixed and are not changed until the port dl’lVCl‘ releases the register by writing the PSRCR
“with a

6‘1,,

.,_The PSRis READ ONLY by the port drlver andis vahd only after an mterrupt and before writing the o
PSRCR with a “1”. A WRITE operation to the PSR can cause false interrupt indications to the port

- driver. Figure A-24 illustrates the register format. The bit assignments are describedin Table A-9.

_161514131211109 8

MUST BE ZERO

76 6 4 32 10

|o|o|o]o]

NRSPEJ

UNINS

MTEL |
MIscH
SE/MEMSE-

DSE—
PIC—

PDC-

MFQE—|

RQAMKV86-2058

- Figure A-24 Port Status Register

Table A-9

Port Status Register Bit D‘efinitions |

Bit

" Description

'“<f3_1:16>’_2 | ‘_'Must be zero
<15>

NO RESPONSE ERROR (DCLOC STAC RO). When this bitis set, 1nd1cates that one
or more of the followmg 1n the PSR is set: UNIN MTE MISC SE, MSE, DSE, PIC,

C<l4:1>

- <10>

PDC, MFQE

Reserved and read as zero

VUNINITIALIZED (DCLOC RO [STAS]) -~ When thlS blt is set, the port is in the

~uninitialized state. The port does not respond to CI traffic. MTE also sets this bit. ‘The
| ummtlahzed state is exited by writing a “l”in the PICR or by a boot tlmeout |
|

- <09>

- MAINTENANCE INTERRUPT FLAG (DCLOC RE, [STAC]) - When MIF=1, an

interrupt-causing condition has occurred in the port. MIF is used with MIE to allow a

diagnostic program to operate the port with interrupts dlsabled MIF 1nd1cates to the |
program that the PSRis vahd ertmg thlS blt has no effect

‘Table A-9 Port Status R'egister Bit Definitions (Cont)
Bit

Descnptlon

<08>

MAINTENANCE ERROR (DCLOC, STAC, RO) — When this bit is set, the port has

~ detected an internal hardware failure. The exact error can be determined by readmg the
PMCSR. When MTEis set, the port enters the uninitialized state. The microcodeis halted
and the port is no longer functional (except for BI slave transactions). An mterrupt is
generated and hardware error flags|remam vahd

N MTE can be set as a result of any panty error flags set in the PMCSR

An MTE can occur at any time. If MTE occurs after the port has mterrupted from another

flag, a new interrupt is generated by the port after the PSRCRis written for the previous
interrupt. After the MTE is serviced, writing the PSRCR clears the interrupt but not the
error flags that caused MTE. When this bit sets, the NRSPE bit also sets.

MISCELLANEOUS ERROR DETECTED (DCLOC, STAC, RO)- When this bitis set,

<07>

informs the port driver that the microcode has detected one of the miscellaneous errors and
is about to enter the disabled or disabled/maintenance state. An interrupt is generated
When this bit sets, the PSR_NRSPE bit also sets. Additional 1nformat10n is availablein

5the PESR

SANITY TIMER EXPIRATION (DCLOC STAC, RO) - When this bit is set, the

_maintenance sanity timer or boot timer has expired and theport has entered the uninitial-

~ ized/maintenance state. When this bit sets, the PSR.__NRSPE bit also sets. This bitis also
,

'referred to as the ME bit.

~ MEMORY SYSTEM ERROR (DCLOC, STAC RO) - ThlS bit sets whenever one of thel
‘hardware error bitsin the Bus Error Registeris set. When this bit sets, the NRSPE bit also
sets. The port 1s in the disabled or disabled/maintenance state when MSEis set.

DATA STRUCTURE ERROR (DCLOC, STAC, RO) When this bitis set, the port has
- encountered an error in a port data structure (thatis; queue entry, PQB BDT, page table,
“values out of range, or MBZ bits that are not zero). The port is in the dlsabled or

<04>

| dlsabled/ mamtenance state. When this bit sets, the NRSPE bit also sets.

<03>

‘PORT INITIALIZATION COMPLETE (DCLOC STAC RO) When this bitis set the

<02>

PORT DISABLE COMPLETE (DCLOC, STAC, RO) - When thlS bitis set, the port is

port has completed internal initialization. The port is in the disabled or disabled/maintenance state. The local store, virtual circuit descrrptor table, and the port’s
internal data structures are initialized. When this bit sets, the NRSPE bit also sets.
disabled. It ceases processing the command queues and does not respond to incoming CI
transmissions, except maintenance class, if enabled. The port is in the disabled or disabled/ mamtenance state. When this b1t sets, the NRSPE bit also sets.

»MESSAGE FREE QUEUE EMPTY (DCLOC STAC RO) -~ When this bit is set the

<0l>

- port attempted to remove an entry from the message free queue and found it empty. Port
processing of commands continues and, therefore, the message free queue may not be
empty at the time the interrupt service routine gets control. An 1nterrupt is posted When

this bit sets, the NRSPE bitalso sets.
|

' RESPONSE QUEUE AVAILABLE (DCLOC STAC, RO)-‘When this bitis set, the port
has mserted an entry on an empty response queue. An mterrupt is posted

A-26

A.4.‘19' Port Maintenance Ccntrol/Status' Register (PMCSR) OFFSET = 1004

Figure A-25 illustrates the register format. The bit assignments are described in Table A-10.

161514131211109 8 76 54 32

DON'T CARE

I O

1 0

lofof

- ‘BCIPE—

'CSPE
IBPE—4

XMPE—-

cre—

- MBIE~J
. )/’-\\\

IPE—
BTO—

HAL'r—J

"MIE~
- WP-—
~ MTD—
STARTH

" MKV86-2059

- Figure A-25‘ Port Maintenance ContrOl/Status RegiSter' |
Table A-10

- Port Maintenance Control/Status Register Bit Definitions

Bit

Description

<31:16>

Don’t care |

- <15>

BCI PARITY ERROR (DCLOC STAC RO) ‘This bitis set when a VAXBI or a BCI

parity error occurs during a master transaction initiated by the CIBCA When this b1tis set,
~the Port Status Register MTE bit also sets.

<l4>

- <13>

CONTROL STORE PARITY ERROR (DCLOC, STAC, RO)- Th1s b1t sets when a
parity error is detected in the control store RAM. CSPE can only be set when the
microcodeis executing. CSPEis inhibited from setting when the control store is READin
the uninitialized state (thatis, a valid console or macrocode access) The MTE bitin the
Port Status Reglsteris set when this bitis set.

INTERNAL BUS PARITY ERROR (DCLOC STAC, RO) This bit sets when a panty

‘error is detected on the internal bus on unsolicited WRITEs to an IB destination (including

control store or on READs when the local store or VCDTis the IB source). The READs

apply to both a microcode specnfied READ as well as to an unsolicited READ. The MTE
“bitin the Port Status Registeris set when this bitis set.

<12> ,

- TRANSMIT BUFFER PARITY ERROR (DCLOC STAC, RO) ‘When thls bitis set
~indicates that a parity error was detected while the link was unloadmg a transmit buffer.
- The current CI transmission is aborted. The circuit that detects XMPEis located on the link
| rnodule The MTE b1tin the Port Status Reglsteris set when thlS b1tis set.

A-27

Table A-10

Port Maintenance Contro-l/Status Register Bit Definitions (‘Cont)

Bit

) ‘Description

<11>

CILP PARITY ERROR (DCLOC, STAC, RO) - This bit is set when a parity error is
detected on the CILP bus or when a parity mismatch occurs on the IB data when the source
is the CILP bus. A CPE results in the setting of the PSR_MTE via microcode. The

assertion of the PSR__MTE via microcode allows the relevant status to be saved.
<10>

MAP BCI/BI ERROR (DCLOC, STAC, RO) - This bit is set when the BIIC EV error

code is detected while the CIBCA is doing a MAP transaction. When this bit is set, the Port
Status Register MTE bit also sets..

- <09>

II PARITY ERROR (DCLOC, STAC, RO) - This bit is set when a parity error is detected

<08>

BI BUS TIMEOUT (DCLOC, STAC, RO) - This bit is set when BTO L is asserted. It can

<07>

on a READ over the II bus. When this bit is set, the Port Status Register MTE bit also sets.

be used by the microcode to recover from a bus timeout.

| HALT SEQUENCER (R/W, DCLOC,V STOPS, STAC)‘ - When this bit is set, the

~ sequencer halts which allows the loading of the control store RAM. In the case of the STOP
‘command, HALT prevents the port from initiating any BI traffic. When this bit is cleared,
the sequencer continues unless a power-up sequence is in progress. If HALT is set as a
consequence of the BI STOP command, the result of a continuation is unpredictable. The

-- ~ actual loading sequence should be:

Set the HALT bit

Load the microcode

- ¢. WRITE the START bit,“wh'i»ch causes the micfoprocesS_Or to_start'running.
<06>

<05>
<04>

Reserved and read as zero.

MAINTENANCE INTERRUPT ENABLE (R/W, DCLOC, STAC) - When this bit is

set, enables interrupts.

WRONG PARITY (R/W, DCLOC, STAC) - When this bit is set, the parity

checker/generator on the internal bus of the port controller checks/generates even rather
“than odd parity. When this bit is set, the Port Status Register MTE does not halt the
microsequencer. -

'<-O3:0”2>
<01>

- Reserved and read as zero.

the boot ‘
MAINTENANCE TIMER DISABLE (R/W, DCLOC, STAC) - When MTD=1,MTD=0,

and maintenance sanity timers are disabled and cannot cause an interrupt. When
the timers are enabled and the PMTCR must be periodically written by the port driver to
prevent the port from entering the uninitialized/maintenance state and generating an SE

-~ interrupt.
<00>

START (SC) - When this bit is set, an initialize signal is generated-fhat clears all port éri'ors

except for the error bits internal in the CIBCA. This leaves the port in the uninitialized
state. START is WRITE ONLY and cleared on power-up and at the end of the clear pulse
generated by setting START. START always reads as “0” and writing a “0” has no effect.

A-28

AA4. 20

Maintenance Address Reglster (MADR) OFFSET = 1008

The Maintenance Address Registeris utilized for reading/writing the control store or the EEPROM. To |
READ or WRITE a particular locationin either the control store or the EEPROM the MADR has to be
loaded with that particular location.
|
|

- The control store is orgamzed as 4K by 48 bits when used by the port sequencer When the control store is

accessed from the BI, it is organized as 12K by 16 bits. When accessmg the EEPROM from the BI, the
EEPROMis organized as 8K by 8 b1ts

The MADR is WRITE ONLY when the port is in the ummtlahzed state and the MADRis not cleared by

START.

The MADR is 1ncremented automatxcally at the end of a MDATR WRITE but not at the end of a

- MDATR READ.

At the end of a WRITE to the control store, the MADR increments to point to the next 16- blt section.
This means that MADR address bits <12:00> are incremented only at the end of a WRITE to control
store bits <47:32> and that MADR address bits <A15:A14> are incremented at the end of each WRITE
to a control store section. A sectlon of the control store can be elther b1ts <47:32>, <31: 16> or <15:00>.

At the end of a WRITE to the EEPROM the MADR b1ts <13 OO> are mcremented however MADR |
bits <15:14> remain unchanged

| The mcrementmg of the MADR at the end of each WRITE to either the control store or to the EEPROM

-allows for sequential WRITEs to the MDATR without having to update the MADR. The MADRis not

1ncremented at the end of a READ of either the control store or the EEPROM

When the port is not in the uninitialized state, a READ returns undefined data and a WRITE has no

effect. Figure A-26 illustrates the register format. The bit assignments are described in Table A-11. Figure
A-271s a map of the control strore.
|
-

DON'T CARE

161514131211109 8 7 6 5 4 3210
o

A4
A13—

- A12—
Al1—
A10—

“A09—

AO8 —

AO7
—
AOB —

AO5—

AO4—

AO3—
A02 —
AO1 —

AOQ
—
MKV86-2060

Figure A-26 Maintenance Address Register
A-29

Table A-11

Mamtenance Address Reglster Blt Defimtlons

Bit

Descnptlon

<3l:16>" |

Don’t"c'are'"

<15:14>

‘Thls field selects bits of control store or EEPROM as follows:

CAIS
0

A14
0

_Selects Bnts
’<1500> of the control store

-0

<31:16> of the control store

'<47:32> of the control store

<07:00> of the EEPROM

| . <13> o _ R‘eservedl

| |

.The meaning of these bits depends on the value Of‘address bits <A15'A14> as f0110wsfi

- <12:00>

Wlth address bltS <A15Al4> equal to 00 Ol or 10 and <A12> equal to zero:

All

Al10

0
|

Bank Selected

000-3FF
400-7FF

800-BFF

COO—FFF

<A09 AQ00> select the word w1th1n the 1K bank.

~ With address bits <AlS: Ald> equal to 11 <A12 A00> select the location (byte) within

. the 8K EEPROM

A-30

A<15:14>=.
-V

V--=11

=10

=01 )

=00

A<12:00>—

EEPROM MAP
MKV86-2061

| Figure A-27

Control Store Map

A-31

A.4.21 Maintenance Data Reglster (MDATR) (R/ W) OFFSET= 100C
When writing the Maintenance Data Register, the datais written into the address specified by the MADR
~ (which can be a locationin the control store or a locationin the EEPROM) The upper 16 bits <31:16> of

the MDATR must be zero. At the end of the WRITE, the MADRis 1ncremented to pomt to the next
section/location.

When readmg the MDATR, the datais READ fromthe address specified by the MADR (which can be a
locationin the control store or a locationin the EEPROM) The upper 16 bits are “don’t care””. At the end
of the READ, the MADRis not incremented.

The MDATRis only vahd when the port is in the ummtrahzed state with HALTin the PMCSR set. When

the port is not in the uninitialized state, a READ returns undefined data and a WRITE has no effect.
Figure A 28 illustrates the register format

MUST BE ZERO

161514131211109 8 76
|

54 32 10

’

015-[

‘D14D13~

D12D11~

D104

D09

DO8—
D07

Do6= |
DO5 —
D04
—

DO3
—
D02
- DO1 -

poo-—

MKV86-2062

Figure A-28 Maintenance Data Register |

CA-32

A4, 22 Port Command Queue 0 Control Reglster (PCQOCR) OFFSET
= 1010
661,.9 :
m
When the port driver inserts an entry in an empty Command Queue 0, the port driver WRITES a
the PCQOCR to initiate port processing of the command queue. The PCQOCRis ignored if the port is in
~ the ummtrahzed uninitialized/maintenance, dlsabled or dtsabled/ maintenance state

The PCQOCR is WRITE ONLY. Readmg this regrster returns undefined data Wrttmg a “O” has no
effect. Figure A-29 illustrates the register format

| | DON'T CARE

1615
_

MUST BE,ZERO\ S

coocJ

MKV86-2063

Figure A-29 Port Command Queue 0 Control Register
A4.23 Port Command Queue 1 Control Reglster (PCQI1CR) OFFSET
= 1014

‘When the port driver inserts an entry in an empty Command Queue 1, the port driver WRITEs a

.
661”

the PCQICR to initiate port processingof the command queue. The PCQICRis ignored if the port is 1n

- the uninitialized, ummtlahzed/ maintenance, disabled, or dtsabled/ mamtenance state.

ThePCQICR is WRITE ONLY Readmg this regtster returns undefmed data Wrttmg a “0” has no, ~
effect. Figure A-30 illustrates the register format

3 i}

L ~

—

DONTCARE

1615

MUSTBEZERO
.

‘Figure A-30

Port Command Queue 1 Control Register

A-33

co1cJ_

MKV86-2064

A4, 24 Port Command Queue 2 Control Register (PCQZCR) OFFSET =1018

When the port driverinserts an entry in an empty Command Queue 2, the port driver WRITES a“l”in
the PCQ2CR to initiate port processing of the command queue. The PCQ2CRis ignored if the port is in
the ummtlahzed ummtlahzed/ mamtenance dlsabled or dlsabled/ maintenance state |

(

The PCQ2CR is WRITE ONLY. Readmg this register returns undefined data. Wrrtmg a “0” has no

her3
-

- effect. Frgure A-31 illustrates the register format.

DON'T CARE

1e15

T
BE ZERO
MUS

- CC).ZCJ

MKV86-2065

Figure A-31

Port Command Queue 2 Control Register

= 101C
A.4. 25 Port Command Queue 3 Control Register (PCQBCR) OFFSET
in
port driver WRITEs a “1”
the
3,
Queue
Command
When the port driver inserts an entry in an empty
in
is
port
the
if
ignored
s
PCQ3CRi
The
queue.
the PCQ3CR to initiate port processing of the command

the ummtrahzed ummtrahzed/mamtenance dlsabled or disabled/ rnamtenance state.

Readmg thrs regrster returns| undefrned| data) Wrrtmg a “0” has no
The PCQ3CR is WRITE ONLY
the regrster format.

effect Frgure A-32 illustrates
o

DONTCARE .

_1615

MUSTBEZERO

co3cJ

MKV86-2066

Figure A-32 Port Command Queue 3 Coutrol‘Register

A-34

( b

| (

A.4.26 Port Status Release Control Reglster (PSRCR) (SC,VMSL) OFFSET= 1020
After the port driver has received an mterrupt and READ the PSR, it returns the PSR to the port by
writing a “1”in the PSRCR. The PSRis invlaid until the next interrupt is received from the port. The

- PSRCR is ignored if the port is in the uninitialized, un1n1tlahzed/mamtenance dlsabled or disabled/ mamtenance state.

‘The PSRCR is WRITE ONLY. Readmg thlS reglster returns undef"med data ertmg a “0” into this
register has no effect Figure A-33 111ustrates the reglster format

)

DONTCARE

- - T

MUSTBEZERO

| |

PSRC—[

MKV86-2067

‘Fig‘ureA-33 ,‘Port Status. Release Control Register

A. 427 Port Enable Control Reglster (PECR) (SC VMSL) OFFSET = 1024

The port driver enables the port by wr1tmg a “1”in the PECR. The PECRis WRITE ONLY and the
‘WRITEis ignored if the port is in the uninitialized, uninitialized/maintenance, enabled, or enabled/maintenance state. Reading the-PECR returns undefmed data ertmg a “0” into this register has no
o effect Flgure A-34 111ustrates the reglster format

331

.,‘

[

R_R1615“"“V =

DON'T CARE

t.”" (;_

.v'1 Q :t

MUSTBEZERO

1 |
-

PECH

MKV86-2068

Figure A-34 Port Enable Control Register

A-35

A.4.28 Port Disable Control Register (PDCR) (SC,VMSL) OFFSET= 1028

(

- The port driver enables the port by writing “1” in the PDCR When the port 1S dtsabled 1t requests an
mterrupt with the PDC bitin the PSR set.

The PDCRis WRITE ONLY andis ignored if the port is in the uninitialized, uninitialized/ mamtenance
disabled, or disabled/maintenance state. Reading the PDCR returns undefined data Wr1t1ng a “0” into
this register has no effect. Figure A- 35 illustrates the reglster format

r ~

DONTCARE

| I

MusTBEZERO

PDCJ

. (

MKV86-2069

Figure A-35

Port Disable Control Register

= 102C
'A.429 Port Initialize Control Register (PICR) (SC,VMSL) OFFSET

The port driver initializes the port by writing a “1”in the PICR. When the initializationis complete the
sets the PICbitin the PSR and requests an mterrupt The port enters the dlsabled state.
'port
:

The PICRis WRITE ONLY andis 1gnored if the port is in the dlsabled or dlsabled/ mamtenance state. If

- the PICRis written with a 1" while the port is in the enabled or enabled/ maintenance state, the port will

|
(

-go to the disabled or disabled /maintenance state with loss of processing state. Reading this register returns

undefmed data ertmg a “O” mto thlS reglster has no effect. Flgure A 36 1llustrates the register format

DONTCARE

MUST BE ZERO

PICR-J

MKV86-2070

| Figure A-36 Port Initialize Control Register

A-36

(

A.4.30 Port Datagram Free Queue Control Regrster (PDFQCR) (SC VMSL) OFFSET
= 1030

The PDFQCRis written with a “1” by the port driver when the datagram free queue 1s found to be empty' |
- at the time of a datagram free queue entry msertlon
|

The PDFQCR is WRITE ONLY and is 1gnored if the port is in the unmlttahzed uninitial-

ized/maintenance, disabled, or disabled/maintenance state. Wntmg a “0” into this register has no effect |
thure A-37 1llustrates the reglster format
|

l o

DON'TCARE

1615

MUST BE ZERO

N 1

]

| or-'oc-] |

‘MKV86-2071

Figure A-37

Port Datagram Free QueueControl Register

Ad. 31 Port Message Free Queue Control Reglster (PMFQCR) (SC VMSL) OFF SET = 1034
The PMFQCRis written with a *“1” by the port driver when the message free queue is found to be empty
~at the time of a free queue 1 entry insertion. If the message free queue is exhausted and the port has posted

an MFQE interrupt, the port W111 wait until the PMFQCR has been written before it removes a free queue B
entry..

The PMFQCR is WRITE ONLY and is 1gnored if the port is in the ummtlahzed ummtlal- ized/maintenance, disabled, or disabled/ maintenance state. Writing a “0” into this register has no effect.
Figure A-38 illustrates the register format.
|
|

~ DONTCARE

MUSTBEZERO

-~ MFacMKV86-2072

Figure A-38 Port Message Free Queue Control Register

A-37

= 0038
A.4.32 Port Maintenance Timer Control Register (PMTCR) (SC,VMSL) OFFSET
timers. The
sanity
and
boot
the
of
times
The PMTCR allows the macrocode to control the expiration
is WRITE
PMTCR
The
PMTCR.
the
into
timers are reset to their initial values when a “1” is written
Figure
effect.
no
has
register
this
into
ONLY. Reading this register returns undefined data. Writing a “0”
A-39 illustrates the register format.

~ MUST BE ZERO

DON'T CARE

[

]

MTCJ
MKV86-2073

Figure A-'39 Port Maintenance Timer Control Register
A.4.33

Sanity Timer

‘The sanity timer is implemented in microcode by branching on a hardware time base. It is reset when the
PMTCR is written with a “1”. If the macrocode fails to WRITE a *“1” in the PMTCR within 100 seconds,
~ the port will post an interrupt and enter the uninitialized/maintenance state with SE=1 in the Port Status
SR

is disabled if MTD=1 in the PMCSR.
Register. The sanity timer

4
Boot Timer
' A43

by backplane setup.
The delay time is selected

If START is set and the PMCTR is written with a “1”, the uninitialized state will be exited after }the_
preset delay unless the time was set for “0” seconds. If the jumpers were set for “0” delay, the port will

will not start.
wait 50 seconds before exiting the uninitialized state. If MTE=1 or MTD=1 the microcode

~ After the boot timer expires, the uninitialized bit in the PSR is cleared. The port then posts an interrupt
and enters the uninitialized/maintenance state with SE=1 in the PSR. The expiration time can be
is disabled if MTD=1
extended indefinitely by periodically writing a “1”” in the PMTCR. The boot timer
in the PMCSR or the port entered the uninitialized state because MTE=1 in the Port Status Register.

A.4.35 Port Maintenance Timer Expiration Control Register (PMTECR) (SC,VMSL) OFFSET =

|
»
|
D
~
103C
The port driver forces a maintenance timer expiration interrupt by writing the PMTECR. This register
may be written only when the port is in the enabled, enabled/maintenance, disabled, or dis" abled/maintenance state and only while the maintenance timer is not disabled. Figure A-40 illustrates the
s

- register format.

TSR

'MUST BE ZERO

)

MTEC-]
MKV87-1054

Figure A-40 Port Maintenance Timer »Expiration Control Register
~

A-38

Digital Equipment Corporation ¢ Bedford, MA 01730