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Document:	CI750 Hardware Technical Description
Order Number:	EK-CI750-TD
Revision:	PRE
Pages:	354
Original Filename:

OCR Text

CI1750 Hardware
|

Technical

Description
Preliminary

dlifgliltiall¥

EK-CI1750-TD-PRE

C1750 Hardware
Technicdadl
Description
Preliminary

Prepared by Educational Services
of

Digital Equipment Corporation

First Edition, July 1984

The reproduction of this material, in part or whole, is strictly prohibited.
For copy information, contact the Educational Services Department,
Digital Equipment Corporation, Bedford, Massachusetts 01730.

Printed in U.S.A.

The information in this document is subject to change without notice
and should not be construed as a commitment by Digital EqQuipment
Corporation. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.

The software described in this document is furnished under a license

and may not be used or copied except in accordance with the terms of
such license.

Digital Equipment Corporation assumes no responsibility for the use

or reliability of its software on equipment that is not supplied by Digital.

This book was produced on a DIGITAL Word Processing System.
Book production was done by Educational Services Development
and Publishing in Nashua, NH.

The following are trademarks of Digital Equipment Corporation:

Rainbow

Efl@flflafl TM

DECtape

DECUS
DECwriter
DIBOL

RSTS
RSX
UNIBUS

DECnet

MASSBUS

VAX

DECset
DECsystem-10
DECSYSTEM-20

PDP
P/OS
Professional

VMS
VT
Work Processor

DATATRIEVE
DEC
DECmate

CONTENTS

Page

CHAPTER 1

MANUAL

ILink

BOAY eeeoeooooaososossssscsssssssssscsssssscsccscsccs

Cyclical Redundancy Check (CRC) ByteS.......... 2-

TYrailereeeoeeeooososscsosscsssssssscsssssssssscsscsscs

(VO
I oy

o
o
e

°*

o
¢
o

JO U

OVERVIEW. cecooocococecscsceoscscscscsososscccccscococscscsosoe

o
o

W
N

o
o
o
e
o
o

WNDND N

SN
S
SO SO O
N SN SO SO

PacCKeteeeossesocoossssossssssscccocccos

Acknowledge/Negative Acknowledge

Information Packet ReceptiON.ccceccoccocscccccsce
ACK/NACK Packet TransmisSSiON.:.cceceececcssccoscscce
Information Packet TransSmiSSiONeccceoscoscscocscsccs

o
o
e
oo
o
o
o

?—
2 -

JuUlWw

JO U1
O 00

|]
®

[]

RO = o

®
[J

[]

e
et
bt b

sosnsoe

SOUYCC e oooooceossscscsscscssssossoscssssscscscsso

OCOWOo

2 Destinations (True and Complement)...eceeeeoseses 2 -

2Packet Type/Length (High).ccceeeooeeecccocccens 2 Packet Length (LOW).eeeecececsocoosscscscccccocssses

LINK

N SO -GN S~ S0 TV B NS I\ O T O I S I 0

DD DD DN

2 -

2 Packet.cceeeceesoosossccccccocscsscccsoes

2~
Bit SynchronizationN.ceeeceeccscccoccccccccccsccs
2 Character SynchronizatioON.eececeeecscocccscccccs

[]

e
e
e

[
[J
[}

[]

FORMATS . e o oeooceecccscssccosoccsssccsscscscsscsocscaoc

WWwwwhh
DN
-

LINK MODULE

oD
s | S

(ACK/NACK)

(PB)ecececoscoccsssososcccoscosns

Data Path Module (DP)eeeeeeoseesosccsssssscssasel
CMI CIPA Interface Module (CCI)eeeeoooonoosssnssel—ll
CI750 POWE T« o v o oeesecoessssssasssssescsssssssessl=l3

Information

[]
®
®
LJ

MOAUlE e e eoeeocooossosscssoscscssssscsssssscscscssse

Packet Buffer Module

PACKET

(CI)ecoccescccocscccosccocsce

RELATED DOCUMENTS e e e oo ccscsecooccsscscsccccssscocosscscscccce
THE CI750 INTERFACE . e e cooecccccccoscsscsococsccsccscsccoccocs

CHAPTER
NN NDNDDDNODNDND
NN

SCOPE e e e oo ceoscocsoocoscsscooscocsoccsssscoccsscocsocscocos

THE COMPUTER INTERCONNECT

| J

BB
D
WD

e b
e
it
b

INTRODUCTION

ACK/NACK Packet RECEPLiON.ceeeeoscssecoccscascssel
LINK OPERATING STATES.............................2-10
RECEIVE CHANNEL...................................2—12
CI Carrier Detection and Path SeleCtiONeeesoesss2=1l2
Carrier Detect Logic..........................2—12
Receive Path Select Mux -- ECL LOgiCeceossseeel2=1ld
Manchester Decoder..............................2—15
Phase Encoding................................2-15
Decoder Logic.................................2-18
sync Character Detect Enable PALcceososssssscssssssl—18
Byte F L OMET o o oo s eosevecossssesossscsssssssssssssesl2=20
RCVR CLK GENELAtOr e eeoeoossosesescsssssssssssssssl—24
CRC Check.......................................2—26

Destination Compare.............................2—28
ACK Source Comparison...........................2-29
Receive Data Parity and Channel Outputeecesesseee2=29

iii

CONTENTS

®
®

o~
w

RS
°

WWWWNH

°
®

G I
G NS

-~
W N

BytE€.eeeescooceccccscssoscccccccaos

Generator....................0..

to Serial

Data

ConverSiONe.oeeoeoo

=
N

.2-33
.2-34

.2-34
.2-34
«2-37

.2-41
.2-43
.2-43

LOgiCeeeesocscoscccccscas

LINK

FUNCTIONS:coeeeeecocosocsccoccocsccoe

LINK

INTERFACE

OPERATING

SIGNALSeceecceeccecoocscss
STATES e e e e ccceccsoccsccsosococsocs

Message

TransSmMit.ceceoccsccecoccsccss

Transmit Control LOogiCeeecoccccose
Transmit StatuUS.eceecececccccccococss
ACK RECE1VEC:eeeeossssccccssscssssscse
ACK Receive PAL StateSeeecececececceos

.2-33

CHECKER:
e e e s eoscesocccscses

GENERATOR AND

sync

®
| ]

.2-33
.2-33
.2-33

CRC Generator.....O................
CRC CheCker......................O.......
ARBITRATION.....................0....

DriverS. ® © & & & o 6 & & o o 6 6 o O o & O O o

Arbitration

Character Detect

Enable

PAL.

Message ReCEe1lVEieeeeeosssoscsossscss
ACK Transmit...................Q...

.2-30
.2-30
.2-30

«2-37
.2-39
.2-41

ECL

ENCOQEr.iceececoosocossosssssscocscs

General.......Q..........l......O....

.
WD
NN -

CLK

XMIT

OO OO0
OO0

BYtEC.eeeceoceoososcooscsscsscsssscsccsocsscs

Manchester

OJdJOoUILbs
W

Type

Parallel

NG
W
W
®
®

e W
G IR

°
®

Packet
SOUrCe

XMIT

Vol
T
S

STy S Ry O
O

e I S I S
o

e
SN
O
o

O
o

InsertSeeeeccecccccccscscssoccsscsocoocoe

Transmit Data Parity CheCKk.i.oeeeseococscs
CRC GeneratiONeceeessocscocscoccscssccsocos

PACKET

DATA

O
e

Packet

Destination ByteS.eeeeceesccsocscoscocscsse
Destination Address RegiStereceeecccecececeoo

CRC

®
[]
[]
[}
[
°
[]
[}

ACK

)
L]

RGN

)

G RS R R

DD NN NDDNDNDDNDNDNDND

DN
e

NN DN

Transmit Data Input...0...........0....0..0..
Bit Sync, Sync Character, and Trailer Bytes..

CHAPTER
WWWWwWwWwwoLbwuwwuww

CHANNEL...............................

TRANSMIT

DD NN

Page

.2-43
.2-46
.2-51

.2-54
.2-54
.2-58
.2-62

.2-63
e e2-65

e e2-65
«e2-67
«e2-69
«e2-72

BUFFER MODULE

FLOW;

GENERAL

DISCUSSIONe:ceceeeososocsese

eoee3—1

LOAdececcecccccsccccoscsccsccsosccscscscssscos

ceee3—3

TraAnNSMiteeeoeosoceoscscsososcsosccsssccscssscsscscscscss
R€Ad.cecocoeocscccscsccccccscscscccsccocssocscsos

ceose3—3
ceee3—3

TBUF
TBUF

ceee3—3
coee3—3
RBUF READ.................O..............
A
ceoee3—-3
PB REAGd MUXeeooooococscocsosscossscscccsascse
ceoss3—3
Control LOQiCeceeeoooecsccsscsscsssscssscasaos
coes3—-4
TBUF DATA FLOW OPERATIONS
. ccceeoooccccccsescs
ceoee3—4
TBUF LOA@Aeceeessscsccccccscscscscscsocscccccscaose
Transmit...........................O............ .3-6
TBUF Read (LOOpbaCk)oooooooooooooooooooooooooooo .36

Valid

RCVR

RBUF MLOAD

DatA@eeeececscsccscecccccoccsescs

(Maintenance

Load).ececececocecoesoe

CONTENTS

|
OWJIdJ

wWwWwww
I

W N
B

WwNhH-=

ceee3-12
BUf...O......Q...........C........
3-16
ceee
Q.
.........
LaSt Data ByteOOOOOO..O...Q.
3-16
ceee
ccocscss
ccssssosscso
ososccecsocc
BUuf.ceceoes
16
s3—
cee
ssccccacs
TranSMit.eeeeseoososocescsocsccssoscsss

o
@

U0k
o0oJO0O

Read

LOADL e e e s eoceccocscsccsccsccsssssoscsoccscsossces

cess3-16
ceee3—16
ceee3-16
ceee3-16
ceee3=17
eoee3-17
ceee3=17

TBUF

Load..............................

00003—19

TBUF

Read

(LOOpbaCk)ooooooooooooooooooo

00003-21

TBUF ¢ ¢ o0 e6cc0occceocscccsssccscoccscsscsce

RBUF .ccececccsceccscscscscscssccscoccs

Release

[]

RSET

00003-12

Load
Load
Read

NOAe

APR:cceocoeocecccccsosscscsscscses

Read Xmit

StatuUSeiceeeccscoccccccsssosssccce

StatuUSeeesccccoccsscsocscscsccocs

Read

RCVR

Link

Enable

and

Link

Disabl€eicecececcecsss

Transmit...................O000000000000000000003—21

Valid RCVR Data...........0.....................3—22

cose3-24
3-25
coee
RBUF Read o o .. ® © 06 06 0 00 06 06 0 06 06 06 06 0 0 06 0 0 0 0 0 0 oo o o
coee3-26
RCVR STATUS ® © 0 06 0 06 0 © 0 0 0 0 0 0 0 0 06 0 0 6 0 0 0 0 oo . e & o o
3—26
ceee
CRC ERR...O.............Q........C..........
3—28
ceee
Full, RBUFBFull........O......
RBUF

RBUF

RCVR

CONTROL

First....................................3—28

BUSO............................

00003-29

Enable..........................

00003—29

BUS...ooooooooooooooooooo00000000000000003—29
Enable...................................3-29

STORE

SIMPLIFIED

BLOCK

DIAGRAM:cecsocoocccoccocoe

=
N

YOI

MICROWORD PARITYe o e oeeooocsc0ccccccsscscscoe
:
sscscccccssscscse
ORD
e e o s ececooccsocc
s ROW
CS MIC

Microword
Microword

FieldS.ceecoscccoscsocccscocscscses
RegiSterecececccccsscccsccccccscs

MAINTENANCE MUX...................................4

RBUF

MLoad ® 0600 06 0 00 060 06 0 06 0 006 0 0606 0 0 0 0 0 0 0 0 o

I
S
SN
i

RBUF

o>
O
0P

[]
o
e
o
o

AU
WHN -

e
o
e
o
O
e

~Noy
Ok Wi

[4
o

[J
[]
[]
[J

[4
®

BUf..........Q..............O.

Load

SEL Read BUE..Q.................................3-12

SEL

SEQUENCING LOGIC...................0000000000000003-17

LuUumummdbwWWwWN
-

CLOCKS.............................O..O....... 00003-10

o
o
o
o

O
¢

S
e

N
N

R€Ad.coecoecsoecscscscscsscsscsccsscsssscsscscsccssscocscss

PB REAA MUX e oo oeeosssssassssssssssssssssssscssssl

FUNCTION DECODER AND BUFFER SELECT LOGIC.:eeeeesee3-12

[}

RBUF

CHAPTER 4

E g

(Maintenance Load).ecececcecocoscsccsscocscs

RBUF MLOAD

[

e
o
o
e
e
o
e
9
o
o
e
o
e
o
o
o
e
e
e
o
e
e
[J

S
scscsccssosoos
ION
e e e oceescsccocccc
RAT
RBUF DATA FLOW OPEce
Valid RCVR Dat@eeceoecccossscccscssccsscssccsscsccccsssos

OO ININIIJoouuvuommuunuonnunnuutonuudedwbwwww

WWWWWWWwWwWwWwwWwWwwWwWwuwWwuwwwWwuwuwwwwwbwww
Wwwwuww

Page

ContrOl Store Space. © 06 0 0 06 © 06 006 0 8 6 0 0 0 00 0 06 0 0 0 0 5 0 0 0 .4-11
Control Store Logic. ® © 06 0 06 0 © 0 © 0 0 © 06 0 06 06 06 0 0 0 0 0 0 0 0 0 2 04-14

CONTENTS

4
o
e
®

MDA'I‘R ® © © © 6 0 6 & 0 & 06 0 0 0 0 0 O O 0 0 0 0 0 o 0

ceeeD=D
«eeed=5
«s.5-10
es.5-10
eeeD=11
eeeD-11
ese5=-13
eee5-16
eeed=17
«ee5-19
eee5=-19

ALU...........................0.......

° 005—23

Receive Puffer Parity Error (RBPE).....

o o 05—29

[Output Parity Error (OPE)]..cceecccoses

ee o529
ese5=32
eseD=32
ese5-33

D W -

[

PB OUT Register...........0.......
PB IN Registe€reeeecess
XBOR RegisterO....................
XBIR Reg iSter. ® 6 6 & 6 &6 & & ¢ & o & & O & 0 O o

BUS......................O.....

°
[

N =
-

e
e

VCDT. ® © © 0 © © 6 ¢ & & &6 0 0 O & 6 & o & 0o 0 o

I.,S/VCDT Address SelectioN.eeeess
LS/VCDT Write Strobe LogiCesecesecoss

w N

a nd

PB IN Register Parity Error

=
N

CIPA
e

e
e

AND

N~
N

| ]

o
o

(PBIR PE)

EXYOFeeeeoocsosossscscscscsscsccsscscccsssocce

DP To CCI

Parity ChecCcKkeseoeoccococcons

CCI To DP Parity Check (IPE).cecceccccs
Packet Buffer Parity (PB PAR)eceecococcss
Local Store Parity Error (LSPE).cceeeees

Parity Error

(PE).cececececcccssscscsaaccscsse

CMI

REQUESTSeecceseccoccccocce

UNSOLICITED
[4

INTERFACE.

2901A MicroprOcessor..................... 00000005-23
es o526
Data ManipulatioN..cecescccscccscecccaos
-27
«eeD5
eccscscsns
Carry Look—-Ahead LOJiCeceocscesss
27
eee5=
esoesoee
CHECKING:
AND
DP PARITY GENERATION
=27
eeed
LogiC.....
Checking
and
Generation
Parity

w N

®
o

AND

PMCSR And Microword LITERAL Field..c.eecs.e 00000005_20

wN
=~

o
o
o
o
o

BUSES

MADR

NOoOY
O b

NI
OO0
OO
OO0
0O 00

cood=27

|
ceeed=D

WWwNND
N

NSNS
o oo oot
e WLWWWWND

IdIdV

U
[
o

e
o

)

oot

o
o
°

®
e

e
)

Uty

o
o

START-UP........O.......

00004_16
...4_]-8
00004-22

GENERAL................
CIPA BUS...............

LOgiCeeceeosocs

0004_16
0004-16
0004-16

DATA PATH MODULE

o
o

Control

Logic....O..........O..

BranCh

®
o
e

QU
U, OTOT
N O On

Microsequencer

MICROCODE

CHAPTER 5

Logicoooooooooooooooooooooooo

MICrosSequenCereseceescscoosocsscsscos

2911

WK
-~

DN
DN

Microsequencer

CONTROL STORE ADPDRESS SOURCE:ccececeececcccccecs
Maintenance Address RegisSter.cecececccccecccscs

®
o

o
°
o

N
o

S
o

N
e

NSO

e We )W e )Mo ) e INo)

Page

Starting An Unsolicited SequencCe....see.
Unsolicited Write SequenCe..cccececcoocsceoe
Obtaining The Write Cata@.esececcscoccocses
Register SeleCtiON.ceeccccocsccccccscs

«ee5-34
eeed=35
es o536
cecesssd—36
ceseeseD—38
ceesssed—4l

I
cessseed—47]
Unsolicited Read SeqUENCE.icecececosscccsscs cessesesD—48
Register SelectiON.eceecececceccccccccccacs ceseesed—49
Transferring The Read Data To The CCI. ceseeesd=50

CONTENTS

=
W N

DP Initialize Logic...........................5—75
=77
Boot Timer And Maintenance TiMEreooooeooccoeeed
/9
sd
ssesse
cscsss
ssccso
cooeoc
ON.
FUNCEL
l
Power Contro

Power-up Sequence.............................5-79
5—85
Power Fail Sequence...........................
87
...5—
.....
.....
.....
.....
ion..
Funct
Remote Reset

(G2~
VO I (O I

o
e

W N
D
N

= O

= 00O Ui W N

o
o
e

o
o

o
o
o
e

o
o
e

b e e b
b et e
pd o

NNNNNNNNNNNMMH'—‘HP—"—‘

CHAPTER 6
AN TN
AR
OO
O
e
©
o
o
o
o

5-54
Control Signals.................................5—56
.....
.....
.....
.....
LOGIC
CCI/DP INTERFACE CONTROL
Port Initiated Write Of CCIeeeocoosasssssssssssssd—D]
ed=DT
Port Initiatted Read Of CCToveeooooaonsossssessse
60
...5—
.....
.....
.....
tions
Unsolicited Reqguest Opera
-62
....5
.....
.....
.....
MODES
TING
PORT CLOCKS AND OPERA
62
Port Clocks.....................................5—64
...5—
.....
.....
.....
.....
.....
Operating Modes.....
Run Mode......................................5—64
4
Uninitialized Mode............................5—6
.....5—64
Stall Mode...............................
...5—65
.....
.....
.....
.....
.....
.....
Mode.
nd
Suspe
Di fferences Between Stall and Suspend Mode....5-69
INTERRUPT, INITIALIZE, AND POWER
CONTROL FUNCTIONS.................................5—6/29
Interrupt FUNCELON . s e oeosocosesssssssssassssossed
..5—75
Initialize Function...........................
-75
...5
CCI Initialize Logic.......................

w N

DD
o
o

¢
®

WWW
W
N NN -

o
©&
e
o
o

b i et

N b
LJ
®
®
LJ
[]
[4
o
o
e

e = =

e
e e

[

....5—51
DP CONTROL LOGIC..............................
.5—51
.....
.....
.....
.....
.....
n....
IB Bus Destinatio
.5—53
....
....
....
....
....
....
....
....
IB Bus Source..

w
e

OO OO

bt = =

SR
NN
NN NN NN

O
O OO

U oo
o Lo
Bt
o
©°
o
SRR
RS RGNS, NE, NS,

Page

CCI

MODULE

......6 1
OVERVIEW.....................................
.........6 2
CMI Protocol............................
Bus Signals....................................6—28
.6
Write Timing....................................6
8
.....
.....
.....
.....
.....
Read Timing...,.....
1
...6—
.....
.....
.....
.....
g....
Write Vector Timin
Major Components................................6-11
Ccommand/Address Hi Register...................6—11

Address Lo Register...........................6—11
Byte Mask Register............................6—14
XMIT File.....................................6—14

.6—14
Return Read Data Register....................
....6—14
Interrupt Vector..........................
....6-14
....
....
....
....
....
....
CNFGR Register....
CMI Mux.......................................6—14
......6—15
Address Decode Logic....................
.....6—15
....
....
....
ster
Regi
Hold
Command/Address
Address Offset Register.......................6-15
Function Register.............................6—15
vii

CONTENTS

W
S

[]
[]
[]
[]

WK
=
=~

o
o

W~
wn
-~

wN
-

U
e
|

o
o

wN
-+

o
o
o

W N+

o
o
[]
|]
[]

WWwWwWwN

[]
o
o

WWwWwWwwLwNpNDD DDV

e
o
o

DR
DN

o
o
o

o
o
©
o

Unload XMIT File And Status CyCl€.ieececeossssb—4l

Read FUNCEION..eeoeeecsosaosecsssossossasesssssssseab—dd

ISSUE GOu e eeoeeesoossoeosoosossssssssssssssssssccsesb—dd
ATDIitratioNeeeeeecseseeecsssssssosscssscossssssccssb—d4d
Command/Address CYClee.eeeceosssossscsscssscsssb—4d
Status Cycle And Load RCV Fil€..eeeeecocsasasab6b—45

Unload RCV Fil€eeeeesssessoccsssssnsssssscsscessb—4d8
Write Vector FUNCLiON..eeeseeccccsscsssssossosseeb=50
Issue Interrupt...............................6-50
AYDItratioN. eeeseesescsssossessssssssesssssssscssb=52
Write Interrupt VecCtOr..eeeeesessesccsccsssosseb=52

UNSOLICITED CMI OPERATIONS........................6—58
Command/AdAress CYCle..eeeeeeosecsoasessosoossesseb=58
Address Space DECOAEr ¢ o vssoseesossssasssssnssesb=60
Register DECOACY e ceoeseseoccccssossssssassscceeb=60
Command/AddresSs SEQUENCE..cseessssocssosssssscesb—63

Read/Writ€ CCIleoeeeecoceccessososssscssssscssscsssseeeb=65
Maintenance FUunNCtioN...eeceeeeecosccscosssssseeesb=65
Writing The CNFGR RegisSter..ceesccccecccccessssb6=05
Reading The CNFGR RegiSter.eecescescsccecsccesseab-68
REAd/Write DPucecececccccoccsossssssssscscssesssosssssb—08
CIPA Transfer ReQUESt...cecececccsssccsssccsseesb=69
WEIte DPecececsccssssoscccscsscsssscsscsscscsssssessseesb=72
Maintenance Initialize (MIN)..eeeeosossesoeesob=74
REAA DPev eeececcoososssssssssssscsssssssssssecsecb—74

CNFGR REGISTBR....................................6-77

WWWWWMNDNDDND

Load XMIT FilEGeeeeooesososoososcssscsssnsssnsscssb=29
ISSUE GOt eooeooooessssassesccsscsssosssssssesesssb=3l
AYDIitratioN..eeeeeesseessccsssossasssessscssessb=34
Command/Address Cycle.........................6—37

PORT-INITIATED TRANSFERS ¢ e e oocessscsccssssssssssssd=24
Load Command/Address And Byte Mask Registers....6-24
WELite FUNCLIiON..eeeesoesesoossssossssasssassssssab=29

T ACLO,

Receive Write Data Register..ceeeeeeseosccccecsssb—lDd
RCV Fil€eeeeeeoososssossccoassssssassssssscsssssssb—l
Simplified Flow DiagramS...seeeeecsessscccsssssab-10
Port Initiated TransSferS..cceeccccceacsssssscssesb—1b
Write Vector FUNCLiON..eesoecescsssosssosssscssab=19
Unsolicited CMI TransferS..cccccceccccccccsscesb=2

Adapter COAE e e eoeoesoseososcsassessscsssasscnssnnesesb=T7

O ~JO

B AR S BDLEDRERWWWWWWWWWWWWWWRNRNDNNONRNODNODNNNDNONDND
NN HE
BB

e N

N R

oo oo oo oo oo R ka

o Xo o koo

[]

[

oo oo e Xa o ko Ka o Xoa k-2 eaKo leale ) Werle W e) e )N o) B o) We) R

)}

Page

PDN, PUP, NO CIPA..ceeocecoscsscccscccccsccscssonsssesecb=77
T DCLO,

PF D e veceooosssosscsscssssssscsssseb=79

NXM, UCE, CRD. e coeoocoscsscssssssssscscscsssssssseeeb=79

DIAGNOSE e e e cocoecscccsssscssscssssscscsscsssssssssssb—80

CTO e o e v ooeveosoososossssesesesessssssssssscssseseab=80

RLTO . ¢ e eooeeccocscsssoosssosccsscssssssscssssssssssssssb=80

CBPE.....C........O.............................6-81

viii

CONTENTS
Page

INITIALIZE AND POWER CONTROL FUNCTIONS............6-81

6.5
6.6

CI1750 MNEMONIC GLOSSARY

APPENDIX B

FLOW DIAGRAM SYMBOLS

APPENDIX C

HARDWARE REGISTERS

C-1
MADR -- Maintenance Address Registerecececcecccecccsne
s C-2

ceeececece
MDATR —-- Maintenance LCata Register...c.cc
Register. Cc-3
atus
ol/St
Contr
e
enanc
PMCSR -- Port Maint
CNFGR -- Configuration RegisSter.cecccecccscccsccce C-4

S W
-

QOO0
0

APPENDIX A

FIGURES

;o
W N

.............1-2
Four—Node CI Cluster......................
.........1—6
CI750 Connection......................
.1-7
CI750 Configuration...............................
....1—8
CI750 Block Diagram............................
..1—14
....
....
....
....
....
....
C1I750 Power Distribution

(\O) e o

DD DD
NN N
!
[
T

oo ~JouUlbd
W K

....2—4
Packet Formats.................................
.2—6
....
....
....
....
....
ram.
Link Simplified Block Diag
13
...2—
.....
.....
.....
am...
Diagr
Receive Channel Block

2-13

2-14
2-15
2-16
2-17
2-18

2-19
2-20
2-21

2-22
2-23

..........2—16
Receive Path Select MUX ECL Logic.......sssss
sssesel=ll
sssss
csess
coece
PE (Phase Encoded) DALA.
....2—19
....
....
....
ram.
Diag
ng
Timi
Manchester Decoder
.......2—21
Byte Framer Block Diagram..................
sssl2=22
eees
eeee
Ster
Regi
t
Shif
al
Enabling the RCVR Seri
...2-23
Byte Framer Timing Diagram.....................
.............2—25
RCVR CLK Generator...................
.............2—27
....
....
....
RCVR CLK Synchronization.
—31
Transmit Channel Block Diagram....................2
............2—32
Sync/Trailer PROM Space...................
.........2-35
....
ram.
XMIT CLK Generator Block Diag
.........2—36
.....
am...
Diagr
XMIT CLK Generator Timing
....2—38
.....
.....
Manchester Encoder Timing Diagram...
.2-40
.....
.....
.....
XMIT ECL Drivers..................
.2—42
.....
.....
.....
.....
CRC Generator/Checker........
45
...2—
.....
.....
Arbitration Flow Diagram.............
7
..2-4
.....
.....
.....
Arbitration Block Diagram........ ...............2-52
.....
.....
Link Functions...........
..........2-55
Link Interface Signals..................atio
n......2-56
Oper
smit
Tran
-Interface Flow Diagram

CONTENTS

Page

2-24
2-25

Interface Flow Diagram -- Receive OperatioN.......2-57
Message Transmit State LOgiCe.ececocscecsoscsscsssssee=59

Transmit

Control

2=27

Transmit

StatuUS..eeeeeeccccosesscsssssccsssscssccselb4

2-28

ACK Recelve State LOgiCeceeeseseocscscssosscosssccsceslb6
Sync Character Detect Enable PAL..cescesscoscsoscsel—68
Message

Recelve

State

LOgiCeeeeoessosccccscsscscssesl—70

FlOWe:e.eceooeosessosoosssosscsossssseeld—2

Data

Function Decoder and Buffer Select LOogiCe.eeeeoseoese3—13
PB LO@d LOQJ1Cieeeeecscscocoscoscoscscsscscsnsosssoscssesl—l8

W oOd

LOgiCeeeeeecocccscescscsccsossesl
73

TBUF
RBUF

State

wWwwwww

Transmit

WWW

ACK

LOgiC.ceeesssscsosscsscssscccscsssl=bl

w W N
= O \O

2-26

Buffer

OperatioNS..eeeccecscsscecscscccscsssossossscssssss3—D
OperatioONS.cececcececscscsossscsssssssscsscssscsesld—8
ClOCKS.:eeeeosecososcsscsscssssosscsonseld—1ll

Sequencing
Sequencing

RCVR

StatusS

BN
OJUTWIO

Microcode
Microcode

Start—Up
Start-Up

Data

Path

Module

CIPA

Bus

With

And

Cia@gramM..ccececocoecocsococssccococse 5 -

CCI

InterfaceS.cceececeocsccccsos 55—

and

InterfacCeS..ceeccecsccscecsoscoscscoscsssedm
5

Block

DiaQraM.e.eeeeeecessossoosssscosssoceesd=l

LS/VCDT Address Selection Block PDiagram...ceceeee.5-15
Write RAM Timing LiagraM..ceececscoscscosccsscsocscessd=18
ALU Block ClagramM..eeceeccsecescccsecscscscsscsscsscsoscscceed—24

Unsolicited CMI Operations - Simplified
Flow DiaAGgramMe..cecececceccccsccscccssccosccscscsccscssscocceed—37
Starting An Unsolicited OperationN..eeeeeeceeossoceesd—39
Unsolicited CMI Request LOgiCeceeeoccccscccsccossssd—40

LOgiC.eeeessececcscscssccosscscsseed—28

Look-Ahead

Parity

—

Carry

LS/VCET

LS/VCDT Address Selection Simplified Block
D1AQYaAM.eeeeeescscssososccscssscssssoscccccccscososssssssd—14

(O2 G2 RNC

Buses

BloCk

LOgiCeceeeesecesssccscccsscssseesd=30
Timing Diagram...ceeeeoeeeocoeoesssd—32
O
N

-HO

LOgiCec.eeecocscosoccscoccsss

BranCh LOJ1lCeeoeeosecososcscsccsssssososssscsscssssssssscsoe
Microcode Start-Up Flow DiagramMe.ceececececccocsocsesosd=28

Control

OJo

Microword Parity CheCKereeeeeeeeeoosooscsoooocsoncseoe
MiCroword Fi€ldS.eeeeeeeceseescssoscosoccccsssosococscese
Control StoOre SPACE.eeeecesossoscscsssosconcossscscsos

[
[4
o B BN
e
|
|~
Y SN 1 N
NN
=
|
!

Simplified Block PiagraM..ceeecesoo
BlocCk DiagraM. eceeeeeccooocscooccsscaes

NN
O
N

Store
Store

Microsequencer

NG SN O

LOG1Ceeeeceoccosscsscscsssscsssscscsccsceseld—2/

G20,
O
|
=
O 00 ~JdOo

OCuomuLmor
|

Control
Control

LOGiCeeeessocosscossosssscscscssessld—20
LOgiCeeeecececsocosecssssosssocssseeld—23

Control StOore LOgiCeceeecesscsecsscesoscsoscscosssscsscoes
Control Store Address MultipleXinNQeeeeeoooeoocoeoseo
2911 MICrOSEQUENCEY .ieseesososossscsssosscssoscacsssssse

O
I

Buffer

Packet

TBUF
RBUF

5-114

Generation

Unsolicited

CMI

And

Write

Checking...coesescoeccsceeeed=30

Operation

Flow

Diagram......5-42

CONTENTS

Page

Unsolicited CMI Read Operation Flow Diagram.......5-44
DP Control Logic..................................5—45

CCI/DP Interface Control LOGiCeesesessossossosocesed=4d7
CCI/DP Interface Control Logic - Port Initiated
Write Of CCI......................................5—58
CCI/DP Interface Control Logic - Port Initiated

Read Of CCI.......................................5—59
CCI/DP Interface Control Logic - Unsolicited
Request Operations................................5-61

POTt CLOCKS .o eeeoeoosesssossessssssssssssnssssassed—00

Stall Mode Timing.................................5—67
Suspend Mode TiMinNge eeeseoeeesossscsssssescscssssseed"68
Interrupt, Initialize, And Power Control

Bl ock Diagram.....................................5—70
Interrupt Logic...................................5—73
Interrupt Sequence................................5-74
Initialize Logic..................................5—76
Initialize Sequence...............................5-78

W+
WO oOoOJoOWuL

OV O

Power Control Logic...............................5—80
Powerup Sequence..................................5—81
Power Fail Sequence...............................5—82
Power-Fail And Power-Up Interrupt SignalSeceeeeess.>-=88
CMI

BUS

SignalS.ceeccescecccccscscscsscscsoscsccsconcs

CMI Data And Command/Address FormatSeecsecceecccccscce
lTM
CMI Write Timing..eceeeeecececcscocscsocscsocosccssccoscess

CMI Read Timing...................................6—1

CMI Write Vector Timing...........................6 1
CCI Block Diagram.................................6-13
Flow Diagram of Port Initiated TransferSeeeecceceees6=17

Write Vector Function Flow Diagram...ccssecsoeeeess6=20

Flow Diagram Of Unsolicited CMI TransferSe.eceeeceees6=22
Load Flow Ciagram for CMD/ADDR HI,
=2D
ADDR LO, and Byte Mask REJIiStErSeeeeeesossoocssosssd
—27
....6
.....
.....
.....
CCI Register Control Logic.....
Load XMIT File Flow Diagram.......................6-30
Issue GO Flow Diagram.............................6-32
GO /DONE Logic.....................................6—335
Arbitration Flow Diagram..........................6-3
Arbitration Logic.................................6—36
Flow Diagram Of Port Initiated

Command/Address Cycle.............................6-38

CCI Control Logic.................................6—40
Unload XMIT File And Status Cycle Flow Diagram....6-42
Status Cycle And Load RCV File Flow Diagram.......6-46
Unload RCV File Flow Diagram......................6-49
Issue Interrupt Flow Diagram..eeeessessocscssscssebdb=5l
Issue Interrupt Logic.............................6—53
Write Interrupt Vector Flow DiagraM.ceecececccooesssb=54
X1i

CONTENTS

Page

Interrupt VECEO e o e oooeosessasesssscsssassosssssessesb=50
CI750 Address Responses...........................6—61

Unsolicited Decode And Register LOgiC.seceseececessssb6=59
CI750 CMI Address Space vs Register

Decoder Outputs...................................6-62

Flow Diagram Of Unsolicited

Command/Address Sequence..........................6—64
Read/Write CCI Flow DiagraMe..cecescsasssssccscsessd=b7

Flow Diagram Of CIPA Transfer REQUESteeeeessacsessb6=70

Write DP Flow Diagram.............................6—73
Read DP Flow Diagram..............................6-75

CNFGR Register Logic..............................6—78

Flow Diagram SyrnbOlSoooooooooooooooooooooooooooooooB—l
Maintenance Address Register (MADR) Bit Fields.....C-2

Maintenance Data Register (MDATR) Bit FieldeeoeeoosC—4
Port Maintenance Control/Status Register
(PMCSR) Bit Fie€ldS.eeeeeeccccossscssasscsssssssssseslTM0

Configuration Register (CNFGR) Bit FieldS.eeoeoees C—8

xii

CONTENTS

Page

—

CI750 Related DocumentSooooooo0000000000000000000001—3

N+

.........2_11
Link State Diagrams...........................
.....2—25
.....
O....
.....
....0
.....
S....
Link ClOCk
NLoad Mux Selectionoooooooooo000000000000000000002—48
i nk Control Codes Vs PB Function CommandSeeeeeses3—14

wN
> w N

...........3_15
Load BUffer SeleCt COde......Q.........
...........3—16
.0.0
....
....
....
COde
t
Read Buffer SeleC
......4—8
Microword Fields.............................
ccsssd—l2
ososs
eoonc
eeeee
e
v
COAE
tion
Selec
Maintenance Mux
essd—20
sssss
Microsequencer Control FUNCE1iONS.eeeseoccc

www
o

p—

TABLES

—

Db
—

P
|

W+~

oo JgouybdWwhh
-

o n
ooy ot n vt
!
R

g
A OYOYOY O

Branch Conditions.................................4—26

CIPA Bus Signals.....fi........0000000000000000000005—83
..5—1
LSA Mux SeleCtiOn Code........................0.
17
0005—
00000
00000
00000
....0
.....
es.O.
MD BUS Data Sourc
—21
....5
.....
PMCSR Bits...............................
....5—25
ALU Source Code...............................
..5—25
.....
.....
ALU Function Code.....................
26
..5....
....
....
ALU Destination Code................
52
...5—
.....
IB DST Code...............................
53
...5—
.....
IB SRC Code...............................
REG SEL Code......................................5—56
Port ClOCKs...............O.......................5—63
CMI Bus Signals.................0.........0........6—2
.....0.....6_7
FunCtionn Code.......C..................
6 06 ¢ 0 0 0 O [ I .6-39
©
©
e
O
o
&
&
&
@
0
9
6
0
6
©
o
COde.
MUXA/MUXB SEL <B:A>
........6-57
.....
.....
.....
s....
Value
r
Interrupt Vecto
CI750 I/O SlOtSoooooooooooooooo00000000000000000006—60
CNFGR Bits.O.......................'...............C-g

xiiil

CHAPTER

INTRODUCTION

l.1

MANUAL

This

SCOPE

document

provides

technical

description

the

CI750

computer interconnect hardware.
It does not treat the CI750 port
architecture or other software applications such as the CI750 port
driver, command queues, or the VAX/VMS operating system.,

A basic description of the CI750 computer interconnect is given 1in
this chapter.
The CI750 contains four extended hex "L" series
modules.

Chapters

four

control

the

store

and

control

store,

its

each

separate

chapter

although

the

and

Three

appendixes

data

and 6

provide

detailed

associated

control

1logic.

addressing

logic,

can

and

treated

1is

distributed

description

its

as
a

describing

branching

single

over

for

1.2

supplement

the

computer

serial

modules

(packet

contained

form

this

this
flow

hardware

registers

1-1)

1is

cluster

1is

confined

description

1in

within
in
the

used

purposes.

interconnect

data bus

function

two

information

THE COMPUTER INTERCONNECT

The

the

path).

Appendix

maintenance

logic

cohesive

manual.
Appendix A defines
the mnemonics
found
document.
Appendix
B explains
the
symbology used

diagrams.

microcode

the

describes

Chapter

hardware

buffer

modules.

that

is used

cluster.

(CI)

(Figure

high-speed,

to link computer subsystems

Typically,

the

(nodes)
to

computer room environment. Nodes may consist of CPUs and memory.
Nodes may also include intelligent mass storage, communication, or
data

acquisition

Features

the

subsystems.
CI

include:

Dual

signal

70-megabit-per-second bandwidth and

32-bit CRC generation and

Low

Packet-oriented

Immediate acknowledgement of the reception of a packet

Contention

error

Internal
purposes.

capable

simultaneous operation

transfer rate

checking

rate

data

transfers

arbitration

paths

and

heavy

1light

external

data

and

round-robin

looping

for

diagnostic

1
R

STAR

COUPLER A
VAX

VAX

11/750

750

11/750

—4
R

STAR

COUPLER B

1
R

VAX

11/750

750

Cl
750

VAX
11/750

flR

MKV84-0127

Figure

1-1

Four-Node

Cluster

Fach node within a cluster connects to the computer interconnect

via

CI750

interface

that

provides two

paths.

signal

separate

Dual paths provide a high degree of data availability between
nodes. One pair of nodes can communicate over one path (path A)
while another pair of nodes communicates over the second path
(path B).

Each path contains a central star coupler (SC008) that receives
the data transmitted by a node and distributes it to the other
nodes within the cluster. A single CI path consists of a pair of

bus cables (one for transmit, one for receive). These cables
provide the connection between a node and the signal distribution
coupler

(star coupler)

1.3

for that path.

DOCUMENTS

Table 1-1 is a list of documents providing additional information
the

CI750.

Table

1-1

CI750

Related Documents

Document

Item

Title

Number

Contents

CI750 User's Guide

EK-CI750-0UG

Contains instructions
for unpacking,
installing, and

acceptance testing
the CI1I750. A physical
description of the
CI750

vided.
is

also

pro-

Information
provided

the C1750 backplane
jumpers.

SC008 Star Coupler
User's Guide

EK-SC008-UG

Contains a description of the SC008

Also
Star Coupler.
provides instructions

for unpacking and
installing the
various Star Coupler
configurations.

Table 1-1

CI750 Related Documents

(Cont)

Document
Item

Title

Number

Contents

VAX-11/750 Central
Processor Unit
Technical Description

EK-KA750-TD

Contains a general
overall description
of the VAX-11/750
plus a detailed
discussion

the

processor

central

unit.
Included 1in
1s a
discussion
this
complete description

of the CMI bus
including bus signals, timing, CMI
protocol, and the
VAX-11/750 modules
that interface with
the CMI.

H7202D Power Supply
Specification

SP-H7202-D

Contains complete
mechanical and
electrical specifications for the

H72020 power supply.
Also included is a
general description
of

H7202B Power
Technical

System

EK-PS730-TD

H7202D.

a physical

Contains

and functional
description of the
H7202B power supply.

Description

VAX Architecture

the

EB-19580-20

the

family

descrip-

Contains
tion

Handbock

VAX

architecture,

including

data

representations,
instructions,

registers,
operational

VAX Hardware Handbook

EB-21710-20

and
modes.

hardware

Provides

overview

of the VAX
Hardware

family.
descriptions include
the 11/780, the
11/750, and 11/730.

THE CI750

1.4

INTERFACE

The CI750 is the interface used to connect a VAX-11/750 system to
the CI cluster. It connects between the CPU memory interconnect
(CMI) of the host system and the CI cluster. Figure 1-2
illustrates

the CI750

connection.

The CI750 is an intelligent

interface that performs the

function

transfer

messages

complete

It utilizes the queue structure

of a buffered communications port.
under

provided

the

VAX/VMS

operating

system

and blocks of data between the host's memory system and other
nodes within the CI cluster. By providing data buffering, address
translation, and serial encoding and decoding, the CI750 reduces

the amount of overhead

software

processing

high-level intercomputer communications.

required

The four modules containing the CI750 logic are listed below.

W N

Link Interface Module

(ILI) L0100

Packet Buffer Module (IPB) L0101
Data Path Module (CDP) L0400

.
.

CMI CIPA Interface Module (CCI) LOOO9

Figure 1-3 illustrates the configuration of the CI750 modules.
The CCI module is installed into one of the three MBA option slots
The other three modules are housed
in the VAX-11/750 backplane.

in a CI750-C Computer Interconnect Port Adapter (CIPA) expander
The CI750-C expander cabinet is commonly referred to as
cabinet.

the CIPA cabinet and will be so referenced throughout this manual.

The CIPA cabinet is connected to the host CPU cabinet by a 40-pin
As shown in Figure 1-3, the cable actually
CIPA bus cable.
interconnects the CCI module (in the host CPU cabinet) with the DP

module

(in

the

CIPA cabinet).

Figure 1-4 is a block diagram of the CI750.
following discussion of the CI750 modules.

l.4.1

Link Module

The link module provides the

Refer to it 1in the

interface to the CI bus and has the

capability of servicing both CI paths. The module is functionally
divided into a transmit path and a receive path with a Cyclic
Redundancy Check (CRC) function shared between the two channels.
The link can transmit or receive over only one CI path at a time
due to the common CRC logic being used by both channels.
Data packets are received from the packet buffer (PB) module over

the XMIT DATA BUS, and are appended with header information and a
trailer.

The

header

functions

identify

source

the

and

destination of the packet. Node address switches provide the node
with an address on the CI cluster. The packet header contains this
address as a source identification. The trailer serves to keep the
node

are

receiver

locked

being processed.

up while

the

last

data

bytes

the

packet

VAX-1 1/750‘
MEMORY

ADAPTER

CMmi

UNIBUS

ADAPTER

MASSBUS

ADAPTER

ci7so

.
*

TX/RXA
TX/RX B

STAR

”

COUPLER A
STAR
COUPLER B
MKV84-0128

Figure 1-2

CI750 Connection

@2anbtg¢€-1 (0GLIDuorjeanbrjuo)d

|| |

_- v1ivaL3NIV|AIII_X1HLVdV
N_|0SL/L—XVA

CPu

HOST

CABINET

CL75C=C (CIPA

(VAX~-11/7750)

CABINET)

_-———————-————-——-—-—_—_-.—-_--—-‘--

RECEIVE
WRITE
.

RCV

CHl

cct

RCV

FILE

CIPA
Bus

CIPA
:

RETURN

XMIT

CfiD/ADR

READ

FILE

_REC

DATA
REG

XBIR

—XEIR

_DATA

LTCHD

wnew

HxXO

rrisG

< Bus IE

XBOR

| .

REG

PBOUT

REG

e
A

BUFFERS

DATA

o
e—{

SELECT

~«<}——«( CI-A

CARRIER

CI-B

MANCH

PATH

:
XMITTER o ENCODER

)
HEADER/

TRAILER

RCVR

PB
REGIN

XMIT DATA BUS

BUS MD

v—l

B (1K)

PORT DATA

("()

—— — =

ALU

CMDADDR

BUFFERS

ccT

XMIT

o — A

(1K)

= —— — —

w—{ B (1K) h— I

NODE
ADDR

CRC

ccT

MODULE
CI?7S8

CONTROL

MICROWQRD

DEST

BUSMD

DECODE

RCVR

MICROCODE

g DATA

STORE

CONTROL
|

BRANCH

CONDITIONS

| BRANCH
LOGIC

I8 IN

hed MANCH.

DECODER

DETECT

RCVR

MAINT

ADDR

REG

MICRO. I

SEQ

DATA PATH

PACKET BUFFER

MODULE

NODULE

LINK

MODULE

Figure

1=4

CI7S0

Block

Diagranm

The

logic

CRC

check

bytes

that

packet

the

uses

are

appended

data
to

the

generate

bytes

data

packet.

The

are unique for the specific data bytes in the packet.
are used for error checking at the packet destination.

CRC

four
CRC

bytes

The

The 1link transmitter converts the data packet from a byte format
to a 70-megabit-per-second serial format and then applies it to a
encoder.

Manchester

The Manchester encoder combines the serial data with the bit rate
clock to produce a modulated (phase encoded) carrier for the CI
bus.

The path selection logic selects the CI path (A or B)
for
The path selection is under microcode control.
transmission.

the

Carrier detection logic monitors the two CI paths and connects the
receiver channel to whichever path is active.

The serial data from the CI is applied to a Manchester decoder
which separates the signal into its clock and data components. The
clock and data signal components are applied to the link receiver.

The

link receiver converts the packet data from a 70 megabit per

second

serial

format

byte

format.

The link receiver then supplies the packet data to the CRC logic.

The

CRC

logic

the

against

response

validates

packet

CRC

returned

the

checking

the

packet

data

detected,

1is

error

CRC

transmitting

the

node.

module

can

PB module

are

full

RCVR

DATA

bus.

node.

the

buffers

the

will

then

retransmit

the

packet.

the

the packet is sent to the PB module over

If there is no CRC error,
If

packet

bytes.

link returns a positive acknowledgement (ACK)

the

packet,

the

to the transmitting
cannot

and

the packet, the link returns a NACK to the transmitting node which
1.4.2

Packet Buffer Module

(PB)

The PB module provides buffering for the data packets transferring

through the CI750. Two transmit and two receive buffers (A and B)
are

provided.

Each buffer

has

capacity

1K.

When

data

packets

are being transmitted, transmit buffer A is filled from the data
path (DP) module over the PORT DATA bus. The next data packet 1is
loaded

into

buffer

Likewise,

buffer

received

while

data

the

packets

1link

are

unloading

loaded

into

the

receive

data

from

buffer

from the link module over the RCVR DATA bus. The following data
packets are loaded into receive buffer B while the DP is unloading
the

data

from receive

buffer A.

The CI750 microcode resides in a 3K RAM/PROM control store located

on the PB module. The control store RAM/PROM outputs a 47-bit
microword that controls and regulates operations throughout the
CI750. Stepping of the microcode is controlled by a microseqguencer
The
field of the microword.
next address
which samples the
microcode

conditions

throughout

located

logic
the

also

subject

branching

in the DP module.

microsequencer

the

CI750.

output

conditions

via

branching

are

CRed

The branching logic tests various
The

test

results

branching

provide

the

with

microcode

sequences.

The CI750 control microword can be read by the host system via the

MD bus

the DP module.

Under certain conditions (system initialization or detection of an
the host system can force a routine by inputting the
error)
the

address via

starting

IN bus

the meintenance

and

address

l1.4.3

Data

Data Path Module

(DP)

flow within the DP is under microcode control.

The microcode

and

destination

for the data on the main LCP internal bus (IB).
There
possible data sources and destinations for the IEB bus.

are several
These are:

selecting

source

the

implements

this

control

XBIR (external bus input register)

OUT

registers

VCDT

ALU

(control

(miscellaneous data)

The PB

(local

(virtual circuit descriptor table)

(arithmetic logic unit)

IN and PB

the

store)

OUT registers

bits

interface

the

DP to

the

PB via

the

source

for

accomplish

the

The PB OUT register can be an IB bus destination

IN bus)

while

the

wide.

The

and

OUT registers

the IP bus (via the MD bus).
are 32

(external bus

and XBOR

output register)

PORT DATA bus.
(via

and

can

The three DP buses (IB, IB IN, MD)

format conversions necessary to interface with the 8-bit PORT [CATA

bus.

The XBIR and XBOR registers interface the DP to the CCI module via

The XBIR register can be a source for the IB bus
the CIPA bus.
The data on
while the XBOR register can be an IB bus destination.
The XBIR and XBOR
the CIPA bus is in a 16-bit word format.

registers accomplish the format conversions necessary to interface

with

the

32-bit

bus.

IS is 256 x 32 of RAM space used to store software status blocks
port
Cl1750
the
with
associated
registers
software
and

LS can be either a destination (via the IB IN bus)

architecture.

or a source

for the

IB bus.

The VCDT 1is 256 x 16 of RAM space used to store CI node
The VCDT can be either a destination (via the IB IN
parameters.,
bus)

source

for

the

bus.

The ALU is used to perform general purpose arithmetic and

operations.

logical

It interfaces directly with the IR bus where it may

serve as either a

source or a destination.

The
The CS in the PP can be read or written from the DP IP bus.
CS can be a data source via the MD bus, or a data destination via
IB bus.

the

The MD bus can access other miscellaneous data (e.g., selected
registers, microword field) which then becomes the data source for
IB

the

1.4.4

bus.

CMI CIPA Interface Module (CCI)

The basic function of the CCI module is to interface the C1750

with the VAX-11/750 CMI bus.

All CMI protocol and timing must be

followed while transferring data to and from the CMI.

XMIT

(transmit)

for data

and RCV

transferring

(receive)

files act as

through the CI750.

isolation buffers

The CMI side of the

files are loaded and unloaded under CMI timing and control while

DP side of

the

microcode

port

microcode

the

control.

initiated

1loads

files

are

operation

command-address

loaded and unloaded under CI750
(CI750

data

CMI

from the

bus

master),

the

the DP into the

The command-address data routes from the CIPA
CMC/ADR register.
bus to the CMD/ADR register via the LTCHD CIPA D bus.

also

loads CI write data

from the

the

operation,

write

specified

data

command-address

the

microcode

LP into

the XMIT file

Up to four data longwords can be stored in the
via the same path.
The microcode then signals the CCI that write data 1is
XMIT file.
Upon being signaled by the microcode, the
ready in the XMIT file.
When the CCI has won control of
CCI arbitrates for the CMI bus.

the CMI bus, the command-address data is unloaded from the CMD/ADR
register

onto

the

CMDADDR

bus.

The

command-address

data

1is

the

controlled and timed

from

selected by a mux and coupled to the CMI DATA lines on the CMI.
The XMIT file is then unloaded onto the CCI XMIT DATA bus where it
The data from the XMIT
is mux selected for the CMI DATA lines.
file

1is

written

command—-address

the

data.

the

CMI

The

address

transfer

to the

CMI

specified

data

from

the

CMD/ADR

bus.

If this is a port initiated read operation, the CMD/ALCR register
is loaded, the microcode signals the CCI that the command-address
the
and
the CMI bus,
for
the CCI arbitrates
data is ready,
The CCI then takes
command-address data is placed onto the CMI.
the read data off the CMI DATA lines and loads it into a Receive
Up to four data
Write Data Register and then into the RCV file.
longwords can be

stored

the

RCV file.

The

transfer of

the

read

data from the CMI to the RCV file is controlled and timed from the
The microcode is notified that read data 1is in the RCV
CMI bus.
it proceeds to unload the RCV file onto the CCI RCV
whereupon
file
DATA bus.

The data

Note the reversal
terms

from

out

how

they

the

were

used

CIPA bus.

"transmit" and "receive"

in orientation of the

the

other

the

CI750

modules.

had been used in the sense of transmitting

"transmit"

Previously,

data

is then coupled to the DP via the

bus,

and

"receive"

sense

receiving

In the CCI, "transmit" is used to indicate
data from the CI bus.
to the CMI bus, and "receive" 1is used to
data
of
the transmission
Hence, the file used
data from the CMI.
of
indicate the reception
the XMIT file because this
Likewise, the file used to

to hold data received from the CI 1is
data is to be transmitted to the CMI.

hold the data to be transmitted to the
this data was received from the CMI.

The

CCI

module

Both

reads

provides

for

CPU

access

the

registers via unsolicited CMI transfers (CI750

unsolicited
Receive
files,

and

Write

writes

operations,
Data

transfer

When a CP register

CIPA bus

and

lines

the

registers

Return

are

is being

read,

the

loaded

data.

into

the

used

the

Return

can

Read

Data

instead

many

CCI

performed.

Pata

because

and

is CMI bus slave).

read data

Read

RCV file

Dur ing

and

the

and

RCV

XMIT

taken

from the

the

LTCHD CIPA D bus.
The read data is then unloaded onto the CCI
XMIT DATA bus and then mux selected for transfer to the CMI DATA
on

CMI

bus.

when a DP register is being written, the write data is taken from
the CMI DATA lines on the CMI bus and loaded into the Receilve
The write data is then unloaded and passed
Write LCata Register.
to the CCI RCV DATA bus.

the DP via

the CIPA bus.

From here the write data is coupled to
|

Another function performed by the CCI module 1s requesting
interrupts of the host CPU when service routines must be run on
the

CI1750.

l1.4.5

C175¢ Power

(Figure

1-5)

in the
power for the CCI module is obtained from the power system
ground
the
The +5.0 V operating voltage and
host CPU cabinet.
1is

the UBS

UBS ACLO and UBS DCLO signal a power-up or
1-1).
condition within the CPU cabinet according to power

system

return are obtained from the card cage backplane as

in Table
ACLC and UBS [CLO (see VAX-11/750 documentation listedpower—d
own
protocol.

Power within the CIPA cabinet (CI750-C)

is supplied from an H7202D

Power Supply containing an H7200 +5.0 V Regulator and an H7216
The supply receives 120 Vv, 60 Hz from a
-5.3 V Regulator.
switched outlet on a power controller located 1in the cabinet. The
supply provides +5.0 V to the three CI750 modules located in the

A
.
CIPA cabinet (DP, PB, link) and =-5.3 V to the 1link mcdule
supply.
the
to
back
module
each
groundéd return is provided from
to signal
The supply also provides ACLO and DCLO to the DP module
.
cabinet
CIPA
the
within
ion
condit
down
a power-up or a power-

supply to the three
Power signals and voltages pass from the powér
Figure 1-5
backplane.

CIPA modules via the CIPA card cage
illustrates the routing of the power signals and voltages.
A description

the

H7202D

power

supply

contained

1in

the

that

the

engineering specification listed in the table of related documents
Also listed as a related document is the technical
(Table 1-1).
description manual for the H7202B power supply. This document 1is
applicable

to the

H7202D supply when

1s considered

removed
H72020 is an H7202B with the H7211 communications moduletor
(the
regula
H7216
the
with
d
replace
and the H7213 regulator
t
curren
their
being
tors
regula
two
the
basic difference between
ratings).

1-13

CIPA

HOST
CPU
CABINET

(vax-u/ ns4)
CCI

ABS

C45

PR MODULE

LINK MODULE

RTN $5.¢V -5,3V

RIN +5,8V.

T A1 33T T 7 BackPLANE ] 34 |75 |

ey
FROM

PP MODULE

OBRIP 9BS

BBS RIN 4sgv
9

(CI 75'¢-C)

ACLO &io RTN +5.gv

MODULE

Q93

CABINET

B 2

Cl]:E}-——'

3¢—/ L

CPU

POWER SUPPLY

l,lJ{ 1J2

34—-/_/

ri-l

|+5.¢V

=33V

|_PCLO

+5.0v RETURN

___ACLO

(

oUTLCTINCasmer|10 v. e

Figure 1-5

WITH H72¢0¢ +5v REGULATOR

H7292D

POWER SuPPLY

AND HF216

CI750

-5,3v REGULATOR

©Power Cistribution

CHAPTER
LINK

MODULE

NOTE

The
2

functional

use

does

logical
not

block

diagrams

AND

and

necessarily

corresponding

gate

exists

Chapter

symbols.
on

that
the

1link

logic
~and
may

prints. The assertion of inputs A
B causing the assertion of output C
be represented on a block diagram by

single

AND

drawing

may
stages
are
operation.

gate,

yet

show
that
1involved

the

engineering

several
in
the

circuit
ANDing

The
functional
block
diagrams
in
this
chapter
are
keyed
to
the
link
engineering
circuit
schematics
(CS
prints)
by
letter
designations
in
parentheses.

The

letters

specify

the

link CS sheet that contains the detailed
logic
associated with
the
functional
blocks

the

diagram.

The signal names used in the functional
block diagrams are the names used on the
engineering
CS
prints.
Where
other
signal names or notes are used, they are
enclosed

2.1

PACKET

Formats

the

FORMATS
two

types

(acknowledge/negative
2.1.1

packets,

acknowledge),

are

information

described

2-1A
information
the

Packet
illustrates the format of an
packet
1is
wused
to
transmit

CI.

Parts

the

packet

are

generated

passes

through

the

2.1.1.1

Synchronization
-The
first
bit synchronization within the

Bit
are

for

hexadecimal

packet

which

the

bit

sync

five
link.

the

link

1link

and

bytes
of
The bytes

the
are

an alternating pattern of 1's and 0's used
detect
circuits
and
to
synchronize
the
to the receipt of useful data.
The
1link

to
turn
on
the
carrier
Manchester decoder prior

inserts

ACK/NACK

information packet.
The
both messages
and
data

inserted
into
transmitted.

packet

and

below.

Information

Figure
across

parentheses.

bytes

into

the

packet.

31T SYNC (55 HEX)
(GENERATED

OR USED
BY LINK)

(LOADED OR

READ BY PORT

PROCESSOR)

FIRST BYTE
TRANSMITTED

BIT SYNC (55 HEX)

B8IT SYNC (55 HEX)

BIT SYNC (565 HEX)

BIT SYNC (55 HEX)

B8IT SYNC (55 HEX)

CHAR SYNC (96 HEX)

PACKET TYPE/LENGTH (HIGH)

PACKET LENGTH (LOW)

DESTINATION (TRUE)

DESTINATION (COMPLEMENT)

SOURCE

SOURCE
CRC-0

BODY

CRC-1

CRC-0

CRC-2

CRC-1

(GENERATED

OR USED
BY LINK)

CRC-2

CRC-3

TRAILER (00 HEX)

A. INFORMATION PACKET

8. ACK/NACK PACKET
MKV84-1871

Figure 2-1

Packet Formats

FIRST BYTE
TRANSMITTED

synchronization byte
start of useful data

(96 hexadecimal)
is
in the packet. When

character

The

Synchronization

Character

2.1.1.2

used to
the sync

1indicate the
character 1is

recognized during packet reception, it starts the framing of the
serial
data
into
eight-bit
bytes.
The
1link
1inserts
the
sync
character

into

the

packet.

2.1.1.3
Packet Type/Length (High) -- The packet type and length
(high)
byte
specifies
the
type
of
packet
(information
or
acknowledge) and contains the upper four bits of a 12-bit packet

length
word.
Bits
<7:4>
are
the
information packet bit
7 is a 0
(1
bits

<6:4>

Bits

<3:0>

are

the

12-bit

packet

the

body.

packet
type
bits.
For an
for an ACK/NACK packet)
and

are 0's.

the

upper

four

bits

the

12-bit

word

that

specifies the packet length. Information packets are of variable
length in one-byte increments up to 1K bytes* with the minimum
packet length being seven bytes. The packet length specified by
type
*

length

word

capacity

(high)

length

and

Limited

the

capable

processing

byte

includes

and

the

packets

all

buffers

data

including

the

from

the

packet

the

last

byte

PB.

The

1link

to 4K bytes,

The port processor supplies the packet type and length (high)
as

part

the

byte

packet.

2.1.1.4

Packet Length (Low)

this

-- This byte

contains

the

low eight

bits of the 12-bit packet length word. The port processor supplies
byte

part

the

packet.

2.1.1.5
Destination (True and Complement) -- The destination 1is
the eight-bit address of the CI node to which the packet 1is

transmitted. There are two destination bytes; the first being the
true node address value and the second being the complement of the
true value. The port processor supplies the destination bytes as
part

the

packet.

Redundant destination addresses are used to preclude a single
logic failure bringing down both paths on the CI bus. With a
single

address

decode

circuit,

failure

which

caused

node

1in both nodes
result
address might
another node's
decode
This would
transmitting an acknowledge packet at the same time.
result in a collision on the CI bus and would be seen as a "no
response"

the

transmitting

node.

2.1.1.6

Source

sending

node

and

The

provided

source

1is

the

port

eight-bit

address

the

processor

part

packet.

2.1.1.7

Body

protocol

information.

the

The

body

The

contains

body

the

data

supplied

and

the

port-processead

port

part

packet.

2.1.1.8

Cyclical

Redundancy

Check

(CRC)

Bytes

Following

the

body are four CRC bytes generated by the CRC 1logic in the link.
During a packet transmission, the packet (starting with the packet
type

and

length

generates

are

the

expressed

packet

data.

generated
During
An

Each

byte),

32-bit

CRC

word

input
CRC

longword
1s

into

the

CRC

polynomial.

that

unique

for

the

1logic

The

which

coefficients

function

the

packet

that

regenerated

and

specific

1it.

packet

compared

(high)

coefficients

reception,

the

error—-free

four

packet

CRC

the

bytes

results

CRC

1longword

generated
a

match

1is

during

between

the
the

transmission.
two

longwords.

2.1.1.9
Trailer -- The trailer consists of six bytes of all
It is used to insure that all bits of a received packet have
shifted
senses

into

the

2.1.2
Figure
and

through
the

packets

collision

node

(CRC

front

end

before

reception.

successful

buffers

packet,

the

sent

that

the

The

the

carrier

detect

link

inserts

the

logic

trailer

the

packet

receiving

arrived

node

successfully

PB,

transaction

the

transmitting
could not be

were

node

without

Packet
packets.

data

ACK

inform

the

loss

bus

into

the

OK).

bus

negative

packet.

are

checked

receiving

buffers

the

1link
packet

Acknowledge/Negative Acknowledge (ACK/NACK)
2-1B
1illustrates
the
format of ACK and NACK

NACK

the

packet.

transmitting

the

end

2's.
been

ACK
and

full

1is

storage

and,

acknowledge

accepted

packet

the

therefore,

(NACK)

packet

node
that
the
packet
was
accepted. The transmitting

the

packet

returned
PB.

indicating
the

receiver

unable

the

inform

the

sent

successfully
received but
node must then retransmit

The
the

entire
link.

ACK

(or

NACK)

packet

An
ACK/NACK
packet
differs
following three ways:
A,

has

are
no

the

packet

from

generated

and

information

transmitted

packet

It
has
no
body.
An
ACK/NACK
packet
only
reception of an information packet.
It does
messages

data

packet
same

type

packet

length

(low)

packet type bits
length
(high)
byte

(high)

=
an

for
NACK

acknowledges
not transfer

ACK

byte

and

bits
are

NACK

packets

<3:0>

the

and

there

0's

byte.

Bit
7
=
1
indicating
information packet)

for

All

(bits <7:4> of
specifies
the

follows:

word.

Consequently

length

The

Bit 6

the

such.

length.

and

the

packet

and

type

ACK/NACK

packet

type
packet

for

ACK packet

packet.

2.2

LINK OVERVIEW
1link
(Figure
2-2)
1is
functionally
divided
into
a
receive
channel and a transmit channel with a CRC function shared between
the
two.
The overview briefly describes
the
following
four
1link

The

operations

with

the

they

would

for

the

operations

are

described

and

following

and

receive

type

they

would

channels

The

reception

information

packet

The

transmission

C.
D.

packet

The
The

transmission
reception of

of an information packet
an ACK/NACK packet

control
link

transfer

logic

receives

operations,

data

being processed.
The
occur with B
following A

Link

functioning

packet

start

CLK)
time

transmit

specific

and

packets

ACK/NACK

commands

senses
through

from

signal
the

the

port

select

and

conditions

control

the

link.

receive

and a transmit clock (XMIT CLK) are generated
operations in their respective channels.

clock

the

(RCVR

link

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Information Packet Reception
2.2.1
Data packets on the CI bus are in serial format at a serial bit
rate of 70 MHz. The data is Manchester encoded (phase encoded)

wherein the clock is incorporated into the modulated signal.

CI paths A and B are input to a RCVR select multiplexer (mux)

1in

the link front end. Carrier detect logic monitors both CI paths.
Wwhen the logic senses the initial presence of a carrier on one of
the paths and if that path has been enabled by the port, it
switches the mux to the active path, selecting CIA RCVR or CIB

RCVR for the Manchester decoder. The port may also select the
internal loop path wherein the mux selects the output from the
transmit channel and loops it back into the port. This feature is
used for maintenance operations.

The mux output is applied to a Manchester decoder where the signal
The
and

clock is extracted from the modulated signal.
decoder outputs the data (RCVR SERIAL DATA)

(MDECODER CLOCK)

sync

character

Manchester
the clock

to the byte framer. The byte framer contains the

detector.

to parallel conversion of the
The byte framer performs serial
by the sync character detector
enabled
is
signal data. The framer
the sync character.
recognizes
it
which activates the framer when

when enabled, the byte framer ouputs a data byte (RDAT <7:0>) for
every eight serial bits received from the Manchester decoder. A

RCVR CLK generator develops RCVR CLK which times the transfer of

data through the link receive channel. SYNC from the byte framer
synchronizes RCVR CLK with the data bytes so as to occur
approximately centered on the asserted time period of RDAT <7:0>.

The RDAT <7:0> data bytes are coupled to the RCVR output register
and

then

The

link

verifies

into

the

node

comparing

the

destination

RCVR

that

packet

address

compare

DATA

the

<7:0>.

destination

switches.

logic.

packet

bytes

The

1is

node

is made

1in

node

the

comparision

match

this

for

meant

not

receiver is cleared and reception is terminated.

address

obtained,

set

the
the

The packet source byte is extracted from the incoming packet and
placed into the ACK destination register. When the link transmits

an ACK packet in response to the information packet now being
received, it will use the address in the register (the source of
the information packet)

as the ACK destination.

The packet bytes extending from the packet type and length (high)
byte up to and including the last byte of the body, are applied to
the CRC checker. The bytes are acted on by the CRC algorithm which
generates the 32-bit CRC 1longword.
The four CRC bytes
1n the
packet are compared to the generated longword and 1f the
free of error, CRC STATUS is asserted to message receive

packet
logic.

After the packet trailer has passed through the 1link front end,
the carrier detect logic senses the end of the packet and informs
the ACK transmit logic. The ACK transmit logic then initiates the
transmission of

an ACK packet.

ACK/NACK Packet Transmission

2.2.2

ACK/NACK

The

link

and

link.

packet

No packet data

enabling

ACK

transmit

generated
received

logic

the

sync/trailer

type

logic

sync

character

byte

and

from the

initiates

PROM

onto

which

the

as XMIT DATA

transmit

outputs

five

the

XMIT

DATA

enabled

and

outputs

<7:0>.

operation

bit-sync

bus

the

entirely

transmitted

(XMIT

bytes

DATA

BUS

<7:0>).

The

ACK

then

the

packet

type

byte onto the XMIT DATA bus. The logic sampled the state of PB
signal RCVR BUFFERS FULL at the start of the information packet
If RCVR BUFFERS FULL was true, the PB was not able to
reception.
In this case, the
accept the information packet Just received.
ACK type logic outputs the code for a NACK packet. If RCVR BUFFERS
FULL was false, the logic outputs the code for an ACK type packet.

the ACK
of
output
the
enables
then
1logic
control
1link
The
destination register which outputs the two destination bytes onto
The destination value used 1is the source
the XMIT DATA bus.
address

The

taken

ACK

from

source

address

from

source

byte.

the

information

then

1logic

node

address

packet

enabled

switches

Jjust

received.

and

transfers

the

XMIT

the

DATA bus

node
the

The ACK/NACK packet 1is transferred to the BUS TDATA bus via the
XMIT data register.
The packet,
starting with the packet type
byte, has also been input into the CRC generator where a 32-bit

CRC longword is generated.

After the source byte has been input to

the

CRC

BUS

generator,

link

bus

inserted

into

the

ACK/NACK

Finally,

the

ACK

transmit

which
the

outputs

ACK/NACK

six

the

TDAT2

byte

trailer

packet.

control

gates

the

re-enables

the

time.

The

four

CRC

longword

onto

sync/trailer

PROM

CRC

bytes

are

thus

packet.

logic

bytes

onto

the

XMIT

DATA bus

complete

TDATA bus is applied to the XMIT
The ACK/NACK packet on the BUS orms
parallel to serial conversion
serial shift register which perf
and then
s are input to the register
of the signal data. Data byte
SERIAL
XMIT
as
der
enco
er
shifted out serially to the Manchest
ster
regl
The
MHz.
79
the serial data 1s
DATA. The bit rate ofXMIT
data
of
sfer
tran
the
s
time
CLK which
logic also generates
with
ized
hron
sync
is
through the link transmit channel. XMIT CLK
the serial data within the shift register.

where
ied to the Manchester encoder
The XMIT SERIAL DATA 1s appl
a
uce
prod
to
data
al
seri
the
the bit rate clock is combined with
the
uts
outp
der
enco
er
hest
The Manc
phase-encoded carrier.
logic
to the CI bus. The ACK transmit
DATA)
(ME
ier
carr
d
nodulate
packet Jjust
used Dby the informationloop
selects the same CI path
path into
rnal
inte
an
ow
foll
received. The ME DATA can also
is 1in internal loop mode and the
the receive channel if the link are
disabled. This feature is used
receiver inputs from the CI bus
for maintenance testing.

2.2.3

Information Packet Transmission

rated by the port and input to
An information packet is mostly gene
packet
the link transmit channel from the PB. The information

bytes that are inserted by the link are:
A.
B.
C.
D.

The
The
The
The

five bit-sync bytes
character sync byte
four CRC bytes
six trailer bytes.

the
et utilizes only some of are
Transfer of an information pack
that
s
tion
func
The
2.
2.2.
functions described in Paragraphibed.
used operate as previously descr

transmit
smit operation via the message
The port initiates the tran
enables
link
the
d,
operation 1is initiate
logic. When the transmit
uts five bit-sync bytes and a sync
the sync/trailer PROM which outp
DATA bus.

character byte onto the XMIT

th (low)

(high) byte and the packet leng
The packet type and lengthport.

byte are provided by the

When the
also provided by the port.ente
The destination bytes are the
rs the
link
the
XMIT DATA bus
destination bytes are on the ACK
the
When
c.
logi
ate
source comp
destination address into 1s received
the
,
node
et
targ
the
from
ACK/NACK response packet
the contents of the compare
packet source byte 1s compared with
logic. If the correct node responded, a match will be obtained.

The
source
byte
is
inserted
by
address
source
1is
the
link
node
address

DATA

bus

the

PB.

from

the

The

source

byte,

CRC

generator

functions

for

ACK/

has

transmission.

body

Finally,

NACK

which

the

PROM

XMIT

bus

2.2.4
of

the

Reception.

The

With
regard
between
the

then,

produce

not
by
the
1link.
which
output
the
is

message

Packet

ACK/NACK

input

four

the

CRC

the

bytes

XMIT

just

1information

CRC

The
node

packet

generator

and

re-enables

the

longword.

transmit

logic

six

information

trailer

bytes

onto

the

packet.

Reception

through

described

functions

the

outputs
the

the

However,

input

generation

complete

functions

also

which

ACK/NACK

Transfer

1link

sync/trailer
DATA

PB,

PB.

The

contributes

the

switches

also

to
the
1link
reception
of

the

receive

Paragraph

operate

channel

2.2.1,

utilizes

Information

previously

most

Packet

described.

receive
channel,
the
basic
difference
ACK/NACK packet
and
an
information
packet 1s in the handling of the packet source byte. The source
byte
1is
not
entered
into
the
ACK
destination
register
but
is
applied to the ACK/NACK source compare logic.
The source compare
logic
presently
contains
the
destination
address
of
the
information packet just transmitted.
The source byte
1s compared
to

the

nodes

destination

are

involved

2.3

address.

the

LINK OPERATING

Paragraphs

2.4

and

2.5

The

data

address

will

match

the

correct

transfer.

STATES
provide

detailed

operation
of
the
receive
channel
and
Control of the hardware is a function

description

transmit

channel

the

hardware.

of commands from the port,
the type of operation being executed, and conditions sensed by the
logic
(e.g.
errors)
during
the
operation.
Hardware
control
is
implemented
via
programmable
array
logic
(PALs)
which
define
various
hardware
states
during
each
operation.
The
states
are
represented
set.

2-1

The

and

four

operations

described

diagrams

contained

described

Paragraph

2.10.

the

diagrams

engineering
are

shown

drawing
in

Table

Table 2-1

Link State Diagrams

Number of States

Information Packet Reception

ACK Packet Transmission

Information Packet Transmission

ACK Packet Reception

Operation

2.4

RECEIVE

CHANNEL

Figure 2-3 is a block diagram of the
referred to throughout Section 2.4.

receive

channel

and

should

The

receive channel hardware contains both transistor-transistor
(TTL)
1logic and open collector emitter coupled logic
(ECL).
The
carrier detection/path selection logic, Manchester decoder, byte
framer, and sync character detector all use ECL logic. ECL has an
active

high

and

different

description
2.4.1.2

2.4.1

non-active

low

interpretation
of

the

receive

example

for

Carrier

state

common

lines

resulting

circuit

1logic

than

with

path

those

select

mux

unfamiliar

Detection

and

Path

1is

with

given

ECL

TTL.

Paragraph

logic.

Selection

The carrier detect and path select logic monitors activity on the
CI bus and, when activity is detected, selects the active path as
an input to the link receive channel. The port uses port and link
control PALs to specify which receive channel(s)
are allowed to

receive

signal

channel(s)

2.4.1.1

inputs

Carrier

monitors

paths

carrier detect
port

has

asserts
the

and

carrier
such

select
ICCS

mux

PAL

PATH

state

outputs

that

the

CLK

which

FORCE

PATH

been

and

corresponding
When the port

for

the

port

FORCE

and

maintenance

path

input.

PATH

from

1link

loop

1is
the

as
to

control

(INT

MLOOP)

flip-flop
DET

the

and

the

port

1is

carrier

receive

the
the

longer

the

reserved
ACK

SELECTED

state

negated

path

select

similar

link

1in

clocked

carrier
receive

RCVR

detect

channel

A
1is

sensed.
logic

control

path
selection
from
the carrier
commands a message
transmission,
receive

flip-flop

soon

input

the
CDET

PATH

input.

the mux

transmission

preparation

The

for

the

1logic

A,
A

state

opened,

path

ICCS

existing

detect

presence

sensed

asserted

flip-flop.

CARRIER

receive

parallel

outputs

flip-flop
the

and

true),

PATH

carrier

the

ENABLE.

present

ICCS

the mux

the

enable

1Identical

asserts

for

once

path

the

may

path A

closed

Thus,

activity

DET

SEL

resets

PALs

RCVR

ENABLE

flip-flop

asserted

negates.

Had

The

carrier detect A

(RCVR

PATH

output

selected

carrier

channel

receiver

the

bus.

ENABLE

the

PAL.

RCVR

select CI

Note

sets

The

receive

CARRIER

CLK.

Logic

channel

causes

select

that

A logic

RCVR

the CI

RCVR

Detect

and

enabled

from

asserting

the

would

logic

have

force

select
state
PAL.
the path selected

receive

channel

1in

response.

PALs

can

wherein

also
ME

select

DATA

from

the

internal

the

transmit

channel is selected for the mux input. The true state of INT MLOOP
inhibits both RCVR PATH A and RCVR PATH B which causes the mux to
select

the

DATA

input

signal.

(FI1G. 212)
A

{

(F1G

CNODE ADDRESS 3.0~

2 20) 4

{

CNODE
ADDRESS
<70

~7:0.

ACK

ACK SGURCE CMP

SUURCE

COMPLEMENT

NODE ADR Sw

(FIG.

(N)

—

230

( FIG ) AR STATE B ’ D
SWAP TRUE,

Fii 2 2m <2

~OMmP

CHECKER
L

TACT

TOST CMmP

1 ‘228’TRUE

aC LN

Che

MR STATE C

{FIG. 2 18)

TRUE NODE

ADR SW

NODE

ADDRESS

30.-

3530

(F1G 2 28) @—

22D

COMPLEMENT

COMPARE

MUDECODER CLUCK

{F)

RCVR

PARITY

e———J

<70 -

RCVR

RCVR CLK

{F1G. 210)
-

HTO
2

30)

FORCE

CHAR

PATH

’

CAKRIER

FORCE PATH B ( (FI1G 221

2 29)

FEIG

21822y

228.230)

DET 8

ICCS
PATH
d
CHAR SYNC

|gxT SYNC

EIG

9K+

SELECTED
-

1CCS
PATH B

{(FIG 2 29)
e

STATE
PAL

(

F:E

¢ bae

C o

;jt,)

o
ICLS PATH

CAHRRIEK

DET A

CDET

)

—

]

)
HOVR CLK

—

SET

Oe T

HCVR

CLK

RCVH A ENABLE

RCVR B ENABLE

_°< }

(S)

RCVR A ENABLE
I

°T1
¥

PARITY

carn

(S)

DET

CARRIER

(FI1G. 226.39)

221,

(S)
'h

VALID RCVR PARITY ( FIG )

(S)

)
SELECT
EL

(FIG 228.2 30

[—

‘GFE)N

‘

JETECT

()

g%i

CARRIER

JeTECT

ENA SYNC

CiK

GENERATOR

SYNC

(FIG

DET

RCVR

DATA

PARITY

P_Al:

SYNC

[

DETECT

BYTE
(FIG. 2 7)

END

ENABLE

REG

(F)

DATA

DET

RUAT

DATA

MSG
SEL

[\CIBUS

ENA SYNC

DATA

<70~

FPATH

FROM )

RCvR

(FIG.

RCVR

SERIAL

RDAT

ROV

CIA

RCVR

REG

OUTPUT

(Fic. 2-12

»
g
HCVR FATH SEL B

228

REG

3 E CiB

MDECODER
CLOCK

REG

RCVR

MEDATA

PRECS

—(F1G 2 28)

FoAT

[

ARSTATE f

RCVR

arsTATEC ) D

FIG

L—

I
(FIG,)

RCVR DATA
6

(J)

(FSF)

)

:
MHSIATED

DECOUDER

2307

]
.

(Hu. MR STATE D

RDAT REG 7

(H1G 2 28.2:30)

Dje

(D)

G 3 3) e——

FIG

DESTINATION

(K}

(FIG 2 20) -

S Cmp l

‘

(FIG. 2 30)

COST CmP

‘
DESTINATION

ADDRESS

——

_—— ——

CD(iMPARt

NODE

CRC STATUS I

HCVR B

ENA INT MLOOP

ENABLE

(FIG.

2 21)

INT ML OOP
(M)

MX STATE A
(FIG. 2 25)

NUTE

Ir Bo20

LETTER DESIGNATIONS IN PARENTHE
SES
HEFER TO ENGINEERING DRAWINGS

CONTAINING CORRESPONDEING LOGIC.

Figure

2-3

Receive

Channel

Block

Diagram

e path
eiv
rec
The
-ic
Log
ECL
==
Mux
ect
Sel
h
Pat
e
eiv
. Thea
.1.2 Recis on sheet 5 of the engineering drawing set
2.4
in
bed
cri
select muxoperat
des
y
all
usu
not
is
ic
log
t
cui
cir
of
ion
of theto mux
detailed
ration
the ope
r, ECL
ual, ehowofevethe
in
criptiasonanmanexa
l desher
ed
err
ref
functiona
ic
log
mpl
e
bed
is descri
Paragraph 2.4.
output R ofPATORH
the
e,
tru
is
A
SEL
H
PAT
R
RCV
If
.
2-4
ure
Fig
to
RCV logic,
Refer A can follow the CIA RCVR signal input. The signal ECL
gate false which holds the output of OR gate B low. 1isIn the active
R issignal low is the non-active state and a high
a
can pull the line up to

line ctive (low) while OR
nected togata ecomB mon
gate conThu
state. Any
ina Manchester decoder.
is heltod the
state. the s,CIAOR RCVR signal
ive nsf
the e act
gat A tra teersof RCVR PATH SEL A also holds the LOOP OR gate in
e sta
The tru
the inactive state.
e A
, OR gat
se)
fal
A
SEL
H
PAT
VR
(RC
e
tru
e
wer
B
SEL
H
PAT
wou
R
e B ld
If RCV
gat
OR
and
ve
cti
ina
d
hel
be
ld
wou
e
gat
OR
P
LOO
the
and
ster decoder.
function to transfer CIB RCVR to the Manche
SEL
H te.
R vePATsta
RCV
h
bot
ed,
ect
sel
is
op
1lo
ce
nan
nte
mai
al
ern
cti
int
the ina ME DATA to
If the
A and B intra
g OR gates
false holdin
signals are
nsfers
and
ive
OR gate 1s nNOwW act
LOOP ode
However,chethe
r.
ster dec
the Man

2.4.2

Manchester Decoder

e 2-5) 1sfora
gur
(Fi
ng
odi
enc
se
Pha
-ng
odi
Enc
se
pha
1
2.4.2.
al occurslevel
nal phadse asrevaerspos
hniqueatiinon.whAic"1"ha sig
tion oftecinf
itive as a
modula
is define a "o" is def
orm
ined
each bit by a neg
le
tion, whitra
transipos
ative by
reversals
se
followed
Pha
n.
ve nsitio
ed a ce iti
el followoOr
or
1's the
ve
negative levdat
uti
sec
con
e.
rat
a
dat
the
twi
at
e
rat
a
ce x
at the
ur atcautwi
are sec
als toandocc0's
se phaseternrevaters
will cauA).
flu
se
con utive 0'sgur
e 1's
Al
e 2-5

e to(Fi
rat
ta
da
occur at the data rate (Figure 2-5B).
reversals

(

CIA RCVR

RCVR PATH SEL A DO:DO—

F'G-)J
(2-3

ME DATA
RCVR PATH SEL B

—3

—

LOOP

—» (FIG. 2-3)

CIB RCVR

NOTES:

THE LOGIC IN THIS FIGURE IS CONTAINED
ON SHEET S OF THE ENGINEERING DRAWINGS.
|
TK-8614

Figure 2-4

Receive Path Select Mux-ECL Logic

B. ALTERNATE 1s AND Os

A. CONSECUTIVE 1s AND Os

Figure 2-5

S
TK-8600

PE (Phase Encoded) Data

Decoder Logic -- The Manchester decoder decodes the
2.4.2.2
encoded signal data by separating out the 70 MHz bit rate clock
(MDECODER CLOCK) leaving the serial data (RCVR SERIAL DATA). The
decoder consists of a flip-flop with the signal data from the
receive path select mux as the D input. The flip-flop clock input
is derived from XORing the delayed output of the receive path
(delayed

mux

select

flip—flop.

10.7

ns)

output

the

with

the

decoder

Figure 2-6 illustrates the action of the decoder logic. The signal
data from the receive path select mux 1is shown with 1 or 0
transitions at the center of each bit cell. With a 70 MHz bit
rate, the width of the bit cells is 14.28 ns. The output of the
delay line is seen as the signal data delayed 10.7 ns. XORing the

data with

delayed

the

(RCVR SERIAL DATA)

flip-flop output

generates the MDECODER CLOCK waveform. Note that in the case of
alternating 1's and 0's, the width of the MDECODER CLOCK pulse 1is
the set and reset times of the decoder flip-flop. In the case of
consecutive 1's or 0's, the clock is identical to the inverse of
the

data.

delayed

The MLDECODER CLOCK is at 70 MHz with a 14.28

ns period.

The XOR

action serves to generate the clock's rising edge 1/4 into each
bit cell. This centers the rising edge in the valid
(first half of the bit cell).

strobe area

sync Character Detect Enable PAL

2.4.3

assert
The purpose of the sync character detect enable PAL 1s d.to The
PAL
expecte
1is
packet
a
when
framer
byte
the
to
ENA SYNC DET
DET
monitors CARRIER DET A and CARRIER DET B and asserts ENA SYNC PAL
when it senses that a signal carrier is being received. The
negates ENA SYNC DET during node transmissions (FORCE PATH A,
FORCE

PATH

transmissions.

The

the

link

PAL asserts

will

not

ENA SYNC

respond

DET

1ts

immediately

information packet transmissions in anticipation of the ACK

NACK)

own

after

(or

response.

The byte framer contains a sync detector which is enabled by ENA

SYNC DET. The sync detector looks for the packet sync character as
a means of recognizing that a packet is being received.

When the

the

detector

detector recognizes the sync character, it enables the byte framer
to

processing

start

the

packet

bytes.

disabled except when a packet 1is
detect PAL prevents the detector
noise

sync

keeping

expected, the sync character
from erroneously recognizing

character.

The sync character detect enable PAL is discussed in more detail
in

Paragraph

2.10.2.2.

111

2-19

Framer

Byte

2.4.4

The byte framer is enabled when it receives the sync character
it then
byte. Once the framer recognizes the sync character,
Manchester
the
from
data
signal
serial
functions to convert the
decoder into eight-bit data bytes for the RDAT bus.
As shown in Figure 2-7, RCVR SERIAL DATA 1s input to the RCVR
serial shift register. The register is held in the load state by
the negated state of E197-R2 (Figure 2-8), thus no data is shifted
into the register. When a carrier presence is sensed at the front
end of the receive channel, the sync character detect enable PAL

If the PAL deems that this

also senses the carrier presence.

1s a

valid time to receive a packet,it asserts ENA SYNC DET to the SYNC

ENA flip-flop. On the next RCVR CLK, the flip-flop outputs SYNC
ENA to another flip-flop which asserts E197-R2 to the RCVR serial
shift register. The true state of E197-R2 enables the register by
changing its state from load to shift. RCVR SERIAL DATA 1s now
shifted into the register at the 70 MHz bit rate by MDECODER
CLOCK. Figure 2-8 illustrates the timing of the enabling of the
RCVR serial shift register.

The RCVR serial shift register outputs eight-bit bytes onto a data

bus. The data bytes are then applied to the RCVR input register.
The sync detector monitors the data on the bus looking for the
sync character byte. When the detector recognizes the sync
it asserts E198-3 to the sync flip-flop. The next
character,
MDECODER CLOCK sets the flip-flop and asserts SYNC to the external
data

framer.

Note that only seven of the eight bits on the data bus are fed
into the sync detector. The eighth bit is taken from the RCVR
SERIAL DATA being fed into the RCVR serial shift register. Thus,
the sync detector recognizes the sync character before the last
next
The
register.
shift
the
into
shifted
is
bit
character
also
register,
the
into
bit
last
MDECODER CLOCK that clocks the
sync

the

sets

character
(Figure

flip-flop.

in the shift

state

RCVR

SYNC

when

asserts

sync

the

later

and not one clock pulse

2-9).

When SYNC asserts,

switch

Hence,

the

(for

SERIAL

RCVR
one

clock

DATA

shift register.

the external

input

pulse)

continues

framer shift register functions

from

every

the

eight

hold

shifted

state

MDECODER

into

the

CLOCK

the

RCVR

load

pulses.

serial

Every eight clock pulses a data byte is present 1in

the shift register and on the data bus. At this time the external
framer shift register switches

load.

into

the

The

the

RCVR

input

from hold

next MDECODER CLOCK pulse then loads the data byte

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The D7 input to the external framer shift register is tied high.
Before the assertion of SYNC, the framer register is in the 1load
state,
hence
the
R7
output
1s
true.
The
true
state
of
the
R7
output keeps the RCVR 1nput register in the load state. When SYNC
asserts, the framer shift register starts to shift. The 1 at R7 1is
shifted in and through the framer shift register.

Every
R7

eight MDECODER CLOCK pulses,

output,

switching

the

RCVR

the

input

shifted

the

through
load

the

state

for

one clock pulse. As seen in Figure 2-9, the timing is such that a
data byte is on the data bus when the RCVR input register is
loaded. The timing for the first three bytes of a packet 1s shown
in

Figure

2-9.

2.4.5

RCVR

Figure

2-10

CLK

Generator

is
a

block

diagram

RCVR

CLK

1is

derived

from

The

RCVR

CLK

pulses

function

the

RCVR

CLK

crystal-controlled
to

time

and

dgenerator.

control

MHz
the

The

oscillator.
operation

the receive channel logic. When a signal packet 1s received, the
RCVR CLK is synchronized to the packet bytes by SYNC received from
the

byte

framer.

The

output

from

the

Manchester

the

MHz

crystal-controlled

doubled to 140 MHz by a frequency doubler.
divided

down

consisting

MHz by four,
=

114.28

Table

2-2

XMIT CLK

ns).

encoder

four

MHz

the

and

flip-flops.

transmit

lists

the

(discussed

frequency

channel.)

then

applied

The

shift

outputing RCVR CLK at a
and

Paragraph

oscillator

The

140

shift

2.5.7)

the

link

included

MHz

1is

the

divides

frequency of 8.75 MHz

period

1is

(The 140 MHz is used in

(period

clocks.

the

The

table.

Pps|

(RESET COND.)

(N)

35 MHZ

) RESET #.SET

RCVR CLK

) (SET

(SET

\cono.)|cono/] Lconp.!|conn.)

<FRAMER )

+»{D SYNC £1539 D SYNC

l
SYNC

'FROM BYTE

2
FIG. 27

CLK

*{CLK

(N)

RCVR TESTCLL'\

(N}

<:> 35 MHZ

TM
[

—

__\ E151-3
(N)

)
EXT SYNC_
—»

. D PwW '_{>0'

(N)

DISABLE RCVR CLK

CLK

(A)

cHA
[SYNC R

) (FIG. 2-3)

RCVR CLK

140 MHZ

~—— / TO MANCHESTER ENCODER

XTAL OSC

70 mHZ | FREQ

(T)

DOUBLER

140 MHZ

70 MHZ

29
\

70 MHZ

FIG. 2:12

(T)

35MHZ

(T)

NOTE:

LETTER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING
LOGIC.
TK-8622

Figure 2-10

Table

Frequency

(MHz)

Period
14,28

RCVR CLK Generator

2-2

(ns)

Link

Clocks

Clock
MDECODER

28.57

114.28

RCVR

CLK

114,28

XMIT

CLK

CLOCK

The

functions

chain.

When

three

flip-flops

are

ANDed

the

chain.

the

1low
are

together

clock

The

shift
in

set.

pulse

cycle

to
1s

then

low

through

rightmost

Outputs

condition

thus

logic

the

from

the

three

flip-flops

set

flip-flop

the

flip-flop
the

the

first

re-inserting

the

flip-flop,

low

into

other

reset

the

flip-flop

repeated.

The
left
and
right
portions
of
Figure
2-11
illustrate
the
operation
cycle
of
the
shift
register.
(The
center
portion
illustrates the synchronization function.)
Waveforms 1, 2, 3, and
4 relate to the corresponding points in Figure 2-10. Also shown is
the

MDECODER

periods

These
as

three

they

CLOCK

that

the

and

RDAT

signals

appear

SYNC

<7:0>

are

the

from

time

byte

the

bytes

byte

are

framer

timing

framer,

the

RCVR

each

other

diagram

and

the

input

time

and

are

(Figure

shown

2-9).

The

35 MHz clock and the shift register waveforms are time related to
each other but are independent of the byte framer timing. The SYNC

signal
1s
used
to synchronize
the
action
with the data bytes from the byte framer.

shown

are

set

1in

MHz

clock

sets

E151-3,

thus

forming

E151-3

pulse

condition

three

Figure

the

2-10,

MHz

when

clock

pulse
an

E151-3

the

first

The

turn

(PwW)

pulse

the

flip-flop

asserts,

1in

width

synchronizes

flip-flops.

SYNC

which

MHz

clock

two

assert

shift

sync

flip-flops

E151-3.

The

flip-flop

which

the

set

shift

forcing

condition

pulse

places

the

negates
The

reset

the

other

into the conditioned state which is to introduce a logic low into
the first flip-flop. Thus, regardless of where the register was in
its cycle, it is restarted at the beginning of the cycle.

The assertion of SYNC
in Figure 2-11.
Note
register by
clock pulse

followed by the assertion of El151-3 is seen
that
the
conditions
forced
onto
the
shift

the E151-3 pulse
are clocked
in
(the first flip-flop is reset and

by the
next 35
the other three

MHz
are

set). As seen in Figure 2-11, the logic low had reached the second
flip-flop when the register cycle was
interrupted and reset back
to
in

its starting point. The register
synchronization
with
the
byte

generation of RCVR CLK
period when the packet

cycles
frame.

from this point on
This
results
in

are
the

pulses approximately centered in the time
bytes
(RDAT <7:0>)
are
in
the
RCVR
input

The

CRC

packet

Check

bytes

bytes, are input
the checker, the
state
packet,

1logic,

the

RDAT

bus,

and

including

to the CRC checker.
If no errcrs
checker asserts CRC STATUS to the

1indicating

the

reception

the

four

CRC

are detected by
message receive

wvalid,

error-free

OH_‘O

060

060
MDECODER

CLOCK (70 MH2)

/
E153 0

—_ — 4

SYNC

— |-

35 MHZ

EXT SYNC

O—_r
L1
®
®

@__J

-——‘

—

RCVR CLK

(8.75 MHZ)

1T
1 J
SN R
I eH e
LI

L1
—
RDAT «.7:0>

iN RCVR INPUT REG.
FOR THIS PERIOD.

LAST BIT OF SYNC CHARACTER BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER
SYNC CHARACTER BYTE IN RCVR SERIAL SHIFT REGISTER.

£151.3

|
N
¢
RDAT <7.0>+

IN RCVR INPUT REG
FOR THIS PERIOD.

" PACKET TYPE/LENGTH BYTE

** PACKET LENGTH BYTE

FIRST BIT OF PACKET LENGTH/TYPE BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER

LAST BIT OF PACKET LENGTH/TYPE BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.

PACKET LENGTH/TYPE BYTE IN RCVR SERIAL SHIFT REGISTER

FIRST BIT OF PACKET LENGTH BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.
LAST BIT OF PACKET LENGTH BYTE CLOCKED INTO RCVK SERIAL SHIFT REGISTER.
PACKET LENGTH BYTE IN RCVR SERIAL SHIFT REGISTER.

o FIRST BIT OF TRUE DESTINATION BYTE CLOCKED INTO RCVR SERIAL SHIFT REGISTER.

Figure 2-11

RCVR CLK Synchronization

1K-8610

Destination Compare

2.4.7

The node address and the complement of the node address are set
into two sets of eight-contact node address switches. The
eight-bit output of the complement node address switch is applied
to the true destination compare logic as CNODE ADDRESS <7:0>. The
eight-bit output of the true node address switch is applied to the
complement destination compare logic as NODE ADDRESS <7:0>.

The

true

destination

byte

and

complement

byte

destination

are

applied from the RDAT bus to both destination compare logic
circuits. The state PALs enable the compare logic outputs such
that when the true destination byte is on the RDAT bus, the output

of the true destination compare 1logic 1s enabled. If the true
destination byte matches CNODE ADDRESS <7:0> from the complement
node address switch, TDST CMP asserts 1indicating that a true

address match was obtained. Likewise, when the complement
destination byte is on the RDAT bus, the output of the complement
TIf the complement
1is enabled.
logic
compare
destination

destination byte matches NODE ADDRESS <7:0> from the true node
address switch, CDST CMP asserts indicating that a complementary
address

match

was

obtained.

DST

True and complement destination matches assert
message receive and ACK receive state logic.

CMP

toO

the

A polarity reversal in the compare logic results in the output of

the

true

node

address

switch

being

destination compare logic and the
address switch being applied to

applied

the

complement

output of the complement node
the true destination compare

logic.

The output of the node address switches

logic

via

XOR

gates.

This

allows

is coupled to the compare

the

true

address

complement address to be swapped for maintenance testing.

and

the

ACK Source Comparison

2.4.8

The ACK source compare logic is used only during the reception of
an ACK packet. The ACK packet was transmitted from its source to
acknowledge an information packet that was transmitted from this

node. When the information packet was in the transmit channel, the
destination
compare

address

was

saved

and

applied

into

the

ACK

source

logic.

The ACK source compare logic receives inputs from the transmit
channel and from the RLDAT bus. When the source byte of the ACK
packet is on the RDAT bus, the output of the compare 1logic 1is
If a match is obtained, ACK SOURCE CMP 1is asserted
sampled.
indicating that the source address of the ACK packet matches
destination address of the preceding information packet.
2.4.9

Cata

Receive

Data Parity And Channel

output

data

bytes

receiver

are

RCVR

transferred
DATA

the

from

The

Output

RDAT bus
bytes

are

the

PE via

output

from

the

the
the

<7:0>.

The data bytes are also applied

from the RDAT bus

into a receiver

data parity generator where odd parity is generated on each byte.
A ninth input to the parity generator (VALID RCVR PARITY) provides
a means of introducing parity errors for maintenance testing. The

output from the parity generator is applied to a parity flip-flop

which outputs RCVR

DATA

PARITY to

the

PB.

TRANSMIT CHANNEL

2.5

and

Figure 2-12 is a block diagram of the transmit channel
be referred to throughout Section 2.5.
2.5.1

Transmit Data Input

from

Transmit

data

disabled

(closed).

2.5.2

Bit Sync,

DATA

(XMIT

the

1into

input

1is

<7:0>)

should

input 1latch and then
transmit channel via the XMIT data
transferred to the XMIT data bus as XMIT DATA BUS <7:0>. The input
latch is transparent in that the data on the XMIT data bus will
follow the XMIT DATA <7:0> input so long as the latch is enabled
by ENA XMIT DATA LATCH from the transmit control logic and by the
high state of XMIT CLK. When XMIT CLK is low, the latch 1is

in a 32 x 8

trailer bytes reside

the

ENA

are

placed onto the XMIT data bus.

address input to the PROM (<A4:A0>)
Figure

the

illustrates

2-13

sync character byte,

and the

five-bit

PROM.

transmit

the

from

SYNC/TR

and Trailer Bytes

Sync Character,

The bit synchronization bytes,

The PROM output is enabled

logic.

control

selects the output bytes which
the

1in

1locations

eight-bit

sync/trailer PROM. The five bit-sync bytes and the sync character
byte are located in the upper area of PROM space. They are spaced
at every other location starting at address 10101. The six trailer
bytes are located in between the sync bytes starting at address
10100. The 1lower area of the PROM is reserved for possible
bit
of
bytes
(15
bytes
to 16
header
the
extension of
synchronization and one byte for the sync character).
PROM address bits <A4:Al> are obtained from a binary counter which

enabled

CNT

ENA SYNC/TR

control

transmit

the

from

logic.

When ENA SYNC/TR CNT is false, the counter is loaded with starting
address 1010. When ENA SYNC/TR CNT asserts, the counter counts up
from 1010 addressing every other PROM location. The PROM's least
control

logic.

addressed.

When

(AO)

bit

address

significant

When SET TRAILER

SEL

TRAILER

1is

SEL

true,

from

TRAILER

false,

the

the PROM

the

sync

transmit
are

bytes

PROM

trailer bytes

cause

LAST

are

addressed.

Address

asserted

bits

<A4:A2>

the

are

transmit

monitored

control

and

logic

when

all

As is shown in Figure 2-13, this occurs when
true.
byte (sync byte 5) is being addressed.
When

the

GONE

binary counter

has

counted

up past

the

SYNC

three bits

last

the

are

last sync

trailer

byte

(or past the sync character byte) it overflows and asserts SYNC/TR
the

PAL state

logic.

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BITSYNCBYTE

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TRAILER

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BITSYNCBYTE

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BITSYNCBYTE

(65)

TRAILER

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BITSYNCBYTE

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TRAILER

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BITSYNCBYTE

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A3
A4
TK-8598

Figure 2-13

Sync/Trailer PROM Space

2-32

packets

the

link

transmitted,
involve

and

source,

type,

The packet

ACK

Inserts

ACK Packet

2.5.3

the

these

1link.

bytes

destination

information

When

the

inserted

are

inserted

packets
port

are

and

into

being

not

hardware.

Packet Type Byte —-- The packet type byte 1is obtained
2.5.3.1
from the ACK type logic. The logic outputs a 1 1in bit position 7
signifying an ACK (or NACK) packet. Bit position 6 is a function
of BUSY which is derived from RCVR BUFFERS FULL from the PB. If
the receive buffers in the PB are full, the information packet
just received could not be accepted by the node causing BUSY to
assert.

causes

This

in bit

that

signifying

position 6

a NACK

If BUSY is false, bit position 6 1is O

packet is being transmitted.

indicating that an ACK packet

is being

transmitted.

from the ACK type logic are always 0.

Bits <5:0>

Byte

2.5.3.2

Source

2.5.3.3

Destination

The

complement

the

byte

source

ACK

node address (CNODE ADDRESS <7:0>) obtained from the complement
node address switch. The source byte is gated onto the XMIT data
bus by ENA ACK SRC from the PAL state logic.
--

Bytes

are

bytes

destination

ACK

The

derived from the source byte of the associated information packet.
The source byte is taken from the RDAT bus in the receive channel

and clocked into the destination address registers by CLK ACK DST
RDAT

REG.

destination

<7:0>

REG

1is

while

entered

the

into

directly

the

(complement)

inverse

ACK

true

entered

into the complement ACK destination register. The true destination

the

and

byte

bus

data

destination

complement

ENA

ACK

and

TDST

ENA

byte

ACK

gated

are

the

respectively.

CDST,

XMIT

The

gating signals are asserted by the PAL state logic to insert the
bytes into the ACK packet at the appropriate insertion times.
Destination Address Register

2.5.4

The destination address register saves the destination address of
an information packet that is being transmitted. CLK DST ADR REG
asserts

into

the

correct

time

The

clock

destination

the

true

byte

destination

wused

when

byte

the

associated ACK packet is received. It is compared to the source of

the

ACK

obtained

packet
if

transmission,

the

receive

<correct

channel

node

where

responded
|

match
the

will

message

Transmit Data Parity Check

2.5.5

Data on the XMIT data bus is transferred to the BUS TDATA bus via
the XMIT data register. The register output is gated to the BUS
TDATA bus by ENA XMIT DATA REG from the PAL state logic.
is

from the BUS TDATA bus

Data

to the XMIT data parity

applied

checker where a parity check is made on the packet bytes. The
(XMIT TCATA PARITY) are received from the PB and
parity bits
applied to a latch flip-flop as TDATA PARITY LATCH. An OR feedback
network holds TDATA PARITY LATCH true for both alternations of
XMIT CLK to allow the latch flip-flop to set (if parity is a 1).

flip-flop outputs the parity bit

The latch

parity

Parity

1is

TDATA

PARITY

ERROR

asserts and enables
occurred,

(TDATA PARITY)

when

ENA

XMIT

asserted

the

checked

checker.

the parity checker output.
is

DATA

to the

PARITY

If a parity error
message

state

the

packet

logic.

CRC Generation

2.5.6

The

packet

into

the

bytes

XMIT data

the

bus,

with

starting

type byte and ending with the last byte of the body,
CRC

functions

generator

The

generator.

32-bit CRC longword unique to the packet being
longword is inserted into the packet,

packet
2.5.7

Figure

input

are

produce

transmitted.

The

generator.

The

after the

a byte at a time,

body.
XMIT

2-14

CLK Generator

a
is

block

diagram

transmit clock (XMIT CLK)

the

CLK

XMIT

is derived from a 70 MHz input receilved

from a crystal oscillator network in the RCVR CLK generator. The
transmit clock generator functions to produce XMIT CLK pulses at
8.75 MHz (period = 114.28 ns). The generator also outputs an RO
pulse to load the XMIT serial shift register from the TDATA bus.
XMIT

The

framer

shift

clocked

MHz

and

has

The inverse of bits <R6:RU>
eight-bit parallel output (<R7:R@>).
are ANDed such that when all seven bits are false, a 1 is 1input to
the framer shift register. The 1 is clocked up to the R7 output at
which time another 1 is generated for the shift register input.
This

action

and

illustrated

from

the

framer

Figure

shift

2-15.

input of the XMIT CLK flip-flop causing the

are

applied

the

flip-flop to set for

two 70 MHz clocks. The output of the flip-flop is XMIT CLK.

Figure

2-15 illustrates the time relationship of XMIT CLK relative to the
outputs

the

framer

shift

For maintenance testing, the output of the XMIT CLK flip-flop can

be disabled and an XMIT TEST CLK substituted.

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Parallel To Serial Data Conversion
2.5.8
Eight-bit data bytes from the TDATA bus are input to the XMIT
serial shift register. RO from the XMIT CLK generator asserts
every eighth 70 MHz clock to load the shift register with a data
byte from the TDATA bus. After being loaded, the register returns
to the shift state and shifts out the data byte a bit at a time as

XMIT SERIAL DATA. As the last bit is shifted out, RO asserts again
to

load

the

Figure 2-15

"serial

packet

illustrates

shift register.

into

byte

the

serial

the

shift

load and shift time periods of the

The XMIT SERIAL DATA is applied to a serial data flip-flop clocked
by 70 MHz. The flip-flop output (E183-11) is then applied to the
Manchester encoder.

2.5.9

Manchester Encoder

The Manchester encoder modulates the serial data with the data bit
rate clock to produce the signal format that 1is placed onto the CI
bus.

The encoder logic

consists

of XORing

the

E183-11

output

the

XOR
serial data flip-flop with the 70 MHz clock. The output of the op.
flip-fl
encoder
ter
Manches
the
to
applied
and
d
gate is inverte

rate)
The encoder flip-flop is clocked at 140 MHz (twice the data
2.4.2.1).
as required for phase encoded (PE) data (see Paragraph
The output of the Manchester encoder flip-flop (ME DATA)
packet data ready to be transmitted onto the CI bus.

1s the

The action of the Manchester decoder can be seen from the timing
diagram of Figure 2-16. The E183-11 output of the serial data
flip-flop is shown for the given data bits. The result of XORing
F183-11 with the 70 MHz

is seen.

Using the

inverse of the XOR

output for the encoder flip-flop D input, and the 140 MHz for the
clock,

signal

the

resultant

format

1is

DATA

1identical

waveform

received from the CI bus as shown

the

1is

format

derived.

in Figure 2-6.

the

The

serial

DATA

data

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XMIT ECL Drivers

2.5.10
to the CI
The ME DATA from the Manchester encoder 1is transferreddriver
s are
XMIT
The
bus via XMIT ECL drivers (Figure 2-17).
bus.
CI
the
on
paths
B
divided into two channels feeding the A and
logic
l
contro
it
transm
the
path selection is made by the port via

which enables the driver in the selected channel.

h
The ME DATA is routed to drivers in both channels and then throug
The
XMIT.
CIB
coupling transformers to the CI bus as CIA XMIT and
XMIT drivers are enabled by redundant XOR gates. When the transmit

control logic selects channel A, A DRIVER ENA asserts (P DRIVER
ENA false) and in turn asserts E151-1 from the channel A AND gate.
The assertion of E151-1 causes outputs from both channel A XOR

gates which in turn enables the channel A driver,.

the transmit control
Likewise, the assertion of B DRIVER ENA from
t of the channel B
outpu
2
logic causes the assertion of the E151-

AND gate and thus enables the channel B driver.

prevent the
Redundancy exists in the driver enabling logic gto the
A and B
causin
possibility of a single component failure
a 1logic
gh
throu
If
channels to be enabled simultaneously.
B
channel
and
A
component failure, the outputs of both the channel
the
of
one
AND gates were asserted (E151-1 and 2 both true),
be
channel A XOR gates and one of the channel B XOR gates would
l
channe
the
inhibited. This would hold the enabling 1inputsthetonode from the
drivers*high to inhibit the drivers and isolate

bus.

where
The port can also select internal maintenance loop operation
1into the

the ME DATA from the transmit channel is looped back
receive channel. To do this, the port control logic asserts INT
MLOOP which inhibits both E151 AND gates, shutting off both output
drivers.

addition,

the signal

1lines

into both

the A

and

channel drivers are held high by INT MLOOP to inhibit any signal
data variations

into the drivers.

* The operation of ECL logic 1is described in Paragraph 2.4.1.2.

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2-40

2.6

CRC

2.6.1

CRC

GENERATOR AND

CHECKER

Figure 2-18 is a block diagram of the CRC generator and checker.
Generator

Packet bytes
input to the
control

from

input

the

from the XMIT data bus in the transmit channel are
CRC input mux as XMIT DATA BUS <7:0>.
The transmit

logic

asserts

transmit

XMIT

CRC

channel.

<7:0>

NEW DATA

lookup

table

logic

The

first

three bytes

new

input

byte

ENA

the

mux

the

output

bytes

generates

mux

select

applied

as NEW DATA

the

CRC

the

longword

bytes

the

<7:0>.

CRC

an XOR gate.

via

table

lookup

CRC

to a

applied

The

for

the

packet

being transmitted. CRC TABLE <31:00> from the lookup table logic
is applied to a CRC register which outputs CRC <31:00>.%
CRC
<31:00> is looped back into the lookup table logic in two parts.
(CRC

<23:00>)

table

logic while the upper byte

bytes

are

from

the

bytes

CRC

input

such

that

the

applied

directly

Thus,

the

compilation

the

into

the

new

data

is XORed with the

(31:24))

integrated

continuously

previous data

are

(CRC

CRC-generated

longword

the

always

a function of the packet bytes received from the transmit channel.

The

CRC

longword

from

the

CRC

each
byte

driver places a byte onto the BUS
into the packet being transmitted.

The

drivers

body

enabled

are

receives a SHIFT IN input

counter

the

CRC

BUS

TDATA

bus.

The

coupled

bus

input

through

shifted

1in

through

before

XMIT

data

TDATA

(see

bus.

that

The
be

This

XMIT

only one

the

source

CRC generator

XMIT CLK during

REG

the

insures

2-12).

before

DATA

place

Figure

sequence

ENA

enabled

that

before

the

AND

Likewise,
is

the

must

first

false

byte

CRC

the

TDATA

bus

each

AND

gate

CRC

driving

logic

sequence.

BUS
CRC

counter

The

counter.

are

addition,

the

insert

through R3 are applied to four AND gates which
appropriate time from the PAL state logic.

gate

When enabled,

(E29-5) when the last byte of the packet

asserting

CLOCK

TDATA

byte

CRC

from

also

four drivers.

in the transmit channel via

TDATA bus

gate

can

AND

isolated

from

must

enabled.
at

the

onto

connected

the TDATA bus

clocked

transmit

logic

the

any one

by CRC CLOCK which

states.

* The CRC register is initially preset to all 1's.

the

disabled

This

(7:0)

(CRC

enabled

the

bus
1in

ensures

time.

seen

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CRC Checker
2.6.2
receive channel are
Packet bytes from the RDAT register bus in the The
transmit control
.
input to the CRC input mux as RDAT REG <7:0>
selecting the
logic negates the XMIT CRC ENA input to the mux
ed to the
appli
is
t
outpu
mux
The
el.
bytes from the receive chann

CRC input register which outputs the bytes as NEW DATA <7:0>.

<31:00>)
The CRC logic functions to generate the CRC longword (CRC The
last
from the packet bytes as described

1in Paragraph 2.6.1.

ted
four bytes input to the CRC logic is the CRC longword genera
CRC
the
into
entered
1is
for the packet. When the CRC longword
Dbe
will
)
ecimal
(hexad
28E3
lookup table, an output of DEBB

obtained if the packet transfer was error free.

checks the value
The longword is applied to a CRC comparator which
the proper value was
of the longword and asserts CRC STATUS 1if
obtained.

ARBITRATION

2.7

General

2.7.1

prevent

collisions

the

Dbus,

only

one

node

should

transmitting at a time. When the port commands a node to transmit

an information packet, the 1link goes through an arbitration
For a node to
process in order to "gain control"” of the bus.*
turn to have
node's
the
is
it
that
"gain control" of the bus means

executed by
the bus within the arbitration process that 1is being
re or
hardwa
no
1is
There
bus.
the
all the nodes competing for
e
exclud
and
bus
the
seize
may
node
a
software control by which
other

The

nodes.

arbitration process

consists

of counting

down

specific

slot is a time period
number of "quiet slots" on the bus. A gquiet is
no activity on the
of approximately 800 ns during which there
ay trip on the
one-w
a
for
time
cient
suffi
bus. Eight hundred ns is
bus and to detect a carrier presence. Thus, a quiet slot is a time
period allocated for an arbitrating node to detect another node's
transmission.

If a node completes its quiet slot countdown (reaches 0), the node

wins the bus and may transmit. If the node detects activity on the
bus (another node is transmitting) before the countdown 1S
started over
complete, the arbitration process is interrupted and compet
ing for
are
nodes
several
once the bus is quiet again. If

ration countdowns
the bus, all but the winner will have their arbit
nodes will
losing
the
again,
interrupted. When the bus goes quiet
them 1in
ng
placi
thus,
usly,
restart their countdowns simultaneo
bus
busy
a
on
only
occurs
sync with each other. This synchronism
to
er"
carri
of
"loss
a
where the competing nodes will sense
synchronize

their countdowns.

* There is no arbitration process when transmitting an ACK packet
the

is assumed the bus has already been acquired for

information and ACK packet transfers.

The

arbitration

algorithm
the

such

lower

countdown

that,

numbered

nodes, however, can
gain the bus again.
slots

each

if more

node

will

than

round

one

robin

node

given

the

dual

trying

bus

countdown

first.

each gain the bus before the lower
This is implemented by the number

node must

transmit,

The

other

node can
of quiet

count.

The number of gquiet slots to be counted down is determined by the
number of the node attempting to transmit and the number of the
node that last had the bus. A node may count N + I + 1 slots or I
+

slots

where:

(the maximum number of allowable nodes)

the

node

wWwhen a node

countdown

starts

winning

node.

number,

the

restarts

number

to arbitrate,

interrupted,
If

the

node

the

winning

counts N + I

determines

node

countdown.

restarts

node
If

was

the
I

lower

winning

slots.

the

+ 1

number

the

node

was

higher

number,

countdown.

the

node

Thus,

when

several nodes are competing for the bus, the lowest number node
wins the bus first but must count down the N + I + 1 slots to gain

The

again.

bus

the

highest.

The

arbitration algorithm

restart

will

nodes

higher

the

arbitration

their

with the I + 1 countdown and all will win the bus before the first
winner can gain the bus again. As each node wins the bus, the N
term is added to its countdown value and the next higher numbered
node wins the bus. Thus, each competing node will have a turn at
the bus, starting with the lowest numbered node and working up to

whenever
that

the

node

receiver

transmitting.

node

receiver

bus,

the

node may

other

have

node

path.

loading 16

The

the

term

lowest

countdown,

1is

illustrated

Figure

2-19.

PATH

BUSY

false)

the

ACK

response.

busy

receiving

continuing

the

countdown

its

free

(ALT

Note

0),

(reaches

that

checks

before

Transmission should not occur from a node unless the
is

free

completed
receiver

When

into the

completes

node

this

countdown

its

could

happens,

node's counter

included
number

the

and gained

one

the transmission
and

two

When

countdown

node

then it will be looking for

1is

Although

path of

packet

the

countdown.

expressions
executing

1 slot -- not

delayed

the

because

I
0 slots.

YES

LOAD N+ 1+ 1INTO

COUNTDOWN
COUNTER

CARRIER

YES

DETECTED

WINNING

YES

NODE NUMBER
.

LOAD COUNTE

WITHN + 1+ 1

WITH | +1

LOAD COUNTER

DECREMENT

[ COUNTER

]

|
RECEIVER

CHANNEL
BUSY

LOAD 16 INTO

COUNTER
TAKE OVER

RECEIVER CHANNEL

[ TRANSMIT PACKET |

TRANSMISSION
DONE

TK-8616

Figure 2-19

Arbitration Flow Diagram

Arbitration Logic

2.7.2

Figure 2-20 is a block diagram of the arbitration logic.

transmit

receiving

COUNT

arbitrator

the

loads

1link

preparation

for

the

gquiet

the true state of LOAD ARB

countdown. The basic slot counter is loaded with 1001
+ 1.

the down counter is loaded with N + I

the

1in

the

In MX state A,

idle state (MX state A).

Prior to

port,

from

command

(binary)

slot

and

The down counter is in two sections: the lower four bits and the
fifth bit. The four-bit section is loaded with the node address
is loaded from an N
(NODE ADDRESS <3:0>). The fifth-bit section
countdown
arbitration
the
in
term
N
the
supplies
that
load mux
expression.

Wwhile

input

the

The mux

1link

load

is
1

select

inputs are

idling

in MX

into

the

fifth

STATE A,
bit

in Table

shown

the mux

section

2-3.

the +V

selects

the

down

counter,

The 1 represents the N term in the N + I + 1 countdown expression.
When the link shifts to MX STATE B,

arbitrator starts

its countdown.

LOAD ARB COUNT negates and the

The slot counter is clocked from

by XMIT CLK and outputs BASIC SLOT after seven clock pulses.

1001

BASIC SLOT is looped back to reload the counter with 1001 and the
The

repeated.

cycle

period

time

Fach time BASIC SLOT asserts

the

counter

down

which

enables

decremented

CLK

the

four-bit

section to decrement.

the

CLK.

XMIT

ns;

114.28

section

this

When

the next assertion of BASIC

section of the down counter reaches 0,

SLOT asserts the carry (CRY)

XMIT

hence, BASIC SLOT asserts every 800 ns (7 x 114.28).

output which enables the fifth bit

fifth bit section contains a 1

(N + I

+ 1 count), the 1 becomes a 0, the four-bit section becomes all
section
fifth bit
the
If
continues.
and the countdown
1's,

contains

ARBC

a 0

+ 1
(I

count),

(arbitration

the CRY output goes

counter

flip-flop to set on the next XMIT CLK.

which

true asserting

conditions

the

ARB

If the alternate bus path

is not busy (ALT PATH BUSY false) ARB and ARB OK assert signifying

a successful countdown and causing the link to shift to MX state

Note

that

after

cause

ARB

the

counter

true.

The

has

reached

count,

one

BASIC

SLOT

assertion of BASIC SLOT is required to assert the CRY output and
go

additional

assertion

represents the 1 term in the two countdown expressions.

FORCE (CAKRIEh

INT MLOOP

(K|

St L PATH CARRIER

(FIG)CARRIER DET B

LOAD ARB COUNT

(FIG 2 21)

CARRIER

(K)

LATCH

XMI1 CLK C

FIG\CARRIER DETA

MX STATE A

(K}

SET

23/

FIG

CNODE ADURESSE

(K)

.
r’

XMIT CL
K

LOAD

;

(K)

FFf

—=——{

;

)IN
:

LOAD

MUX
1K)

F1G. 2 3)

)
<.
NODE
AGDRESS
- .3 0

ool

XMIT CLK

——*|CLK

BASIC

(K)

ADD <30

CKMP

ALT PATH BUSY

(k)

CLK

(K)

LOAD

CRY

iK)

’

(FIG 227)

CRY

ARBC - ©

LETTER DESIGNATIONS
IN FARENTHESES REFER TO

ENGINEE RING DRAWINGS CONTAINING CORRESPONDINC

UUVYN

LOAU??HNTEH

CLK

BASIC SLOT —

Mx STATE B8
P16

2 30)

LOGIC

ARE

XMIT Cirf

XMIT CLK

NOTE

ENA

~30

X MITCLK

Ct}

ARb CMF

DOWN

ENA CQL)NTER

8ASIC SLUT

LOAD

(a\fi
-

LT ~<IPLUST -

ADDR

COUNTER

.
SEL

NODE

{(FIG 2 2%5)
O————=in

CLH

ALT PATH

{Kj

BUS;Y______J

(K}

I (FIG
ARb

OLYDHUORTO

HiG

(FIG 2 30)

HCVR ACTIVE

——

220

{F1G 225;{

FUR(L

—

AKE

XMIT F{ A

QL_J
.

225
AFbB UM

(J)

!
Fig

)

Z 30

MXx STATE B

Th @va

Figure 2-20

Arbitration Block Diagram

Table

Select
MX

STATE

2-3

Load

Code
SEL

Mux

Selection
Input

PATH

CARRIER

True

False

True

False

don't

care

Selected

(load

arb.)

Load

Latch

FF
FF

If a carrier from another node is detected during the arbitration
countdown, the arbitrator is reloaded and the countdown starts
over. The node address comparator determines whether the
interrupting (winning) node is above or below this node in order
(See Paragraph 2.7.1 for a
to determine the new countdown value.
general

discussion

the

arbitrator.)

The

comparator

compares

the node address with ARB CMP ADD <3:0> from the four-bit section
of the down counter and asserts, LT * if this node

number is less than the winning node number. For example, assume
this to be node 5 and the winner to be node 2. ARB CMP ADD <3:0>
is down counted to 3, the comparator A input is greater than the B
input;

therefore,

PLUS

false.

This

node

not

1less

than the winning node. If the winner were node 7, ARB CMP ADD
<3:0> would be 14 (the fifth bit having been decremented), the
comparator A input is less than the B input; therefore, LT is true. This node is less than the winning node. The LT <I

PLUS 1> signal is used to determine which count down value 1s to
be reloaded into the down counter for the next countdown.

when a carrier is detected (interrupting the countdown), CARRIER
DET A or CARRIER DET B asserts. If the carrier 1is detected on the

1s
SELL. TPATH selected by the link control PAL, SEL PATH CARRIER
COUNT
ARB
[LOAC
asserted. The assertion of SEL PATH CARRIER causes
to assert and reload the basic slot counter and both sections of
the down counter. The fifth bit section of the down counter
again loaded from the N 1load mux; however, now the mux
selecting its input from the N load flip-flop (see Table 2-3).

is
1s

During the countdown, the false state of SEL PATH CARRIER holds
the N load flip-flop reset. When SEL PATH CARRIER asserts, it
allows the J input to the flip-flop to look at LT from
the node comparator. If LT is true (this node is less

than the winning node), the flip-flop is set and a 1 is loaded
into the fifth bit section.

If LT is false (this node

is higher than the winning node), the flip-flop remains reset and

a 0

is loaded

into the fifth bit section.

The output from the N load mux is latched up in a latch flip—-flop.

When SEL PATH CARRIER negates,

the N load mux

selects

the

output

of the latch flip-flop thus maintaining the fifth bit selection
after

* 1T =

SEL

PATH

less

CARRIER negates.

than

described

algorithm

first,
For

same

Paragraph

used

then

the

1in

the

loop

which

higher,

way

that

any

node

beaten

the

preceding

PLUS

loaded
must

Node

1is

false

with

appear

and

0.,

that

has

been

added

the

fifth

bit

node

15.

1's)

and

<3:0>

all

1's),

load

flip-flop

all

Hence,

counter

and

the

Thus,

has
the

1is
0

does

this

been

its

the

load

1loop.

beaten

the

fifth

node

15
+

flip-flop

«I
is
it

restart
1its
1> is true.

when

bit

countdown

flip-flop

(CNODE

in
the
node X

LT
counter
node 15

and
PLUS

counter

node

bus

therefore,

section
of
the
0
is beaten by

and
1

the

continuous

restarts

winner,

transferring

into
an

bit
node

1inhibited

reloaded

node

the

input

gate

wins

must
follow node 15
node preceding it.
When

section

just

AND

arbitration

node

by
a
lower
node
this case, LT <I

when

robin

force

node

ADDRESS

(ARB
1>

CMP

into

remains

section

<3:0>

ADD

the

reset.

the

down

countdown.

the

link
receive channel
1is
busy on
the
alternate
bus
path,
ACTIVE will be true, causing ALT PATH BUSY to also be true.
condition inhibits the assertion of ARB and loads 16 into the

RCVR
This
down

the

however,

forth

(X-1),

beaten

1into
by

round

than

when

was

Logic
beaten

less

Likewise,

the

node
fifth

node

the

countdown

and

follows
not

lowest-numbered

continuous,

2.7.1,

the

counter,

ALT

PATH

BUSY

loads

only

the

down

mode.

counter.
The
four-bit
section
ALT PATH BUSY generates the 16 by

fifth

bit

section

remains
enabled
disabling the N

in
count
load mux

causing

it to output a 0 into the fifth bit section. The four-bit
section 1s at all 0 s (countdown successfully completed),
hence,
as the fifth bit section is loaded with a 0,
the four-bit section

is
decremented
to
all
1's.
Thus,
when
enabled again, it contains a count of 16.

the

entire

counter

1is

The true state of RCVR ACTIVE inhibits a successful arbitration by
asserting ALT PATH BUSY. RCVR ACTIVE negates after the message on
the
alternate
path
has
been
received.
The
transmission
that
is
arbitrating for the bus, however, still cannot be allowed because

the
transmit
channel must
be
used
to
transmit
an ACK
This
point
1in
the
message
receive
state
sequence
is
Hence,
MR STATE
I 1is
the assertion of ARB.
The

false

state

used

LCLYD

HDR

keep

ALT

also

PATH

BUSY

asserts

ALT

inhibits
a
successful
arbitration.
DLYD
HDR
TO
transmission is occurring from this node (A DRIVER

ENA

true)

would

as
the

shown

Figure

transmission

2-30.
an

ACK

The

true

the

state
TI.
to inhibit

PATH

BUSY

1is

false

ENA

transmission

packet

response,

DRIVER

this

alternate

and

case

path.

LINK FUNCTIONS

2.8

four

are commanded from the port via

Link functions (Figure 2-21)

link control lines (LINK CONTROL <3:0>) and eight port data lines
(PORT DATA <7:0>). The port asserts SELECT when a valid function

exists on the link control lines.

A function decoder decodes the link control lines and outputs the
specific function commanded by the port. The function commands are
described

below:

initiates

function

- This

XMIT FCN

arbitration and transmission on

paths.
CI
the
of
one
path used 1is selected

bit
B).

data
path

path

resets

function

- This

RESET XMIT STATUS

CI
The
by port

transmission status bits at the
transmission
a
of
end
operation.

function

- This

ABORT XMIT FCN

currently

active

aborts

transmit

operation.

The 1link mode control,
the

port

control

data

lines

information

PAL,

from

receives the 1link control lines and

the

relating

port.

The

the

port

data

specify various maintenance functions for the link.

2-51

lines

commanded function,

carry

and

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The

control

information

and

are

functions

maintenance

described

below:

- This signal selects the CI path

XMIT PATH B SEL

associated

the

with

FCN

XMIT

command.

signal enables path A

RCVR A ENABLE

- This

RCVR B ENABLE

- This signal enables path B 1n

EXT MLOOP

- This 1is a maintenance function

the
receiver making
1link
the
node accessible on CI path A.

the
receiver making
1link
the
node accessible on CI path B.

that allows the link to receive
its own transmission by looping

on the

selected CI path.

- This is a maintenance function

INT MLOOP

that allows the link to receive
its own transmission by looping
inside the transmit drivers and

This

receiver detectors.

input

operation will not interfere
with the CI operation of other
nodes.

FORCE CARRIER

- This is a maintenance function

FORCE ARB

- This is a maintenance function

VALID RCVR PARITY

- This is a maintenance function

see

that causes the link
detected carrier.

the link to force a
ation.
arbitr
sful
succes
that causes

that

is used to generate parity

errors in the receive channel.

- This 1is a maintenance function

SWAP TRUE/COMP ADR

that

causes

complementary

the

to be swapped resulting
address mismatch.

The transmission path select signal
asserts

corresponding

FORCE

PATH

and

true

address

sources

(SEL PATH A or SEL PATH B)
signal

after

the

node

has

successfully arbitrated for the bus (ARB OK true). The FORCE PATH
signal enables the corresponding path 1in the receive channel 1in

preparation to receive the ACK response.

2.9

LINK

Figure

2-22

INTERFACE

1illustrates

SIGNALS

the

link

interface

signals.

Most

link interfacing is with the PB. Figures 2-23 and 2-24
diagrams of a typical transmit and receive operation.

are
The

the

flow
flow

diagrams highlight the interface signals to illustrate their basic
functions.

Some other major signals, internal to the 1link,
are
for completeness. The two flow diagrams utilize most of

included

the interface signals and explain their basic functions. Interface
signals not included in the flow diagrams are the three clocks
(PORT

CLK,

<7:4>),

PORT

XMIT

and

CLK

generated

CLK,

RCVR

CLK),

received

NODE ADDRESS <7:0> is sent
into the transmitted packet

to
as

the

INITIALIZE

the

All

and

within

from

link.

the

node

address

(NODE

ADDRESS

INITIALIZE.

while

three

XMIT

CLK

and

RCVR

CLK

are

clocks

are

used

both

the

PB)

and

1inserted

link.

used

for

system

the port (via the
the source byte.

initialization.

The flow diagrams illustrate a typical error-free sequence of a
transmit and a receive operation. They can be used in conjunction

2-3)

and

the

transmit channel block diagram
(Figure 2-12), or with
detailed state diagrams discussed in Paragraph 2.10.

the

with

the

receive

channel

block

diagram

(Figure

INITIALIZE
SELECT

LINK CONTROL <3:0>

BUFFER

XMIT DATA ENABLE

(PB)

XMIT DATA <7:0>

_ _ | _o T FCN

XMIT PATH B SEL
o - — ——==
e RCVR A ENABLE
L —
l

NODE ADDRESS <7:0>

XMIT BUFFER EMPTY

XMIT STATUS<7:0>

RCVR A ENABLE

RCVR B ENABLE

XMIT ATTENTION

-— — * RCVR B ENABLE

XMIT DATA PARITY

—

PACKET

PORT DATA <7:0>

- —» RESET XMIT STATUS

LINK

VALIU RCVR DATA
RCVR BUFFERS FULL
RCVR DATA <7.0>

RCVR DATA PARITY

PACKET LENGTH
RCVR PACKET END
VALID RCVR STATUS
CRC STATUS

ICCS PATH B

PORT CLK

XMIT CLK

RCVR CLK
!

TK-B615

Figure 2-22

Link Interface Signals

A valid function exists on

LINK CONTROL lines.
*LINK CONTROL <3:0>

XMIT FCN

Port commands
a transmit function via

LINK CONTROL lines.
*"PORT DATA <7:0>
XMITPATH B SEL
Port selects transmit path

|
|
|

via PORT DATA lines.

inserted into the

packet.

Trailer bytes are

inserted into the

packet.

v
SYNC/TR GONE
Packet has been
transmitted.

WACK

Walt for ACK response.

Link arbitrates for

*SELECT

CRC bytes are

ACK RCVD
ACK response has been

the selected bus.

successfully received.

Link transmits header (bit
sync bytes and sync

[ XMIT ATTENTION

character byte).

An ACK response has

been detected.

*XMIT DATA ENABLE
Link is ready to receive

*XMIT STATUS <7:.0>

data from the PB.

Transmit status
available to the
*XMIT DATA <7:0>
*XMIT DATA PARITY

port,

Packet bytes (with

*LINK CONTROL <3:0
RESET XMIT STATUS

parity) are transferred
from the PB to the link.

Command (via LINK
CONTROL lines) to
reset most of XMIT

*XMIT BUFFER EMPTY
All packet bytes have
been received from the

STATUS bits.

)

]

*Interface signal

TK-8601

Figure 2-23

Interface Flow Diagram - Transmit Operation

2-56

( Start
l

)

*PORT DATA <7:0>
*RCVR A ENABLE

*RCVR PACKET END
Last byte of packet

body has bee”PB .

transferred to

*RCVR B ENABLE

Port selects receiver path

via PORT DATA lines.

Y
*VALID RCVR STATUS
Valid receiver status

information is available

ICCSPATH SELECTED

to the port.

Carrier is detected on bus.

*CRC STATUS

CHAR
Carrier SYNC
is a valid packet.

}

*VALID RCVR DATA
Valid packet data ready

1o be transterred
to PB.

;
*RCVR BUFFERS FULL

True if PB receive
buffers are full.

*RCVR DATA <7:0>

Indicates CRC status on
received packet.

*ICCSPATH
B which Cl
Indicates over
path the packet was
received.

TACK
Transmit an ACK
(or NACK) packet.
;

ACK DONE
ACK (or NACK) packet

has been transmitted.

*RCVR DATA PARITY
Packet bytes (with

parity) are transferred

Done

from iink to PB.

*PACKET LENGTH
Data being transferred

to PB specifies length
of received packet.

L
*Interface signal
TK-8602

Figure 2-24

Interface Flow Diagram - Receive Operation

STATES

OPERATING

2.10

The following description of the four link operations utilizes the

the

engineering

task(s)

and

then advances

The

set.

drawing

contained

diagrams

state

various states are shown 1in the diagrams as circles. A path
looping back into a circle holds the link in that state so long as
the signal condition shown in the loopback path is true. The 1link
goes to its next state if the signal's condition shown 1in the
connecting path to the next state is true. Where no loopback paths
are shown, the link stays in that state for one clock pulse to
perform the

indicated

XMIT/RCVR MSG

set

drawing

the

included

Also

next state.

the

State

Flow

Diagram. The diagram shows the normal state flows for a message
transmission and ACK reception operation and for a message
reception and ACK transmission operation. The diagram 1llustrates
what PALs are used and how the sequence shifts from one PAL to
another as the operation is executed. The diagram 1llustrates a

basic point in link operations; that an ACK receive sequence is a
part of the message transmit sequence in that the message transmit
sequence is not complete until the ACK receive sequence 1s done.
Likewise, the ACK transmit sequence is part of the message receive

sequence

the

that

and

the ACK transmit

until

2.10.1
Figure

Message Transmit
2-25 illustrates the

conjunction

used

state

sequence.

engineering

drawing

recelve

message

with

set.

the

done.

1is

sequence

message

Two

MESSAGE

used

are

PALs

INITIALIZE from the port asserts TINIT which
state.

asserts

transfer

from

When

the

port

commands a

link

state

the

1link

PAL

control

diagram

and

the

message

XMIT

initializes

the

1link

function,

XMIT

the

for

MX State A is the transmit

and asserts MX STATE A from PAL No. 1.
idle

STATE

complete

logic

state

transmit

XMIT

not

sequence

transmit

causing

TXMIT

assert

FCN

and

The 1link arbitrates for the bus in state B. When the arbitration
is successful, ARB asserts and the link transfers to state C.
In state C the link transmits the bit synchronization bytes and
the sync character byte. After the sync character byte has been
SYNC/TR GONE asserts and

state

the

link

goes

loop

CRC

operations),

PAL no.
long as
asserts

generator

the

state

second

transfers

MSG

XMIT

link to state D.

(except

State

PAL

for maintenance
is

enabled,

and

1 stays in state E
there is no parity

and

sends the

enabled

the

for the rest of the transmission
error. If a parity error occurs,

link

state

the

transmitted,

so
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the

link

ATTENTION

transmission.

placed

asserted

The

link then

state

the

PAL no.

port

returns

which

state A,

MX STATE

reset

then

and

abort

XMIT

the

to state H when PAL

PAL no. 2 moved from its idle state (state G)

no.l asserted

will

From state H the link goes to state I where the destination byte
is clocked into the destination address register.

The link then transfers to state J where it waits for the body of

the packet to be transmitted. When the last byte of the body 1is
transmitted, XMIT BUFFER EMPTY 1s received from the PB and
trransfers the 1link to state K [if this is not a mailntenance
a maintenance operation (LOOP true), the
operation; if this is
link goes directly to state L].

In state K the CRC bytes are transmitted. MAX CRC 3 asserts when
the last CRC byte is transmitted. MAX CRC 3 causes the link to
to

transfer

state

In state L the packet trailer bytes are transmitted. After the
trailer bytes are transmitted, SYNC/TR GONE asserts and transfers
the

link

state

In state M the link has completed its transmission and is waiting
for the ACK receive sequence to complete. The end of the ACK

receive sequence is indicated by the assertion of AR STATE D or AR

STATE H from the ACK receive state logic. Either of these signals

asserts ACK RCVD to both PALs causing them to return to their idle

ACK RCVD also negates TXMIT to complete the message XMIT

states.

sequence.,

When the link enters state M,

(wait

WACK

for ACK)

1is asserted

the ACK receive state logic enabling the ACK RCVR PAL to start the

ACK receive sequence. When the ACK response
asserts

The

and

port

negates

can

abort

is received,

ACK RCVD

WACK.

the

transmission

asserting

ABORT

XMIT

FCN

via the LINK CONTROL lines. ABORT XMIT FCN asserts XMIT STATUS 4
and then TABORT via two flip-flops. TABORT is applied to both
message XMIT PALs resetting them to their idle states.

The MSG XMIT sequence is also reset by HEADER TIME OUT which
asserts ABORT RCVR to PAL no. 1. HEADER TIME OUT is asserted by
the

MSG

character

RCVR

state

logic

recognition does

when

carrier

not occur.

detected

but

sync

2.10.1.1

Transmit

Control

Logic --

performed

various

states

2-26

Figure

the

illustrates

logic that controls the flow of data through the transmit channel
shown 1in Figure 2-12.
The control signals are regulated by the
state signals generated by the XMIT state PALs.
The assertion and
negation of the control signals can be related to the task(s)
the

shown

1in

the

XMIT

state

diagrams.

and

signals

ENA SYNC/TR CNT is asserted by the appropriate STATE
enables the sync/trailer counter to start counting.

ENA SYNC/TR gates the bit sync bytes and the trailer bytes onto
ENA SYNC/TR is negated by ENA XMIT DATA LATCH
the XMIT DATA bus.
which gates the packet bytes from the PB onto the XMIT DATA bus.
ENA XMIT DATA LATCH also asserts

ENA XMIT DATA PARITY.

ENA

BUS

XMIT

while

bus

TINIT

bytes

DATA

the

REG

CRC

isolates

bytes

initially asserts

BUS

the

onto

the

are

TDATA

being

bus

ENA XMIT DATA

from

REG which passes

from the PB.
XMIT BUFFER EMPTY negates
remains negated until all the CRC bytes

ENA
are

XMIT

TDATA

DATA

bus.

the packet

recived

EMPTY

until XMIT BUFFER

TDATA bus

the

onto

placed

XMIT DATA REG which
placed onto the BUS

When this occurs, MX STATE L asserts thereby
TDATA Dbus.
MX STATE L
re-asserting ENA XMIT DATA REG for the trailer bytes.
of the
out
bytes
trailer
the
gate
to
TRAILER
SEL
also asserts
sync/trailer PROM onto the XMIT DATA bus.

A DRIVER ENA and B DRIVER ENA enable the drivers that output the
During a message
transmitted packet onto the selected CI path.
XMIT operation, the selected LCRIVER ENA signal is asserted by the

SEL TPATH signal selected by the port via the LINK CONTROL lines,
and

STATE

the

selected

The

DRIVER

ENA

state L when SYNC/TR GONE asserts.

RCVR = B.

path

asserts

DRIVER

ENA

LAST RCVR = B

message

was

The

(ICCS

transmit

received.

signal

PATH

the

is true
B

ACK

signal

1is

negated

during

During an ACK XMIT operation,

asserted

by AX

STATE

and

LAST

if the last message was receilved

true).

over

Conversely,

the

this

the

same

case,

path

message

was

during

DRIVER

which

ENA

the

received

CI path A, A DRIVER ENA would assert, transmitting the ACK over CI
path

LCRIVER

ENA

SYNC/TR GONE asserts.

signal

negated

state

when

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2.10.1.2

Transmit

<7:0>)

are

Status -to

used

status

the

bits

status

transmit

Eight

indicate

(XMIT

transmit

STATUS
operation (see Figure 2-27). The bits are available to the port
along

with XMIT ATTENTION.

the
XMIT ATTENTION is asserted when a response is received from from
ed
destination node (ACK or NACK), when no response is receiv
the destination node (ACK packet timeout occurs), when a transmit

parity error occurs,
issued

Or when an abort transmission command 1s

(ABRORT XMIT FCN is asserted).

The XMIT STATUS bits are asserted as described below:

XMIT STATUS 7

This

bit

the

error

1is

during

parity

set

detected on the data on the BUS TDATA bus
channel

transmit

transmission. A parity error will cause
XMIT ATTENTION to be asserted to the port
which will then abort the transmission.

XMIT STATUS 6

When set,

this bit indicates the presence

XMIT STATUS 5

When set,

this bit indicates the presence

XMIT STATUS 4

This

bit

FCN)

commanded

bit

of a carrier on CI bus A.

of a carrier on CI bus B.

set

when

transmission

aborted by the abort function
port

the

set

when

1is

(ABORT XMIT

via

the

LINK

CONTROL lines.

arbitration

XMIT STATUS 3

This

XMIT STATUS 2

—-

This bit is set when a NACK is received

countdown has reached 0. It does not
necessarily mean that a transmission will
occur (see Paragraph 2.7).

from the destination node. A NACK response
causes XMIT ATTENTION to assert to the
port.

XMIT STATUS 1

-—

This

bit

set when

an ACK

received

from the destination node. An ACK response
causes XMIT ATTENTION to assert to the

port.

XMIT STATUS O

This bit is set when a transmit operation
is in progress or whenever XMIT ATTENTION
is

asserted,

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2.10.2

ACK

Receive

Figure 2-28 illustrates the ACK receive state logic and is used 1in
conjunction with the the ACK RCVR STATE diagraem in the engineering
drawing

set.

Two

PALs

are

used

for

the

ACK

RCVR

state

sequence.

2.10.2.1
ACK
Receive
PAL
States
-INITIALIZE
from
the
port
initializes the receive channel and asserts RINIT to both ACK RCVR
PALs placing them into their idle states (state A for PAL no.l;
state E for PAL no.
2).
The link is transferred to AR state B

when PAL no. 1 senses that a valid packet is being received (CHAR
SYNC true), that the receiver is waiting for an ACK response (WACK
true), and that the packet is an ACK (RDAT REG 7 = 1) rather than
a

message

In
is

packet.

state B the packet true destination byte is
obtained (DST CMP true), the link transfers

checked.
to state

If
C.

a match

In state C, ACK RCVR state PAL no.
2 1is enabled
(AR STATE E
asserts)
and the complement destination byte
1s checked.
If a
destination match 1is obtained (DST CMP true) PAL no. 2 moves to
state F.
PAL no. 1 remains in state C until the ACK RCVR state
sequence

State

if
is

entered

State

"receiver

clear"

state

which

PAL no.

from

state

entered

occurred.

state

returns
F

the

from

the

packet

true

state

After

clearing

idle

source

destination

the

state
byte

entered

or C. State D
true but RDAT

State D

not an ACK response).

is a message packet,

(this

mismatch

PAL no.

an improper response is obtained i1n states A, B,
entered from state A if CHAR SYNC and WACK are

REG 7 = 0
is

completed.

mismatch

complementary

various

receiver

occurred.

destination
functions,

(state A).

checked.

The

link

then

passes

CRC checker which

checks

to state G provided this is not a maintenance operation (INT MLOOP
false). If this is a maintenance operation (INT MLOOP true), the
link

goes

state

G the

CRC

for

any CRC error.

CRC

checker)

State

bytes

input

When MAX CRC

the

returned

their

The last
MX STATE

state in a
M asserts,

various

are

link moves

the

last

receive

state

functions

idle

the

asserts

state

(last

CRC byte

the ACK RCVR sequence.
are

into the

cleared

and

then

this

both

state

PALs

are

states.

MESSAGE XMIT state sequence is state M. When
an ACK timeout counter is enabled and starts

counting. If, after 3.66 microseconds, the ACK RCVR sequence 1is
not completed, the counter asserts ACK TO which terminates the
sequence and returns both ACK RCVR PALs to their idle states. The
port then reads status bits to determine the trouble.

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2-66

Sync Character Detect Enable PAL -- The purpose of the

2.10.2.2

2-3)

1is

the detector when transmitting from this node.

The

sync

character

detect

PAL

enable

(Figure

the

enable

sync character detector when a packet 1is expected and to inhibit

sync character

detector should be enabled during the following times:
A.

During an internal maintenance loop operation.

After a transmission when an ACK packet is expected.

To receive a message packet from another node taking care
respond

not

transmissions

(transmission of an ACK packet).

Figure
enable

applied

functionally illustrates the sync character detect
ENA SYNC DET is asserted by any of five signals

2-29
PAL.
to

node

this

from

an output OR gate,

When in maintenance loop operation, INT MLOOP is true and enables
the

detector.

sync

The next two signals enable the sync detector when an ACK packet

is received.

state

negated

One

is generated by ANLCing CARRIER DET A with the
ICCS

PATH

while

the

other

generated

ANDing CARRIER DET B and the asserted state of ICCS PATH B. Thus,

the two gates look for a carrier presence in both CI paths.
Enabling of the two gates is restricted to ACK packets by ACK ENA
which asserts while waiting for an ACK packet (WACK true) and
after a loss of carrier has been sensed. The carrier lost would be
the message transmit carrier from this node.

false)

enables one of the AND gates

ICCS PATH B (true or

in the ACK ENA logic.

When

that gate senses a loss of carrier (CARRIER DET negates), ACK ENA

asserts and is latched. The next time a carrier is sensed (the ACK

response), the output AND gate is enabled and asserts ENA SYNC DET

via

the

output

The

last

are

enabled

two

OR gate.

signals

when

detector

enable

the

sync

not

transmitting

message

packet 1is received. The signals are generated by AND gates which
when

the

node

message

packet

(both FORCE PATH signals false), and a carrier is detected on one
of the CI paths. The gates are inhibited by trailer delay (TR DLY)
which is true at the end of an ACK transmission when the packet
trailer

being

transmitted.

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2-68

Message Receive

2.10.3

Figure 2-30 illustrates the message receive state logic. 1t is
used in conjunction with the MSG RCVR GSTATE diagram in the
engineering
state

drawing

Two

set.

are

PALs

used

message

the

for

RVI'R

seqguence.

INITIALIZE from the port asserts ABORT + INIT FCN which 1in turn
asserts RINIT. RINIT initializes the logic in the receilve channe]
and

places

and

not

two

the

state

TPAlLs

into

their

transfers

to MR

state

RCVR

MSG

1dle

stat-s

(state A for PAIL no. 1; state M for DPAIL no. 2). When the receiver
is not disabled due to transmission from the transmit channel
(RXMIT false), a valid packet is in the receive channel (CHAR SYMNC
true), and the packet is recognized as a message (RDAT REG 7 = 0)

that

state R,

asserted

contains

valid

packet

enabled and

MR state

VALID RCVR

the

1is

DATA

being

indicating

length

starts

¢ on

PAL no.

an ACK;

is asserted

received,

that

information.

receiving

the

byte

Also,

the

the packet bytes.

PACKKT

and

being

CRC

The

indicating

LENGTH

transferied

checker

link moves

the next clock pulse.

In MR state C the true destination byte is checked. If a match s
obtained (DST CMP true), the link woves to state D. PACKET LENGTH
remains asserted in state C as the byte being transferred to the
PBE contains packet length information.

MR state

D the

match is obtained

complement destination byte

(DST CMP true),

checked.

the link moves to MR state E.

In MR state E the packet source byte is clocked into the true and

complement ACK destination registers to serve as the destination

for the ACK response. The next RCVR CLK pulse moves the link to MR

state

PAL no.

1 remains in MR state G for the rest of the MSG RCVR state

sequence. The assertion of MR STATE G enables PAL no. 2 in that it

allows it to move from its idle state (state M) to state H when
its condition signal (RCVR PACKET END) 1is asserted.

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If any of the three condition tests made by PAL no.
link is transferred to MR state F.
would

1 fails, the

Failing any of the three tests

be:

while in state A with RXMIT false, CHAR SYNC asserts but

(this is an ACK packet)

RDAT REG = 1

A true destination mismatch occurred in state C

A complement destination mismatch occurred in state D.

In MR state F the receive logic is cleared, and PAL no. 1 returns
to the idle state (state A) on the next RCVR CLK pulse.

idle state (state M) while the packet
the PB. After the last byte of the
to
body is being transferred
in

remains

PAL no.

its

body has been sent to the PB, the PB asserts RCVR PACKET END and
PAL no.

to MR state

goes

In state H the packet CRC bytes are input to the CRC checker. When

the last byte is in the checker, MR CRC 3 asserts. If there 1s no
the
CRC error, CRC OK is true when MR CRC 3 asserts. In this case,false
is
OK
CRC
error,
CRC
a
is
there
If
link moves to state I.
and

the

link

goes

state

In state I the MSG RCVR state sequence

1is aborted. The receive

channel is cleared, PAL no. 1 is moved to its 1dle state (state

A), and PAL No. 2 moves to its idle state (state M) .

The message receive state sequence remains 1in state I while the
link

transmits

asserts

TACK

the

ACK

(transmit

response.

ACK)

The

the

assertion

ACK

transmit

STATE

PAL

state

initiating the ACK transmit sequence. When the ACK transmission 1is

done AX STATE H negates to assert ACK DONE to MSG RCVR PAL no. 2.

The assertion of ACK DONE moves the link to MR state K.

In MR state K the receive channel

is cleared and PAL no.

1 1is

returned to its idle state (MR state A). The next RCVR CLK pulse
return PAL no. 2 to its idle state (state M).
The message

receive

state

logic

contains

header

timeout

counter

to prevent receive
ICCS PATH SELECTED

channel hangups. The counter is turned on by
(removes the counter LOAD signal) and cleared

3.66 microseconds)

and outputs

HEADER TIME OUT.

CLEAR

the

logic.

by CHAR SYNC. It thus starts counting when a carrier is detected
and is cleared when the carrier is recognized as being a valid
packet. If SYNC CHAR fails to assert, the counter t imes out (1in
The

assertion

HEADER TIME OUT causes MSG END + HTO to assert, thereby asserting
RCVR

reset

receive

The header timeout counter is enabled and disabled at the RCVR CLK
t«
rate via a flip-flop. Thus, the four-bit counter is extended
x
(32
five bits, producing the 3.66 microsecond timeout period

disabled
114.28 ns = 3.66 microseconds). Note that the counterit 1ischanne
1s
by WACK. WACK asserts in MX state M when the transm the detecltion
nts
transmitting a message packet. Thus, WACKingpreve
header timeour
the
start
from
er
carri
of the transmitted

period.

RCVR. One of
Other signals besides MSG END + HTO assert CLEAR
ed) which asserts 1f a
these is RCAR DROP (receive carrier dropp
SELECTED
carrier is 1lost during a message reception. ICCS PATHCHAR
SYNC
es after
asserts before CHAR SYNC asserts and negat
PATH
ICCS
lost,
urely
premat
is
r
negates. If a receive carrie
RCAR
ng
causi
true,
still
is
SYNC
CHAR
SELECTED will negate while
to the ANDing
DROP to assert. Note that CHAR SYNC 1s not appliedgates
CHAR SYNC
which
flop
flipa
operation until MR STATE E sets
state E
MR
until
SYNC
CHAR
ing
Delay
to the RCAR DROP AND gate.

allows the header portion of the packet to pass before the node
looks for carrier drop—out.

ACK Transmit
2.10.4
mit state logic and 1is used
Figure 2-31 1illustrates the ACK trans
ing
in conjunction with the ACK XMIT STATE diagram in the engineer
drawing

set.

initializes the link
INITIALIZE from the port asserts TINIT which
AX state A is the
PAL.
XMIT
ACK
and asserts AX STATE A from the
ACK) 1is received from

ACK transmit idle state. When TACK (transmitAX state B.
the MSG RCVR state PAL, the link goes into

d and outputs the
In state B the sync/trailer PROM logic 1is enable
byte onto the
cter
chara
sync
the
and
bit synchronization bytes
r is also enabled. When
YMIT DATA BUS. The selected transmit drive
SYNC/TR GONE asserts, the link transfers to state C.

9id)

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The link
the

ACK

type

byte

1is

generator is enabled.
state

While in state C,

for one clock pulse.

in AX state C

placed

onto

the

XMIT

DATA

BUS

and

In AX state E the
the XMIT DATA BUS.

output

state

onto

placed
state

onto

the

ACK complement destination byte 1is placed
The link then advances to AX state F.

onto

XMIT

DATA

placed

In AX state F the ACK source byte 1is
BUS. The link then moves to state G.
AX

CRC

In AX state D the ACK true destination byte is placed
XMIT DATA BUS. The link then advances to AX state E.

the

The next XMIT CLK pulse moves the link to AX

onto

the

CRC

BUS

bus,

bytes

TDATA
MAX

generated

and

bus.

CRC

When

the

asserts

the

last

onto

CRC

moves

the

generator

byte
the

has

link

are

been

In AX state H the sync/trailer PROM 1is enabled again and the
packet trailer bytes are output from the PROM onto the XMIT DATA
After the trailer bytes have been placed onto the bus,
BUS.

SYNC/TR
state

GONE

asserts

(state A).

and

returns

the

ACK

XMIT

PAL

its

1idle

Note in Figure 2-31 that the assertion of each gate coupling a
byte to the XMIT DATA BUS depends on the negation of the gate that
coupled the preceding byte to the bus. This insures that only one
source is driving the XMIT DATA BUS at any one time.

CHAPTER 3
BUFFER MODULE

PACKET
NOTE

The
3

functional

use

block diagrams

1logical

AND

and

in Chapter

symbols.

does
not
necessarily
follow
that
a
corresponding gate exists on the packet

buffer

1logic

prints.

inputs
output

A
C

and
may

B causing the assertion of
be represented on a block

diagram by a
engineering

single AND gate,
yet the
drawing
may
show
that

several
the

circuit

ANDing

The

stages

assertion

are

involved

operation.

functional

chapter

The

are

block

keyed

diagrams

the

packet

module
(PB)
engineering
schematics
(CS
prints)
by

this

buffer

circuit
1letter

designations

in parentheses. The letters
specify
the
PB CS
sheet
that
contains
the detailed
logic
associated with the
functional

blocks

The

names

used

signal

block

diagrams

engineering
signal names
enclosed
3.1

DATA

FLOW;

are

the

packet

the

functional

names

used

the

parentheses.

GENERAL

DISCUSSION

buffer

module

data
flow through the packet
of
messages
and
data,
flows

(PBR)

packets

Data going to the CI bus flows from the data
the link while data received from the CI bus
to

CS
prints.
Where
other
or notes are used, they are

Figure
3-1
1is
a
block
diagram of
buffer.
Information
in
the
form
through

diagram.

various

size.

path module (DP) to
flows from the 1link

DP.

A transmit buffer (TBUF)
is in the data path to the CI bus and a
receive buffer
(RBUF)
is
in the data path from the CI bus.
The
buffers

Six

are

loaded

operations

buffers.

Four

for

under

LOAD

VALID

RCVR

RBUF

MLOAD

RBUF

READ

READ
DATA

control

transferring
normal

maintenance
and
listed below:

TRANSMIT

TBUF

read

used

TBUF

are

AL
WHN -

are
used
for
operations are

and

are

the

port

microcode.

data

and

out

transfer

self-directed

data.

the

The

other

two

commands.

The

six

XNWI 3N8Y

TBUF LOAD

3.1.1

Data from the DP is loaded into the TBUF via the TBUF in register.
The TBUF LOAD operation is controlled from the PB.
3.1.2

TRANSMIT

3.1.3

TBUF

Data is read out of the TBUF into the 1link via the TBUF
register. The TRANSMIT operation is controlled by the link.

out

READ

k
Data is read out of the TBUF back into the CP via the loopbac
the
on
data
d
receive
register. The loopback data is muxed with the
RBUF DATA <7:0> data lines and returned to the port bus via the PB
read mux. This operation is controlled by the PB and is used for

maintenance and self-directed commands.

VALID RCVR DATA

3.1.4

Received data (RCVR DATA <7:0>) from the link is loaded into the
RBUF via the RBUF in mux and the RBUF in register. The VALID RCVR
DATA operation is controlled from the link.

RBUF MLOAD (Maintenance Load)
3.1.5
Data from the DP (PORT DATA <7:0>) is loaded into the RBUF via the

RBUF in mux and the RBUF in register. The RBUF MLOALD operation 1is
controlled by the PB and is used for malntenance purposes.,
RBUF READ

3.1.6

Data is read out of the RBUF to the DP via the RBUF out register
and the PB read mux. The data from the RBUF out register is muxed
with the loopback data on the RBUF DATA <7:0> cata lines. The RBUF
READ operation is controlled by the PB.
PB Read Mux

3.1.7

Other data is provided to the CP over the PORT DATA <7:0> bus via
the PB read mux. This data is NODE ADDRESS <7:0> and XMIT STATUS
status
<7:0> from the link,

logic

the

and receive status

from the receive

PB.

Control Logic

3.1.8

The PB operations are controlled by decoding and sequencing logic.
A function decoder issues commands that specify the operation to
be executed. Buffer select 1logic selects the buffer for the
operation specified by the function decoder. If a TBUF is selected

the control
(there are two), the TBUF sequencing logic generates logic
exists
cing
signals for the operation. Corresponding sequen
for

the

RBUFs

which

generate

the

control

signals

for

RBUF

operation,

The function decoder and buffer select logic are controlled by the
port microcode.

TBUF

3.2

DATA FLOW OPERATIONS

The TBUF (Figure 3-2) is divided into two parts (TBUF A and TBUF
B) with each TBUF having a separate, parallel data path. Thus,
throughput

increased

that

TBUF

can

loaded

from

the

LCP

while TBUF B is being transmitted to the link. Each TBUF has 1K of
storage. The following discussion will describe TBUF A and its
data path. TBUF B and its data path are identical to TBUF A.
3.2.1

TBUF

LOAD

SELL. TBUF A enables TBUF A, selecting it for a TBUF A operation. WR
TBUF A enables the TBUF A input and disables the output thereby
setting up TBUF A for a write. (TBUF A has a common I/O.) A data
byte (PORT DATA <7:0> is clocked into the TBUF A in register Dy
PORT CLK. PORT CLK also clocks a parity bit (PB PAR) from the
into the TBUF parity in register. TBUF A REG ENA then asserts
enable the data byte (TBUF A DATA
PAR A) to be written into TBUF A.
The TBUF

address

A address

counter.

to loading

counter is
the

buffer,

(TBUF

The

A ADDR

counter

a data packet

<7:0>)

<9:0>)

cleared

into TBUF A.

and

the

obtained

parity

bit

from

the

(TBUF

TBUF

by CLR TBUF A ADDR prior
each byte

1s written,

incremented by CLK TBUF A ADDR to the next location

the

1in

When the last byte of the data packet is on the port data bus, a
LOAD LAST DATA BYTE flag is asserted and clocked into a "last byte
in" register by PORT CLOCK. The flag is written into TBUF A along
with the last data byte and its parity bit. The flag 1s used to
indicate

the

operation,

end of

the

data

packet

the

link during

a TRANSMIT

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TRANSMIT

3.2.2

SEL TBUF A enables TBUF A, selecting it for a TBUF A operation. WR
TBUF A is false to inhibit the TBUF A input and enable the output

for a read. The TBUF A address counter
ADDR to address location 0 in TBUF A.

cleared

CLR

TBUF

The first data byte is read out of TBUF A from address 0. The byte
(TBUF A DATA <7:0>) is clocked into the TBUF A output register by
XMIT CLK from the 1link. "TBUF A OUT ENA" 1is true and gates the
data byte out of the register as XMIT DATA <7:0>. The parity bit
from TBUF A (TBUF PAR A) is gated to the TBUF parity out register
where it is clocked in by XMIT CLK. The data byte is clocked into
the TBUF A out register at the same time the parity bit is clocked
into the TBUF parity out register.

The data byte

parity

the

availble

now

The parity bit

checker.

link

as XMIT

DATA

(XMIT CATA PARITY)

and

<7:0>

from the

TBUF parity out register is also applied to the parity checker. If
a parity error 1is detected, XBUF PE is asserted to the DP where it
sets

error

bit

the

port

maintenance

control

and

status

(PMCSR).

XMIT DATA PARITY is also applied
the XMIT DATA

<7:0>

data byte.

to the

link as

the parity bit

for

CLLK TBUF A ADDR increments the TBUF A address counter to the next
The address counter 1s a 1K counter
location in the buffer.
locations of TBUF A. In practice, a
1K
the
addressing
of
capable
packet will be less than 1K bytes of data; thus, the address
counter should never reach a full count. If the counter 1is not
a full count may be
cleared prior to a TRANSMIT operation,

reached. In this event, TBUF
BUFFER EMPTY to the link.

When the

last data byte

is read

is also read out and clocked

OVFL

comes

true

and

asserts

the

BUS

LAST TBUF bit

from TBUF A,

"last byte out"

into the

XMIT CLK. This in turn asserts XMIT BUFFER EMPTY to the
indication that it has received the entire data packet.
3.2.3

TBUF READ

XMIT

link as

(Loopback)

SEL TBUF A enables TBUF A, selecting it for a TBUF A operation. WR
TBUF A is false to inhibit the TBUF A input and enable the TBUF A
output for a read. The TBUF A address counter 1is cleared by CILR
TBUF A ADDR to address location 0 in TBUF A.
The first data byte at address 0
(TBUF A DATA <7:0>) and 1its
parity bit (TBUF PAR A) is clocked into loopback register A by CLK
TBUF

true
the

A ADDR.

and

Signals

respectively

read mux

and

"LOOPBACK

the

couple

parity

REG A

ENA"

the

data

bit

(RBUF

and

byte

PAR)

TBUF

(RBUF
to

READ ENA are

DATA

the

DP.

<7:0>)

CLK TBUF A ADDR increments the TBUF A address counter to the next
location

in the buffer.

3.3

RBUF DATA FLOW OPERATIONS

(RBUF A and RBUF
path. RBUF A
data
l
paralle
e,
B) with each RBUF having a separat
by the DP,
read
being
is
B
RBUF
while
link
can be loaded from the
storage.
of
1K
has
RBUF
Each
ut.
throughp
greater
thus allowing
path.
data
its
and
A
RBUF
describe
will
on
The following discussi
is divided into two parts

The RBUF (Figure 3-3)

RBUF B and its data path is identical to RBUF A.
3.3.1

VALID RCVR DATA

A VALID RCVR DATA operation is an RBUF load of received data from

the link. The operation is initiated and controlled from the link.

SEL RBUF A enables RBUF A, selecting it for an RBUF A operation,
WR RBUF A enables the RBUF A input and disables the output,
setting up RBUF A for a write. (RBUF A has a common I/O.)

The data byte and parity bit from the link are input to the PB
through an RBUF in mux. The mux uses two select signals; one for

the data byte and one for the parity bit. When mux select signal
RBUF INPUT MUX SEL is false, the data byte from the link (RCVR
DATA <7:0>) is applied to the RBUF A in register as RBUF IMUX DATA
<7:0>. The byte is clocked into the register by RBUF REG CLK and
then gated to RBUF A by the true state of RBUF A REG ENA.

RBUF REG CLK also clocks the parity bit (RCVR DATA PARITY) into
the RCVR parity in register. When mux select signal RBUF MLOAD 1s
false,

from the

the parity bit

applied

to RBUF A as

PARITY.

A address (RBUF A ADDR <9:0>)
The RBUF

is obtained from the RBUF A

address counter. The counter is cleared by "CLR RBUF A ADDR" prior
to loading in a data packet. As each byte is written,

the counter

is incremented by CLK RBUF A ADDR to the next location 1in the
buffer. The address counter is a 1K counter capable of addressing
the 1K locations of RBUF A. In practice, a packet will be less

than 1K bytes of data; thus, the address counter should never
reach a full count. If the counter is not cleared prior to a VALID

RCVR DATA operation,

a full count may be reached.

In this event,

RBUF A OVFL asserts and terminates the VALID RCVR DATA operation.

The link uses a RCVR byte counter to indicate when the data packet

has been loaded into RBUF A. The first two bytes of a data packet
specify how many data bytes are in the packet (packet length).
PACKET LENGTH from the link asserts and loads the first two packet
length

bytes

into

the

RCVR

byte

counter.

The

counter

down

counter which is decremented by RCVR CLK each time a byte
loaded into RBUF A. RCVR PACKET END asserts when the packet
completely

loaded.

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RBUF MLOAD (Maintenance Load)

3.3.2

for an RBUF A operation.
cel RBUF A enables RBUF A, selecting it and
disables the output,
1nput
A
WR RBUF A enables the RBUF
setting up RBUF A for a write.

via the port data bus and
The data packet is obtained from the DP
mux. When muX select signal

in
input to the PB through the RBUF
bytes from the port bus (PORT
data
true,
RBUF INPUT MUX SEL is
register as RBUF IMUX DATA
A 1in
DATA <7:0) are applied to the RBUF the
register by RBUF REG CLK and
into
ed
<7:0>. The bytes are clock
RBUF A REG ENA.
then gated to RBUF A by the true state of

the TBUF
The parity bit from the port bus (PB PAR) is clockedto into
RBUF 1in
the
ed
appli
then
and
parity in register (Figure 3-2)
TBUF
true,
MLOAD
RBUF
mux as TBUF PARITY. With mux select signal
PARITY is coupled to RBUF A as R PARITY.

A
The RBUF A address (RBUF A ADDR <9:0>) is obtained from theA RBUF
ADDR"

cleared by "CLR RBUF
address counter. The counter is
As each byte is written, the
t.
before loading in a data packe
ADDR toO the next location 1in
A
counter is incremented by CLK RBUF
the

buffer.

RBUF Read
3.3.3
tion.
ting it for an RBUF A opera
SEL RBUF A enables RBUF A, selec
the
le
enab
A input and
WR RBUF A is false to inhibit the RBUF
output for a read. The RBUF A address counter is cleared by "CLR

RBUF A ADDR" to address location 0 in RBUF A.

(RBUF A PAR) read
A data byte ("RBUF A DATA <7:0>) and parity bit
ter by CLK RBUF
regis
out
A
out of RBUF A are clocked into the RBUF
and parity bit
byte
data
the
A ADDR. EN RB A is true, gating out
RBUF B in the
(READ
ly.
ctive
as RBUF DATA <7:0> and RBUF PAR, respe
applied to
is
PAR
RBUF
A.)
RB
RBUF B data path corresponds to ENplaced on the port data
bus via

the DP while RBUF DATA <7:0> is
the

read mux.

asserts and couples the
When reading RBUF A out to the DP, EN RB ABUS
RBUF DATA <7:0> bus
to the
data in the RBUF A out register
The data in the RBUF A out
before CLK RBUF A ADDR asserts. RBUF
A ADDR asserts and clocks
register is undetermined until CLK
ter. Thus, when
the first data byte from RBUF A into the regis
invalid data.
as
byte
first
reading RBUF A, the DP discards the

to be done
The reading of a data packet from RBUF A does not have
and the
read
ally
parti
in consecutive cycles. The packet can betime.
ion
operat
read
a
If
remainder of the packet read at a later

is interrupted, the first data byte read when the read operation
is continued,

is valid data.

PB Read Mux
read mux muxes

3.3.4
The PB

the

port

the

RBUF

data
DATA

STATUS,
<7:0>,

and

bus

and

<7:0>

READ

XMIT

signals

relating

read

the

lines

are

<7:0>,

<K7:0>

selected.

STATUS
and

come

PB.

"RCVR

received

enabled

NODE

"RCVR

status".

from

data

from

and

eight

(Paragraph

whenever

any

not

status

3.8).

from

3.4

ENA

link

<7:0>

Three clocks are used within the PB and these are obtained
the DP and the link (Figure 3-4). The three clocks used are:

MUX

the

ALDDRESS

1link

comprised

XMIT

ADDRESS

four

signals

1is

READ

NODE

the

onto
asserted,

ADR,

select

directly

status"

REALC

respectively

each

the

select

mux

four signal groups of eight bits
PORT DATA <7:0>. When READ BUF 1s

RCVR

STATUS

pertain

The

asserted.

CLOCKS

PORT CLK?*

2.
3.

XMIT CLK
RCVR CLK

PORT

CLK

1s obtained from
involve data flow to

that

the

PP and synchronizes all operations
from the DP. PORT CLK has a 200 ns

the

link

and

synchronizes

flows

from

the

period.

XMIT

CLK

1is

obtained

operation

which

has

period.

114

RCVR

CLK

DATA

operation

CLK

has

1is
a

obtained

114

from

data

from

which

period.

the

link

data

flows

Figure 3-4 illustrates the six
synchronize them. Note that the

(RBUF
RBUF

(RBUF

loaded

The
1s

PORT CLK when

MLOAD

operation),

from

the

TBUF

and

link

RBUF

synchronizing

and

(VALID

address
the

the

link

operations

being

CLK

RCVR

DATA

operation).

are

PB.

CLK

RCVR

clocked

the

REG CLK.

from

RBUF

whichever

the

being

clock

operation.

the PB

to PORT CLK.
The
two
signals
hence the different mnemonics.

when

loaded

RCVR

* PORT CLK T3 also appears on

VALID

the

synchronized by RBUF

RBUF

counters

the

TRANSMIT
XMIT

the clocks that
that load the RBUF,

particular

the

link.

and

operations

are

the

synchronizes

from

two

MLOAD and VALID RCVR DATA)
REG CLK

and

fan

logic prints but
out

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3.5
The

FUNCTION DECODER AND BUFFER SELECT LOGIC
SELECT bit from the microword asserts for one microcycle

and

enables the function decoder and the buffer select logic (see
Figure 3-5). Four 1link control bits from the microword (LINK

CONTROL

<3:0>)

which

control

codes are

microcycle.

one

outputs

decoder

The

the

carry

function
shown

function

thirteen

command

possible

and

commands

in Table 3-1.

their

the

commands

function
for

associated

one

link

The following paragraphs describe each of the function commands.
SEL LOAD BUF

3.5.1

Prior to issuing a load buffer command

(LOAD BUF or LOAD LAST DATA

BYTE), or a RESET TBUF command, the microcode selects the buffer
with the SEL LOAD BUF command. The selection is made by the buffer
select logic during the microcycle in which the microword SELECT

bit is true. The selected output is latched and remains true until
SELECT asserts again and another buffer is selected.

SFL LOAD BUF enables the "load" section of the buffer select logic
which outputs one of four "buffer load enable" signals according
to port data bits PORT DATA <7:6> (Table 3-2).
SEL. READ BUF

3.5.2

Before issuing a read buffer command (READ BUF) or a RELEASE RBUF
command, the microcode selects the buffer with the SEL READ BUF
command. The selection is made by the buffer select logic during
the microcycle in which the microword SELECT bit is true. The
selected output is latched and remains true until SELECT asserts
again and another buffer is selected.

SEL READ BUF enables the "read" section of the buffer select logic
which outputs one of four "buffer read enable" signals according
to port data bits PORT DATA <7:6>
LOAD BUF

3.5.3

(Table 3-3).

The LOAD BUF command loads port data

the

SEL LOAD BUF command.

The

into the buffer

RBUF MLOAD. The VALID RCVR DATA operation (loading
from the link) is not a function of the PB microword.
A data packet does not have to be loaded
packet can be partially loaded and the
loaded

later

selected

load operations are TBUF LOAD and
of

the

RBUF

in consecutive cycles. A
remainder of the packet

time,

When loading a TBUF,

the

last byte of data must be

LOAD LAST DATA BYTE command.

loaded with a

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Table 3-1

Link Control

Codes Vs

Function Commands

LINK CONTROL

Function Command

LOAD

—-—-

TRANSMIT

-—-

"Enable

"Disable

READ

RCVR

STATUS

READ

XMIT

STATUS

READ

BUF

LOAD

BUF

RELEASE

RESET

SEL

READ

BUF

SEL

LOAD

BUF

READ NODE ADR
LAST

DATA

BYTE

1link"

link"

RBUF

TBUF

Table 3-2

PORT DATA

Load Buffer Select Code

Buffer Selected

TBUF A LOAD ENA

TBUF B LOAD ENA

RBUF

RBUF B MLOAD ENA

Table 3-3

PORT DATA

A MLOAD ENA

Read Buffer Select Code

Buffer Selected

RBUF

RBUF B READ ENA

TBUF A READ ENA

TBUF B READ ENA

A READ

ENA

LOAD LAST DATA BYTE
LAST DATA BYTE command

3.5.4
The LOAD

the

load

command

for

the

last

byte of data loaded into one of the TBUFs.
It performs the same
function as a LOAD BUF command and in addition, loads a "last data
byte" bit into the TBUF along with the data byte.
3.5.5

The

SEL

via

READ BUF

REALD

READ
the

BUF

command reads data from the buffer selected by
command. The data is read out to the port data

read

initiated by the

link.

The

read

operations

are

TBUF

READ

and

RBUF

(reading of the TBUF to the 1link)

PB microword

but

separate

1is

command.

TRANSMIT

3.5.6

The

mux.

The TRANSMIT operation

READ.

the
bus

TRANSMIT

After

operation.

command

the

The

link

"last data byte"

During

the

reads

command

data

continues

flag

microcycle

read

that

from

1issued,

reading

the

selected

1link

TBUF

selected

the

read

TBUF

until

the

port

data

controls

out,.

TRANSMIT

true,

one

is sampled to determine which TBUF will be
(PORT DATA 1)
bits
transmitted. A TBUF XMIT flip-flop asserts TBUF A XMIT ENA 1f the
port data bit is false, and TBUF B XMIT ENA if the bit is true.

only one TRANSMIT operation can be executed at a time, (Only one
TBUF can be read at a time by the link.) A TBUF must be completely
read, or the operation aborted and the transmit
before another TRANSMIT command can be issued.

the

cleared,

RESET TBUF

3.5.7

The

status

RESET TBUF

command

resets

TBUF.

selected

3.5.8

RELEASE

3.5.9

READ NODE ADR

the

address

counter

associated

with

RBUF

The RELEASE RBUF command resets the address counter associated
with the selected RBUF. It also clears the "full" flag (negates
RBUF FULL; Figure 3-9) for the selected buffer making it available
to the link for a VALID RCVR DATA operation.

The READ NODE ADR command selects the node address (NODE ADDRESS
<7:0>) from the link to be muxed onto the port data bus by the PB
read

mux.

3.5.10

READ XMIT

The

READ

XMIT

STATUS

<7:0>)

the

read

STATUS

command

selects

the

transmit

status

(XMIT

from the link to be muxed onto the port data bus by

mux.

READ RCVR STATUS
s"”
the eight "receive statuThe
STATUS command selects bus
RCVR
The READ
the PB read mux.
bits to be muxed onto the port data1in Parabygrap
h 3.8.
3.5.11

"receive status" bits are discussed

Link Enable and Link Disable

the link
ands are used inasse
and "link disable"thecomm
The "link enable”
rt PB
to
than
r
othe
PR
on
module and perform no function
le the path to the link for the
LOAD. PB LOAD must be true to enab3.6.)
raph
3.5.12

commands. (See PB LOAD; Parag

PB LOAD
3.6
the DP is obtained from a
Data placed on the port data bus fromoutp
ut is enabled by PB LOAD
32-bit PB OUT register. The register
all commands that require

from the PB. PB LOAD is assertedPB for
OUT register to the port data
data to be transferred from the
bus.

(See Figure 3-6.)

and function for
an eight-bit disable commvia
An eight-bit enable and to
the port data
DP
the
from
the 1link
the link is transferred
pertain to the
these commands do not to
bus (Figure 3-1), Although LOAD
transfer the
r
orde
in
be true

ired that PB ster to the port data bus.
PB, it is requthe
PB OUT regi
commands from

Referring to Figure 3-6:

ands reguire port data
SEL LOAD BUF and SEL READ BUF comm
or
bits PORT DATA (7:6) to select which buffer to load
read.

LOAD BUF and LOAD LAST DATA BYTE commands obtain the byte

ires PORT DATA ] to select which
The TRANSMIT command requlink
.

to be loaded from the port data bus.

TBUF to transmit to the

path
ble” commands require a bus.
"rLink enable" and "link disa
data
port
the
to
DP
the
on
from the PB OUT register

SEQUENCING LOGIC
generates the
tion decoder and buffer select logicRBUF
func
The PB
load/read
and
the TBUF
necessary signals to enable
tions
opera
six
the
nent to each of
operations. The signals perti3.7.
is
er
buff
A
The
.
3.7.6
1 through
are discussed in Paragraphs corre
B
the
for
s
exist
sponding logic
used in all the discussions.
ed
ciat
asso
c
logi
ng
strates the sequenci
buffer. Figure 3-7 1illu
ations. Figure 3-8 illustrates the
oper
TBUF
e
thre
with the
sequencing logic associated with the three RBUF operations.
3.7

(SELLOADBUF
SEL READ BUF
LOAD BUF

(FIG. 3-5) J LOAD LAST DATA BYTE
TRANSMIT

PB LOAD
|

(FIG. 5-2)

(LINK ENABLE)

l\ (LINK DISABLE)
NOTES:
1. THE LOGIC IN THIS FIGURE IS CONT

AINED
ON SHEET A OF THE ENGINEERING DRAWI
NGS.
TK-7789

Figure 3-6

PB Load Logic

3.7.1

The

TBUF

LOAD

sequencing

1is

1logic

3-7.

Figure

1in

illustrated

Before a TBUF LOAD operation is initiated, a RESET TBUF command 1is

issued to clear the selected TBUF address counter. The RESET TBUF
command is ANDed with TBUF A LOAD ENA to assert CLR TBUF A ADDR.
The next PORT CLK pulse asserts CLK TBUF A ADDR which clears the

counter.

requires

(The

1is

counter

address

clock

pulse

while

the

clear

counter

asynchronous
input

true

which

order

reset.)

The TBUF

LOAD operation

initiated

the

LOAD BUF

command.

The

LOAD BUF command (or LOAD LAST DATA BYTE if this is the last byte)
is ANDed with TBUF A LOAD ENA

pulse width

flip-flop to be

flip-flop output

(or TBUF

LOAD ENA)

to enable

set by the next PORT CLK pulse.

the

The

is ANDed with TBUF A LOAD ENA to assert WR TBUF A

and SEL TBUF A. SEL TBUF A enables TBUF A and WR TBUF A enables it
for

load.

The output of the pulse width flip-flop is delayed 80 ns, and then
used to clear the flip-flop. Thus, SEL TBUF A and WR TBUF A become
80

pulses,

Another

output

the

pulse

width

flip-flop

delayed 20

and

ANDed with TBUF A LOAD ENA to assert TBUF A REG ENA and CLK TBUF A
ADDR. These two signals are also 80 ns wide and are delayed 20 ns
with respect to SEL TBUF A and WR TBUF A.

TBUF A REG ENA gates the output of the TBUF A in register to TBUF
A. Delaying TBUF A REG ENA allows time for the tri-state output of
TBUF A to be disabled by WR TBUF A before the write data is gated
into TBUF A from the TBUF A in register.

The TBUF A address counter is incremented on the trailing edge of

CLK TBUF A ADDR.
disabled

Delaying CLK TBUF A ADDR assures that TBUF A 1s

(SEL TBUF A is negated)

before the address

to the next location.

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TRANSMIT
3.7.2
A
Figure 3-7.
The TRANSMIT sequencing logic 1is illustrated incomm
the
from
and

both a TRANSMIT
TRANSMIT operation requires
link. XMIT
DATA ENA signal from the tran
XMIT
the
function decoder and
smitted
ive
rece
to
DATA ENA is true when the link is ready
data

from the PB.

the selected TBUF
Before a TRANSMIT operation can be executed,
operation the
SMIT
TRAN
address counter must be cleared. Inof a TRANS
ad of by a
inste
MIT
counter is cleared by the assertion
A XMIT ENA to

d with TBUF
RESET TBUF command. TRANSMIT is ANDeCLK
pulse asserts CLK TBUEF A
assert CLR TBUF A ADDR. The next PORT
it
ADDR. Clocking the counter with the clear input asserted resets
to

zero.,

A XMIT ENA to assert "TBUF A OUT
XMIT DATA ENA is ANDed with TBUF enabl
es TBUF A. "TBUF A OUT ENA"
A
ENA" and SEL TBUF A. SEL TBUF TRBUF
A register to the 1link.
gates the data byte out of the

A address counter during the
CLK TBUF A ADDR increments the TBUF
XMIT
asserted by the ANDing of izes
TRANSMIT operation. The clock 1is CLK.
hron
sync
link
the
,
Thus
XMIT
DATA ENA, TBUF A ENA, and
XMIT CLK.
the address counter with

TBUF READ (Loopback)

3.7.3

in Figure 3-7.
The TBUF READ (loopback) sequencing logic is shown befor
e the TBUF
to zero
The TBUF A address counter must be reset code
resets the address
READ operation can be executed. TheSELmicro
LOAD BUF command (asserting
counter by selecting TBUF A with a
logic) and then asserting
TBUF A LOAD ENA from the buffer select RESET
TBUF and TBUF A LOAD
g of
the RESET TBUF command. The ANDin
CLK
ENA asserts CLR TBUF A ADDR. The next PORT CLK pulse asserts
TBUF A ADDR thereby resetting the counter.

BUF and TBUF A READ
Wwith the address counter reset to zero, READ
SEL
PBACK REG A ENA" and SEL TBUF A. from
ENA are ANDed to assert "LOOPBAC
data
the
K REG A ENA" gates
TBUF A enables TBUF A. "LOO
loopback register A onto the RBUF data lines.

PORT CLK asserts CLK
The ANDing of READ BUF; TBUF A READ ENA, and
CLK
TBUF A ADDR. Thus, the address counter is synchronized by PORT
from

the

DP.

3.7.4

VALID

RCVR

DATA

The

RCVR

DATA

logic

VALID

address
counter
Thus, the VALID

is illustrated in Figure 3-8.
The RBUF
1is cleared
at
the end of all RBUF operations.
RCVR DATA operation will start with the address

counter

set

already

The VALID RCVR DATA
under
1link
control.
buffer

(RBUF

but

the

When

"RBUF

both

operation 1is initiated and executed entirely
Consequently,
the
selection of
the
receive

RBUF

load

RBUFs

zero.

are

not

selection"

empty,

made

logic

RBUF

the

shown

buffer

selected

select

Figure
to

logic

3-8.

receive

the

data

packet as described below.
The RBUF A LOAD ENA and the RBUF B
LOAD ENA flip-flops are initially in the reset state. Signals RBUF

A FULL
When

ENA

and

VALID

flip-flops
The

RBUF

RCVR

are

FULL

DATA

ENA

are

false

asserts,

the

VRD

enabled

corresponding

and

RBUF

become

LOAD

set

ENA

keeping

After

the

asserted

RBUF

packet

the

LOAD

1is

ENA

loaded

receive

are

RBUF

empty).
LOAD

ENA

RCVR CLK pulse.

flip-flop

does

not

RBUF

logic.

set

VALID RCVR DATA
loaded, holding

flip-flop

into

status

RBUFs

the

the negated state of RBUF A FULL ENA.
while the entire data packet is being
and

(both

and

set

via

RBUF

When

VALID

due

stays
"VRD"

feedback

true
true
gate.

FULL

ENA

RCVR

DATA

asserts

to load another packet, the true state of RBUF A FULL ENA inhibits
the setting of the RBUF A LOAD ENA flip-flop but allows the RBUF B

LOAD ENA

flip-flop

the

data

Selection

RBUFs

assert

and

causes

full,
the

the

and

the

The

load

DATA.

will

are

and

RBUF

load

status

Paragraph

are

OVFL

ENA

the

RBUF

flip-flop

assert

RBUF

width

the

enables

RBUF

flip~flop

flip-flop,

into 50

and

raise

not

selected

empty

RBUF

executed.

flag

the

has

overflowed

"VALDAT"

RBUF A

REG
to

RCVR

RBUF

for

converting

pulses,

logic

output

SEL

the

nor

synchronized

ENA

counter

assert

The

pulse

receive

RBUF.

Dboth

LOAD ENA will

This

condition

both

the

1link

3.8).

false),

flip-flop.

LOAD

initiated

address

1is

RBUF

alternate

operation will

operation

"VALDAT"

Thus,

RBUF A

neither

set.

neither

(see

LOAD

output

continue

receive

packet.

the

SEL

asserts

ENA.

CLK

and

SEL
50

and

RBUF

and

RCVR

OVFL

ANDed

with

ENA gates

the

1is

pulse-width

LOAD

ENA

enables

RBUF

output

the

then

and

VALID

RBUF

the

RBUF

operation.

REG

sets

with

(both

RBUF A

RBUF

ANDed

load

delayed

assertion

The

the

fed
WR

back

RBUF

reset

signals

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Another output

ANDed

with

RBUF

from
A

the

LOAL

pulse-width

ENA

of the pulse-width flip-flop
the
1incrementation
of
the
synchronized by RCVR CLK.
The
CLK

RBUF
RBUF

that

After

CLK

disabled

the

data

(SEL

ENA

asserts

out

the

has

indicating

signals

pulse,

CLK

preparing

been

negated)

loaded

clock

the
RBUF
of RBUF A

flip—-flop

and

The

RBUF

LOAD

CLR

the trailing
20 ns, it is
before

into

cycle,

RBUF

3.7.5

RBUF

this

Refer
to
assertion

RBUF

The

and

setting

hence
also
|

RBUF

that

During

asserts

counter,

ALDR.

the

edge

of
assured

address

location.

packet

port.

delayed 20

1is synchronized by RCVR CLK,
RBUF
A
address
counter
1is

address
counter must
be
reset
to
zero.
operation,
VALID RCVR DATA negates.
One

these

RBUF

A address counter is incremented on
A ADDR. By shifting CLK RBUF A ADDR

RBUF

changed

flip-flop

assert

ADDR

RBUF

ADDR.

full

the

RBUF

of
the
RBUF
A

and

ready

state

both

clears

the
the

next
RBUF

read

RCVR
A

1load
FULL

negated

and,

This

RBUF

At
the
end
cycle
later

of
CLK

address

A READ operation.,

MLOAD

load
selection
1logic
MLOAD ENA directly sets

directly

ENA

MLOAD

resets

true

the

during

operation

1is

RBUF

the

RBUF

LOAD

in
Figure
3-8.
the RBUF A LOAD
ENA

flip-flop.

The
ENA

Thus,

MLOAD operation.

1initiated

the

assertion

LOAD

BUF. The LOAD BUF command is ANDed with RBUF MLOAD (asserted by
either RBUF A MLOAD ENA or RBUF B MLOAL ENA) to assert RBUF INPUT
MUX SEL. RBUF MLOAD and RBUF INPUT MUX SEL switch the RBUF 1in mux
to

select

the

parity

bit

and

the

data

byte

from

the

DP.

RBUF

INPUT

MUX SEIL also enables the MLOAD flip-flop to be set by the next
PORT CLK pulse. The flip-flop output ("MLOAD")
is ANDED with RBUF
A MLOAD ENA to assert RBUF A REG ENA. RBUF A REG ENA gates the
output

the

"MLOAD"
1s

ANDed

also

SEL

RBUF

output

back
A

with

sets

the

RBUF

enables
the

reset

signals

Another

RBUF

into

output

pulse

LOAD

RBUF

pulse

the

width

from

RBUF

flip-flop.

The

ENA

assert

RBUF

and

RBUF

enables

delayed

flip-flop

flip-flop,
ns

converting

SEL

flip-flop

output

and

SEL

for

load.

and

then

fed

RBUF

and

the

RBUF

The

pulses.

the

pulse

width

flip-flop

delayed

and

ANDed with RBUF A LOAD ENA to assert CLK RBUF A ADDR. The setting
of the pulse-width flip-flop is synchronized by PORT CLK
(via the
MLOAD flip-flop), hence the incrementation of the RBUF A address
counter

1is

also

synchronized

PORT

CIK.

The RBUF A address counter is incremented on the trailing edge of

CLK RBUF A ADDR. By shifting CLK RBUF A ADDR 20 ns, it is assured
RBUF A is disabled

that

changed

the

before

(SEL RBUF A false)

address

location.

to the next

After the MLOAD operation is completed, the RBUF A address counter
must be reset to zero. The microcode accomplishes the reset by
selecting RBUF A with the SEL READ BUF command (asserting RBUF A

from

ENA

READ

and

logic)

select

buffer

the

then

asserting

the

The

RBUF

REALD

RELEASE RBUF command. The ANDing of RELEASE RBUF and RBUF A READ
ENA asserts CLR RBUF A ADDR. The next RCVR CLK pulse asserts CLK
RBUF A ADDR,

thereby resetting the counter.

RBUF READ

3.7.6

The RBUF READ logic

illustrated

Figure 3-8.

A READ

ENA

operation is initiated by the assertion of READ BUF. The READ BUF
command

is ANDed with

RBUF

assert

and

SEL

signal

RBUF A. SEL RBUF A enables RBUF A and EN RB A gates the data from
the

RBUF data

RBUF A out register onto the

(The

lines.

the RBUF B data path corresponding to EN RB A is READ RBUF B.)
The ANDing of READ BUF,

and PORT CLK asserts CLK

RBUF A REALD ENA,

RBUF A ADDR. Thus, the RBUF A address counter is synchronized by
PORT CLK

After

from

the

counter

the

LP.

READ RBUF

must

operation

reset

zero.

completed,

The

selecting RBUF A with the SEL READ BUF command

READ ENA

from the buffer

RELEASE RBUF command.

select

logic)

and

RBUF A ADDR thereby resetting

A address

this

asserting

the

does

(asserting RBUF

then

The ANDing of RELEASE RBUF

ENA asserts CLR RBUF A ADDR.

RBUF

the

microcode

and RBUF

A READ

The next PORT CLK pulse asserts CLK
the

counter.

3.8

RCVR

STATUS

"RCVR status" is placed on the port data
when
the
READ RCVR
STATUS
command
is

bus from the PB read mux
asserted.
"RCVR
status”

consists

described

3.8.1

eight

through

signals.

3.8.7,

CRC

ERR

RBUF

FULL

are

RBUF

4,
5.

RBUF
RBUF

B FIRST
A BUS

RBUF

7.
8.

RCVR
RCVR

A ENABLE
B ENABLE

Figure

3-9

3.8.1

signals,

Paragraphs

below:

BUS

1llustrates
CRC

The

listed

the

RCVR

status

logic.

ERR

The link does a CRC check on received data packets. The
status CRC ERR bit is asserted if a CRC error 1is detected.
ERR bit is used only in maintenance loop modes. It is not
normal operation.,

receive
The CRC
used in

The CRC ERR bit asserts after the associated data packet has been
loaded into the RBUF. Thus,
1f a CRC error is flagged, the packet
containing the error is in the RBUF.

VALID RCVR STATUS asserts after a data packet has been loaded into
the
RBUF
with
a
VALID
RCVR
DATA
operation.
If
no
CRC
error
occurred, CRC STATUS 1is true when VALID RCVR STATUS 1s asserted.
This causes CRC OK to assert. CRC OK enables the CRC OK flip-flop
to set on the next RCVR CLK pulse. The asserted output from the
flip—-flop

results

negated

CRC

ERR

bit

for

RCVR

STATUS.

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3.8.2
If RBUF

RBUF A FULL, RBUF B FULL
A had just been loaded with a data packet having no CRC
error, CRC OK is asserted and ANDed with RBUF A LOAD ENA to enable
the RBUF A FULL ENA flip-flop to set. RCVR CLK sets the flip-flop
asserting
RBUF
A
FULL
ENA.
The
flip-flop
1is
held
set
via
a
feedback

gate

holding

RBUF

FULL

pulse asserts RBUF A FULL via
A FULL 1s true it asserts REC

RBUF A 1s emptied
After a READ RBUF
reset

the

link.

The

RBUF

(read out to
operation, a

address

CLR

with

the

and

releases

via

two

state

RBUF

set

out;

therefore,

RBUF

The

READ

ENA

will

CLK

RBUF

ENA

PORT CLK.

REALC

PORT

When

release

flip-flops.
B

flip-flop.

by a READ RBUF operation.
RBUF command is issued to

counter

negated

flip-flop

the DP)
RELEASE

command

RBUF

true.

RBUF

RELEASE

asserting

ENA

the RBUF A FULL
ATTN to the DP.

RELEASE

has

false.)

back

the

1link

RBUF

enable

(RBUF
be

by
ANDed

1is

the

first

CLR

just

been

read

output

from

The

the first
is set by

flip-flop enables the second CLR RBUF A flip-flop which
RCVR CLK. Thus, CLR RBUF A is synchronized by RCVR CIK.

CLR

RBUF

flip-flop

breaks

set.

the

This

feedback

negates

Should

both

FULL

and

RBUF

from

the

RCVR

3.8.3
If both

another

occurred

the

bit

FULL

status"

RRUF

asserted

VALID

have

for

RBUF

ENA

FULL

RBUF

and

1link

RBUF

corresponding

FULL

preventing

load

ENA

FULL,

"RBUF FULL" logic exists for RBUF B. If the data packet
1loaded
1into
RBUF
B
1instead
of
RBUF
A,
an
1identical
would

ready

the

Identical
had
been

"RCVR

holding

that

sequence

RBUF

indicating

causing

RBUF

latch

both

link.

RBUF

1logic

assert.
be

true,

RCVR

BUFFERS

1initiating

FULL

from

another

true),

the

RBUF

FIRST

status

first.

The

RBUF

FIRST

status

DATA operation,

RBUF B FIRST
RBUFs are full

bit

indicates

bit

which

invalid

(not

RBUF

(RBUF

FULL

was

filled

sampled)

until

both

RBUFs

are

filled.

RBUF B FULL ENA is ANDed with CRC OK and the negated state
FULL to enable the first RBUF B FIRST flip-flop to be set

of
by

RBUF
RCVR

CLK.

The

second

flip-flop

RBUF

FIRST

set

flip-flop

RBUF

1is

full

but

set

PORT

CLK

still

not

RBUF

asserting

RBUF

FIRST.

RBUF

loaded

while

RBUF

full,

RBUF

FULL

asserts

holding the first RBUF B FIRST flip-flop set via a feedback gate.
With both RBUFs full, the RBUF B FIRST bit is sampled and found to
be

true.

RBUF A BUS
indicates which

3.8.4
This bit

loaded into RBUF A.

on CI bus A.
bus

the

bus

received

If the bit is negated,

bit

asserted,

the

1last

data

packet

the pack was received

pack was

received

while RBUF A is being loaded, RBUF A LOAD ENA is true. RBUF A LOAD
ENA is ANPDed with VALID RCVR STATUS and ICCS PATH B. Thus, when
VALID RCVR STATUS asserts, the ICCS PATH B signal 1is sampled. If
the signal is true, the data packet just loaded into RBUF A was
received on CI bus B. In this case, the RBUF A BUS flip—-flop 1is
enabled and sets on the next RCVR CLK. When the flip-flop sets,
the RBUF A BUS bit is asserted as part of "RCVR status."
3.8.5

RBUF B BUS

indicates

bit

This

loaded

into RBUF B.

bus

bus A.

The

RBUF

BUS

the

RCVR A

bus

If the bit

bit

logic

replacing RBUF A.

3.8.6

which

received

is negated,

asserted,

identical

the

pack

the

1last

data

the pack was

RBUF

was

packet

received

BUS

logic

with

ENABLE

This bit is set if the RCVR A ENB bit (bit<00>) of a "link enable"
command byte is set. The RCVR A ENB bit must be set for the link
to

respond

3.8.7

traffic

bus

RCVR B ENABLE

This bit is set 1if the RCVR B ENB bit (bit <07>) of a "link
enable" command byte is set. The RCVR B ENB bit must be set for
the

link to respond

to traffic on CI bus B.

CHAPTER

STORE

- CONTROL
NOTE

The functional block diagrams in Chapter
It
4 use logical AND and OR symbols.
that

necessarily

not

does

the
on
exists
gate
corresponding
n
assertio
The
prints.
logic
ing
engineer
on
asserti
the
causing
B
and
A
of inputs
C may be represented on a
by a single AND gate, yet
diagram
block
drawing may show that
engineering
the
of

output

involved

The block diagrams are keyed to
schematics
circuit
engineering
ions
designat
1letter
by
prints)

the
(CS
1in

circuit

several

stages

are

the ANDing operation.

The letters specify the CS

parentheses.

sheet that contains the logic associated
the
1in
blocks
functional
the
with
function
CS
the
for
logic
The
diagram.
discussed in this chapter, 1is divided
A
between the DP and the PB modules.
specifies
diagram
block
each
on
note

which module contains the logic used in
the

diagram.

The signal names used in the functional
block diagrams are the names used on the
CS

engineering

Where

prints.

enclosed

parentheses.

SIMPLIFIED BLOCK DIAGRAM

4.1

The

used

control

store

microwords.

the

Fach

other

they are

signal names or notes are used,

(Figure

4-1)

consists

port microcode.

microword

consists

The

bytes

microcode
47

uses

storage

48-bit

bits

contrcl

(BUS

The 3K of

U<46:00>) and a sync bit used for maintenance purposes.
storage consists of 2K of RAM and 1K of PROM.

The RAM area of the CS is written during the uninitialized state.

IB IN <31:00> from the DP is placed on the CS I/0 bus (BUS
The lower 32 bits are
U<46:00>) and then written 1into the CS.
written

Bit

bit).

first and

the

then

the

parity bit

A parity check

upper bits.

for

the microword

(excluding

is performed on each microword

the

sync

read out of

the CS during the initialized state when the microcode 1is running.
If

a parity error

error

flag.

is detected,

CSPE

asserted

the

DP as

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Most

the

microword

the

microword

port

read

The

from

the

(CS

1is

outputs

latched

control

into

signals

the

all

modules.

The CS
1s
addressed
via
12
address
bits
(CSA
<11:00>)
obtained
from
either
the
microsequencer
or
the maintenance
address
register.
In the uninitialized state
(e.g.
during power up)
the
maintenance address register provides the address (MADR <11:00>).
The register input is IB IN <12:00> from the LP.
The microcode
start-up
logic
enables
the
maintenance
address
register
by
asserting EN MALR.
In

the

initialized

address
enabled

microsequencer

base

bits.

control
a

uses

address.

address

the
PC

state

(while

1s provided by the
by
EN
SEQ
from

bits

Branching
The
SEQ
for

BUS

The

<4:0>

U<11:00>

1is

running)

from

the

microword

to specify the
are selected by

which

actually

are

the

The microsequencer 1is
start-up
logic.
The

is used
conditions

microsequencer

address

microcode

logic

branching

CNTL

microword.

counter

bits

the

microsequencer.
the
microcode

bits

contains

control,

the

lower
four
sequential

BUS

memory

U<16:12>

stack

and

The

CS
microword
and
the
contents
of
the
meintenance
address
register can be read by the DP via the maintenance mux.
The mux
selects the lower 32 bits of the microword, the upper bits of the

microword,

input
Figure
and

or
the
13
bits
the DP (31:00).

4-2 -is

should

detailed

referred

from

block

the

maintenance

~
diagram

to throughout

the

rest

control

this

store

chapter.

area

5-13

EN CS DATA IN [~

18 IN <31:00

00>

CS WE

B IN <12:00>

oom=mrs

?,18553,

.
BUS U <46:00>

ol (FIG. 46)

MAID

BUS U <45:00>

BUS U <46:32>j
MADR <12:00>

?EUL)ECT
(U)

(R)

dammm
;
!

LOGIC.

MADR <11:04>

MADR

<03:00>

MADR <11:00>

IBSRC2

BUS
U <22:21>

1B SRC <1:0>

BUS U <20:17>

.
{> IB DST <3:0>

(FIG. 5-16)

(FIG. 5-6)

SEQUENCER
FIG. 4-

BR <3:0>

CONTROL

DFE

(FIG. 4-9)

E%Jg §J2>
:

<
\____BUS U1

[ BUSU09

N BUSU 007

BRANCH
LOGIC
(FOIG
2100

——

b |
|

FIG.

(BRANCH CONDITIONS)

SEQ CNTL <4:0>

(V)

SUSPEND DEL
FIG. 5-17)
PMUX <1:0>

BUS U 05

ASRT DEAD

1[:@

| BUSU04

MCLR

INTR

PE VLD

WRT

UP PDN

INH RBPE
BUS U 00

LOGIC CLR

SET A GO
SET B GO

5-23)

(V) INITIALIZE _ (ric. 3.5; 2-25: 2-30)

BUS U 03

L (NOT USED)

—————(NOT USED)(FIG.

BUS U 01

»(FIG. 5-3)

_> ((FIG.527)

ASRT FAIL

___BUSUO8

N—

=T CORTROL <ic()t=>|c; 3-5; 2-21)

| BUSU10

BUS U<11:00>

(FIG. 3-5; 2-21)

SELECT

BUS U <29:28>

___BusU02

COMMON 1/0.

LITERAL <7:0>

| (FIG. 4-12)UNS'§?TCLK T3

( 5-25 )

(FIG. 5-8)

=
ALU A/B <3:0>

BUS U <27:24>

(FIG. 4-12)

Y-

BUSU 30

{1 FORCE ZERO

CLK cLR

|ALUSRC<2:0>

ALU DST <2:0> )

BUS
U <31:24>

MICROCODE

STARTUP

SEQUENCER

l ENSEQ T

MICRO-

<§51:50>

MODULE

cLk .|(P)

(V)

@us U <36:33>
i

MAINT.
ADDRESS

SYNC
» (BACKPLANE FLAG)
MICROWORD ALY FCN <2:O>¢

\_BUS U <42:40>

MICRO-

\ EN MADR

TS
=

L BUS U <39:37>

2911

1. THE LOGIC SHOWN IN

PARENTHESES REFER TO
ENGINEERING DRAWINGS
CONTAINING CORRESPONDING

~ BUS

u47

2. LETTER DESIGNATIONS IN

~ BUS

| CSA <11:04>

MADR 12

(FIG, £-13) —=< MADR

AS NOTED.

~ BUS

\ e

IB IN <12:00>

ON THE PB MODULE EXCEPT

~ BUS

MADR 12

THIS DIAGRAM IS LOCATED

~ BUS

U<16:12>| U <11:00> | U <32:24>| U <45:33> |9U <23:17> BUSU
23 [N\

NOTES:

+ (FIG. 5-3; 5-10)

CHECKER

CSA <03:00>

(U)

(FIG, ' 5.13) —BUS LSA GO

PARITY

CSA <11:00>

MADR <12:10>

MAINT.

u47

~ BUS U <31:00>

.
(31:00)

BUS U <46:00>

EN RBPE

(FIG. 5-25)
+» (FIG. 5-13)

‘

» (FIG. 5-27)

(FIG. 6-14)
+ (FIG. 5-27)
(FIG. 5-10)

MISC CNTL

READ BUF

(FIG. 3-5)
MKV84-0141

Flgure

4-2

Control

Store

Plock

Ciagram

MICROWORD PARITY

4.2

1is read out of CS.

is made on each microword as

A parity check

BUS U<46:00> is input to a microword parity checker which outputs
Bit 46 1is the
CSPE to the DP if a parity error 1is detected.
Also, note
parity bit generating odd parity for each microword.
that

parity

the microword

with

The SYNC bit

(U47)

bit

programmable

error
the

the

microword

the

PROM

parity bits

area whose

1is a

the CS microwords,

that can be used with any of
in

contalning

in the parity check as

included

is not

the microwords

even

resets

error.

cannot

changed.

Figure 4-3 is a block diagram of the parity checker. Each byte of
the microword is checked for odd parity in parity generators.
Those bytes with an odd number of bits asserted will assert the
output of their respective generator. The generator outputs are
themselves input into a summation parity generator where again an

asserted output means an odd number of asserted inputs. This 1s a
state which would condition the parity error

"no error"

flip-flop

reset.

If the number of asserted inputs to the summation parity generator

is even, the generator output is false and the parity error
flip-flop sets on the next SEQ CLK T3 pulse. When the flip-flop
4.3

asserted.

MICROWORD

Microword Fields

4.3.1

bits of the CS microword are shown

The 48

CSPE

sets,

Table 4-1

fields.

describes each of

Figure 4-4,

grouped

are

latched

the

fields

the

shown

in the

figure.

4,3.2

Microword Register

When a microword

the microword

into

fields

are

the

SRC

and

select

The

the

read

of CS,

out

SEQ CLK T3.

field

next microaddress,
DST

most

and

and the

the

bits

The

remaining

SEQ CNTL field

used

bit

IB SRC and IB DST fields.
at

the

in the uninitialized state and whenever

the

fields

must

present

the

start of the microcycle, hence, they cannot wait for SEQ CLK T3 to
clock

the microword

The register

is reset

current microword produces a parity error.

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1 1 1 1
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1
T 1
ALU A/B

ALU FCN{ALU SRC ALU DST

]

PAR

‘

TYPE

SYNC

LITERAL

{

LINK AND

BUFFER CONTROL |
R

e — A ——
PMUX

NOT USED

LINK

CONTROL

SELECT

23 22 21 20 19 18 17 16 15 14 13 12
L

1 1
T 17
SEQ CNTL

1T 1
IB DST
L1 1

1
IB SRC

11 10 09 08 07 06 05 04 03 02 01 00
0 0 17T 1T 11
1 1 1 0

I]l
INTR|

MCLR

NEXT MICRO ADDRESS

17T

MISCELLANEOUS

lllllllllllllI
CLR

\7\5&

(NOT USED)
INITIALIZE

|ASRT | SET | UP
DEAD

éo

VLD ASRT

PDN

NOT USED

INH RBPE
SET
B GO

FAIL

MKV84-0132

Figure 4-4

Microword Fields

Table

Bit

Name

SYNC

4-1

Microword

Fields

Description
A

programmable

during

bit that is
debugging

port

indicate

the

execution

used
to

specific microword.
The
SYNC
bit
1is
not
1included
1in
the
parity check of the microword.
The

SYNC bit can be written
both the RAM and PROM areas
the CS. The bit is available

PAR

the

port

The

odd

<45:00>

<45:43>

ALU

FCN

<2:0>

<42:40>

<39:37>

<36:33>

ALU

SRC

DST

A/B

<2:0>

<3:0>

the

backplane.
parity
of

Function

in
of

the

bit

code

bits

microword.

for

the

2901

ALU

code

for

the

DP.

Operand

source

2901

ALU

the

Cestination
ALU

the

The

and

the

2901

DP.

code

for

the

2901

lines

for

DP.

address

scratch

pads

the

definition

bits

DP.

<31:24>

TYPE

LITERAL

<7:0>

Selects

the

<31:24>

Valid

the

shown

when

below.

TYPE

Used

number

1in

address.
<31:24>

SELECT

Link

and

when

TYPE

are

de?ined

Not

used.

Indicates
lines

<29:28>

<27:24>

PMUX

LINK

<1:0>

CONTROL

The

bits.

Valid

bit

fields

below.

that

the

(<27:24>)

Selects

<3:0>

control

byte

buffer

input

registers

LINK

are
in

the

and

the

CONTROL

valid.
packet

output

DP.

Specifies

operations

link

and

PB.

valid

when

SELECT

This
=

the

field

1is

Table 4-1

Microword Fields (Cont)
Description

Bit

Name

<23:21>*

IB SRC

<2:0>

<20:17>*

IB DST

(3:0)

<16:12>

SEQ CNTL

(4:0)

1IB

LCP.

the

data

BUS

source

the

gelects

gelects the destination for BUS
the

IB data

DP.

specifies the operation of the
2911 microsequencer, selects
that
conditions
branch
the
alter

selects

and

microaddress,

the

the definition

bits

<11:00>.

<11:00>

Next microaddress

This field is the base address
that is modified by the branch
bits to form the address of the

next microword. It allows the
any
to
Jjump
to
microcode
field
This
address in the CS.
is valid so long as the SEOQ
CNTL field is not all 1ls.
<11:00>

MISC

CNTL

field

This

allows

control)

(miscellaneous

microcode

the

flags

miscellaneous

control

and functions in the port.
1is wvalid when the
field

CNTL

field

all

1ls.

The

The
SEQ

MISC

CNTL bits are described below.
used.

'MCLR

Not

INTR

Sets the interrupt request flag
1interrupt
initiates an
that
to

sequence

the

host

CPU.

INITIALIZE

Generates

initialize

signal

CLR REG WRT

Clears the REG WRT flag

in the

VLD

the

link.

DP.

when
is

the

set,

power-fail

the

ASRT

valid

DEAD and

FAIL bits are valid.

bit
ASRT

* These bits bypass the microword register and go directly to the
DP.

Table
Name

ASRT

DEAD

ASRT

SET

Microword

Fields

(Cont)

Description

Bit

4-1

FAIL

Facilitates
initialization

and

processor
booting.

Facilitates
initialization

and

processor
booting.

Starts an external bus transfer
with
the
host
wusing
the
A

parameters,

SET

Starts an external bus transfer
with
the
host
using
the
B

parameters.

INH

Allows the microcode to set the
PDN
(power
down)
bit
in
the
port configuration register.

PDN

RBPE

This

bit

read

packet

1s
the

INH

RBPE

Not

byte

from

always

used.

The

first

byte

undefined

data.

prevents

from

undefined
00

during

buffer.

read
error

set
first

asserting

data.

parity
on

the

MAINTENACE MUX

4.4

During the uninitialized state the CS can be read by the LCP for
The CS microword is input to the DP via a
maintenance purposes.
maintenance mux and a 32-bit bus
(31:00).
The microword
1is

applied
lower

mux

the maintenance

bits

U<46:32>; U47).

U<31:00>)

(BUS

wupper

the

then

and

first

the muX

where

selects
bits

address

The DP can also read the 13 bits from the maintenance
register (MADR <12:00>) via the maintenance muX.
MUX selection is accomplished using one of the
address

logic

to select

false

selects

XBUS

address.

maintenance

(XBUS

from the DP

bits

the

upper

LSA 00

upper or

portion

lower portion of

the microword.

(BUS

U<46:32>;

4.5.1

Control Store Space

(Figure

4-5)

The

control

bits

(CSA

<11:10>)

(1K)

word

locations within each bank.

The

flag

store

flag

storage

U47).

has

the

throughout

the

MALR

MADR 12 true

(BUS U<31:00>).

CONTROL STORE SPACE AND LOGIC

space

and

used here

4.5

store

store address

the maintenance

the microword

lower portion

the mux selection code.

local

from

MADR 12

and

selects either

MADR 12

selects the

the

00)

LSA

the

(BRUS

Table

a microword

4-2

lists

store

area

and a flag store area. The microword store area consists of 1K x
47 of PROM and 2K x 47 of RAM. The area is addressed by 12 control
store address bits CSA <11:00>. The two most significant address
divide

the

store

programmable

area

bit

even

area

SYNC bit

thus

for each word

can

the

1is

(U47).

giving

written

location

CSA

SYNC

anywhere

microwords in the
in as bit 47.

bit written

area

into

three

banks

and

are

RAM

wused

store

the

Bits CSA <09:00> address the 1024

used as the bank select bits.

<11:00>

bit

also addresses

location

the microword

across

PROM

area

the

store

address

(bank

the

the 3K of

area.

The

spectrum;

could

store

flag

have

SYNC

thus,

SYNC

Table 4-2

Maintenance Mux Selection Code

32-Bit Bus

(31:00)

XBUS LSA 00

MADR 12

BUS

BUS U<46:32>;

MADR

negated
asserted
care

don't

U<K31:00>

<K12:00>

U47

: T 1

1.1 11

MICROWORD
STORE

3072

RAM

1111

, 00

0000

000G

BANK 2

2048

,00

0000

00000
1

BANK 1

1094

;00

0000

000

0
0

FLAG
STORE

PROM
fl

00
—CSA

CSA 01

CSA 02

0
BANK

47 BITS

—+] 1817 ja—

CSA 03

CSA 04

CSA 05
CSA 06

CSA 07

CSA 08
CSA 09

. _ o

CSA 10 (MADR 10) }BANK SELECT
CSA 11 (MADR 11)
TK-8724

Figure 4-5

Control

Store

Space

4.5.2

Figure 4-6

Control Store Logic
is

comprised

onto

the

block

six

microword

I/0

bits

seven

outputs only

diagram

bus

(BUS

I/0

Bits MADR

are

lines

<11:10>

logic.

The

high-order

U<46:00>).

Banks

bits
PROM

each

are

and

Bank

eight

outputs

Each RAM has a

(identical

bank

select

bits.

signals.

When

true,

each

are

they

store

four-bit I/O to the

(BUS U<46:44>).

the

where

PROM

The high-order RAM in each bank uses only three of

microword bus.
four

control

Each

(BUS U<46:40>).

made up of twelve 1K x 4 RAMs.
its

the

PROMs.

decoded

to CSA <11:10>

They

are

shown

applied

SEL BANK signal

Figure 4-5)

select

logic

SEL BANK enabling

three

to output one of

bank

enables

all

the

RAMs

(or

selected

bank

are

four

are
Address bits CSA <09:00>
1its respective bank.
in
PROMs)
(or
RAMs
the
only
however,
PROMs;
and
applied to all the RAMs
The
address.
the
to
respond
will
in the enabled bank
PROMs)
address bits select a location in each of the RAMs (or PROMs) of
the

bank.

selected

bits

All 47

available

addressed

from the

bus

microword

the

location

write operation. All 47 bits are read simultaneously.

The

RAMs

two

each.

The

(BUS U<15:00>),

part

receives

banks

CS&

writable

parts

MID

are

bits

each

write

and

enable

three
are

parts

designated

(BUS U<46:32>).

and HI

(BUS U<31:16>),

separate

into

are divided

during

except

reading

for

Each

signal.

To write the CS RAMs, the signal CS WE is asserted from the DP and
then ANDed with MALCR 12.

thus

enabling

Write

data

the

asserts WR CS HI,

DATA IN)

(IB

MADR false

enabling

is received

LO and WR CS MID

write.

for

the HI part

for a write.

a data

in enabling

and

IN<31:00>)

asserts WR CS

parts

MID

and

from the DP.

MADR 12

true

MADR

(EN CS

signal

is ANDed with EN CS DATA

IN to again select the high or low portion of the microword. When

MADR

The

flag

written

false,

1IN<31:00>

coupled

BUS

U<31:00>

true,

1IN<14:00>

1is

coupled

BUS

U<46:32>

into the LO and MID parts of

selected RAM bank.

the

written into the HI part of the selected RAM bank.

the

flag

store

reading
along

The

store

microword

flag

input

output

except

with

RAM

its

store

to the

being

addressed

(U47)

during

associated

flag

written

by CSA<K11:00>

the

available

write

microword
on

the

operation.

select

store

bit

area.

microword

and

When

bus

and

The

for

read

out

input microword.

The

Bit

U47

microword.

store RAM

bit 47
IB

IN 15.

the

The

flag

store

is enabled

by WR CS HI. Thus, the flag is written when IB IN <14:00> is being
coupled to BUS U <46:00> and the upper portion of the microword

being

written.

1is

EN CS DATA IN

[ (1) )
)

MADR

IB IN <31:00>

IBIN <14:00>

IBIN 15
CSA <11:00>

)

BUS U<46:32>

FLAG -

]

RAM

ADDR

WR CS HI

[(\T)\

U<31:00>

STORE

CSA <11:00>

(FIG. 4-2){

BUS

(T)

(W)
*{WREN

FIG

4-2
BUS U<46:00>

BUS

1BUS

U<46:44> | U<43:40> | U< 39:36>|

BUS

U<35:32>

|U<31:28>|U<27:24>| U<23:20>

BUS

CSA <09:00>
]

*’

k—.

SEL BANK 2

SELECT

SEL BANK 1

LOGIC

SEL BANK O

(R)

£ RAM

RAM

RAM
RAM
(1K X4) ] (1K
X 4) | (1K
X 4)

(TIKX4)]

—»{\WR EN
-

(N)

BUS

G
CS WE

Ifi(m WR CS HI |

»|

RAM
RAM
RAM
RAM
(MK X4)] (MK X4) | (1K
X 4) ]| (1K
X 4)

Fb WR EN

(N)

BUS

(N)

BUS

(N)

(M)

RAM

(M)

BUS
BUS
BUS
|U<31:28>|U<27:24>|U<23:20>| y<19:l16>

(N)

Lo] WR EN

(N)

(M)

BUS
BUS
BUS
BUS
|u<i15:12>|Uu<11:08>| U<07:04>| U<03:00>

ADDR

= RAM

(1K
X 4)| 1K
X 4) | (1K
X 4) | (1K
X 4)

RAM | RAM
RAM
RAM
(MK X4)| (1K
X 4) | (1K
X 4) ]| (1K
X 4)

! WR EN

» ADDR

o N RAM

ADDR

o|en

BUS

|U<43:40> |U<39:36>[U<35:{32>

—»{ ADDR

wrcsmID

BUS

| U<15:12>|U<11:08>| U<07:04>|U<03:00>

ADDR

U<46:44>

BUS
U<19:16>

*
ADDR

MADR <11:10> | o\

BUS

RAM

(N)

(M)

MKXM (1IKX4) | KX
4)| (1K
X 4)

Lol WREN

(N}

RAM

EN ik xa)]

RAM

(M)

(ik x4) | (1K
X 4) | (1K
X 4)

ol WR EN

(M)

(R)

WR CS LO

MADR 12

7m
)j

(.BUS
U<46:40>

fBUS

(-BUS

iBUS

U<39:32>

U<31:24>

U<23:16>

U<15:08>

U<07:00>

»| ADDR

__.®

PROM

(1K X 8)

NOTE:

LETTER DESIGNATIONS IN PARENTHESES REFER
TO THE PB ENGINEERING DRAWINGS CONTAINING:
THE CORRESPONDING LOGIC.

(N)

PROM

(1K X 8)
(N)

PROM

(1K X 8)
(N)

PROM

(1K X 8)
(M)

PROM

(1K X 8)

(M)’

(M)

TK-8726

Figure

4-6

Control

Store

Logic

4-15

4.6

The

CONTROL

STORE

ADDRESS

addressing

bits

(CSA

maintenance

address

SOURCE

<11:00>)

are

the

obtained

from

microsequencer

either

the

1logic.

The

selection 1s made by the microcode start-up logic which asserts EN
MACR to enable the output from the maintenance address register,
or

SEQ

4.6.1

The

enable

the

Maintenance

maintenance

<12:00>

from

<12:00>.

All

back

into

select

logic

bits

When

32-kit

bus.

select

bus.

MADR

low

portion

bus.

MADR

<11:10>

the

high

also

the

used

muxed

<11:00>

1is

from

the

wicrosequencer.

onto

4.6.2
Microsequencer
The microsequencer logic
microsequencer
control
various microsequencing

and

maintenance
12

portion

the

logic

for

common

lines

with

the

2911

MADR

mux

read

for

1in

the

mux

microword

select

the

from

the

bank

the

outputs

used

written

Logic
consists

receives

MALCR

low

used

the

MADR

2911

the

microword
in

bits

the

applied

the

over

the

has

enabled

are

for

TIP.

high

microseguencer.

Address

address

the

2911

selection.

12-bit

output

microsequencer,

the

1logic
which
regulates
and
controls
functions, and the branch logic.

the

4.6.2.1
2911 Microsequencer -- The 2911 microsequencer outputs a
12-bkit address onto common address lines MALDR <11:00> where it 1is

muxed

with

the

12-bit

Figure

that

microseqguencer

the

outputting

the

MALCR

four

bits

address

bits

lines

respectively.

branch

bits

The

the

muxing

comprises

the

MADR

<11:04>

1lower

four

from

bits

the

address
Also

2911

<chips,

The

upper

eight

address

bits

CSA

(MADR

branch

function.

three

lines.

become

maintenance

<03:00>)

logic

the

note

each

bits

<K11:04>,

are

CRed

with

produce

<03:00>.

lower

the

microsequencer

four

onto

<03:00>

CSA

from

illustrates

(MALCR

The

receives

4-7

output

bkits

the

four

bits

outputs

onto

the

microword

formulate
from

MADR

the

lines.

the

(RBUS

U<11:00>)

microword

address.

that

are

used

Each

correspond

chip
its

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Figure 4-8 is a functional block diagram of a 2911 microsequencer
chip. The source of the four-bit chip output could be an address
register
(which
would
be
the
four
next
address
bits
from
the
microword), a 4
x 4 memory stack,
or a PC counter/incrementer.
A
mux
selects
the
address
source
according
to
select
code
<S1:S0>
from the microsequencer control logic.
The

memory

stack

enabled

file

enable

(FE)

received

microword
via
the
microword
control
(PUP)
1is
also
obtained
microword register,

The
stack
microword

FORCE

start-up

1logic

ZERO

from

microsequencer

the

output

microcode

causing

the

output

all

from

the

push/pop
via
the

negates

the

zeros.

4.6.2.2
Microsequencer Control Logic -- Figure 4-9
is
a
block
diagram of the microsequencer control logic.
BUS U <16:12> is the
microsequencer
control
field
in
the
CS
microword.
The
field
specifies how the next CS address is formulated.
BUS

<K16:12>

control

logic.

CNTL

SEQ

becomes

SEQ

CNTL

SEQ CNTL
<1:0>
are
stack
enable
logic.
defaults

(DFE)

from

false

(0)

enable

false.

CNTL

<4:0>

respectively

SEQ

CNTL

from

the

mux

false,

select

logic

negated.

also

control

logic

The

responds
to
SEQ
CNTL
<1:0>;
has no effect, while the stack

<4:0>

within

goes

the

branch

the

bits

and

this
case,
the
mux
select
logic
and SO true
(1), and decoded file

stack

(DFE)
SEQ

logic
(DPUP)

1inhibited

the

control
push/pop

CNTL

the

output
enable

push/pop

stack

however,
decoded
file enable signal

1logic

control

the

4-3
1lists
the
five
SEQ CNTL
bits
in
binary
sequence
shows how the bits control the various sequencing functions.
32 bit counts (or bit states)
are listed.

and
all

branching

function.

Table

The

first

the

first

four

counts
bit

(bit

branch 0 are
1 and the A

portion

states,

states

find

states

CC)

enabled.

the

asserted.

branch

logic

SEL
is

the

branch
of

portion

operate

branches

During

portion

branch

states)

states,

branch

are
0

branch

the

four

branch
and

bit

enabled.
1is

logic.

the

states,

For

enabled.

During

portion

of
branch

only

the

eight

The

eight

logic

operation

0
has

enabled.
The last four bit
select
condition
code
(SEL

actually

the

D portion

described

Paragraph

4.6.2.3.

branch

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4-21

Tpa3=1asy

Note
that
during
the
28
bit
states
of
branch
logic
operation,
either SEQ CNTL 4, SEQ CNTL 3, or SEQ CNTL 2 1is false, hence the
S1
and
SO
control
bits
from
the
mux
select
1logic
are
1in
the
default state
(S1 = @;
S@ = 1)
and the DFE signal from the stack
enable
1logic
1is
false.
With
the
control
bits
1in
the
default
state, the microsequencer mux selects the address register and the

microsequencer

serves

only

couple

the

microword

address

field
(BUS U <K11:00>) to the MADR <K11:90> common address
the base address for branching operations.
The stack 1is
by

the

negated

state

During

the

disabling
used

<1l:0>

last

the

are

state

DPUP

i1s

during

branching

operations,

four

bit

states,

logic

addressing

the

SEQ

causing

control.

CNTL

the

shown

bits

Figure

the

mux

logic

and

state

the

S1,S0

control

#DFE)

for

the

last

four

enabling

signal

are

4-9,

the

stack

select

<4:2>

true,

microsequencer

Table

1input

and

4-3 .,thows

logic.

hence,

meaningless.

branch

now

DFE

lines as
disabled

the

bit

SEQ

stack
bits

CNTL

enable
and

the

states.

The first of the four bit states
is a jump to subroutine
(JSR)
function.
In this state SEQ CNTL <1l:9> are both € hence S1 and S0
remain in their default state and the address register is still
selected; however, now the stack is enabled and DPUP 1s asserted.
DPUP true causes the output of the PC counter/incrementer (PC + 1)

pushed

onto

the

stack.

The microcode

jumps

a subroutine but saves the next address (PC
main flow after the subroutine is finished.

the

address

return

of
the

The second state is a return from subroutine
(RTS)
function.
In
this
state
the mux
selects the stack for the next address.
The
stack 1s enabled and DPUP is false which pops the stored address
from
the
stack
to
the
mux.
The
microcode,
returning
from
a
subroutine, uses the address stored on the stack to return to the
malin

flow.

The

third

state

"pop

the

stack"

housecleaning

function.

this state the mux selects the PC counter/incrementer
address, hence the microcode simply advances
to the

the

pops

main

the

manner

continues
flow

via

flow.

stack

The
an

necessary
on

from

RTS.

stack

unwanted

when
the

the

enabled

and

DPUP

address.

Clearing

microcode

jumps

subroutine

without

the

false

stack

which

subroutine

returning

for the next
next address

the

this

and
main

The fourth state is the MISC CNTL function. In this state the mux
again selects the PC counter/incrementer for the next address and
the microcode advances to the next address 1in the main flow. The
stack
1s
disabled
by
the
negated
state
of
DFE.
The
MISC
CNTL
function
1is
the
wutilization
of
the
next
address
field
of
the

microword

(BUS

flags

and

control

bits

(SEQ

CNTL

and
MISC
microword
and
*

for

one

microcycle

for

this

state,

sequential

<4:0>)

are

all

CNTL
1is
asserted
next address field

controls)

Bits

<K11:00>)

functions.

into

and

1ls,

BUS

miscellaneous

<K16:12>

control

are

all

(Figure
4-9).
MISC
CNTL
gates
the
(now carrying the miscellaneous flags

the microword
the

hence

the

address

(Paragraph

field

(ASRT

FAIL

4.3).*%*
and

ASRT

DEAD)

are
not
gated
directly
by
MISC
CNTL.
However,
they
are
indirectly
gated
by
MISC
CNTL
because
they
are
subsequently
gated

VLD.

describing

the

states

sequential

control

<4:09>,
four
special microsequencer
states
and
were discussed.
It may have been noticed that
be no
state
that
used
the next address
field
unchanged.

will

seen

the

section

branching,

4.6.2.3),
one
conditions are

of
the
branching
states
is
a
checked.
This allows
the next

pass

unchanged.

the

4.6.2.3

branch

Branch

1logic.

branch

Logic

Four

1logic

Figure

4-10

branch

bits

(BR

modify

the

base

bits

CNTL

(Paragraph

null
wherein
address
field

block

<3:0>)

SEQC

28
branch
states
there appeared to
of the microword

are

no
to

diagram

the

generated

the

address

from

the

2911

microsequencer. Branch bits BR <3:1> each have a mux for selecting
the various conditions affecting that branch. Branch bit BR @ has

four

muxes

The

branch

muxes

CNTL

<4:@>.

The

SEQ

CNTL

are

enabled

select

<4:€>

enabled,

bits

logic.

The

enable

bit
SEQ

one

logic

controlled

all
from

CNTL

1in

sequential

during

Table

these

4-3;

of
When

bit

control

bits

SEQ

bit

states

not

all

the

however,

states.

addressing

the

1is

branch

mux

determined

muxes

not

the

microsequencer.

<4:3>

bits

the

conditions.

function

shown

control

32
bit
states
and also shows
select

branch

associated

corresponding
Control

are

muxes

during

the

its

are

branch

are

applied

decoded
0

muxes.

the

assert
The

branch

€

one

four

control

bits

mux

select

outputs

divide

the

1into groups of eight.
Table 4-3 1llustrates this
the state of the four outputs from the branch 0 mux

for

the

eight-bit

groups.

IBIN 19

BRANCH
3 MUX

> EN

4-2

SET

MSE SYNC

(FIG. 5-2)
| SEQ CNTL <1:0>

PWR FAIL

(FIG. 5-27)

BRANCH
1
2

|
SEQCNTL <2:0>

(FIG. 6-14){

| SEQ CNTL 2

EN BR 0A/1

|
SEQ CNTL <4:3>
BRANCH

0
MUX

ENBR23

(FIG. 5-28) —

B DN

TICK <1>
IB IN 17

EN BR OB

1B IN 26

EN BR OC

IBIN 14

SELECT

IB IN 10

@fiLU C
MTD
IB IN 16

IB IN 25
IB IN 13

1B 1IN 09

(FIG. 5-3) ——

IB IN 22

(BRANCH 3)

> BRANCH
1

MUX

—1

(BRANCH 2)

(BRANCH 1)

SEL

BR
3

BRANCH

OQUTPUT

BR
2
>\ [ FlG.
BR
1

(BRANCH 0)

PRl
o\ 42

BRO

—{>O—— LOAD

»lEN

\;&JJ??

IB IN 26

SEQ CNTL <1:0>

A DN

»CLK

CLR

P UNINIT

TM\

MUX

@——QSEL

T3 DLY T40

SUSPEND DEL

(FIG. 5-25)
(FIG. 5-6)
(FIG. 5-17)

IB IN 31

|
SEQCNTL 2

IBIN 15
IB IN 12

| SEQCNTL 3

_ SEQ CNTL 4

—{
TM\
(ENBROD)

~©

IB IN 24
IB IN 00

rALU N

IB IN 20

ALU Z

RSVD JMPR

[l> O

(FIG. 5-13)
BACKPLANE

(FIG. 5-25)
(FIG. 3-9)
(FIG. 2-27)

DISABLE ARB E> o )

BTO

XMIT ATTENTION /
IB IN 21

IB IN 08

SEL

Logic

BRANCH

0D MUX

(D)—

MUX

NOTE:

THE LOGIC IN THIS FIGURE IS CONTAINED ON
»{ EN

Branch

BRANCH

Figure 4-10

ALUC {

REG WRT

REC ATTN

ALU V

RSVD

(

FIG.
| SEQ CNTL <4:0>

SHEET J OF THE DP ENGINEERING DRAWINGS.

MKV84-0134

EN BR 0A/1 enables the branch 1 mux and the A mux of branch 0.
is

asserted

for

the

eight

bit

states

that

SEQ

CNTL

<4:3>

It
are

false.

EN BR 0OA/1

mux.

state

is ANDed with

2/3.

Making

the

2/3

branch

the

negated

state

SEQ CNTL

2 to assert

the

mux

enables

the

branch

mux

the

branch

3 mux

function

and

SEQ CNTL

limits

branch

the

and

to only

enabled

four

bit

states.

EN BR OB enables the B mux of branch 0 for the
that SEQ CNTL <4:3> are 0 and 1, respectively.

eight

bit

states

EN BR 0C enables the C mux of branch 0 for the
that SEQ CNTL <4:3> are 1 and 0, respectively.

eight

bit

states

The

fourth

by the

output

from

the

branch

mux

<4:3>.

state of SEQ CNTL

1:1

select

logic

1is

asserted

is ANDed with the negated

state of SEQ CNTL 2 to produce SEL CC. SEL CC selects the branch
conditions of the branch 0 "D" mux. Making SEL CC a function of
SEQ CNTL 2 limits the asserted state of SEL CC to only four bit
states.

Table 4-4

lists

SEQ CNTL <4:0>.
branch muxes.

the

When

corresponding bit
The

branch

branching

conditions

for

the

bit

condition

the

branch

states

mux

sampled

from the microsequencer
is

enabled

for

the

for

other

three

enabled

for

is always

first

logic,

The mux

(ground)

output

the

cutput

The

branch

routes
line,

mux

the

also

the

four

bit

states.

states

SEQ

CNTL

four

bit

branch output
the

first

the

selects IB IN 19 when SEQ CNTL <1:0> are in the 1:1 state.
selects

Refer to it during the following discussion of the

The mux

The mux
<1:0>.

then

states,

The mux selects one of four condition inputs as determined by SEQ

CNTL <1:0>. The SET MSE SYNC condition (negated) 1is selected for
both the 0:0 and the 0:1 states of SEQ CNTL <1:0>. The mux output
is placed on

The

mux

CNTL
the

branch

selects

<2:0>.

branch

the

mux

one

output

line

via

enabled

for

the

first

eight

condition

inputs

eight

The mux output

output

the

placed on

branch output

the BR

bit

states.

determined

The
SEQ

output line via

Table 4-4

Branch

Conditions

Bit

SEQ CNTL

State

<4:0>

Function

Branch

00000

Branch

SET

MSE

SYNC

00001

SET MSE

SYNC

00010

PWR
IN

Branch

FAIL
IN

Branch

TICK

Branch

ALU

<1>

MTD

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

‘

01101

01110

RSVD

01111

RSVD

10000

REG

10001

DISABLE

10010

BTO

20
JMPR

WRT

10011

REC

10100

XMIT

ATTN
ATTENTIO!?

10101

10110

10111

11000

ALU

11001

ALU

11010

ALU

11011

ALU

11100

JSR

11101

RTS

11110

POP STACK

11111

MISC

CNTL

ARB

The A, B, and C mux of branch 0 have their outputs connected to a
common output line. Mux A is enabled for the first group of eight
bit states, mux B for the second group,
and mux C for the third
group.
The enabled mux selects one of eight condition inputs as
determined by SEQ CNTL
<2:0>.
Thus,
the
common mux
output
1line
receives

branch

condition

for

the

first

bit

states.

Note
that
one
of
the
branch condition
inputs
of
mux
C
is
O
(ground).
When this condition is selected
(bit state 24),
there
are
no
branch
conditions
and
the
next
address
from
the
2911
microsequencer is applied to the CS unchanged.

The branch condition on the common output line is applied
four low order inputs of the branch 0
"D" mux.
The three
bits

for

most

significant

(Table

the

4-3)

Thus,

couples

the

for

the

mux

first

branch
the

bit

SEQ

<1:0>

false

selects
24

for

only

bit

the

SEL

from

the

four

the

common

line

SEL
28),

order

the

states

low
mux

through

high

being
bit

four

first

from

output

(states

from

with

the

states,

condition

branch

states

select

and
is

the

via

four

<1:0>

CC
CC

the

for

line

SEL
SEL

selected

output

CNTL

are

bit.

hence,

inputs.
BR

mux

to the
select

order
simply
to

1is

the
true

causing

inputs

SEQ

(ALU

functions).
Branch 0 1s
Also it can
states.,

active for all 28 bit
states
be seen that the branch D mux

<4:2>
all
enabled.

1s)

4.7

The

of
branch operations.
is enabled for all 28
disabled
during
states
29
through
32
(SEQ
CNTL
when
the
microsequencer
special
functions
are

MICROCODE

two

START-UP

address

sources

-the microsequencer)
EN

MADR

enables

uninitialized
EN

MADR

are
the

state.

negates

(the

enabled

maintenance

from

maintenance

When

and

microsequencer
which
initialized state.

the

address

microcode

address

initialization

SEQ

asserts.

supplies

the

CCS

start-up

during

process

SEQ

and

logic.

the

complete,

enables

the

during

the

address

Figure 4-11 is a flow diagram of the microcode start-up process.
The following discussion follows the sequence illustrated in the
diagram. Figure 4-12 is a block diagram of the logic involved
1in
the start-up process.
Upon

system

power-up,

UNINIT

and

in the DP and places the port
assertion of UNINIT
(or UNINIT
the

maintenance

the

microsequencer

take

the

over

the

address

preparation

addressing

inhibited

UNINIT

into
DLY)

Also

for

function.

thereby

DLY

asserts

simultaneously

the uninitialized state.
The
causes EN MADR to assert
to

disabling

FORCE

when

the

ZERO

addition,

the

asserted

microsequencer
SEQ

CLK

microsequencer.

will
from

D
$ UNINIT
§

UNINITDLY

Port enters the

uninitialized state,

SEQCLK T3

Microsequencer
is disabled.

4 EN MADR

Maintenance address

§ FORCE ZERO

Microsequencer gene-

rates zero address,
however output is
not enabled.

addresses to control
store.

Initialization

complete

MKV84-0151

Figure

4-11

Microcode Start-Up
(Sheet 1 of 2)

Flow

Diagram

¥ UNINIT
Port enters the
initialized state.

Y
} SEQCLK T3
Microsequencer is

is enabled.

PSA=0

YES

¥ EN MADR
Disable maintenance
address register.,

4 ENSEQ
Enable microsequencer
which outputs zero as
first address in the

| First address in the

initialized state obtained from the main-

initialized state.

tenance address register.

SEQCLK T3

¥ FORCE ZERO
-

Microsequencer generates addresses under

]

¥ UNINIT DLY

[
,

¥ FORCE ZERO

Microsequencer gene-

rates addresses under
control of microse-

control of microsequencer control logic.

quencer control logic.

EN MADR
Disable maintenance
address register,

} EN SEQ

‘Enable microsequencer.

MKV84-0152

Figure

4-11

Microcode

Start-Up

(Sheet 2 of 2)

Flow

Diagram

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When
initialization
is completed,
the
DP negates UNINIT
(UNINIT
DLY is not negated until the next clock cycle)
and the port goes
from
the
uninitialized
to
the
initialized
state.
Once
1in
the
initialized state,
microseqguencer.
The

address

the

source

enables

for

the

SEQ

first

CLK

therby

microcycle

enabling

the

state may not be the microsequencer depending on the
PSA
(programmable
starting
address)
bit
in
the

initialized

state of the
PMCSR
(port

maintenance

control/status

During

PSA

this

negation

UNINIT

directly

1In

case,

the

MADR
which
in
turn
directly
microsequencer then responds to
outputs

pulse

starting

resets

address

the

FORCE

microcode

respond

the

If,

while

the

ZERO

asserts
true

the

flip-flop
in

the

uninitialized

normal

SEQ.
of

CS.

The

allowing

start-up,
negates

The

state

ZERO

SEQ

CLK

negate

and

clock

initialized
the

address

When

MADR

and

the

state,

address.
of

the

CS.

state,

the

same

SEQ

assert.

This

for

the

maintenance

The

address

SEQ

CLK

pulse

negate

and

SEQ

maintenance
CLK

determined

that

address

not

occur

bit

=
bit

address

sequences

asserts)

Figure
Note

4-13B

the

point

and

what

causes

that

provides

the

starting

resets

0.
=

the

routine,.

the

Figure
4-13
1is
a
timing
diagram
sequence.
Figure 4-13A illustrates
PSA

still

the

FORCE

microsequencer.

ZERO

flip-flop

allowing the microsequencer to respond to the next
of the first microword of the diagnostic routine.

PSA
the

With
MADR

until

microcycle

occurs, UNINIT DLY negates causing
assert,
The negation of EN MADR
causes the CS address source to shift

SEQ

pulse

does

first

provided

diagnostic

assertion

from

Thus,

desired

next
to

SEQ

pulse.

microsequencer

diagnostic routine should be run, the PSA bit is set to 1.
PSA = 1, the negation of UNINIT DLY 1s required to cause EN
to

enabled
and

FORCE

the

start-up

illustrates
the

difference

which

the

negate.

MADR

address

microcode
timing

start-up

The

thereby

field

start-up
when the

timing

when

between the two timing
negates
(and
EN
SEOQ

PSA

UNINIT

FORCE ZERO
EN MADR

EN SEQ

SEQCLK T3

—TLTLTL
A.PSA =0

PSA

UNINIT

UNINIT DLY

FORCE ZERO

EN MADR

EN SEQ

SEQCLK T3 M
¥*SET DURING UNINITIALIZED STATE.
B. PSA =1
MKV84-0124

Figure

4-13

Microcode

Start-Up

Timing

CHAPTER
DATA

PATH

MODULE

NOTE

The functional block diagrams in Chapter
It
AND and OR symbols.
logical
5 use
a
that
follow
necessarily
not
does
DP
the
on
exists
gate
g
correspondin
The assertion of inputs A
logic prints.
and
B causing the assertion of output C
may be represented on a block diagram by
gate, yet the engineering
AND
a single
that several circuit
show
may
drawing
ANDing
the
in
involved
are
stages
operation.

diagrams in this
block
functional
The
chapter
are keyed to the DP engineering
circuit schematics (CS prints) by letter
designations
in
parentheses,
The
letters
specify
the
DP
CS sheet that
contains
the
detailed logic associated
with
the
functional
blocks
1in
the
diagram.

The

signal names used

in the

functional

block diagrams are the names used on the
engineering
CS
prints.
Where
other
signal names or notes are used, they are
enclosed in parentheses.
GENERAL

5.1

Both
information data and control data flow within the CI750 Data
Path
Module
(referred
to as DP) (Figure 5-1).
Data flow may be
initiated by the port (port initiated transfer) or by the host CPU

(unsolicited
CMI
transfer).
Port
initiated
transfers
are
controlled
by
the
port
microcode
1located
1in
the CS (control
store).
In
an
unsolicited CMI operation, the port microcode is
suspended
and the data transfer is controlled by the host CPU via
the

CCI

There

module

are

and

the

CIPA bus.

three buses within

1.
2.

IB Bus
MD Bus

the

DP.

These

are:

(internal bus)
(miscellaneous data)
Bus

The
main
bus
is
the
1IB bus (internal bus) over which all data
flows.
All
three buses are 32-bits wide while the PORT DATA bus
(interfaces
with
the
PB)
1is
8-bits
wide
and
the
CIPA
Dbus
(interfaces
with
the
CCI)
1is
16-bits
wide.
Hence,
data
reformatting is required as data flows in and out of the DP.

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Control of data transfers within the DP involves:
1.

Selecting

Transferring

Selecting the destination for

the

data

Transferring

source

for

from the

data

from

the

selected

bus

source

the

IB bus

bus

enters

and

leaves

the

IB bus

selected

destination

the

data

for

the

sources

tlocal

store)

Microword

IB bus

are

the

the:

RAMs

literal

* Via the MD bus
@ Only in an unsolicited

Possible

destinations

field*

CMI

for

VCDT

2901A microprocessor

data

the

CCI)

IB bus

are

the:

RAMs#

XBOR register
PB

LS/VCDT

7.
8.

Microword
MADR#
%

PMCSR#%

OUT

IB
an

Local
store
blocks
and

(output

Address

selection

the

PB)
#

logict#

logic#%

IN bus
unsolicited CMI

write

operation

WALS)
many

architecture.
parameters.

operation

RAMs#

# Via the
% Only in

read

the

(read

VCDT (virtual circuit descriptor table) RAMs
2901A microprocessor
XBIR register (input from CCI)
PB IN register (input from PB)
*
Microword from the CS (control store)*d
MADR (maintenance address register)
from the CS*@
PMCSR (port maintenance control/status register)*@

OCooJouUlds
LN -

Possible

Reformatting

the RAM)

1is
a
256
x 32 RAM containing software status
software
registers
associated
with
the
port
The VCDT is a 256 x 16 RAM used to store CI node

The

or a BUS

VCDT

can

selected

IB destination

BUS

(write the RAM).

source

The

and

selection
address
from the

VCDT

logic.

are

addressed

During

may
be
obtained
microword LITERAL

bus
source,
address.
If

the
the

port

parallel

initiated

from

the

address

operations,

the

LS/VCDT

from the IB bus (via the IB IN bus)
field.
1If the LS or the VCDT is the

or
IB

microword
IB
SRC
LS
or the VCDT is

field
selects
the LS/VCDT
the IB bus destination, the
the LS/VCDT address.
During an
LSA
<K07:00>
1is
the
LS/VCDT

microword
IB
DST
field
selects
unsolicited
CMI
operation,
XBUS
address.

The
DP
purpose

contains
a
2901A
microprocessor which performs general
arithmetic
and
1logical
operations under control of the

microword
or
an IB

ALU
control fields.
The 2901A can be an IB bus source
bus destination.
The function performed by the 2901A is
specified
by
the ALU FCN field from the microword.
The 2901A 1is
not accessed by an unsolicited CMI operation.

The PB IN and PB OUT registers are the data 1interface between the
DP and the PB.
The PB IN register functions to convert the data
bytes on the PORT DATA bus into longwords for the MD bus.
The PB
OUT register functions to convert the longwords on the IB IN bus
into
In

bytes
a

for

the

similar

PORT

manner,

interface between the
to
convert longwords

bus.
into

The XBIR
longwords

When
Data

enabled, the
carried over

DATA bus.
the

DP
on

and
the

XBOR

and XBIR

convert

words

MD bus carries miscellaneous
the MD bus 1is the:

1.
2.

Output from the PB IN register
Microword LITERAL field

3.
4,
5.

Output from the PMCSR register
Output from the MADR register in
Microword from the CS

Control

registers

Logic

controls

are

the

data

the CCI.
The XBOR register functions
IB bus into 16-bit words for the CIPA

the

flow

the

data

the CIPA

the

bus

bus.

DP.

The

data

through

the

logic
enables
the selected source and destination for the IB bus
and
controls the data flow to and from the IB bus.
When the port
is
under microword control, the microword IB DST field and IB SRC
field select the IB bus destination and source respectively.

The

Unsolicited

between

the

unsolicited

CMI

CCI

CMI

and

Request/Control
the

operation,

DP.

When

the

Logic

controls

the

port

Unsolicited

CMI

data

flow

executing

an
Request/Control

Logic
receives commands and control information from the host CPU
via
the CIPA bus.
The Request/Control Logic enables the selected
source and destination for the IB bus and then asserts commands to
the
DP
Control Logic to control the data flow to and from the IB
bus.
Parity

generated

and

checked

5-4

data

flow

throughout

the

DP.

5.2
The

CIPA BUS
(computer

CIPA

module
The

bus

the

has

CPU

interconnect

cabinet

signal

with

lines

port

the

which

adapter)

module

are

divided

bus

connects

the

into

CIPA

the

CCI

cabinet.

groups

shown

below.
Data:-

Control:

5-2

illustrates

DP.

Status:

lines

Reserved:

lines

the

CIPA bus

and

interface

which lines are bidirectional.
Also shown are
the
bus
signals
within
the
CCI
and
the
DP.

Table

5-1

each.

The

functional

5.3
Data

1list

given

the

signals

CCI

signals
are

area

the

its

and
for

what

shows

used)

the

figure

(not

and

identifying
vice-versa.

The

1lines

lines

control:

Power

Figure

signal

which

group

explained
to

direction

they

DP BUSSES AND INTERFACE
transfers
throughout
the
DP

called

and

with

the

gives

the

the
in

CCI

lines

the mnemonics
This
allows

within

detail

the

signal

and

function

the

discussion

pertain.

undergo

reformatting

the

interfaces.
The PB IN and PB OUT registers perform this function
at the DP/PB interface.
The XBIR and XBOR registers perform this
function at the DP/CCI interface.
Refer

Figure

the

OUT

data

the

The

latch

5.3.1
When
the

5-3

throughout

the

following

discussion.

PB OUT Register

latch.

latch
HOLD
<31:00>)
1is

bus

(BUS

output

1input
(LATCH
then applied

selected
IB

<31:00>)

follows

the

1IB)
1is
true.
in 8-bit bytes

the

inputs

latch

bus

into

input

destination,
a

the

destination

for

the

(IB
the

1IN
PB

by
DP
is

The
latch output
to four sections of

OUT register.
The 32-bit longword is clocked into the
CLK PB OUT which is asserted by the LD PB OUT command
Control Logic.
LD PB OUT is asserted when the PB OUT
selected

transparent

long

bus.

____________

CIPA

—

BUS

|
!
]

L _CIPA
¥

ouT
CIPA

|
‘V I

C1PA PARITY

XBOR
:
| t:—l_DRlYE

(

CIPA

|
:

CIPA

<15:¢6>

{

peLo

PRIVE

PARITY

CJPA

< BUE _CIPA DATA <IS:86)

EVEN _PARITY

DATA <15:¢8)>

|
|
|
(

’

PAR
ClPA

PARITY

R
—_—

Bi
PS LpCiLo

bCLO

ERROR

|
|

|
|
|

!
|

|
|

CIPA A GO

CIPA

PORT

CIPA

GRANT

|
i
|

CIPA

||
I

INT

REG SEL <3:¢)
AcCLO

CIPA T

DCLO

CIPA

CLK

CIPA

CIiPA

CIPA

|
!
!
:

!
l
|

]

|
|

ACLO

I
I

MIN

A _DONE

B DONE

:
|

v ||

CIPA CPU ACLO
CIPA MIN

CIPA A DONE

CIPA REQUEST

CIPA

DONE

cipA

READ

l
|

|
|

C{PA

CPU

MIN

INIT

ACLO
-

RLYO

:
\V4

|
CIPA

SET

MSE

Note:

Letter designations in parentheses

refer to engineering drawings
containing corresponding logic.

Figure

5-2

CIPA Bus

with

and

CCI

Interfaces

Table

Group

Mnemonic

Data

CIPA

DATA

5-1

<K15:00>

CIPA PARITY

CIPA

Bus

Signals

Direction

Function

Bidirectional

Transfers

Bidirectional

data

Odd parity for the
data

the

CIPA

DATA

lines

Control

CIPA

REG

SEL

CIPA A GO

<3:0> DP to

CCI

DP to

CCI

Selects a CCI register and specifies a
write or a read of
the register

Initiates

CMI

transfer(s)

CIPA A

DONE

CCI

Indicates CMI
fer(s)

CIPA

B GO

DP to

CCI

trans-

1nitiated

(are)

Initiates

done

CMI

transfer(s)

CIPA

DONE

CCI

CIPA

REQUEST

CCI

Indicates CMI transfer(s)
1nitiated by a
B GO is (are) done

Indicates
that

the DP

unsolicited

CMI function
pending

CIPA

READ

CCI

Specifies

licited

CMI

tion

unsoopera-

write

read

CIPA

GRANT

DP to

CCI

Indicates

the

1is

servicing an unsolicited CMI operation

CIPA PORT

CIPA CLK

INT

DP to

CCI

DP to CCI

Initiates

rupt

sequence

host

CPU

interto

Clocks DP data

the

1into

CCI and increments
read counter for CCI
RCV

end

XMIT

files

Table

5-1

CIPA

Bus

Signals

Group

Mnemonic

Direction

Status

CIPA

Bidirectional

ERROR

(Cont)

Function
Indicates
error

CCI

a
a

parity
DP

CCI

data

transfer
CIPA

SET

MSE

CCI

Indicates

UCE,

either

RLTO

NXM,

error

1in

CC1I
Power

CIPA

CCI

Control

Indicates

cabinet

CIPA

present,

powered-up,

and

initialized
CIPA

CPU

ACLO

CCI

Indicates

down
CIPA

DCLO

Bidirectional

power

CPU

Indicates

going

cabinet

power

non-operational

1in

either the
cabinet or

CPU
the

CIPA

cabilinet
CIPA

MIN

CCI

CIPA

ACLO

CCI

Initializes

Initiates

system

keeping

CIPA

power-down

host

the

while
CI750

powered-up
CIPA

DCLO

CCI

Completes
system

initiated
ACLO

the

host

power-down

by CIPA

P8 OUT

- 15 )—EN_XBIR
N

2 TMUX <1:@>

onaneas
ow a» ase

xRB&.2 l

)

SeLecT

P8 LOAD

m’IENPBBYTfa

(F16. 8-10)

REG —-—'{| )
)

(F1G. 3.0

Bus. IB

Bus IB

2901A

Si90

?.:)

(PIG.

'l)

r"x-B-o-R'- |
'

R&€

Hi ouT
REG

: Bus TB

l<3, 1)

)

| Bus IB
| [Lo our pledtLISS0DD>

[

reé

]

[ kU‘
‘

(rie. 5-6)‘%..”‘93'&)

8US 18 <31:00>

T3 LLY T100

) <. 24>l

DST CLK A

([ ———
EN MD LO

8US MD

BUSMD
<15:08>

CLK
oy comms e

HTD

11D
l

LITERA

K
0

(F18. &2)

c::PA'ERROR |
XMIT

e 5=13)

STATUS 7

L
-

_PBIR PE

\__LSPE
L__..."”E
(Kl

‘

(FLOW THRU)

) 1

Lo m
j cLkps

;

(FIG.

UNINIT

F1Q. $-293)

{F1Q. 3=10)

5-10)
* ©

(Fid. 32
© -

{FIQ. 2:27)

(FI0. $=28)

Frol

lKl

-.
pridponcd

1.9

—()

[ RSVD

QP o |

DCLO {FIG. 5=27)

wp | (FIG. 5-25)-

(H)

BUS MD

|
5

- PORT DAT »

CLK

<31:00>

' PSA

%(H) | '
D

ANIT k16, 5-25)

<07:00>

B N REG
1.

<15:00>

MIF

————(FIG. 823

R
o
BUS MD

f 1-'

CLK"OU‘T-

onDPCLK
T3 A

FI1G.
(s-ns)

18 IN

FiG.\LDPB
5-"1

'<02!:-‘10>l

(Fig. 5-4; 5-10)

DF;

NLE

18 IN <08:04>

BUS 1B <18:0> _A

18 IN

1B IN <02:00>

SET | LAaTCY
FF
18

18 IN <07:00>

412) Sez3ra,|
(F1G. (FIG.
4=10)
*IG - 5=10)4

[ oorres]
PB OUT REG -I

(FIG. 5=1))@g—2 %

5-8)

<31100>
-

Jo i
100>

(FIG, S-4)

PROCESSOR

BUS 18

IPA DP

!
Ls |\ vcor

BUS IB <15300>

RICRU-

(F‘G. 5=/

v ':

L_ - o -J

10U

ENPBBYTE O

BYTE[ENPBBYTE
E

M eues

BUS MD 31
=X

-—F'N |

| ST

READ

PSR
.

(FIG.$-13)

ENMISC

— (F1G. 3-17)

UNGOL

(FIG.
3-23)

PAR

J | Rec sEL g }(Fl&. 5=17)

QLD

sl b

‘fi;

)

j‘ e

CLK

CIZ

seLf—

&Lgn

‘(::K

'T EN_ PBIN

T ()
'

;

ek T3

MLD P8

PB MUX ENA = ¥ TM

—={FIG. 3J)

REFER TO ENGINEERING DRAWINGS

— —

LETTER DESIGNATIONS IN PARENTHESES

(FIG. 5=1¢)

CONTAINING CORRESPONDING LOGIC.

(31100)
EN

AlNT (FI1G, S=13)
Figure

5-3

Buses

and

Interfaces

The

OUT

LOAD

command

flow

from

command

OUT

the

enables

code

asserts

<1:0>

code

and
the

one

unloaded
PMUX

under

the

code

from

<K1:0>

out

byte

the

control
the

PORT

select

DATA

logic

the

four

BYTE

output

the

four

BYTE

<3:0>

the

PB.

control
bus.

while

asserts

thereby
wunloading
the
PB
OUT register
byte
at a time.
After the last byte has
is
again
asserted
by
the
DP
Control
longword into the PB OUT register,

The

the

LOAD
<1:0>

The

data

PMUX

signals.

signals

the

PMUX

sequence

onto the PORT DATA bus a
been unloaded, LD PB OUT
Logic
to load the next

5.3.2
PB IN Register
Input
data
bytes
from the PB (PORT DATA <7:0>) are applied to a
transparent
latch.
The
1latch output follows the latch input so
long as the latch HOLD input (LATCH IB) 1is true.
The latch output

byte

The

applied
IN

four

sections

loaded

under

the

32-bit

the

PB IN

control

PB.

A PB

MUX
ENA
command
and
a
PMUX <K1:0> code from the PB control the
loading
of
data into the PB IN register.
The PB MUX ENA command
enables
the
PB
1IN
byte
select logic while the PMUX <K1:0> code
asserts
one
of
the
four CLK PB IN signals to clock a data byte
into the PB IN register.
The PMUX <K1:0> code asserts the four CLK
PB
IN
signals
1in sequence thereby loading up the PB IN register
from
the PORT DATA bus a byte at a time.
After the last byte has
been
loaded, EN PB IN is asserted by the DP Control Logic to gate
the
32-bit register output onto the MD BUS as BUS MD <31:00>.,
EN
PB
IN
1is
asserted
when
the
PB IN register is selected as the
source
for
the
1IB
bus.
EN PB IN then negates while PB MUX ENA
asserts
The
bits

MD
are

start

bus

gated

new data

bytes

into

gated to the IB bus in two
EN MD LO while the upper

HI.
Logic.

and

5.3.3

XBOR Register

are

the

sections.
The lower 16
16 bits are gated by EN

generated

the

Control

Data
on
the
IB
bus
(BUS
1IB <31:00>) is applied to two 16-bit
sections
of
the
XBOR
register.
The 32-bit longword is clocked
into
the
register
by
CLK
XBOR
PAR
from the CCI/DP Interface
Control
Logic.
CLK
XBOR
PAR asserts when the XBOR register 1is
selected

the

destination

for

the

bus.

The XBOR register is unloaded a word at a time by REG SEL 0.
When
false, REG SEL 0 selects the high word from the XBOR register (BUS
IB <31:16>) and outputs the word as CIPA D OUT <15:00>.
REG SEL O
then asserts to select the low word from the XBOR register (BUS IB
<15:00>)

and

outputs

CIPA

D OUT

<15:00>.,

The

true

state

REG
SEL
3 asserts DRIVE CIPA thereby placing the data words from
the
XBOR
register onto the CIPA bus as CIPA DATA <K15:00> (Figure
5-2).
CLK
XBOR PAR then asserts again to load the next longword
into the XBOR register.

REG

SEL

Control

and

Logic.

REG SEL 3 are obtained from the CCI/DP Interface

XBIR Register
a high
register 1is also divided into two sections;
XBIR
The
(CIPA
CCI
the
from
data words
section and a low section. Inputsecti
ed
clock
are
they
where
ons
DATA <15:00>) are applied to both
face
Inter
P
CCI/D
the
from
in by CLK XBIR HI and CLK XBIR LOW
from the CCI are transmitted
Control Logic. Longwords transferread time
with the high word being
over the CIPA bus a word at
5.3.4

CLK XBIR HI asserts to load the high word on
transmitted first.
ter. CLK XBIR
the CIPA bus into the high section of the XBIR regis
section of
word
low
the
LOW then asserts to load the low word into
IN to
XBIR
EN
s
assert
The DP Control Logic then
the register.

gate

the

longword in the XBIR register onto the IB bus as BUS IB

EN XBIR 1IN then negates while CLK XBIR HI asserts to
<31:00>.
start loading the next longword into the XBIR reglister.
re 5-4)

LS AND VCDT (Figu
5.4
addressed 1in
LS (local store) consists of eight 256 X 4 RAMs
LS space (256 x 32)
parallel to form a 32 bit output. Thengtotal
a 256 X 16 LS HI section
is enabled in two 16-bit segments formi
and a 256 x 16 LS LO section.

four 256 X
The VCDT (virtual circuit descriptor table) consists of One
signal
.
output
16-bit
a
form
4 RAMs addressed in parallel to
enables the total VCDT space.

sing
Figure 5-4 illustrates the LS and VCDT sections and the addres
(LS
ns
sectio
three
All
each.
with
and enabling signals associated
from an
HI,
I.SA

LS LO, VCDT) are addressed in parallel by LSA <07:00>
Thus access 1is to the same
(local store address) mux.

location in each section.

Data placed into the LS and VCDT is from the IB IN bus. IB IN
¢31:16> is input into the LS HI section. IB IN <15:00> is input
into the LS LO section and the VCDT.

HI
Data out of the LS and VCDT is placed onto the IB bus. The LS the
and
n
sectio
LO
LS
The
>.
<31:16
IB
BUS
section outputs onto
VCDT output onto BUS IB <15:00>. When the LS is read out, 32 LS
bits are placed onto the IB bus. When the VCDT is read out, the
upper 16 bits of the IB bus (BUS IB <31:16>) are zeros supplied
from the MD bus (Paragraph 5.8.3.1).

sections LS HI, LS LO, and the VCDT are enabled by EN LS HI, EN LS

section
L0, and EN VCDT respectively. The enabling signal for any of
that
out
read
or
into
n
writte
be
must be true before data can
the
,
section
d
enable
an
into
In addition, to write data
section.
of
out
data
read
To
true.
be
LS/VCDT write strobe (WR RAM) must
be
must
RAM
WR
and
true
be
must
an enabled section, EN LS/VCDT OUT
RAM
the
s
inhibit
strobe
write
RAM
WR
false (assertion of the
output).

—

BUS 1B <31:00>

BUS iB <31:16> I
(FIG.

BUS 1B <15:00>

EN LS/VCDT OUT

5=16)

(F1G.

5=6)

(FIG. 5=16)

LSA <07:00>
‘

VCDT

(256 X 16)

ADR — —

ADR

(C)

EN LS HI

FI1G. \EN LS LO
-16

(D)

(FIG., 5=6)

LS
- LO

(256 X 16)

()

F16.\

(C)

EN N VCDT
VCD

-1

WRRAM
IB IN

<31:16>

(FIG.

5=3)

IB IN <31:00>

)

IB IN <15:00>
NOTE:
LETTER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS

CONTAINING CORRESPONDING LOGIC.

Figure

5-4

LS/VCDT

Block

Diagram

I.S/VCDT Address Selection

5.4.1

a simplified block diagram of the LS/VCDT address
1is
5-5
Figure
selection
function.
The
LS
and
VCDT address (LSA <07:00>) is
LSA mux which functions to select the address
an
from
obtained
Address source decode logic monitors
four possible sources.
from
IB DST and IB SRC fields from the microword to determine if
the
to be an IB bus destination or a possible IB bus
is
the LS/VCDT

Accordingly the address source decode logic decodes the
source.
IB DST field or the IB SRC field to effect mux selection of the
I.§/VCDT address source. When the logic senses that the LS/VCDT has

been

the

selected

write

write strobe

as the IB bus destination,

strobe

The

1logic.

(WR RAM)

it asserts EN RAM WR to

write strobe logic generates the

for the LS/VCDT RAMs.

1is a detailed block diagram of the LS/VCDT address
Figure 5-6
Refer to it during the following discussion.
function.
selection

The

LSA

address

mux has two select inputs (SEL 2, SEL 1) that select the

source.

Table

5-2 lists the address source selected by

the mux for the four states of SEL 2 and SEL 1.
Table 5-2

LSA Mux Selection Code

SEL 2

SEL 1

Address Source

Literal
Index Register
Translate Register
XBUS LSA Register

0
1
1

1
0
1

Both
The SEL 2 and SEL 1 inputs are obtained from two flip-flops.
the
into
goes
port
the
when
SEQ
SUSPEND
by
set
are
flip-flops
and
2
SEL
forcing
thereby
5.11.2.4)
Paragraph
(see
mode
suspend
With SEL 2 and SEL 1 both true, the mux selects XBUS
1 true.
SFLL,
SUSPEND SEQ asserts during an
LSA <07:00> as the LS/VCDT address.
control of the LS/VCDT
microcode
when
request
CMI
unsolicited
address is suspended and the host CPU supplies the LS/VCDT address
via
the unsolicited CMI request/control logic (see Figure 5-1 and
Paragraph 5.8).

When not executing an unsolicited CMI request (SUSPEND SEQ false),
select decode logic controls the two SEL bits by conditioning
the
The decode logic causes
SEL flip-flops to set or reset.
two
the
or the other to be set,
one
or
reset,
to
flip-flops
the
both
the LITERAL, the index
select
to
LSA mux
the
causing
thereby
LSA address source.
the
as
register
translate
the
or
register,
to set and hence
flip-flops
both
cause
not
will
1logic
decode
The
the LSA address
as
input
<07:00>
LSA
XBUS
the
select
never
will
source.,

LITERAL <07:00>

LSA <07:00>

IB IN <08:00>
~

INDEX

LD INDEX

(FIG.

5=6)
¢

REG

J1 LD XLATE J REG

LSA
MUX

IB IN <13:08>

]

TRANSLATE

F-.

XBUS LSA <07:00>
IB DST <3:0>

1B SRC <1:0>

Figure

ADDRESS

vI SOURCE
o{

DECODE
LOGIC

| SELECT

LLS/VCDT Address Selection
5-5
Simplified Block Diagram

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5-6)

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The

decode logic operates from a two-bit source/destination input

(S/D
<1:0>)
obtained
from
the
S/D mux.
The
mux
selects
destination
bits IB DST <1:0> or source bits IB SRC <1:0> for the
S/D <1:0> output.
The mux selection is made by ANDing IB DST bits
3 and 2.
If both bits are true (EN RAM WR asserts), the LS or the
VCDT is selected as the IB bus destination (see Table 5-8) and the
If either (or
DST <1:0> for the S/D <1:0> bits.
IB
selects
mux

false, another destination is being selected for
are
bits
both)
In this case, the mux defaults to IB SRC <1:0> for
Dbus.
IB
the
in the event the LS/VCDT is selected as the
bits
<1:0>
S/D
the
source

for

the

IB bus.,

SEL
LSA mux
the
when
(LITERAL
<07:00>)
from
<07:00>

address

0:0, the literal input
are
<K2:1>
bits
the
microword
1is
selected for the LSA

lines.

When
the
LSA mux SEL bits <2:1> are 0:1, the output of the index
register is selected for the LSA <07:00> address lines.
The index
register
is
1loaded with IB IN <08:00> when LD INDEX asserts from
the
DP
Control
Logic.
IB
IN
<07:00>
provides the eight bit
address
input
to
the
mux.
IB IN 08 provides INDEX 08 which is
used
in
the DP Control Logic to select the LS or the VCDI (INDEX
08
negated
=
LS; INDEX 08 asserted = VCDT).
Also note that the
four
least significant bits from the index register are ORed with
the four least significant bits of the LITERAL input.
This allows
the
1literal bits to perform four-bit wide indexing into the LS or
VCDT

tables.

the
When
translate

1:0, the output of the
are
<K2:1>
bits
SEL
LSA mux
register is selected for the LSA <07:00> address lines.

The translate register is loaded with five bits from the IB IN bus
(IB
IN
<13:09>) when LD XLATE asserts from the DP Control Logic.
These five bits output from the register as address lines <05:01>.
Address lines <07:06> are grounded.
The least significant address
line
(00)
1is
LITERAL
00
which
translate LS or VCDT entries.

allows

5.4.2
LS/VCDT Write Strobe Logic
As
previously
mentioned,
when the LS or

one

bit

the VCDT

indexing

selected

the

the destination for the IB bus, IB
asserting
EN
RAM WR to the write
logic
generates
a
write
strobe

DST <3:2> are both true thereby
strobe logic.
The write strobe
for
the LS/VCDT RAMs (WR RAM)

(Paragraph 5.4)
PAR) (Paragraph

for

and a write
5.7.6).

strobe

the

LS/VCDT parity RAMs

(WR

EN
RAM
WR
1is
applied
to
a
flip-flop.
If
this
1is
not an
unsolicited CMI request (DST INHIBIT false) and the port is not in
the
wuninitialized
state
(UNINIT false), the flip-flop output is
ORed
with XBUS WR LS/VCDT from the unsolicited CMI request logic,

The
OR
gate
output
is applied to delay logic where the LS/VCDT
write
strobe
(WR
RAM)
and the parity write strobe (WR PAR) are
generated.
Delays
are
incorporated into the write strobe logic
making the WR RAM strobe and the WR PAR strobe 40 ns wide.
The WR
the trailing edge of the WR RAM strobe as
on
begins
strobe
PAR
shown

Figure

5-7.

The first flip-flop
logic consists of two flip-flops.
delay
The
The
by the OR gate output and is set by DP CLK T3 A.
enabled
is
is applied to an AND gate which then asserts WR
output
flip-flop
The clock pulse that set the flip-flop is applied to a delay
RAM.
T3 DLY T40
it is delayed 40 ns to become T3 DLY T40.
where
line
and applied to the WR RAM AND gate causing WR RAM to
inverted
is
negate.

The
DLY T40 clocks the second flip-flop.
T3
of
assertion
The
which
gate
AND
PAR
1is applied to the WR
output
flip-flop
second
T3 DLY T40 is delayed 40 ns, inverted, and
WR PAR.
asserts
then
then applied
5.5

to the WR PAR AND gate causing WR PAR to negate.

MD BUS

The
MD
(miscellaneous
data) bus carries data from miscellaneous
sources
to
the
1IB bus.
The sources are enabled onto the MD bus
one
at
a
time thereby isolating the bus from all sources except
the one driving the bus.
The enabling signals are supplied by the
DP
Control Logic and the unsolicited CMI request logic.
The data
sources and their enabling signals are shown in Table 5-3.

Table

5-3

MD Bus

Data

Sources

Data Source

Enabling Signal

PB IN register
MADR register

EN PB IN EN MAINT -

CS microword

EN MAINT -

(MDATR)

PMCSR register
Microword LITERAL field

Selection

between

EN MISC
EN MISC

from DP control logic
from unsolicited CMI

request

logic

from unsolicited CMI

request

logic

from DP control
from DP control

1logic
logic

the MADR register and the CS microword

(MDATR)

is
made
by the maintenance mux in the CS.
Selection between the
PMCSR
register
and
the
microword
LITERAL field is made by the

U‘l

PMCSR/LITERAL mux.

DP CLK T3 A

E147=5

\e-20 nsB|

WRRAM e 40N ———s]
T3 DLY T40

E147=9

]

WR PAR

fe—
40 NS ————n

E148-6

Figure

5-7

Write

RAM Timing

Diagram

EN MD LO

and

sections

the

MD bus

supplied

from

the

The

data

32-bit

bits,

EN MD HI

supplied

1longword

the

supplies

the

Control
to

bit

fill-in

bus

When

from

the
1is

locations must be

zeros

5.5.2

MADR and

low word

EN MD

source

when

and

high word

EN MD HI

are

MD bus
read

zeros.

must

that

not

The MD bus

a
32

logic

necessary.

5.5.1
PB IN Register
EN PB IN gates the 32-bit output of the
bus as discussed in Paragraph 5. 3. 2.

EN
MAINT
onto
the

the

bus.

Logic.

the

format.

unused

the

respectively gate

the

MDATR

gates
the 32-bit output of the maintenance mux (31:00)
MD bus.
The maintenance mux is shown in Figure 4-2 and

discussed

Paragraph

4.4.

The
maintenance
mux output is always
in zeros when the selected data source

32-bits wide. The mux
is less than 32 bits,

fills

The
maintenance
mux
selects
the
maintenance
address register
(MADR)
or
the
maintenance
data
register
(MDATR)Y*.
The
mux
selection
1is accomplished by XBUS LSA 00 from the unsolicited CMI
request

1logic.

unsolicited
low portion

(Accessing

Accessing

the

maintenance
data
physical register.

When
write

the MADR or
data

MADR

CMI operation.)
MADR 12 is
of the 48-bit microword for

the

input

microword
register

MDATR register
to

the

(MDATR).

is
via

MDATR

1is

only done

used to select
the MD bus.

read

(or

write)

MDATR does

the
the

the

not

via

high

exist

IB bus destination,
IB

bus.

the
as

the

5.5.3
PMCSR and Microword LITERAL Field
EN
MISC gates the 16-bit output of the PMCSR/LITERAL mux onto the
lower
half
of the MD bus (BUS MD <15:00>).
Zeros are gated onto
the
upper
half
of
the
MD
bus
(BUS
MD <31:16>) for all read
operations
of
the
PMCSR
or
the microword LITERAL field.
When
executing
an
unsolicited CMI read of the PSR (UNSOL READ and PSR
true), bit 31 becomes MTE?*.
|
* The

PSR

(port

status

32-bit

software

located
in LS. Bits <30:16> of the register are all zeros.
Bit
31
is the MTE (maintenance error) bit.
When the PSR is read by
an
unsolicited
CMI operation, the lower 16 bits output from LS
onto the lower half of the IB bus.
The upper half of the IB bus
is
supplied
from the MD bus by asserting EN MD HI and EN MISC.
EN MISC enables the 15 zeros and the MTE bit onto BUS MD <31:16>
and EN MD HI gates them to the upper half of the IB bus.

When
the port is not in the uninitialized state and not executing
an
unsolicited
CMI read operation (UNINIT and UNSOL READ false),
the
PMCSR/LITERAL
mux
selects LITERAL <7:0> for the lower eight
bits
of the MD BUS (BUS MD <07:00>).
The next eight bits (BUS MD
<15:08>)

are grounded

the mux

supply

zeros.

When
the
port
is
in
the
uninitialized state (UNINIT true) or
executing an unsolicited CMI read operation (UNSOL READ true), the
PMCSR/LITERAL muXx selects the 16-bit PMCSR register.
Register
bit 00 (MIN) is grounded and
0.
If
the
host
CPU
writes
a
1

therefore always reads as a
1into
PMCSR bit 00, the CCI

initializes
and
asserts CIPA MIN on the CIPA bus.
CIPA MIN then
functions to initialize the DP (see Paragraph 5.12.2).

An
unsolicited
CMI
the
unsolicited CMI
PSA, MTD, WP, RSVD).

The

write of the PMCSR will
request logic, to write

PMCSR register bits

are described

assert CLK PMCSR from
five PMCSR bits (MIE,

in Table 5-4.

Table 5-4
Bit

Mnemonic

PMCSR

Description
Parity

Error:

parity error
<l14:98>.
PE
are
14

the

all

the

port

bits.
These are PMCSR bits
1s cleared when PMCSR <14:08>

cleared.

Control

CSPE

Store

parity

PB.

Parity

Error:
CSPE
detected in the

error

can

only

CSPE

microcode
during an
13

Bits

sets when
CS in the

set

when

is running.
unsolicited

It
CMI

will not set
operation.

the

Local Store Parity Error:
LSPE sets when a
parity error is detected while reading the

LS PE

LS or the VCDT.
LSPE can only be
microcode read of LS or the VCDT.
not set during an unsolicited CMI

set
It

by a
will

when

operation.
12

Receive

RBPE

parity
from
11

XMIT

STATUS

Buffer

error

the

Transmit

Parity

is
to

Data

Error:

detected
the

CIPA

ERROR

CIPA

Error:

detected

Parity

Set

Error:

when

Set

data

transfer

DP.

parity error 1is detected
transmit channel.
10

CCI

Set

when

the

link

parity

error

CCI

DP data

transfer.
@9

PBIR

(OPE)

XBUF

Set

detected

IN
28

Error):

UNINIT

data

the

Transmit Buffer
parity error is
unloading

Parity

when

(Output

error

transfer

When

uninitialized state.
running and the port
data packet traffic.

through

Set
the

writing

timeout.

into

the

when a
PB 1is

buffer.

set

the

port

1is

the

The microcode is not
will not respond to
UNINIT is set by DCLO

(during power-up), MIN, or MTE.
microcode is started when UNINIT

Parity

bus.

Parity Error:
detected while

transmit

Uninitialized:

Error

parity

the

PICR or

The

cleared

boot

Table
Bit

Mnemonic

PSA

5-4

PMCSR Bits

(Cont)

Description

Programmable

Starting

Address:

When

the

PSA

bit is set, the port microcode will start
‘running at the address in the MADR register.,
When the PSA bit is reset the microcode

starts

location

0@9@.

RSVD

Not

used.

Wrong Parity:
When set the DP parity
generator/checker will generate and check
even

MIF

MIE

parity

instead

generate

parity

purposes.

odd.

errors

for

cleared

Used

maintenance

Initialization.

Maintenance Interrupt
bit indicates that an

Flag:
When set, this
interrupt causing

condition

MTE)

(DCLO,

Maintenance

INTR,

Interrupt

has

Enable:

occurred.

When

set

interrupts are enabled.
This bit is set by
DCLO during power—-up or by writing MIE with
a l.
It is cleared during DP initialization
or

MTD

writing

Malintenance
boot

MIE

Timer

timer

interrupt.

with

Disable:

disabled

When

and

reset,

When

set,

cannot

the

cause

the

timer

1is

When

set,

enabled.

Maintenance

Initialize:

initialize
all

port

signal

(see

and

generated
leaves

Paragraph

the

that

5.12.2).

port

clears

in the
uninitialized state.
MIN 1s write only and
always reads as @.
The MIN bit does not
exist in the DP.
MIN 1s written in the CCI

module

errors

MIN

5.6

The
the
by
the

ALU

DP contains eight 2901A microprocessor chips which constitutes
DP ALU, shown in Figure 5-8.
The ALU functions are controlled
the
microword
from the CS.
The following paragraphs discuss
ALU 2901A microprocessor and its operations.
2901A Microprocessor

5.6.1

are used in parallel to formulate a 32-bit longword
2901As
Eight
The 2901A contains a 16 x 32 RAM, an
the IB bus.
to
input/output
ALU
(arithmetic logic unit), a Q register, and control circuitry.
The

16-word RAM has two output ports

(A and B)

and a single input

port.
The ALU A/B <3:0> address field is used to address the RAM.
The
A
address
selects
RAM
data to be output at port A.
The B
address
selects
RAM
data to be output at port B.
The B address
also
selects the write location for data input at the input port.
The
A
and
B
address lines are tied together, hence for a given
address, both port A and port B output the same data.

Data
1is
input to the RAM through a RAM shifter.
The shifter has
three
input
ports;
F, 2F, and F/2.
Port F applies the input to
the
RAM
unchanged.
Port
2F applies twice the input to the RAM
while
port
F/2 applies 1/2 the input to the RAM.
The input port
is

selected

The

RAM

1is

the

used

ALU

DST

<2:0>

code.

scratch pad

where

the

results

arithmetic

and logical operations are stored temporarily for future use.
The
contents
of
the RAM are muxed into the ALU by the source control
signals supplied from the CS microword.

The

high

speed

ALU can perform three binary arithmetic

and

five

logic
operations
on
the
two input words, R and S.
The R input
field
1is
driven from a two-input mux, while the S input field is
driven
from
a
three-input
mux.
Both
muxes
have
an inhibit
capability;
that
1is, no data is passed.
This is equivalent to a
Zzero

source

operand.

The ALU R-input mux has port A of the RAM and the IB bus connected
as
inputs
A
and
D
respectively.
The ALU S-input mux has both
output
ports
of the RAM and the Q register as inputs A, B, and O
respectively.

The muxes can select various combinations of input pairs among the
A,
B,
D,
0, and zero inputs as source operands to the ALU.
ALU
SRC <2:0> from the port microword is used to select the ALU source
operands.

The

ALU

source

code

defined

in Table

5-5,

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Table

ALU Source Code

5-5

source

SRC

ALU

Mnemonic

AQ
AB
Z0
ZB
ZA

O
0O
0
0
1

0
0
1
1
0

O
1
O
1
O

A
A
0
0
0

0,
B
@)
B
A

DA
DO

1
1

0
1

1
0

D
D

A
@)

input to the mux is the direct data input from the IB bus.
D
The
This
port
1is
wused to insert all data into the working registers
inside

the

2901A data

path.

The
O input to the mux is from the Q register.
The Q register is
a separate file used as an accumulator or holding register.
It is

loaded
from the ALU through a Q shifter (input F) or from its own
output
via
feedback
1loops
(inputs
20
and
0/2).
Input 2Q is
enabled
for
multiplication
while
1input
Q/2
1is
enabled
for
division.
Data
in
the
O
shifter
1is shifted right or left to
perform
arithmetic
operations.
Operation
of
the Q shifter 1is
controlled by the ALU

The

ALU

microword.

functions

The ALU

DST

are

field.

selected

function code

Table

Mnemonic

The

<2:0>

5-6

ALU

FCN

is defined

<K2:0>

in Table

from

5-6.

the

ALU Function Code

ALU FCN

Function

ADD
SUBR
SUBS

0
0O
0O

0
0
1

O
1
O

R plus S
S minus R
R minus S

OR
AND

0O
1

1
O

R OR S
R AND S

NOTRS
EXOR

1
1

0
1

1
0

Not R AND S
R EXOR S

EXNOR

output select mux selects the RAM port A (mux input A) or the

ALU (mux input F) for the output bus.
The selection
by the ALU DST <2:0> code from the microword.

is controlled

The
{or

ALU DST code also selects the ALU destination by enabling cne
none)
of
the
three
inputs
+to
the
RAM
shifter
and
the

shifter.

The

ALU

DST

code

Table

ALU

3-7

DST

ALU

defined

ALU

Table

Destination

Code

Destination
Q

5-7.

Output

RAM

- -

———

g
g

1
1

@
1

F
F

——
-

A
F

F/2

Q/2

1
1

9
1

1
0

F/2
2F

———
20

-—-

Bus

Note that although the ALU DST code selects mux inputs
the output bus, data on the output bus is not gated to

A or F
the IB

until

for

the

Control

bus

asserting

The

bus

the

always

ALU

1is

selected

The

has

ALU

(ALU
used
the

ALU

SRC

four

ALU

and

1is

the

ALU

source

input

the

input

the

bus

destination

the

however

input

1is

carry out
(ALU C),
sign bit
and overflow (ALU V).
ALU C
is the most
significant digit

F3
1is
of

outputs:

F=@
(ALU
2Z),
flag.
ALU
N

wused

unless

mux

field.

status

N),
=zero
bit
as the carry

selects

ALU.

inputs

not

the

Logic

for
bus

determine

positive

negative

results

without enabling the tri-state outputs.
ALU Z is used for a zero
detect.
ALU Z 1s asserted when all the F outputs are low.
ALU V
i1s
used
to
flag
arithmetic
operations
that
exceed
the
available

2's
to

complement
the

5.6.2
After
can

data
be

RAM

range.

logic

the

The

the

RAM

shifter.

shifted

data

can

During

four

status

outputs

are

applied

CS.

Data Manipulation
is loaded into the

rotated

Likewise,
the

number

branching

microprocessor,

the

1left

the

shifter.

shifted

left

right

out

one

end

right

rotated

rotate,

the

bit

transferred

data

transferred

bit shifted
at
the
far
most

in on the other end.
During a shift operation, the
out is lost and a new bit is generated and shifted in
end.
To
accomplish
these
shifts
and
rotations,
the

significant

least

bit

significant

bidirectional
Lo

rotate

the

LSB

(LSB)

transfer

data,

via

(MSB)

bit

the

MSB

line.
of

the

bidirectional

each

4-bit

2991A

the

complete

entire

the

32-bit

transfer

connected

adjacent

line.

29p9lA

wraparound

longword

via

the

required
connected

5.6.3
Carry Look-Ahead Logic
Circuitry
associated
with
the
look—-ahead
1logic
that
speeds
instructions and allows the DP to

2901As
contains
the
execution
of

look-ahead

illustrates

generation.

function

Figure 5-9

with

full
carry
arithmetic
32-bit carry

full

this

logic.

Each

of
the
2901A chips
generates
both
a
carry generate
output
(GEN or G)
and a carry propagate output
(PROP or P).
The four
pairs of GEN and PROP signals for bits <15:00> are combined 1in a
carry skipper along with a C IN signal derived from ALU function
codes ALU FCN <1:0>.
The sum of the outputs of the carry skipper
are

combined

skipper

and

to
is

output

combined

<31:16>
2901As.
combined to output

5.7
The

The
ALU

ALU

Cl6.

with

the

outputs
C (carry

ALU
GEN

Cl6

and

goes

PROP

links

perform various

the

available

the

bus

parity

not
using
the
parity
Paragraph 5.7.2).

parity

the

another
from

carry

the

bit

of
the
second
carry
skipper
are
flag)
to the CS branching logic.

DP PARITY GENERATION AND CHECKING
DP parity generation and checking logic

IN bus

signals

functions.

thereby

making

bus

logic.

RBPE

generation

(Figure 5-10)
receives data

and

the

only

checking

from

flow-thru
IB

bus

DP parity
1logic

the

latch
data

signal

(see

RBPE;

The only parity check made during an unsolicited CMI operation 1is
on
the
data
transferred
over
the CIPA bus
(CIPA
ERROR check).
Even this check is not made when the offset address is transferred
over

the

bus

5.7.1

(see

Paragraph

5.8.1).

Parity Generation

Data on
applied

the IB
to four

IN bus
parity

and

Checking

parity

bit

(BYTE

<3:0>

PAR)

byte.

BYTE

©®

PAR

odd

parity

for

<K15:08>,

odd

parity

Logic

(IB IN <31:00>)
1s divided
generators.
Each generator

generated
for

on
IN

the

into bytes
outputs an

associated

<@7:00>,

BYTE

and
odd

input
PAR

1is

etc.

The parity bits for the two lower bytes (BYTE <1:0> PAR) are XORed
to generate a parity bit (LO WD PARITY) for the low word on the IB
IN bus (IB IN <15:00>). In a similar manner,
the parity bits for
the
two
upper
parity bit (HI

IN
The

bytes
(BYTE
<K3:2>
WD PARITY)
for the

PAR)
high

are
word

XORed
to
on the IB

generate
a
IN bus
(IB

<31:16>).
byte

data,

parity

are

used

functions

bits
to

and

perform

discussed

word

parity

various

bits

generated

parity

generation

and

paragraphs

5.7.3

through

the

checking

5.7.6.

A wrong parity (WP)
bit from the PMCSR is 1input to the low byte
parity generator.
The WP bit
is
used
to
insert a parity error
into the parity logic for maintenance testing purposes.
When WP
is

asserted,

even

the

parity

through

parity

word

the

low

bit
LO

checks.

byte

parity

1instead
PARITY

of
bit

generator

odd.
and

produces

The

therefore

BYTE

even

parity

effective

PAR

carries
1in

all

ALUFCNO _

ALU FCN 1 ] (A)

ALU CO

r G <03:00>

P <03:00>

G <07:04>

P <07:04>

FROM
:
2901A |4 G <11:08>

(A)

P <11:.08>

ALUC4

ALUCB

2901A

|CARRY | AiucI12

SKIPPER
(A)

(A)

—4C IN

(TO 2801A (B))

ALU C16

G <15:12>

G
ALU <15:00>

CARRY

P <15:12>

ALU <15:00>
P

‘SBK)IPPER

;®

| SR

ALUC16

® G<me>
)
P <19:16>

G <23:20>

]

C IN

ALU C24

|
CARRY

o b [ 2001A

ALU C28

ALUC

PRR——

)

‘

*~ (TOCS)

(B)

FRoM | BS23:20>1 skiPPER

(2901A>4 G <27:24> | (B)
(B)

P <27:24>

G <31:28>

(ALU <31:00> G)

P <31:28>

(ALU <31:00> P)

NOTE:

LETTER DESIGNATIONS IN PARENTHESES

REFER TO ENGINEERING DRAWINGS

CONTAINING CORRESPONDING LOGIC.

Figure

5-9

Carry

Look-Ahead

Logic

For byte parity

checks,

OUT

asserted

(to

load

the

PB OUT

register) and gates WP to the other three byte parity generators.
This results in even parity being generated on each data byte
transferred from the PB OUT register to the PB over the PORT DATA

bus.

Receive Buffer Parity Error (RBPE)

5¢7.2

RBPE indicates a parity error on data transferred from the PB into
the

1is

DP,.

the only parity check that does not involve the

parity generation and checking

logic.

over the PORT DATA bus,
received
are
PB
the
from
bytes
Data
The
PB IN register.
the
to
applied
and
a latch,
through
coupled

are also applied to an even parity generator where an
bytes
data
RB PAR parity bit is generated for each byte.

even parity bit (RBUF PAR) is received from the PB along with
An
with the
compared
are
PAR bits
RBUF
The
Dbyte,.
1input
each

generated RB PAR bits
a

parity

error

has

in an XOR gate.

a match

is not obtained,

occurred.

If the data byte was valid data (not undefined residue left in the
PB),
EN
RBPE
from
the
CCS will be true.
With EN RBPE true, an
error

RBPE

output

from

is applied

5.7.3

the

XOR gate

will

assert

RBPE.

to a PE OR gate and

to the

PMCSR register,

PB IN Register Parity Error
Error (OPE)]
PE
1indicates a parity error
register to the IB bus.

PBIR
PB IN

Data
bytes
applied
to
PB MUX ENA.
proper

(PBIR PE)
data

[Output Parity

transferred

through

the

from the PORT DATA bus are coupled through a latch and
the 32-bit PB IN register.
The register is enabled by
The PMUX <1:0> code places the input bytes into their

position

within

the

The
RB
PAR parity bits (generated on the data bytes input to the
PB IN register) are applied to a four-bit parity latch.
The latch
is
enabled
by
PB MUX EN each time a data byte is input from the
PB.,
the
bits
bits

The PMUX <1:0> code latches one of the parity bits in each of
four
output positions.
The four bits latched are the parity
for the four bytes loaded into the PB IN register. The parity
are applied from the parity latch to the A inputs of a parity

comparator.,

PARITY
GEN

l
|

EVEN
PARITY

l
I

|
|

|
|
CCI

RcV

DATA <I5:04>

(Fic 4-5){

(FIG. 6-34)
(Fi6. 5-2 )S1PA

LTCHD CIPA

CIPA

D <I§;

cea T

E29-3

fvEN

errROR
| WRT
FF C

BUF CIPA

LATCH

[

|+PARLTY

(1)

Ere)

PAR 'yGEN <—J CIPA

(13)
(m)
LR Ml
6~
4

M—FF J jeSINC (K] FF
n

(m)c

-l

CLR ENA CE_

(FiG. 6-34)

_______________ CEINES GEENDER Bz auanlh ST

__——————-———

—J

NOTE:
.

LETTER

DESIGNATIONS

INPARENTHESES REFER

TO ENGINEERING
DRAWINGS CONTAINING

CORRESPONDING LOGIC.

Figure

5-10

Parity
(Sheet

Generation
1

and

Checking

j— e — - ——— —
l

C'PA |

CIPA

D___EABAIJ

D
ctx
F”F.
ABIR M Lle (1)

cLk

‘

DAToA
D_.QLE!L{_

BYTE

XV @

IB IN _<31:00>

{31: 06> [LATCH
©

|
r"xBOR
| RE6 gy 1B

S hcutie

=TT

xgoR

| m?gfr c |

REG SKL

PAR

FIG., §~17)

WORD
WR PAR

AR H
Er)ARITY J—.

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<C/D)

¢@

AWHr OIS CEED CTTEG GEED CGENE IR T

()

LO WD

|PARITY @

2l o)

RRO

SEL

‘|l

O—<ms

(FIG. 42)

CSPE

(TG,
(R) re 5-3
5-23

(F1G. 227 ZMTSTAMS

ENPBBYTE 4

4- 3

5. ¢

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(R) En|aPBMUYX ENA
PAR

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(H)

FIG.)

-2

trux <iiod (712)
|

(F16. 2-3)

—_—

RBYE, PAR

(FlG. 3"’3)

(FIG. 4-2)
.

|
|

5-10

PORT

DATA

LATCH
:

<
PAR PE:DB:Y
GEN

EN_RBPE

Figure

—
o

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-X:

:p¢

AL
PARITY

O
IFIG. 32):

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BUS MD

{Is:98>

(FIG. 5 %)

_®

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Bus IB

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—

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I8 IN <16:08>

XBIR LO

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--!lt—"lW PARITY

1B IN <23:18>

LOGIC

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FIG. sw8) £+16) — =20
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l

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LY. S N

PARITY GENERATION AND CHECKING

IPE

BUS |

Parity Generation
(Sheet

and Checking

the

bus.

From

asserts

the

and

passed

and
and

then

parity

the

true).

5.7.4
CIPA

bus.

the

made

CIPA

ERROR

CBPE

Parity

(BYTE

and

are

the

(through

generated

PAR)

the

applied

bus

error

the

mismatch

asserted

parity

gate

between

causing

PBIR

and

PMCSR

the

error

can

on
in

DP
to

the

for

OR gate

error)

also

either

set

error

when

Thus

Parity

bus,

makes

difference.

data

from

its

Data

the

parity

and

The

high

low

parity

gated

the
word

bit.

out

CIPA

source
1IB

low
This

word

the

inputs

and

the

byte

the

assert

(EN

over

the

direction;

from

the

and

bit

the

parity

both

the

PMCSR

the

CCI

error

modules

The
will

bus

detected

warned

are

REG

applied

parity

bit.

SEL
It

have

1is

word

REG

source

data

flow

the

already

data
been

and

bits

the

parity

bus)

(HI

PARITY,

discussed

Paragraph

word

parity

CLK

SEL

then

discussed

XBOR

become

the

bus

checked

the

bus.

latch

parity

on data transferred from
register, over the CIPA bus, and

the

low

only

performed

latch.

(via

and

XBOR

Parity

process

bus.

parity

where

The

Check

the

flip-flops
by

logic

data.

transferred

directions

check

through
CCI input

1logic

generated.

flow-thru

direction.

both

parity

IB
through

checking

data

the CCI to the DP.
This
unsolicited CMI function.

parity

CCI

the

data

either

from

transfer.

checking

transfer

data

5.7.4.1

the

bus

the

below.

The

bus,

checking

purposes,

bus

generation

<3:0>

for

checking

are

detects

applied

(CNFGR)

transfer

bits

source

the

transferred

the

parity

output

data

during

bus

parity

the

ERROR

CCI

(CIPA

the

1indicates
The

check

A# B

CIPA
ERROR

bus

parity

applied

CIPA

data

as
from

comparator,

the

PBIR

data

For

comparator

the

generated

inputs,
IN

selected
the

HI.

word

bits

the

parity

gates

MD bus,

from

latch)
byte

and

bits

PAR.
XBOR

asserts

are

clocked

flip—-flop

and

false

gate

out

then

word

PARITY)

are

into

high

and

outputs

are

CIPA

gate

the

and

high

5.7.1.

The
PAR

initially

generation

where

low

out

PARITY

the

word

high

parity

The IB bus data
by

CLK

(BUS IB <31:00>)

XBOR PAR,

and

0.
The
1initially
onto
the CIPA bus.
out

the

CIPA

is clocked

then gated

out onto

into the XBOR register
the CIPA bus

by REG SEL

false
state of REG SEL (0 gates the high word
When REG SEL 0 asserts, the low word is gated

bus.

Thus,
the
data high word and its associated high word parity bit
input together into the CCI, followed by the data low word and its
associated low word parity bit.
The data words are passed through

an
input
latch
and
applied
to
a parity generator where it is
combined
with
1its
associated
parity bit from the CIPA bus.
An
error
free
data
transfer results in odd parity being generated.
If
a
data
error
occurred,
the
generator produces even parity
resulting
in
the
assertion
of E59-5 to a CIPA ERROR flip-flop.
The
CIPA
ERROR
flip-flop
1is
<clocked
by
WRT PARITY ENA which
for every DP to CCI data transfer. Thus the true state of
asserts
CIPA ERROR returns to
the assertion of CIPA ERROR.
causes
E59-5

the CIPA ERROR line of the CIPA bus where it sets a

over

the

CIPA ERROR flip-flop

in the

DP.

ERROR on the CIPA bus is also looped back into the CCI where
CIPA
SYNC CE sets a CBPE flip—-flop which asserts
SYNC CE.
asserts
it
the CBPE bit

the CNFGR register,

5.7.4.2
CCI to DP Parity Check (IPE)
The
CCI
to
DP
parity
check
is
performed on data transferred
through
the
CCI
output
drivers, over the CIPA bus, through the
register to the IB bus, and then through the flow-thru latch
XBIR
to

the

IN bus.

Data on the CCI RCV DATA bus in the CCI

is in word format

(CCI RCV

DATA
<15:00>).
The
data
1is transferred through the CCI output
drivers, over the CIPA bus (CIPA DATA <15:00>), and applied to the
XBIR register as CIPA D IN <15:00>).

The
data
on
the
CCI
RCV
DATA bus is also epplied to a parity
generator
where
odd
parity
1is generated.
The generated parity
bits
(EVEN
PARITY*)
are transferred to the DP over the CIPA bus
(CIPA PARITY) and applied to high and low parity flip-flops in the
DP.

* 0dd
the

parity

is used.

generator

chip.

The mnemonic relates to the output pin of

In a data transfer, the first word applied to the XBIR register is
a high word. Its associated parity bit is applied to the high word

parity
£flip-flop.
CLK XBIR HI loads the high word into the high
portion
of
the
XBIR
register.
CLK XBIR HI also loads the high
word parity bit into the high word parity flip-flop asserting XBIR
HI

PARITY.

The

data

associated
into
the
clocks

transfer

parity bit.
1low
portion

the

low

word

asserting

XBIR

The

longword

data

XBIR

over

CLK
of

the

CIPA

bus

the

XBIR LOW asserts to
the XBIR register.

parity

bit

into

the

low

word

clock the
CLK XBIR

word

parity

and

its

low word
LOW also
flip-flop

PARITY.
in

1IN.

the

From

XBIR

the

1IB

bus,

gated

the

out

longword

to
is

the

bus

transferred

through
the
flow-thru
latch
to
the
IB IN bus and then to the
parity
generation
and
checking logic.
In the parity generation
and
checking
1logic,
high
word
and
1low
word
parity bits are
generated
(HI
WD PARITY, LO WD PARITY) and compared (XORed) with
the corresponding parity bits from the XBIR parity flip-flops.
1If
the
corresponding bits do not match, an error has occurred during
the
data
transfer.
In this case, IPE (input parity error) will
assert
when the CCI/DP Interface Control Logic checks XBIR parity
(by asserting CHK XBIR PAR).

IPE

coupled

back

the

CIPA

bus

where

asserts

CIPA

ERROR.

CIPA
ERROR
1loops back into the DP where it asserts CIPA ERROR to
the PE OR gate and the PMCSR register.
IPE is also applied to the
PE OR gate, however it is not applied to the PMCSR register.

CIPA
CCI

ERROR
(on the CIPA bus) also sets the CBPE error bit in
configuration register as discussed in Paragraph 5.7.4.1.

5.7.5
PB

Packet

PAR

are

Buffer

parity

OUT register
with the its

bits

Parity

(PB

generated

PAR)
on

to the PORT DATA bus.
associated data byte.

Data

longwords

and

checking

logic

<1:0>

the

where

bus

byte

the

data

are

PAR

input

parity

bits

bytes

output

sent

the

are

from

the

parity

the

along

generation

generated

(four for
each longword).
The four parity bits (BYTE <3:0> PAR) are applied
to
a PB parity mux.
The mux select code (PMUX <1:0>) selects the
output parity bit which is placed on the PB PAR line to the PB.

PMUX
to

Hence

the

1is

output

code

from

the
parity
PORT DATA bus.

that

the
bit

selects

OUT

the

which

byte

onto

the

PAR

line

for

the

longword

PORT

the

DATA

data

bus.

byte

5.7.6

Local

LSPE
from

Store

1indicates
the

A data

bus,

longword

Parity

parity
or

read

being

Error

error

out

written

(LSPE)

data

into

written
or

the

into

VCDT

the

onto

VCDIr*

the

VCDT

the

bus.

from

the

bus,
1is
also input into the parity generation and checking logic
where
high word and low word parity bits are generated.
The high
word
and
1low
word
parity bits (HI WD PARITY, LO WD PARITY) are
respectively
written
1into
a high word parity RAM and a low word
parity
RAM.
The
two RAMs are addressed by LSA <07:00> from the
LS/VCDT address selection logic thereby writing the parity bits at
the
same
address
as the data being written into LS or the VCDT.
EN
VCDT
1s
applied
to
the parity RAMs as the most significant
address
Dbit.
If
the
VCDT
1s
being
written, EN VCDT is true
thereby writing the VCDT parity bits in a location within the RAMs
separate
from
the LS parity bits.
The RAM write strobe (WR PAR)
is
obtained
from
the
write strobe logic in the LS/VCDT address
selection logic (Figure 5-6).

* The

VCDT

word

half

the
IB
bus
1is
on
the
function
checked

only
of

the

bits

wide.
bus

and

receives

outputs

inputs
the

low

from

the

low

word

half

bus.
When writing the VCDT, the high word on the IB IN
all zeros.
When reading out the VCDT, zeros are placed
high
word
of
the
1IB bus.
Thus the high word parity
operates
normally
with
parity
being
generated and
on

all

zero

16-bit

word.

When
the
LS
or the VCDT is read, the data is output onto the IB
bus.
The flow-thru latch couples the data from the IB bus to the
IB
1IN bus where it inputs into the parity generation and checking
logic.
The logic generates high word and low word parity bits on
the input data.

The

LS/VCDT

operation,
parity
RAM

LS/VCDT

address

addresses
thereby

data

(now being

false
thereby
LS/VCDT LO PAR.
The

high

(LSA

read)

enabling

word

<7:0>)

the
high
accessing

and

1low

was

associated

word parity
the
parity

written.

Write

parity

RAM

outputs

word

parity

bits

with

the

RAM and the
bits stored

strobe

LS/VCDT

(HI

read

low word
when the

WR PAR
HI

PAR

PARITY,

is
and

LO WD

PARITY)
generated
from
the read data, are compared respectively
with
LS/VCDT
HI PAR and LS/VCDT LO PAR from the parity RAMs.
If
the
compared
bits do not match, a data error occurred during the
writing
or
reading
of the LS/VCDT RAMs.
1In this case LSPE will
assert

when

asserting
LSPE

the

LS/VCDT

applied

Control

Logic

checks

the

LS/VCDT

parity

PAR).

the

OR gate

and

the

PMCSR register.

(by

5.7.7

Parity

comprise

(RBPE,
from

OR
the

PBIR

function

PE,

1link

CSPE

from

the

XMIT

STATUS

seven

eight

parity

CIPA

port

error

ERROR,

IPE,

module.
XBUF PE
control store RAMs

7
(TDATA
channel.

transmit
and

(PE)

five

the

Error

the

PARITY

eight

parity

bits

bits.
in

The

this

bits

section

LSPE), two from the PB, and one
from the PB transmit channel and
are received from the PB module.

ERROR)

parity

error

discussed

1is

error

received

signals

that

from

the

assert

link

are

applied to the PMCSR register (see Figure 5-3 and Table 5-4).
The
eighth parity error signal (IPE) is not part of the PMCSR register
as
an
IPE
parity
error
sets
the
CIPA
ERROR
bit (Paragraph
5.7.4.2).

PE
an

is also applied to the
interrupt to the CPU.

error/interrupt

logic

where

initiates

5.8
UNSOLICITED CMI REQUESTS
An unsolicited CMI request is a read or a write of a port register
that
was initiated by the host CPU and not by the port microcode.
The
register
may
be
1located
in
the
CCI
or
the
DP.
The
configuration
register
(CNFGR) is the only CCI register accessed
by
an
unsolicited
request.
All
other
registers
accessed by
unsolicited requests are located in the DP.

The
DP
1is in the suspend mode of operation while the unsolicited
request
1s
being
executed
(see
Paragraph
5.11.2.4).
In the
suspend mode of operation, the microsequencer clock is stopped and
the microcode branch flags and status information are saved.
Thus
the
port
can
resume
microcode
operation after the unsolicited
operation is completed.
A

brief

overview

5-11.

host

The

then

host

unsolicited

CPU

1loads

issues

the

address

offset register
requested,
the
write

address
in

the

data

of
CCI.

When

the

receives

operation.

then

the

offset

DP,

write

the
If

reads
CCI

and

the

shown

via

the

write

operation

the

Receive

request,

target

loads

The

into

the

being

Write

Data

address
into

Figure

CCI.

target

into

wunsolicited

The

address

the

operations

loaded

microcode

CMI

request

the

suspends

from

the

XBUS

LSA

function
was
requested,
the DP reads the XBUS LSA
register,
decodes
the
output to select the target register, and
enables
the selected register for a write operation.
The DP then
reads
the
write data from the Receive Write Data Register in the
CCI
and loads the data into the selected register. Control of the
port
1s
then
returned
to
the
port
microcode
which
resumes
operation at the address frozen during the suspend mode.

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DP reads the XBUS LSA
the
requested,
function was
read
a
If
output to select the target register, and
the
decodes
register,

The DP
data from the selected register to the IB bus.
the
gates
then
transfers the read data from the IB bus to the CCI and loads
The host CPU takes
into the Return Read Data Register.
data
the
the
read
data
from
the
Return Read Data Register via the CMI.
port microcode which
of the port is then returned to the
Control
resumes operation at the address frozen during the suspend mode.

(Figure 5-12)
Starting An Unsolicited Sequence
5.8.1
the host CPU via the
by
requested
is
operation
CMI
unsolicited
An
CIPA REQUEST SYNC and CIPA READ SYNC are
CCI.
the
and
bus
CMI
CIPA
asserted to the CCI/DP Interface Control Logic from the CCI.
CIPA READ SYNC
initiates the unsolicited sequence.
SYNC
REQUEST
to read the CCI offset
necessary
operation
read
the
specifies
register to determine which register is to be accessed.

The

CCI/DP

1Interface

Control

Logic asserts GRANT UNSOL causing

CIPA GRANT indicates to the CCI
CIPA GRANT to assert to the CCI.
that the unsolicited request is being serviced.

Logic also asserts SUSPEND SEQ to
Control
Interface
CCI/DP
The
stop the port microcode from running and place the port into the
suspend mode of operation. SUSPEND SEQ also forces the LSA mux to

select XBUS LSA <07:00> for the LS/VCDT address (Paragraph 5.4.1).

the Control Logic asserts the REG SEL <3:0> code to
addition,
In
the CCI specifying the address offset register as the register to
be

read.

the

CCI,

the REG SEL <3:0> code is decoded to assert RD ADDR

RD ADDR OFFSET enables the data out of the address offset
OFFSET.
1is in the DP, the
to be accessed
register
the
If
register.
register is returned to the DP over the
the offset
contents of

CIPA DATA lines on the CIPA bus.

Twelve

bits

(CIPA D IN <11:00>) of the 16-bit data word received

the CCI specifies the address of the register to be accessed
from
The address is clocked into the
operation.
unsolicited
the
for

XBUS LSA register (see Figure 5-13) by LD XBUS LSA from the CCI/DP
Interface Control

Logic.

from the CCI to the XBUS LSA register in the DP, the
passing
In
Hence
not route through the XBIR register.
does
address
of fset
the offset address

is not checked

for parity.

ACIPA REQUEST SYNC
Unsolicited

CMI

request

from

CCI,

4 CIPA READ SYNC
Specifies

read

operation.

4 REG SEL <3:0>

A SUSPEND SEQ

[QGRANT UNsoi]

Selects offset

Microcode stops running.

CCIl.

LSA
y

selects
for

XBUS

LSA

LS/VCDT

address,

4 CIPA GRANT
CCI notified that

DP is servicing
the
CMI

mux

<07:00>

|#ciea REG SEL <3:0>

unsolicited

request.

selection'

ANED

ASEEED

oame

——————-—--.

‘

CCI

4 RD ADDR OFFSET
Data

enabled

from

address

offset

Access

CCI

CNFGK

A CIPA DATA <15:00>
Address

accessed,

|4c1pn D IN <1x:oo>]

4 LD XBUS LSA
Load

XBUS

LSA

'
register

with

address

accessed.

Write

Read

operation

Fig,

Figure

5-12

Starting

S5=15

Unsolicited

Operation

(FI6. 5-3)_ILLN_Q.Q___1:>_,_©
_Clk Te

(FIG. 5=~ 6)

(Fr6. :-m){—'lw

| busor geab

}(Fuc.sj-/e)

LSA

(FI6. 5= 16)

CIPA D

(Fi. s-2)-Lgiieer
g

(FI6. 4=2)

Xgus|

(FiGy 5= 6)

LS
A

XBUS

LsA €03:00),

LSA 000000
X XXX,

XX /
XX00
LSA 1001

ADDR

gM[-RHESR

(FIe. 5-1b)

(FI1G6. 5-3)

MADR

(FlG. 4-2)

(F16. 5-17)
{MI—DHRATR

PROM

(129 %8)
3M |
4M|
5M

, (FIG. 5-23)
{)-E3RCR

4 )

| BEG MWRT p (FIG. 4-10)

L_(:)

NOTE:

THE LOGIC IN THIS FIGURE IS CONTAINED
ON SHEET L OF THE ENGINEERING
DRAWINGS EXCEPT WHERE NOTED IN
PARENTHESES.

Figure

5-13

Unsolicited

CMI

Request

Logic

The

CCI/DP

line
read

from
or a

Interface

Control

Logic

now

checks

the CCI
to determine
if
the
write.
If the request is for

(CIPA°.

READ

5-14.

SYNC

true),

5-13

1illustrates

the

sequences

false),

request

continue

and

continue

for

with

the

should

with

CIPA

Paragraph

READ

SYNC

request
is
a
a DP location

5.8.2

and

Figure

read

of a DP location
(CIPA READ
5.8.3 and Figure 5-15.
Figure

Paragraph

logic
be

the

unsolicited
a write of

associated

referenced

with

the

write

throughout

both

discussions.

and

read

5.8.2
Unsolicited Write Sequence (Figures 5-13 and 5-14)
unsolicited
write
sequence
involves
obtaining
the
write
data
from the CCI,
selecting the register to be written, and generating

the

clock

5.8.2.1
Logic

load

the

Obtaining

asserts

Receive

data

the Write

the

REG

Write

Data

bus

(CIPA

REG

the

CIPA

decoded

the

high

RCV

DATA

assert

word

from

<15:80>).

CLK

XBIR

The

state

REG

CCI/DP

assertion

SEL

REG

low word from
code 1s again

Interface

the

The

code

coupled

REG

word

the

RCV

CIPA

the

CCI/DP

the

high

portion

Control

access

the

CCI

REG

into

SEL

the

(CIPA

Interface

word

input

enables

onto

bus

CCI
DATA

Control

portion

selected

the

over

the

false

5.3.4).

Logic

alters

Receive

CCI

RD
the

Paragraph

dispatched

the

Data

word

onto

asserted

CCI

HI.

Write

then

Control

SEL

the

CCI/DP

Receive

(see

high

Interface
of

-- The

<3:0>).

high

selected

code

RCV

data

Data

the

<3:0>

and

XBIR

the

into

SEL

bus

load

SEL

the

<K15:00>

Logic

The

write

then

asserts

REG

SEL

The

the

REG SEL code so as to select the
Data Register.
The REG SEL <3:0>

Write
to

the CCI where it asserts RD RCV WD REG
to retrieve the write data low word.
The write data low word
coupled
from
the
Receive Write
Data
Register,
over
the
CIPA
bus, and clocked into the low word portion of the XBIR register by

LO
is

CLK

XBIR

The

CCI/DP

apply

the

LOW.

Interface

write

Control

data

clock

pulse.

WRITE

asserts

UNSOL

data
from
the
XBIR
coupled from the IB
bus

where

The

UNSOL

CLK

write

REG

WRT,

selection

The

CLK

UNSOL

WRITE

This

bus,

XBIR

the

(Figure

5-16)

through

the

flow-thru

selected

the

assertion

(Figure

the

5-17).

selected

LS/VCDT

area.

bus.

UNSOL

The

WRITE

generate

gate

the

write

the

write

latch

data

1is

and

the

discussed

PMTCR,
below

PSRCR,
in

the

discussion.

pulse

after

the

assertion

true.

CLK

UNSOL

clock

asserts

after

true

clock
or

write

then

selected

available

WRITE

Logic

the

WRITE

UNSOL

WRITE,

enables

the

causes

if
the
selected
register
is
the
PMCSR or
the
MADR.
discussed below in the register selection discussion.

5-41

Fig.

5«12

$ REG SEL <3:0>
Select
Data

Receive

VWrite
in

CCI,

4CIPA REG SEL <3:0>
Register

l—

selection

GE)

awe

GED

GEER

CCI.

oEal

cuEE

ARD RCV WD REG HI (LO)

| High (low) word enanled from

|
|

Receive Write Data Register.|

!
Y

)

|fcct rev paTA <15:00>

4CIPA DATA <15:00>
Data

selected

written

?CLK XBIR HI
Data

high

clocked

(LOW)

(low)

into

Selects

word

XBIR

Data

longword 1n
XBIR/::g}///

4REG SEL 0
Llow

into

YES

data

word,

Figure

5-14

Unsolicited

CMI

(Sheet

Write

Operation

Flow

Diagram

y
UNSCL

{

WwRITE

4 XBUS LSA <07:00>

f xBus wr Ls/vcoT

LS/VCDT

LSA

mux,

]

4 xBUS EN LS/VCDT

$wr RAM

4 XBUS LSA <03:00>,
LSA

000000XXXX,

LSA

1001G0XXXX

Selects
to

$wr Par

m—

written,

PSR

$EN LS LO

AEN LS LO

|L--—-.dv

AEN LS HI

\
CLK

YES

$EN UNSOL WRITE

via

# EN XBIR IN

Enables
out

data
XBIR

longword
register.

4 UNSOL WwRITE
Clocks

PMTCR,

PSKCR,

LS/VCDT

CLK

wnen

PICR,

REG

selected.

1
Data

longword

YES

bus.,

14 pMcsR]|

fIB IN <31:00>
Data

longword

bus

MADR

CLK
on

available

Sselected
when

4 CLK UNSOL WRITE
PMCSR

YES

Clocks

$BuUs 18 <31:00>

_UNSOL WRITE

|4 MADR |

4 MDATR

14 PSR

CLK _UNSOL WRITE
V

[# cLk Puesr|

[+ CLk MADR]

CLk

T¢

CLK T2

selected,

|4 EN CS DATA [N]

|4CS WE|

( bone )

{

)

<<‘I=’,~o
YES

UNSOL

WRITE

|# PICR WRT|

YES

UNSOL WRITE

YES

UNSOL WRITE

[4PMTCR CLR|

[ PSRCR

UNSOL WRITE

P CLK

T3 A

[4 REG WRT
|

Figure

5-14

Unsolicited

CMI

(Sheet

WRT,

-43

Write

Operation

Flow

Diagram

5.8.2.2

address

the

Selection

selected

-- The
XBUS
LSA register contains
the
register to be written (Paragraph 5.8.1).

XBUS

LSA

from

the

area

this

case,

XBUS

LSA

LS/VCDT

address

(Paragraph

When

UNSOL

write
are

XBUS

Logic
The

true

alsc

XBUS

LSA

false,

case

Port

XBUS

LSA

outputs

from

the

XBUS

state

IM,

2M,

true,

The

case

the

When

CLK

outputs

UNSOL
¢M

selected
into

PROCM

write
loaded

output
into

the

LS/VCDT

PAR

the
write

strobes

LSA

selected

the

only EN

except

low

1In

(MTE)

5.5. 3).

reglster

the

is not selected as
the area
made
by
a
128
x
8
PROM
which

located

LS.

LS/VCDT

for

the

LSA

selected

area.

(QQQ000@XXXX,

and

PROM

outputs

The

LSA

are

PROM

10010@0XXXX

availlable

inclusive.
IB

0¢

designate

the

area

written.

6M,

will

designate

the

4M,

5M,

false

asserts
PROM

write
from

(MADR)

CLK

1is

MADR

from

the

1is

which

false,

considered

first.

wParagraph

5.8.2.1),

output

operation

the

and
MADR

and

LO asserts.

bit

determines

the

thereby
If XBUS

written.

Control

examined.

assert
written.

area

zeros

(U0

LS/VCDT

enable

PSR*,

all

the

PMCSR

operation

the

2M.

for

the

applied

WRITE

and

the

LS/VCDT

assert

output
IN

and

to the

<@3:90>,

bit

selected

software

signal

used.

will

selection

LSA

Paragraph

false,

The

write

PROM

PSR

(see

LSA

asserts

RAM

the

through

are

XBUS

€M

outputs

enabling

terminals

data

the

addressed

l1s

LSA

the

written.

LS/VCDT

from

LS access

only

Status

The

the

portion

read

5.4.2).

EN LS HI and EN LS
sections respectively.

which

this
high

the

selected

XBUS

the

XBUS

that

XBUS

upper

LS/VCDT

the

asserts

VCDT

The

the

from

the

(Paragravh

state

Note

trus,

where

XBUS

where

specifying
1s

mux

asserts,

LS/VCDT

where

5.4.1).

logic

generated

<@7:¢0>

selection

WRITE

strobe

the

written.

and

bus

true,

the

asserts

(PMCSR)

CLK

IN bus.

MADR

the

1is

PMCSR

(Figure

PROM

the

PROM

outputs

area.

samples

true,

@M,

the

asserts

PROM
PMCSR

load

for

the

5-3).
is

selected

where

write

data

PROM output

(MDATR)

true,

the

MDATR

selected

for
the
write
operation.
1In this case, EN CS DATA IN and CS WE
are
asserted
by
CLK
TO and CLK Tl respectively.
EN CS DATA IN
gates
the
write
data into the CS from the IB IN bus while CS WE
strobes the write data into the CS.
|

PROM
output
3M is asserted when the PSR is selected.
The PSR is
located
1in
the
LS area, therefore the LS/VCDT has actually been
selected as the destination for the write data. (XBUS LSA 09 true).
The
assertion
of
PSR
from
the
PROM
supplements
the LS/VCDT
selection
by
specifying the PSR.
= With PSR true, only the low
section

the

1i1s

enabled

discussed

earlier

this

paragraph.

1IN 00

is true,

PROM outputs

by
UNSOL
WRITE.
When UNSOL WRITE
PROM output to perform the function
If

output

asserts

thereby

uninitialized

true,

PICR WRT

negating

state

(port

UNINIT

(Paragraph

4M,

5M,

6M,

and 7M are sampled

asserts it clocks
described below.
initialize

and

taking

the

control

the

port

asserted

the

5.12.2.2).

If
output
5M is true, PMTCR CLR ( port maintenance timer
register)
1is
asserted
to
reset
the
boot
timer logic
extending the boot timeout period (Paragraph 5.12.2.3).

control
thereby

If output 6M is true, PSRCR (port status release control register)
is asserted to
interrupt flag

the interrupt logic where it resets the maintenance
(MIF) in the PMCSR (Paragraph 5.12.1).

If
output 7M
pulse)
as
a
is
a flag to
microcode can

is true, REG WRT asserts (after the next DP CLK T3 A
branch condition to the CS branching logic.
REG WRT
the microcode that a register has been written.
The
then check the registers for new data.

5.8.3

Unsolicited Read

Sequence

(Figures

5-13

and

5-15)

An unsolicited read sequence involves selecting the register to be
read, reading the register out to the IB bus, and transferring the
read data from the IB bus to the CCI.

The

CCI/DP

enables

the

Interface
read

1is
the

assertion

the

data

out

PMCSR,

Control

the

READ

asserts

selected

MDATR,

selection

UNSOL

Logic
or

the

EN UNSOL READ which

MADR.

This

the

selected

discussed

discussion.
causes

UNSOL

READ

assert

5-17).
UNSOL
READ
enables
the
read
data
out of the
register if the selected register
is in the LS/VCDT area.
discussed below in the register selection discussion.

(Figure

selected
This

FIG,
S=12

4 EN UNSOL READ
Enables data from
PMCSR, MDATR, or
MADR

when

selected.

$ XBUS
LSA

PMCSR/LITERAL mrux
selects PMCSR,
Enables

data

LS/VCDT

when

LSA <p3:¢9),

LSA ¢000d0
x XXX,

Quuson READ

Selects rngs+er Yo

from

4 XBUS

|19 10
XX0
XX

UNSOL

read.

[iBEG SEL g]

selected,

LSA <07:0¢)

LSANVCDT wia

[$ XBus

LSA mux,

READ

RD LSACDT
|
T

[4 xBUS

\
BUS
Read

f REG SEL <3:0>

<31:00>

data

{in

|4 EN

word

High

Data

out

CIPA

CCI,

(low)

word

XBOR

gated

bus,

PSR

f CLK XBOR PAR
BUS 1b6
loaded

selection

fcpr DATA <15:00>
CCI.

Return

read

_____;_____._.__._.
fwar RTN RD HI (LO)
High
into

(low) word loaded
Return Read Data

data

CCI.

REG

SEL

Select

low

4 EN LS LO

MD HI

4 EN LS HI

|
Read

CIFA

Return read
Return Read
Register.

dats

L
§

YES

Y ISA 09

|V LS4 ¢9

Maintenance

nu‘x selee"’s cS
microwonrd.

data

4RD RTN RD REG
data

Dats

[f Prcsr]

bus.

<15:00>

Transfer

daTa Transferred

te TR
LTCHDO

$ EN LS LO

4 EN MD HI

YES

word.

} EN VCDT
EN

@ No

h c1pa REG SEL <3:0>

<31:00> longword
into XBOR register.

LSAiCDT ouT]

fciPa D CUT <15:00>

Selects a high (low)
write of Return Read

bus.

EN Ls/vcDT]

mux selects
MADR data.

longword

CMI,

Y
EN

CCI

UNSOL

(4 MDATR |

[¢ MADR]

READ
EN

——_-b——_———_————-

UNSOL

READ

{4
EN MAINT]

Qoone D

"y
¢ EN

MISC

Inh.bits PMECSR/ALITERAL wux OuTAuT,

$ EN MD HI

Read data trnsferred 1o IB bus.

Figure

5-15

Unsolicited

CMI

Read

Operation

Flow

Diagram

Register Selection -- The XBUS LSA register contains the
5.8.3.1
address of the selected register to be read (Paragraph 5.8.1).
XBUS LSA 09 from the reglster is true, the LS/VCDT is selected

If
as

area

the

read.

to bhe

from the register is applied to the

In this case, XBUS LSA <07:00>

LS/VCDT

address

address selection mux where it is selected as the LS/VCDT

(Paragraph

5.4.1).

RD LS/VCDT goes true causing EN
XBUS
Wwhen UNSOL READ asserts,
OUT gates the output from the
LS/VCDT
EN
to assert.
LS/VCDT OUT

VvCDT

and

the

from

sections of the LS onto the IB bus when the

both

VCDT

are

The

assertion

enabled.

XBUS RD LS/VCDT also causes XBUS EN LS/VCDT to

assert to the DP Control Logic where it enables either the VCDT or
the state of XBUS LSA 08 from the XBUS LSA
on
depending
LS
the
register.

LSA 08 is true, EN VCDT asserts to enable the VCDT.

XBUS

via

the MD bus

The

outputs onto the low word
and
wide
16-bits
only
is
RAM
VCDT
Hence, EN MD HI asserts (along with EN
bus.
IB
the
of
portion
VCDT) to enable all zeros onto the high word portion of the IB bus
(Paragraph

5.5).

08 is false, EN LS HI and EN LS LO assert to enable
LSA
XBUS
If
Note that
high and low sections of LS onto the IB bus.
the
both
if the LS access is to the PSR, EN MD HI asserts in place of EN LS

As
HI.
PSR
the
are read
1IB
the
supplied

discussed in Paragraph 5.8.2.2, only the lower 16 bits of
When the PSR is read, the 16 bits
are written into LS.
out of the low section of LS onto the low word portion of
16 bits (15 zeros and the MTE bit) are
upper
The
Dbus.
to the IB bus from the MD bus (Paragraph 5.5.3).

LSA

XBUS

false,

the

area

output enables

the

read data

The

PROM

output OM is true, PMCSR asserts to the DP Control Logic.

The

to be read.

Instead,

the

LS/VCDT

not

selected

the selection is made by a 128
from the

selected

x 8

PROM whose

<K@3:00>, LSA 000000XXXX, and LSA
is addressed by XBUS LSA
100100XXXX from the XBUS LSA register.
PROM outputs used
1in
accessing read locations are at PROM terminals oM, 1M, 2M, and 3M.

assertion
of EN UNSOL READ causes PMCSR to assert EN MD HI
MD LO to gate the PMCSR data to the IB bus.

and EN

asserts indicating a read of the
MDATR
true,
is
1M
output
If
maintenance data register.
XBUS LSA 00 from the XBUS LSA register
is negated and applied to the maintenance mux in the CS causing it
to

select

the microword

from

the

RAMs,

When

MAINT

UNSOL

READ

assert

and

asserts,
EN

MISC

the

true

negate.

state
EN

MAINT

MDATR
gates

causes
the

output

from
the maintenance mux onto the MD bus while the negation of EN
MISC
1isolates the output of the PMCSR/LITERAL mux from the MD bus
(Figure 5-3).
EN MAINT also causes the DP Control Logic to assert
EN
MD HI and EN MD LO to gate the MDATR data (the microword) from
the MD bus to the IB bus.

output

true,

MADR

asserts

1indicating

maintenance
address
register.
XBUS
LSA
00
from
register
1is
asserted
causing
the
maintenance mux
select the data from the MADR register.
When
to

UNSOL

assert

the

READ

and

maintenance

asserts,
MISC

mux

onto

the

true

negate.

the

state
EN

MD bus

MAINT

while

MADR
gates

the

read

the

the XBUS LSA
in the CS to

causes
the

MAINT

output

negation

from

MISC

isolates
the output of the PMCSR/LITERAL mux from the MD bus.
also
causes the DP Control Logic to assert EN MD HI and
MD LO to gate the MADR data from the MD bus to the IB bus.
MAINT

output

true,

PSR

asserts

indicating

read

the

EN
EN

PSR

register
in
the
LS.
1In this case the LS/VCDT has actually been
selected as the area to be read (XBUS LSA 09 true).
The assertion
of
PSR
from
the
PROM,
supplements
the
LS/VCDT
selection by
specifying
the
PSR.
A read of the PSR was described earlier in
this

paragraph

5.8.3.2

when

the

LS/VCDT

area

was

discussed.

Transferring
the
Read Data to the CCI -- The read data
selected register is now on the IB bus as BUS IB
CCI/DP
Interface
Control
Logic will initiate a
of the read data from the IB bus to the Return Read Data
in the CCI (and then to the CMI).

taken
from
the
<31:00>).
The
transfer

The

CCI/DP

1Interface

the
data
1longword
negated
state
of

out

data

high

LTCHD

CIPA

The

CCI/DP

code

for

The
bus

the

word

Control

1is

applied

Interface
a

high

write

Control

word

select

decoder.

decoder

outputs

<15:00>)

1into

asserts

CLK

XBOR

the

Return

Read

Data

<15:00>,.

write

The

Logic

1In
WRT
the

PAR

load

from
the IB bus into the XBOR register.
The
REG
SEL
0
gates the high word from the XBOR
CIPA BUS as CIPA DATA <15:00>.
1In the CCI the

Logic
of

the

also
CCI

asserts
Return

transferred

the

Read

the

CCI

REG
Data

over

SEL

<3:0>

the

CIPA
|

code
is
1input to the CCI and applied to a
response to the input REG SEL code, the write
RTN RD HI to load the read data (LTCHD CIPA D
high

word

section

the

Return

Read

Data

The CCI/DP Interface Control Logic then asserts REG SEL 0 which
The
the low word from the XBOR register onto the CIPA bus.
gates
is transferred to the CCI over the CIPA bus where it 1is
low word
applied to the Return Read Data Register as LTCHD CIPA D <15:00>.

Asserting REG SEL 0 altered the REG SEL code to specify a low word
The REG SEL code 1s
Register.
Data
Read
Return
the
of
write
transferred
to
the CCI where it is applied to the write decoder.
code by
SEL
REG
altered
the
to
responds
decoder
write
The
WRT RTN RD LO to the Return Read Data Register where it
outputing
loads the read data into the low word section of the register,

With the requested read data in the Return Read Data Register, the
to initiate a data transfer of the
RD RIN RD REG
asserts
CCI
requested

5.9
The

data

the

CMI.

DP CONTROL LOGIC (Figure 5-16)
Control Logic generates the commands

and

enabling

signals

controlling
the
data
flow within
the DP.
The control
1logic
receives
its commands from the CS microword
except during
unsolicited CMI operations when the microcode 1is suspended and
control shifts to the host CPU.
The commands received from the
microword specify the source and destination for the IB bus.
5.9.1
IB Bus Destination
The
IB
DST
<03:00>
field
from
the
destination
for
the
data on the IB bus.
DST code and the destinations it selects.

microword
Table 5-8

selects
the
lists the IB

A destination
decoder
decodes
the
1IB DST field and outputs the
selected
destination.
The decoder is enabled when IB DST 03 = 0
(first
eight
codes
1in Table 5-8).
The remaining three bits (IB
DST
<02:00>)
are decoded to select the destinations shown in the
table.
Note
that
if
the
port
1is
1in the uninitialized state
(UNINIT
true),
or
an
unsolicited
CMI operation is in progress
(SUSPEND DEL true), the decoder is disabled and the destination of
the IB bus is selected by the host via
LSA register (Paragraph 5.8).

the CCI module

and

the XBUS

Decoder
outputs
LD INDEX or LD XLATE are asserted when the LS or
the
VCDT
1is to be the IB bus destination.
The selection process
takes
two cycles of microcode.
During the first microcycle (when
IB
DST
03
= 0), LD INDEX (or LD XLATE) loads the index register
(or
the
translate
register) with the LS or VCDT address (Figure

5-6).

The selection between the LS or the VCDT

second microcycle when

DST

is made during the

(FIG.

5-17)_EM UNSOL WRITE

DECODER

LO PB OUT

DESTINATION

I8 DST <02:00>

SEL

_SUSPEND

DEL

EN ALU

DECODER

}| ENABLE

(FIG, 5=13)

(FIG. 5=17)
(FIG. S=13){

S{FIG,

SR€

SUSPEND
(FIG. 5=17)
|
SEQ

soveea0

UNSO

t} (FIG. 5=6)

E3=15

SOURCE

(FIG. Se25) UNINT

LD INDEX

e —————

5=8)

L8/VCDT
s

FIG.)
EN MAINT
5«13

l E3=13

[
H—

—
@—r\

(FIG. 5=4)
EN(LJSNCDT

XBUS EN LS/VCDT

PAR

FIG,

EN MISC L
-

/L
\_

LS/VCDT
%

ENPS IN

—

PSR
xgus RD LS/VCDT

- (FIG, 5=10)

(F1g., S=17; 5=21)

LD XLATE

) ENABLE

DST XBUS

(FIG. 5-2%) _UNINIT
S=17)

_} (FIG. S=3)

—
TM

(FIG. 42)" § |5 psT
03

(F1G.

XBIR

[ LA

E3-1s

)

ENMD LO

}

(FIG. ' $=3)

EN MD Hi

—

XBUS LSA 08

(FIG, 5=21 )
-

(FIG. 5<6)

DST

INHIBIT

NDEX 0B

EN VCDT

202

1
S/D

l/v

‘

S=13){
o

(FIG. 5=21)

INHIBIT

{:x:

S/D 0

(FIG, 5=6)

ol
INDEX 08

‘

PSR

3 (FIG. 5=4)
—

Do :}

_XBUSEN LS/vcDT

DST

ENLSLO

XBUS LSA 08
(F1G.

L} (FIG, S5=10

——»

EN LS i

Se-

l
DG

—)—'

NOTE:
THE LOGIC IN THIS FIGURE IS CONTAINED
ON SHEET S OF THE ENGINEERING
DRAWINGS.

Figure

5-16

5-50

Control

Logic

Table

IB DST

5-8

DST Code

Destination

S/D

LLS/VCDT
Address

)

%)
1)

)
Y

1
1

")
1

No
LD
LD

operation
INDEX
XLATE

DST

XBUS

(XMIT

DST XBUS (byte
register)

m—————-

file)

=
=

mask

me————-

m——————
meme———-

m—————

)

DST

e ————

PB
used

=
-

me————
mm—————

XBUS

(command/

Source

address reg.)
LD PB OUT

Y
1

1
Y

1
0

MLD
Not

)

m—————-

)

1
1

@
1

1
@

1
4]

"
LS

=
0

—e————
LITERAL

1
1

)
1

1
)

LS or
LS

VCDT*

g
l

1
0

Index Register
Translate Register

VCDT

LITERAL

*Depending

The

INDEX

three

£8;

codes

INDEX
INDEX

from

the

@,
l,

@8
@8

LS selected
VCDT selected

destination

decoder

assert

DST

XBUS.

This output is asserted when the CCI module is selected as the IB
bus destination.
The three possible destinations within the CCI

are

the

XMIT

registers.

Control
Control

SEL

file,
The

DST

the

byte mask

XBUS

output

applied

and
to

Logic along with the DST <1
bits.
Logic responds to the DST <K1:£> code

<3:0>

code

specifying

the

selected

the
the

command/address
CCI/DP

Interface

The CCI/DP Interface
by asserting the REG

destination

(Paragraph

5.10.1).

Decoder output LD PB OUT is asserted
selected as the IB bus destination.
register

(via

the

bus)

MLD

output

the

loop

(Figure

5-3).

Decoder

output

enables

the

and

allows

the

data

for

output

maintenance

OUT

back

when the PB OUT register 1is
LD PB OUT loads the PB OUT

function.

onto

the

onto
DP by

the

PORT

When

the

DATA

asserted

PORT

enabling

DATA
the

bus

bus
IN

when IB DST <@3:92> = 1l:1, the LS/VCDT area 1s selected as the IB
bus destination.
The IB DST code
1is converted
1into an S/D

(source/destination) code generated to control the LS/VCDT address
selection in the LS/VCDT address selection 1logic
(Paragraph
The S/D code 1is 1listed 1in Table 5-8 along with the
5.4.1).
address sources that it selects.
The S/D code also enables the LS
or VCDT as an IB bus destination as shown 1in Table 5-8 and
described

Paragraph

5.9.2

Bus

5.9. 3.

Source

The IB SRC <02:900> field from the microword selects the data
Table 5-9 lists the IB SRC code and the
source for the IB bus.
it

sources

selects.

Table 5-9

ALU

VCDT

* Depending

INDEX

A source decoder decodes
source.

Note

that

(Paragraph

= LS,

the

1
0
1

LITERAL

Index Register
Translate Register

LITERAL
-

-——-

-———

= VCDT

IB SRC

port

Source

(EN XBIR IN)

(LITERAL)

E3-15

)
1

E3-13

LS or VCDT*
LS

%)
1

Address

1
0

)
)

LS/VCDT

S/D

IB Source

IB SRC
2

SRC Code

1is

field and outputs the selected
in

the

wuninitialized

state

(UNINIT true), or an unsolicited CMI operation 1is 1in progress
(SUSPEND SEQ true), the decoder is disabled and the source for the
IB bus is selected by the host via the CCI module and the XBUS LSA
5.8).

The first four codes listed in Table 5-9 assert SRC RD LS/VCDT
The IB
thereby selecting the LS or the VCDT as the IB bus source.
code
(source/destination)
SRC code is converted into a S/D
generated to control the LS/VCDT address selection in the LS/VCDT
address selection logic (Paragraph 5.4.1). The S/D code is listed
The
in Table 5-9 along with the address sources that it selects.
S/D code also enables the LS or VCDT as a source for
shown in Table 5-9 and described in Paragraph 5.9.3.

the

IB bus

SRC RD LS/VCDT asserts EN LS/VCDT PAR to the DP parity logic to
enable a parity check on the data read out of the LS or the VCDT.

SRC RD LS/VCDT also asserts EN LS/VCDT OUT to enable the output of
the

LS/VCDT

RAMs.

true state of EN LS/VCDT OUT causes EN MD HI to assert 1if the
The
Thus the all-zeros high
selected (EN VCDT true).
been
has
VCDT
bus along with the low
IB
from the MD bus is placed onto the
word
5.8.3.1).
and
word from the VCDT (see Paragraphs 5.4
1IN is asserted when the PB IN register is
EN PB
Decoder output
As shown in Figure 5-3, EN
selected as the source for the IB bus.
The
onto the MD bus.
register
IN
PB IN gates the data from the PB
Note
LO.
MD
EN
and
HI
MD
EN
by
bus
then gated to the IB
1is
data
that EN PB IN asserts EN MD HI and EN MD LO, and
5-16
Figure
in
The assertion of EN MD HI and EN MD LO effects
EN MISC.
negates
The negation of
the MD bus to the IB bus.
from
the data transfer
from the MD bus
output
mux
AL
PMCSR/LITER
the
1isolates
EN MISC

while the PB IN register data is being transferred.

Decoder output E3-13 is asserted when the microword LITERAL field
The true state of EN
the source for the IB bus.
as
selected
is
AL mux onto the MD
PMCSR/LITER
the
from
data
LITERAL
the
MISC gates

decoder output asserts EN MD HI and EN MD LO to
E3-13
The
bus.
transfer the LITERAL data (and the all-zero high word) from the MD
bus

the

bus.

Decoder output EN ALU is asserted when the ALU is selected as the
EN ALU enables the ALU logic.
data source for the IB bus.

Decoder

output

onto

E3-15

asserted

when

the

XBIR

E3-15 asserts EN XBIR IN
the source for the IB bus.
as
selected
EN XBIR IN gates the data in the XBIR register
an OR gate.
via

the

XBIR

bus.

1IN is also applied to the CCI/DP Interface Control Logic

CHK XBIR PAR is applied to the DP
it asserts CHK XBIR PAR.
where
an IPE parity check on data transferred
to enable
logic
parity

An IPE parity
from the CCI to the IB bus via the XBIR register.
error results in the assertion of CIPA ERROR in the DP (PMCSR) and
in the assertion of CBPE in the CCI (CNFGR) (Paragraph 5.7.4.2).
5.9.3

Control Signals

the gating signals generated by the DP
This paragraph discusses
conditions they are asserted.
what
under
and
Logic
Control

1in the MD bus logic (Figure 5-3) to gate the
1is used
EN MISC
EN MISC 1s
L mux onto the MD bus.
PMCSR/LITERA
the
of
output

except when the MD bus is being used to transfer
asserted
always
IN register to the IB bus (EN PB IN true), or to
PB
the
from
data
(EN MAINT true).

the IB bus

data from the MDATR or the MADR registers (in the CS) to

)

transfer

EN MD HI and EN MD LO gate the MD bus high word and the MD bus low
word
respectively
onto the IB bus.
Both signals are asserted by
EN
PB
IN
thus
gating
the
assembled
longword
from the PB IN
register
to
the
1IB
Dbus.
Both signals are also asserted by EN
MAINT
thus gating the MADR and MDATR data from the CS onto the IB
bus.
Both
signals
are
again
asserted
by the E3-13 (LITERAL)
output
of
the source decoder thus gating the LITERAL data to the
IB bus (via the PMCSR/LITERAL mux).
When
executing
an unsolicited
CMI read operation (EN UNSOL READ
true),
and
1if the PMCSR is specified (PMCSR true), both EN MD HI
and
EN
MD
LO
are
operation
specifies
(Paragraph 5.8.3.1).

again
asserted.
If
the
PSR
(PSR
true),

the
unsolicited read
only EN MD HI asserts

EN
MD
HI is also asserted by the ANDing of EN LS/VCDT OUT and EN
VCDT.
EN
LS/VCDT
OUT
1is
asserted
by an unsolicited CMI read
request of the LS or the VCDT (XBUS RD LS/VCDT true), or by a port
initiated
read
request
of
the
LS
or the VCDI (SRC RD LS/VCDT
asserted
by
the
source decoder).
When the VCDT is the selected
source (EN VCDT true), EN MD HI is asserted to supply the all-zero
high word onto the IB bus.
Control
signals EN VCDTI, EN LS LO, and EN LS HI enables the VCDT,
the
low
word
section
of
LS,
and
the high word section of LS
respectively.
Each
of
the
three enabling signals are asserted
from an OR gate.
Each OR gate is fed from three AND gates.
During
an
unsolicited
CMI
request,
DST
INHIBIT
asserts
and
disables two of the three AND gates in each signal area. The third
AND
gate
1is
used
to
enable
the signal during the unsolicited
operation.
XBUS EN LS/VCDT from the unsolicited CMI request logic
is
applied
to the three active AND gates along with XBUS LSA 08,
XBUX

LSA
08 selects between the LS and the VCDT.
If XBUS LSA 08
is true, the VCDT is enabled (EN VCDT asserts).
If XBUS LSA 08 is
false, the high and low section of LS are enabled (EN LS HI and EN

LS
LO
assert).
If
the
LS access is to the PSR, only EN LS LO
asserts.
However, in this case EN MD HI asserts to gate the high
word portion of the PSR from the MD bus to the IB bus.
When
the
port
is
under
microcode control (DST INHIBIT false),
enabling of the VCDT, the low section of LS , and the high section
of
LS
1is
done
via
the other two AND gates in the three signal
areas.
The
two-bit
S/D
code
generated in the LS/VCDT address
selection
logic
1s applied to the six AND gates to select the LS
or
the
VCDT.
Using
the
S/D
code
from
Table 5-8 or 5-9 and
following

the

VCDT

used

the

logic

enabled

select

between

Figure

shown

the

5-16,

the

and

can

tables.

the

VCDT

seen

Note

when

that

the

INDEX

necessary.

5.10

CCI/DP

INTERFACE CONTROL LOGIC

The CCI/DP Interface Control Logic is shown in Figure 5-17.
The
logic consists of a PAL (programmable array logic) and two PROMs.
port
the
and
CCI
the
from
commands
input
senses
1logic
The

outputs

and

microword,
commanded

operations.

Included

in the output

four-bit

is a

signals

required

the

(REG SEL

select code

the

execute

<3:9>) which is sent to the CCI where it is decoded to select the
The register select code is
CCI register or file to be accessed.
3 of the code specifies
SEL
REG
Note that
given in Table 5-14.
the operation is a read or a write (false = read; true =
Hence when REG SEL 3 is true, DRIVE CIPA asserts to the

whether
write).

interface

the

logic

(Figure 5-2)

enable write

data

out

the

DP to

CCI.

REG SEL

Table 5-10

REG SEL Code

Decoded Mnemonic
(Read)

REG SEL
3210

321040

9 0 0 0
g

9 1

861

111

"
HI

RD RCV FILE

01
0

1 10

RD RCV REG LO
RD RCV FILE

0 0 @

RD RCV REG

g 1

RD ADDR OFFSET

Decoded Mnemonic
(Write)

LD CMD/ADDR HI

LD ADDR LO

LD BYTE MASK

110

111

LD XMIT

FILE

LD RTN

RD REG

LD XMIT FILE

LD RTN RD REG

LO
HI

The functioning of the CCI/DP Interface Control Logic is explained
in terms of a port initiated read and write of the CCI (from the
These
DP.
the
of
write
and
read
unsolicited
an
and
DP),
sections
other
in
detail
in
operations have already been discussed
Only the commands issued by the CCI/DP Interface
of this chapter.
Control

Logic

are

The PAL contained
as a sequencer.

discussed

here.

in the Interface Control
DP CLK T3 A clocks the

Logic (E6@)
PAL causing

functions
it to go

CI750 state
the
on
shown
sequence of states as
through a
drawings .*
If a location is addressed in the Interface Control
Logic that does not correspond to a valid state, the logic asserts
ILLEGAL STATE to the port clock logic (Figure 5-21) to stop the DP
clock

(DP

CLK

* The

state

T3).

drawings

are

part

the

CI750

Engineering

set.

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the

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5-56

5.10.1
Port Initiated Write of CCI
Figure 5-18 illustrates the CCI/DP Interface Control
involved in a port initiated write operation.

Logic

signals

When
the
DP
has
data to be transferred to the CCI, DST XBUS is
asserted
by
the
DP Control Logic.
The CCI/DP Interface Control
Logic
responds
by outputting LOAD XBOR to load the XBOR register

with

the data

The

DST

transferred.

<1:0> code

from the microword

specifies where

the CCI

the
data is to be written.
The destination for the data could be
the command/address registers, the byte mask register, or the XMIT
file.
The Interface Control Logic outputs the appropriate REG SEL
code

according

the

DST

input.

CIPA CLK

the

CCI

to clock

CCI

destination

was

the

byte mask

the

output

<1:0>

the data

from the
the

DP.

operation

is
complete
as
only
one
transfer
1s
necessary.
If the CCI
destination
was
the
XMIT
file
or
the
command/address
high
register,
another transfer is required to write the low word into
the XMIT file or the low address into the low address register.

another

transfer

required,

the

DST

<1:0>

code

specifies

the

destination
to
the
CCI/DP Interface Control Logic which outputs
the
appropriate REG SEL code along with the CIPA CLK EN signal to
clock the data into the CCI.
NOTE

A write
operation
of
the
CCI
always
takes
800 ns (two 400 ns cycles).
When
writing
the byte mask register only one
transfer
is
required,
however
the
microcode
executes
a
no-op
cycle
resulting
1in
the transfer time for the
byte mask register also being 800 ns.
5.10.2

Figure

Port

5-19

involved

Initiated

illustrates
a

port

Read

the

initiated

CCI

CCI/DP

Interface

read

operation.

Control

Logic

signals

When
data
1is
1in the CCI RCV file ready to be transferred to the
DP,
the DP Control Logic specifies a read of the CCI by asserting
EN
XBIR
1IN.
The CCI/DP Interface Control Logic outputs the REG
SEL
code
for a high word read of the CCI RCV file.
The RCV file
is
the
only
CCI
location
that can be read by the DP in a port
initiated transfer.
The

logic

CCI

into

The

logic

RCV
file

then

the

asserts

high

LOAD XBIR

section

the

XBIR

load

the

high

word

from

the

also outputs the REG SEL code for a
file.
CIPA
CLK EN is output to the CCI
read pointer.

low word

read of the
increment the RCV

start

)

4
4 DST xBUS *
DP

has

data

to CCl,

4 LOAD XBOR
Load

transferred

into

XBOR

4 pST <1:0>
*

Specifies register
byte mask, or high

to be written (CMD/ADDR
wvord of XMIT fi{le),

hi,

f REG SEL <3:0>
Specifies

written.

fcm CLK EN
Clocks

data

into CCI.

Wwrite
byte

mask

f DST <1:0> *
Specities register to be written
register

(low address

wvord

lov

written.

XMIT file).,

} REG SEL <3:0>
Specifies

;

¥ Input to Interface

f CIPA CLK EN
Clocks

aata

Control

into

Loglic

CCI,

~—

<j Done

Figure 5-18

CCI/DP Interface Control
Write

CCI

Logic —-- Port Initiated

<
4 en XBIR IN t]

RCV

file

has

data

read,

?REG SEL <3:30>
Selects

high

word

from CCI

RCV

file,

into

4 LoaD xBIR HI
Clock

high

word

4 REG SEL <3:0>
Selects

low

receive

parity

CCI

RCV

tile.

file

pointer.

word

f CHK XBIR PAR
Check

from

fcu( XBIR LOW
Clock

into

XBIR

input

longword,

Done
Figure

5-19

word

} CIPA CLK EN
Increments

XBIR

Input

CCI/DP Interface Control
Read

CCI

Interface

control Logic
Logic --

Port

Initiated

logic then asserts CLK XBIR LOW to load the low word from the

The
CCI

into the low section of the XBIR register.

Finally

CHK XBIR PAR asserts to enable a parity check on the data

longword

transferred

from the CCI,

5.10.3

Unsolicited Request Operations

involved

in an unsolicited

Figure 5-20 illustrates the CCI/DP Interface Control Logic signals
When
SYNC

Logic

request operation.

unsolicited request operation is initiated, CIPA REQUEST
an
are asserted to the Interface Control
READ SYNC
CIPA
and
from

the

CCI.

The
logic
responds to CIPA REQUEST SYNC by asserting GRANT UNSOL
and
SUSPEND SEQ.
GRANT UNSOL is sent to the CCI to indicate that
an
unsolicited
operation is in progress.
SUSPEND SEQ is applied
to
the
clock
1logic
to
stop
the
port
microcode from running
(Paragraph

5.11.2).

The logic responds to CIPA READ SYNC by asserting the REG SEL code
for
a
read
of the CCI address offset register.
All unsolicited

operations
start
by
a
read
of
the address offset register to
determine
the
address
of
the
register
to
be accessed by the
operation,
The
address
passes from the CCI, over the CIPA bus,
and
then to the LSA address register in the DP.
The address does
not
pass through the XBIR register, hence does not undergo parity
checking.

The
Interface Control Logic then outputs LD XBUS
register address into the LSA address register.

LSA to clock the

At this point, the CIPA READ SYNC input
the
operation
1is
a read or a write.,

is checked to determine if
TIf CIPA READ SYNC is true,
the
Interface
Control
Logic outputs EN UNSOL READ indicating an
unsolicited read operation is in progress.

The
logic
then
outputs LOAD XBOR to load the data read
selected register, into the XBOR register for transfer to

from the
the CCI.

The
1logic also outputs the REG SEL code for writing the data high
word
into
the
Return
Read Data Register.
The Return Read Data
Register
is
the only CCI location that is written from the DP 1in
an

unsolicited

read

operation.

The

Interface

Control

the

data

word

completes

1low

the

Logic

1into

unsolicited

increments

the

read

Return

operation.

the
Read

REG SEL code
Data

write

This

[f CIPA REQUEST SYNC LI

[f GRANT uNs%]

[f CIPA READ SYNC zl

A suseEND sEQ
Port

microcode

stopped,

f REG SEL <3:0)
Read

address

’ LD XBUS LSA

offset

CCIl.

Load

unsolicited

target

into

LSA

address

address
'

If EN UNSOL READI

[f EN UNSOL unxr:]

BE" XBIR IN # l

4 LoaD xBOR
Load

read

XBOR

dats

into

A REG SEL <3:0>
Read

f REG SEL <310>
write
Read

high
Data

word

high

Vrite

into

word

Data

ftroa

Receive

Return

f LOAD XBIR HI

Clock

high

word

into

DP,

A REG SEL <310>
Write

lov

word

into

Read Data Register.

Return

f REG SEL <310>

Read lov waord from Receive Write Dats Register.

\
¢

Inout

Control

Intertace

fcux

XBIR

Clock

low

LOV

Loglic
word

into

DP.

4 CHK XBIR PAR

\
Done

Check

parity

input

longvord.

]

Figure 5-20

CCCI/DP Interface Control Logic —-- Unsolicited
Request

Operations

CIPA

READ

SYNC

being

determined,

UNSOL

WRITE

checked

the

false

when

1Interface

1indicating

the

type

Control

unsolicited

Logic
write

operation

would

was

output

operation

asserting

progress.

The

XBIR

Control

The

CCI/DP

the

SEL
code
Register

Logic

CCI/DP

Interface
for

specifies

Interface

Control

reading

read

Control

Logic

high

the

responds

word

logic

The

outputs

LOAD XBIR

then

increments

the

logic

CCI

to
read
Register.

the

LOW

data

CLK

XBIR

into

the

DP,

Finally,

CHK

longword

transferred

asserts

the

XBIR

PAR asserts
in

Port

clocks

5.11.1

Port

Clocks

CMI
has a
the CMI bus

period

the

160

done

with

is
MHz

(200
of

place

of
inputting

from
CLK

160

the
T3.

REG

SEL

word

the

logic

high

code

and

REG
Data

the

from

the

Write

the

word

into

outputs
Receive

clock

the

DP.

the

Write

data

Data

low

word

from

And

The

enable

parity

check

the

data

CCI.

Operating

bus cycle of
clock (CMI B
ns.

to
the

Modes

160 ns.
The bus cycle is established
CLK) which is a 6.25 MHz clock with a

CI750 port uses a 5 MHz clock with a time
transfers at the port-to-CMI interface use
ns bus clock.
Timing throughout the rest of the port is
the 200 ns clock.

200

seen in
applied

out

from

clock

Receive

5.11

The
by

1low

by outputting

from

1in the CCI.
The Receive Write Data
CCI
1location
that
1is
read
from the DP in
operation.

The

CCI

Logic.

ns.

Data

Figure

5-21,

to
ns)

phase

the

the
clock

the output of a 20 MHz crystal oscillator
<clock logic where the 20 MHz is divided down to 5
and phase shifted to produce four 200 ns clocks 90°

with

each

MHz
external

logic

are

other.

oscillator

external

clock can be used in
asserting EXT CLK SEL and
CLK.
The four clocks output

clock as EXT
designated as

CLK

TO,

CLK

T1,

CLK

T2,

and

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CLK T3 is the base clock used to generate all the port critical
clocks.
The clocks derived from CLK T3 are listed in Table 5-11.
The table also lists where the clocks are used and the modes 1in
which

they are

enabled

(indicated

Table

Clock

an X).

Port Clocks

5-11

Where

Modes

Used
Run

Uninitialized

©Stall

Suspend

DP CLK T3 A

SEQ

UWORD CLK

PB@

CLK

DST CLK

PORT CLK
PORT

CLK

in the

@ PORT CLK is also used

DP CLK T3 A is

used

registers. It is
asserted by the

link module.

to clock control

signals and some destination

running at all times except when ILLEGAL STATE 1is
CCMDP Interface Control Logic.
ILLEGAL STATE

indicates a fatal error condition wherein the error hardware may
not be reliable.
By gating off DP CLK T3 A,
the port error
condition is preserved for maintenance testing.

SEQ CLK T3

used

clock

the

runs

the

microsequencing

and

CS microsequencer

port microcode. It is used mainly
to load microcode registers.

control

UNORD CLK is
used
to
clock
microword
1logic
functions of the port microword on the CS bus.

that

whose

1inputs

are

DST CLK A
1is
wused
to
1load
most
of
the
destination
registers
controlled by the microcode (e.g. the PB OUT and PB IN registers).
PORT

CLK and

PB
and
the
identical to

PORT CLK

are

used

control

operations

1link
modules.
The
two
<clocks
CLK T3 and are always running.

are

within

the

functionally

5.11.2
Operating Modes
The DP operates in one of
1.

Run

Uninitialized

Stall

Suspend

5.11.2.1

comes

modes:

Mode

are

This

true,

STOP

SEQ

stopping

the

port

stops

address

1is

executed

Uninitialized

four

Mode

Run

powered

following

Mode

Microinstructions
operational.
5.11.2.2

the

Mode

the

-- This

error

normal

every

200

mode

condition

asserts

and

microcode.

All

entered

mode.

«clocks

when

detected.

are

the

port

When

UNINIT

CLK

thereby

microsequencer

1in

the

gates

The

operating

ns.

off

SEC

zero.

5.11.2.3
Stall
Mode
There
are
occasions
when
a
microinstruction cannot be completed within the basic 200 ns clock
cycle,
for
example
when
the
data
to
be
transferred
is
not
yet
available.
Under
such
conditions,
the
microcode
1is
stalled
thereby stretching out the microcycle in multiples of 208 ns.

seen

1in

Figure

transferred

over

to be
but:

transferred

low

the

complete

5-21,
the

UCODE

CIPA

the

word

input

cycle

(CLK

XBIR

LOW

STALL may

assert

direction.

bus

still

either

from

the

CCI

preceding

when

(EN

data

XBIR

input

When

being

data

1is

asserts)

transfer

not

true)

the

preceding

progress

then

UCODE

When

data

and

DRIVE

the

STALL

low

UCODE

CIPA

has

STALL

from

the

CCI

still

the

CCI

(DST

true),

asserts.

transferred

assert)

word

direction)
then

transfer

(DRIVE

cycle
not

out

the

XBUS

but:

the

completed

asserts.

preceding
(EN

RSEL

transfer

still

true),

(in

either

The
assertion
of
UCODE
clocking of the microword
and

DST

stops

INHIBIT

the

port

STALL
gates
off
UWORD
CLK
to
prevent
logic.
UCODE STALL also causes STOP SEQ

assert.

microcode

STOP

from

SEQ

gates

running.

off

DST

SEQ

CLK
A
to
addition,

prevent
1loading
of the
destination
UCODE
STALL
inhibits
the
assertion
of
delaying the start of any new transfers.

thereby
Figure
time

5-21A

1llustrates

period

operational.

finish

resulting

STALL.

UCODE

DST

CLK

the

three

STALL
logic

CLK

time

period

remain

time
and

the

microword

off

3
5

clocks

and

off

SEQ

the

CLK

stall

while

5.11.2.4

Suspend

CPU

may

Mode

want

request.

To
make
the
CMI
access,

(suspended)

until

case

the

CCI/DP

suspend

SUSPEND

X+1

the

port

port
the

CLK,

and

continues

removed,
UCODE
The microword

data

unsolicited

said

port

(X+2)
from the CS.
run
mode
and
the

via

paths
1is

the

run

mode,

the

CMI

temporarily

CMI

access

the

suspend

mode.

and

SUSPEND

SEQ

SUSPEND

DEL

are

Control

Logic.

SUSPEND

SEQ

SEQ CLK T3 thereby
controlled by the host

asserts

stopping
CPU.

the

port

off

DEL

asserts

DST

INHIBIT

which

inhibits

Thus

during

the

cycle

CLK

still

active

load

the

DST

which

SUSPEND

destination

asserted
STOP

CLK

SEQ

5-21B

period

time

CMI

microword

period

request

gates

illustrates
1

off

SEQ

CLK

microword.

logic

execution

and

action

during

executed

with

X+l

causes

thereby

Note
in
STOP SEQ

asserts,

DST

Hence,

(not
stalled).
the last cycle

that

executing

SUSPEND

the

SEQ

microcode

the

all
to

suspend

clocks

when

the

assert.

does

not

mode.

1In

operational.
unsolicited
SUSPEND

advance

SEQ

the
CLK and DST CLK A respectively clock
the
the destination
registers
thereby completing

UWORD

and

microword

pulse

microword

appears

microword
CLK

port

and

X+1.

gates

off

SUSPEND
DST

CLK

Figure
time

by
SEQ

mode.

run

microcode.

registers.

eXxecution
of
the
current
microword
is
completed
This makes the cycle in which SUSPEND SEQ asserts,
the

for
the
stopped

completed.

mode

now

In
X+2

unsolicited

available

microcode

asserts.

UCODE

remains

condition

preventing
the destination registers
from being
loaded.
Figure 5-17 that SUSPEND DEL is asserted one cycle after
A

cannot

T3,

UWORD

clocks

but

Interface

gates

the

port

While

access

unsolicited

The

mode.

all

microword

SEQ CLK T3 clocks the next microword
time
period
6
the
port
returns
to
the
microword executes.

which

1In
CCI

assertion

stall condition is
clocks are gated on.

X+1,

this

registers.
GO
in
the

stall

the

three

DST

executes

the

which

off

with

X+l

and

gates

and destination
registers are clocked by
UWORD CLK and DST
respectively, thereby completing the execution of microword

host

the

executed

condition

gated

period

during

1is

stall

gates

negates,

action
X

period

the

STALL

clocks

execute.

port

microword

CLK

INHIBIT

DEL

asserts

the

DP CcLk T3 A

Time Feriod
Microword

eoScaEomsb-~SEyeS

UWORD CLk

DST ¢tk A

UCODE STALL |_

——ey

"lr"

SEQ ClLk T3

I
l
RUN
"¢MODE

I'&

’

‘

]

Figure

5-21A

Stall

5-67

Mode

Timing

RUN
t

[

r—

MODE ——

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During

time

periods

through

executing.
UWORD
CLK
1is
portions
of
the microword

operation.,

completed
and
enables SEQ CLK

time

the

unsolicited

CMI

function

active during the suspend mode because
logic are used for the unsolicited CMI

period

SUSPEND
T3 which

the

wunsolicited

operation

SEQ
negates. The negation of SUSPEND SEQ
clocks the next microword (X+2).
DST CLK

A remains
gated
off
(due to the one cycle delay of SUSPEND DEL)
thereby
preventing
data
from the unsolicited CMI operation from
being
clocked
1into
the destination registers.
1In time period 9
the

run

mode

resumed

microword

X+2.

5.11.2.5

Differences

with

Between

all

clocks

Stall

Mode

operational

and

Suspend

execute

Mode

The

major
difference
between
the stall mode and the suspend mode is
that
1n
the stall mode, destination registers are inhibited from
loading
wuntil the final cycle of the stall condition.
Whereas in
the
suspend
mode, destination registers are enabled in the first
suspend

cycle

suspend

cycles.

microword

and

inhibited

the

from loading throughout the remaining
necessary
to complete execution of the

first

cycle

the

suspend

mode

(as

opposed

deferring
it
until
the
final cycle as is the case in
mode).
The reason for this is that some microword logic
are

used

unsolicited
longer

Note

contain

1in

the

out

contrast

unsolicited

function

Figure

stretched

period

service

CMI

1is

original

5-21A
over

microword

that

four

Figure

5-21B

There

functions.

CLK

where

these

the

time

registers

will

contents.

microword

CMI

completed,

X+1

microword

1is

time

stalled

periods.

X+1

execution

completed

the

being

This

time

operates. Microword
the
completion of

5.12

CONTROL

INTERRUPT,

5-22

power

control

The

1is

INITIALIZE,

block

AND

diagram of

POWER

the

interrupt,

logic

asserts

interrupt

INTR

the

host

CPU
CPU.

the

1.
2.

SET

MIF

SET

(maintenance

PDN

CPU
PE

when

INTR

interrupt

(power-down)

cabinet

initialize,

CCI

Interrupts

by:

from

port

the

CIPA

parity

port

during

flag)
a

power

microword

has

which
are

port

failure

cabinet

error

occurred

X+2
the

FUNCTIONS

functions,

1interrupt

generates

periods while the unsolicited CMI function
executes
in
the
time
period
following
unsolicited CMI function (time period 9),

Figure

the stall
registers

and

turn

generated

power-up
in

the

host

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Interrupts
caused
(maintenance error)
the

uninitialized

by
port
failures
(PE or SET PDN) assert MTE
to the initialize logic to place the port into

state.

The
initialize
logic
1is
divided between the CCI and the DP.
A
port
initialize
command may be issued by the host CPU to the CCI
initialize
1logic.
The CCI initialize logic responds by asserting
INIT
to the CCI logic and MIN (maintenance initialize) to the DP.
INIT
clears
the CCI logic to its reset state.
MIN is applied to
the
DP
1initialize
1logic
as
MIN
INIT.
MIN INIT causes the DP
initialize
1logic
to output INIT to clear the DP logic, and LOGIC
CLR
to
clear the PB logic.
The DP initialize logic also asserts
UNINIT to place the port into the uninitialized state.

During

reset

port

the

uninitialized
port

into

the

power-up,
and CCI
state.

DCLO

asserts

to the initialize logic to
into the

logic circuits and place the port

MTE

from the

uninitialized

state

interrupt

but

does

logic

not

also places

reset

the

DP.

The
power control logic functions to initialize the port during a
power-up,
and
generate
an interrupt as the power-up sequence 1is
completed.
During
power-up,
DCLO
in
the
DP
asserts
to the
initialize
1logic to initialize the CCI.
As the power-up sequence
completes,
the
power
control
1logic
asserts
SET
MIF
to
the
interrupt logic where it generates an interrupt to the host CPU.

The

power

control

1logic

also functions

to perform a power fail

sequence
when a power failure occurs.
During port operation, the
power
control
1logic monitors ac and dc power in the CIPA cabinet
and in the host CPU cabinet.
TIf power fails in either cabinet, an
ACLO
signal
1is asserted to the power control logic which asserts
PWR
FAIL to the microcode branching logic.
If the port is in the
initialized state (UNINIT false), the microcode suspends operation
at
a
1logical break point and returns UP PDN to the power control
logic.
UP
PDN
causes the power control logic to assert SET PDN
indicating
that the port is powering down.
If the port is in the
uninitialized
state
(UNINIT true), PWR FAIL directly asserts SET
PDN
via
the
power
control
hardware.
SET PDN is inverted and
transferred
to the CCI as a negated CIPA UP.
The negated CIPA UP
is
applied
to
the
configuration register where it sets bits NO
CIPA
and PDN, and resets the PUP bit.
SET PDN 1is also applied to
the interrupt logic where it causes an interrupt to the host CPU.

When

assertion
NO
CIPA
interrupt

power

resumes,

SET

PDN negates

and

CIPA UP

asserts.

of CIPA UP causes the PUP bit to assert, and the PDN
bits
to negate. In addition, SET MIF is asserted to
logic to generate an interrupt to the host CPU,

The
and
the

Interrupt Function
5.12.1
Figure
5-23
1illustrates
the
flow
diagram of the interrupt
the following discussion.
An

interrupt
1.
2.
3.
4,

The

the

host

interrupt
sequence.

CPU can

logic.
Figure 5-24 is a
Refer to them throughout

initiated

by:

a port power failure (SET PDN)
a port parity error (PE)
the port microcode (INTR)
the port powering up (SET MIF)

assertion

of SET PDN causes SET MTE to assert until

the next

DP CLK T3 A clock pulse (the next DP CLK T3 A pulse resets the SET
MIE
flip-flop negating SET MTE).
The assertion of SET MTE causes
MTE
to
assert.
The
assertion of PE also causes MIE to assert.
MTE
is
applied
to the initialization logic where it asserts SET
UNINIT
thereby
causing the port to enter the uninitialized state
(Paragraph

MIE

5.12.2.2).

is a bit

in the PSR register

(Paragraph 5.5.3).

MTE is also applied to an AND gate where the maintenance interrupt
flag (MIF) is sampled,
TIf MIF is true, another interrupt is being
serviced
and
the
AND
gate is disabled.
The interrupt seqguence
must

completed

generate
resulting
pulse and

The
assertion
output
is
fed
results

the

logic

and

MIF

negated

an
interrupt.
If MIF
in flip-flop E32 being
asserting E32-2,

the

before

the

current

error

can

is false, the AND gate is enabled
set on the next DP CLK T3 A clock

of
E32-2
sets
back to the E32
negation

resets

itself

another
flip-flop whose inverted
input.
The negative feedback path
of E32 after two DP CLK T3 A pulses.
Thus
in preparation for another interrupt.

E32-2
1is
ORed with INTR from the CS microword.
The assertion c¢f
either
E32-2
or
INTR
sets
a
MIF flip-flop on the next CLK T2
pulse,
causing
MIF to assert. MIF, 1n turn, asserts INTR CPU due
to
the
true state of MIE.
(MIE is asserted on power-up by DCLO;
see
Paragraph
5.12.3.1.
It
1s
negated
only
for maintenance
testing of the interrupt logic.)
During
SET MIF
MIF

a system power-up, MIF
from the power control
a

bit

the

is directly
logic.

PMCSR register,

set

the

assertion of

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5=26)

(oone

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)

5-24

Interrupt

enters

uninitialized

—
IR

Sequence

Microcode
running.

INTR
the

CPU

CCI

where

transferred over the CIPA bus (as CIPA PORT INT) to
it

asserts

PORT

INT to the CCI issue interrupt

initiates a write vector
write vector function is
the
When
CPU.
host
function to the
by asserting PSRCR
flip-flop
MIF
the
resets
complete, the host CPU
The

logic.

1issue

interrupt

1logic

The host CPU then
via an unsolicited CMI write sequence.
as described 1in
command
MIN
a
initializes the port by issuing
Paragraph

5.12.2.

5.12.2

Initialize Function

The initialize function is divided between the CCI module and the
DP module. Both the CCI and the DP have initialize logic which are
described in Paragraphs 5.12.2.1 and 5.12.2.2.

Figure

5-25

illustrates

the initialize logic.

flow diagram of the initialize sequence.

the

Figure 5-26 is a

Refer to them throughout

following discussion.

-- The CI750 port <can be
Logic
Initialize
5.12.2.1 CCI
e (MIN) command from the
initializ
ce
maintenan
a
initialized by
host

CPU.

Wwhen the CCI decode logic senses an initialize command, it asserts
When the MIN
it to set.
SET MIN to a MIN flip-flop causing
causing
logic
initialize
CCI
the
to
MIN
flip-flop sets, it asserts
INIT A, INIT Al, and INIT A2 to assert. INIT A, INIT Al, and INIT
the error bits in the CNFGR register and
to <clear
function
A2
for the FPLA logic array
except
circuits
logic
CCI
reset the
circuitry.

MIN

also

applied to the CIPA bus as CIPA MIN and then to the

DP.

The

output of the MIN flip-flop enables a four-bit binary counter

After five B CLK cycles, the counter output
by B CLK.
clocked
goes true and resets the MIN flip-flop negating MIN.

During power-up the CCI initialize logic receives DCLO
As DCLO and SYNC
1logic.
control
power
the
from
DCLO
power control signals, the response of the CCI initialize
of the
description
the
in
covered
1is
signals
these
Sequence

5.12.2.2

via

the

and SYNC
DCLO are
logic to
Power-Up

(Paragraph 5.12.3.1).

DP Initialize Logic -- CIPA MIN is received from the CCI

CIPA

bus,

and

becomes

MIN INIT in the DP.,

MIN INIT

asserts MIN which in turn resets the MIE and MIF bits in the PMCSR
In addition, MIN sets an INIT flip-flop causing INIT to
register.
assert.

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£ INIT A2

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o
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Clears error bits in CNFGR register,
logic

CCI

except

FPLA

logic

array.

|
|

Resets

[;-EIPA nrfl'
f MIN INIT

[

Clears

Enables interrupts.

MIE

PMCSR

and MIF
register.

bits

Resets CCl/DP

[’ LOGIC CLR]

Interface _Control

Logic to idle
steate,

[f SET UNINIT]
Y

} UNINIT
Port

enters

Microcode

uninitialized

stops

state.

running,

Y
BTO
or

PICR

WRT

[¥ uNrwit|
Y
(

Figure

Donej

5-26

Initialize

[Clears DP errorle

Sequence

—'

The

assertion

Clears

Asserts

INIT
DP

accomplishes

CLR

Resets

the

CCI/DP

the

into

the

Asserts

Resets

the

(Paragraph
6.
The

Resets

assertion

UNINIT

and

UNINIT

and

third

system

System
before

The
PICR

the

sets

SET

the

can

start

5.12.2.3

wused

the
delay

The
load

port

UNINIT

placed

INIT

DCLO

reset
the

into

the

when

1in

the

has

CPU

assertion

UNINIT

placing

into

SET

flip-flop

the

UNINIT

into

and

delay
1is
wused
the microcode.

uninitialized

power-up,

causing

DCLO

INIT

MTE
SET

state.

and

state

asserts

SET

that +5 V be up and

CMI

by
and

UNINIT

operational

performs

before

in the uninitialized state
BTO from the boot timer or

request

logic.

unsolicited

(PICR).

assertion

CMI

Thus
BTO

write

the

host

(before

the

expired).
Maintenance

the

allow

1500

Timer

The

microcode

state.

Boot

wuninitialized
be

the

asserting

state.
assertion of
also asserts

uninitialized

system

control

starting

the
can

port

uninitialized

holds
the port
the assertion of

microcode

Timer

the

requires

unsolicited

delay

thereby

assert,

period

Boot

which

the

flip-flop

initialization

place

via

sets

into

During

flip-flop

1is

up
timeout

boot

Logic

timer

port

protocol

and

asserts

WRT

port

power
ACLO

from

PICR

timer

port

the

WRT

the

module

state

UNINIT

the

power-up.

Control

5.12.2.3)

places

UNINIT

until

the

state
boot

assert.*

functions:

flow diagram of Figure 5-26 that the
error)
from
the
interrupt
1logic

way

directly

initialize

Interface

maintenance

placing

Note
1in the
(maintenance

idle

SET

uninitialized
5.

following

errors

LOGIC

the

seconds

time

for

the

boot

timer

temporarily

logic

holding

jumpers select the
100-second increments.

cluster

boot

and

one second oscillator outputs into a decade counter
timer
A boot
The decade counter divides by 100
at a one cycle per second rate.
A
once every 100 seconds.
counter
binary
into a
outputs
and
set
count
the binary counter output with the
compares
comparator
When the output from the binary counter
boot jumpers.
four
into
count set into the boot jumpers (A=B), the BTO (boot
the
matches
and asserts BTO to the UNINIT flip-flop
sets
flip-flop
timeout)
via
an
OR
gate.
BTO
<causes
the UNINIT flip-flop to reset and
The negation of UNINIT takes the port out of the
UNINIT.
negate
uninitialized state and starts the microcode running.

the
clears
UNINIT
SET
Hence
reset.
flip-flop

holds the BTO
and
counter
BTO decade
the BTO counter is not enabled until the

condition causing SET UNINIT to be true,

is cleared.

signals that clear the BTO flip-flop and decade counter are
Other
MTD (maintenance timer disable) from the PMCSR register, and PMTCR
CLR
from
the
wunsolicited
CMI
request
logic.
The BTO timeout
period
can
be extended by clearing the boot timer with PMTCR CLR
via

unsolicited

CMI

write

sequence.

outputs a TICK
oscillator
microsecond
400
timer
A maintenance
signal
to
the
CCS
branching logic every 400 microseconds.
TICK
forms a

time base

used

by the port microcode.

Power Control Function
5.12.3
The
power
control
function
causes the CIPA cabinet and the CCI
module
1in
the
host
CPU
cabinet
to
be
1initialized on system
power—-up,
and
shuts
down
the CI750 when a power failure occurs
within
the
CIPA
or
the
host
CPU
cabinet.,
It also generates
interrupts
to
the
interrupt logic for both system power-ups and
power

failures.

Figure 5-27
5-29
show

Refer

illustrates the power control logic.
Figures 5-28 and
the
power-up
and
power fail sequences respectively.

to Figure

5-27

throughout

Section

5.12.3.

Power
system
protocol
requires
that
a power failure cause the
assertion
of ACLO followed by the assertion of DCLO (Figure 1-5).
During power-up the reverse is true, that i1s DCLO negates and then
ACLO negates.

5.12.3.1
Power—-up Sequence
-- When system power 1s applied, both
the
CCI
in
the
host CPU cabinet and the DP in the CIPA cabinet
undergo
a
power-up
sequence.
Both sequences are illustrated 1in
Figure
5-28.
The
power-up
sequence in the host CPU cabinet is
considered

first.

—_--————

————————

—_————-—

_—.

I ACLO

AClO

Gra

ple

ASSER

T
_DCLO

e
{
T

DcLo

5;;5{
;

(Fie 6-34)

I _ACLO . p
Liptc

(FIG.

)

’(/sb),

SYNC
pero L)

DCLD

cto,lp

T ACLO

sync | Elba

(7)

I—

Dlé?.g

LKl

—{(1p))-AC

-25

STNC

45 (FIG.

CIPA,

‘-{bl CIPA
|_DCLOQ

YNC|

Lo
|

v—

o}—

Elb2

FF
(3)cn—]

(3)

3)
(3)

_____4;_______________'

cleB

CIPA

(FIG. 5-3;5-25)

SLK

(FlG

(FIG. 5-25)

)

J@Mrfi&k—»—(m&, 4-1¢)
|

UNINIT

|[, B
B cix
c
'

—b2 ACLO

SET
up

ClLk T1

UNINIT _ (FiG. 5-25)

—>— I CPU ACLO : |
|

E VLD

cf—(w

clPA

(N cleB Cbk

(W)

_-.@
Fig\ | ¥

DCLO

vV v

—Jue)—

UBS

fiJ>O___J

(1)

_____ a

;
INIT 5%A

3
)
5-25

(44;

(Fi16. 1-5)

@—EQ&—-DO—}_

T beio 0y

BFD

UNINIT

_53
(FIG. §-23 )e—ro

L
|

(4- :2_)

T_MIF

7ol

}(F\G)

cleLWORD
LUK [)

P DN
(pG.
__
4-2)

—

BUF CMI D 22

)
M

—

: (Fi6. 5723)

(M) c|< 2P cik T3 A
CLR

B ctk

o (9

|
‘l

i ()

(FlG. (-3 4)

—————_

_————-

————.—

__—-—-

—

|
:

|
|

N ote:
Letter designations in parentheses

refer to engineering drawings
containing corresponding logic.

Figure

5-27

Power

Control

Logic

SED

aEd

‘

(seare
)
’

[_EEE power on.]

GEND

aED

SEED

eEn

--—.

CCL)
=

4 ps aclo

$ ves acco

8
u8s

1 PS

oCLO

[

[f ocuo%]

$ 117 1}

RUHTES

[fALIPA ocza]

4 INIT A2

£ INIT AY

¥ ues ocLo

|
8

CLK

INIT ci
¢¥ INIT

INIT

’

y uBs acLO

e
f

'
|
L

[ n CIPA’ ocuo]

[& SYNC DCLO]
Y

8 CLK

——

Li_cun pup/pE;-]

v INIT A
Y
T

I
|

(from

CCID)

Port

enters

state

uninitialized

(Fiqure

5-26).

[

[* SET PON ]

Y
y

Sequence

CPU

PICR

|
I
I

hos:

S5-24).

[iUNINIT ]

[
CLK

WRT

{nterrupt

(FPlqgure

$ ser mrF
Generasces

L_ CIFA CIPA UP

8TO

[* SET mrrJ

I
/
y

[} SET pufl

CCI

|
|
|

Done

l y CIPA Ccpu ACLO]

inftiallzed.

| [f LOGIC CLR}

p—

|
l

A unpurr

PS DCLO (in CIPA)

CIPA

)

¥ CIPA cpu ACLO

;

$ vt

Lf SET UNINI;]

4 mie

enabled,

$ S ACLO

oCLO

tim éer

¥ Ps DCLO

BTO0

$INIT A

$ ser v NINIT

[t SYNC ocuo]

l
|

[f CLR PUF/PSZ]

DCLU

Y
Lf CIPA DCLO l

({in

I CLP power o;?i]

[

PS ACLO (in CIPA)

Figure

5-28

Power-up

Sequence

The
power-up
sequence
in
the
host
CPU cabinet resets the CCI
hardware
registers
and logic circuits.
When power is applied to
the CCI, the +5 V becomes operational after which UBS ACLO and UBS
DCLO come true.*
UBS ACLO is obtained from terminal C45 while UBS
DCLO
1is
obtained from terminal C93.
UBS DCLO asserts DCLO which
in
turn
resets
the
INIT
flip-flop in the CCI initialize logic
(Figure
5-25)
thereby
asserting
INIT.
The
assertion of INIT
causes INIT Cl, INIT C2, INIT C3, and CLR PUP/PDN to assert.
When

CLR
PUP/PDN comes true, it causes INIT A, INIT Al, and INIT A2 to
assert,
DCLO
also
asserts
CIPA DCLO causing SYNC DCLO to come
true on the next DELAYED B CLK pulse.
SYNC DCLO is applied to the
INIT flip-flop which is presently being held reset by DCLO.

* System

power

before

ACLO

protocol requires that +5 V be up and operational

and

DCLO

assert,

when UBS DCLO negates in
The
negation
of
DCLO
flip-flop
conditioning
DCLO
true).
The next B
negating

INIT,

INIT

Cl,

the power-up sequence, DCLO also negates.
removes
the
<clear
signal from the INIT
both halves of the flip-flop to set (SYNC
CLK pulse sets the INIT flip-flop thereby
INIT

C2,

and

INIT

C3.

The
negation of DCLO also causes CIPA DCLO to negate when the the
corresponding signal in the CIPA cabinet (PS DCLO) negates.*
When
this
occurs, SYNC
CLK
pulse
resets
negating

DCLO negates.
With SYNC DCLO false, the next B
the
1lower
half of the INIT flip-flop thereby

CLR PUP/PDN,

INIT

INIT Al,

and

INIT A2.

* The purpose of interactive DCLO signals between the CIPA and the
CPU cabinet will be seen in the power fail sequence described in
Paragraph

UBS

ACLO

negation

5.12.3.2,.

and

ACLO

of ACLO

negate

negates

The
and

power-up sequence
1logic
circuits.

ACLO

becomes
from
sets

operational
1is

obtained

terminal
the
MIE

thereby

* System
before

B5.
bit

enabling

In
addition,
asserts
INIT
asserts
SET
uninitialized
initializes

the

after

the CCI
the

power—-up.

DCLO

is obtained

PS DCLO asserts CIPA DCLO and then DCLO.
(maintenance
interrupt
enable) in the

DCLO

The

CIPA bus.

which PS ACLO and PS DCLO come true.*

from terminal B10 while

protocol

and

complete

the CIPA cabinet resets the CIPA hardware
When
power is applied to the DP, the +5 V

interrupts

power
ACLO

CIPA CPU ACLO on

the

host

DCLO
PMCSR

CPU.

requires that +5 V be up and operational

assert.,

DCLO is applied to the DP initialize logic where it
and
LOGIC
CLR.
INIT initializes the DP logic and
UNINIT
and
UNINIT
placing
the
port
1into
the
state
(see
Paragraph
5.12.2.2).
LOGIC
CLR
PB

module.

As
the
sequence
proceeds,
PS
DCLO
corresponding
signal
in the CPU cabinet

negates
and
when
(DCLO)
goes
false,

will

CLK

negate.

the

INIT

With

DCLO

flip-flop

false,

(Figure

negate.
The negation of
then begins counting down
The

CPU

ACLO

step

cabinet

from

causes

PWR

The

negation

CLK

MIF
the

flip-flop
interrupt

CPU

(Paragraph

The

negation

CIPA
CIPA

and

SET

When the
the host
UNINIT

negation

PDN

then

SET

MIF

CLK

(indicating

reset

UNINIT

timer

which

ACLO.

CIPA

that

the

host

CPU

the

negation

negate.

assert

T3
A

until

pulse

also

assert.

asserting

AND gate
the R2
R3

boot

causes

CIPA

UP to assert
CIPA bit
in

the

resets

the

SET

that
input

output

asserted,

SET

the

CIPA

PUP

directly

bit

generates SET
to flip-flop

E162.

forming

Thus

200

and

the

port

the

1leaves

sets

the

of
to

PUP

configuration

PUP receives two 1input
E162; the other is the

SET

the

PUP

negated

one

pulse.

timer startup delay has timed out
PICR WRT via an unsolicited CMI

negates

assert

in the CCI.
The true state
the
configuration
register

(BTO

asserts

(Paragraph

will

SET

SET MIF).
The SET MIF pulse is applied to
generate an interrupt sequence to
the host

the

SET

causes

PDN

PUP

The

after

pulse

and

5.12.1).

One

inverse

INIT

initialized),

(the

negating
logic to

thereby

false

then

PDN

pulse

SET

flip-flop

Note

SET

clock

signals.

1is

and

bus and then CIPA
UP causes
the NO

reset

CLK

FAIL

causing

SET UNINIT enables the BTO
the boot time-out period.

sequence
CCI

piwered-up

ACLO

the

5-25)

the
DCLO

the

write

asserts)
or
operation,

uninitialized

state

5.12.2.2).

PDN)
Only

1in Figure 5-28 that the negation of PWR FAIL
(and then SET
1indicates the completion of a successful power-up sequence.
then
is the PUP bit
set and
the CPU interrupted.
For PWR

FAIL

negate,

completed
CPU

ACLO

good
from

the

5.12.3.2
Power
failure
occurs
terminal

Bl@

asserted

failure
CCI.

both

CPU

the

power

and

failure

the

CPU

cabinet

ACLO

false

thereby

cabinet

indicated

cabinet

With

asserts

CPU

and

ACLO

and

the

false

the

causing

asserts
within

PWR FAIL.
the host CPU

CIPA

must

have

state

CIPA

When
comes

a
power
true
on

PWR FAIL
cabinet.

is also
A power

DP.

Fail
Sequence
(Figure
5-29)
-within
the CIPA
cabinet,
PS
ACLO

in
a

the

power-ups

asserts UBS ACLO on terminal C45 in the
(discussed
in
Paragraph
5.12.3.3),
ACLO

CIPA

CPU

ACLO

assert

the

CIPA

bus.

lPo-er tajlure in ClPA caoinet.l

|
~

>
(@]
|
(@]

[=4
©

[7]

—'

[f PS Acuov1

|
|

[f CIPA CPU ACLU ]

[f PWR FAIL ]

YES

UNINIT
NO

[ Microcode brancnes to power tatl routine.]

[

[ Powser fail routine saves current information. ]
Y

{4 ve pon |

[

\A
SET PCN ]

[f SET nTeJ

-y

o
>

I*CIPA CIPA UF ]

$ mre
Generates

Places

[

:
'|

$ sywuc ocz.o]
[f CLR PUP/PD;]

into

foc%'

ILCIPA DCLO

A INIT A2

CCL reset to the

INIT

vninftialized

cabpinet

not

functional,

tplocnce to he

E‘

’ INIT'

state,

* pcLe

CPU

C175@

resumes

state

Operation.

: CCL

&5“

PJ]

functioral.

* PuP

CIPA power not

}

CLK

-1

|4 ser unwrfl

\ .

|
out

CCI :

uninitialized

takes

TED G| D EID D e G G euEy e =

| &C“’* J]

)
Host

IX IPA CIPA a

Generates interrupt
sequence to host CPU

4 c1pa bcLu
j

:
|

§S=26).

Power in CPU

5-24),

(Fig.

SET MIF

’ PS DCLO

1:;;:1' A

(Fig.

state

CPU

host

uninitialized

—l

fues DCLO

interrupt

oort

SET PuP l

’
CIPA

resets té the
uninitialized stacte,

[

§ ser omrr

LOGIC CER]
-

(ibong;:)

Figure

5-29

Power-Fail

Sequence

(Sheet

PWR FAIL is applied to the microcode branching logic.
If the port
is
not in the uninitialized state (UNINIT false) the microcode 1s
running.
PWR FAIL causes the microcode to branch to a power fail
routine.
The
power
fail
routine
functions
to
save
current
information
so
that operation may be resumed when power returns.

The

power

resulting

FAIL

fail

routine

the

returns

assertion of

SET

UP PDN to the power fail

logic

PDN,

port is in the uninitialized state (UNINIT true) when PWR
the
asserts,
SET
PDN
1is
asserted
by
the hardware - not the

microcode,
assertion of

Referring
to
Figure
5-27,
PWR FAIL directly asserts SET

with
PDN.

UNINIT

true,

the

SET PDN is inverted and placed onto the CIPA bus as a negated CIPA
CIPA UP signal.
The false state of CIPA CIPA UP causes CIPA UP 1in
the

CCI

two

flip-flops

assert.,
the PUP

The

negation

<causing

SET PDN sets the
flip-flop negating

SET
PDN
flip-flop
PDN.

negate.

PUP,

Back

SET

and

the

PDN

logic

1is

NO CIPA are

DP,

SET

<coupled

(Paragraph

microcode

CIPA UUP

negate

and

PDN flip-flop
PUP.

formed

PDN

and

from

into

bits

asserts
SET MTE and then
CPU (Paragraph 5.12.1).

MIE

transferred

CIPA

asserting

through

and

SET

PDN

PDN,

and

resets

1is
asserted
by
ANDing
NO
CIPA
and the R3 output of
El162.
The next B CLK resets E162 thereby negating SET

Thus

PDN,

a genuine power

the

200

the

CCI

the

applied
MTE

interrupt

port

into

where

interruption

the

pulse.

configuration

interrupt

to generate

the

5.12.2.2)

place

logic where

interrupt

logic to the
asserts

is occurring,

the

host

initialization

UNINIT

uninitialized

stop

the

state.

PWR FAIL will

still

be true and, if this is a CIPA power failure, PS DCLO will assert,.
When
PS
DCLO comes true it asserts CIPA DCLO.
CIPA DCLO asserts
DCLO
indicating
that
power
in
the
CIPA
<cabinet 1is no longer
functional.

CIPA
DCLO
1is
also
transferred to the CCI where 1t asserts SYNC
DCLO, CLR PUP/PDN, and the "A" set of initialization signals (INIT
A,
INIT
Al,
INIT
A2).
CLR
PUP/PDN
and
the
"A"
set
of
initialization signals clears the error bits in the CNFGR register
and resets the CCI logic (except the FPLA logic array circuitry).
If

the

power

asserted.

indicates

failure occurred

UBS

DCLO

that power

turn

the CPU cabinet,

asserts

DCLO

the CPU cabinet

and

CIPA

UBS

DCLO will

DCLO.

longer

CIPA

DCLO

functional.

CIPA

DCLO

UNINIT,

also

transferred

UNINIT,

uninitialized

and

state.

interactive

between

one

cabinet

will

only

a
PS

DCLO

causes

SET

PDN

The

negation

causing

the

SET
to

through

assertion

the

PUP

SET

PUP

output

negating

and

dip

the

DCLO

the

occurred,

CIPA
The

flip-flops

CIPA

and

asserts

asserting

PUP,

ANDing

the

flip-flop

E162.

The

SET

formed

asserted

SET

PUP.

negation

Thus
SET

PDN

CLK

the

SET

MIF

flip-flop

the

interrupt

CPU

Just

the

(via

SEP

the
of

(the

SET

CIPA
CIPA

SET
PDN

and

the

inverse

CLK

sets

MIF

a
to

pul se.

assert

until

pulse

normal

taking

the

during

unsolicited

Figure

5-30

illustrates

with

respect

power

failure),

port

into

SET

the

CMI

CI750

write

when

out

sequence

interrupt

SET

MTE

asserts

PDN.

the

uninitialized

)

and

resuming

signals

SET

MTE

uninitialized

sequence

When
to

SET

generate

state.

completes),

SET

interrupt.

normal

interrupt

and

place

SET

fail

wvalid)

flip-flop

microcode

(Figure

set

flip-£flop.

Setting

CIPA

the

where

CCI

ACLO.

ACLO

GSYNC

and

ACLO

the
on

FAIL
the
CIPA

DELAYED

asserts

ANDed

asserts

bus.

via

the

inverse

with

disable)

and
the
inverse
of
PDN.
(discussed
1later),
the
AND
gate

asserted

ACLO

the

terminal

functions

host

system.

C45

and

initiate

then

When

a
an

the

CI750

VLD

(power

PFD

enabled
to

the

fail
the

turn

coupled

E164.

PFD

and

power-down

a
set

produce

and
CPU

which

ACLO

flip-flop

out

simulated

clock

E62-5
T

CLK

ACLO

to
PF

and

conditions

Tl1

CIPA

(as

generate

packet
FAIL

gates

flip-flop

the

ASSERT

negates

maintenance
mode
the
by means
of
a
reset

ASSERT

VLD

synced

then

are

assert

5-27).

while

asserts

PDN

asserts

Remote
Reset
Function -In
the
port
can
be
reset
from
another
node
packet.
The
remote
node
sends
the
reset
port

MIF

(due

5.12.3.3

the

SET

asserts

When

MIF

and

PDN

CI750

causing

the

resets

negating

where

occur

power-up

the

thereby

operation.

the

The

sets

flip-flop

E162

20@

CLK

bus

PUP

the

into

assert.

PUP.

resets

input

causes

pulse

being

SET MIF).
SET MIF 1is applied
to
generates
an
interrupt
to
the
host
power-up sequence.
The CPU responds

logic

also

clock

interrupt

PUP

the

signal

assertion

causing

and

SET

PWR FAIL may hegate
negation of
PWR FAIL

the

CIPA

CCI.

INIT,

CIPA

the CIPA, a power loss
in the other cabinet.

case,

asserts

assert

the

module(s)

this

two

state

cabinet

reset

PDN.

The

port

PDN

negates

flip-flop

negating

where

due

power

assert

transferred

DP
to

negate.

CIPA

CPU
the

asserts.
to

the

CLR

Thus,

reset

transient

before

.OGIC

SYNC

(power

fail

are

false

PDN

UBUS

ACLO

cabinet.

UBUS

sequence

within

l3s AW 4Sanby0¢=-S 1ed=a8M0d puydn-1amod adniajulsTeubrs
———

.
e
ce——
-

— — ———

]

5-88

The

microcode

results
of

SYNC

C93.

power-down

asscrts ASSERT

assertion

DCLO

The

Note

then

the

and

that

the

PF VLD which

similarly

DCLO

and

assertion

causes

UBUS

DCLO

UBUS

DCLO

within

true

DEAD and

SYNC

DCLO

assertion
sequence

the

state

host

DCLO
from
being
asserted
to
thereby
preventing
the
1logic

the port is still able
simulated powered-down

The

assert

completes

the

terminal

simulated

system.

ACLO

the
from

to function
state.

DCLO.

and

DCLO

inhibit

ACLO

CCI
and DP power down
shutting down the port.

while

the

host

system

and

logic
Thus

the

The
microcode
then
asserts
PF
VLD
with
ASSERT
DEAD negated
resulting
1in the resetting of the dead flip-flop and the negation
of
SYNC
T DCLO, T DCLO and UBUS DCLO in the CCI.
With UBUS DCLO
false, the host system attains a partial powered-up state,
When

SYNC

pulse

DCLO

resets

negated

before

possibly

negates,

flip-flop
T

DCLO

causing

DCLO

i1s

E164.

goes

false

spurious

held

This

true

until

insures

thereby

assertion

the

that

preventing

DCLO

UBUS
UBUS

the

DCLO
DCLO

CCI

CLK
has
from

and

the

DP.

The

host

still
packet

ACLO,

ACLO

and

one

delay

ACLO

the

prevents

the

remote

port

microcode

resetting

UBUS
B

partial

port

ACLO
CLK

possible

the

UBS

ACLO

simulated
ACLO

the

When

false,

power-

and

the

fail

DCLO

PFD

are

bit

the

start

assert

the

host

sequence
bits

1in

the

state

packet.,

VLD with

flip-flop

and

(UBS

ACLO

The

start

ASSERT

negating

FAIL

SYNC

negation

SYNC

ACLO

and

ACLO

assertion

the

CCI

and

system

now powered-up

and

the

DCLO.

This

allows

maintenance

ASSERT

FAIL

true

inhibited

from asserting

the

UBUS

power-fail

the

ACLO

DCLO

UBS DCLO.
(PDN true), inputs from the
the port power-up sequence.

Thus,
ACLO

state

PDN

UBS

DEAD

bits

also

inhibits

ACLO

without

and

test

true,

ACLO and
a

CPU,

UBUS

activating

ASSERT

host

diagnostics

microword

and

powered
down
do not disrupt

configuration

the

asserting

CCI

configuration

1logic

sequence

completed.

the

DCLO

from

CCI.

spurious

ACLO/T

The

to
fail

between

powered-up

sends

DP,

With

the

thereby

remains

until

causes

negated

system

true)

and

logic

when the port is
and T DCLO logic

CHAPTER
CCI

MODULE

NOTE

The functional block diagrams in Chapter
6 use
logical
AND
and OR symbols.
It
a
that
follow
necessarily
not
does
the
on
exists
gate
corresponding

The assertion
engineering logic prints.
inputs A and B causing the assertion
of
represented on a
be
may
C
output
of
block
diagram by a single AND gate, yet
may show that
drawing
engineering
the
involved 1in
are
stages
circuit
several
the ANDing operation.

diagrams in this chapter are
block
The
circuit
engineering
the
to
keyed
letter
by
prints)
(CS
schematics
letters
The
designation in parentheses.
CS sheet that contains the
the
specify
logic
associated
with
the
functional
blocks

The

the diagram.

signal names used

in the

functional

block diagrams are the names used on the
engineering
CS
prints.
Where
other
signal names or notes are used, they are
enclosed in parentheses.

6.1

Overview

The CMI CIPA interface
the
CMI
(CPU
memory
CI750.
The
module
interfacing
with
the
signal
formats
when

(CCI) module serves as an interface between
interconnect) bus and the port logic of the
follows
CMI
protocol
and
timing
while
CMI
bus,
and responds to port timing and

interfacing

with

the DP module

the CIPA

cabinet.

The
overview
begins
with
a description of the CMI bus, CMI bus
signals,
and
CMI bus timing.
The overview then provides a block
diagram
of
the
CCI
with
a
brief description of the CCI major

components
and their functions.
Lastly, simplified flow diagrams
are
used to illustrate functioning of the major components during
port initiated data transfers and unsolicited CMI transfers.?*
*

An unsolicited CMI transfer is a transfer wherein
slave (transfer not initiated by CI750).

the CI750

addition

serving

overview

CCI

operation,

the

simplified
flow
diagrams
are
related to flow diagrams found in
other sections of Chapter 6. These sections expand on each area of
the
overview flows with more detailed diagrams and text as to how
each of the areas performs its function. Consequently the overview
flows
are
used, along with the CCI block diagram, throughout the
rest

the

6.1.1

The
The

chapter.

CMI

CMI
bus

1is
1is

Protocol

45 line synchronous, interlocked communication bus.
1interlocked
1in
that
when
a
master and slave are
communicating, the bus is locked out to other nexus.

The
CI750
(including

port
1is a master
interrupts).
It

for
1s

all
a

port initiated bus transfers
slave
for
all
unsolicited

transfers.

6.1.1.1
Figure

Bus
6-1

and

Signals

described

Table
No.

The

Table

6-1

CMI

bus

1lines

are

illustrated

6-1.

Bus

Signals

ILines

Name

Mnemonic

Data/Address

CMI

DATA

Function
<31:00>

Thirty

two multiplexed

lines

that

bytes

32-bit

carry

data

four
a

command/address

longword.
the

the

The format
longword and
command/address

data

longword is illustrated
in Figure 6-2.
1

Busy

CMI

DBBZ

Indicates

that

the

CMI

is busy doing a
master/slave transfer.
1

Hold

CMI

HOLD

The
to

CPU

asserts

perform

high

transaction
nexus.

all

CMI

HOLD

priority

with

HOLD

other

obtaining

inhibits
nexus from

the

CMI

bus.

Table 6-1
No.

CMI

Bus

Signals

(Cont)

Lines

Name

Mnemonic

Function

Wait

CMI

CMI WAIT is asserted by
a nexus that is issuing

WAIT

an interrupt to the CPU.
WAIT informs the CPU
that an interrupt
transaction is about to
occur.,

Arbitration

CMI ARB <7:1>

Arbitration
bus

follows

for the CMI

distributive priority
scheme.
Each nexus
(except the CPU) 1is
assigned a priority ARB
line (ARB 7 = highest
priority).
Among
arbitrating nexus, the
one with the highest
arbitration priority
will

obtain the bus.
Each nexus monitors all
higher priority ARB
lines.
If a higher
priority nexus 1is not
arbitrating for the CMI
bus, and the bus is free

(CMI

DBBZ

and CMI

HOLD

false), a nexus can
obtain the bus.
The CPU
1s not assigned a CMI
ARB line and thus
becomes

the

lowest

priority

nexus

CMI

0).

(ARB

the

Table
No.

6-1

CMI

Bus

Signals

(Cont)

Lines

Name

Mnemonic

Status

CMI

Function

STATUS

Each

<1:8>

slave

addressed
return

code

the

end
action.

that
by

is
master,

two-bit

the

status

master

the transThe code

indicates the success
failure of the
transaction as shown

below.
CMI

Meaning

STATUS

NXM

(non-

existent
memory)

(This

equivalent

response.,)

UCE

(uncorrect-

able

CRD

error)

(corrected

read

Bus

clock

CMI

CLK

that
CMI

is
a

bit

to the
always

command/address

Also, that address bits <@1:00>
addresses are longword aligned.

longword
valid.

format

zero.,

interest,

the

are
If

byte

error

the

bus

clock

synchronizes
bus

all

activity.

a 6.25 MHz
period

160

Referring

data)

(bus

CLK

clock

with

cycle)

ns.

Figure

note

that

not used because all CMI
only a portion of the data

mask

specifies

which

bytes

are

32 DATA/ADDR.
4

1 WAIT

DATA/ADDRESS

(35 lines)

1 HOLD

1BUSY

3 MBA
1 UBl
1 RDM

ARBITRATION

lines)

2 RESERVED

CI750

NEXUS

PORT

STATUS

lines)

6.25 MHZ B CLOCK (1 line)

Figure

6-1

CMI

Bus

Signals

[

24| 23

BYTE 3

1615

BYTE 2
A,

28 27

—

00|

BYTE 1

Data

~ BYTE O

Format

2524 23

02 0100

¢
~

BYTE MASK

PHYSICAL

FUNCTION

6-2

LONGWORD

ADDRESS

CODE

Figure

08] 07

CMI

Command/Address

Data

and

Format

Command/Address

Formats

The

three-bit

Table

function

code

shown

Table 6-2

Function
Bits
27
26 25
]

Figure

Function

defined

Read

Port Initiated
Operation

Unsolicited
Operation

(CI758

(C1750

CMI

is master)
device

Read

Lock

Same

read

Read With
Modify

off

CI750

"write

"read"

CMI

locked
the

plus

devices
the

CMI

Undefined

Write

1in

slave)
read

CPU.

Treated
"read"

until

executes

unlock"

all

are

as
by

a
the

CI7580.

function.

Cannot be initiated
the CI750.

Treated as a
"read" by the

Intent

CI750
the

other

)

Function Code

' CI750.

]

6-2B

6-2.

CI750.

—_———

————

A CMI device is
by the CI754.

written

The

CI750 1is
by the

written
CPU.

Write
Unlock

Write
Vector

This function follows
"read lock" function.
Same

all

other

are

unlocked

can

access

The CI750
interrupt

"write"

CMI

plus

Treated
"write"

Undefined

a
the

Cl175@.

devices
so

the

they
CMI.

writes
vector

an
to

Not

applicable.

the

CpPU.

as
by

———

6.1.1.2
Write
Timing
-illustrated in Figure 6-3.
The

command/address

the CMI
cycle,

comnand/address
In

the

onto

bus

command/address

lines.

ready

could

take

the

takes

the
the

than

write

data

CMI master.
last
cycle

the

cycle.

status
the

CMI,

The

slave

one

bus

slave

the

transfer

and

write

didn't).

The

transfer

the

write

two

master

two

and

NXM

data

error

Timing

Figure

command/address

the CMI
cycle,

hold

Figure

has

take the
in
only

write
two

the

return

until

the

Figure 6-4,
When

the

negates

the four status
(either
the
slave

states

Timing

not

applicable.

for

CMI

is the first bus
control of the bus.

the
the

the

CMI,

data.

could
is

and

the

master

CMI,

and

The

place

read

transfer

The

place
read

bus

cycle
read

data

than

the

slave

the

transfer

data

and

immediately
and

status

the

1is

one

the

bus

read

data

and

following

transfer

ready

completes

status).
onto

the

In
CMI,

6-8

the

DBBZ

onto

places

the

removes

the

DBBZ,

for

asserts

read

negates

waits

slave

the

take

ready

places

takes

cycle that occurs after
In the command/address

the

slave
to

bus.

cycle.

data

onto

the

CMI,

onto

the

bus

for

DBBZ

the

onto

the

places

the

negation

place

the

read

data

two

bus

only

case
does

bus

seen

designated

this

the

but

hold

and

nexus

status

cycle.,

(command/address
read

the

this

CMI master.
last
cycle

status

cycle,

from

slave

from the
cycles

states are used.
responded
or
1t

are

cycle

ready

DBBZ

bus
this

6-4.

won

bus

read

the

6-3,

data
bus

the
master
nexus
asserts
DBBZ
and
command/address onto the CMI data/address lines.

command/address

the
the

and
1is
designated
as
the
is still on the CMI during

data

ready

only

error"

6.1.1.3
Read
illustrated in

DBBZ

seen

status).
In
this case
the
slave
but does not assert DBBZ.

transfer,

The

lines.

asserts
As

completes

status,

"no

after

take

immediately

and

are

occurs

the command/address
and
places
the

‘

data
a

that

1is

cycle.

write

that

(command/address

These

nexus
data.

cycle.

returns

cycle

transfer

the

Note

bus

write

the write data,
it negates DBBZ,
bus, and places status on the bus for
cycle
following the negation of DBBZ
is

off

The
of

first

CMI
»

master
negates
DBBZ,
removes
and places the write data onto

the

bus

ready

data/address

the
CMI,

take

for

of the bus.
In
asserts
DBBZ

the

slave

the

status

the

CMI

cycle,

until

control
nexus

the

from

data/address

When

cycle

master has won
the
master

Timing

the
not

slave

assert

cycles

DBBZ.

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read

transfer,

all

four

two
data
error
states
refer
transferred to the master,
6.1.1.4

Write
Vector
is illustrated

function

The

the
to

status
the

Timing
-Timing
in Figure 6-5,

command/address cycle

the

first

states

read

for

bus cycle

are

used.

data

that

write

CMI

that occurs

The
being

vector

after

the
interrupting
nexus
(master) has won control of the bus.
1In
the
command/address
cycle
the
master
(CI750) asserts DBBZ and
places
the interrupt vector onto the CMI data/address lines.,
CMI
WAIT
1is
already
true,
having been asserted by the interrupting
nexus when the interrupt was initially generated.
During

the

while

the

interrupt
Note

bus cycle (status cycle), the master negates DBB?Z
(CPU)
returns
status
to
the
master.
1In an
transaction, the CPU always returns a "no error" status.
slave

that

the

command/address

interrupt

and

vector

status

1is

XMIT

during

both

the

in
of

Figure 6-6 and listed
each component.

File

Return

Read

Interrupt

Data

Vector

CNFGR Register
CMI

Mux

Address Decode Logic
Command/Address Hold

1ll.

Address

12.

Function

13.

Receive

14.

RCV

6.1.2.1
register
the DP.
address

Offset

Data

File

Command/Address
Hi
the command

The

bits.

The

low

receives

6.1.2.2
the

CMI

Address Lo Register
Byte Mask Register
| J

O OoOJdOOHhUTLH
WN -

6.1.2
Major Components
The major components of the CCI are shown
below.
This is followed by a description

Command/Address

the

cycles.

contains

Address

order

address

and

two

function

outputs

-from

onto

The
the

bits

the

address
DP.

and

CMDADDR

The

the

six

lower

upper

bus.

eight

receives

bits of
the
register
form
a
counter
that is incremented to change the
address for each transfer without reloading.
The register outputs

onto

the

CMDADDR

bus.

mzp<pm
' -

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n
i
v
y
s
s
n
d
<3740
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Figure

6-5

CMI

Write

Vector Timing

BUF

cecmr

D <L<3i:d¢>

r—-—
- ——
= ==

nT
T T = -1

BUF C‘Ml' ;
<23.

‘

ADDRESS

MI)/ADD

[ADDRESS

REG.

DECODE —.AD.D.R_SLL&D_Q,C"MD

FO'C

fae

—C-CI—R-EL—-»

or;ser

—CNFGR

Bur

éfib;

oarh REcraren

EG.

FUNCTION

RE G,

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(29)

[BUF CMI
s

[

bisioes

:(¢e)

RCV

'
|

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wbD

Is!do>

CMT

(Fi. 6-2b)

T
——
-

‘

= -

RcY

)

B
. (31:00) >
ul®

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DATA

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cuem—’

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REG,

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/ I3

LYCHD

INTERRUPT
VECTOR

(Fc. ¢-25)

RETURN

31:08>

)

[emr

Mux

(o/z)

READ

XMIT DATA

0pR

<31:fe>
SEL

6}(FIG, 6-18)

xMiT

316y

[<is:09)

DATA

I5:44)>

—

<B!A

FiLE

14) | (14)

DATA

<31:60)

XMIY

CCL

LTckD CIPA

CIPA D <ispe
>

PAtA REGISTER

CMI DATA

CIPA

—

_DL5:¢8>

LTCHOD

LYCHD

:2';:0)

D<5: 47,

(13)

BUF CIPA
DATA

KIS

)

44:13)

BITE

AOP R

MASk

Lo REG,

REG,

(2)

(12)

CMDADDR

DATA

[aren L

[CHBABOR

<31.28)

[CMDADDR

0 23,

<2308

]ize,u,m,w)

Note:

Letter designations in parentheses

refer o engineering drawings

containing corresponding logic.

Figure

6-6

CCI

Block

Diagram

Mask Register -- The byte mask register recelves the

6.1.2.3 Byte

byte mask from the DP.
The register is eight bits wide capable of
holding
two
4-bit
byte
masks.
This
capability
1is
used for
quadword

data

transfers,

The

bus.

onto

the

CMDADDR

6.1.2.4 XMIT File -- The XMIT file
The
operations.
write
initiated
that is to be transferred
DP
the
XMIT file out to the CMI under CMI

is used as a buffer during port
file stores the write data from
to the CMI. The CCI unloads the
protocol.

The size of the XMIT file 1is 4 x 32; capable of holding four
implemented by dividing the file into
1is
Buffering
longwords.
(A
halfs
being
is

unloaded

While one half
and B) with two longwords in each half.
half can be
other
the
DP,
from the
with data
loaded

out

the

CMI.

from a 16-bit LTCHD CIPA D bus hence, each
1loaded
1is
file
The
The file
longword location requires two load cycles to be filled.
outputs onto the

32-bit CCI XMIT

DATA bus.

6.1.2.5 Return Read Data Register -- The Return Read Data Register
operations. The register
read
unsolicited
CMI
used during
is
to be transferred to the
is
that
DP
the
from
read
receives data
to the CMI under CMI
out
register
the
unloads
The CCI
CMI.
protocol,

The

Return

Read

Data Register is 32-bits wide.

The register is

loaded from the 16-bit LTCHD CIPA D bus hence, two load cycles are
required.
The register outputs onto the 32-bit CCI XMIT DATA bus.

6.1.2.6 Interrupt Vector -- The interrupt vector circuit supplies
a write vector
during
mux
CMI
the
vector to
interrupt
the
function,

CNFGR Register —-- The CNFGR register contains status,
6.1.2.7
control bits associated with operation of the CCI and
and
error,
The output of the CNFGR register is one of the selectable
the DP.
inputs

the

CMI

mux.

Mux -- The CMI mux selects one of four data sources
CMI
6.1.2.8
The four data sources
the data/address lines on the CMI bus.
for

Command/address bus (CMDADDR <31:00>)
Transmit data bus (CCI XMIT DATA <31:00>)
e

are:

CNFGR register
Interrupt

vector

Address Decode Logic -- The address decode logic decodes
6.1.2.9
the command/address longword received during the command/address
Outputs from the address
cycle of an unsolicited CMI operation.
logic

decode

indicate:

the

longword

command/address

addressed

to the

CI750.,

The

If the reference is to the CCI or the DP,.

1f the reference is a diagnostic maintenance function.

outputs

the

address

command/address hold register.

6.1.2.10

Command/Address

latched

data

Hold

decode

logic

are

applied to the

The command/address

wused to latch all the data received during the
1is
register
hold
The
operation.
CMI
unsolicited
an
of
cycle
command/address

1is

used

during

the

execution of the unsolicited

includes all the outputs from the
data
latched
The
operation.
address decode logic as well as address and function data from the

CMI.

The data in the command/address hold register is transferred

to the address offset register and the function register.

Register -- The address offset register
6.1.2.11 Address Offset
during an unsolicited CMI access to the DP. The register
wused
is
offset address (offset from the CI750 base address) of
the
holds
The register receives the offset
DP register to be accessed.
the
address from the command/address hold register.

1is used
function register
6.1.2.12 Function Register -- The
function
holds
register
The
operation.
during an unsolicited CMI
data received from the command/address hold register.

6.1.2.13
Register
the

Receive
latches

Write Data Register —- The Receive Write Data
the data off the buffered CMI data lines during

CMI status cycle.

With the CMI data latched, the CMI bus can

be released to allow another nexus to make a bus transfer,.

Data Register is 32-bits wide and is longword
Receive Write
The
The full 32-bit register output is
D bus.
CMI
BUF
the
loaded from
register high word and low word
The
file.
RCV
the
to
available
Hence to
CCI RCV DATA bus.
16-bit
the
to
coupled
are
outputs
cycles
unload
two
bus,
DATA
RCV
CCI
register onto the
the
output
are

required.

RCV File -- The RCV file is used as a buffer during port
6.1.2.14
The file stores the read data obtained
initiated read operations.
CMI (via the Receive Write Data Register) that is to be
the
from
The DP unloads the RCV file when the CCI
the DP.
to
transferred
©Unloading of the
1is available in the file.
that data
indicates

RCV file

is done under DP control.

The

size

longwords.

halfs
is

unloaded

RCV

Buffering

being

the

and

with

file

1is

32;

capable

holding

four

1is

implemented

dividing

the

file

into

two

longwords

each

half.

While

one

half

the

CMI,

the

1loaded
with
out to the DP.

data

from

other

half

can

The

RCV
file
1is
1longword
1loaded
from
the Receive Write Data
Register.
The RCV file high word and low word outputs are coupled
to
the
16-bit
CCI
RCV
DATA bus. Hence, each longword location
requires two unload cycles to be read out.

6.1.3
Simplified Flow Diagrams
Simplified
flow diagrams are provided
transfers,

write

The
the

execution

blocks

dotted

number.

The

of
represented
flows should
can

than
block

the

flow

title

seen

once.

This

repeats

and/or

that

some

itself

the

Therefore
rest

the

Port

data

number

key

flow

diagram

the

function

initiated

area enclosed
and/or figure

the

block

into

types

blocks

appear

represented

the

transfers.

described
in
Paragraph
6.1.2
and
are also included in the flow diagram

Figure

Chapter

Initiated

transfer,

the
that

various

components
Figure
6-6

throughout

CMI

Each block (or block
descriptive
title

figure

indicates

discussions,

6.1.3.1

port

Chapter
6 which describes in detail how the function
by
the
Dblock
1is
carried out.
Thus the simplified
be referenced throughout the rest of Chapter 6.

The
CCI
major
1llustrated
1in

illustrating

functions, and unsolicited CMI transfers.
diagram represent functions that occur in

of the transfer.
1lines)
includes
a

section

vector

6-6

should

also

port

initiated

referenced

Transfers

initiated

-the

port

which

transfer

the

CI750

port

and

read

is
the
bus master.
Figure 6-7 is a simplified flow diagram of a
port
1initiated
transfer
illustrating
the
major
steps
1in the
sequence,

The

1llustration

includes

operation.
The
HI,

port
the

are

loaded

bus.

three
At

microcode

ADDR
A

LO,

and

the

from

the

separate

byte
via

write

the

transfer

mask

the

bus

and

write

registers.

CIPA

cycle

The
the

required

the

three

16-bit

load

CMD/ADDR
registers

LTCHD

each

CIPA

the

registers.

this

write

initiates

both

point

read

the

flow

operation

sequence

being

divides

executed.

according

whether

LStart

Load
Load
Load

)

(Fig.

6=10)

CMD/ADDR HI register.
ADDR LO register.
byte mask register,

Write

operation

[Read operation
-

—_— =4

\
Load

XMIT

file,

6-12)

(Fig,

Issue

GO,

(Fig.

6=13)

\
Issue

GO.

(Fig.

6-13)

Arbitrate
(Fig.

I
(Fig.

for

Transmit

CMI,

for

CM1,

6-15)

—

Arbitrate

command/address

CMI.

6=15)

Transmit

command/address

;

|
|

to CMml,

Load Receive wWrite Data Register,
Receive status from slave,

Load

RCV

file.,

= === - T = =77|

Unload

]

data longword

Issue DONE to

port microcode,
—_— e

|
|

Unloaa

RCV

file,

|
(F1g.

)
e |e e

6=21)

—J

Done

’

Flow Diagram of Port Initiated Transfers

Figure 6-7

o))

(F19, 6-19)

Issue DONE to
port microcode,

transfterred

—

|
|

Receive status from Slave,

file.

XmKIT

|
|

Write
If

Operation

write

loaded with
required to
LTCHD

CIPA

longwords

operation

1is

executing,

write data from
load a longword
D

bus.

The

the DP.
into the
XMIT

the

XMIT

Two write
file from

file

can

hold

file

cycles are
the 16-bit
up

four

data.

After
the XMIT file is loaded, the port microcode issues
a GO
command to initiate the transfer of write data over
the CMI bus.
GO
starts
the
attempts to gain

arbitration
process
of the CMI.

wherein

the

port

control

When
the
arbitration is successful and the port has won
the bus, a command/address bus cycle is executed.
1In the
command/address
bus
cycle,
the outputs of the CMD/ADDR
HI, ADDR LO, and byte mask registers are combined to form
a command/address
1longword
on
the CMDADDR bus (CMDADDR
<31:00>).
The
command/address
longword is selected by

the

CMI

mux

and

placed

bus

cycle

onto

the

data/address

lines

the

CMI.

the

XMIT

file

the

data

unloaded,

longword

selected

first

placed onto the CMI data/address lines.
with
the
status
bus
cycle
wherein
status

from

transfer

the

DONE

signal

that
then
If

the

slave

was

data

write

issued

quadword

the

sequence

from

longword

can

The
the

the
1s

single

port

microcode

completed.

The

was

for

CMI"

block

Note

that

into

mux,

and

transfer ends
port receives

longword

"arbitrate
that

loaded

CMI

nexus.

the
CMI
transfer
terminates.

returns

the

point.
transferred

operation,
If
a quadword
the port must arbitrate for

transferred.

of data
the CMI

informing
flow

transferred,

the

is
bus

and

diagram

the

flow

repeats

only
CMI

data,

the

single

per

write

to be transferred,
for each longword

Read Operation

issues
over

a GO command

the

CMI

starts

attempts

executing,

1is

operation

read

initiate

the

the port microcode

transfer of

read

data

the

port

bus.

the

arbitration

to gain control

process

wherein

the CMI.

Wwhen
the
arbitration
1is sucessful and the port has won
the
bus,
a
command/address
cycle is executed.
1In the
command/address
cycle,
the
outputs of the CMD/ADDR HI,
ADDR
LO,
and byte mask registers are combined to form a
command/address
longword
on
the
CMDADDR
bus (CMDADDR
<31:00>).
The
command/address
longword is selected by
the CMI mux and placed onto the data/address lines of the
CMI.

When
the
slave
nexus
1is ready with the requested read
data, it initiates the status bus cycle wherein it places
the
data
1longword
onto
the CMI data/address lines and
status
onto
the
CMI
status
1lines.
During the status
cycle
the
port
takes
the
data
1longword
off the CMI
data/address
lines
and
1loads it into the RCV file (via
the
Receive
Write
Data Register).
The port also takes
status from the CMI during the status cycle.

If
the transfer was to read a single longword of data, a
DONE
signal is issued to the port microcode informing it
that
the
CMI
transfer
1s
completed.
The
sequence
proceeds to the next block to unload the read data out of
the RCV file.

data

returns
sequence
longword

quadword

to the
from
can

was

transferred,

"arbitrate for CMI" block
that
point.
Note
that
be
transferred
on
the

operation.
If
a quadword
the port must arbitrate for

of data
the CMI

the

flow

and repeats the
only
a single
CMI
per
read

is to be transferred,
bus for each longword

transferred.

Unloading

the

RCV file

Vector

Function

out

the

DP completes

the

read

sequence.,

6.1.3.2

Write

-- A write

special
"port
interrupts
the

initiated"
write
CPU
to
send
it

requests

from

result

port
The

error

conditions
vector

the CPU interrupt starting
simplified flow diagram of

address
a write

function

transfer
in
which
an interrupt vector.

1interrupt

contains
6-8 is a

etc.

o)}

power—-downs,

vector

such

the
port
Interrupt

parity

transferred

errors,

the CPU
for the CI750.
Figure
vector function.

( start )

y
Issue

interrupt

command.

Arbitrate
(Fig.

Transmit

Receive

for

CMI.

6=15)

interrupt

vector

status,

CMI.

(;;Donei)

Figure

6-8

Write Vector

Function

Flow

Diagram

Interrupt
logic
in the DP monitors those areas which could cause
an
interrupt.
When
the
1logic
senses an interrupt condition it
issues

command

the

CCI

which

1initiates

the

interrupt

sequence,

The

interrupt

port

attempts

command
to gain

starts

control

the
of

arbitration process wherein

the

CMI.

Wwhen
the arbitration is sucessful and the port has won the bus, a
command/address
cycle is executed.
In the command/address cycle,
the
CMI
mux
data/address
cycle
port

selects the interrupt vector
lines
of
the
CMI.
This is

1in
which
keeps
the

during

the

status

the the slave CPU
interrupt
vector
cycle.

and places it onto the
followed by the status
sends status to the port.
The
on the CMI data/address lines

6.1.3.3
Unsolicited
CMI Transfers -- An unsolicited CMI transfer
is
a
CMI
transaction in which the CI750 port is the slave.
The
port is addressed by the host CPU which commands either a write or
a read
of
a
port
register.
Figure
6-9
is a simplified flow
diagram
of unsolicited CMI transfers illustrating the major steps
in
the
sequence.
The
1illustration includes both a write and a
read

transfer.

The

CCI
contains
address
decode
1logic
connected
to
the CMI
data/address
1lines. When the decode logic detects an address that
falls within the address range (I/0 slot) of the CI750, it asserts
CI
SPACE.
Other outputs from the decode logic indicate what area
of the CI750 is being referenced.

The
outputs
f rom
the
decode
logic,
along
with
other
command/address
data
from
the
CMI,
is
clocked
1into
a
command/address
hold
register,
From the hold register, address
data
1is clocked into an address offset register and function data
is
applied
to
a
function
register.
If
the
command/address
reference 1s to the CI750 (CI SPACE true), DBBZ is asserted on the

CMI

and

the

function

data

clocked

into

the

function

Note
that
most
of
the
action described above occurs for every
command/address cycle.
All command/address longwords get decoded,
checked
for
a
CI750 reference (CI SPACE true), and latched into
the
command/address
hold register. The command/address is on the
bus

only

one

bus

bus,

for

decoded,

and

latched.

port,

the

Actions

assertion
assertion
only

latched

that

of
of

data

require

cycle
is

not

that

during

which

reference

the

must

taken

was

not

off

the

CI750

used.

the

reference

DBBZ
and
1loading
DBBZ in response to

the

CI750,

are

the
function
register.
a command/address cycle is

the

The
done

by the slave that was referenced.
Outputs from the function
register
are
command
signals
that
initiate
and
control
CCI
operations,
hence
these should only be asserted if the reference
was to the CI750.

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point the flow sequence divides according to whether the
reference address is to the CCI or the DP,.

this

CCI

Access

The

only

CCI register referenced (in normal mode) by an

operation
unsolicited
CCI
the
to
reference

Hence, a
the CNFGR register.
1is
CNFGR
the
to
reference
a
1is

the commanded function is a write, bits BUF CMI D
If
22, 20, 19, 17, 16, 14, 13, and 08 from the CMI,
23,
written
1into
the register during the status cycle.
then returns status to the host CPU and releases
CCI

31,
are
The
the

CMI.

the commanded function is a read, the CMI mux selects
If
CMI
the
for
register
CNFGR
the
from
output
the

data/address
host CPU
DP

and

lines.

The CCI

releases

the

then returns status to the

CMI.

Access

the DP and the
to
1is
reference
unsolicited
the
wWwhen
commanded
operation
1is a write, the write data is taken
off
the
CMI
data/address
1lines
and
latched into the
Receive
Write Data Register.
Status is then returned to
the
host
CPU and the CMI is released.
Thus the CMI
is not tied up while the CCI interfaces with the DP.

bus

In both a write and a read operation, a request 1s 1issued
to
the DP requesting access for a CIPA transfer.
The DP
responds
by
reading
the CCI address offset register to

determine which DP register

to be

accessed.

If
the
commanded operation is a write, the DP transfers
the
write
data
from the Receive Write Data Register to
the
selected
register in the DP via the CIPA bus.
This
completes

the

the unsolicited write

commanded

operation

sequence

is a read,

to the DP.

the DP reads the

selected
register
and
transfers
the
read data to the
Return
Read
Data
Register in the CCI via the CIPA bus.
The
read data is then unloaded from the Return Read Data
Register
onto
the CCI XMIT DATA bus.
The CCI XMIT DATA
bus
1is
selected
by
the
CMI
mux
for output onto the
data/address
1lines of the CMI bus.
The CCI then returns
status
to
the
CPU and releases the CMI to complete the
unsolicited

read

sequence.

6.2

Port

Figures

5-18

Interface

data

Initiated
and

Control

transfers

Logic

that

read

The

flow

diagrams

expansion

transfers

and

the

Load

Figure

6-19

over

general

Fiqures

CCI

block

bus

and

BUF

CIPA

DATA

latch

which

applied

CIPA

REG

write

decoder.

REG

SEL

case,

the

CMDADDR

the

six

CMD/ADDR

the

and

write

files.
In

loads

the

high

addition,

also

WRT

longword

transfer

the

bit

FLG

CMD/ADDR

low

word

low

CIPA

decoder

(quadword

indicating

On the next DP
associated REG
LTCHD

from

the
is

that

CCI

SEL

latched
D

<K15:00>.

and

CIPA

The

the

Figures

block

lines

latched

data

the

CCI

CIPA

written.

this

bits

quad

applied
SEL

The

quadword

REG

code

which outputs WRT ADDR LO.
WRT
address into the ADDR LO register.

SEL

CIPA

causing

the

and

RCV

and

for

When

asserts

progress.

low

word

bus.

The

ADDR

applied

the

conditioned

the
ADDR

<14:11.>)

into

XMIT

bit

sets

address

the

transfer.

flip-flop

the

from

the

flip-flop

transfer

cycle,

15).

CMI

CIPA

<@5:00>)

counters

the

quadword

write

for

(LTCHD

CIPA

and

(LTCHD

REG

applied

the

clocks

then

is
when

decodes

(LTCHD

taken

the

becomes

then

are

and

asserted.

read

and

diagram

state

location

6-7

following

true

address

data

which

are

initiated

the

data

bus

transfer),

The

asserted

function

transfer

code

buffered

<15:00>

false)

the

bits

and

<15:8¢>.

SEL

two

6.2

port

command/address

the

from

5-10).

CMDADDR

CMI

the

Control

Registers
is

Refer

6-11

taken

output

clears

pointers

QUAD

REG

address

bit

Figure

DATA

section

"load

where

select
HI

Interface

6-6)

Mask

(DIAGNOSE

6-8.

Byte

CCI/DP

initiated

Table

CMDADDR

1in

(Figure

CMDADDR

read

input

WRT

and

(see

and

CIPA

the

port

specifies
the
CCI
associated data (CIPA

The

CCI

code

CIPA

The

diagrams

And

CIPA

<3:0>

decoder

<2:0>

the

WRT

SEL

written

enables

BUF

LTCHD

CMD/ADDR

The

the

<K15:00>.

the

word

outputs

CCI

high

applied

for

that

gdiven

flow

6-7

Command/Address

command/address

DP)

CIPA bus.

diagram

a
flow diagram
byte mask registers"
function.
the register control logic.
The

CCI.

the

CIPA

the

descriptions

the

sequencing

the

code
written.

discussion.

6.2.1

and

the
in

<3:8>

transferred

given

SEL

detalled
6-8

the

REG

<15:00>) is

and

(located

DATA

CMI

Transfers
illustrated

Logic

between

supplies

location

5-19

and

its

address

to
the
write
loads the 16-bit

’

start

{
1 CIPA DATA <15:00>
Command/address high aata placed on CIPA bus by 0P (Fig. 5-18),

4 BUF CIPA DATA <15:00>
\

4 LICHD CLPA D <15:00>
Command/adaress

nigh

data

latched

{in

CCI.

f wRT CMDADDR HI
REG SEL code

Function bits

D €14:13>)

from DP

svecifies

‘

CMD/ACDR

(LTCHD CIPA

Read and write

and high address

counters cCleared

low

data

{is clocked

into

quadword flipflop.
y

placed

(Fig.,

LTCHD CIPA D 1S

files,

4 ciPA DATA <15:00>
bus

address location 0
in XMIT and RCV

Address

bits (LTCHD CIPA D <05:00>)
loaded into CMDADDR Hl

CIPA

S=18),

Quadword

Longword

CMI
transter.

CMl
transter,

f BUF CIPA DATA <15:00

4 urcuo crpa 0 <15:00>
Address

low

data

Figure 6-10

latched

CCI,

Load Flow Diagram for CMLC/ALDR HI, ALDR LO,

and Byte Mask Registers (Sheet 1 of 2)

* WRT ADOR LO
REG

SEL

Lo«

address

code

from

bits

specifties

(LICHD

CIPA

ADDR

<15:00>)

loaded

into

ADOR

f CIPA DATA <15:00>
Byte

masx

data

placed

CIPA

bus

(Fig.

S5=18).

1 sur crea vata <1s:00>

f LTCHD CIPA D <15:00>
Byte

mask

data

latched

CCI.

f WRT BYTE MASK
REG

Byte

SEL

code

mask

from

(LTCHD

specifies

CLPA

<07:00>)

YES

Write

operation

Fig.,
6~-12

Figure

6-10
and

byte

Write

mask

loaded

into

byte

mask

Read

operation

reqgister,

Fig.
6-13

Load

Flow

Byte

Mask

LCiagram for CMLC/ADDR HI,
Registers (Sheet 2 of 2)

ADDR

LO,

RD_CNTR <I'¢> [

READ

(F1G. 6b=18)

COUNTER

(4 cir®

RCV FILE
(;:,G,

b-18

ADR

@Mfi_fl_&*::

ADR

WRT ccI

tuL;mmm&JmQD

whR

DRIVE

(31:16)

(15:80)

CcCT

RCY DAIA <'5'¢¢>—%(Fl& 6-6)

RoV

File SEL

cc1

REG SEL &

RD RCY FILE K
RD

BVF CMT

(Fie. b-0)

. D €31:902,1p

WRT RCV
CFIG.

6-18

[RECEIVE

Rcv WD <31:16)

Wé?éi:

poy WD <5108 ~1

RCY FILE

((f-'zce)

(8)—fctk g

RCY

SEL

QFESET

REG

(:)"E“

}(FlG. 6-26)

cip
N

(F16. b-34)

GIPA REG SEL <2°'9)

DEC

(FI6. 6-/9) @-SMPADDR 27

DIAGNOSE

READ

RD ADDR

(Fi6.5-2)

CI_ADDRESS

RD RCY WD REG HJ

EEmam—

CJPA

}(rnG. s-2)

SEL

‘

CMDADDg

27 25, <23'|8)

LTCHD CIPA

crm/Aoos

b 142137, <B5: 60>

(F)=RRIYE_CIPA__

Cl ADDRESS

REG.

(F16. & - 6){

(1) Stk

]

CMPADDR

]

.
SLHL);

CIPA
ARDR L0l LTCHD
D15 8g)

CMDADDR

{89:02>

[ApDF

CMDADD

31:28

E75-5
[ GUAD Aprr:,bam
CiPA P |5, HD
( FIG. b-b)_LTC ‘;"F”w
Yer
A

CMDAD

LTCHD CIPA

D <B7-¢92

SeL
A

BYTE

cLg

cLK

(12)

SEL

DECODER

} ’G.)

——

EN|-

LTCHD CIPA

D<0n 982

WRT

BYTE

A REG SEL <2:. <2:6)

DIAGNOSE
_{}_!!_BI__E_M

__CLR

T XMIT FILE

RT XMIT FILE Lo

LTCHD

RETURN

READ

CIPA

1) <'5¢¢>

DATA
IN
REG. CLk Hi}e

(13) ck
o

RD_RTN

ccT XMIT.

REG

)

Rp xMIT EILE [(FIG- 6718

(FI6. 6-6)«—RATA <31:06> |

LTCHD CIPA

XMIT

FILE

Note:
b

v
(19 Xt

Number designations in parentheses

refer to engineering drawings
L
:
:
containing corresponding
logic.

(D)-BRCHIRLE2

»if7,

{I5:99>

—

Rl
%

WRITE

COUNTE R

WRT CNTYR) 9D

(19

CLR

Figure

6-11

CCI

¢l

@@a—

wRT

FIG. b-20b)

( (F1G.y b-34)
}(me.s-a)

r....flxm.szg. 3 |

__ WRT RTN Rp_ 10

,L:](IZHE"‘”S '

WRT RIN RD H)

DIAGNOSE

MASKI

]

6—/8)

(MuxaMuxB

clL ,q_EJ}J.L.&_@

E7S

F16.)\

T
WRITE

COUNTER

(IZ)

WRT CHMPADDR HJ

Control

Logic

(FIG. 6-18)

The
lower
counter,

eight
Dbits
The counter

£E134-8.

1£134-8

the

(MUXA/MUXB

CMI

Paragraph
registers

page
On

each

and

data

blocks.

registers

crossed.

CCI

eightNote

bit

that

byte

mask

while

the

<31:28>).

output

transfer

into

two

halves

E75-5

from

E75

This

negates

output
byte

from

cleared

the

byte

The

lower

lines.

mask

for

longword

transferred

contain

the

quadword

transfer.

quadword

set

FLG

conditions

WRT

occurred,

a
of

transfer

E75

CLR

byte

the

whenever

mask

and

1its

applied to
BYTE
MASK

the write
1loads
the

loaded

into

four-bit

the

byte

nibble

are

muxed

the

end

mask

(CMDADDR
onto

the

each

CMI

E75.
MASK

onto

bits

and

the
the

QUAD FLG.

After

MUXA

SEL

and

MUXA

command/address

cycle

the

second

mask

The

quad

the

SEL

<K31:28>

contain
of

the

upper

the

first

four

flip-flop

The

true
CMI

both

transfer

lower

bits

transferred

first

the

CMDADDR

longword

the

enabling

the

transfer.

second

occur,

set.

the

thereby

quadword

address

output

the

to
see

reloads

page

BYTE

E75-5

asserting

the

four

CMDADDR

cycle

false;

only

transfer,

mask

byte

mask

byte

mask

1wnicrocode

new

SEL code
1is
MAGSK.
WRT

both

from the CIPA bus.
The byte
to
the
byte
mask
register
as

flip-flop

the

transfer

the CMD/ADDR and ADDR LO
for
each
transfer
when

cycle,

byte

output

transfer.
bits

the

eight-bit

Flip-flop

four

The REG
WRT
BYTE

The

lines

SEL

The

with

assoclated
REG SEL code are
taken
mask
is
latched
and
then
applied

LTCHD CIPA D <K15:00>.
decoder
which
outputs

form
an
address
CMI
transfer
by

command/address
MUXA/MUXB

and Table 6-3).
Thus
have
to
be
reloaded

ADDR

the
ADDR
LO
register
1incremented
after
each

for

SEL

large

and

boundary

the

asserts

6.2.2.4
do
not

transferring
CMD/ADDR

of
1is

clocked

state

QUAD

transfer

has

negate

(Table

1in

for

5-3)

the

thereby

asserting
£E134-8
and
setting
E75.
The
true
state
of
E75-5
switches the
upper
four
bits of the byte mask
register
onto
the
four output
1lines
thereby
placing
the byte mask
of
the
second
longword

LAST

onto

XFER

CMDADDR

asserted

E75-5

false)

FLG

and

E75-5

control

the

true).

logic

byte mask

<31:28>

after
and

each

after

LAST

XFER

and

flip-flop

assert

CLR

output

single

each

longword

quadword

is ANDed
BYTE

lines.

with

MASK.

transfer

ALLOW DONE

CLR

BYTE

from

MASK

the

resets

E75.

Resetting E75

negates

bits

from

mask

thereby selecting the lower
the next byte mask.

four

the

port

6.2.2.

the

byte

(QUAD

FLG

CCIL

the

E75-5

the

continue
read,

function

with

continue

commanded

Paragraph
with

Paragraph

6. 2. 3.

microcode

comnanded

1is

write,

function

6.2.2

Write

execute

W N

.
.
.
.

Load

XMIT

file"

data

high

the

CIPA

bus.

high

word

two-bit

one

written,
the file.

word

and

The

its

data

section

four

cleared

File

Figure

6-12

CMI.

flow diagram

the

function.

pointer

the

function:

XMIT file is loaded with the write data
port arbitrates for the CMI bus
command/address longword is placed on the
XMIT file is unloaded out to the CMI

The

the

Function

write

The
The
The
The

6.2.2.1
"load

(WRT

the

CNTR

longword

WRT

hence

the

associated

high

word

XMIT

file

<1:0>)

pointer

SEL

latched

code

are

and

then

LTCHD CIPA

from a

locations

CMDADDR

REG

write

the

XMIT

file.

when

the

CMD/ADDR

addressing

addresses

The

from

<15:00>.

counter,

initially

taken

applied

counter

location

The

REG SEL code from the CIPA bus is applied to the write decoder
which
outputs
WRT
XMIT
FILE
HI.
WRT
XMIT FILE HI loads the
latched data high word into the high word section of location 0 in
the XMIT file.
Another

into

the

code

are

and

then

CIPA

XMIT

CCI

<cycle

file.

taken
applied

The

from
to

the

data

required

write

low

and

its

CIPA

low

word

bus.

word

The

section

data
of

the

data

low

associated
low

the

word

XMIT

file

word

REG

SEL

latched
as

LTCHD

K15:00>,

The REG SEL code from the
which
outputs
WRT
XMIT
latched

data

the

XMIT

file.

WRT

XMIT

FILE

WRT

CNTR

<1:0>

this

1is

1low

word

also

CIPA

bus

FILE

into

applied

LO.

the

write

XMIT

FILE

section

WRT

the

low

word

increments

the

write

counter

XMIT

point

quadword

location

transfer,

the

second

decoder

loads

location

causing

the
0

pointer

file.

longword

transferred

from

the DP to the CCI where it is written into location 1 of the
XMIT
file.
The
REG
SEL code will accompany both halves of the
longword
selecting the high word section of the XMIT file for the
first
half
of
the longword and the low word section of the file
for

the

WRT

XMIT

second

FILE

half.

point

Two

longwords

XMIT

file

before

the

The

write

counter

location

could

written

into

file

has

read

again

the

locations

out

incremented

file.

the

and

CMI.

the

4 cipa DaTA <153:00>
Data

high

word

placed

CIPA

bus

(Fig.

5-18),

4 Bur c1pA DATA <1szoo>]

Y
4 LTCHD CIPA D <15:00>
Data

high

word

latched

CCI.

f WRT XMIT FILE HI
REG

SEL

code

from DP

specities

high

section

XMIT

file.

Hign word (LTCHD CIPA D <15:00>) loaded into high section of XMIT file.

f CLIPA DATA <15:00>
Data

low

word

placed

CIPA

bus

(Fig.

5-18).

[t;auv CIPA DATA <1s:oo>|
4

f LTCHD CIPA D <15:00>
vata

WRT

XMIT

REG

SEL

Low

word

write

FIlLE

code

counter

word

latched

CCI.

from

(LTCHD

low

CIPA

specifies

D <15:00>)

incremented

low

section

loaded

into

location

XMIT

low
in

file,

section

XMIT

tile.

Second
longword
XM1T

Figure

f£ile

6-12

Load

XMIT

File

Flow

Diagram

tile,

6.2.2.2

Issue

~--

SET

A GO is

issued by the port microcode

when
the
port
1is ready to arbitrate for control of the CMI bus.
For a write operation, this is after the XMIT file has been loaded
with the write data.
For a read operation, this is after the byte

mask

has

been

loaded.

Figure
6-13 is a flow diagram of the "issue GO"
6-14 is a block diagram of the GO/DONE logqgic,

Figure

If the preceeding

port microcode asserts SET A GO to the DP.,

The

function.

microinstruction
has
not
been stretched out (UCODE STALL false)
(Paragraph
5.11.2.3),
GO
flip-flop El is set and asserts E1-10.
E1-10
in
turn
asserts
CIPA A GO on the CIPA bus.,
CIPA A GO is
received

the

CCI

where

becomes A GO and

SYNC A GO is applied

to GO/DONE PAL E121.

Had

the

asserted

SYNC

similar

microcode

sequence would

PAL

SET

have occurred

then SYNC A GO.

(instead of SET A GO),

resulting

the

assertion of

E121.

In response to SYNC A GO (or SYNC B GO), PAL E1l21 outputs POSSIBLE
GO.
If there is no CIPA transfer in progress to/from the DP (CIPA
XFER
false)
and
the CMI
POSSIBLE GO will assert GO
When
a
nexus
nexus
(except
CMI
1is
"read
function is the

is
to

not
the

"read locked" (READ LOCK
arbitration logic.

false),

executes
a
read lock function, it places all CMI
1itself) into the "read lock" state.
Thus when the
1locked",
the
nexus
that
executed the read lock
only one that can arbitrate for the CMI.

The GO/DONE logic senses a "read lock" function by detecting a BUF
CMI
D
27,25
function
code
of
0:1
(Table
6-2)
during
a
command/address cycle.
When function bits BUF CMI D 27,25 specify
a "read lock" function, they condition a Read Lock flip-flop to be
set
by
CLK RDLCK FF.
CLK RDLCK FF asserts every command/address
cycle
(except
port
initiated command/address cycles) (Paragraph

6.3.1).
is
READ

If
read

the

function

1lock

associated

function,

the

Read

with
Lock

the

command/address

flip-flop

sets

cycle

asserting

LOCK.

If
the
GO/DONE logic attempts to issue a GO command while in the
"read
lock" state, POSSIBLE GO asserts but the assertion of GO is
inhibited,
The
assertion
of
POSSIBLE
GO
enables a Read Lock
counter (clocked by B CLK) to start counting.
When

function
function
(1:1
reset.
During

bits
BUF
CMI
D
27,
<code),
the
Read Lock
the
command/address:

specify a
flip-flop is
cycle of the

"write unlock"”
conditioned to
"write unlock"

function,
CLK RDLCK FF asserts and resets the Read Lock flip-flop
negating
READ
LOCK.
The
negation of READ LOCK clears the Read
Lock counter and enables the GO AND gate.

6—-31

*szr A GO
From

microword.,

UCODE

YES

STALL

wait

for

current

instruction

1 E1=10

complete,

e
—

f SYNC A GO

f POSSIBLE GO

Present

LOCK

i{n

master

nas

Wait

i{ssued

for

wRITE

READ

UNLOCK,

transter
progress,

Bl
us

cycles

ASSERT

} A oonE

6=1

Figure

)

6-13

Atort

Issue

[

CIPA

CMI

function,

RLTO

Set RLTO error
bit

oreration,

Flow

Diagram

CMGR

614

‘

'1 GO ARBl

4 ARB OUT (A]

Y
A

higher

priority

device

requesting

the

CMI,.

Host

CPU

has

locked

the

CMI,

4
Another

device

using

the

CMI.

t DO CMI MASTER

WALT

JES
Port

executing

interrupt

6=17

function,

6-24

Figure

With

ARB

6-15

Arbitration

Flow

Diagram

CI750

level

6-36

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3
of
1level
arbitration
an
Similarly
connecting terminal A64 to terminal A62.

be established by
could
The assertion of ARB OUT

assert CMI ARB 3 to inhibit arbitration by the CPU and
would
[A]
Terminals A63 and A66
CMI devices at ARB levels 2 and 1.
the
by
are
left
open
so that the state of the CMI ARB 2 and 1 lines do
not effect the CI750 arbitration process.

In addition to higher level arbitration lines, the ARB AND gate 1is
CMI HOLD is
also inhibited by the true state of CMI HOLD or DBBZ.
asserted by the CPU to hold the CMI while an essential function is

executing.
other

DBBZ

indicates

that

the

CMI

If no higher arbitration levels are pending,

are

both

causing
of

is being used by some

device.

the

CMI

false,
CMI

and CMI

HOLD and

the ARB AND gate will be enabled by ARB OUT

MASTER to assert.

DBBZ

[A]

The CI750 port now has control

bus.

A WAIT
signal
1is
received
from
the
interrupt
1logic
1f
the
arbitration
resulted from an interrupt command.
If WAIT is false
(arbitration
due
to "issue GO" function), the flow passes to the
command/address
function
shown
in Figure 6-17.,
If WAIT 1is true
(arbitration
due
to
interrupt
command), the flow passes to the

write vector function shown

The
arbitration
from Figure 6-19
in
the
"read
quadword
data
transferred
and

in Figure 6-24,

flow
diagram shows DO CMI MASTER being asserted
in the "write operation" sequence and Figure 6-20
operation" sequence.
These inputs are used during
transfers
after
the arbitration

the
first
1longword
has
Dbeen
logic must regain control of the

CMI to transfer the second longword.
This is discussed further in
the
discussions
associated
with Figure 6-19 (Paragraph 6.2.2.5)
and Figure 6-20

(Paragraph 6.2.3.4).

6.2.2.4
Command/Address
Cycle
=-During
the
command/address
cycle, the port asserts DBBZ and places the command/address on the
CMI
bus.
Figure
6-17
1is
a
flow
diagram of a port initiated
command/address cycle.
The
next
B
CLK
after
a
successful arbitration (DO CMI MASTER
asserted)
that
was
initiated
by
an
"issue GO" function (WAIT
false),
1initiates
the
command/address cycle.
B CLK sets a DBBZ
flip-flop
(conditioned
to set by DO CMI MASTER) asserting ASSERT
DBBZ
and
then
CMI DBBZ on the CMI bus.
CMI DBBZ indicates that
the
CMI
is
Dbusy.
The
true
state
of
CMI
DBBZ inhibits the
arbitration process in all other CMI devices.

CMI
DBBZ
asserts
DBBZ
which
negates
conditioning
the DBBZ flip-flop to reset

CMI

DBBZ

1is

command/address

DBBZ
set.

1is

asserted

the

port

DO
on

CMI
MASTER
thereby
the next B CLK.
Thus

for only one bus cycle

(the

cycle).

also applied to a PREV DBBZ

flip-flop conditioning

it to

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Sl-9

)

6e2.2.5

Unload

the main
data
1in

XMIT

File

And Status Cycle —-- The next B CLK in
the period in which the port transfers the
to
the
CMI
and
negates
CMI
DBBZ.
This
the status cycle in which the port receives

flow initiates
the
XMIT
file

period

1is

status

from

followed
the

slave

illustrating

the

unloading

device.

Figure

the

XMIT

6-19

file

1is

and

the

flow

diagram

status

cycle.

NOTE

the

port

case

places

negates

two-cycle

the

CMI

(Paragraph

data

DBBZ

transfer,

onto

during

the

status

6-16),
B
CMI DBBZ.

ready

will

taken

the

one

bus

CLK

cycle

also

Logic

this

ENA

when

CMD/ADDR

E26

also

<31:00>

The

CLK

the

slave

DBBZ,

and

places

the

CMI,.

asserts

The

The
STATUS

WRT

ENABLE

STATUS

outputs
the

true
The

takes

logic

array
RD

the

status

negation

DBBZ

until

shows

this

DBBZ.

the

(Figure

file

FILE

(read

see

status
write

bus

bits

(CMI

CMI

DBBZ

samples

indicates

asserting
enables

counter

reset

6-19

and

SEL

code

CMI

mux

input.

the

data

which

Figures

MUXA/MUXB

file

6-18),

CMDADDR

responds

XMIT

loaded;

the

CMI

asserting

state

XMIT

resets
the
DBBZ
the slave is not

diagram

1s placed on the CMI bus and
slave holds CMI DBBZ asserted

select

cycle.

During

off

CMI,

the

STATUS

<K1:¢2>)
negates
DBBZ

the

6-11).

transferred

until

ENA

the
taken

has

the

CCI

status

negates

CMI

(Table 6-1)
on
which
in
turn

CYCLE.

assertion

assert

control

the

CLK
If

assert

flow

flip-flop

was

initiates

cycle

longer.

asserts

from

data longword
slave device. The

data.

The

the

CCI

turn

location

array
DATA

may

27.

bus.

operation.

the

write

out

Logic

XMIT

data,

the

PREV DBBZ

CMDADDR

data

XMIT

the

E26

bit
be

XMIT.

write
from

although

sets

array

function

the

data

and

6.1.1.2).

With
DO
CMI
MASTER
false
(Figure
flip-flop negating ASSERT DBBZ and
has

the

CMI

ENABLE

CLK

STATUS

enables

the

to
and

the

logic

negate

status

decoder

bits
from
the
CMI
and
configuration
register.

outputs
any
The
negation

inhibits
from the

CMI

the

output

CMI

bus.

the

mux

array

DRIVE

causes

CMI

which

the

HI/LO

decodes

array

1/40.

the

status

error
condition
to
of
DRIVE
CMI
HI/LO

thereby

removing

the

WRT

write

the
1/0

data

CLK

r
f MUXA/MUXB SEL <B:A>
MUXA/MUXB

selects
<31:00>

SEL

\
[f ENA xnxxJ

Y
[f PREV Dssz]

1
[ ASSERT oaaz'

coage

CCl

XMIT

tor

CMI.

DATA

’

[{ CHI ueaz]
\

f RD XMIT FILE

f CMl DBBZ

Enable

location

ouUt

Oof

XMIT

CLK

Assertea

Slave,.

{ CMI DBBZ
Slave

¢file.

takes

A cM1 sTATUS <1:0>
write

Slave

data otg CMI.

returns

to CI750u.

status

DBBZ ]
\

[f STATUS CYCLE]

@
Figure

6-19

Unload XMIT

File

(Sheet

and

Status

Cycle

Flow

Diagram

CLK

i
YES

~Quadword

‘\\£1223te

f‘wnr ENABLE STATUS

¥ DRIVE CNI HI/LO 1/0

Decode

Write

status

ApPply

any

error

bits.

transter

trom

CNFGR

data

removed

CM1,

transterred

[i!fbuow oc~s]

$ A oone

Filqg.
6-15

CMI

write

transter

completed,

[

A cLr BYTE Mask
Y
Reset

LiAcpr A DONE]

quadword

flip=flop

E75S

and

oyte

mask

Cclear

reqgister,

LA A DN SYNC]

{

* A DN
To

branching

logic.

bone

Figure

6-19

Unload

XMIT

File

(Sheet

and

Sta tus

Cycle

Flow

Diagram

this

been

quadword

transferred,

function
second

(Figure

the

6-15)

longword,

transfer
flow

When

and

diagram

rearbitrate
a

only

quadword

the

first

returns

for

the

transfer

CMI
was

longword

the

and

has

arbitraticn

transfer

sensed

the

during

the

command/address cycle, the arbitration sequence was executed up to
the
assertion
of
ARB
OUT
[A]
(Figure
6-17).
Now with DBI:7
negated, the arbitration sequence can proceed.
If in the interirn,
the
CPU
has
not asserted CMI HOLD or a higher priority nexus is
not
requesting
the
CMI,
the
CI750 will regain the CMI for the
second half of the quadword transfer.

If
this
control
MASK.

1s
the
1last
1logic
asserts
CLR

quadword

BYTE

transfer
of
the write function, the CCI
ALLOW DONE which in turn asserts CLR BYTE

MASK

flip-flop

E75

<clears

the

CCI

byte

mask

control

and

resets

logic,.

In
addition,
GO/DONE
PAL
El21 sensing the true state of STATLU
3
CYCLE,
outputs A DONE indicating that the write transfer functicn
is completed.
A DONE is placed on the CIPA bus as CIPA A DONE and
then
be

coupled

asserted

thereby

the

informed

(€S

SYNC.

branching

the

SYNC

logic.

completion

then

The

causes

port

the

microcode

is
write

commanded

function.
6.2.3

Read

execute
G
W
-

.
.
.
.
.

Function

read

function:

GO is issued from the port microcode
The port arbitrates for the CMI bus
The command/address is placed on the
The
The

6.2.3.1

RCV
RCV

Issue

file
file
GO

resulting

1in

Issue

sequence

the

is
is
=--

SET

assertion
1s

shown

Paragraph

6.2.2.2.

6.2.3.2

Arbitration
-GO is
to arbitrate for

which

proceeds

port
gains
arbitration

control

sequence

Paragraph

6.2.2.3.

6.2.3.3

Command/Address

initiates
the
command/address
command/address
slave device.
and described

CMI

written from the CMI
read out to the DP
GO

GO
in

1is

issued

the

Figure

received
control

the

port

arbitration
6-13

by
of

and

the
the

CMI

Cycle

assertion

command/address
bus
cycle
the
port
asserts
longword
on
the CMI bus
The command/address sequence
in Paragraph 6.2.2.4.

arbitration logic
bus.
When the

bus, it asserts DO
shown
in
Figure 6-15

The

described

CMI

the

microcode

logic.

and

MASTER.
The
described in

CMI

MASTER

cycle.,
During
the
CMI DBBZ and places the
for transmission to the
is shown in Figure 6-17

6.2.3.4

the

Status

Cycle

command/address

negates

which

CMI

the

device.

Write

DBBZ.

cycle

The

and

This

port

data

the

Load

the

File

the

data

into

6-20
RCV

and

the

The

period

followed

read

loaded

Figure
of

RCV

initiates

period

receives

read

Data

And

cycle

CLK

which

the

status

from

RCV

file

via

flow diagram

port

cycle

the

after

the

slave

Receive

the

status

file.

NOTE

In the case of a two-cycle transfer, the
port
negates CMI DBBZ during the status
cycle (Paragraph 6.1.1.3).

With
DO
flip-flop
assert
on

CMI

the

CLK

while

may

longer.

sets

the

slave
1t

has

CMI,

CCI.
the

The

port

uses

read

data

and

cycle

the

the
RCV

from

the

CMI

The

control

from

negation
status

CLK

(start

REG

false

clocks

into

the

1logic

slave

this

bits

the

CMI
are

data
to

asserting

requested

data

the

and
one

bus

DBBZ.

and

placed

DBEZ

will
places it

negation

DBBZ
on

resets the
The slave

DBBZ

cycle

it
in

indication

CMI

and

assert

the

on
the

that

bus

cycle.

decoder.
the

the

causing

DBBZ

also

the

flip-flop

obtained

DBBZ

WRT

DBBZ

B CLK
DBBZ.

requested

shows

CMI

the
the

the

diagram

responds

status

negates

status

The negation
true).
On

flow

the

(Figure 6-16),
and
CMI

DBBZ
obtains

The

also

After

DBBZ

CMI.

although
B

CMI
MASTER
false
negating
ASSERT

causes

status

state

the

STATUS

Receive

also

outputs

status

and

outputs

and

write

Write

The

cycle),

DBBZ

buffered

CYCLE

Data

WRT

decoder
any

the

CCI

outputs
data

control

WRT

(BUF

(PREV

RCV

CMI

DBBZ

logic

REG.

<31:00>)

ENABLE

STATUS

decodes

the

error

CMI

condition

enable
status

the

the
bits

CNFGR

third

the

read

pointer

output
B

data

into

(WRT

write

counter
command/address

WRT

RCV

asserted

CLK,

FILE

WRT

(RCV

CNTR

also

CCI

control

WRT

RCV

<31:00>)

logic

FILE.

from

the

RCV

file.

WRT

Data

write

1is

pointing

CMDADDR

6-11),.

increments

the

write

RCV

location

counter

location 1 in the file.
next
1longword
if
this

loads

file

<1:0>)

(Figure

ENA.

FILE

Write

the

WRT

RCV

Receive

cleared

The

being

cycle

the

asserts

location

pointer to address
location
of
the
transfer.

ENA

due

during

causing

the

the
the

write

This would be the file
were a multi-longword

CLK

[} ASSERT DBBZ]

l;* PREV 0BBZ

[§ CNI oesz]
\

CMI DBRZ

Asserted

slave,

c»\jes

pBBZ

; psaz
Read

data

CM],

[f STATUS cxcue]

Figure

6-20

Status

Cycle

and

(Sheet

Load

RCV

File

Flow

Ciagram

YES

CLK

‘

~Quadword
gransfer
NO

f WRT RCV WD REG

—t\

Load

SHI

read

data

(BUP

? <Jb:oz>)

into

ecelve

rite

Q WRT ENABLE STATUS

$ wrT
ENA'
a—r———

Decode

status

Apply any

Date

error

CNFGR

d 4 oone
CHI

| 4 auov oo~e]

8 CLK

read

transfer

completed,

[f CIPA A DONE

§ cLR BYTE MASK

4 WRT RCV FILE

Reset quadword
tlip=tlop E7S

Load
into

and clear byte
mask

read dJdata
RCV gflile,

Increment

write

counter.,

14 A oN sync
Y
4 A oN
To

Figure

branching

6-20

logic.

Status

Cycle

and

(Sheet

Load

6-47

RCV File

Flow

Diagram

bits,

transfer

this

been

1is

quadword

transferred,

function
the

(Figure

second

transfer

the

flow

6-15)

longword.

and

only

diagram

re-arbitrate

When

the

first

returns

quadword

for

the

transfer

longword

the

CMI

and

was

has

arbitration

transfer

sensed

during

the
command/address
cycle, the arbitration sequence was executed
up
to
the assertion of ARB OUT [A]
(Figure 6-17).
Now with DBBZ
negated, the arbitration sequence can proceed.
If in the interim,
the

CPU

not

requesting

second

not

half

the

this

logic

has

asserts

asserted

the
the

last

DONE

addition,

GO/DONE

CI750

higher

will

priority

regain

nexus

the

CMI

for

the

CCI

control

transfer,

transfer

ALLOW

HOLD

the

quadword

which

BYTE
MASK
<clears
the
flip-flop E75 in the CCI

CMI

CMI,

the
in

read

turn

function,

asserts

CLR

BYTE

byte
mask
register
and
register control logic.

PAL

El21

sensing

the

MASK.

resets

true

state

CLR

quadword

STATUS

CYCLE,
outputs
A DONE indicating that the read transfer function
is completed.
A DONE is placed on the CIPA bus as CIPA A DONE and
then coupled to the DP as A DN SYNC. A DN SYNC then causes A DN to
be
asserted
to
the
CS
branching logic.
The port microcode is

thereby

informed

6.2.3.5

Unload

"unload
5-19

RCV

1in

data

The

the

5-19

read

commanded

6-21

Figure

Figure
of

Figure

sequence.

6-21

the

function.

flow diagram

interfaces

illustrates

data

read

the

RCV

with

sequence

file

and

the

Figure
that

receives

unloaded.

microcode

transferred

completion

RCV File

unload

that

port

the

file"

Chapter

requests

the

requests
DP

that

the

asserting

read

the

data

REG

SEL

the

code

RCV

for

file

read

the RCV file.
The REG SEL code is applied to the CCI read decoder
via the CIPA bus.
REG SEL 3 is false for a register read function
(Table
5-10).
A negated REG SEL 3 enables the read decoder which
then

decodes

outputs

The
0 of

high
the

applied

The

word
RCV

half

for

read

bus.

The

RCV

file.
location
then

repeats

of
of
CCI

FILE

LO.

The
0

bits

<2:0>

enabling

(Figure

the

high

€-11).

section

The
the

decoder

RCV

DATA <15:00>) is transferred from
the CIPA bus as CIPA DATA <15:00>

file.

location
and then

DP.

microcode
low

SEL

FILE

(CCI RCV
file to

the

and

REG

RCV

low

of
applied

the
the

low

read
RD

preceding

longword.
word

decoder

RCV

word
the

the

data

section
LO

(CCI

RCV
to

DATA

in
RCV

the

REG

SEL

code

the

CIPA

bus

file,

code

low

<15:00>)
CIPA

order

places

the

enables

the

responds

FILE

RCV file
the DP.

sequence
The

asserting

section

is
as

retrieve

the

transferred
CIPA

DATA

RD
RCV

from

<15:00>

* CIPA REG SEL <3:0>
REG SEL code

from

word

section

DP selects hign

RCV

file

(Fig.,

5-19).

{

f RD RCV FILE HI
High word
out

(CCI

RCV

location

DATA
of

<15:00>)

RCv

gated

file,

fcpr DATA <15:00>
High

woro

transferred

DP,

1
$ C1PA REG SEL <3:0>
SEL

REG
word

from

code

from

RCV

selects

tile

(Fig.

DATA

<15:00>)

low

S~19).

4
f RD RCV FILE LC
Low word
out

(CCI

RCV

location

RCV

gated

fille,

Y
f CIPA DATA <15:00>
Low

YES

word

transterred

DP.

Cuadwora

\\\Qi:

:ster

NO
data

lohgwor

[§—C1PA ka]
\

+ WRT CCI REG ENA
Increments

read

location

pointer

RCV

tile,

(joone i)
Figure 6-21

Unload RCV File Flow diagram

this

1is

longword

<1:0>)

has

quadword
been

read

incremented
The

read

DP.

CLK

becomes

read

of
the

repeated.
CIPA

read
out,

this

1is
of

6.2.4

the
the

location

pointer
WRT

write

last

CMI

Write

The

CCI

file

and

ENA

which

only

Vector

vector

transfer

Issue

Arbitration

Write

6.2.4.1

read

the

RCV

When

CIPA.

PORT

Interrupt

INT

from

the

then

clocks

the

CCI

file,

the

consists

two

status

cycle,
sequences. These

port

read

CMI

The

cycles:

write

vector

are:

Vector

condition

interrupt"
Figure 5-24 and

PORT

INT

SYNC

PORT

INT.

which

then

outputs

the

CIPA

logic

as
described

transferred

bus

CLK

Interrupt

"issue

CNTR

Function
function

interrupt

first

(RD

sequence

CIPA

Issue
Interrupt -- Figure 6-22 is a flow
interrupt" function.
Figure 6-23 is a block
interrupt" logic,

"issue
"issue

1is

from

the

pointer

the

incremented
REG

and

read

completed.

command/address
cycle
and
a
function is described in three

RCV

counter.

sequence

the

SYNC

request

occurs
bus

which

the

diagram
diagram

CI750,

then

PORT

INT.
This action
Paragraph 5.12.1.

through
PORT

asserted

two

INT

flip-flops

used

the

applied

clock

of
of

DP
to

the
the

places
the

CCTI

illustrated

PORT
BR

INT

and

flip-flop

BR.

placed

on the Unibus at the BR priority level
16-pin socket E31.
BR is applied to four AND
gates
with the second input of each gate tied to an E31 pin.
The
socket
connects
a
+
voltage
from
pin
12
to
the pin at the
specified
BR level.
For the CI750, this is normally pin 13 for a
BR
level
of
4,
This enables the BR4 AND gate resulting in the
assertion of UBS BR4 on the Unibus,
established

the

The

CPU

arbitrates

the

ready

respond

asserts

bus

request

from

one

bus

grant

to
grant

(level

device

4).

requests

the

Bus

another.

the

CI750

grants

from

all

the

C(CI750's
the

are

Connector

same

CMI

priority

daisy-chained

socket

devices.

interrupt

E31

When

request,
level

the

connects

it
the

Unibus

all

the
inputs ([A]) to their corresponding outputs ([A+1]) for
all
priority levels except level 4.
The bus grant input at level
4 (UBS
BG4
[A])
1is applied to the "issue interrupt" logic as BG
IN.
There 1is no output at the corresponding BG OUT terminal.

(start
)

i
’ CIPA PORT INT

[Q PORT INIJ
\

[f D1 PURT lfl
Y

FSYUC PORT INT]

1\
UBsS

8G4é (A)

[f 8¢ Ig]

DELAYED

}

‘l
A higher priority device
1s

interrupting the CPU,

CLK

8 CLK

DELAYED 8 CLK

y
*":%E]
\

|4 cm wAIT |
Fig.

6-15

Figure 6-22

Issue Interrupt Flow diagram

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6-52

some

other

request,

OUT

the

device

also

interrupt

logic

would

terminal

passing

and

the

bus

clocks

then

grant

the

along

level

output

Unibus

the

device

had
bus

UBS

that

issued
grant

BG4

the

[A+1]

bus

the

thereby

had

issued

set

the

bus

from

the

request.,

1IN

flip-flop.

E118

OUT.

would

Had

not

have

delay?*).

grant

* Time

the

allowed

the

bus

where
The

output

the

when

the

(UBS

would

the
vector"

the

CCI

the

CI750),

asserted

have

(after

returned

E118

the

bus

the

event

the CI750

three flip-flops.
The output
flip-flop thereby removing

BR
the

Unibus.

arbitration

flip-flop

WAIT

1logic.

quadword

The

the

and

inhibits
Thus

1is

the

operation

the

logic

sequence.

(WAIT)

logic,

output

arbitration

applied

assertion

GO/DONE

happened

the

CMI.

CMI

logic

does

not

progress

occurred.

the

WAIT

indicates to logic array E26
data transfer) is executing.

proper

(Paragraph

CMI

Arbitration

which

When

assertion

MUXA/MUXB

SEL

code

for

that

The

the

"write

pending

"write

6.2.4.3).

informs

the

host

CPU

the

function.

6.2.4.2

logic

the

terminal.

applied

control

logic,

output

function

from

1is

third

the

CMI,

been

set

the

CCI control logic, WAIT
interrupt
transfer
(not
a

from

would

[A+1]

chain

the

vector”

have

BG4

resets
BR4)

GO/DONE

then

inhibits

request

BG OUT

UBS

(E120-5)

interrupt

can

doing

bus

flip-flop E118

GO ARB

(no

OUT

applied to
flip-flop

logic,

the

array

The

via

arbitration

interrupt.

asserts

re-assert

In
an

for

request

arbitration
In

and

assertion

conditioned

false

set

flip-flop

XFER

been

(E118)
and

The

1IN 1s also
the
first

second

sets

Unibus

requesting

flip-flop

the

port

gains

arbitration

6.2.2,.3.

6.2.4.3

Write

MASTER.

CLK

1is

arbitrate
is

Interrupt

arbitration,

The

which the
CMI
bus.

E120-5

control

sequence

Paragraph

successful

proceeds

the

shown

received

for

bus,

Vector
the

asserts

Figure

6-15

Upon

arbitration

initiates

the

control

—-—

status

"write

interrupt

the

vector"

port.

Figure

sequence.

flow

bus.

MASTER.

described

asserts

command/address

6-24

CMI

completion

1logic

port asserts DBBZ and places the interrupt
This
1is followed by the status cycle in

returns

the

and

arbitration

cycle

of
DO

a
CMI

during

vector on
which the
diagram

the
CPU
the

CLK

% oRIVE CMI HI/LO 1/0

4 muxa/muxe SEL <BiA>

Enable

MUXA/MUXB

CMI

mux

outpat

CMI.

SEL code
interrupt

Sselects
i

vector

d AsSerT DBBZ

for

CMI.

4 cu1 osez

*DO CMI MASTER
B8

CLK

fwar ENA STATUS

}muvs CMI HI/LO 1/0

| Decode status
bits.

CPU

always

returns

fpas:v DBBZ

}Assmr 0BBZ

Interrupt vector

removed

from

CMI.

"no error”

* CMI

status.

DBBZ

L LL |

Q STATUS CYCLE

Figure

6-24

Write

Interrupt

Vector

Flow

Diagram

B CLK

sets a DBBZ

asserting
6-16).
process

ASSERT

flip-flop

(conditioned to set by DO CMI MASTER)

DBBZ

then CMI

and

The
true
state
of
CMI
in all other CMI devices.

DBBZ

CMI
DBBZ
asserts
DBBZ
which
negates
conditioning
the DBBZ flip-flop to reset

CMI

DBBZ

1is

asserted

command/address

DBBZ

1is

the

port

the

CMI

bus

1inhibits

the

arbitration

DO
on

(Figure

CMI
MASTER
thereby
the next B CLK.
Thus

for only one bus

cycle

(the

cycle).

also applied to a PREV DBBZ

flip-flop conditioning

set.

Also

occurring

during the command/address cycle

is the assertion

of DRIVE CMI HI/LO 1/0 by logic array E26 in the CCI control 1logic
(Figure
6-18).
When
the
array
senses
that the CMI bus has a
master
(DBBZ
true)
and
that
the
CI750 is that master (DO CMI
MASTER
true),
it
asserts DRIVE CMI HI/LO 1/0 to gate the output
from

the

CMI

mux

the

CMI

bus.

Logic
array
E26
interrupt
logic.

also
senses
the
true
state of WAIT from the
WAIT
indicates
to
the
memory
array that an
interrupt
sequence
is
executing.
Accordingly
the memory array
outputs
the
MUXA/MUXB SEL code that selects the interrupt vector
for the CMI mux input (Table 6-3).

The
next
false,
B
DBBZ,

B
CLK
1initiates the status cycle.
With DO CMI MASTER
CLK resets the DBBZ flip-flop negating ASSERT DBBZ, CMI

and

DBBZ.

B CLK also sets
PREV

DBBZ

true

the PREV DBBZ
and

DBBZ

flip-flop asserting PREV DBBZ.

false,

STATUS

CYCLE

With

asserts.,

In addition, B CLK causes logic array E26 to assert WRT ENA STATUS
and negate DRIVE CMI HI/LO 1/0.
WRT ENA STATUS enables the status
decoder
which
decodes
the
status
bits
from the CMI.
The CPU
always
returns
a "no error" status in response to a write vector
function.
Hence there is no output from the status decoder.

The

negation of

mux

thereby

The

CPU

now

DRIVE

removing

takes

CMI
the

the

HI/LO

1/0

inhibits

the

interrupt

vector

from

appropriate

action

output

the

CMI

response

the

CMI

bus.

the

CI750

interrupt.

The

interrupt

vector

(Figure

6-25)

32-bit

command/address

longword.
The byte mask field (bits <31:28>) is all zeros and the
function
code
(bits
<27:25>)
1is
6,
The
address field (bits
<23:00>)
1is determined by the CMI I/0 "frequency slot" and the BR
level assigned to the CI750.
This is discussed below.

6-56

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Most

the

vector

bits

are

supplied

the

CMI

mux

use

voltage
pull-up and ground
connections.
These
1include
the
mask bits, the function bits and 19 of the 24 address bits.
of

the

values

address

the

bits

are

interrupt

Table

I/0

Slot

Level

selectable.

Table

lists

all

Five

possible

6-4

Interrupt

Vector

Values

Bits

Interrupt
Vector

4
5

byte

vector.

No.

6-4

006

(hex)

g
g

@0
1

0
)

1
1

@
0

PCPO

<31:06>

0128
68

EC
30
70

0
0

0
1

1
1

g
g

1
1

34
74

g
g

1
1

B4
F4

F8
3C

6
7

1
1

0
1

1
1

l
1

1
1

BC
FC

6-57

The five selectable bits are 07, 06, 04, 03, and 02.
Three of the
selectable
bits (04, 03, 02) are established by the I/0 "slot" in
which
the
CI750 is located.
There are six I/0 "slots" (numbered
10
through
15
1inclusive)
which could be assigned to the CI750.
Each
slot
has
1its
own
base
address.
Bits 04, 03, and 02 are
connected
to
terminals
designated
as
CMI
SLOT
SEL
<2:0>
respectively.
By use of jumpers, the three SLOT SEL bits are made
l1's or 0's according to the I/0 slot assigned to the CI750.

The
three
SLOT
SEL bits are used in the address decode logic to
establish
the
I/0
slot
that
the logic will recognize as being
CI750 addresses.
The address decode logic and the use of the SLOT
SELL,
bits
1is described in Paragraph 6.3.1 (Command/Address Cycle)
and
Figure
6-26.
It 1is sufficient here to say that the value of
the
SLOT
SEL bits have already been established by the selection
of the CI750 I/0O slot,

The

remaining

two

selectable

address

bits

(07

and

06)

are

designated
as
VECTOR
<07:06>
respectively.
The value of these
bits
1is established by the BR level selected by jumper socket E31l
(Figure
6-23).
As seen in Table 6-4 and Figure 6-23, the binary
value
level

of
bits
VECTOR
<K07:06>
changes from BR4 to BR7.

increases

from

the

Table
6-4 lists the binary values of vector bits <07:00>, and the
hex
values
of the entire vector longword, for all four BR levels
in
each I/0O slot.
The normal selections for the CI750 is BR4 and
I/0
slot 15, resulting in a normal interrupt vector value of 0CO0O
013C.

6.3

UNSOLICITED CMI

OPERATIONS

The
flow
diagrams
and
descriptions
given in section 6.3 are a
detailed
expansion of the general flow diagram of unsolicited CMI
transfers
given
1in
Figure 6-9.,
Refer to Figure 6-9 and the CCI
block diagram (Figure 6-6) in the following discussion.

6.3.1
Command/Address Cycle
In the command/address cycle, the CPU addresses the CI750 port and
the register that is to be accessed.
It places the address on the
CMI
along
with
DBBZ and the requested function (read or write).
The
CI750
takes
the
command/address
longword
off the CMI and
decodes

the

address

and

function

fields.

that
the
command/address reference is
the CMI while the operation executes,
Figure

6-26

illustrates

the

logic

for

involved

the

it,

CI750

determines

asserts

decoding

the

DBBZ

address

field.
The
1logic includes an address space decoder to determine
if
the
CI750
1is
being
addressed,
and
a
register decoder to
determine
the
register or register area that is being addressed.
The

decoders

are

discussed

Paragraphs

6.3.1.1

and

6.3.1.2.

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6-59

(BUF CMI D <31:28>) are ignored by the CI750.

mask bits

byte

The

Function
bits
BUF
CMI D <26:25> are also ignored.
Function bit
BUF CMI D 27 is used to specify either a read or a write operation
(these are the only two unsolicited functions; see Table 6-2).
6.3.1.1

Decoder

Address Space

Address
bits
BUF
CMI
D <23:12> are applied to an address space
decoder where they are compared with the base address of the CI750
(Figure 6-27).
If a match is obtained, the logic asserts CI SPACE
indicating
that
the
port
1is being addressed by the CPU and the
command/address data

for

the CI750.

15, 14 and 13 in the address space decoder are designated as
Bits
The bits are connected to backplane
SEL <2:0> respectively.
SLLOT
jumpers, can take on values of one or
of
use
by
and
terminals
The jumpers select the port base address from six possible
Zzero,
values thereby placing the 8K of CI750 address space in one of six
The CI750 is
6-5.
1in Table
shown
as
slots"
"frequency
I1/0
normally

in I/0 slot no.

15.

CI750 I/0 Slots

Table 6-5

No.

Address

12
13
14
15

F34000
F36000
F38000
F3A000
F3C000
F3E00O0

6.3.1.2

Bit 14

Bit 15

Base

I/0 Slot

SLOT

SEL 2

SLOT SEL 1

SLOT SEL O

0
1
0
1
0
1

0
0
1
1

1
1
1
1

Decoder

Bit 13

Offset

Address

BUF

bits

CMI D

<11:02>*
are applied to a register decoder where they are decoded
to
specify
the
port
register
or
register
area that is to be
accessed.
Figure
6-27
1illustrates the response of the register
decoder
to
the
address
bits.
Figure
6-28
1illustrates CI750
address
space
relative
to
the signals asserted by the register
decoder.,
The
total CI750 address space is 8K, As seen in Figure
6-28,
all
the
CI750
registers
(including the LS and VCDT) are
located within

the

first

address

space.

* The
two
lowest address bits (BUF CMI D <01:00>) are
all unsolicited CMI transfers are longword aligned.

the

this

range

address

decoder

from 000

range are

000

asserts

all

the

to 03C

the port

(hex), ADDR <11:06> 0

hardware

reference

registers.

1is asserted.

1is to the CNFGR register and

CNFGR.

ignored as

the

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catre

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Figure

6-27

CI750

Decoder

Address

6-61

Responses

[Y S

Figure

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6-28

CI750

Decoder

CMI

= s

]

Address

Outputs

6-62

Space

uTrs

From
address
#2080
to
maintenance
function.

(CMD/ADDR HI,

byte mask,

accessed

are

ADDR

the

accessed

LO,

host

only

CPU

for

CCI
REG
registers

for

XMIT

normal

diagnostic

CNFGR
register
is
the
unsolicited
operation.

only CCI
(Hence,

indicates

DP.)

The

the

range

access

(local
are

the

store)

from

900

most

area

93C,

the

software

asserted
the
@20

file,

and

1indicating
a
to
@3C
range

RCV file)

unsolicited

testing

are

operations.

the

CCI

not
They

hardware.

The

the

ADDR

1is
in

extends

<K11:96>

registers

from

1is

BFC.

asserted.

800

this

the

port

associated

with

architecture.
The

range

descriptor

6.3.1.3
diagram

from

C@@

FFC

table)

the

DP.

1is

for

the

VCDT

(virtual

Command/Address
Sequence -- Figure 6-29
the unsolicited command/address sequence.

«circuit

flow

The CPU asserts CMI DBBZ on the CMI and places the command/address
on the CMI data/address lines (CMI DATA <31:00>).
As shown in
Figure 6-16
(arbitration logic), CMI DBBZ asserts DBBZ which 1in
turn
asserts
CMDADDR CYCLE.
The
true
state
of
CMDADDR CYCLE
indicates this to be a command/address cycle from some other nexus

the

DBBZ

The

CMI,

not

cycle.
the

CLK

B CLK

CI753

initiated

(designated

[l1]

address

function

bit

addition,

asserts CLK

command/address

decoder

hold

BUF

CMI

B CLK

[l1]

are

sets

CLK

RDLCK

space

command/address

cycle

(ASSERT

false).

and

[1])

the

DBBZ

command/address

into

the outputs
decoder

bits BUF

loaded

the

loads

Address
also

ends

which

CMI

the

hold

from

1into

<11:02>

and

flip-flop asserting

DBBZ.

SPACE

CYCLE true)
on
the
CMI

true,

CLK

CMI

ASSERT

DBBZ

sets

the

DBBZ

flip-flop

asserting ASSERT DBBZ.
ASSERT DBBZ
bus
thereby
holding
the
bus
until

function
1is
completed.
command/address
was
not
assert

[1]

for

(CMDADDR

asserts CMI DBBZ
the
wunsolicited

CI
SPACE
were
false,
the
the
CI750
and
the
port
would

CMI
not

DBBZ.

also

negates

CMDADDR

CYCLE

indicating

the

end

the

command/address cycle.
Note that the false state of CMDADDR CYCLE
no longer conditions the DBBZ flip-flop to set.
However NS BIT 3
is
now
asserted
by
logic
array E26
to
hold
the
flip-flop
set
(thereby
keeping
CMI
DBBZ
asserted)
wuntil
the
unsolicited
operation 1s completed.

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)

6-64

~un0OaUG3wMQ_

Still
another ASSERT DBBZ branch exists possibly resulting in
assertion
of
SET
MIN.
This
1is a special case of a "write
function and is discussed in Paragraph 6.3.3.3.

the
DP"

If there is no CIPA transfer in progress to/from the DP (CIPA XFER
false),
the
next
B
CLK
(B CLK [2]) will assert ALLOW RD which
clocks
the offset address from the hold register into the address
offset register.
The base offset address is address bits <11:02>,
ADDR
K11:06>
24,
and
ADDR K11:06> 0.
ADDR <11:06> 24 and ADDR
<11:06>
<01:00>

O output from
respectively.

B CLK

[2]

the
the

access
control

1is to
logic

If
CIPA
access.
DP

also

function
function

the

clocks

address

offset

function data

from the hold

CCI

RCV

DATA

into

from
that

a register in the DP. CIPA REG
to indicate a CIPA transfer.

applied

to the CCI

REG
1is
false,
continue with Paragraph 6.3.2 for
If CIPA REG is true, continue with Paragraph 6.3.3

a CCI
for a

access.

6.3.2
Figure

Read/Write
6-30
1is
a

operations

a maintenance
register.

6.3.2.1
capable

the

CCI
flow

CCI.

diagram

function

Maintenance
writing and

unsolicited

all

unsolicited

access

reference

the

read/write

CCI

either

configuration

Function
-CCI maintenance functions
reading all the CCI registers.

are

If
a
maintenance function is executing, CCI REG is asserted from
the
function
register to enable the CCI diagnostic logic (Figure
6-26).
The
CCI
diagnostic
logic
samples
the
READ and WRITE
commands

from

the

function

and

the

CCI

REG

SEL

code

from

the
command/address
hold
register, to generate enabling signals
for
the RCV file and the XMIT file.
The CCI REG SEL code is also
applied to the read and write decoders in the CCI register control
logic
(Figure
6-11)
for
additional
register
and
function
selection.
After
the
maintenance
6.3.2.2
is

not

Writing
executing,

indicating
register,

that

and
are

the

the function
run,

CNFGR Register --

CNFGR

the

are

SEL

unsolicited

selected,

asserted

the

diagnostic

a maintenance

function

from

reference

the

1is

hold

the

CNFGR

YES

Maintenance
function

{ CNFGR SEL
AcCcCess

f CCI REG

YES

CNFGR

BUF

Enable

CCI

Function
write

diagnostic

and

CCl

Function

read

control

logic

samples

READ

WRITE

and

comrmands

and

CCI

SEL

code

and

Run

CCI

select

function,

diagnostic

routine,

operation.

CLK

fVRT ENA

l
f WRITE CNFGR
Write

1logic

A
Frem

+ READ

logic.

* WRITE

operation,

CCI

REG

* WRITE

diagnostic

yNS BIT 3

f DRIVE CMI HI/LO 1/0
Enable
to

CMI

mux

output

CM],

ENA

MUXA/MUXB
MUXA/MUXE

CNFGR

tor

U
Figure

6-30

Read/Write

(Sheet

6-66

CCI

Flow

SEL

selects

CNFGR

SEL

Diagram

<B:A>

code
CMI.

Pre—

CLK

—_—

+ ASSERT DBBZ

f CMI STATUS

l
Y CMI DBBZ
CCI

Status

releases

CMI

bits

placed

CMI,

bus.

Y o882

f STATUS CYCLE

l,_
(_Emm—i)

Figure

6-30

Read/Write

(Sheet

CCI

Flow

Ciagram

When

function

bit

true,

write

operation

specified.

1In

this
case
the
function
register
outputs
an
asserted
WRITE
resulting in a negated READ.,
The false state of READ is sensed by
the
CCI
control
1logic (Figure 6-18) which responds by asserting
WRT
ENA
ANDed
to

on
the
generate

next
B CLK.
CNFGR SEL, WRITE, and WRT ENA are
WRT CNFGR ENA.
WRT CNFGR ENA clocks write data

bits
BUF CMI D 31, 23, 22, 20, 19, 17, 16, 14, 13 and 08 into the
CNFGR
register,
Due to the relatively quick access to the CNFGR
register
(as
compared to having to access a register in the DP),
the

ten

them

write

The

CLK

control

data

bits

holding

that

logic

are

asserted

taken

negate

WRT

directly

not

ENA

from

the

CMI.

BIT

Latchirjy

necessary.

also

caused

thereby

conditioning

resets

the

NS
the

from

DBBZ

the

CCI

flip-flop

t»>

reset.

The

following

DBBZ.

The

CLK

negation

ASSERT

The
negation
of
DBBZ
true)
indicating
that
data 1s on the CMI.
The

CLK

that

control

logic

6.3.2.3

Reading
executing

not

read

operation

outputs

state

READ

reset

sensed

DBBZ

flip-flop

also

true)

the

bits

1In
CCI

the

and

ASSERT

then

caused

If a maintenance
function bit 27 is

this
in

case
an

the

function

asserted

control

logic

the

CCI

CMI.

and

resulting

negating

CMI

status

specified.
WRITE

flip-flop

negates

DBBZ

CMI

the CNFGR
(CNFGR SEL

negated

the
the

DBBZ

DBBZ.
STATUS CYCLE to assert (PREV DBR’
the status cycle and valid status

causes
this is

assert

DBBZ

READ.

which

function
false, 1
registe:
The

true

responds

asserting
DRIVE CMI HI/LO 1/0 and MUXA/MUXB SEL <B:A> on the nex!
B CLK.
DRIVE CMI HI/LO 1/0 enables the CMI mux output to the CMI
The
asserted MUXA/MUXB SEL code selects the CNFGR register outpu.
for
the CMI mux input.
The register bits are thus transferred to
the data/address lines on the CMI.
CLK

and

the

control

that

asserted

MUXA/MUXB
1logic

SEL
negate.

DBBZ

flip-flop

reset,

The

following

CLK

DBBZ

and

"write

asserting

CNFGR

CIPA

releasing

HI/LO

1/0

enabling

code,
also caused NS BIT
The negation of NS BIT 3

status

the

bits

read
on

the

sequence
CMI

bus

signal

3 from the
conditions

negating

just

for

CCT
the

CMth

the

and

involves

Request

provides

the

CMI

operation.

Transfer

transfer

DRIVE

completes

the

6.3.3
Read/Write
Read/write access to

the

it
the

into

the

CMI

bus.

three
The
DP

this
the

Receive

The

operations.
CCI

requests

with

These

the

data

Data

CCI/DP

address

write

Write

are:

the

function,

the

off

the

CMI,

and

Write
DP - Write data is transferred
selected register in the DP.

Read
DP
- Read data is taken from the
in
the
DP
and transferred to the CMI
CMI bus 1s then released.

Paragraph
5.10.3
(Unsolicited
corresponding
actions
occurring
operations are executing.

6.3.3.1

the

CIPA

Transfer

"CIPA transfer

Request
1in
the

from

operation.

CCI

the

selected register
the CCI.
The

via

Operations)
DP
while

Request -- Figure 6-31

request"

the

is a

describes
the
three

flow diagram

When
function
bit 27 is true, a write function is specified.,
1In
this
case the function register (Figure 6-26) outputs an asserted
WRITE
1indicating
that
a
DP
register
is
to
Dbe written.
The
assertion
of
WRITE
results
1in the negation of READ.
The false
state
of
READ
1is
sensed by the CCI control logic (Figure 6-18)
along
with
the
true
state
of
CIPA
REG.
In response to the
asserted
CIPA
REG
and
the
negated READ, the CCI control logic
asserts
WRT
RCV
WD
REG
on
the next B CLK.
WRT RCV WD REG is
applied
to
the
Receive
Write
Data Register where it loads the
write data from the CMI bus into the register.

The
BIT
the

CCI
control logic also negates NS BIT 3.
The negation of NS
3
conditions
the DBBZ flip-flop to reset (Figure 6-16).
On
next
B
CLK
the DBBZ flip-flop resets negating ASSERT DBBZ.

The
negation
of ASSERT DBBZ
negation of CMI DBBZ releases

negates
the CMI

CMI DBBZ
bus.

and

then

DBBZ.

The

The
negation
of
DBBZ
causes
STATUS CYCLE to assert (PREV DBE?Z
true)
indicating
that
this is the status cycle and valid status
data from the CCI control logic is now on the CMI.
In
addition,
the
CCI
control
1logic
REQUEST
asserts for both write and read

asserts SET
functions.

REQUEST.
SET
The assertion

SET
REQUEST asserts REQUEST which is placed onto the CIPA bus
as
CIPA
REQUEST.
The
DP responds to CIPA REQUEST by returning
CIPA
GRANT
and
the
REG
SEL
code that specifies a read of tre
offset
register
(Paragraph 5.10.3).
CIPA GRANT indicates to the
CCI
that
the DP is executing the requested function.
CIPA GRANT
asserts GRANT and then SYNC GRANT which in turn negates REQUEST.

The
REG SEL code is applied to the CCI read decoder which asserts
RD
ADDR
OFFSET.
RD ADDR OFFSET enables the output of the offset
register
(CCI RCV DATA <11:00>) onto the CIPA.
The 12-bit offset
address
specifies
the
DP
register
to
be
accessed
for
the
unsolicited function.

6-69

8VF

2ES cal D 27 NO
4

’»

WRITE

1is

vwritten,

\
B

CLK

4 wrT RCY WD REG

H NS BIT 3|

Data fron CMI
loaded inte Receive
Write Data Register,

y
B

CLK

$cni sTATUs <1:0>
status

4 ser Rseucs;]

LLASSERT oaazj

bits

placed on CAmI,

Y CHI D88z
CCI

releases

CMI,.

4 status crcuel

Figure

6-31

Flow

LCiagram

(Sheet

CIPA

Transfer

Request

[?REQUEST]

‘

f CIPA REQUEST
Request
an

4 cipa xFER

asserted

unsolicited

to DP for

CTO0 counter enabled,

operation.,

)

DP responds with CIPA
GRANT and REG SEL code
(Figs.

5-12,

5-20).

f C1PA REG SEL <3:0>
DP

DP asserts REG SEL code
tor a read of the

address

offset

‘

Oftset

address

<11:00>)

(CCI

chpa GRANTJ
RCV

read out

of address oftset register,

Otfset address ot DP
register

transferred

(Figs.

S=12

A Grant

4 C1PA DATA <15:00>

DPp

completed

A RO ADDR OFFSET
DATA

has

requested operation,

and

‘ll

[' SYNC GRA“T]

5-20).

* SET CTO
Set

CTO

bit

Assert

* REQUEST

"no

CT
in

response"

status on CMI,

NOREAD

Fig.

6-33

Figure

6-31

Flow

Diagram

(Sheet

CIPA

Transfer

CNFGR

Request

The
the
*

address offset on the CIPA (CIPA DATA <15:00>)* is applied to
DP

to enable

the

Bits CIPA DATA <15:12> are
insure
that
these
1lines
serve

function

the requested

the

function

that
added
are

to be

to the
not at

accessed.

12-bit offset address to
a tri-state level.
They

DP,

is a write operation

(negated READ from

function
register),
<continue
with
Paragraph
6.3.3.2,.
If the
requested
function
is
a
read
operation
(asserted
READ
from
function register), continue with Paragraph 6.3.3.4.

It
1is
seen
1in Figure 6-31 that when the unsolicited request was
sent
to
the
DP (REQUEST asserted), CIPA XFER was asserted which
enabled
a
CTO
(CIPA time-out) counter in the CCI control logic.
The
return of CIPA GRANT from the DP asserted GRANT and then SYNC
GRANT
which
1in
turn
negated REQUEST.
With REQUEST false, SYNC
GRANT
holds
CIPA
XFER
asserted thereby keeping the CTO counter
enabled.
The counter is incremented by B CLK and continues to run
until
SYNC GRANT is negated by the DP.,
The DP negates SYNC GRANT
after
it
has completed the unsolicited operation.
If the DP has
not
completed
its
read
or
write
of the selected register and
negated

CTO.
CNFGR

SYNC

CTO

GRANT within

1in

microseconds,

the

turn asserts SET CTO which sets

CTO

counter

asserts

the CTO bit

the

In addition, if this
the
true
state
of

is a read operation, the logic array (sensing
CTO)
negates
NS
BIT 3.
Negating NS BIT 3

releases
the
CMI
bus on the next B CLK and places status on the
CMI as shown in Figure 6-31.
In this case, the status bits placed
on the CMI bus will indicate a "no response".
If this is a write operation, the CMI bus would have
right after the write data was taken off the bus.
6.3.3.2

The

from

write

Write

the

already

operation

Receive Write

been

consists of transferring

Data

released

the write data

The CMI

bus has

released.

Figure 6-32

is a flow diagram of the

READ

the

from

to the DP.

been

flip—-flop E41
6-26).
The
logic.
With

function

"write DP"

operation.

"D"

input of

in the unsolicited decode and register logic (Figure
flip-flop is clocked by REQUEST from the CCI control
READ false, the flip-flop output (UNS READ) remains

false
resulting
in
a
negated CIPA READ sent to the DP.
The DP
interprets
the negated CIPA READ as a write command.
The DP then
returns the REG SEL code for a high word read of the Receive Write

Data

* READ
DP

written,

¥ UNS READ

§ CIPA READ
Write command to DP.

interprets

negated

CIPA

READ

write

command.

DP places REG SEL code on CIPA bus to read data
from Receive WNrite Data Register (Figs. S-14, S=20),

’ CIPA REG SEL <3:0>
REG SEL code
from Receive

read high

Write

Data

(low)

A R0 RCV WD REG HI (LO)

*.ccx RCV DATA <15:00>
High

(low)

word

read

out

Receive Write Data Register.,

A REG SEL O
Increment
read

Write

low

REG

SEL

word

from

Data

code

DP writes data longword
into selected register.

Receive

Figure

6-32

Write

Flow

word

Diagram

The

REG

SEL

decoder

1in

Receive

Write

code
the

(CIPA

CCI.

Data

The

REG

SEL

decoder

<3:0>)

applied

outputs

RCV

RD RCV WD REG

enables

from
the
register
onto
the CCI RCV DATA bus.
DATA
bus, the high word is transferred to the DP
as CIPA DATA <15:00>,

REG

the
HI

bits

read

the

<31:16>

From the CCI RCV
via the CIPA bus

The

DP accepts the data high word and increments the REG SEL code
to read the low word from the Receive Write Data Register,
The DP
increments
the
REG
SEL
code by asserting REG SEL 0 changing it
from a 0 to a 1 (see Table 5-10).

The
incremented
the
CCI
which
applied
to
the
<15:00> from the
RCV
DATA
bus
bus as CIPA DATA

REG
SEL code is returned to the read decoder in
outputs
RD
RCV
WD REG LO.
RD RCV WD REG LO is
Receive Write Data Register where it enables bits
register onto the CCI RCV DATA bus.
From the CCI
the low word is transferred to the DP via the CIPA
<15:00>.

The
DP then proceeds to
register to complete the

6.3.3.3
when the

write the data longword into
unsolicited write operation.

the

selected

Maintenance
1Initialize
(MIN)
-- A special case
MIN bit in the PMCSR in the DP is to be written.

When

ASSERT
DBBZ
asserts
command/address
bus
cycle

during

(Figure

occurs

the
bus
cycle following the
6-29), the command/address in

the hold register is examined by a SET MIN AND gate (Figure 6-26).
Address
bit
<K11:06> 0 and address bits <05:02> are examined.
If
the
address
bits
show the access is to the PMCSR (Figure 6-28),
and
the
commanded
function is a write (CMI bit 27 true), and if
the
PMCSR
MIN
bit
(bit
00)
1is being referenced (BUF CMI D 00
true), then SET MIN asserts.

SET
MIN
the
DP.
described

1initiates
an initialization sequence within the CCI and
The initialization sequence and the associated logic is
in Paragraph 5.12.2 and illustrated in Figures 5-25 and

6.3.3.4

Read

the

read

Data

from

data

6-33

The

the

read

DP,

transferring

the
1is

CMI,
a

and

consists

the

data

into

the

data

from

the

Return

releasing

flow diagram

operation

the

receiving

Return

Read

Data

CMI.

"read

DP"

operation.

READ
from
the
function
register is applied to the "D" input of
flip-flop E41 in the unsolicited decode and register logic (Figure
6-26).
The
flip-flop is clocked by REQUEST from the CCI control
logic.
With READ true, the flip-flop sets asserting UNS READ and
sending
an
asserted
CIPA READ to the DP.
The DP then reads the
selected register and places the high word of the read data on the

CIPA
Dbus along with the REG
Return Read Data Register,

SEL

code

for

high

word

write

the

6.4

CNFGR

The

CNFGR

adaptor

zeros

code.
supplied

The

CNFGR

from

the

the
13
T ACLO,

The
mux

contains

The

remaining
CMI mux.

the

written

information
T DCLO) are

bits
read

1information

bits

the

logic

assertion

(Paragraph

are writeable.
only.

CNFGR

bit

fields

are

shown

CNFGR

and

other

8-bit

WRITE

6.3.2.2).

The

CNFGR register is read by selecting it
and enabling the mux output to the CMI

The

the

bits

are

CNFGR
Only

three

(NO

ENA

CIPA,

as the input to the CMI
(Paragraph 6.3.2.3).

Figure

C-4

Appendix

C (Hardware
in
Figure
are

Registers),
The CNFGR register logic is illustrated
6-34,
The information bits and the 8-bit adapter code
described below.

6.4.1

Adapter

The
bus.

adapter
<code
1is
The
code number

via
+V
only.

pull-up

6.4.2

PDN,

Code

and

PUP,

ACLO

cabinet.

PDN

BUF

CMI

PUP/PDN
PUP
PUP

set

asserted.

the
NO

CCI

PUP

connections.

The

adapter

code

the

CMI

mux

read

flag indicating that
the assertion of SET

the port is powering
PDN which comes true

1n
the
CIPA
cabinet or in the host CPU
cleared by writing the CNFGR register with
PDN

initialize

also

cleared

SET

PUP

CLR

logic.

the

flag indicating that the system is powered up.
assertion of SET PUP which comes true when ACLO
the CIPA cabinet and the host CPU cabinet.
PUP
by
writing the CNFGR register with BUF CMI D 22

initialize

CIPA is a
NO
CIPA
1is
initialized.

CCI

in
both
cleared

a
by

asserted.

the

(power-up)

negates
can

from

that identifies the CI750 on
(hex) and is supplied by the

CIPA

asserts

can

ID
38

ground

PDN
(power—-down)
is
down.,
PDN
1is
set
whenever

an
is

also

cleared

SET

PDN

CLR

PUP/PDN

from

logic.

flag indicating
false
1if
the

Otherwise

the ready
CIPA
1is

CIPA

state of
present,

true.

complete
description
of the PDN, PUP,
given
in Paragraph 5.12.3 (Power Control
5-27, 5-28, and 5-29,

6-77

CIPA

the CIPA cabinet.
powered-up,
and

read

only,

and NO CIPA functions is
Function) and in Figures

|
|

]

—

| _BUE CMI D 23

_ucpmu

~1- FF

ary

l
l

SET_PYP

a
|

_BuF cMI D 22

—

Pup,

__ANO CIPA

" a

_T_DCLo

]

T FF

—IL_ACLQ

L%@ T‘ |

|: (F16 §-217)

PED

® prD
FF

BUE CML D 29¢

SET | NXM

__’an
°K FF

SET

BUE CMT D [7

(F!6.|5-Z)
Uce

[]duce
v FF

/FiG.

—(16-18
CRD

SET

E_CMI D I

_BUE CMT

|| CRP

K FF

—

DIAGNOS E

DIAGNO
SE

GS. 510

6-26

‘_")

{SEL‘-IQ(;\@ 6-18)
SET
>3

CTO

- »iC FF

cTO

(FI16. 6-14ASSERT_RLTO I3

BUF CMI P 19 = —

RLTO

Fi6. 5-2)

CBPE

DELAT
B cik
ED
|
UF CMI P

6)J¢R.LILC.N.E§.L.=.NA__J

FiG.

Note:

(FIG. 5-/®)

The logic in this tigure is contained

on sheet I of the engineering

drawings,

Figure

6-34

CNFGR

Logic

T ACLO,

6.4.3

PFD

T DCLO,

T ACLO (transmitted ACLO) and T DCLO (transmitted DCLO)
result
T
from a reset command issued by a remote node on the CI cluster.,
ACLO and T DCLO function to power down and power-up the host

T ACLO and T
system while leaving the CI75@8 port operational.
bits are read
Both
microcode.
port
the
by
cleared
and
set
are
DCLO
only.

PFD (power fail disable) asserts to inhibit T ACLO and T DCLO from
Thus
powering down the host system during maintenance testing.

diagnostics can check the T ACLO and T DCLO function without
PFD is set by writing the CNFGR
affecting the host system.
register with BUF CMI D @8 asserted.
PFD is cleared by writing
the

CNFGR register

with BUF CMI

D 08

negated.

A complete description of the T ACLO, T DCLO, and PFD functions is
given in Paragraph 5.12.3 (Power Control Function) and in Figure
6.4.4

NXM,

UCE,

CRD

and CRD
(uncorrectable error),
(non-existent memory), UCE
NXM
indicate status of a port initiated CMI
(corrected read data)
The CMI status bits are returned by the addressed nexus
transfer.

and applied to a status decoder in the CCI control 1logic (Figure
The decoder outputs SET NXM, SET UCE, or SET CRD if any of
6-18).
No output is asserted by the
these transfer errorg occurred.

decoder

for

error

free

transfer.

NXM indicates a "no response" by a nexus that was addressed by the
port.

NXM

decoder.

BUF CMI D

NXM

set

can be

the

20 asserted.

NXM

logic

the CS branching

assertion

cleared by

writing

asserts

SET

SET MSE

via

(Figure 4-10)

NXM

from

the

status

(memory system

error)

the CNFGR

the CIPA bus

with

(Figure

5-2).

UCE

indicates

returned

operation.

decoder.

uncorrectable

nexus

that

was

error

addressed

contained

the

port

the

for

data

read

UCE is set by the assertion of SET UCE from the status

UCE can be cleared by writing

the CNFGR register with

UCE asserts SET MSE to the
BUF CMI D 17 asserted.
CIPA bus (Figure 5-2).
the
via
4-1¢)
logic (Figure

CS branching

CRD indicates a correctable error occurred in the data returned by
CRD
a nexus that was addressed by the port for a read operation.
is

can

set by

the

cleared

asserted.

assertion

writing

SET

the

CRD from

CNFGR

the

status

with

decoder.

BUF

CMI

CRD

DIAGNOSE

6.4.5

DIAGNOSE asserts to place the CCI into the diagnostic maintenance
DIAGNOSE enables test logic for reading and
mode of operation.
so that diagnostic routines can check
registers
CCI
the
writing
hardware.

the CCI

out

DIAGNOSE
asserted.

is set by writing the CNFGR register with BUF CMI D 14
DIAGNOSE 1is cleared by writing the CNFGR register with

6.4.6

CTO

BUF CMI

D 14 negated.

CTO (CIPA time-out) indicates an unsolicited read or write of the
DP did not complete within 10 microseconds. CTO is set by the
assertion of SET CTO from the CCI control logic.

During an unsolicited read of the DP, the port holds CMI DBBZ
asserted on the CMI bus until the read operation is completed. If
the read operation is not completed within 10 microseconds, the
CCI control 1logic places a NXM status code on the CMI bus,
releases the CMI bus, and asserts SET CTO to the CNFGR register.

unsolicited

During

write

the DP, CTO indicates that the

write data taken off the CMI was not written into the DP.

CTO can be cleared by writing the CNFGR register with BUF CMI D 13
asserted.

description

A complete
6.3.3.1

of the CTO function is given in Paragraph

(CIPA Transfer Request).
RLTO

6.4.7

RLTO (read lock time-out) indicates that more than 1024 bus cycles
have occurred since a CMI nexus executed a read lock function
RLTO is set by the
without executing a write unlock function.
assertion of ASSERT RLTO from the GO/DONE logic (Figure 6-14).

when

logic

a CMI nexus executes a read lock function, the CI750 GO/DONE
1is

inhibited

from asserting GO until the nexus executes a

write unlock function. If a write unlock function has not occurred
(163.8 microseconds), ASSERT RLTO 1is
after 1024 bus cycles
asserted to the CNFGR register.

RLTO
19

can

be cleared by writing the CNFGR register with BUF CMI D

asserted.

RLTO

asserts SET MSE SYNC in the CS branching logic (Figure 4-10)

via the CIPA bus

A complete

(Figure 5-2),

description

Paragraph 6.2.2.2

(Issue GO).

the

read

1lock

function is given in

6.4.8

CBPE

(CIPA bus

during
to

CCI

a
or

parity

data
CCI

DP).

complete

CBPE

indicates

over

CBPE

the CCI parity logic.
register when BUF CMI
A

error)

transfer

description

CIPA

set

can

the

CCI

parity

Figure

5-10.

6.5

PARITY

GENERATION AND CHECKING

Chapter
5
along
(Paragraph 5.7 and
6.6

and

INITIALIZE

The

power

and

initialize

control

initialize

and

Figures

and

AND

the

DP
5-10).

described

power
5-25

within

the

parity

and

POWER CONTROL

functions

are

5.12.3,

checking

with
Figure

and

(CIPA

generation

error

either

assertion

cleared

5.7.4

Parity

write

has

occurred

direction
SYNC

the

(DP
from

CNFGR

asserted.

Paragraph

ERROR)

parity

bus

control
through

logic

given

CCI

described

checking

function

FUNCTIONS

power-up,

power-down, ACLO, DCLO,
Chapter
5
along with the DP
functions
(Paragraphs 5.12.2 and

5-30

inclusive).

APPENDIX

CI750
ACK

Acknowledge

ACLO

ADD

Address

ADDR

Address

ALT

Al ternate

ALU

Arithmetic

logic

ACK

receive

ARB

(state)

ARBC

Arbitration
Arbitration

ASRT

counter

Assert

ATTN

Attention

ACK

Bus

transmit

Bus

Branch
Bus

BTO

Boot

BUF

Ruffer

BUF

Buffered

request

timeout

Carry

CBPE

CIPA

CCI

CMI

bus
to

parity

CIPA

CDEST

Complement

CDET

Carrier

CIPA

CHAR

error

interface

destination

detect

error

CHK

Character
Check

Computer

CIPA

interconnect

Computer

(formerly

CLK

interconnect

Clock

port

CMD/ADDR
CMDADDR

Clear
Command

Command/address
Command/address

CMI

CPU

CMP

Compare

CNFGR

CNODE

IPA)

(state)

grant

CMD

ICCS

unit

CLR

GLOSSARY

low

ADR

memory

interconnect

Configuration
Complement

CNT

Counter

CNTL

Control

CNTR

Counter

COMP

Complementary

CRC

Cyclic

CRD

Corrected

CRY

Carry

Control

node

redundancy
read

store

check

data

MNEMONIC

adapter

and

Control store
Control store
CIPA time-out

CSA
CSPE
CTO

address
parity error

Data

DEL

Data bus
DC low
Delay

DET

Detector

PBBZ
DCLO

CFE

Decoded

DLY

Delay

busy

DLYD

Delayed

Done

Data path

DPUP

Decoded

DST

CMP

enable

file

(module)

push/pop

Destination
Destination

compare

coupled

logic

ECL

Emitter

Enable

ENA
ENB

Enable
Enable

ERR

Error

EXT

External

FCN

FPLA

Function
File enable
Flag
Field programmable

GEN

Generate

FLG

HDR

Header

High
Header

HTO

IB
IB

DST

SRC

bit

logic

time-out

Internal bus
IB destination
IB

source

ICCS

Intercomputer

IMUX

Input

INH

Inhibit

communications

Initialize

INT

Internal

INT

Interrupt

INTR

Interrupt

IPA

Interprocessor adapter
Input parity error

JMPR

Jumper

JSR

Jump

Load

Low

switch

mux

INIT

IPE

array

subroutine

(see

CI)

(see

CI)

Local

LSA

Local

store

LSB

Least

LSPE

significant

Local

store

Less

LTCHD

Latched

MADR

Maintenance
Maintenance

MAINT
MCLR

MDATR

store

address
bit

parity

address

MDECODER

Manchester

decoder

Manchester

encoded

MIE

Maintenance

MIF

Maintenance

MIN

Maintenance

MISC

CNTL

MLD
MLOAD

MLOOP

interrupt enable
interrupt flag
initialize

Miscellaneous
Miscellaneous control
Maintenance load
Maintenance

1load

Maintenance

loop

Message

MSB

Most

MSE

Memory

receive

(state)

significant
system

bit

error

MSG

Message

MTD

Maintenance

timer

Maintenance

error

MTE

Message

NACK

transmit

Negative
Next

N XM

Non-existent

(state)

Operation

state

OPE

Output

OVFL

Overflow

PAL

Programmable

Parity

Packet

PBIR

memory

parity

PAR

error

array

buffer

logic

(module)

Program

PDN

Power-down

counter

Parity

error

Phase

encoded

VLD

disable

acknowledge

Maintenance clear
Miscellaneous data
Maintenance data register

MISC

error

than

Power

fail

PFD

valid

Power

fail

PICR

disable

Port

PMCSR

initialize

Port

maintenance

PMTCR

Port

control/status

maintenance

timer

PMUX

Packet

PROM

buffer

Programmable

control

mux
read-only

A-3

memory

PROP

Propagate

PSA

Programmable

PSR

Port

status

release

PSRCR

Port

PUP

Power-up

PUP

Push/pop

Pulse

PWR

Power

QUAD

Quadword

starting

RAM

Random

Recelve

RBPE
RB UF

Receilve buffer
Receive buffer

access

memory

buffer

RCAR

Receiver

RCV

Receive

RCVD
RC VR

Received
Receliver

Re ad

Read

RDAT

Receilive

RDLCK

Read

parity

carrier

data

lock

REC

Receiver
Register

RINIT

Receive

RLTO

Read

(state)

lock

RSEL

RSVD

Reserved

RTN

Re turn

initialize

time-out

select

RTS

Return

RXMIT

Receive

S/D

Source/destination
Select
CC

error

data

REG

SEL

control

width

SEL

address

Select

from

subroutine

(state)

transmit

condition

SEQ

Sequencer

SRC

sSource

Time

code

ACLO

Transmitted

low

DCLO

Transmitted

low

TABORT

Transmit

(state)

TACK

Transmit

ACK
buffer
data

abort

TB UF

Transmit

TDATA

Transmit

TDEST

TINIT

True destination
Transmit (state)

Time-out

TPATH

Transmit
Trailer

TTL

Transistor-transistor

TXMIT

Transmit

initialize

path

(state)

A-4

logic

transmit

UBS

UNIBUS

UCE

Uncorrectable

UCODE

Microcode
Uninitialized

UNINIT

error

UNS

Unsolicited

UNSOL

Unsolicited

UWORD

Microword

VALDAT

Valid

VCDET

Virtual circuit descriptor
Valid receive data

VRD

data

WACK

wWait

Word

Write
Write

data
parity

for

ACK

enable

Wrong
Write

WRT

Write

XBIR

External

bus

XBOR

External
Transmit

bus output
buffer

XBUS

External

bus

XFER

Transfer

XBUF

table

XLATE

Translate

XMIT

Transmit

XTAL

Crystal

input

APPENDIX
FLOW

DIAGRAM

SYMBOLS

The flow diagram symbols used in this manual are defined in Figure
B-1.
Signal mnemonics are shown
in upper case.
All other flow
diagram text is in lower case.

tPWRFL

] THE SIGNAL PWRFL IS ASSERTED (UPPER CASE).

+PWRFL

] THE SIGNAL PWRFL IS NEGATED.

J X = DESCRIPTION OF AN EVENT OR ACTION (LOWER CASE),

LKk

FLOWDELAYED
UNTIL CLK ASSERTS.

IF CONDITION OR SIGNAL IS TRUE FLOW

CONDITION

FOLLOWS YES BRANCH, OTHERWISE FLOW

OR SIGNAL

FOLLOWS NO BRANCH.

ON PAGE CONNECTOR.

D
(

OFF PAGE CONNECTOR.
)

BEGINNING OR ENDING POINT OF A FLOW
DIAGRAM.

Figure

B-1

Flow

Diagram

Symbols

TK-6071

APPENDIX
HARDWARE

Appendix

description

accessed

registers

described

the

port

four

software

hardware

for

registers

maintenance

MADR

2,
3.

MDATR
PMCSR

---

Address Register
Maintenance Data Register
Port Maintenance Control/Status

CNFGR

Configuration

MADR

Maintenance Address

C.l

that

can

purposes.

are:

REGISTERS

be
The

Maintenance

Figure
C-1
1illustrates
the
function
of
the
MADR
bits.
The
register address = XXXXX014
(hex).
MADR contains the address of

the

only

control

the

store

location

uninitialized

accessed.

read

written

4.6.1,

and

4.7

for

state.

Refer
to
Figure
4-1
and
Paragraphs
discussion of MADR operation.

4.1,

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C.2

MDATR -- Maintenance Data Register

Figure C-2
illustrates
the MDATR bits.
The
register
address =
XXXXX018 (hex).
MDATR does not exist as a physical register.
A
read or write of MDATR will read or write the microword
in the
control store location specified by the address in the MADR.
When

MADR 12
MADR 12
<31:16>

= 0, MDATR <31:00> contains microword bits <31:00>.
When
= 1, MDATR <K15:00> contains microword bits <47:32> (MPATR
are
all
O0s).
MPDATR
is
read
or
written
only
1in
the
uninitialized state.

Figure 4-4
Figure

4-2

and

writing

the

control

and

Table 4-1

Paragraph
store.

define
4.4

the

for

a
\

microword

discussion

bits.
of

Refer

reading

and

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C.3

PMCSR -- Port Maintenance Control/Status Register

Figure

The

C-3

illustrates

hardware

address

error

flags,

the

function

XXXXX004

interrupt

bits,

the

PMCSR

XXXXX010.
and

bits.

PMCSR

contains

initialization

port

control

bits.

A description
Table 5-4,

the

PMCSR

bits

given

Paragraph

5.5.3

and

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C.4

CNFGR -- Configuration Register

Figure

C-4

illustrates

The

CNFGR

CI750

CMI

address =

the

function

the

CNFGR bits.

XXXXX000

contains

CI750

status

and

control

bits

and

the

code.

Table C-1 describes the CNFGR bit
6.4 for a more detailed discussion

functions.
Refer to Paragraph
of the CNFGR register.

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Table

Bit

Mnemonic

CBPE

PDN

CNFGR

CIPA

Bus

Parity

error

detected

data

Read

Power-Down:
PDN

PUP

Set

when

CCI

parity
CCI

the

port

set

the

assertion

cabinet or
is cleared

setting

Power-Up:

Set

PUP

when

set

the

powering
of

setting

PUP

bit.

the port is
ACLO negates

the

PDN

Read

powered
in both

Reserved.

NXM

Non-Existent

Memory:

when

initiates

CMI

and

RLTO

Set
transfer

receive

any

response

bit

Read

Lock

cycles

since

bit

nexus

(other

read

1lock

write

Reserved.

UCE

Uncorrectable

receives

Read

UCE

than

the

function

unlock

cleared

port
not

when 1024 CMI bus
(163.8 microseconds)

executing

RLTO

the
does

Set

occurred

CMI

executed

The
or

from the slave nexus.
cleared by writing a 1 to

Time-Out:

have

The
it.

NXM

upn.
the

bit.

ACLO

host CPU cabinet.
by writing a 1 to

CIPA
cabinet
and
host CPU cabinet.
PUP bit 1s cleared by writing a 1 to
by

Os.

Set
is

in the CIPA
The PDN bit
i1t

Error:

transfer.

Reserved.

down.,

Bits

Description

30:24

C-1

CI750)
without

function.

writing

The

it.

Error:

status

Set

from

when

the

CI750

slave

nexus

during a read operation.
UCE indicates an
uncorrectable
error
1is
contained
1in
the
read data returned by the slave.
The UCE
bit is cleared by writing a 1 to it.

Table C-1

CNFGR

Bit

Mnemonic

Description

CRD

Corrected

Bits

Read

receives
during a

(Cont)

Data:

Set

when

a CRD status from a
read operation.
CRD

correctable
error
occurred
data returned by the slave.
is cleared by writing a 1 to

Reserved.

Read

DIAGNOSE

Diagnose:
DIAGNOSE
is
set
to
place

CTO

CIPA

CI75%9

1in
the
read
The CRD bit
1t.

1s a control bit that
the
CI758
1into
the
maintenance mode of operation.

diagnostic
13

the

slave nexus
indicates a

Time-Out:

Set

when

read or write of the DP
within 10 microseconds.

did

unsolicited

not

complete

NO CIPA

NO CIPA:
present,
Otherwise

Cleared 1f the CIPA cabinet 1is
powered-up,
and
1initialized.
this bit is set.

Reserved.

Read

ACLO

Transmitted

DCLO

Set

the

powered

the

and

cleared

system

while

effect

power-up

CI750

ACLO:

microcode

port

host

powered

Power

that

from

Fail

set

down

host

These

bits

code.

ACLO

the

testing.

adapter

PFD

inhibit

code:

CMI

p—

Adapter

CI750

Disable:

powering

@]
!

———-

power-—-down
the
CI750

up.

maintenance

B7:09

keeping

Transmitted DCLO:
Set and cleared by the
port microcode.
Used in conjunctionwith
ACLO to effect a host system
and
power-up
while
keeping

PFD

the

and

up.

power-down

control
and

bit

DCLO

contain

the

system

during

Digital Equipment Corporation.Bedford, MA 01730