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EK-BDV11-TM-001

March 1978

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Document:	BDV11 Bus Terminator, Bootstrap, and Diagnostic ROM Technical Manual
Order Number:	EK-BDV11-TM
Revision:	001
Pages:	46
Original Filename:

OCR Text

BDV11 bus
term ina tor,

bootstrap, and

diagnost ic ROM

technical manual

BDV11 bus

terminator,

bootstrap, and
diagnostic ROM
technical manual

EK-BDV11-TM-001

digital equipment corporation - maynard, massachusetts

1st Edition, March 1978

Copyright © 1978 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:

DEC

DECtape

PDP

DECCOMM

DECUS

RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

CONTENTS

Page

CHAPTER 1

INTRODUCTION

1.1

MANUAL SCOPE......... ES PP
PR PP PPPPPPPPPPPPN 1-1

1.2
1.4

GENERAL DESCRIPTION.....ootiiiiiiiieeen
s reeiivvtrteee s e e e s snrenneeaeeeseesasnens 1-1
BD V11 SPECIFICATIONS.......ottiiiiiieiiiiiiereee
e ereeseennnrerreeees s sesereeneeesessssenens 1-3
RELATED PUBLICATIONS ...ttt
eccrrereeeee e
nerree e e e s s eesneeeeenes 1-3

CHAPTER 2

INSTALLATION

2.1

SCOPE ...ttt ettt teee e e e e s s rraerreeesesessssssstaaeeaaeaesessassassenteeeeesasesannen 2-1
PRELIMINARY STEP.......eieeeie
e ereeseceeevereeeeees
e s senaeeneeeeeeeeesennns 2-1
INSTALLING THE MODULE IN ABACKPLANE. ..o 2-1
MODULE PIN-OUTS AND LOGICDRAWINGS ..., 2-3

CHAPTER 3

OPERATION

3.1

SWITCHES AND INDICATORS ..ottt 3-1
POWER OK LED (D6), HALT/ENABLE Switch (S1), RESTART
Switch (S2), and BEVNT L Switch (Section 5 of E21).....ccooociiiiiinniiinnnne. 3-1
Diagnostic/Bootstrap SWitChes ..........cccoovviiviiiiiiiiiiiiii, 3-1
Diagnostic Light Display.......ccceeeeiiieiieiiiniiiiiiiiiiiias 3-1
HARDWARE REGISTERS .....ooiiiiteeee
ettt e rerrece s e snanns 3-1

1.3

2.2
2.3

3.1.1

CHAPTER 4

TECHNICAL DESCRIPTION

4.1

4.11

ADDRESSING ROM ON THE BDV11 MODULE ......cccoooviiiiiiiiiiiiininiiineeee 4-1
BDV11 BLOCK DIAGRAM ...ttt
ettt e ee e seinanste e e e e s sanns4-4
TRANSCEIVER/SWITCH REGISTER LOGIC ..., 4-6
CONTROL LOGIC....... ittt
ssinnnt s e et sse e s s s s een4-8
POWER-UPLOGIC ...
naaes4-12
ROM ADDRESS SELECTION LOGIC .......ccccoiiiiiiiiiiiniininniiiniieeec, 4-12
SOCKET SELECTION LOGIC.......ccoiiiiiiciiiitieeecn
e 4-16
ROM SOCKETS LOGIC ...ttt
iininsccs e cenavanais e 4-19
BEVNT LOGIC ...ttt
e ernrece e e eee e s csisbanseae s e s s s s ssaanssee s 4-19
DISPLAY LOGIC ........cieireiiirecviinteeseesecescerannnnnrnessessssseeesssssomerenersssenssnsnnnnnnns 4-19
READ/WRITE REGISTER LOGIC ........ccocoiiiiiiiiiiiiiiiccci i 4-23

APPENDIX A

ROM SPECIFICATIONS

4.2
4.3

4.4
4.5
4.6
4.7
4.8
4.9
A

F.aV

1ii

FIGURES

Figure No.

Title

Page

BD V11 MOQUIE.....ioiiiiiieiiieiiieicccier
e
rereraereseseseeaeseesaeanaaanens 1-2
Insertion and Removal of Modules Having Extractor-Type Handles..................... 2-2
BDV11 Switches and INdicators ............eueeeeieeiiemiiieiiieiiiiiierereeeeeeeeereneeeeneeeeeenen 3-2
Diagnostic Light Display.......ccccceeiiiiiiiiiiiiiieiiiiriieiieeieaiierrrereeseeeeereseesaeeseeeessanens 3-2
BD V11 Block Diagram ..........cccceiiiiiiiiiiiiiiiiieiiisieeeecerieenecsisrsssssessaseseessasessenssnnnns 4-5
Transceiver and Switch Register Logic, Bits 0-3 .........ccccooiiiiiiiiirininicereenieeceeneenen. 4-7

(070
418 o) I 0 -4 1R
UPRUPRP 4-9
Operation Sequence, DATO Cycle .......uuviiiiiiiiiieiiiiiiieeee
s reneeeee e 4-11
POWET-UP LOZIC....ciiiiiiiiiiiiiiieicerccereiees
e ceeceercir
e s e s e seeeseseeseeaeesesesss e naen 4-13
ROM Address Selection LOZIC..........cuvveiieriiiieciiiiieeereeeeeeenrnrereesesseesnsneeeeeeens 4-14
Address Bit SElECtION........uuuuuiereiiiiieeeiiieirereeererereereeeereetrereeeeee
e e seaesese s
eananes4-15
Socket Selection LOZIC......ccuuueuuiiiiiiiiereeie
et eeecrertreeee e e ee e e eeeeeeereeraas
s 4-17

Logic Block Diagram, ROM SocKets.......c.ccovieeriiiieiirierneieesccciereereenreereeeeeeeeens 4-20
System ROM JUMPETS.....ccouvuiiiiiiiriciiine
e ceeetrneericese e s e s eseseeeeeeeeereasnessnssesnnns 4-21
BEVNT LOZIC ..cccitiiiiiiiiiiiiiniiirieiieiteetetetireeteseereteetsensesteessreesssesssesasssssssnsnsnsnsnnsses 4-22
Display Logic/LEDsS DI-DA4..........cccoiiiiiiiiiiiiiiiiiicriices
e4-22
Read /Write RegiSter LOZIC........oceeieiiiiiiiiee

e 4-23

TABLES

Table No.

Title

Page

BD V11 SPecifiCations........ccuvireieieeiieiiiiiiieirieeteessrssiiireseeeesessssssenessesssssssssssseasess 1-3
BD V11 Bus Pin-Outs....ccoouueiiiiiiiieiiiiiceic
ettt
ceecevevr e vves e
sessnsaeaenens 2-3

Functions of the Maintenance Aids ............cvviiiiiiiiiiriiiiiiiiieeeeee
e eseesecssessesree s 3-3
BDV 11 Hardware REeISTETS ......uevviiiiiieiiieiiiiiiiiiiecceiee e 3-4
BDVI11 Bus Addresses/PCR Pages.........cccccouviiiiiiiiiiiiiiiiiiiieeccnece
e4-2
Functions Of ROM SOCKELS .......cceeeiiiiiiiiiiiiiiiiei
et
crere e e s s annaeee e 4-2
PCR Contents/Page Relationship, Pages 0—17............cooouiiiiiiiniiinniiniiccee, 4-3
PCR Contents, Pages 20-57, 200-377 .....ccoureiiiririiiriieiieriiiiieee
e eeeeevrieiee e eernnae e 4-4

DC004 Select QULPULS ...ccvveiiiiiieiieiiieieiieiieeee
e e e e eesereses
s ceveva raenes 4-10

DC004 Protocol Signals.........cceceeeeieiiiiniiiiiiiiii
e 4-10
e 4-10

DCO004 Byte Signals.......ccuvverriiiiiiimiiiiiiiiiiirceiiee

BDV11 Selection Signals/SOCKEts......ccuvveeieiriiieeiiiiiiieeceeee

e 4-18

CHAPTER 1
INTRODUCTION

1.1

MANUAL SCOPE

The BDV11 is an LSI-11 bus option that provides both 120-ohm terminations for LSI-11 bus signal
lines and diagnostic aids that help a user to determine the operating condition of his system. The
BDV11 module can be equipped with a variety of read-only memories (ROMs) to provide the user

with bootstrap and additional diagnostic capabilities; in such a case, a new option designation is
assigned, e.g., BDV11-AA.

This manual gives a technical description of only the BDV11 module. Each variation of the BDV11is
described in a user manual that pertains only to that variation. The reader should be familiar with the
LSI-11 microcomputer and its peripheral equipment. The necessary information can be obtained from
the 1977-1978 Microcomputer Handbook* published by DIGITAL.

1.2

GENERAL DESCRIPTION

The BDV11 logic components are mounted on a 26.7 X 21.6 cm (10.5 X 8.5 in) quad-height printed
circuit board (Figure 1-1) that can be inserted in any LSI-11 bus quad backplane. Physical space on the
module is reserved by DIGITAL for 4K words of ROM; this ROM space contains diagnostic and
bootstrap programs for a number of system components. Furthermore, user-available space is furnished on the module for 2K words of eraseable, programmable ROM (EPROM) and 16K words of
ROM or EPROM. This 18K of user ROM can be executed directly or loaded into ROM for later
execution; all ROM is mapped into only 256 words of LSI-11 I/O address space.

The BDVI11 contains switches that permit the user to choose diagnostic and bootstrap programs for
execution and a diagnostic light display that indicates failures in these programs. In addition, the
BDV11 module is equipped with a green LED that monitors dc power, two test points for the dc
power, a HALT/ENABLE switch that allows the user to force the CPU into the halt mode, and a
RESTART switch that enables the user to re-boot the system. All of these controls are edge-mounted.
? switch mounted in the interior of the module permits control of the LSI-11 line-time clock (LTC)
unction.

*See Paragraph 1.4 for ordering information.

1-1

9036-3BW-A0043

Figure 1-1

BDV11 Module

1-2

1.3 BDVI11 SPECIFICATIONS
The specifications listed in Table 1-1 are for informational purposes only and are subject to change
without notice.

Table 1-1

BDVI11 Specifications

Specification

Item

Physical Characteristics
Length (without handles)
Height (without handles)
Depth

26.7 cm (10.5 in)
21.6 cm (8.5 in)
1.27 cm (0.5 in)

Electrical Characteristics

BDVI11 Module Type

MR012

Power Requirements

+5Vdc @ 1.6 A (max)
+12 Vdc @ 0.07 A (max)

LSI-11 Bus Loading

2 ac unit loads

Environmental Requirements

Operating Temperature*

5°-50° C (41°-122° F)

Operating Humidity

10-95%, with a maximum wet bulb temperature of 32° C (90° F)
and a minimum dew point of 2° C (36° F)

* The maximum allowable operating temperature is based on operation at sea level, i.e., at 760 mm Hg (29.92 in
Hg); maximum allowable operating temperature must be reduced by a factor of 1.8° C/1000 m (1.0° F/1000
ft) for operation at higher altitudes.

1.4

RELATED PUBLICATIONS

Information that is useful to the BDV11 user can be found in the following DIGITAL publications.
Publication

Document Number

Remarks

BA11-N Mounting Box
Technical Manual

EK-BA11IN-TM-001

In microfiche library;

BA 11-N Mounting Box
User’s Guide

EK-BA1IN-UG-001

Available in hard copy

Microcomputer Handbook,
1977-1978 (2nd Edition)

EB-07948-53/77

Available in hard copy

PDP-11 Software Handbook

EB-08127-20/70

Available in hard copy

1-3

available in hard copy

also

For information concerning microfiche libraries, contact:
Digital Equipment Corporation
132 Parker St.
Maynard, MA 01754
Attn:

Micropublishing Group
(PK3-2/T12)

Hard copy documents can be ordered from:
Digital Equipment Corporation
444 Whitney St.
Northboro, MA 01531
Attn:

Communications Services (NR2/M15)
Customer Services Section

1-4

CHAPTER 2

2.1 SCOPE
This chapter describes the steps to take
before installing the BDV11 in a backplane and tells how and
where to install the module. Detalled information concernmg the 1nstallat10 of LSI-11system components can be found in the reference publications listed in Paragraph 1.4. Refer to the specific
BDV11-variation user manual for procedures that check for correct system operation after the installation.

2.2 PRELIMINARY STEP
A number of switches on the module must be set before the module is inserted in the backplane. The

diagnostic/bootstrap switches are used for maintenance and system configuration; the BEVNT switch
is used to select the mode of control of the LSI-11 bus BEVNT signal. The location of these switches is
shown in Figure 3-1; their operation is described in Paragraphs 3.1.1 and 3.1.2. Ensure that the
switches are in the desired positions before installing the module.
2.3 INSTALLING THE MODULE IN A BACKPLANE
The BDV11 can be inserted in any LSI-11 quad backplane. In multiple-backplane systems the module
must be inserted in the last backplane of the system. When inserting the module, make sure the power

is turned off. Connector A of the module is inserted in connector A of the backplane (connector A on
the module is the right-most connector when viewing the component side of the module with the
connector fingers pointing down; connector A on the backplane is on the left side when viewing the
slot side of the backplane). The LSI-11 bus signals will appear on module connectors A and B.
The BDV11 is equipped with metal extractor-type handles that facilitate module insertion and removal. When inserting such a module into the backplane, begin by sliding the module, component side

up, into the card guides. Slide the module all the way in and just start the module connector fingers
into the backplane connectors. Fit the prongs of the handles into the holes in the card frame (Figure 21). Press in on both handles simultaneously to fully insert the fingers in the backplane connector.
To remove the module, pull both handles out simultaneously until the prongs of the handle are clear of

the holes in the card frame. The module fingers will now be nearly free of the backplane connector and
the module can be removed easily.
CAUTION
The module and/or the backplane assembly might be
damaged if the module is inserted or removed with
the power on or if the module is inserted upside down.

2-1

TO REMOVE MODULE

HANDLE PRONGS

-—

EXTRACTOR-TYPE HANDLE

TO INSERT MODULE

—

}

COMPONENT SIDE OF
MODULE

MODULE

]
CONNECTOR—
FINGERS

NOTE:

VIEW IS FROM THE TOP

OF THE CARD FRAME, LOOKING
TOWARD THE REAR OF THE

BACKPLANE CONNECTOR

UNIT.

MA-1339

Figure 2-1

Insertion and Removal of Modules Having
Extractor-Type Handles

2-2

2.4

MODULE PIN-OUTS AND LOGIC DRAWINGS

The M8012 print set includes logic drawings. Signal names in the iogic drawings have the following

form.
IGNAI

RITY

QURCE

SOURCE indicates the particular sheet of the drawings where the signal originates. SIGNAL NAME
is the proper name of the signal; the names used in the drawings are also used in this manual. POLARITY is either H or L to indicate the voltage level of the signal when asserted: H & +3 V; L = Ground.
As an example, the signal SH2 REG L originates on sheet 2 of the drawings and means when REG is
true, this signal is at approximately ground level.

LSI-11 bus signal lines do not carry a SOURCE indicator. These names represent a bidirectional wireORed bus. As a result, multiple sources for a particular bus signal exist. The LSI-11 bus signal names
begin with a “B” for “bussed.” The bus pin-outs for the BDVI11 are listedin Table 2-1.

Table 2-1

BDV11 Bus Pin-Outs

Mnemonic

+5
+5
+12
BBS7L
BDALOL
BDAL 1L

AA2
BA2
AD?2
AP2
AU2
AV?2

BIAKI L*
BIAK O L
BINIT L
BDMGI L*
BDMGO L*
BIRQL

AM?2
AN?2
AT2
AR2
AS2
AL2

BDAL2L
BDAL3L
BDAL4L
BDALSL
BDALG6L
BDAL7L
BDALSL

BE2
BF2
BH2
BJ2
BK2
BL2
BM2

BRPLY L
BSYNCL
BDCOKH
GND
GND
GND
GND

AF2
AJ2
BA1
AC2
ATI1
BC2
BTI

BDAL I10L
BDALI11L
BDAL 12 L

BP2
BR2
BS2

MSPARE B(EXT R CLK)

AL1
BK1+
BL1

BDAL 13 L
BDAL 14L
BDAL15L
BDIN L
BDOUTL

BT?2
BU?2

SSPARE 4
SSPARES

BCl1
BDI1

BV2
AH2
AE2
AP1

SSPARE 6
SSPARE 7
SSPARE 8 (EXT T CLK)

BEI1
BF1
BH1

BDALO9L

BHALTL
*

BN2

These signals are not bussed; they are daisy-chained.

+ This jumper is wired on the backplane.

MSPAREA (-12V)

AKl1t ::]

CHAPTER 3

OPERATION

3.1

SWITCHES AND INDICATORS

[Paniy

There are two lever switches {S1 and S2) and five LEDs (D1-D4 and D6) mounted on the front edge of
n
on the interior of the
the BDV11 module, and two dip-socket switch units (E15 and E21) mounted
module. These components are identified in Figure 3-1 and described in the following paragraphs.

3.1.1

POWER OK LED (D6), HALT/ENABLE Switch (S1j, RESTART Switch (S2), and BEVNT L

Switch (Section 5 of E21)

These components are maintenance aids. Table 3-1 describes the function of each component.
3.1.2

Diagnostic/Bootstrap Switches

3.1.3

Diagnostic Light Display

The dip-socket switch units, E15 and E21, are used with BDV11 variations. The switches, except
switch S of E21, allow the user to select diagnostic programs and/or a bootstrap program that run
automatically when power is turned on or when the system is re-booted. (Refer to the appropriate user
manual for details.) The 12 individual switches comprise the switch register, which can be read at bus
address 177524. (Table 3-2 includes a description of this register and its function in the BDV11.)

The diagnostic light display is used primarily with BDV11 variations. In these applications, the display
indicates the area of failure of a diagnostic or bootstrap. Figure 3-2 illustrates the left front edge of the
module (as viewed from the rear of the mounting box), showing the five LEDs that comprise the
display. D6 is the POWER OK LED, which is lighted when the +12 Vdc and +5 Vdc supplies are
operating correctly and which indicates the octal point for the display value. Refer to the appropriate
user manual for information.

3.2

HARDWARE REGISTERS

The BDV11 contains six hardware registers. These are listed in Table 3-2, together with a functional
description of each.

3-1

HALT « ENABLE

i3 a2

00 [ 7] fesrae U0
SWITCH

SWITCH | D1 D2 D3D6D4

OFF

3
4

___ 5
6
7

OFF

3
4

Ei5

(DIAGNOSTIC/BOOTSTRAP

\ CONNECTOR 4

(DIAGNOSTIC/BOOTSTRAP

SWITCHES, BEVNT SWITCH)

SWITCHES)
MA-1340

Figure 3-1

BDVI11 Switches and Indicators

D4 D6 D3 D2 D1

00000

[=1 =1,
/
MA-1341

Figure 3-2

Diagnostic Light Display

Table 3-1

Functions of the Maintenance Aids

Component

Function

POWER OK LED

This green LED is lighted when the +12 Vdc supply voltage is greater
than +10 V and the +5 Vdc supply voltage is greater than +4 V. The
+12 Vdc voltage and the +5 Vdc voltage can be measured at the tip
jacks as indicated below. (Both J2 and J3 have a 560-ohm resistor in
series to prevent damage from a short circuit; use at least a 20,000ohm/V meter to measure the voltage.)

J1
J2
J3

Black
Red
Purple

Ground
+5Vdc
+12Vdc

Secondarily, the LED indicates the octal point for the diagnostic
light display (Paragraph 3.1.3).
HALT/ENABLE Switch

When this switch is in the ENABLE position, the LSI-11 CPU can
operate under program control. If the switch is placed in the HALT
position, the CPU enters the halt mode and responds to console
ODT commands. While in the halt mode, the CPU can execute single
instructions, facilitating maintenance of the system. Program control
is re-established by returning the switch to the ENABLE position
and entering a “P” command at the console terminal (providing the
contents of register R7 were not changed). Refer to Chapter 2 of the
1977-1978 Microcomputer Handbook for a description of console
ODT command usage.

RESTART Switch

When the RESTART switch is cycled, i.e., moved from one side to
the other and back, the CPU automatically carries out a power-up
sequence. Thus, the system can be re-booted at any time for maintenance purposes.

BEVNT L Switch

Contact 5 of dip-socket switch E21 is the BEVNT L switch. When the

switch is off (open) the LSI-11 bus BEVNT L signal can be controlled
by the power supply-generated LTC signal. When the switch is on
(closed), the LTC function is program-controlled; i.e., a single-bit,
write-only register in the logic (address 177546, bit 6) clamps BEVNT
L low when the register is cleared. (The register is automatically
cleared when the power is turned on or when the RESTART switch is
cycled.) The KW11-L line-time clock option also uses bit 6 as the
enable bit.

Table 3-2

BDV11 Hardware Registers

Size

Function

Bus Address

Page Control Register
(PCR)

16 bits

Controls mapping of ROM
pages into physical ROM ad-

177520 (word or byte addressable; can be read or
written)

dresses. Cleared when power is
turned on or when RESTART
switch is activated.

Read/Write Register

16 bits

Maintenance register used for diagnostics. Cleared when power is
turned on or when RESTART
switch is activated.

177522 (word or byte addressable; can be read or
written)

Switch Register

12 bits

Used for maintenance and system configuration (selects diagnostic and/or bootstrap
programs for execution). Bits
0-11 of the register (corresponding to E15-1 through E15-8 and
E21-1 through E21-4, respectively) are associated with BDAL
<0:11> L, respectively; when an
individual switch of the register
is closed (on), the corresponding
BDAL signal is low (1).

177524 (read-only register)

Display Register

4 bits

Controls the diagnostic light display. Bits 0-3 of the register control LEDs D1-D4, respectively;
when a bit is set, the corresponding LED is off. Cleared (all lights
on) when power is turned on or
when RESTART switch is activated. -

177524 (word or byte addressable; write-only register)

BEVNT Register

1 bit

When cleared, this register
clamps the BEVNT signal low (if
the BEVNT switch is closed).
This action permits program
control of the LSI-11 line-time
clock (LTC) function. Register
cleared when power is turned on
or when RESTART switch is activated.

177546 (word or byte addressable; write-only register)

3-4

CHAPTER 4
TECHNICAL DESCRIPTION

4.1

ADDRESSING ROM ON THE BDV11 MODULE

A block of 256 LSI-11 bus addresses is reserved for use in addressing ROM locations on the BDV11
module. This block resides in the upper 4K address bank (28K-32K), which is normally used for
peripheral-device addressing, and consists of byte addresses 173000173776 (512 byte addresses correspond to 256 word addresses in the LSI-11 addressing scheme).

The BDV11 logic enables all 2048 locations in a selected 2K ROM (or 1024 locationsina IK ROM) to
be addressed by just these 256 bus addresses. The logic includes a page control register (PCR) at bus
address 177520; the contents of this read /write register determine the specific ROM location that is
accessed when one of the 256 bus addresses is placed on the BDAL lines. The PCR is loaded with
“page” information, i.e., the PCR contents point to one of 16 (or one of 8) 128-word pages in the
seiected ROM (i6 pages X 128 words = 2048 words). To illustrate, if the PCR contents represent
pages 0 and 1, bus addresses 173000-173776 access ROM locations 0000-0377; if the PCR contents
represent pages 10 and 11, bus addresses 173000-173776 access ROM locations 2000-2377. Table 4-1
relates bus addresses, PCR pages, and ROM locations.

At the top of each column of PCR pages in Table 4-1 appear two circuit component designations;
column 1, for example, is headed by E53/E48. These designations represent the ROMs and EPROMs
that one might find on a BDV11 module. For instance, the BDV11-AA is supplied with 2K words of
diagnostic ROM. The ROM inserted in socket XES53 supplies the high byte (bits 8-15) of these 2K
words, while the ROM inserted in socket XE48 supplies the low byte (bits 0-7). To access the BDV11
diagnostic ROM locations, the user must load the PCR with the pages in column 1; thus, when 12 and
13, for example, are loaded in the PCR, diagnostic ROM locations 2400-2777 can be addressed by the
LSI-11 BDAL signals. Another variation of the BDV11 could have 1K-word EPROM:s inserted in
sockets XE57/XE40 (E57 supplies the high byte, while E40 supplies the low byte). To access these
EPROM locations, the user would load the PCR with pages in column 3; thus, with 44 and 45 in the
PCR, EPROM locations 1000-1377 are accessible.
As Table 4-1 implies, the PCR pages are assigned to specific module ROM sockets. Furthermore, the
sockets are assigned specific kinds of ROM:s, as indicated in Table 4-2; e.g., the diagnostic/bootstrap
ROM can occupy only sockets XE53 and XE48. Thus, a specific ROM can be addressed only when the
PCR contains the page or pages assigned to the socket that the ROM occupies. To illustrate, if 2K
ROMs are inserted in sockets E39 and ES0, they can be addressed only when the PCR contains pages
360-377. The page/socket assignments indicated in Table 4-1 apply to the BDV11 module shipped by
DIGITAL. There are eight locations on the BDV11 printed circuit board in which jumpers are inserted
selectively to achieve these assignments. It is possible to change the factory arrangement of these
jumpers; by doing so, the user can cause the CPU to execute instructions directly from a ROM or
EPROM of the user’s choice when power is turned on, rather than from the diagnostic ROMs. Paragraph 4.7 describes the jumpers in detail and shows how they can be rearranged.

4-1

Table 4-1

BDV11 Bus Addresses/PCR Pages

PCR Pages

Bus Address

ROM

ES3/| ES8/| E57/ |E52/| E54/|ES9/|E60/| ESS5/| E51/| E47/|E43/|E39/| Location
E48 |E44 | E40 |E36 |E49 |E45 |E41 |E37 | E38 |E42 |E46 |ES0 | Accessed

173000-173376 | 0
173400-173777 | 1

|20
|21

|40
|41

[50
|51

200
|201

|220
|221

{240
{241

{260
[261

|300
|301

|320
|321

|[340
|341

360
|361

|0000-0177
|0200-0377

173000-173376 | 2
173400-173777 | 3

|22
|23

|42
|43

|52
|53

202
[203

|222
|223

|242
243

|262
263

|302
|303

|322
|323

|342
|343

|362
|[363

|0400-0577
|0600-0777

173000-173376 | 4
173400-173777 | 5

|24
|25

|44
|45

|54
|55

204
|205

224
|225

|244
|245

|264
265

|304
|305

|324
|325

|344
|345

|364
|365

|1000-1177
|1200-1377

173000-173376 | 6
173400-173777 | 7

(26
|27

|46
|47

|56
|57

[206
|207

{226
|227

|246
|247

266
|267

|306
|307

|[326
|327

|346
|347

|366
|367

|1400-1577
|1600-1777

173000-173376 | 10
173400-173777 | 11

|30
|31

210
211

|230
|231

250
251

270
|271

(310
[311

{330
|331

|350
|351

[370
|371

|2000-2177
|2200-2377

173000-173376 | 12
173400-173777 | 13

|32
|33

212
213

{232
233

252
253

272
273

|312
{313

|332
333

(352
|353

|372
|[373

|2400-2577
|2600-2777

173000-173376 | 14
173400-173777 | 15

|34
|35

214
215

234
235

254
255

274
275

|314
|315

|334
|335

|354
|355

(374
|[375

|3000-3177
|3200-3377

173000-173376 | 16
173400-173777 | 17

|36
|37

216
217

236
1237

|256
257

276
277

|316
317

|336
337

|356
|357

|[376
|377

|3400-3577
|3600-3777

Table 4-2

Functions of ROM Sockets

Sockets

ROM Function

Sockets

ROM Function

XE53/XE48
XES58/XEA44

2K Diagnostic/Bootstrap
2K Diagnostic/Bootstrap

XE47/XE42
XES51/XE38

2K System ROM
2K System ROM

(reserved for DIGITAL)

XE55/XE37

2K System ROM

XES57/XE40

1K EPROM

XE60/XE41

2K System ROM

XES52/XE36

1K EPROM

XES59/XE45

2K System ROM

XE39/XE50

2K System ROM

XE54/XE49

2K System ROM

XE43/XE46

2K System ROM

The PCR is a 16-bit register comprising two 8-bit bytes. The low byte consists of bits 0-7, while the
high byte consists of bits 8-15. When page 6, for instance, is loaded into the low byte of the PCR, bus
addresses 173000-173376 access the 128 ROM locations in the block 1400-1577. When a bus address
falls in this range, the logic considers only the low byte of the PCR. On the other hand, if a bus address
is in the range 173400-173777, only the high byte of the PCR is used to seiect the ROM location.

Table 4-3 relates the PCR contents to the PCR page for pages 0-17. As an example, if the PCR is
loaded with data 000400, the PCR low byte contains data 000, while the high byte contains data 001.
The PCR bytes can be loaded separately. To select ROM locations 1600-1777, for instance, one only
needs to load the PCR high byte with page 7; thus, the high byte contains 007, while the low byte can
contain anything. Table 4-4 lists the PCR contents for the remaining PCR pages.

Table 4-3

PCR Contents/Page Relationship, Pages 0-17

PCR Contents

PCR Page

000400

001402

002404

003406

004410

005412

006414

007416

PCR High Byte

(Bits 15-8)

PCR Low Byte

(Bits 7-0)

000
001

002
003

004
005

006
007

010
011

012
013

014
015

016
017

Table 4-4

Page

Contents

20, 21
22,23

PCR Contents, Pages 20-57, 200-377

Page

Contents

Page

Contents

010420

240, 241

120640

340, 341

160740

011422

242,243

121642

342, 343

161742

24,25
26, 27
30, 31

012424
013426
014430

244, 245
246, 247
250, 251

122644
123646
124650

344, 345
346, 347
350, 351

162744
163746
164750

32,33
34, 35
36, 37

015432
016434
017436

252,253
254,255
256, 257

125652
126654
127656

352,353
354, 355
356, 357

165752
166754
167756

40, 41
42,43
44, 45
46, 47

020440
021442
022444
023446

260, 261
262,263

50, 51
52,53

024450
025452

54, 55
56, 57

026454
027456

264, 265
266, 267
270, 271
272,273
274,275
276, 277

130660
131662
132664
133666
134670
135672
136674
137676

360, 361
362, 363
364, 365
366, 367
370, 371
372, 373
374, 375
376, 377

170760
171762
172764
173766
174770
175772
176774
177776

200, 201
202, 203
204, 205
206, 207
210, 211
212,213
214, 215

100600
101602
102604
103606
104610
105612
106614

300, 301
302, 303
304, 305
306, 307
310, 311
312,313
314, 315
316, 317

140700
141702
142704
143706
144710
145712
146714
147716

216, 217

107616

220, 221
222,223
224,225
226, 227

110620
111622
112624
113626

230, 231
232,233
234,235
236, 237

114630
115632
116634
117636

320, 321
322,323
324, 325
326, 327
330, 331
332,333
334, 335
336, 337

150720
151722
152724
153726
154730
155732
156734
157736

4.2 BDVI11 BLOCK DIAGRAM
Figure 4-1 shows a block diagram of the BDV11 logic. The DCO00S5 transceivers monitor the LSI-11 bus
BDAL lines. When an address in the upper 4K bank of bus addresses is placed on the BDAL lines, the
transceivers gate the address information onto the BDV11 DAL lines. If the address is one of those

assigned to the BDV11 (173000-173777, 177520, 177522, 177524, 177546), the transceivers generate
ADDRESS MATCH signals. These signals cause the control logic to decode the bus address and to
respond to the protocol signals that effect bus data transfers.

BHALT L
BREPLY L =

BRPLY L —————»
RUN/HALT

SW —8

RESTART SW ————»

POWER-UP
LOGIC

—* DC NOK L/H

BDCOK H
BSYNC L

——

SYNC L/H

BWTBT L

——

BRPLY L

BDOUT L
BDIN L

CONTROL

SYNC L/H ————»

LOGIC

DAL <0:2> H ——»

|—
& INWD
— L

——» REG L/H
> OUT LB/HB L

—» SEL 0/2/4/6 L

ADDRESS
MATCH

]

R<0:15> H

BDAL <0:15> L «—»

DCOOs
TRANSCEIVER

DAL <0:15> H

ADDRE

A<10:14> H

SELECTION

BBS7 L—»

DATA

UUREI

SELECTION

DATA

LOGIC

INWD L

XMIT H

SWITCH

READ/WRITE

REG

SEL4 L

SELO L

REG L

OUT LB/HB L

A<0:10> H

ROM

SOCKETS

520155 H

EEA?THH

SEL2 L

REG L

REG L/H

INWD L

XMIT H

OUTLB/HB L

SB<L1:2> L
SE<1:2> L

BEVNT Le—

ST<1:2>

DAL6 H

—>

BEVNT

LOGIC

BEVNT

DAL<L0:3> H—»

DISPLAY
LOGIC

SEL6 L

SEL4 L

REG L

DIAGNOSTIC
DISPLAY

SP<1:8> L

D1-D4

MIT e

VUV

LD
-

Figure 4-1

BDV11 Block Diagram

The bus address placed on the BDAL lines can be the address of one of the BDV11 registers, or the
address of a ROM location. If one of the registers has been addressed, the control logic asserts those
signals that are necessary to carry out the operation directed by the protocol signals that follow. For
example, if the 16-bit read/write register is addressed, the control logic asserts the signals that permit
the register to be either read or written. When the actual transfer of data takes place, the information is
gated to or from the register on the DAL lines in response to the protocol signals.

If the bus address is that of a ROM location, the address is loaded into the ROM address selection
logic. This logic includes the PCR, which contains page information previously loaded by a writing
operation into the PCR. The address selection logic decodes the address and asserts relative address
signals (A0 H - A10 H) that are applied to all the ROM sockets. Other address signals (A1I0 H - A14
H) are applied to the socket selection logic; this logic generates signals that select the particular ROM
identified by the PCR page information. This ROM responds to the relative address signals and places
the data in the addressed location on the O<0:15> H lines. The data is then gated onto the DAL lines
by the data selector and placed on the BDAL lines in response to the protocol signals.
The data selector is also used when the PCR is read. When this operation is executed, the PCR page
information carried on the R<0:15> L lines is gated onto the DAL lines and from those lines to the

bus.

All the foregoing logic blocks are described in detail in the following paragraphs. The power-up logic,
the BEVNT logic, and the display logic (all of which are self-descriptive, functionally) are also discussed. For detailed information concerning bus transfer operations, refer to the 1977-1978 Microcomputer Handbook.

4.3

TRANSCEIVER/SWITCH REGISTER LOGIC
Figure 4-2 shows the transceiver/switch register logic for bits 0-3. The DCO005 transceiver is a bidirectional buffer between the LSI-11 data/address lines, BDAL <0:15> L, and the BDV11 data /address
lines, DAL <0:15> H. The transceiver also provides a constant generator (which is used for selecting
BDVI11 diagnostic and bootstrap addresses) and comparison circuits for address selection.

The transfer of information between the BDAL lines and the DAL lines is controlled by signals XMIT
H and INWD L, which are generated in the control logic in response to the LSI-11 bus protocol
signals. XMIT H and INWD L are related to bus transfer cycles as follows.
INWDL

XMITH

Bus Transfer Cycle

LO
LO

LO
HI

No transfer (DAL and BDAL lines open)
DATI (DAL-BDAL)

}

DATO/DATOB (BDAL-DAL)

Information can also be put on the BDAL lines by the transceiver JAV inputs. These three inputs drive
three bus lines directly, overriding the XMIT H and INWD L control signals (JAV3,JAV2, and JAVI
are paired with BUS3, BUS2, and BUSI, respectively, in each DC005). A high input causes a low to be
transmitted on the corresponding bus line, while a low or open input causes an open condition to occur
on the bus line. The JAV inputs allow the user to read the contents of the switch register and are
related to the BDAL<0:2> L signals as follows.

JAV3 (HI/LO-OR-OPEN)

JAV2 (HI/LO+OR-OPEN)
JAV1 (HI/LO-OR-OPEN)
*

BDALOL

BDALIL

BDAL2 L

(LO/OPEN)*
-

(LO/OPEN)

When JAV3, for example, is high, BDALO L is low; when JAV3 is low or open, BDALO L is open.

4-6

BDALO L
BDAL1 L
BDAL2 L
BDAL3 L

8 QlBUS3
3 Q|BUS2
olsust
N
120 BUSO

192

+5V

DAT3
DAT2
DAT1 17
DATO 18

yiaTCH
DCOO5
E19

lias
JA2

DALO H
DAL1T H
DAL2 H
DAL3 H
ADDRESS MATCH

1A
QO MENB

161 jav3
151 ,av2

14 JAV1

XMIT

REC

XMIT H

INWD L
E15

A3
A2

2
1

+5V

REGL ——Q)
SEL4 L —
Q)

INWD L——CO
MA-1343

Figure 4-2

Transceiver and Switch Register Logic, Bits 0-3

4-7

The JA inputs of the transceiver are part of the comparison circuits. When the signal state at a JA
input is the same as that at the corresponding bus line, a match exists. If three matches exist, and if the
MENB L signal is low, the MATCH output of the DC005 is open-circuited. This open-collector
output permits more than one transceiver output to be wire-ANDed, thereby forming a2 composite
address match signal. The relation between the JA signals and the BDAL signals, and between
MENB
L and MATCH H is shown below.

JA3 (GROUND/OPEN)
JA2(GROUND/OPEN)
JA1(GROUND/OPEN)

4.4

BDALOL

BDALIL

BDAL2L

LO/HI
-

LO/HI

MENBL

JA-BDAL Match

MATCHH

HI1
LO
LO

All 3 match
All 3 match
One mismatch

LO
OPEN
LO

CONTROL LOGIC

The control logic (Figure 4-3) includes a DC004 protocol chip (E8) and an 82523 PROM (E9). The
PROM monitors LSI-11 bus addresses via the DCO0OS transceivers and generates two important signals. One of these, at output DO(1) is asserted (high) when the address of any of the BDV11 registers is
placed on the bus. The other, at output D1(1), is also asserted when a register is addressed; furthermore, this output is wire-ANDed (at A) with two signals from transceiver E17 (MATCH and DAL12
H) to produce an enabling signal when any one of the assigned bus addresses (173000-173777) is
placed on the BDAL lines.

This enabling signal is applied to the DC004 ENB input, allowing this chip to generate signals that
select the BDV11 registers for data transfers (SELO L, SEL2 L, SEL4 L, and SEL6 L). The DC004 also
generates the protocol signals that permit data transfers to take place. Tables 4-5, 4-6, and 4-7 relate
the inputs and outputs of the DCO004.

As an exampie of the controi logic operation, consider the foliowing description. Figure 4-4 represents
the sequence of operations in a DATO bus cycle. Let us assume that we are going to place page
information in the BDV11 PCR, address 177520. When this address is put on the BDAL lines, PROM
E9 asserts outputs DO and DI, and wire-AND gate A causes the DC004 ENB input to go high (because BSYNC L is high, INWD L is high and the bus address causes the DC00S transceivers to assert
MATCH and DAL signals; refer to Table 4-6). When the processor asserts BSYNC L, flip-flop E10 is
set, generating the REG H and REG L signals; in addition, the DC004 generates SELO L (Table 4-5),
thereby completing the “‘device-selected’ operation in the BDV11 (SELO L remains low until BSYNC
L is negated). Now the CPU places the PCR page information on the BDAL lines and asserts BDOUT
L. As Table 4-7 shows, both the OUTHB L and OUTLB L signals, as well as the BRPLY L, signal, are
asserted. (Even though ENB might have gone low when the page information was placed on the
BDAL lines, this input was high when BSYNC L was asserted.)
The OUTHB L and OUTLB L signals clock the PCR, loading it with the page information on the
DAL lines. After the CPU negates the BDOUT L signal, the BDV11 negates BREPLY L and the CPU
terminates the operation by negating BSYNC L.

4-8

E17- MATCH

DAL12 H——(4>—DC)—‘

RXCX

ENB

}VECTOR

INWD

p—

DCO04

BDAL2 L——

BDALT L——

pcoos —DALT H———O) DAL

BDALO L ——

| DALO H————Q) DALO

INWD WD L

[-DAL2 H———(QDAL2

’

SELO L

SEL 60>

SEL 4jp2EL2 L

XMIT L

SEL 2jpSEL4
L
sEL 0O SELB L

BWTBT L
BDOUT L

o wTsT
Aoout

BSYNC L

SYNC

ouT B YT LB L
ouT LBPYT HB L
sRPLYIoBRPLY L

BDIN L

SYNC H

SYNC L

SYNCHI.

DAL11 H——
A4

JUA
J

E18-MATCH

£10

o—

DALS H—— A3

D2(1)

DAL4 H

o3(1)

REG H

BREPLY L

REG L

DO(1)

D1(1)

+5Vv

82523

E14-MATCH

XMIT H

DC NOK L
d

D4(1)

(1)

D5(1

D6(1)

D7(1)

iI—O

ENB
E19-MATCH

MA-1344

Figure 4-3

Control Logic

4-9

Table 4-5

DC004 Select Qutputs

BD AL2L*

BDAL1L*

Sl apeofie o

(qniie
il quiie s

| SEL6L
pasgasgen

erfesfaniioy

BSYNCL
onlonlienllen

Inputs

*H and L for these signals indicate the state of the input line at the falling edge of BSYNC.

Table 4-6

DC004 Protocol Signals

Inputs

BDINL | ENB*

INWD L

BREPLY L

X
X
L
H

S aa
offa o

piasfacfias

ol quilte ol s

BSYNCL

onl
anll anlie »

Outputs

*H and L for these signals indicate the state of the input line at the

falling edge of BSYNC.

Table 4-7

DC004 Byte Signals

Inputs

BDALO L*

OUTHBL

OUTLBL

BREPLY L

nee

(quiiaslent Mlenliesi
o

S
ol o effanjia

BWTBT L

ENB*

esl eV Besf e

BDOUTL

(onll onll unll BN enlll quilfe o

BSYNCL

Outputs

*H and L for these signals indicate the state of the input line at the falling edge of BSYNC.

4-10

CPU

BDV11

ADDRESS DEVICE/MEMORY

ASSERT BDALO-15 L WITH
ADDRESS AND

ASSERT BBS7 L (IF ADDRESS
IS IN THE 28-32K RANGE)

ASSERT BWTBT L (WRITE
Ia\7al i =\
VIGULE]

ASSERT B SYNCL — ——

OUTPUT DATA
«

REMOVE THE ADDRESS FROM

—DECODE ADDRESS

_—

STORE “DEVICE SELECTED"”

OPERATION

BDALO-15 L
AND NEGATE BBS7 L AND BWTBT L

{(BWTBT L REMAINS ACTIVE iF
DATOB CYCLE)
s

PLACE DATA ON BDALC-15 L

ASSERT BDOUT L —

—_— —

- — —— ——

TERMINATE OQUTPUT TRANSFER*
e

® TAKE DATA
RECEIVE DATA FROM BDAL LINES

ASSERT BRPLY L

REMOVE DATA FROM BDALO-16 L
AND NEGATE BDOUT L

~——

~— —_
S—

TERMINATE BUS CYCLE
o

—

~& OPERATION COMPLETED

_
___——*

TERMINATE

B BRPLY L

NEGATE BSYNC L (AND BWTBT L
IF

A DATOB BUS CYCLE)

MA-1345

Figure 4-4

Operation Sequence, DATO Cycle

4-11

4.5 POWER-UP LOGIC
The power-up logic (Figure 4-5) includes the ENABLE/HALT switch and the RESTART switch. In
normal operation, the ENABLE /HALT switch is in the ENABLE position. When the switch is placed
in the HALT position, inverter E16 causes NAND gate E7A to assert the BHALT L signal. The CPU
enters the halt mode and responds to console ODT commands. To resume operation, the user must
return the switch to the ENABLE position and enter a “P” command at the console terminal,
The RESTART switch must be cycled to re-boot the system. If the switch is in the position shown in
Figure 4-5, cycling the switch lever generates a pulse that is differentiated by capacitor C13. The
leading edge of the negative spike is inverted by E13 and causes E7B to negate the BDCOK H signal;
thus, DC NOK L is asserted, initializing the BDV11 registers. When the negative spike decays, NAND
gate E7B is disabled; the reasserted BDCOK H signal causes the CPU to carry out a power-up sequence and normal operation is resumed. BDCOK H can also be negated by the LSI-11 power supply,
which negates the BDCOK H signal if the dc voltages fall below specified levels.
The bus BREPLY L signal is asserted during the protocol routine when ES8 asserts BRPLY. Contrarily, the bus BSYNC L signal causes SYNC H and SYNC L to be asserted, also during the protocol
routine.
4.6 ROM ADDRESS SELECTION LOGIC
The logic shown in Figure 4-6 decodes the 256,o LSI-11 bus addresses and produces the 2048,, addresses needed to access ROM locations. Several examples are given here to illustrate how the logic
works.

In the first example, assume that we want to address location 0400 in the diagnostic/bootstrap ROMS,
which occupy sockets XE53 and XE48. Table 4-1 shows that to address this location we must have
page 2 in the PCR; then, bus address 173000 will access location 0400. It is usual (but not necessary) to
load the PCR with a pair of pages. Therefore, we will put pages 2 and 3 in the PCR by addressing the
PCR at address 177520 and loading it with data 001402; i.e., the PCR low byte contains 002 and the
high byte contains 003 (Figure 4-7).

Now, address 173000 is placed on the LSI-11 BDAL lines. Bits 1-8 of the address are loaded into the
flip-flops, E33 (because the bus addresses differ only in the first 9 bits, BDAL<9:15> L need not be
considered). ROM address bits A0O-A6 assume the logic state of DAL bits 1-7, respectively. The logic
looks at DALS8 H to determine which of the PCR bytes will form ROM address bits A7-A14. Since
DALS H is low, the low byte is selected; i.e., E32 gates R<0:3> H to A<7:10> H and E34 gates
R<4:7> Hto A<11:14> H. Bits AO-A10 are used to select the ROM location 0400; bits A11-A14 are
used to select the correct ROM, i.e., the ROMs in sockets XE53 and XE48. (This procedure is explained in the next section.)

Now that the PCR contains pages 2 and 3, any ROM location from 0400 to 0777 can be addressed.
Consider location 0600, for example, which is addressed by bus address 173400. Example 2 in Figure 47 illustrates the bit selection. Because DALS8 H is high, the high byte of the PCR is selected to form
ROM address bits A7-A14. Bits A0-A
10 select ROM location 0600, while bits A11-A14 again select
sockets XE53/XE48.

The same bus address, 173400, can address seven other ROM locations, providing the PCR page
number is changed. For example, let us address ROM location 3200. To do this, we must change the
PCR high byte from page 3 to page 15. We can do this either by loading 006414 (pages 14 and 15) into
the PCR or by loading only the high byte with 015. (This can be done by keeping the LSI-11 bus
BWTBT L signal asserted throughout the data transfer cycle; thus, only OUT HB L is asserted and
only the PCR high byte is loaded.) Let us load only the high byte, as illustrated in Example 3, Figure 47. The high byte again forms bits A7-A14 of the ROM address, and we have location 3200 being
addressed.

4-12

S1 . ENABLE
o HALT

_A}

BHALT L

+5V
BDCOK H

DC NOK H

}

RESTART

{E13

DC NOKL

;E
3

BREPLY L

fi’f{>:

| E6

E8 BRPLY D—BRPLY L

E13

|
1

SYNC H

)

E13

SYNC L

£7
MA-1346

Figure 4-5

Power-Up Logic

4-13

7415273

SH3 R14H
SH3 R13H

r718
R6 ‘f

SH2 DAL 11 H—2lpa

BYTE

R4—9—-‘—-—SH3 R11 H

R5}=

H
SH3 Ri0
R3 6
H
R2|———SH3 R9

5 |

SH2 DA

8 H —>1D1
SH2 DAL

SH2 REG L—(
8
1074127\
SH2 SELO L—(
;,

CLR
CLK
BiE

R1j-2——SH3 R8H

7415273
E29

SH2 DAL 0 H—>1p1
SH2 DAL 1 H —ioz

R12T""sn3 RO H
Rz—z—J—SHS R1 H

H—D3

R3———SH3 R2 H

SH2 DAL3H—24D4

R4|

SH2 DAL2

CJLKM

i ;41527 \ 6
SH2SELREG0 LL—=0
SH2

/ SH2 DC NOK L

= SH3 R3 H

gsf2
REP2
r7H8
ra|!2

BYTE

SH2 DAL 4 H—3lps
SH2 DAL 5 H — b6
SH2 DAL 6 H —{p7
SH2 DAL 7 H —-8lpg

74LS257
E32

3183

1
e

0]
11

|
|

JSHZ DC NOK L

SH3 R12H

r.n

7 3
SH2 DAL 10 H—"p
LO9H —p2

SH2 OUT 1R L ——)

H
SH3 R15

SH2 DAL 14 H—{p7
sH2 DAL 13 H—%4]p6

SH2 DAL 12 H—3Ips

SH2 OUT HB L——(C

RS 19

E27

18 g
SH2 DAL 15 H—381p

SH3 A10H

| ® SH3 A9 H

6
A
A1
3180

| 7 SH3 A8 H
L4

2 AO
oUT
CONT
i
=

SH3 A7 H

E34

13183
14],

12
H3 A14H
F3}—=——S

1Az

SH3 A13 H

]

6181
5 A1
3180

Fil-.—sH3 A12 H
4 H3 A11 H
FO2—S

2 AO
SO

74L5257

SH3 R4 H
SH3 R5H
SH3 R6 H
SH3 R7 H

ouUT
CONT
=

oi1

7415273

SH2 DAL 8 H—]p8

E33

Rrel>

SH2 DHL
7 H 1107
Hp g
6 H —13
SH2 DAL
SH2 DAL 5

SH2 DAL 4 H

R7PE—sH3
A6 H
A5H
R6H2—SH3
12
R5

H—={D5

3 D4

OUTCONT | SO | A

—SH3 A3 H

R385 sH3 A2 H
R22>— SH3 A1 H
R1 2 SH3 AOH

D3
SH2 DAL 3 H
SH2 DAL 2 H —Hp2
SH2 DAL1 H —1p1

CLK

SH2 SYNC H-—-I

7415257 TRUTH TABLE

SH3 A4 H

CLR

L
-

]

)

]

SH2 DC NOK L
MA-1347

Figure 4-6

ROM Address Selection Logic
4-14

BIT

NUMBER

15 14 1312 1110

1
EXAMPLE

PCR (001402)

0 000

BDAL L (173000)

0O 0 0

0 o\o

DAL <1:8> H

A <0:6> H

A <7:14> H

A <0:10> H (0400)

001

00O

EXAMPLE
2

PCR (001402)

BDAL L (173400)

11 1\ o1 1100 0

DAL <1:8> H

110

(Mo

A <0:6> H
A <7:14> H

0O0O0O0

A <0:10> H (0600)

0 0 0

o o

o of

\o 0

0 0 0

01100

EXAMPLE
3

PCR

oo oo

BDAL L (173400)

117110111000

DAL <1:8> H

(Mfo 0 o

A <0:6> H

A <7:14> H

1170100

0000110

A <0:10> H (3200)

o of

MA-1348

Figure 4-7

Address Bit Selection

4-15

Note that the PCR and the flip-flops are cleared whenever DC NOK L is asserted; this happens when
the RESTART switch is activated or when the dc voltages drop below reliable operating levels. Also,
since the R<0:15> H signals can be gated onto the DAL<0:15> H lines, the PCR can be read as well
as written.
4.7 SOCKET SELECTION LOGIC
The socket selection logic determines which pair of sockets responds to the ROM address signals
(although the ROMs in the sockets actually respond, we will state, for ease of explanation, that the
sockets respond). The selection signals SB1 L, SB2 L, SE1 L, SE2 L, and SP1 L through SP8 L are
generated by two decoders, E30 and E35 (Figure 4-8). Each selection signal causes two sockets to
respond to the address signals; one socket contains the high-byte ROM, the other contains the lowbyte ROM. Table 4-8 includes the relationship between the selection signals and the selected sockets.
Jumpers are inserted selectively in positions W1-W4 and W9-W12. These jumpers cause the PCR page
numbers and the selection signals (and, therefore, the sockets) to be related in definite ways. Earlier,
Table 4-1 indicated that PCR pages are assigned to specific ROM sockets. This is true within the
confines stated for Table 4-1; i.e., the table applies only to the BDV11 module shipped by DIGITAL.
On such a module, jumpers W1-W4 and W9-W
12 are arranged as indicated under Group A in Table
4-8. Thus, PCR pages 0-17, for example, cause selection signal SB1 L to be asserted, and SBI L causes
sockets XE53 and XE48 to respond to address signals A<0:10> H. Other combinations of jumpers are
possible, as indicated by Groups B through G in Table 4-8. Note that each selection signal always
selects the same pair of sockets; however, the relation of PCR pages to selected sockets varies with
jumper configuration.
Now, in Example 1 in the preceding section, the PCR was loaded with pages 2 and 3 so that bus
address 173000 could address location 0400. This location was specified by 11 ROM address bits, A0
H - A10 H. The remaining four ROM address bits, A1l H - A14 H, are applied to the socket selection
logic; here, they determine the ROMs in which location 0400 is addressed. If we assumme that we have
a BDVI11-AA, which has the Group A jumper arrangement, sockets XE53 and XE48 should be selected; i.e., SB1 L should be asserted by decoder E30 (Figure 4-8). With a jumper in both W9 and W12,
SB1 L is asserted when Al4 H is low, A12 H is low, and A1l H is low (A10 H and A13 H are
irrelevant). Figure 4-7, Example 1, shows that the three signals are low, as they are for all pages in the

0-17 range. That these signals are low for pages 0-17 is indicated by the entry in the primary address
column of Table 4-8; i.e., for addresses in the 0-2K range, address bits A1! H - A14 H are low. Note
that there is correlation between PCR pages and primary addresses throughout Table 4-8.
The jumper configurations in Groups B-G allow a choice of where program execution begins. That is,
the user can cause the CPU to execute instructions directly from a system ROM or an EPROM when
power is turned on, rather than from the diagnostic/bootstrap ROM. To illustrate, in the preceding
example the PCR contained pages 2 and 3; hence, bus address 173000 addressed location 0400 in
ROMs E53 and E48. However, if jumpers W1-W4 are arranged as shown in Group F, the same PCR

pages, 2 and 3, will cause bus adress 173000 to address location 0400 in ROMs E54 and E49; or, if
jumpers W9-W12 are arranged as in Group B, 173000 will address 0400 in E57 and E40.
Note that in both of these examples, one group of four jumpers is not specified; i.e., W9-W12 are not
specified in Group F and W1-W4 are not specified in Group B. These unspecified jumpers can have
any arrangement as long as there is no conflict in chip selection. To illustrate: If we have the Group F
configuration, we want PCR page 0 to cause 173000 to addresss 0000 in XE54/XE49; but, if jumpers
W9-W12 are arranged as in Group A or B, PCR page 0 causes two other sockets to respond to the
same address. Therefore, either there can be no chips in these other sockets, or the arrangement of
W9-W12 must be changed; for instance, there would be no conflict at all if W9-W
12 were arranged as
in Group C.

4-16

+5v

A4 L

A14 H————B(}

%
W3

° o

YOO——sSP8 L

-O1G2A

Y1O——SP7 L

——QJG2B

Y2[0——SP6 L
745138
E35

A11 H

A12 H

A10 H

A13 H

W2
o o

Y4O——SP4 L

Y5[0——SP3 L

Y6[D——SP2 L

Y7 0——SP1 L

W12
o

Y3[D——SP5 L

2YO——o

2Y1 ——
2A

2Y2

SE1 L

1Y0!

SB1 L

1Y1

SB2 L

E30

W11

o—

1Y2}——

1Y3——

1A
W9

W10

-0

745138 TRUTH TABLE

G1|G2 | C | B

OUT LOW

L|L

YO (SP8 L)

L|[H

Y1(SP7 L)

Y2 (SP6 L)

L{L|H|H

Y3 (SP5 L)

H|L]|L

Y4 (SP4 L)

H{L]|H

Y5 (SP3 L)

Y6 (SP2 L)

H!H]|H

Y7 (SP1 L)

| H

o—

74LS139 TRUTH TABLE (EACH HALF)
G

OuT LOW

YO(SB1 L)

Y1(SB2 L)

Y2 (SE1 L)

Y3 (SE2 L)

MA-1349

Figure 4-8

Socket Selection Logic

4-17

Table 4-8

BDV11 Selection Signals/Sockets

PCR

Primary
Selection | Addresses

Sockets

Group |W1

|W2 |W3| W4 |W9| W10{W11W12|Page

Signal

(A<0:14>H) | Selected

|[R

0-17
20-37
40-47
50-57
360-377
340-357
320-337

SB1 L

0K-2K

SB2 L
SE1 L
SE2 L
SP1 L
SP2 L
SP3 L

2K-4K
4K-5K
5K-6K
30K-32K
28K-30K
26K-28K

XES3/XE48
XES58/XE44
XES57/XE40
XES52/XE36
XE39/XES0
XE43/XE46
XE47/XE42

300-317

SP4 L

24K-26K

XES1/XE38

260-277
240-257
220-237

SP5 L
SP6 L
SP7 L

22K-24K
20K-22K
18K-20K

XES5/XE37
XE60/XE41
XES59/XE45

40-57

SBI L

4K-6K

XES53/XE48

60-77
0-7
10-17

SB2 L
SE1 L
SE2 L

6K-8K
0K-1K
1K-2K

XES8/XE44
XES57/XEA40
XES52/XE36

[200-217

SB1 L

16K-18K

Ibid

220-237

SB2 L

18K-20K

240-247

SE1I L

20K-21K

250-257

SE2 L

21K-22K

[240-257
260-277

SB1 L
SB2 L

20K-22K
22K-24K

200-207
210-217

SE1 L
SE2 L

16K-17K
17K-18K

[270-277
250-257
230-237
210-217
260-267
240-247
220-227

SP1 L
SP2 L
SP3 L
SP4 L
SP5 L
SP6 L
SP7 L

23K-24K

XE39/XES0

21K-22K
19K-20K
17K-18K
22K-23K
20K-21K
18K-19K

XE43/XE46
XE47/XE42
XES51/XE48
XES55/XE37
XE60/XE41
XES59/XE45

200-207

SP8 L

16K-17K

XE54/XE49

[160-177

SP1 L

14K-16K

Ibid

140-157
120-137

SP2 L
SP3 L

12K-14K
10K-~12K

60-77
40-57
20-37

SP5 L
SP6 L
SP7 L

6K-8K
4K-6K
2K-4K

200-217

|[R

100-117

0-17

*See text describing these configurations.

4-18

SP8 L

SP4 L

SP8 L

16K-18K

8K-10K

0K-2K

XE54/XE49

Ibid

Table 4-8

BDV11 Selection Signals/Sockets (Cont)
Primary
PCR

Selection

| Addresses

Sockets

Group| W1 | W2 |W3 [W4|W9I|{W10|{W11j W12 | Page

Signali

(A<0:14>H) | Seiected

70-77
50-57

SP1 L
SP2 L

7K-8K
5K-6K

30-37
10-17
60-67
40-47
20-27
0-7

SP3 L
SP4 L
SPS L
SP6 L
SP7 L
SP§ L

3K-4K
1K-2K
6K-7K
4K-5K
2K-3K
0K-iK

Ibid

NOTE
R = Removed; I = Inserted

4.8

ROM SOCKETS LOGIC

Figure 4-9 represents the ROM sockets and shows the address signals and enabling signals for each
functional group of sockets. The diagnostic/bootstrap ROM sockets (which are selected by signals
SB1 L and SB2 L) are supplied with 11 address bits, since these sockets are reserved for 2K-word
ROMs. The EPROM sockets (selected by signals SE1 L and SE2 L) are reserved for 1K ROMs;
therefore, these sockets are supplied with 10 address bits. The system ROM sockets can be occupied by
either 2K ROMs or 1K ROMs; five jumpers on the BDV11 module permit ROMs of either size to be
used. Figure 4-10 shows how these five jumpers control the selection signals for the system ROM
sockets, and relates the jumpers to the types of ROM that can be used in the BDV11. (If ROMs other
than 8316E, 2716, and 2708 are used, they must meet the specifications given in Appendix A.)
The output data from the selected memory is applied to data selectors that gate the data onto the DAL
<0:15> H lines. These selectors also allow the user to read the contents of the PCR.,

4.9

BEVNT LOGIC

The logic shown in Figure 4-11 permits the user to choose how to control the LTC function. When the
BEVNT switch, E21, is open, the bus BEVNT L signal can be controlled by the LTC signal generated
in the LSI-11 power supply. If the switch is closed, the BEVNT L signal can be program controlled.
Program control is effected by the 1-bit register, E10. Address 177546 is placed on the BDAL lines,
causing signals SEL6 L. and REG L to be asserted by the control logic. When data bit 6 is issued, the
OUT LB L signal causes E2 to clock the flip-flop, loading it with the state of DAL6 H. If DAL6 H is
high, the flip-flop output turns Q4 off, permitting the LTC signal to assert BEVNT L; but, if DAL6 H
is low, Q4 is switched on and clamps BEVNT L low. Note that the register is cleared when the power is
turned on or when the system is re-booted.
4.10

DISPLAY LOGIC

The dlsplay loglc and the dlagnostlc LED:s, D1 D4 are illustratedin Figure 4-12. Address 177524
ICDUILD lll

LJLJ

Ucllls UIUUI\DU

S P

)

Wllbll uaLa UILD U_J Cl.l\« IDDUUU,

s+l

012

£fi e

pmnnbkam

~mnmiioo L o

oam o

LIIC l.lly IIUP UUL}JULD LaudT tiic AUDHVULIV\/

LEDs to glow, indicating the source of the program error. All the flip-flops are cleared when power is
turned on or when the system is re-booted; hence, display value 17; is indicated; i.e., all the LEDs
(including the green POWER OK indicator) are lighted. If the LEDs indicate 173 and the PC =
173000, the ENABLE/HALT switch might be in the HALT position, or a bus error might have
occurred.
4-19

741857
DATA

R <0:15> H

A <0:10> H

XEB3/XE48

(Hi BYTE/LO BYTE)

SB1 L

: 16>
H
0 <0:15>H 0 <0:

SELECTORS

(g20)

(E28)

{ g23)

DAL <0:15> H

—>

(E31)
ouT
SO

CONT

SB2 L ————»

]

0 <0:15> H

XE58/XE44

REG H

(HI BYTE/LO BYTE)

XMIT H_E

A <0:9> H

0 <0:15> H

XE57/XE40

(HI BYTE/LO BYTE)

SE1 L

REG
L

H—

XE52/XE36

(HI BYTE/LO BYTE)

SE2 L

_ | XE39, XE43, XE47

XE51, XE55, XE60

ST <1:2>

0 <8:15> H

SELD L

‘:

XEB9, XEb4

SP <1:8> L

(HI BYTE)
74LS257

XESQ,

XE48, XE4

XE38, XE37, XE41

0 <0:7> H

XE45, XE49
.

(LO BYTE)

ouTT
CON

SO | An n | B n

X | X | X

|HI-Z

X]|H

H|H

XE53/X48, XE58/XE44 ARE DIAGNOSTIC ROM SOCKETS (XE58/XE44 RESERVED FOR

XE57/XE40, XE52/XE36 ARE EPROM SOCKETS; REMAINING SOCKETS ARE 16K SYSTEM
ROM SOCKETS.
MA-1350

Figure 4-9

Logic Block Diagram, ROM Sockets

4-20

A10 H

o
_J_

+12V

+5V
-L

ST2

w8
o o—

W13

ST1

-0

CB2

o0—

DB2

ROM TYPE

JUMPERS INSERTED!
W5

wé

| w7

| wi3

27082

2716

[

8316E3

8316E*

I=INSERTED: R=REMOVED
CB2 AND DB2 MUST BE SUPPLIED WITH EXTERNAL -5V POWER.

CHIP SELECT SIGNALS MUST BE PROGRAMMED AS FOLLOWS:
CS1

CS2

CS3

LOW

CHIP SELECT SIGNALS MUST BE PROGRAMMED AS FOLLOWS:
CS1

CS2

CS3

LOW

HIGH
MA-1351

Figure 4-10

System ROM Jumpers

4-21

BEVNT L

+5v
5

iE—21

DAL H—D
REG L—O
OUT LB L—Q)

1}—

+5V

E10 O
-

’

a_l
Q4

SEL6 L

DC NOK L
MA-1352

Figure 4-11

BEVNT Logic

+5V

74LS175

E25

DAL3 H

DAL2 H

DAL1 H

DALO H

R3(1)

R3(0)

R2(1)

/D3

R1(1)

/b2

RO(1)

/D1

R2(0)

R1(0)

RO(0)

DO
CLK

CLR

O
REG L—O

OUT LB L—O}

SEL4 L—Q

DC NOK L
MA-1353

Figure 4-12

Display Logic/LEDs D1-D4

4-22

READ/WRITE REGISTER LOGIC

4.11

The read/write register logic is shown in Figure 4-13. The logic includes two 8-bit universal shift
registers, 74L.S299 integrated circuits, which are used only in the “hold” and “load”” modes.
When the register is addressed, the SEL2 L, REG H, and REG L signals are asserted by the control
logic. If the register is being read, the control logic also asserts the XMIT H signal. The asserted OUT2
L signal puts the register into the hold condition; thus, the information on the DAL lines is that held in
the register output stages. On the other hand, when the register is to be written, the XMIT H signal is

negated and the register is placed in the load condition. Either or both bytes of the register are clocked
and the data on the DAL lines is loaded into the output stages of the register. The entire register is
cleared when power is turned on or when the system is re-booted.

ouT2

R\ XMIT H

DAL15 H

QH' 74LS299

DALS H

DAL14 H

DALY H

CLK

R3——DAL10 H

E22

QA!

REG H

S/L
S/R

DAL13 H

R2}——DAL12 H

OUTHB L——O)

R1}——DAL11 H

CLR G1

—O

REG L—/O

(a_fi

1
R8——DAL7 H

—s/L

—1S/R

—{QH'

74LS299

R7}——DALO H
R6——DAL1 H

R3|——DAL2 H

CLK

OUTLB L———O__J

R2—DAL4 H
R1—DAL3 H

7415299

CLR | s1 | so | cLK

]

)

|[HOLD CONDITION

|LOAD CONDITION

cLR G1 G2

T ? T
=

DC NOK L

MA-1354

Figure 4-13

Read/Write Register Logic
4-23

APPENDIX A
ROM SPECIFICATIONS

This appendix gives specifications of the ROMs recommended for use in BDV
11 variations. If ROMs
other than those listed are used, they must meet the specifications listed here.

A-1

2708-TYPE EPROM (1K X 8 ORGANIZATION)
READ OPERATION
DC AND OPERATING CHARACTERISTICS

AC CHARACTERISTICS

TA=0°CTO70°C,VcCc = +5V £5% Vpp = +12V +5%, VBg[1] = -5V £5%,Vgg =0V,
UNLESS OTHERWISE NOTED.

TA=0°CTO70°C, VcCc = +5V £5%, VDD = +12V £5%,Vgg = -5V +£5%
Vss =0V,
UNLESS OTHERWISE NOTED.

SYMBOL

PARAMETER

MIN. | MAX.

'ADDRESS AND CHIP

| UNIT | CONDITIONS
LA

VIN = 5.26V or VIN = V|L

2708-1 LIMITS | 2708 LIMITS

SYMBOL

PARAMETER

tACC

ADDRESS TO OUTPUT

MIN.

[ MAX.

| MIN

MAX.

| uNITS

SELECT INPUT
SINK CURRENT

350

450

120

DELAY
ILO

OUTPUT LEAKAGE

CURRENT

VouT = 55 V.CS/WE =5V

tco

CHIP SELECT TO

OUTPUT DELAY

ippl3]

VDD SUPPLY

CURRENT

WORST CASE SUPPLY CURRENTS:

tDF

CHIP DESELECT TO

120

OUTPUT FLOAT

Iccl3]

Vce SUPPLY

CURRENT
IgBI3]

VBB SUPPLY

CURRENT
ViL

tOH

ALL INPUTS HIGH

Vgs | 0.65

TA = 25°C,
f = 1 MHz

SYMBOL

iINPUT HIGH

3.0

CIN

OUTPUT LOW

0.45

loL = 1.6 mA

IoH = -100 uA

CouT

VOLTAGE

OUTPUT HIGH

3.7

VOLTAGE

VOH2

OUTPUT HIGH

2.4

POWER

\Y;

IOH = -1 mA

800

mwW

Ta = 70° C

DISSIPATION

TYP. | MAX.|

UNIT|

CONDITIONS

INPUT CAPACITANCE

|[pF

[ViIN=0V

OUTPUT CAPACITANCE(S

|pF

|vour=o0V

NOTE
1.

PIN CONFIGURATION
THIS PARAMETER IS PERIODICALLY SAMPLED AND IS NOT

INPUT RISE AND FALL TIMES: <20 ns

TIMING MEASUREMENT REFERENCE LEVELS: 0.8 V AND
2.8 V FOR INPUTS; 0.8 V and 2.4 V FOR OUTPUTS.

TYPICAL VALUES ARE FOR TA = 25° C AND NOMINAL SUPPLY VOLTAGES.

THETOTAL POWER DISSIPATION OF THE 2704/2708 IS SPECIFIED AT 800 mW. IT IS

BY SUMMING THE VARIOUS CURRENTS (Ipp. IcC., and IBB)
MULTIPLIED BY THEIR RESPECTIVE VOLTAGES SINCE CURRENT PATHS EXIST
BETWEEN THE VARIOUS POWER SUPPLIES AND Vsgs. THE Ipp. Icc. AND BB
IRIVIiWY

QUM

Gilww
i

110 T
CLw iV

MCTOOAAIAIE

WEICAIVIIING

SAALAIEm

TUVVER

SN LS

OUPrrCLY

<41 JVvCC

As[]2
asds

23[] As
221Agl1]

Ag-Ag

oA ey

CAFAUIITYT

SR LS

UNLY.

2111VeB

A3(]s

20[] CS/WE

270872704

A107
(LSB)

PIN NAME

A4l 4
axle

INPUT PULSE LEVELS: 0.65 V TO 3.0 V

ADDRESS INPUTS

01-08

DATA OUTPUTS/INPUTS

CS/WE

CHIP SELECT/WRITE ENABLE INPUT

19fvpp

18[JPROGRAM

Ao []8

17[]07 (MSB)

(LSB) 0p[]9

NOT CALCULATED

OUTPUT LOAD: 1 TTL GATE AND CL = 100 pF

VBB MUST BE APPLIED PRIOR TO Vcc AND Vpp. VBB MUST ALSO BE THE LAST
POWER SUPPLY SWITCHED OFF.

CIHIDDEAITE

—_

Aot .

.
AC TEST CONDITIONS:

NOTES:
1.

PARAMETER

100% TESTED.

VOLTAGE

|vcet+1|V

VOLTAGE

VOH1

CS/WE = 5V; Ta = 0° C

VOLTAGE

VoL

HOLD

CAPACITANCEI1]

iNPUT LOW

VIH

ADDRESS TO OUTPUT | 0

16[] 06

01[J10

15[105

02011

14104

Vssq 12

13[]03

NOTE 1: PIN 22 MUST BE CONNECTED

TO VSSFOR THE 2704.
MA-1381

A-3

8316E-TYPE ROM (2K X 8 ORGANIZATION)
DC AND OPERATING CHARACTERISTICS

AC CHARACTERISTICS

TA = 0°CTO +70° C, Vcc = 5V +10% UNLESS OTHERWISE SPECIFIED.

TA =0°CTO +70°C, Vcc = +5V £10%, UNLESS OTHERWISE SPECIFIED.

LIMITS

SYMBOL

PARAMETER

INPUT LOAD

MIN. | MAX. | UNIT | TEST CONDITIONS

CURRENT

VIN =0to 525V

(ALL INPUT PINS)

ILOH

OUTPUT LEAKAGE

CURRENT
ILoL

OUTPUT LEAKAGE

POWER SUPPLY
CURRENT

VIL

INPUT “LOW"

-20

VOLTAGE
VIH

INPUT “HIGH"

120

(0.8

\Y,

VOLTAGE

450

tCo

CHIP SELECT TO OUTPUT ENABLE DELAY TIME

120

tDF

CHIP DESELECT TO OUTPUT DATA

100

CHIP DESELECTED, VouT =

0.4

| MAX.

CONDITIONS OF TEST FOR

AC CHARACTERISTICS

ALLINPUTS 5.25 V DATA OUT
OPEN

OUTPUT LOAD ...t 1 TTL GATE AND C =
100 pF
INPUT PULSE LEVELS ..o
08T024V

INPUT PULSE RISE AND FALL TIME
(10% S
TO 90%) ......cceveeveemeeeeseeeeeoeeeooeooeoooeooooooeoo 20 ns
TIMING MEASUREMENT REFERENCE LEVEL

\Y;

et e 1VAND22V

CAPACITANCEI2]
loL = 2.1 mA

TA =25°C. f = 1

\Y;

loH = -400 uA

PIN CONFIGURATION
—

A
SYMBOL

CIN

TEST

ALL PINS EXCEPT PIN UNDER/|

TEST TIED TO AC GROUND

TYPICAL VALUES FOR TA = 25° C AND NOMINAL SUPPLY VOLTAGE.

0.8VAND 20V

MHz
LIMITS

2.4

UNIT

04V

NOTE
1.

FLOAT DELAY TIME

|[Vce

+iO0V

OUTPUT “LOW"

OUTPUT “HIGH"

ADDRESS TO OUTPUT DELAY TIME

MIN.

OQUTPUT .ot

VOLTAGE
VOH

INPUT

VOLTAGE

VOL

PARAMETER

40V

CURRENT

Icc

LIMITS

SYMBOL

Cout

NOTE

ALL PINS EXCEPT PIN UNDER
TESTTIED TOAC GROUND

TYP.

5pF

110 pF

24hv

70
MAX.

[1Vee

Asd2

As[]3

223 Ag

10 pF

15pF

THIS PARAMETER IS PERIODICALLY SAMPLED AND IS

NOT 100% TESTED.

A4l 4

211]Cs3

A3[]s

20[]csq

A2[d6

190 A10

A1Q7

18[] CS2

Aods

171 D7

16D

o9
D1010

106
15[]Ds

D2]11

14[]Da

GND[J12

13[] D3

PIN NAMES

Ap-A10

ADDRESS INPUTS

D7-Do

DATA QUTPUTS

CS1-CS3

| CHIP SELECTINPUTS
MA-1382

A-5

2716-TYPE EPROM (2K X 8 ORGANIZATION)
PIN CONFIGURATION

READ OPERATION
DC AND OPERATING CHARACTERISTICS

AC CHARACTERISTICS

TA = 0° CTo 70° C, Vccl1.2] = +5 V £5%, Vpp [2] = Vcc £0.6 V(3]

TA = 0° C TO 70° C. vecl!l = +5 vV £5%, Vppl2] = Ve £0.6 V (3]

SYMBOL
I

PARAMETER

LIMITS

MIN. |MAX. [ UNIT [ CONDITIONS

INPUT LOAD

VIN = 525 V

SYMBOL

PARAMETER

tACCT

ADDRESS TO

CURRENT

ILo

OUTPUT

LEAKAGE

VouTt = 525V

tACC2

vuUnnoivi

lcctl2]
Icc2(2]

Vpp CURRENT

Vee CURRENT

(STANDBY)

Vce CURRENT

INPUT LOW

VOLTAGE

VIH

INPUT HIGH

VOLTAGE

VoL

100

mA
mA

Vpp = 5.85 V

1CO
—

|08

-0.1
2.2

|vcct+1|

450

As(]2

23[] Ag

As5[]3

22[]A

A3[]s

20[]CSs

A107

18[JPD/PGM

Oo[s

16[]06

0110

15[]05

02011

140004

1Ag

A4)4

—

PD/PGM = CS = V|L

21 j‘fi’P

A2[6

PD/PGM TO QUTPUT
A LS

—

CS = V|L

19[JA10

Ao(]s

PD/PGM = ViH, CS = V)L

CHIP SELECT TO

120

tPE

PD/PGM TO OUTPUT | O

100

PD/PGM = V||

—

CS = VL

CS = PD/PGM = V|

CHIP DESELECTTO

PD/PGM = V|L

tOH

PIN NAMES

A0-A10 |ADDRESSES

—

OUTPUT FLOAT

ADDRESS TO

PD/PGM =

CS = V||

PD/PGM

OUTPUT HOLD

2.4

loL = 2.1 mA
IoH = -400 uA

13(J03

FLOAT

\Y;

045 | V

17007

GND[]12

TA = 25° C,f = 1 MHz

|POWER DOWN/PROGRAM

CHIP SELECT

00-07

CAPACITANCEI4]

OUTPUT LOW

OUTPUT HIGH
VOLTAGE.

450

OUTPUT DELAY

tDF

VOLTAGE

VOH

MIN. |MAX. | UNIT | TEST CONDITIONS

UELATY

(ACTIVE)

ViL

LIMITS

24 Vee

OUTPUT DELAY

MIBDEMNT

lpp1l2]

A7+

[OuUTPUTS

AC TEST CONDITIONS

SYMBOL | PARAMETER

TYP.| MAX. | UNIT | CONDITIONS

CIN

INPUT CAPACITANCE

VIN =0V

CouT

QUTPUT CAPACITANCE!

|12

VouT =0V

OUTPUT LOAD:1 TTL GATE AND CL = 100 pF
INPUT RISE AND FALL TIMES:
<20 ns
INPUT PULSE LEVELS: 08V TO22V
TIMING MEASUREMENT REFERENCE LEVEL:

NOTES
1.

Vcc MUST BE APPLIED SIMULTANEOUSLY OR BEFORE Vpp AND REMOVED

INPUTS

1VAND2V

OUTPUTS

O08VAND2V.

SIMULTANEOUSLY OR AFTER VPpp.
2.

Vpp MAY BE CONNECTED DIRECTLY TO Vcc EXCEPT DURING PROGRAMMING. THE

THE TOLERANCE OF 0.6 V ALLOWS THE USE OF A DRIVER CIRCUIT FOR SWITCHING

MODE SELECTION

SUPPLY CURRENT WOULD THEN BE THE SUM OF Icc AND Ipp1.

PINS| PD/PGM

vpp | Vce | ouTPUT

MODE

(18)

(20)

(21) | (24) | (9-11,13-17)

THE Vpp SUPPLY PIN FROM Vcc IN READ TO 25 V FOR PROGRAMMING.

READ

VIL

| +5

| DouT

THIS PARAMETER IS ONLY SAMPLED AND IS NOT 100% TESTED.

DESELECT

DON'T CARE

ViH

| +5

| HIGHZ

tacc2 IS

POWER DOWN

VIH

DON'TCARE

|+5

| +5

HIGH Z

PULSED

VIH

+25|

VIH

+25 | +5

REFERENCED TO PD/PGM OR THE ADDRESSES, WHICHEVER OCCURS

LAST.
PROGRAM

| DIN

VILTO VIH

PROGRAM INHIBIT

VIL

| HIGHZ
MA-1383

A-7

Reader’s Comments

,
BDV11 BUS TERMINATOR,
BOOTSTRAP, AND DIAGNOSTIC ROM
TECHNICAL MANUAL
EK-BDV11-TM-001

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