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EK-KDJ1A-UG-002

June 1986

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Document:	KDJ11-A CPU Module User's Guide
Order Number:	EK-KDJ1A-UG
Revision:	002
Pages:	331
Original Filename:	EK-KDJ1A-UG-002_KDJ11-A_CPU_Module_Users_Guide_2ed_Jun86.pdf

OCR Text

EK-KOJ 1A-UG-002

KDJ11-A
CPU Module
User's Guide

EK-KDJ1A-UG-002

KDJ11-A
CPU Module
User's Guide

Prepared by Educational Services
of
Digital Equipment Corporation

Preliminary Edition, January 1984
1st Edition, May 1984
2nd Edition, June 1986

The material in this manual is for informational purposes and is subject to change without notice. Digital
Eq~ipment Corporation assumes no responsibility for any errors that may appear in this manual.
The manuscript for this book was created on a VAX-ll/780 system and, via a translation program, was
automatically typeset by Digital's DECset Integrated Publishing System. The book was produced by
Educational Services Development and Publishing in Marlboro, MA.
The following are trademarks of Digital Equipment Corporation:

mamaama

DEC
DECmate
DEC net
DECsystem-1 0
DECSYSTEM-20
DECUS
DEC writer
DIBOL
EduSystem
lAS
MASSBUS

MicroPower /Pascal
MINC-ll
OMNIBUS
OS/8
PDP
PDT
P/OS
Professional
Q-Bus
Q22-Bus
Rainbow
RSTS

RSX
RT
RT-ll
TOPS-I0
TOPS-20
UNIBUS
VAX
VAXstation
VAXstation II
VMS
VT
Work Processor

CONTENTS

Page
CHAPTER 1

ARCHITECTURE

1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.4
1.5
1.5.1
1.5.1.1
1.5.1.2
1.5.1.3
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.6.1
1.5.6.2
1.5.7
1.5.7.1
1.5.7.2
1.5.7.3
1.5.7.4
1.5.7.5
1.5.7.6
1.5.7.7
1.5.8
1.5.8.1
1.5.8.2
1.5.8.3
1.5.9

DESCRIPTION ......................................................................................................... 1-1
GENERAL PURPOSE REGISTERS ...................................................................... 1-2
Registers ............................................................................................................. 1-2
Stack Pointer ...................................................................................................... 1-3
Program Counter ................................................................................................ 1-3
SYSTEM CONTROL REGISTERS ........................................................................ 1-3
Processor Status Word (Address: 17 777 776) ................................................. 1-3
CPU Error Register (Address: 17 777 766) ..................................................... 1-5
Program Interrupt Request Register (Address: 17 777 772) ............................ 1-6
Line Time Clock Register (Address: 17 777 546) ............................................ 1-7
Maintenance Register (Address: 17 777 750) ................................................... 1-7
INTERRUPTS ........................................................................................................... 1-8
MEMORY MANAGEMENT ................................................................................ 1-10
Memory Mapping ............................................................................................. 1-10
16-Bit Mapping ........................................................................................ 1-11
18-Bit Mapping ........................................................................................ 1-11
22-Bit Mapping ........................................................................................ 1-12
Compatibility .......... ,......................................................................................... 1-12
Virtual Addressing ........................................................................................... 1-13
Interrupt Conditions Under Memory Management ControL ......................... 1-13
Construction of a Physical Address ................................................................. 1-14
Memory Management Registers ...................................................................... 1-16
Page Address Registers ............................................................................ 1-18
Page Descriptor Register ......................................................................... 1-18
Fault Recovery Registers ................................................................................. 1-18
Memory Management Register 0 (Address: 17 777 572) ...................... 1-20
Memory Management Register 1 (Address: 17 777 574) ...................... 1-21
Memory Management Register 2 (Address: 17 777 576) ...................... 1-21
Memory Management Register 3 (Address: 17 772 516) ...................... 1-21
Instruction Back-Up/Restart Recovery ................................................... 1-22
Clearing Status Registers Following Abort.. ........................................... 1-22
Multiple Faults ......................................................................................... 1-22
Typical Usage Examples .................................................................................. 1-22
Typical Memory Page ............................................................................. 1-23
Nonconsecutive Memory Pages ............................................................... 1-25
Stack Memory Pages ............................................................................... 1-26
Transparency .................................................................................................... 1-27

iii

CONTENTS (Cont)
Page
1.6
1.6.1
1.6.1.1
1.6.1.2
1.6.2
1.6.2.1
1.6.2.2
1.6.2.3
1.7

CACHE MEMORy ................................................ ................................................. 1-27
Parity ................................................................................................................ 1-29
Parity Errors ............................................................................................ 1-29
Multiple Cache Parity Errors .................................................................. 1-30
Memory System Registers ............................................................................... 1-30
Cache Control Register (Address: 17 777 746) ...................................... 1-30
Hit/Miss Register (Address: 17 777 7 52) ............................................... 1-32
Memory System Error Register (Address: 17 777 744) ......................... 1-32
SOFTWARE SySTEMS ......................................................................................... 1-33

CHAPTER 2

INSTALLATION

2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.3
2.4
2.5
2.6
2.7

2.13

INTRODUCTION .............. :............................................................ .......................... 2-1
CONFIGURATION ...................................................... ............................................ 2-1
Power-Up Options .................................................................... .......................... 2-2
Power-Up Option 0 ..................................................... ............................... 2-2
Power-Up Option 1.................................................................................... 2-2
Power-Up Option 2 ..................................................... ............................... 2-2
Power-Up Option 3 ..................................................... ............................... 2-2
HALT Option ..................................................................................................... 2-2
Boot Address ...................................................... ................................................ 2-3
Wakeup Disable ...................................................... ........................................... 2-3
BEVNT Recognition .......................................................................................... 2-3
Factory Configuration ...................................................... .................................. 2-3
DIAGNOSTIC LEDS ...................................................... .......................................... 2-4
MAINTENANCE REGISTER (ADDRESS 17 777 750) ...................................... 2-6
POWER-UP SEQUENCE ........................................................................................ 2-7
POWER-DOWN SEQUENCE .............................................. ................................... 2-8
EXIT MICRO-ODT SEQUENCE .............................................. .............................. 2-8
MODULE CONTACT FINGER IDENTIFICATION ........................................... 2-9
HARDWARE OPTIONS ........................................................................................ 2-10
LSI-II Options ................................................................................................. 2-10
Restricted LSI-II Options ...................................................... ......................... 2-12
Enclosures ......................................................................................................... 2-14
SYSTEM DIFFERENCES ... ................................................................................... 2-15
KDJII-A SYSTEM ...................................................... ........................................... 2-16
MODULE INSTALLATION PROCEDURE ............................................. ........... 2-16
SPECIFICATIONS .............................................................................................. .... 2-18

CHAPTER 3

CONSOLE ON-LINE DEBUGGING TECHNIQUE (ODT)

3.1
3.2

INTRODUCTION ...................................................... ............................................... 3-1
TERMINAL INTERFACE ...................................................... ................................ 3-1
CONSOLE ODT ENTRY CONDITIONS .............................................................. 3-1
ODT OPERATION OF THE CONSOLE SERIAL-LINE INTERFACE ............ 3-2
Console ODT Input Sequence ............................................................................ 3-3
Console ODT Output Sequence .............................................. ........................... 3-3
CONSOLE ODT COMMAND SET ........................................................................ 3-3
/(ASCII 057) - Slash ...................................................... .................................. 3-4
<CR> (ASCII 15) - Carriage Return .............................................................. 3-5

2.8
2.9
2.9.1
2.9.2
2.9.3
2.10
2.11

2.12

3.3
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.2

CONTENTS (Cont)
Page

3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7

<LF> (ASCII 12) - Line Feed ......................................................................... 3-5
$ (ASCII 044) or R (ASCII 122) - Internal Register Designator ................... 3-6
S (ASCII 123) - Processor Status Word Designator ........................................ 3-6
G (ASCII 107) - Go .......................................................................................... 3-6
P (ASCII 120) - Proceed .................................................................................. 3-7
Control-Shift-S (ASCII 23) - Binary Dump ..................................................... 3-7
KDllI-A ADDRESS SPECIFICATION ................................................................. 3-8
Processor I/O Addresses .................................................................................... 3-8
Stack Pointer Selection ...................................................................................... 3-8
Entering of Octal Digits ..................................................................................... 3-8
ODT Timeout ..................................................................................................... 3-9
INVALID CHARACTERS ....................................................................................... 3-9

CHAPTER 4

FUNCTIONAL THEORY

4.1
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.2.7
4.2.2.8
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.3.4
4.2.3.5
4.2.3.6
4.2.3.7
4.2.3.8
4.2.3.9
4.2.3.10
4.2.3.11
4.2.4
4.2.5
4.2.5.1
4.2.5.2
4.2.5.3
4.2.5.4
4.2.5.5
4.2.5.6
4.3
4.3.1
4.3.2

INTRODUCTION ..................................................................................................... 4-1
DClll MICROPROCESSOR ................................................................................... 4-3
Initialization (MINIT L) .................................................................................... 4-3
Output Signals .................................................................................................... 4-3
Address Input/Output (AIO<03:00> H) .................................................. 4-3
Bank Select, (BS 1 H, BSO H) ................................................................... 4-4
Address Latch Enable (ALE L) ................................................................ 4-5
Stretch Control (SCTL L) ......................................................................... 4-5
Strobe (STRB L) ....................................................................................... 4-5
Buffer Control (BUFCTL L) ..................................................................... 4-5
Predecode Strobe (PRDC L) ..................................................................... 4-5
Clock (CLK H) .......................................................................................... 4-5
Input Signals ....................................................................................................... 4-5
MISS L ...................................................................................................... 4-5
Data Valid (DV 'L) ..................................................................................... 4-5
Continue (CONT L) .................................................................................. 4-5
DMA Request (DMR L) ........................................................................... 4-5
IRQ <07:04> H ........................................................................................ 4-5
HALT H .................................................................................................... 4-5
EVNT H .................................................................................................... 4-6
PWR FAIL L ............................................................................................ 4-6
PARITY L ................................................................................................. 4-6
ABORT L .................................................................................................. 4-6
FPA FPE L ............................................................................................... 4-6
MDAL <21 :00> ................................................................................................ 4-6
DClll Timing .................................................................................................... 4-6
NOP ........................................................................................................... 4-6
Bus Read .................................................................................................... 4-7
Bus Write ................................................................................................... 4-8
General-Purpose Read ............................................................................... 4-9
General-Purpose Write ............................................................................ 4-10
lACK ....................................................................................................... 4-10
STATE SEQUENCER ............................................................................................ 4-10
DClll ............................................................................................................... 4-12
LSI-II Bus Signals ........................................................................................... 4-12

CONTENTS (Cont)
Page
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.10.1
4.3.10.2
4.3.10.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.4.10
4.4.11
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12

LSI-II Bus Receivers ....................................................................................... 4-12
LSI-II Bus Transmitters .................................................................................. 4-12
Maintenance Register ....................................................................................... 4-12
DMA Register .................................................................................................. 4-12
Cache Data Path .............................................................................................. 4-12
Cache Memory ................................................................................................. 4-13
Floating-Point Accelerator ................................, .............................................. 4-13
Bus Traffic ....................................................................................................... 4-13
Address Busing ......................................................................................... 4-13
Read Data ............................ :................................................................... 4-13
Write Data ............................................................................................... 4-13
CACHE DATA PATH ............................................................................................ 4-17
DCJ 11 Input Signals ........................................................................................ 4-17
State Sequencer Inputs ..................................................................................... 4-17
System Memory Parity .................................................................................... 4-19
Cache Memory Parity ...................................................................................... 4-19
Timeout ............................................................................................................ 4-19
Cache Control Register .................................................................................... 4-19
Memory System Error Register ....................................................................... 4-19
LTC Register .................................................................................................... 4-20
Flush Counter ................................................................................................... 4-20
Address Register .............................................................................................. 4-20
CDP Outputs .................................................................................................... 4-20
CACHE MEMORy ................................................................................................. 4-21
Cache Data ....................................................................................................... 4-22
Data Parity Logic ............................................................................................. 4-22
Parity Data ....................................................................................................... 4-23
TAG RAM ....................................................................................................... 4-23
Hit/Miss Logic ................................................................................................. 4-23
BUS RECEIVERS ................................................................................................... 4-24
BUS TRANSMITTERS .......................................................................................... 4-25
OUTPUT CONTROL ............................................................................................. 4-26
INPUT CONTROL ................................................................................................. 4-26
DMA MONITOR REGISTER ............................................................................... 4-27
INITIALIZATION/MAINTENANCE REGISTER ............................................ 4-27
STATUS LEOs ........................................................................................................ 4-29

CHAPTER 5

EXTENDED LSI-ll BUS

5"1
5.2
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.1.5
5.3.1.6
5.4

INTRODUCTION ..................................................................................................... 5-1
BUS SIGNAL NOMENCLATURE ........................................................................ 5-3
DATA TRANSFER BUS CYCLES ........................................................................ 5-3
Bus Cycle Protocol ............................................................................................. 5-4
Device Addressing ...................................................................................... 5-4
DATI .......................................................................................................... 5-5
DATO(B) ................................................................................................... 5-7
DATIO(B) ................................................................................................ 5-10
DATBI ..................................................................................................... 5-12
DATBO .................................................................................................... 5-12
DIRECT MEMORY ACCESS (DMA) .................................................................. 5-14
vi

CONTENTS (Cont)
Page

5.5
5.5.1
5.5.2
5.5.3
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.4.1
5.6.4.2
5.6.4.3
5.6.4.4
5.6.5
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
5.7.8
5.7.8.1
5.7.8.2
5.7.8.3
5.7.8.4
5.8
5.8.1
5.8.2
5.8.3

INTERRUPTS ......................................................................................................... 5-17
Device Priority ................................................................................................. 5-17
Interrupt ProtocoL ............................................................................................ 5-18
4-Level Interrupt Configurations ..................................................................... 5-21
CONTROL FUNCTIONS ...................................................................................... 5-22
Memory Refresh .............................................................................................. 5-22
Halt ................................................................................................................... 5-22
Initialization ...................................................................................................... 5-22
Power Status ..................................................................................................... 5-22
BDCOK H ............................................................................................... 5-22
BPOK H ................................................................................................... 5-22
Power-U,p ................................................................................................. 5-23
Power-Down ............................................................................................. 5-24
BEVNT L ......................................................................................................... 5-24
BUS ELECTRICAL CHARACTERISTICS .......................................................... 5-24
Signal-Level Specification ................................................................................ 5-24
AC Bus Load Definition .................................................................................. 5-24
DC Bus Load Definition .................................................................................. 5-25
120 Q LSI-II Bus ............................................................................................ 5-25
Bus Drivers ....................................................................................................... 5-25
Bus Receivers ................................................................................................... 5-26
KD111-A Bus Termination .............................................................................. 5-26
Bus Interconnection Wiring ............................................................................. 5-27
Backplane Wiring ..................................................................................... 5-27
Intrabackplane Bus Wiring ...................................................................... 5-27
Power and Ground ................................................................................... 5-27
Maintenance and Spare Pins ................................................................... 5-28
SYSTEM CONFIGURATIONS ............................................................................. 5-28
Rules for Configuring Single-Backplane Systems ............................................ 5-29
Rules for Configuring Multiple-Backplane Systems ........................................ 5-29
Power Supply Loading ..................................................................................... 5-31

CHAPTER 6

ADDRESSING MODES AND BASE INSTRUCTION SET

6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.3.1
6.2.3.2
6.2.3.3
6.2.3.4
6.2.4
6.2.5
6.2.5.1
6.2.5.2
6.2.5.3
6.2.5.4
6.2.6

INTRODUCTION ..................................................................................................... 6-1
ADDRESSING MODES ........................................................................................... 6-1
Single-Operand Addressing ................................................................................ 6-3
Double-Operand Addressing ............................................................................... 6-3
Direct Addressing ............................................................................................... 6.. 4
Register Mode ............................................................................................ 6-6
Autoincrement Mode [OPR (Rn)+] .......................................................... 6-7
Autodecrement Mode [OPR-(Rn)] ............................................................ 6-9
Index Mode [OPR X(Rn)] ....................................................................... 6-11
Deferred (Indirect) Addressing ....................................................................... 6-13
Use Of The PC as a General-Purpose Register .............................................. 6-17
Immediate Mode [OPR #n,DD] .............................................................. 6-18
Absolute Addressing Mode [OPR @#A] ................................................. 6-18
Relative Addressing Mode [OPR A or OPR X(PC)] ............................. 6-20
Relative-Deferred Addressing Mode [OPR @A or OPR @X(PC)] ........ 6-20
Use Of The Stack Pointer as a General-Purpose Register ............................. 6-21
vii

CONTENTS (Cont)
Page
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.4.1
6.3.4.2
6.3.4.3
6.3.4.4
6.3.5
6.3.5.1
6.3.5.2
6.3.6
6.3.6.1
6.3.6.2
6.3.6.3
6.3.6.4
6.3.6.5
6.3.6.6
6.3.6.7
6.3.6.8
6.3.7
6.3.8

INSTRUCTION SET .............................................................................................. 6-21
Instruction Formats .......................................................................................... 6-22
Byte Instructions ............................................................................................... 6-26
List Of Instructions .......................................................................................... 6-27
Single-Operand Instructions ............................................................................. 6-30
General ..................................................................................................... 6-31
Shifts And Rotates .................................................................................. 6-36
Multiple-Precision .................................................................................... 6-42
PS Word Operators ................................................................................. 6-45
Double-Operand Instructions ............................................................................ 6-46
General ..................................................................................................... 6-47
Logical. ..................................................................................................... 6-53
Program Control Instructions ........................................................................... 6-56
Branches ................................................................................................... 6-56
Signed Conditional Branches ................................................................... 6-61
Unsigned Conditional Branches ............................................................... 6-63
Jump and Subroutine Instructions ........................................................... 6-65
Traps ........................................................................................................ 6-69
Miscellaneous Program Control... ............................................................ 6-73
Reserved Instruction Traps ...................................................................... 6-76
Trace Trap ............................................................................................... 6-76
Miscellaneous Instructions ................................................................................ 6-77
Condition Code Operators ................................................................................ 6-80

CHAPTER 7

FLOATING-POINT ARITHMETIC

7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
7.5
7.6
7.7

INTRODUCTION ..................................................................................................... 7-1
FLOATING-POINT DATA FORMATS ................................................................. 7-1
Nonvanishing Floating-Point Numbers .............................................................. 7-1
Floating-Point Zero ............................................................................................ 7-1
Undefined Variables ...'........................................................................................ 7-2
Floating-Point Data ............................................................................................ 7-2
FLOATING-POINT STATUS REGISTER (FPS) .................................................. 7-3
FLOATING EXCEPTION CODE AND ADDRESS REGISTERS ...................... 7-6
FLOATING-POINT INSTRUCTION ADDRESSING .......................................... 7-7
ACCURACY ............................................................................................................. 7-7
FLOATING-POINT INSTRUCTIONS ................................................................... 7-8

CHAPTER 8

PROGRAMMING TECHNIQUES

8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5

INTRODUCTION ..................................................................................................... 8-1
POSITION-INDEPENDENT CODE ....................................................................... 8-1
Use of Addressing Modes in the Construction of Position-Independent Code ........ 8-1
Comparison of Position-Dependent and Position-Independent Code ................. 8-3
STACKS ..................................................................................................................... 8-5
Pushing onto a Stack ......................................................................................... 8-6
Popping from a Stack ........................................................................................ 8-6
Deleting Items from a Stack .............................................................................. 8-7
Stack Uses .......................................................................................................... 8-7
Stack Use Examples ........................................................................................... 8-8
viii

CONTENTS (Coot)
Page
8.3.6
8.3.6.1
8.3.6.2
8.3.7
8.3.7.1
8.3.7.2
8.3.8
8.3.8.1
8.3.8.2
8.3.9
8.3.9.1
8.3.9.2
8.3.9.3
8.3.10
8.3.11
8.3.11.1
8.3.11.2
8.3.12
8.4
8.5
8.6
8.7

Subroutine Linkage .......................................................................................... 8-10
Return from a Subroutine ....................................................................... 8-10
Subroutine Advantages ............................................................................ 8-10
Interrupts .......................................................................................................... 8-11
Interrupt Service Routines ....................................................................... 8-11
Nesting ..................................................................................................... 8-11
Reentrancy ....................................................................................................... 8-12
Reentrant Code ........................................................................................ 8-13
Writing Reentrant Code .......................................................................... 8-14
Coroutines ......................................................................................................... 8-14
Coroutine Calls ........................................................................................ 8-15
Coroutines Versus Subroutines ................................................................ 8-16
Using Coroutines ...................................................................................... 8-17
Recursion .......................................................................................................... 8-19
Processor Traps ................................................................................................ 8-20
Trap Instructions ...................................................................................... 8-21
Use of Macro Calls .................................................................................. 8-22
Conversion Routines ......................................................................................... 8-22
PROGRAMMING THE PROCESSOR STATUS WORD .................................. 8-26
PROGRAMMING PERIPHERALS ...................................................................... 8-27
PDP-II PROGRAMMING EXAMPLES .............................................................. 8-27
LOOPING TECHNIQUES ..................................................................................... 8-34

CHAPTER 9

BOOT ROMS AND DIAGNOSTICS

9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.4

INTRODUCTION ..................................................................................................... 9-1
MXVII-B2 ROM SET .............................................................................................. 9-1
Power-Up ............................................................................................................ 9-1
Automatic Booting ............................................................................................. 9-2
Manual Booting .................................................................................................. 9-2
Error and Help Messages ................................................................................... 9-3
DIAGNOSTICS ......................................................................................................... 9-6
DIAGNOSTIC EXAMPLE ....................................................................................... 9-7

APPENDIX A

INSTRUCTION TIMING

A.l
A.2
A.3

GENERAL ................................................................................................................ A-l
BASE INSTRUCTION SET TIMING ................................................................... A-I
FLOATING-POINT INSTRUCTION SET TIMING ........................................... A-6

APPENDIX B

PROGRAMMING DIFFERENCES

APPENDIX C

CONFIGURATION NOTES

C.1
C.2
C.3

GENERAL ................................................................................................................ C-l
KDJ11-A CPU MODULE CONFIGURATION NOTES ...................................... C-l
FPJ11-AA FPA CONFIGURATION NOTES ....................................................... C-l

FIGURES
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6
1-8
1-9

1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18
1-19
1-20
1-21
1-22
1-23
1-24
1-25
1-26
1-27
1-28
1-29
1-30
1-31
2-1
2-2
2-3
2-4
2-5
2-6

4-1
4-2
4-3

4-4
4-5
4-6
4-7
4-8
4-9

4-10
4-11
4-12
4-13
4-14

Title

Page

Programming Model ................................................................................................... 1-2
Processor Status Register ........................................................................................... 1-3
CPU Error Register .................................................................................................... 1-5
Program Interrupt Request Register (PIRQ) ............................................................. 1-6
Line Time Clock Register (BEVNT) ......................................................................... 1-7
Maintenance Register ................................................................................................. 1-7
18-Bit Mapping ......................................................................................................... 1-11
22-Bit Mapping ......................................................................................................... 1-12
Virtual Address Mapping into Physical Address ..................................................... 1-13
Interpretation of a Virtual Address .......................................................................... 1-14
Displacement Field of a Virtual Address ................................................................. 1-14
Construction of a Physical Address ......................................................................... 1-15
Active Page Registers ............................................................................................... 1-16
Page Address Register (PAR) .................................................................................. 1-18
Page Descriptor Register (PDR) .............................................................................. 1-18
Memory Management Register 0 (MMRO) ............................................................. 1-20
Memory Management Register 1 (MMRl) ............................................................. 1-21
Memory Management Register 3 (MMR3) ............................................................. 1-21
Typical Memory Page .............................................................................................. 1-23
Nonconsecutive Memory Pages ................................................................................ 1-25
Typical Stack Memory Page .................................................................................... 1-26
Cache Physical Address ................. " .. " .................................................................... 1~27
Cache Data Format .................................................................................................. 1-27
Cache Control Register (CCR) ...................................... ~ ......................................... 1-30
Hit/Miss Register (HMR) ........................................................................................ 1-32
Memory System Error Register (MSER) ................................................................ 1-32
Single-Precision Format ............................................................................................ 1-34
Double-Precision Format .......................................................................................... 1-34
2's Complement Format ........................................................................................... 1-35
Floating-Point Status Register .................................................................................. 1-36
KDJII-A Jumper Locations ....................................................................................... 2-4
Maintenance Register ................................................................................................. 2-6
KDJII-A Power-Up Sequence ................................................................................... 2-7
KDJII-A Power-Down Sequence ............................................................................... 2-8
Micro-ODT Exit Sequence ......................................................................................... 2-8
KDJII-A Module Contacts ........................................................................................ 2-9
Functional Block Diagram .......................................................................................... 4-2
DCJII-A Microprocessor ........................................................................................... 4-3
NOP Transaction ........................................................................................................ 4-6
Stretched NOP Transaction ....................................................................................... 4-7
Bus Read Transaction ................................................................................................. 4-7
Stretched Bus Read Transaction ................................................................................ 4-8
Bus Write Transaction ................................................................................................ 4-9
General-Purpose Read Transaction ............................................................................ 4-9
General-Purpose Write Transaction ......................................................................... 4-10
Interrupt Acknowledge Transaction ......................................................................... 4-11
State Sequencer ........................................................................................................ 4-11
Address Traffic Pattern ............................................................................................ 4-14
Read Data Busing ..................................................................................................... 4-15
Write Data Busing .................................................................................................... 4-16

FIGURES (Cont)
Figure No.
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12

5-13
5-14
5-15
5-16
5-17
5-18
6-1
6-2
6-3
6-4

6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12

6-13
6-14
6-15
6-16
6-17
6-18
6-19

Title

Page

Cache Control Logic ................................................................................................. 4-18
Cache Meillory ......................................................................................................... 4-21
Cache Memory Physical Address ............................................................................. 4-22
Cache Data ............................................................................................................... 4-22
Cache Data Parity Logic .......................................................................................... 4-23
Cache HIT/MISS Logic ........................................................................................... 4-24
KDJ11-A Bus Receivers ........................................................................................... 4-24
KDJ11-A Bus Transmitters ...................................................................................... 4-25
DCJ11-A Output Control ......................................................................................... 4-26
DCJ11-A Input Control ............................................................................................ 4-26
DMA Monitor Register ............................................................................................ 4-27
Initialization/Maintenance Register Logic ............................................................... 4-28
Status LEDs Logic ................................................................................................... 4-29
DATI Bus Cycle ......................................................................................................... 5-5
DATI Bus Cycle Timing ............................................................................................ 5-6
DATO or DATO(B) Bus Cycle .................................................................................. 5-8
DATO or DATO(B) Bus Cycle Timing ..................................................................... 5-9
DATIO or DATIO(B) Bus Cycle ............................................................................. 5-10
DATIO or DATIO(B) Bus Cycle Timing ................................................................ 5-11
DATBI Bus Cycle Timing ........................................................................................ 5-13
DATBO Bus Cycle Timing ...................................................................................... 5-14
DMA Request/Grant Sequence ............................................................................... 5-15
DMA Request/Grant Bus Cycle Timing ................................................................. 5-16
Interrupt Request/Acknowledge Sequence .............................................................. '5-18
Interrupt Protocol Timing ........................................................................................ 5-19
Position-Independent Configuration ......................................................................... 5-21 .
Position-Dependent Configuration ............................................................................ 5-21
Power-Up/Power-Down Timing ............................................................................... 5-23
Bus Line Termination ............................................................................................... 5-26
Single-Backplane Configuration ............................................................................... 5-29
Multiple-Backplane Configuration ............................................................................ 5-30
Single-Operand Addressing ......................................................................................... 6-3
Double-Operand Addressing ....................................................................................... 6-3
Mode 0 Register ......................................................................................................... 6-4
Mode 2 Autoincrement .............................................................................................. 6-5
Mode 4 Autodecrement .............................................................................................. 6-5
Mode 6 Index ............................................................................................................. 6-5
INC R3 Increment ..................................................................................................... 6-6
ADD R2,R4 Add ....................................................................................................... 6-7
COMB R4 Complement Byte .................................................................................... 6-7
CLR (R5)+ Clear ....................................................................................................... 6-8
CLRB (R5)+ Clear byte ............................................................................................ 6-8
ADD (R2)+,R4 Add .................................................................................................. 6-9
INC -(RO) Increment ................................................................................................ 6-9
INCB -(RO) Increment Byte ................................................................................... 6-10
ADD -(R3),RO Add ................................................................................................ 6-10
CLR 200(R4) Clear .................................................................................................. 6-11
COMB 200(R 1) Complement Byte .......................................................................... 6-12
ADD 30(R2),20(R5) Add ........................................................................................ 6-12
Mode 1 Register-Deferred ........................................................................................ 6-13
xi

FIGURES (Cont)
Figure No.

6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
7-1
7-2
7-3
7-4
7-5
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11

8-12

Title

Page

Mode 3 Autoincrement-Deferred ............................................................................. 6-13
Mode 5 Autodecrement-Deferred ............................................................................ 6-14
Mode 7 Index-Deferred ............................................................................................ 6-14
CLR @R5 Clear ....................................................................................................... 6-15
INC @(R2)+ Increment ........................................................................................... 6-15
COM @-(RO) Complement ..................................................................................... 6-16
ADD @1000(R2),Rl Add ........................................................................................ 6-16
ADD #10,RO Add .................................................................................................... 6-18
CLR @ #1100 Clear ................................................................................................ 6-19
ADD @ #2000 Add ................................................................................................. 6-19
INC A Increment ..................................................................................................... 6-20
CLR @A Clear ......................................................................................................... 6-21
Single-Operand Group .............................................................................................. 6-22
Double-Operand Group 1 ......................................................................................... 6-22
Double-Operand Group 2 ......................................................................................... 6-22
Program Control Group Branch ............................................................................... 6-23
Program Control Group JMP .................................................................................. 6-23
Program Control Group JSR ................................................................................... 6-23
Program Control Group RTS ................................................................................... 6-23
Program Control Group Traps ................................................................................. 6-23
Program Control Group Subtract ............................................................................ 6-24
Mark ......................................................................................................................... 6-24
Call to Supervisor Mode ........................................................................................... 6-24
Set Priority Level ..................................................................................................... 6-24
Operate Group .......................................................................................................... 6-25
Condition Group ....................................................................................................... 6-25
Move To and From Previous Instruction/Data Space Group ................................. 6-25
Byte Instructions ...................................................... :................................................ 6-26
Single-Precision Format .............................................................................................. 7-2
Double-Precision Format ............................................................................................ 7-2
2's Complement Format ............................................................................................. 7-3
Floating-Point Status Register .................................................................................... 7-3
Floating-Point Addressing Modes ............................................................................... 7-9
Word and Byte Stacks ................................................................................................ 8-5
Push and Pop Operations ........................................................................................... 8-6
Byte Stack Used as a Character Buffer ..................................................................... 8-9
JSR Stack Condition Example ................................................................................. 8-10
Nested Interrupt Service Routines and Subroutines ................................................ 8-12
Reentrant Routines ................................................................................................... 8-13
Sharing Control of a Routine ................................................................................... 8-13
Coroutine Example ................................................................................................... 8-15
Coroutines Versus Subroutines ................................................................................. 8-16
Coroutine Path .......................................................................................................... 8-17
Coroutine Interaction ................................................................................................ 8-18
Recursive Routine Flow ........................................................................................... 8-19

xii

TABLES
Table No.

1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17

1-18
2-1

2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10

3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
5-1
5-2
5-3
5-4
7-1
9-1
9-2
9-3

Title

Page

General-Purpose Registers ... ~...................................................................................... 1-2
Stack Pointer (PSW 15, 14 or 13, 12) ...................................................................... 1-3
Processor Status Bit Description ................................................................................ 1-4
CPU Error Register Bit Description .......................................................................... 1-5
PIRQ Bit Descriptions ................................................................................................ 1-6
Line Time Clock (LTC) Register Bit Descriptions .................................................... 1-7
Maintenance Register Bit Description ........................................................................ 1-8
Asynchronous Interrupts ............................................................................................. 1-9
Synchronous Interrupts ............................................................................................. 1-10
KDJII-A Compatibility ........................................................................................... 1-12
Memory Management Register Addresses ............................................................... 1-17
Page Descriptor Bit Description ............................................................................... 1-19
MMRO Bit Descriptions ........................................................................................... 1-20
MMR3 Bit Description ............................................................................................. 1-22
Cache Response Matrix ............................................................................................ 1-28
Cache Parity Errors .................................................................................................. 1-29
Cache Control Register Description ......................................................................... 1-31
Memory System Error Register ............................................................................... 1-32
KDJII-A Jumper Identification ................................................................................. 2-1
Power-Up Options ...................................................................................................... 2-2
Factory Configuration ................................................................................................ 2-3
LED Functions............................................................................................................ 2-5
Probable System Failure............................................................................................. 2-5
Maintenance Register Bit Description ........................................................................ 2-6
KDJII-A Module Signals ......................................................................................... 2-10
LSI-II Compatible Options ...................................................................................... 2-11
Restricted or Noncompatible LSI-II Options ......................................................... 2-12
Upgrade Choices ....................................................................................................... 2-17
Console ODT Commands ........................................................................................... 3-3
Console ODT States and Valid Input Characters ...................................................... 3-9
AIO Coding ................................................................................................................ 4-4
Bank Select Address Codes ........................................................................................ 4-4
General-Purpose Read Codes ..................................................................................... 4-9
General-Purpose Write Codes .................................................................................. 4-10
Select Codes .............................................................................................................. 4-13
Output Select Codes ................................................................................................. 4-17
TAG Parity ............................................................................................................... 4-17
Parity Error Action .................................................................................................. 4-19
Abort and Parity Response ...................................................................................... 4-20
Summary of Signal Line Functions ............................................................................ 5-1
Data Transfer Bus Cycles ........................................................................................... 5-3
Data Transfer Bus Signals .......................................................................................... 5-4
Position-Independent, Multilevel Device Requirements ........................................... 5-18
FPS Register Bits ....................................................................................................... 7-4
MXVII-B2 Boot Commands ..................................................................................... 9-2
MXVI1-B2 Error Messages ....................................................................................... 9-3
KDJ 11-A Diagnostics ................................................................................................. 9-7

xiii

TABLES (Cont)
Table No.

A-I
A-2
A-3
A-4
A-5

A-6
A-7
A-8
A-9
A-10
A-ll
A-12
A-13

B-1

Title

Page

Source Address Time: All Double Operand ............................................................. A-I
Destination Address Time: Read-Only Single Operand ............................................ A-2
Destination Address Time: Read-Only Double Operand .......................................... A-2
Destination Address Time: Write-Only ..................................................................... A-2
Destination Address Time: Read-Modify-Write ....................................................... A-3
Execution, Fetch Time .............................................................................................. A-3
Instruction Execution Times (In Microseconds) ....................................................... A-6
Floating Source Modes 1-7 ....................................................................................... A-7
Floating Destination Modes 1-7 ................................................................................ A-7
Floating Read-Modify-Write Modes 1-7 .................................................................. A-8
Integer Source Modes 1-7 ........................................................................................ A-8
Integer Destination Modes 1-7 ................................................................................. A-9
FPJ11-AA Instruction Execution Times ................................................................... A-9
KDJ11-A Programming Differences .......................................................................... B-2

xiv

PREFACE

This user's guide is intended to support the users of the KDlll-A CPU module by providing them with
architecture, programming, diagnostic and configuration information. The architecture is described in
Chapter I and is supported by the functional theory description in Chapter 4. The diagnostics and booting
procedures are described in Chapter 9, and Chapter 3 provides the techniques used for on-line debugging
(ODT). The configuration requirements for both the module and system applications are described in
Chapter 2. Chapter 5 provides the information on the LSI-II bus used in most system applications.
The KDlll-A module uses the standard instruction set described in Chapter 6 and the floating-point
instruction set described in Chapter 7. Also described in Chapter 6 are addressing modes, which are
supported by the programming techniques given in Chapter 8. The detailed timing information is provided
in Appendix A and the differences between other LSI-II and PDP-II microprocessors are listed in
Appendix B. Appendix C includes configuration notes which must be observed when the floating-point
accelerator option (FP1l1-AA) is installed on the KD1l1-A module.

CHAPTER 1
ARCHITECTURE

1.1 DESCRIPTION
The KDJII-A is a dual-height processor module for LSI-II type bus systems. It is designed for use in
high-speed, real-time applications and for multiuser, multitasking environments.
The KDJ11-A module executes the complete PDP-II integer and FP-II floating-point instruction sets.
Full 22-bit memory management is provided for both instruction references and data references in three
protection modes - kernel, supervisor, and user. The KDJ11-A module is fully downward compatible with
older PDP-II models which have 18-bit memory management or no memory management.
The three protection modes provide the ability to implement layered software protection. Memory
management separately manages each mode, allowing each mode to access different sections of main
memory. Furthermore, each section can have different access protection rights. Each mode uses a separate
system stack pointer that offers an additional degree of isolation. The protection modes are organized so
that a higher protection mode can always enter a lower protection mode, while a lower protection mode
can never accidentally enter a higher protection mode. Kernel mode has full privileges and can execute all
instructions. Supervisor mode and user mode, the two lower privileged modes, cannot execute certain
instructions.
The module interfaces to the extended LSI-ll bus and can address up to 4 megabytes of main memory.
Block mode DMA transfers, which are allowed on the extended bus, are supported by the KDJ1I-A. The
22-bit extended LSI-II bus is fully downward compatible with the standard 18-bit LSI-II bus.
The KDJ ll-A module supports console emulation (micro octal debugging tool or ODT). This allows users
to interrogate and write main memory and CPU registers as if a console switch panel and display lights
were available.
The module contains an 8 Kbyte write-through direct map cache (set size one, block size one). The cache
is transparent to all programs and acts as a high-speed buffer between the processor and main memory.
The data stored in the cache represents the most active portion of the main memory being used. The
processor accesses main memory only when data is not available in the cache.
The user-visible registers are shown in Figure 1-1 and are classified as general purpose, system control,
memory system, floating point and memory management registers.
Self-diagnostic LEDs are provided on the KDJII-A module and indicate the status of the module and
system when the module is powered-up. The LEDs aid in troubleshooting module failures.
The KDJ11-A module can run RT-ll VS.l, RSX-IIM, RSX-llM PLUS, RSTSjE, UNIX, and micropower PASCAL operating systems.

1-1

RO'

Rl'

R2'

R3'

R4'

R5'

~
SP
SSP

PSW

LTC

1CACHE CTRL ,

USP

PIRO

MAl NT

I MEM SYS ERR'

CPU ERROR

1 FEC

HIT/MISS

MEMORY MANAGEMENT

FLOATING POINT
'--F-PS--',

MEMORY SYSTEM

SYSTEM CONTROL

GENERAL PURPOSE

1....-F-EA---'

1 MMRO ,

1 MMRl I

1MMR2\

1MMR3 ,

ACCUMULATORS (64 BIT)
AGO

PAGE REGISTERS (32 BIT)

r-----------------~

~----------------~
AC2 ~----------------~
ACl

AC3
AC4
AC5

~----------------~
~----------------~

KERNEL (00)

SUPERVISOR (01)

USER (11)

WWW
B I SPACE AND 8 D SPACE
MA-11041

Figure 1-1

Programming Model

1.2 GENERAL PURPOSE REGISTERS
There arc 16 general purpose registers (GPR), as iisted in Table 1-1, but only 8 are visible to the user at
any given time. All these registers can be used as accumulators, deferred addresses, index references,
autoincrement, autodecrement, and stack pointers.
1.2.1 Registers
There are two groups of six registers designated RO-R5 and RO'-R5'. The group currently being used is
selected by bit 11 in the processor status word (PSW). When bit 11 is set (1), the RO'-RS' group is
selected, and when bit 11 is cleared (0), the RO-R5 group is selected.

Table 1-1
Register
Number

0
I
2
3
4

5
6
7

General-Purpose Registers

Designation
RO
RI
R2
R3
R4
RS

RO'
RI'
R2'
R3'
R4'
RS'

KSP
PC

SSP

1-2

USP

1.2.2 Stack Pointer
Register six (R6) is desig~ated as the system stack pointer. There are three stack pointers available, one for
each corresponding protection mode. However, only one is visible to the user at a given time. The
processor status bits 14 and 15 select the active stack pointer used for all instructions except MFPI,
MFPD, MTPI, and MTPD. When these instructions select R6 as the destination register, bits 12 and 13 of
the processor status word select the active stack pointer. In both cases, the 2-bit selection code is encoded
as described in Table 1-2 to select the active register.
Table 1-2 Stack Pointer (PSW 15, 14 or 13. 12)
Code

Selected R6

00
01
II
10

Kernel stack pointer (KSP)
Supervisor stack pointer (SSP)
User stack pointer (USP)
Illegal - User stack pointer selected

1.2.3 Program Counter
The program counter (PC) contains the 16-bit address of the next instruction stream word to be accessed.
It is designated as R 7 and controls the sequencing of instructions. The PC is directly addressable by singleand double-operand instructions and is a general purpose register, although it is normally not used as an
accumulator.
1.3 SYSTEM CONTROL REGISTERS
The processor status word (PSW), program interrupt request (PIRQ), CPU error register, line clock
register, and the maintenance register are the system control registers. These registers are used by the
module to control system-oriented functions.
1.3.1 Processor Status Word (Address: 17777776)
The processor status word (PSW) contains the current and previous operational modes, the general
purpose register group being used, the current priority level, the condition code status, and the trace trap
bit used for program debugging. The PSW is initialized at power-up and is cleared with a console start.
The PSW register is defined in Figure 1-2 and is described in Table 1-3.
15

~~
CURRENT
MODE

PRIORITY
LEVEL

PREVIOUS
MODE

GENERAL PURPOSE
REGISTER GROUP

TRACE BIT

CONDITION
CODES

SUSPENDED
INFORMATION
MR-'1042

Figure 1-2 Processor Status Register

1-3

Table 1-3

Processor Status Bit Description

Bit

Name

Status

Description

IS, 14

Current mode

RjW

Indicates the current operating mode and is coded as follows.
Bits
15
0
0
1
1

Mode

Kernel
Supervisor
Illegal
User

0
1

13, 12

Previous mode

RjW

Indicates the previous operating mode and is coded the same as
bits IS, 14.

RjW

Selects the group of general purpose registers being used. When
the bit is set, the RO'-RS' group is selected and when cleared, the
RO-RS group is selected.

10,09

NjA

Not used. Reads as zero.

Suspended
information

RjW

Reserved.

07:0S

Priority

RjW

Indicates the current priority level of the processor and is coded
as follows.
Bits
7
1
1
1
1
0
0
0
0

1
1

1
0
1
0
1
0
1
0

0
0
1
1
0
0

Priority Level

7
6

S
4
3
2
1

Trap*

RjW

The trap bit is inactive when it is cleared. When set, the processor traps to location 14 at the end of the current instruction. It is
useful for debugging programs and setting breakpoints.

Negative

RjW

Condition code N is set when the previous operation result was
negative.

Zero

RjW

Condition code Z is set when the previous operation result is
zero.

Overflow

RjW

Condition code V is set when the previous operation resulted in
an arithmetic overflow.

Carry

RjW

Condition code C is set when the previous operation caused a
carry out.

* The T-bit cannot be set by explicitly writing to the PSW. It can only be changed by the RTI/RTT instructions.

1-4

1.3.2 CPU Error Register (Address: 17 777 766)
The CPU error register identifies the source of any trap or abort condition that caused a trap through
location 4. Six separate error conditions are identified in Figure 1-3 and are described in Table 1-4. The
register is cleared by any write reference, power-up, or by console start. It is not changed by the RESET
instruction.

1 0

1 0 1 0 1 0 101010lOI

J I I

I 0I 0

I LLEGAL HALT
ADDRESS ERROR
NON-EXISTENT MEMORY

1/0 BUS TIMEOUT
YELLOW STACK VIOLATION
RED STACK VIOLATION
MR·9326

Figure 1-3

Table 1-4

CPU Error Register

CPU Error Register Bit Description

Status

Function

Illegal HALT

Read only

Set when execution of a HALT instruction is attempted in
user or supervisor mode, or in kernel mode if W 5 is
removed.

Address error

Read only

Set when word access to an odd byte address or an instruction fetch from an internal register is attempted.

Nonexistent
memory

Read only

Set when a reference to main memory times out

I/O bus timeout

Read only

Set when a reference to the I/O page times out.

Yellow stack
violation

Read only

Set on a yellow zone stack overflow trap. (Kernel mode
stack reference less than 400 octal).

Red stack
violation

Read only

Set on a red stack trap - a kernel stack push abort during
an interrupt, abort, or trap sequence.

01,00

Not used

Bit

Name

15:08

Not used

1-5

1.3.3 Program Interrupt Request Register (Address: 17 777 772)
The program interrupt request register (PIRQ) implements a software interrupt facility. A request is
initiated by setting one of the bits <15:09>, which corresponds to a program interrupt request for priority
levels 7-1. Bits <07:05> and <03:01> are set by hardware to the encoded value of the highest pending
request set. When the interrupt is acknowledged, the processor vectors to address 240 for a service routine.
It is the responsibility of the service routine to clear the interrupt request. The PIRQ register is defined in
Figure 1-4 and is described in Table 1-5. The PIRQ register is cleared at power-up, by a console start, or
by the RESET instruction.
15

IPIR 71 PIR 61 PIR 51 PIR 41 PIR 31 p'R 21 PIR 11

,
REQUEST

08
0

LEVELS~

PRIORITY ENCODED VALUE OF BITS 9-15

Figure 1-4

MA·9013

Program Interrupt Request Register (PIRQ)

Table 1-5

PIRQ Bit Descriptions

Bit,

Name

Status

Function

Level 7

Read/write

P_equests an interrupt piiority of level 7

Level 6

Read/write

Requests an interrupt priority of level 6

Level 5

Read/write

Requests an interrupt priority of level 5

Level 4

Read/write

Requests an interrupt priority of level 4

Level 3

Read/write

Requests an interrupt priority of level 3

Level 2

Read/write

Requests an interrupt priority of level 2

Level I

Read/write

Requests an interrupt priority of level 1

07:05

Encoded value

Read only

Bits <07:05> represent the encoded value of highest priority level set in bits < 15 :09>

03:01

Encoded value

Read only

Bits <03:01> represent the encoded value of the highest
priority level set in bits <15:09>. Same as bits <07:05>.

08, 00

Not used

1-6

1.3.4 Line Time Clock Register (Address: 17 777 546)
The line time clock register (LTC) controls the recognition of the LSI-II bus BEVNTL signal. When bit
06 of the register is set (1), the BEVNTL signal can be recognized and will generate the highest possible
level 6 interrupt request through address location 100. The BEVNTL input is disabled when bit 06 of the
register is cleared (0). The BEVNTL input can be permanently disabled by installing the W9 jumper. The
register is defined in Figure 1-5 and is described by Table 1-6. The register is cleared at power-up, by a
console start, or by the RESET instruction.

I I I
0

I IoI I I I
0

05
0

I I I I I
0

BEVNTL ENABLE
MR-l1043

Figure 1-5

Line Time Clock Register (BEVNT)

Table 1-6 Line Time Clock (LTC) Register Bit Descriptions
Bit

Name

15:07

Not used

BEVNT ENABLE

05:00

Not used

Status

Function

Read/write

When this bit is set (1), the LSI-II BEVNT L signal can
be recognized (unless W9 is installed).

1.3.5 Maintenance Register (Address: 17 777 750)
The maintenance register provides a way for software to determine the power-up options selected by the
user. It also indicates if the floating-point accelerator (FPll1-AA) is available. The register is defined in
Figure 1-6 and is described by Table 1-7.
15

I :

BOOT
ADDRESS

I I I
0

Io I I
0

FPJ11·AA
AVAILABLE

~Po!ER

HJT
OPTION

OK
POWER UP (POK)
OPTION

MR-l1044

Figure 1-6

Maintenance Register

1-7

Table 1-7

Maintenance Register Bit Description

Bit

Name

Status

Function

15:12

Boot address

Read only

These bits read the user's selected boot address. The
address is selected by jumpers, WI (bit 15), W2 (bit 14),
W4 (bit 13) and W6 (bit 12). A "1" indicates the jumper is
inserted and a "0" indicates the jumper is removed.

11:09

Not used

FPJlI-AA
available

Read only

07:04

Module ID

Read only

The "0001" code identifies this module as a KDJII-A
microprocessor.

HALT option

Read only

The option determines how the HALT instruction is used
in the kernel mode. If W5 is removed, the bit is set (1) and
the processor traps through vector address 4. If W5 is
installed, the bit is cleared (0) and the processor enters
console ODT mode.

02,01

Power-up

Read only

These bits read the power-up mode for the processor. Bit 2
is set (1) by removing jumper W3 and bit 01 is set (1) by
removing jumper W7. The following power-up options are
available.

BPOKH

The bit is set (1) if floating-point accelerator (FPJlI-AA)
is installed on the module.

Read only

Bit 02

Bit 01

Option

0
0
1
1

0
1
0
1

PC at 24, PS at 26
Micro-ODT, PS = 0
PC = 173000, PS = 340
User Bootstrap, PS = 340

The bit is set (l) when the LSI-II bus signal BPOK H is
asserted, indicating that the ac power is okay.

1.4 INTERRUPTS
The KDll1-A supports a variety of trap, hardware, and software interrupts. They are described in Tables
1-8 and 1-9.

1-8

Table 1-8 Asynchronous Interrupts
Internal
or
External

Vector
Address

Priority
Level *

Red stack trap
(CPU error register, bit 02)

Internal

Address error
(CPU error register, bit 06)

Internal

Memory management violation
(MMRO, bits <13:15»

Internal

250

I/O timeout/nonexistent memory
(CPU error register, bits <04:05»

Internal

Parity error

External

114

Trace (T-bit) trap (PSW, bit 04)

Internal

Yellow stack trap
(CPU error register, bit 03)

Internal

Power fail

External

, Floating-point exception

External

244

PIR 7 (PIRQ, bit 15)

Internal

240

IRQ 7

External

User-defined

PIR 6 (PIRQ, bit 14)

Internal

240

BEVNT

External

100

IRQ 6

External

User-defined

PIR 5 (PIRQ, bit 13)

Internal

240

IRQ 5

External

User-defmed

PIR 4 (PIRQ, bit 12)

Internal

240

IRQ 4

External

User-defined

PIR 3 (PIRQ, bit 11)

Internal

240

PIR 2 (PIRQ, bit 10)

Internal

240

PIR 1 (PIRQ, bit 09)

Internal

240

Halt linet

External

None - places system
in console mode.

Interrupt

NM = Nonmaskable

The halt line usually has the lowest priority. However, it has highest priority during vector reads.

1-9

Table 1-9 Synchronous Interrupts
Vector
Address

Interrupt
FP instruction exception
TRAP (trap instruction)
EMT (emulator trap instruction)
lOT (I/O trap instruction)
BPT (breakpoint trap instruction)
CSM (call to supervisor mode instruction)
HALT instruction*
WAIT (wait-for-interrupt instruction)
*

244
34
30

20
14
10
4
Does not trap, but frees the bus when
waiting for external interrupt.

Execution of the HALT instruction performs different operations, depending on jumper W5 and the protection mode. Jumper
W5 determines the operation of a HALT instruction in the kernel mode. If it is installed, the processor enters the ODT mode,
and, if it is removed, the processor traps to location 4. The HALT instruction in the supervisor or user mode is an illegal
instruction and the processor traps to location 4. This condition also sets bit 07 of the CPU error register.

1.5 MEMORY MANAGEMENT
The KDJ11-A provides memory management hardware that facilitates multiuser multiprogramming. The
KDJ11-A memory management allows a supervisory program to:
1.
2.
3.

Control the execution of the various user programs
Manage the allocation of memory and peripheral device resources
Safeguard the integrity of the system as a whole by control of each user program.

In general, memory management provides the means for assigning memory pages to a user program and
preventing that user from making any unauthorized access to pages outside his assigned area. Thus, a user
can effectively be prevented from accidental or willful destruction of any other user program or the system
executive program.
The following are the basic characteristics of KDJ11-A memory management.
•
•
•
•
•
•
•
•
•
•

16 user mode memory pages
16 supervisor mode memory pages
16 kernel mode memory pages
8 pages in each mode for instructions
8 pages in each mode for data
Page lengths from 64 to 8192 bytes
Each page provided with full protection and relocation
Transparent operation
3 modes of memory access control
Memory access to 4 megabytes.

1.5.1 Memory Mapping
The processor can perform 16-bit, 18-bit or 22-bit address mapping. The I/O page, which is the uppermost
4 K words of memory, always uses the physical addresss locations 17 760 000 to 17 777 777.

1-10

1.5.1.1 16-Bit Mapping - There is a direct mapping relocation from virtual to physical addresses. The
lowest 28 K virtual addresses are the same corresponding physical addresses. The I/O page physical
addresses are located in the upper 4 K block as shown in Figure 1-7.
1.5.1.2 18-Bit Mapping - Each of the three modes; kernel, supervisor, and user, are allocated 32 K
words that are mapped into 128 K words of physical address space. The lowest 124 K words of physical
memory or the I/O page can be referenced as shown in Figure 1-8.

17777777
4K
17760000

177777
160000

I--------t''- -

-.,,--------...,
00157777

VIRTUAL
(16 BITS)
000000

2B K

_ _ _ _ _ _ -'L..-.00000000
______-I

INCOMING
ADDRESS

PHYSICAL ADDRESS
SPACE (22 BITS)
MR-11045

Figure 1-7

16-Bit Mapping

17777777
4K
17760000

00757777
177777
124 K
VIRTUAL
(16 BITS)

MEM
r - - - " MGMT

000000

00000000

INCOMING
ADDRESS

PHYSICAL ADDRESS
SPACE (22 BITS)
MA-11046

Figure 1-8

18-Bit Mapping

1-11

1.5.1.3 22-Bit Mapping - This mode uses the full 22-bit addresses to access all of the physical memory.
The upper 4 K block is still the I/O page as shown in Figure 1-9.
1.5.2 Compatibility
The operation of 16-, 18-, and 22-bit mapping can be used to provide compatibility among other PDP-II
computers. This means that software written and developed for any PDP-II computer can be run on the
KDJII-A without modification. Refer to Table 1-10.

17777777
4K
17760000
17757777

2044K

177777

VIRTUAL
(16 BITS)

MEM

t - - - + MGMT ---~

000000

___

00000000
- J ._
_ _ _ _--...J

INCOMING
ADDRESS

PHYSICAL ADDRESS
SPACE (22 BITS)
MR-l1047

Figure 1-9

22-Bit Mapping

Table 1-10 KDJll-A Compatibility
Mapping

Memory
Management

System

16-bit .

Off

PDP-I 1/.05, 11/10, 11/15, 11/20, 11/03

18-bit

PDP-I 1/35, II/40, 11/45, II/50, 11/23

22-bit

PDP-II/70, 11/44, 11/24, 11/23 plus

1-12

1.5.3 Virtual Addressing
When memory management is operating, the normal 16-bit address is no longer interpreted as a direct
physical address but as a virtual address containing information to be used in constructing a new 22-bit
physical address. The information contained in the virtual address is combined with relocation information
contained in the page address register to yield a 22-bit physical address as shown in Figure 1-10. Using
memory management, memory can be dynamically allocated in pages, each composed of from 1 to 128
integral blocks of 64 bytes.
The starting physical address for each page is an integral multiple of 64 bytes, and each page has a
maximum size of 8192 bytes. Pages may be located anywhere within the physical address space. The
determination of which set of 16 page registers is used to form a physical address is made by the current
mode of operation (i.e., kernel, supervisor, or user mode), and the reference type - instruction or data.

PHYSICAL
ADDRESS SPACE
PAGE 5

11
VIRTUAL
INSTRUCTION/DATA
ADDRESS SPACE
32 K

PAGE 6
PAR 7
PAR 6
PAGE 7

PAR 5
PAR 4
PAR 3
PAR 2
PAR 1

PAR 0

o
VI RTUAL ADDRESS
(16 BITS)

PAGE ADDRESS t:EGISTERS

PAGE 4

0
PHYSICAL ADDRESS
(22 BITS)

PAR = PAGE ADDRESS REGISTER
MA-ll048

Figure 1-10 Virtual Address Mapping into Physical Address

1.5.4 Interrupt Conditions Under Memory Management Control
Memory management relocates all addresses. When it is enabled, all traps, aborts, and interrupt vectors
are mapped using the kernel mode data space mapping registers. Therefore, when a vectored transfer
occurs, the new program counter (PC) and processor status word (PS) are obtained from two consecutive
words physically located at the trap vector and are mapped using kernel mode data space registers.
The stack used for the "push" of the current PC and PSW is specified by bits 14 and 15 of the new PSW.
The PSW mode bits also determine the new mapping register set. This allows the kernel mode program to
have complete control over servicing all traps, aborts or interrupts. The kernel program may assign the
service of some of these conditions to a supervisor or user mode program by simply setting the mode bits of
the new PSW in the vector to return control to the appropriate mode.

1-13

1.5.5 Construction of a Physical Address
All addresses with memory relocation enabled either reference information in instruction (I) space or data
(D) space. I space is used for all instruction fetches, index words, absolute addresses, and immediate
operands; D space is used for all other references. I space and D space each have eight page address
registers (PARs) in each mode of CPU operation (kernel, supervisor, and user). Memory management
register 3 can separately disable D space for each mode and map references (instructions and data)
through I space.
The basic information needed for the construction of a physical address comes from the virtual address,
which is illustrated in Figure 1-11, and the appropriate PAR set.

00
OF

~--~Y~--~"~----------------------~T~----------------------~
ACTIVE PAGE
FIELD

DISPLACEMENT FIELD
MR-l1049

Figure I-II

Interpretation of a Virtual Address

The virtual address consists of:
1.

The active page field. This 3-bit field determines which of 8 page address registers from the
PAR set (PARO-P,A~R7) will be used to form the physicai address.

The displacement field. This I3-bit field contains an address relative to the beginning of a page.
The longest page length is 8 Kbytes (2 13 = 8 Kbytes). The DF is further subdivided into two
fields as shown in Figure 1-12.

The displacement field consists of:
1.

The block number. This 7-bit field is interpreted as the block number within the current page.

The displacement in block. This 6-bit field contains the displacement within the block referred
to by the block number.

00
BN

~----------~y------------~"~--------~y~--------~
DISPLACEMENT IN BLOCK

BLOCK NUMBER

Figure 1-12

Displacement Field of a Virtual Address

1-14

The remainder of the information needed to construct the physical address comes from the contents of the
PAR referenced by the page address field. This 16-bit register specifies the starting address of the memory
page. The PAF is actually a block number in the physical memory. For instance, PAF = 3 indicates a
starting address of 96 (3 X 32) words in physical memory.
The construction of the physical address is illustrated in Figure 1-13.
The logical sequence involved in constructing a physical address (P A) is as follows.
1.

Select a set of page address registers. This depends on the space being referenced,
MMR3<2:0>, and the protection mode being used.

The active page field of the virtual address selects one of eight page address registers
(PARO-PAR7) from the appropriate set.

The page address field of the selected page address register contains the starting address of the
currently active page as a block number in physical memory.

The block number from the virtual address is added to the page address field to yield the
number of the block in physical memory. This is bits <21:06> of the physical address.

The displacement in block from the displacement field of the virtual address is concatenated to
the physical block number to yield a true 22-bit physical address.

15
VI RTUAL ADDRESS

SELECT PAR

: :

: : :

:
13

: :

OFFSET INTO
PAGE (VA)

+ PAF

I:
21

PHYSICAL ADDRESS

:l[ :
00

s! :

MA-l10S1

Figure 1-13

Construction of a Physical Address

1-15

1.5.6 Memory Management Registers
Memory management implements 3 sets of 32 16-bit registers as shown in Figure 1-14. One set of registers
is used in kernel mode, another in supervisor mode, and the other in user mode. The protection mode in
use determines which set is to be used. Each set is subdivided into two groups of 16 registers. One group is
used for references to instruction (I) space, and one to data (D) space. The 1 space group is used for all
instruction fetches, index words, absolute addresses, and immediate operands. The D space group is used
for all other references, providing it has not been disabled by memory management register 3. Each group
is further subdivided into two parts of eight registers. One part is the page address register (PAR) whose
function was described previously. The other part is the page descriptor register (PDR). PARs and PDRs
are always selected in pairs by the top three bits of the virtual address. A PARjPDR pair contains all the
information needed to describe and locate a currently active memory page.
The memory management registers are located in the uppermost 8 Kbytes of physical address space,
which is designated as the I/O page. The addresses allocated to the memory management registers are
listed in Table 1-11.

PROCESS STATUS WORD

KERNEL (00)
PAR

PDR

SUPERVISOR (01)
PAR

PDR

USER (11)
PAR

PDR

I SPACE

PAR

PDR

PAR

PDR

PAR

PDR

D SPACE

MR-,,052

Figure 1-14

Active Page Registers

1-16

Supervisor D space descriptor register (SDSDR 7)

17 772 236

1-17

1.5.6.1 Page Address Registers - The page address register (PAR) contains the page address field
(PAF), a 16-bit field that specifies the starting address of the page as a block number in physical memory.
The page address register (see Figure 1-15) contains the page address field that may be alternatively
thought of as a relocation register containing a relocation constant, or as a base register containing a base
address. These registers are not changed by either console starts or the reset instruction. They are
undefined at power-up.

MR·11053

Figure 1-15

Page Address Register (PAR)

1.5.6.2 Page Descriptor Register - The page descriptor register contains information relative to page
expansion, page length, and access control. The register is shown in Figure 1-16 and is described in Table
1-12.

PAGE LENGTH FIELD (PLF)

BYPASS
CACHE

PAGE
WRITTEN

PAGE LENGTH
FIELD

EXPAL~
DIRECTI~~ I

ACCESS
CONTROL FIELD
MA-8920

Figure 1-16

Page Descriptor Register (PDR)

1.5.7 Fault Recovery Registers
Aborts generated by the memory management hardware are vectored through kernel virtual location 250.
Memory management registers 0, 1, 2, and 3 are used to determine why the abort occurred and to allow
for program restarting.

NOTE
An abort to a location which is itself an invalid
address will cause another abort. Thus, the kernel
program must ensure that kernel virtual address 250
is mapped into a valid address; otherwise, a loop will
occur that will require console intervention.

1-18

Table 1-12 Page Descriptor Bit Description
Bit

Name

Status

Function

Bypass cache

Read/write

This bit implements a conditional cache bypass mechanism.
If the PDR accessed during a relocation operation has this bit
set, the reference will go directly to main memory. Read hits
result in invalidation of the accessed cache location.

14:08

Page length
field

Read/write

This field specifies the block number which defines the page
boundary. The block number of the virtual address is compared
against the page length field to detect length errors. An error
occurs when expanding upwards if the block number is greater
than the page length field, and when expan"::ng downwards if the
block number is less than the page length field.

Not used

Page written

Read only

The written into (W) bit indicates whether the page has been
written into since it was loaded in memory. When this bit is set, it
indicates a modified page. The W-bit is automatically cleared
when the PAR or PDR of that page is written.

05, 04

Not used

Expansion
direction

Read/write

This bit specifies in which direction the page expands. If ED = 0,
the page expands upward from block number 0 to include blocks
with higher addresses; if ED = 1, the page expands downward
from block number 127 to include blocks with lower addresses.

02,01

Access control
field

Read/write

This field contains the access code for this particular page. The
access code specifies the manner in which a page may be accessed
and whether or not a given access should result in an abort of the
current operation. Implemented codes are:

Nonresident - abort all accesses

Read only - abort on write

Not used - abort all accesses

Read/write access

Not used

1-19

1.5.7.1 Memory Management Register 0 (Address: 17 777 572) - Memory management register 0
(MMRO) provides memory management unit control and records memory management unit status. The
register contains abort and status flags as shown in Figure 1-17 and described in Table 1-13.

ABORT READ-ONLY
ACCESS VIOLATION
ABORT PAGE
L----LENGTH ERROR

PAGE MODE

PAGE NUMBER

ABORT

~----- NON-RESIDENT

Figure 1-17

PAGE ADDRESS
SPACE liD

ENABLE RELOCATION

Memory Management Register 0 (MMRO)

Table 1-13

MMRO Bit Descriptions

Bit

Name

Status

Function

15*

Nonresident
abort·

Read/write

Bit 15 is set by attempting to access a page with an access control
field key equal to 0 or 2. It is also set by attempting to use memory
relocation with a processor mode (PS<15:14» of 2.

14*

Page length
abort

Read/write

Bit 14 is set by attempting to access a location in a page with a
block number (virtual address bits <12:06» that is outside the
area authorized by the page length field of the page descriptor
register for that page.

13*

Read only
abort

Read/write

Bit 13 is set by attempting to write in a read-only page. Read-only
pages have access keys of l.

12:07

Not used

06,05

Processor
mode

Read only

Bits <06:05> indicate the processor mode (kernel, supervisor,
user, illegal) associated with the page causing the abort (kernel =
00, supervisor = 01, user = II, illegal = 10). If the illegal mode is
specified, an abort is generated and bit 15 is set.

Page space

Read only

Bit 04 indicates the address space (I or D) associated with the page
causing the abort (0 = I space, I = D space).

03:01

Page number

Read only

Bits <03:01> contain the page number of the page causing the
abort.

Enable
relocation

Read/write

Bit 00 enables relocation. When it is set to I, all addresses are
relocated. When bit 00 is set to 0, memory management is inoperative and addresses are not relocated.

Bits <15:13> can be set by an explicit write; however such an action does not cause an abort. Whether set explicitly or by an
abort, setting any bit in bits <15:13> causes memory management to freeze the contents of MMRO <06:01>, MMRl, and
MMR2. The status registers remain frozen until MMRO <15:13> is cleared by an explicit write.

1-20

1.5.7.2 Memory Management Register 1 (Address: 17 777 574) - Memory management register 1
(MMR 1) records any auto increment or autodecrement of a general purpose register, including explicit
references through the PC. The increment or decrement amount by which the register was modified is
stored in 2's complement notation. The lower byte is used for all source operand instructions and the
destination operand may be stored in either byte, depending on the mode and instruction type. The register
is cleared at the beginning of each instruction fetch. The register is defined in Figure 1-18.
15

AMOUNT CHANGED
(2'5 COMPLEMENT)

AMOUNT CHANGED
(2'S COMPLEMENT)

Figure 1-18

Memory Management Register 1 (MMR 1)

1.5.7.3 Memory Management Register 2 (Address: 17 777 576) - Memory management register 2
(MMR2) is loaded with the program counter of the current instruction and is frozen when any abort
condition is posted in MMRO,
1.5.7.4 Memory Management Register 3 (Address: 17 772 516) - Memory management register 3
(MMR3) enables the data space for the kernel, supervisor, and user operating modes, It also selects either
18-bit or 22-bit mapping and enables the request for the supervisor macroinstruction (CSM). The register
is shown in Figure 1-19 and is defined in Table 1-14. MMR3 is cleared during power-up, by a console
start, or by a RESET instruction.
15

UNINTERPRETED
ENABLE 22-BIT MAPPING - - - - - - '
ENABLE CSM INSTRUCTION - - - - - - - '
ENABLE KERNEL DATA SPACE - - - - - - - - - - '
ENABLE SUPERVISOR DATA SPACE - - - - - - - - - - - '
ENABLE USER DATA SPACE - - - - - - - - - - - - - - - '
MR-8925

Figure 1-19

Memory Management Register 3 (MMR3)

1-21

Table 1-14 MMR3 Bit Description
Status

Function

Uninterpreted

Read/write

This bit can be set or cleared under program control, but it is not
interpreted by the KDJ II-A.

Enable 22-bit
mapping

Read/write

This bit enables 22-bit memory addressing (the default is 18-bit
addressing).

Enable CSM
instruction

Read/write

This bit enables recognition of the call supervisor mode instruction.

Enable kernel
data space

Read/write

This bit enables the data space mapping for the kernel operating mode.

Enable supervisor
data space

Read/write

This bit enables the data space mapping for the supervisor operating
mode.

Enable user
data space

Read/write

This bit enables the data space mapping for the user operating mode.

Bit

Name

15:06

Not used

1.5.7.5 Instruction Back-Up/Restart Recovery - The process of "backing up" and restarting a partially
completed instruction involves the following.
1.

Performing the appropriate memory management tasks to alleviate the cause of the abort (e.g.,
loading a missing page).

Restoring the general purpose registers indicated in MMRI to their original contents at the start
of the instruction by subtracting the "modify value" specified in MMRI.

Restoring the PC to the "abort-time" PC by loading R 7 with the contents of MMR2, which
contains the value of the virtual PC at the time the "abort-generating" instruction was fetched.

Note that this back-up/restart procedure assumes that the general purpose register used in the program
segment will not be used by the abort recovery routine. This is automatically the case if the recovery
program uses a different general purpose register set.
1.5.7.6 Clearing Status Registers Following Abort - At the end of a fault service routine, bits <15:13>
of MMRO must be cleared (set to 0) to resume error checking. On the next memory reference following
the clearing of these bits, the various registers will resume monitoring the status of the addressing
operations. MMR2 will be loaded with the next instruction address, MMRI will store register change
information, and MMRO will log memory management status information.
1.5.7.7 Multiple Faults - Once an abort has occurred, any subsequent errors that occur while the
memory management registers are frozen will not change MMRO, MMRI or MMR2. The information
saved in MMRO through MMR2 will always refer to the first abort that it detected.
1.5.8 Typical Usage Examples
The memory management unit provides a general purpose memory management tool. It can be used in a
manner as simple or complex as desired. It can be anything from a simple memory expansion device to a
complete memory management facility.

1-22

The variety of possible and meaningful ways to use the facilities offered by the memory management unit
means that both single-user and multiprogramming systems have complete freedom to make whatever
memory management decisions best suit their individual needs.
In most typical applications, the control over the actual memory page assignments and their protection
resides in a supervisory type program which operates in kernel mode. This program sets access keys in such
a way as to protect itself from willful or accidental destruction by other supervisor or user mode programs.
1.5.8.1 Typical Memory Page - When the memory management unit is enabled, the kernel mode
program, a supervisor mode program, and a user mode program each have eight active pages described by
the appropriate page address registers and page descriptor registers for data and eight pages for instructions. Each segment is made up of from 1 to 128 blocks and is pointed to by the page address field of the
corresponding page address register as illustrated in Figure 1-20.

PA331777

VA 157777

PA316777

VA 144777

BLOCK 478 (3910)

BLOCK 1
BLOCK 0

VA 140000 {

PARS

PDR6

PA 312000

:~~

39'0

~478~0~0111
PLF

ED ACF
MA-11054

Figure 1-20 Typical Memory Page

1-23

The memory segment illustrated in Figure 1,-20 has the following attributes.
1.
2.
3.
4.
5.
6.

Page length: 40 blocks
Virtual address range: 140000-144777
Physical address range: 312000-316777
Nothing has been modified (i.e., written) in this page
Read-only protection
Upward expansion

These attributes were determined according to the following scheme.
1.

Page address register (PAR6) and page descriptor register (PDR6) were selected by the active
page field (APF) of the virtual address. (Bits < 15: 13> of the VA = 68.)

The initial address of the page was determined from the page address field of PAR6 (312000 =
.31208 blocks X408 (3210) words per block X 2 bytes per word).
NOTE
The PAR that contains the P AF constitutes what is
often referred to as a base register containing a base
address or a relocation register containing a relocation constant.

The page length (478 + 1 = 4010 blocks) was determined from the page length field (PLF)
contained in page descriptor register PDR6. Any attempts to reference beyond these 4010
blocks in this page will cause a "page length error," which will result in an abort, vectored
through kernel virtual address 250.

The physical addresses were constructed according to the scheme illustrated in Figure 1-13.

The written (W) bit indicates that no locations in this page have been modified (i.e., written). If
an attempt is made to modify any location in this particular page, an access control violation
abort will occur. If this page were involved in a disk swapping or memory overlay scheme, the
W-bit would be used to determine whether it had been modified and, thus, required saving
before overlay.

This page is read-only protected; i.e., no locations in this page may be modified. The mode of
protection was specified by the access control field of PDR6.

The direction of expansion is upward (ED = 0). If more blocks are required in this segment,
they will be added by assigning blocks with higher relative addresses.

The attributes which describe this page can be determined under software control. The parameters
describing the page are loaded into the appropriate page address register (PAR) and page descriptor
register under program control. In a normal application, the particular page, which itself contains these
registers, would be assigned to the control of a kernel mode program.

1-24

1.S.8.2 Nonconsecutive Memory Pages - Higher virtual addresses do not necessarily map to higher
physical addresses. It is possible to set up the page address fields of the PARs so that higher virtual address
blocks may be located in lower physical address blocks as illustrated in Figure 1-21.
Although a single memory page must consist of a block of contiguous locations, consecutive virtual
memory pages do not have to be located in consecutive physical address locations. The assignment of
memory pages is not limited to consecutive nonoverlapping physical address locations.

VA 037777

PA467777

I
I

:
PAR 7

VA 020000
PAF

....

PA460000

VA 017777

PA 560777

I
I

PAR 1
PAR 0

PAF
PAF

PA 541000

MR·11055

Figure 1-21

Nonconsecutive Memory Pages

1-25

1.S.S.3 Stack Memory Pages - When constructing programs, it is often desirable to isolate all program
variables from pure code (i.e., program instructions) by placing them on a register indexed stack. These
variables can then be "pushed" or "popped" from the stack area as needed. (See Chapter 6.) Since stacks
expand by adding locations with lower addresses, when a memory page which contains "stacked" variables
needs more room, it must "expand down," i.e., add blocks with lower relative addresses to the current
page. This mode of expansion is specified by setting the expansion direction bit of the appropriate page
descriptor register to a 1. Figure 1-22 illustrates a typical stack memory page. This page will have the
following parameters.
PAR6: PAF = 3120
PDR6: PLF = 1758 or 1251O{1281O-3)

ED= 1
W = 0 or 1
ACF = nnn (to be determined by programmer as necessary)

NOTE
The W -bit will be set by hardware.
In this case the stack begins 128 blocks above the relative origin of this memcry page and extends
downward for a length of three blocks. A page length error abort will be generated by the hardware when
an attempt is made to reference any location below the assigned area, i.e., when the block number from
the virtual address is less than the page length field of the appropriate page descriptor register.
VA 157777

r----------..,

PA331777

BLOCK 1778 (12710)
BLOCK 1768 (12610)

VA 157500

BLOCK 1758 (12510)

PA331500

PA 312000

VA 140000

PAR 6
PDR 6

ACF
MR·11D56

Figure \-22 Typical Stack Memory Page

1-26

1.5.9 Transparency
In a multiprogramming application, it is possible for memory pages to be allocated such that a program
appears to have a complete 64 Kbyte memory configuration. Using relocation, a kernel mode supervisorytype program can perform all memory management tasks entirely transparent to a supervisor or user mode
program. In effect, a system can use its resources to provide maximum throughput and response to a
number of users, each of whom seems to have a powerful system "all to himself."

1.6 CACHE MEMORY
The statistics from executing programs show that at any given moment, a program spends most of its time
within a relatively small section of code. The KDJ11-A cache memory exploits this phenomenon by using
a small amount of high-speed memory to store the most recently accessed memory locations. Cached code
will execute much faster than noncached code because of the large difference between the access times of
the cache memory and the LSI-II bus main memory.
The following illustrates how the KDJ11-A cache is constructed. It is a direct map (set size one; block size
one), 8 Kbyte cache. Each physical address is logically subdivided into a 9-bit label, 12-bit index, and 1-bit
byte select field as shown in Figure 1-23.

INDEX

LABEL

MA-l1057

Figure 1-23

Cache Physical Address

The index field is used to select the cache entry. The index is 12 bits long, selecting one of 4096 separate
cache entries. Each cache entry contains a 9-bit tag field (TAG), tag parity bit (P), tag valid bit (V), two
bytes of cache data (BO and Bl) and two corresponding byte parity bits (PO and PI). (See Figure 1-24.)

TAG

Iv I

BO
MR-l1058

Figure 1-24 Cache Data Format

1-27

Data is stored 'in the cache when the tag field of the cache entry specified by the index field equals the
label field, the valid bit is set, and no parity errors are seen. When a cache read hit occurs in physical
address <12:1> (i.e., the data is stored in the cache), BI and BO are used as the source of the data. When a
cache read miss occurs (i.e., the data is not stored in the cache), main memory is accessed to obtain the
data.
Data is stored in the cache whenever the cache is allocated. To allocate the cache, the tag field of a cache
entry specified by the index field is set equal to the label field, the V-bit is set, BI and BO are loaded with
the fresh data, and the parity bits are correctly calculated. This guarantees that the next access to this
address will report a cache hit. It should be noted that allocating the cache typically destroys a previously
allocated valid cache entry. The cache is allocated whenever a nonbypassed read miss or word write miss
occurs.
Write cycles are separated into word write and byte write operations. Main memory is always updated
during writes. A cache hit will cause the proper byte(s) to be written in both the cache and in main
memory. This is called writing through the cache. A cache miss during a word write will allocate the
cache; however, since two bytes are allocated together, a byte write only updates main memory. The cache
response matrix is summarized in Table 1-15.
The I/O page (top 8 Kb) is never cached and therefore always reports misses. This is because the I/O page
contains dynamic status registers which, when read, must always convey the latest information.
When the system is powered up, the cache is cleared and correct parity is written into each entry. This is
called flushing the cache. The cache is also flushed on a console start command. Reset has no effect on the
cache.
Table 1-15 Cache Response Matrix

CPU

DMA

Operation

Hit

Miss

Hit

Miss

Read

Read memoryno cache change

Read cached data

Read memoryallocate cache

Write word

Invalidate cacheupdate memory

Update memoryno cache change

Write through
cache to memory

Write memoryallocate cache

Write byte

Invalidate cacheupdate memory

Update memoryno cache change

Write through
cache to memory

Write memoryno cache change

Read bypass

Read memoryinvalidate cache

Read memoryno cache change

Read force
miss

Read memoryno cache change

Write force
miss

Write memoryno cache change

1-28

A potential stale data problem can occur when a DMA device writes to a cached location. The overwritten
cache entry must be invalidated. To avoid this problem, the cache system monitors each DMA transaction
to determine when the DMA transaction invalidates the cache. This also includes block mode DMA which
is possible on the 22-bit LSI-II bus.
For both diagnostic and availability reasons, it is important to be able to turn off the cache via software.
The cache is disabled by setting either of the force cache miss bits, 02 and 03, in the cache control register.
When disabled, all references are forced to miss the cache. That is, main memory is always accessed,
cache parity errors are ignored, and no cache allocation is performed. The cache is essentially removed
from the system. This is different than bypassing the cache. Bypass references access the main memory,
check cache parity, and invalidate the cache entry if previously allocated. Read references that bypass the
cache check for parity errors and will invalidate any address hits.

1.6.1 Parity
The KDJ11-A module has a main memory parity error detection mechanism. The BDAL<16> and <17>
data lines are sampled when BDIN L is negated. BDAL<16> is the parity error signal and the
BDAL<17> bit is the parity enable signal. A DAL parity error occurs when both are asserted.
The cache memory also has a parity error detection mechanism. The cache uses even parity for the even
data bytes stored in the cache memory and odd parity for the odd data bytes stored in the cache memory.
It also uses even parity for the tag field stored in the cache memory.

1.6.1.1 Parity Errors - A parity error indicates that a single bit error has occurred. Parity errors can
occur in either the main memory or the cache memory. A main memory parity error is always fatal since
the data stored in this memory is wrong arid it cannot be restored. This type of parity error will always
cause an abort through virtual address 114 in kernel D space. Cache parity errors are not considered to be
fatal since the data in the cache memory can be updated with the correct data from the main memory.
When they occur, the KDJ11-A module will either abort, interrupt, or continue without an abort or
interrupt. The action is determined by the state of bits 07 and 00 in the cache control register as defined in
Table 1-16.

Table 1-16 Cache Parity Errors

CCR <07>

CCR <00>

Action

o
o

Update cache, interrupt through 114
Update cache only
Update cache, abort through 114 should only be used for diagnostics

X = Either 1 or O.

1-29

1.6.1.2 Multiple Cache Parity Errors - If a cache parity error occurs while the error status from a
previous cache parity error is not cleared from the memory system error register, then no abort or
interrupt occurs. The main memory is accessed again to retrieve the correct data and the corrupted cache
entry data is updated with the correct data. This prevents a cache hardware failure from generating an
infinite series of interrupt or abort service loops.
1.6.2 Memory System Registers
The memory system registers 'consist of the cache control register, the memory system error register, and
the hit/miss register. These registers are used by modules to control the memory system and report any
errors that occur.
1.6.2.1 Cache Control Register (Address: 17777 746) - The cache control register (CCR) controls the
operation of the cache memory. The cache bypass, abort, and force miss functions can be controlled by
software via this register. The cache control register is shown in Figure 1-25 and is described in Table 1-17.
The register is cleared by either power-up or a console start. It is unaffected by the RESET instruction.

WRITE WRONG _ _ _ _ _--'
TAG PARITY

UNCONDITIONAL _ _ _ _ _ _ _-'
CACHE BYPASS
FLUSH CACHE _ _ _ _ _ _ _ _ _ _--1

---'I

WRITE
PARITY
PARITYWRONG
ERROR DATA
AB_O_R_T
_ _ _ _ _ _ _ _ _ _ _---1
___

UNINTERPRETED
FORCE CACHE MISS - - - - - - - - - - - - - - - - - - - - - - '
DIAGNOSTIC MODE - - - - - - - - - - - - - - - - - - - - - - - - - - - '
DISABLE CACHE PARITY INTERRUPT-------------------~
MA·11059

Figure 1-25

Cache Control Register (CCR)

1-30

Table 1-17 Cache Control Register Description
Bit

Name

15: 11

Not used

Status

Function

Write wrong
tag parity

Read/write

When set (1), this bit causes the cache tags to be written with wrong parity
on all update cycles. This will cause a cache tag parity error to occur on the
next access to that location.

Bypass cache

Read/write

When set ()), this bit forces all CPU memory references to go directly to
main memory. Read hits will result in invalidation of accessed locations in
the cache.

Flush cache*

Write only

When set (1), this bit causes the entire contents of the cache to be declared
invalid. Writing a 0 into this bit will have no effect.

Enable parity
error abort

Read/write

This bit is used with bit 0 to define the action taken as a result of a parity
error. This bit is reserved for diagnostic purposes only.

Write wrong
data parity

Read/write

When set (1), this bit causes high and low parity bytes to be written with
wrong parity on all update cycles. This will cause a cache parity error to
occur on the next access to that location.

05:04

U ninterpreted

Read/write

These bits can be set or cleared under program control, but are not interpreted by the KDJ11-A.

03:02

Force miss

Read/write

When either is set, they force all CPU memory references to go directly to
main memory. The cache tag and data stores are not changed. The parity is
not checked. When set (1) these bits remove the cache memory from the
system.

Diagnostic mode

Read/write

When set (1), all non-bypass and non-forced miss word writes will allocate
the cache, irrespective of nonexistent memory (NXM) errors. In addition,
NXM writes will not trap.

Disable cache
parity interrupt

Read/write

Bits <07:00> specify the action to take following a cache parity error. If
both bits are cleared (0) and a parity error occurs, an interrupt through
vector 114 is generated. If bit 07 is cleared and bit 00 is set, a cache parity
error neither aborts the reference nor generates an interrupt. In any case, all
cache parity errors force a memory reference and update the cache with the
fresh data.

* It takes approximately 1 millisecond to flush the cache. During this time DMA and interrupt requests are not serviced and no
data processing occurs.

1-31

1.6.2.2 Hit/Miss Register (Address: 17777752) - The hit/miss register (HMR) records the status of
the most recent cache accesses. The HMR is a shift register that records a hit as a 1 and a miss as a 0 for
the most recent memory reads. A hit represents data located in the cache memory and a miss means the
data is located in the main memory. Bit 00 represents the most recent memory access and is shifted to the
left on successive memory access. The HMR is a read-only register and is shown in Figure 1-26.
1.6.2.3 Memory System Error Register (Address: 17 777 744) - The memory system error register
(MSER) is a read-only register that is cleared by any write reference. The register monitors parity error
aborts and records the type of parity error. The register is shown in Figure 1-27 and is described in Table
1-18. The memory system register is cleared by any write reference, during power-up, and by a console
start. It is unaffected by the RESET instruction.

I I I I I I

00
....~--FLOW

MA-8899

Figure 1-26

It I

11
N7

TUS

Hit/Miss Register (HMR)

PARITY
ERROR
ABORT

02
N:OT

US~D

f i f
I

PARITY
ERROR
HIGH

TAG
PARITY
ERROR
PARITY
ERROR
LOW

Figure 1-27

MR-l1060

Memory System Error Register (MSER)

Table 1-18 Memory System Error Register
Bit

Name

Status

Description

Parity error abort

Read only

This bit is set (1) when cache or memory parity error aborts on instruction. Parity aborts occur on all main memory parity errors and when bit
07 of the CCR is set. A cache parity error occurs on a non-prefetch bus
cycle.

14:08

Not used

07*

Parity error high

Read only

This bit is set (1) when the parity error was caused by the high byte data.

06*

Parity error low

Read only

This bit is set (1) when the parity error was caused by the low byte data.

05*

Tag parity error

Read only

This bit is set (I) when the parity error was caused by the tag field.

04:00

Not used

* Bits <07:05> are individually set when a cache parity error occurs and CCR bit 07 is set. All three bits are set when the CCR
bit 07 is cleared and a cache parity error occurs irrespective of where the error occurred.

1-32

1.7 SOFTWARE SYSTEMS
The KDll1-A module can run the RT-ll, RSX-11 VS.1, RSX-ll PLUS, RSTS/E, UNIX, and micropower PASCAL operating systems. These systems are described in the PDP-ll Software Handbook
(EB 18687-20/80).
Operating systems configuration notes that apply when the floating-point accelerator option (FPll1-AA)
is present are included in Appendix C.

1-33

CHAPTER 2
INSTALLATION

2.1 INTRODUCTION
This chapter discusses the considerations and requirements to configure and install a KDJ1I-A module in
an LSI-II system. The module can be installed in systems using the extended LSI-II bus backplane as well
as existing systems that use one of the standard LSI-II backplanes. The items that must be considered
before installing the module are as follows.
1.

Configuration of the user selectable features.

Selection of an LSI-II compatible backplane and mounting box.

Selection of LSI-ll options compatible with the KDJll-A.

Knowledge of system differences when replacing an LSI-II processor with the KDJII-A
module.

2.2 CONFIGURATION
The KDJII-A has nine jumpers for the user selectable features. The locations of these jumpers are shown
in Figure 2-1 and their functions are described in Table 2-1. A jumper is installed by pushing an insulated
jumper wire (PIN 12-18783-00) onto the two wirewrap pins provided on the module.

Table 2-1

KDJll-A Jumper Identification

Jumper

Function

WI
W2
W3
W4
WS
W6
W7
W8
W9

Bootstrap address bit IS
Bootstrap address bit 14
Power-up option selection bit 02
Bootstrap address bit 13
HALT trap option bit 03
Bootstrap address bit 12
Power-up option selection bit 0 I
Wakeup disable
BEVNT recognition

2-1

2.2.1 Power-Up Options
There are four power-up options available for the user to select. These options are selected by jumpers W7
and W3. The bits are set (1) when the jumpers are removed. A power-up option is selected by configuring
W3 and W7, as described in Table 2-2. A description of each option is provided below.

Table 2-2

Power-Up Options

Option

Power-Up Mode

0
I
2
3

Installed
Installed
Removed
Removed

Installed
Removed
Installed
Removed

PC at 24, PS = 26
Micro-ODT, PS = 0
PC at 173000, PS = 340
Users bootstrap, PS at 340

2.2.1.1 Power-Up Option 0 - The processor reads physical memory locations 24 and 26 and loads the
data into the PC and PS, respectively. The processor either services pending interrupts or starts program
execution, beginning at the memory location pointed at by the PC.
2.2.1.2 Power-Up Option 1 - The processor unconditionally enters micro-ODT with the PS cleared.
Pending service conditions are ignored.
2.2.1.3 Power-Up Option 2 - The processor sets the PC to 173000 and the PS to 340. The processor
then starts program execution, beginning at the memory location pointed to by the pc. This option is used
for the standard bootstrap.
2.2.1.4 Power-Up Option 3 - The processor reads the four bootstrap address jumpers and loads the
result into PC<15:12>. PC<11:00> are set to zero, and the PS is set to 340. The processor then starts
program execution, beginning at the memory location pointed to by the PC.
2.2.2 HALT Option
The HALT option determines the action taken after a HALT instruction is executed in the kernel mode.
At the end of a HALT instruction, the processor checks the BPOK bit 00 before checking the HALT
option bit 03. If BPOK is set, the processor will recognize the HALT option, which is controlled by the W5
jumper. When the jumper is removed, bit 03 is set (1) and the processor will trap to location 4 in the
kernel data space and set bit 07 of the CPU error register. When the jumper is installed, bit 03 reads as a
zero and the processor enters the micro-ODT mode. If BPOK bit 00 is not set when the processor checks,
the option is not recognized and the processor loops until BPOK is asserted and the power-up sequence is
initiated.

2-2

2.2.3 Boot Address
The boot address jumpers selects the starting address for the user's bootstrap program when power-up
option 3 is selected. The state of the highest four bits, <15:12>, is determined by jumpers WI, W2, W4,
and W6, respectively. A bit will be set (1) when the respective jumper for that bit is installed and the bit
will be read as a zero when the jumper is removed. During the power-up sequence, the processor reads the
address determined by bits <15:12> and forces the remaining bits to read as zeros. Therefore, the user's
bootstrap program can reside on any 2048 word boundary.
2.2.4 Wakeup Disable
The KDll1-A module has an onboard wakeup circuit to properly sequence the BDCOK signal. When
jumper W8 is removed, the wakeup circuit is enabled and the module will properly sequence the BDCOK
signal. The wakeup circuit will be disabled when W8 is installed and external logic must be used to
properly sequence the BDCOK signal.
2.2.5 BEVNT Recognition
The LSI-II bus signal BEVNT provides an external event interrupt request to the processor. This feature
is disabled when the W9 jumper is installed and disables the line time clock register. When the jumper is
removed, the BEVNT input is recognized and is under control of the line time clock register. Specifically,
the signal is recognized by the module when bit 06 of the line time clock register is set (1) and is disabled
when bit 06 is not set (0). The line time clock register address is 17 777 546 and is a read/write register.
2.2.6 Factory Configuration
The factory or shipped configuration is described in Table 2-3. The user should review these features and
change them accordingly to match the requirements of the system using the module.

Table 2-3

Factory Configuration

Jumper

Status

Function

WI
W2
W3
W4
W5

Installed
Installed
Removed
Installed
Installed
Installed
Installed
Removed
Removed

Bit 15 set (1)
Bit 14 set (1)
Selects power-up option 2
Bit 13 set (1)
HALT instruction halts in kernel mode
Bit 12 set (1)
Selects power-up option 2
Wakeup circuit is enabled
BEVNT register is enabled

W7
W8
W9

2-3

2.3 DIAGNOSTIC LEDS
The module has four LEDs that monitor the status of the module. The LEDs are designated as DI through
D4 and are located on the edge of the module, as shown in Figure 2-1. The Dl LED is turned on only when
the module is operating in the micro-ODT mode. LEDs D2-D4 are used during the power-up sequence.
These LEDs are turned on at the beginning of the sequence and are turned off upon the successful pass of
the diagnostic. Each LED monitors a primary function of the module operation, as described in Table 2-4.
When troubleshooting the system, the LEDs indicate the most probable failure, as described in Table 2-5.

Table 2-4

LED Functions

LED On

Test Conditions

Micro-ODT is entered.

Module could not do a write and read transaction to the CPU error register. Indicates the microcode is not
running.

Module attempted to read location 0 and timed out or attempted to read location 17 777 700 and did not time
out. Indicates the memory system is not responding.

Module attempted to read location 17 777 560 and timed out. Indicates SLU is not responding.

Table 2-5
LEDs
D1

X
X
X
X
X
X
X
X

On
Off
On
Off
On
Off

On
On
Off
Off
On
On
Off
Off

On
Off

Probable System Failure

Probable Failure

CPU module
LSI-II bus
CPU module
SLU module
CPU module
Memory module
CPU module
Console terminal

On
On
On
Off
Off
Off
Off

2-4

E36

MICROPROCESSOR

CJW9
waCJ
CJW7
W6CJ
CJW5
W4CJ
CJW3
W2CJ
CJWl

E34

E13

CACHE
CONTROL

STATE
SEQUENCER

MR-l1061

Figure 2-1

KDJlI-A Jumper Locations

2-5

2.4 MAINTENANCE REGISTER (ADDRESS 17777750)
The contents of the maintenance register is primarily determined by the user's selection of jumpers WI
through W7. In addition to these, the register bit 00 monitors the status of the LSI-II bus signal BPOK,
and bit 08 monitors the availability of a floating-point accelerator. The register is defined in Figure 2-2 and
its contents are described in Table 2-6. It is a read-only register.
15

11
0

I I I
0

FPJ11-M
AVAILABLE

BOOT
ADDRESS

1
I

~:JER

HJT
OPTION

OK
POWER UP (POK)
OPTION

MR-11044

Figure 2-2

Maintenance Register

Table 2-6 Maintenance Register Bit Description
Bit

Name

Status

Function

15: 12

Boot address

Read only

These bits read the user's boot address selected by
jumpers WI, W2, W4, and W6. A I indicates the jumper is installed and a 0 indicates the jumper is removed.

11:09

Not used

Read only

Read as zeros

FPJlJ-AA
available

Read only

A I indicates the presence of a floating-point accelerator
and a 0 indicates that an accelerator is not installed.

07:04

Module ID

Read only

The 000 I code identifies to the microprocessor that this
is a KDJlJ-A module.

HALT

Read only

This bit reads the status of the W5 jumper. A J indicates
the jumper is removed and a 0 indicates the jumper is
installed.

02:01

Power-up

Read only

These bits read the user's power-up mode selected by
jumpers W3 and W7. A I indicates the jumper is
removed and a 0 indicates the jumper is installed.

POK

Read only

Reads as a I when BPOK H is asserted and the power
supply is okay.

2-6

2.5 POWER-UP SEQUENCE
The power-up sequence for the module is shown in Figure 2-3.

EXPLICITLY SET
CCR<8> TO FLUSH
THE CACHE AND CLEAR
CCR<15:9,7:0>

EXPLICITLY READ
MEMORY LOCATION
177700

EXPLICITLY READ
MEMORY LOCATION
177560

PC@24
PS@26

ENTER
MICRO-ODT
PS = 0

PC = 173000
PS = 340
BEGIN
EXECUTING
CODE

BEGIN EXECUTING CODE

Figure 2-3

KDJ \\-A Power-Up Sequence

2-7

MR-l1062

2.6 POWER-DOWN SEQUENCE
The power-down sequence for the module is shown in Figure 2-4.
2.7 EXIT MICRO·ODT SEQUENCE
The micro-ODT mode is exited by the G command and the module sequence is shown in Figure 2-5.

CONTINUE EXECUTING CODE

SET CPU ERROR
Qt:r../.,.......... TDl\n
............ ....... ,....-,

Ill""\r

VECTOR 4
EXPLICITLY SET
CCR<8> TO FLUSH
THE CACHE
INITIATE POWER UP
SEQUENCE

CLEAR PS
SET CPU ERROR
REG<7>; TRAP
VECTOR 4

BEGIN EXECUTING CODE

Figure 2-5
MR·l1063

Figure 2-4

KD1l1-A Power-Down Sequence

2-8

Micro-ODT Exit Sequence

2.8 MODULE CONTACT FINGER IDENTIFICATION
The LSI-II type modules, including the KDJ11-A, all use the same contact (pin) identification system.
Figure 2-6 identifies the contacts used on a dual-height module. The LSI-II bus signals are carried on rows
A and B, each with 18 contacts on the component side and the solder side. The KDJ11-A signals are
identified along with the LSI-II bus signals in Table 2-7. The pins are identified as follows.
AE2

Module Side Identifier Side (solder side)
Pin Identifier (Pin E)
Row Identifier (Row A)

The positioning notch between the two rows of pins mates with a protrusion on the connector block for the
correct module positioning. A complete description of the backplane and bus operation is provided in
Chapter 5.

BV1

PIN BV2
MR-7177

Figure 2-6

KDJlI-A Module Contacts

2-9

Table 2-7 KDJll-A Module Signals
Component Side
Pin
LSI-ll Bus

KDJll-A

Solder Side
LSI-ll Bus

KDJll-A

AAI
AB1
ACI
ADI
AEI
AF1
AHI
All
AKI
ALl
AMI
ANI
API
AR1
ASI
ATl
AUI
AVI

BIRQ 5 L
BIRQ 6 L
BDAL 16 L
BDAL 17 L
SSPARE 1
SSPARE 2
SSPARE 3
GND
MSPAREA
MSPARE A
GND
BDMRL
BHALT L
BREFL
+12 B
GND
PSPARE 1
+5 B

BIRQ5L
BIRQ 6 L
BDAL 16 L
BDAL 17 L
Not used
SRUN L*
Not used
GND
Not used
Not used
GND
BDMRL
BHALTL
Not used
Not used
GND
Not used
Not used

AA2
AB2
AC2
AD2
AE2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

+5
-12
GND
+12
BOOUTL
BRPLY L
BDINL
BSYNC L
BWTBT L
BIRQ 4 L
BIAKI L
BIALO L
BBS7 L
BDMGI L
BDMGOL
BINIT L
BDAL 0 L
BDAL 1 L

+5
Not used
GND
Not used
BDOUTL
BRPLY L
BDINL
BSYNC L
BWTBTL
BIRQ 4 L
Not used
BIAKL
BBS 7 L
Not used
BDMGL
BINIT L
BDAL 0 L
BDAL I L

BAI
BBI
BCI
BDI
BEl
BFI
BHl
BJI
BKI
BLl
BM1
BNI
BPI
BRI
BSl
BTl
BUI
BVl

BDCOKH
BPOKH
BDAL 18 L
BDAL 19 L
BDAL 20 L
BDAL2lL
SSPARE 4

BDCOKH
BPOKH
BDAL18L
BDAL 19 L
BDAL 20 L
BDAL21L
Not used

BA2
BB2
BC2
BD2
BE2
BF2
BH2

GND

Bj2

MSPAREB
MSPAREB
GND
BSACK L
BIRQ 7 L
BEVNT L
PSPARE 4
GND
PSPARE 2
+5

Not used
Not used
GND
BSACKL
BIRQ7L
BEVNTL
Not used
GND
Not used
+5

BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

+5
-12
GND
+12
BDAL 2 L
BDAL 3 L
BDAL 4 L
BDAL 5 L
BDAL 6 L
BDAL 7 L
BDAL 8 L
BDAL 9 L
BDAL 10 L
BDAL 11 L
BDAL 12 L
BDAL 13 L
BDAL14L
BDAL 15 L

+5
Not used
GND
Not used
BDAL 2 L
BDAL 3 L
BDAL 4 L
BDAL 5 L
BDAL 6 L
BDAL 7 L
BDAL 8 L
BDAL 9 L
BDAL 10 L
BDALllL
BDAL 12 L
BDAL 13 L
BDAL 14 L
BDAL 15 L

* The SRUN L signal is primarily used to drive a panel run light indicator. It is used for BAlI-N and later systems. It indicates
the processor is executing instructions.

2.9 HARDWARE OPTIONS
The KDJl1-A module can be configured into an operating system using a variety of backplanes, power
supplies, enclosures, and LSI-II type modules.
2.9.1 LSI-ll Options
The LSI-II options that are compatible with the KOJ1I-A module are listed in Table 2-8. These options
meet the following requirements and may be used in any KDJ1I-A system configuration.
1.

The backplanes, memory, apd I/O devices must support 22-bit addressing.

These devices must use backplane pins BC1, BDI, BEl, BFI and DCl, 001, DEI, DFl, for the
BDAL bits <18:21> only.

2-10

Table 2-8

LSI-ll Compatible Options

Option

Identification

4X9
4x9
4x8

LSI-II/LSI-I I backplane
LSI-ll/CD backplane
LSI-II/CD and 4 X 5 LSI-I I/LSI-I I backplane

M8631
M8059
MS067
M7915
MS57S

CMOS nonvolatile memory
MaS memory
MaS memory
Multifunction module
PROM/ROM module

AAVII-C
ADVII-C
AXVII-C
DLVII
DLVII-E
DLVII-F

A600S
ASOOO
A0028
M7940
M8017
M8028

D/ A converter
A/D converter
D/ A and A/D combination converter
Asynchronous serial line interface
Asynchronous serial line interface
Asynchronous serial line interface

DLVII-J

MS043

Four asynchronous serial line interfaces (CS Rev. E or later, ECO
MS043-MR002 installed)

DMVII-AC
DMVII-AF
DPVII
DRVII
DRVII-J
DUVII
DZVII
IBVII-A
KPVll-A

MS053-MA
MS064-MA
MS020
M7941
MS049
M7951
M7957
M7954
MS016

Synchronous communications interface
Synchronous communications interface
Programmable synchronous EIA line
Parallel interface
Parallel interface
Programmable synchronous EIA Line
4-line asynchronous EJA multiple
IEEE instrument bus interface
Power-fail and LTC generator (KPVII-B and -C are not compatible)

KWVll-C
LAVII
LPVll
RLV12
RQDXl

A4002
M7949
M8027
M8061
MS639

Programmable real-time clock
LA ISO line printer interface
LA ISO/LP05 printer interface
RLOI/2 controller
MSCP controller for RX50 floppy disk and RD5I Winchester

RXVII
TSV05

M7946
M7I96

RXO I interface
Magnetic tape interface

Name
Backplanes
H9275
H9276
Micro/PDP-II
Memory
MCVll-D*
MSVII-D
MSVII-P
MXVII-B t
MRVII-D
Options

Bus Cable Cards
M9404
M9404-YA

Cable connector
Cable connector with 240 n terminators

M9405
M9405-YA

Cable connector
Connector with 120 fl terminators

Boot ROMs
MXVII-B2

Boot ROMs

Not supported if FPJ11-AA option is used.
Must be Rev. C or later to support FPJ11-AA. Refer to Appendix C.

2-11

2.9.2 Restricted LSI-ll Options
The LSI-II options that are not compatible or restricted for use with the KOJlI-A module are listed in
Table 2-9. Backplanes, memories, or I/O devices that are not capable of 22-bit addressing may generate or
decode erroneous addresses if they are used in systems that implement 22-bit addressing. Memory and
memory-addressing devices which implement only 16- or 18-bit addressing may be used in a 22-bit
backplane, but the size of the system memory must be restricted to the address range of these devices (32
KW for systems with a 16-bit device, and 128 KW for systems with an 18-bit device).
Any device that uses backplarie pins BCl, BOI, BEl, BFI or OCI, 001, DEI, OFI for purposes other
than BOAL <18:21> is electrically incompatible with the 22-bit bus and may not be used without
modification to the hardware.
NOTE
Eighteen-bit DMA devices can potentially work in
Q22 systems by buffering I/O in the 18-bit address
space.
Table 2-9

Restricted or Noncompatible LSI-ll Options

Option

Identification

DDVII-B

6x9

Backplane
(l8-bit addressing only)

H9270

4X4

Backplane
(l8-bit addressing only)

H9273-A

4x9

Backplane
(l8-bit addressing only)

H9281-A, -B, -C

2Xn

Dual-height backplane n = 4, 8, and 12
(I8-bit addressing only)

VTl03 B.P.

4X4

Backplane (54-14008)
(I8-bit addressing only)

MMVI I-A

G653

Core memory
(l6-bit addressing only, Q-Bus required on C/D backplane
connectors)

MRV11-AA

M7942

ROM
(l6-bit addressing only)

MRVII-BA

M8021

UV PROM-RAM
(l6-bit addressing only)

MRVII-C

M8048

PROM/ROM
(l8-bit addressing only)

MSVII-B

M7944

MaS
(l6-bit addressing only)

MSVII-C

M7955

MaS
(l8-addressing only)

Name
Backplanes

Memories

2-12

Table 2-9

Restricted or Noncompatible LSI-ll Options (Cont)

Name

Option

Identification

MSVll-D/E

MS044/MS045

MOS
(\ S-bit addressing only)

MXVll-A

MS047

Multifunction module
OS-bit addressing only on memory, the memory can be
disabled)

AAVll

A6001

D/ A converter
(Use of BCl for purposes other than BDAL IS)

ADVll

AOl2

A/D converter
(Use of BCl for purposes other than BDAL IS)

BDVll

MS012

Bootstrap/terminator
(CS Revision D or later for use with KDFll-A, or KDFll-B,
EDD MS012-ML0002. CS Revision E or later for use in 22bit systems, ECO MS012-ML005)

DLVll-J

MS043

Serial line interface
(CS Revision E or later for use with KDFII-A, or KDFII-B,
ECO MS043-MS002)

DRVll-B

M7950

DMA interface
OS-bit DMA only)

KPVll-B, -C

MSOl6-YB, -YC

Power-fail/line-time clock terminator
(Termination for IS bits only)

KUVll

MSOlS

WCS
(For use with KDll-B and KDll-BA processors only)

KWVII-A

M7952

Programmable real-time clock
(Use of BCI for purposes other than BDAL IS)

REVII

M9400

Terminator, DMA refresh, bootstrap
(Bootstrap for use with KDII-F and KDll-HA processors
only. Termination for IS bits only. DMA refresh may be
used in any system.)

RKVII-D

M7269

RK05 controller interface
(16-bit DMA only)

RLVll

MSOl3 + MS014

RLO 1, 2 controller
(IS-bit DMA only, use of BCl and BLl for purposes other
than BDAL IS AND BDAL 19, requires CD-interconnect
on backplane C/D connectors)

RXV21

MS029

RX02 interface
(IS-bit DMA only)

TEVII

M9400-YB

Terminator
(Termination for IS bits only)

VSVII

M7064

Graphics display
(IS-bit DMA only)

Options

2-13

Table 2-9
Name

Restricted or Noncompatible LSI-ll Options (Cont)

Option

Identification

Bus Cable Cards
M9400-YD

Cable connector
(I8-bit bus only)

M9400-YE

Cable connector with 240 Q terminators
(I8-bit bus only)

M9401

Cable connector
(l8-bit bus only)

Boot ROMs
MXVII-A2

Boot ROMs

2.9.3 Enclosures
The KDJ ll-A module may be installed in a variety of enclosures, including, but not limited to, the
following.
BAll-S Mounting Box - Contains the H9276 backplane and the H7861 power supply. It supports 22-bit
addressing for up to nine quad- or dual-height modules. The H7861 power supply provides 36 A at +5 V
and 5 A at +12 V.
BAII-N Mounting Box - Contains the H9273 backplane and tht; H786 power supply. It supports 18-bit
addressing for up to nine quad- or dual-height modules. The H786 power supply provides 22 A at +5 V
and 11 A at +12 V.
BAll-M Mounting Box - Contains H9270 backplane and the H780 power supply. It supports 18-bit
addressing for four slots, each of which may contain one quad- or two dual-height modules. The H780
power supply provides 18 A at +5 V and 3.5 A at +12 V.
Refer to the PDP-II/23B Mounting Box Technical Manual for a complete description of the BAll-S
mounting box and the Microcomputer Interfaces Handbook for a complete description of the BAll-N
and BAII-M mounting boxes.

2-14

2.10 SYSTEM DIFFERENCES
The KOJII-A module does not have a bootstrap loader, serial line interface, I/O bus map, real-time clock,
or memory. A complete listing of the differences between the module and other LSI-II type processor
modules are listed in Appendix B.
Several key system differences between the KDFII-A and KDJ1I-A modules are highlighted below.
1.

The KOJ1I-A contains an on-board line time clock register (LTC). No LSI-II bus cycle is
started when the LTC register is accessed at its bus address of 17 777 546. The access is
completely contained on board the KDJ11-A and does not use the LSI-II bus. Therefore, an
LSI-II bus option register addressable at 17 777 546 can never be accessed.
An example of a problem this causes with options can be found in the BOVII option (M8012).
The BOVII contains an LTC register which disables recognition of the LSI-II bus signal
BEVNT by continually asserting BEVNT. Since only the negative edge of BEVNT triggers the
interrupt through location 100, recognition of BEVNT is disabled by this action. The LTC
register on the BDVll powers-up with BEVNT disable and will only release its grip when a
programmer writes to the register. When the BOVII is used with a KOJ1I-A, the BDVII 's
copy of the LTC can never be written and, therefore, unless the BOVII is configured with
switch B5 in the off position, all BEVNT interrupts are forever blocked. Switch B5 disconnects
the BEVNT signal from the BOVIl.
In general, no option should contain a register at address 17 777 546.

Bit 11 in the processor status (PS) word selects the alternate register set in the KDJ11-A. This
bit is not implemented in the KDFII-A.

Odd word addresses cause addressing error traps (through location 4) in the KDJ11-A. The
KDF11-A does not generate any error condition when word references are addressed with odd
addresses. Any existing code which generates odd word addresses will not work on the
K0J11-A. The existing BDVll has code that generates odd word addresses.
The BDVII generates the error in the ROM diagnostics. The BDVII can bypass the error code
if the diagnostics are eliminated (switches Al and A2 off).

BDAL <21: 13> are driven as "110000111" during I/O references (BBS7 asserted). The
KOFll-A drives these bits differently: "000000111" when memory management is turned off,
"000011111" when 18-bit memory management is selected, and "111111111" when 22-bit
memory management is selected.

2-15

2.11 KDJll-A SYSTEM
A KDJ II-A module can be installed to upgrade an existing Digital system or a custom-built system using
LSI-ll components. The existing system must be either a KDFll-A or KDFII-B processor. There are
three considerations that must be addressed to upgrade a system.
I.
2.
3.

The boot mechanism
18- or 22-bit addressing system
Single or multiple box system

If the system processor is not a KDFII-A or KDJII-A, such as the 11/03 and 1l/03L, it should not be
considered for upgrade.

In the following upgrade descriptions, the systems have been labeled as being field serviceable or not. A
system which is field serviceable has a bootstrap which meets Field Service requirements. However, there
is no guarantee that the overall system will be field serviceable.

NOTE
It is recommended that the ac and dc loading for the
final configuration be checked for conformance with
the Q-bus loading rules. It is also recommended to
check for overloading on the +S V and + 12 V power
supplies.
For each system upgrade, Table 2-10 lists the parameters for both the old system and the upgraded
system.

2.12 MODULE INSTALLATION PROCEDURE
Certain guidelines should be followed when installing or replacing a KDJII-A module.
I.

Verify dc power before inserting the module in a backplane.

Ensure that no dc power is applied to the backplane when removing or inserting the module.

Verify the configuration of option jumpers.

Insert the KDJll-A module into the first slot or position in the backplane with the component
side facing up.

Ensure that either the module or the selected system components provide the power-up
protocol.

Use a single switch to apply all power to the system.

2-16

Upgrade Choices

Table 2-10

KDJ11-A
BDVII (I)
Not Field
Serviceable

Current System

KDJ11-A/MXVII-B
or MRVll-D w/B2
ROM Field
Serviceable

KDJII-A/MXVII-A
Not Field
Serviceable

IS-Bit Systems
Component upgrades
KDFII-A/MXVII-A
I box
Multibox

X
X

KDFI I-A/BDVI I
I box
Multibox

X
X(2)

X(8)
X(2)

X
X(6)

X
X(2)

X
X(6)

PDP-II/23S system upgrades
KDFII-BA (boot on CPU)
I slot required
I box
Multibox (3)
PDP-II/23A system upgrades
KDFII-A
Same as component upgrades
22-Bit Systems
Component upgrades
KDFII-A/MXVII-A (4)
I box
Multibox (10)

PDP-I 1/23 PLUS or MICRO/PDP-II (7,9)
KDFII-B/BE (boot on CPU)
I slot required
I box
X
Multibox (3, 10)

X(4)

XeS)

NOTES:
1.

Disable the Processor and Memory test and also the BEVNT register on the BDVII.

Use BCV I A and BDV I B expansion cables.

It is not currently possible to expand out of the POP-ll/23-S or MICRO/PDP-II box while maintaining FCC
compliance.

Memory must be disabled.

Must have BDV II ECO M8012-MLOOS installed.

Use BCV2B cable set between the first and second box and BCVIA or BCV2B between second and third box. In a
3-box system, expansion cable set lengths must differ by 4 feet.

Neither the BDY II nor the MXY II-A boot code support the ROSI (10 megabyte Winchester) or the RXSO S-I /4
inch diskettes.

Check ac loading, since termination was removed when the BOY II was removed from the system.

The PDP-II /23 PLUS and MICRO/PDP-II system upgrades will require an extra backplane slot to accommodate
the additional boot module.

10.

Not currently configurable with Digital equipment.

For further information regarding upgrade parts, contact your local Field Service Representative.

2-17

2.13 SPECIFICATIONS
Identification

M8192-YB, -YC

Size

Dual

Dimensions

13.2 cm X 22.8 cm (5.2 in X 8.9 in)

Power Consumption

+5 V ±5% at 4.5 A (maximum) with FP111-AA
+5 V ±5% at 4.0 A (maximum) without FP11l-AA

AC Bus Loads

3.4 unit loads

DC Bus Loads

1 unit load

Environmental
Storage

-40°C to 65°e (-40°F to 150°F) 10% to 90% relative humidity,
non condensing

Operating

For ambient temperatures above 55°e, sufficient air flow must be
provided to limit the module temperature to less than 65°e. For
inlet temperatures below 55°C, air flow must be provided to limit
temperature rise across the module to 10o e.
Derate maximum temperature by IOC (1.8°F) for each 305 m
(1000 ft) above 2440 m (8000 ft).

Instruction Timing

See Appendix A.

DMA Latency

DMA latency is defined as the time between receiving a DMA
request (MDMRL) and granting the request (BDMGO L). The
worst case DMA latency is 2.2 p,seconds.

Interrupt Latency

10 p,seconds without floating-point instructions
20 p,seconds with floating-point instructions (no FP111-AA)
13 p,seconds with floating-point instructions (FP111-AA present)

2-18

CHAPTER 3
CONSOLE ON-LINE DEBUGGING TECHNIQUE (ODT)

3.1 INTRODUCTION
A portion of the microcode in the KOJ1I-A module emulates the capability normally found on a
programmer's console. Since the KOJ1I-A does not have a programmer's console (one with lights and
switches) or a console switch register at bus address 17777570, the terminal at the standard bus address of
17777560 is used to perform console functions. Communication between the processor and the user is via
a stream of ASCII characters interpreted by the processor as console commands. The console terminal
addresses 17777560 through 17777566 are generated in microcode and cannot be changed.
This feature is called the microcode on-line debugging technique, or micro-~OT. The KOJ1I-A microOOT accepts 22-bit addresses, allowing it to access 4088 Kbytes of memory, plus the 8 Kbyte I/O page.
Micro-OOT provides a more sophisticated range of debugging techniques, including access of memory
locations by virtual address.
The differences in use of console OOT in the KOJ1I-A as compared with that in the KOII-F (LSI-II) and
the KOII-HA (LSI-I 1/2) are listed in Appendix E.
3.2 TERMINAL INTERFACE
The KOJ 11-A does not provide a serial line interface on the module. Therefore, the console must interface
with an LSI-II serial line interface module connected into the backplane. This allows the console to
communicate with the KOJ1I-A via the LSI-II bus.
3.3 CONSOLE ODT ENTRY CONDITIONS
The OOT console mode can be entered by the following ways.
1.

Execution of a HALT instruction in kernel mode, provided the HALT TRAP jumper (W5) is
installed.

Assertion of the BHALT signal on the bus. Note that the signal must be asserted lof'~ enough
that it is seen at the end of a macroinstruction by the service state in the processor. ! '
level-triggered, not edge-triggered. Typically, BHALT remains asserted until th
';SOl
enters OOT.

3-1

If power-up mode option 1 has been selected, ODT is entered upon processor power-up.
NOTE
Unlike the KDll-F and KDll-HA, the KDJ11-A
does not enter console ODT upon occurrence of a
double bus error (for example, when R6 points to
nonexistent memory during a bus timeout trap). The
KDJl1-A creates a new stack at location 4 and
traps through 4. If a bus timeout occurs while getting an interrupt vector, the KDJ11-A ignores it and
continues execution of the program, whereas in such
a case the KDll-F and KDll-HA enter console
ODT. Refer to Appendix E for a listing of the different ways certain processors interpret the same
console ODT commands.

OOT causes the following processor initialization upon entry.
1.

Performs a DATI from RBUF (input data buffer at 177775628) and then ignores the character
present in the buffer. This operation prevents the ODT from interpreting erroneous characters
or user program characters as a command.

Prints a carriage return <CR> and line feed <LF> on the console terminal.

Prints the contents of the PC (program counter R 7) in six digits.

Prints a <CR> and <LF>.

Prints the prompt character @'

Enters a wait loop for the console terminal input. The DONE flag (bit 07) in the RCSR at
17777 5608 is constantly being tested via a DATI by the processor for a 1. If bit 07 is a 0, the
processor keeps testing.

3.4 ODT OPERATION OF THE CONSOLE SERIAL-LINE INTERFACE
The processor's microcode operates the serial-line interface in half-duplex mode by using program I/O
techniques rather than interrupts. This means that when the ODT microcode is busy printing characters
using the output side of the interface, the microcode is not monitoring the input side for incoming
characters. Any characters coming in while the ODT microcode is printing characters are lost. Overrun
errors detected by the universal asynchronous receiver/transmitter (UART) will be ignored because the
microcode does not check any error bits in the serial-line interface registers.
Therefore, the user should not "type ahead" to ODT because those characters will not be recognized.
More importantly, if another processor is at the end of the serial line, it must obey half-duplex operation.
In other words, no input characters should be sent from the console terminal until the processor's OOT
output has finished. This restriction does not pertain to echoed characters, however.

3-2

3.4.1 Console ODT Input Sequence
The input sequence for ODT follows. (Upon entry to ODT, the RBUF register at 17777562 is read, but
the character is ignored to prevent the character from being interpreted as a command by the console
ODT.)
1.

Test RCSR bit 07 (DONE flag) of RCSR at 177775608 using a DATI bus cycle; if it is a 0,
continue testing.

If RCSR bit 07 is a 1, read the low byte of RBUF at 177775628 using a DATI bus cycle.

3.4.2 Console OnT Output Sequence
The output sequence of ODT is as follows.
1.

Test bit 07 (DONE flag) of the XCSR at 177775648 using a DATI bus cycle; if it is a 0,
continue testing.

If XCSR bit 07 is ai, write to the XBUF at 177775668 using a DATO bus cycle. The desired
character is in the low byte. The data in the high byte is undefined and is ignored by the serialline interface.

If the interrupt enable (bit 06) in the XCSR is aI, an interrupt will be created to the software when the
proceed (P) console ODT command is used. If a go (G) command is used, all interrupt enables in
peripherals are cleared and an interrupt will not occur.

3.5 CONSOLE OnT COMMAND SET
The ODT command set is listed in Table 3-1 and described in Paragraphs 3.5.1 through 3.5.9. The
commands are a subset of ODT-l1 and use the same command characters. ODT has 10 internal states.
Each state recognizes certain characters as valid input and responds with a question mark (?) to all others.

Table 3-1

Console ODT Commands

Command

Symbol

Function

Slash

Prints the contents of a specified location.

Carriage return

<CR>

Closes an open location.

Line feed

<LF>

Closes an open location and then opens the next
contiguous location.

Internal register
designator

$ or R

Opens a specific processor register.

Processor status
word designator

Opens the PS; must follow an $ or R command.

Starts execution of a program.

Proceed

Resumes execution of a program.

Binary dump

Control-shift-S

Manufacturing use only.

3-3

The parity bit (bit 07) on all input characters is ignored (i.e., not stripped) by console ODT and if the input
character is echoed, the state of the parity bit is copied to the output buffer (XBUF). Output characters
internally generated by ODT (e.g., <CR» have the parity bit equal to O. All commands are echoed except
for <LF>.
In order to describe the use of a command, other commands are mentioned before they have been defined.
For the novice user, these paragraphs should be scanned first for familiarization and then reread for detail.
The word location, as used in the following paragraphs, refers to a bus address, processor register, or
processor status word (PS).
The descriptions of the ODT commands include examples of the printouts that the processor will output to
the console terminal in response to the commands entered by the user. In the examples given, the processor
output is underlined.
3.5.1 / (ASCII 057) - Slash
This command is used to open a bus address, processor register, or processor status word and is normally
preceded by other characters that specify a location. In response to /, ODT will print the contents of the
location (six characters) and then a space (ASCII 40). After printing is complete, ODT will wait for either
new data for that location or a valid close command. The space character is issued so that the location's
contents and possible new contents entered by the user are legible on the terminal.
Example:

@00001000/012525 <SPACE>

where:

@ = ODT prompt character.

octal location in the Q-Bus address space desired by the user (leading
Os are not required).

00001000

command to open and print contents of location.

012525

contents of octal location 1000.

<SPACE>

space character generated by ODT.

The / command can be used without a location specifier to verify the data just entered into a previously
opened location. The / produces this result only if it is entered immediately after a prompt character. A /
issued immediately after the processor enters ODT mode will cause? <CR>, <LF> to be printed because
a location has not yet been opened.
Example:

@1000/012525 <SPACE> 1234 <CR> <CR> <LF>
@/001234 <SPACE>

where:

first line

new data of 1234 entered into location 1000 and location closed
with <CR>.

second line

a / was entered without a location specifier and the previous
location was opened to reveal that the new contents was correctly entered into memory.

3-4

3.5.2 <CR> (ASCII 15) - Carriage Return
This command is used to close an open location. If a location's contents are to be changed, the user should
precede the <CR> with the new data. If no change is desired, <CR> will close the location without
altering its contents.
Example:

@Rl/004321 <SPACE> <CR> <CR> <LF>
@

Processor register Rl was opened and no change was desired, so the user issued <CR>. In response to the
<CR>, OOT printed <CR>,<LF>, and @.
Example:

@R1/004321 <SPACE> 1234 <CR> <CR> <LF>
@

In this case, the user desired to change Rl. The new data, 1234, was entered before the <CR>. OOT
deposited the new data into the open location and then printed <CR>,<LF>, and @. OOT echoes the
<CR> entered by the user before it prints <CR>, <LF>, and @.
3.5.3 <LF> (ASCII 12) - Line Feed
This command is used to close an open location and then open the next contiguous location. Bus addresses
and processor registers will be incremented by two and one, respectively. If the PS is open when an <LF>
is issued, it will be closed and <CR>, <LF>, @ will be printed; no new location will be opened. If the open
location's contents are to be changed, the new data should precede the <LF>. If no data is entered, the
location is closed without being altered.
Example:

@R2/123456 <SPACE> <LF> <CR> <LF>
@R3/054321 <SPACE>

In this case, the user entered <LF> with no data preceding it. In response, OOT closed R2 and then
opened R3. When a user has the last register, R7, open, and issues <LF>, OOT will "roll over" to the first
register, RO.
Example:

@R7/000000 <SPACE> <LF> <CR> <LF>
@RO/123456 <SPACE>

Unlike other commands, OOT will not echo the <LF>. Instead, it will print <CR>, then <LF>, so that
teletype printers will operate properly. To make this easier to decode, OOT does not echo ASCII 0, 2, or
10, but responds to these three characters with? <CR>, <LF>, @.

3-5

3.5.4 $ (ASCII 044), R (ASCII 122) or r (ASCII 162) - Internal Register Designator
The characters $, R or r, when followed by a register number (0 to 7) or PS designator (S), open the
processor register specified. The $ character is recognized to be compatible with ODT-11. The R character
was introduced for its being a one key stroke representation of its function.
Examples:

@$O /000123 <SPACE>
@R7/000123 <SPACE> <LF>
@RO/05432I <SPACE>

If more than one character (digit or S) follows the r, R or $, ODT uses the last character as the register
designator.

3.5.5 S (ASCII 123) or s (ASCII 163) - Processor Status Word Designator
This designator is for opening the processor status word and must be used after the user has entered an r, R
or $ register designator.
Example:

@RS/I00377 <SPACE> 0 <CR> <CR> <LF>
@/000020 <SPACE>

Note that the trace bit (bit 04) of the processor status word cannot be modified by the user. This is to
prevent the PDP-ll program debugging utilities (e.g., ODT-ll), which use the T-bit for single-stepping,
from being accidentally harmed by the user. If the user issues an <LF> while the processor status word is
open, the word is closed and ODT prints a <CR>, <LF>, @. No new location is opened in this case.
3.5.6 G (ASCII 107) or g (ASCII 147) - Go
This command is referred to as a console start and is used to start program execution at a location entered
immediately before the G or g. This function is equivalent to the LOAD ADDRESS and START switch
sequence on other PDP-II consoles.
Example:

@200 G <NULL> <NULL>

The ODT sequence for a G, after echoing the command character, is as follows.
1.

Print two nulls (ASCII 0) so the bus initialize that follows will not flush the G character from
the double buffered UART chip in the serial-line interface.

Load R 7 (PC) with the entered data. If no data is entered, 0 is used. (In the above example, R 7
will equal 200 and that is where program execution will begin.)

The floating-point status (FPS) register and the PS will be cleared to O.

The LSI-II bus is initialized by the processor asserting BINIT L for 12.6 microseconds,
negating BINIT L, and then waiting for 110 microseconds.

The service state is entered by the processor. Anything to be serviced is processed. If the
BHALT L bus signal is asserted, the processor reenters the console ODT state. This feature is
used to initialize a system without starting a program (R 7 is altered). If the user wants to
single-step a program, he/she issues a G and then successive P commands, all done with the
BHALT L bus signal asserted.

3-6

3.5.7 P (ASCII 120) or p (ASCII 160) - Proceed
This command is used to resume execution of a program and corresponds to the CONTINUE switch on
other PDP-II consoles. No machine state visible to the programmer is altered using this command.
Example:

Program execution resumes at the place pointed to by R 7. After the P is echoed, the ODT state is left and
the processor immediately enters the state to fetch the next instruction. If a HALT request is asserted, it is
recognized at the end of the instruction (during the service state) and the processor will enter the ODT
state. Upon entry, the contents of the PC (R 7) will be printed. In this fashion, a user can single-step
through a program and get a PC "trace" displayed on his/her terminal.
3.5.8 Control-Shift-S (ASCII 23) - Binary Dump
This command is used for manufacturing test purposes and is not a normal user command. It is intended to
display a portion of memory more efficiently than the / and <LF> commands do. The protocol is as
follows.
1.

After a prompt character, ODT receives a control-shift~S command but does not echo it.

The host system at the other end of the serial line must send two 8-bit bytes which ODT will
interpret as a starting address. These two bytes are not echoed. The first byte specifies starting
address <15:08> and the second byte specifies starting address <07:00>. Bus address bits
<21:16> are always forced to 0; the DUMP command is restricted to the first 32 K words of
address space.

After the second address byte has been received, ODT outputs 109 bytes to the serial line,
starting at the address previously specified. When the output is finished, ODT will print <CR>,
<LF>, @'
If a user accidentally enters this command, it is recommended that, in order to exit from the
command, two @ characters (ASCII 100) be entered as a starting address. After the binary
dump, the user will get the prompt character @'

3-7

3.6 KDJll-A ADDRESS SPECIFICATION
The KDll1-A micro-ODT accepts 22-bit addresses, allowing it to access 4088 Kbytes of memory, plus the
8 Kbyte I/O page. All I/O page addresses must be entered by users with a full 22 bits specified. For
example, if a user wishes to open the RCSR of the serial-line unit (SLU), he/she must enter 17777560, not
177560.
3.6.1 Processor I/O Addresses
Certain processor and memory management unit registers have I/O addresses assigned to them for
programming purposes. If referenced in ODT, the PS responds to its bus address, 17777776.
The MMU status registers and PAR/PDR pairs can be accessed from ODT by entering their bus address.
Example:

@17777572/000001 <SPACE>

In this case, memory management status register 0 is opened to show the memory management enable bit
set.
The FP11 accumulators cannot be accessed from ODT. Only FP11 instructions can access these registers.

3.6.2 Stack Pointer Selection
Accessing kernel and user stack pointer registers is accomplished in the following way. Whenever R6 is
referenced in ODT, it accesses the stack pointer specified by thePS current mode bits (PS<15:14». This
is done for convenience. If a program operating in kernel mode (PS<15:14> = 00) is halted, and R6 is
opened, the kernel stack pointer is accessed.
Similarly, if a program is operating in user mode (PS<15: 14> = 11); the R6 command accesses the user
stack pointer. If a different stack pointer is desired, PS<15:14> must be set by the user to the appropriate
value, and then the R6 command can be used. If an operating program has been halted, the original value
of PS< 15: 14> must be restored in order to continue execution.
Example:

PS = 140000
@R6/123456 <SPACE>

The user mode stack pointer has been opened.
@RS/140000 <SPACE> 0 <CR> <CR> <LF>
@R6/54322 <SPACE> <CR> <CR> <LF>
@RSjOOOOOO <SPACE> 140000 <CR> <CR> <LF>

In this case, the kernel mode stack pointer was desired. The PS was opened and PS< 15: 14> was set to 00
(kernel mode). Then R6 was examined and closed. The original value of PS<15:14> was restored, and
then the program was continued using the P command.

3.6.3 Entering of Octal Digits
In general, when the user is specifying an address or data, ODT will use the last eight digits if more than
eight have been entered. The user need not enter leading Os for either address or data; ODT forces Os as
the default. If an odd address is entered, the low-order bit is ignored, and a full 16-bit word is displayed.

3-8

3.6.4 ODT Timeout
If the user specifies a nonexistent address, ODT will respond to the bus timeout by printing ?, <CR>,
<LF>, @.
3.7 INV ALID CHARACTERS
In general, any character that ODT does not recognize during a particular sequence is echoed (with the
exception of ASCII codes 0,2, 10, and 12 as noted earlier) and ODT will print ?, <CR>, <LF>, @. ODT
has 10 internal states, with each state having its own set of valid input characters. Some commands are
allowed only when in certain states or sequences; thus an attempt has been made to lower the probability
of a user's unconsciously destroying data by pressing the wrong key. Table 3-2 defines the ODT states and
valid input characters.

Table 3-2

State

Console ODT States and Valid Input Characters
Example of
Terminal Output

Valid Input

0-7

R, S
G
p
Control-shift-S

@R or @$
S

0-7

@1000/123456

0-7

<CR>
<LF>
4

0-7

@Rl/123456

<CR>
<LF>
5

0-7

.@1000

/
G

@Rl or @RS
S

0-7

/
7

@1000/123456 1000

0-7

<CR>
<LF>
8

@Rl/123456 1000

0-7

<CR>
<LF>
9*

@ Control-shift-S

2 binary bytes

*Indicates previous location was opened.

3-9

CHAPTER 4
FUNCTIONAL THEORY

4.1 INTRODUCTION
The KDllI-A is a dual-height microprocessor module on a multilayer printed circuit board for use in an
LSI-II type system. Figure 4-1 shows the interconnecting data paths between the major functional blocks
of the module which include the following.

•
•
•
•
•

the DClii microprocessor
the cache data path and memory
the state sequencer
the input/output control circuits
the bus interface input/output transceivers

The module uses a DClli microprocessor CMOS chip to execute the PDP-II instruction set described in
Chapter 6, control the memory management, support the console micro-ODT and the other architectural
features described in Chapter 1. The DClli initiates all the KDllI-A data transfers and operations. The
KDllI-A provides an interface between the DClli and the LSI-II bus via the A-bus and B-bus data
paths.
An on-board 8 Kbyte direct map cache memory is provided. The cache data path chip is a 68-pin gate
array that contains the control logic to support the cache memory. The cache memory is transparent to all
programs and is designed with high-speed RAM memory. The memory locations currently being accessed
from the system memory are automatically stored in the cache memory. The next time these locations are
accessed, the data is retrieved from the cache memory and eliminates the time-consuming LSI-II bus
transaction. Full parity protection is provided for the cache memory and much of the parity calculations
are done by the cache data path chip. The KDllI-A monitors DMA writes into the system memory to
ensure that the cache data does not become stale. Each DMA write address is checked to see if the address
is cached, and if it is, the cached data is invalidated.
There are four LEDs on the module that provide a visual indication and monitor the status of the module.
Three of the indicators are set during the power-up sequence to indicate when a hardware failure occurs.
The fourth indicator is set when the module is in the micro-ODT mode. There is also a 40-pin socket
provided on the module for the floating-point accelerator option.

4-1

A BUS
RSYNC H

'\/

DMA REG DE L

ALE H
ILOE L

~
RLE L

BUS
RECEIVERS

INITIALIZE/
MAINTENANCE
REGISTER

PARITY L
MEVNT L

~TAGBUS)

MDAL BUS

CONT L

STRB L

1FPA STAT\JS
1 COMP L
.. POINT
ABORT L
FPA ACK L .1 ACCELERATOR 1

ABORT L

.1
1 FLOATING

I (OPTIONAL)

I
I

L ____ J

COMP L

k;-QBUS DE L
DRCP H

GP WRITE L

STRB L

BUS
TRANSMITTERS

CACHE CONTROL

~EL

LJ----,

DVL

A BUS

MISS L
CACHE
MEMORY

ABORT L

PROCESSOR CONTROL

BUFCTL L

MEVNT L

ALE H

DV L

'\.

B BUS

CACHE
DATA PATH PARITY L

r---DCJll·AC
MICROPROCESSOR

V,k
~BUS~

MDALB.v

MISS L

ALE H

B BUS

CONTROL

SYSTEM INPUT

.j::.

GP DATA DE L

BUF CTL L

I-----N

.,/ INPUT

UPA H

RLOE L

OUTPUT
CONTROL

""-

A BUS

STATUS
LEDS

GP WRITE L

BUFCTL L

B BUS
DMA
REGISTER

STATE
SEQUENCER

RLOE L
BUS DE L
LOAD DMA H
DMA REG DE L
GP DATA DE L
ILOE L
DV L
CO NT L
FPA ACK L
DRCP H

SYSTEM
INTERFACE

A BUS

MR-12089

Figure 4-1

Functional Block Diagram

4.2 DCJll MICROPROCESSOR
The DClll is a microprocessor contained on a 60-pin VLSI chip. The input/output pins are shown in
Figure 4-2 and the signals are described below.

MAIO<O>H

AIO<O>H

MDAlO·21 )

MAIO<1>H

AIO<1>H

MAIO<2>H

AIO<2>H

MAIO<3>H

AIO<3>H

PARITY l
MISS l
MINIT H

RIRQ5 H
RIRQ6 H

STRB l

MABORT l

STRB H

MPRDC l

ABORT l

RIRQ7 H

SRUN l

INIT l

...,

PWR FAil l

ALE H
SCTl H

MSTRB l

RIRQ4 H

-F

BUFFER/
DRIVERS

MSCTl l

".~.»:~

ALE l

MALE l

FPA FPE l

UPA H
DCJ11-AC
MICRO PROCESSOR

f----ENB

~ ENA

R HALT H
UPA H

EVNT l
DV l

FPA STL H
RDMR H
CONT l

)

'" DMR l
~

MBS<O>H
MBS<l>H

,..,

.... CONT l
RRPLY H ]

M BUF CTl l

J ClK H
XTAL1

~~
T
XTAlO
MR 12090

Figure 4-2 DCJll-AC Microprocessor

4.2.1 Initialization (MINIT L)
The MINIT L input is asserted by the BDCOK bus signal, which must be asserted for a minimum of 1.5
microseconds. BDCOK H is asserted by the KDllI-A during power-up when jumper W8 is removed. If
jumper W8 is inserted, BDCOK H must be asserted externally in order to start the KDJ11-A. The DCJ11
starts the power-up sequence (described in Chapter 2) after MINIT L is asserted. MINIT L also clears the
PWR FAIL circuit, initializes the state sequencer, asserts the LSI-II bus initialization signal BINIT L,
and turns on the diagnostic LEDs.
4.2.2 Output Signals
The DCJ11 output signals control the various module functions and are described below.
4.2~2.1

Address Input/Output (AIO<03:00> H) - These four signals classify the current transaction as a
bus read, bus word write, bus byte write, GP read, GP write, interrupt acknowledge, or NOP as shown in
Table 4-1.

4-3

AIO Coding

Table 4-1
AIO SIGNAL
"3

Type of Transaction*

I
I
I
I
I
I
I
I
0
0
0

I
I
I
I
0
0
0
0
I
0
0

I
I
0
0
I
I
0
0
0
I
0

I
0
I
0
I
0
I
0

Non I/O (NOP)
General-purpose read
Interrupt acknowledge (read vector)
Instruction stream request read
Read-modify-write, no bus lock
Read-modify-write, bus lock
Data stream read
Instruction stream demand read
General-purpose word write
Bus byte write
Bus word write

The NOP, lACK, bus and general-purpose (GP) transactions are defined as follows.
I.

A NOP transaction is an internal operation that does not require a bus transfer.

A bus transaction uses the DAL bus to access memory, I/O devices or explicit addressable registers.

A general-purpose transaction is used to access interface devices that are not directly addressable by the DAL bus.

Interrupt acknowledge (lACK) transactions are in response to the DCJlI granting an interrupt request.

4.2.2.2 Bank Select, (BSt H, BSO H) - These signals are time multiplexed during the transaction.
During the first portion of a bus transaction, they are used to define the type of address on the MDAL bus.
The addresses identified by the BSO Hand BSI H signals are defined in Table 4-2.
The memory types are all addresses below 17 600 000. The system register types are bus addressable
registers in the address range of 17 777 740 to 17 777 753. The internal register types are addressable
registers that reside within the DCJ11. The external I/O types are addresses greater than 17 577 777
which are neither internal registers nor system registers.
During the second half of the transaction, the BSI H signal indicates the cache bypass status and the BSO
signal indicates the cache force miss status as described below.

BS 1 H Asserted - Cache bypass
Negated - No cache bypass

BSO H Asserted - Cache force miss
Negated - No cache force miss
Table 4-2

Bank Select Address Codes

BSt

BSO

Address Type

0
1
0
I

Memory
KDJlI-A register
. External I/O
Internal DCJll-AC register

0
I
I

4-4

4.2.2.3 Address Latch Enable (ALE L) - The ALE L output is asserted at the start of a transaction and
latches the physical address, the AIO code and the BSI H, BSO H code. The negation of ALE L latches
the cache hit/miss calculated data.
4.2.2.4 Stretch Control (SCTL L) - The SCTL L is asserted for the stretched portion of a transaction
and negated when the DCJ1I receives CONT L input. When SCTL L is asserted, it generates the LSI-II
bus signal BSYNC L that is used for the LSI-II bus read and write transactions. It also activates the
ABORT L input/output signal.
4.2.2.5 Strobe (STRB L) - This signal is asserted at the end of the second DCJ1I clock period and is
negated at the end of the transaction. The address is latched into the cache data path and the LSI-II bus
drivers when STRB L is asserted. The negation of STRB L clears the parity error flip-flop that drives the
PARITY L input to the DClii.
4.2.2.6 Buffer Control (BUFCTL L) - The BUFCTL L is asserted to enable the input control logic for
the A-bus to drive the MDAL bus. It is negated to enable the output control logic for the MDAL bus to
drive the B-bus. The signal is asserted when the DCJ1I is reading data from the A-bus and negated when
the DClil is writing address or data information onto the B-bus.
4.2.2.7 Predecode Strobe (PRDC L) - The signal is asserted for the first two DCll1 clock periods of
any transaction that decodes a PDP-II instruction. It also drives the SRUN L output of the module.
4.2.2.8 Clock (CLK H) - The CLK H output initiates and continuously clocks the timeout logic circuits
used to detect nonexistent memory and the no BSACK L error condition.
4.2.3 Input Signals
The DC] 11 receives status and control information from a variety of input signals. These signals and their
associated functions are described below.
4.2.3.1 MISS L - The MISS L input reports the cache memory hit and miss status during bus read and
write transactions.
4.2.3.2 Data Valid (DV L) - The DV L input is generated by the state sequencer and is used to latch
read data from the MDAL bus.
4.2.3.3 Continue (CONT L) - The CONT L input is generated by the state sequencer and the LSI-Ii
bus signal BRPLY L to indicate that the current stretched transaction can end. It is asserted when the
state sequencer enables the continue output, while the bus signal BRPLY L is negated on the LSI-II bus,
or if the memory location being accessed times out.
4.2.3.4 DMA Request (DMR L) - The DMR L input is used to stall the DCJ11 by stretching the next
transaction. It is asserted by the FPA STL L signal from the floating-point accelerator or by the LSI-II
bus signal BDMR L. The input is sampled at the beginning of the current transaction, and, when present, it
will stretch the next transaction until the DMA or FPA transfer is complete.
4.2.3.5 IRQ <07:04> H - These inputs are coded priority levels from external devices that drive the
LSI-II bus signals BIRQ<07:04> L. The IRQ<07:04> H inputs are interrupt requests to the DCJ1I and
are coded to determine a priority level. The acknowledgement of these inputs is dependent on the current
priority level of the processor status word.
4.2.3.6 HALT H - The HALT H input is driven by the LSI-II bus signal BHALT L and is the lowest
interrupt priority for an external device.

4-5

4.2.3.7 EVNT L - The EVNT L input is driven by the LSI-ll bus signal BEVNT L and has a level-6
priority. This signal can be disabled by installing the W9 jumper or by software clearing bit 6 of the line
time clock (LTC) register.
4.2.3.8 PWR FAIL L - This input is asserted by the power fail flip-flop which is set by the negation of
the LSI-II bus signal BPOK H. The flip-flop is reset by either MINIT L or CLR PWR FAIL L signals.
This input is a nonmaskable interrupt to the DC] 11.
4.2.3.9 PARITY L - The PARITY L input is driven by the cache data path when a parity error is
detected. This input is a nonmaskable interrupt to the DCJ1I.
4.2.3.10 ABORT L - The ABORT L signal is an input/output line that can be driven by the DCJ11 or
an external device such as the cache data path. The signal is used in conjunction with the PARITY L input
to determine when the DC} 11 aborts the current transaction.
4.2.3.11 FPA FPE L - The FPA FPE L input is driven by the floating-point accelerator and is a
nonmaskable interrupt request.
4.2.4 MDAL<21:00>
The MDAL<21 :00> bus is a time-multiplexed data/address bus. The basic bus consists of DAL bits
<15:00> and is bidirectional. DAL bits <21:16> are outputs only and used as the extended bus. The data
being transmitted or received is dependent on the type of transaction being performed by the DClii.
4.2.5 DCJ 11 Timing
The DC} II controls the type of transaction being executed and indicates this to the module circuits by
coding the AIO<03:00> signals. There are six basic transactions performed and these are described as
follows.
4.2.5.1 NOP - This transaction performs a DCJ11 internal operation and does not require the use of the
MDAL bus. The normal transaction is shown in Figure 4-3. The stretched transaction (Figure 4-4) occurs
when DMR is asserted early in the transaction and remains stretched until the CONT input is asserted to
end the transaction.

\\\\\
STRB _ _ _ _

--LJ.!i,.u.J11l

IIJ/i//JI/

Figure 4-3

[//il
'\'\W:>'\w:>._ _ _ _ _ _ _ __
Ala CODE

NOP Transaction

4-6

( (

\\\\\

ALE

I/lJ]

STRB

AIO

[!117[J}

) j

!I/II

\\m

\§~\\SS

AIO CODE

DMA
DMR

'§.~~REQUEST[fJ!l

\SS\\

BUFCTL

TIm

mil

(

\\\\\

SCTL

Rill

( (

) j
(

CONTINUE

(

) )

CONT

\S%

1/10
MA-1207S

Figure 4-4 Stretched NOP Transaction

4.2.5.2 Bus Read - The bus read transaction uses the MDAL bus to read data from cache memory, main
memory, input/output devices or the addressable module registers. These transactions occur during
instruction stream reads, data stream reads and the read portion of read-modify-write. The transaction
reads complete words and if only a byte is required, the DClll ignores the excess byte. A cache bus read
transaction (Figure 4-5) occurs when the physical address scores a hit in the cache memory. The DClli
will abort the transaction if any memory management or address errors assert the ABORT L signal. When
this happens, all current information is ignored and the transaction is immediately aborted.

DAL

««««({«««««««

»»)

{{«{«««««««««

CACHE DATA

PHYSICAL ADDRESS

\\\\\

ALE

IIfIl

_ _--Ll.I!JUJ'IJ! RE~~~ST \'\I.I.i~'\W~_ _ _ _ _ _ _.L.lxmULJU'-j~""'XX'«uuu~__
DMA REQUEST
BS

\\\\\ I/O BANK SELECT

!!III

CACHE STATUS
CACHE HIT

»X«

\\\\\

BUFCTL

»X«

MMU ABORT STATUS

(/i;l
MR-12076

Figure 4-5

Bus Read Transaction

4-7

The non-cache or stretched bus read transaction (Figure 4-6) is used when the data must be accessed via
the LSI-II bus. This occurs when any of the following conditions exist.
1.

2.
3.
4.
5.

Either BSI H or BSO H is set to one indicating an I/O address
Cache bypass is indicated
Cache force miss is indicated
DMR L is asserted
Cache MISS is reported

The BUFCTL Land SCTL L outputs are asserted during the stretched portion of the read transaction.
The data is read by the DCJ1I when data valid (DV L) is asserted. When the transaction is stretched only
because the DMR input was asserted, then DV L is not asserted because it will overwrite the valid data
received from the cache. The transaction will remain stretched until the CaNT L input is asserted to end
the transaction.

PHYSICAL ADDRESS
DAL

(({{({({{(({{( (((ill

ALE
DMA REQUEST

=;
«(({

LSI BUS DATA

~------------~\r~----------------------IIJU

MISS

BUFcn

\\\\\

scn

\r~I____________~~~W

_ ______________________________________-\( {'t--_~CONTINUEfrrf"r----CONT

\\\\\

t /1/U

___________________~\(rl-~g,~VJ
MA-12077

Figure 4-6

Stretched Bus Read Transaction

4.2.5.3 Bus Write - The bus write transaction writes data to memory,I/O devices, or other addressable
registers via the DAL bus. The transaction can write either bytes or words as determined by the Ala code.
The DCJ11 reports any memory management or address errors by asserting the ABORT L signal. This
causes the transaction to be terminated immediately and all data is then ignored.
The write transaction as shown in Figure 4-7 and all bus write transactions are stretched. The SCTL L
signal is asserted and the write data is on the bus during the stretched portion of the transaction. For byte
writes, an even address selects the low byte and an odd address selects the high byte. The data for the
remaining byte is not used.

4-8

l PHYl~J~{{({

DAL

({{{(({{{{{{{{{({{

ALE

---------~~~m

})X{{

DATA OUT

))X{{

CACHE STATUS

: If-I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

I/O BANK SELECT

}}X{{

ABORT
BUFCTL

~ ~f-----------""}}""'})"""}}

tmmW/----------~I~f----------------------

( If

MMU ABORT STATUS

1 ~_~M.:.;;M..;;.U.;.;A.:.;;ND::....:.SY;..:S;.;",TE:;;.M;,;.;A.:.;;B:..;;O.;.;RT.;...;;..ST;;..A;;..TU:..;;S~_

\\\\\

~----------------------------~{~f----------------~~
IllU

\1.I.l.I\\\\.I.....---111-1 _ _ _ _ _-I.u.u.uVI

SCTL

CONTINUE

CONT

---------------;111-----...\'1"""&\\
Figure 4-7

rr- - - t 7
ffT

MR·12078

Bus Write Transaction

4.2.5.4 General-Purpose Read - The general-purpose read transaction accesses non-user-addressable
module hardware. The MDAL address used for general-purpose reads is in the form of 17 777 XXX,
where the "XXX" bits represent the general-purpose read code described in Table 4-3. The codes use
MDAL bits <07:00> to access the hardware.
All general-purpose read transactions (Figure 4-8) are stretched. The DellI reads the data when DV L is
asserted. The transaction is stretched until CONT L is asserted to end the transaction.
Table 4-3

DAL

General-Purpose Read Codes

Code

Function

000

Reads the power-up mode, HALT option, FPJlI-AA option, POK, and boot address
during power-up.

001

Reads FPJlI-AA data (if FPJlI-AA exists).

002

Reads the power-up mode, HALT option, FPJlI-AA option, POK, and boot
address, and clears FPJlI-AA FPS.

003

Acknowledges FPE and reads FEe (floating exception code) register (if FPJlI-AA
exists).

~«(=(<<~«{~({~{(~({(~({(~GP_C_OD_E~)~»}~)}=})}~)}}~})~}}}~}})~m~_G_p_DA_TA_~~\_ _ _ _ _ _ _ _ _~«~«(
!!.".."Ii/,.,.------>,~ ~I---------

\\\\\

\w\\\:~\ _ _LLJ!I/'J,jv

\~\\\~\______-;\

'1-\_ _ _ _ _ _ _ _

LlI/I

\\\\\
( l

CONTINUE

----------------~)~)~~~~

______________________

--"'!1lllrJJ

~~~~

___

~mww

+ !!.~W,.,.----\\\\\
MA-12079

Figure 4-8

General-Purpose Read Transaction

4-9

4.2.5.5 General-Purpose Write - The general-purpose write transaction accesses non-user-addressable
module hardware. The MDAL address used for general-purpose writes is in the form 17 777 XXX, where
the "XXX" bits represent the general-purpose write code described in Table 4-4. The codes use MDAL
bits <07:00> to access the hardware.
All general-purpose write transactions (Figure 4-9) are stretched. The DClli writes the data when SCTL
is asserted during the stretched portion of the transaction. The transaction is stretched until CONT L is
asserted to end the transaction.
Table 4-4

General-Purpose Write Codes

Code

Function

003
014
034
040
100
214
140
220
224
230
234

Writes FPJ1l-AA l6-bit data
Asserts bus reset signal
Indicates exit from console (OOT) mode
Acknowledges parity error
Acknowledges EVNT interrupt
Negates bus reset signal
Acknowledges power fail
Microdiagnostic test 1 passed
Microdiagnostic test 2 passed
Microdiagnostic test 3 passed
Indicates entrance into console (OOT) mode

DAL

{({(({((({{{(((((({(( GP CODE })}))~((({

ALE

\\\\\

GP DATA OUT

p~;____________~}))~m
~~\------------------------

ml/

BUFCTL----------------------------------------~~~~------------------------

~\ \~--------J.jO~/O
\\
CONTINUE
t /'""/0"""'7- - CaNT - - - - - - - - - - - - - - - - \ 1----r"'\\rTT\\\\

SCTL

\u..I.l\\\.....
\

MA-12080

Figure 4-9

General-Purpose Write Transaction

4.2.5.6 lACK - The read interrupt vector transaction acknowledges an interrupt request received on one
of the IRQ<03:00> inputs by reading a device interrupt vector. All interrupt vector transactions (Figure
4-10) are stretched. The device interrupt vector is latched by the DClll when the DV L input is asserted.
4.3 ST ATE SEQUENCER
The state sequencer (Figure 4-11) controls the routing of address and data information on the KDJII-A
module and the LSI-II bus handshaking signals. The module data path buses consist of the A-bus, B-bus
and the MDAL bus. The MDAL bus is bidirectional; it interfaces with the A-bus by the input control logic
and the B-bus by the output control logic. These data paths allow the DClli to transmit addressing and
data information on the B-bus to the LSI-II bus, and receive read data on the A-bus from the LSI-II bus.
The A-bus and B-bus are also connected to the DMA register, which allows DMA addresses to connect to
the B-bus.

4-10

DAl

ALE

««m((((((((({((((

)}))})}}})}}}}}})}}}}})}}}

DEVICE VECTOR

~ ~1-_ _ _ _ _ _ _...u{(.l.U{{{

t:: INTERRUPT lEVEL
------------~
mm------------~~r\--------------------\\\\\
Ii!ll

A'£i'OiiT _ _ _..uLJ.LIJ!I/
BUFCTl

011]

\\\\\

~ ~ SYSTEM ABORT STATUS

\Ss~

\%\

SCTL

,\
[uJ7

) ~

/
(

)

CONT

r, rJ

CONTINUE

~ + LUL7

II/II

\\§\
MR-120B1

Figure 4-10

Interrupt Acknowledge Transaction

AIO<O>H
AIO<I>H
AI0<2>H
AI0<3>H
MBS<O>H
MBS<I>H
ABORT l
ALE l
SCTL H
RX DOUT H
FPA OP l
FPA RDY H
FPA FPE l
FPA STL L
CONT FRM RPlY H
SAS H
FlOVFl H
AO H

RDOUT H

RRPlY H

DRCP H
QBUS OE l
TWTBT H
TDIN H
TDOUT H
TIAK H
TDMG H
TSYNC l
GP DATA OE l
lOAD DMA LATCH H
DMA REG OE l
STATE
SEQUENCER

SEl<O>H
SEl<1 >H
lONGCYCLE H
UPDATE l
CHECK H
TAG CS l
DATA CS BO l
DATA CS Bl l
RAM WE l

TDMG H
RDMR H
MINIT l

DV l
CONT l
END DMA H
UPA H

RlE l
RlOE l
FPA ACK l
IlOE l
ClK IN

ClK PO H
ClK P1 H

TIME DELAY
MR-12Q91

Figure 4-11

State Sequencer

4-11

The steady or quiescent state of the sequencer sets up the module data paths for high-speed cache memory
read operation. When a transaction is stretched, the state sequencer leaves the steady state to control the
module functions and the LSI-II bus. This allows the module to perform memory read/write, interrupt
vector reads, board register read/write, floating-point accelerator memory I/O, general purpose I/O, or
DMA arbitration. A stretched transaction is initiated when SCTL L is asserted. This starts the state
sequencer's clock and, if necessary, generates the LSI-II bus signal BSYNC L. The CLK H output drives
the external delay line to generate two delayed clock inputs of 40 ns and 60 ns. These are used to
determine the cycle time of the sequencer and provide short periods of 80 ns or long periods of 120 ns. The
state sequencer decodes the AIO inputs to identify the type of transaction and the BSI H, BSO H inputs to
classify the address. The state sequencer provides control signals to the functional areas of the module to
\ support the transaction being performed.
4.3.1 DCJll
The state sequencer informs the DClll when valid data is on the MDAL bus by asserting DV L. It also
asserts the CONT L input to the DClll when the transaction is completed. It receives the ABORT Land
ALE L inputs from the DCJl1.
4.3.2 LSI-II Bus Signals
The state sequencer provides the handshaking control signals when the module is transmitting or receiving
data via the LSI-II bus. These signals are TWTBT H, TDIN H, TDOUT H, TIAK H, TDMG Hand
TSYNC. The use of these signals and the LSI-ll bus protocol are described in Chapter 5.
4.3.3 LSI-ll Bus Receivers
The LSI-II bus data is latched into the bus receivers when RLE L is asserted and this data is driven onto
the A-bus when RLOE L is asserted.

4.3.4 LSI-II Bus Transmitters
The LSI-II bus data is latched into the bus transmitters from the B-bus when the DRCP H signal is
asserted and driven onto the LSI-II bus when the Q-BUS OE L signal is asserted.
4.3.S Maintenance Register
The maintenance register data is placed on the A-bus when GP DATA OE L signal is asserted.
4.3.6 DMA Register
The DMA register receives an address from the LSI-II bus via the A-bus and latches it into the register
when LOAD DMA LATCH H is asserted. The address is driven onto the B-bus to check it against the
addresses in the cache memory when DMA REG OE L is asserted.
4.3.7 Cache Data Path
The cache data path provides the SAS H, FLOVFL Hand A<O> H inputs to the state sequencer and
receives the SEL <01:00> H, LONGCYCLE H, UPDATE L and CHECK H from the state sequencer.
The special address status (SAS H) is asserted whenever the maintenance or LTC registers are addressed.
The A<OO> H input represents the status of address bit zero. The flush counter overflow status (FLOVFL
H) input is asserted when the cache memory is being flushed. The LONGCYCLE H output is asserted
each time a location is flushed and increments the address stored in the flush counter to the next location.
The SEL<Ol :00> H provide the select output code used to drive the contents of a register selected in the
cache data path onto the B-bus. The select codes are described in Table 4-5. The UPDATE Land
CHECK H signals are used by the cache data path to control the tag parity function.

4-12

Table 4-5

Select Codes

SEL
I

Selections

The cache data path DAL outputs are tristated.

The contents of the address register is driven on the DAL outputs.

The status of the memory system error register is driven on the DAL outputs, except when the LTC
register is specifically addressed.
The current address/or contents of the flush counter is driven on the DAL outputs.

4.3.8 Cache Memory
The cache memory asserts the COMP L input when an address is not cached. The memory read/write
functions are controlled by the TAG CS L, DATA CS BI-BO L and the RAM WE L outputs. The tag
chip select (TAG CS L) signal is asserted to select the II-bit TAG memory. The high byte data chip select
(DATA CSBI H) and the low byte data chip select (DATA CSBO H) signals are asserted to select words
or bytes stored in the cache memory. The RAM write enable signal (RAMWE L) is asserted to write data,
or negated to read data into the selected memory.
4.3.9 Floating-Point Accelerator
Signals present at the empty floating-point accelerator socket are overridden by FP111-AA signals when
the option is installed. Upon removal of the FP111-AA, the socket returns to the previous operation mode.
4.3.10 Bus Traffic
The on-board buses transfer the addresses and the read/write data to and from the DC111. They also
provide communications between the on-board functions and the system I/O. An overview of the bus
traffic flow is described below.
4.3.10.1 Address Busing - The DCJ 11 uses the B-bus to address cache memory, main memory, and the
I/O devices. The address flow pattern is shown in Figure 4-12.
4.3.10.2 Read Data - The DCJll uses the A-bus to read data from the FPJll-AA, cache memory,
maintenance register, main memory, and the I/O devices. The read pattern is shown in Figure 4-13.
4.3.10.3 Write Data - The De111 uses the A-bus and B-bus to write data to the FPll1-AA, cache
memory, status LEDs, main memory, and the I/O devices. The write data pattern is shown in Figure 4-14.

4-l3

)

A BUS
RSYNC H

- "\
ALE H

ILOE L

:)
BUS
RECEIVERS

UPA H

INPUT
CONTROL

BUF CTL L

B.!QLL..
-4
I

MISS L
GP DATA OE L
ALE H

INITIALIZE/
MAINTENANCE
REGISTER

PARITY L

MEVNT L

MDALB~

CACHE
DATA PATH

-r

PARITY L

CO NT L

STRB L

OBUS OE L
DRCP H

GP WRITE L

STRB L

CACHE CONTROL

~EL

---..f-----,

DVL

ABORT L

.. I ~~~~;ING

1FPA STATUS
1 COMP L
FPA ACK L .1 ACCELERATOR 1
ABORT L
J (OPTIONAL)
1
1
I

A BUS

STATE
SEQUENCER

-- - - _ . -

Figure 4-12

A BU~,
-

Address Traffic Pattern

RLOE L
BUS OE L
LOAD DMA H
DMA REG OE L
GP DATA OE L
ILOE L
DV L
CONT L
FPA ACK L
DRCP H

L ____ J

ABORT L

PROCESSOR CONTROL

BUFCTL L

COMP L

MEVNT L

ALE H

DV L

CACHE
MEMORY

TAG BUS)

"\j

-v'

MISS L

"'I

B BUS

B BUS';

BUS

MDAL BUS
DCJll-AC
MICROPROCESSOR

-",

-0 ,~

SYSTEM I N PUT

.j::.

STATUS
LEOS

GP WRITE L
OUTPUT
CONTROL

BUFCTL L I

t
"'-

)

DMA REG OE L

A BUS

B BUS

DMA
REGISTER

SYSTEM
INTERFACE

BUS
TRANSMITTERS

A BUS

RSYNC H
DMA REG DE L

~
~
~

- '"
r--v
~

BUS
RECEIVERS

A BUS

INPUT
CONTROL

MISS L
GP DATA DE L
ALE H

INITIALIZE/
MAINTENANCE
REGISTER

PARITY L

r--v

MEVNT L

t
L.-_

ILOE L

~'"~
CACHE
DATA PATH

CONT L

STRB L

CACHE
MEMORY

PARITY L

ABORT L
GP WRITE L

CACHE CONTROL

L-r----,

DVL
ABORT L
FPA ACK L

.1
1 FLOATING

IFPA STATUS
1

COMP L

.1 ACCELERATOR 1

ABORT L

•

POINT
1 IOPTIONAL)

A BUS

1
1

L ____ J

-------

Figure 4-13

COMP L

K=-

QBUS DE L
DRCP H
STRB L

~EL

PROCESSOR CONTROL

BUFCTL L

-V

MISS L

MEVNT L

,--.

B BUS

)

ALE H

DV L

B BUS

BUFCTL L

MDAL BUS
DCJll·AC
MICROPROCESSOR

STATUS
LEOS

V
GP WRITE L

OUTPUT
CONTROL

MDALBiV

BUF CTL L

SYSTEM I N PUT

I--

UPA H

"'/V

ALE H

"'-

B BUS
DMA
REGISTER

A BUS

Read Data Busing

- -

STATE
SEQUENCER

RLOE L
BUS DE L
LOAD DMA H
DMA REG DE L
GP DATA DE L
ILOE L
DV L
CO NT L
FPA ACK L
DRCP H

SYSTEM
INTERFACE

BUS
TRANSMITTERS

A BUS
RSYNC H

-'")

DMA REG OE L

~
~

BUS
RECEIVERS

-~
f------

.......

UPA H

INPUT
CONTROL

BUF CTL L

MISS L
GP DATA OE L
ALE H

INITIALIZE/
MAINTENANCE
REGISTER

PARITY L
MEVNT L

_..

OUTPUT
CONTROL

DCJ11-AC
MICROPROCESSOR

./ "k

STRB L

CACHE
MEMORY

OBUS OE L

ABORT L

DRCP H

CACHE CONTROL

IFPA STATUS

.1 ~~~~ING
I
FPA ACK L .1 ACCELERATOR 1
ABORTL

I (OPTIONAL)

COMP L
ABORT L

L _____ J
A BUS

Figure 4-14

STRB L

~EL

L.r-----,

DVL

K=-

MEVNT L

PROCESSOR CONTROL

CO NT L

)

COMP L

GP WRITE L

...

MISS L

V.l

CACHE
DATA PATH PARITY L

,---.

B BUS

ALE H
BUFCTL L

STATUS
LEOS

GP WRITE L

-"
~BUS

DV L

A BUS

- '"

B BUS

MDAL BUS

, -

ILOE L

MDALB~

SYSTEM INPUT.

ALE H

BUFCTL L_ ..

t
A BUS

B BUS

-V DMA

Write Data Busing

STATE
SEQUENCER

RLOE L
BUS OE L
LOAD DMA H
DMA REG OE L
GP DATA OE L
ILOE L
DV L
CO NT L
FPA ACK L
DRCP H

SYSTEM
INTERFACE

BUS
TRANSMITTERS

4.4 CACHE DATA PATH
The cache data path is a multifunction gate array (Figure 4-15) that controls the 8 Kbyte direct map cache
memory. It generates B-bus bits <21:13> as TAG data for the cache memory during cache write
transaction. Parity for the TAG data is generated, predicted, and checked by the gate array. The LTC,
memory system error, and address registers are contained within the array. It also contains the flush
address counter used to clear or flush the cache memory.
4.4.1 DCJII Input Signals
The cache data path decodes the AIO input to identify the transaction and the BS<OI :00> H inputs to
identify the type of address. The SEL<OI :00> H inputs selects the contents of an internal register or
counter as described in Table 4-6.
The cache data path receives the ALE L, STRB Land SCTL L signals to synchronize and control the
cache operation. The assertion of ALE L latches the BS<01:00> H data and gates the GP WRITE L
output. The assertion of STRB L latches the address data into the address register. The negation of STRB
L clears the parity error latch and enables the GP WRITE L output. The assertion of SCTL L enables the
ABORT L output and latches the write data. The negation of SCTL L clears the flush counter and
disables the ABORT L output.
Table 4-6 Output Select Codes

SEL
1

Selections

o
o

The DAL output are tristated
The contents of the address register
Either memory system error or BEVNT register
Flush counter

1
1

1
0
1

4.4.2 State Sequencer Inputs
The cache data path receives CHECK H, UPDATE Land LONGCYCLE H signals to control the cache
memory. The CHECK H and UPDATE L inputs control the generation, checking and prediction of the
TAG parity as described in Table 4-7. The cache data path predicts the parity of address bits <21:13> in
the same way it calculates the TAG parity bit. The predicted parity is driven as the PREDICT PAR H
output signal and compared with the stored TAG parity bit by the data parity logic to determine a hit or
miss. The TAG parity bit is calculated for bits <21: 13> and stored with the TAG data. The parity is
checked when the predicted parity and the stored parity bits are compared within the cache data path to
enable the PERR L output when an error is detected. The LONGCYCLE H input is asserted to increment
the address stored in the flush counter.
Table 4-7 TAG Parity
Update L

Check H

Function

Negated
Negated
Asserted
Asserted

Negated
Asserted
Negated
Asserted

Predict TAG parity
Cheek TAG parity
Generate TAG parity
Undefined

4-17

BS<O>H
BS<I>H

-I

B BUS <21:0>

AI0<3>H
AI0<2>H
AIO<I>H

TAG BUS <8:0>

TAG V BIT H
SEL <O>H

TAG PAR H

SEL <1>H
FLOVFL H

ALE L
STRB L

A<O>

SCTL H

WR WRONG PAR H

CHECK H
UPDATE L

UPA H

LONG CYCLE H
A<16>H
MEMPERR H

.J;>.
I
.......

A<17>H
MEM
TDIN L

~
BO PAR ERR H
Bl PAR ERR H
+50V

TDOUT H

ABORT L
PERR L

I
I

MEM PERR L

GP WRITE L

TDIN H

PREDICT PAR H
CACHE DATA
PATH ARRAY

TBS7 H
SAS H

'V"HN H
UPA H
+5V

TIMEOUT H
M EVNT L
TIMEOUT L
CLR EVNT L
TINIT L
MR-12092

Figure 4-15

Cache Control Logic

4.4.3 System Memory Parity
The system memory parity data is transmitted to the module via A-bus bits <17,16>. These inputs are
monitored and when asserted, a parity error is detected. The MEM PERR H input is asserted and enables
either ABORT Land/or PERR L output.
4.4.4 Cache Memory Parity
The cache memory parity error inputs BO PAR.ERR Hand Bl PAR ERR H are asserted when a parity
error is detected in the cache data memory. The low byte is monitored by BO PAR ERR H and sets bit 06
of the MSER. The high byte is monitored by Bl PAR ERR H and sets bit 07 of the MSER. Either input
can enable the PERR L or ABORT L output.
4.4.5 Timeout
The TIMEOUT H input is enabled when the LSI-II bus fails to assert the RRPL Y H input within 10
microseconds after the TDIN H or TDOUT H signal was asserted by the module. When TIMEOUT is
asserted, it causes the ABORT L output to be asserted and aborts the transaction.
4.4.6 Cache Control Register
The cache control register in the cache data path is shadow copied when the CCR register in the DCJ11 is
written and its contents are used to control the cache memory system. The cache data path logic only
interprets bits 10, 08, 07, 06, 01, and 00. The write wrong parity logic is enabled by bit 10 being set (1)
and it inverts the current TAG parity bit. This will force a TAG parity error the next time that location is
accessed. When bit 08 is set (1), the FLOVFL H output is asserted to flush the cache and the flush counter
is enabled. The bit is reset when the flush counter overflows and SCTL L is negated. The parity error
abort, bit 07, is used with the disable cache parity interrupt, bit 00 to determine the action taken in
response to parity errors. The conditions for bits 07 and 00 are summarized in Table 4-8. The write wrong
data parity logic is enabled when bit 06 is set (1) and it inverts both of the data parity bits. This changes
the high byte even parity to odd and the low byte odd parity to even. This causes a data parity error the
next time that location is accessed. The cache diagnostic mode is enabled when bit 01 is set (1) and the
cache is allocated on all write transactions, regardless of ABORT L, except when bypassing or forcing a
cache miss.
Table 4-8

Parity Error Action

Bit 7

Bit 0

Action

1
1

Abort through vector 114, update cache
Abort through vector 114, update cache
Interrupt through vector 114, update cache
Update cache only

o
o

o
1

4.4.7 Memory System Error Register
The memory system error register is a read-only register that uses bits 15, 07, 06, and 05 to store parity
error data for the memory system. The register is cleared by any write into it. The parity abort, bit 15, is
set whenever a parity abort occurs. A parity abort is defined as any parity error or memory error occurring
during a demand read with the cache control register bit 07 set. When this occurs, bits 07, 06, and 05 are
individually set to identify the type of parity error. Bit 07 is set for a high byte data parity error, bit 06 is
set for a low byte parity error, and bit 05 is set for a tag parity error. However, if the cache control register
bit 07 is not set, then any type of parity error in the cache sets all three bits. The register is read when the
SEL <01,00> bits are set to 1 and 0, respectively, and the LTC register address is not selected. Bit 15 is
always set on main memory parity errors.

4-19

4.4.8 LTC Register
The LTC register is a read/write register that allows software to set bit 06 and enable the EVNT EN
output. The EVNT EN H signal allows the bus BEVNT L input to be routed to the microprocessor as an
external event interrupt. The BEVNT L input can be disabled by the user inserting the W9 jumper. When
enabled, the flip-flop is clocked by REVNT H and the output is gated with EVNT EN H to enable the
MEVNT L signal. The flip-flop is reset by either CLR EVNT L or TINIT L.
4.4.9 Flush Counter
The contents of the cache memory is flushed or cleared during power-up and whenever bit 08 of the cache
control register is set. This requires each address location in the cache to be addressed and cleared. The
process is initiated by the cache control chip asserting FLOVFL H to the state sequencer and zeroing the
flush counter. The contents of the flush counter is used to address the cache memory via the B-bus bits
<12:01>. Every time an address is cleared, the counter is incremented to the next address by the
LONGCYCLE H input from the state sequencer. Flushing the cache memory takes up to 1.3 microseconds and during this time, no DMA or processor activity is performed. The counter contains 12 bits and
when the cache memory is completely flushed, the counter overflows. This causes the cache control chip to
negate the FLOVFL H signal to the state sequencer, indicating the cache flush operation is complete.
4.4.10 Address Register
The address register latches the address received via the B-bus during the early portion of the transaction.
The A<OO> output is driven directly from address bit 00. During the later portion of the transaction, the
SEL <01, 00> H code enables the address to be driven via the B-bus to the main memory and the cache
memory. All 22 bits are used to address the main memory and bits <12:01> are used to address the cache
memory. Register bits <21:13> are placed on the TAG bus as data for storage in the cache memory when
the UPDATE L input is asserted.
4.4.11 CDP Outputs
The cache data path transmits and receives address and data information via the B-bus <21 :00> and the
TAG bus <10:00>, including the TAG V bit and TAG parity bit. The FLOVFL H output is asserted while
the cache memory is being flushed and negated when flushing cycle is completed. The A<OO> H output is
asserted whenever the B-bus bit 00 is set (1). The WR WRONG PAR H output is asserted whenever bit
06 of the CCR is set and writes the wrong parity into the cache memory. The PREDICT PAR H output is
the predicted TAG parity of B-bus bits <21: 13> and it is compared with the stored TAG parity to
determine the hit/miss results. The PERR L and ABORT L outputs are generated by the parity logic and
interpreted by the DClll as described in Table 4-9. The GP WRITE L output is asserted when the AIO
coded input specifies a GP write transaction. The output is used to externally latch the GP data. The TBS7
H output is asserted when the BS <01, 00> H code specifies an external I/O address during the early
portion of the transaction. The SAS H output is asserted whenever the maintenance register or the LTC
register is being addressed. The EVNT EN H output is described in Paragraph 4.4.8.
Table 4-9 Abort and Parity Response
Abort

Parity

DCJll Action

Negated
Negated
Asserted
Asserted

Negated
Asserted
Asserted
Negated

No interrupt or abort
Interrupt; vector to location 114
Abort; vector to location 114
Abort; vector depends upon reason for abort (MMU, Bus timeout, etc.)

4-20

4.5 CACHE MEMORY
The cache memory (Figure 4-16) consists of RAM memory for data, TAG and parity, the data parity
logic, and the hit/miss logic. The cache memory is used to temporarily store data received from the system
memory that the processor is currently using. This allows the DCJ11 to quickly access on-board data
without performing external bus transactions. The physical address is divided into three sections as shown
in Figure 4-17. The byte bit is used to access either high or low bytes of data. The index bits are used as the
address of the cache memory. The label bits are stored as TAG data for valid cache entries. Each cache
entry is organized as shown in Figure 4-18. The high and low bytes of data are stored as data. The low byte
parity (PO) is stored as even parity and the high byte parity (PI) is stored as odd parity. The label bits with
a tag valid bit (V) and the tag parity bit (P2), stored as even parity are stored as TAG data. The byte
parity is calculated by the data parity logic and the hit/miss logic interprets the physical address as a valid
cache address.
The cache memory is controlled by the state sequencer signals DATA CS BO, BIL, TAG CS L, UPDATE
L, and the write enable signal RAM WE L. The WR WRONG PAR H, PREDICT PAR H signals and
the TAG data are controlled by the cache data path chip. The physical addresses are received via the Bbus, the data is read/written via the A-bus and the TAG data is read/written via the TAG bus.
ADDRESS
B BUS<12:1 >

DATA
CACHE
DATA
4KX16

.r:>

BO, B1 DATA CS LV
RAM WE L -

/'-

A BUS <15:0>

- -- ' r

ENM
WR

.....
RAM WE L

WREN

BO, B1 DATA CS L _:::

.....

B BUS<21:1>

rJ
r

ENO

A BUS<1 5:0>. )

BO, B1 PAR ERR H
DATA
PARITY
LOGIC

BO, B1 DATA CS L

PARITY
DATA
4KX1

WWRONG PAR H

BO, B1 PAR OK L

UP DATE L
BO, B1 PAR OUT H

BO, B1 PAR IN H

B BUS <21:13>

PREDICT PAR H

B BUS<12 1>

RAM WE L ;:

CaMP L

TAGVBITH
TAG PAR H
TAG DATA
4KX12

TAG CS L

MISS L
HIT/MISS
LOGIC

~
- -- ....

TAG BUS <8:0>

ENM
WR

MA 12093

Figure 4-16

Cache Memory

4-21

INDEX

LABEL

MR-l1067

Figure 4-17

Cache Memory Physical Address

00
TAG

~P-1~--------------B-1------------~11~_PO~I_______________BO______________~
MA-l1058

Figure 4-18

Cache Data

4.5.1 Cache Data
The cache data RAM is 8 Kbytes of read/write memory that is addressed by the index field, B-bus bits
<12:01>. These bits will always access the data stored in an address location, but the data is not validated
until the label field of the address is verified as the TAG data.
The read/write operations are controlled by the state sequencer. The low byte of cache data is read when
the DATA CS BO L input is asserted and is written when both the DATA CS BO L and RAM WE L
inputs are asserted. The high byte of cache data is read when the DATA CS B1 L input is asserted and is
written when both the DATA CS Bl L and RAM WE L inputs are asserted. The data is routed via the
A-bus to the DCllI.

4.5.2 Data Parity Logic
The data parity logic generates parity bits for the high and low bytes of data. The same logic is used to
check the parity bits when data is read from the cache memory. The high byte stores odd parity and the
low byte stores even parity. The parity logic is shown in Figure 4-19.
The parity logic uses the selected byte data and the UPDATE L signal from the state sequencer to
generate data parity. The UPDATE L input enables the parity generator. The parity generator produces a
parity bit for the high and low bytes based on the number of high inputs. The low byte stores the status of
the parity bit as BO PAR IN H, and the high byte stores the status of the parity bit as Bl PAR IN H when
the data is written into the cache memory. The cache data path can invalidate the data entry by enabling
the WR WRONG PAR H input. This signal uses the exclusive-OR gate to invert the generated parity bit
and store the error in the parity RAM.
The parity bits of the data are checked when the cache memory is accessed. The data is received by the
parity generator and the UPDATE L input is not asserted at this time. The parity data is accessed, the low
byte parity bit is received as BO PAR OUT H, and the high byte parity bit is received as Bl PAR OUT H.
The NAND gate is enabled and functions as an inverter for the BO, Bl PAR OUT H signals. The DATA
CS BO, B1 L enables parity checking for the respective bytes.

4-22

BO PAR OK L
EVEN 1 - - - - - - /

A BUS <7:0>

BO PAR ERR H

ODDI--,~-----------------------

BO PAR O~UT:....:H~.f-"'"

LOW BYTE
PARITY
GENERATOR

BO PAR IN H

UPDATE L

B1 PAR OK L
ODD 1---------1
B1 PAR...,:O...;:..UT.:...H'-'--L_.....

B1 PAR ERR H

EVENI--,~--------------

B1 PAR IN H
A BUS <15:8>

HIGH BYTE
PARITY
GENERATOR

Figure 4-19

Cache Data Parity Logic

4.5.3 Parity Data
The parity RAM has 8 Kbytes of read/write RAM memory that stores the high and low byte data parity
bit. The low byte parity bit is read when DATA CS BO L input is asserted and is written when both the
DATA CS BO L and RAM WE L are asserted. The high byte parity bit is read when DATA CS Bl L
input is asserted and is written when both the DATA CS Bl L and RAM WE L are asserted. The data
parity bits are generated and used by the data parity logic.
4.5.4 TAG RAM
The TAG RAM is an 8 X 11 Kbyte read/write memory. The data consists of the 9-bit label field (address
bits <21: 13», the TAG valid bit (VBIT), and the TAG parity bit (TAG PAR). The data is received from
the cache data path. The data is read when TAG CS input is asserted and is written when both TAG CS
and RAM WE inputs are asserted. These signals are controlled by the state sequencer.
4.5.5 Hit/Miss Logic
The hit/miss logic (Figure 4-20) compares the TAG stored data and bits <21:13> of the current address
on the B-bus for a match condition. The TAG valid bit is also checked. When a match occurs, the current
address is recognized as a valid cache entry and sets the comparator outputs low. If they do not match, the
comparator outputs are set high. The TAG PAR H bit is checked with the PREDICT PAR H bit by the
exclusive-OR gate and the output is low when a match occurs. The MISS Land COMP L gates are
identical and monitor the two comparator outputs, the two data PAR OK L bits, and the output of the
TAG PAR H gate. When all five inputs are low, the MISS Land COMP L outputs are high to indicate a
hit. The MISS L signal goes to the DClli and the COMP L signal goes to the state sequencer to indicate
that the current address is stored in the cache memory. If MISS Land COMP L outputs are low,
indicating one of the inputs is invalid, then the current address is not a valid cache entry and the data is
retrieved from the system main memory.

4-23

A OUTPUT
TAG BUS <B:O>

BOPAROKL---.-----;

MISS L

COMPARATORS
AANO B
B BUS <21 :13>
TAG VB IT H
UPA H
B1PAROKL~~~--4

COMP L

B OUTPUT

MA-10265

Figure 4-20

Cache HIT/MISS Logic

4.6 BUS RECEIVERS
The module receives addresses and data from the LSI-II bus via six 2908 bus transceivers as shown in
Figure 4-21. The state sequencer provides the control signals RLE Land RLOE L that transfer LSI-II
bus data to the module A-bus. The data is latched when RLE L is asserted. The output drivers are then
enabled by RLOE L and transmits the LSI bus data to the module A-bus.
The LSI-II bus control signals are transmitted to the module by the input transceivers. These signals are
used by the module to control the LSI-II bus interface.

BUS
TRANSCEIVER

ABUS<21:0>

RLE L
--,-R:..=L;;:..OE::...=;L~RXEN
'-------'
BIRO<4>L

RIR04 H

BIRO<5>L

RIR05 H

BIRO<6>L

RIR06 H

BIRO<7>L

RIRQ7 H

BHALT L

RHALT H

BOCOK H

MINIT H

BPOK H

BUS INPUT
TRANSCEIVER

BSACK L
BEVNT L

RPOK L
RSACK H
REVNT H

BOMR L

ROMR H

BOOUT L

ROOUT H

BSYNC L

RSYNC H

BRPLY L
UP A H

....

~,..

- -

RRPLY H

rENO
MR-12094

Figure 4-21

KDJ II-A Bus Receivers

4-24

4.7 BUS TRANSMITTERS
The module transmits addresses and data to the LSI-II bus via six 2908 bus transceivers as shown in
Figure 4-22. The address and data inputs are controlled by the LATCH H input. The address is clocked
into the transceiver when the STRB L input from the DCJ1I is asserted. Write data is checked into the
transceiver when DRCP L (normally low) is pulsed from high to low. The DRCP L input is generated by
the state sequencer. The state sequencer enables the QBUS OE L input to transmit the data over the LSI11 bus. When TBS7 H (Bank Select) signal is asserted to indicate the reference is to the I/O page, bits
< 19: 16> are driven as zeros. This allows the KDJ 11-A module to work in a 64 Kbyte system with the
older MSV 11-D memories.
The LSI bus control signals are transmitted by the output transceivers. The state sequencer provides most
of the handshake protocol with the LSI bus. The WAKEUP H signal is enabled by removing the W9
jumper to generate the BDCOK H initialization pulse at power-up.

B BUS <21:0>
TBS7 H

BBS7 L

1WTBT H

BWTBT L

Q BUS OE L

DRCP H

BUS
TRANSCEIVER t - - - - - J
BDAL <21:0>

D _ _ _ _ _ _LA_T_C_H_H_--.t TXCLK
STRB L

TBS7 H

~>--_ _ _ __ BUS ENABLE
FOR BITS
16, 17, 18, 19

QBUSOEL~

+5V

TDOUT H
TDIN H

BUS OUTPUT
TRANSCEIVER

TIAK H
M17

M18

+5V
D5

BDOUT L
BDIN L
BIAK L

TDMG H

BDMGO L

TINIT H

BINIT L

WAKE UP H

BDCOK H

BSYNC L

TSYNC L

----END
MR-12095

Figure 4-22

KDJlJ-A Bus Transmitters

4-25

4.8 OUTPUT CONTROL
The output control logic (Figure 4-23) has 22 D-type latch circuits with output drivers that transfer the
address or data on the MDAL bus to the B-bus. The ILOE L signal from the state sequencer enables the
drivers to the B-bus. A decoder circuit uses the DClll outputs, BUFCTL L and ALE L, to control the
latches. When BUFCTL L and ALE L are negated, the output latches are opened. When either ALE L or ,
BUFCTL L are asserted, the latches are closed.

MDAL BUS <21 :0>

B BUS <21:0>
22
TRANSPARENT
D TYPE
LATCHES

MBUFCTL L

IL LATCH L

>---~EN

ILOE L

DECODER

....;A-=L~E..;.;H-<JI EN
MR-10268

Figure 4-23

DCll J-A Output Control

4.9 INPUT CONTROL
The input control logic (Figure 4-24) uses 16 D-type latch circuits to transfer data from the A-bus to the
MDAL bus. The latches are used as buffers (latches are always opened) and are enabled when the
BUFCTL L input is asserted.

to..

"MDAL BUS <15:0>

A BUS <15:0>. )
16
TRANSPARENT
D TYPE
LATCHES

UPA H _" --------.... LATCH
BUFCTL L,..

..... DE
MA-l0269

Figure 4-24

DCJII-A Input Control

4-26

4.10 DMA MONITOR REGISTER
The KDllI-A does not perform direct DMA transfers, but it does monitor DMA transfers when the
system memory is being updated via DMA. This ensures that the data stored in the cache memory is not
being changed in the system memory. During a DMA transfer, the initial address of the DMA transaction
is transferred over the A-bus. It is clocked into the DMA monitor register when RSYNC H is asserted. For
DMA, DATO, DATIO and DATOB bus cycles, this register is used to address the cache memory in order
to determine if the referenced location is in the cache memory. If it is, the cache data is invalidated.
Successive block mode DMA write cycles (DATOB) are also monitored. Address bits <04:01> of the
initial DMA address are clocked into the DMA monitor register when RSYNC H is asserted. These bits
are incremented to the next address when RDOUT H is negated. Therefore, an entire 16-word aligned
block mode transfer can be monitored. The four-bit incrementor with bits 00 and 05 is designed into the
FPLA shown in Figure 4-25. The remaining 16 bits are controlled by the D-type flip-flops. The DMA
REG OE L signal is controlled by the state sequencer and the INC/LOAD DMA ADR H input is
controlled by the DMA LSI-II bus signals BSYNC Land BDOUT L, and LOAD DMA LATCH H from
the state sequencer.
4.11 INITIALIZATION/MAINTENANCE REGISTER
The initialization/maintenance register allows the user to select the options available as described in
Chapter 2. This register (Figure 4-26) is read by the DClll during the power-up sequence and can be read
by software accessing location 17 777 750 to determine which options were selected. The register uses
jumpers WI to W7 to determine the input state. The W3, W5, and W7 jumpers read as "I" when the
jumper is removed; WI, W2, W4 and W6 jumpers read as "I" when the jumper is inserted. The UPA
input is pulled up to +5 Vdc representing a "I" for bit 04 and a "0" for bits <11:09>. The grounded
inputs represent a "0" for bits <07:05>. The FPA OP L input will be a "I" if an FPllI-AA is mounted
on the module and the PWR OK H input is a "1" when the LSI-II bus signal is asserted. The BDCOK H
signal indicates the dc power is at its proper value.

A BUS <5.0>

A BUS <21:1>

RSYNC H

RDOUT H

)

.....

FPLA TYPE

INC/LOAD
DMA ADR H

B BUS <5:0>

B BUS <21:0>

--------CLK

r--<l ENO
16 D TYPE

A BUS <21:6>

RSYNC H
LOAD DMA
LATCH H

- f

FF
B BUS <21:6>

,.. ~

RSYNC H
DMA REG OE L

---------CLK
_ ENO
MR-l0270

Figure 4-25

DMA Monitor Register

4-27

The low byte of the register is implemented by using eight D-type latches. The data is clocked by the
assertion of ALE L from the DeJ1l. The high byte of the register is implemented by using eight buffer
drivers. The entire register is read onto the A-bus by GP DATA OE L input from the state sequencer.

RPOK L

PWR OK H
A<O> H

+5V
M2 W7
~

DTYPE
LATCH

PUJ<O> H

A<2> H

+5V
M4 W3
~

~"71

A<3> H

PUJ<l> H

A<4> H

+5V
M14 W5

A<l> H

A<5>H

HlT OPT H

A<S>H

UPA H

-::?'

A<7>H

=GP DATA OE l

-- - - ---" EN

ALE H

FPA OP l
UPA H

ClK

A<S> H
DRIVER/
BUFFER

A<9> H
A<10> H

+5V
MS WS

~~ BAJ<12> H

A<ll> H
A<12> H

+5V
MS
~

~~ BAJ<13> H

A<13> H
A<14> H

+5V
Ml0 W2

~~ BAJ<14>H

A<15> H

+5V
M12
r.. Wl
_

BAJ<15> H

GP DATA OE L __

------EN

MR·12071

Figure 4-26

Initialization/Maintenance Register Logic

4-28

4.12 STATUS LEDs
The status LED logic (Figure 4-27) uses an addressable latch circuit for the LED displays and a decoder
circuit to reset either EVNT or PWR FAIL. The DCJ11 controls these functions by performing GP writes
on the B-bus.
The EVNT or PWR FAIL conditions are cleared by GP write codes 100 and 140. The decoder circuit
decodes B-bus bits 05 and 06 and is enabled by the GP WRITE L signal from the cache data path. When
both bits are set, the CLR PWR FAIL L output is enabled and when bit 06 is set and bit 05 negated, the
CLR EVNT L output is enabled.
The status LEDs are controlled by an addressable latch circuit. The circuit is reset by the MINIT L signal
generated at power-up. MINIT L latches all the outputs low, thereby turning on the three diagnostic LEDs
and turning off the ODT LED. It also enables the TINIT L output to initialize the module. During the
initialization period the DClll performs diagnostics, and upon successful completion, it issues GP write
codes to turn off the LEDs. GP code 224 turns off the SLU LED, GP code 230 turns off the MEMORY
OK LED and GP code 220 turns off the SEQUENCING LED. After the initialization period, the DClll
enters its start up mode. If it enters ODT, then GP write code 234 is issued and turns on the ODT LED.
The LED functions are described in Chapter 2.

DECODER

B<6>H
B<5>H

CLR EVNT L

CLR PWR FAIL L

GP WRITE L - - - - . - - - - 0 1 EN

ADDRESSABLE 0
LATCH
1

B<2>H
B<3>H

B<4>H

TINIT H

TINIT L

5
D4

6
7

B<7>H

+5V

CPU
SLU

MEM

------DATA

ODT

RESET

MR-12072

Figure 4-27

Status LEDs Logic

4-29

CHAPTER 5
EXTENDED LSI-11 BUS

5.1 INTRODUCTION
The processor, memory and I/O devices communicate via signal lines that constitute the extended LSI-II
bus. The extended LSI-II bus contains 4 additional address lines (BDAL<2I: 18» in addition to the 3 8
lines of the original LSI-II bus. The four additional address lines extend the 256 Kbyte physical address
space of the LSI-II bus to 4 megabytes. Addresses, 8-bit bytes or 16-bit data words, bus synchronization,
and control signals are sent along these 42 lines. Addresses may be either 16-, 18-, or 22-bits wide,
depending on the addressing capability of the processor installed in the system. The I6-bit data and the
first 16 address bits are time-multiplexed over the same 16 dataladdress lines. Two additional address bits
( < 17: 16» and the memory parity bits are also time-multiplexed over two signal lines. The signal lines are
functionally divided as listed in Table 5-1. Refer to Chapter 2 for a list of the extended LSI-II bus signals.
The LSI-II bus lines may be considered transmission lines that are terminated in their characteristic
impedance (Zo) at both the near and far ends of the bus. The near end of the bus is defined as the first bus
interface slot in the backplane, the far end is the last bus interface slot.
Table 5-1

Summary of Signal Line Functions

Quantity

Function

Bus Signal Mnemonic

Data/address lines

BDAL<15:00>

Memory parity/address lines

BDAL<17:16>

Address lines

BDAL<21 :18>

Address and data transfer
control lines

BSYNC, BDIN, BOOUT,
BWTBT, BBS7, BRPLY

Direct memory access (DMA)
control lines

BDMR, BDMG, BSACK

Interrupt control lines

BIRQ4, BIRQ5, BIRQ6,
BIRQ7, BIAK

System control lines

BPOK, BDCOK, BINIT,
BHALT,BREF,BEVNT

5-1

Most LSI-II bus signals are bidirectional and use a terminating resistor network connected between +5 V
and ground to provide a negated (high) signal level. Devices may be connected to any point along the bus
to receive signals from the near or far end of the bus via high-impedance bus receivers, or to transmit
signals to the near or far end through gated open-collector bus drivers. A bus driver asserts a signal by
causing the line to go from a high level (approximately 3.4 V) to a low level (approximately 0.5 V).
Although bidirectional lines are electrically bidirectional, certain lines carry signals that are functionally
unidirectional. The functionally unidirectional lines carry signals that are required to travel in only one
direction. For example, when a device asserts a bus request signal (BIRQ), the signal always travels from
the requesting device to the processor and never in the reverse direction.
The interrupt acknowledge (BIAK) and direct memory access grant (BDMG) signals are unidirectional
signals that are wired to each LSI-II bus slot in a daisy-chain scheme. These signals are generated by the
processor in response to interrupt and direct memory access requests. Each grant signal is received by a
device (BIAKI or BDMGI) and is conditionally retransmitted (BIAKO or BDMGO) if the grant is not
needed by the device. Device priority is, therefore, determined by distance from the KDJ11-A. Closer
devices have a higher priority than distant devices, since they get a grant first. DMA and I/O interrupt
priorities are discussed in Pargaraphs 5.4 and 5.5.1.
Bus Master/Slave Relationship
Communication between devices on the bus is asynchronous. A master/slave relationship exists throughout each bus transaction. At any time, there is one device that has control of the bus. This controlling
device is termed the bus master. The master device controls the bus when communicating with another
device on the bus, termed the slave. The bus master initiates a bus transaction. The slave device responds
by acknowledging the transaction in progress and by receiving data from, or transmitting data to, the bus
master. The extended LSI-ll bus control signals transmitted or received by the bus master or bus slave
device must complete the sequence according to the protocol established for transferring address and data
information. The processor controls bus arbitration (i.e., it ~'decides" which device is to be bus master at
any given time).
An example of a master/slave relationship is the processor, as master, fetching an instruction from
memory, which is always a slave. Another example is a disk drive, as master, transferring data to memory,
again, as the slave. Any device may be master or slave depending on the circumstances. Communication
on the extended LSI-ll bus is interlocked; therefore, for each control signal issued by the master device,
there must be a response from the slave in order to complete the transfer. It is the master/slave signal
protocol that makes the extended LSI-II bus asynchronous. The asynchronous operation allows both fast
and slow devices to use the bus and eliminates the need for synchronizing clock pulses between the bus
master and slave device.
Since bus cycle completion by the bus master requires response from the slave device, each bus master
must include a timeout error circuit that will abort the bus cycle if the slave device does not respond to the
bus transaction within 10 JLS. The KDJ11-A has a bus timer that restarts the clock when no device
responds to BDIN L or BOOUT L within 10 JLS. An immediate trap to location 4 occurs. The slowest
peripheral or memory device must respond in less than 10 JLS to prevent a bus timeout error.

5-2

5.2 BUS SIGNAL NOMENCLATURE
Throughout the following protocol specifications, bus signals are referred to in several different ways.
1.

In general discussions where timing, polarity, and physical location are unimportant, the base
signal name without any prefixes or suffixes is used. For example:
SYNC, WTBT, BS7, DAL<2l:00> or the DAL lines

Most signals on the backplane are asserted low and are referred to with a prefix character B,
and a suffix (space) L. For example:
BSYNC L, BWTBT L, BBS7 L, BDAL<21:00> L
BPOK Hand BDCOK H are asserted high.

Receivers and drivers are considered part of the bus. Signal inputs to drivers are referred to with
a prefix character T for transmit. For example:
TSYNC, TWTBT, TBS7, TDAL<2l:00>

Signal outputs of receivers are referred to with the prefix character R for received. For
example:
RSYNC, RWTBT, RBS7, RDAL<2l:00>

Whenever timing is important, the designations in items 3 and 4 above are used to reference timing to a
receiver output or driver input. For example, after receipt of the negation of RDIN, the slave negates its
TRPLY for 0 ns (minimum) to 8000 ns (maximum). It must maintain data valid on its TDAL lines until 0
ns (minimum) after the negation of RDIN, and must negate its TDAL lines 100 ns (maximum) after the
negation of its TRPLY.
5.3 DATA TRANSFER BUS CYCLES
Data is transferred between a bus master and slave device to accomplish various functions. The data
transfer bus cycles and their functions are described in Table 5-2.
These bus cycles, executed by bus master devices, transfer 16-bit words or 8-bit bytes to or from slave
devices. The data to be written in the destination byte during byte output operations is valid on the
appropriate BDAL lines. For example, BDAL<15:08> contains the high byte, and BDAL<07:00> contains the low byte. Table 5-3 describes the bus signals used in a data transfer operation.
Table 5-2

Data Transfer Bus Cycles

Bus Cycle
Mnemonic

Description

Function (with respect
to the bus master)

DATI
DATO
DATOB
DATIO
DATIOB
DATBI
DATBO

Data word input
Data word output
Data byte output
Data word input/output
Data word input/byte output
Data block mode input
Data block mode output

Read
Write
Write byte
Read-modify-write
Read-modify-write byte
Read
Read

5-3

Table 5-3

Data Transfer Bus Signals

Mnemonic

Description

Function

BDAL<21 :00> L

22 data/address lines

BDAL<21: 18> L are used for 22-bit extended
addressing; BDAL<17:16> L are used for 18-bit and
22-bit extended addressing, memory parity error,
and memory parity error enable functions;
BDAL<15:00> L are used for 16-bit addressing,
word and byte transfers.

BSYNC L
BDIN L
BDOUT L
BRPLY L

Synchronize
Data input strobe
Data output strobe
Reply

Strobe signals

BWTBT L
BBS7 L

Write/byte control
Bank 7 select

Control signals

Data transfer bus cycles can be reduced to five basic types: DATI, DATO(B), DATIO(B) , DATBI and
DATBO. These transactions occur between the bus master and one slave device selected during the
addressing portion of the bus cycle.
5.3.1 Bus Cycle Protocol
Before initiating a bus cycle, the previous bus transaction must have been completed (BSYNC L negated)
and the device must become bus master. The bus cycle is divided into two parts: an addressing portion, and
a data transfer portion. During the addressing portion; the bus master outputs the address for the desired
slave device (memory location or device register). The selected slave device responds by latching the
address bits and holding this condition for the duration of the bus cycle (until BSYNC L becomes
negated). During the data transfer portion of the bus cycle, the operations performed will vary slightly,
depending on the type of data transfer desired. Paragraphs 5.3.1.2 through 5.3.1.4 describe the data
transfer portion of the various bus cycles.
5.3.1.1 Device Addressing - The device addressing portion of a data transfer bus cycle comprises an
address setup/deskew time and an address hold/deskew time. During the address setup/deskew time, the
bus master does the following.
1.

It asserts TDAL<21:00> with the desired slave device address bits.

It asserts TBS7 if a device in the I/O page is being addressed.

It asserts TWTBT if the cycle is a DATO(B) bus cycle.

It asserts TSYNC 150 ns (minimum) after gating TDAL, TBS7, and TWTBT onto the bus.

During this time the address, RBS7, and RWTBT signals are asserted at the slave bus receiver for at least
75 ns before RSYNC becomes active. Devices in the I/O page ignore the 9 high-order address bits
RDAL<21 : 13> and, instead, decode RBS7 along with the 13 low-order address bits. An active R WTBT
signal indicates that a DATO(B) operation follows, while an inactive RWTBT indicates a DATI or
DA TIO(B) operation.
The address hold/deskew time begins after RSYNC is asserted. The slave device uses the active RSYNC
to clock RDAL address bits, RBS7 and RWTBT, into its internal logic. RDAL<21:00>, RBS7, and
RWTBT will remain active for 25 ns (minimum) after the RSYNC becomes active. RSYNC remains
active for:. the duration of the bus cycle.
5-4

Memory and peripheral devices are addressed similarly, except for the way they respond to RBS7.
Addressed peripheral devices must not decode address bits on RDAL< 17: 13>. Addressed peripheral
devices may respond to a bus cycle only when RBS7 is asserted during the addressing portion of the cycle.
When asserted, RBS7 indicates that the device address resides in the I/O page (the upper 8 Kbyte address
space). Memory devices generally do not respond to addresses in the I/O page; however, some system
applications may permit memory to reside in the I/O page for use as DMA buffers, read-only memory
bootstraps, or diagnostics, etc.
5.3.1.2 DATI - The DATI bus cycle is a read operation that inputs data from the slave device to the bus
master. The operations performed by the bus master and slave device during a DATI are shown in Figure
5-1. The DATI bus cycle timing is shown in Figure 5-2. Data consists of 16-bit word transfers over the bus.
During the data transfer portion of the DATI bus cycle, the bus master asserts TDIN 100 ns (minimum)
after it asserts TSYNC. The slave device responds to RDIN active by asserting:
1.

TRPLY after receiving RDIN and 125 ns (maximum) before TDAL bus driver data bits are
valid;

TDAL<17:00> L with the addressed data and error information.

SLAVE
(MEMORY OR DEVICE)

BUS MASTER
(PROCESSOR OR DEVICE)
ADDRESS DEVICE OR MEMORY
• ASSERT BDAL <21:00> L WITH
ADDRESS AND
• ASSERT BBS7 IF THE ADDRESS
IS IN THE I/O PAGE
• ASSERT BSYNC L

REOUEST DATA
• REMOVE THE ADDRESS FROM
BDAL<21.00> LAND
NEGATE BBS7 L
• ASSERT BDIN L

- --

---,.

----- --

DECODE ADDRESS
• STORE"DEVICE SELECTED"
OPERATION

----- ---

INPUT DATA
• PLACE DATA ON BDAL < 15:00> L
_ _ _ • ASSERT BRPLY L

TERMINATE INPUT TRANSFER
• ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

TERMINATE BUS CYCLE
• NEGATE BSYNC L

------- ---_

OPERATION COMPLETED
- - - - - - - - - . NEGATE BRPLY L

Figure 5-1

DATI Bus Cycle

5-5

MR-6028

T/R DAL

(4)

R DATA

(4)

1 + - - - - - - - - 2 0 0 NS MINIMUM------_.",

TSYNC
100 NS MINIMUM
8 jiSMAXIMUM
TDIN

14-~~-300 NS MINIMUM---~

R RPLY

150NS
MINIMUM

r,100 NS MINIMUM

TBS7

(4)

TWTBT

(4)

TIMING AT MASTER DEVICE

RfT DAL

(4)

RADDR

X
~25NS

(4)

TDATA

ONS MINIMUM

,~ •. _
10 I~~

(4)

100 NS MAXIMUM
o NS MINIMUM

MINIMUM

RSYNC

X
~

MINIMUM
R DIN

300 NS MINIMUM
TRPLY

R BS7

(4)

25 NS MINIMUM
RWTBT

(4)

TIMING AT SLAVE DEVICE
NOTES:
1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX.
4. DON'T CARE CONDITION.

MR·6037

Figure 5-2 DATI Bus Cycle Timing

5-6

When the bus master receives RRPLY, it does the following.
1.

It waits at least 200 ns deskew time and then accepts input data at RDAL<15:00> bus

receivers. RDAL<17:16> are monitored for a possible parity error indication.
2.

It negates TDIN 150 ns (minimum) after RRPLY becomes active.

The slave device responds to RDIN negation by negating TRPL Y and removing read data from TDAL
bus drivers. TRPLY must be negated 100 ns (maximum) prior to removal of read data. The bus master
responds to the negated RRPLY by negating TSYNC.
Conditions for the next TSYNC assertion are as follows.
1.

TSYNC must remain negated for 200 ns (minimum).

TSYNC must not become asserted within 300 ns of the previous RRPL Y negation.

5.3.1.3 DATO(B) - DATO(B) is a write operation. Data is transferred in 16-bit words (DATO) or 8-bit
bytes (DATOB) from the bus master to the slave device. The data transfer output can occur after the
addressing portion of a bus cycle when TWTBT has been asserted by the bus master, or immediately
following an input transfer part of a DATIO(B) bus cycle. The operations performed by the bus master
and slave device during a DATO(B) bus cycle are shown in Figure 5-3. The DATO(B) bus cycle timing is
shown in Figure 5-4.
The data transfer portion of a DATO(B) bus cycle comprises a data setup/deskew time and a data
hold/deskew time. During the data setup/deskew time, the bus master outputs the data on
TDAL<15:00> 100 ns (minimum) after TSYNC is asserted. If it is a word transfer, the bus master
negates TWTBT while gating data onto the bus. If the transfer is a byte transfer, the bus master asserts
TWTBT while gating data onto the bus. During a byte transfer, the condition of BDAL 00 L during the
address cycle selects the high or low byte. If asserted, the high byte (BDAL<15:08> L) is selected;
otherwise, the low byte (BDAL<07:00> L) is selected. An asserted BDAL 16 L at data transfer time will
force a parity error to be written into memory if the memory is a parity-type memory. BDAL 17 L is not
used for write operations. The bus master asserts TOOUT L 100 ns (minimum) after the TDAL and
TWTBT bus driver inputs are stable. The slave device responds to RDOUT by accepting the input data
and asserting TRPLY (8 J.f,S maximum to avoid bus timeout). This completes the data setup/deskew time.
During the data hold/deskew time the bus master negates TOOUT 150 ns (minimum) after the assertion
of RRPLY. TDAL<21 :00> bus drivers remain stable for at least 100 ns after TDOUT negation. The bus
master then negates TDAL inputs.
During this time, the slave device senses ROOUT negation and negates TRPLY. The bus master responds
by negating TSYNC. However, the processor will not negate TSYNC for at least 175 ns after negating
TDOUT. This completes the DATO(B) bus cycle. Before the next cycle, TSYNC must remain unasserted
for at least 200 ns. Also, TSYNC may not assert until 300 ns (minimum) after RRPLY negates.

5-7

BUS MASTER
(PROCESSOR OR DEVICE)

SLAVE
(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY

° ASSERT BDAL <21 :00> L WITH
ADDRESS AND

° ASSERT BBS7 L IF ADDRESS IS
IN THE I/O PAGE

° ASSERT BWTBT L (WRITE
CYCLE)

° ASSERT BSYNC L

-- -- -- ---...-

--0
--

----- ---- --

DECODE ADDRESS
STORE "DEVICE SELECTED"
OPERATION

OUTPUT DATA
° REMOVE THE ADDRESS FROM
BDAL<21:00> LAND NEGATE BBS7 L
° NEGATE BWTBT L UNLESS DATOB
° PLACE DATA ON BDAL < 15:00> L
° ASSERT BDOUT L
__

-------

TERMINATE OUTPUT TRANSFER . . - - ° NEGATE BDOUT L (AND BWTBT L
IF A DATOB BUS CYCLE)
• REMOVE DATA FROM BDAL <15:00> L _

.....

TAKE DATA
RECEIVE DATA FROM BDAL
LINES
_0 ASSERT BRPLY L

---- ---....
---- ---

OPERATION COMPLETED

° NEGATE BRPLY L

TERMINATE BUS CYCLE

...----

° NEGATE BSYNC L

MA-6029

Figure 5-3

DATO or DATO(B) Bus Cycle

5-8

T DAL

=:1

T ADDR

1'-150NS;M

, 0 NS MINIMUM

Xr-----T-D-A-T-A-----

},(r--......!-----(4-)---------

1'--100NS MINIMUM

~100NS

~INIMUM Ir-___~~
______________________+_----~M~I~N~IM~UM

TSYNC

:-:.lI ,....________________

8 pS
MAXI MUM

T DOUT

i-..,.,L----......

j.e-,1----300 NS MINIMUM

R RPLY

T BS7

(4)

TWTBT

ASSERTION = BYTE
t100 NS MINIMUM

--+I

(4)

100 NS
MINIMUM

TIMING AT MASTER DEVICE

R DAL

..IX

_(_4_)_ _

R ADDR

X'-______

R_D_A_T_A_ _ _ _ _.J

(4)

~25 NS MINIMUM

R SYNC
100 NS MINIMUM--C:150 NS MINIMUM
R DOUT

T RPLY

(4)

R BS7

(4)

RWTBT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX.
4. DON'T CARE CONDITION.

MA·1179

Figure 5-4

DA TO or DA TO(B) Bus Cycle Timing

5-9

5.3.1.4 DATIO(B) - The protocol for a DATIO(B) bus cycle is identical to the addressing and data
transfer portions of the DATI and DATO(B) bus cycles. After addressing the device, a DATI cycle is
performed as explained in Paragraph 5.3.1.2; however, TSYNC is not negated. TSYNC remains active
for an output word or byte transfer [DATO(B)]. The bus master maintains at least 200 ns between
RRPLY negation during the DATI cycle and TDOUT assertion. The cycle is terminated when the bus
master negates TSYNC, which follows the same protocol as described for DATO(B). The operations
performed by the bus master and slave device during a DATIO or DATIO(B) bus cycle are shown in
Figure 5-5. The DATIO and DATIO(B) bus cycle timing is shown in Figure 5-6.

SLAVE
(MEMORY OR DEVICE)

BUS MASTER
(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
•
ASSERT BDAL <21 :00> L WITH
ADDRESS
•
ASSERT BBS7 L IF THE
ADDRESS IS IN THE 1/0 PAGE
•
ASSERT BSYNC L

- - - - - - ... DECODE ADDRESS

REQUEST DATA
•
REMOVE THE ADDRESS FROM
BDAL <21:00> L
•
ASSERT BDIN L

.....------

•

---

STORE "DEVICE SELECTED"
OPERATION

-------...INPUTDATA

TERMINATE INPUT TRANSFER
•
ACCEPT DATA AND RESPOND BY
TERMINATING BDIN L

.... ------

-- -- --..,.
A-

OUTPUT DATA
•
PLACE OUTPUT DATA ON BDAL < 15:00 > L
•
(ASSE RT BWTBT L I F AN OUTPUT
BYTE TRANSFER)
•
ASSERT BDOUT L

---

----...

,A--

TERMINATE OUTPUT TRANSFER
•
REMOVE DATA FROM BDAL LINES
•
NEGATE BDOUT L

TERMINATE BUS CYCLE
•
NEGATE BSYNC L
(AND BWTBT L IF IN
A DATIOB BUS CYCLE)

•
•

----

-- -- .....

PLACE DATA ON BDAL < 15:00> L
ASSERT BRPL Y L

COMPLETE INPUT TRANSFER
•
REMOVE DATA
•
NEGATE BRPL Y L

TAKE DATA
•
RECEIVE DATA FROM BDAL LINES
•
ASSERT BRPL Y L

... -- --- -

OPERATION COMPLETED
NEGATE BRPL Y L
•

MR-6030

Figure 5-5

DATIO or DA TIO(B) Bus Cycle

5-10

rRIT DAL

(4)

0 NS MINIMUM

T DATA

TSYNC
100 NS MINIMUM
~
200NS .,~----+-~~~,
MINIMUM

T DOUT
200 NS
MINIMUM

---I

T DIN

R RPLY

100 NS MINIMUM
(4)

(4)

TIMING AT MASTER DEVICE

RT/DAL

~ 25NS

R SYNC

R DOUT

X
.

(4)

T DATA

(4)

R DATA

MINIMUM
NS
-. ~_100
MAXIMUM
25 NS MINIMUM_

- 7 5 NS MINIMUM

125 NS IMAXIMUM

x~25

(4)

NS MINIMUM

- '''''I

Ir
J

MINIMUM

150 NS
MINIMUM

1--150 NS MINIMUM_
R DIN

\'\

T RPLY

150NS

R BS7

R WTBT (4 )

(I+-

300NS _
MINIMUM

)

~ MINIMUM

I+- 75 NS MINIMUM

I-- 75 NS MINIMUM

1/
11\

(4)

I-- 25 NS MINIMUM

i+- 25 NS MINIMUM
ASSERTION ~ BYTE

1;:25 NS MINIMUM
(4)

TIMING AT SLAVE DEVICE

NOTES:
1. TIMING SHOWN AT REOUESTING DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW'
T ~ BUS DRIVER INPUT
R ~ BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX.
4. DON'T CARE CONDITION.

MR-6036

Figure 5-6

DA TIO or DA TIO(B) Bus Cycle Timing

5-11

5.3.1.5 DATBI - The device addressing portion of the cycle is the same as described earlier for other bus
cycles. The bus master gates BDAL<21:00>, BBS7, and the negation of BWTBT onto the bus.
The master asserts the first BDIN 100 ns after BSYNC, and asserts BBS7 a maximum of 50 ns after
asserting BDIN for the first time. BBS7 is a request to the slave for a block mode transfer. BBS7 remains
asserted until a maximum of 50 ns after the assertion of BDIN for the last time. BBS7 may be gated as
soon as the conditions for asserting BDIN are met.
The slave asserts BRPLY a minimum of 0 ns (8 J,tS maximum to avoid bus timeout) after receiving BDIN.
It asserts BREF concurrently with BRPLY if it is a block mode device capable of supporting another
BDIN after the current one. The slave gates BDAL<15:00> onto the bus a minimum of 0 ns after the
assertion of BDIN and 125 ns maximum after the assertion of BRPLY.
The master receives the stable data from 200 ns maximum after the assertion of BRPLY until 20 ns
minimum after the negation of BDIN. It negates BDIN a minimum of 200 ns after the assertion of
BRPLY.
The slave negates BRPLY a minimum of 0 ns after the negation of BDIN. If BBS7 and BREF are both
asserted when BRPLY is negated, the slave prepares for another BDIN cycle. BBS7 is stable from 125 ns
after BDIN is asserted until 150 ns after BRPLY is negated. The master asserts BDIN a minimum of 150
ns after BRPLY is negated and the cycle is continued as before. (BBS7 remains asserted and the slave
responds to BDIN with BRPLY and BREF.) BREF is stable from 75 ns after BRPLY is asserted until a
minimum of 20 ns after BOIN is negated.
If BBS7 and BREF are not both asserted when BRPLY is negated, the slave removes the data from the
bus a minimum of 0 ns and a maximum 100 ns after negating BRPLY. The master negates BSYNC a
minimum of 250 ns after the assertion of the iast BRPLY and a minimum of 0 ns after the negation of
that BRPLY. DATBI bus cycle timing is shown in Figure 5-7.

5.3.1.6 DATBO - The device addressing portion of the cycle is the same as described earlier. The bus
master gates BDAL<21:00>, BBS7, and the assertion of BWTBT onto the bus.
A minimum of 100 ns after BSYNC is asserted, data on BDAL<15:00> and the negated BWTBT are put
onto the bus. The master then asserts BDOUT a minimum of 100 ns after gating the data.
The slave receives stable data and BWTBT from a minimum of 25 ns before the assertion of BDOUT to a
minimum of 25 ns after the negation of BDOUT. The slave asserts BRPLY a minimum of 0 ns after
receiving BDOUT. It also asserts BREF concurrently with BRPLY if it is a block mode device capable of
supporting another BDOUT after the current one.
The master negates BOOUT 150 ns minimum after the assertion of BRPLY. If BREF was asserted when
BDOUT was negated and the master wants to transmit more data in this block mode cycle, then the new
data is gated onto the bus 100 ns minimum after BOOUT is negated. BREF is stable from 75 ns
maximum after BRPLY is asserted until 20 ns minimum after BDOUT is negated. The master asserts
BDOUT 100 ns minimum after gating new data onto the bus and 150 ns minimum after BRPLY negates.
The cycle continues as before.
If BREF was not asserted when BOOUT was negated or if the bus master does not want to transmit more
data in this cycle, then the master removes data from the bus a minimum of 100 ns after negating
BDOUT. The slave negates BRPLY a minimum of 0 ns after negating BOOUT. The bus master negates
BSYNC a minimum of 175 ns after negating BOOUT, and a minimum of 0 ns after the negation of
BRPLY. DATBO bus cycle timing is shown in Figure 5-8.

5-12

TIMES ARE MIN EXCEPT WHERE "0" DENOTES MAX

SIGNALS AT BUS MASTER

TBS7

T ADDRESS

RIT DAL

_ 1 5 D t l 0 0 ...

I
I
_2000~ -O~

XXXXX

R DATA

-200 0 -

-0--

XXXXXX

R DATA

TSYNC

250

-- ~ggoo '----I
I

--lOlTDIN
tl

~15°1

_200 0
2000

~300

J
t7

(

R RPLY
R REF

------------------~

address to T SYNC

150 ns min

address hold

100 ns min

T SYNC to T DIN

100 ns min

T DIN to R RPLY
T (drive) + T (prop) + T (receive) + T (delay)
+ T (drive) + T (prop) + T (receive)

R RPLY to data

200 ns max

R RPLY to T DIN

200 ns min

T DIN to R RPLY
T (drive) + (prop) + T (receive) + T (delay)
+ T (drive) + T (prop) + T (receive)

R RPLY to data

o ns min

R RPLYto T DIN

150 ns min

Tcell

t4 + t6 + t7 + t9

- since t6 must be > t5 for master

to have valid data and t9 > t8

MR-0586-0789

Figure 5-7

DA TBI Bus Cycle Timing

5-13

TIMES ARE MIN. EXCEPT WHERE ..... DENOTES MAX.

SIGNAL AT BUS MASTER

TBS7

TDAL

150

TSYNC

ADDRESS

DATA

I-- 100--1

100

_100

r- 1

~'OOi

TDOUT

DATA

--j

I"'~--- 300

----t-I

100

r'''l '''--'''+'''1
I

t1
Lt7j
R RPLY
RREF~

____________________

~--~

address to T SYNC

150 ns min

address hold

100 ns min

data to T DOUT

100 ns min

T DOUT to R RPLY
T (drive) + T (prop) + T (receive) + T (delay)
+ T (drive) + T (prop) + T (receive)
R RPLY to T DOUT

T DOUr to R RPlY

~--~I

t41

150 ns mm

T (drive) + T (prop) + T (receive) + T (delay)
+ T (drive) + T (prop) + T (receive)
t7

R RPLY to T DOUT

150 ns mm

Teell

t3 + t4 + t5 + t6 + t7

-smcet3<t7
MR-0586-0790

Figure 5-8

DATBO Bus Cycle Timing

5.4 DIRECT MEMORY ACCESS (DMA)
The direct memory access (DMA) capability allows direct data transfers between I/O devices and
memory. This is useful when using mass storage devices (e.g., disk drives) that move large blocks of data
to and from memory. A DMA device only needs to know the starting address in memory, the starting
address in mass storage, the length of the transfer, and whether the operation is read or write. When this
information is available, the DMA device can transfer data directly to or from memory.
DMA is accomplished after the processor has passed bus mastership to the highest-priority DMA device
that is requesting the bus. The processor arbitrates all requests and grants the bus to the DMA device
located electrically closest to the processor. A DMA device remains bus master until it relinquishes its
mastership. The following control signals are used during bus arbitration.
Signal

Name

BDMGI L
BDMGOL
BDMRL
BSACK L

DMA Grant Input
DMA Grant Output
DMA Request Line
Bus Grant Acknowledge
5-14

A DMA transaction is divided into three phases: the bus mastership acquisition phase, the data transfer
phase, and the bus mastership relinquish phase. The operations performed by tthe processor and bus master
during the DMA request/grant sequence are shown in Figure 5-9. The DMA request/grant bus cycle
timing is shown in Figure 5-10.
During the bus mastership acquisition phase, a DMA device requests the bus by asserting TDMR. The
processor arbitrates the request and initiates the transfer of bus mastership by asserting TDMG. The
maximum time between BDMR L assertion by the DMA device and BDMGO L assertion by the processor
is DMA latency. This time is processor-dependent. The KDJ11-A asserts TDMG 2.2 /-LS (maximum) after
the assertion of RDMR.

BUS MASTER
(CONTROLLER)

KDJll-A PROCESSOR
(MEMORY IS SLAVE)

GRANT BUS CONTROL
• NEAR THE END OF THE
CURRENT BUS CYCLE
(BRPLY L IS NEGATED),
ASSERT BDMGO LAND
INHIBIT NEW PROCESSOR
GENERATED BSYNC L FOR
THE DURATION OF THE
DMA OPERATION

- -

- - -...

______

TERMINATE GRANT
SEQUENCE
• NEGATE BDMGO LAND
WAIT FOR DMA OPERATION TO BE COMPLETED

• MONITOR TRANSACTION TO
INVALIDATE CACHE IF
CACHE HIT

______

RESUME PROCESSOR
______
OPERATION
..--• ENABLE PROCESSORGENERATED BSYNC L
(PROCESSOR IS BUS
MASTER) OR ISSUE
ANOTHER GRANT IF BDMR
L IS ASSERTED

Figure 5-9

REQUEST BUS
• ASSERT BDMR L

ACKNOWLEDGE BUS
MASTERSHIP
• RECEIVE BDMG
• WAIT FOR NEGATION OF
BSYNC LAND BRPLY L
• ASSERT BSACK L
• NEGATE BDMR L

EXECUTE A DMA DATA
TRANSFER
• ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS
OF DATA AS DESCRIBED
FOR DATI. OR DATO BUS
CYCLES
• RELEASE THE BUS BY
TERMINATING BSACK L
(NO SOONER THAN
NEGATION OF LAST BRPLY L)
AND BSYNC L

WAIT 4 "S OR UNTI L
ANOTHER FIFO TRANSFER
IS PENDING BEFORE
REQUESTING BUS AGAIN.

DMA Request/Grant Sequence

5-15

SECOND
REQUEST
DMA LATENCY

r-r-r-r-r-TTT7/7/7
//////1//1/1

TDMR

t o NS MINIMUM
R DMG

TSACK

RfT SYNC

1
250 NS MINIMu:
300 NS MINIMUM1

o NS MINIMUM--j

RfT RPLY

TDAL
(ALSO BS7,
WTBT, REF)

r-r--______________________--JIC

0 NS MINIMUM
0 NS MINIMUM
ADDR

j4-100 NS MAXIMUM

I
)(~--------D-A-T-A------~~

NOTES:
1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER INPUTS
AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT
3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL NAMES
INCLUDE A "B" PREFIX.
MR-3690

Figure 5-10 DMA Request/Grant Bus Cycle Timing

BDMGO L/BDMGI L is one of two signals that are daisy-chained through each module in the backplane.
The signal is driven out of the processor on the BDMGO L pin, enters each module on the BDMGI L pin
and exits on the BDMGO L pin. This signal passes through the modules in descending order of priority
until it is stopped by the requesting device. The requesting device blocks the output of BDMGO Land
asserts TSACK. If no device responds to the DMA grant, the processor will clear the grant and rearbitrate
the bus.
NOTE
The KDJll-A uses a "NO-SACK" timer, which
clears BDMGO L if BSACK L is not received from
the DMA device within 10 J.Ls.
During the data transfer phase, the DMA device continues asserting BSACK L. If multiple-data transfers
are performed during this phase, consideration must be given to the use of the bus for other system
functions, such as memory refresh (if required). The actual data transfer is performed in the same manner
as the data transfer portion of the DATI, DATO(B), DATIO(B), DATBI and DATBO bus cycles
described in Paragraphs 5.3.1.2 through 5.3.1.6.

5-16

The DMA device can assert TSYNC L for a data transfer 0 ns (minimum) after it receives RDMGI L,
250 ns (minimum) after RSYNC is negated, and 300 ns (minimum) after RRPL Y is negated.
During the bus mastership relinquish phase, the DMA device relinquishes the bus by negating TSACK.
This occurs after the last data transfer cycle (RRPLY negated) is completed (or aborted). TSACK may be
negated up to 300 ns (maximum) before negating TSYNC.
5.5 INTERRUPTS
The interrupt capability of the LSI-II bus allows any I/O device to temporarily suspend (interrupt)
current program execution and divert processor operation for service of the requesting device. The
processor inputs a vector from the device to start the service routine. As with a device register address, the
hardware fixes the device vector at locations within a designated range of addresses between 000 and 7768.
The vector indicates the first of a pair of addresses. The content of the first address is read by the
processor; it is the starting address of the interrupt handler. The content of the second address is a new
processor status word (PS). The PS bits <07:05> can be programmed to a priority level from 0 to 7. Only
interrupts on a level higher than the number in the priority level field of the PS are serviced by the
processor. If the interrupt priority level of the new PS is higher than that of the original PS, the new PS
raises the interrupt priority level and thus prevents lower-level interrupts from breaking into the current
interrupt service routine. Control is returned to the interrupted program when the interrupt service routine
is completed. The original program address (PC) and its associated PS are stored on a "stack." The
original PC and PS are restored by a return from interrupt instruction (RTI or R TT) at the end of the
service routine. The use of the stack and the LSI-II bus interrupt scheme can allow interrupts to occur
within interrupts (nested interrupts) if the requesting interrupt has a higher priority level than the interrupt
currently being serviced.
Interrupts can be caused by LSI-II bus options and can also originate in the processor. Interrupts
originating in the processor are called traps and are caused by programming errors, hardware errors,
special instructions, and maintenance features. The following are the LSI-II bus signals used in interrupt
transactions.
Signal

Name

BIRQ4 L
BIRQ5 L
BIRQ6 L
BIRQ7L

Interrupt request priority level 4
Interrupt request priority level 5
Interrupt request priority level 6
Interrupt request priority level 7

BIAKI L
BIAKO L

Interrupt acknowledge input
Interrupt acknowledge output

BDAL<15:00> L

Data/address lines

BDINL
BRPLY L

Data input strobe
Reply

5.5.1 Device Priority
The LSI-II bus supports the following two methods of determining device priority.
1.

Distributed arbitration - Priority levels are implemented on the hardware. When devices of
equal priority level request an interrupt, priority is given to the device electrically closest to the
processor.

Position-defined arbitration - Priority is determined solely by electrical position on the bus. The
device closest to the processor has the highest priority, while the device at the far end of the bus
has the lowest priority.
5-17

The KDJ1l-A uses both methods - distributed arbitration, with four levels of priority, and positiondefined arbitration within each level. Interrupts on these priority levels are enabled/disabled by bits in the
processor status word (PS<07:05». Single-level interrupt (position-defined) devices that interrupt on
BIRQ4 can also be used in KDJ11-A systems but must be placed in a bus slot following the last bus slot in
which a position-independent device is installed.
5.5.2 Interrupt Protocol
Interrupt protocol has three phases: the interrupt request phase, the interrupt acknowledge and priority
arbitration phase, and the interrupt vector transfer phase. The operations performed by the processor and
interrupting device are shown in Figure 5-11. Interrupt protocol timing is shown in Figure 5-12.

DEVICE

PROCESSOR

---- -------

INITIATE REOUEST
_ . ASSERT BIRO l

...-

STROBE INTERRUPTS
• ASSERT BDIN l

I
I

RECEIVE BDIN L
• STORE "INTERRUPT SENDING q
IN DEVICE

•

GRANT REOUEST
• PAUSE AND ASSERT BIAKO l

-- --- ----

RECEIVE BIAKI L
• RECEIVE BIAKI L AND INHIBIT
BIAKO L
• PLACE VECTOR ON BDAL < 15:00 > L
• ASSERT BRPlY l
_ . NEGATE BIRO L

RECEIVE VECTOR & TERMINATE
REOUEST
• INPUT VECTOR ADDRESS
• NEGATE BDIN LAND BIAKO l

-------- ---- ------ ---

COMPLETE VECTOR TRANSFER
• REMOVE VECTOR FROM BDAl BUS
_ _ • NEGATE BRPlY l

PROCESS THE INTERRUPT
• SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK
• LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION
• EXECUTE INTER'1UPT StRVICE
ROUTINE FOR THE DEVICE

MR-1182

Figure 5-11

Interrupt Request! Acknowledge Sequence

5-18

INTERRUPT LATENCY
MINUS SERVICE TIME

r - - I_ _ _

--+_~

TIRQ
150 NS MINIMUMi
r---------r--+----------~

R DIN

R IAKI

T RPLY
125 NS MAXIMUM---.I

r-'OONSMA'''MUM

______________________(_4)__________________--J)(r----~V-E-C-T-O-R----~)(

TDAL

R SYNC

(UNASSERTED)

R BS7

(UNASSERTED)

(4)

Figure 5-12 Interrupt Protocol Timing

The interrupt request phase begins when a device meets its specific conditions for interrupt requests (for
example, when the device is "ready," "done," or when an error has occurred). The interrupt enable bit in a
device status register must be set. The device then initiates the interrupt by asserting the interrupt request
line(s). BIRQ4 L is the lowest hardware priority level and is asserted for all interrupt requests for
compatibility with previous LSI-II processors. The level at which a device is configured must also be
. asserted. (A special case exists for level 7 devices that must also assert level 6.) The interrupt request line
remains asserted until the request is acknowledged.
Interrupt Level

Lines Asserted by Device

BIRQ4 L
BIRQ4 L, BIRQ5 L
BIRQ4 L, BIRQ6 L
BIRQ4 L, BIRQ6 L, BIRQ7 L

5
6

5-19

During the interrupt acknowledge and priority arbitration phase, the KDJ11-A will acknowledge interrupts under th~ following conditions.
1.

The device interrupt priority is higher than the current priority level stored in PS<07:05>.

The processor has completed instruction execution and no additional bus cycles are pending.

The processor acknowledges the interrupt request by asserting TDIN and 150 ns (minimum) later, by
asserting TIAKO. The device electrically closest to the processor receives the acknowledge on its RIAKI
bus receiver.
On the leading edge of RDIN, each bus option capable of requesting interrupts decides whether to accept
or to pass on the RIAKI signal. A device that does not support position-independent, multilevel interrupts
accepts RIAKI if it is requesting an interrupt when RDIN asserts. A device that does support positionindependent, multilevel interrupts accepts RIAKI if it is requesting an interrupt and if there is no higherpriority request pending when RDIN asserts. This decision must be clocked into a flip-flop, which settles
within 150 ns of TDIN.
Devices that support position-independent, multilevel interrupts assert from one to three IRQ lines when
requesting an interrupt. Table 5-4 presents the IRQ lines a device at each level must assert in order to
request an interrupt and lists the lines it must monitor to determine whether a higher-priority device is
requesting an interrupt.
During the interrupt vector transfer phase, the responding interrupt device receives RIAKI and then
asserts TRPLY. The vector address must be stable at TDAL<08:02> 125 ns (maximum) after TRPLY is
asserted. The processor receives the assertion of RRPLY, and 200 ns (minimum) later it inputs the vector
address and negates both TDIN and TIAKO. The interrupting device negates TRPLY after the negation
of RIAKI and removes the vector address from TDAL<08:02> 100 ns (maximum) after TRPLY negates.
Since vector addresses are constrained to be between 000 and 7748, none of the remaining TDAL lines are
used.

Table 5-4
Interrupt
Level
4

5
6

Position-Independent, Multilevel Device Requirements

IRQ Lines Asserted

IRQ Lines Monitored

TIRQ4
TIRQ4, TIRQ5
TIRQ4, TIRQ6
TIRQ4, TIRQ6, TIRQ7

RIRQ5, RIRQ6
RIRQ6
RIRQ7

5-20

5.5.3 4-Level Interrupt Configurations
Users having high-speed peripherals and desiring better software performance can use the 4-level interrupt
scheme. Both position-independent and position-dependent configurations can be used with the 4-level
interrupt scheme.
The position-independent configuration is shown in Figure 5-13. This configuration allows peripheral
devices that use the 4-level interrupt scheme to be placed in the backplane in any order. These devices
must send out interrupt requests and monitor higher-level request lines, as described in Paragraph 5.5.2.
The level-4 request is always asserted by a requesting device, regardless of priority, to allow compatibility
if an LSI-II or LSI-I 1/2 processor is in the same system. If two or more device~ of equally high priority
request an interrupt, the device physically closest to the processor will win arbitration. Devices that use the
single-level interrupt scheme must be modified or placed at the end of the bus for arbitration to function
properly.
The position-dependent configuration is shown in Figure 5-14. This configuration is simpler to implement,
with the following constraint, however. Peripheral devices must be ordered so that the highest-priority
device is located closest to the processor with the remaining devices placed in the backplane in decreasing
order of priority. With this configuration each device must only assert its own level and level 4 (for
compatibility with an LSI-II or LSI-I 1/2). Monitoring higher-level request lines is unnecessary. Arbitration is achieved through the physical positioning of each device on the bus. Single-level interrupt devices on
level 4 should be positioned last on the bus.

KDJ11

BIAK (INTERRUPT ACKNOWLEDGE)

LEVEL 4
DEVICE

BIRQ 4 (LEVEL 4 INTERRUPT REQUEST)

BIAK

LEVEL 6
DEVICE

BIAK

LEVEL5
DEVICE

BIAK

LEVEL 7
DEVICE

BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)
BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)
BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)
MR-2888

Figure 5-13

KDJ11

Position-Independent Configuration

LEVEL 7
DEVICE

BIAK (INTERRUPT ACKNOWLEDGE)

BIRQ4 (LEVEL4INTERRUPT REQUEST)

BIAK

LEVEL 6
DEVICE

BIAK

LEVEL 5
DEVICE

BIAK

LEVEL4
DEVICE

BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)
BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)
BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)
MR-2889

Figure 5-14

Position-Dependent Configuration

5-21

5.6 CONTROL FUNCTIONS
The following LSI-II bus signals provide system control functions.
Signal

Name

BREFL

~emory refresh

BHALT L
BINIT L
BPOKH
BDCOK H
BEVNT L

(in Q22-Bus systems, used for block mode D~A)
Processor halt
Initialize
Power OK
DC power OK
External event interrupt request

5.6.1 Memory Refresh
If BREF is asserted during the address portion of a bus data transfer cycle, it causes all dynamic ~OS
memories to be addressed simultaneously. The sequence of addresses required for refreshing the memories
is determined by the specific requirements of each memory. The complete memory refresh cycle consists
of a series of refresh bus transactions. (A new address is used for each transaction.) The entire cycle must
be completed within 2 ms. ~ultip1e-data transfers by D~A devices must be avoided since they could
delay memory refresh cycles. The KDJ1I-A does not perform memory refresh.
5.6.2 Halt
Assertion of BHALT L stops program execution and forces the processor unconditionally into console
ODT mode. The processor does not assert the BHALT L bus line when it comes to a programmed HALT.
5.6.3 Initialization
Devices along the bus are initialized when BINIT L is asserted. The processor asserts the BINIT L signal
under the following conditions.
1.
2.
3.
4.

During a power-down sequence
During a power-up sequence
During the execution of a RESET instruction
After a console start

5.6.4 Power Status
Power status protocol is controlled by two signals, BDCOK Hand BPOK H. These signals are driven by an
external device (usually the power supply) and are defined as follows.
5.6.4.1 BnCOK H - The assertion of this line indicates that dc power has been stable for at least 3 ms.
Once asserted this line remains asserted until the power fails.
5.6.4.2 BPOK H - The assertion of this line indicates that there is at least an 8 ms reserve of dc power
and that BDCOK H has been asserted for at least 70 ms. Once BPOK H has been asserted, it must remain
asserted for at least 3 ms. BPOK H normally remains asserted (high).
The negation of this line indicates that power is failing and that only 4 ms of dc power reserve remains.
The negation of this line during processor operation initiates a power-fail trap sequence.

5-22

5.6.4.3

Power-Up - The following events occur during a power-up sequence.

Logic associated with the power supply negates BDCOK H during power-up and asserts
BDCOK H 3 ms (minimum) after dc power is restored to voltages within specification.

The processor asserts BINIT L after receiving nominal power and negates BIN IT L 0 ns
(minimum) after the assertion of BDCOK H.

Logic associated with the power supply negates BPOK H during power-up and asserts BPOK H
70 ms (minimum) after the assertion of BDCOK H. If power does not remain stable for 70 rns,
BDCOK H will be negated; therefore, devices should suspend critical actions until BPOK H is
asserted.

BPOK H must remain asserted for a minumum of 3 ms. BDCOK H must remain asserted 4 111:;
(minimum) after the negation of BPOK H.

The timing diagram for the power-up/power-down sequence is shown in Figure 5-15.

---,
BINIT L

- I,

I-- 0 NS MI NIMUM

3MS

~MINIMUM-

3MS ~
MAXIMUM

8-20J,LS

1J,LS
MAXIMUM

B POK H

....

70 MS
MINIMUM

4MS

MINIMUM

BDCOK H

- 3 MS MINIMUM
DC POWER

5 J,LS
MINIMUM

POWER-UP
NORMAL-+_ _ _ 'OW".OOWN
SEQUENCE---ilot+-pOWER
SEQUENCE

70 MS
MINIMUM

NORMAeJ

Ii r-"-------+-. . ~."~.-.J

--~~- 'OW".U'

SEQUENCE --+-POWER

NOTE:
ONCE A POWER-DOWN SEQUENCE IS STARTED,
IT MUST BE COMPLETED BEFORE A POWER-UP
SEQUENCE IS STARTED.
MR 6032

Figure 5-15

Power-Up/Power-Down Timing

5-23

5.6.4.4

Power-Down - The following events occur during a power-down sequence.

If the ac voltage to a power supply drops below 75% of the nominal voltage for one full line
cycle (15-24 ms), BPOK H is negated by the power supply. Once BPOK H is negated, the
entire power-down sequence must be completed.
A device that requested bus mastership before the power failure that has not become bus master
should maintain the request until BINIT L is asserted or the request is acknowledged (in which
case regular bus protocol is followed).

Processor software should execute a RESET instruction 3 ms (minimum) after the negation of
BPOK H. This asserts BINIT L for from 8 to 20 J,LS. Processor software executes a HALT
instruction immediately following the RESET instruction.

BDCOK H must remain asserted a minimum of 4 ms after the negation of BPOK H. This 4 ms
allows mass storage and similar devices to protect themselves against erasures and erroneous
writes during a power failure.

The processor asserts BINIT L I J,LS (minimum) after the negation of BDCOK H.

DC power must remain stable for a minimum of 5 J,LS after the negation of BDCOK H.

BDCOK H must remain negated for a minimum of 3 ms.

5.6.5 BEVNT L
The BEVNT L signal is an external line clock interrupt request to the processor. When BEVNT L is
asserted, the processor internally assigns location 1008 as the vector address for the BEVNT service
routine. Because the vector is internally assigned, the processor does not execute the protocol for reading-in
the interrupt vector address as is the case for other external interrupt requests.

5.7 BUS ELECTRICAL CHARACTERISTICS
This paragraph contains information about the electrical characteristics of the LSI-II bus.
5.7.1

Signal-Level Specification

Input Logic Levels
TTL logical low:
TTL logical high:

0.8 Vdc (maximum)
2.0 Vdc (minimum)

Output Logic Levels
TTL logical low:
TTL logical high:

0.4 Vdc (maximum)
2.4 Vdc (minimum)

5.7.2 AC Bus Load Definition
ACbus loading is the amount of capacitance a module presents to a bus signal line. This capacitance is
measured between each module signal line and ground. AC bus loading is expressed in ac unit loads where
each unit load is defined as 9.35 pF. AC bus loading for the KDllI-A is 3.4 ac unit loads.

5-24

5.7.3 DC Bus Load Definition
DC bus loading is the amount of leakage current a module presents to a bus signal line. A dc unit load is
defined as 105 /-LA flowing into a module device when the signal line is in the unasserted (high) state. DC
bus loading for the KDJlI-A is 1.0 dc unit loads.
5.7.4 120 Q LSI-ll Bus
The electrical conductors interconnecting the bus device slots are treated as transmission lines. A uniform
transmission line, terminated in its characteristic impedance, will propagate an electrical signal without
reflections. Insofar as bus drivers, receivers, and wiring connected to the bus have finite resistance and
nonzero reactance, the transmission line impedance becomes nonuniform, and thus introduces distortions
into pulses propagated along it. Passive components of the LSI-II bus (such as wiring, cabling, and etched
signal conductors) are designed to have a nominal characteristic impedance of 120 Q.
The maximum length of the interconnecting cable in multiple-backplane systems (excluding wiring within
the backplane) is limited to 4.88 m (16 ft).

NOTES
The KDJll-A processor (as well as all standard DIGITAL-supplied LSI-ll interfaces)
connects to the bus via special drivers and
receivers, described in Paragraphs 5.7.5 and
5.7.6.
The KDJ11-A processor provides resistive (330
Q) pull-up (on all bused lines) to 3.4 Vdc for
thi~ wired-OR interconnecting scheme.

5.7.5 Bus Drivers
Devices driving the 120 Q LSI-II bus must have open collector outputs and meet the specifications that
follow.
DC Specifications (These conditions must be met at worst-case supply voltage, temperature, and input
signal levels.)
Vee can vary from 4.75 V to 5.25 V.
Output low voltage when sinking 70 rnA of current: 0.7 V (maximum).
Output high leakage current when connected to 3.8 Vdc: 25 /-LA (even if no power is applied to them,
except for BDCOK Hand BPOK H).
AC Specifications
Bus driver output pin capacitance load: Not to exceed 10 pF.
Propagation delay: Not to exceed 35 ns.
Driver skew (difference in propagation time between slowest and fastest bus driver): Not to exceed
25 ns.
Rise/fall times: Transition time from 10% to 90% for positive transition, and from 90% to 10% for
negative transition, must be no faster then 5 ns.

5-25

5.7.6 Bus Receivers
Devices that receive signals from the 120 n LSI-II bus must meet the following requirements.
DC Specifications (These conditions must be met at worst-case supply voltage, temperature, and output
signal conditions.)

Vee can vary from 4.75 V to 5.25 V.
Input low voltage: 1.3 V (maximum).
Input high voltage: 1.7 V (minimum).
Maximum input leakage current when connected to 3.8 Vdc: 80 JLA with Vee between 0.0 V and
5.25 V.
AC Specifications

Bus receiver input pin capacitance load: Not to exceed 10 pF.
Propagation delay: Not to exceed 35 ns.
Receiver skew (difference in propagation time between slowest and fastest receiver): Not to exceed
25 ns.
5.7.7 KDJ11-A Bus Termination
The 120 Q LSI-II bus must be terminated at each end by an appropriate resistive termination. A pair of
resistors in series from +5.0 V to ground is used to establish a voltage for each bidirectional line when that
line is not being driven (negated). The parallel impedance of this pair of resistors is 250 Q. The terminating
resistors are shown in Figure 5-16. The KDJ11-A contains terminating resistor networks in 18-pin singlein-line packages to provide the 250 Q terminations for the data/address, synchronization, and control lines
at the processor end of the bus.

+5 V

330n
250n
BUS LINE
TERMINATION

680n

MR-6033

Figure 5-16 Bus Line Termination

Some system configurations do not require terminating resistors at the far end of the bus. If the system
configuration does require such termination, it is typically provided by a M9404-YA cable connector
module. Rules for configuring single- and multiple-backplane systems are described in Paragraphs 5.8.1
and 5.8.2.

5-26

5.7.8 Bus Interconnection Wiring
This paragraph contains the electrical characteristics of the bus interface. The bus interface for the module
connectors is provided by one, two, or three backplanes, depending on the system configuration. Since
each backplane contains 9 slots, a system may have a maximum of 27 module interfaces to the bus.
5.7.8.1 Backplane Wiring - The wiring that interconnects all device interface slots on the LSI-II bus
must meet the following specifications.
1.

The conductors must be arranged so that each line exhibits a characteristic impedance of 120 n
(measured with respect to the bus common return).

Crosstalk from a pulse-driven line to an undriven line to which a constant 5 V is applied must be
less than 5% of the 5 V. Note that worst-case crosstalk is manifested by simultaneously driving
all but one signal line and measuring the effect on the undriven line.

. DC resistance of a bus segment signal path, as measured between the near-end terminator and
far-end terminator modules (including all intervening connectors, cables, backplane wiring,
connector-module etch, etc.) must not exceed 2 n.

DC resistance of a bus segment common return path, as measured between the near-end
terminator and far-end terminator modules (including all intervening connectors, cables, backplane wiring, connector-module etch, etc.) must not exceed an equivalent of 2 n per signal path.
Thus, the composite signal return path dc resistance must not exceed 2 n divided by 40 bus
lines, or 50 mn. Note that although this common return path is nominally at ground potential,
the conductance must be part of the bus wiring; the specified low-impedance return path must
be provided by the bus wiring as distinguished from common system or power ground path.

5.7.8.2 Intrabackplane Bus Wiring - The wiring that interconnects the bus connector slots within one
contiguous backplane is part of the overall bus transmission line. Due to implementation constraints, the
nominal characteristic impedance of 120 n may not be achievable. Distributed wiring capacitance in
excess of the amount required to achieve the nominal 120 n impedance may not exceed 60 pF per signal
line per backplane.
5.7.8.3 Power and Ground - Each bus interface slot has connector pins assigned for the following dc
voltages.
Voltage

Number of Pins

+5 Vdc

Three pins, 4.5 A (maximum) per bus device slot

+12 Vdc

Two pins, 3.0 A (maximum) per bus device slot)

Ground

Eight pins, shared by power return and signal return

The maximum allowable current per pin is 1.5 A. The +5 Vdc must be regulated to ±5% and the
maximum ripple should not exceed 100 mV peak-to-peak. The + 12 Vdc must be regulated to ±3% and the
maximum ripple should not exceed 200 mV peak-to-peak.
NOTE
Power is not bused between backplanes on any interconnecting LSI-U bus cables.

5-27

5.7.8.4

Maintenance and Spare Pins

Maintenance Pins - There are four M SPARE pins per bus device slot assigned to maintenance (AKI,
ALl, BK 1, BLl). The maintenance pins on the basic LSI-II system are not bused from module to module.
Instead, at each bus device slot, the maintenance pins are shorted together as pairs. These pins must be
shorted together for some modules to operate. This allows a module to use these pins during initial testing
as two separate points. This feature is used by DIGITAL for manufacturing tests only.
Spare Pins - Spare pins are allocated on the backplane as follows.
S SPARES - These four pins, AEI, AHI, BHI, AFI (with the exception of AFI in slot 1), are
reserved for the particular use of a module or set of modules. They may be used as test points or for
intermodule connection. Appropriate wires must be added for intermodule communication since
these pins are not connected in any way. The processor uses AFI in slot 1 as an output pin for the
SR UN signal. S SPARE lines cannot be used as bus connections.
P SPARES - These two pins, AUI and BUI are similar to the S SPARE pins except that they are
located in a manner that causes dc voltages to appear on them if a module is inserted backwards. Use
of these pins is not recommended.
5.8 SYSTEM CONFIGURATIONS
LSI-II bus systems can be divided into two types. The first type comprises those systems that use only one
backplane, the second type comprising those systems that use multiple backplanes. Two sets of rules must
be followed when configuring a system to accommodate the different electrical characteristics of the two
types of systems. These rules are listed in Paragraphs 5.8.1 and 5.8.2.
Three characteristics of each component in an LSI-II bus system must be known before configuring any
system:
1.

Power consumption - The total amount of current drawn from the +5 Vdc and + 12 Vdc power
supplies by all modules in the system.

AC bus loading - The amount of capacitance a module presents to a bus signal line. AC loading
is expressed in ac unit loads, where one ac unit load equals 9.35 pF of capacitance.

DC bus loading - The amount of dc leakage current a module presents to a bus signal when the
line is high (undriven). DC loading is expressed in terms of dc unit loads, where one dc unit load
equals 105 }.LA (nominal).

Power consumption, ac loading, and dc loading specifications for each module are included m the

Microcomputer Interfaces Handbook.
NOTE
The ac and dc loads and the power consumption of
the processor module, terminator module, and backplane must be included in determining the total bus
loading of a backplane.

5-28

5.8.1 Rules for Configuring Single-Backplane Systems
The following rules apply only to single-backplane systems. Any extension of the bus off the backplane is
considered a multiple-backplane system and must be configured accordingly. A single-backplane configuration diagram is shown in Figure 5-17.
l.

The bus can accommodate modules that have up to 20 ac loads (total) before an additional
termination is required. The processor has on-board termination for one end of the bus. If more
than 20 ac loads are included, the other end of the bus must be terminated with 120 Q.

A terminated bus can accommodate modules comprising up to 35 ac loads (total).

The bus can accommodate modules up to 20 dc loads (total).

The bus signal lines on the backplane can be up to 35.6 cm (14 in) long.

BACKPLANE WIRE
14
..- - - - 35.6 CM (14 IN) MAXIM7:""U'"'"'M:-----.lf

ONE
UNIT
LOAD

220n

ONE
UNIT
LOAD

OPTIONAL
120 n

+
3.4 V

35 AC LO A DS
20 DC LO A DS

PROCESSOR

20 AC LO DS
20 DC

} WITH TERM

LO~DS JWITHOUT TERM

Figure 5-17

3.4 V

TERM

Single-Backplane Configuration

5.8.2 Rules for Configuring Multiple-Backplane Systems
Multiple-backplane systems can contain a maximum of three backplanes. A configuration diagram for a
multiple-backplane system is shown in Figure 5-18.
1.

The signal lines on each backplane can be up to 25.4 cm (10 in) long.

Each backplane can accommodate modules that have up to 20 ac loads (total). Unused ac loads
from one backplane may not be added to another backplane if the second backplane loading
will exceed 20 ac loads. It is desirable to load backplanes equally or with the highest ac loads in
the first and second backplanes.

DC loading of all modules in all backplanes cannot exceed 20 loads (total).

The first backplane must have an impedance of 120 Q (obtained via the processor module). The
second backplane is terminated by 120 Q resistor networks contained on the cable connector
inserted in the third backplane.

5-29

BACKPLANE WIRE
25.4 em (10 in) MAX

I
ONE
UNIT
LOAD

ONE
UNIT
LOAD

.>
•

2500

3.4V

y
22AC LOADS MAX

3.4V

CABLE/TERM

PROCESSOR
BACKPLANEWIRE
25.4CM ( 10 in) MAX

I I

rI
CABLE

))

ONE
UNIT
LOAD

ADDITIONAL
CABLES

I
ONE
UNIT
LOAD

I
y
22 AC LOADS MAX

I
I

CABLE

BACKPLANE WIRE
25.4CM (10 in) MAX

~}r---~----~

.---+-----,
ONE
UNIT
LOAD

ONE
UNIT
LOAD

1200

+
CABLE

~~------~yr-------JI

3.4 V

22 AC LOADS MAX

TERM
NOTES:
1. TWO CABLES (MAX) 4.88 m (16 tt) (MAX)
TOTAL LENGTH.
2. 20 DC LOADS TOTAL (MAX)
MR·0586·0787

Figure 5-18

Multiple-Backplane Configuration

5-30

The cables connecting the backplanes must observe the following rules.
a.

The cable(s) connecting the first two backplanes must be 61 cm (2 ft) or greater in length.

The cable(s) connecting the second backplane to the third backplane must be 22 cm (4 ft)
longer or shorter than the cable(s) connecting the first and second backplanes.

The combined length of both cables must not exceed 4.88 m (16 ft).

The cables used must have a characteristic impedance of 120 Q.

5.8.3 Power Supply Loading
Total power requirements for each backplane can be determined by obtaining the total power requirements for each"module in the backplane. Obtain separate totals for +5 V and +12 V power. Power
requirements for each module are specified in the Microcomputer Interfaces Handbook.
Do not attempt to distribute power via the LSI-II bus cables in multiple-backplane systems. Provide
separate, appropriate power wiring from each power supply to each backplane. Each power supply should
be capable of asserting BPOK Hand BDCOK H signals according to bus protocol. This is required if
automatic power-fail/restart programs are implemented or if specific peripherals require an orderly powerdown sequence. The proper use of the BPOK Hand BDCOK H signals is strongly recommended.

5-31

CHAPTER 6
ADDRESSING MODES AND BASE INSTRUCTION SET

6.1 INTRODUCTION
The first part of this chapter is divided into six major sections as follows.
•

Single-Operand Addressing - One part of the instruction word specifies the operation code; the
other part provides information for locating the operand.

•

Double-Operand Addressing - One part of the instruction word specifies the operation code; the
remaining parts provide information for locating two operands.

•

Direct Addressing - The operand is the content of the selected register.

•

Deferred (Indirect) Addressing - The contents of the selected register is the address of the
operand.

•

Use of the PC as a General-Purpose Register - The PC is different from other general-purpose
registers in one important respect. Whenever the processor retrieves an instruction, it automatically advances the PC by 2. By combining this automatic advancement of the PC with four of
the basic addressing modes, we produce the four special PC modes - immediate, absolute,
relative, and relative-deferred.

•

Use of the General-Purpose Registers as a Stack Pointer - General-purpose registers can be
used for stack operations.

The second part of this chapter describes each of the instructions in the KDJ11-A instr-ction set.

6.2 ADDRESSING MODES
Data stored in memory must be accessed and manipulated. Data handling is specified by a KDJ11-A
instruction (MOV, ADD, etc.), which usually specifies the following.
•

The function to be performed (operation code)

•

The general-purpose register to be used when locating the source operand, and/or destination
operand (where required)

•

The addressing mode, which specifies how the selected registers are to be used

A large portion of the data handled by a computer is structured (in character strings, arrays, lists, etc.).
The KDJ 11-A addressing modes provide for efficient and flexible handling of structured data.

6-1

A general-purpose register may be used with an instruction in any of the following ways.
1.

As an accumulator - The data to be manipulated resides in the register.

As a pointer - The content& of the register is the address of an operand, rather than the operand
itself.

As a pointer that automatically steps through memory locations - Automatically stepping
forward through consecutive locations is known as autoincrement addressing; automatically
stepping backwards is known as autodecrement addressing. These modes are particularly useful
for processing tabular or array data.

As an index register - In this instance, the contents of the register and the word following the
instruction are summed to produce the address of the operand. This allows easy access to
variable entries in a list.

An important KDJ11-A feature, which should be considered with the addressing modes, is the register
arrangement.
•

Two sets of six general-purpose registers (RO-R5 and RO' -RS')

•

A hardware stack pointer (SP) register (R6) for each processor mode (kernel, supervisor, user)

•

A program counter (PC) register (R7)

Registers RO-RS and RO' -RS' are not dedicated to any specific function; their use is determined by the
instruction that is decoded.
•

They can be used for operand storage. For example, the contents of two registers can be added
and stored in one of the registers.

•

They can contain the address of an operand or serve as pointers to the address of an operand.

•

They can be used for the autoincrement or autodecrement features.

•

They can be used as index registers for convenient data and program access.

The KDJ ll-A also has instruction addressing mode combinations that facilitate temporary data storage
structures. These can be used for convenient handling of data that must be accessed frequently. This is
known as stack manipulation. The register that keeps track of stack manipulation is known as the stack
pointer (SP). Any register can be used as a stack pointer under program control; however, certain
instructions associated with subroutine linkage and interrupt service automatically use register R6 as a
"hardware stack pointer." For this reason, R6 is frequently referred to as the SP.
•

The stack pointer (SP) keeps track of the latest entry on the stack.

•

The stack pointer moves down as items are added to the stack and moves up as items are
removed. Therefore, the stack pointer always points to the top of the stack.

•

The hardware stack iSA\lsed during trap or interrupt handling to store information, allowing an
orderly return to the interrupted program.

Register R 7 is used by the processor as its program counter (PC). It is recommended that R 7 not be used
as a stack pointer or accumulator. Whenever an instruction is fetched from memory, the program counter
is automatically incremented by two to point to the next instruction word.

6-2

6.2.1 Single-Operand Addressing
The instruction format for all single-operand instructions (such as CLR, INC, TST) is shown in Figure 6-1.
Bits < 15:06> specify the operation code that defines the type of instruction to be executed.
Bits <05:00> form a 6-bit field called the destination address field. The destination address field consists
of two subfields:
•

Bits <05:03> specify the destination mode. Bit 03 IS set to indicate deferred (indirect)
addressing.

•

Bits <02:00> specify which of the 8 general-purpose registers IS to be referenced by this
instruction word.

~-----------------y----------------~A~---------V----

OP CODE

______

DESTINATION ADDRESS
MR-5458

Figure 6-1

Single-Operand Addressing

6.2.2 Double-Operand Addressing
Operations that imply two operands (such as ADD, SUB, MOV, and CMP) are handled by instructions
that specify two addresses. The first operand is called the source operand; the second is called the
destination operand. Bit assignments in the source and destination address fields may specify different
modes and different registers. The instruction format for the double operand instruction is shown in Figure
6-2.
The source address field is used to select the source operand (the first operand). The destination is used
similarly, and locates the second operand and the result. For example, the instruction ADD A, B adds the
contents (source operand) of location A to the contents (destination operand) of location B. After
execution, B will contain the result of the addition and the contents of A will be unchanged.

15
OP

~ODE

06
Rn

:MODE:

SOURCE ADDRESS

02
Rn

:MODE:
J.

DESTINATION ADDRESS
MA-5459

Figure 6-2

Double-Operand Addressing

6-3

Examples in this paragraph and the rest of the chapter use the following sample KOJI1-A instructions. (A
complete listing of the K0J11-A instructions appears in Paragraph 6.3.)
Mnemonic

Description

Octal Code*

CLR

Clear. (Zero the specified destination.)

005000

CLRB

Clear byte. (Zero the byte in the specified
destination.)

105000

INC

Increment. (Add one to contents of the
destination.)

005200

INCB

Increment byte. (Add one to the contents of
the destination byte.)

105200

COM

Complement. (Replace the contents of the
destination by its logical complement;
each 0 bit is set and each 1 bit is
cleared.)

005100

COMB

Complement byte. (Replace the contents of
the destination byte by its logical
complement; each 0 bit is set and each
1 bit is cleared.)

105100

ADD

Add. (Add the source operand to the
destination operand and store the result
at the destination address.)

06SS00

*DD = destination field (six bits)
SS = source field (six bits)
= contents of

6.2.3 Direct Addressing
The following summarizes the four basic modes used with direct addressing.
Direct Modes (Figures 6-3 to 6-6)
Mode

Name

Assembler
Syntax

Function

I·INSTRUCTION

OPERAND
MR-S460

Figure 6-3

Mode 0 Register

6-4

Mode

Name

Assembler
Syntax

Autoincrement

(Rn)+

INSTRUCTION

Function

OPERAND

ADDRESS

+2 FOR WORD,
+1 FOR BYTE

MR-5461

Figure 6-4

Mode 2 Autoincrement

Mode

Name

Assembler
Syntax

Autodecrement

-(Rn)

Function

-2 FOR WORD,
-1 FOR BYTE

INSTRUCTION

OPERAND

MR-5462

Figure' 6-5

Mode

Name

Assembler
Syntax

Index

X(Rn)

INSTRUCTION

Mode 4 Autodecrement

Function

Value X is added to (Rn) to produce address
of operand. Neither X nor (Rn) is modified.

ADDRESS
OPERAND

x
MR-5463

Figure 6-6

Mode 6 Index

6-5

6.2.3.1 Register Mode - With register mode any of the general registers may be used as simple
accumulators, with the operand contained in the selected register. Since they are hardware registers
(within the processor), the general registers operate at high speeds and provide speed advantages when
used for operating on frequently accessed variables. The assembler interprets and assembles instructions of
the form OPR Rn as register mode operations. Rn represents a general register name or number and OPR
is used to represent a general instruction mnemonic. Assembler syntax requires that a general register be
defined as follows.

RO = %0 (% sign indicates register definition)
Rl = %1
R2 = %2, etc.
Registers are typically referred to by name as RO, Rl, R2, R3, R4, R5, R6, and R7. However, R6 and R7
are also referred to as SP and PC, respectively.
.
Register Mode Examples (Figures 6-7 to 6-9)
l.

Symbolic

Octal Code

Instruction Name

INC R3

005203

Increment

Operation: Add one to the contents of general-purpose register R3.

15
0

'I
I

SELECT

I REGISTER

I
I

DESTINATION FIELD

OP CODE (INC(0052))

RO
R1
R2
R3

I
+- J

R4
R5
R6 (SP)
R7 (PC)
MA·5467

Figure 6-7

INC R3 Increment

6-6

Symbolic

Octal Code

Instruction Name

ADD R2, R4

060204

Add

Operation: Add the contents of R2 to the contents. of R4.

BEFORE

AFTER

R21

000002

R21

000002

R41

000004

R41

000006
MR-6468

Figure 6-8

ADD R2,R4 Add

Symbolic

Octal Code

Instruction Name

COMB R4

105104

Complement byte

Operation: 1's complement bits <07:00> (byte) in R4. (When general registers are used, byte instructions
operate only on bits <07:00>; i.e., byte 0 of the register.)

BEFORE

AFTER

022222

R41

022155
MR-5469

Figure 6-9

COMB R4 Complement Byte

6.2.3.2 Autoincrement Mode [OPR (Rn)+J - This mode (mode 2) provides for automatic stepping of a
pointer through sequential elements of a table of operands. It assumes the contents of the selected generalpurpose register to be the address of the operand. Contents of registers are stepped (by one for byte
instructions, by two for word instructions, always by two for R6 and R 7) to address the next sequential
location. The autoincrement mode is especially useful for array processing and stack processing. It will
access an element of a table and then step the pointer to address the next operand in the table. Although
most useful for table handling, this mode is completely general and may be used for a variety of purposes.

6-7

Autoincrement Mode Examples (Figures 6-10 to 6-12)
1.

Symbolic

Octal Code

Instruction Name

CLR (R5)+

005025

Clear

Operation: Use contents of R5 as the address of the operand. Clear selected operand and then increment
the contents of R5 by two.

AFTER

BEFORE

ADDRESS SPACE

20000

005025

30000

111)116

20000

30000

R51

005025

030002

000000
MR-5464

Figure 6-10 CLR (R5)+ Clear

Symbolic

Octal Code

Instruction Name

CLRB(R5)+

105025

Clear byte

Operation: Use contents of R5 as the address of the operand. Clear selected byte operand and then
increment the contents of R5 by one.

BEFORE

20000

AFTER
ADDRESS SPACE

ADDRESS SPACE

105025

R5 L.---,r----'

30000

20000

105025

30000 1111 : 000

030001

I
MR-5465

Figure 6-11

CLRB (R5)+ Clear Byte

6-8

Symbolic

Octal Code

Instruction Name

ADD (R2)+,R4

062204

Add

Operation: The contents of R2 are used as the address of the operand, which is added to the contents of
R4. R2 is then incremented by two.

AFTER

BEFORE

ADDRESS SPACES

ADDRESS SPACE

10000

062204

10000

R41

1000021

062204

010000

100002 1

REGISTERS

100004

020000

010000
MR·5470

Figure 6-12

ADD (R2)+,R4 Add

6.2.3.3 Autodecrement Mode [OPR-(Rn)] - This mode (mode 4) is useful for processing data in a list in
reverse direction. The contents of the selected general-purpose register are decremented (by one for byte
instructions, by two for word instructions) and then used as the address of the operand.
Autodecrement Mode Examples (Figures 6-13 to 6-15)
1.

Symbolic

Octal Code

Instruction Name

INC -(RO)

005240

Increment

Operation: The contents of RO are decremented by two and used as the address of the operand. The
operand is incremented by one.

BEFORE

AFTER

ADDRESS SPACE

1000 1

005240

000000

1777 4

REGISTERS

ADDRESS SPACE

017776

1000 1

005240

177741

000001

'----,r--~

MR-5466

Figure 6-13

INC -(RO) Increment

6-9

Symbolic

Octal Code

Instruction Name

INCB -(RO)

105240

Increment byte

Operation: The contents of RO are decremented by one and then used as the address of the operand. The
operand byte is increased by one.

BEFORE

AFTER
REGISTER

ADDRESS SPACE

1000

105240

ADDRESS SPACE

017776

1000

105240

017775

t
17774EE

17774

17776

001 I 000

MR-5471

Figure 6-14 INCB -(RO) Increment Byte

Symbolic

Octal Code

Instruction Name

ADD -(R3),RO

064300

Add

Operation: The contents of R3 are decremented by two and then used as a pointer to an operand (source),
which is added to the contents of RO (destination operand).

BEFORE

AFTER
REGISTER

ADDRESS SPACE

10020

064300

000020

R31

077776

ADDRESS SPACE

10020

064300

0000070

R31

077774

~t=9

77774~

77774

77776

c=J

000050

MR-6472

Figure 6-15

ADD -(R3),RO Add

6-10

6.2.3.4 Index Mode [OPR X(Rn)] - In this mode (mode 6) the contents of the selected general-purpose
register, and an index word following the instruction word, are summed to form the address of the
operand. The contents of the selected register may be used as a base for calculating a series of addresses,
thus allowing random access to elements of data structures. The selected register can then be modified by
program to access data in the table. Index addressing instructions are of the form OPR X(Rn), where X is
the indexed word located in the memory location following the instruction word and Rn is the selected
general-purpose register.
Index Mode Examples (Figures 6-16 to 6-18)
1.

Symbolic

Octal Code

Instruction Name

CLR 200(R4)

005064
000200

Clear

Operation: The address of the operand is determined by adding 200 to the contents of R4. The operand
location is then cleared.

BEFORE
ADDRESS SPACE
1020

005064

1022

000200

1024

1200
1202

001000

1000
+200
1200

AFTER
ADDRESS SPACE

005064

1022

000200

001000

1024

1200

Figure 6-16 CLR 200(R4) Clear

6-11

MR-5413

Symbolic

Octal Code

Instruction Name

COMB 200(R 1)

105161
000200

Complement byte

Operation: The contents of a location, which are determined by adding 200 to the contents of Rl, are l's
complemented (i.e., logically complemented).

BEFORE
ADDRESS SPACE
1020

105161

1022

000200

20176

AFTER
ADDRESS SPACE

017777

1020

105161

1022

000200

017777

017777
+200
020177

Io~, ! I

20176

000

20200

Figure 6-17

ffi

MR-5474

COMB 200(RI) Complement Byte

Symbolic

Octal Code

Instruction Name

ADD 30(R2),20(R5)

066265
000030
000020

Add

Operation: The contents of a location, which are determined by adding 30 to the contents of R2, are added
to the contents of a location that is determined by adding 20 to the contents of R5. The result is stored at
the destination address, that is, 20(R5).

BEFORE
ADDRESS SPACE
1020

066265

1022

000030

1024

000020

1130

2020

AFTER
ADDRESS SPACE

1020

066265

1022

000030

1024

000020

000001

1130

000001

2020

000002

001100

002000

001100

002000

1100 2000
+30 +20
1130 2020
MR-5475

Figure 6-18

ADD 30(R2),20(R5) Add

6-12

6.2.4 Deferred (Indirect) Addressing
The four basic modes may also be used with deferred addressing. Whereas in register mode the operand is
the contents of the selected register, in register-deferred mode the contents of the selected register is the
address of the operand.
In the three other deferred modes, the contents of the register select the address of the operand rather than
the operand itself. These modes are therefore used when a table consists of addresses rather than operands.
The assembler syntax for indicating deferred addressing is @ [or 0 when this is not ambiguous]. The
following summarizes the deferred versions of the basic modes.
Deferred Modes (Figures 6-19 to 6-22)
Mode

Name

Assembler
Syntax

Function

Registerdeferred

@Rn or (Rn)

INSTRUCTION

OPERAND
MR·o476

Figure 6-19

Mode

Name

Assembler
Syntax

Autoincrementdeferred

@(Rn)+

INSTRUCTION

Mode 1 Register-Deferred

Function
Register is first used as a pointer to a word
containing the address of the operand and then
incremented (always by two, even for byte
instructions).

ADDRESS

OPERAND

MR·5477

Figure 6-20

Mode 3 Autoincrement-Deferred

6-13

Assembler
Mode

Name

Syntax

Function

Autodecrementdeferred

@-(Rn)

Register is decremented (always by two, even
for byte instructions) and then used as a pointer to a word containing the address of the
operand.

-2

INSTRUCTION

ADDRESS

OPERAND

MA-5478

Figure 6-21

Mode 5 Autodecrement-Deferred

Assembler
Mode

Name

Syntax

Function

Index-deferred

@X(Rn)

Value X (stored in a word following the
instruction) and (Rn) are added; the sum is
used as a pointer to a word containing the
address of the operand. Neither X nor (Rn) is
modified.

INSTRUCTION

Figure 6-22

Mode 7 Index-Deferred

6-14

OPERAND

The following examples illustrate the deferred modes.
Register-Deferred Mode Example (Figure 6-23)
Symbolic

Octal Code

Instruction Name

CLR @R5

005015

Clear

Operation: The contents of location specified in R5 are cleared.

BEFORE

AFTER

ADDRESS SPACE

1676
1700

c=J

ADDRESS SPACE
1676

001700

1700

Figure 6-23

MR-5480

CLR @R5 Clear

Autoincrement-Deferred Mode Example (Mode 3) (Figure 6-24)
Symbolic

Octal Code

Instruction Name

INC @(R2)+

005232

Increment

Operation: The contents of R2 are used as the address of the address of the operand. The operand is
increased by one; the contents of R2 are incremented by two.

BEFORE

AFTER

ADDRESS SPACE

1010
1012

ADDRESS SPACE
R2
1010
1012

010302

MR-5481

Figure 6-24

INC @(R2)+ Increment

6-15

Autodecrement-Deferred Mode Example (Mode 5) (Figure 6-25)
Symbolic

Octal Code

COM @--(RO)

005150

Operation: The contents of RO are decremented by two and then used as the address of the address of the
operand. The operand is 1's complemented (i.e., logically complemented).
AFTER

BEFORE
ADDRESS SPACE
10100
10102

10774
10776

ADDRESS SPACE

10100

010776

10102

t=j

10774
10776

t=j
t=j

MR-5482

Figure 6-25

COM @-(RO) Complement

Index-Deferred Mode Example (Mode 7) (Figure 6-26)
Symbolic

Octal Code

Instruction Name

ADD @1000(R2),Rl

067201
001000

Add

Operation: 1000 and the contents of R2 are summed to produce the address of the address of the source
operand, the contents of which are added to the contents of R 1; the result is stored in R 1.
AFTER

BEFORE
REGISTER

ADDRESS SPACE
1020

067201

1022

001000

001234

000100

ADDRESS SPACE
067201

1022

001000

t=9

1050

1100

1100
1000
+100
1100

R2
1024

1024

1050

1020

I
I

001236

000100

t=9
t=9
MR·5483

Figure 6-26

ADD @IOOO(R2),Rl Add

6-16

6.2.S Use of the PC as a General-Purpose Register
Although register 7 is a general-purpose register, it doubles in function as the program counter for the
KDJII-A. Whenever the processor uses the program counter to acquire a word from memory, the
program counter is automatically incremented by two to contain the address of the next word of the
instruction being executed or the address of the next instruction to be executed. (When the program uses
the PC to locate byte data, the PC is still incremented by two.)

The PC responds to all the standard KDJII-A addressing modes. However, with four of these modes the
PC can provide advantages for handling position-independent code and unstructured data. When utilizing
the PC, these modes are termed immediate, absolute (or immediate-deferred), relative, and relativedeferred. The modes are summarized below.
Mode

Name

Assembler
Syntax

Function

Immediate

Operand follows instruction.

Absolute

@#A

Absolute address of operand follows
instruction.

Relative

Relative address (index value) follows the
instruction.

Relativedeferred

Index value (stored in the word after the
instruction) is the relative address for the
address of the operand.

When a standard program is available for different users, it is often helpful to be able to load it into
different areas of memory and run it in those areas. The KDJII-A can accomplish the relocation of a
program very efficiently through the use of position-independent code (PIC), which is written by using the
PC addressing modes. If an instruction and its operands are moved in such a way that the relative distance
between them is not altered, the same offset relative to the PC can be used in all positions in memory.
Thus, PIC usually references locations relative to the current location.
The PC also greatly facilitates the handling of unstructured data. This is particularly true of the immediate
and relative modes.

6-17

6.2.5.1 Immediate Mode [OPR #n,DD) - Immediate mode (mode 2) is equivalent in use to the autoincrement mode with the PC. It provides time improvements for accessing constant operands by including the
constant in the memory location immediately following the instruction word.
Immediate Mode Example (Figure 6-27)
Symbolic

Octal Code

Instruction Name

ADD #10,RO

062700
000010

Add

Operation: The value lOis located in the second word of the instruction and is added to the contents of RO.
Just before this instruction is fetched and executed, the PC points to the first word of the instruction. The
processor fetches the first word and increments the PC by two. The source operand mode is 27 (autoincrement the PC). Thus, the PC is used as a pointer to fetch the operand (the second word of the instruction)
before it is incremented by two to point to the next instruction.

AFTER

BEFORE
ADDRESS SPACE
1020
1022

1--0_62_70_0--1' RO
000010

000020

"-PC

1024

ADDRESS SPACE
1020

062700

1022

000010

1024

000030

MA·5484

Figure 6-27

ADD #lO,RO Add

6.2.5.2 Absolute Addressing Mode [OPR @#A)- This mode (mode 3) is the equivalent of immediatedeferred or autoincrement-deferred using the PC. The contents of the location following the instruction are
taken as the address of the operand. Immediate data is interpreted as an absolute address (i.e., an address
that remains constant no matter where in memory the assembled instruction is executed).

6-18

Absolute Mode Examples (Figures 6-28 and 6-29)
1.

Symbolic

Octal Code

Instruction Name

CLR @#IIOO

005037
001100

Clear

Operation: Clear the contents of location 1100.

AFTER

BEFORE
ADDRESS SPACE
20

005037

001100

ADDRESS SPACE

005037

001100

1100

1102

Figure 6-28

t=9

MR-5485

CLR @ #1l00 Clear

Symbolic

Octal Code

Instruction Name

ADD @#2000,R3

063703
002000

Add

Operation: Add contents of location 2000 to R3.
AFTER

BEFORE
REG ISTER

ADDRESS SPACE
20

063703

002000

ADDRESS SPACE

000500

063703

002000

001000

•
MR-5486

Figure 6-29

ADD @ #2000 Add

6-19

6.2.5.3 Relative Addressing Mode [OPR A or OPR X(PC)] - This mode (mode 6) is assembled as index
mode using R 7. The base of the address calculation, which is stored in the second or third word of the
instruction, is not the address of the operand, but the number which, when added to the (PC), becomes the
address of the operand. This mode is useful for writing position-independent code since the location
referenced is always fixed relative to the PC. When instructions are to be relocated, the operand is moved
by the same amount. The instruction OPR X(PC) is interpreted as "X is the location of A relative to the
PC."
Relative Addressing Mode Example (Figure 6-30)
Symbolic

Octal Code

Instruction Name

INCA

005267
000054

Increment

Operation: To increment location A, contents of memory location immediately following instruction word
are added to (PC) to produce address A. Contents of A are increased by one.

BEFORE
ADDRESS SPACE

1020

005267

1022

000054

AFTER
ADDRESS SPACE

1020

0005267

1022

000054

1024

1026

;026

1100

000000

1024
+54
'----------1100

I--PC

1100

000001

MR-5487

Figure 6-30 INC A Increment

6.2.5.4 Relative-Deferred Addressing Mode [OPR @A or OPR @X(PC)] - This mode (mode 7) is
similar to relative mode, except that the second word of the instruction, when added to the PC, contains
the address of the address of the operand, rather than the address of the operand. The instruction OPR
@X(PC) is interpreted as "X is the location containing the address of A, relative to the PC."
Relative-Deferred Mode Example (Figure 6-31)
Symbolic

Octal Code

Instruction Name

CLR@A

005077
000020

Clear

Operation: Add second word of instruction to updated PC to produce address of address of operand. Clear
operand.

6-20

BEFORE
ADDRESS SPACE
(PC = , 020) 1020

005077

1022

000020

AFTER
ADDRESS SPACE

'~
10100

100001

005077

1022

000020

1024

1024
+20
1044

1024

1020

1044

010100

10100

000000

MR-5488

Figure 6-31

CLR @A Clear

6.2.6 Use of the General-Purpose Register as a Stack Pointer
The processor stack pointer (SP, register 6) is, in most cases, the general register used for the stack
operations related to program nesting. Autodecrement with register 6 "pushes" data onto the stack, and
autoincrement with register 6 "pops" data off the stack. Since the SP is used by the processor for interrupt
handling, it has a special attribute: autoincrements and autodecrements are always done in steps of two.
Byte operations using the SP in this way leave odd addresses (upper bytes) unmodified.
6.3 INSTRUCTION SET
The rest of this chapter describes the KDJ11-A instruction set. The explanation of each instruction
includes the instruction's mnemonic, octal code, binary code, a diagram showing the format of the
instruction, a symbolic notation describing its execution and effect on the condition codes, a description,
special comments, and examples. Each explanation is headed by its mnemonic. When the word instruction
has a byte equivalent, the byte mnemonic also appears.
The diagram that accompanies each instruction shows the octal op code, binary op code, and bit assignments. [Note that in byte instructions, the most significant bit (bit 15) is always a one.]
Symbols:
( ) =

contents of

v = Boolean OR

SS or src = source address

Y = exclusive OR

DO or dst = destination address

,.., = Boolean not

loc = location

REG or R = register

+- =

becomes

B = byte

T= "is popped from stack"

• = 0 for word, 1 for byte

1 = "is pushed onto stack"

, =

1\ = Boolean AND

6-21

concatenated

6.3.1 Instruction Formats
The following formats include all instructions used in the KDll1-A. Refer to individual instructions for
more detailed information.
1.

CLR, CLRB, COM, COMB, INC, INCB,
DEC, DECB, NEG, NEGB, ADC, ADCB,
SBC, SBCB, TST, TSTB, ROR, RORB,
ROL, ROLB, ASR, ASRB, ASL, ASLB,
JMP , SWAB, MFPS, MTPS, SXT,
TSTSET, WRTLCK

Single-Operand Group:
(Figure 6-32)

MA-S191

Figure 6-32

Single-Operand Group

Double-Operand Group:
a. Group 1:
(Figure 6-33)

BIT, BITB, BIC, BlCB, BIS, BlSB,
ADD, SUB, MOV, MOVB, CMP, CMPB

:
MR-5192

Figure 6-33

b. Group 2:
(Figure 6-34)

Double-Operand Group 1

ASH, ASHC, DIV, MUL, XOR

MR-11554

Figure 6-34

Double-Operand Group 2

6-22

Program Control Group:
a.

Branch (all branch instructions) (Figure 6-35)
08

MA-5193

Figure 6-35

Program Control Group Branch

Jump (JMP) (Figure 6-36)
15

:
MR~0586-0788

Figure 6-36

Program Control Group JMP

Jump to Subroutine (JSR) (Figure 6-37)
09

:
MR·5194

Figure 6-37

Program Control Group JSR

Subroutine Return (RTS) (Figure 6-38)
03

MA-5190

Figure 6-38

Program Control Group RTS

Traps (breakpoint, lOT, EMT, TRAP, BPT) (Figure 6-39)
00

MA-5196

Figure 6-39

Program Control Group Traps

6-23

Subtract 1 and Branch (if = 0) (SOB) (Figure 6-40)
09

MR-5197

Figure 6-40

Program Control Group Subtract

Mark (Figure 6-41)
15

MA·11548

Figure 6-41

Mark

Call to Supervisor Mode (CSM) (Figure 6-42)
15

05
j

DD
MR-11549

Figure 6-42 Call to Supervisor Mode

Set Priority Level (SPL) (Figure 6-43)
15

02
N

MR-11550

Figure 6-43

Set Priority Level

6-24

HALT, WAIT, RTI, RESET, RTT, NOP, MFPT

Operate Group:
(Figure 6-44)

15
0

OP CODE

MA-5198

Figure 6-44 Operate Group

Condition Code Operators (all condition code instructions)
(Figure 6-45)
06

I I Iz I I
0/1

MR-5199

Figure 6-45

Move To/From
Previous
Instruction/Data
Space Group:
(Figure 6-46)

Condition Group

MTPD, MTPI, MFPD, MFPI

~P COD~
MR-11551

Figure 6-46

Move To and From Previous Instruction/Data Space Group

6-25

6.3.2 Byte Instructions
The KDJlI-A includes a full complement of instructions that manipulate byte operands. Since all KDJllA addressing is byte-oriented, byte manipulation addressing is straightforward. Byte instructions with
autoincrement or autodecrement direct addressing cause the specified register to be modified by one to
point to the next byte of data. Byte operations in register mode access the low-order byte of the specified
register. These provisions enable the KDJIl-A to perform as either a word or byte processor. The
numbering scheme for word and byte addresses in memory is shown in Figure 6-47.
WORD OR BYTE
ADDRESS

HIGH BYTE
ADDRESS

002001

BYTE 1

BYTE 0

002000

002003

BYTE 3

BYTE 2

002002

MR-5201

Figure 6-47

Byte Instructions

The most significant bit (bit 15) of the instruction word is set to indicate a byte instruction.
Example:
Symbolic

Octal Code

Instruction Name

CLR
CLRB

0050DD
l050DD

Clear word
Clear byte

6-26

6.3.3 List of Instructions
The following is a list of the K0J11-A instruction set.
SINGLE-OPERAND
General
Mnemonic

Instruction

Op Code

CLR(B)
COM(B)
INC(B)
OEC(B)
NEG(B)
TST(B)
WRTLCK

Clear destination
Complement destination
Increment destination
Oecrement destination
Negate destination
Test destination
Read/lock destination,
write/unlock RO into
destination
Test destination, set low bit

.05000
.05100
.05200
.05300
.05400
.05700

Mnemonic

Instruction

Op Code

ASR(B)
ASL(B)
ROR(B)
ROL(B)
SWAB

Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Swap bytes

.06200
.06300
.06000
.06100
000300

Mnemonic

Instruction

Op Code

ADC(B)
SBC(B)
SXT

Add carry
Subtract carry
Sign extend

.05500
.05600
006700

TSTSET

007300
007200

Shift and Rotate

Multiple-Precision

PS Word Operators
Mnemonic

Instruction

Op Code

MFPS
MTPS

Move byte from PS
Move byte to PS

106700
1064SS

6-27

DOUBLE-OPERAND
General
Mnemonic

Instruction

Op Code

MOV(B)
CMP(B)
ADD
SUB
ASH
ASHC
MUL
DIV

Move source to destination
Compare source to destination
Add source to destination
Subtract source from destination
Arithmetic shift
Arithmetic shift combined
Multiply
Divide

.1SSDD
.2SSDD
06SSDD
16SSDD
072RSS
073RSS
070RSS
071RSS

Mnemonic

Instruction

Op Code

BIT(B)
mqB)
BIS(B)
XOR

Bit test
Bit clear
Bit set
Exclusive OR

.3SSDD
.4SSDD
.5SSDD
074RDD

Logical

PROGRAM CONTROL

Mnemonic

Instruction

Op Code
or
Base Code

Branch (unconditional)
Branch if not equal (to zero)
Branch if equal (to zero)
Branch if plus
Branch if minus
Branch if overflow is clear
Branch if overflow is set
Branch if carry is clear
Branch if carry is set

000400
001000
001400
100000
100400
102000
102400
103000
103400

Branch
BR
BNE
BEQ
BPL
BMI
BVC
BVS
BCC
BCS

Signed Conditional Branch
Op Code
or
Base Code

Mnemonic

Instruction

BGE

Branch if greater than or equal
(to zero)
Branch if less than (zero)
Branch if greater than (zero)
Branch if less than or equal
(to zero)

BLT
BGT
BLE

6-28

002000
002400
003000
003400

Unsigned Conditional Branch

Mnemonic

Instruction

Op Code
or
Base Code

BHI
BLOS
BHIS
BLO

Branch if higher
Branch if lower or same
Branch if higher or same
Branch if lower

101000
101400
103000
103400

Jump and Subroutine

Mnemonic

Instruction

Op Code
or
Base Code

JMP
JSR
RTS
SOB

Jump
Jump to subroutine
Return from subroutine
Subtract one and branch (if =1= 0)

OOOlDD
004RDD
00020R
077RDD

Trap and Interrupt

Mnemonic

Instruction

Op Code
or
Base Code

EMT
TRAP
BPT
lOT
RTI

Emulator trap
Trap
Breakpoint trap
Input!output trap
Return from interrupt
Return from interrupt

104000-104377
104400-104777
000003
000004
000002
000006

RTT

Miscellaneous Program Control

Mnemonic

Instruction

Op Code
or
Base Code

CSM
MARK
SPL

Call to supervisor mode
Mark
Set Priority Level

0070DD
0064NN
00023N

6-29

MISCELLANEOUS

Mnemonic

Instruction

Op Code
or
Base Code

HALT
WAIT
RESET
MFPT
MTPO
MTPI
MFPO
MFPI

Halt
Wait for interrupt
Reset external bus
Move processor type
Move to previous data space
Move to previous instruction space
Move from previous data space
Move from previous instruction space

000000
000001
000005
000007
106600
006600
1065SS
0065SS

CONDITION CODE OPERATORS

Mnemonic

Instruction

Op Code
or
Base Code

CLC
CLV
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN

Clear C
Clear V
Clear Z
Clear N
Clear all CC bits
Set C
Set V
Set Z
SetN
Set all CC bits
No operation

000241
000242
000244
000250
000257
000261
000262
000264
000270
000277
000240

sec

NOP

6.3.4 Single-Operand Instructions
The KOJll-A instructions that involve only one operand are described in the paragraphs that follow.

6-30

6.3.4.1 General-

CLR
CLRB
CLEAR DESTINATION

-05000

0/1

:a : a :

a :

:a:a

Operation:

(dst) .- 0

Condition Codes:

N:
Z:
V:
C:

Description:

Word: The contents of the specified destination are replaced with Os.
Byte: Same.

Example:

CLR Rl

cleared
set
cleared
cleared

Before-

After

(Rl) = 177777

(R 1) = 000000

NZVC
1 1 1 1

NZVC

o10 0

6-31

COM
COMB
COMPLEMENT OST

0/< 0 : 0 : 0 : 1 : 0 : 1 : 0 : 0 : 1 I

:
MR-115Q5

Operation:

(dst) - ,.., (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Word: Replaces the contents of the destination address by their logical
complement. (Each bit equal to 0 is set and each bit equal to 1 is cleared.)

set if most significant bit of result is set; cleared otherwise
set if result is 0; cleared otherwise
cleared
set

Byte: Same.
Example:

COMRO
Before

After

(RO) = 013333

(RO) = 164444

NZVC

NZVC
100 1

o1 10
INC
INCB

-05200

INCREMENT OST

15
0<

06
0

: 0
MR-11506

Operation:

(dst) - (dst) + 1

Condition Codes:

N:
Z:
V:
C:

set if result is < 0; cleared otherwise
set if result is 0; cleared otherwise
set if (dst) held 077777; cleared otherwise
not affected

6-32

Description:

Word: Add 1 to the contents of the destination.
Byte: Same.

Example:

INCR2

Before

After

(R2) = 000333

(R2) = 000334

NZVC

o0 0 0

DEC
DECB
-053DD

DECREMENT DST

MR-11507

Operation:

(dst) ~ (dst) - 1

Condition Codes:

N:
Z:
V:
C:

Description:

Word: Subtract 1 from the contents of the destination.
Byte: Same.

Example:

DECR5

set if result is < 0; cleared otherwise
set if result is 0; cleared otherwise
set if (dst) was 100000; cleared otherwise
not affected

Before

After

(R5) = 000001

(R5) = 000000

NZVC

o10 0

1 000

6-33

NEG
NEGB
NEGATE OST

-05400

15
0/1:

06
0

0
MA-11503

Operation:

(dst) +- - (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Word: Replaces the contents of the destination address by its 2's complement. Note that 100000 is replaced by itself. (In 2's complement notation the
most negative number has no positive counterpart.)

set if result is < 0; cleared otherwise
set if result is 0; cleared otherwise
set if result is 100000; cleared otherwise
cleared if result is 0; set otherwise

Byte: Same.
Example:

NEGRO
Before

After

(RO) = 000010

(RO) = 177770

NZVC
0000

NZVC
100 1

6-34

TST
TSTB
-057DD

TEST DST
06

o : o : o :

0/1 :

1 :

o :

1 :

:
MR-11501

Operation:

Cdst) -

Condition Codes:

N:
Z:
V:
C:

Description:

Word: Sets the condition codes Nand Z according to the contents of the
destination address; the contents of dst remain unmodified.

Cdst)

set if result is < 0; cleared otherwise
set if result is 0; cleared otherwise
cleared
cleared

Byte: Same.
Example:

TST

Before

After

CRl) = 012340

NZVC
o0 1 1

NZVC
o0 0 0

WRTLCK
READ/LOCK DESTINATION
WRITE/UNLOCK RO INTO DESTINATION

0073DD

00
I
DD
MR·11498

Operation:

Cdst) -

Condition Codes:

N:
Z:
V:
C:

Description:

Writes contents of RO into destination using bus lock. If mode is 0, traps to

CRO)

set if RO < 0
set if RO = 0
cleared
unchanged

to.

6-35

TSTSET
007200

TEST DESTINATION AND SET LOW BIT

MR-11499

Operation:

(RO) - (dst), (dst) - (dst) V 000001 (octal)

Condition Codes:

N:
Z:
V:
C:

Description:

Reads/locks destination word and stores it in RO. Writes/unlocks (RO) V 1
into destination. If mode is 0, traps to 10.

set if RO < 0
set if RO = 0
cleared
gets contents of old destination bit O.

6.3.4.2 Shifts and Rotates - Scaling data by factors of two is accomplished by the shift instructions:
ASR - Arithmetic shift right
ASL - Arithmetic shift left
The sign bit (bit 15) of the operand is reproduced in shifts to the right. The low-order bit is filled with Os in
shifts to the left. Bits shifted out of the C-bit, as shown in the following instructions, are lost.
The rotate instructions operate on the destination word and the C-bit as though they formed a 17-bit
"circular buffer." These instructions facilitate sequential bit testing and detailed bit manipulation.

6-36

ASR
ASRB
ARITHMETIC SHIFT RIGHT

-06200

15
0/1:

06
0

1 :

0
MR-,1502

Operation:

(dst) +- (dst) shifted one place to the right

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise

Description:

set if result = 0; cleared otherwise

loaded from exclusive OR of N-bit and C-bit (as set by the completion
of the shift operation)

loaded from low-order bit of destination

Word: Shifts all bits of the destination right one place. Bit 15 is reproduced.
The C-bit is loaded from bit 0 of the destination. ASR performs signed
division of the destination by 2.
Byte: Same.

Example:

1--8-

BYTE:

~~15~:__~__~O_00__AO~0_R_E_SSr-~r-~:~0~8~c:r~0~7-r:__~__~E~V~E~N~A~0~0~RE~S~S__~__~0~0~1~
MR-5209

6-37

ASL
ASLB
ARITHMETIC SHIFT LEFT

MR-11510

Operation:

(dst) ~ (dst) shifted one place to the left

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise

Description:

set if result = 0; cleared otherwise

loaded with exclusive OR of N-bit and C-bit (as set by the completion of
the shift operation)

loaded with high-order bit of destination

Word: Shifts all bits of the destination left one place. Bit 0 is loaded with a O.
The C-bit of the status word is loaded from the most significant bit of the
destination. ASL performs a signed multiplication of the destination by 2
with overflow indication.
Byte: Same.

Example:
WORD:

BYTE:

8-1

ODD ADDRESS

ro&1

EVEN ADDRESS

MR·5211

6-38

ROR
RORB

ROTATE RIGHT

06000
00

0/1: 0

MR-11500

Operation:

(dst) +- (dst) rotate right one place

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise
Z:

set if all bits of result = 0; cleared otherwise

loaded with exclusive OR of N-bit and C-bit (as set by the completion of
the rotate operation)

loaded with low-order bit of destination

Word: Rotates all bits of the destination right one place. Bit 0 is loaded into
the C-bit and the previous contents of the C-bit are loaded into bit 15 of the
destination.

Description:

Byte: Same, except the C-bit is loaded into MSB 7 or 15.
Example:
WORD:

BYTE:

+r------t~~-----.
15

I [

~
00

EV:EN

MR-5213

6-39

ROL
ROLB
ROTATE LEFT

-06100

on: 0 : 0 : 0 : 1 : 1 : 0 : 0 : 0 : 1

00
:
MR-11509

Operation:

(dst) ~ (dst) rotate left one place

Condition Codes:

N: set if high-order bit of result word is set (result < 0); cleared otherwise

Description:

set if all bits of result word = 0; cleared otherwise

loaded with exclusive OR of the N-bit and C-bit (as set by the completion of the rotate operation)

loaded with high-order bit of destination

Word: Rotates all bits of the destination left one place. Bit 15 is loaded into
the C-bit of the status word and the previous contents of the C-bit are loaded
into bit 0 of the destination.
Byte: Same, except the C-bit is loaded into LSB 8 or O.

Example:
WORD:

BYTE:

r-------~.~r_--------_.
15

E~EN

MR-5215

6-40

SWAB
SWAP BYTES

000300
06

o : o : o : o : o : o : o : o :

~o :
MA-1150B

Operation:

byte l/byte 0 - byte O/byte 1

Condition Codes:

N: set if high-order bit of low-order byte (bit 7) of result is set; cleared
otherwise
Z:

set if low-order byte of result = 0; cleared otherwise

cleared

Description:

Exchanges high-order byte and low-order byte of the destination word. (The
destination must be a word address.)

Example:

SWAB Rl
Before

After

(RI) = 077777

(RI) = 177577

NZVC
1 1 1 1

o0 0 0

NZVC

6-41

6.3.4.3 Multiple-Precision - It is sometimes necessary to do arithmetic operations on operands considered as multiple words or bytes. The KDJ11-A makes special provision for such operations with the
instructions ADC (add carry) and SBC (subtract carry) and their byte equivalents.
For example, two 16-bit words may be combined into a 32-bit double-precision word and added or
subtracted as shown below.
32-BITWORD

---

(
31
OPERANDI

(~---------------------------~---------------------------~1

,f'. . _____________

16
OPERANDj'
....___________B_1___________---J

B_O_ _ _ _ _ _ _....

r15~

____________________

..J1 1...._____________________--'1

RESULTI......._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

MR-5217

Example:
The addition of -1 and -1 could be performed as follows.
-1 = 37777777777
(Rl) = 177777 (R2) = 177777 (R3) = 177777 (R4) = 177777
ADD Rl,R2
ADCR3
ADDR4,R3
1. After (Rl) and (R2) are added, 1 is loaded into the C-bit.
2. The ADC instruction adds the C-bit to (R3); (R3) = O.
3. The (R3) and (R4) are added.
4. The result is 37777777776, or -2.

6-42

ADC
ADCB
ADD CARRY

-055DD

0/< 0 : 0 : 0 : 1 : 0 : 1 : 1 : 0 : 1

~D
MR-11575

Operation:

(dst) +- (dst) + (C-bit)

Condition Codes:

N:
Z:
V:
C:

Description:

Word: Adds the contents of the C-bit to the destination. This permits the
carry from the addition of the low-order words to be carried to the high-order
result.

set if result < 0; cleared otherwise
set if result = 0; cleared otherwise
set if (dst) was 077777 and (C) was 1; cleared otherwise
set if (dst) was 177777 and (C) was 1; cleared otherwise

Byte: Same.
Example:

Double-precision addition may be done with the following instruction
sequence.
ADD
ADC
ADD

AO,BO
BI
AI,BI

6-43

;add low-order parts
;add carry into high-order
;add high-order parts

SBC

SHeH
SUBTRACT CARRY

-05600

15
0/1 :

06
0:

0 :

1 :

MA-11576

Operation:

(dst) +- (dst) - (C)

Condition Codes:

N:
Z:
V:
C:

Description:

Word: Subtracts the contents of the C-bit from the destination. This permits
the carry from the subtraction of two low-order words to be subtracted from
the high-order part of the result.

set if result < 0; cleared otherwise
set if result = 0; cleared otherwise
set if (dst) was 100000; cleared otherwise
set if (dst) was 0 and C was 1; cleared otherwise

Byte: Same.
Example:

Double-precision subtraction is done by:
SUB
SBC
SUB

AO,BO
BI
AI,Bl

SXT
006700

SIGN EXTENO

MR-11674

Operation:

(dst) +- 0 if N-bit is clear
(dst) +- 1 if N-bit is set

Condition Codes:

N: not affected
Z: set if N-bit is clear
V: cleared
C: not affected

6-44

Description:

If the condition code bit N is set, a -1 is placed in the destination operand; if
the N-bit is clear, a 0 is placed in the destination operand. This instruction is
particularly useful in multiple-precision arithmetic because it permits the sign
to be extended through multiple words.

Example:

SXTA

6.3.4.4

Before

After

(A) = 012345

(A) = 177777

NZVC
1 000

PS Word Operators -

MFPS
MOVE BYTE FROM PROCESSOR STATUS WORD

1067DD

I :
1

: :
1

1
:

:
MR11495

Operation:

(dst) <- PS
dst lower 8 bits

Condition Codes:

N: set if PS <07> = 1; cleared otherwise
Z: set if PS <07 :00> = 0; cleared otherwise
V: cleared
C: not affected

Description:

The 8-bit contents of the PS are moved to the effective destination. If the
destination is mode 0, PS bit 07 is sign-extended through the upper byte of
the register. The destination operand address is treated as a byte address.

Example:

MFPS RO
Before

After

RO [0]
PS [000014]

RO [000014]
PS [000000]

6-45

MTPS
1064SS

MOVE BYTE TO PROCESSOR STATUS WORD

MR-11496

Operation:

PS - (src)

Condition Codes:

Set according to effective SRC operand bits <03:00>

Description:

The eight bits of the effective operand replace the current contents of the
lower byte of the PS. The source operand address is treated as a byte address.
Note: The T-bit (PS bit 04) cannot be set with this instruction. The SRC
operand remains unchanged. This instruction can be used to change the
priority bits (PS bits <07:05» in the PS only in kernel mode. If not in kernel
mode, PS bits <07:05> cannot be changed.

Example:

MTPS Rl
Before

After

(Rl) = 000777
(PS) = XXXOOO

(Rl) = 000777
(PS) = XXX357

NZVC

NZVC
1 1 1 1

o0 0 0

6.3.5 Double-Operand Instructions
Double-operand instructions save instructions (and time) since they eliminate the need for "load" and
"save" sequences such as those used in accumulator-oriented machines.

6-46

6.3.5.1

General-

MOV
MOVB
.1SSDD

MOVE SOURCE TO DESTINATION
15

MR-11497

Operation:

(dst) +- (src)

Condition Codes:

N:
Z:
Y:
C:

Description:

Word: Moves the source operand to the destination location. The previous
contents of the destination are lost. Contents of the source address are not
affected.

set if (src) < 0; cleared otherwise
set if (src) = 0; cleared otherwise
cleared
not affected

Byte: Same as MOY. The MOYB to a register (unique among byte instructions) extends the most significant bit of the low-order byte (sign extension).
Otherwise, MOYB operates on bytes exactly as MOY operates on words.
Example:

MOY XXX,Rl

;loads register 1 with the contents of memory location;
XXX represents a programmer-defined mnemonic used
to represent a memory
location

MOY #20,RO

;loads the number 20 into register 0; # indicates that the
value 20 is the operand

MOY @#20,-(R6)

;pushes the operand contained
in location 20 onto the stack

MOY (R6)+,@#177566

;pops the operand off a stack
and moves it into memory
location 177566 (terminal
print buffer)

MOY Rl,R3

;performs an inter-register
transfer

MOYB @#177562,@#177566

;moves a character from the
terminal keyboard buffer to
the terminal printer buffer

6-47

CMP
CMPB
COMPARE SRC TO DST

·2SSDD

~D
MR-11562

Operation:

(src) - (dst)

Condition Codes:

N: set if result < 0; cleared otherwise

Description:

set if result = 0; cleared otherwise

set if there was arithmetic overflow; that is, operands were of opposite
signs and the sign of the destination was the same as the sign of the
result; cleared otherwise

cleared if there was a carry from the result's most significant bit; set
otherwise

Compares the source and destination operands and sets the condition codes,
which may then be used for arithmetic and logical conditional branches. Both
operands are not affected. The only action is to set the condition codes. The
compare is customarily followed by a conditional branch instruction. Note:
Unlike the subtract instruction, the order of operation is (src) - (dst), not
(dst) - (src).

6-48

ADD
ADD SRC TO DST

06SSDD

11
:

S~
MR-11563

Operation:

(dst) <- (src) + (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z:

set if result = 0; cleared otherwise

set if there was arithmetic overflow as a result of the operation; that is,
both operands were of the same sign and the result was of the opposite
sign; cleared otherwise

set if there was a carry from the result's most significant bit; cleared
otherwise

Description:

Adds the source operand to the destination operand and stores the result at
the destination address. The original contents of the destination are lost. The
contents of the source are not affected. Two's complement addition is performed. Note: There is no equivalent byte mode.

Example:

Add to register:

ADD 20,RO

Add to memory:

ADD Rl,XXX

Add register to register:

ADD Rl,R2

Add memory to memory:

ADD @#17750,XXX

XXX is a programmer-defined mnemonic for a memory location.

6-49

SUB
16SSDD

SUBTRACT SRC FROM DST
12

MR·11564

Operation:

(dst) <- (dst) - (src)

Condition Codes:

N: set if result < 0; cleared otherwise
Z:

set if result = 0; cleared otherwise

set if there was arithmetic overflow as a result of the operation; that is, if
operands were of opposite signs and the sign of the source was the same
as the sign of the result; cleared otherwise

cleared if there was a carry from the result's most significant bit; set
otherwise

Description:

Subtracts the source operand from the destination operand and leaves the
result at the destination address. The original contents of the destination are
lost. The contents of the source are not affected. In double-precision arithmetic the C-bit, when set, indicates a "borrow." Note: There is no equivalent
byte mode.

Example:

SUB Rl,R2
Before

After

(Rl) = 011111
(R2) = 012345

(Rl) = 011111
(R2) = 001234

NZVC
1 1 1 1

NZVC
o0 0 0

ASH
ARITHMETIC SHIFT

072RSS

09
0

00
SS
MR-'1660

Operation:

R <- R shifted arithmetically NN places to the right or left where NN =
(src)

Condition Codes:

N:
Z:
V:
C:

set if result < 0
set if result = 0
set if sign of register changed during shift
loaded from last bit shifted out of register
6-50

Description:

The contents of the register are shifted right or left the number of times
specified by the source operand. The shift count is taken as the low-order six
bits of the source operand. This number ranges from -32 to +31. Negative is
a right shift and positive (less than +31) is a left shift.
NOTE
A shift count of +31 shifts the contents of the register to the right 31 times.

ASHe
ARITHMETIC SHIFT COMBINED

.073RSS

00
SS
MR-11561

Operation:

R, R V 1 ~ R, R V 1
The double word is shifted NN places to the right or left where NN = (src)

Condition Codes:

N:
Z:
V:
C:

Description:

The contents of the register and the register ORed with 1 are treated as one
32-bit word. R V 1 (bits <15:00» and R (bits <31:16» are shifted right or
left the number of times specified by the shift count. The shift count is taken
as the low-order 6 bits of the source operand; the upper 11 bits of the source
operand must be o. This number ranges from -32 to +31. Negative is a right
shift and positive is a left shift.

set if result < 0
set if result = 0
set if sign bit changes during shift
loaded with high-order bit when left shift; loaded with low-order bit
when right shift (loaded with the last bit shifted out of the 32-bit
operand)

When the register chosen is an odd number, the register and the register
ORed with 1 are the same. In this case, the right shift becomes a rotate. The
16-bit word is rotated right the number of times specified by the shift count.
NOTE
Bits <5:0> shift count. Bits <15:6> must be O.

6-51

MUL
MULTIPLY

070RSS
09

MR-11572

Operation:

R, R VI+- R X (src)

Condition Codes:

N: set if product < 0
Z: set if product = 0
V: cleared C: set if the result is less than -2 ** 15 or greater than or equal
to 2 **15 -1.

Description:

The contents of the destination register and source taken as 2's complement
integers are multiplied and stored in the destination register and the succeeding register, if R is even. If R is odd, only the low-order product is stored.
Assembler syntax is: MUL S,R. (Note that the actual destination is R, R V
1, which reduces to just R when R is odd.

DIV
071RSS

DIVIDE

Sf
MA-11573

Operation:

R, R VI+- R, R V 1/(src)

Condition Codes:

N: set if quotient < 0

Description:

set if quotient = 0

set if source = 0 or if the absolute value of the register is larger than the
absolute value of the instruction in the source. (In this case the instruction is aborted because the quotient would exceed 15 bits.)

set if divide by zero is attempted.

The 32-bit 2's complement integer in Rand R V 1 is divided by the source
operand. The quotient is left in R; the remainder is of the same sign as the
dividend. R must be even.

6-52

6.3.5.2 Logical - These instructions have the same format as those in the double-operand arithmetic
group. They permit operations on data at the bit level.

BIT
BITB
BIT TEST
15

:
MR-11566

Operation:

(src) /\ (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Performs logical AND comparison of the source and destination operands
and modifies condition codes accordingly. Neither the source nor the destination is affected. The BIT instruction may be used to test whether any of the
corresponding bits set in the destination are also set in the source, or whether
all corresponding bits set in the destination are clear in the source.

Example:

BIT #30,R3

set if high-order bit of result set; cleared otherwise
set if result = 0; cleared otherwise
cleared
not affected

;test bits three and four of R3 to see if
both are off.

R3 = 0 000 000 000 011 000
Before

After

NZVC
1 1 1 1

NZVC
000 1

6-53

BIC
BICB
BIT CLEAR
15

MA·11657

Operation:

(dst) - -(src) A (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Clears each bit in the destination that corresponds to a set bit in the source.
The original contents of the destination are lost. The contents of the source
are not affected.

Example:

BIC R3,R4

set if high-order bit of result set; cleared otherwise
set if result = 0; cleared otherwise
cleared
not affected

Before

After

(R3) = 001234
(R4) = 001111

(R3) = 001234
(R4) = 000101

NZVC
1 1 1 1

NZVC
000 1

Before:

(R3) = 0 000 001 010 011 100
(R4) = 0 000 001 001 001 001

After:

(R4) = 0 000 000 001 000001

6-54

BIS
BISB
BIT SET
15

:
MR-11558

Operation:

(dst) +- (src) V (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Performs an inclusive OR operation between the source and destination
operands and leaves the result at the destination address; that is, corresponding bits set in the source are set in the destination. The contents of the
destination are lost.

Example:

BIS RO,R1

set if high-order bit of result set; cleared otherwise
set if result = 0; cleared otherwise
cleared
not affected

Before

After

(RO) = 001234
(Rl) = 001111

(RO) = 001234
(Rl) = 001335

NZVC
o0 0 0

Before:

(RO) = 0 000 001 010 011 100
(R1) = 0 000 001 001 001 001

After:

(R1) = 0 000 001 011 011 101

6-55

XOR
074RDD

EXCLUSIVE OR
15

I >>
0

09
:

06
:

D:D

:
MR-11559

Operation:

(dst) <- (reg) ¥ (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

The exclusive OR of the register and destination operand is stored in the
destination address. The contents of the register are not affected. The assembler format is XOR R,D.

Example:

XOR RO,R2

set if result < 0; cleared otherwise
set if result = 0; cleared otherwise
cleared
not affected

Before

After

(RO) = 001234
(R2) = 001111

(RO) = 001234
(R2) = 000325

NZVC
1 1 1 1

NZVC
000 1

Before:

(RO) = 0 000 001 010 011 100
(R2) = 0 000 001 001 001 001

After:

(R2) = 0 000 000 011 010 101

6.3.6 Program Control Instructions
The following paragraphs describe the KDJ11-A instructions that affect program control.
6.3.6.1 Branches - These instructions cause a branch to a location defined by the sum of the offset
(multiplied by 2) and the current contents of the program counter if:
1.

The branch instruction is unconditional.

It is conditional and the conditions are met after testing the condition codes (NZVC).

The offset is the number of words from the current contents of the PC, forward or backward. Note that
the current contents of the PC point to the word following the branch instruction.

6-56

Although the offset expresses a byte address, the PC is expressed in words. The offset is automatically
multiplied by 2 and sign-extended to express words before it is added to the PC. Bit 7 is the sign of the
offset. If it is set, the offset is negative and the branch is done in the backward direction. If it is not set, the
offset is positive and the branch is done in the forward direction.
The 8-bit offset allows branching in the backward direction by 200 (octal) words (400 octal bytes) from
the current PC, and in the forward direction by 177 (octal) words (376 octal bytes) from the current PC.
The KDJ 11-A assembler typically handles address arithmetic for the user and computes and assembles the
proper offset field for branch instructions in the form:
Bxx loc
Bxx is the branch instruction and loc is the address to which the branch is to be made. The assembler gives
an error indication in the instruction if the permissible branch range is exceeded. Branch instructions have
no effect on condition codes. Conditional branch instructions where the branch condition is not met are
treated as NOPs.

DR
000400 PLUS OFFSET

BRANCH (UNCONDITIONAL)

o : 0

Operation:

PC +- PC + (2 X offset)

Condition Codes:

Not affected

Description:

Provides a way of transferring program control within a range of -128 to
+ 127 words with a one word instruction.
New PC address = updated PC + (2 X offset)
Updated PC = address of branch instruction +2

Example:

With the branch instruction at location 500, the following offsets apply.
New PC Address

Offset Code

Offset (decimal)

474
476
500
502
504
506

375
376
377
000
001
002

-3
-2
-1
0
+1
+2

6-57

BNE
001000 PLUS OFFSET

BRANCH IF NOT EQUAL (TO ZERO)

Operation:

PC - PC + (2 X offset) if Z = 0

Condition Codes:

Not affected

Description:

Tests the state of the Z-bit and causes a branch if the Z-bit is clear. BNE is
the complementary operation of BEQ. It is used to test: (1) inequality following a CMP, (2) that some bits set in the destination were also in the source
following a BIT operation, and (3) generally, that the result of the previous
operation was not O.

Example:

Branch to C if A =F B
CMPA,B
BNEC

;compare A and B
;branch if they are not equal

Branch to C if A + B =F 0
ADD A,B
BNEC

;add A to B
;branch if the result is not
equal to 0

BEQ
001400 PLUS OFFSET

BRANCH IF EQUAL (TO ZERO)

o :

1
MR-6233

Operation:

PC - PC + (2 X offset) if Z = 1

Condition Codes:

Not affected

Description:

Tests the state of the Z-bit and causes a branch if Z is set. It is used to test:
(1) equality following a CMP operation, (2) that no bits set in the destination
were also set in the source following a BIT operation, and (3) generally, that
the result of the previous operation was O.

6-58

Example:

Branch to C if A = B
CMPA,B
BEQC

;compare A and B
;branch if they are equal

Branch to C if A + B = 0
ADDA,B
BEQC

;add A to B
;branch if the result = 0

BPL
100000 PLUS OFFSET

BRANCH IF PLUS

MR·5234

Operation:

PC +- PC + (2 X offset) if N = 0

Condition Codes:

Not affected

Description:

Tests the state of the N-bit and causes a branch if N is clear (positive result).
BPL is the complementary operation of BMI.

BMI
BRANCH IF MINUS

100400 PLUS OFFSET
00

MR·5236

Operation:

PC +- PC + (2 X offset) if N = 1

Condition Codes:

Not affected

Description:

Tests the state of the N-bit and causes a branch if N is set. It is used to test
the sign (most significant bit) of the result of the previous operation), branching if negative. BMI is the complementary function of BPL.

6-59

Bve
BRANCH IF OVERFLOW IS CLEAR

102000 PLUS OFFSET
08

a : a : a : a :

a : a
MR·5236

Operation:

PC +-- PC + (2 X offset) if V = 0

Condition Codes:

Not affected

Description:

Tests the state of the V-bit and causes a branch if the V-bit is clear. BVC is
complementary operation to BVS.

BVS
BRANCH IF OVERFLOW IS SET

102400 PLUS OFFSET
08

MR-5237

Operation:

PC <-- PC + (2 X offset) if V = 1

Condition Codes:

Not affected

Description:

Tests the state of the V-bit (overflow) and causes a branch if V is set. BVS is
used to detect arithmetic overflow in the previous operation.

Bee
103000 PLUS OFFSET

BRANCH IF CARRY IS CLEAR
08

MA-5238

Operation:

PC <-- PC + (2 X offset) if C = 0

Condition Codes:

Not affected

Description:

Tests the state of the C-bit and causes a branch if C is clear. BCC is the
complementary operation of BCS.

6-60

BCS
103400 PLUS OFFSET

BRANCH IF CARRY ISSET

MR-5239

Operation:

PC ;- PC + (2 X offset) if C = 1

Condition Codes:

Not affected

Description:

Tests the state of the C-bit and causes a branch if C is set. It is used to test for
a carry in the result of a previous operation.

6.3.6.2 Signed Conditional Branches - Particular combinations of the condition code bits are tested with
the signed conditional branches. These instructions are used to test the results of instructions in which the
operands were considered as signed (2's complement) values.

Note that the sense of signed comparisons differs from that of unsigned comparisons in that in signed, 16bit, 2's complement arithmetic the sequence of values is as follows.
largest
positive

077777
077776

000001
000000
177777
177776

smallest
negative

100001
100000

Whereas, in unsigned, 16-bit arithmetic, the sequence is considered to be:
highest

177777

lowest

000002
000001
000000

6-61

BGE
BRANCH IF GREATER THAN OR EQUAL
(TO ZERO)

002000 PLUS OFFSET
08

MA·5240

Operation:

PC +- PC + (2 X offset) if N ¥ V = 0

Condition Codes:

Not affected

Description:

Causes a branch if N and V are either both clear or both set. BGE is the
complementary operation of BLT. Thus, BGE will always cause a branch
when it follows an operation that caused addition of two positive numbers.
BGE will also cause a branch on a 0 result.

BLT
002400 PLUS OFFSET

BRANCH IF LESS THAN (ZERO)
08

MR-5241

Operation:

PC +- PC + (2 X offset) if N ¥ V = 1

Condition Codes:

Not affected

Description:

Causes a branch if the exclusive OR of the N- and V-bits is one. Thus, BLT
will always branch following an operation that added two negative numbers,
even if overflow occurred. In particular, BLT will always cause a branch if it
follows a CMP instruction operating on a negative source and a positive
destination (even if overflow occurred). Further, BLT will never cause a
branch when it follows a CMP instruction operating on a positive source and
negative destination. BLT will not cause a branch if the result of the previous
operation was 0 (without overflow).

6-62

BGT
BRANCH IF GREATER THAN (ZEROI

003000 PLUS OFFSET

o :

~ I
MR-5242

PC + (2 X offset) if Z V (N Y V) =·0

Operation:

PC -

Condition Codes:

Not affected

Description:

Operation of BGT is similar to BGE, except that BGT will not cause a branch
on a 0 result.

BLE
003400 PLUS OFFSET

BRANCH IF LESS THAN OR EQUAL (TO ZEROI

MA-5243

PC + (2 X offset) if Z V (N Y V) = 1

Operation:

PC -

Condition Codes:

Not affected

Description:

Operation is similar to BLT, but in addition will cause a branch if the result
of the previous operation was O.

6.3.6.3 Unsigned Conditional Branches - The unsigned conditional branches provide a means for testing
the result of comparison operations in which the operands are considered as unsigned values.

BHI
BRANCH IF HIGHER

101000 PLUS OFFSET

MR-S244

PC + (2 X offset) if C = 0 and Z = 0

Operation:

PC -

Condition Codes:

Not affected

Description:

Causes a branch if the previous operation caused neither a carry nor a 0
result. This will happen in comparison (CMP) operations as long as the source
has a higher unsigned value than the destination.

6-63

BLOS
BRANCH IF LOWER OR SAME

101400 PLUS OFFSET
08

MR-5245

Operation:

PC ~ PC + (2 X offset) if C V Z = 1

Condition Codes:

Not affected

Description:

Causes a branch if the previous operation caused either a carry or a 0 result.
BLOS is the complementary operation of BHI. The branch will occur in
comparison operations as long as the source is equal to or has a lower
unsigned value than the destination.

BHIS
103000 PLUS OFFSET

BRANCH IF HIGHER OR SAME
08

MA-5246

Operation:

PC ~ PC + (2 X offset) if C = 0

Condition Codes:

Not affected

Description:

BHIS is the same instruction as BCC. This mnemonic is included for convenience only.

BLO
103400 PLUS OFFSET

BRANCH IF LOWER
08

MA-5247

Operation:

PC ~ PC + (2 X offset) if C = 1

Condition Codes:

Not affected

Description:

BLO is the same instruction as BCS. This mnemonic is included for convenience only.

6-64

6.3.6.4 Jump and Subroutine Instructions - The subroutine call in the KDJ11-A provides for automatic
nesting of subroutines, reentrancy, and multiple entry points. Subroutines may call other subroutines (or
indeed themselves) to any level of nesting without making special provision for storage of return addresses
at each level of subroutine call. The subroutine calling mechanism does not modify any fixed location in
memory, and thus provides for reentrancy. This allows one copy of a subroutine to be shared among
several interrupting processes.
JMP
000100

JUMP

o :

:
MR·11555

Operation:

PC <-- (dst)

Condition Codes:

Not affected

Description:

JMP provides more flexible program branching than the branch instructions
do. Control may be transferred to any location in memory (no range limitation) and can be accomplished with the full flexibility of the addressing
modes, with the exception of register mode o. Execution of a jump with mode
owill cause an "illegal instruction" condition, and will cause the CPU to trap
to vector address ten. (Program control cannot be transferred to a register.)
Register-deferred mode is legal and will cause program control to be transferred to the address held in the specified register. Note that instructions are
word data and must therefore be fetched from an even-numbered address.
Deferred-index mode JMP instructions permit transfer of control to the
address contained in a selectable element of a table of dispatch vectors.

Example:

First:
JMP FIRST

;transfers to FIRST

JMP @LIST

;transfers to location
pointed to at LIST

List:
FIRST

;pointer to FIRST

JMP @(SP)+

;transfer to location
pointed to by the top of
the stack, and remove the
pointer from the stack

6-65

JSR
JUMP TO SUBROUTINE

004RDD

00
:

:
MR-11556

Operation:

(tmp) +- (dst) (tmp is an internal processor register)

1 (SP) +- reg (Push register contents onto processor stack)
reg +- PC (PC holds location following JSR; this address now put in register)
PC +- (dst) (PC now points to subroutine destination)
Description:

In execution of the JSR, the old contents of the specified register (the linkage
pointer) are automatically pushed onto the processor stack and new linkage
information is placed in the register. Thus, subroutines nested within subroutines to any depth may all be called with the same linkage register. There is
no need either to plan the maximum depth at which any particular subroutine
will be called or to include instructions in each routine to save and restore the
linkage pointer. Further, since all linkages are saved in a reentrant manner on
the processor stack, execution of a subroutine may be interrupted. The same
subroutine may be reentered and executed by an interrupt service routine.
Execution of the initial subroutine can then be resumed when other requests
are satisfied. This process (called nesting) can proceed to any level.
A subroutine called with a JSR reg,dst instruction can access the arguments
following the call with either autoincrement addressing, (reg) +, if arguments
are accessed sequentially, or by indexed addressing, X(reg), if accessed in
random order. These addressing modes may also be deferred, @(reg)+ and
@X(reg), if the parameters are operand addresses rather than the operands
themselves.
JSR PC, dst is a special case of the KDJ11-A subroutine call suitable for
subroutine calls that transmit parameters through the general registers. The
SP and the PC are the only registers that may be modified by this call.
Another special case of the JSR instruction is JSR PC,@(SP) +, which
exchanges the top element of the processor stack with the contents of the
program counter. This instruction allows two routines to swap program control and resume operation from where they left off when they are recalled.
Such routines are called coroutines.
Return from a subroutine is done by the R TS instruction. R TS reg loads the
contents of reg into the PC and pops the top element of the processor stack
into the specified register.

NOTE
JSR with register mode destination 0 is illegal and
traps to 10.
6-66

Example:
R5

R7
SBCALL

CONT

MOV (R5)+,dst 1
MOV (R5)+,dst 2

SBCALL+4

n-2

SBR

MOV (R5)+,dst M
Other Instructions
RTS R5

SBCALL+2+2M
CONT
CONT

n-2

EXIT

SBCALL:
SBCALL+4:

JSR R5,SBR
ARG 1
ARG2

SBCALL+2+2M:
CONT:

ARGM
Next Instruction

SBR:

EXIT:

JSR R5, SBR

BEFORE:

(PC)

(SP)

I
I

SBR

AFTER:

STACK

DATA 0

DATA 0
R6

n-2

PC+2

JSR PC, SBR
BEFORE:

AFTER:

(PC)

R71

STACK

(SP)

DATA 0

SBR

-I

n-2

6-67

DATA 0
PC+2
MA·6260

RTS
00020R

RETURN FROM SUBROUTINE

o :

I
MR-l1S53

Operation:

PC (- (reg)
(reg) (- (SP) T

Description:

Loads the contents of the register into PC and pops the top element of the
processor stack into the specified register.
Return from a nonreentrant subroutine is typically made through the same
register that was used in its call. Thus, a subroutine called with a JSR PC, dst
exits with a RTS PC and a subroutine called with a JSR R5, dst, may pick up
parameters with addressing modes (R5) +, X(R5), or @X(R5) and finally
exits, with an RTS R5.

Example:

RTS R5
RTS R5
BEFORE:

(PC)

STACK

SBR

R51

DATA 0
(SP)

AFTER:

n+2

DATA 0

MR-5252

6-68

SOB
SUBTRACT ONE AND BRANCH (IF *01

onRNN

MR-11552

Operation:

(R) - (R) - 1; if this result #- 0, then PC -PC - (2 X offset); if (R) = 0
then PC - PC

Condition Codes:

Not affected

Description:

The register is decremented. If the contents does not equal 0, twice the offset
is subtracted from the PC (now pointing to the following word). The offset is
interpreted as a 6-bit positive number. This instruction provides a fast, efficient method of loop control. The assembler syntax is SOB R,A where A is
the address to which transfer is to be made if the decremented R is not equal
to O. Note: the SOB instruction cannot be used to transfer control in the
forward direction.

6.3.6.5 Traps - Trap instructions provide for calls to emulators, I/O monitors, debugging packages, and
user-defined interpreters. A trap is effectively an interrupt generated by software. When a trap occurs, the
contents of the current program counter (PC) and processor status word (PS) are pushed onto the
processor stack and replaced by the contents of a 2-word trap vector containing a new PC and new PS.
The return sequence from a trap involves executing an RTI or RTT instruction, which restores the old PC
and old PS by popping them from the stack. Trap instruction vectors are located at permanently assigned
fixed addresses.

6-69

EMT
104000-104377

EMULATOR TRAP

MA-5254

Operation:

1 (SP)
1 (SP)

PS
PC
PC <- (30)
PS f-- (32)
f-f--

Condition Codes:

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Description:

All operation codes from 104000 to 104377 are EMT instructions and may
be used to transmit information to the emulating routine (e.g., function to be
performed). The trap vector for EMT is at address 30. The new PC is taken
from the word at address 30; the new processor status (PS) is taken from the
word at address 32.
NOTE
EMT is used frequently by DIGITAL system
software and is therefore not recommended for general use.

PC
BEFORE:
SP

AFTER:

I
I
I

PS 1

PC 1

STACK

1 I
DATA 1

(32)

(30)

n-4

DATA 1
PS 1

I
I

PC 1

MR-5265

6-70

TRAP
TRAP

104400-104777
08

15
1

: :o: : :o:
0

I
MR-5256

1 (SP) ~ PS
1 (SP) ~ PC

Operation:

PC ~ (34)
PS ~ (36)
Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Operation codes from 104400 to 104777 are TRAP instructions. TRAPs and
EMTs are identical in operation, except that the trap vector for TRAP is at
address 34.
NOTE
Since DIGITAL software makes frequent use of
EMT, the TRAP instruction is recommended for
general use.

BPT
000003

BREAKPOINT TRAP

MR-5267

Operation:

1 (SP) -- PS
1 (SP) ~ PC
PC ~ (14)
PS ~ (16)

Condition Codes:

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 14. Used to call
debugging aids. The user is cautioned against employing code 000003 in
programs run under these debugging aids. (No information is transmitted in
the low byte.)

6-71

lOT
000004

INPUT/OUTPUT TRAP

o :

0
MR-5258

1 (SP) <- PS

Operation:

1 (SP) <- PC
PC <- (20)
PS <- (22)

Condition Codes:

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 20. (No information is
transmitted in the low byte.)

RTI
000002

RETURN FROM INTERRUPT

: :
0

MR-5259

Operation:

PC <- (SP) T
PS <- (SP) T

Condition Codes:

N:
Z:
V:
C:

Description:

Used to exit from an interrupt or TRAP service routine. The PC and PS are
restored (popped) from the processor stack. If the R TI sets the T -bit in the
PS, a trace trap will occur prior to executing the next instruction.

loaded from processor stack
loaded from processor stack
loaded from processor stack
loaded from processor stack

When executing in kernel mode, any legal mode can be stored in PS <15:14,
13:12>. When executing in supervisor mode, only supervisor or user mode
can be stored, and in user mode, only the user mode can be stored.
When executing in kernel mode, either a 1 or a 0 can be stored in PS <11>.
When executing in supervisor mode, a stored 0 can be changed to a 1, but a
stored 1 cannot be changed to a O.

6-72

RTT
RETURN FROM TRAP

000006

MR-5260

Operation:

PC - (SP) T
PS - (SP) T

Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Operation is the same as RTI except that it inhibits a trace trap, whereas RTI
permits a trace trap. If the new PS has the T -bit set, a trap will occur after
execution of the first instruction after R TT.
When executing in kernel mode, any legal mode ~an be stored in PS <15:14,
13:12>. When executing in supervisor mode, only supervisor or user mode
can be stored, and in user mode, only the user mode can be stored.
When executing in kernel mode, either a 1 or a 0 can be stored in PS <11>.
When executing in supervisor mode, a stored 0 can be changed to aI, but a
stored 1 cannot be changed to a O.

6.3.6.6 Miscellaneous Program Control -

MARK
MARK

0064NN

05
j

MR-11566

Operation:

SP - PC + 2 X NN
PC-R5
R5 - (SP)+
NN = number of parameters

Condition Codes:

N:
Z:
V:
C:

Description:

Used as part of the standard subroutine return convention. MARK facilitates
the stack clean-up procedures involved in subroutine exit. Assembler format
is: MARK N.

unaffected
unaffected
unaffected
unaffected

6-73

Example:

MOY R5,-(SP)
MOY Pl,-(SP)
MOY P2,-(SP)

;place old R5 on stack
;place N parameters on
;the stack to be used
;there by the subroutine

MOY PN,-(SP)
MOY =MARKN,-(SP)

;place the instruction
;MARK N on the stack
;set up address at MARK N
;instruction
;jump to subroutine

MOY SP,R5
JSR PC,SUB

At this point the stack is as follows

OLD RS
Pl

PN
MARKN

OLD PC
MR-11569

The program is at the address SUB which is the beginning of the subroutine.
SUB:

;execution of the
;subroutine itself

RTSR5

;the return begins:
;this causes the contents
;of R5 to be placed in the
;PC which then results in
;the execution of the
;instruction MARK N. The
;contents of the old PC
;are placed in R5.

MARK N causes: (1) the stack pointer to be adjusted to point to the old R5
value; (2) the value now in R5 (the old PC) to be placed in the PC; and (3)
the contents of the old R5 to be popped into R5, thus completing the return
from the subroutine.

NOTE
If memory management is in use, the stack must be
mapped through both I and D space to execute the
MARK instruction.

6-74

SPL
SET PRIORITY LEVEL

oo023N

N
MR-11667

Operation:

PS bits <07:05> - priority
(priority = N)

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

In kernel mode, the least significant three bits of the instruction are loaded
into the processor status word (PS) bits <07 :05>, thus causing a changed
priority. The old priority is lost. In user or supervisor modes, SPL executes as
a NOP.
Assembler syntax is: SPL N

CSM
007000

CALL TO SUPERVISOR MOOE
06

~o
MR-11668

Operation:

If MMR3 bit 3 = 1 and current
mode = kernel then
supervisor SP - current mode SP
temp<15:04> - PS<15:04>
temp<03:00> - 0
PS<13:12> - PS<15:14>
PS<15:14> - 01
PS4-0
-(SP) - temp
-(SP) - PC
-(SP) - (dst)
PC - (10)
otherwise, traps to lOin kernel mode.

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

6-75

Descri ption:

CSM may be executed in user or supervisor mode, but is an illegal instruction
in kernel mode. CSM copies the current stack pointer (SP) to the supervisor
mode, switches to supervisor mode, stacks three words on the supervisor stack
(the PS with the condition codes cleared, the PC, and the argument word
addressed by the operand), and sets the PC to the contents oflocation 10 (in .
supervisor space). The called program in supervisor space may return to the
calling program by popping the argument word from the stack and executing
R TI. On return, the condition codes are determined by the PS word on the
stack. Hence, the called program in supervisor space may control the condition code values following return.

6.3.6.7 Reserved Instruction Traps - These are caused by attempts to execute instruction codes reserved
for future processor expansion (reserved instructions) or instructions with illegal addressing modes (illegal
instructions). Order codes not corresponding to any of the instructions described are considered to be
reserved instructions. JMP and JSR with register mode destinations are illegal instructions; they trap to
virtual address lOin kernel data space. Reserved instructions trap to vector address lOin kernel data
space.
6.3.6.8 Trace Trap - Trace trap is enabled by bit 4 of the PS and causes processor traps at the end of
instruction execution. The instruction that is executed after the instruction that set the T-bit will proceed
to completion and then trap through the trap vector at address 14. Note that the trace trap is a system
debugging aid and is transparent to the general programmer.

NOTE
Bit 4 of the PS can only be set indirectly by executing a RTI or RTT instruction with the desired PS on
the stack.
The following are special cases of the T-bit.

NOTE
The traced instruction is the instruction after the
one that set the T -bit.
1.

An instruction that cleared the T-bit - Upon fetching the traced instruction, an internal flag,
the trace flag, was set. The trap will still occur at the end of this instruction's execution. The
status word on the stack, however, will have a clear T-bit.

An instruction that set the T-bit - Since the T-bit was already set, setting it again has no effect.
The trap will occur.

An instruction that caused an instruction trap - The instruction trap is performed and the entire
routine for the service trap is executed. If the service routine exits with an R TI, or in any other
way restores the stacked status word, the T-bit is set again, the instruction following the traced
instruction is executed, and, unless it is one of the special cases noted previously, a trace trap
occurs.

An instruction that caused a stack overflow - The instruction completes execution as usual. The
stack overflow does not cause a trap. The trace trap vector is loaded into the PC and PS and the
old PC and PS are pushed onto the stack. Stack overflow occurs again, and this time the trap is
made.

6-76

An interrupt between setting of the T-bit and fetch of the traced instruction - The entire
interrupt service routine is executed and then the T-bit is set again by the exiting RTI. The
traced instruction is executed (if there have been no other interrupts) and, unless it is a special
case noted above, causes a trace trap.

Interrupt trap priorities - See Table 1-8.

6.3.7 Miscellaneous Instructions
HALT
HALT

000000

a : a : a : a : a : a : a : a : a : a : a : a : a : a : a : a

1 (SP) +- PS

Operation:

1 (SP) +- PC
PC +- restart address
PS +- 340

Condition Codes:

Not affected

Description:

The effect of HALT depends upon the CPU operating mode and the halt
option currently selected. See Chapter 8 for more details on halt options. In
kernel mode, a halt option of 1 (external logic driving a 1 on DAL3 in
response to a GP Read with a GP code of 000) causes a trap through location
4 and sets bit 7 of the CPU error register when HALT is executed. If the halt
option is 0 in kernel mode, execution of the HALT instruction causes the
KDJ11-A into console ODT. Execution of the HALT instruction in user or
supervisor mode causes a trap through location 4 and sets bit 7 of the CPU
error register.

WAIT
WAIT FOR INTERRUPT

000001

MR-5262

Condition Codes:

Not affected

Description:

In WAIT, as in all instructions, the PC points to the next instruction following the WAIT instruction. Thus, when an interrupt causes the PC and PS to
be pushed onto the processor stack, the address of the next instruction
following the WAIT is saved. The exit from the interrupt routine (i.e.,
execution of an RTI instruction) will cause resumption of the interrupted
process at the instruction following the WAIT. If not in kernel mode, WAIT
executes as a NOP.
6-77

RESET
RESET EXTERNAL BUS

000005

MR·5263

Condition Codes:

Not affected

Description:

The following sequence of events occurs: (1) a GP Write cycle is performed
and a GP code of 014 is generated; (2) operation is delayed for 69 microcycles; (3) a GP Write is performed and a GP code of 214 is generated; (4)
operation is delayed for 600 microcycles. If not in kernel mode, RESET
operates as a Nap.

MFPT
MOVE FROM PROCESSOR TYPE WORD

000007
00

MA-7198

Operation:

RO- 5

Condition Codes:

Not affected

Description:

The number 5 is placed in RO, indicating to the system software that the
processor type is DClll.

6-78

MTPD/MTPI
MOVE TO PREVIOUS DATA SPACE (BIT 15 = 1)
MOVE TO PREVIOUS INSTRUCTION SPACE (BIT 15 = 0)

_006DD

0/1

06
0

05
DD

MR-11571

Operation:

(temp) - (SP)+
(dst) - (temp)

Condition Codes;

N:
Z:
V:
Z:

Description:

The instruction pops a word off the current stack determined by PS bits
<15:14> and stores that word into an address in the previous space (PS bits
<13:12». The destination address is computed using the current registers
and memory map.

set if the source < 0
set if the source = 0
cleared
unaffected

MFPD/MFPI
MOVE FROM PREVIOUS DATA SPACE (BIT 15 = 1)
MOVE FROM PREVIOUS INSTRUCTION SPACE (BIT 15 = 0)
15

0/1

_005SS

06
0

00
SS
MR-11570

Operation:

(temp) - (src)
-(SP) - (temp)

Condition Codes:

N:
Z:
V:
Z:

Description:

Pushes a word onto the current stack from an address in the previous space
determined by PS<13:12>. The source address is computed using the current
registers and memory map. When MFPI is executed and both previous mode
and current mode are user, the instruction functions as though it were
MFPD.

set if the source < 0
set if the source = 0
cleared
unaffected

6-79

6.3.8 Condition Code Operators
CLN SEN
CLZ SEZ
CLV SEV
CLCSEC
CCCSCC
05

MR-S266

Description:

Set and clear condition code bits. Selectable combinations of these bits may
be cleared or set together. Condition code bits corresponding to bits in the
condition code operator (bits <03:00» are modified according to the sense of
bit 4, the set/clear bit of the operator; i.e., set the bit specified by bit 0, 1, 2,
or 3, if bit 4 = 1. Clear corresponding bits if bit 4 = o.
Mnemonic

Operation

Op Code

CLC
CLV
CLZ
CLN
SEC
SEV
SEZ
SEN
SCC
CCC

Clear C
Clear V
Clear Z
Clear N
Set C
Set V
Set Z
Set N
Set all CCs
Clear all CCs
Clear V and C
No operation

000241
000242
000244
000250
000261
000262
000264
000270
000277
000257
000243
000240

NOP

Combinations of the above set or clear operations may be ORed together to
form combined instructions.

6-80

CHAPTER 7
FLOATING-POINT ARITHMETIC
7.1 INTRODUCTION
The KDll1-A executes 46 floating-point instructions. The floating-point instruction set is compatible with
the FPll instruction set for PDP-II computers. Both single- and double-precision floating-point capabilities are available with other features, including floating-to-integer and integer-to-floating conversion.
The floating-point instruction set is available on the KDll1-A. With the FPll1-AA option, the performance of computation-intensive applications is significantly improved. Refer to the FPJ11 Data Sheet
(EJ-28767) for complete details, and to Appendix C for configuration notes related to use of the option.

7.2 FLOATING-POINT DATA FORMATS
Mathematically, a floating-point number may be defined as having the form (2 ** K) * f, where K is an
integer and f is a fraction. For a nonvanishing number, K and f are uniquely determined by imposing the
condition 1/2 < f < 1. The fractional part (f) of the number is then said to be normalized. For the number
0, f is assigned the value 0, and the value of K is indeterminate.
The floating-point data formats are derived from this mathematical representation for floating-point
numbers. Two types of floating-point data are provided. In single-precision, or floating mode, the data is
32 bits long. In double-precision, or double mode, the data is 64 bits long. Sign magnitude notation is used.

7.2.1 Nonvanishing Floating-Point Numbers
The fractional part (f) is assumed normalized, so that its most significant bit must be 1. This 1 is the
hidden bit. It is not stored explicitly in the data word, but the microcode restores it before carrying out
arithmetic operations. The floating and double modes reserve 23 and 55 bits, respectively, for f. These bits,
with the hidden bit, imply effective word lengths of 24 bits and 56 bits.
Eight bits are reserved for storage of the exponent K in excess 200 notation [i.e., as K + 200 (octal)],
giving a biased exponent. Thus, exponents from -128 to +127 could be represented by 0 to 377 (base 8),
or 0 to 255 (base 10). For reasons given below, a biased exponent of 0 [the true exponent of -200 (octal)],
is reserved for floating-point O. Therefore, exponents are restricted to the range -127 to + 127 inclusive
(-177 to + 177 octal) or, in excess 200 notation, 1 to 377.
The remaining bit of the floating-point word is the sign bit. The number is negative if the sign bit is a 1.

7.2.2 Floating-Point Zero
Because of the hidden bit, the fractional part is not available to distinguish between 0 and nonvanishing
numbers whose fractional part is exactly 1/2. Therefore, the KDJII-A reserves a biased exponent of 0 for
this purpose, and any floating-point number with a biased exponent of 0 either traps or is treated as if it
were an exact 0 in arithmetic operations. An exact or "clean" 0 is represented by a word whose bits are all
Os. A "dirty" 0 is a floating-point number with a biased exponent of 0 and a nonzero fractional part. An
arithmetic operation for which the resulting true exponent exceeds 177 (octal) is regarded as producing a
floating overflow; if the true exponent is less than -177 (octal), the operation is regarded as producing a
floating underflow. A biased exponent of 0 can thus arise from arithmetic operations as a special case of
overflow (true exponent = -200 octal). (Recall that only eight bits are reserved for the biased exponent.)
The fractional part of results obtained from such overflow and underflow is correct.
7-1

7.2.3 Undefined Variables
An undefined variable is any bit pattern with a sign bit of 1 and a biased exponent of O. The term
undefined variable is used, for historical reasons, to indicate that these bit patterns are not assigned a
corresponding floating-point arithmetic value. Note that the undefined variable is frequently referred to as
-0 elsewhere in this chapter.
A design objective was to ensure that the undefined variable would not be stored as the result of any
floating-point operation in a program run with the overflow and underflow interrupts disabled. This is
achieved by storing an exact 0 on overflow and underflow if the corresponding interrupt is disabled. This
feature, together with an ability to detect reference to the undefined variable (implemented by the FIUV
bit discussed later), is intended to provide the user with a debugging aid: if -0 occurs, it did not result from
a previous floating-point arithmetic instruction.
7.2.4 Floating-Point Data
Floating-point data is stored in words of memory as illustrated in Figures 7-1 and 7-2.
F FORMAT, FLOATING POINT SINGLE PRECISION
15
+2

FRACTION <15:0>

MEMORy+o~I S~I ~ ~ ~~_E_X~P ~ ~ ~
__

____

~ ~ ~_F_R~A_CT <_22~:_16_>~ ~ ~
__

MR-3604

figure 7-1

Single-Precision Format

D FORMAT, FLOATING POINT DOUBLE PRECISION
15
+6

~1 ~ ~ ~~ ~ ~ ~ FR~A_C_T_IO~N~<_15_:0~> ~ ~ ~~ ~ ~ ~ ~
__

15
+4

~1 ~ ~ ~~ ~ ~ ~ F~RA_C_T_IO~N~<_31_:~16_> ~ ~ ~ ~ ~ ~ ~
__

~1 ~ ~ ~~ ~ ~ ~ F~RA_C_T_IO_N~<4_7_:3~2_> ~ ~ ~ ~ ~ ~ ~
__

15
MEMORY +0

15
+2

~1__s~I__~____~__~__E~XP ~ ~~ ~ ~ ~ ~ FR_A~C_T_<_5~4_:4_8>~ ~ ~
__

S ~ SIGN OF FRACTION
EXP ~ EXPONENT IN EXCESS 200 NOTATION, RESTRICTED TO 1 TO 377 OCTAL
FOR NON·VANISHING NUMBERS.
FRACTION ~ 23 BITS IN F FORMAT, 55 BITS IN D FORMAT + ONE HIDDEN
BIT (NORMALIZATION). THE BINARY RADIX POINT IS TO THE LEFT.
MR·3605

Figure 7-2

Double-Precision Format

7-2

The KDJll-A provides for conversion of floating-point to integer format and vice-versa. The processor
recognizes single-precision integer (I) and double-precision integer long (L) numbers, which are stored in
standard 2's complement form. (See Figure 7-3.)
I FORMAT, SHORT-INTEGER SINGLE PRECISION
15

NUMBER <15:0>

00
NUMBER <15:0>

L FORMAT, LONG-INTEGER DOUBLE PRECISION
15
14

MEMORY +0

I I
S

00
NUMBER <30:16>

S = SIGN OF NUMBER
NUMBER = 15 BITS IN I FORMAT, 31 BITS IN L FORMAT.
MA·3606

Figure 7-3

2's Complement Format

7.3 FLOATING-POINT STATUS REGISTER (FPS)
This register provides mode and interrupt control for the currently executing floating-point instruction and
also reflects conditions resulting from the execution of the previous instruction. (See Figure 7-4.) In this
discussion a set bit = 1 and a reset bit = O. Three bits of the FPS register control the modes of operation as
follows.

Single/Double - Floating-point numbers can be either single- or double-precision.

Long/Short - Integer numbers can be 16 bits or 32 bits.

Chop/Round - The result of a floating-point operation can be either "chopped" or "rounded."
The term "chop" is used instead of "truncate" to avoid confusion with truncation of series used
in approximations for function subroutines.

RESERVED

Figure 7-4

Floating-Point Status Register

7-3

The FPS register contains an error flag and four condition codes (5 bits): carry, overflow, zero, and
negative, which are analogous to the CPU condition codes.
The KDJ11-A recognizes six floating-point exceptions:
•
•
•
•
•
•

Detection of the presence of the undefined variable in memory
Floating overflow
Floating underflow
Failure of floating-to-integer conversion
Attempt to divide by 0
Illegal floating op code

For the first four of these exceptions, bits in the FPS register are available to individually enable and
disable interrupts. An interrupt on the occurrence of either of the last two exceptions can be disabled only
by setting a bit that disables interrupts on all six of the exceptions, as a group.
Of the 13 FPS bits, 5 are set as part of the output of a floating-point instruction: the error flag and
condition codes. Any of the mode and interrupt control bits may be set by the user; the LDFPS instruction
is available for this purpose. These 13 bits are stored in the FPS register as shown in Figure 7-4. The FPS
register bits are described in Table 7-1.
Table 7-1

FPS Register Bits

Bit

Name

Description

Floating Error (FER)

The FER bit is set by the KDJ! I-A if:
1.

Division by zero occurs

An illegal op code occurs

Anyone of the remaining floating-point exceptions occurs and
the corresponding interrupt is enabled

Note that the above action is independent of whether the FID bit is set
or clear.
Note also that the KDJ\l-A never resets the FER bit. Once the FER
bit is set by the KDJII-A, it can be cleared only by an LDFPS
instruction (note the RESET instruction does not clear the FER bit).
This means that the FER bit is up-to-date only if the most recent
floating-point instruction produced a floating-point exception.
14

Interrupt Disable (FID)

If the FlO bit is set, all floating-point interrupts are disabled.
NOTES
1.

The FID bit is primarily a maintenance feature. It should normally be clear. In particular, it must be clear is one wishes to
assure that storage of -0 by the KDJll-A is always accompanied by an interrupt.

Throughout the rest of the chapter, assume that the FID bit is
clear in all discussions involving overflow, underflow, occurrence
of -0, and integer conversion errors.

7-4

Table 7-1
Bit

Name

FPS Register Bits (Cont)
Description

Reserved for future DIGITAL use.

Interrupt on Undefined
Variable (FlUV)

An interrupt occurs if FIUV is set and a -0 is obtained from memory
as an operand of ADD, SUB, MUL, DIV, CMP, MOD, NEG, ABS,
TST, or any LOAD instruction. The interrupt occurs before execution
on all instructions. When FlUV is reset, -0 can be loaded and used in
any floating-point operation. Note that the interrupt is not activated by
the presence of -0 in an AC operand of an arithmetic instruction; in
particular, trap on -0 never occurs in mode o.
A result of -0 will not be stored without the simultaneous occurrence
of an interrupt.

Interrupt on Underflow (flU)

When the flU bit is set, floating underflow will cause an interrupt. The
fractional part of the result of the operation causing the interrupt will
be correct. The biased exponent will be too large by 400, except for the
special case of 0, which is correct. An exception is discussed later in the
detailed description of the LDEXP instruction.

Interrupt on Overflow (FIV)

When the FIV bit is sct, floating overflow will cause an interrupt. The
fractional part of the result of the operation causing the overflow will
be correct. The biased exponent will be too small by 400.
If the FIV bit is reset and overflow occurs, there is no interrupt. The
KDlll-A returns exact O.

Special cases of overflow are discussed in the detailed descriptions of
the MOD and LDEXP instructions.
08

Interrupt on Integer
Conversion Error (FIC)

When the FIC bit is set and a conversion to integer instruction fails, an
interrupt will occur. If the interrupt occurs, the destination is set to 0,
and all other registers are left untouched.
If the FIC bit is reset, the result of the operation will be the same as
detailed above, but no interrupt will occur.

The conversion instruction fails if it generates an integer with more bits
than can fit in the short or long integer word specified by the FL bit.
07

Floating Double-Precision Mode (FD)

The FD bit determines the precision that is used for floating-point
calculations. When set, double-precision is assumed; when reset, singleprecision is used.

Floating Long-Integer Mode (FL)

The FL bit is active in conversion between integer and floating-point
formats. When set, the integer format assumed is double-precision 2's
complement (i.e., 32 bits). When reset, the integer format is assumed
to be single-precision 2's complement (i.e., 16 bits).

Floating Chop Mode (FT)

When the FT bit is set, the result of any arithmetic operation is
chopped (truncated). When reset, the result is rounded.
Reserved for future DIGITAL use.

04
03

Floating Negative (FN)

FN is set if the result of thc last floating-point operation was negative;
otherwise it is reset.

7-5

Table 7-1

FPS Register Bits (Cont)

Bit

Name

Description

Floating Zero (FZ)

FZ is set if the result of the last floating-point operation was 0; otherwise it is reset.

Floating Overflow (FV)

FV is set if the last floating-point operation resulted in an exponent
overflow; otherwise it is reset.

Floating Carry (FC)

Fe is set if the last floating-point operation resulted in a carry of the
most significant bit.

7.4 FLOATING EXCEPTION CODE AND ADDRESS REGISTERS
One interrupt vector is assigned to take care of all floating-point exceptions (location 244). The six possible
errors are coded in the 4-bit floating exception code (FEC) register as follows.
2
4
6
8
10
12

Floating op code error
Floating divide by zero error
Floating-to-integer or double-to-integer conversion error
Floating overflow error
Floating underflow error
Floating undefined variable error

The address of the instruction producing the exception is stored in the floating exception address (FEA)
register.
The FEC and FEA registers are updated only when one of the following occurs.
1.
2.
3.

Division by zero
Illegal op code
Any of the other four exceptions with the corresponding interrupt enabled

This implies that only when the FER bit is set, the FEC and FEA registers are updated.
NOTES
1.

If one of the last four exceptions occurs with

the corresponding interrupt disabled, the FEC
and FEA are not updated.
2.

If an exception occurs, inhibition of interrupts

by the FID bit does not inhibit updating of the
FEC and FEA.
3.

The FEC and FEA are not updated if no exception occurs. This means that the STST (store
status) instruction will return current information only if the most recent floating-point
instruction produced an exception.

Unlike the FPS, no instructions are provided
for storage into the FEC and FEA registers.
7-6

7.5 FLOATING-POINT INSTRUCTION ADDRESSING
Floating-point instructions use the same type of addressing as the central processor instructions. A source
or destination operand is specified by designating one of eight addressing modes and one of eight central
processor general registers to be used in the specified mode. The modes of addressing are the same as those
of the central processor, except in mode o. In mode 0 the operand is located in the designated floatingpoint processor accumulator rather than in a central processor general register. The modes of addressing
are as follows.

o = Floating-point accumulator
1 = Deferred
2 = Autoincrement
3 = Autoincrement-deferred
4 = Autodecrement
5 = Autodecrement-deferred
6 = Indexed
7 = Indexed-deferred
Autoincrement and autodecrement operate on increments and decrements of 4 for F format, and 10
(octal) for D format.
In mode 0 users can make use of all six floating-point accumulators (ACO-AC5) as their source or
destination. Specifying floating-point accumulators AC6 or AC7 will result in an illegal op code trap. In all
other modes, which involve transfer of data to or from memory or the general registers, users are restricted
to the first four floating-point accumulators (ACO-AC3). When reading or writing a floating-point
number from or to memory, the low memory word contains the most significant word of the floating-point
number, and the high memory word the least significant word.
7.6 ACCURACY
General comments on the accuracy of the KDJ11-A floating-point instructions are presented here. The
descriptions of the individual instructions include the accuracy at which they operate. An instruction or
operation is regarded as "exact" if the result is identical to an infinite precision calculation involving the
same operands. The a priori accuracy of the operands is thus ignored. All arithmetic instructions treat an
operand whose biased exponent is 0 as an exact 0 (unless FIUV is enabled and the operand is -0, in which
case an interrupt occurs). For all arithmetic operations, except DIV, a 0 operand implies that the
instruction is exact. The same statement holds for DIV if the 0 operand is the dividend. But if it is the
divisor, division is undefined and an interrupt occurs.
For nonvanishing floating-point operands, the fractional part is binary normalized. It contains 24 bits or 56
bits for floating mode and double mode, respectively. For ADD, SUB, MUL, and DIV, two guard bits are
necessary and sufficient for the general case to guarantee return of a chopped or rounded result identical to
the corresponding infinite precision operation chopped or rounded to the specified word length. Thus, with
two guard bits, a chopped result has an error bound of one least significant bit (LSB); a rounded result has
an error bound of 1/2 LSB. These error bounds are realized by the KDJ11-A for all instructions.

7-7

In the rest of this chapter, an arithmetic result is called exact if no nonvanishing bits would be lost by
chopping. The first bit lost in chopping is referred to as the "rounding" bit. The value of a rounded result is
related to the chopped result as follows.
I.

If the rounding bit is I, the rounded result is the chopped result incremented by an LSB.

If the rounding bit is 0, the rounded and chopped results are identical.

It follows that:

If the result is exact: rounded value = chopped value = exact value.

If the result is not exact, its magnitude is:
•
•
•

always decreased by chopping.
decreased by rounding if the rounding bit is O.
increased by rounding if the rounding bit is I.

Occurrence of floating-point overflow and underflow is an error condition: the result of the calculation
cannot be correctly stored because the exponent is too large to fit into the eight bits reserved for it.
However, the internal hardware has produced the correct answer. For the case of underflow, replacement
of the correct answer by 0 is a reasonable resolution of the problem for many applications. This is done by
the KDJ II-A if the underflow interrupt is disabled. The error incurred by this action is an absolute rather
than a relative error; it is bounded (in absolute value) by 2 ** -128. There is no such simple resolution for
the case of overflow. The action taken, if the overflow interrupt is disabled, is described under FlV (bit 09)
in Table 7-1.
The FlV and FlU bits (of the floating-point status word) provide users with an opportunity to implement
their own correction of an overflow or underflow condition. If such a condition occurs and the corresponding interrupt is enabled, the microcode stores the fractional part and the low eight bits of the biased
exponent. The interrupt will take place and users can identify the cause by examination of the floating
overflow (FV) bit or the floating exception register (FEC). The reader can readily verify that (for the
standard arithmetic operations ADD, SUB, MUL, and DIV) the biased exponent returned by the instruction bears the following relation to the correct exponent.
1.

On overflow, it is too small by 400 (octal)

On underflow, if the biased exponent is 0, it is correct. If the biased exponent is not 0, it is too
large by 400 (octal).

Thus, with the interrupt enable, enough information is available to determine the correct answer. Users
may, for example, rescale their variables (via STEXP and LDEXP) to continue a calculation. Note that
the accuracy of the fractional part is unaffected by the occurrence of underflow or overflow.
7.7 FLOATING-POINT INSTRUCTIONS
Each instruction that references a floating-point number can operate on either single- or double-precision
numbers, depending on the state of the FD mode bit. Similarly, there is a mode bit FL that determines
whether a 32-bit integer (FL = 1) or a 16-bit integer (FL = 0) is used in conversion between integer and
floating-point representations. FSRC and FDST operands use floating-point addressing modes (see Figure
7-5); SRC and DST operands use CPU addressing modes.

7-8

DOUBLE OPERAND ADDRESSING

FOC

00
FSRC,FDST,SRC,DST

SINGLE OPERAND ADDRESSING

FOC

00
FSRC, FDST,SRC,DST

OC = OPCODE = 17
FOC = F LOATI NG OPCODE
AC= FLOATING POINT ACCUMULATOR (ACO-AC3)
FSRC AND FDST USE FPP ADDRESSING MODES
SRCAND DST USE CPU ADDRESSING MODES
MR·3608

Figure 7-5

Floating-Point Addressing Modes

Terms Used in Instruction Definitions

op code = 17

FOC

floating op code

contents of accumulator, as specified by AC field of instruction

fsrc

address of floating-point source operand

fdst

address of floating-point destination operand

fraction

largest fraction that can be represented:
1 - 2 ** (-24), FD = 0; single-precision
1 - 2 ** (-56), FD = 1; double-precision

XLL

smallest number that is not identically zero =
2 ** (-128)

XUL

largest number that can be represented =
2 ** (127) * XL

largest integer that can be represented:
2 ** (15) - 1; FL = 0; short integer
2 ** (31) - 1; FL = 1; long integer

ABS (address) = absolute value of (address)
EXP (address) = biased exponent of (address)

7-9

.LT

"less than"

.LE.

"less than or equal to"

.GT.

"greater than"

.GE.

"greater than or equal to"
least significant bit

LSB

Boolean Symbols
1\

AND

inclusive OR

exclusive OR
NOT

ABSF/ABSD
MAKE ABSOLUTE FLOATING/DOUBLE

1706 FDST

MR-11467

Format:

ABSF FDST

Operation:

If (FDST) < 0, (FDST) +- - (FDST).

If EXP(FDST) = 0, (FDST) +- exact O.
For all other cases, (FDST) +- (FDST).
Condition Codes:

FC +- 0
FV +- 0
FZ +- 1 if (FDST) = 0, else FZ +- 0

FN +- 0
Description:

Set the contents of FDST to its absolute value.

Interrupts:

If FIUV is enabled, trap on -0 occurs before execution. Overflow and
underflow cannot occur.

Accuracy:

These instructions are exact.

7-10

ADDF/ADDD

ADD FLOATING/DOUBLE
15

172(AC) FSRC

AC
MR-1146B

Format:

ADDF FSRC,AC

Operation:

Let SUM = (AC) + (FSRC)
If underflow occurs and FlU is not enabled, AC <- exact O.
If overflow occurs and FlV is not enabled, AC <- exact O.
For all others cases, AC <- SUM.

Condition Codes:

FC <- 0
FV <- 1 if overflow occurs, else FV <- 0
FZ <- 1 if (AC) = 0, else FZ <- 0
FN <- 1 if (AC) < 0, else FN <- 0

Description:

Add the contents of FSRC to the contents of AC. The addition is carried out
in sing1e- or double-precision and is rounded or chopped in accordance with
the values of the FD and FT bits in the FPS register. The result is stored in
AC except for:
1.
2.

Overflow with interrupt disabled.
Underflow with interrupt disabled.

For these exceptional cases, an exact 0 is stored in AC.
Interrupts:

If FlUV is enabled, trap on -0 in FSRC occurs before execution. If overflow
or underflow occurs, and if the corresponding interrupt is enabled, the trap
occurs with the faulty result in AC. The fractional parts are correctly stored.
The exponent part is too small by 400 for overflow. It is too large by 400 for
underflow, except for the special case of 0, which is correct.

Accuracy:

Errors due to overflow and underflow are described above. If neither occurs,
then: for oppositely signed operands with exponent difference of 0 or 1, the
answer returned is exact if a loss of significance of one or more bits can
occur. Note that these are the only cases for which loss of significance of
more than one bit can occur. For all other cases the result is inexact with
error bounds of:
1.
2.

Special Comment:

LSB in chopping mode with either single- or double-precision.
1/2 LSB in rounding mode with either single- or double-precision.

The undefined variable -0 can occur only in conjunction with overflow or
underflow. It will be stored in AC only if the corresponding interrupt is
enabled.
7-11

CFCC

COpy FLOATING CONDITION CODES

170000

: 0

MA-11469

Format:

CFCC

Operation:

C <- FC
V <- FV
Z <- FZ
N<- FN

Description:

Copy the floating-point condition codes into the CPU's condition codes.

CLRFjCLRD
1704 FDST

CLEAR FLOATING/DOUBLE

05
I

FDST
MA-11470

Format:

CLRF FDST

Operation:

(FDST) <- exact 0

Condition Codes:

FC <- 0
FV <- 0
FZ <-1
FN <- 0

Description:

Set FDST to O. Set FZ condition code and clear other condition code bits.

Interrupts:

No interrupts will occur. Overflow and underflow cannot occur.

Accuracy:

These instructions are exact.

7-12

CMPF/CMPD

COMPARE FLOATING/OOUBLE
15

173(AC+4) FSRC

MR·11471

Format:

CMPF FSRC,AC

Operation:

(FSRC) - (AC)

Condition Codes:

FC-O
FV-O

FZ - 1 if (FSRC) = 0, else FZ <-- 0
FN - 1 if (FSRC) < 0, else FN - 0
Description:

Compare the contents of FSRC with the accumulator. Set the appropriate
floating-point condition codes. FSRC and the accumulator are left unchanged
except as noted below.

Interrupts:

If FIUV is enabled, trap on -0 occurs before execution.

Accuracy:

These instructions are exact.

Special Comment:

An operand that has a biased exponent of 0 is treated as if it were an exact o.
In this case, where both operands are 0, the KDll1-A will store an exact 0 in
AC.

7-13

DIVF/DIVD
174(AC+4) FSRC

DIVIDE FLOATING/DOUBLE

00
FSRC

MR·11472

Format:

DIVF FSRC,AC

Operation:

If EXP(FSRC) = 0, (AC) <- (AC) and the instruction is aborted.
If EXP(AC) = 0, (AC) <- exact o.
For all other cases, let QUOT = (AC)/(FSRC).
If underflow occurs and flU is not enabled, AC <- exact o.
If overflow occurs and FlV is not enabled, AC <- exact O.

For all others cases, AC <- QUOT.
Condition Codes:

FC <- 0
FV <- 1 if overflow occurs, else FV ........ 0
FZ <- 1 if (AC) = 0, else FZ <- 0
FN <- 1 if (AC) < 0, else FN <- 0

Description:

If either operand has a biased exponent of 0, it is treated as an exact O. For

FSRC this would imply division by 0; in this case the instruction is aborted,
the FEC register is set to 4, and an interrupt occurs. Otherwise, the quotient
is developed to single- or double-precision with two guard bits for correct
rounding. The quotient is rounded or chopped in accordance with the values
of the FD and FT bits in the FPS register. The result is stored in the AC
except for:
1.
2.

Overflow with interrupt disabled.
Underflow with interrupt disabled.

For these exceptional cases, an exact 0 is stored in AC.
Interrupts:

If FlUV is enabled, trap on -0 in FSRC occurs before execution. If (FSRC)
= 0, interrupt traps on an attempt to divide by O. If overflow or underflow

occurs, and if the corresponding interrupt is enabled, the trap occurs with the
faulty result in AC. The fractional parts are correctly stored. The exponent
part is too small by 400 for overflow. It is too large by 400 for underflow,
except for the special case of 0, which is correct.
Accuracy:

Errors due to overflow "and underflow are described above. If none of these
occurs, the error in the quotient will be bounded by 1 LSB in chopping mode
and by 1/2 LSB in rounding mode.

Special Comment:

The undefined variable -0 can occur only in conjunction with overflow or
underflow. It will be stored in AC only if the corresponding interrupt is
enabled.
7-14

LDCDFILDCFD
LOAD AND CONVERT FROM DOUBLE-TO-FLOATING
AND FROM FLOATING-TO-DOUBLE

177(AC+4)FSRC

I ~C I

00
FSRC

MR-11473

Format:

LDCDF FSRC,AC

Operation:

If EXP(FSRC) = 0, AC .- exact O.
If FD = 1, FT = 0, FlV = 0 and rounding causes overflow, AC .- exact O.
In all other cases, AC .- Cxy(FSRC), where Cxy specifies conversion from
floating mode x to floating mode y.
x = D, Y = F if FD = 0 (single) LDCDF
y = F, Y = D if FD = 1 (double) LDCFD

Condition Codes:

FC.- 0
FV .- 1 if conversion produces overflow, else
FV.- 0
FZ <- 1 if (AC) = 0, else FZ <- 0
FN .- 1 if (AC) < 0, else FN .- 0

Description:

If the current mode is floating mode (FD = 0), the source is assumed to be a
double-precision number and is converted to single-precision. If the floating
chop bit (FT) is set, the number is chopped; otherwise, the number is
rounded.
If the current mode is double mode (FD = 1), the source is assumed to be a
single-precision number and is loaded left-justified in AC. The lower half of
AC is cleared.

Interrupts:

If FlUV is enabled, trap on -0 occurs before execution. Overflow cannot
occur for LDCFD.

A trap occurs if FlV is enabled, and if rounding with LDCDF causes overflow. AC .- overflowed result. This result must be +0 or -0. Underflow
cannot occur.
Accuracy:

LDCFD is an exact instruction. Except for overflow, described above,
LDCDF incurs an error bounded by 1 LSB in chopping mode and by 1/2
LSB in rounding mode.

7-15

LDCIF /LDCID/LDCLF /LDCLD

LOAD AND CONVERT INTEGER OR LONG INTEGER
TO FLOATING OR DOUBLE-PRECISION

177(AC)SRC

MR-11474

Format:

LDCIF SRC,AC

Operation:

AC +- Cjx(SRC), where Cjx specifies conversion from integer mode j to
floating mode x.
j = I if FL = 0, j = L if FL = 1
x = F if FD = 0, x = D if FD = 1

Condition Codes:

Descri ption:

°°

FC +FV +FZ +- 1 if (AC) = 0, else FZ +FN +- 1 if (AC) < 0, else FN +-

°°

Conversion is performed on the contents of SRC from a 2's complement
integer with precision j to a floating-point number of precision x, Note that j
and x are determined by the state of the mode bits FL and FD.

If a 32-bit integer is specified (L mode) and (SRC) has an addressing mode of
or immediate addressing mode is specified, the 16 bits of the source register
are left-justified and the remaining 16 bits loaded with Os before conversion.
In the case of LDCLF, the fractional part of the floating-point representation
is chopped or rounded to 24 bits for FT = 1 or 0, respectively.

Interrupts:

None; SRC is not floating-point, so trap on -0 cannot occur.

Accuracy:

LDCIF, LDCID, and LDCLD are exact instructions. The error incurred by
LDCLF is bounded by 1 LSB in chopping mode and by 1/2 LSB in rounding
mode.

7-16

LDEXP
176(AC+4ISRC

LOAD EXPONENT

I ~C I

MR-11475

Format:

LDEXP SRC,AR

Operation:

NOTE: 177 and 200, appearing below, are octal numbers.
If -200 < SRC < 200, EXP(AC) unchanged.

SRC + 200 and the rest of AC is

If (SRC) > 177 and FIV is enabled, EXP(AC) - [(SRC) + 200]<07:00>.

If (SRC) > 177 and FIV is disabled, AC - exact O.
If (SRC) < -177 and flU is enabled, EXP(AC) - [(SRC) + 200]<07:00>.
If (SRC) < -177 and flU is disabled, AC - exact O.
Condition Codes:

FC-O
FV - 1 if (SRC) > 177, else FV - 0
FZ - I if (AC) = 0, else FZ - 0
FN - 1 if (AC) < 0, else FN - 0

Description:

Change AC so that its unbiased exponent = (SRC). That is, convert (SRC)
from 2's complement to excess 200 notation and insert it into the EXP field
of AC. This is a meaningful operation only if ABS(SRC) LE 177.
If SRC > 177, the result is treated as overflow. If SRC < -177, the result is
treated as underflow.

Interrupts:

No trap on -0 in AC occurs, even if FIUV is enabled. If SRC > 177 and FlV
is enabled, trap on overflow will occur. If SRC < -177 and flU is enabled,
trap on underflow will occur.

Accuracy:

Errors due to overflow and underflow are described above. If EXP(AC) = 0
and (SRC) = -200, AC changes from a floating-point number treated as 0
by all floating arithmetic operations to a non-O number. This happens because
the insertion of the "hidden" bit in the microcode implementation of arithmetic instructions is triggered by a nonvanishing value of EXP.
For all other cases, LDEXP implements exactly the transformation of a
floating-point number (2 ** K) * f into (2 ** (SRC)) * f where 1/2 .LE.
ABS(f) .LT. 1.

7-17

LDF/LDD

LOAD FLOATING/DOUBLE
15

172(AC+4)FSRC
OB

MR-11476

Format:

LDF FSRC,AC

Operation:

AC +- (FSRC)

Condition Codes:

FC +- 0
FY +- 0
FZ +- 1 if (AC) = 0, else FZ +- 0
FN +- 1 if (AC) < 0, else FN +- 0

Description:

Load single- or double-precision number into AC.

Interrupts:

If FIUY is enabled, trap on -0 occurs before AC is loaded. Overflow and

underflow cannot occur.
Accuracy:

These instructions are exact.

Special Comment:

These instructions permit use of -0 in a subsequent floating-point instruction
if FIUY is not enabled and (FSRC) = -0.

LDFPS

LOAD FLOATING-POINT PROGRAM STATUS
15

1701 SRC
06

a
MR-11477

Format:

LDFPS SRC

Operation:

FPS +- (SRC)

Description:

Load floating-point status register from SRC.

Special Comment:

Users are cautioned not to use bits 13, 12, and 04 for their own purposes,
since these bits are not recoverable by the STFPS instruction.

7-18

MODF/MODD
MULTIPLY AND SEPARATE INTEGER
AND FRACTION FLOATING/DOUBLE
12

I : : :
1

171(AC+4)FSRC

\
AC

MR-1'478

Format:

MODF FSRC,AC

Description
and Operation:

This instruction generates the product of its two floating-point operands,
separates the product into integer and fractional parts, and then stores one or
both parts as floating-point numbers.
Let PROD = (AC) * (FSRC) so that in
Floating-point: ABS(PROD) = (2 ** K) * f, where
1/2 .LE. f .LT. 1, and EXP(PROD) = (200 + K)
Fixed-point binary: PROD = N + g, where
N = INT(PROD) = integer part of PROD, and
g = PROD - INT(PROD) = fractional part of PROD with 0 .LE. g
.LT.1.
Both Nand g have the same sign as PROD. They are returned as follows:
If AC is an even-numbered accumulator (0 or 2), N is stored in AC+ 1
(1 or 3), and g is stored in AC.
If AC is an odd-numbered accumulator, N is not stored and g is stored
in AC.
The two statements above can be combined as follows:
N is returned to AC V 1 and g is returned to AC.

7-19

Five special cases occur, as indicated in the following formal description with
L = 24 for floating mode and L = 56 for double mode.
1.

If PROD overflows and FlV is enabled, AC VI+- N, chopped to L
bits, AC +- exact O.
Note that EXP(N) is too small by 400 and that -0 can be stored in AC
V 1.
If FlV is not enabled, AC VI+- exact 0, AC +- exact 0, and -0 will
never be stored.

If 2 ** L .LE. ABS(PROD) and no overflow, AC VI+- N, chopped to
L bits, AC +- exact o.
The sign and EXP of N are correct, but low-order bit information is lost.

If 1 .LE. ABS(PROD) .LT. 2 ** L, AC VI+- N, AC +- g.
The integer part N is exact. The fractional part g is normalized, and
chopped or rounded in accordance with FT. Rounding may cause a
return of + unity for the fractional part. For L = 24, the error in g is
bounded by 1 LSB in chopping mode and by 1/2 LSB in rounding mode.
For L = 56, the error in g increases from the above limits as ABS(N)
increases above 8 because only 59 bits of PROD are generated.
If 2 ** P .LE. ABS(N) .LT. 2 ** (p + 1), with p > 2, the low order p - 2
bits of g may be in error.

If ABS(PROD) .LT. 1 and no underflow, AC VI+- exact 0 and AC +g.
There is no error in the integer part. The error in the fractional part is
bounded by 1 LSB in chopping mode and 1/2 LSB in rounding mode.
Rounding may cause a return of + unity for the fractional part.

If PROD underflows and FlU is enabled, AC VI+- exact 0 and AC +g.
Errors are as in case 4, except that EXP(AC) will be too large by 4008
(if EXP = 0, it is correct). Interrupt will occur and -0 can be stored in
AC.
If flU is not enabled, AC VI+- exact 0 and AC +- exact o.
For this case the error in the fractional part is less than 2 ** (-128).

7-20

Condition Codes:

FC.- 0
FV .- 1 if PROD overflows, else FV ........ 0
FZ .- 1 if (AC) = 0, else FZ .-0
FN .- 1 if (AC) < 0, else FN .- 0

Interrupts:

If FIUV is enabled, trap on -0 in FSRC occurs before execution. Overflow
and underflow are discussed above.

Accuracy:

Discussed above.

Applications:

Binary-to-decimal conversion of a proper fraction. The following
algorithm, using MOD, will generate decimal digits D(1), D(2) ... from
left to right.
Initialize:

1.- 0;
X.- number to be converted;
ABS(X) < 1;

While X =f= 0 do
Begin PROD .- X * 10;
I .- I + 1;
D(I) .- INT(PROD);
X <- PROD - INT(PROD);
End;
This algorithm is exact. It is case 3 in the description because the
number of nonvanishing bits in the fractional part of PROD never
exceeds L, and hence neither chopping nor rounding can introduce error.
2.

To reduce the argument of a trigonometric function.
ARG * 2/PI = N + g. The low two bits of N identify the quadrant, and
g is the argument reduced to the first quadrant. The accuracy of N + g
is limited to L bits because of the factor 2/pI. The accuracy of the
reduced argument thus depends on the size of N.

To evaluate the exponential function e ** x, obtain x * (log e base 2) =
N + g, then e ** x = (2 ** N) * (e ** (g * In 2».
The reduced argument is g * In2 < 1 and the factor 2 * * N is an exact
power of 2, which may be scaled in at the end via STEXP, ADD N to
EXP and LDEXP. The accuracy of N + g is limited to L bits because of
the factor (log e base 2). The accuracy of the reduced argument thus
depends on the size of N.

7-21

MULF/MULD
171(AC)FSRC

MULTIPLY FLOATING/DOUBLE

FSRC

MR-11479

Format:

MULF FSRC,AC

Operation:

Let PROD = (AC) * (FSRC)

If underflow occurs and flU is not enabled, AC f - exact o.
If overflow occurs and FlV is not enabled, AC f - exact O.
For all others cases, AC f - PROD.

Condition Codes:

FC f - 0
FV f - 1 if overflow occurs, else FV f - 0
FZ f - 1 if (AC) = 0, else FZ f - 0
FN f - 1 if (AC) < 0, else FN f - 0

Description:

If the biased exponent of either operand is 0, CAC) f - exact o. For all other
cases PROD is generated to 48 bits for floating mode and 59 bits for double
mode. The product is rounded or chopped for FT = 0 or 1, respectively, and
is stored in AC except for:
1.
2.

Overflow with interrupt disabled
Underflow with interrupt disabled

For these exceptional cases, an exact 0 is stored in AC.
Interrupts:

If FIUV is enabled, trap on -0 in FSRC occurs before execution. If overflow
or underflow occurs, and if the corresponding interrupt is enabled, the trap
occurs with the faulty result in AC. The fractional parts are correctly stored.
The exponent part is too small by 400 for overflow. It is too large by 400 for
underflow, except for the special case of 0, which is correct.

Accuracy:

Errors due to overflow and underflow are described above. If neither occurs,
the error incurred is bounded by 1 LSB in chopping mode and 1/2 LSB in
rounding mode.

Special Comment:

The undefined variable -0 can occur only in conjunction with overflow or
underflow. It will be stored in AC only if the corresponding interrupt is
enabled.

7-22

NEGF/NEGD
NEGATE FLOATING/DOUBLE

1707 FDST

o
MR-114S0

Format:

NEGFFDST

Operation:

(FDST) -

Condition Codes:

FC-O
FV-O
FZ - 1 if (FDST) = 0, else FZ - 0
FN - 1 if (FDST) < 0, else FN - 0

Description:

Negate the single- or double-precision number; store result in same location
(FDST).

Interrupts:

If FIUV is enabled, trap on -0 occurs before execution. Overflow and
underflow cannot occur.

Accuracy:

These instructions are exact.

- (FDST) if (FDST) = 0, else (FDST) -

exact 0

SETD
SET FLOATING DOUBLE MODE

170011

00
1

0
!

MA·11481

Format:

SETD

Operation:

FD-l

Description:

Set the KDJll-A in double-precision mode.

7-23

SETF
170001

SET FLOATING MODE

i
0

1
I

MR-11482

Format:

SETF

Operation:

FD-O

Description:

Set the KDJ11-A in single-precision mode.

SETI
SET INTEGER MODE

170002
12

MR-11483

Format:

SET!

Operation:

FL-O

Description:

Set the KDJ11-A for short-integer data.

SETL
170012

SET LONG-INTEGER MODE
15

;, :

12
1

I 0

:0 :a :a : a : a : a : 0 : 1 :a :1

i
!

MA-11484

Format:

SETL

Operation:

FL -1

Description:

Set the K0J11-A for long-integer data.

7-24

STCFD/STCDF

STORE AND CONVERT FROM FLOATING-TO-DOUBLE
AND FROM DOUBLE-TO-FLOATING
15

176 (AC) FOST
07

MR-11485

Format:

STCFD AC,FDST

Operation:

If (AC) = 0, (FDST) -

exact O.

If FD = 1, FT = 0, FIV = 0 and rounding causes overflow, (FDST) - exact

O.
In all other cases, (FDST) - Cxy(AC), where Cxy specifies conversion from
floating mode x to floating mode y.
x = F, y = D if FD = 0 (single) STCFD
x = D, y = F if FD = 1 (double) STCDF
Condition Codes:

FC-O

FV -

1 if conversion produces overflow, else

FV-O

FZ - 1 if (AC) = 0, else FZ - 0
FN - 1 if (AC) < 0, else FN - 0
Description:

If the current mode is single-precision, the accumulator is stored left-justified
in FDST and the lower half is cleared.
If the current mode is double-precision, the contents of the accumulator are
converted to single-precision, chopped or rounded depending on the state of
FT, and stored in FDST.

Interrupts:

Trap on -0 will not occur even if FIUV is enabled because FSRC is an
accumulator. Underflow cannot occur. Overflow cannot occur for STCFD.
A trap occurs if FIV is enabled, and if rounding with STCDF causes overflow. (FDST) - overflowed result. This must be +0 or -0.

Accuracy:

STCFD is an exact instruction. Except for overflow, described above,
STCDF incurs an error bounded by 1 LSB in chopping mode and by 1/2 LSB
in rounding mode.

7-25

STCFI/STCFL/STCDI/STCDL
STORE AND CONVERT FROM FLOATING OR DOUBLE
TO INTEGER OR LONG INTEGER
15

I : : : I
1

11
1

175(AC+4)DST
07

MR-11486

Format:

STCFI AC,DST

Operation:

(DST) - Cxj(AC) if -JL - 1 < Cxj(AC) < JL + 1, else (DST) - 0, where
Cjx specifies conversion from floating mode j to integer mode x.
j = I if FL = 0, j = L if FL = 1
x = F if FD = 0, x = D if FD = 1
JL is the largest integer.
2 ** 15 - 1 for FL = 0
2 ** 32 - 1 for FL = 1
0 if -JL - 1 < Cxj(AC) < JL + 1, else
1
0
1 if (DST) = 0, else Z, FZ - 0
1 if (DST) < 0, else N, FN - 0

Condition Codes:

C, FC C, FC V, FV Z, FZ N, FN -

Description:

Conversion is performed from a floating-point representation of the data in
the accumulator to an integer representation.
If the conversion is to a 32-bit word (L mode), and an addressing mode of 0
or immediate addressing mode is specified, only the most significant 16 bits
are stored in the destination register.
If the operation is out of the integer range selected by FL, FC is set to 1 and
the contents of the DST are set to O.

Numbers to be converted are always chopped (rather than rounded) before
they are converted. This is true even when the chop mode bit FT is cleared in
the FPS register.
Interrupts:

These instructions do not interrupt if FIUV is enabled, because the -0, if
preSent, is in AC, not in memory. If FIC is enabled, trap on conversion failure
will occur.

Accuracy:

These instructions store the integer part of the floating-point operand, which
may not be the integer most closely approximating the operand. They are
exact if the integer part is within the range implied by FL.

7-26

STEXP

STORE EXPONENT

175(AC)DST

MR-11487

Format:

STEXP AC,DST

Operation:

(DST) - EXP(AC) - 200

Condition Codes:

C, FC - 0
V, FV - 0
Z, FZ - 1 if (DST) = 0, else Z, FZ - 0
N, FN - 1 if (DST) < 0, else N, FN - 0

Description:

Convert AC's exponent from excess 200 notation to 2's complement and
store the result in DST.

Interrupts:

This instruction will not trap on -0. Overflow and underflow cannot occur.

Accuracy:

This instruction is exact.

STF/STD
STORE FLOATING/DOUBLE

174(AC) F DST

MR-11488

Format:

STF AC,FDST

Operation:

(FDST) - AC

Condition Codes:

FC-FC
FV-FV
FZ-FZ
FN-FN

Description:

Store single- or double-precision number from AC.

Interrupts:

These instructions do not interrupt if FIUV is enabled, because the -0, if
present, is in AC, not in memory. Overflow and underflow cannot occur.

7-27

Accuracy:

These instructions are exact.

Special Comment:

These instructions permit storage of a -0 in memory from AC. There are two
conditions in which -0 can be stored in an AC of the KDJ11-A. One occurs
when underflow or overflow is present and the corresponding interrupt is
enabled. A second occurs when an LDF or LDD instruction is executed and
the FIUV bit is disabled.

STFPS
STORE FLOATING-POINT PROGRAM STATUS
12

I >
1

1702DST

06
:

D~T

MA-11489

Format:

STFPS DST

Operation:

(DST) +- FPS

Description:

Store the floating-point status register in DST.

Special Comment:

Bits 13, 12, and 04 are loaded with O. All other bits are the corresponding bits
in the FPS.

STST
STORE FPP'S STATUS

1703 DST

MR-11490

Format:

STST DST

Operation:

(DST) +- FEC (DST + 2) +- FEA

Description:

Store the FEC and FEA in DST and DST+2. Note the following.
1.

If the destination mode specifies a general register or immediate addressing, only the FEC is saved.

The information in these registers is current only if the most recently
executed floating-point instruction caused a floating-point exception.

7-28

SUBF/SUBD

SUBTRACT FLOATING/DOUBLE

173(AC)FSRC

(

MR-11491

Format:

SUBF FSRC,AC

Operation:

Let DIFF = (AC) - (FSRC)
If underflow occurs and FlU is not enabled, AC If overflow occurs and FlV is not enabled, AC -

exact o.
exact o.

For all others cases, AC - DIFF.
Condition Codes:

FC-O
FV - 1 if overflow occurs, else FV - 0
FZ - 1 if (AC) = 0, else FZ - 0
FN - 1 if (AC) < 0, else FN - 0

Description:

Subtract the contents of FSRC from the contents of AC. The subtraction is
carried out in single- or double-precision and is rounded or chopped in accordance with the values of the FD and FT bits in the FPS register. The result is
stored in AC except for:
1.
2.

Overflow with interrupt disabled
Underflow with interrupt disabled

For these exceptional cases, an exact 0 is stored in AC.
Interrupts:

If FIUV is enabled, trap on -0 in FSRC occurs before execution. If overflow

or underflow occurs, and if the corresponding interrupt is enabled, the trap
occurs with the faulty result in AC. The fractional parts are correctly stored.
The exponent part is too small by 400 for overflow. It is too large by 400 for
underflow, except for the special case of 0, which is correct.
Accuracy:

Errors due to overflow and underflow are described above. If neither occurs:
for like-signed operands with exponent difference of 0 or 1, the answer
returned is exact if a loss of significance of one or more bits can occur. Note
that these are the only cases for which loss of significance of more than one
bit can occur. For all other cases the result is inexact with error bounds of:
1.
2.

Special Comment:

LSB in chopping mode with either single- or double-precision
1/2 LSB in rounding mode with either single- or double-precision

The undefined variable -0 can occur only in conjunction with overflow or
underflow. It will be stored in AC only if the corresponding interrupt is
enabled.

7-29

TSTFjTSTD
TEST FLOATING/DOUBLE

1705 FDST

MR-11492

Format:

TSTF FDST

Operation:

(FDST)

Condition Codes:

FC~O
FV~O

FZ ~ 1 if (FDST) = 0, else FZ ~ 0
FN ~ 1 if (FDST) < 0, else FN ~ 0
Description:

Set the floating-point condition codes according to the contents of FDST.

Interrupts:

If FIUV is set, trap on -0 occurs before execution. Overflow and underflow
cannot occur.

Accuracy:

These instructions are exact.

7-30

CHAPTER 8
PROGRAMMING TECHNIQUES

8.1 INTRODUCTION
The KDJII-A offers a great deal of programming flexibility and power. Utilizing the combination of the
instruction set, the addressing modes, and the programming techniques, it is possible to develop new
software or to utilize old programs effectively. The programming techniques in this chapter show the
capabilities of the KDJ II-A. The techniques discussed involve position-independent coding (PIC), stacks,
subroutines, interrupts, reentrancy, coroutines, recursion, processor traps, programming peripherals, and
conversion.
8.2 POSITION-INDEPENDENT CODE
The output of a MACRO-II assembly is a relocatable object module. The task builder or linker binds one
or more modules together to create an executable task image. Once built, a task can only be loaded and
executed at the virtual address specified at link time. This is so because the linker has had to modify some
instructions to reflect the memory locations in which the program is to run. Such a body of code is
considered position-dependent (i.e., dependent on the virtual addresses to which it was bound).
The KDJ11-A processor offers addressing modes that make it possible to write instructions that do not
depend on the virtual addresses to which they are bound. This type of code is termed position-independent
and can be loaded and executed at any virtual address. Position-independent code can improve system
efficiency, both in use of virtual address space and in conservation of physical memory.
In multiprogramming systems like RSX-llM, it is important that many tasks be able to share a single
physical copy of common code (a library routine, for example). To make the optimum use of a task's
virtual address space, shared code should be position-independent. Code that is not position-independent
can also be shared, but it must appear in the same virtual locations in every task using it. This restricts the
placement of such code by the task builder and can result in the loss of virtual addressing space.
8.2.1 Use of Addressing Modes in the Construction of Position-Independent Code
The construction of position-independent code is closely linked to the proper use of addressing modes. The
remainder of this explanation assumes you are familiar with the addressing modes described in Chapter 6.
The following addressing modes, which involve only register references, are position-independent.
R
(R)

(R)+
@(R)+
-(R)
@-(R)

Register mode
Register-deferred mode
Autoincrement mode
Autoincrement-deferred mode
Autodecrement mode
Autodecrement-deferred mode

When employing these addressing modes, the user is guaranteed position independence, providing the
contents of the registers have been supplied independently of a particular virtual memory location.
8-1

The following two relative addressing modes are position-independent when a relocatable address is
referenced from a relocatable instruction.
A
@A

Relative mode
Relative-deferred mode

Relative modes are not position-independent when an absolute address (that is, a nonrelocatable address) is
referenced from a relocatable instruction. In such case, absolute addressing (i.e., @#A) may be employed
to make the reference position-independent.
Index modes can be either position-independent or position-dependent, according to their use in the
program:
X(R)
@X(R)

Index mode
Index-deferred mode

If the base, X, is an absolute value (e.g., a control block offset), the reference is position-independent. The
following is an example.
MOV

2(SP),RO

;POSITION-INDEPENDENT

MOV

N(SP),RO

;POSITION-INDEPENDENT

N=4

If, however, X is a relocatable address, the reference is position-dependent, as the following example
shows.
CLR

ADDR(RI)

;POSITION-DEPENDENT

Immediate mode can be either position-independent or not, according to its use. Immediate mode references are formatted as follows.
#N

Immediate mode

When an absolute expression defines the value of N, the code is position-independent. When a relocatable
expression defines N, the code is position-dependent. That is, immediate mode references are positionindependent only when N is an absolute value.
Absolute mode addressing is position-independent only in those cases where an absolute virtual location is
being referenced. Absolute mode addressing references are formatted as follows.
@#A

Absolute mode

An example of a position-independent absolute reference is a reference to the processor status word (PS)
from a relocatable instruction, as in this example.
MOV

@#PSW,RO

;RETRIEVE STATUS AND PLACE IN REGISTER

8-2

8.2.2 Comparison of Position-Dependent and Position-Independent Code
The RSX-ll library routine, PWRUP, is a FORTRAN-callable subroutine for establishing or removing a
user power failure asynchronous system trap (AST) entry point address. Imbedded within the routine is the
actual AST entry point that saves all registers, effects a call to the user-specified entry point, restores all
registers on return, and executes an AST exit directive. The following examples are excerpts from this
routine. The first example has been modified to illustrate position-dependent references. The second
example is the position-independent version.
Position-Dependent Code

PWRUP::
CLR
CALL

-(SP)
.x.PAA

.WORD

1.,$PSW

MOV

$OTSV,R4

MOV

(SP)+,R2

BNE

10$

CLR
BR

-(SP)
20$

MOV
MOV

R2,F.PF(R4)
#BA,-(SP)

;SET AST ENTRY POINT
;PUSH AST SERVICE
;ADDRESS

CALL
.BYTE

.x.EXT
109.,2.

;ISSUE DIRECTIVE, EXIT.

MOV
MOV
MOV

RO,-(SP)
R1,-(SP)
R2,-(SP)

;PUSH (SAVE) RO
;PUSH (SAVE) Rl
;PUSH (SAVE) R2

;ASSUME SUCCESS
;PUSH (SAVE)
;ARGUMENT ADDRESSES
;ONTO STACK
;CLEAR PSW, AND
;SET R1=R2SP
;GET OTS IMPURE
;AREA POINTER
;GET AST ENTRY
;POINT ADDRESS
;IF NONE SPECIFIED,
;SPECIFY NO POWER
;RECOVER Y AST SERVICE

10$:

20$:

BA:

8-3

Position-Independent Code

PWRUP::
CLR
CALL

-(SP)
.X.PAA

.WORD

1.,$PSW

MOV

@#$OTSV,R4

MOV

(SP)+,R2

BNE

10$

CLR
BR

-(SP)
20$

MOV
MOV
ADD

R2,F.PF(R4)
PC,-(SP)
#BA-.,(SP)

;SET AST ENTRY POINT
;PUSH CURRENT LOCATION
;COMPUTE ACTUAL LOCATION
;OF AST

CALL
.BYTE

.X.EXT
109.,2.

;ISSUE DIRECTIVE, EXIT .

;ASSUME SUCCESS
;PUSH ARGUMENT
;ADDRESSES ONTO
;STACK
;CLEAR PSW, AND
;SET Rl=R2-SP.
;GET OTS IMPURE
;AREA POINTER
;GET AST ENTRY
;POINT ADDRESS
;IF NONE SPECIFIED,
;SPECIFY NO POWER
;RECOVERY AST SERVICE

10$:

20$:

;ACTUAL AST SERVICE ROUTINE:
1)
; 2)
; 3)

; 4)
BA:

MOV
MOV
MOV

SA VE REGISTERS
EFFECT A CALL TO SPECIFIED
SUBROUTINE
RESTORE REGISTERS
ISSUE AST EXIT DIRECTIVE

;PUSH (SA VE) RO
;PUSH (SAVE) Rl
;PUSH (SAVE) R2

RO,-(SP)
RI,-(SP)
R2,-(SP)

The position-dependent version of the subroutine contains a relative reference to an absolute symbol
($OTSV) and a literal reference to a relocatable symbol (BA). Both references are bound by the task
builder to fixed memory locations. Therefore, the routine will not execute properly as part of a resident
library if its location in virtual memory is not the same as the location specified at link time.
In the position-independent version, the reference to $OTSV has been changed to an absolute reference. In
addition, the necessary code has been added to compute the virtual location of BA based upon the value of
the program counter. In this case, the value is obtained by adding the value of the program counter to the
fixed displacement between the current location and the specified symbol. Thus, execution of the modified
routine is not affected by its location in the image's virtual address space.

8-4

8.3 STACKS
The stack is part of the basic design architecture of the KDJlI-A. It is an area of memory set aside by the
programmer or the operating system for temporary storage and linkage. It is handled on a LIFO (lastin/first-out) basis, where items are retrieved in the reverse of the order in which they were stored. A stack
starts at the highest location reserved for it and expands linearly downward to lower addresses as items are
added.
It is not necessary to keep track of the actual locations into which data is being stacked. This is done
automatically through a stack pointer. To keep track of the last item added to the stack, a general register
is used to store the memory address of the last item in the stack. Any register except register 7 (the PC)
may be used as a stack pointer under program control; however, instructiens associated with subroutine
linkage and interrupt service automatically use register 6 as a hardware stack pointer. For this reason, R6
is frequently referred to as the system SP. Stacks may be maintained in either full-word or byte units. This
is true for a stack pointed to by any register except R6, which must be organized in full-word units only.
Byte stacks (see Figure 8-1) require instructions capable of operating on bytes rather than full words.

WORD STACK
007100
ITEM # 1
007076 t---'-IT~E~M"""'#~2=---t
007074
ITEM # 3
007072 1-----;"IT==E""M"""'#~4---I -

007072

007075

007070 t _ - - - - - - _ t
oo7~6t_------_t
007064
______
~

BYTE STACK
=:E:":"M:-#,,-1:----t
007100 t-----:cIT
007077
ITEM # 2
007076 t - - - : -IT
:O:;E=::M,,"",#i:-'3=---t
007075 t -_ _IT..;..;E:.,;;M;;,.;#::....4.;....._-t -

NOTE:
BYTES ARE
ARRANGED IN
WORDS AS FOLLOWING:
BYTE 3

WORD
MR--3662

Figure 8-1

Word and Byte Stacks

8-5

8.3.1 Pushing onto a Stack
Items are added to a stack using the autodecrement addressing mode. Adding items to the stack is called
pushing, and is accomplished by the following instructions.
MOV

Source,-(SP)

MOVB

Source,-(SP)

;MOV contents of source word
;onto the stack
or
;MOVB source byte onto
;the stack

Data is thus pushed onto the stack.

8.3.2 Popping from a Stack
Removing data from the stack is called popping. This operation is accomplished using the autoincrement
mode.
MOV

(SP)+,Destination

MOVB

(SP)+,Destination

;MOV destination word
;off the stack
or
;MOVB destination byte
;off the stack

After an item has been popped, its stack location is considered free and available for other use. The stack
pointer points to the last-used location, implying that the next lower location is free. Thus, a stack may
represent a pool of sharable temporary storage locations. (See Figure 8-2.)

HIGH MEMORY

~-}S~ACKt~-SP ~
~

AREA

t~_SP

LOW MEMORY
1 AN EMPTY STACK AREA

2 PUSHING A DATUM
ONTO THE STACK

3 PUSHING ANOTHER
DATUM ONTO THE
STACKS

o
,;tE2~O
~
t
t~-~
El

4 ANOTHER PUSH

-SP

5 POP

El
E3

_SP

6 PUSH

EO
El

_SP

7 POP
MR-3663

Figure 8-2

Push and Pop Operations

8-6

8.3.3 Deleting Items from a Stack
The following techniques may be used to delete items from a stack. To delete one item use:
INC SP or TSTB(SP)+ for a byte stack
To delete two items use:
ADD#2,SP or TST(SP)+ for word stack
To delete 50 items from a word stack use:
ADD# 1OO.,SP

8.3.4 Stack Uses
A stack is used in the following ways.
I.

Often one of the general-purpose registers must be used in a subroutine or interrupt service
routine and then returned to its original value. The stack can be used to store the contents of the
registers involved.

The stack is used in storing linkage information between a subroutine and its calling program.
The JSR instruction, used in calling a subroutine, requires the specification of a linkage register
along with the entry address of the subroutine. The content of this linkage register is stored on
the stack, so as not to be lost, and the return address is moved from the PC to the linkage
register. This provides a pointer back to the calling program so that successive arguments may
be transmitted easily to the subroutine.

If no arguments need be passed by stacking them after the JSR instruction, the PC may be used
as the linkage register. In this case, the result of the JSR is to move the return address in the
calling program from the PC onto the stack and replace it with the entry address of the called
subroutine.

In many cases, the operations performed by the subroutine can be applied directly to the data
located on or pointed to by a stack without the need to move the data into the subroutine area.
Example:
MOV SP,Rl
JSR PC,SUBR
ADD

(RI)+,(Rl)

;CALLING PROGRAM
;Rl IS USED AS THE STACK
;POINTER HERE.
;SUBROUTINE
;ADD ITEM # 1 TO #2, PLACE
;RESULT IN ITEM #2,
;Rl POINTS TO
;ITEM #2 NOW

Because the hardware already uses general-purpose register R6 to point to a stack for saving
and restoring PC and processor status word (PS) information, it is convenient to use the same
stack to save and restore immediate results and to transmit arguments to and from subroutines.
Using R6 in this manner permits extreme flexibility in nesting subroutines and interrupt service
routines.

8-7

Since arguments may be obtained from the stack by using some form of register-indexed
addressing, it is sometimes useful to save a temporary copy of R6 in some other register which
has been saved at the beginning of a subroutine. If R6 is saved in R5 at the beginning of the
subroutine, R5 may be used to index the arguments. During this time, R6 is free to be
incremented and decremented while being used as a stack pointer. If R6 had been used directly
as the base for indexing and not "copied," it might be difficult to keep track of the position in
the argument list, since the base of the stack would change with every autoincrement/decrement that occurred.
However, if the contents of R6 (SP) are saved in R5 before any arguments are pushed onto the
stack, the position relative to R5 would remain constant.
Return from a subroutine also involves the stack, as the return instruction, RTS, must retrieve
information stored there by the JSR.
When a subroutine returns, it is necessary to "clean up" the stack by eliminating or skipping
over the subroutine arguments. One way this can be done is by insisting that the subroutine keep
the number of arguments as its first stack item. Returns from subroutines then involve calculating the amount by which to reset the stack pointer, resetting the stack pointer, then storing the
original contents of the register that were used as the copy of the stack pointer.
5.

Stack storage is used in trap and interrupt linkage. The program counter and the processor
status word of the executing program are pushed on the stack.

When the system stack is being used, nesting of subroutines, interrupts, and traps to any level
can occur until the stack overflows its legal limits.

The stack method is also available for temporary storage of any kind of data. It may be used as
a LIFO list for storing inputs, intermediate results, etc.

8.3.5 Stack Use Examples
As an example of stack use, consider this situation. A subroutine (SUBR) wants to use registers 1 and 2,
but these registers must be returned to the calling program with their contents unchanged. The subroutine
could be written as follows.
Not Using the Stack
Address

Octal Code

076322
076324
076326
076330

010167 SUBR:
000074
010267
000072

076410
076412
076414
076416
076420
076422
076424

016701
000006
016702
000004
000207
000000
000000

Assembler
Syntax

Comments

MOV Rl,TEMPl

;save Rl

MOV R2,TEMP2

*
MOV TEMP1,Rl

MOV TEMP2,R2

RTSPC
TEMP1:0
TEMP2:0

*Index constants

8-8
-------

;save R2

;restore Rl
;restore R2

U sing the Stack
R3 has been previously set to point to the end of an unused block of memory.

Address

Octal Code

Assembler
Syntax

Comments

010020
010022

010143 SUBR:
010243

MOV R1,-(R3)
MOV R2,-(R3)

;push Rl
;push R2

010130
010132
010134

012302
012301
000207

MOV (R3)+,R2
MOV (R3)+,Rl
RTSPC

;pop R2
;pop R1

Note: In this case R3 was used as a stack pointer.

The second routine uses four fewer words of instruction code and two words of temporary "stack" storage.
Another routine could use the same stack space at some later point. Thus, the ability to share temporary
storage in the form of a stack is a way to save on memory usage.
As another example of stack use, consider the task of managing an input buffer from a terminal. As
characters come in, the user may wish to delete characters from the line; this is accomplished very easily
by maintaining a byte stack containing the input characters. Whenever a backspace is received, a
character is popped off the stack and eliminated from consideration. In this example, popping characters
to be eliminated can be done by using either the MOVB (MOVE BYTE) or INC (INCREMENT)
instructions.
Note that in this case the increment instruction (INC) is preferable to MOVB, since it accomplishes the
task of eliminating the unwanted character from the stack by readjusting the stack pointer without the
need for a destination location. Also, the stack pointer (SP) used in this example cannot be the system
stack pointer because R6 may point only to word (even) locations. (See Figure 8-3.)

001011
001010
001007
001006
001005
001004
001003
001002
001001

C
U

u
S

INC R3

T
0

0
M

E
R
Z

E
R

4-R31

Figure 8-3

4-R31

001001

Byte Stack Used as a Character Buffer

8-9

001002

8.3.6 Subroutine Linkage
The contents of the linkage register are saved on the system stack when a JSR is executed. The effect is
the same as if a MOV reg,-(R6) had been performed. Following the JSR instruction, the same register is
loaded with the memory address (the contents of the current PC), and a jump is made to the entry location
specified.
Figure 8-4 shows the conditions before and after the subroutine instruction JSR R5, 1064 is executed.
Because hardware already uses general-purpose register R6 to point to a stack for saving and restoring PC
and PS (processor status word) information, it is convenient to use that stack to save and restore
intermediate results and to transmit arguments to and from subroutines. Using R6 this way permits
nesting subroutines and interrupt service routines.

BEFORE

AFTER

(R5) = 000132

(R5) = 001004

(R6) =001776
(PC) = (R7) = 001000

(PC) = (R71 = 001064

(R6) = 001774

nnnnnn
002000
001776 t---m--m--m--mm--m----I ... SP
001774
001772 ~-----I

002000

001776

nnnnnn
mmmmmm
000132
+-spi
001772 ~_ _ _--I
001776
001774

001774

MR-3666

Figure 8-4 JSR Stack Condition Example

8.3.6.1 Return from a Subroutine - An RTS instruction provides for a return from the subroutine to the
calling program. The R TS instruction must specify the same register as the one the JSR instruction used in
the subroutine call. When the R TS is executed, the register specified is moved to the PC, and the top of
the stack is placed in the register specified. Thus, an RTS PC has the effect of returning to the address
specified on the top of the stack.
8.3.6.2 Subroutine Advantages - There are several advantages to the subroutine calling procedure
affected by the JSR instruction.
I.

Arguments can be passed quickly between the calling program and the subroutine.

If there are no arguments, or the arguments are in a general register or on the stack, the JSR
PC,DST mode can be used so that none of the general-purpose registers are used for linkage.

Many JSRs can be executed without the need to provide any saving procedure for the linkage
information, since all linkage information is automatically pushed onto the stack in sequential
order. Returns can be made by automatically popping this information from the stack in the
order opposite to the JSRs.

Such linkage address bookkeeping is called automatic nesting of subroutine calls. This feature enables
construction of fast, efficient linkages in a simple, flexible manner. It also permits a routine to call itself.

8-10

8.3.7 Interrupts
An interrupt is similar to a subroutine call, except that it is initiated by the hardware rather than by the
software. An interrupt can occur after the execution of an instruction.
Interrupt-driven techniques are used to reduce CPU waiting time. In direct program data transfer, the
CPU loops to check the state of the DONE/READY flag (bit 7) in the peripheral interface. Using
interrupts, the CPU can handle other functions until the peripheral initiates service by setting the DONE
bit in its control/status register. The CPU completes the instruction being executed, then acknowledges
the interrupt, and vectors to an interrupt service routine. The service routine will transfer the data and may
perform calculations with it. After the interrupt service routine has been completed, the computer resumes
the program that was interrupted by the peripheral's high-priority request.

8.3.7.1 Interrupt Service Routines - With interrupt service routines, linkage information is passed so
that a return to the main program can be made. More information is necessary for an interrupt sequence
than for a subroutine call because of the random nature of interrupts. The complete machine state of the
program immediately prior to the occurrence of the interrupt must be preserved in order to return to the
program without any noticeable effects. This information is stored in the processor status word (PS). Upon
interrupt, the contents of the program counter (PC) (address of next instruction) and the PS are automatically pushed onto the R6 system stack. The effect is the same as if:
MaY PS,-(SP)
MaY PC,-(SP)

;Push PS
;Push PC

had been executed. The new contents of the PC and PS are loaded from two preassigned consecutive
memory locations which are called vector addresses.
The first word contains the interrupt service routine entry address (the address of the service routine
program sequence). The second word contains the new PS that will determine the machine status,
including the operational mode and register set to be used by the interrupt service routine. The contents of
the vector address are set under program control.
After the interrupt service routine has been completed, an RTI (return from interrupt) is performed. The
top two words of the stack are automatiCally popped and placed in the PC and PS, respectively, thus
resuming the interrupted program. Interrupt service programming is intimately involved with the concept
of CPU and device priority levels.

8.3.7.2 Nesting - Interrupts can be nested in much the same manner that subroutines are nested. It is
possible to nest any arbitrary mixture of subroutines and interrupts without any confusion. When the
respective RTI and RTS instructions are used, the proper returns are automatic. (See Figure 8-5.)

8-11

PROCESS IS RUNNING; SP IS
POINTING TO LOCATION PO.

SUBROUTINE A RELEASES THE TEMPORARY STORAGE HOLDING TA 1 AND
TA2.

INTERRUPT STOPS PROCESS WITH
PO ~
PC = PCO, AND STATUS = PSO, STARTS
pso
PROCESS 1.
SP pco

sp_

PSO
PCO
TEO
TEl
PSl
PCl
PC2

o
3.

PROCESS 1 USES STACK FOR TEMPORARY STORAGE (TEO, TE 1 )

PO I---p""so::-----I

SP_

PCO
TEO
TEl

SUBROUTINE A RETURNS CONTROL
TO PROCESS 2 WITH AN RTS R7; PC IS
RESET TO PC2.

SP_

PROCESS 1 INTERRUPTED WITH PC =
PCl AND STATUS = PS1; PROCESS 2
IS STARTED.

PSO
PCO
TEO
TEl
PSl
PCl

SP_

PSO
PCO
TEO
TEl
PSl
PCl

PROCESS 2 COMPLETES WITH AN RTI
INSTRUCTION (DISMISSES INTERRUPT); PC IS RESET TO PCl AND
STATUS IS RESET TO PS 1; PROCESS
1 RESUMES.

PO I----;::~__I
PSO

pco
TEO
SP_t--_TE
......l _ - t

a
5.

PROCESS 2 IS RUNNING AND DOES A
JSR R7, A TO SUBROUTINE A WITH
PC = PC2.

SP_

SUBROUTINE A IS RUNNING AND
USES STACK FOR TEMPORARY
STORAGE.

PSO
PCO
TEO
TEl
PSl
PCl
PC2

10. PROCESS 1 RELEASES TH E TEMPORARY STORAGE HOLDING TEO AND
TEl.

PO~
PSO

SP--:

PCO

11. PROCESS 1 COMPLETES ITS OPERA- S P _ PO ~
TION WITH AN RTI, PC IS RESET TO
PCO, ANDF STATUS IS RESET TO PS~.
0

SP_

PSO
PCO
TEO
TEl
PSl
PCl
PC2
TAl
TA2

Figure 8-5

8.3.8

Nested Interrupt Service Routines and Subroutines

Reentrancy

Other advantages of the KDJII-A stack organization occur in programming systems that handle several
tasks. Multitask program environments range from simple single-user applications that manage a mixture
of I/O interrupt service and background data processing (as in RT-ll), to large, complex, multiprogramming systems that manage an intricate mixture of executive and multiuser programming situations (as in
RSX-ll). In all these situations, using the stack as a programming technique provides flexibility and
time/memory economy by allowing many tasks to use a single copy of the same routine with a simple
straightforward way of keeping track of complex program linkages.
The ability to share a single copy of a program among users or among tasks is called reentrancy. Reentrant
program routines differ from ordinary subroutines in that it is not necessary for reentrant routines to finish
processing a given task before they can be used by another task. Multiple tasks can exist at any time in
varying stages of completion in the same routine. Thus, the situation as shown in Figure 8-6 may occur.

8-12

MEMORY

MEMORY
PROGRAM 1
PROGRAM 2
PROGRAM 3

PROGRAM 1
SUBROUTINE

A
PROGRAM 2

PROGRAM 3

KDJ 11 -A APPROACH

CONVENTIONAL APPROACH

PROGRAMS 1,2, AND 3 CAN
SHARE SUBROUTINE A.

ASEPARATECOPYOFSUBROUTINEAMUST
BE PROVIDED FOR EACH PROGRAM.
MR-3667

Figure 8-6

Reentrant Routines

8.3.8.1 Reentrant Code - Reentrant routines must be written in pure code (that is, any code that consists
exclusively of instructions and constants). The value of using pure code whenever possible is that the
resulting code has the following characteristics.

1.
2.

It is generally considered easier to debug than standard code.
It can be kept in read-only memory (is read-only protected).

Using reentrant code, control of a routine can be shared as follows. (See Figure 8-7.)
1.
2.
3.
4.
5.

Task A requests processing by reentrant routine Q.
Task A temporarily gives up control of reentrant routine Q before it completes processing.
Task B starts processing the same copy of reentrant routine Q.
Task B completes processing by reentrant routine Q.
Task A regains use of reentrant routine Q and resumes where it stopped.

REENTRANT
ROUTINE Q

MR-3668

Figure 8-7

Sharing Control of a Routine

8-13

8.3.8.2 Writing Reentrant Code - In an operating system environment, when one task is executing and is
interrupted to allow another task to run, a context switch occurs in which the processor status word and
current contents of the general-purpose registers (GPRs) are saved and replaced by the appropriate values
for the task being entered. Therefore, reentrant code should use the GPRs and the stack for any counters,
pointers, or data that must be modified or manipulated in the routine.
The context switch occurs whenever a new task is allowed to execute. It causes all of the GPRs, the PS,
and often other task-related information to be saved in an impure area. It then reloads these registers and
locations with the appropriate data for the task being entered. Notice that one consequence of this is that a
new stack pointer value is loaded into R6, thereby causing a new area to be used as the stack when the
second task is entered.
The following should be observed when writing reentrant code.
1.

All data should be in or pointed to by one of the general-purpose registers.

A stack can be used for temporary storage of data or pointers to impure areas within the task
space. The pointer to such a stack would be stored in a GPR.

Parameter addresses should be used by indexing and indirect reference rather than by putting
them into instructions within the code.

When temporary storage is accessed within the program, it should be by indexed addresses,
which can be set by the calling task in order to handle any possible recursion.

8.3.9 Coroutines
In some programming situations it happens that several program segments or routines are highly interactive. Control is passed back and forth between the routines, each going through a period of suspension
before being resumed. Since the routines maintain a symmetric relationship with each other, they are
called coroutines.
Coroutines are two program sections, either subordinate to the call of the other. The nature of the call is,
"I have processed all I can for now, so you can execute until you are ready to stop, then I will continue."
The coroutine call and return are identical, each being a jump to subroutine instruction with the destination address being on top of the stack and the PC serving as the linkage register, as follows.
JSR PC,@(R6)+

8-14

8.3.9.1 Coroutine Calls - The coding of coroutine calls is made simple by the stack feature. Initially, the
entry address of the coroutine is placed on the stack, and from that point the
JSR PC,@(R6)+
instruction is used for both the call and the return statements. This JSR instruction results in an exchange
of the contents of the PC and the top element of the stack; this permits the two routines to swap control
and resume operation where each was terminated by the previous swap. An example is shown in Figure
8-8. Notice that the coroutine linkage cleans up the stack with each control transfer.

ROUTINE A

MOV #LOC,-(SP)

STACK

LOC

ROUTINEB

COMMENTS
LOC IS PUSHED
ONTO THE STACK
TO PREPARE FOR
THE COROUTINE
CALL.

<-SP

LOC:
JSR PC,@(SP)+
(PCO)

PCO

<-sP

PCl

JSR PC,@(SP)+
(PC1)

WHEN THE CALL
IS EXECUTED,
THE PC FROM
ROUTINE A IS
PUSHED ON THE
STACK AND EXECUTION CONTINUESAT LOC.
ROUTINE B CAN
RETURN CONTROL
TO ROUTINE A
BY ANOTHER
COROUTINE CALL.
PCO IS POPPED
FROM THE STACK
AND EXECUTION
RESUMES IN
ROUTINE A JUST
AFTER THE CALL
TO ROUTINE B,
I.E., AT PCO.
PCllSSAVED
ON THE STACK
FOR A LATER
RETURN TO
ROUTINE B.
MR-3669

Figure 8-8

Coroutine Example

8-15

8.3.9.2 Coroutines Versus Subroutines - Coroutines can be compared to subroutines in the following
ways.
I.

A subroutine can be considered to be subordinate to the main or calling routine, but a coroutine
is considered to be on the same level, as each coroutine calls the other when it has completed
current processing.

When called, a subroutine executes to the end of its code. When called again, the same code will
execute before returning. A coroutine executes from the point after the last call of the other
coroutine. Therefore, the same code will not be executed each time the coroutine is called. An
example is shown in Figure 8-9.

The call and return instructions for coroutines are the same:
JSR PC,@(SP)+
This one instruction also cleans up the stack with each call. The last coroutine call will leave an
address on the stack that must be popped if no further calls are to be made. Refer to Paragraph
8.3.6.1 for information on the return from subroutine instruction.

Each coroutine call returns to the coroutine code at the point after the last exit with no need for
a specific entry point label, as would be required with subroutines.

COROUTINES

MAIN PROGRAMS

~Rl~l+

>
~,e'~I+
~R~,"~I+
j
1

SUBROUTINES

JSA

RTS

JSR Rn, LOC

JSA PC",SPI'

MA-3870

Figure 8-9 Coroutines Versus Subroutines

8-16

8.3.9.3

Using Coroutines - Coroutines should be used in the following situations.

Whenever two tasks must be coordinated in their execution without obscuring the basic structure of the program. For example, in decoding a line of assembly language code, the results at
anyone position might indicate the next process to be entered. A detected label must be
processed. If no label is present, the operator must be located, etc.

To add clarity to the process being performed, to ease-in the debugging phase, etc.

An assembler must perform a lexicographic scan of each assembly language statement during pass 1 of the
assembly process. The various steps in such a scan should be separated from the main program flow to add
to the program's clarity and to aid in debugging by isolating many details. Subroutines would not be
satisfactory here, as too much information would have to be passed to the subroutine each time it was
called. Such a subroutine would be too isolated. Coroutines could be effectively used here with one routine
being the assembly pass 1 routine and the other extracting one item at a time from the current input line.
Figure 8-10 illustrates this example.

ROUTINE A

ROUTINE B

END
MR-3611

Figure 8-10 Coroutine Path

8-17

Coroutines can be utilized in I/O processing. The example above shows coroutines used in double-buffered
I/O using lOX. The flow of events might be described as:
Write 01
Read 11
Process 12

concurrently,

Write 02
Read 12
Process II

concurrently,

then

Figure 8-11 illustrates a coroutine swapping interaction.
When routine 1 is operating; it executes:
MOY #PC2,-(R6)
JSR PC,@(R6)+
with the following results.
1.

PC2 is popped from the stack and the SP autoincremented.

SP is autodecremented and the old PC (i.e., PCl) is pushed.

Control is tranferred to the location PC2 (i.e., routine 2).

When routine 2 is operating; it executes:
JSR PC,@(R6)+
with the result that PC2 is exchanged for PCI on the stack and control is transferred back to routine 1.
ROUTINE #1 IS OPERATING, IT THEN
EXECUTES:
MOV #PC2,-( R6)
JSR PC,@(R6)+
WITH THE FOLLOWING RESULTS:
1.

PC2 IS POPPED FROM THE STACK
AND THE SP AU10INCREMENTED.

SP IS AUTODECREMENTED AND
THE OLD PC (I.E., PC1) IS PUSHED.

CONTROL IS TRANSFERRED TO THE
LOCATION PC2 (I.E., ROUTINE #2).

ROUTINE #2 IS OPERATING, IT THEN
EXECUTES:
JSR PC,@(R6)+
WITH THE RESULT THAT PC2 IS
EXCHANGED FOR PC1 ON THE
STACK AND CONTROL IS
TRANSFERRED BACK TO ROUTINE #1.

SP_

PC2

~
~

SP_

PC1

MA-3672

Figure 8-11

Coroutine Interaction

8-18

8.3.10 Recursion
An interesting aspect of a stack facility, other than its providing for automatic handling of nested
subroutines and interrupts, is that a program may call on itself as a subroutine just as it can call on any
other routine. Each new call causes the return linkage to be placed on the stack, which, as it is a lastin/first-out queue, sets up a natural unraveling to each routine just after the point of departure. Typical
flow for a recursive routine might resemble that shown in Figure 8-12.

MR·3673

Figure 8-12

Recursive Routine Flow

The main program calls function 1, SUB 1, which calls function 2, SUB 2, which recurses once before
returning.
Example:
DNCF:

,
BEQ 1$
JSR R5,DNCF

;TO EXIT RECURSIVE LOOP
;RECURSE

,
RTS R5

;RETURN TO 1$ FOR
;EACH CALL, THEN TO
;MAIN PROGRAM

The routine DNCF calls itself until the variable tested becomes equal to 0, then it exits to 1$ where the
RTS instruction is executed, returning to the 1$ once for each recursive call and a final time to return to
the main program.
In general, recursion techniques will lead to slower programs than the corresponding interactive techniques, but recursion will produce shorter programs, and thus save memory space. Both the brevity and
clarity produced by recursion are important in assembly language programs.

8-19

Uses of Recursion - Recursion can be used in any routine in which the same process is required several
times. For example, a function to be integrated may contain another function to be integrated, as in
solving for XM, where
SM = 1 + F(X)
and
F(X) = G(X)
Another use for a recursive function could be in calculating a factorial function, because
FACT(N) = FACT(N - 1) * N
Recursion should terminate when N = 1.
The macroprocessor within MACRO-II, for example, is itself recursive since it can process nested
macrodefinitions and calls. For example, within a macrodefinition, other macros can be called. When a
macro call is encountered within definition, the processor must work recursively; that is, it must process
one macro before it is finished with another, then continue with the previous one. The stack is used for a
separate storage area for the variables associated with each call to the procedure.
As long as nested definitions of macros are available, it is possible for a macro to call itself. However,
unless conditionals are used to terminate this expansion, an infinite loop could be generated.

8.3.11 Processor Traps
Certain errors and programming conditions cause the KDJ11-A processor to enter the service state and
trap to a fixed location. A trap is an interrupt generated by hardware. Pending conditions are arbitrated
according to a priority. The following list describes the priority from highest to lowest.
Condition

Description

Memory Management Violation*
(MMUERR)

A memory management violation causes an abort and
traps to location 2508.

Timeout Error* (BUSERR)

No response from a bus device during a bus transaction
causes an abort and traps to location 48.

Parity Error* (PARERR)

A parity error signal received by the processor during a
bus transaction causes an abort and traps to location 1148.

Trace (T) Bit*

If PS bit 4 is set at the end of instruction execution, the
processor traps to location 148.

Stack Overflow* (STKOVF)

If the kernel stack pointer was pushed below 4008 during
an instruction execution, the processor traps to location 48
at the end of the instruction.

Power Fail* (PFAIL)

If bus signal power OK (BPOKH) became negated during
instruction execution, the processor traps to location 248
at the end of the instruction.

Nonmaskable software cannot inhibit the condition. MMUERR, BUSERR, P ARERR are mutually exclusive when the
processor is executing a program.

8-20

Condition

Description

Interrupt Level 7 (BIRQ7)
Interrupt Level 6 (BIRQ6)
Interrupt Level 5 (BIRQ5)
Interrupt Level 4 (BIRQ4)

If device interrupt requests are asserted and PS<07:05>

are properly set, the processor at the end of the present
instruction execution will initiate an interrupt vector
sequenced on the bus. These inputs are maskable by
PS<07:05>.
PS<07:05>

Levels Inhibited

7
5

All
6, 5, 4
5,4

0-3

None

Halt Line

If the BHALT L bus signal is asserted during the service

state, the processor will enter ODT mode.
8.3.11.1 Trap Instructions - Trap instructions provide for calls to emulators, I/O monitors, debugging
packages, and user-defined interpreters. When a trap occurs, the contents of the current program counter
(PC) and program status word (PS) are pushed onto the processor stack and replaced by the contents of a
2-word trap vector containing a new PC and new PS. The return sequence from a trap involves executing
an RTI or RTT instruction, which restores the old PC and old PS by popping them from the stack. Trap
vectors are located at permanently assigned fixed addresses.
The EMT (trap emulator) and TRAP instructions do not use the low-order byte of the word in their
machine language representation. This allows user information to be transferred in the low-order byte. The
new value of the PC loaded from the vector address of the TRAP or EMT instructions is typically the
starting address of a routine to access and interpret this information. Such a routine is called a trap
handler.
A trap handler must accomplish several tasks. It must save and restore all necessary GPRs, interpret the
low byte of the trap instruction and call the indicated routine, serve as an interface between the calling
program and this routine by handling any data that needs to be passed between them, and, finally, cause
the return to the main routine.
A trap handler can be useful as a patching technique. Jumping out to a patch area is often difficult
because a 2-word jump must be performed. However, the I-word TRAP instruction may be used to
dispatch to patch areas. A sufficient number of slots for patching should first be reserved in the dispatch
table of the trap handler. The jump can then be accomplished by placing the address of the patch area into
the table and inserting the proper TRAP instruction where the patch is to be made.

8-21

8.3.11.2 Use of Macro Calls - The trap handler can be used in a program to dispatch execution to any
one of several routines. Macros may be defined to cause the proper expansion of a call to one of these
routines, as in the example below .
.MACRO SUB2 ARG
MOY ARG, RO
TRAP +1
.ENDM
When expanded, this macro sets up the one argument required by the routine in RO and then causes the
trap instruction with the number 1 in the lower byte. The trap handler should be written so that it
recognizes a 1 as a call to SUB2. Notice that ARG here is being transmitted to SUB2 from the calling
program. It may be data required by the routine or it may be a pointer to a longer list of arguments.
In an operating system environment like R T -II, the EMT instruction is used to call system or monitor
routines from a user program. The monitor of an operating system necessarily contains coding for many
functions, such as I/O, file manipulation, etc. This coding is made accessible to the program through a
series of macro calls that expand into EMT instructions with low bytes, indicating the desired routine or
group of routines to which the desired routine belongs. Often a GPR is designated to be used to pass an
identification code to further indicate to the trap handler which routine is desired. For example, the macro
expansion for a resume execution command in RT-il is as follows .
.MACRO .RSUM
CM3,2 .
.ENDM
CM3 is defined:
.MACRO CM3 CHAN, CODE.
MOY #CODE *400,RO
.IIF NB
CHAN,BISB CHAN,RO
EMT 374
.ENDM
Note that the EMT low byte is 374. This is interpreted by the EMT handler to indicate a group of
routines. Then the contents of RO (high byte) are tested by the handler to identify exactly which routine
within the group is being requested - in this case routine number 2. (The CM3 call of the .RSUM is set up
to pass the identification code.)
8.3.12 Conversion Routines
Almost all assembly language programs require the translation of data or results from one form to another.
Code that performs such a transformation is called a conversion routine in this guide. Several commonly
used conversion routines follow.
Almost all assembly language programs involve some type of conversion routine. Octal-to-ASCII, octal-todecimal, and decimal-to-ASCII are a few of the most widely used.

8-22

Arithmetic multiply and divide routines are fundamental to many conversion routines. Division is typically
approached in one of two ways.
1.

The division can be accomplished through a combination of rotates and subtractions.
Example:
Assume the following code and register data; to make the example easier, also assume a 3-bit
word.
DIY:
1$

MOY #3,-(SP)
CLR -(SP)
ASL (SP)
ASL R1
ROLRO
CMP RO,R3
BLT 2$
SUB R3,RO
INC (SP)
DEC 2 (SP)
BNE $1

;SET UP DIGIT COUNTER
;CLEAR RESULT

;RO CONTAINS REMAINDER
;INCREMENT RESULT
;DECREMENT COUNTER

Therefore, to divide 7 by 2:
RO = 000
R1=111
R3 = 010
C bit = a

remainder
7 (multiplicand)
2 (multiplier)

STACK
011
000

counter
quotient

Following through the coding, the quotient, remainder, and dividend all shift left, manipulating
the most significant digit first, etc.
At the conclusion of the routine:
RO = 001
R1 = 000
R3 = 010

remainder

STACK
000
011

counter
quotient

8-23

The second method of division works by repeated subtraction of the powers of the divisor,
keeping a count of the number of subtractions at each level.
Example:
To divide 221 IO by 10, first try to subtract powers of 10 until a nonnegative value is obtained,
counting the number of subtractions of each power.
221
-1000
Negative, so go to the next lower power, and count for 103 = o.
221
-100
121
-100

count for 102 = 1

21
-100

count = 2

Negative, so reduce power, and count for 102 = 2.
21
-10
11

count for 10 1 = 1.

11
-10
1
-10

count = 2

Negative, so count for 10 1 = 2.
No lower power, so remainder is 1.
Answer = 022, remainder 1.

8-24

Multiplication can be done with a combination of rotates and additions or with repetitive additions.
Example:
Assume the following code and a 3-bit word.
CLR RO
MOV #3,CNT
MOV R1,MULT;

;HIGH HALF OF ANSWER
;SET UP COUNTER
;MULTIPLICAND

ROR R2
BCC NOW
ADD MULT,RO ;IF INDICATED,

ADD
;MULTIPLICAND
RORRO
R04 Rl
DEC CNT
BNE MORE

NOW;

o
o

MULT:
CNT:
The following conditions exist for 6 times 3:
RO = 000
R1=l1O
R3 = 011

high-order half of result
multiplicand
multiplier

After the routine is executed:
RO = 010
R 1 = 010
R2 = 100
CNT=O
MULT = 110

high-order half of result
low-order half of result

Example:
Multiplication of RO by 508(101000).
MUL50:

MOV RO,-(SP)
ASLRO
ASLRO
ADD (SP)+,RO
ASLRO
ASLRO
ASLRO
RETURN

If RO contains 7:
RO = 111
After execution:
RO = 100011000
(78 * 508 = 4308).
8-25

ASCII Conversions - The conversion of ASCII characters to the internal representation of a number, as
well as the conversion of an internal number to ASCII in I/O operations, presents a challenge. The
following routine takes the 16-bit word in R 1 and stores the corresponding six ASCII characters in the
buffer addressed by R2.
OUT:
LOOP:

MOV
MOV
BIC
ADD
MOVB
ASR
ASR
ASR
DEC
BNE
BIC
ADD
MOVB
RTS

;LOOP COUNT
;COPY WORD INTO STACK
;ONE OCTAL VALUE
;CONVERT TO ASCII
;STORE IN BUFFER
;SHIFT
;RIGHT
;THREE
;TEST IF DONE
;NO, DO IT AGAIN
;GET LAST BIT
;CONVERT TO ASCII
;STORE IN BUFFER
;DONE,RETURN

#5,RO
R1,-(SP)
# 177770,@SP
#'O,@SP
(SP)+,-(R2)
Rl
Rl
Rl
RO
LOOP
#177776,RI
#'O,Rl
R5,-(R2)
PC

8.4 PROGRAMMING THE PROCESSOR STATUS WORD
The current processor status can be read and written using several programming techniques on the PS. The
PS has an I/O address of 17777776. The KDJII-A and other PDP-II processors implement this address,
whereas LSI-II and LSI-11/2 processors do not. One technique is to use the 1/0 address as a source or
destination address with any instruction.
CLR @#17777776
MOV @#I7777776, RO
The first instruction clears the PS and the second instruction moves the contents of the PS to general
register RO.
The PS explicit address (17777776) can be accessed on a word or byte basis. The KDJII-A will recognize
the PS odd address (17777777) and the access result will be identical to an odd memory address reference.
Another technique is to use the two dedicated PS instructions, MTPS and MFPS. These instructions only
reference the even byte. If memory management is enabled certain PS bits are protected.

8-26

8.S PROGRAMMING PERIPHERALS
Programming LSI-II bus-compatible modules (devices) is simple. A special class of instructions that deals
with input/output operations is unnecessary. The bus structure permits a unified addressing structure in
which control, status, and data registers for devices are directly addressed as memory locations. Therefore,
all operations on these registers, such as tranferring information into or out of them or manipulating data
within them, are performed by normal memory reference instructions.
The use of all memory reference instructions on device registers greatly increases the flexibility of
input/output programming. For example, information in a device register can be compared directly with a
value and a branch made on the result.
CMP RBUF,
BEQ SERVICE

#101

In this case, the program looks for WI in the DLVl1 receiver data buffer register (RBUF) and branches if
it finds it. There is no need to transfer the information into an intermediate register for comparison.
When the character is of interest, a memory reference instruction can transfer the character into a user
buffer in memory or to another peripheral device. The instruction:
MOV DRINBUF LOC
transfers a character from the DRVII data input buffer (DRINBUF) into a user-defined location.
All arithmetic operations can be performed on a peripheral device register. For example, the instruction
ADD #10, DROUT BUF will add 10 to the DRVll's output buffer. All read/write device registers can be
treated as accumulators. There is no need to funnel all data transfers, arithmetic operations, and comparisons through one or a small number of accumulator registers.
8.6 PDP-11 PROGRAMMING EXAMPLES
The programming examples on the following pages show how the instruction set, the addressing modes,
and the programming techniques can be used to solve some simple problems. The format used is
MACRO-ll.

8-27

Program
Address

Program
Contents

Label

Op Code

Operand

Comments
;PROGRAMMING EXAMPLE
;SUBTRACT CONTENTS OF LOCS 700-710
;FROM CONTENTS OF LOCS 1000-1010

000000
000001
000002
000003
000004
000005
000006
000007

RO=%O
Rl=%1
R2=%2
R3=%3
R4=%4
R5=%5
SP=%6
PC=%7

000524
000526
000430
000532
000534
000536
000540
000542

000500
012706
000500
012701
000700
012702
000712
012703
001000
012704
001012
005000
005005
062105
020102
001375
062300
020304
001375

000544

160500

000546

000000

HALT

000700
000702
000704
000706
000710

000700
000001
000002
000003
000004
000005

=700
WORD 1,2,3,4,5

001000
001002
001004
001006
001010

001000
000004
000005
000006
000007
000010

=1000
WORD 4,5,6,7,8

000500

END

000500
000504
000510
000514
000520

START:

SUM1:
SUM2:

DIFF:

.=500
MaY

#.,SP

MaY

#700,Rl

MaY

#712,R2

MaY

#1000,R3

MaY

#1012,R4

CLR
CLR
ADD
CMP
BNE
ADD
CMP
BNE

RO
R5
(Rl)+,R5
Rl,R2
SUMl
(R3)+,RO
R3,R4
SUM2

;START ADDING
;FINISHED ADDING?
;IF NOT BRANCH BACK
;START ADDING
;FINISHED ADDING?
;IF NOT BRANCH BACK

SUB

R5,RO

;SUBTRACT RESULTS

;INIT STACK POINTER

;THAT'S ALL FOLKS

8-28

Program
Address

Program
Contents

Label

Op Code

Operand

Comments
;PROGRAM TO COUNT NEGATIVE
NUMBERS
;IN A TABLE
;20. SIGNED WORDS
;BEGINNING AT LOC VALUES
;COUNT HOW MANY ARE NEGATIVE IN RO

RO=%O
Rl=%l
R2=%2
SP=%6
PC=%7

.=500
START:

MOV#.,SP
MOV #VALUE,Rl
MOV #V ALUES+40.,R2
CLRRO

;SET UP STACK
;SET UP POINTER
;SET UP COUNTER

CHECK:
BPL NEXT
INC RO

TST(Rl~

;TEST NUMBER
;POSITIVE?
;NO, INCREMENT
;COUNTER
;YES, FINISHED?
;NO, GO BACK
;YES, STOP

NEXT:
CMP Rl,R2
BNECHECK
HALT
VALUES:
.END

8-29

Program
Address

Program
Contents

Label

Op Code

Operand

Comments
;PROGRAM TO COUNT ABOVE AVERAGE
QUIZ SCORES
;LIST OF 16. QUIZ SCORES
;BEGINNING AT LOC SCORES
;KNOWN AVERAGE IN LOC AVERAGE
;COUNT IN RO SCORES ABOVE AVERAGE

RO=%O
Rl=%l
R2=%2
R3=%3
SP=%6
PC=%7
.=500
START:

MOV #.,SP
MOV #16.,RI
MOV #SCORES,R2
MOV #A VERAGE,R3
CLR RO

;SET UP STACK
;SET UP COUNTER
;SET UP POINTER

CHECK:

CMP (R2)+,(R3)
BLE NO

;COMPARE SCORE AND AVERAGE
;LESS THAN OR EQUAL
;TO AVERAGE?
;NO, COUNT
;YES, DECREMENT COUNTER
;FlNTSHED? NO, CHECK
;YES, STOP

INC RO
DEC Rl
BNE CHECK
HALT
AVERAGE: 65.
NO:

SCORES*

25.,70.,100.,60.,80.,80.,40.
55.,75.,100.,65.,90.,70.,65.,70 .
.END

8-30

Program
Address

Program
Contents

Label

Op Code

Operand

Comments

;PROGRAMMING EXAMPLE
;ACCEPT (IMMEDIATE ECHO) AND
;STORE 20. CHARS
;FROM THE KEYBOARD, OUTPUT CR & LF
;ECHO ENTIRE STRING FROM STORAGE
RO=%O
Rl=%l
SP=%6
CR=15
LF=12
TKS=177560
TKB=TKS+2
TPS=TKB+2
TPB=TPS+2
.TITLE ECHO

OUT:

SAVE:

START:
MOV

.=1000
MOV
#.,SP
#SAVE+2,RO

MOV

#20.,Rl

IN:

TSTB
BPL

@#TKS
IN

ECHO:

TSTB

@#TPS

BPL
MOVB
MOVB
DEC
BNE

ECHO
@#TKB,@#TPB
@#TKB,(RO)+
Rl
IN

MOV

#SAVE,RO

MOV

#22.,Rl

TSTB

@#TPS

BPL
MOVB
DEC
BNE
HALT

OUT
(RO)+,@#TPB
Rl
OUT

.BYTE
.=.+20,
.END

CR,LF

;INITIALIZE STACK POINTER
;SA OF BUFFER
;BEYOND CR & LF
;CHARACTER COUNT
;CHAR IN BUFFER?
;IF NOT BRANCH BACK
;AND WAIT
;CHECK TELEPRINTER
;READY STATUS
;ECHO CHARACTER
;STORE CHARACTER A WAY
;FINISHED INPUTTING?
;SA OF BUFFER INCLUDING
;CR & LF
;COUNTER OF BUFFER
;INCLUDING CR & LF
;CHECK TELEPRINTER
;READY STATUS
;OUTPUT CHARACTER
;FlNISHED OUTPUTTING?

8-31

Program
Address

Program
Contents

Label

INPUT:
IN:
OUT:

Op Code

Operand

MOY #BUFFER,RO
MOY #-lO.,Rl
TSTB@#TKS
BPL IN
TSTB@#TPS
BPL OUT
MOYB @#TKB,@#TPB
MOYB @#TKB,(RO)+
INC RI
BNEIN
RTS PC

Comments
;PROGRAMMING EXAMPLE
;SUBROUTINE TO INPUT TEN YALUES
;SET UP SA OF
;STORAGE BUFFER
;SET UP COUNTER
;TEST KYBD READY STATUS
;TEST TTO READY STATllS
;ECHO CHARACTER
;STORE CHARACTER
;INC COUNTER
;EXIT
;PROGRAMMING EXAMPLE
;SUBROUTINE TO SORT TEN YALUES

SORT:
NEXT:

LOOP:
LT:
GT:
INSERT:

COUNT:
LINEl:
LINE2:
BUFFER:

MOY #-1O.,R4
MOY COUNT,R3
MOY #BUFFER+9.,RO
ADD R3,RO
MOYB (RO)+,Rl
CMPB (RO)+,Rl
BGEGT
MOYB -(RO),R2
MOYB R 1,(RO)+
MOY R2,RI
INC R3
BNE LOOP
MOYB Rl,BUFFER+1O.(R4)
INC R4
INC COUNT
BNE NEXT
MOY #-9.,COUNT
;RESTORE LOCATION COUNT
;EXIT
RTSPC

.WORD -9.
.ASCII/INPUT ANY TEN SINGLE-DIGIT YALUES (0-9); I'LL/
.ASCII/SORT AND OUTPUT THEM IN/
.ASCII/SMALLEST TO LARGEST ORDER./
.=.+10 .
.END INITSP
;FINISHED!!!

8-32

Program
Address

Program
Contents

Label

Op Code

Operand

Comments
;PROGRAMMINO EXAMPLE
;SUBROUTINE EXAMPLE
;INPUT TEN VALUES, SORT, AND
;OUTPUT THEM IN SMALLEST TO LARGEST
ORDER

RO=%O
Rl=%l
R2=%2
R3=%3
R4=%4
R5=%5
SP=%6
PC=%7
TKS=177560
(address of terminal control status register)
TKB=TKS+2 - (terminal data buffer register)
TPS=TKB+2
(terminal output control and status registers)
TPB=TPS+2 - (terminal output data buffer)
.=3000
INITSP:

MOV #.,SP
JSR PC,CRLF
JSR R5, OUTPUT
LINEI
69.
JSR PC,CRLF
JSR R5,OUTPUT
LINE2
26.
JSR PC,CRLF
JSR PC,INPUT
JSR PC,SORT
JSR PC,CRLF
JSR R5,OUTPUT
BUFFER
10.
JSR PC,CRLF
HALT

8-33

;INITIALIZE STACK POINTER
;GO TO CRLF SUBROUTINE
;GO TO OUTPUT SUBROUTINE
;SA OF LINE 1 BUFFER
;NUMBER OF OUTPUTS
;GO TO CRLF SUBROUTINE
;GO TO OUTPUT SUBROUTINE
;SA OF LINE 2 BUFFER
;NUMBER OF OUTPUTS
;00 TO CRLF SUBROUTINE
;00 TO INPUT SUBROUTINE
;GO TO SORT SUBROUTINE
;GO TO CRLF SUBROUTINE
;00 TO OUTPUT SUBROUTINE
;INPUT BUFFER AREA
;NUMBER OF OUTPUTS
;THE END!!!

Program
Address

Program
Contents

Label

Op Code

Operand

Comments
;PROGRAMMING EXAMPLE
;SUBROUTINE TO OUTPUT A CR & LF

CRLF:
LNFD:

OUTPUT:
AGAIN:

TSTB @#TPS
BPL CRLF
MOYB #15,@#TPB
TSTB @#TPS
BPL LNFD
MOYB # 12,@#TPB
RTS PC

MOY (R5)+,RO
MOY (R5)+,Rl
NEG Rl
TSTB @#TPS
BPL AGAIN
MOYB (RO)+,@#TPB
INC Rl
BNE AGAIN
RTS R5

;TEST TTO READY STATUS
;OUTPUT CARRIAGE RETURN
;TEST TTO READY STATUS
;OUTPUT LINE FEED
;EXIT

;SUBROUTINE TO OUTPUT A
;Y ARIABLE LENGTH MESSAGE
;PICK UP SA OF DATA BLOCK
;PICK UP NUMBER OF OUTPUTS
;NEGATE IT
;TEST TTO READY STATUS
;OUTPUT CHARACTER
;BUMP COUNTER

8.7 LOOPING TECHNIQUES
Looping techniques are illustrated in the program segments below. The segments are used to clear a 50word table.

Autoincrement (pointer address in GPR)

LOOP:

RO= %0
MOY #TBL,RO
CLR (RO)+
CMP RO,#TBL+ 100.
BNE LOOP

Autodecrement (pointer and limit values in GPR)

LOOP:

RO=%O
Rl=%1
MOY #TBL,RO
MOY #TBL+I00.,Rl
CLR - (Rl)
CMP Rl,RO
BNE LOOP

8-34

Counter (decrementing a GPR containing count)

LOOP:

Index Register Modification (indexed mode; modifying index value)

LOOP:

RO=%O
CLRRO
CLR TBL (RO)
ADD #2,RO
CMP RO,#lOO.
BNE LOOP

Faster Index Register Modification (storing values in GPR)

LOOP:

RO=%O
Rl=%l
MOV #TBL,RO
MOV #50.,RI
CLR (RO)+
DEC RI
BNE LOOP

RO=%O
Rl=%l
R2=%2
MOV #2,Rl
MOV #lOO.,R2
CLRRO
CLR TBL (RO)
ADD Rl,RO
CMP RO,R2
BNE LOOP

Address Modification (indexed mode; modifying base address)

LOOP:

RO=%O
MOV #TBL,RO
CLR O(RO)
ADD #2,LOOP+2
CMP LOOP+2,#lOO.
BNE LOOP

8-35

CHAPTER 9
BOOT ROMS AND DIAGNOSTICS

9.1 INTRODUCTION
The KDJ ll-A module may be incorporated into some type of LSI-II based system using a mass storage
device and a system console. The system should contain a multifunction option such as the MXV II-B with
a system device bootstrap program that is included in the MXVII-B2 ROM option. These ROMs are
required for on-site Field Service support.
The operation of the XXDP+ diagnostics for the KDJ11-A module are described in this section.
9.2 MXVll-B2 ROM SET
The MXVII-B2 ROM set is a bootstrap/diagnostic option for the MXVII-B multifunction module and
the MRVII-D universal PROM module. The option performs bootstrap programs for mass storage
devices and diagnostic programs on the CPU, memory, and I/O devices during power-up or when
manually invoked.
The bootstrap function is automatic at power-up if the CPU is configured for this feature. The system
console can be used to boot devices at nonstandard I/O page addresses, select a secondary system device,
or run a diagnostic program.
CAUTION
In the event of a power failure, if a system uses
battery backup, the user should not power-up using
the automatic mode. During the power-up sequence,
this mode executes a memory diagnostic and could
destroy the data stored. An alternative power-up
mode should be selected.
The MXV II-B2 supports turnkey operation so that the user does not have to initiate the bootstrap
function. It supports all the system devices currently available for the LSI-II bus. These include the
RLOl, RL02, TVS05, TU58, RX50/RD51.
9.2.1 Power-Up
The MXVI1-B2 performs a memory diagnostic at power-up. On completion of the memory test, a search
is conducted for a bootable device. During the power-up sequence, the console port is monitored for a
CTRL C command and, if it occurs, the sequence is aborted and the BOOT?> prompt appears on the
console.

9-1

9.2.2 Automatic Booting
The KOJII-A will power-up at 17 773 000 when power-up option 2 is selected. The MXVll-B2 option
will automatically perform the power-up diagnostics and then search for a bootable device as follows.
RLOljRL02 (units 0 through 3)
RX50jR051 * (units 0 through 7)
RX02 (units 0 and 1)
RXOI (units 0 and 1)
TSV05 (unit 0 only)
TU58
The MXVII-B2 boots a volume from unit 0 of the first mass storage device found. If unit 0 cannot be
booted, it searches through RX and RO units 1-7 in sequence of the same device for a bootable volume.
When a bootable volume cannot be located, it proceeds to the next device in sequence and exercises the
same routine. A message appears on the console approximately every 30 seconds until a volume is
bootstrap loaded. If no devices exist or respond to the booting sequence, then it will try to boot a TU58.
When a bootable volume is found, the MXVII-B2 reads the boot code from the selected mass storage
device and unit (logical block 0) into successive memory locations, starting at address O. It loads the unit
number and the device CSR address into registers 0 and I, respectively.
9.2.3 Manual Booting
Pressing a CTRL C before a device is booted will abort the program and enter the manual mode by issuing
the BOOT?> program or OOT prompt "@". A list of the MXVII-B2 boot commands is given in
Table 9-1.
Table 9-1
Command *

Group

Function

CLn
mDDn
mDLn
mDUn
mDXn
mDYn
HE
IN
LD
MP
mMSn

Utility
Boot
Boot
Boot
Boot
Boot
Utility
Utility
Utility
Utility
Boot
Utility
Boot
Boot
Boot
Boot
Utility
Utility
Utility
Utility
Utility

Clock on/off
Boot TU58
Boot RLOI/RL02
Boot MSCP devices (RX50/RD5l)t
Boot RXOI
Boot RX02
Help
Initialize bus
Load boot block
Show memory map
Boot TSV05
Examine/deposit memory
Boot DECnet via DLVll-E
Boot DECnet via DLVll-F
Boot DECnet via DPVII
Boot DECnet via DUV II
Enter console ODT
Clock test
Floating-point test
Test memory
Serial line test

n/
mNEn
mNFn
mNPn
mNUn
OD
mTCn
TF
mTMn
mTSn

*
t

MXVll-B2 Boot Commands

For devices, m = octal device address and n = device number. For utilities, m = repetition count or
device address and n = option number.
The boot searches for removable (RX50) disk and then fixed disk (RD51).

Sequences through MSCP (mass storage control protocol) removable units 0 through 7, then MSCP fixed units 0 through 7.

9-2

9.2.4 Error and Help Messages
The MXVII-B2 ROMs will printout on the system console a variety of error and help messages when the
system fails to be booted. In the automatic mode, a message is displayed every 30 seconds while it searches
for a bootable device, this does not represent a failure. The messages can occur for either the automatic or
manual mode. A fatal message is always preceded by BOOTROM-F-; other messages will provide helpful
information to the user. The messages are listed in Table 9-2 with suggestions to help the user.
Table 9-2
Message

MXVll-B2 Error Messages

Cause

Suggested User Action

No bootable device or volume available
to load. This message repeats at 30second intervals until 10th message,
then repeats at IS-minute intervals
(approximately).

Close doors on floppy if system is on
RXO 1 or RX02 media. Make sure that
RLOI/RL02 READY (white) indicator
is on, etc. If problem is not obvious and
the message repeats, press CTRL C and
try to boot desired device with a keyboard command. More specific messages
will appear.

Defective memory unit or MMU
detected.

Record the message and number. Turn
power off, then on. If problem remains,
service is required. If you wish to bypass
the memory test, use manual mode by
rebooting system, pressing CTRL C, and
then using the LOAD command.

?BOOTROM-F Unknown error call for help.

Fatal hardware failure detected.

Record all relevant information about
the system, including the LED indicators
on MXVII-B module (if installed). Service is required.

xxxxxx

Fatal hardware failure or bad system
volume detected.

Try a different system volume, if available (one you know works, if possible). If
the problem remains, record information
as above. Service is required.

Fatal hardware failure detected, possibly the console.

If possible, try a different console. If the
problem remains, record information.
Service is required.

?BOOTROM-F Syntax error in
command.

Illegal character or other general input
error occurred.

Retype command correctly.

?BOOTROM-F No such command - type HE for help.

Invalid or misspelled command
entered.

Refer to manual, or type HE to get a
list of all valid commands.

?BOOTROM-F Too many
characters.

More than 8 octal digits typed before
the 2-letter command, or more than 1
digit following command, or more than
17 letters in command.

Retype command correctly.

?BOOTROM-F Number not
octal.

An 8 or 9 was typed.

Determine correct number and retype
command.

Automatic Boot Soft Error Message
No device ready after x tries.

Automatic Boot Fatal Error Messages
?BOOTROM-F Memory parity
error at xxxxxx.
?BOOTROM-F Memory error at
xxxxxx.

Any partially printed message.

General Command Error Messages

9-3

Table 9-2
Message

MXVll-B2 Error Messages (Cont)
Suggested User Action

Cause

Manual Boot Messages
You can produce these messages by using one of the commands in the boot group (Table 9-1). Some device-specific messages
are listed in the next section of this table.
Enter a device and unit

Previous command was LD.

If you wish to load a device boot block

into memory without executing it, enter
a valid command from the boot group.
Normal load-and-go operation is restored
after the command executes.

xx x boot block read.

Normal termination for a boot group
command when the previous command
was LD.

Examine or alter the boot block in locations 000000 to 00077 6 by using console
ODT.

No boot block on volume.

The volume has a format that corresponds to a Digital data-only volume.

Remove the volume and replace with
correct one, or (if it is not a Digital system volume) boot it with the LD command. (Refer to LD command section.)

Unknown boot block on volume
boot anyway?

The volume has a format that does not
correspond to any Digital standard.

Type N and retry with a different volume. If it is not a Digital system volume, type Y; this transfers control to
secondary boot at location zero.

?BOOTROM-F No XX device
at x.

If a CSR was explicitly typed in, it
may be incorrect. If none was typed,
the device is missing, defective, Oi configured for a nonstandard I/O page
address.

If CSR was incorrect, retype with correct CSR. If not, service is required.
(Hardware must be supported by Digital,
and device must be part of your system.)

?BOOTROM-F XX x read error.

Error detected in the device or volume.

Try another volume you know is good.
If the problem remains, service is
required.

?BOOTROM-F XX x error.

Device error detected.

Service may be required, unless there is
an obvious solution.

?BOOTROM-F XX x not ready.

Volume not ready to be read by device
(for example, not loaded).

The solution depends on the device, and
is usually obvious after inspection (for
example, volume not inserted into
device, floppy drive door open, or RL02
disk cover left out). If the device has a
panel of status indicators, they may give
a clue. If there is no obvious solution,
service may be required.

9-4

Table 9-2

MXVll-B2 Error Messages (Cont)

Message

Cause

Suggested User Action

?BOOTROM-F Bad CSR
number.

CSR number typed in is greater than
177560, less than 160000, or odd, or
specified CSR is that of the console.

Retype the command, using correct
CSR address.

?BOOTROM-F Bad Unit
number.

Specified unit does not exist in system,
or the number is greater than maximum number of units supported by
single controller for specified device
type.

If device uses unit- number plugs, such

?BOOTROM-F Unknown error call for help.

Fatal hardware failure detected.

Record all relevant information about
the system, including LED indicators on
the MXV II-B module (if installed). Service is required.

Fatal hardware failure or a bad system
volume detected.

Try a different system volume, if available (one you know works, if possible). If
the problem remains, record all relevant
information, including the LED indicators on the MXVII-B module (if
installed). Service may be required.

Any partially printed message.

Fatal hardware failure detected, possibly the console.

If possible, try a different console. If
problem remains, record all information.
Service may be required.

?BOOTROM-F Memory cache
parity error.

Cache memory parity error or failure
detected.

Replace processor module or continue to
use system without cache (cache turned
off). System simply runs slower.

?BOOTROM-F Fatal ROM
error.
xxxxxx
@

as RL disks, they may have been
changed or removed without operator
knowledge. Check device for plugs and
retype command. If not, there may be a
hardware fault.

Device-Specific Manual Boot Messages

RX02 unit with RXO 1 volume.
Boot anyway? (Occurs with
RX02 floppy disk systems.)

RX02 drive loaded with single-density
volume.

?BOOTROM-F Comm error.
(Occurs only while booting
DECnet via a serial line from a
keyboard command, such as

DECnet boot could not be executed
due to hardware or software problem
in host system, target system, or communication link.

If you know the volume contains a valid
RX02 boot-only block, type Y. If vol-

ume is unknown, it may be an RXO I
disk.

NE.)

9-5

Check the communication line. Service
may be required.

If the option is installed in the MXVII-B module, the LEDs on the module can indicate errors.
The LEDs read as follows. The single red LED to one side of the green LED is bit 3; the three red LEOs to
the other side of the green LED are bits 2 to 0, with bit 2 being the red LED closest to the green LED.

3
Green

Red

(As seen looking at the edge of the board, with the
components up.)

In the following chart, a 1 indicates the LED is on, and 0 indicates the LED is off. The green LED
indicates +5 Vdc is applied to RAM memory.
The chart shows which part of the ROM program was executing when the system hung up.

LEDs
2
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
I
1

0
0
1
1
0
0

0
0
I
0
1
0
1
0

1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1

Successful boot
Comprehensive memory test
Waiting for console input
Low memory test (below 2000 octal)
MSCP device (RX50/RD51)
Not assigned
Not assigned
RLO 1/RL02 boot
RXOl/RX02 boot
TSV05 boot
Not assigned
DPVll DECnet boot
DUVII DECnet boot
DLVII DECnet boot
TU58 boot
Power-up initialization

LED indicator codes that are not assigned should never appear when using the MXVll-B2.
NOTE
A 1111 indicator code appears after a successful
DECnet boot.
9.3 DIAGNOSTICS
The XXDP+ diagnostic programs help to verify the system is functioning correctly or to isolate a faulty
component. These are used for maintenance purposes and not as part of the normal system operation. The
XXDP+ diagnostic software consists of a library of diagnostic programs designed to test individual system
components. These can be chained together, dependent on the system configuration, to provide an overall
system diagnostic. The diagnostics specifically used for the KD111-A module are listed in Table 9-3 and
are described below.

9-6

Table 9-3

KDJt I-A Diagnostics

Name

Function

CZKDJBO
CZKDKBO
CZKDLBO
CZKDMBO

CPU tests
Memory management tests
Floating-point tests
Cache memory tests

The HALT trap option must be disabled by installing the W5 jumper when running these diagnostics. The
diagnostic program can be halted by asserting the HALT line. This is done by pressing the BREAK key on
the system console for systems configured to assert HALT when BREAK is keyed. They can be restarted
by addressing location 152 010 and pressing the G key on the system console. The system monitor"." will
prompt and the diagnostic program can be selected by the run command R followed by the diagnostic
name. The name will be echoed and the program started. The name of the diagnostic is printed on the first
pass and completed tests are identified by the system console printing END PASS. When an error is
detected, the diagnostic will halt and print out the error condition as follows.
Error = Specific Function Being Tested
Error = (Unique Error Number)
Error PC = (PC at Time of Error)
9.4 DIAGNOSTIC EXAMPLE
An example of running the diagnostics is described below. The response of the user is underlined and the
system response is typed. The W5 jumper must be installed. Comments are listed on the right hand side to
further explain the example.
Diagnostic

Comments

28
START? DL<CR>

Booted DL device

CHMDLC 1 XXDP+ DL MONITOR
BOOTED YIA UNIT 0
28K UNIBUS SYSTEM

XXDP+ monitor
May
be
LSI BUS
or
UNIBUS
28K=MEMORY SIZE OR STANDARD
User enters date

ENTER DATE (DD-MMM-YY): I-NOY-83
RESTART ADDRESS: 152010
THIS IS XXDP+. TYPE "H" OR
"H/L" FOR HELP

Identifies restart address

.R ZKDJBO<CR>

. = System monitor
R = RUN command
ZKDJBO = Diagnostic
<CR> = RETURN key

ZKDJBO.BIC

9-7

CZKDJ-B-O KDJll CPU Diagnostic
CZKDJB END PASS # I
CZKDJB END PASS # 2
CZKDJB END PASS # 3
027622

Halt test by pressing break
Address at HALT

@152010G

Key restart address and
G for GO
Run diagnostic and return

.R ZKDKBO<CR>
ZKDKBO.BIC
SET BIT 8 = 1 FOR 18 BIT SYSTEM
SWR = 000000 NEW = <CR>

Set bit 8 by 000400
Press return

CZKDK-B-O KDJll Memory Management
CZKDKB END PASS # 1
CZKDKB END PASS # 2
CZKDKB END PASS # 3
CZKDKB END PASS # 4
012404

Halt test by pressing break
address at halt

@152010G

Key restart address and
G for GO
Run diagnostic and return

.R ZKDLBO<CR>
ZKDLBO.BIC
CZKDL-B-O KDJll Floating Point
CZKDLB END PASS # 1
CZKDLB END PASS # 2
CZKDLB END PASS # 3
CZKDLB END PASS # 4
CZKDLB END PASS # 5
022242

Halt by pressing BREAK
address at HALT

@152010G

Key restart address and
G for GO
Run diagnostic and return

.R ZKDMBO<CR>
ZKDMBO.BIC
SET BIT 8 = 1 FOR 18 BIT SYSTEM
SET BIT 9 = 1 FOR CACHE RAM AND TAG
RELIABILITY TESTS

Set bit 8 by 000400
Set bit 9 by 001000
Set bits 8 and 9 by 001400

SWR = 000000 NEW = <CR>

Press RETURN

9-8

CZKDM-B-O KDJll Cache Memory System
CZKDMB END PASS # 1
CZKDMB END PASS # 2
CZKDMB END PASS # 3
CZKDMB END PASS # 4
CZKDMB END PASS # 5
CZKDMB END PASS # 6
010152

Halt test by pressing BREAK
address at HALT

@152010G

Key restart address and
G for GO
System monitor and run
command

9-9

APPENDIX A
INSTRUCTION TIMING

A.I GENERAL
The execution time required for the base instruction set and the floating-point instruction set used by the
KDJ ll-A is described in this appendix. The execution time for an instruction is dependent upon the type
of instruction, the addressing mode used, and the type of memory accessed. In general, the total execution
time is the sum of the base instruction fetch/execute time and the operand(s) address calculation/fetch
time.
The execution time provided for all read instructions assumes that the data is accessed from the module
cache memory. When the data is accessed from the main memory, the execution time provided must be
degraded. Memory write instructions, indicated by the "+" notation, must have the memory write time
added to the listed time in order to determine the total time.
The floating-point instruction execution timing is provided as a range. The actual performance is data
dependent and will fall within the described range.
A.2 BASE INSTRUCTION SET TIMING
The execution times for the base instruction set are provided in Tables A-I through A-6 and are subject to
the general notes listed at the end of Table A-6.
Table A-l

Instruction
ADD, SUB,
CMP, BIT,
BIC, BIS,
MOV

Source Address Time: All Double Operand

Source
Mode

Source
Register

Microcode
Cycles

Time
(ns)

Read
Memory
Cycles

0
1
2
2
3
3
4
4

0-7
0-7
0-6
7
0-6
7
0-6
7
0-6
7
0-7
0-7

0
2
2

0
534
534
267
1068
801
801
1602
1335
2136
1068
1602

0
1
1
1
2
2
1
2 (Note 1)
2
3 (Note I)
2
3

5
5

6
7

4
3
3
6
5
8
4
6

A-I

Table A-2

Instruction
TST, MUL, DlV,
ASH, ASHC, MTPS,
MFPI, MFPD, CSM

Destination Address Time: Read-Only Single Operand

Destination
Mode

Destination
Register

Microcode
Cycles

Time
(ns)

0-7
0-7
0-6
7
0-6
7
0-6
7
0-6
7
0-7
0-7

0
2
2

0
534
534
267
1068
801
801
1869
1335
2403
1068
1602

2
2
3
3
4
4
5
5
6
7

Table A-3

4
3
3
7
5
9
4
6

Read
Memory
Cycles
0
I
I
I

2
2
I

2 (Note 2)
2
3 (Note 3)
2
3

Destination Address Time: Read-Only Double Operand

Instruction

Destination
Mode

Destination
Register

Microcode
Cycles

Time
(ns)

CMP, BIT

0-7
0-7
0-6
7
0-6
7
0-6
7
0-6
7
0-7
0-7

0
3
3
2
5
4
4
8
6
10
5
7

0
801
801
534
1335
1068
1068
1236
1602
2670
1335
1869

2
2
3
3
4
4
5
5
6
7

Table A-4

Read
Memory
Cycles
0
I

1
1
2
2
I

2 (Note 2)
2
3 (Note 3)
2
3

Destination Address Time: Write-Only
Memory Cycles

Instruction

Destination
Mode

Destination
Register

Microcode
Cycles

Time
(ns)

MOV, CLR, SXT,
MFPS, MTPI, MTPD

0
0

0-6
7
0-6
7
0-6
7
0-6
7
0-6
7
0-6
7
0-7
0-7

0
5
2
6
2
6
4
3
3
7
5
9
4
6

0
1335
534+
1602+
534+
1602+
1068+
801+
801+
1869+
1335+
2403+
1068+
1602+

I
I

2
2
3
3
4
4
5
5
6
7

A-2

Read

Write

0
0

0
I

0
1
I
I

0
I
I

2
I

I
I
I
I
I
I
I
I
I
I
I
I

Table A-5

Destination Address Time: Read-Modify-Write
Memory Cycles

Instruction
ADD, SUB, AOC,
SBC, BIC, BIS,
SWAB, NEG, INC,
DEC, COM, XOR,
ROR, ROL, ASR,
ASL

Destination
Mode

Destination
Register

Microcode
Cycles

Time
(ns)

Read

Write

0
0
1
1
2
2
3
3
4
4
5
5
6
7

0-6
7
0-6
7
0-6
7
0-6
7
0-6
7
0-6
7
0-7
0-7

0
5
3
7
3
7
5
4
4
8
6
10
5
7

0
1335
801+
1869+
801+
1869+
1335+
1068+
1068+
2136+
1602+
2670+
1335+
1869+

0
1
1
2
1
2
2
2
1
2
2
3
2
3

0
0
1
1
1
1
1
1
1
1 (Note 2)
1
1 (Note 3)
1
1

Table A-6

Execution, Fetch Time
Memory Cycles

Instruction

Microcode
Cycles

Time
(ns)

Read

Write

Double Operand
ADD, SUB, CMP,
BIT, BlC, XOR,
MOY, BIS

267

Single Operand
SW AB, CLR, COM,
INC, DEC, NEG,
ADC, SBC, TST,
ROL, ROR, ASL,
ASR, SXT, MFPS,
XOR
MFPI, MFPD

1335+

MTPS

2136

MTPI, MTPD

801

CSM

7476+

MUL

5874

o (Notes 5, 11)

DIY
By zero
Other

5
34

1335
9078

o (Note 6)
o (Notes 6, 7)

ASH

1068

o (Notes 8, 11)

ASHC
No shift
Left
Right

5
6
7

1335
1602
1869

o (Notes 8, 9,11)
o (Notes 8, 10, 11)

Extended Instruction Set

A-3

Table A-6

Execution, Fetch Time (Cont)
Memory Cycles

Microcode
Cycles

Time
(ns)

Read

Write

BRANCH
Not Taken
Taken

2
4

534
1068

1
2

0
0

SOB
Not Taken
Taken

3
5

801
1335

1
2

0
0

lOT, TRAP,
EMT, BPT

5340+

MARK

2670

Instruction

Destination
Mode

Destination
Register

Microcode
Cycles

Time
(ns)

Read

Write

1
2
3
4
5
6
7

0-7
0-7
0-7
0-7
0-7
0-6
7
0-7

4
6
5
5
6
6
5
7

1068
1602
1335
1335
1602
1602
1335
1869

2
2
3
2
3
3
3
4

0
0
0
0
0
0
0
0

1
2
3
3
4
5
6
6
7

0-7
0-7
0-6
7
0-7
0-7
0-6
7
0-7

9
10

2403+
2670+
2670+
2403+
2670+
2937+
2670+
2403+
3204+

2
2
3
3
2
3
3
3
4

Instruction

Microcode
Cycles

Time
(ns)

Read

Write

RTS 0-6

1602

RTS 7

1335

RTT, RTI

2403

Instruction
Program Control

Memory Cycles

JMP

JSR (Note 4)

9
10
11
10

9
12
Memory Cycles

A-4

Table A-6

Execution, Fetch Time (Cont)
Memory Cycles

Microcode
Cycles

Time
(ns)

MFPT

534

NOP,
SET or CLEAR
C, V, N,Z

801

SPL

1869

HALT

TBD

RESET

TBD

WAIT

TBD

Instruction

Read

Write

Miscellaneous Instructions

General Notes to Tables A-I through A-6
I.

Subtract 534 ns and one read if both source and destination modes autodecrement PC, or if WRITE-ONLY or READMODIFY-WRITE mode 07 or 17 is used.

READ-ONL Y and READ-MODIFY-WRITE destination mode 47 references actually perform 3 read operations. For
bookkeeping purposes, one of the reads is accounted for in the EXECUTE, FETCH TIMING.

READ-ONLY and READ-MODIFY-WRITE destination mode 57 references actually perform 4 read operations. For
bookkeeping purposes one of the reads is accounted for in the EXECUTE, FETCH TIMING.

Subtract 267 ns if link register is Pc.

Add 267 ns if the source operand is negative.

Subtract 267 ns if the source mode is not zero.

Add 267 ns if the quotient is even.
Add 534 ns if overflow occurs.
Add 1335 ns and I read if the PC is used as a destination register, but only if source mode 47 or 57 is not used.

Add 267 ns per shift.

Add 267 ns if source operand<15:6> is not zero.

10.

Subtract 267 ns if one shift only.

II.

Add 1068 ns and I read if the PC is used as a destination register, but only if source mode 47 or 57 is not used.

A-5

A.3 FLOA TING-POINT INSTRUCTION SET TIMING
The execution time range for the floating-point instruction set is described in Tables A-7 through A-13.

Table A-7
Instruction

Minimum

ABSD
ABSF
ADDD
ADDF
CFCC
CLRD
CLRF
CMPD
CMPF
DlVD
DlVF
LDCDF
LDCFD
LDCID
LDCIF
LDCLD
LDCLF
LDD
LDEXP
LDF
LDFPS
MODD
MODF
MULD
MULF
NEGD
NEGF
SETD
SETF
SETI
SETL
STCDF
STCDI
STCDL
STCFD
STCFI
STCFL
STD
STEXP
STF
STFPS
STST
SUBD
SUBF
TSTD
TSTF

6.1
5.1
10.9
8.3
1.3
3.7
3.2
6.4
4.8
42.7
15.7
6.4
5.3
8.3
6.9
8.3
6.9
4.3
4.5
3.2
1.6
53.9
21.9
44.0
14.9
5.9
4.8
1.6
1.6
1.6
1.6
4.5
6.9
6.9
5.1
6.1
6.1
3.2
4.3
2.1
2.4
1.9
12.5
9.9
2.9
2.4

Instruction Execution Times (In Microseconds)
Typical

Maximum
6.4
5.3
31.7
31.7
1.3
3.7
3.2
6.7
5.1
44.5
16.8
6.9
5.6
11.2
9.6
13.9
11.7
4.5
4.8
3.5
1.6
71.5
30.1
46.1
16.3
6.1
5.1
1.6
1.6
1.6
1.6
5.3
10.1
14.4
5.3
9.3
13.6
3.2
4.3
2.1
2.4
1.9
32.5
27.7
3.2
2.7

12.8
9.3

51.9
25.1

14.7
10.9

A-6

Non-mode 0
Section

IV
IV
II
II
III
III
II
II
II
II
II
II

V
V
V
V
II

V
II

V
II
II
II
II

IV
IV

III

VI
VI
III

VI
III

VI
VI
II
II
II
II

Instruction

Table A-8

Floating Source Modes 1-7

Mode

Microcode
Cycles

Time
(ns)

Memory
Read

Memory
Write

1
2
2
3
3
4
5
6
7

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

3
3
1
4
3
4
5
4
6

801
801
267
\068
801
1068
1335
1068
1602

2
2
1
3
3
2
3
3
4

0
0
0
0
0
0
0
0
0

1
2
2
3
3
4
5
6
7

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

5
5
0
6
5
6
7
6
8

1335
1335
0
1602
1335
1602
1869
1602
2136

4
4
1
5
5
4
5
5
6

0
0
0*
0
0
0
0
0
0

Single Precision
ADDF, CMPF,
DJVF, LDCDF,
LDF, MODF,
MULF, SUBF,
TSTF

Double Precision
ADDD, CMPD,
DJVD, LDCFD,
LDD, MODD,
MULD, SUBD,
TSTD

* Mode 27 references only access single word operands. The execution time listed has been compensated in order to accurately
compute the total execution time.

Table A-9

Instruction

Floating Destination Modes 1-7

Mode

Microcode
Cycles

Time
(ns)

Memory
Read

Memory
Write

1
2
2
3
3
4
5
6
7

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

3
3
1
4
3
4
5
4
6

801+
801+
267+
\068+
801+
1068+
1335+
1068+
1602+

0
0
0
1
1
0
1
1
2

2
2
1
2
2
2
2
2
2

1
2
2
3
3
4
5
6
7

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

5
5
0
6
5
6
7
6
8

1335+
1335+
0
1602+
1335+
1602+
1869+
1602+
2136+

0
0
0
1
1
0
1
1
2

4
4
1*
4
4
4
4
4
4

Single Precision
CLRF, STCDF, STF

Double Precision
CLRD, STCFD, STD

* Mode 27 references only access single word operands. The execution time listed has been compensated in order to accurately
compute the total execution time.

A-7

Table A-I0

Instruction

Floating Read-Modify-Write Modes 1-7

Mode

Microcode
Cycles

Time
(ns)

Memory
Read

Memory
Write

1
2
2
3
3
4
5
6
7

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

5
5
1
6
5
6
7
6
8

1335+
1335+
267+
1602+
1335+
1602+
1869+
1602+
2136+

2
2
1
3
3
2
3
3
4

2
2
1*
2
2
2
2
2
2

1
2
2
3
3
4
5
6
7

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

9
9
0
10
9
10

1403+
2403+
0
2670+
2403+
2670+
2937+
2670+
3204+

4
4
1
5
5
4
5
5
6

4
4
1*
4
4
4
4
4
4

Single Precision
ABSF, NEGF

Double Precision
ABSD, NEGD

10
12

* Mode 27 references only access single word operands. The execution time listed has been compensated in order to accurately
compute the total execution time.

Instruction

Mode

Table A-ll

Integer Source Modes 1-7

Microcode
Cycles

Time
(ns)

Memory
Read

Memory
Write

7
0-6
7
0-7
0-7
0-7
0-7

2
2
0
3
2
3
4
3
5

534
534
0
801
534
801
1068
801
1335

1
1
1
2
2
1
2
2
3

0
0
0*
0
0
0
0
0
0

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

4
4
0
5
4
5
6
5
7

1068
1068
0
1335
1068
1335
1602
1335
1869

2
2
1
3
3

0
0
0*
0
0
0
0
0
0

Integer
LDCID, LCDIF,
LDEXP,LDFPS

1
2
2
3
3
4
5
6
7

0-7
0-6

Long Integer
LDCLD, LCDLF

1
2
2

3
3
4
5
6
7

3
3
4

* Mode 27 references only access single word operands. The execution time listed has been compensated in order to accurately
compute the total execution time.

A-8

Integer Destination Modes 1-7

Table A-12

Instruction

Mode

Microcode
Cycles

Time
(ns)

Memory
Read

1
2
2
3
3
4
5
6
7

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

2
2
2
3
2
3
4
3
5

534+
534+
534+
801+
534+
801+
1068+
801+
1335+

0
0
0
1
1
0
1
1
2

1
2
2
3
3
4
5
6
7

0-7
0-6
7
0-6
7
0-7
0-7
0-7
0-7

4
4
2
5
4
5
6
5
7

1068+
1068+
534+
1335+
1068+
1335+
1602+
1335+
1869+

0
0
0
1
1
0
1
1
2

Memory
Write

Integer
STCm, STCFI,
STEXP, STFPS

Long Integer
STCDL,STCFL,STST

Table A-13
Instruction
ADDDjSUBD
ADDFjSUBF
DIVD
DIVF
MULD
MULF

FPJll-AA Instruction Execution Times
Minimum
Cycles

Typical
Cycles

7
7
35
19
26
15

9
9
45
26
26
15

A-9

Typical
(15 MHz)
1.2 IlS
1.2 IlS
6.0 IlS
3.5 IlS
3.5 IlS
2.0 IlS

2
2
1
2
2
2
2
2
2

APPENDIX B
PROGRAMMING DIFFERENCES

The programming differences between the KDJII-A processor and the other processors of the PDP-II
family are summarized in Table 8-1.

8-1

Table B-1

KDJll-A Programming Differences
Processors

Feature
I.

OPR %R, (R) +; OPR %R, - (R) using
the same register as both source and
destination: contents of R are incremented (decremented) by 2 before being
used as the source operand.

23/24

~
I
IV

OPR %R, @ (R) +; OPR %R, @ - (R)
using the same register as both
source and destination: contents of R
are incremented (decremented) by 2
before being used as the source
operand.

OPR PC, X (R); OPR PC, @ X (R); OPR
PC, @ A; OPR PC, A: location A will
contain the PC of OPR +4.

45 70 60 KDJll-A

35/40

JMP (R) + or JSR reg, (R) +: contents
of R are incremented by 2, then used
as the new PC address.
JMP (R) + or JSR reg, (R) +: initial
contents of R are used as the new Pc.

15/20

OPR PC, X (R); OPR PC, @ X (R), OPR
PC, A; OPR PC, @ A: location A will
contain the PC of OPR +2.
4.

OPR %R, @ (R) +; OPR %R, @ - (R)
using the same register as both
source and destination: initial
contents of R are used as the source
operand.
3.

05/10

OPR %R, (R) +; OPR %R, - (R) using the
same register as both register and
destination: initial contents of Rare
used as the source operand.
2.

44 04 34 LSI/ll

Table 8-1

KDJll-A Programming Differences (Cont)
Processors

Feature
5.

JMP %R or JSR reg, %R traps to 10
(illegal instruction).

23/24 44 04 34 LSI/II

05/10 15/20 35/40 45 70 60 KDJll-A

JMP %R or JSR reg, %R traps to 4
illegal instruction).
6.

SWAB does not change Y.
SWAB clears Y.

X
X

Register addresses (177700-177717)
time out when used as a program
address by the CPU. Can be addressed
under console operation.

OJ
I
W

Basic instructions noted in PDP-]]
Processor Handbook.

SOB, MARK, RTT, SXT instructions*
ASH, ASHe, DIY, MUL, XOR

X
X

Floating-point instructions in base
machine.
MFPT instruction.

*RTT instruction is available in 11/04 but is different than other implementations.

X
X

The external option KE11-A provides
MUL, DIY, SHIFT operation in the
same data format.

Table B-1 KDJlI-A Programming Differences (Cont)
Processors
Feature

t:p

44 04 34 LSI/ll

05/10

15/20 35/40 45 70 60 KDJll-A

The KEll-E (expansion instruction set)
provides the instructions MUL, DIY,
ASH, and ASHe. These new instructions
are 11/45 compatible.

The KEII-F (floating instruction set)
adds unique stack ordered oriented
point instructions: FADD, FSUB, FMUL,
FDIB.

The KEY-II adds EIS/FIS instructions
MFP, MTP instructions

.J:o,.

23/24

SPL instruction

CSM instruction

Power fail acts the same as 11/45
(22 milliseconds with about 300
nanoseconds minimum). Power fail
during RESET fetch is fatal with no
power down sequence.

X X

X
X

Power fail during RESET instruction
is not recognized until after the
instruction is finished (70 milliseconds). RESET instruction consists
of 70 millisecond pause with INIT
occurring during first 20 milliseconds.
Power fail immediately ends the RESET
instruction and traps if an INIT is
in progress. A minimum INIT of microsecond occurs if instruction aborted.
PDPII-04/34/44 are similar with no
minimum INIT time.

X X

X X X

Table B-1

KDJll-A Programming Differences (Cont)
Processors

Feature
RESET instruction consists of 10
microseconds of INIT followed by a
90 microsecond pause. Reset instruction consists of a minimum 8.4
microseconds followed by a minimum
100 nanosecond pause. Power fail not
recognized until the instruction
completes.
10. No RTf instruction.
If RTf sets the T-bit, the T-bit
trap occurs after the instruction
following RTT.

tp
VI

23/24

44 04 34 LSI/ll

12. If an interrupt occurs during an
instruction that has the T-bit set,
the T-bit trap is acknowledged
before the interrupt.

35/40

X· X

If an interrupt occuurs during an
instruction and the T-bit is set,
the interrupt is acknowledged
before T-bit trap.
13. T-bit trap will sequence out of
WAIT instruction.

T-bit trap will not sequence out
of WAIT instruction. Waits until
an interrupt.

45 70 60 KDJll-A

X
X

15/20

II. If RTI sets T-bit, T-bit trap
is acknowledged after instruction
following RTf.
If RTI sets T-bit, T-bit trap is
acknowledged immediately following
RTf.

05/10

X
X

Table B-1

KDJll-A Programming Differences (Cont)
Processors

Feature

23/24

44 04 34 LSI/ll

14. Explicit reference (direct access)
to PS can load T-bit. Console can
also load T-bit.
Only implicit references (RTf, RTT,
traps and interrupts) can load T-bit.
Console cannot load T-bit.

15. Odd address/nonexistent references
using the SP cause a HALT. This is
a case of double bus error with the
second error occurring in the trap
servicing the first error. Odd address
trap not implemented in LSI-II, 11/23
or 11/24.

t::Ij
I
0'\

Odd address/nonexistent references
using the stack pointer cause a fatal
trap. On bus error in trap service,
new stack created at 0/2.

16. The first instruction in an
interrupt routine will not be
executed if another interrupt occurs
at a higher priority level than
assumed by the first interrupt.

05/10

15/20

Dual general-purpose register set
implemented.

45 70 60 KDJll-A

The first interrupt in an interrupt
service is guaranteed to be executed.
17. Single general-purpose register
implemented.

35/40

X
X

Table B-1

KDJII-A Programming Differences (Cont)
Processors

Feature

23/24

44 04 34

PSW address implemented, MTPS and
MFPS not implemented.

tA:I
I

21. Odd address trap not implemented.

KDJII-A

X
X

Odd address trap implemented.

X
X

22 .. FMUL and FDIV instructions
implicitly use R6 (one push and
pop); hence R6 must be set up
correctly.

FMUL and FDIV instructions do not
implicitly use R6.

23. Due to their execution time, EIS
instructions can abort because of
a device interrupt.

24. Due to their execution time, FIS
instructions can abort because of
a device interrupt.

45 70

Some sort of stack overflow
implemented.

EIS instructions do not abort
because of a device interrupt.

35/40

20. Stack overflow not implemented.

-..J

15/20

19. Only one interrupt level (BR4)
exists.
Four interrupt levels exist.

05/10

18. PSW address, 177776, not implemen ted; must use instructionns MTPS
(move to PS) and MFPS (move from PS).

PSW address and MTPS and MFPS
implemented.

LSI/II

X
X

Table B-1

KDJll-A Programming Differences (Cont)
Processors

Feature

23/24

25. Due to their execution time, FPII
instructions can abort because of
a device interrupt. "I

44 04 34 LSI/ll

FP II instructions do not abort
because of a device interrupt.

15/20

35/40

45 70 60 KDJll-A

X
X

26. EIS instructions do a DATIP and
DA TO bus sequence when fetching
source operand.

t::7:'
I

05/10

EIS instructions do a DATI bus
sequence when fetching source
operand.

27. MOY instruction does just a DATO
bus sequence for the last memory
cycle.

MOY instruction does a DA TIP and
DA TO bus sequence for the last
memory cycle.
28. If PC contains nonexistent memory
and a bus error occurs, PC will
have been incremented.

If PC contains nonexistent memory
address and a bus error occurs, PC
will be unchanged.

29. If register contains nonexistent
memory address in mode 2 and a bus
error occurs, register will be incremented.
Same as above but register is
unchanged.

tlntegral floating point assumed on 11/23 and 11/24; FPllE assumed for 11/60.

Table B-1

KDJ11-A Programming Differences (Cont)
Processors

Feature

23/24

30. If register contains an odd value
in mode 2 and a bus error occurs,
register will be incremented.

If register contains an odd value
in mode 2 and a bus error occurs,
register will be unchanged.

04 34 LSI/ll

05/10

15/20

32. Op codes 075040 through 0753777
unconditionally trap to 10 as
reserved op codes.

Op codes 210 through 217 are used as
a maintenance instruction.

If KEY-II option is present, op
codes 75040 through 07533 perform
a memory read using the register
specified by the low order 3 bits
as a pointer. If the register contents
are a nonexistent address, a trap to 4
occurs. If the register contents are
an existent address, a trap to 10
occurs.
33. Op codes 210 through 217 trap to
10 as reserved instructions.

KDJll-A

Condition codes that are restored
after EIS/FIS interrupt abort are
indeterminate.

45 70 60

31. Condition codes restored to
original values after FIS interrupt
abort (EIS does not abort on 35/40).

t:l:j

35/40

X
X

Table B-1

KDJll-A Programming Differences (Cont)
Processors

Feature

23/24

44 04 34 LSI/ll 05/10

15/20

35/40

45 70 60 KDJll-A

34. Op codes 75040 through 75777 trap
to 10 as reserved instructions.

X
X

If KEY-II options is present, op
codes 75040 through 7577 can be used
as escapes to user microcode. If no
user microcode exists, a trap to 10
occurs.

35. Op codes 170000 through 177777 trap
to 10 as reserved instructions.

Op codes 170000 through 177777 are
implemented as floating-point
instructions.

~
I

X
X

Op codes 170000 through 1777777 can
be used as escapes to user microcode.
If no user microcode exists, a trap
to 10 occurs.

Op code 076600 used for maintenance.
36. CLR and SXT do just a DA TO
sequence for the last bus cycle.

X
X

CLR and SXT do DA TIP-DA TO sequence
for the last bus cycle.

37. MEM MGT maintenance mode MMRO
bit 8 is implemented.

MEM MGT maintenance mode MMRO bit
8 is not implemented.
38. PS <15:12>, nonkernel mode, nonkernel stack pointer and MTPx and
MFPx instructions exist even when
MEM MGT is not configured.

PS <15:12>, nonkernel mode, nonkernel stack pointer, and MTPx and
MFPx instructions exist only when
MEM MGT is configured.

X
X

Table B-1

KDJll-A Programming Differences (Cont)
Processors

Feature

23/24

39. Current mode PS bits <15:14> set
to 01 or 10 will cause a MEM MGT
trap upon any memory reference.

Current mode PS bits <15:14> set
to 10 will be treated as kernel
mode (00) and not cause a MEM MGT
trap.

44 04 34 LSI/II
X

05/10

15/20

35/40

45 70 60 KDJll-A

Current mode PS bits <15:14> se.t
to 10 will cause a MEM MGT trap
upon any memory reference.

40. MTPS in user mode will cause MEM
MGT trap if PS address 177776 not
mapped. If mapped, PS <07:05> and
<03:00> affected.

~
I

MTPS in nonuser mode will not cause
MEM MGT trap and will only affect
PS <03:00> regardless of whether PS
address 177776 is mapped.
41.

MFPS in user mode will cause MEM
MGT if PS address 177776 not mapped.
If mapped, PS <07:00> are accessed.
MTPS in user mode will not trap
regardless of whether PS address
177776 is mapped.

42. Programs cannot execute out of
internal processor registers.
Programs can execute out of internal
processor registers.

Table B-1

KDJll-A Programming Differences (Cont)
Processors

Feature

23/24 44 04 34 LSI/ll 05/10 15/20 35/40 45 70 60 KDJll-A
X

43. A HALT instruction in user or
supervisor mode will trap through
location 4.
A HALT instruction in user or supervisor mode will trap through location
10.

44. PDR bit <00> implemented.
PDR bit <00> not implemented.

PDR bit <07> (any access) not
implemented.

45. PDR bit <07> (any access)
implemented.

X
X

t::C
I

46. Full PAR <15:00> implemented.

Only PAR <11:00> implemented.

MMR3 <02:00> not implemented.

49. MMR3 <05:04>-IOMAP, 22-bit
mapping enabled-implemented.

X
X

50. MMR3 <03>-CSM enableimplemented.
X

MMR3 <05:04> not implemented.

X
X

48. MMR3 <02:00> -D space
enable-implemented.

MMR3 <03> not implemented.

X
X

47. MMRO <12>-trap-memory
management-implemented.
MMRO <12> not implemented.

Table B-1

KDJll-A Programming Differences (Cont)
Processors

Feature

23/24

44 04 34 LSI/ll

05/10

15/20

35/40

51. MMR2 tracks instruction fetches
and interrupt vectors.
MMR2 tracks only instruction
fetches.
52. MFPx %6, MTPx when PS <13:12> =
10 gives unpredictable results.

45 70 60 KDJll-A

X
X

MTPx %6, MTPx %6 when PS <13:12> =
10 uses user stack pointer.

tjC
......
Vol

53. The ASH instruction with a source
operand of octal 37 will shift
left 31 decimal times.

X:\:

The ASH instruction with a source
operand of octal 37 (shift left 31
decimal times) will cause the
register to be shifted right instead
of left.

)(

X§

54. The ASHC instruction with an octal
value of 37 (shift left 31 decimal
times) in source operand bits
<05:00> will shift the register left
31 times, regardless of the value of
bits <15,06> of the operand.

X:\:

The ASHC instruction with an octal
value of 37 (shift left 31 decimal
times) in source operand bits
<05:00> when bits <15:06> of the
operand are not zero, will cause
the register to be shifted right
instead of left.

X§

:\: DCJlI-AC hybrids marked 57-19400-08
§ DCJI1-AC hybrids marked 57-19400-04A

APPENDIX C
CONFIGURATION NOTES

C.I GENERAL
To ensure proper system operation, the configuration notes included in this appendix should be considered
when configuring a system using the KDJII-A CPU module and the FPJII-AA Floating-Point Accelerator (FP A) chip.
C.2

KDJ1I-A CPU MODULE CONFIGURATION NOTES
1.

The KDJ11-AA (M8192) does not support the FPJ11-AA (floating-point accelerator) chip. The
KDJ11-AB (M8192-YB) is a direct replacement for the KDJ11-AA and does support the
FP111-AA.

Customers who use third party peripherals that incorporate read-modify-write instructions for
register manipulation may experience a compatibility issue when upgrading their CPU from the
LSI-ll/23 to the LSI-ll/73 (KDFll-A to KDJ11-A).
NOTE
For customers using Digital peripherals, compatibility in upgrading a CPU is not an issue. Digital
peripherals do not require read-modify-write instructions for register manipulations. The readmodify-write instructions available on the LSI-II /7 3
(KDJ11-A) are as follows: ASRB, TSTSET and
WRTLOCK.

C.3 FPJll-AA FPA CONFIGURATION NOTES
The following configuration notes should be considered when installing the FPJll-AA on KDJ11-AB
modules (M8192-YB), or when a KDJII-AC module (M8192-YC) is installed in your system. KDJII-AC
modules include the FPJ11-AA.
1.

Neither RSTS/E nor lAS customers are able to use the FPJ11-AA on their KDJ11-A modules,
due to a design issue which impacts software that uses the alternate register set in conjunction
with floating-point store instructions.

Customers who have applications with intense DMA activity should ensure that their module
has a revision level of B2 or higher. The markings on the top of the handles should be checked
for the number M8192 on one handle and either YB or YC on the other handle.

When using an MXVII-BF (multifunction) module in a configuration that includes the
KDJ11-A and FPJll-AA, verify the current revision level on the MXVll-BF as Cl or higher
to ensure proper operation.

C-l

INDEX

A
Abort (ABORT), 4-6
Abort, function of, 4-17
Address Input/Output, (AIO) 4-4
Address Latch Enable, (ALE) 4-5
Addressing modes, 6-1
auto decrement, 6-9
autoincrement, 6-7
deferred, 6-13
direct, 6-4
double-operand, 6-3
index, 6-11
PC relative, 6-17
register, 6-6
single-operand, 6-3
AI/O coding, 4-4

Cache control
data path, 4-12, 4-17
register, 4-19
Cache memory, 1-27, 4-13
control register, 1-30,4-19
data, 1-27, 4-13, 4-22
description, 1-27, 4-21
error register, 1-32, 4-1 9
hit/miss register, 1-32, 4-23
operation, 4-21
parity, 1-29, 4-19, 4-21
timeout, 4-19
Cache miss, 4-5, 4-23
Clock (CLKl, CLK2), 4-5
Code, 8-1
coroutine, 8-] 4
position-dependent, 8-3
position-independent, 8-1
reentrant, 8-13
Configuration, 2-1
factory, 2-3
jumpers, 2-1
Console ODT, 3-1
commands, 3-3
input sequence, 3-3
invalid characters, 3-9
output sequence, 3-3
serial line interface, 3-2
timeout, 3-9
Continue (CONT), 4-5
CPU error register, 1-5

B
Bank Select (BS), 4-4
BEVNT signal, 2-3
Boot address, 2-3
Boot ROM set, 9-1
Buffer Control (BUFCTL), 4-5
Bus cycles, 4-6
AIO, codes for, 4-4
bus read, 4-7
bus write, 4-8
general-purpose read, 4-9
general-purpose write, 4-10
interrupt acknowledge, 4-10
non-I/O (NOP), 4-6
Bus, 4-6
read transaction, 4-7
receivers, 4-12, 4-24
transmitters, 4-12, 4-25
write transaction, 4-8

D
Data Address Lines (DAL), 4-6
Data Valid (DV), 4-5
Diagnostics, 9-6
Diagnostic LEDs, 2-4, 4-29
Direct Memory Access (DMA), 4-27
INDEX-1

E
Error message, 9-3
Event (EVNT), 4-6

F
Floating-point, 7-1
accelerator (FPJ11-AA), 7-1, C-l
accuracy, 7-7
address register, 7-6
addressing, 7-7
data, 7-2
data formats, 7-1
exception code register, 7-6
nonvanishing numbers, 7-1
status register, 7-3
undefined variables, 7-2
zero, 7-1
Floating-point instructions, 7-8
ABSD,7-10
ABSF,7-10
ADDD,7-11
ADDF,7-11
CFCC, 7-12
CLRD,7-12
CLRF,7-12
CMPD,7-13
CMPF,7-13
DIVD,7-14
DIVF, 7-14
LDCDF,7-15
LDCFD,7-15
LDCID,7-16
LDCIF,7-16
LDCLD,7-16
LDCLF,7-16
LDD,7-18
LDEXP, 7-17
LDF, 7-18
LDFPS,7-18
MODD,7-19
MODF,7-19
MULD,7-22
MULF,7-22
NEGD,7-23
NEGF,7-23
SETD,7-23
SETF,7-24
SETI,7-24
SETL,7-24
STCDF,7-25

STCDI,7-26
STCDL,7-26
STCFD,7-25
STCFI,7-26
STCFL,7-26
STEXP,7-27
STD,7-27
STF,7-27
STFPS,7-28
STST,7-28
SUBD,7-29
SUBF,7-29
TSTD,7-30
TSTF,7-30
Flush counter, 4-20

G
General-purpose codes, 4-9, 4-10
General-purpose read cycle, 4-9
General-purpose registers, 1-2
General-purpose write cycle, 4-10

H
Halt (HALT), 4-5
Halt option, 2-2
Help message, 9-3
Hit/miss logic, 4-23

I
I and D space, 1-16
Initialization, 4-27
Initialize (INIT), 4-3
Instruction, 6-21.
byte, 6-26
formats, 6-22
list, 6-27
symbols, 6-21
Instruction set, 6-21
ADC,6-43
ADCB,6-43
ADD, 6-49
ASH, 6-51
ASHC,6-51
ASL,6-38
ASLB,6-38
ASR,6-37
ASRB,6-37
BCC,6-60
BCS,6-61
BEQ,6-58
INDEX-2

BGE,6-62
BGT,6-63
BHI,6-63
BHIS,6-64
BlC,6-54
BlCB,6-54
BIS,6-54
BISB, 6-54
BIT, 6-53
BITB,6-53
BLE,6-63
BLO,6-64
BLOS,6-64
BLT,6-62
BMI,6-59
BNE,6-58
BPL,6-59
BPT, 6-71
BR,6-57
BVC, 6-60
BVS, 6-60
CCC, 6-80
CLC, 6-80
CLN,6-80
CLV, 6-80
CLZ, 6-80
CLR,6-31
CLRB,6-31
COM,6-32
COMB,6-32
CMP, 6-48
CMPB,6-48
CSM,6-75
DEC, 6-33
DECB,6-33
DIV, 6-52
EMT,6-70
HALT, 6-77
INC, 6-32
INCB,6-32
IOT,6-72
JMP, 6-65
JSR,6-66
MARK,6-73
MFPD,6-79
MFPI,6-79
MFPS,6-45
MFPT,6-78
MOV, 6-47
MOVB,6-47
MTPD,6-79
MTPI,6-79
MTPS, 6-46
MUL,6-52

NEG,6-34
NEGB,6-34
NOP, 6-67
RESET,6-78
ROL,6-40
ROLB,6-40
ROR,6-39
RORB,6-39
RTI,6-72
RTS, 6-68
RTT,6-73
SOB,6-67
SBC, 6-44
SBCB,6-44
SCC, 6-66
SEC, 6-66
SEN,6-66
SEV, 6-66
SEZ, 6-66
SPL,6-75
SUB,6-50
SWAB, 6-41
SXT,6-44
TRAP, 6-71
TST,6-35
TSTB,6-35
TSTSET, 6-36
WAIT,6-77
WRTLCK, 6-35
XOR,6-56
Installation, 2-16
Interrupt acknowledge cycle, 4-11
Interrupt and DMA control
direct memory access (DMR), 4-5
event (EVNT), 4-6
floating-point exception (FPE), 4-6
interrupt request (IRQ), 4-5
power fail (PWRF), 4-6
Interrupts and traps, 1-8, 1-9, 1-10

L
Line time clock register, 1-7, 4-2('
LSI bus
characteristics, 5-22
configuration, 5-26
DATBO,5-12
DATBI,5-12
DATI,5-5
DATIO,5-10
DATO,5-7
DMA,5-12
interrupts, 5-15, 5-16
loading, 5-23, 5-29
priority, 5-15
INDEX-3

M
Maintenance register, 1-7, 2-6, 4-27
Memory management, 1-10
addressing, 1-13, 1-14
fault recovery, 1-18, 1-22
I and D space, 1-16
implementation, 1-10
mapping, 1-10
page address registers (PAR), 1-18
page descriptor registers (PDR), 1-18
physical address construction, 1-15
register 0 (MMRO), 1-20
register 1 (MMRl), 1-21
register 2 (MMR2), 1-21
register 3 (MMR3), 1-21
registers, 1-16
MMRO,I-20
enable relocation bits, 1-20
error flags, 1-20
page address space bits, 1-20
page number bits, 1-20
processor mode bits, 1-20
reserved bits, 1-20
MMR1, 1-21
MMR2,1-21
MMR3,1-21
enable 22-bit mapping bit, 1-22
enable CMS instruction bit, 1-22
enable I/O map bits, 1-22
kernel, supervisor and user bits, 1-22
reserved bits, 1-22
Module pinout, 2-9
Memory system registers, 1-30, 4-19

Page address registers, 1-18
Page descriptor registers, 1-18
access control field, 1-19
bypass cache bit, 1-19
expansion direction bit, 1-19
page length field, 1-19
page wri tten bit, 1-19
reserved bits, 1-19
Parity error (PARITY), 4-6
Power-down routine, 2-8
Power-up circuit, 2-7
Power-up routine, 2-7
Predecode (PRDC), 4-5
Processor status word, 1-3, 1-4, 8-26
Program counter, 1-3
Program interrupt request (PIRQ), 1-6
Programming model, 1-2

s
Software, 1-40
Specifications, 2-18
Stack pointer, 8-3, 8-6
Status signals
abort (ABORT), 4-6
cache miss (MISS), 4-5
parity error (PARITY), 4-6
predecode (PRDC), 4-5
Stretch control (SCTL), 4-5
Strobe (STRB), 4-5
System control
address I/O, 4-4
bank select, 4-4
buffer control, 4-5
continue, 4-5
data valid, 4-5

N
Non-I/O (NOP) cycle, 4-6

T
TAG RAM, 4-23
Timeout, 4-19

Options, 2-10

w
Wakeup, 2-3

INDEX-4

EK-KDJ1 A-UG-002
KDJ11-A CPU Module User's Guide

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