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EK-KD11A-MM-001

March 1975

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Document:	KD11-A Processor Maintenance Manual
Order Number:	EK-KD11A-MM
Revision:	001
Pages:	188
Original Filename:	EK-KD11A-MM_001_KD11-A_Processor_Maintenance_Manual_197503.pdf

OCR Text

KD11-A processor
maintenance manual

EK-KDl lA-MM-001

KD11-A processor
maintenance manual

digital equipment corporation • maynard, massachusetts

1st Edition, September 1973
2nd Printing, October 1973
3rd Printing, February 1974
4th Printing, August 1974
5th Printing, December 1974
6th Printing, March 1975

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
UNIBUS

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page
CHAPTER 1

INTRODUCTION

1.1
1.2

SCOPE . . . . . . .
ORGANIZATION .

CHAPTER 2

MICROPROGRAMMING

2.1
2.2
2.3
2.4
2.5

SCOPE . . . . . . . . . . . . . . . . . . . .
BASIC PROCESSOR . . . . . . . . . . . . .
CONVENTIONAL IMPLEMENTATION
MICROPROGRAMMED IMPLEMENTATION
BASIC READ-ONLY MEMORY (ROM)

CHAPTER3

BLOCK DIAGRAM DESCRIPTION

3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.4.11.1
3.4.11.2
3.4.11.3

SCOPE . . . . . . . . . . . . . . .
INTERFACE . . . . . . . . . . . .
KYl 1-D Programmer's Console
Unibus Timing and Control
DATAPATHS . . . . . . . . . . . .
Data Paths, Multiplexers and Registers
Decoding . . . . . . .
Arithmetic Logic Unit
PS Register . .
Register (REG) . . . .
MICROCONTROL . . . . .
Condition Codes Input
ALU Control . .
Flag Control . .
U Branch Control
BUTMUX . . .
U WORD Control ROM and U WORD Reg
Microaddress Alteration
JAMUPP Logic . . . . .
PUPP Register . . . . .
BUPP & SR MATCH . .
Clock Logic
. . . . . .
Clock Pulse Generator
Clock Control
Clock Enable Gates

CHAPTER4

MICROPROGRAM FLOW DIAGRAMS

4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3

SCOPE . . . . . . . . . . . . . . .
HOW TO READ FLOW DIAGRAMS
Entry Point
. . . . . .
Microprogram Word . . . . .
Exit Points . . . . . . . . . .
Branch Microprogram Test (BUT)
Operation Symbols . . . .
FLOW DIAGRAM EXAMPLES . . . . . .

1-1
1-1

iii

2-1
2-1
2-2
2-3
2-5

3-1
3-1
3-1
3-2
. 3-12
.. 3-12
. 3-15
. 3-15
. 3-15
. 3-15
. 3-16
. 3-16
. 3-16
. 3-16
. 3-16
. 3-17
. 3-18
. 3-18
. 3-20
. 3-20
.. 3-20
. 3-21
. 3-21
. 3-22
. 3-22

4-1
4-1
4-2
4-2
4-3
4-3
. 4-11
. 4-12

CONTENTS (Cont)
Page
CHAPTERS

LOGIC DIAGRAM DESCRIPTION

5.1
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
5.2.1.4
5.2.1.5
5.2.1.6
5.2.1.7
5.2.1.8
5.2.1.9
5.2.1.10
5.2.1.11
5.2.1.12
5.2.1.13
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
5.3
5.4
5.5
5.6
5.7

INTRODUCTION . . . . . . .
PRINT FORMAT . . . . . . .
Circuit Schematic Format
Logic Flow ..
Module Pins
Print Prefixes . . . .
Signal Level Indicators
Flip-Flop Outputs
Inhibit Situations
Parentheses and Colons
Parentheses and Commas . .
Basic and Expansion Signals
Logic Symbols . . .
System Information
Jumper Information
Cable Connection
Wire List Format . . . . . .
Alphabetical Searches
Print References .
Etch Backpanel
Forward Searching ..
M7231,DATAPATHS,Kl MODULE .
M7232, U WORD, K2 MODULE . . . .
M7233, IR DECODE, K3 MODULE ..
M7234, TIMING, K4 MODULE
M7235, STATUS, KS MODULE . . . .

CHAPTER6

KYl 1-D PROGRAMMER'S CONSOLE

6.1
6.2
6.2.1
6.2.2
6.3

KYl 1-D CONSOLE
KYl 1-D CONSOLE BOARD
Print KYD-2, Display
Print KYD-3, Switches
CABLES . . . . . . . .

5-1
5-1
5-1
5-1
5-1
5-1
5-2
5-2
5-2
. . . . . 5-2
5-2
5-2
5-3
. . . . . . . 5-3
5-3
5-3
5-3
5-3
5-3
5-3
5-3
5-3
.. 5-21
.. 5-41
. . . . . 5-59
. . . . . 5-71

. . . . .
. . . . .

6-1
6-1
6-1
6-1
. . . . . 6-1

CHAPTER 7

PROCESSOR OPTIONS

7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.4.1
7.4.2
7.4.3
7.4.4

SCOPE . . . . . . . . . . . . . . . . .
KJl 1-A STACK LIMIT REGISTER
Functional Description . . . . . .
Detailed Description . . . . . . .
KMl 1-A MAINTENANCE CONSOLE .
Functional Description . . . . . .
Physical Description
Configurations . . . . . . . . . .
Power . . . . . . . . . . . . .
KWl 1-L LINE FREQUENCY CLOCK
General Description
Address Selector
Interrupt Control
Status Register .

7-1
7-1
7-2
7-3
7-4
7-7
7-7
7-8
7-8
. 7-11
. . . . . . 7-11
. . . . . . . 7-12
. . . . . . 7-12
. . . . . . . 7-14

ILLUSTRATIONS
Figure No.
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5

3-6
3-7
3-8
3-9

3-10
3-11
4-1

4-2
7-1

7-2
7-3
7-4

7-5

Title
Conventional Control Section, Simplified Block Diagram
Microprogrammed Control Section, Simplified Block Diagram
Basic ROM Structure . . . . . . . . . . . . . . . . . .
Microword Format . . . -.- . . . . . . . . . . . . . . .
KDl 1-A Priority Transfer Timing and Control for NPRs
KDl 1-A Priority Transfer Timing and Control for BRs
NPR Priority Transfer Timing Sequence . . .
BR Priority Transfer Timing Sequence . . . . . . .
KDl 1-A Bus Data XFER Timing and Control
KD 11-A DA TI(P) Bus Transaction Timing Diagram
KDl 1-A DATO(B) Bus Transaction Timing Diagram
KDl 1-A Power Up Timing Sequence . . . . . . . .
KDl 1-A Power Down Timing Sequence . . . . . .
U Branch Control Sequence, Simplified Branching Operation
KDl 1-A Processor Clock, Block Diagram
Basic Flow Diagram Symbols
Flow Diagram Example
. . . . . . . .
KDl 1-A Maintenance Console Overlay
KTI 1-D, KEl 1-E,F Maintenance Console Overlay
KWl 1-L Block Diagram . . . . . . . . . . .
Interrupt Request Section, Simplified Diagram
Status Register, Simplified Logic Diagram

Page
2-3
2-4
2-6

2-7
3-3
3-4

3-6
3-7
3-8
3-9

3-10
3-11
3-11
3-19

3-21
4-1

4-2
7-5
7-8
7-11
7-13
7-14

TABLES
Table No.
1-1
2-1
3-1
3-2

3-3
4-1

4-2
4-3
4-4
4-5
7-1

7-2
7-3
7-4

7-5
7-6

Title
Related Documents
...... .
Function of Microword Bits (U WORD)
PDP-11/40 Data Path Multiplexer Control
Table of Combinations, 74181 ~Arithmetic Logic Unit
KDl 1-A Functional Components
BUTCHART . . . . . .
Flow Diagram Example 1
Flow Diagram Example 2
Microwords (Numerical Order)
Microwords (Alphabetical Order)
Comparison of Address and SLR
Detecting Type of Violation ..
KMl 1-A Controls and Indicators for KDl 1-A Overlay
KMll-A Indicators for KTll-D and KEll-E,F Overlay
KM 11-A Configurations
Interrupt Control Flip-Flops . . . . · . . . . . . . . . .

Page
1-1

2-8
3-14
3-17
3-23

4-5
4-13
4-17
. 4-19

. 4-25
7-3
7-4

7-6
7-9
7-10
7-13

CHAPTER 1
INTRODUCTION

1.1 SCOPE
This manual describes the KDll-A Processor which is the basic component of the PDP-11/35 and PDP-11/40
computer systems. The processor is connected to the Unibus as a subsystem and controls time allocation of the
Unibus for peripherals, and performs arithmetic and logic operations through instruction decoding and execution.
The information contained in this manual pertains primarily to the processor itself, however, certain processor
options are also described (KYl 1-D, KJl 1-A, KMl 1-A, and KWI 1-L).
Table 1-1 lists the other manuals that are necessary for a complete understanding of the basic PDP-11/35 or
PDP-11/40 system.

Table 1-1
Related Documents
Title

Document
Number

Remarks

PDP-11/35 System
Manual

DEC-l l-H35SA-A-D

Describes overall PDP-11/35 system and includes
sections on installation, operation, and programming.

PDP-11/40 System
Manual

DEC-1 l-H40SA-A-D

Describes overall PDP-11/40 system and includes
sections on installation, operation, and programming.

K.El 1 Instruction Set
Options Manual

DEC-11-HKEFA-A-D

Covers the KE 11-E Extended Instruction Set and
KE 11-F Floating Instruction Set processor options.

KTI 1-D Memory
Management Option
Manual

DEC-11-HKTDA-A-D

Covers the KTI 1-D Memory Management Option.

1.2 ORGANIZATION
The description of the KDl 1-A Processor is divided into four major sections: microprogramming (Chapter 2), block
diagram (Chapter 3), flow diagrams (Chapter 4), and logic diagrams (Chapter 5).
Chapter 2 first discusses the processor and briefly covers the conventional method of implementing the instruction
set. The remainder of the chapter is devoted to a discussion of microprogrammed implementation, the basic
microprogram memory, and the structure of the microprogram word.

1-1

Chapter 3 describes the processor at a block diagram level and introduces the processor architecture by describing
the basic block diagram which illustrates all of the major logic elements and interconnections within the processor.
The narrative in this chapter is summarized by a table that lists each functional block on the diagram, describes the
block, and lists inputs and outputs to and from that block.
Most of the information required to follow a sequence of machine states on a flow diagram is contained in the flow
diagram itself. Chapter 4 is, therefore, divided into two major parts: The first part explains the format of the flow
diagram, and the second part provides examples of tracing instruction operations through the flow diagrams.
Chapter 5 is the last section covering the KD 11-A Processor. It provides a description of the processor logic and
includes an explanation of print set conventions.
Chapter 6 of this manual provides a complete description of the KYl 1-D Programmer's Console, with the exception
of operating procedures which are covered in the PDP-11/40 System Manual, DEC-l l-H40SA-A-D.
Chapter 7 describes three of the internal processor options that may be used with the KDll-A. These options
are: the KWl 1-L Line Frequency Clock, the KJl 1-A Stack Limit Register, and KMl 1-A Maintenance Console. The
other available processor options (KEl 1-E, KEl 1-F, and KTl 1-D) are included in the manuals listed in Table 1-1.
A complete drawing set is supplied with this manual in a companion volume entitled PDP-11 /40 System Engineering
Drawings. The drawing set includes the basic block diagram, microword format, function tables, flow diagrams, and
logic diagrams. Familiarity with the ISP notation (Paragraph 4.2 of the PDP-11/40 System Manual) as well as the
print format (Paragraph 5 .2 of this manual) will aid in understanding the prints.

1-2

CHAPTER 2
MICROPROGRAMMING

2.1 SCOPE
This chapter provides a general introduction to the microprogramming techniques used in the KDl 1-A Processor.
Because microprogramming is the key to KDl 1-A Processor operation, it is essential to understand the basic
techniques before attempting to use the block diagram, flow diagrams, and logic diagrams. This chapter first
describes the basic processor and briefly covers the conventional method of implementing the instruction set. An
introduction into microprogrammed implementation is then covered. The remainder of the chapter is devoted to a
discussion of the basic microprogrammed memory and the structure of the microprogrammed word.
2.2 BASIC PROCESSOR
A computer system must be capable of manipulating, storing, and routing data. The component of a computer that
operates on the data is the processor. Although the processor is designed to effect complicated changes to the data
that it receives, it actually consists of elements making only simple changes. The complex data manipulations are
achieved by combining a large number of these simple changes in a variety of ways.
The processor consists of logical elements, each element designed to perform a specific function. For example, some
elements store data, some read data from another part of the computer, and others perform simple modifying
functions such as complementing the data or combining two operands by either addition or by logical ANDing.
These simple basic operations can be combined into functional groups known as instructions. An instruction can
include a number of operations so that data can be combined, changed, moved, or deleted. The instructions can be
further combined into programs which use a number of instructions to construct even more complex operations.
The basic logical elements of a processor can perform only a small number of operations at one time. Therefore, to
combine a number of these operations into an instruction, the instruction must be divided into either a series of
sequential steps or into groups of functions that can be performed simultaneously. One method of describing the
procedure the processor uses to execute an instruction is to call each operation (or group of operations) a machine
state. An instruction then becomes a sequence of machine states which the processor always enters in a specific,
predetermined order, depending on the individual instruction.
The processor can be divided into three general functional parts: the INTERFACE section, which exchanges data
with devices external to the processor; the DATA PATHS section, which performs data handling functions; and the
MICROCONTROL section, which includes the logic that determines which operations are to be performed during a
particular state and what the next machine state should be. (These sections of the processor and their component
elements are shown on the KDl 1-A Processor Block Diagram, drawing B-BD-KDl 1-A-BD.) The INTERFACE section
consists basically of logic necessary for transferring data between the processor, the Unibus, and the programmer's
console. The DATA PATH and MICROCONTROL sections interact to perform the three main processor functions
of data storage, modification, and routing.

2-1

In order for the processor to combine data operands, it must be capable of storing data internally while
simultaneously reading additional data. The processor often stores information about the instruction being executed,
about the program from which the instruction was taken, and about the location of the data being handled, in
addition to storing a number of data operands. When the processor must select some of this internally stored data, or
store new data, the MICROCONTROL section provides the required control signals to initiate appropriate actions
within the data storage section.
Data manipulation is performed both on data that remains within the processor and on data being transferred
between the processor and the rest of the system. In some instances, the data remaining within the processor is used
to control the processor by providing in£!1tS to the sensing logic in the MICROCONTROL section. The various logic
elements that actually modify data are controlled by signals from the MICROCONTROL section which selects the
particular operation to be performed.
Interconnections between the logic elements that store data and the logic elements that manipulate data are not
fixed; they are established as required by the specific machine state. The MICROCONTROL section generates signals
that cause data routing logic elements to form appropriate interconnections within the processor and between the
INTERFACE and DAT A PATHS sections of the logic.
2.3 CONVENTIONAL IMPLEMENTATION
Before attempting to understand the microprogramming implementation of the MICROCONTROL section, which is
the key to the KDl 1-A Processor, it is advantageous to reveiw the conventional method of implementation which
uses combinational logic networks to produce the necessary control outputs.
In a conventional processor, each control signal is the output of a combinational network that detects all of the
machine states, as well as other conditions, for which the signal should be asserted. The machine state is represented
by the contents of a number of storage elements (such as flip-flops) which are loaded from signals that are, in turn,
outputs of combinational networks. The inputs to these networks include: the current machine state, sensed
conditions within the processor, and sensed external conditions.
The number of logical elements in a conventional processor is often reduced by using logic networks to generate
intermediate signals that can be used to produce a variety of control signals and/or machine states. Unfortunately,
while this sharing of logic reduces processor size, it increases the complexity and makes it more difficult to
understand the processor logic because it is no longer obvious what conditions cause each signal. In addition, the
distinction between sequence control and function control is often lost, making it more difficult to determine
whether improper operation is caused by a faulty machine state sequence or by erroneous control signals within an
otherwise correct machine state.
A simplified block diagram of a conventional control section of a processor is shown in Figure 2-1. The Instruction
Register (IR) and associated decoding logic determine the logic function (instruction) that is to be performed. The
major and minor state identification logic serves as a sequence control to determine the order of functions to be
performed. The major state logic selects the major operation to be performed, such as Fetch (obtain an instruction),
Source (obtain the source operand), Destination (obtain the destination operand), Execute (perform the action
specified by the instruction), or Service (handle required interrupts, traps, etc.).
Within each major state, the processor MICROCONTROL section must perform several minor operations. For
example, the Fetch major state obtains an instruction from core memory. Minor states during Fetch
include: retrieve the instruction from memory, update the Program Counter, load the Instruction Register, and
decode the instruction.
Finally, a set of subcommands must be generated to perform the elemental operations required by a minor state.
The subcommand set that is selected is dependent on which major and minor states have been selected by the state
control logic.

2-2

The sequence control of the processor (major state, minor state, and subcommand set logic) is practical only if a
well-defined set of elementary operations is generated. This is the function of the state control logic shown in Figure
2-1. The state control consists of a complex array of combinational logic that monitors the output of the IR decoder
which defines the instruction, the current machine states (major and minor), and external sources (state of Processor
Status Register, console switches, Unibus signals, etc.) to set the required major and minor machine states at the
occurrence of each system clock pulse. It should be noted that the state control logic selects the next elementary
operation as a function of the current operation and external conditions.
Although the KDl 1-A Processor does not employ the type ofMICROCONTROL section discussed in this paragraph,
the concepts presented serve as a review of conventional control and are a desirable starting point from which to
discuss the principles of microprogramming. In both cases, the prime function of the MICROCONTROL section is
the same; only the hardware implementation differs.

ON
OFF

MACHINE
STATE

MAJOR
STATE
IDENTIFICATION
SUB
COMMAND

IR
DECODE

~+--+--GENERATOR

SUB
} COMMAND
SET

MINOR
STATE
IDENTIFICATION
HISTORY
11-1656

Figure 2-1 Conventional Control Section, Simplified Block Diagram

2.4 MICROPROGRAMMED IMPLEMENTATION
When the control system is implemented by microprogramming techniques, each control signal is completely defined
for every machine state. The section of the processor that selects the control signals can thus be implemented as a
storage device (read-only memory). This memory is divided into words; there is a separate word for each machine
state. Each word, in turn, contains a bit for every control signal associated with the related machine state. During
each machine state, the contents of the corresponding word in the read-only memory is transmitted on the control
lines. For most control signals, the output of the memory is the control signal and no additional logic is required.
The heart of the microprogrammed processor is the read-only memory (ROM) which stores a copy of the required
control signals for each machine state and a list of the machine states to follow the current state. Each word in the
ROM defines an elementary operation and the bit pattern within the word corresponds to subcommands. All that is
required to generate a unique set of subcommands is to read out the contents of a location in the ROM. To generate
a sequence of elementary operations, the address input to the ROM is changed with each system clock pulse. Some
of the bits in the ROM are used to define the next location to be read, often depending on conditions sensed by the
processor.
Each microprogram word that defines an elementary operation or machine state is referred to as a microword
(sometimes referred tO' as a microinstruction). Sequences of microwords are referred to as microroutines. The
register that defines which microword is to be read is referred to as the microprogram pointer.

2-3

An instruction fetched from core memory is loaded into the Instruction Register, decoded, and used in generating a
microprogram address that points to the starting location of a group of microroutines stored in the ROM. When the
microroutines are executed, the required subcommand sets are produced to activate other elements within the
processor, such as DATA PATHS or Unibus control in the INTERFACE section.
The microprogram may be viewed as a group of hardware subroutines carefully designed to implement the
PDP-11/40 instruction set and permanently stored in the ROM.
In order to maintain proper sequencing of a microroutine, each microword contains an address field for the next
microword. However, provisions are made to modify this address when it is required to branch to other microwords
or microroutines because of conditions sensed within the processor (e.g., instruction, address mode, interrupt flag,
etc.).
A simplified block diagram of the microprogrammed control logic is shown in Figure 2-2. As can be seen on the
diagram, the instruction loaded into the Instruction Register (IR) from core memory is decoded to provide a ROM
address. This address causes a specified control word (microword) to be retrieved from the ROM and loaded into a
Buffer Register. This microword contains the control fields used by the processor to perform the selected function.
The microword also contains a next address field and a branch test field which are fed back to the ROM Address
Generator to select the next microword in the sequence. The microword present in the Buffer Register operates on
the machine while the next microword in the sequence is being fetched.
IR

MACHINE
IR
1-----~STATES
DECODE

ROM
ADDRESS
GENERATOR

BRANCH TEST
FIELD

NEXT ADDRESS
FIELD

ROM
ADRS
REGISTER

ON
CLOCK

CONTROL
ROM

t----~

OFF

CONTROL WORD REGISTER

I ..

,rn

~---CONTROL

FIELDS

Figure 2-2 Microprogrammed Control Section, Simplified Block Diagram
2-4

11-1ss7

The combination of the next address field and the branch test field controls the sequence of microroutines. The next
address field provides a base address which selects the next microword to be used in the normal sequence. However,
this base address can be modified prior to being loaded into the microprogram Address Register.
Before discussing the address modification, it is important to understand that modification occurs prior to storage in
the ROM ADRS Register and, therefore, is performed on the subsequent next address (the next, next address). For
example, microword 1 in the sequence contains an address pointing to microword 2, and microword 2 contains an
address pointing to microword 3. When microword 1 is being operated on, the next address field (microword 2) is
already present in the ROM ADRS Register and, therefore, cannot be modified. However, when word I is being used
and the address for word 2 is in the ROM ADRS Register, the address for word 3 can be modified between the ROM
output and the ROM ADRS Register.
The branch test field of the microword specifies conditions to be tested and controls when the test is to occur; the
conditions determine to what location the microprogram is to branch. Logic within the processor permits testing of
the Instruction Register, flags, and other internal and external conditions to determine if branching is required. If a
branch is necessary, processor logic modifies the address of the next ROM microword. After the modified address
has been loaded into the ROM ADRS Register, a branch occurs to the new location and the specified microword is
retrieved from the ROM.
2.5 BASIC READ-ONLY MEMORY (ROM)
The microprogram read-only memory (ROM) contains 256 56-bit words. During each processor cycle, one word is
fetched from this ROM and stored in a Buffer Register. The outputs of the Buffer Register are transmitted to other
sections of the processor to act as control signals or to be used as the address of the next microword. The first eight
bits of every microword (07 :00) are used to hold the address of the next microword to be used. The remaining bits
(56:09) are control bits. (Bit 08 is reserved for use with extended ROM addresses for Extended Instruction Set
options.)
Figure 2-3 illustrates the basic structure of the microwords in the ROM. The detailed format of the microword is
shown in print D-BD-KDl 1-A-BD and in Figure 24. Note that this format is identical for all 256 microwords in the
ROM. The function of each bit position in the microword is described in Table 2-1.
NOTE
In the KDl 1-A Processor documentation, the prefix MICRO
(from the Greek Mu) is abbreviated as U (similar toµ). The U
abbreviation appears in the names for the microword buffer (U
WORD), in the ROM ADRS (Microprogram Pointer, UPP), and
in other logic block names and signal names.

2-5

DETAILED FORMAT OF THE
56- BIT MICROWORD IS
SHOWN IN FIGURE 2-4

1 CLK
I

FORMAT

I CLKS I BUS
I

DAD

SPS

I SALU
I

II SD , SB II UBF

SBC

RIF

000

MICROWORD
ADDRESS
(OCTAL)

001

002
I

I
I

256 56-BIT
MICROWORDS
I

I
I

375

376

377
56

00
11-2124

Figure 2-3 Basic ROM Structure

2-6

CLOCK LENGTH CONTROL . - - - - - - - - - - - - A L L O W S MICROPROGRAM TO
SELECT ONE OF THREE CLOCK LENGTHS

CLOCK OFF-ALLOWS MICROPROGRAM TO TURN
OFF THE PROCESSOR CLOCK

CLK L 1

CLKLO

CLKOFF

CLKIR

WRH

WRL

CLKB

CLKO

SPECIFIES TYPE OF DATA
TRANSFER ON UNIBUS

ALLOWS CLOCKING THE UNIBUS DATA
INTO THE INSTRUCTION REGISTER

_ --~---!
1

ALLOWS CLOCKING THE BUS
ADDRESS REGISTER

CLKBA

C1 BUS

----,

,--r::=;-

COBUS

ALLOWS INITIATING DATA
TRANSFER ON UNIBUS

BGBUS

ALLOWS CLOCKING DMUX (15:00)
INTO THE B REG.

~-----------ALLOWS

SALU3

SALU2

SALLI 1

SALUO

SBC3

SBC2

SBC1

DAD2

DAD1

DADO

SPS2

SPS1

SPSO

SALUM

I 7 OJ INTO THE

SELECTS LOADING
AND CLOCKING OF
THE PROCESSOR
STATUS WORD
(PSW)

DATA PATH (eg: MODIFY ALU

OPERATION AS A FUNCTION OF [IR]

SELECTS
MODE OF
ALU OPERATION
(ARITHMETIC
OR LOGICAL I

GENERAL REG.

WRITING D"'UX (15.81 INTO THE GENERAL REG.

SBCO

DAD3

DAD(3:0l-D!SCRETE ALTERATION
OF DATA-ALLOWS MICROPROGRAM
TO ALTER OPERATION OF THE

OUTPUT INTO THE D REG.

ALLOWS WRITING DMUX

~--~-----'~

I " L """ '"'"''""""

I "

SBMH1

SBMHO

SBMLI

SBMLO

SDM1

SOMO

SBAM

UBF4

UBF3

UBF2

UBF1

UBFO

~--~-~ ~ ~-------~--------~
ALLOWS MICROPROGRAM TO
SPECIFY CONSTANTS TO BE
INSERTED IN BIN OF ALU

SELECTS OPERATION TO BE
PERFORMED IN THE
ARITHMETIC LOGIC UNIT
(ALU) eg. (ADD, SUB, etc. I

SELECTS INPUTS SELECTS INPUTS
OF HIGH SIDE
OF LOW SIDE
OF THE BMUX
OF THE BMUX
I 15:81
I 7: OJ

VIA BMUX

ALLOWS MICROPROGRAM TO SPECIFY
GENERAL REGISTER ADDRESS IF
ENABLED BY SRI (BIT 13)

I
L

rT
SRS

SRO

SELECTS
INPUTS
OF BUS
ADDRESS
MUX

UBF(4 0) -M!CROBRANCH FIELD-ALLOWS
MICROBRANCH CONDITION TO BE TESTED (BUTI

UP: 9 } DISABLES MAI~! CONTRO. L STORE
ALLOWING AN .~ux. CONTROL TO
SPECIFY MICRO INSTR

~--------~--------~

SELECTS
INPUTS
OF DMUX

,.-----,----,.----~----..

SRBA

SRI

RIF3

RI F2

RI Fi

R!FO

UPF7

IL_____ ~~~~~~ g; ~~No~RT2L BREE~~SETDE:~iDRESS

UPF6

UPF5

UPF4

UPF3

UPF2

UPF1

UPFO

UPF I 7:01-8 BIT NEXT ADDRESS FIELD. USED TO SPECIFY ADDRESS
OF NEXT MICROINSTRUCTION TO BE EXECUTED BUT MAY BE
MODIFIED AS A RESULT OF A BRANCH TEST.

ALLOWS IR (2:01 TO BE USED AS A
SOURCE OF GENERAL REGISTER ADDRESS
ALLOWS IR (8 61 TO BE USED AS A
SOURCE OF GENERAL REGISTER ADDRESS
11- 1620

Figure 24 Microword Format

Table 2-1
Function of Microword Bits (U WORD)
UBit

Mnemonic

Meaning and Function

56
55

CLKLl
CLKLO

Clock length control. Pennits the microprogram to select one of three clock
lengths.

CLKOFF

Permits the microprogram to tum off the processor clock.

CLKIR

Pennits clocking Unibus data into the Instruction Register (IR).

52
51

WRH
WRL

Permit writing the Data Multiplexer data into the general registers. WRH writes
the high-order byte; WRL writes the low-order byte.

CLKB

Permits clocking the entire Data Multiplexer (full word) into the B Register.

CLKD

Permits clocking the ALU output into the D Register.

CLKBA

Permits clocking the Bus Address Register.

47
46

ClBUS
CO BUS

Specify the type of data transfer on the Unibus.

BG BUS

Initiates data transfer on the Unibus.

44
43
42
41

DAD3
DAD2
DADl
DADO

Discrete alteration of data. Permit the microprogram to alter operation of the
data path. For example, modifying the Arithmetic Logic Unit (ALU) operation
as a function of the Instruction Register.

40
39
38

SPS2
SPSl
SPSO

Select loading and clocking situations on the Processor Status (PS) word.

SALUM

Selects the mode of ALU operation (mode can be either arithmetic or logical).

36
35
34
33

SALU3
SALU2
SALUl
SALUO

Select the operation to be performed by the ALU, such as add, subtract, etc.
This selection can be modified by the DAD code noted above.

32
31
30
29

SBC3
SBC2
SBC!
SBCO

Permit the microprogram to specify the constants to be inserted into the B input
of the ALU by way of the B Multiplexer.

28
27

SBMHl
SBMHO

Select the inputs of the high-order byte of the B Multiplexer.

2-8

Table 2-1 (Cont)
Function of Microword Bits (U WORD)
U Bit

Mnemonic

26
25

SBMLl
SBMLO

Select the inputs of the low-order byte of the B Multiplexer.

24
23

SOMl
SOMO

Select the inputs of the 0 Multiplexer.

SBAM

Selects the inputs of the Bus Address Multiplexer.

21
20
19
18
17

UBF4
UBF3
UBF2
UBFl
UBFO

Represent microbranch field. Select the microbranch condition to be tested.
This test is referred to as the Branch Microprogram Test (BUT).

SRS

Permits bits (8:6) of the Instruction Register to be used as the source of the
general register address.

SRO

Permits bits (2:0) of the Instruction Register to be used as the source of the
general register address.

SRBA

Permits bits (3 :0) of the Bus Address Register to be used as the source of the
general register address,

SRI

Enables RIF (3 :0) of the microword for general register address.

Permit microprogram to specify general register address, provided these bits are
enabled by SRI (bit 13).

10
09

RIF3
RIF2
RIFl
RIFO

07
06
OS
04
03
02
01
00

UPF7
UPF6
UPFS
UPF4
UPF3
UPF2
UPFl
UPFO

Represent an 8-bit next address field that is used to specify the address of the
next microinstruction to be executed. However, it may be modified as the result
of a BUT. The U08 bit is for UPF8 and is provided for the KEl 1-E option.

Meaning and Function

2-9

CHAPTER 3
BLOCK DIAGRAM DESCRIPTION

3.1 SCOPE
This chapter introduces the KDl 1-A Processor architecture by describing the basic block diagram which illustrates
all of the major logic elements and interconnections within the processor.
The block diagram (drawing D-BD-KDl 1-A-BD) has been divided into three major functional groupings:
INTERFACE, DATA PATHS, and MICROPROGRAM CONTROL. All of the components in each of these segments
are covered in detail in succeeding paragraphs. Paragraph 3.5 contains a tabular listing of all components on the
block diagram and includes a brief physical description as well as related inputs and outputs. This abbreviated
summary can be used as a quick reference once the more detailed description of the block diagram is understood, or
it can be used for a quick overview of the KDl 1-A Processor by those who are already familiar with PDP-11
processors and microprogramming techniques.
The block diagram format provides blocks with major functions titled, and with major data and control
interconnections, as well as specific clock and microcontrol signals indicated. In the lower right hand corner of each
block is a K- reference which indicates the module schematic or schematics on which the contents of the block can
be found. For example, Kl-7 indicates sheet 7 of the Kl, or M7231 module print; K2 indicates several sheets on the
K2, or M7232 module print. The details of logic operation are contained in Chapter 5.
3.2 INTERFACE
The first section of the processor shown on the block diagram is the INTERFACE section which is used to
interconnect the KDl 1-A Processor with other components of the PDP-11/40 system. Each of the functional blocks
shown on the INTERFACE portion of the block diagram is covered in the following discussion.
3.2.1 KYl 1-D Programmer's Console
The KYl 1-D Programmer's Console is an integral part of the PDP-11 /40 system and provides the programmer with a
direct system interface. The console allows the user to start, stop, load, modify, or continue a program. Console
displays indicate data and address flow for monitoring processor operations. The console control logic is part of the
processor INTERFACE section, while the Switch Register, the DATA display, and the ADDRESS display are part of
the KYl 1-D console.
The Switch Register is located on the KYl 1-D console and consists of the manually-operated switches with resistor
pull-ups gated through 8881 drivers to the Unibus. During console operation, the Switch Register is addressed on the
Unibus via a microroutine. When the Switch Register address is decoded, the driver gates are enabled, allowing the
contents of the Switch Register to appear on the Unibus.

3-1

The DATA display indicates the output of the processor Data Multiplexer (DMUX) which selects information from a
variety of sources within the processor (e.g., the Unibus, the ALU output, and BUS RD). The display consists of
light-emitting diodes (LEDS) and associated current limiting resistors mounted in the programmer's console. The
indicators are connected to the processor by cables. The output line of the Data Multiplexer [D MUX (15:00)]
always controls the display, but since the multiplexer can select multiple inputs onto its output line, displayed
information is varied.
The ADDRESS display indicates the contents of the processor Bus Address Register (BA Register). This display also
consists of LEDS and current limiting resistors mounted on the console and connected to the processor by cables.
Note that there is no multiplexing involved with the ADDRESS display as there is with the DATA display. Although
it is possible to load specific data into the Bus Address Register for display, the display usually indicates the last used
Unibus addresses.
Console control logic is associated with the programmer's console operational switches that provide such manual
functions as start, halt, load address, examine, deposit, and continue. The console contains the manual switches and
associated set-reset flip-flops used for preliminary contact bounce filtering. However, primary console control is
handled by the processor either by means of the microprogram, or by combinational· logic and flag flip-flops. The
microprogram senses switch activation and branches to the specific routine required. The flags accommodate the
special needs of the START and CONT switch sequences as well as the incrementation requirements of consecutive
EXAM or DEP sequences.
The remaining functional components of the INTERFACE portion of the processor are the Unibus timing and
control, the bus terminator and connector module, and the Unibus drivers and receivers.
3.2.2 Unibus Timing and Control
The Unibus timing and control logic provides the required processor control of the Unibus, controls data transfer
functions, bus ownership functions, and other miscellaneous functions. The control logic includes drivers and
receivers for Unibus signal lines as well as timing and priority logic. Combinational logic, pulse circuits, and discrete
flip-flops provide control for data transfers (DATI, DATIP, DATO, DATOB) between the processor and the Unibus
with associated error checking (odd address, memory parity, stack overflow) and correction (data timeout).
In addition to the data transfer function, the Unibus timing and control logic provides the necessary control for bus
ownership, transfer of bus ownership for non-processor requests (NPRs) and bus requests (BRs), and the timeout
function for non-response conditions. The logic also provides power-fail timing related to BUS AC LO, BUS DC LO,
and BUS INIT signals. Combinational logic, which includes a number of one-shot timing circuits, sequences these
signals for power on and power off conditions.

Bus ownership is arbitrated by the processor on a priority basis. The highest priority is the NPR, followed by BR7,
BR6, BR5, and BR4. In order for a device to gain bus ownership, its priority must be greater than that of the then
current bus master. A flowchart showing the process of arbitrating bus ownership for NPRs is shown in Figure 3-1
and for BRs in Figure 3-2. The timing sequence on the Unibus for NPR transfers is shown in Figure 3-3, and the
timing sequence for BRs is shown in Figure 34.
A device requests bus ownership by asserting its associated request line, either NPR or BRn. The request is
acknowledged when the processor asserts a corresponding bus grant line, NPG or BGn. The bus grant signal causes
the requesting device to then assert SACK, which is sent back to the processor. The processor has been asserting the
BBSY signal up to this time, and when it receives SACK in response to BGn, it drops BBSY. On an NPR, BBSY is
dropped on the next <;LK BUS or P CLR MSYN after the NPR flag is set. However, the requesting device reasserts
BBSY as soon as the processor drops it, and the requesting device is now the bus master. Several devices may share a
common BR priority and request bus ownership simultaneously. In that event, the device closest to the processor
has the higher priority since each BG and NPG line is serially wired through every device on the Unibus. When a
device asserts a BR or NPR line, it also opens the BG or NPG line to the device next to it, on the side opposite from
the processor.

3-2

FROM
DEVICE

NOTE 1

(-AC LO)* !-OATIP) * - (SACK+ NPR (1) +GRANT BR)* CLK NPR

K4-5

PROC ACTION

NOTE 2
BBSV(1) * (CLK BUS+ PCLR MSYN)

,~ =···-"~

NEGATE BUS BBSY
AT THIS TIME THE DEVICE
WILL ASSERT BUS BBSV AND
NEGATE SACK.

DEVICE
BUS CYCLE

DEVICE WILL RELEASE BUS BY
NEGATING BUS BBSY

- (SACK+ BUS BBSY + SSYN +GRANT)

K4-5
BBSY +- 1

INHIBIT BUS FLOP
FROM TRIGGER ING
MSYN DELAY CLOCK

NPR ,___ 0
TSACK +--0
NOSACK +-0

K4-5

NOTE 3
PROCESSOR TAKES CONTROL
OF BUS AND INITIATES

(SEE DATA XFER FLOWS)

BUS CYCLE WHICH WILL
RESTART CLOCK.
II- 1680

Notes:
1. NP Rs are clocked frequently to determine if NPR
Service needed. NPG occurs.
a. BG BUS (1) - microword specifies a data transfer
b. ENPR CLK -- from EIS/FIS option
c. CLK IR - microprogram in FETCH
d. BUT26*P3 - microprogram 1ust entered SERVICE
e. -AWBY*SET CLK ·-clock restarting after bus cycle
f. P MSYN - A device has asserted BUS MSYN.
2. Microprogram either just starting or finishing a data XFE R
Bus Cycle or in Service when processor gives up the bus to
the NPR device.
a. CLK BUS- just starting processor Data XFER -clock will be turned off in this U word or succeeding
U word.

b PCLR MSYN - just finishing a Data XFEA Bus
Cycle·· clock is on but will go off when micro·
program reaches next Data XFER microroutine.
c. SERVICE - give Ufl the bus to do NPRs on
BUT26 and on AWBBY.
3. SACK timeouts will not cause a trap but will generate CLR
PTA which cleans up the NPR Priority XFER control
flip flops, and will restart Processor Clock.

Figure 3-1 KDl 1-A Priority Transfer Timing and Control for NPRs

3-3

NOTE 1

K4-6

- (NPR (1) +SACK+ GRANT BR)
NOTE 2
K...

100ns

========

COMPARE BR LEVEL WITH PS (7:5)
TO DETERMINE IF BR IS AT A
HIGHER PRIORITY LEVEL THE
THAN THE PROCESSOR

PTRD (0}

BRQ
BRn>PS (7:5)
BRPTR - 1
BRO

BBSY (1) .. -NPR

WAIT FOR MICROPROGRAM TO
BRANCH TO SERVICE AS A RESULT
OF BUT SERVICE .. BRPTR ( 1)

BUT 25 .. P2 • BAPTR (1}

{ SER07 LOC 320}

K5-4

BBSV (1)" -NPR" BAO* BRPTR(1)
K4-5

GRANT BR

K4-5

TSACK - 1

K4-6

K4-5

15usec

- BUS SACK

FROM

NOSACK ..-1

K4-6

CLR PTA

K4-5

DEVICE-~K4-5

75nsec

TSACK •· 0
NOSACK •· 0
BRPTR ~ 0

BRSV (1)
RESET PROCESSOR'S
BBSV ... 0
BUSY FLOP TO RELEASE
..__ _....,._ _ __, THE BUS

Note5:

K4-5
AT THIS TIME THE DEVICE ASSERTS
BUS BBSY AND TAKES CONTROL OF
THE BUS.
THE MICROPROGRAM TURNS OFF THE
CLOCK AND IS WAITING IN SERlO- LOC 22.
WHEN CLOCK IS RESTARTED RESULT OF BUT 07
IN SER 10WILL CLEAR BRSV.

'--.GOTO SHEET 2

1. CLK PTRD clocks a one·shot, PTRD 1100 ns) at the
following times:
a. CLK IA - start of each instruction
b. BUT26 - entering service microroutine
c. MSYN -· MSYN of every bus cycle if not
an overlap situation
2. At the leading edge of PTRD the request is stored, during
the 100 ns the request is arbitrated and the trailing edge

will set BRPTR if BRn>PS (7:5)

11-1681

Figure 3-2 KDl 1-A Priority Transfer Timing and Control for BRs (Sheet 1 of 2)

3-4

DEVICE HAS CONTROL OF
THE UNIBUS AS A RESULT
OF A BR TRANSFER

ACTIVE

PASSIVE RELEASE

RELEASE

- (BUS BBSY + SACK+ SSYN + GRANT)
FROM

BUS INTR

DEVICE

K4-5
D PERIPH
RELEASE

K4-5

K4-4

BBSY +-1

DEVICE PLACES
VECTOR ADDRESS ON
0 LINES DURING
INTERRUPT

B INTR

K4-2
SET CLK

K4·2
STARTS CLOCK
EXECUTION OF SER10
RESETS BASV (BUT07)

SET CLK

NOTE 1

INTR-1

INTR 111

STARTS CLOCK
EXECUTION OF SER 10
1. BUTS INTR
2. RESETS BRSV (BUT07)
3. R [14] .._BUS DATA (VECTOR)

350 ns

SER 11
TO

BUS SSYN

DEVICE
NOTE 2

PROCESSOR
ANSWERS
INTERRUPT
WITH SSYN

LDC 23

INTR 111

UPON RECEIPT OF
SSYN THE DEVICE
RELEASES THE BUS BY
DROPPING BUS BBSY
AND BUS INTR

Notes:

MICROPROGRAM BRANCHES
TO TRAP SERVICE MICROROUTINE

1. INTR normally gets reset by working BUT in trap service
microroutine {TAP16: BUT03*P1) K5-4

- (BUS BBSY +SACK+ SSYN +GRANT)

2. SSYN Timing:

.:~:~~.J---_.,-1_T_._t-==:f-~----

K4-5

DPERIPH
RELEASE

BBSY +-1

K4-5

I
BUS SSYN

~350 "'~

.._ _ _ _ _ _..
PROCESSOR TAKES
BACK CONTROL OF
THE BUS.

T= f gate delays on UNIBUS

Figure 3-2 KDl 1-A Priority Transfer Timing and Control for BRs (Sheet 2 of 2)

3-5

'1-1682

BUS NPR

BG BUS

CLK NPR

NPR(1 l

BUS NPG

CLK BUS

BBSY (1 l

BUS SACK

D SACK
TA
BUS BBSY

\fj

n
n

PERI PH RELEASE
NOTE:
1. Setting NPR conditional upon- ( DATIP + B AC LO)
2. From TA TO Te the NPR device has control of the Unibus

,,_ 2125

Figure 3-3 NPR Priority Transfer Timing Sequence

After a device has become bus master, it proceeds to transfer data on the Unibus. The sequence is shown on the
flowchart in Figure 3-5. The timing of data transactions are shown in Figures 3-6 and 3-7, for DATI and DATO,
respectively.
The power up sequence is shown on the timing diagram in Figure 3-8. BUS AC LO and BUS DC LO are generated by
the power supply and indicate the status of the input ac power and the derived de power. When BUS DC LO goes
high, it triggers a 20 ms one-shot, PWRUP INIT. The PWRUP INIT signal initializes all the processor logic and all the
Unibus devices. It also causes the microaddress 377 to be generated and set into the UPP Register in order to load it
with Os. The trailing edge of PWRUP INIT triggers the POWER RESTART signal if AC LO is not asserted. The
trailing edge of POWER REST ART causes a starting microaddress to be generated and set into the UPP Register,
starts the processor clock, and inhibits the initiation of a power down sequence for 3 ms, should BUS AC LO be
asserted.
The timing sequence of the power down sequence is shown in Figure 3-9. Powering down causes the power supply to
assert BUS AC LO followed by BUS DC LO. The BUS AC LO signal sets the LOWAC flip-flop, assuming the 3 ms
PWRDN DELAY signal is not present. With LOWAC (1) set, the next Pl or P3 clock pulse causes CLK PWRDN to
be generated, setting the PWRDN flag. The LOWAC flip-flop is reset on the next Pl or P3 clock pulse when PWRDN
(1) is asserted. At the completion of the current instruction, the PWRDN flag causes the microprogram to branch to
SERVICE and subsequently to the TRAP SERVICE microroutine. The power fail trap routine can call a subroutine
from memory that causes all volatile information to be saved and the program to be halted at a known location for
restarting. Meanwhile, the BUS AC LO signal causes a 15 ms AC LO signal to be generated, locking up the original
AC low condition which may or may not still be present. The BUS AC LO signal inhibits further NPR transactions.
Also, a 7 ms DELAY DC LO signal was triggered at the same time. The trailing edge of this signal pulses BUS DC
LO, which in turn generates PWRUP INIT, if BUS DC LO is not being asserted by the power supply. At the trailing
edge of PWRUP INIT, it is possible to enter the power up sequence if BUS AC LO indicates normal power again on
the bus. (Detailed examples of the power down and power up sequences are given in Chapter 5 in the discussion of
the logic on Sheet K5-8.)
3-6

BUS BR n

----i___ ~-----------1
* p.:LJ
I

[BUT 26
PTRD (I)

JOO

-~~~~I.
BR Q
BRPTR (I)

L.......tI

ns-

1-----------------~~~~~~~~~~~~~-

-~~~~~I

l__

•

[UREG) -----------1~~---S-E_R_0_7_ _"""'T"_ _S_E_R_0_8_ _~,--S-E_R_0_9-~-~I/

SER 11

SER 10

P2_jl_ Pl~>---------'
BRSV ( l ) _ _ J
GRANT BR _ _ __,

~..-----------f 1------------------1-

SACK~
-I f

BUS BG n
BUS

75ns

D SACK

BBSY (I)
BUS BBSY _ _ _ _ _ _

_.r:... - - - - - - - - - ~ f- - - - - - - _J ' - - - - - - - + -

CLKOFF

(I)~

r ~

IDLE (I) _ _ _ _ _ _ _...
NOTES·

1. TIMING SEQUENCE ASSUMES BRn

* BUS INTR

ENJOYS HIGHEST PRIORITY IN SYSTEM
2. ~DEVICE SENDS VECTOR ADDRESS ON UNIBUS D LINES WITH INTR
3.... PROCESSOR STORES VECTOR AND ACTIVATES SSYN
TO RESPOND TO DEVICE

B INTR

SETCLK
INTR (1)

1---------+-

~ ______.
--------_..~
~

~ _____.___

........._ __

'
1
BUS SSYN

=::j 350ns
11-1676

Figure 34 BR Priority Transfer Timing Sequence

BEG_IN

NOTE 1

CL KOFF (1)

CLKBA{1)

BGBUS (1)
K2-7
BBSY" DATO (8)

ALLOW CLK" RECLK INHIBIT

K4-2

CLK BA

BUS
0(15:00)

~~~FMC___.,

CLK BUS

NOTE2

NOTE3

OVERFLOW
SITUATION

ODD ADDRESS
SITUATION

BUT 37 • OVLAP CYCLE
+ALLOW CLK
K4-4

CATO+
OATOB

CKOVF ·- 1

CKODA ·-1

BUS-1

BC1 - 1

DATIP+
DATOB *BYTE INSTR

1
K4-4

K4-4

K44
NOTE 4

:~~~~OVERFLOW

~~~OA~ORESS

BBSY (1) ~BUS CO

!PROC RELEASE+ SSYN!
- - - - - - - - - - BBSY ( 1 ) - - - - + - BUSC1

----~----;----------·:~~v~,)-J

BUSSSYN

BBSY (1)

I
I

150ns

BUS STOP

BBSY

BUS FM BA
K4-5

K4-4 :
I

K4-2
BUS STOP

CLKMSYN +-----J
IDLE (1) • MSYN (1)

BUSA (17:00)
JBERR -· 1
K4-4

K4-3

SETCLK
•• FOR DETAILS ON BBSY
SEE THE PRIORITY
XFR CONTROL & TIMING
FLOW CHART

) - - - - - - NO MSYN----+ BUS MSYN
K4-4

K4-2

K4-6

RESTART
CLOCK

sons
K4-2

/- -

Notes:
1. CLKOFF. CLKBA. & BGBUS are b•ts in each micro
instruction and are asserted in U words that initiate
datatransfers(CLKOFF does not have to occur in
same U word as BGBUS & CLKBA i e., updating a
regdelaysturnmgofftheclock).

/
/

IDLE• 0

SWAIT• 0
K4-4

NOOAT• 1

/
/

K4-6

Odd Address situations are specified by the DAO code
and IR dec<Jde= bytemstr.

4. Processor has control of the Bus and 11 is now getting
ready to release it as a result of a NPR or BR transac·
tionalsoSSYN 1smactive

Pl+P3

2. Overflow s1tuat1ons are specified by the U word DAD
code and a reg.

3. Inhibit bus cycle 11 in FET04and not an overlap
situation or if m U word that delivers result during
a BIT+CMP+TST.

NO SSYN
RESPONSE

JAMMUPP
SEQUENCE

IF OATt (Pl CLOCK
--+UNIBUS DATA tNTO
TEMPORARY STORAGE AS
A FUNCTION OF UWORD
1 BREG
2 IREG
3 GPR

P CLR MSYN
K4-4

MSYN • 0
BUS• 0

ENO

ll-1679
TRAP
FLOWS

FC_.

Figure 3-5 K.Dl 1-A Bus Data XFER Timing and Control

3-8

[UREG]J

FET 04

FET 03

FET 02

BG BUS (1)

CLKOFF (1)

CLKBA(1)

CLKIR (1)

WRL(1)•WHR(1)

CLKB(1)

CLK BUS

CLK BA

RECLK

IDLE (1)

BWAIT(1)

BUS (1)
150ns==:r

MSYN (1)

BUS MSYN
DEVICE GATES DATA
ONTO UNIBUS D(15,00)

BUS SSYN

B SSYN

P CLR MSYN

CLK IR

CLK B
CLK MSYNA

--i--~~~i~:~-------------~ - ---------

OATIP(1) ____ j

NOTES: 1.
2.
3.
4.
5.
6.

EFFECTS OF GATE DELAYS AND F.F. RESPONSE NOT SHOWN
ASSUMES KD11-A HAS CONTROL OF THE UNIBUS [BBSY (11]
"CLOCK NPR REQUESTS: IF NPR (1) THEN BBSY ,__ 0
.. TRIGGERING DELAY TO CLOCK MSYN CONDITIONAL UPON
MACHINE STATE: -- (PROC RELEASE+ SSYN)" BBSV (1)
MSVN BEING SET TRIGGERS 15 USEC BUS TIMEOUT DELAY
INHIBIT SETTING MSVN IF BUS STOP ACTIVE: [RED ZONE OVFL +ODA ERR] TRAP

SCALE: 1INCH"'100 NSEC.
11-1677

Figure 3-6 KDl 1-A DATl{P) Bus Transaction Timing Diagram

3-9

[UREG)

CON 05

DEP 09

CON 06

BG BUS (1)

CLKOFF (1)

C1BUS (1)
CO BUS (1)

CLK BUS

BC1 (1)

BUS FM D

RECLK

IDLE (1)

BWAIT (1)

BUS (1)

**
' - - - - - - 150 ns - - - - " "

MSYN (1)

BUS MSYN

BUS SSYN

B SSYN

SET CLK

P CLR MSYN
NOTES:

1. EFFECTS OF GATE DELAYS AND F.F. RESPONSE NOT SHOWN
2. ASSUMES K011-A HAS CONTROL OF THE UNIBUS [BBSY(HJ
3. • CLOCK NPR REQUESTS. IF NPR (1) THEN BBSY ·- 0

4. •*TRIGGERING DELAY TO CLOCK MSYN CONDITIONAL
UPON MACHINE STATE: - {PROC RELEASE+ SSYN). BBSY (1)
5.

t MSYN BEING SET TRIGGERS 15 USEC BUS TIMEOUT DELAY

6. INHIBIT SETTING MSYN IF BUS STOP IS ACTIVE:
[RED ZONE OVFL +ODA EARi

TRAP

11-1678

7. SCALE: 1 INCH :o: 100 NSEC.

Figure 3-7 KDl 1-A DATO(B) Bus Transaction Timing Diagram

3-10

ON
POWER
OFF

K5-8 BUS DC L O - - - - - - - -

_ T ... 2ms

K5- 8 BUS AC LO
i + - - - - 20ms - - - - . i

K5-8 PWRUP INIT L

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...ro----70ms----<•-i._I_ _ _ _ _ _ _ __
K5-8 PWRRESTART H

.------------'I\~------- . - - - - - -U-2,...s
-U-2,...s

K4-3 JAMUPP

DELAY POWER DOWN
11-1668

Figure 3-8 KDl 1-A Power Up Timing Sequence

ON---..,
POWER

OFF

K5-8 BUS DC LO

K5-8 BUS AC LO

(----------------------------------

_ -...L_/__,\~

K5-8 LOWAC (1)

:::!

•

r.,__I

-\~'.

!--._
_ _._,,, . . . . - - - - - - - - - - - - - - - - - - - -

~/ ~---/__,;~f--------------------

K4-2 (P1 + P3JH _ _ _ __,_\_11_ _ _ _ _
K5-8 CLK PWRDN

K5-4 PWRDN (1)H -

~r-u

1,r\

~BUT 04 IN PWR FAIL TRAP SERVICE

_ _ _ _ _ _'_,_ _ _ _ __.
\

..---------.....

~----------......

•I.____________

K5-8 AC LO ONE SHOT _ _ _ _ _ _. , . , _ - _ ! - - - - - - - - - - l 5 m s - - - - - - - - -...
I

K5-8 DELAY DC LO -

______
'-_-}_.+----7ms--------.i.__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

::!

=u=2ms

K5-8 PULSE DC LO

•I

i + - - - - 20ms - - -..

K5-8 PWRUP INIT
NOTE: TIMING OF LOW AC, P1+P3, CLK PWR DN
PWR DN (1)

IS EXAGGERATED FOR CLARITY
THIS SEQUENCE IS VERY FAST
AND COMPLETES WITHIN A FEW
MICROSECONDS.

11-1669

Figure 3-9 KDl 1-A Power Down Timing Sequence

3-11

The microprogram interfaces directly with the Unibus timing and control logic. The start or error checking flip-flops
are loaded, either directly or conditionally from the microword. The loading of Unibus data and the deactivation of
MSYN occur as a function of the next microword after a DATI or DATIP transfer operation. The processor
transmits address and data information to the Unibus under control of the microprogram. Note, however, that bus
ownership, the power fail logic, and the Unibus data transfer operate asynchronously and are independent of the
microprogram.
The interface portion of the processor contains both bus transmitters (8881 gates) and bus receivers (380 gates) to
provide the necessary conversion so that processor and Unibus signals are compatible. The transmitters (drivers)
permit the processor to place groups of signals on the bus; the individual signals are noted on the block diagram on
the output line of the associated gate. These signals include the outputs of the Bus Address (BA) Register, the D
Register, the Processor Status (PS) Register, and the Switch Register. Inputs to the processor from the bus are gated
through the bus receiver to the D Multiplexer, which then routes the signals to the proper component within the
data paths.
The final functional component in the INTERFACE section of the processor is the bus terminator and connector
module, which interconnects system units and also provides the termination required by the Unibus. In the KD 11-A
Processor, a single set of slots (A09, B09) is provided for the Unibus interface and the processor is single ended. Note
that the Unibus Terminator module (M930) is located in, and powered from, the last device on the bus.
3.3 DATA PATHS
The DATA PATHS portion of the KDl 1-A Processor manipulates, stores, and routes data within the processor.
The prime element of the data path logic is the ALU which operates, both logically and arithmetically, upon input
data from the interface portion of the processor. To a certain extent, data path logic is ordered upon the ALU
because of the requirements to provide data to each of its inputs and to store, or otherwise use, its output. The ALU
and all other components in the processor data paths are described in the following paragraphs.
For the purposes of the following discussion, the term "Scratch Pad Register" refers to one of the 16 internal
processor registers shown on the block labeled REGISTER (REG). These registers are also referred to as the General
Registers.
3.3.1 Data Paths, Multiplexers and Registers
The Scratch Pad Register supplies operands for the ALU. These operands either come directly from an instruction
source or destination mode operation, or they are stored in the Scratch Pad Register during address calculations. In
either case, the ALU receives a direct input from the BUS RD (15 :00) line. This input is referred to as the A input.
In the Scratch Pad Registers, only one address may be accessed at a time, and simultaneous read and write
operations are not permissible. In order to provide the two ALU operands (when both operands come from the
Scratch Pad Register), it is necessary to provide temporary storage. This storage is provided by the B Register; the
contents of the B Register can be fed through the B Multiplexer (B MUX) into the B input of the ALU.
The ALU A input provides variable operands; the B input provides variable operands, constants, and swapped and
sign-extended byte operands. The A input usually comes from the Scratch Pad Register on the wire-ORed BUS RD
lines (as shown by the dotted OR gates on the block diagram). The Processor Status Register of the basic machine
and certain multiplexers with the KEl 1-E and KEl 1-F options are also connected to the A input.
The B input comes from the B MUX which receives its input from either the B constants or the B Register. The B
Register, in tum, receives its input from the D Multiplexer (D MUX) which has four possible inputs. Therefore, the B
input to the ALU comes from a variety of sources with two levels of multiplexing. These various inputs are discussed
in the following paragraphs.

3-12

The four inputs to the D MUX are: Unibus data lines BUS D (15:00), which permit the ALU to receive operands
from other devices within the system; the buffered BUS RD {15:00) lines, which permit operands from the Scratch
Pad Register; the output of the D Register, which is the output of the ALU and can permit the result of a previous
arithmetic operation to be used as an operand; and the shifted output of the D Register.
The desired D MUX output can be stored in the B Register, which, in turn, can be fed to the ALU by means of the B
MUX. Note that the buffered BUS RD signal can be fed through the D MUX into the B Register. This data path is of
special interest in the machine instruction for the register-to-register operations, where both the A and B inputs of
the ALU must come from the Scratch Pad Register. For example, the first operand passes through the D MUX into
the B Register for storage. The second operand can then be fed to the A input of the ALU, and the first operand fed
to the B input by means of the B MUX.
The B constants, which are applied through the B MUX to the ALU, provide elementary values (such as 18 and 2 8 )
for incrementation or decrementation throughout machine operation. They also provide other values such as the
Switch Register address, more complex constants such as trap vectors or masks for manipulating instruction offsets,
and the conditional constants which are a function of machine status and jumper selection.
The B input to the ALU can be either the B constants value or one of the four possible functions of the B Register.
The four B Register functions are:
a.

B Register - The contents of the register are applied directly to the ALU. Therefore, BIN (15 :00) of the
ALU equals B {15:08) and B (07:00).

B Extend - The B Register contents are gated so that bit 07 (MSB of the low-order byte) provides an
extension for the high-order byte. Note that in this case, the value in the high-order byte is either all ls
or all Os depending upon bit 07 of the B Register; the low-order byte is the B Register directly.

Byte Duplication - Either the low-order byte or the high-order byte may be duplicated. Therefore, BIN
{15:00) of the ALU equals either B {15:08) and B (15:08), or B (07:00) and B {07:00).

Byte Swapping -The high-order and low-order bytes may be exchanged. Therefore, BIN (15:08) of the
ALU equals B (07:00) and BIN (07:00) equals B {15:08) for the high byte and the low byte,
respectively.

The ALU provides an altered data output that is used for Unibus addresses and data, and by internal processor
registers such as the Scratch Pad Register and the Processor Status Register. The output of the ALU is stored in the
D Register and/or the Bus Address Register.
The D Register storage capability permits data which has been operated upon in the ALU to be fed around to the B
MUX for further manipulation, thus permitting data to be stored in another register {the B Register). This additional
path and storage capability is important because it is necessary for single or double operand register operations and is
very often necessary in iterative operations.
Operation of the ALU is also determined by the carry-in (CIN logic) and carry-out (COUT MUX) signals. The
carry-in signal does not come directly from the microprogrammed word but is a function of the microprogrammed
word and the conditions (usually the Instruction Register) that are enabled at specific locations in the
microprogrammed flow.
The Carry-out multiplexer (COUT MUX) provides multiplexing of the specific carry information normally used in
the PDP-11. The signals that can be selected are: COUT 15, COUT 07, ALU 15, and PS(C). The COUT 15 signal
represents the carry from a word operation; the COUT 07 signal represents the carry from a byte operation. These

3-13

signals are used for condition code inputs and rotate/shift operations. The ALU 15 signal is the bit 15 output of the
ALU which is used for rotate/shift operations. The PS(C) signal is the carry bit from the Processor Status Register.
The signal selected by the COUT MUX is clocked into an extension of the D Register which is called D(C). This
storage extension is used in rotate/shift operations and in certain arithmetic operations.
A summary of the functions of the BA MUX, the D MUX and the B MUX, and their associated control signals is
given in Table 3-1.
Table 3-1
PDP-11/40 Data Path Multiplexer Control
Function

Signal
BAMUX
Select BA Mux, bits (I 5 :00)
SBAM(O)
SBAM(I)

Select BUS RD data
Select ALU output
DMUX

Select D Mux, bits (15:00)
SDMl(O) * SDMO(O)
SDMl(O) * SDMO(I)
SDMl(l) * SDMO(O)
SDMl(I) * SDMO(I)

Select BUS RD data
Select Unibus data
Select D Register
Select D Register shifted right with D(C) shifted into bit position 15.
BMUX

Select B Mux Low, bits (07:00)
SBMLl(O) * SBMLO(O)
SBMLl(O) * SBMLO(I)
SBMLl(l) * SBMLO(O)
SBMLl(l) * SBMLO(l)

Select B (07:00)
Select B (07:00)
Select B (15 :8)
Select BC (07:00)

Select B Mux High, bits (15:08)
SBMHl(O) * SBMHO(O)
SBMHl(O) * SBMHO(I)
SBMHl(l) * SBMHO(O)
SBMHl (I) * SBMHO(I)

Select B (15:8)
Select B (07)
Select B (07:00)
Select BC (15 :8)

(a+b)*e

Selects B Register

(a+b)*f

Selects B Register with sign extension in high byte [B(I5:8) +- B(7)]

c*g

Swaps bytes

c*e

Duplicates high byte in low byte

d*h

Selects constant

a+b*g

Duplicate low byte in high byte

3-14

3.3.2 Decoding
The address and data decoding IOgic is a combinational logic network that decodes the output of both the D and BA
Registers. When the D Register output is decoded, the decoder senses whether or not the output (for both byte and
word segments) is 0 [D (15:00) = 0 H]. The Bus Address Register is decoded to determine if a processor address has
occurred, or if an address is less than specified values. It should be noted that the decoding logic decodes the BA
Register and not the Unibus address. In the first case, the processor addresses, which represent only those internal
registers that can be accessed by the processor itself, are used to gate Unibus responses for bus operations. If the
decoded address of the Processor Status Register or the console Switch Register, then either PS ADRS Hor SR
ADRS H is true. Other addresses also exist. If the decoded address is less than the specified value, then a stack
overflow violation may occur and the BOVFL signal is true. Stack limit errors are either yellow zone (warning) or
red zone (fatal) indications.
3.3.3 Arithmetic Logic Unit
The Arithmetic Logic Unit (ALU) is the heart of the data path logic. It performs 16 Boolean operations and 16
arithmetic operations on two 16-bit words. The ALU is controlled by six input signals. One signal, ALUM H, selects
either the logic or arithmetic mode of operation. Four signals (ALUSO through ALUS3) select the desired function.
The sixth signal is the output of the carry-in (CIN) logic. Basically, the ALU receives two 16-bit words as inputs
(AIN and BIN) and performs the operation selected by the six control signals. The output of the ALU is, therefore,
altered data which is used for Unibus addresses and data, and is also used by the internal processor registers such as
the Scratch Pad Register or the Processor Status Register. The output of the ALU is stored in the D Register or the
BA Register for use.
3.3.4 PS Register
The Processor Status (PS) Register is an 8-bit register that stores information on the current priority of the processor
[bits (07:05)], the result of the previous operation (condition codes bits N, Z, V, C), and an indicator for detecting
the execution of an instruction to be trapped during program debugging (T bit). The PS Register is located between
two basic data paths: D MUX (15:00) and BUS RD (15:00). The register is loaded from the D MUX. In addition,
the co11dition codes control logic provides inputs to the N, Z, V, and C bits. The register output is either gated
directly onto the Unibus (in cases where the processor has addressed the Unibus as an absolute address) or is gated
onto the BUS RD (15:00) line for use by the processor data paths. This latter case is used, for example, by the
condition code instructions which alter the contents of the Processor Status Register.
3.3.5 Register (REG)
The 16 internal processor registers comprise the Scratch Pad Register. Eight of these are programmable general
registers which include the Program Counter (PC) and Stack Pointer (SP). In the KD 11-A Processor, the additional
eight registers (not accessible to the program) are used for a variety of functions as shown on the block diagram.
Such functions include: intermediate address (TEMP), source and destination data (SOURCE, DEST), a copy of the
Instruction Register (IR), the last interrupt vector address (VECT), registers for console operation (TEMPC,
AD RSC), and a stack pointer for operation of the KTl 1-D Memory Management Option (SP USER).
In summation, the data path logic is the fundamental section of the processor; it performs data storage,
modification, and routing functions. The other two sections of the processor (interface and control) exist primarily
to support the data path logic.
An important aspect of the data path logic is its expandability. The D MUX signals represent an outgoing bus and
the BUS RD lines are a wired-OR input bus. Just as the Scratch Pad Register and the Processor Status Register are
connected between these two signal buses, other devices can also be connected between them. For example, the
KEll-E Extended Instruction Set option and the KEll-F Floating Instruction Set option are connected between
these two signal buses for arithmetic expansion of the basic processor.

3-15

3.4 MICROCONTROL
The final section of the block diagram is the microcontrol logic which provides the required control signals for the
data path logic and the interface logic. The prime element of the control logic is the read-only memory (ROM)
which provides the microwords. The bits in each microword (U WORD), in turn, control machine operation as
described in Chapter 2. Other elements within the MICROCONTROL section includes microaddress and
microaddress modification logic that receives inputs from the ROM, the Instruction Register with associated
decoding logic, various processor flags, and basic machine timing and flag control logic.
When an instruction is fetched from an external data storage location, the instruction enters the processor from the
Unibus, passes through the D MUX, and is loaded into the Instruction Register under microword control. The
output of the Instruction Register is decoded by combinational logic (IR DECODE) to provide the microbranch
code (BUBC) for several branch conditions and the discrete auxiliary signals required by the condition code logic
and. ALU control logic. The last sections of logic are discussed immediately because of their interaction with the
DATA PATHS section. The operation of the basic microcontrol follows.
3.4.1 Condition Codes Input
The condition codes are used to store information about the results of each instruction so that this information can
be used by subsequent instructions. The information recorded in the condition code bits (N, Z, V, C) of the
Processor Status Register differ for each instruction type, and often for the part of the instruction being executed.
The decoded output of the IR DECODE logic and the select processor status (SPS) code of the microword
determine which conditions are to be presented as the data input to the Processor Status Register. In addition, the
SPS code determines when the Processor Status Register should be loaded directly from the D MUX.
3.4.2 ALU Control
The ALU control combinational logic receives the DAD (discrete alteration of data) code from the microword as a
function of the IR decode logic. In general, the SALU and SALUM microword bits directly alter operation of the
ALU; however, during the latter part of an instruction, where common instruction flow paths exist for several
instructions, the DAD code is combined with the Instruction Register to alter operation of the ALU.
There are 32 possible ALU functions, depending on the state of SALU (03:00), ALUM and CIN. Some of these
functions are contained in Table 3-2.
3.4.3 Flag Control
The flag control logic is closely related to the IR decode logic because certain instructions require specific flags, such
as WAIT and HALT. Other flags exist for service of peripherals and console request, as well as for error conditions.
Flip-flops within the flag control logic interact directly with the microbranch logic to provide the required branch
conditions in the machine flow to provide flag service.
3.4.4 U Branch Control
In a microprogrammed computer, the next ROM address (next machine state) is dependent on a number of previous
conditions. The purpose of the microword branch control (U BRANCH CONTROL) logic and the Branch
Microprogram Test (BUT) Multiplexer is to select the next proper machine state. The microbranch control provides
some of the inputs to the BUT decoding logic. The microbranch control combines the diverse instruction decoding
of the Instruction Register and encodes it into two, three, four, or five bits of a microaddress alteration, called
"basic microbranch codes," for specific BUTs [BUBC (BUT XX)] . For most of the complicated branches, such as
the first instruction branch or some of the subsequent source or destination instruction branches, these codes are
fairly extensive. They may also be fairly simple, consisting of only three bits or, in some cases, three bits of another
BUT encoded with another single condition. The latter case is particularly true with the INSTR 2 BUBC and the
(BYTE and INSTR 2) BUBC.

3-16

Table 3-2
Table of Combinations
74181 - Arithmetic Logic Unit

Selection
S3

ALUM=H
Logic
Functions

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

F=A
F=A+B
F=AB
F=O
F=AB
F=B
F=A+B
F=AB
F=A+B
F=A+B
F=B
F=AB
F=l
F=A+B
F=A+B
F=A

Active High Data
ALUM=L Arithmetic Operations
CIN=O

CIN = 1

F=A
F=A+B
F=A+B
F=minus 1 (2's COMPL)
F=A plus AB
F=(A+B) plus AB
F=A minus B minus 1
F=AB minus 1
F=Aplus AB
F=A plus B
F=(A+B) plus AB
F=AB minus 1
F=A plus A*
F=(A+B) plus A
F=(A+B) plus A
F=A minus 1

F=A plus 1
F=(A+B) plus 1
F=(A+B) plus 1
F=O
F=A plus AB plus 1
F=(A+B) plus AB plus 1
F=A minus B
F=AB
F=A plus AB plus 1
F=A plus B plus 1
F=(A+B) plus AB plus 1
F=AB
F=A plus A plus 1
F=(A+B) plus A plus 1
F=(A+B) plus A plus 1
F=A

*Each bit is shifted to the next more significant position.

3.4.5 BUT MUX
The Branch Microprogram Test Multiplexer (BUT MUX) selects sets of address alterations to alter data into the
Microprogram Pointer (UPP) which points to the next ROM address. The BUT MUX provides a 5-bit output with the
number of possible inputs on the lowest order bits being greater than the number of inputs that can be selected for
the higher order bits. This corresponds to the fact that few of the branches involve all five or six bits of address
alteration. There are a number of address alterations that involve only one bit, usually the lowest order bit.
The gradation of inputs in the multiplexers is as follows: there are two 6-bit multiplexers for bit 0, a single 16-bit
multiplexer for bit 1, 8-bit multiplexers for bits 2 and 3, and a 4-bit multiplexer for bits 4 and 5. Besides this
ordering of multiplexers, the inputs to the BUT MUX also determine the required branch. The microbranch control
logic provides wide branch encoding situations for instruction situations (INSTR 1, INSTR 2, and INSTR 3) and a
5-bit input is possible for the BUBC signal. In other cases, the Instruction Register itself may be used for a single
BUBC bit code when the decision between a bit enabled or not enabled is simply a choice between two different
microaddresses. The flag control logic also provides certain inputs which alter only one bit of the microaddress.
The actual selection of which of these inputs (wide or narrow branch, branch on instruction, branch on flag) is to be
used, is determined by the microprogram branch field (UBF) of the microword. The UBF field directly selects which
inputs of the multiplexers are applied to the rnicroaddress alteration logic (the NOT OR gate on the block diagram).

3-17

3.4.6 U WORD Control ROM and U WORD Reg
The heart of the control logic is the microword control read-only memory (ROM) which stores 256 56-bit words.
The format and purpose of these control words is described in more detail in Chapter 2. Basically, each of these
control words represents a different machine state of the processor. The ROM provides a wired-OR output as
indicated by BUS U (56:09) and BUS U (08:00). This wired-OR condition permits easy expansion of the processor
as required by the KEl 1-E and KEl 1-F options.
The microword output of the ROM is applied to a Buffer Register (U WORD Register) that permits a microword to
be used for machine control and selection of the next address, while the ROM itself is obtaining the contents of the
next address. Although advantageous from a time standpoint, this implementation slightly increases the complexity
of the hardware and concepts.
Each microword from the ROM consists of a control portion and a next address portion. At the beginning of the
current machine state, a ROM output microword is clocked into the U WORD Register. The bits in the control
portion of the microword select addresses, select multiplexers, and enable clocking gates (these gates enable clock
pulses toward the end of the machine state). The bits in the address portion of the microword access the ROM to
obtain the next ROM word. At this point, this address is fixed in the microword register and alteration for a BUT
has not occurred.
The delay in using the buffer (U WORD Register) is fixed by the settling time of the flip-flops (approximately
15-20 ns). This is significantly better than the 60-90 ns required for addressing the ROM. For this reason, the
buffer takes the delayed output of the ROM, clocks it at the beginning of the machine state, and provides it almost
immediately (in that machine state) to the rest of the processor (data path, interface, and the microprogram
control).
The clock for the U WORD Register is taken directly from the basic processor clocking and is related to the clock
length selection bits in the microword control. The clock is a function of a machine cycle and is the last pulse edge
of the previous machine cycle.
Each microword is divided into two segments: address and control. The address portion of the word is represented
by BUS U (08 :00) which is the address of the next ROM word. The control portion is represented by BUS U
(56:09) which includes the control bits for the microword. The control bits are applied directly to the U WORD
with the address bits passing through a NOT OR gate to the Microprogram Pointer (UPP) portion of the U WORD.
The outputs of the U WORD Register are diverse and are used throughout the processor. Outputs control the basic
processor clock, microcontrol branching, and elements of the interface and data path. These outputs are indicated
both by the labels on the U WORD Register outputs and by signals prefixed with a K2 on other blocks in the
diagram.
3.4.7 Microaddress Alteration
Each microprogrammed word contains the address of the next microprogrammed word to be used by the processor.
This address is referred to as the microprogram field (UPF) of the ROM. If this address were always exactly as
specified by the ROM, it would receive little attention from the processor. However, alterations to this address are
made for branching purposes. Therefore, there must be a method of modifying and storing this address so that the
next specified word can be output in parallel with current word control. As shown on the block diagram, the
hardware used to perform these functions consists of the NOT/OR gates on the UPF ou\put [BUS U (08:00)], the
output of the BUT MUX and the UPP Register. The base address of the UPF can be altered by the BUT MUX inputs,
resulting in a different next ROM word address in the UPP. Register.

3-18

In discussing the address in the rnicroaddress loop, it is important to realize that an altered next address has been
stored in the UPP Register and that alterations for the subsequent next address are fed to the NOT /OR gate. Both of
these addresses are clocked simultaneously; therefore, the address fed through the NOT /OR gate is clocked into the
UPP and the address that had been stored in the UPP is clocked out. Consequently, in any given microword, the
control portion of the U WORD is performing manipulations while the UPP address portion of that word is
addressing the next ROM word. The last UPP contents, the rnicroaddress of the present U WORD, are stored in the
Past Microprogram Pointer (PUPP) for reference. The logic diagram in Figure 3-10 shows, in simplified form, how an
address change is performed.

>----+-----! D
UPP3

>-~-+---ID

INPUT CONDITIONS
FROM THE INSTRUCTION
REGISTER,FLAG FLIP-FLOPS
AND DATA PATH DECODING

UPP2

>-------+----< D

UPP1

'--v---'
MULTIPLEXER
SELECTION FROM
BUT FIELD
OF U WORD
REGISTER

,____._--+----< D

UPPO
~-~-+--tC

CLK

ROM OUTPUT FOR
NEXT BASE ADDRESS
"OR" BASE ADDRESS
TO BRANCH CONDITIONS

SELECT THE CONDITION

ROM ADDRESS

11- 1659

Figure 3-10 U Branch Control Sequence, Simplified Branching Operation

Another address in the address loop is the output of the ROM which has been selected by the next address from the
UPP Register. This address does not appear immediately in the machine cycle (as is the case for the UPP next
address) because ROM access time is greater than flip-flop settling time. However, it is present about midway
through the U WORD state. This ROM output address, which appears on BUS (08:00), is a subsequent next address
and is applied through the NOT/OR gate to the UPP Register. The next word data is becoming available across the
entire ROM and is to be clocked in after the current machine state ends. If the subsequent next address is fixed (i.e.,
no branches are required), then there is no real difference between the address and control portion of the ROM/U
WORD interface. In effect, the NOT/OR gate simply inverts the already complemented address output of the ROM.
However, if a microbranch is to occur, it must occur at this point before the subsequent next address is clocked into
the fixed UPP Register. The branch requires a subsequent next address from the ROM with Os in it; it also requires
the BUT MUX logic to input alterations to this address. Both of these occurrences require that the current
microword has enabled appropriate control bits in the address and control sections.
3-19

Note that the microbranch test in a· current word cannot alter the next word. However, it can alter the following
word (the subsequent next word) as described below.
Assume that there are three microwords in sequence: A, B, and C. When the 'current word is A, the address portion
of that word is causing word B to be accessed from the ROM (the address portion of word A selects the next word,
which is B). Word B contains an address segment which is used for accessing word C and is present on BUS U
(08 :00). The address portion of word B, however, is a base address so that it can be altered if there is to be a branch.
This alteration occurs in the NOT/OR gate while word A selects word B. The address for word C (contained in word
B) can be either the base address for C or an altered address for C. For example, the altered address could be Cl or
Cn, depending on how wide the branch is.
This technique means that selection of branch conditions and related enabling of that selection to the NOT /OR gate
occurs a microword ahead of the word in which the branch takes place. During word A, a decision to branch can
affect what word is used for word C, but it cannot affect word B. If a branch to C or Cn is desired, then conditions
. must be enabled to alter C in word A. By the time the processor goes to word B, the next address for word C is
already fixed and stored in the UPP Register.
3.4.8 JAMUPP Logic
The microprogram address loop is also affected by the JAM Microprogram Pointer (JAMUPP) logic which alters the
sequential nature of the microprogram. The JAMUPP logic provides a means of jamming an address into the UPP to
modify the microprogram for certain conditions such as bus errors, stack overflow, auto restart, etc. This logic
provides the next microword address directly, without regard for the previous microword's address. The output of
the JAMUPP logic directly sets or directly clears the UPP Register flip-flops to establish the required address. This
method differs from the normal NOT/OR gate outputs which are clocked into the UPP Register flip-flops.
3.4.9 PUPP Register
The output of the UPP Register is also fed to the Past Microprogram Pointer (PUPP) Register at each system clock.
The PUPP Register maintains a history of the previous UPP and displays its contents on the maintenance console.
Note that the PUPP indicates the current microword address. The PUPP Register is clocked each time the microword
is clocked and the data input to the register is the address of the next ROM word present in the UPP Register. As the
microword changes to the next word, the address of that word is clocked into the PUPP Register. The address of the
current microword is therefore available and can be referenced on the maintenance console. The PUPP Register
serves to identify ·the current microword address and to permit access to the ROM listings to determine which
control bits should be enabled or disabled, and which operations would be taking place at this time. Note that the
register itself does not perform these functions. It is the output of the register on the maintenance console display
that permits determination of the current address.
3.4.10 BUPP&SRMATCH
The output of the UPP Register is also fed to the BUPP & SR MATCH logic, which is used for maintenance
purposes. This logic compares the contents of the UPP Register [UPP (08:00)) with the low-order bits of the Switch
Register [SR (08:00)) and generates a MATCH signal when UPP (08:00) equals SR (08:00). This MATCH signal can
be used either as a synchronizing signal to trigger an oscilloscope, to stop the clock (halt the machine) in that word,
provided the appropriate switches on the maintenance console are set. For example, to obtain a strobe signal upon
entering ROM address 234, this address would first be set in the Switch Register on the programmer's console. When
the contents of the UPP Register matched the Switch Register value, the end clocking pulse of that machine state
would be enabled as a strobe signal. Because the UPP Register contains the next ROM address, the pulse would occur
at the end of the machine state just prior to the microstate addressed in the Switch Register.

3-20

3.4.11 Clock Logic
The clock logic and related timing signals are basic to any processor. The clock signals that are generated are either
used directly or are gated with enabling signals. These enabling signals are derived directly from either the microword
or from machine states (flags, flip-flops, Unibus states, etc.). Data transfers and processor initializations within the
processor itself are synchronous; they occur at specific times within machine states. Three different clock cycles are
provided by the logic. This synchronous operation is designed for continuous running of the processor as the ROM
sequences one microword after another. The processor should, however, be considered as a combination of both
synchronous operation and asynchronous operation. The asynchronous nature of the processor is due to the fact
that, upon certain conditions, the clock is turned off and waits for a restart. An obvious turn-off situation is that
which occurs during Unibus data or bus ownership operations which are specified as asynchronous functions.
There are three functional elements that comprise the processor clock logic: the clock pulse generator, the clock
control logic, and the clock enable gates. A simplified block diagram of the clock is shown in Figure 3-11.

SYNCHRONOUS REGENERATION

RECLK
ASYNCHRONOUS RESTART

CLOCK
PULSE
GENERATOR

CLOCK
CONTROL

MAINTENANCE CONTROL

P2
P3

CLOCK
ENABLE
GATES

OUTPUT TIMING
} PULSES TO DATA
PATH, INTERFACE
AND MICROCONTROL

CLKOFF(1)

MI CROW ORD
REGISTER
CONTROL

CLKL1------~

CLKLO - - - - - - - - - - '

VARIOUS{-------------~

ENABLING
SIGNALS

-"""------------------'
P1
I

CL1 1,__ _ _ _ __.

:
TYPICAL TIMING WAVEFORMS

CL2..,.i_ _ _ _ _ _--:._ _
1

_.ll~------P2

CL3,_'--------.,.--.-

I
I

i-----140ns I
I

1------2.00ns---i--------300ns------~

11- 1661

Figure 3-11 KDl 1-A Processor Clock, Block Diagram

3.4.11.1 Clock Pulse Generator - The clock pulse generator provides the system clock pulses when pulsed by the
clock control logic. These clock pulses are used throughout the processor and are combined with the enable signals
of the U WORD Register to act on the three major segments of the processor (INTERFACE, DATA PATHS, and
MICROCONTROL). Three pulses are generated by the clock pulse logic: the CLl cycle, which generates a Pl pulse;
the CL2 cycle, which generates a P2 pulse; and the CL3 cycle, which essentially combines the CU and CL2 cycles
and consists of P2 and P3 pulses. The prime purpose of the CL3 cycle is to complete a read/write cycle around the
data path loops to allow the transfer to the D Register and from the Scratch Pad Register storage back into the
Scratch Pad Register. The specific cycle length (CU, CL2, CL3) for a microword is determined by microword clock
control bits in that word. (See print D-CS-M7234-0-1 and Figure 3-11 for CLK waveforms.)

3-21

3.4.11.2 Clock Control - The clock control logic consists of a clock (CLK) and an idle (IDLE) flip-flop. The CLK
flip-flop provides a pulse to the clock pulse generator when activated by the input signals RECLK, Asynchronous
Restart, and Maintenance Control. The pulse is not generated when the Microword Register signal CLKOFF (1) is
active and the IDLE flip-flop is set. The clock is restarted by the Asynchronous Restart or Maintenance Control
signals which deactivate the IDLE flip-flop and reinitiate the CLK flip-flop.
3.4.l l.3 Clock Enable Gates - The clock enable gates receive the pulses generated by the clock pulse generator.
During each machine state, microcontrol bits control the passage of these clock pulses to specific registers. When it is
desired to clock a register, the rnicrocontrol word has the appropriate bit enabled and the clock pulse passes through
the enable gate to the clock input of the specified register.

3-22

Table 3-3
K.Dl 1-A Functional Components
Component

Description

Input

Output

ADDRESS Display

Indicator lights located
on the KYl 1-D Programmer's Console.

Contents of the Bus Address
(BA) Register.

Displays contents of the BA
Register on console ADDRESS
display.

Arithmetic Logic
Unit (ALU)

Four 74181 IC chips
and one 74182 IC chip
provide a 16-bit arithmetic logic unit with a
lookahead carry.

Data:

Dependent on mode
selected, can perform
up to 16 logic functions
and up to 16 arithmetic
functions. (See ALU
TABLE, print
D-BD-K.Dl 1-A-BD.)

w
w

Arithmetic Logic
Unit Control
(ALU CONTROL)

One 8233 IC (dual
2-line to 1-line multiplexer) and combinational logic.
Generates control signals
that are used to specify
the ALU function.

AIN-16-bit wide
input from buffered
BUS RD bus
BIN-16-bit wide
input from B MUX
CIN-carry insert to
LSB of ALU from
CIN logic

Control:

Provides 16-bit
output to either the
D Register or to the
BA Register through
the BAMUX.

Status: COUT 7, COUT 15,
ALU 15 to input of
COUT multiplexer.

SALUM,SALU
(03 :00) 5-bit
wide control that
specifies ALU
function.

ALU control signals from:
microword bits, IR decode
logic, and external control
(KEl 1-E).

Five control signals, SALUM,
SALU (03:00) that select the
ALU function to be performed.

Table 3-3 (Cont)
KD 11-A Functional Components
Component
B Constants

Input

Description
Combinational logic network providing elemental
values for incrementation
and decrementation. Also
provides more complex
constants such as trap vectors and masks.

Constants generated are a
function of the following
inputs:

Output
Selected constants applied to
the B MUX.

SBC (03:00) from the
microword.
STPM (04:02) from the
trap sensing logic.

B Multiplexer (B MUX)

Eight 74153 multiplexer
IC chips.
Provides the means of
selecting the data input
to the B input (BIN) of
the ALU.

Control of the high and low
bytes are independent signals from the microword.
Any one of the following
inputs can be selected:
a.

BC (15 :00) (B co.nstants)

B (15:00) (direct)

B (15:08, 15:08)
(duplicate upper byte
of B Register)

B (07:00, 07:00)
(duplicate lower byte
of B Register)

B (07:00, 15:08)
(swap bytes of B Register)

B (15:08=7, 07:00)
(sign extend lower byte
of B Register)

Provides 16-bit wide input
to the B input of the ALU.

Table 3-3 (Cont)
KD 11-A Functional Components
Description

Input

B Register

Four 74174 IC chips
provide a 16-bit ternporary storage register
for the B input of the
ALU.

Input is loaded from the output
of the D MUX and is therefore
dependent on the D MUX selection.

Provides a data input to the
B MUX. This input (which is
the B Register output) is partitioned into a high (15:08)
and low (07:00) byte.

Bus Address
Multiplexer
(BAMUX)

Four 8233 multiplexer
IC chips. The BA MUX
loads the BA Register.

Receives 16-bit wide input from
either the Register Data bus (BUS
RD) or the output of the ALU.

A 16-bit wide output that is
loaded into the Bus Address
(BA) Register.

Component

Output

A single microword control signal selects one of the two possible
inputs. A high signal selects the
ALU.
Bus Address Register
(BA Register)

Four 74174 IC chips
that form a 16-bit
temporary storage
register.

Receives a 16-bit wide input
from the BA MUX.

Transmits a 16-bit address to
the Unibus. This address is
applied through bus drivers
to bus address lilies BUS BA
(17:00). The address is also
applied to the address display
and is decoded for processor
address response.

Table 3-3 (Cont)
KD 11-A Functional Components
Component
Bus Register Data
(BUS RD)

Description
Four 74H04 IC chips
that provide 16 inverters to establish proper
input polarity for the A
Input (AIN) of the ALU.

Input
Receives input from three
sources by means of a
wired-OR bus:
a.

Scratch Pad Register
data (16 bits)

Processor Status
Register (8 bits)

External options
(16 bits)

Output
Output provides 16-bit data
to either the A input (AIN)
of the ALU or to the bus
address (BA) multiplexer.

Branch Microtest
Decode
(BUT DECODE)

Network of combinational logic circuits that
decodes the Microbranch
Field (UBF) in each
microword and generates
auxiliary control signals.

UBF (04:00) from the
microword.

Control signals, especially to
the flag control logic.

Branch Microtest
Multiplexer
(BUTMUX)

Six multiplexer IC chips:

Any one of the following are
selected by microword UBF
(04:00) field:

Control signals that allow modification of the microprogram
field, UPF (07:00), prior to
clocking the address into the
UPP of the Microword Buffer
(UWORD).

three 16-line to 1line type 74150
multiplexers

two 8-line to 1-line
type 74151 multiplexers

one dual 4-line to
1-line type 74153
multiplexer

IR Register bits

branch microbranch
control signals

IR decode signals

machine status and
flags

Table 3-3 (Cont)
KD 11-A Functional Components
Output

Component

Description

Input

Buffered Microprogram
Pointer and Switch
Register MATCH (BUPP
&SRMATCH)

Nine exclusive-OR gates
connected as an equivalence detector.

BUPP (08:00) and SR (08:00)

UPP MATCH signals

Compares the contents of
the Microprogram Pointer
Register (UPP) with the
Switch Register (SR) to
generate a MATCH signal.
The MATCH signal can be
used to stop the clock during
maintenance operation or to
generate a scope synchronizing
signal.
Comparing the two registers
permits stopping operation
or monitoring operation at
a specific ROM word.
Clock Control

Network of combinational
logic circuits and delay line
controls the CLK and IDLE
flip-flops.

CLKOFF from the microword
as well as various restart and
continue signals.

Control signals to the clock
pulse generator.

Clock Pulse Generator

Three delay lines selected
by combinational logic
circuits to generate the
clock pulses specified by
the current microword.

Pulse signal from clock control and the clock length signals CLKLO and CLKLl from
the microword.

Timing pulses Pl, P2, and
P3. The RECLK signal which
provides for continuous
microword operation.

Table 3-3 (Cont)
KD 11-A Functional Components
Component
Clock Enable Gates

D Multiplexer (D MUX)

Input

Description

Output

Combinational logic network that routes clock
outputs to the INTERFACE,
DATA PATHS, and MICROCONTROL portions of the
processor.

Timing pulse Pl, P2, or P3
from the clock pulse generator.

Various clock signals. (CLK
IR, CLK D, CLK BA, etc.).

Eight 74153 multiplexer
IC chips.

A 2-bit microcontrol field
selects one of the following
four inputs:

The D MUX distributes 16-bit
data word to:

Various clock enable signals:
CLKIR, CLKBA, CLKB, CLKD,
WRH, WRL bits from the current
microword.

BUS RD (including
the Scratch Pad
Register)

Instruction Register

Scratch Pad Register

D Register

B Register

D Register shifted
right

PS Register

DATA display

Unibus data
f.

Internal data bus (D MUX)
for basic machine and
options

t'.J

D Register

Four 74174 IC chips
form a 16-bit temporary
storage register.

Output of ALU.

Provides a 16-bit output to the
D Multiplexer (D MUX) and to
the Unibus data lines [BUS D
(15:00)]

Table 3-3 (Cont)
KD 11-A Functional Components
Component

Description

Input

Output

DAT A Display

Four 7380 IC chips that
invert the output of the
D MUX for display on
the console.

16-bit output of the D MUX.

16-bit data to the console DATA
indicators.

Decoding
(ADRS & DATA)

Combinational logic net18-bit inputs from Bus Address
work that decodes the Bus
(BA) Register and the D Register.
Address Register and generates
internal control signals for
addressing processor registers.
Sensing is provided for stack
overflow situations and zero
data in the D Register.

Processor status (PS) Address
Stack Limit Register (SLR)
address (KJI 1-A Option)
Scratch Pad Register (REG)
address
Switch Register (SR) address
BOVFL STOP and BOVFL
signals D Register zero data.

Drivers

Instruction Register
(INSTR REG)

Three 74H04 driver IC
chips provide 18 buffer
gates transmitting the
UPP address to the PUPP
Register and to an expansion ROM.

Microprogram Pointer (UPP)
output of UPP Register.

Four 74175 IC chips
forming a 16-bit storage
register that holds the
instruction.

Output of D MUX clocked
the instruction fetch sequence.

Basic Microprogram Pointer
(BUPP) for application to
PUPP register.
Expansion Microprogram
Pointer (EUPP) for an expansion ROM (KEl 1-E, KEl 1-F).
Output applied to IR decode
logic where it is decoded and
used to control the microprogram sequence. Some bits
used directly for microbranching
and Scratch Pad Register selecti on.

Table 3-3 (Cont)
KD 11-A Functional Components
Component
Instruction Register
(IR) Decode

JAM Microprogram
Pointer (JAMUPP)

w
0

Processor Status (PS)
Register

Input

Description
Large network 'of combinational logic circuits
that decodes the lnstruction Register instruction
and generates appropriate
control signals to perform
the specified function.

16-bit instruction from the
Instruction Register.

Sequential logic network
consisting of flip-flops,
one-shots, and decoders.
This logic permits jamming
an address into the UPP
to modify the microprogram
if certain conditions are
present.

Internal control signals dependent
on existing condition. Conditions
causing J AMUPP are:

Four 7474 IC chips
providing eight storage
flip-flops to hold the
processor status word.
This word contains
condition codes and
processor priority.

Output
Generates control signals that are
a function of: the operation code,
instruction format, and specified
register.
Primary control signals are sent
to the: ALU, rnicrobranch
control logic, and the BUT MUX.

bus errors

stack overflow (red zone)

auto restart (PWR UP)

console switches (INIT)

Input may be either from D
MUX (07:00) or may be from
condition code logic.

Set and clear signals to UPP portion of the U WORD. Timing
signals to load newly selected
ROM word into the Microword
Buffer (U WORD).

Output may be gated onto
Unibus on lines BUS D (07:00)
or may be gated for processor
use on lines BUS RD (07 :00).
Individual bits used from
branch instruction decode and
for microbranching.

Table 3-3 (Cont)
KD 11-A Functional Components
Component

Description

Input

Output

Past Microprogramming
Pointer (PUPP) Register

Two 74174 IC chips
providing a 9-bit
storage register for
keeping a history of
the previous UPP
address, which is the
present microword
address.

Loaded with the contents of
the UPP Register at each systern clock.

Four 3101 IC chips
providing a 16 x 16
read/write facility.
Basically, this represents the 16 generalpurpose processor
registers (referred to
as the Scratch Pad
Register).

Data:

Provides 16-bit data word to BUS
RD buffer for transfer to one of
the following:

Combinational logic
network used as an
address multiplexer to
select one of the 16
general-purpose Scratch
Pad Registers for reading
or writing.

There are four possible sets of
inputs. One of the four is selected
by the microword signals:

16-bit input from
the D MUX

Control:

4-bit address
input from REG
ADRS input
logic
2-bit read/write
control from
microword

IR (02:00) - 3-bit destination field from instruction
register

IR (08 :06) - 3-bit source
field from instruction register.

AIN of ALU

BA Multiplexer

D Multiplexer

Provides address selection to the
register (REG).

Table 3-3 (Cont)
KDl 1-A Functional Components
Component

Description

Input
c.

RIF (03:00) - 4-bit field
from microword directly

BA (03 :00) - 4-bit field
from Bus Address Register

Output

Microword signals are:
SRD - Selects Register
Destination, IR (02:00)
SRS - Selects Register
Source, IR (08:06)
w

w
N

SRI - Selects Register
Immediate, RIF (03:00)
SRBA - Selects Register
Bus Address, BA (03:00)
Microbranch Control
(U BRANCH CONTROL)

Large network of combinational logic circuits
that provide data signals
for modifying the base
ROM address.

Instruction Register bits
IR decode signals
Machine status (i.e., switches,
Unibus, control flip-flops,
etc.).

Data signals to the BUT MUX.
These signals are used to modify
the basic ROM address as a function of BUT MUX selection from
the microword.

Table 3-3 (Cont)
KDll-A Functional Components
Component
Microword Control
(ROM)

Description
A read-only memory
storing the KD 11-A
microprogram. The ROM
stores 256 56-bit words.

Input

Output

Contents of UPP Register
selects the next control
word to be retrieved from
the ROM.

56-bit microword divided into
address bits BUS U (08:00),
and control bits BUS U (56:09).

Output of the NOT /OR gate
that receives inputs from the
ROM, the BUT MUX, and the
EUBC for U (08:00); output
of the ROM directly for
u (59:09).

UPP (08:00) are the nine loworder bits of the U word which
are used to select the next U
word.

Fourteen ROM IC chips
providing storage for the
256 words. Each chip
stores 4 bits of the 56-bit
word.

w
w

Microword WORD
Register
(UWORD)

A 56-bit storage register
consisting of type 74H74
and 74174 IC chips. This
register is used to buffer
the output of the ROM
which provides the signals
defining the operation of
the KDl 1-A data path
and control.

U WORD for U (56:09) have a
variety of mnemonics related
to their control functions.

Table 3-3 (Cont)
KDl 1-A Functional Components
Component

Description

Input

Output

Microprogram Pointer
(UPP) Register

Five 74H74 IC chips
forming an 8-bit address
register. The UPP register
points to the address of
the next microword to
be read.

Address of ROM location to
be read during current machine
cycle. The address loaded is
a function of:

UPP (08:00) - selects one of
256 control words stored in
the ROM.

UPF (07:00) of ROM
word presently being
addressed by the UPP
Register.

Basic Microbranch
Control (BUBC)
signals for microaddress
modification (basic
machine).

Expansion Microbranch
Control (EUBC) signals
for microaddress modification (optional
expansion).

It is the address portion of the
U WORD Buffer noted above.

CHAPTER 4
MICROPROGRAM FLOW DIAGRAMS

4.1 SCOPE
This chapter describes and explains the microprogram flow diagrams (print D-FD-KDl 1-A-FD) that are included in
the KDl 1-A Processor print set. These flow diagrams illustrate the operation of the processor on a machine state
level; each operation shmun on the flo~ ,Wagrara. G9Uiipou~;ls to o.ue gxoces~2r...tjme Cj'.chi :arh~. i.1!....!.IDJ:L
~e.s11oni.:J~ lll QUIO' w~d QL .the micn;;iprgBnn 1? OM The first section of this chapter describes the format,
symbology, and layout of the flow diagrams; the second section explains their use.
4.2 HOW TO READ FLOW DIAGRAMS

Virtually all of the information needed to follow and understand the flow diagram is located on the flow diagram
itself, however, it is necessary to understand the format of the diagram before this information can be easily used.
The diagram contains two basic types of information: the operations performed by each machine state, and the
flow of control from each machine state to all of the possible succeeding states.
As shown in Figure 4-1, only three basic symbols are used on the flow diagrams, the most important being the box
that represents a specific machine state. This box contains information about the operations that take place during
the machine time cycle for the microprogram word represented by the box. In certain cases, it also contains a test
operation to determine the path of the control information. The oval represents an entry point in the flow path; the
diamond represents an exit point.

(

)
ENTRY POINT

MACHINE STATE
(MICROPROGRAM WORD)

<>
EXIT POINT

11- 2127

Figure 4-1 Basic Flow Diagram Symbols

In Figure 4-2, a representative example taken from one of the flow diagrams, the flow is shown for logic activated
when the console ST ART flip-flop is sensed. The figure is annotated to indicate the type of information found on
the flows. Each of these items is discussed separately in the following paragraphs.

4-1

SHEET NUMBER OF
( 11,12) .....--PREVIOUS FLOW EXIT
START (1)

ENTRY POINT

MICROWORD MNEMONIC~

/
STAOO

GENERAL DESCRIPTION

MICROWORD ADDRESS

032

LOAD NEW R(PC)

INFORMATION IN CONSOLE
DATA DISPLAY DURING
SINGLE CLOCK MODE

r-------~~---1

ACTION EFFECTED
BY MICROWORD
MNEMONIC OF
MICROWORD BRANCH TEST

Pt:R(PC)-D
)
10_
..__Bu_T_l_H_AL_T_ _
BU_T_

STA01

UBF CODE OF BRANCH
_,016
MICROPROGRAM TEST
"'-BASE MICROADDRESS THAT CAN
BE ALTERED BY THE BRANCH
MICROTEST(BUT 10)

076

NO-OP FOR BUT

R (PC)

P1:NO-OP

LEADING DASH INDICATES
LOGICAL NEGATION~

BRANCH OCCURS HERE
,,.......--(CONDITIONS NOTED)
-HALT SW

HALT SW

EXIT POINT

( 1, _
016

FC~~EJ0~¥~NBUEA';-1~N -

t1oi
017

ADDRESS OF NEXT
MICROWORD, BASE
ADDRESS UNALTERED
BY BUT 10

ADDRESS OF NEXT
MICROWORD, BASE
ADDRESS ALTERED
BY BUT 10
11-2126

Figure 4-2 Flow Diagram Example

4.2. l Entry Point
As shown in Figure 4-2, the entry point is labeled START (1). This indicates that the section of the flow beginning
at this point is activated when the console START flip-flop is sensed. The numbers in parentheses above the entry
point indicate pages of the flow containing previous flow information. Thus, (11) indicates print 11, which is the
console loop flow diagram. Following this flow through to the bottom shows that START (1) on print 12 is one of
the possible exit points for the console loop flow. The other number (12) above START (1) indicates that this flow
can also be entered from a point on print 12. In this case, START (1) is an exit point for the LOAD ADRS switch
function, provided BEGIN is true.
4.2.2 Microprogram Word
Each box on the flow diagram indicates one specific microprogram word (machine state). As shown in Figure 4-2,
this box contains a variety of information.
Above the box, on the left hand side, is a mnemonic for the microword. In this case it is STAOO, indicating itis the
first (00) microword in the START (STA) sequence. Note that the numbers used with the mnemonic are decimal
numbers and begin with 00. On the right hand side of the box is an octal. number indicating the address of this
microword in the ROM. Thus, whenever ROM address 032 is used, it is always the STAOO microword.
Directly below the microword mnemonic is a line containing a general description of the function performed by the
microword. In this case, it is LOAD NEW R(PC), which indicates that the function of the microword is to load a
new value into the Program Counter (PC) Register.
·

4-2

The main description of the microword operation is in a particular form which is explained more fully in Paragraph
4.2.S. In the case illustrated in Figure 4-2, it states: Pl: R(PC) +- D. This means that the D Register is being placed
(+-)into a register R, called Program Counter, R(PC), at clock time Pl in a CLI.
The upper right hand section of the block indicates what information is shown in the console DATA display during
this microstate. In this case, the D Register is displayed. Thus, when the maintenance console is being used and the
program is being single clocked, the console DATA display allows the value being loaded into R(PC) to be observed.
Operation at speed prevents this observation.
The bottom portion of the box contains the Branch Microprogram Test information which determines the sequence
of microwords used to perform a specific fiinction. In this case, the Branch Microprogram Test (BUT) is
BUT(HALT). The other designation (BUT 10) indicates the octal microbranch field (UBF) code. It is important to
note that a BUT in any microword affects not the next word, but the word after the next word.
The purpose of the BUT(HALT) branch test is to determine if the HALT/ENAB switch on the console is set to
HALT. This condition is tested by microword 032 (STAOO). The branch does not occur until after the next word,
which is microword 076 (STAOl). If the HALT/ENAB switch is set to HALT, then HALT is true and the flow exits
at SERVICE C exit point. If the HALT/ENAB switch is set to ENAB, then -HALT SW is true, and the flow exits at
the FETCH C exit point.
A more detailed discussion of BUT instructions is given in Paragraph 4.2.4.
4.2.3 Exit Points
At the bottom of each flow there is a diamond(s) containing the name of the next entry point for the flow. The
number in parentheses beneath the diamond indicates the print of the flow diagram(s) containing the entry point.
For example, in Figure 4-2, one of the possible exit points is FETCH C, therefore, the (I) indicates print 1 of the
flow diagrams. Turning to print 1, it can be seen that FETCH C is one of the entry points. The other exit point on
the figure is SERVICE C which is on print 10. On print 10, SERVICE C is one of the possible entry points.
The exit points also have a number located below the flow page reference; this is the octal address of the next ROM
word. When the machine is microword STAOl with the microaddress 076 in the PUPP display of the KMl 1-A
Maintenance Console, the UPP display indicates either 016 or 017, depending on the success of the branch
microprogram test for BUT(HALT). Note the ORing of the low-order address bit over the base address (016 noted
next to the BUT 10 entry of microword STAOO) if the branch was successful; the next address would be 017.
4.2.4 Branch Microprogram Test (BUT)
Most machine states (or microprogrammed words) specify a unique succeeding state by means of a microprogram
address in the microprogram word. However, the sequence of machine states can be altered. This allows a particular
state, or sequence of states, to be shared by various larger sequences. For example, all instruction fetching is
performed by one sequence of machine states. Once the instruction has been fetched, then specific sequences are
followed, according to the requirements of the fetched instruction.
The BUT instructions may be divided into two functional groups: narrow or wide branch. The first type of BUT is
the type previously explained in Paragraph 4.2.2. In this case, the condition of the HALT/ENAB switch is sensed
and the branch occurs, depending on whether HALT SW is true or false. An example of a wide branch is shown on
print 1 of the flow diagrams. In this case, BUT 37 [labeled BUT(INSTR 1)] is a function of Instruction Register
encoding and the program may branch to any one of 25 different locations.
The name of the BUT indicates the possible branches that can be taken as a result of the BUT. For example, refer to
page 6 of the flow diagrams at the first machine state after the TRAP A entry. The BUT in this machine state is BUT
(MM FAULT), indicating that it is testing for faults in the KTI 1-D Memory Management option. The line after the
next machine state follows one of two paths: MM FAULT or -MM FAULT. The BUT is further defined in Note 2
on the diagram.

4-3

Another example of the narrow BUT occurs after the RTS entry point on the same flow diagram. This test is called
· BUT (SERVICE C + FETCH C). Looking at the flow after the next machine state, it can be seen that the program
can branch to either the SERVICE C or FETCH C exit point.
When a BUT instruction lists two or more possible branches as OR conditions, the priority is always from left to
right. For example, in the expression BUT (SERVICE B +FETCH OVLAP +FETCH B), the service request always
takes precedence over both the fetch overlap and normal fetch cycle entry. The expression also indicates that fetch
overlap takes precedence over a normal fetch cycle.
Table 4-1 contains a listing of all the BUT instructions along with their microword addresses and microword
mnemonics. Flow diagram sheet numbers are also included.
Notes on BUT instructions are included on each page of the flow diagrams. The notes pertain to the BUTs on that
specific page and are used to clarify points not always obvious from the flows themselves. For example, there is a
BUT on page 8 of the flow diagrams that is called BUT (NOWR + BYTEWR + WORDWR). By the conventions used,
it is known that after the next machine state there is a branch to one of three places and that these three paths are
labeled NOWR, WORDWR, and BYTEWR. However, the note on the flow diagram indicates that these branches
provide for different register write operations as a function of the Instruction Register (IR) decoding.
In a number of instances, the machine state general description indicates that it is a NO-OP FOR BUT. This means
that the previous entry requires an immediate branch before entering any other state but, because a branch can
occur only after the next machine state, it is necessary to add a non-operational state after the BUT microword. This
is the purpose of a NO-OP FOR BUT.
Some of the notes on the flow diagrams refer to a working BUT, which means that it performs a specific task and
may or may not cause the flow to branch. As an example of a working BUT, refer to the second machine state in the
RESET flow shown on page 6 of the flow diagrams. The BUT in this machine state is called: BUT (CBR2); INIT;
DELAY. This BUT senses the HALT switch for a console bus request and branches as a function of HALT SW or
-HALT switch. In addition to the branching, it also activates the INIT and RESTART delay, thereby making it a
working BUT. Another working BUT is shown on the same page as the last machine state under the TRAP D
sequence. This BUT is called BUT (REG DEP). This particular BUT is used in the sequential clearing of various
TRAP request flags but does not cause any branching. The branching shown below the machine state is caused by
the previous BUT [BUT (CBRl)] .

Table 4-1
BUT CHART
BUT Number
(octal)

BUT Name

Microword
Location

Microword
Mnemonic

Flow
Diagram
Sheet

NO-OP

Everywhere except
where a BUT is used.

CBRl

332

TRP20

CBR2

RSTOl

REGDEP

DEPOl

DEP07

333

TRP21

EXMOl

EXM04

140

TRP16

REG EXAM

BEGIN

LADOl

SWITCH

CON04

315

CON13

INTR

SERIO

HALT

STAOO

MM FAULT

TRP03

D=O

CON08

342

SOBOl

Table 4-1 (Cont)
BUT CHART
BUT Number
(octal)

BUT Name

Not Used

JSR+ JMP

SERVICE C + FETCH C

Microword
Location

Microword
Mnemonic

Flow
Diagram
Sheet

151

JMPOO

153

JMP05

154

JMP03

155

JMP06

235

JMP02

302

JMPlO

305

JMP15

110

NBROO

117

SC COO

125

MOV22

277

RSRlO

306

JMP12

324

RTS02

340

BRAOl

Table 4-1 (Cont)
BUT CHART
BUT Number
(octal)

BUT Name

16 (Cont)

IR03

BYTE + SERVICE + FETCH

IR03, BYTE AND SOURCE

Microword
Location

Microword
Mnemonic

Flow
Diagram
Sheet

344

SOB03

345

SOB05

350

CCCOl

356

MRK04

366

DOPll

367

DOP12

374

SSL09

166

DST07

167

DST06

176

MOV06

177

MOV05

160

MOV19

170

MOV18

206

MOV08

Table 4-1 (Cont)
BUT CHART
BUT Number
(octal)

BUT Name

BYTE AND SOURCE

Microword
Location

Microword
Mnemonic

Flow
Diagram
Sheet

171

MOVOO

172

MOVOl

174

MOV02

207

MOVll

Not Used

CBR+HALT

255

CON12

BR,WAIT + FETCH

SER07

REQUESTS

SERO I

SER04

SER02

114

SEROO

123

SER03

003

MOV21

132

SXTOO

135

SWBOl

271

RSROl

273

RSR04

SERVICE B + FETCH OVLAP + FETCH B

Table 4-1 (Cont)
BUT CHART
BUT Name

BUT Number
(octal)

27 (Cont)

Microword
Location

Microword
Mnemonic

Flow
Diagram
Sheet

363

DOPOl

364

DOP03

370

DOP14

371

DOP16

372

SSLOl

373

SSL03

Various Switches

CONlO

NOWR + BYTEWR + WORDWRITE

102

DOP02

104

SSL02

105

SS LOO

120

DOP15

260

DST03

266

DST14

237

DST16

Not Used

OB+ INSTR4

INSTR4

Table 4-1 (Cont)
BUT CHART
BUT Name

BUT Number
(octal)

f"
......
0

OB+ INSTR3

Microword
Location

Microword
Mnemonic

Flow
Diagram
Sheet

240

SRC03

247

SRC14

INSTR3

137

SRC16

INSTR 1

FET04

4.2.5 Operation Symbols
Previous paragraphs have discussed the basic symbology and format of the KDl 1-A flow diagrams. Another set of
symbols to understand is the ISP notation which provides the detailed description of each machine state. Although
ISP is covered in the PDP-11/40 Processor Handbook, this paragraph explains KDl 1-A flow diagram usage.
In KDll-A ISP notations, a few general rules are helpful. The first item appearing in each statement always has a
specific clock pulse, which indicates at which clock time the machine state operation occurs. The clock pulse is
always Pl, P2, or P3 and is associated with CU, CL2, and CL3, respectively. A statement describing the machine
state operation follows the clock pulse. These statements are always read from right to left. For example:
P2: D *-RO
In the above statement, D indicates the processor D Register and RO indicates one of the eight general registers. The
above statement is read: at clock time P2, the D Register is loaded with the contents of the RO Register, or D gets
RO.
A variation of the above is used when a register address appears in parentheses after the designation R (register). For
example:
Pl : B *- R(SF)
The above statement is read: at clock time Pl, the contents of the register, addressed by the IR source field, is
loaded into the B Register. This type of notation is used because a number of registers or locations may be used to
store SOURCE data. An example of this notation is shown on print 2 of the flow diagrams. This print carries a note
which states that the Source Register is selected by the IR (Instruction Register).
A more complex example of machine state operation statements is:
P2: D *- f DAD { R(SF) AND B}; DAD 14
Before reading this expression, it is necessary to know that the symbol f indicates "as a function of," that the term
to the right of the semicolon is a separate statement, and that the items in brackets are considered first. Thus, the
statement is read: D gets a function of the register, specified by the source field and the contents of the B Register.
The function is determined by the DAD (discrete alteration of data) code and its operation on the ALU; the DAD
14 function is used. The user can look up DAD 14 in the U WORD TABLES in print D-BD-KDl 1-A-BD to find the
function of DAD 14. The table indicates that DAD 14 is used for ALU CNTL f IR; in other words, the Instruction
Register determines what function the ALU is to perform.
There are times that two or more completely separate actions occur at the same time pulse. The different actions are
either separated by a semicolon, or by placing them on different lines, or both. For example:
P2: BA*- R(DF); DATI
D *- R(DF) PLUS 2
This indicates that three separate actions take place at clock time P2. First, the register defined by the destination
field of the IR is loaded into the Bus Address Register. Secondly, a DATI bus transfer is begun. And finally, the
register defined by the destination field plus 2 is loaded into the D Register.
Note that the usual use of parentheses is to further define the preceding symbol. R(PC) means that the register used
as the Program Counter in the Scratch Pad Registers is being referenced. This is true for all situations except R(DF),
R(SF), and R(BA) where specific address bits in the IR (for destination field and source field) or the bus address are
used to select a Scratch Pad Register. A note to this effect occurs on print 1 of the flow diagram.

4-11

The above example would be exactly the same if all three actions had simply been separated by semicolons:
P2:

BA~ R(DF); DATI; D ~ R(DF) PLUS 2

or if each separate action had been placed on a separate line:
P2: BA~ R(DF)
DATI
D ~ R(DF) PLUS 2
Statements that have an equal sign, such as SBC=7, DAD=lO, BUS CODE=06, etc., are explanatory statements that
list the codes internally generated during performance of the operation specified in the box. The meaning of these
codes can be determined by referring to the page of tables in the block diagram prints, D-BD-K.Dll-A-BD. For
example:
P3: PS(C) ~ DOO; SPS=l
The above expression indicates that the value on bus data line DOO is to be loaded into bit C of the processor status
(PS) word during clock pulse time P3. The explanatory expression after the semicolon (SPS=l) indicates that a
specific U WORD code is used to perform this function. By referring to the table, it can be seen that SPS code 1 is
used to clock bit C of the PS word.
4.3 FLOW DIAGRAM EXAMPLES
Once the format of .the flow diagrams is understood, it is possible to follow the flows through any instruction
sequen~e. Examples of following an operation through the flow diagrams are given in Tables 4-2 and 4-3.

In the example in Table 4-2, the following instruction (not micro) program is present:

Program Address

Contents

5000
R(SF) = (Rl) = 300 (Rl)
R(DF) =(R2) =400 (R2)

ADD (1),(2)
5

In effect, the operation adds two numbers together. The instruction ADD (1), (2), which is 061112 in octal form, is
loaded at location 5000. The first number to be added (Rl) is the number 5 (octal) stored at address 300. The
second number (octal 5) is stored at address 400.
Based on the above conditions, Table 4-2 lists all microwords in the flow when performing this operation. The table
also includes a description of what is happening during each machine state. If the table is followed carefully while
referring to the flow diagrams, the operations should be apparent;
·
Table 4-3 describes a subtract operation and is identical to Table 4-2 in format except that the description column
has been eliminated to allow the reader to determine if he can follow the table and the flows by himself.
Two tables are included in this chapter as an aid in finding specific microwords on the flow diagrams. Table 4-4 is a
numerical listing of all microwords in the ROM and includes the mnemonic, a general statement of the functibn, and
the page of the flow diagrams on which it is shown.
Table 4-5 lists all microwords in alphabetical order according to the microword mnemonic. The only other entry in
this table is the ROM address. Once the ROM address is found on Table 4-5, then Table 4-4 can be used to find the
microword on the flows.
4-12

Table 4-2
Flow Diagram Example 1

Microword
Mnemonic

ROM
Address
(PUPP)

Next ROM
Address
(UPP)

DATA
Display

FET02

016

001

5000

Pl:

BA+- R (PC); DATI;
CLKOFF; SPS=O

The contents of the PC is loaded into the Bus
Address Register; a Unibus data transfer is
performed to bring the instruction into the
processor. The address of the instruction [ADD
(1), (2)] is displayed.

FET03

001

004

061112

Pl:

IR, R(IR),
B +-UNIBUS DATA

The instruction (Unibus data) is loaded into the B
Register, a Scratch Pad Register, and the Instruction Register. The Unibus data for the instruction
is displayed.

FET04

004

005

5000

P2:

D, BA+- R(PC) PLUS 2;
DATI IF
OVLAP FETCH;
BUT INSTR 1

The value of PC plus 2 is loaded into both the Bus
Address and D Registers. No DATI is performed
for OVERLAP FETCH. Branch test BUT (INSTR
1) is performed, which is the first wide branch for
all instructions. Value of current PC is displayed.

FET05

005

141

5002

PCl: R(PC) +- D

Operation

Description

Program Counter is updated by moving data in the
D Register (which contains next PC+2) into the
PC. The new PC is displayed. Note that the display
of Din a given microword is a display of what is in
D at the beginning of the microword - not what
will be clocked into it this microword. The next
microword to be used is at ROM address 141 for a
source mode 1 (SMl) calculation on sheet 2. This
address occurs as a function of the IR and BUT
(INSTR 1) with ALLDOP * -SMO indicating a
double operand instruction with a non-zero source
mode.

Table 4-2 (Cont)
Flow Diagram Example I

Microword
Mnemonic

ROM
Address
(PUPP)

Next ROM
Address
(UPP)

SRCOO

141

247

DATA
Display
300

Operation
Pl :

BA +-- R(SF);
DATI; DAD=Ol;
MM=l4

Description
The register specified by the source field (address
of the source operand) is loaded into the Bus
Address Register. The source address is displayed.
NOTE
It would be normal to expect the location of

this microword to be 100 because that was
the value of the previous UPP. However, the
UPP was modified by BUT (INSTR 1) as a
function of the instruction, resulting in
ROM address 141 for this microword.
SRC14

247

250

061112

Pl:

NO-OP; CLKOFF
BUT (OB+ INSTR 3)

This is a no operation word to provide a BUT.
Clock is turned off to wait for Unibus response to
DATI.

SRC15

250

161

Pl:

B, R(SOURCE) +-UNIBUS DATA

The source operand (the number 5) is taken from
external memory and stored in a temporary register R(SOURCE). The value of the operand is displayed. The next microword to be used is at ROM
address 161 for a destination mode 1 (DMl) calculation on sheet 3. This address occurs as a function
of the IR and BUT (OB+INSTR 3) with
PARTDOP * -SMO * DMO indicating a double
operand instruction with a non-zero destination
mode.

Table 4-2 (Cont)
Flow Diagram Example 1

Microword
Mnemonic

ROM
Address
(PUPP)

Next ROM
Address
(UPP)

DSTOO

161

266

400

Pl:

BA~ R(DF);
DATIP; DAD=07;
MM=Ol

The register specified by the destination field
(address of the destination operand) is loaded into
the Bus Address Register. The destination address
is displayed. Note that this microword address was
modified by BUT (OB+INSTR 3). Referring to the
flow diagram, the output of SRCl 5 followed the
path marked -OB because an odd byte was not
being processed.

DST14

266

267

061112

Pl:

NO-OP; CLKOFF
BUT (OB+INSTR 4)

This is a no operation word to allow for a BUT.
Oock is turned off to await Unibus response to
the DATIP.

DST15

267

225

Pl:

B, R(DEST) ~
UNIBUS DATA

The destination operand (the number 5) is taken
from external memory and stored in a temporary
register, R(DEST), and in the B Register. The
value of the operand is displayed. The rtext microword address (225) results from the BUT
(OB+INSTR 4) for the PARTDOP * -DMO conditi on.

DOP03

225

367

P2:

D~t DAD R (SOURCE)
ANDB (DATO+DATOB)
DAD=l 7; MM=Ol

The source operand and the B Register (storing the
destination operand) are loaded into the D Register as a function of DAD. In other words, the
source and destination operands are added and
moved to the D Register. The source operand is
displayed.

DATA
Display

Operation

Description

f"'

'-"

Table 4-2 (Cont)
Flow Diagram Example 1

Microword
Mnemonic

ROM
Address
(PUPP)

Next ROM
Address
(UPP)

DOP12

367

375

DOP20

375

016

FET02

016

001

DATA
Display

Operation

Description

Pl:

ALTER COND CODES
CLKOFF; DAD=l2;
SPS=3
BUT (SERVICE C +
FETCHC)

The condition codes are altered and the result of
the addition of the source and destination operands is displayed. (Note that adding octal 5 to
octal 5 results in octal 12.)

Pl:

NO-OP

This is a no operation required by the BUT in the
previous word. The BUT determines whether the
processor is to enter the SERVICE or FETCH
flows.

5002

Pl:

BA+- R(PC); DATI;
CLKOFF; SPS=O

Fetch of next instruction.

Table 4-3
Flow Diagram Example 2
Program Conditions
Address

Contents

5000
5002
5004
5006
6000

SUB #20, @ #6000
20
6000
NEXT INSTRUCTION
30

Microword
Mnemonic

ROM
Address
(PUPP)

Next ROM
Address
{UPP)

DATA
Display

FET02

016

001

5000

Pl:

BA+- R{PC); DATI
CLKOFF; SPS=O

FET03

001

004

162737

Pl:

IR, R(IR), B +- UNIBUS
DATA

FET04

004

005

5000

P2:

D, BA+- R{PC) PLUS 2;
NO OVLAP FETCH
BUT {INSTR 1)

FET05

005

142

5002

Pl:

R(PC)+-D

SRCOl

142

240

5002

P2:

BA+- R(SF); DATI;
DAD=Ol; SBC=03
D +- R(SF); PLUS 1; MM=l4

SRC03

240

250

5004

Pl:

R(SF) +- D; CLKOFF
BUT (OB+INSTR 3)

SRC15

250

163

Pl:

B, R(SOURCE +- UNIBUS)
DATA

DST04

163

264

5004

P2:

BA+- R(DF) DATI
D +- R(DF) PLUS 2
R(DF) +- D; CLKOFF

Operation

P3:

NOTE
New D content does not
occur until end of
microword.

DST12

264

265

6000

4-17

Pl:

B, R(DEST) +- UNIBUS
DATA

Table 4-3 (Cont)
Flow Diagram Example 2

Microword
Mnemonic

ROM
Address
(PUPP)

Next ROM
Address
(UPP)

DST13

265

266

6000

Pl:

BA+- R(DEST) DATIP;
DAD=Ol; MM=Ol

DST14

266

267

162737

Pl:

NO-OP; CLKOFF;
BUT (OB+INSTR4)

DST15

267

227

Pl:

B, R(DEST) +- UNIBUS
DATA

DOP05

227

365

Pl:

B +- R(SOURCE)

DOP06

365

367

P2:

D +- R(DEST) MINUS B;
DAD=lO DATO; MM=Ol

DOP12

367

375

Pl:

ALTER COND CODES;
CLKOFF; DAD=l2;
SPS=3; BUT (SERVICE C
+ FETCHC)

DOP20

375

016

Pl:

NO-OP - If no service
request, go to FET02

. DATA
Display

Operation

4-18

Table 44
Microwords (Numerical Order)
ROM
Address

Microword
Mnemonic

000
001
002
003
004
005
006
007
010
011
012
013
014
015
016
017
020
021
022
023
024
025
026
027
030
031
032
033
034
035
036
037
040
041
042
043
044
045
046
047
050
051
052
053
054
055
056

FETOl
FET03
SEROl
MOV21
FET04
FET05
SER04
TRP08
TRP03
CONOl
SER06
FETOO
SER09
SER05
FET02
SER02
SERO?
SER08
SERIO
SERll
CON03
RSTOl
CON04
CON07
CON05
EXM06
STAOO
LAD03
DEPOO
EXMOO
CNTOO
LADOO
RST02
CON02
RST04
RST03
CON08
CONlO
CON06
CON09
CONll
LADOl
LAD02
EXMOl
EXM02
EXM05
EXM04

General Function
Fetch next instruction
Store instruction
Clock for PTR
Sign extend byte data
Modify register (PC)
Restore modified register (PC)
Clock for PTR
Get new status
Form, store trap vector
Display register (PC)
Await bus busy
Fetch next instruction
Wait for interrupt
No-op for BUT
Fetch next instruction
Clock for PTR
Clock again for PTR
No-op for BUT
Store vector, flags
No-op for BUT
Display register
Reset delay and INIT
Test for switch
Contact bounce count
No-op for console entry
Get data, timeout flag
Load new register (PC)
Display zero data
Load console address
Load console address
No-op after a BUT
Get address data from SR
No-op for BUT
Await bus busy
No-op for fetch entry
No~op for console entry
Test count
Test which switch
No-op for BUT
Increment count
Load last console address
Store data as console address
Display console address
Console flags
Conditional plus 1
Read register of bus address
Console flag

4-19

Flow
Print
1
1
10
4
1
1
10
6
6
11
10
1
10
10
1
10
10
10
10
10
11
6
11
11
11
12
12
12
12
12
12
12
6
11
6
6
11
11
11
11
11
12
12
12
12
12
12

Table 44 (Cont)
Microwords (Numerical Order)
ROM
Address

Microword
Mnemonic

057
060
061
062
063
064
065
066
067
070
071
072
073
074
075
076
077
100
101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130
131
132
133
134
135

EXM03
EXM07
EXM08
DEPOl
DEP02
DEP03
DEP04
DEP05
DEP06
DEP07
DEP08
DEP09
DEPlO
DOP21
SSLll
STAOl
TRP15
FET07
RTIOO
DOP02
DOPOO
SSL02
SS LOO
RSROO
RSR02
NBROO
BRAOO
MRKOO
TRP12
SEROO
TRP09

General Function

Flow
Print
12
12
12
12
12
12
12
12
12
12
12
12
12
8
9
12
6
1
6
7
7
7
7
9
9
7
7

SC COO
DOP15
DOP13
CONOO
SER03
RTSOO
MOV22
TRP06
RS TOO
SOBOO

Conditional plus 1
Store data
Display data
Console flags
Conditional plus 1
Conditional plus 1
Get deposit data from SR
Store deposit data
Load console address
Load deposit data
No-op for BUT
Deposit data
Deposit data
Alter codes
Alter codes
No-op for BUT
Enable new status
No-op after a BUT
Get new register (PC), modify
Put destination into B
Put source into B
Operate upon destination
Put destination into B
Operate upon destination
Put destination into B
No-op after a BUT
Add half of offset
Double offset
Deskew word for DATO
Uock for PTR
Store new status
Mask register (IR) for PS mask
Mask register (IR) for PS mask
Put destination into B
Put source into B
Display register (PC)
Uockfor PTR
Get new register (PC)
Alter condition codes
Form, store trap vector
Get reset data display
Decrement count

SXTOO

Extend sign

SWBOO
SWBOl

Put destination into B
Swap bytes

7
7

cccoo

4-20

6
10
6
7
7
8
8
10
10
6
4
6
6
7

Table 4-4 (Cont)
Microwords (Numerical Order)
ROM
Address

Microword
Mnemonic

General Function

136
137
140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
172
173
174
175
176
177
200
201
202
203
204
205
206
207
210
211
212
213
214

FET06
SRC16
TRP16
SRCOO
SRCOl
SRC04
SRC02
SRC05
SRC06
SRC09
TRP07
JMPOO
JMPOl
JMP05
JMP03
JMP06
JMP08
JMP07
MOV19
DSTOO
DSTOl
DST04
DST02
DST05
DST07
DST06
MOV18
MOVOO
MOVOl
MOV03
MOV02
MOV04
MOV06
MOV05
MOV16
MOV17
MOV14
MOV13
MOV20
MOV15
MOV08
MOVll
MOV12
SSLIO
MOV09
MOVIO
TRP05

Modify, store register (PC)
Duplicate upper byte
Load new status
Get source data
Get source data, modify
Get address, modify, restore
Get source data, modify
Get address, modify, restore
Get index data, modify
Get index data, modify
Form, store trap vector
Get destination address
Post modification
Get address, modify, restore
Get destination address, modify
Get address, modify, restore
Overlap, modify register (PC)
Overlap, modify register (PC)
Get destination data
Get destination data
Get destination data, modify
Get address, modify, restore
Get destination data, modify
Get address, modify, restore
Overlap, modify register (PC)
Get index data, modify
Get destination data
Load destination address
Load destination address, modify
Get address, modify, restore
Load destination address, modify
Get address, modify, restore
Overlap, modify register (PC)
Get index data, modify
Store data
Store data
Load byte data
Load byte data
Store destination data
Store justified data
Store index data
Store address data
Load destination address
Alter code PS(C)
Store indexed destination address
Get indexed address
Store MM vector

4-21

Flow
Print
1
2
6
2
2
2
2
2
2
2
6
5

5
5
5
5

5
5
4
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
9
4
4
6

Table 44 (Cont)
Microwords (Numerical Order)
ROM
Address

Microword
Mnemonic

215
216
217
220
221
222
223
224
225
226
227
230
231
232
233
234
235
236
237
240
241
242
243
244
245
246
247
250
251
252
253
254
255
256
257
260
261
262
263
264
265
266
267
270
271
272
273

TRP02
TRP04
FET08
SSI..06
SSI..04
SSI..08
SSI..07
DOP07
DOP03
DOP04
DOPOS
DOP09
DOPlO
RSR06
RSR08
SXTOl
JMP02
SS LOS
DST16
SRC03
SRC07
SRC08
SRClO
SRCll
SRC12
SRC13
SRC14
SRClS
SRC17
FET09
SSL12
DOP22
CON12

Get new status
Get MM vector (250)
New instruction from MM
Operate upon destination, store
Negate destination, store
Operate upon destination
Negate destination
Operate upon B, source, store
Operate upon B, source, store
Put source into B
Put source into B
Operate upon B, source
Operate upon B, source
Operate upon destination
Operate upon destination
Extend sign, store
Get destination address
Swap bytes, store
Duplicate upper byte
Restore modified base
Store index data
Get indexed source data
Store index data
Get indexed address data
Store address data
Get source data
No-op for BUT
Store source data
Store justified data
Store new instruction
Alter code PS(C)
Alter code PS(C)
Display status

9
3
2
2
2
2
2
2
2
2
2
2
1
9
8
11

MOV07
DST03
DST09
DSTlO
DSTll
DST12
DST13
DST14
DSTlS
DST17
RSROl
RSR03
RSR04

Restore base address
Restore modified base
Store index data
Get indexed destination data
Get indexed address
Store address data
Get destination data
No-op for BUT
Store destination data
Store justified data
Store destination
Operate upon destination
Duplicate byte, store

4
3
3
3
3
3
3
3
3
3
9
9
9

General Function

4-22

Flow
Print
6
6
1
9
9
9
9
8
8
8
8
8
8
9
9
8

Table 4-4 (Cont)
Microwords (Numerical Order)
ROM

Address
274
275
276
277
300
301
302
303
304
305
306
307
310
311
312
313
314
315
316
317
320
321
322
323
324
325
326
327
330
331
332
333
334
335
336
337
340
341
342
343
344
345
346
347
350
351
352

Microword
Mnemonic

General Function

Flow
Print

RSR05
RSR07
RSR09
RSRlO
JMP04
JMP09
JMPlO
JMPll
JMP14
JMP15
JMP12
JSROO
JSROl
JSR02
JSR03
JMP13

Alter codes
Store destination
Duplicate byte, store
Alter codes, finish store
Store destination address
Store index data
Get indexed address
Store destination address
Store index data
Get destination a,ddress
Get destination address
Modify Stack Pointer
Stack Linkage Pointer
Get new linkage
Store new linkage
Store as new register (PC}

9
9
9
9
5
5
5
5
5
5
5
5
5
5
5
5

CON13

Test for switch

TRPOl
RTIOl
RTI02
RTI03
RTSOl
RTS02
RTS03
TRPlO
TRPll
TRP13
TRP14
TRP20
TRP21
TRP18
TRP19
TRPOO
TRP17
BRAOl
BRA02
SOBOl
SOB02
SOB03
SOB05
SOB04
SOB06
CCCOl
CCC02
SCCOl

Form, store trap vector
Store new register (PC}
Get new status, modify
Store new status
Store new register (PC)
Get top of stack, modify
Store top of stack
Modify stack pointer
Store old status on stack
Modify stack pointer
Store old PC on stack
Get new PC
Store new PC
Get new status
Store new status
Jam register SP to 4
Form, store power up vector
Modify PC
Rest of offset, modify
Test count
Mask IR register for offset
Subtract half of offset
No-op for BUT .
Subtract half of offset
No-op for BUT
Complement PS mask bits
AND PS mask to PS
OR PS mask to PS

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7

4-23

Table 44 (Cont)
Microwords (Numerical Order)
ROM
Address

Microword
Mnemonic

General Function

3S3
3S4
3SS
3S6
3S7
360
361
362
363
364
36S
366
367
370
371
372
373
374
37S
376
377

MRKOl
MRK02
MRK03
MRK04
MRKOS
DOP19
DOP18
DOP17
DOPOl
DOP03
DOP06
DOPll
DOP12
DOP14
DOP16
SSLOl
SSL03
SSL09
DOP20
RSRll

Modify PC with offset
Form new Stack Pointer
Stack points to old RS
Load RS with old RS
Load PC with old PC
Alter codes, word store
Alter codes, byte store
Alter codes, no store
Subtract B from destination
Operate upon B, source
Subtract B from destination, store
Duplicate lower byte, store
Alter codes, finish store
Subtract B from destination
Operate upon B, source
Negate destination
No-op for BUT
Duplicate byte, store
No-op for BUT
No-op for BUT

4-24

Flow
Print

s
s
s
s
s
8
8
8
7
7
8
8
8
8
8
7
7
9
8
9

Table 4-S
Microwords (Alphabetical Order)
Microword
Mnemonic

ROM
Address

Microword
Mnemonic

-ROM
Address

Microword
Mnemonic

ROM
Address

BRAOO
BRAOl
BRA02

111
340
341

cccoo

116
350
351

DOPOO
DOPOl
DOP02
DOP03
DOP04
DOP05
DOP06
DOP07
DOP08
DOP09
DOPlO
DOPll
DOP12
DOP13
DOP14
DOP15
DOP16
DOP17
DOP18
DOP19
DOP20
DOP21
DOP22

103
364
102
225
226
227
365
224

EXMOO
EXMOl
EXM02
EXM03
EXM04
EXM05
EXM06
EXM07
EXM08

035
053
054
057
056
055
031
060
061

FETOO
FETOl
FET02
FET03
FET04
FET05
FET06
FET07
FET08
FET09

013
000
016
001
004
005
136
100
217
252

JMPOO
JMPOl
JMP02
JMP03
JMP04
JMP05
JMP06
JMP07
JMP08
JMP09
JMPlO
JMPll
JMP12
JMP13
JMP14
JMP15

151
152
235
154
300
153
155
157
156
301
302
303
306
313
304
305

CCCOl
CCC02

CONDO
CONDI
CON02
CON03
CON04
CON05
CON06
CON07
CON08
CON09
CONlO
CONll
CON12
CON13

315

CNTOO

036

DEPOO
DEPOl
DEP02
DEP03
DEP04
DEP05
DEP06
DEP07
DEP08
DEP09
DEPlO

034
062
063
064
065
066
067
070
071
072
073

122
011
041
024
026
030
046
027
044
047
045
050

230
231
366
367
121
370
120
371
362
361
360
375
074
254

DSTOO
DSTOl
DST02
DST03
DST04
DST05
DST06
DST07
.DST08
DST09
DSTlO
DSTll
DST12
DST13
DST14
DST15
DST16
DST17

161
162
164
260
163
165
167
166
261
262
263
264
265
266
267
237
270

4-25

Table 4-S (Cont)
Microwords (Alphabetical Order)

ROM

Microword
Mnemonic

Address

LADOO
LADOl
LAD02
LAD03

037
051
052
033

MOVOO
MOVOl
MOV02
MOV03
MOV04
MOV05
MOV06
MOV07
MOV08
MOV09
MOVIO
MOVll
MOV12
MOV13
MOV14
MOV15
MOV16
MOV17
MOV18
MOV19
MOV20
MOV21
MOV22

171
172
174
173
175
177
176
257
206
212
213
207
210
203
202
205
200
201
170
160
204
003
125

MRKOO
MRKOl
MRK02
MRK03
MRK04
MRK05

112
353
354
355
356
357

NBROO

110

ROM

Microword
Mnemonic

Address

RSROO
RSROl
RSR02
RSR03
RSR04
RSR05
RSR06
RSR07
RSR08
RSR09
RSRlO
RSRll

106
271
107
272
273
274
232
275
233
276
277
376

RSTOO
RSTOl
RST02
RST03
RST04

127
025
040
043
042

RTIOO
RTIOl
RTI02
RTI03

101
320
321
322

RTSOO
RTSOl
RTS02
RTS03

124
323
324
325

SCCOO
SCCOl

117
352

SEROO
SEROl
SER02
SER03
SER04
SER05
SER06
SER07
SER08
SER09
SERIO
SERll

114
002
017
123
006
015
012
020
021
014
022
023

4-26

ROM

Microword
Mnemonic

Address

SO BOO
SOBOl
SOB02
SOB03
SOB04
SOB05
SOB06

130
342
343
344
346
345
347

SRCOO
SRCOl
SRC02
SRC03
SRC04
SRC05
SRC06
SRC07
SRC08
SRC09
SRCIO
SRCll
SRC12
SRC13
SRC14
SRC15
SRC16

141
142
144
240
143
145
146
241
242
147
243
244
245
246
247
250
137

SS LOO
SSLOl
SSL02
SSL03
SSL04
SSL05
SSL06
SSL07
SSL08
SSL09
SSLlO
SSLll
SSL12

105
372
104
373
221
236
220
223
222
374
211
075
253

STAOO
STAOl

032
076

SWBOO
SWBOl

134
135

Table 4-5 (Cont)
Microwords (Alphabetical Order)
Microword
Mnemonic

ROM
Address

Microword
Mnemonic

ROM
Address

SXTOO

132

TRPOO
TRPOl
TRP02
TRP03
TRP04
TRP05
TRP06
TRP07
TRP08
TRP09

336
317
215
010
216
214
126
150
007
115

TRPlO
TRPll
TRP12
TRP13
TRP14
TRP15
TRP16
TRP17
TRP18
TRP19
TRP20
TRP21

326
327
113
330
331
077
140
337
334
335
332
333

4.27

CHAPTER 5
LOGIC DIAGRAM DESCRIPTION

5.1 INTRODUCTION
Detailed logic discussions are presented in Paragraphs 5.3 through 5.7 for each of the basic KDll-A Processor
modules. These discussions correlate with the previous information on the block and flow diagrams.
The format of the discussion is ordered toward quick reference with each module and each module print identified
separately. Detailed information on specific output logic signals is coupled with information on overall logic
operation. The balance between these two varies as a function of the logic.
5.2 PRINT FORMAT
Certain print formats are used in the Circuit Schematics and Wire List of the KDl 1-A Processor, and its processor
options (KEl 1-E, KEll-F, KTl l-D, and KJl 1-A). Since information is resident in these formats, they are noted in
the following paragraphs.
5.2.1 Circuit Schematic Format

5.2.1.l Logic Flow - Logic flow is from left to right with inputs on the left and outputs on the right. All inputs of
a given name are interconnected on a given print unless different module pins exist. Signals which output to module
pins are brought to the extreme right. Signals which do not have module pins may not be brought to the extreme
right. In any case, signal names are grouped in vertical columns wherever possible. Connectors with input signals have
the signal name to the right of the connector, output signals are referenced to the left of the connector.
5.2.1.2 Module Pins - Module pins are redundantly noted for each signal occurrence. If a signal occurs on several
sheets of a module, the module pin appears for each entry. Module pins are presented in their backpanel context
with machine slot and section noted. For example, F07Dl refers to the Dl module pin in section F of slot 07.
5.2.1.3 Print Prefixes - Print prefixes are provided for each signal to identify the print upon which the signal was
generated. Since a most usual manner of logic debugging involves the tracing of signals back to their source, the print
prefixes are most important. For example, Kl-7 BOVFL L signal indicates a source print of Kl-7, which is sheet 7
of the Kl print set for the M7231, DATA PATHS module. Print prefixes for the various modules are correlated as
follows.

5-1

Module

Print Prefix

M7231
M7232
M7233
M7234
M7235
M7236
M7237
M7238
M7239

Kl
K2
K3
K4
KS
KT
KJ
KE
KF

Option

KDl 1-A Processor

KTl 1-D Memory Management
KJ 11-A Stack Limit Register
KEl 1-E Expanded Instruction Set
KEl 1-F Floating Instruction Set

Sheet information for each print prefix occurs as a dash and number after the print prefix. BUS print prefixes occur
when multiple sources for a signal can exist; these signals are usually associated with wired-OR signal connections.
5.2.1.4 Signal Level Indicators - Signal level indicators are provided by print suffixes of H for high and L for low.
These indicators attempt to relate a level with signal activation. The high and low levels in the KDll-A Processor
usually correlate with TTL logic levels. For example, K3-6 WAIT L indicates that the line, so labeled, will be low
when the situation WAIT exists.
Two exceptions and qualifications to this nomenclature exist. The BUS U (56:09) L signals from the ROM have a
low indicator because of the wired-OR nature of the bus; in reality, the U WORD Buffer and ROM are active for
high levels out. Clock signals such as K4-2 CLK IR Hare active on the positive transition of the signal as they clock
D-edge type flip-flops.
5.2.1.5 Flip-Flop Outputs - Flip-flop outputs are allowed two forms for a single signal output. The 1 output of a
flip-flop can be represented as (1) Hor (0) L with corresponding references for the 0 output of (0) Hor (1) L. This
nomenclature recognizes the duality of any given logic signal, but in the KDl 1-A Processor, it is allowed only on the
flip-flops. Signals such as K3-8 CINOOL are not presented as K3-8 -CINOO H, where the leading dash represents
negation of the signal name.
5.2.1.6 Inhibit Situations - Inhibit situations are noted on the input to logic gates when the signal level indicator
of the input signal does not match the state indicator on the logic gate input. This technique allows the assignment
of a singular name to a logic line, with the duality of names resolved in a gate inhibit. Instead of trying to match an
input state indicator with a signal level indicator and a negated name, a direct inhibit appears in the conflict between
the state indicator and the singularly named signals with assigned signal level indicators.
5.2.1.7 Parentheses and Colons~ Parentheses and colons are used to indicate inclusi,ve groups of bits. A signal BUS
U (56:09) L indicates the BUS U signals for bits 56 through bit 09. This grouping of bits occurs in actual signal
names used on the prints; it is also used to group for discussion, signals of like nature that appear singularly on the
prints.
5.2.1.8 Parentheses and Commas - Parentheses and commas are used to specify singular bits in a signal. The signal
K4-3 CLR UPP (7, 6, 2) L indicates a clearing operation on bit 7, bit 6, and bit 2.
5.2.1.9 Basic and Expansion Signals - Basic and expansion signals in the machine are noted with leading Bs or Es.
For example, Kl-7 BOVFL STOP His a signal generated in the basic KDl 1-A Processor, while KJ-2 EOVFL STOP
H is a signal generated in an option or expansion of the basic processor.

5-2

S.2.1.10 Logic Symbols - Logic symbols for the KDll-A Processor include simple logic gates and flip-flops, and
complicated medium and large scale integration (MSI and LSI) gates. Symbols for the latter devices tend to be
rectangular with function information and grouping provided on the symbols. Truth tables are provided on the
appropriate logic prints.
S.2.1.11 System lnfonnation - System information is provided on a number of logic prints in the form of tables
and waveforms.
S.2.1.12 Jumper Infonnation - Jumper information is provided on each print for option connection. Fixed
formats on the etch board also provide information. Jumper numbers (Wl, W2, etc.) are etched in the rest (or basic)
position where two jumper positions are possible. Note on the STATUS board that W notations for the PWR UP
jumpers provide the basic vector of 24.
S.2.1.13 Cable Connection - Cable connection information is provided on each print and on the etch boards.
Special attention must be given to shield location as noted on the prints and on the etch.
S.2.2 Wire List Fonnat
S.2.2.l Alphabetical Searches - Alphabetical searches for signal names are eased by the listing of signal names
without their print prefixes. The print prefix can still be determined by noting the source print in the REMARK
column. The print prefix is needed in identifying the signal on the logic prints.
S.2.2.2 Print References - Print references are noted in the DRAW column for all prints on which a signal occurs.
Multiple sheet entries within a print set are noted without commas between the sheet references. For example, the
entry K4-235 indicates that the signal occurs on sheets 2, 3, and 5 of the K4 print set (no print sets have more than
nine sheets).
S.2.2.3 Etch Backpanel - Etch backpanel information is contained in the wire list and is identified by an Hin the
Q column and a Pin the REMARK column. EXCEPTION column notations for etch connections should be ignored.
S.2.2.4 Forward Searching - Forward searching for logic interaction (where the signals are used) is best done
through the wire list. All signals for a given name are noted with appropriate print references.
S.3 M7231, DATA PATHS, Kl MODULE
The DATA PATHS module includes the following logic:
a.

The Arithmetic Logic Unit (ALU) with an A input and a B input with multiplexer (B MUX) and register
(B), and an output register (D).

The Bus Address Register (BA) with its input multiplexer (BA MUX) and output drivers to the Unibus.

Processor address decoding upon the internal Bus Address Register. This address decoding is not on the
Unibus; therefore, these addresses only respond to processor (console or program) addressing.

D Register decoding for sensing when portions or all of D is zero.

The Scratch Pad Register (REG) with its associated addressing selection under direct microword control.

A console interface with drivers for data display of the D MUX signals, input receivers of the Switch
Register setting on the console, and XOR matching circuit between the low order Switch Register (SR)
settings and the Buffered Microprogram Pointer (BUPP) to determine when the microprogram matches
the console switch settings.

5-3

Print Kl-2: DATA PATHS (03:00)

This print shows the data path for the data bits 03 to 00. It has the ALU and its associated A and B input logic as
well as the output D Register and Bus Address Multiplexer (BA MUX).
Kl-2 D MUX (03:00) H signals at the output of the D Multiplexer provide a main data path in the machine with
inputs to the B Register associated with the ALU- and to each of the other processor registers including the Scratch
Pad (REG) and the Processor Status (PS) Registers. These signals are also available on the back panel and are used in
processor options (KEl 1-E, KEl 1-F, KTl 1-D).
The following inputs are combined or multiplexed into the D MUX signal: the D Register at the output of the ALU,
the buffered UNIBUS BUS D signals, a right shifted output of the D Register, and the buffered BUS RD signals. The
latter signals (BUS RD) are from the outputs of the various processor registers located in the DATA PATHS section
of the machine and include Scratch Pad (REG), Instruction (IR), and Processor Status (PS) Registers, as well as
other processor option registers. The D MUX signals are displayed on the DATA display on the console.
Kl -2 COUT03 L signal is the carry out of the third bit of the ALU. It is a signal derived in the carry bridging
network of the 74182. This carry bridging is used to allow a faster settling of the 74181 by looking ahead to
determine if carries exist.
Kl-2 D (03:00) (1) H signals output the D Register as noted, input to driver 8881 gates to the UNIBUS, and feed
around to the D MUX on the input to the B side of the ALU. The D Register is essential in the data path because of
the need to hold data for Unibus operations and for rewrite to the Scratch Pad Register (REG). The latch nature of
the Scratch Pad Register requires a storage device in the data loop to avoid a simultaneous read and write situation in
the scratch pad. The Kl-2 DOO (1) H signal is also used for carry data (K3-9 C DATA H) in a Rotate Right
instruction.
BUS D (03:00) L provide the Unibus BUS D signals through appropriate drivers (8881s) with gating signal K4-5 BUS
FMDH.
Kl -2 CLR D H signal is noted as an output only to avoid repetition of the pull-up resistor throughout the next three
prints. The clear input of the D Register is essentially tied high and is not used as a signal. The D Register, as many
of the other registers in the KDl 1-A Processor, are never cleared; they are assumed to have erroneous information
until proper information is clocked into them.
Kl-2 BA MUX (03:00) H signals are the inputs to the Bus Address Register (BA) located on the module (print
Kl-6). Multiplexed signals allow selection of either the output of the ALU or the buffered bus RD signals as the
input to the Bus Address Register. The choice of these inputs is a function of microcontrol for a flow operation in
process. The buffered bus RD input is provided for speed for operations in which the machine waits on bus
operation, with the address coming from the Scratch Pad Register (REG). The ALU input accommodates those
situations in which data is altered before use.

5-5

Kl-2

Print Kl-3: DATA PATHS (07:04)

Kl-3 D MUX (07:04) H
Kl-3 D (07:04) (1) H
BUS D (07:04) L
Kl-3 BA MUX (07:04) H
Kl-3 COUTO? L

With the exception of bit references, these signals are
similar to signals on the Kl-2 print.

Kl-3 D07 (1) H signal provides sign information for byte data and is used as an input to the condition codes on print
KS-2.
Kl-3 RD07 H signal is the highest order bit of byte data for the A input of the ALU. It is used in the status module
(print KS-2) to determine overflow conditions in the ALU.
Kl-3 B MUX07 H signal is the high order bit of the byte input to the B input of the ALU. It is used in the status
module (print KS-2) to determine the overflow condition.
Kl-3 ALU07 H signal is the direct output of the ALU prior to the B Register. It is provided for test purposes.

5-7

Kl-3

Print K14: DATA PATHS (11:08)

K14 D MUX (11 :08) H
K14 D (11 :08) (1) H
BUS D (11 :08) L
K14 BA MUX (11 :08) H
K14 COUTll L

With the exception of bit references, these signals are
similar to signals on the Kl-2 print.

5-9

Kl-4

Print Kl-5:

Kl-5 D MUX (15:12) H
Kl-5 D (15:12) (1) H
BUS D (15:12) L
Kl-5 BA MUX (15:12) H

DATA PATHS (15:12)

With the exception of bit references, these signals are
similar to signals on the Kl-2 print.

Kl-5 D(C) (1) H signal is fed around into the D MUX on this same sheet and is used in a rotate right situation. The
D(C) flip-flop is an extension of the D Register for the carry bit. The COUT MUX allows microcontrol selection of
the carry output of the ALU on its inputs for word or byte, the carry bit of Processor Status PS(C), and bit 15 of
the ALU output for shift or rotate.
Kl-5 COUT MUX (L) signal is the selection of the aforementioned signals on the input to the D(C) flip-flop. The
signal provides a test point.
Kl-5 COUTl 5 L signal is the carry output of bit 15 of the ALU. It is used as one of the inputs for the COUT MUX
and is used in the KE 11-E option.
Kl-5 RD 15 H signal inputs to bit 15 of the arithmetic input on the A side. This signal is used in this module as an
input to the D MUX and BA MUX, as are all of the buffered BUS RD signals. It is also used as an input to the
condition code logic for determination of word overflow conditions (print K5-2).
Kl-5 B MUXl 5 H provides the bit 15 input to the ALU on the B side. This intermediate signal is used on the
STATUS board in the condition code logic to determine word overflow conditions (print K5-2).
Kl-5 ALUl 5 H is the output of bit 15 of the ALU and is used as an input to the D Register, the BA MUX, and the
COUTMUX.
Kl-5 Bl 5 (1) H signal is bit 15 of the B Register. It is used as an input to the B MUX on this print and the SWAP
BYTE input on print Kl-3. The KEll-E and KEl 1-F options also utilize this signal.

5-11

Kl-5

Print Kl-6: BA (15:00)

This print contains the Bus Address Register (BA) and the bus driving gates to the Unibus. The bus address signals
for bits 16 and 17 are derived from bits 13, 14, and 15 for the basic K.Dl 1-A. The Unibus drivers, BUS A (15 :00),
on the print can be disabled when the KTl 1-D option is installed; then the above bus address bits are provided by
logic on the M7236 module of the option.
Kl -6 BA ( 17* 16) H signal is a direct function of the bus address bits 15, 14, and 13 being set. This signal is used for
display purposes (print Kl -9) and with the KTl 1-D option.
BUS A (17:00) L Unibus signals provide the bus address signals from the processor and are gated by K4-5 BUS FM
BA H. If the KTl 1-D option is installed, a jumper (WlO) grounds the enabling signal of the 8881 gates for bus
address bits (15 :06).
Kl-6 BA (15:00) (1) H signals are the direct output of the Bus Address Register. These direct outputs are used for
driving the Unibus gates on this print, for decoding of processor addresses (print Kl -9), for data display (print K5-7),
and for generation of Unibus addresses for the KTl 1-D option (if installed). Some of the signals are used with the
KJl l option for comparison against the Stack Limit Register. Low order signals for bits 03 to 00 are used as one of
the REG selection address inputs. Additional uses for the BAOO are odd byte address sensing, allowance of odd byte
(print K44), and byte branching information for the BUBC codes (print K3-7).

5-13

Kl-6

Print Kl-7: ADRS DECODE

The decoding of the Bus Address Register prior to the Unibus limits the use of these addresses to processor
references. The addresses are not derived from the Unibus and it is not possible for a peripheral to access these
addresses. The Bus Address Register is also decoded to determine the absoluteness of an address for stack overflow
sensing. Decoding logic is also provided on the D Register to sense the status of its contents on byte or word basis.
The table at the right of the sheet ·provides correlation between the mnemonic for an address and the octal value of
the address in the bus address register. Notes are also provided for jumper selection.
Kl-7 PS ADRS H decodes the processor status address to enable the combinational logic inputs to the Processor
Status Register (print K5-2) and sequencing of a BUS SSYN response by the processor (print K4-6). The address is
also utilized in the microbranch code to ensure a reservice of possible bus requests because of a change in machine or
processor status (print K5-7). The signal is provided by the KTll-D option when installed; the jumper (WI) is
removed and the option provides the processor status address.
Kl-7 SLR ADRS H addresses the Stack Limit Register and is normally disabled by a jumper (W2) to ground, unless
the option KJII-A is installed. When KJll-A is installed, the signal provides selection of that register and the
sequencing of a BUS SSYN through logic on print K4-6. The signal is also wired to the KTI 1-D slot so that if this
option is installed it can provide the address. The jumper (W2) is removed and the KTI 1-D provides the Stack Limit
Register address.
Kl-7 REG ADRS H provides the scratch pad Unibus addresses used during console operation. The jumper (W3)
allows generation of the signal from this source or from the KTl 1-D option, if installed. The signal, when present, is
utilized in the branch circuits of console operation to effect proper incrementation and access under console
operation (print K3-2). Access to the Scratch Pad Register during instruction operation is through Instruction
Register decode. Direct specification of registers is done by the address selection logic on print Kl-8 under
microprogram control.
Kl-7 SR ADRS H provides Switch Register address decoding and allows derivation, either from this module or by
removal of the W4 jumper from the KTl 1-D option. The generation of this address, as with other processor
addresses, results in the sequencing of BUS SSYN through the logic shown on print K4-6.
Kl-7 BA (06:03) = 0 H signal is a test point for determining that those bits of the bus address are zero.
Kl-7 BA (07:05) = 1 L signal is a decoding of the segment of the bus address bit 07-05, and is used with the
KJl 1-A option.
Kl-7 BA (15:08) = I L signal is a decoding of the Bus Address Register to determine content and not an address
situation. This output is for test purposes.
Kl-7 BOVFL STOP H signal detects a red zone stack violation and is used to interrupt the microflow (print K4-4).
Kl-7 BOVFL L signal is used to sense a yellow zone stack violation and is used to set a trap servicing flag (print
K5-4).
Kl-7 D (15 :00) = 0 H indicates that those bits of the D Register are zero. This signal is used as an input to the
condition codes for the Z bit of processor status (print K5-2); it is also used as an input to the microbranch logic
(print K3-2). This signal is also used in the KEI 1-E and KEl 1-F options.
Kl-7 D (03 :00) = 0 H signal is used for a partial indication that the byte data of bits D (07 :00) is zero for the inputs
to the conditional codes of processor status (prints K5-2).

5-15

Kl-7

Print Kl-8: REG [15:00] (15:00)

This print contains the Scratch Pad Register (REG), basic to the PDP-11 architecture. There is address selection
enabling either direct and complete selection by the microprogram control, or selection by the Instruction Register
source field, the Instruction Register destination field, or the lower bits of the Bus Address Register. Some variations
in the addressing are affected by jumpers (W5, W6, and W9) when the KTl 1-D option is installed. The registers
themselves take data from the D MUX signals and output data onto the BUS RD lines. The resistor terminator for
this wired-OR BUS RD bus are shown on this print.
BUS RD (15:00) L common input bus in the data paths has several sources. Its input is shown on prints Kl-2
through Kl-5, with sources from the Scratch Pad Register (REG) (this print), from the processor status system (PS)
(print K5-2), and from the KEl 1-E and KEl 1-F options, as well as the KTl 1-D options.
Kl-8 R (X6+ X7) H signal senses selection of either register 6, 7, 16, or 17 (octal addresses) and is used to force an
increment of 2 on any byte operations referencing register 6 or 7 in the instruction set (print K3-8). It is also used to
enable the check overflow logic when the Processor Stack Register is accessed (print K4-4). This last use requires the
Kl-8 RADRSO L signal.
Kl-8 RAD RS (03 :00) L. These are the actual signals applied to the Scratch Pad Register ICs. They are the
complement of the address applied to the selection AND/NOR gates. The signal Kl-8 RADRS 0 L is used in
conjunction with Kl-8 R (X6+X7) H to specifically indicate the Stack Pointer (REG 06) to enable the check
overflow logic in the bus timing circuitry (print K4-4).

5-17

Kl-8

Print Kl-9: CONSOLE AND MATCH

This print shows the connector interface to the KYl 1-D console. The DATA display is provided with type 380 gates
buffering the D MUX (15:00) signals. In addition, the Switch Register signals from the console are brought in and
enabled by the Kl 4 BUS FM SR H signal through type 8881 gates to the Unibus BUS D (15 :00). A matching circuit
is provided which compares the lower order Switch Register settings [SR (08:00)] with the basic microprogram
pointer (BUPP) signals. Upon a match, pulse Kl-9 P MATCH Lis generated. This pulse occurs at the beginning of
the microword specified in the Switch Register. The signal Kl-9 UPP MATCH H is used with the maintenance
console for a HALT on match. (See restrictions below.)
Kl-9 SR (17: 16) H signals for the bits 17 and 16 Switch Register settings come from the console through this
module and are provided to the KTl 1-D option, which allows a physical address involving these address bits (print
KT-9) during console operation.
BUS D ( 15 :00) L Unibus signals are enabled by K44 BUS FM SR H to allow the Switch Register settings onto the
Unibus.
Kl-9 UPP MATCH H signal provides a level output when the Switch Register settings bits (08:00) match the
buffered UPP signals. This signal is used on the timing board in conjunction with the KM 11-A Maintenance Console
option to halt the machine at the specified microaddress. The limitation is that the matching address must have a
CL2 or CL3 preceding it.
Kl-9 P .MATCH Lis a timing pulse which occurs at the end of a machine cycle, gated against the aforementioned
match signal to provide a scope triggering pulse at the beginning of the selected word. This occurs independently of
the maintenance module and is of value in situations where the machine will not be halted. For both of these
instructions, the maintenance console section should be referenced for specifics of operation.

5-19

Kl-9

5.4 M7232, U WORD, K2 MODULE
The M7232 module for the U WORD (U is used in place of the Greek letter Mu for micro) provides the central
portion of the microcontrol. It contains the basic processor's read-only memory (ROM), the U WORD Register
(various mnemonics per function), the Past Microprogram Pointer Register (PUPP), and certain driving buffering
gates for signals BUPP (08:00) and EUPP (08:00). Connectors at the back module edge interconnect to the KEl 1-E
option for expansion of the basic microword ROM.
The U WORD logic on the M7232 module is very regular. The ROM has 256 words, each of which has 56 bits.
Output signals from the ROM, BUS U (56:00), feed a resistor terminator with a wired-OR input from the module
connectors located on the rear of the module. l'hese inputs are for optional expansion of the ROM beyond 256
words. The BUS U signals feed the U WORD Register that controls the machine. The first segment of the ROM
(07:00), on prints K2-2 and K2-3, is concerned with the microaddress and has 74H10 gates between the ROM
output and the U WORD Register [UPP (08:00)]. These gates allow the next base address, BUS U (08:00), to be
modified, if necessary, by basic microbranching logic [K3-2 BUBC (04:00)] or expanded microbranching [KE4
EUBC (04:01)]. Additional logic exists on the output of the UPP portion of the U WORD for driving expansion
ROMs and for storage of the present microaddress, PUPP (08:00).
The use of the BUS U (56:00) L signals and the low state indicator on the ROM gate output indicate the physical
wired-OR nature of these signals. No absolute correlation should be made between low active and the state of the
ROM output or the U WORD Register. For U (56:09), a high level indicates a true or active signal, both at the ROM
output and in the U WORD Register. This is presented in the microflow diagrams on sheets 9 through 12. For U
(08:00), the microaddress portion of the microword, a low output at the ROM output represents an active or true
signal. This complementing of the ROM pattern occurs because of the inversion in the 74H10 gate prior to the U
WORD Register, UPP (08:00). In the U WORD Register, a high level represents an active or true signal. The flow
diagrams on sheets 9 through 12 show the complement of the ROM output for the UPF field; this is done to allow
the address reference from the flow diagrams without the need to complement. Note that the UPF field represents
the complemented ROM output of the next address without reference to microbranch inputs. If there are not
microbranch inputs, the UPF field represents the U WORD Register, UPP (08:00).
The output signals noted in detail for this module are primarily those of the U WORD Register. These signals, with
the alterations possible to the UPF field, are directly compatible to the BASIC U WORD noted in the block diagram
of the U WORD and the tables shown on engineering drawing D-BD-RDl 1-A-BD. This drawing also provides
numerous tables of the microprogram control fields, noting the codes, the effect, and occasionally the purpose.
The signals on prints K24 through K2-8 are presented in order from bottom to top. This is in order of ascending
BUS U allocation, and represents a logical presentation of the functions.

5-21

Print K2-2: U (03:00)

K2-2 BUPP (03 :00) H signals are the Buffered Microprogram Pointer signals for the noted bits. They are used to
address expansion ROMs in the KTll-D, KEll-E, and KEll-F options. They are also displayed on the KMll-A
Maintenance Console and are matched against the Switch Register for a HALT or for scope timing pulses (print
Kl-2). Note that the microword address present here is the address of the next microword. Alterations for
microbranching will have already occurred prior to the input to the UPP Register, if they were to occur. Only a
microjam (JAM CLK on print K4-3) can alter this address by setting or clearing the UPP Register. This change is
then reflected in the signals.
K2-2 PUPP (03:00) (1) H signals are the output of the Past Microprogram Pointer Register. It provides the
microprogram address of the microword presently in the U WORD Register. The PUPP Register is displayed in the
KMl 1-A Maintenance Console option for the basic machine. This register is necessary to record the present
microword address since the microword in the U WORD Register contains only the next address. As this word is
changed [K4-2 CLK (UPP*PUPP) H], the next address (now the present address) is transferred to the PUPP
Register. Most searches in the microflow diagrams (prints 9 through 12 of the M7232) for detailed operation will use
the PUPP address as the starting point.
K2-2 CLR PUPP L signal is used only to hold the CLR input of the PUPP Register high. It is labeled for reference on
print K2-3 to eliminate repetition of the pull-up resistors.

5-23

K2-2

Print K2-3: U (07:04)

K2-3 BUPP (08:04) Hand K2-3 PUPP (08:04) (I) Hare similar to the corresponding signals on the K2-2 print with
the exception of bit references.

5-25

K2-3

Print K2-4: U (16:09)

K24 CLR U {16:09) signal represents a pull-up resistor to the clear lines noted for the U WORD Register.
K24 RIFO (0) H is used on the address input to the Scratch Pad Register for a special situation in which the
KTl 1-D Memory Management option provides the user Stack Pointer instead of the usual REG 06 Stack Pointer.
The RIF notation is discussed in the following paragraph.
K24 RIF (03:00) (I) Hare the Register Immediate Field signals which allow direct microprogram addressing of the
16 Scratch Pad Registers (REG) when the Select Register Immediate microcontrol is enabled. Direct microword
selection of a Scratch Pad Register occurs at several points in the microflow. It is used during FETCH and in the
immediate address mode to explicitly select the program counter for incrementation. Trap sequences RTI and RTS
instructions directly address the Stack Pointer and Program Counter registers. REG 0 is selected during the
execution of the HALT instruction and during console operations.
K24 RI 25 PULL UP H signal is an identification of the resistor pull-up noted for use on print K2-3.
K24 SRI (I) H is the Select Register Immediate signal which is used in the Scratch Pad Register selection logic
(Kl-8). It enables the register immediate field provided by the microword to directly select a Scratch Pad Register
(REG).
K24 SRBA (I) H signal is the Select Register Bus Address signal which enables the lower four bits of the Bus
Address Register to select a Scratch Pad Register. This selection is used in the EXAMINE and DEPOSIT microflow
for console operation. It is specifically used when an internal Scratch Pad Register address is accessed. The
nomenclature used in the flow diagrams is R(BA), which indicates an internal register addressed by the Bus Address
Register.
K24 SRD (I) H is the Select Register Destination signal which is used in the scratch pad address logic to enable the
destination field of the Instruction Register IR (02:00). This field is used for various instructions that have
destination addresses.
K24 SRS (I) H is the Select Register Source signal which is used in the Scratch Pad Address logic to enable the
source field of the Instruction Register IR (08:06). This field is used in binary instructions.
NOTE
The use of discrete 74H74 flip-flops for the U WORD Buffer
for REG addressing controls reflects the emphasis on reducing
access time for data.

5-27

K2-4

Print K2-S: U (28:17)

K2-5 UBF (04:00) (1) H are the Microbranch Field signals which enable various test conditions for branching the
microprogram address. The actual switching of various conditions is done in the multiplexers shown on print K3-2.
A total of 32 possible microbranch tests are enabled throughout the microflows and are directly noted in the flow
diagrams by the BUT notation (Branch Microprogram Test) and in the table on print D-BD-KDl 1-A-BD. The
enabled tests may consist of a number of bits or a single bit and may relate to the Instruction Register or to a single
flag flip-flop.
The UBF field is also decoded on the STATUS board (print KS-3) to provide enabling signals during the microwords
in which this field of a specific BUT is present. The decoded signals are used to clear or set flags relating to the tests
upon which a Branch Microprogram Test is being performed.
K2-5 SBAM (1) H is the Select Bus Address Multiplexer signal and is used on the data path to control the Bus
Address Multiplexer (prints Kl-2, 3, 4, 5). It selects either the buffered BUS RD data or the output of the ALU for
input to the BA Register. A high level in this microcode control bit enables the ALU output to the Bus Address
Register data input.
K2-5 SDM (01 :00) (1) Hare Select D Multiplexer signals and are used in the data path (Kl-2 through Kl-5) to select
the D MUX signal from four possible sources. The output code, or enabling levels, provided by this field can be
directly associated with the 74153 multiplexer logic symbol and truth table located on the DATA PATHS prints.
Essentially, a 00 SDM code selects the A input (BUS RD); a 01 SDM code selects the C input (D Register); a 10 code
selects the buffer Unibus data (BUS D); and a 11 SDM code selects the D input (right shifted D Register).
K2-5 SBML (01 :00) (1) H are Select B Multiplexer Low microcontrol signals which provide selection signals to the
lower eight bits of the B MUX in the DATA PATHS shown on prints Kl-2 and Kl-3. The separation of the B MUX
into an upper and lower portion for microcontrol allows additional flexibility in handling byte, sign extend, or swap
byte situations. The code enables the following to the B input of the ALU:
a.

An SBML code of 00 selects the low byte of the B Register directly.

An SBML code of 01 selects the low byte of the B Register directly and is used for sign extension in the
upper byte [B MUX (15 :08)] .

An SBML code of 10 selects the upper byte of the B Register for a swap byte instruction. For example,
bit 8 of the B Register is put in the bit 0 position of the ALU; this is true in sequence for the other bits.

An SBML code of 11 selects the B constants [BC (07:00)] as inputs to the ALU.

K2-5 SBMH (01 :00) (1) Hare the Select B Multiplexer High signals which provide selection signals to the upper byte
of the B MUX in the DATA PATHS on print Kl4, 5. The code enables the following to the B input of the
arithmetic logic.
a.

An SBMH code of 00 selects the B Register directly for the B input.

An SBMH code ofOl selects the sign extension bit (B07) for the B input.

An SBMH code of 10 selects the lower byte of the B Register for a swap byte situation.

An SBMH code of 11 selects the B constants. These constants are not discrete for each bit input on the
higher byte, but instead consist of a discrete input for bit 11 and a composite input BC (15: 12, 10:08) H
for the other inputs.
5-29

K2-5

Print K2-6: U (40:29)

K2-6 SBC (03:00) (1) H are Select B Constant signals which provide selection through combinational logic (print
K5-5) of a possible 16 constants for use by the B Multiplexer. The encoding of constants selection is utilized to
conserve microcontrol storage (ROM) bits. A table of the constants is provided on print K5-5 and the block diagram
print D-BD-K.Dl 1-A-BD.
K2-6 SALU (03:00) (1) H are the Select Arithmetic Logic Unit signals which provide direct microcode selection of
the functions that the ALU will perform. These signals are selected by logic on print K3-8 for direct ALU control
unless a DAD microcode of 1 lXX is present. (See the DAD table on print D-BD-K.Dl 1-A-BD. The ALU table on the
same print also notes the Instruction Register and ALU interaction.)
K2-6 SALUM (1) H is the Select Arithmetic Logic Unit Mode signal which is used in the same way as the SALU
codes previously mentioned. It is used directly on the logic shown on print K3-8 and comprises a DAD code which
allows IR selection of the ALU function.
K2-6 SPS (02:00) (1) H are the Select Processor Status signals which provide an encoded combination for various
functions on the processor status word. These operations on the processor status word are not unlike the encoding
of the microword for the discrete alteration of data (DAD) codes. A table of SPS codes and functions is noted on
the block diagram print D-BD-K.Dl 1-A-BD. Specific bits perform certain functions, and there is also a total decoding
of these bits to perform other functions. The code is used in the logic shown on print K5-2 to directly select the
inputs to the Processor Status Register, in the logic shown on print K5-2 to directly select the inputs to the
Processor Status Register, and in the logic shown on print K3-9 to effect the condition code inputs.

5-31

K2-6

Print K2-7: U (52:41)

K2-7 DAD (03:00) (I) H are the Discrete Alteration of Data signals which provide an encoded portion of the
microword used throughout the machine to allow exceptions. It is used with Unibus cycles to check for odd address
or stack overflow, and in the ALU logic to allow alteration of the code as a function of the Instruction Register. The
DAD code is also used within the console loop for setting and clearing EXAM and DEP flags on consecutive
operations. A summary of usage is provided in the DAD table on the block diagram, U WORD, and tables, print
D-BD-KDl 1-A-BD.
K2-7 BGBUS (1) H is the Begin Bus signal which forms a clock bus signal with a Pl or P2 pulse (print K44). This
clock bus signal, in tum, is used to clock the initiating signals shown on print K44 to begin a bus cycle, and also to
load registers with various error and stack conditions which should be checked on each operation. Signal BGBUS,
shown on print K4-5, is used to clock the NPR signals.
K2-7 C (01 :00) BUS (I) H signals consist of the Cl BUS and CO BUS signals usual to the Unibus. These control
signals are clocked into holding flip-flops shown on print K44 for use throughout the bus cycle.
K2-7 CLKBA (1) His the Clock Bus Address signal and it provides an enabling signal for the pulses (print K4-2) used
to clock the Bus Address Register.
K2-7 CLKD (I) H is the Clock D signal which provides an enabling signal for the pulses (print K4-2) used to clock
the D Register.
CLKB (1) His the Clock B signal which provides an enabling signal for the pulses (print K4-2) used to clock the B
Register.
K2-7 WRL (1) H is the Write Low signal which provides a signal to enable a Write signal (print K4-2) to the Scratch
Pad Register for the lower byte.
K2-7 WRH (1) H is the Write High signal which provides a signal to enable a Write signal (print K4-2) to the Scratch
Pad Register for the upper byte.

5-33

K2-7

Print K2-8: U (56:53) AND CONNECTORS

K2-8 CLKIR (1) H is the Clock IR signal which provides an enabling signal for the pulses (print K4-2) used to clock
the Instruction Register. It is enabled only during the FETCH cycle.
K2-8 CLKOFF (1) H is the Clock OFF signal which is used in the logic shown on print K4-2 to provide direct
microprogram control of clock continuance. When this bit is enabled, the Clock IDLE flip-flop is clocked on while
the Clock RUN flip-flop is clocked off. The CLKOFF microcontrol stops the processor directly after the microword
in which it appears. The processor then waits for an external asynchronous start signal on the set input of the RUN
flip-flop.
K2-8 CLKL (01 :00) (1) Hare the Clock Length Code signals which provide selection of the cycle lengths used in the
current microword. This signal (print K4-2) controls the pulse stream within the delay line chains. A CLKL code of
00 or 01 causes a Clock Length 1 (CLl) signal. If the CLKL code 00 is used, a special overlap situation may be in
effect. A CLKL code of 10 effects a Clock Length 2 (CL2), a CLKL code of 11 effects a Clock Length 3 (CL3). The
normal duration of these respective cycles are:
CLl
CL2
CL3

140 ns
200 ns
300 ns

K2-8 CLKL (01 :00) (0) H signals are the complement of the clock length code and are used to ensure direct and
rapid gating of the basic clock signals within the delay line chains.
CONNECTORS - On this sheet, the interconnection to the KEl 1-E and KEl 1-F options are shown. The BUS
signals noted as inputs (signals to the right of the connector) are wire-ORed throughout the module to the basic
ROM output. EUPP (07:00) output signals (to the left of the connector) provide the address signals for the
expansion ROM.

5-35

K2-8

U WORD Microprogram Listing

Sheet 9 (ADR000-077)
Sheet 10 (ADRl00-177)
Sheet 11 (ADR200-277)
Sheet 12 (ADR300-377)
The U WORD Microprogram Listing presents the--read-only memory (ROM) content of the M7232 module and of
the KD 11-A Processor. The format is as follows:
Octal notation is used throughout the listing for word addresses and the contents of the individual
microprogram fields.
Addresses of the U WORD are presented downward in octal numerical sequence under the ADR (address)
column. The addresses correspond to those noted in the flow diagrams (D-FD-KDl 1-A-FD). Each address
presents the complete microword for that address in the same horizontal line.
Functions of the U WORD are listed across the top of each table. These functions represent individual bits in
the U WORD and are presented in fields. The fields are associated with the individual U WORD bits in the
block diagram, U WORD, and tables print D-BD-KDl 1-A-BD.
The mnemonics for the U WORD fields (right to left) are as follows:
UPF
U(08:00)

Microprogram Pointer Field represents the next microword base address in the present ROM word.
This field is complemented at the output of the ROM. The field is uncomplemented in the U
WORD Buffer Registers (UPP 08:00) but may have microbranch alterations already made to the
ROM output. At this point, the address becomes that of the next ROM word and is used to
address the ROM. The transfer of this address to the PUPP Register when the next ROM word
enters the U WORD Buffer Register facilitates comparison of the U WORD and the Microprogram
Listing. In the single clock mode of the maintenance console option (KMl 1-A), the PUPP address
can be used in the ADR column to find the current controlling microword. The Microprogram
Listing can also be correlated with the flow diagram from its microword address.
NOTE
With the exception of the UPF field, the function and states of
the other fields are directly (uncomplemented) represented at
the output of the ROM and in the U WORD Buffer. Details of
operation have already been presented in the logic discussion
on the U WORD Buffer signal outputs.

RIF
U(12:09)

Register Immediate Field selects a scratch pad address when enabled by the Select Register
Immediate bit (Ul 3) of the SRX field.

SRX
U(16:13)

Select Register provides an address mode for Scratch Pad Register selection where X can be Select
Register Immediate (SRI), Select Register Bus Address (SRBA), Select Register Destination
(SRD), or Select Register Source (SRS).

UBF
U(21: 18)

Microbranch Field enables the logic which can alter the UPF microword address to allow a
branching of the microprogram flow. The U WORD Buffer for this field is UBF (04:00). A
correlation is made between the Branch Microprogram Test (BUT) number and its purpose on
print D-BD-KDl 1-A-BD.

5-37

U-WORD

SBA
U22

Select Bus Address directly controls the Bus Address Multiplexer on the input to the Bus Address
Register. When enabled, the U WORD Buffer signal, SBAM, selects the ALU output instead of the
BUS RD signal output.

SDM
U(24:23)

Select D Multiplexer directly controls the selection of inputs on the D Multiplexer (D MUX). Its
octal codes 0, 1, 2, and 3 correlate respectively to the A, B, C, or D inputs in the logic symbol.

SBM
U(28:25)

Select B Multiplexer directly controls the selection of the inputs on the upper and lower byte
sections of the B Multiplexer (B MUX).

SBC
U(32:29)

Select B Constants controls the logic which generates B constants, which are then selected by the
B Multiplexer. The code, the constants, and the purpose of the codes are presented in the SBC
table on print D-BD-KDl 1-A-BD.

ALU
U(37:33)

Arithmetic Logic Unit controls the mode of operation of the ALU in the data paths. The code is
not used directly and allows discrete alteration as a function of the Instruction Register. This
interaction is shown in the ALU table of the block diagram, U WORD, and tables print
D-DA-KDl 1-A-BD.

SPS
U(44:41)

Select Processor Status provides a discrete and encoded microcontrol of the input and clocking of
the processor status word. This control is especially concerned with the individual response by the
condition code portion to each instruction.

DAD
U(44:41)

Discrete Alteration of Data is a microcode field that provides for the alteration of usual usages of
data (including microcode data). A usual alteration is the checking for odd addresses or stack limit
violations during bus operations initiated by microprogram data. A table of functions and codes is
noted on the block diagram, U WORD and tables print D-BD-KDl 1-A-BD.

BUS
U(47:4S)

BUS operations for the Unibus are controlled by this microcontrol field. Included are the bus
control signals, Cl BUS and CO BUS, and their initiating signal BGBUS. A table of bus operations
(including the non-data transfers) is shown on print D-BD-KDl 1-A-BD.

CBA
U48

Clock Bus Address field provides the direct enabling signal for clocking the Bus Address Register.

CD
U49

Clock D field provides the direct enabling signal for docking the D Register.

CB
USO

Clock B field provides the direct enabling signal for clocking the B Register.

WR
U(S2:Sl)

Write field provides two directly used microword bits for writing into upper or lower byte of the
Scratch Pad Register.

CIR
USS

Clock IR field provides the direct enabling signal for clocking the Instruction Register.

CLK

Clock field contains both the clock cycle length control (CLKL 0, CLKL 1) and on-off control
(CLKOFF).

U-WORD

S-38

The three other columns contained in the Microprogram Listing are:

ADR

The microprogram address of the microword displayed on that line. This address can be obtained
from the flow diagram or from direct observation of the PUPP Register with the K.Mll-A
Maintenance Console option.

STATE

The mnemonic used in the flow diagram (D-FD-KDl 1-A-FD) to provide an immediate
identification of a microword. It is possible to refer to a microword in easier terms than its
address.

FLOWS

The page in the flow diagram (D-FD-KDl 1-A-FD) upon which the microword occurs. This
reference provides for a backward search from an address to a microword in its flow context.

5-39

U-WORD

5.5 M7233, IR DECODE, K3 MODULE

The IR DECODE module contains extensive combinational logic which decodes the Instruction Register (IR),
providing discrete instruction signals, as well as re-encoded microaddress information necessary for the
microbranches. The Instruction Register is present on this module, as is the BUT Multiplexer. In addition,
combinational logic exists for instruction control of the ALU and condition code inputs for the carry (C) and
overflow (V) bits of the Processor Status Register.

541

Print K3-2: BUT MUX

This print shows the Branch Microprogram Test Multiplexer which combines diverse microbranch tests into a limited
number of bits for a next microprogram address. There are essentially six multiplexers, two of which affect bit 0 of
the address; the other four multiplexers affect bit 1 through bit 4 of the address. The conditions gated to the address
are occasionally singular and named by the actual signal condition, such as JSR. The conditions are often complex
and affect more than one address bit; they are named in the standard way, such as K3-5, BUBCO (BUT37) H. This
signal is essentially a basic micro branch code that will affect the 0 bit of the microaddress for the BUT37. A table of
these branch microtests and their mnemonics appears on the block diagram print D-BD-KDl 1-A-BD. BUT37 is the
INSTR! branch occurring in FETCH; it branches to all the various response microflows for instruction
implementation. It has an input to each of the five affected address bits. Other BUTs only require one or two bits,
and therefore only input into one or two address bits. For this reason, the type of multiplexer related to specific
address bits changes. On bit 0 there are two multiplexers which input into two possible inputs in the NOR/OR gate.
For the next address bit there is a single 16-input multiplexer. For the next two address bits, there are 8-input
multiplexers and the upper two address bits have only 4-input multiplexers.
K3-2 BUT (37:34) Lis a decoding of the microbranch field (UBF) for BUTS 37 through 34. It is a single pin run and
is provided for test purposes.
K3-2 BUT (3X) signal is a decoding of the microbranch field (UBF). The signal is used to enable the multiplexers on
this sheet and on the STATUS module (prints K5-3 and K5-6) as an enabling signal for clocking flag flip-flops. The
signal is a partial decoding of branch microprogram test for BUT 30 through 37 octal.
K3-2 BUBC (05:01) L signals represent the basic micro branch code for address bits 5 through 1. They each represent
a single input to the NOR/OR gate where they can modify a base address when a branch test is called. These bits
provide the inputs for all branch tests, unlike the input for the 0 address bit which required two distinct inputs for
lower order and higher order BUTs. Selection of these inputs is a function of the microbranch field from the U
WORD applied against the appropriate multiplexers. In conjunction with the basic microbranch code, there are
expansion microbranch code bits also input to the NOR/OR gate.
K3-2 BUBCO (BUT37:20) L provides basic microbranch code 0 for BUT 37 through 20 (the notation is octal). It is
used in conjunction with the next signal to the exclusion of the expansion microbranch code for this bit. It is used
on K2-2 print in the NOR/OR gate.
K3-2 BUBCO (BUTl 7:00) L provides the basic microbranch code for bit 0 for the BUT 17 through 00. The signal is
selected as a function of the multiplexer and the UBF field in the U WORD, with the UBF field selecting the BUT
being applied against the base address. Thus, bit 0 has many test conditions applied against it, not only in the
complex codes but the single bit codes.

543

K3-2

Print K3-3: IR AND DECODE

This print shows the complete Instruction Register (IR), which has input data from D MUX (15 :00). All of the IR is
brought to the module edge for expansion and basic machine use. In addition to the IR, the first level of decoding is
provided by the 8251 Decoders. The binary instructions, the source mode, the destination modes, and intermediate
IR bit patterns are decoded.
K3-3 IR (15:00) (1) His the (1) side of the IR brought out for use within the basic and expansion machine. It is
used on various inputs in the IR DECODE itself, on other prints within the basic machine; it is also used in the
KEll-E option, the KEll-F option, and the KTll-D option. The low order bits, in the case of the Source or
Destination Registers, are used in the register selection logic associated with the Scratch Pad Register.
K3-3 IR (14:12)=0 Lis a partial decoding of the IR for bits 14 through 12 equal to 0 and is utilized on the STATUS
module for branch instruction decoding and enabling.
K3-3 SM=l L
K3-3 SM=2 L
K3-3 SM=3 L

These signals are partial decoding of the IR (bits 11
through 09) for the source mode equal to the
respective number. They are used on the STATUS
board (K5-3) for branch instruction decoding and
enabling.

K3-3 SM=O Lis a partial decoding of that portion of the IR (bits 11 through 09) for source mode equal to 0. It is
used throughout the IR module, on the STATUS board (K5-3) for branch instruction decoding, and on the KTl 1-D
option (print KT-9).
K3-3 SM=7 L is a partial decoding of the IR for source modes equal to 7 (bits 11 through 09). This is a single pin
entry and is a test point.
K3-3 IR (08 :06)=6 Lis a partial decoding of the IR, indicating that the octal code for bits 8 through 6 inclusive is 6.
It is used in the KTl 1-D option.
K3-3 IR (08:06)=0 Lis a partial decoding of the IR Register, indicating that bit.s 8 through 6 are 0. It is used in the
KEl 1-F option.
K3-3 DM=O Lis a partial decoding of the IR for a destination mode 0. It is used in the KTl 1-D option.
K3-3 CLR IR L signal is a pull-up resistor signal for the clear input of the IR.

5-45

K3-3

Print K3-4: IRD & OVLAP

This print contains additional decoding of the IR with a relatively fast and direct decoding of the single operand
instructions. In addition, the low order bits IR (02:00) are decoded. Combinational logic is provided for the overlap
signals with the signals consisting of an overlap cycle and an overlap instruction.
K34 IR (02:00)=6 Lis a partial decode of the IR Register bit 2 through 0 inclusive, equal to 6 octal. It is utilized by
the KTI 1-D option.
K34 OVLAP CYCLE L includes the next signal overlap instruction, as well as additional situations. An overlap cycle
is based on the same premise as an overlap instruction; i.e., the next bus address desired in FETCH is the
incremented PC.
In certain instructions, time can be saved by beginning the address calculation which uses the incremented PC (this is
true in index operations), and, in this case, it is done for destination modes 6 or 7 on single operand instructions of
JMP and JSR. It is also done for destination mode 6 or 7 if the source mode of a double operand instruction is O; it
is done for a source mode 6 or 7. Here the exceptions for service between instructions do not prohibit the overlap
cycle; the overlap cycles pertaining to internal instruction operations occur. The signal is used on TIMING (print
K44) to initiate another bus cycle during FETCH.
K34 OVLAP INSTR H signal for overlap instructions is active for certain instructions with certain address modes. It
is also necessary that specific service requirements and some instruction modes do not exist. Overlap is a situation
where, in the FETCH of a given instruction as the PC is being incremented, it is possible to initiate a bus cycle using
the incremented PC. This can only be done when it is known that the next bus address desired is a DATI to the
incremented PC. If this is true, the cycle can begin while the processor is still busy with the present instruction. The
situations where overlap instructions occur are usually single operands with destination mode 0, or double operands
with both source and destination modes 0. Exceptions to this are that the Destination Register cannot be REG 07,
nor can the Program Counter that is being used as the next address be in the process of change. Other exceptions to
overlap involve service requirements for bus requests, power fail, console bus requests (HALT switch), and the
TRACE bit in the STATUS word. MOVE instructions for byte operations are not overlapped. This signal is used on
STATUS (print K54) as a data input to the OVLAP flag. The flag ensures proper re-entry into the FETCH
microflow.
K34 IRl 5 H and K34 IRl 5 L are buffered signals provided for the additional drive requirements of this particular
bit of the IR.

5-47

K3-4

Print K3-S: BUBC (INSTRl)

This signal is basic microbranch code for instruction 1. The print contains combinational logic which further decodes
the initial IRD decoding, provided on the previous pages, into specific instruction signals. In addition, some of the
instruction signals from this sheet and instructions from subsequent sheets are re-encoded into basic microbranch
code (BUBC) for the first instruction branch. This instruction branch is known as INSTR! for BUT37 and appears
on sheet I of the flow diagram (D-FD-KDl 1-A-FD).
K3-5 BUBC (05 :00) (BUT3 7) H is the basic micro branch code for microaddress bits 5 through 0 and is activated on
the INSTR! branch test for BUT37. It is decoded from the IR and is available on the input to the multiplexer. The
multiplexer itself on print K3-2 provides the selection for BUT37 and this code is enabled over the base
microaddress for this test. This branching code is especially critical and basic to the machine since it is the first
instruction branch in FETCH.
K3-5 DOP * -SMO L is a double operand instruction and not source mode zero encoded together and provided for
use within the IR board.

5-49

K3-5

Print K3-6: IR DISCRETE

Combinational logic shown on this print further decodes the initial decoding of print K2-3 and provides discrete
signals for certain instructions. These instructions are the non-double operand and non-single operand instruction
which often require a flag set or a unique function performed. These signals are at the right and at the interior of the
print.
Most of the instruction signals noted are mutually exclusive and are active (H) or low (L) as noted. Some signals of
interest are noted below.
K3-6 PRIV INSTR L signal provides the KTl 1-D option with information on privileged instructions (HALT and
RESET) to make their implementation in USER mode appear as NO-OPs. Note the inhibiting of the discrete HALT
and WAIT signals by the KT02 PSI 5 (O) H signal.
K3-6 IlKO (CINSTR) Lis an internal intermediate signal for instruction 1 constant for bit 0 for C instructions. It is
used as an element of the BUBCO (BUT3 7) signal for bit 0 on print K3-5. Like other elements of the BUBC signal, it
represents a microaddress re-encoding from the decoded Instruction Register.

5-51

K3-6

Print K3-7: BUBC (OTHER)

Located on this print are various basic microbranch codes (BUBC) for tests other than INSTRl, consisting of
different numbers of address bit inputs for different BUTs. The ones shown on the extreme right are as important as
the ones shown on the left or center. Essentially, BUBC codes for BUTs 20, 21, 25, 26, 27, 31, 33, 34, 35, and 36
are shown. There are also some additional Instruction Register signals, such as SERVICE, TRACE, and BYTE
CODES. The majority of signals (BUBC codes) are used on print K3-2 as inputs to the multiplexers. A table of the
BUTs used is on the block diagram, U WORD, and table print D-BD-KDl 1-A-BD, as well as in Table 4-1.
K3-7 TRACE L signal provides for an immediate trace trap during service if PS(T) is set and the IR does not contain
an RTT instruction. The signal is used on this print in the BUBCl (BUT26) signal and on STATUS prints K54, 5 for
flag control and trap vector generation.
K3-7 SERVICE H is a definition of the reasons to enter the service section of the microflows after instruction
execution. It contains flags and inputs for internal (bus error, basic overflow on the stack, power down, and trace)
and external (BUS Request Priority flag, console bus request, and reference to processor status address) situations
requiring service. The signal is used on this print in the BUBC 1 (BUT20) signal for microbranching and is provided as
a test point.
K3-7 BYTE CODES H signal indicates to the condition codes logic (print K5-2) that a byte instruction is in the IR.
The signal is used on STATUS (print K5-2) for selection of input data to the condition codes of the Processor Status
Register.
K3-7 BUBC (5,03:00) (BUT36) H is the basic microbranch code for microaddress bits 5, 3, and 0 for the BUT36.
BUT36 is the INSTR3 branch associated with the next flow sequences after SOURCE calculations.
K3-7 BUBC (5,03:00) (BUT35) H is the basic microbranch code for microaddress bit 5 and bits 3 through 0 for
BUT35. BUT35 is the odd byte and INSTR3 branch associated with byte formatting of incoming data or the next
flow sequences after SOURCE calculations.
K3-7 BUBC (03:00) (BUT34) His the basic microbranch code for microaddress bits 3 through 0 for BUT34. BUT34
is the INSTR4 branch associated with the next flow sequences after destination calculations.
K3-7 BUBC (03:00) (BUT33) His the basic microbranch code for microaddress bits 3 through 0 for BUT33. BUT33
is the odd byte and INSTR4 branch associated with byte formatting of incoming data or the next flow sequences
after destination calculations.
K3-7 ODD BYTE L is the combination of a BYTE instruction decode from the IR and a 1 in bit 00 of the Bus
Address Register. This signal is used within the IR DECODE module in the microbranching logic of BUBC (BUT33).
K3-7 BUBC (01 :00) (BUT20) H is the basic microbranch code for microaddress bits 1 and 0 for BUT20. BUT20 is
the Byte, Service, or Fetch branch associated with the end of instruction execution.
K3-7 BUBCO (BUT31) His the basic microbranch code for microaddress bit 0 for BUT31. BUT31 is the No Write or
Byte Write or Word Write associated with instructions of destination mode zero requiring register rewrite.
K3-7 BUBCO (BUT27) His the basic microbranch code for microaddress bit 0 for BUT27. BUT27 is the Service B or
Fetch Overlap or Fetch B branch associated with the end of instruction execution where an overlap situation might
exist.

5-53

K3-7

K3-7 BUBC (01 :00) (BUT26) His the basic microbranch code for microaddress bits 1 and 0 for BUT26. BUT26 is
the Request branch associated with the entry into the SERVICE flow and provides for the proper sequencing and
servicing of requests.
K3-7 BUBC (01 :00) (BUT25) His the basic microbranch code for microaddress bits 1 and 0 for BUT25. BUT25 is
the Bus Request or Wait or Fetch branch associated with the servicing of these requests in the WAIT loop of
SERVICE.
K3-7 BUBC (01 :00) (BUT21) His the basic microbranch code for microaddress bits 1 and 0 for BUT21. BUT21 is
the IR03 and Byte or Source branch associated with index address operations in the MOV address calculations.

K3-7

5-54

Print K3-8: ALU CONTROL

This print shows two sets of combinational logic. One set is ordered toward the ALU control signals and provides for
a multiplexer selection of either the U WORD directly, or control as a function of IR decode. Multiplexer selection
is a function of the DAD code. The other set of logic is the carry-in for the ALU and control of the Carry-Out
Multiplexer. See Table 3-2 for ALU functions.
K3-8 COMUXS (01 :00) H provide the inputs of the COUT Multiplexer Selection (print Kl-5) which forms the data
input of the D(C) flip-flop. Selection is solely a function of the IR decode and inputs from the KEl 1-E option; no
direct control from the U WORD exists.
K3-8 CINOO L provides the carry-in for bit 00 of the ALU (print Kl-2). Control of this data input is a function of
the IR decode and indirect control from the U WORD through the Discrete Alteration of Data (DAD) and Select
Arithmetic Logic Unit (SALU).
K3-8 BIT+CMP+TST H is a simple combination of the bit test, compare, and test instruction from the IR decode. It
is used with the IR DECODE module and TIMING (print K44) to alter DATIP bus cycles to DATI bus cycles for
destination data references.
K3-8 ALUS (03:00) H are the direct control for the ALU selection signals on prints Kl-2, 3, 4, and 5. The
multiplexer selects either direct U WORD control by the SALU signals, or Instruction Register control by either the
basic processor or KEl 1-E option. Multiplexer selection is controlled by the Discrete Alteration of Data (DAD)
signals of the U WORD.
K3-8 ALUM H is the direct control of the ALU mode on prints Kl-2, 3, 4, and 5. Combinational logic allows U
WORD control by the DAD microfield or IR decode.
K3-8 DAD (3*2) L is a decoding of discrete bits in the DAD microfield. It is used in the KE! 1-E and KEl 1-F
options.

5-55

K3-8

Print K3-9: CODES C,V

This print shows combinational logic associated with the input data required for the C and V bits of the condition
codes. Conditioning of these data inputs is a function of the IR decode and the present processor status.
K3-9 V DAT A L is the V DAT A input of the overflow bit of the condition code portion of the processor status
word. This input reflects direct loading inputs (D MUXOl) as well as instruction data inputs: V(ROTSHF),
V(COMPAREl), and V(COMPARE2). The signal is used on print KS-2 of STATUS.
K3-9 C DAT A H is the C DAT A input of the C or carry bit of the condition code portion of the processor status
word. This input reflects direct loading inputs (D MUXOO), as well as instruction data inputs. The signal is used on
print KS-2 of STATUS.

5-57

K3-9

5.6 M7234, TIMING, K4 MODULE
Timing for the K.Dl 1-A Processor consists of the basic processor clock for data path and microcontrol, and the
Unibus-ordered control for data and bus ownership transfers. Microcontrol techniques are used in each section, but
discrete flip-flop, combinational logic, discrete timing (delay or pulse) circuits are necessary. These circuits and logics
are discussed in context with the overall timing and not ordered upon output signals.

5-59

Print K4-2:

CLOCK

This print contains the basic processor clock which consists of the CLK flip-flop, pulse-width forming delay line
logic, and cycle-length forming delay line logic. Necessary peripheral logic provides on/off control (IDLE flip-flop),
asynchronous restart inputs, and output enabling gates.
Assuming sequential, uninterrupted operation, the end of one clock cycle is the beginning of the next clock cycle.
The trailing edge of the K4-2 RECLK H signal clocks a 1 to the CLK flip-flop (assuming continuous operation)
which activates the pulse forming logic loop with Delay Line 1 (DLl). After the delay, the DLl loop clears the CLK
flip-flop. The CLK flip-flop, therefore, forms a pulse of approximately 40 ns (DLl time plus gate time). This pulse is
now passed through additional delay lines to form the various cycle lengths (CLl, CL2 and CL3).
A CLl is formed by passing the CLK pulse through Delay Line 2 (adjustable per CLOCK ADJUSTMENT note) to
74HOO gates at E63 (output pins 08 and 11). If a CLl was specified by the U WORD CLK field, the signal K2-8
CLKLl (0) H enables the CLK pulse through the upper 74HOO gate (E63, output pin 08) where, after inversion
(74HOO gate at E66, output pin 06), it becomes K4-2 Pl H.
A CL2 is formed by the CLK pulse if, after passing through Delay Line 2, the bottom 74HOO gate (E63, output pin
11) is enabled by K2-8 CLKLl (1) H signal. The upper 74HOO gate (E63, output pin 08) is disabled. The CLK pulse
now passes through Delay Line 3 to the 74HOO gates at E72 (output pins 08 and 11). Here a P2 pulse is generated
with the upper 74HOO gate (output pin 08) allowing the pulse as an End of Cycle signal to the microcontrol and
clock.
If a CL3 is to be formed, the bottom 74HOO gate (E72, output pin 11) enables the P2 pulse to the data path and to
the next delay line (DL4). The upper 74HOO gate (E72, output pin 08) is not enabled to allow the P2 pulse as an
End of Cycle signal. That signal is provided by the P3 pulse from the 74HOO gate at E72 (output pin 03).

Reference to the CLK WAVEFORMS table allows correlation between the clock output pulses, their relative timing,
and the U WORD enabling signals.
The output enabling gates service the three sections of the KDl 1-A Processor: the INTERFACE, the DATA
PATHS, and the MICROCONTROL. The microcontrol clocking signals (CLK U signals, RECLK PEND, and PART P
END) are ordered toward end-of-cycle pulses. For a CLl, this is a Pl pulse; for a CL2, a P2 pulse; and for a CL3, a
P3 pulse. Clocking to the U WORD and the clock logic is not conditioned by any enabling signal and is usually on
the final pulse transition. The End of Cycle signals are also used in the flag control logic of STATUS, especially P
END and PART PEND. Here the signals may be used as set or clear pulses with enabling BUT signals.
The output enabling gates for data path and interface control use a variety of the Pl, P2, and P3 pulses. The pulses
are enabled singularly or in combination by specific U WORD control bits to provide the several CLK signals noted.
The pulse signals are also provided directly for generation of other CLK signals in the basic (STATUS) and expansion
(KEl 1-E, KEll-F, KTl 1-D) processor. Note that any end (enabled) CLK signal must have only one gate (H series)
between the pulse signals (Pl, P2, P3) and the end CLK signal; this prevents excessive clock skew.

5-61

K4-2

Continuance of clock cycles, one after another,is determined by the End of Cycle signal, K4-2 RECLK H, and the
data input signal to the IDLE flip-flop. If a new clock cycle (microword, machine state) is to begin, the IDLE
flip-flop data input is inactive (a high logic level); the CLK flip-flop data input is therefore the inverse (74HOO gate at
E73, output pin 03), and the CLK flip-flop is clocked to the 1 state. This begins the pulse forming and delay
sequences already noted. If a next clock cycle is not to begin, the IDLE flip-flop data input is active (a low logic
level) and the flip-flop is clocked to the 1 state; the CLK flip-flop is not clocked to the 1 state and no pulse forming
occurs. Conditions to halt the clock are noted on the inputs to the 74H53 gate at E77; the most common input
would be the U WORD control signal K2-8 CLKOFF (1) H. Note that the U WORD is clocked by the last pulse
transition of the halting clock cycle, the machine halts in the beginning of the next microword and awaits timing
signals.
The restarting of the clock is effected by the combination logic on the set input of the CLK flip-flop. This input has
interlocking signals from the CLK pulse forming logic and IDLE flip-flop to ensure that the clock restarts without
partial pulses and that the clock is completely off before restart. The actual restart inputs provide for a fast direct
restart for data transfer situations (K4-6 B SSYN H input) and a combination of lower priority (time wise) restarts.
Common to each of these restart inputs are the enabling conditions for the restart condition and the restart signal.
An additional control flip-flop, MCLK, is provided for single clock manual operation. This flip-flop functions in
parallel with the CLK flip-flop and generates the beginning transition to the pulse forming logic. It does this as a
function of maintenance console switch activation (KM-2 MCLK L). The IDLE flip-flop is not directly affected by
this manual operation mode. The CLK flip-flop is affectively disabled with neither its data or set inputs enabled.
Details of maintenance console interaction are contained in Paragraph 7.3 of this manual.

K4-2

5-62

Print K4-3: CLK JAM

Discontinuities exist in the microprogram flow. The majority of these interruptions are accommodated by halting
and restarting the CLK logic (noted for print K4-2); the next microword after the halting signal [usually K2-8
CLKOFF (1) H] is entered and the machine awaits a restart signal. An interruption (or pause) has occurred in the
microprogram flow, but sequential flow still occurs after restart.
The CLK JAM logic is ordered toward non-sequetttial interruptions of the microprogram flow. Error conditions or
power-up sequences enable this timing such that the usual microcontrol timing is disabled (K4-3 JAMUPP H signal
on IDLE flip-flop input) and special clocking signals are provided to force the microprogram flow to specific
microaddresses. The microprogram flow is irrevocably JAMmed to a specific operating flow. The JAMUPP
ADDRESSES table on this print correlates the reasons (USE) for the microprogram jam and the new microaddresses
(UPP).
The CLK JAM logic has three parts: error sensing and power-up flag flip-flops, asynchronous serial timing logic, and
combination logic for the new microprogram address generation.
The flag flip-flops which are clocked to the 1 state for activation are the JBERR flag for odd address bus errors and
red zone stack overflow, and the JPUP flag for START switch activation in the HALT mode and Power Restart. The
PERJ RS type flip-flop is set when a memory parity error is detected. These three flags, with additional inputs from
the NODAT flag (print K4-6) for non-existent bus address error and PWRUP INIT (print KS-8), activate the timing
logic.
The JAMUPP one-shot, when activated, provides an enabling signal to the combination logic generating the new
microaddress. This logic encodes the various error and power up flags to provide direct set and clear signals to the
Microprogram Pointer (UPP) Register. Usual machine timing is disabled (IDLE data input of print K4-2); less
important machine flags (TRAP and INTR of print K54) are cleared; and the BERR flag and STALL flag are
clocked (print K54). Deactivation of the JAMUPP .one-shot removes the set and clear signals to the UPP Register,
and after a delay (8 = 100 ns), provides the K4-3 JAM CLK H signal. This signal clocks the newly selected
microword (see JAMUPP ADDRESSES table) into the U WORD Buffer and activates the JAM START one-shot. The
pulse output of the JAM START one-shot clears the NODAT flag (print K4-6) if appropriate, and restarts the CLK
logic.
The PERR flip-flop stores the fact that a memory parity error has occurred and is used to generate the parity trap
vector.

5-63

K4-3

Print K4-4: BUS DATA CNTL

The logic shown on this print is associated with processor Unibus data transfers and the variety of required error
checking and cycle alterations. Some decoding of the Unibus BUS C signals is provided for processor and processor
option use. The logic consists of control flip-flops (BUS, CKOVF, CKODA, BWAIT, BCl, arid BCO) which are
activated by U WORD and IR decode input. Delays for skew correction are provided between the bus activating
control flip-flop (BUS) and the actual MSYN flip-flops. Appropriate checking logic combines error conditions with
error check enabling signals. Bus cycles are aborted or allowed with error conditions affecting the flag flip-flops of
STATUS (print K54). Tables are provided for the BUS and DAD fields of the microword.
BUS, MSYN, MSYNA Flip-Flop - The BUS flip-flop initiates all processor Unibus cycles. It is clocked to the 1 state
by K4-2 CLK BUS H signal (derived from BGBUS of the U WORD), except for the DAD code (IXlX) in the
execution flow of the BIT or CMP or TST instruction, and the non-existence of an overlap cycle in the FETCH flow
(BUT37 at FET04 microword). The activation of the flip-flop is gated by bus ownership signals in the 74H20 gate
. (E9, output pin 06). For a bus cycle to occur, the processor must be in charge of the bus [K4-5 BBSY (1) H], no
Unibus cycles are in process (K4-6 B SSYN L), and the processor is not giving up bus ownership (K4-5 PROC
RELEASE L). With these conditions met, the delays associated with Unibus data skew and address decode are
activated. Two delays exist: one for normal Unibus delay to the MSYN flip-flop, and a shorter delay to the MSYNA
flip·flop.
During the deskewing delay, error conditions disable the data inputs of the MSYN and MSYNA flip-flops. Normally,
however the flip-flops are clocked to the 1 state and drive the Unibus through appropriate gates. Disabling exists for
the KTl 1-D option. The MSYN, MSYNA and BUS flip-flops are pulsed clear from the BWAIT flip-flop.
CKOVF Flip-Flop - The CKOVF flip-flop controls the check of overflow on the processor Stack Pointer. Only
certain address modes in certain bus operations need to be checked. This is controlled by the DAD code (Xl lX) of
the U WORD with register selection information; a disabling flag [K54 STALL (1) L] from STATUS can inhibit the
check. The CKOVF flip-flop is clocked by the K4-2 CLK BA H signal with activation of the flip-flop further
conditioned by the KTl 1-D option and the Unibus cycle type. The check enabling signal enables the error detection
signals and provides for possible abortion of the Unibus cycle (inhibits data input to MSYN flip-flop) with
corresponding raising of error flags. This occurs here only for red zone stack overflow; the yellow zone stack
overflow is handled solely by the error flags.
CKODA Flip-Flop - The CKODA flip-flop controls the check of odd address errors on processor data bus cycles.
The flip-flop is always clocked to the 1 state by the K4-2 CLK BA H signal unless a byte instruction exists with a
DAD code (XXXl) from the U.WORD. Checking, however, is further conditioned by console operation and the
KTl 1-D option. The check enabling signal enables the error detection signals [Kl-7 BADO (1) Hor KT-3 FAULT H]
and provides for possible abortion of the Unibus cycle (inhibits data input to MSYN flip-flops) with corresponding
raising of error flags.
BWAIT Flip-Flop - The BWAIT flip-flop provides the clearing signal (K44 P CLR MSYN L) for the processor BUS,
MSYN, and MSYNA flip.flops. The flip-flop is set by activation of the IDLE flip-flop (print K4-2); this is usual for
processor data bus cycles. The BWAIT flip-flop remains set during BWAIT for the usual peripheral response (K4-6 B
SSYN L), which restarts the CLK. Usual deactivation of BUS, MSYN, and MSYNA flip-flops occurs at the end of the
first microword [K4-2 (Pl + P3) H] when the BWAIT flip-flop is clocked to the 0 state. Other clearing signals are
combined in the pulse logic to accommodate situations where no peripheral response is made (NO DAT error,
microcontrol JAMUPP for other bus errors) and processor initializing.

5-65

K4-4

BCl and BCO Flip-Flops'-- The Unibus control signals are held in the BCI and BCO flip-flops. The flip-flops are
loaded from ClBUS and COBUS bits of the U WORD by the K4-2 CLK BUSH signal (derived from BBUS of the U
WORD). Modification of the data input for BCO is made for byte instructions (to change DATO operation to
DATOB) and for BIT or CMP or TST instructions (to change DATIP operation to DATI). Appropriate gates drive
the Unibus with additional logic providing conditioning inputs to processor and processor options (KJ 11-A
especially) which respond through the processor to absolute bus addresses.

K4-4

5-66

Print K4-5: BUS OWNERSHIP

Shown on this print are the discrete flip-flops and combinational logic associated with the granting and acceptance
of Unibus ownership by the KDl 1-A Processor. Processor ownership exists with the BBSY flag in the 1 state, and is
necessary on power-up, console operation, processor data bus cycles, RESET instruction, power fail, and prior to
release of bus ownership for bus requests. The processor usually controls the bus unless it has specifically given up
control.
The granting of bus ownership requires that peripheral requests for ownership are acquired by the processor in the
appropriate flag flip-flops: the NPR flag for a non-processor request; the BRPTR flag for bus requests with a
priority request greater than processor status priority; and the CBR flag for the KYl 1-D Console HALT switch.
Clocking signals combining various inputs are necessary with proper sequencing of Unibus bus ownership signals
[BUS SACK L, BUS NPG H, and the BUS BG (07:04) H] on the Unibus (PDP-11 Peripherals and Interfacing
Handbook).
The major clocks for priority determination and acquisitions of requests are K4-5 CLK NPR H and K4-5 CLK PTRD
H. Both clocks contain clocking signals with a BUS MSYN clock necessary for situations when the processor is
inactive; no separate continuous clocking exists in the processor for the priority determination logic.
The K4-5 CLK NPR H signal, in addition to the BUS MSYN clock, has clock inputs for clock restart (K4-2 SET CLK
L), data bus cycle beginnings [K2-7 BG BUS (1) H], BUT26 in service flow, the activation of MSYN (K4-5 P MSYN
H pulse), and CLK IR for overlap situations. Independent of clocking, the data input to the NPR flag is inhibited for
power fail (KS-8 B AC LO L), during console operations, and across DATIP/DATO operations. A DATIP flag
flip-flop prevents the granting of bus control for non-processor requests across DATIP/DATO cycles as the DATIP
address location is still selected by the processor with the probability of a partial read/restore cycle m the penpheraJ.
BG BUS (1) H produces a pulse which strobes the NPR line each time the processor is ready to initiate a bus data
cycle. If any NPR is present, it will be serviced prior to the execution of the processor data cycle.
B MSYN L and SET CLK L clock the NPR flag during and upon restart following a processor bus data cycle. NPRs
clocked in by either of these signals will be serviced immediately following the bus cycle.
BUT26 in the SERVICE flow provides clocking of the NPR flag while the WAIT instruction is being executed.
ENPRCLK provides an external clock from the KEl 1-E option. Both of these signals clear the BBSY flag directly so
that all NPRs are serviced immediately.
The BBSY flag is clocked each time the processor initiates (K4-2 CLK BUSH) and terminates (K4-4 P CLR MSYN
L) a bus data cycle. It is cleared, relinquishing bus control, whenever an NPR is clocked into the NPR flag.
Clocking for the K4-5 CLK PTRD H occurs for BUS MSYN clock and for BUT26 in the SERVICE flow and CLK IR
for overlap situations. Associated with this clock is the PTRD one-shot that delays the actual clocking of the BRPTR
flag flip-flop until the comparison of peripheral bus request priority levels can be made against processor status
priority levels (print K4-6). The result of that comparison is signal K4-6 BRQ H on the data input of the BRPTR
flag. The BRPTR flag is used to store the fact that a bus request of higher priority than the present processor
priority has been received. It is used as a source of information for branching to SERVICE at the end of an
instruction and also for branching to the interrupt service microflow.
Console control of the processor via the HALT switch is gained in a manner similar to the servicing of a bus request.
The PTRD one-shot clocks the CBR flag which stores the condition of the HALT switch. If the HALT switch is
activated, the processor will branch to SERVICE at the end of the current instruction, at which time BUT26 will
cause the machine to enter the CONSOLE microflow.

5-67

K4-5

Print K4-6:

BUS RESPONSE

Three types of bus response are provided by the logic shown on this print: the Bus Grant signals in response to Bus
Requests; the SSYN and Bus Address selection of processor registers in response to processor or console bus cycles;
and the processor timeout flags for NO SACK and NOD AT.
The Bus Grant signals [BUS BG (07:04) HJ are generated by comparison logic for the incoming Bus Request signals
and the existing Processor Status signals. The results of the comparison are used in the bus ownership logic shown on
print K4-5 to determine if the BRPTR flag should be enabled. With the flag enabled, processor service of the flag
results in the K4-5 GRANT BR H signal activating one of the BUS BG (07:04) H signals on the Unibus.
Processor register response to absolute bus addresses is not completely specified by microprogram control. Bus
address decoding (print Kl -7) and Unibus control decoding (print K44) are combined to read or write these
registers. Timing signals are provided for Unibus response (BUS SSYN L) and clocking of the registers [K4-6 PS (P
FM BUS) HJ. Note that a read from a processor register usually results in data gated onto the Unibus; a Write to a
processor register results in the data being available on the D MUX signals. The Scratch Pad Register (REG) does not
respond with SSYN to processor and console Bus Address references; rather, it responds to console references
directly, and then under microprogram control.
The processor register addresses that respond with SSYN are PS ADRS (Processor Status Register), SR ADRS
(Switch Register), and if the KJI 1-A option is present, the SLR ADRS (Stack Limit Register). Normally, the Load
Address function addresses the Switch Register for the address data, however, in the case of a BEG IN operation, the
Switch Register data gating enable (K4-6 BUS FM SR H) is inhibited. BEGIN is a remote Load Address/Start
function, and the address data must be provided by the remote device. A further discussion of the BEGIN function
is contained in the logic description of the KS print.
The timeout flags for no SACK and no data provide a processor response when peripherals fail to respond. The
NOSACK flag is set when peripherals granted bus ownership fail to respond; the NODAT flag is set when data bus
operation receives no SSYN response. In each case, the timeout duration is 15 µs. The service of the timeout flags
differs. The NODAT flag results in microprogram interruption (JAMUPP) and a trap sequence. The NOSACK flag
merely allows the processor to regain bus ownership and continue operation. Each timeout may be disabled for
maintenance operation. See the note on the print or details of maintenance module operation in Paragraph 7.3 of
this manual.

5-69

K4-6

(

5.7 M7235, STATUS, KS MODULE
The STATUS module contains miscellaneous combinational logic relating to processor status. This includes:
a.

Processor status word with priority bits for comparison to bus request, a TRACE bit, and condition
codes N, Z, V, and C.

Branch instruction implementation with comparison of the condition codes with IR decoding.

Branch Microprogram Test (BUT) decoding with discrete outputs as a function of specific microwords.

Flag flip-flops for a variety of machine and error states that require unique servicing.

B constants decoding with Special Trap Pointer Marker (STPM) signals for trap vectors.

Console flags for START, BEGIN, and proper incrementation on double EXAMs and DEPs.

Console interface for the ADDRESS display and control inputs.

Power fail and bus delay one-shots for proper sequence of some Unibus signals (BUS AC LO L, BUS DC
LO L, BUS INIT L), as well as processor start-up.

5-71

Print KS-2: PS (07:00)

The processor status word consists of PS (07:00), with PS (07:05) associated with the priority of machine operation.
It is this portion of processor status that is compared against the bus request signals to determine whether a bus

request should be granted. These processor status bits are represented by discrete flip-flops and are loaded from the
D MUX signals upon a specific LOAD processor status clock. Other bits of the processor status are the PS(T) bit and
the condition codes. PS(T) is the TRACE bit and its function is described in detail in the appropriate Processor
Handbook. Loading of the TRACE bit does not occur as a function of a processor reference to an absolute bus
address. The TRACE bit is implicitly altered only in RTI and RTT instructions and in trap sequences.
The condition codes portion of the processor status word consists of bits PS(N), PS(Z), PS(V), and PS(C). These bits
are loaded from the D MUX upon a specific LOAD processor status clock from the processor, in addition to
conditional inputs as a function of instruction operations and data results from those operations. The conditional
inputs for PS(C) and PS(V) are already generated upon the IR DECODE module (print K3-9). The inputs for PS(Z)
and PS(N) are generated by the combinational logic on this module. The major conditions of all these inputs are
indicated in the Processor Handbook for each instruction.
Other logic on the K5-2 print is the PASTA and PASTC flip-flops necessary for holding PAST A input (to the ALU)
and PASTC [PS(C)] information for condition code operations. A multiplexer is used for the selection of input
data, usually high byte or low byte for the PASTA flip-flop and other condition code logic [PS(N) and PASTB].
Combinational logic is utilized in the generation of the processor status clocking signal with direct interaction
occurring between the clock pulses [K4-2 PS(Pl+P3) H], U WORD control [K2-6 SPS (02:00) (1) H], address
decoding (Kl-7 PS ADRS H), and instruction decoding (K3-6 CC INSTR H).
KS-2 PS (07:05) ( 1) Hare the priority bits of the Processor Status Register and are compared against the bus request
signals on the TIMING module (print K4-6). These flip-flops are loaded from the D MUX (07:05) lines when the
processor status word is referenced by the processor or console with its absolute bus address.
BUS RD (07:00) Lare the signals connecting the Processor Status Register to the internal Processor Register Data
Bus. These signals allow the routing of the processor status word through the machine in trap sequences and
condition code instructions.
BUS D (07:00) L are the Unibus signals that allow the Processor Status to respond to processor or console requests
to its absolute bus address.
K5-2 PS(T) (1) H is the TRACE bit of the processor status word and is used on the IR DECODE module (print
K3-7) to generate a branch to SERVICE (no RTT instruction present). Signals K3-7 TRACE Land K3-7 SERVICE
L reflect this input with the appropriate flag flip-flop on the STATUS module (print K54) being set. The PS(T) bit
is not loaded with the rest of the processor status word, it is implicitly altered only on RTI and RTT instructions
and during trap sequences.
K5-2 PS(N) (1) H is the negative bit of the condition codes portion of the processor status word. It is loaded as a
function of absolute bus address reference to the processor status or under microprogram control in instruction or
trap operations. Input data for condition code operation comes from combinations of logic which select upper or
lower byte information. The signal is used in combinational logic generating the ALU control signal K3-8 ALUM H
on the DATA PATHS module and in the branch instruction logic (print K5-3).
K5-2 PS(Z) (1) H is the zero bit of the condition codes portion of the processor status word. It is loaded as a
function of absolute bus address reference to the processor status, or under microprogram control in instruction or
trap operations. Input data for condition code operation consists simply of combinational logic to sense word or
byte zeroing of the D Register. The signal is used in the branch instruction logic (print K5-3).

5-73

KS-2

KS-2 PS(V) (1) His the overflow bit of the condition codes portion of the processor status word. It is loaded as a
function of absolute bus address reference to processor status, or under microprogram control in instruction or trap
operation. Input data for condition code operation is provided by K3-9 V DATA L from the IR DECODE module.
The PS(V) signal is used in the branch instruction logic (print KS-3).
KS-2 PS(C) (1) H is the carry bit of the condition codes portion of the processor status word. It is loaded as a
function of absolute bus address reference to processor status, or under microprogram control in instruction or trap
operations. Input data for condition code operation is provided by K3-9 C DATA H from the IR DECODE module.
The PS(C) signal is used in the branch instruction logic (print KS-3), on the input multiplexer for D(C) Register
(print Kl-5), and in combinational logic for generation of signals K3-8 CINOO L, K3-9 V DATA L, and K3-9 C
DATAH.
KS-2 BUSRD FM PS H gates the processor status word to the Bus Register data lines for condition code instructions
and for microcontrol Select Processor Status (SPS) codes of 6 for trap sequences and console display.
KS-2 N DATA L is the input data to PS(N) and provides byte-selected data [DIS (1) H or D07 (1) H] to the
combinational logic generating K3-9 V DAT A Lon the IR DECODE module (print K3-9).
KS-2 LOAD PS L is the enabling signal for the combinational logic on the data inputs of the condition codes to
allow the D MUX data signals instead of condition code inputs. The signal is used on this print and on the IR
DECODE module (print K3-9).
KS-2 PASTA (1) His a holding flip-flop for the most significant bit (word or byte) for the AIN input of the ALU.
This signal is necessary in the calculation of overflow data (K3-9 V DATA L); storage of the input is required
because the condition code calculation occurs after the AIN input is removed.
KS-2 PASTB His a simple gating of the most significant bit (word or byte) for the BIN input of the ALU. The signal
is necessary to the calculation of overflow data (K3-9 V DATA L).
KS-2 PASTC (1) L is a holding flip-flop for the past value of the PS(C) flip-flop. The signal is used in the
combinational logic generating signal K3-9 V DATA L for SBC and DEC instructions, and in signal K3-9 C DATA H.
KS-2 SPS (02:00)=7 H is a decoding of the Select Processor Status (SPS) code and is used with the KTl 1-D option.

KS-2

5-74

Print KS-3: BUT & BRANCH

Two distinct sets of combinational logic are shown on this print: branch instruction logic for comparison of
instruction decoding with condition codes; and BUT decoding of the microprogram field.
K5-3 TRUE BR L indicates that TRUE conditions specified by the Instruction Register for a branch instruction have
been met by the condition codes. The signal, when active, provides BUBC signals (print K3-5) to alter flows and
implement the instruction.
K5-3 FALSE BR L indicates that FALSE conditions specified by the Instruction Register for a branch instruction
have been met by the condition codes. The signal, when active, provides BUBC signals to alter flows and implement
the instruction.
K5-3 BR INSTR L is the decode of the Instruction Register for a branch instruction. It is used in the BUBC signals
(K34 print) for the INSTR! microbranch.
BUT signals noted for this print are decoded from the microbranch field (UBF) of the U WORD. These decoded
signals are used throughout the processor as auxiliary timing signals unique to the microword in which a specific
BUT is called. A table on the print correlates the numeric code of a BUT with its mnemonic function; BUTs that are
decoded and used for auxilliary purposes (besides branching the microflow) are called "working BUTs." Flow
diagram notations (D-FD-KDl 1-A-FD) indicate when and what functions these BUTs perform. A usual function is to
clear and set machine flag flip-flops such as those on STATUS module prints K54, K5-6, and K5-8. In these
instances, the BUT signal acts as an enabling signal to a timing pulse.

5-75

KS-3

Print KS-4: FLAGS

Flag flip-flops for error conditions and machine sequencing are shown on this print. The logic discussion will deal
with the interaction and function of each flag flip-flop instead of discussing output signals.
Provided below, from top to bottom, is the sequence of service to the internal processor traps, external interrupts,
and HALT and WAIT. This order of sequence is affected by the interaction of the flag flip-flops and is basic to
understanding their operation.
BUS ERROR Traps - Odd Address Fatal Stack Overflow (Red) Memory Management Violations to 250 (if
KTl 1-D) and Memory Parity Errors.
HALT Instruction - Console Operation (and certain changes if KTI 1-D).
TRAP Instructions - Illegal or Reserved Instructions, BPT, IOT, EMT, TRAP.
TRACE Trap - T Bit of Processor Status.
OVFL Trap - Warning (Yellow) Stack Overflow.
PWR FAIL Trap - Power Down.
BERR Flag - The Bus Error flip-flop provides a flag for trap service upon the occurrence of a NODAT or odd
address error in a processor Unibus data transfer. The flip-flop is clocked to the 1 state by the activation of the data
inputs from the NODAT flip-flop (on TIMING) or the Odd Address Error signal with the clocking signal K4-3
JAMUPP H (which also jams the microflow to a trap routine). The BERR flag output generates appropriate STPM
constants from trap vectors and accommodates the ordered sequence of service for the various processor flags. This
sequence is noted in the Processor Handbook and is repeated in the introduction to this print.
Certain clearing signals are common to the BERR, TRAP, and INTR flag flip-flops. They are: the processor
Initialize (INIT) signal; the External Pulse Clear Trap signal from the KEl 1-E option; BUT03 in TRP16 microword
'at microaddress 140 in the trap sequence; and the establishment of a new stack at location 024 for a power-down
situation. Common clearing signals work for BERR, TRAP, and INTR flag flip-flops because their service is mutually
exclusive. A BERR flag aborts the other two, TRAP service is due to instruction operation, and INTR service occurs
only after instruction operations.
In addition to the common clearing signals, the BERR flag is cleared and held clear for KYl 1-D Console operation.
This allows the bus error of NODAT and Odd Address Error to occur without a trap sequence that would alter
Processor Status, the Program Counter, or the Stack Pointer. No trap response to the bus error in console operation
is considered the safe response. The JAMUPP signal does occur but the microflow is jammed to the console switch
loop microflow.
Normal sequential servicing of the BERR flag results in the BUT03 clearing the flag. The BERR is first priority and
prohibits the clearing of lower order priority flag flip-flops during its trap service.
TRAP Flag - The TRAP flip-flop provides a flag for trap service in proper sequence for trap instructions (BPT, IOT,
EMT, and TRAP). The flip-flop is clocked to the 1 state by the data input of an IR decode of a trap instruction with
the clocking signal K5-6 P BUT37 H, which occurs in the FETCH cycle. The micrologic branches to the trap
sequence for service with appropriate STPM constants generated by the TRAP flag and the IR decoding.

5-77

KS-4

In addition to the common clearing signals noted under the BERR flag, the JAMUPP signal directly clears the TRAP
flag. TRAP flag service is aborted if a JAMUPP signal occurs. Normal sequential servicing of the TRAP flag results in
the BUT03 clearing the flag with lower priority flag flip-flops unaltered.
INTR Flag - The Interrupt (INTR) flip-flop is clocked to the 1 state by the data and clock input of the K44 B
INTR H signal (decoded from the Unibus) with the clocking signal requiring the non-existence of the INTR flag, and
the K4-2 SET CLK L signal for machine restart. (If the KMl 1-A Maintenance Module is present, single clock mode
inhibits the K4-2 SET CLK L signal and the P3 signal is used to clock. Note that the INTR bus cycle waits for the
next signal clock before completion.) After the INTR flag is set, the micrologic branches to the trap sequence with
the trap vector provided by the interrupting peripheral. Exactly the same clearing signals used for the TRAP flag are
used for the INTR flag.
The INTR flag is used both within this module for the sequential clearing of flags and on print KS-6 for Slave Sync
(SSYN) response for the INTR bus cycle. Normal sequential clearing of this flag is done by BUT03 in the trap
service.
AWBY Flag - The Await Bus Busy signal is utilized by the processor in its instruction flow and defines no trap
service condition. It is set for specific U WORD BUS codes (Cl BUS=O, COBUS=l, BGBUS=O) with Pl or P3 timing
pulses. These codes are generated in the SERVICE flow where the processor must have absolute control of the bus
prior to granting the bus requests.
The A WBY flag is cleared by a Pl or P3 pulse and the absence of the U WORD bus codes previously used to set
AWBY. This occurs directly after the machine restarts. Clearing also occurs for the processor INIT signal and the
operation of a new stack at location 04 at power down. This last set of clearing signals is named K54 FLAG CLR H
and is common to other flags.
The output of the AWBY flip-flop is utilized directly on TIMING (print K4-2) to enable machine restart on
processor BBSY (1) H. It is also used on print K4-5 to disable the SET CLK signal from clocking the NPR flag.
BOVFLW Flag - The Basic Overflow flag senses stack overflow error for red zone violations (K4-4 OVFLW ERR L)
and for yellow zone violations (Kl-7 BOVFL, or KJ-2 EOVFL if the KJll-A option is installed). The BOVFLW
flip-flop is clocked to the 1 state by the K44 CLK OVFLW H signal if either error is present. Once the flag is set, a
feedback signal to the data input allows further clocking without zeroing the flag. The output of the BOVFLW flag
generates the STPM constants for the trap vector and provides for proper trap sequencing.
A red zone stack error results in a JAMUPP signal so that the BERR, TRAP, and INTR flags are zeroed. The jam
entry into the trap sequence provides for the clearing of the BOVFLW flag by BUTOl in the TRP20 microword at
address 332. (Note that the T bit of new Processor Status should not be set so that the K3-7 TRACE L signal is not
active.)
A yellow zone stack error results in a normal microprogram flow with the BOVFLW flag being serviced in sequence;
appropriate BUBC bits for a micro branch to SERVICE are enabled on IR DECODE (print K3-3). The BOVFLW flag
is still cleared in sequence by BUTOl in TRP20 microword but only if the higher priority flags (BERR, TRAP, or
INTR) have been serviced. If they are not serviced, the microprogram flow recycles through the trap sequence until
service is complete.
PWRDN Flag - The Power Down flip-flop is clocked by the power fail synchronizing signal KS-8 CLK PWR DN H.
The flag output alters microprogram flow by enabling appropriate BUBC bits for a microbranch to SERVICE on IR
DECODE (print K3-3); STPM constants for the trap vector are also generated. Normal sequential service results in
the flag being cleared by BUT04 of the TRP21 microword at address 333. The higher priority flags (BERR, TRAP,
INTR, and BOVFLW) must have been serviced or recycling through the trap sequence.

KS-4

5-78

If a JAMUPP signal occurs when the PWRDN flag is enabled, power fail takes precedence by clearing (K54 FLAG
CLR H) the higher priority flags and using the new stack at location 04.
STALL Flag - The STALL flag inhibits the jam stack overflow checking and provides a no trap service condition.
The flip-flop is clocked to the 1 state for Double Bus Error, red zone stack overflow (K44 OVFLW ERR L) or
PWRDN flag with the clocking signal K4-3 JAMUPP L. Feedback from itself prevents the flag from being lost on
reclocking. The ST ALL flag directly inhibits the overflow checking logic on TIMING (print K44). The flag is cleared
by the processor INIT signal and by Blff04 in the TRP21 microword in the trap service. No inhibits exist on the
BUT04 clearing of the ST ALL flag since the error condition requiring a suspension of overflow checking is serviced
in the first trap service.
WAIT Flag - The WAIT flip-flop is clocked to the 1 state by the IR decode of the WAIT instruction with the K54 P
BUT37 L clocking signal during the FETCH cycle. The flag enables BUBC signals for a WAIT loop in the SERVICE
segment of the microflows.
BRSV Flag - The Bus Request Service flag is set in the SERVICE flows if a bus request requires service. The actual
signal is BUT26 (in SERO? microword at address 020) and the BRPTR flag is active. The flag is used to enable
asynchronous restarting signals to the CLK flip-flop (TIMING, print K4-2) after the bus request; the flag is also used
to inhibit the clearing of BBSY and to generate the K4-5 PART GRANT BR H signal. The flag is cleared by the same
signal used for WAIT clear, with the BITTO? clearing in the bus request SERVICE flow being the most usual.
OVLAP Flag - The Overlap flag is clocked to the 1 state by the data input of K34 OVLAP INSTR H with the K54
P BUT37 L clocking signal during the FETCH cycle. Once set, the flip-flop remains set (unless K54 FLAG CLR H
occurs) for the instruction and provides proper microbranching information (BUBC signals of print K3-7) for a
FETCH OVLAP entry to the FETCH flow sequence for the next instruction. The flag also enables the IDLE flip-flop
(print K4-2) on FETCH OVLAP entry and provides an additional PTR clock (print K4-5). The flag is reclocked
during the next FETCH cycle and is clocked to I or 0, depending upon the K34 OVLAP TNSTR H signal.

5-79

KS-4

Print KS-5: CONSTANTS

Two sets of constants are generated on this print: STPM constants for trap vectors; and the B constants used
throughout the microflows. Tables note the constants and their use.
K5-5 STPM (4,3,2) Hare Special Trap Markers used for trap vectors. Input signals from IR decode and flag flip-flops
provide the highest priority trap vector as the output STPM constant. The STPM signals input to the B constant logic
where they are enabled by a BC code of 00. The STPM constants and use are noted in the STPM table.
K5-5 SBC=lO Lis a decoded signal of the Select B Constant microcode used on the KTl 1-D option.
K5-5 BC (15: 12, 10:09) H
K5-5 BC (11, 08) H
K5-5 BC (07:00) H signals are the B con~tants generated and selected by the Select B Constant (SBC) microcode of
the U WORD. Correlation between the SBC code, the B constants, and their use can be found in the SBC table. Of
special interest are the jumpers {W2 through W7) which allow a power-up vector different from 24 to be used; the
initial jumper selection, however, is for location 24.
Jumper W8 allows the signal PERR (1) L in conjunction with BERR {l) L to generate the trap vector 114 for
memory parity errors.
KS-5 BCON {l +2) His a conditional B constant output which allows a B constant of 1 to become 2 by providing a
K3-8 CINOO L signal. The signal results from the SBC=3 code and is used through the flows in address calculations
where the last address incrementation may be byte or word ordered. A REG {X6+ X7) input forces the
incrementation to 2 for byte incrementation on PC or SP Registers.
K5-5 SBC=16 Lis a decoded signal of the Select B Constant microcode used on the KTl 1-D option.

5-81

KS-5

PrintKS~:

CONSOLE

The logic associated with this print provides the necessary flags and BUBCs for console operation. The following
logic discussion is ordered toward console operation rather than output signals. A functional description of console
switch operation is presented in Chapter 3 of the PDP-11/40 System Manual.
Console logic consists of the flag flip-flops necessary to service the control switches with associated combinational
logic to set and clear the .flags. Some additional logic is necessary to generate the BUBCs utilized in the console
SERVICE flow for microbranches to the individual switch SERVICE flows.
Activation of any console control switch (except HALT/ENAB) results in the SWITCH flag flip-flop being clocked
to the 1 state. This flag is sensed directly through the BUT MUX of print K3-2 in the console loop by BUT06 in.
CON04 microword at location 026. The transitions that clock the SWITCH flag also provide the signal levels
necessary for the Basic Microbranch Test [BUBC (02:00) (BUT30)] to access the individual switch flow responses.
Reference to the flow diagram (D-FD-KDl 1-A-FD) for console operation and BUT30 shows the exclusive nature of
the switch BUBC code; only one switch can be serviced. The SWITCH flag is cleared by the processor INIT signal, by
BUT37 in the FETCH cycle (for START), and by BUT3X (at BUT30 when switch type is being sensed). The PART
P END signal indicates a cycle end pulse for a CL2 or CL3 only.
The START and BEGIN switches require console flags. Each produces a non-filtered (contact bounce exists) INIT
signal when the console switch is activated. Each clocks its flag flip-flop (and the SWITCH flag) to the 1 state as the
switch is released. Both flag flip-flops provide inputs to the BUBC logic for switch sensing; the BEGIN flag is also
used for microbranching to sequence a START flow sequence after a LOAD ADRS flow sequence. The flags are each
cleared by the processor INIT signal by BUT37 in the FETCH flow or by BUTlO in the START flow.
The CONSL flag flip-flop is clocked to the 1 state on entry into the console loop by BUT24 in CON12 microword at
address 255 and by BUT06 in CON04 microword at address 026; both are in the console flow. The CONSL flag
allows single instruction operation by inhibiting the HALT signal in the BUBC (BUT26) signal (print K3-7) in the
SERVICE flow. This allows the CONT switch one instruction FETCH before the HALT switch is serviced as a
console bus request. The CONSL flag also inhibits usual bus error responses by disabling logic for ODA ERR (print
K44) and altering the JAMUPP microaddress (print K4-3). Clocking for NPRs and BRs is also disabled (print K44).
The flag is also used in the KTl 1-D option. The CONSL flag is clocked to the 0 state by a BUT 10 in the START
flow, by a BUT04 if BEGIN, and by a BUT26 in SERVICE flow.
The EXAM and DEP flags are used for essentially the same purpose. They provide automatic address incrementation
for console operations which are consecutive EXAMs or DEPs. The flags are clocked to the 1 state during the latter
part of their respective flow sequences: the EXAM flag is clocked by BUT04 and DADO (1) H; the DEP flag is
clocked by BUT03 and DADO (1) H. The outputs are ORed together (K5-6 CONSL INC H) and used in the B
constant for SBC=7. To prevent the incrementation when EXAM and DEP are directly intermixed, the EXAM flag is
zeroed at input to the DEP flow and the DEP flag is zeroed at the input to the EXAM flow (BUT03 and BUT04,
respectively). Both flags are cleared on entry in the CONSOLE flow (BUT24), in the SERVICE flow (BUT26), and
in the START flow (BUT05).

5-83

KS-6

Print KS-7: CABLES

Two connectors are shown on this print. The KYll-D connector (Jl) has associated logic to drive the ADDRESS
display and accommodate the console control signals utilized on print K5-6.
The other connector (J2) provides an interface for a remote Unibus console to allow remote control of the stop,
initialize, and start functions at a console-provided Unibus address. A manual or automatic remote console interface
may be used, however, care must be taken to avoid simultaneous use of the remote console and the programmer's
console, as both consoles are logically active. Signal interconnections should be twisted pair cables, with the ground
returns provided on the connector. Length is limited to twenty feet. The remote console's Unibus interconnection
for the starting address is governed by appropriate Unibus rules.
The characteristics of the connector signals are noted in their order of activation.
REMOTE STOP L input signal is logically ORed with the KYl 1-D HALT switch to halt the machine after
instruction completion. This signal should be asserted for a minimum of 100 ms.
K5-7 CONSOLE H output signal indicates that the processor is in console mode, awaiting switch activation. This
signal should be present before either REMOTE INIT Lor REMOTE START Lare activated. The K5-7 CONSOLE
H signal should become active sometime during the REMOTE STOP L signal activation. It is cleared during
REMOTE INIT L activation and is reasserted under control of the microprogram approximately 450 ns after the
deactivation of REMOTE INIT L. It is deactivated again under control of the microprogram approximately 40 ms
after activation of REMOTE LOAD L.
REMOTE INIT L signal input clears both the Unibus and the processor. This signal should be asserted for a
minimum of 100 ms and only if the processor has responded to the REMOTE STOP L signal with K5-7 CONSOLE
H. Note that direct enabling of REMOTE INIT L by K5-7 CONSOLE His not possible due to variations in the K5-7
CONSOLE H signal.
REMOTE LOAD L input signal clocks the BEGIN flip-flop to the 1 state and activates the microprogram BEGIN
sequence. This sequence consists of a LOAD ADRS and a START. The REMOTE LOAD L signal should be a
minimum 2 µ.s pulse with a Unibus address provided at activation and maintained as noted below; actual
microprogram action begins at the trailing edge of the pulse. The signal should be asserted when the K5-7 CONSOLE
H is reasserted after the REMOTE INIT.
BUS D (15:00) L Unibus signals are used to provide the starting address for the BEGIN sequence. Electrical
characteristics of these signals are the same as for any other device on the Unibus data lines. The address should be
gated upon the Unibus at the leading edge of the REMOTE LOAD L signal and can be removed with the next
deactivation of K5-7 CONSOLE H.

5-85

KS-7

Print KS-8: BUS DELAYS

Delay circuits associated with Unibus and processor operation are shown on this print. Several delays sequence the
BUS AC LO L and BUS DC LO L signals of the Unibus for power fail operation. Another two delays provide a
RESET instruction Unibus INIT signal and a RESET RESTART signal. Start-up delays for processor operation are
provided by the PWRUP INIT and POWER RESTART one-shots.
KS-8 CLK PWRDN His the Clock Power Down clock signal to the PWRDN flag flip-flop on print K54. Necessary to
this signal is the synchronizing LOWAC flip-flop; this flip-flop, with its associated gating, ensures that no power fail
indication (the activation of BUS AC LO L) is missed and that none provides more than one clocking signal. Sensing
of power failure occurs immediately unless the DELAY POWER DOWN delay is still active after the power-up
situation. Some of the other power fail delays interact (AC LO delay) but these are ordered primarily toward the
proper sequencing of BUS AC LO Land BUS DC LO L signals on the Unibus. Typical waveforms are shown in the
table USUAL POWER FAIL WAVEFORMS. Examples of the power-down and power-up sequences are presented in
detail in Chapter 3.
KS-8 PWR REST ART H signal initiates a JAMUPP to begin microprogram sequences (print K4-3) approximately
70 ms after the deactivation of BUS AC LO L. The PWR flip-flop associated with the POWER REST ART delay
prevents the one-shot from firing unless a power-up situation exists; variations in BUS AC LO L for power-down are
ignored.
KS-8 P ENDRESET L signal is an asynchronous pulse restart signal to the CLK flip-flop (print K4-2) for the RESET
instruction. This restart signal occurs approximately 70 ms after the halt in the RESET flow at RSTOl microword at
address 025 containing a BUT02.
KS-8 RESET REST ART L signal indicates the status of the 70 ms RESET REST ART one-shot.
KS-8 INIT + RESET H signal provides a test point for the signal producing the BUS INIT signal.
BUS INIT L is the Unibus INIT signal consisting of a RESET initialize and the processor initialize (INIT 1). The
signal is used by Unibus peripherals.
KS-8 INIT 1 L
KS-8 INIT 2 L
KS-8 INIT H are signals for the processor to initialize itself and the system. The signal consists of START and
BEGIN switch initialize, direct BUS DC LO L initialize, and a PWRUP INIT one-shot initialize which becomes active
at the deactivation of BUS DC LO L. The signal is used by the processor control flip-flops and all Unibus peripherals.
KS-8 PWRUP INIT L signal is approximately 20 ms and occurs on the deactivation of BUS DC LO L. The signal
initiates a JAMUPP in the microcontrol (print K4-3) to location 377, which contains all Os.
KS-8 B DC LOH is an identification signal for the buffered BUS DC LO L signal.
KS-8 D DC LO Lis the buffered BUS DC LO L signal and is used to directly set the IDLE flip-flop on print K4-2.
KS-8 B AC LO L is the buffered BUS AC LO L signal used as a data input to the JPUP flip-flop and as an inhibit to
the clocking of NPRs.
BUS DC LO Lis the Unibus signal indicating low de voltages. See table of USUAL POWER FAIL WAVEFORMS.
BUS AC LO L is the Unibus signal indicating low ac voltages. See table of USUAL POWER FAIL WAVEFORMS.

5-87

KS-8

CHAPTER 6
KYll-D PROGRAMMER'S CONSOLE

6.1 KYll-D CONSOLE
The KYl 1-D Programmer's Console consists of the KYl 1-D Console Board (5409701) and two cables (BC08R-03)
which are used to interconnect the console to the KDl 1-A Processor. Both power and logic signals are provided by
these cables that connect to the DATA PATHS (M7231) board and the STATUS (M7235) board. Operating
instructions for the console are included in the PDP-11/40 System Manual.
A remote Unibus console interface also exists in the KDl 1-A Processor. This interface is described in Chapter 5 in
relation to print K5-7.
6.2 KYl 1-D CONSOLE BOARD
The KYI 1-D Console Board shown on print D-CD-5409701-0-1 consists of displays with data and control switch
inputs.
6.2.1 Print KYD-2, Display
The display on the console consists simply of light-emitting diodes (LEDs) with current limiting resistors; the drivers
for these displays are located on the DATA PATHS and STATUS boards of the KDll-A Processor. Input signals
from the processor are shown at the left of the displays; actual console panel notation for the displays is shown in
parentheses near the diode symbol.
Connectors (Jl, J2) for processor interconnection are also shown on this print. These connectors provide for the
display signals from the processor, as well as the Switch Register data and control signals to the processor.
6.2.2 Print KYD-3, Switches
The data switch inputs from the Switch Register are shown at the right. Simple resistor inputs are used. The console
functions are shown in parentheses [(SR09) for example] with the connector signals at the right.
The control switches have Set-Reset flip-flops to eliminate contact bounce, in addition to a driving gate. The console
functions are noted in parentheses; the connector signals are at the right.
An additional switch for OFF/POWER/PANEL LOCK is also shown. Its connectors (J3, J4) consist of two quick
disconnect tabs to allow direct interconnection to the cabinet power control unit.
6.3 CABLES
The BC08R-03 cables are interconnected to the KYl 1·D console (Jl, J2) and the M7231 and M7235 modules
according to the instructions on the printed circuit boards and the circuit schematics. Orientation of the shield is
specified and required for proper interconnection. Connection for power control to J3 and J4 is simple: this
connector provides only a switch closure and, therefore, either interconnection of the two wires is acceptable.

6-1

CHAPTER 7
PROCESSOR OPTIONS

7.1 SCOPE
This chapter provides a complete description of three of the internal processor options that may be used with the
KDll·A Processor. These options are:

KJl 1-A Stack Limit
Register

In the basic machine, a fixed boundary is provided to prevent stacks
from expanding into locations containing other information. The Stack
Limit Register provides a programmable boundary with both warning
(yellow) and fatal (red) stack error indications.

KMl 1-A Maintenance
Console

This option provides indicators and switches for manually operating the
system and for monitoring the status of key signals during maintenance
procedures.

KWl 1-L Line Frequency Clock

This option references real intervals and generates a repetitive interrupt
request to the processor. The rate of interrupt is derived from the ac
line frequency.

Processor options differ from bus options in two respects: they are physically mounted within the processor, and
they interact with the processor without necessarily using the Unibus. For example, for many processor options,
jumpers are often added or removed from the processor modules so that the option is logically connected directly to
the processor.
Other processor options are available for use with the KDl 1-A. Because of their size and relative complexity, they
are covered in other manuals. The KEl 1-E Extended Instruction Set and KEl 1-F Floating Instruction Set are both
covered in the KEll-E and KEll-F Instruction Set Options Manual. The KTl 1-D Memory Management option is
covered in the KTI 1-D Memory Management Option Manual.
7.2 KJl 1-A STACK LIMIT REGISTER
The KDl 1-A Processor is capable of performing hardware stack operations. Because the number of locations
occupied by a stack is unpredictable, some form of protection must be provided to prevent the stack from
expanding into locations containing other information. In the basic machine, the protection is provided by a fixed
boundary; the KJl 1-A Stack Limit Register provides a programmable boundary.
The KJl 1-A consists of a single addressable register, accessible to both the console and the processor, that is used to
change the stack limit and to provide warning (yellow zone violation) and error (red zone violation) indications for
the stack. The Stack Limit Register is an 8-bit register (high-order byte) that can be addressed either as a high-order
byte (777775) or as a full word (777774).

7-1

During operation, the register is loaded with an address signifying the lower limit of the stack (stack violations occur
at or below this limit). During subsequent stack pointer related operations of certain bus cycle types (DATO,
DATOB, and DATIP), if the address of the bus operation is less than the contents of the Stack Limit Register, an
error condition exists.
If the difference is less than or equal to 16 words, a yellow zone viqlation occurs. The operations that caused the
yellow zone violation are completed and then a bus error trap occurs. This error trap, which itself uses the stack,
executes without causing an additional violation.
If the space between the bus address and the Stack Limit Register is greater than 16 words, a red zone violation

occurs and the operation causing the error is aborted. The stack is repositioned and a bus error trap occurs; i.e., the
old PS and PC are pushed into locations 2 and 0 and the new PC and PS are taken from locations 4 and 6. A red
zone violation is a fatal stack error. Note that these two stack error conditions exist in the basic KDl 1-A Processor;
however, in this case the stack limit is fixed at memory location 4008 • Other fatal stack errors are odd stack or
non-existent stack.
The KJl 1-A Stack Limit Register Option is a single-height module that plugs into slot E03 of the processor. It
requires the movement or removal of the following jumpers on KDl 1-A Processor modules.

Module

Jumper

New Position

M7231

Kl-7

Connect W2 between module pin E04H2 and pin 06 of E63.

M7234

K44

Connect Wl between module pin B07F2 and pin 10 of E 16.

M7235

K54

Connect Wl between module pin D06R2 and pin 01 of E51.

7 .2.1 Functional Description
The Stack Limit Register logically determines if a particular address is within valid limits or if it is in the yellow
(warning) or red (error) zone of the stack. The logic first compares the high-order byte of the address with the value
in the Stack Limit Register. If the high-order byte is greater than the Stack Limit Register value, then the address is
valid and not infringing on the stack. If, however, the high-order byte of the address and the contents of the Stack
Limit Register are equal, then the address is not valid and the logic must determine which type of violation (yellow
or red) has occurred. The logic then examines bits {07:05) of the low-order byte of the address to determine if the
violation is a yellow zone or red zone violation. If the high-order byte of the address is less than the Stack Limit
Register value, a red zone violation has occurred.
The comparison of the high-order byte of the address and the contents of the Stack Limit Register is shown in Table
7-1.

For the situation where the upper bytes of the Stack Limit Register and the bus address are equal, it is necessary
only to monitor the value of bits {07:05) to determine if a red or yellow zone violation has occurred. If all three of
these bits are set, then the value of the low-order byte must be somewhere in the range of 340 to 377 {20 octal or 16
decimal word locations) which is a yellow zone violation. If any one of the bits is not set, then the highest possible
address would be 33 7, which is the upper limit of the red zone.
Table 7-2 summarizes the method of monitoring the low-order byte to determine whether a red or yellow zone
violation is present.

7-2

Table 7-1
Comparison of Address and SLR
Bit Position
(High Byte)

Octal Value

0
0

0660
0650

1
1

0
0

0650
0650

1
0

0
0

0650
0660

VALID ADDRESS (GREATER THAN)
Bus Address
SLR Contents

0
0

1
1

0
0

1
1

INVALID ADDRESS (EQUAL)
Bus Address
SLR Contents

0
0

1
1

0
0

1
1

0
0

INVALID ADDRESS (LESS THAN)
Bus Address
SLR Contents

0
0

1
1

0
0

0
1

7.2.2 Detailed Description
The Stack Limit Register logic is shown on print D-CS-M7237-0-1. The prime elements of this logic are two 74175
IC circuits (D type registers) and two 7485 IC circuits (4-bit comparators).
The high byte of the Stack Limit Register is loaded by a Unibus reference by the processor or console to the SLR
bus address. The processor decodes this address and routes the data through the D MUX to the Stack Limit Register
logic, providing a proper SSYN signal on the Unibus. These D MUX signals are loaded through the 5384 gates to the
74175 registers with the processor providing the clocking signals. The clock input is true when the Stack Limit
Register has been selected for use (ADRS 777774 His true) and is being loaded (DATI HIGH His true). Under these
conditions, the register is clocked, storing the desired value, and the value of the Stack Limit Register is applied to
the input lines of the comparators. The 8881 gates provide a Unibus output so that the Stack Limit Register can be
read. A processor or console reference to the SLR address with a DATI bus cycle enables the 8881 gates. Again, the
basic KD 11-A Processor provides all Unibus signals in addition to the gating signals.
The two comparator ICs function as a single 8-bit comparator circuit. The 8-bit byte that indicates the value of the
Stack Limit Register is the A input to the comparator. The high byte of the Bus Address Register (which indicates
the address of the bus operation being performed) is applied as the B input to the comparator circuit.
If A<B, indicating that the bus operation is not infringing on the stack because the bus address is higher than the
stack limit value, no action occurs.
If A=B, it indicates that either a yellow (warning) or red (fatal) stack error exists because the stack limit value and
the high byte of the bus address are identical. In this case (A=B), bits 07 through 05 are examined by the processor
address decoding logic. If all three of these bits are set, then Kl-7 BA (07:05)=1 Lis true, gates are enabled, and
KJ-2 EOVFLW L indicates a yellow zone violation. Note that one line on the gate that produces KJ-2 EOVFLW Lis
tied to +5 V. When the KTl 1-D Memory Management option is installed, that input is used to inhibit all overflow
conditions in user mode.

7-3

If any one of the bus address bits 07 through OS is not set, then the signal Kl-7 BA (07:05)=1 Lis high and qualifies
an AND gate for KJ-2 BOVFLSTOP 11, thereby indicating a red zone violation.
If A>B, indicating that the bus operation is infringing on the stack because the bus address is lower than the stack
limit value, then a red zone violation occurs and the logic produces KJ-2 EOVFL STOP H, which is used by the
processor to provide appropriate service of the error.

Table 7-2
Detecting Type of Violation
High-Order Byte
Bus
Address

421

Low-Order Byte

Morn thm SLR ~I

>VALID

400

o..

"'I

377

0
Equal to S L R /
bits7,6,Sue ~
all set

>YELLOW

340

337

Equal to S L R /
bits 7,6,5 are.
not all set
~
000

NOTES:

~
>RED

In above example, SLR is loaded with 000.

In all cases, highest yellow zone address must end in either 377 or 777.

In all cases, highest red zone address must end in either 337 or 737.

0 .J

7.3 KMl 1-A MAINTENANCE CONSOLE
The KMll-A Maintenance Console (also referred to as the maintenance module) provides the user with a means of
manually operating the system and monitoring machine states during maintenance operations.

7-4

The maintenance console itself contains four switches and 28 indicators that monitor various signals within the
processor. When an indicator lights, it means that the associated logic level is high. An overlay can be attached to the
module to indicate what signals are being monitored. This overlay is necessary because the console is designed as a
general-purpose device and can be used, with different overlays, in many PDP-11 devices. The specific functions
monitored by the console depend on the logic signals wired to the device.
If the maintenance console is to be used for monitoring KDll-A Processor operation, then the KDll-A overlay
(Figure 7-1) is used and the module is inserted into processor slot FOL The functions controlled by the switches and
monitored by the indicators are listed in Table 7-3.

PUPP PUPP PUPP
8

PUPP PUPP PUPP
5

T
R

5
5

BUPP BUPP BUPP

N
M
5
y

PUPP PUPP PUPP

BUPP BUPP BUPP
5

BUPP BUPP BUPP
2

MCLK

MCLK
ENAB

! MSTOP !

KDl 1-A
Figure 7-1 KD 11-A Maintenance Console Overlay
(A-SS-5509081-0-12)

7-5

Table 7-3
KMl 1~A Controls and Indicators for KDl 1-A Overlay
Control
Indicator

Indication

Print Showing
Signal Origin

PUPP (08 :00)

Indicates the Previous Microprogram Pointer (PUPP). These nine
indicators represent a 3-digit octal word from 000 to 777. These
indicators are the ROM address of the present U WORD.

K2-2, K2-3

BUPP (08:00)

Indicates the output of the Basic Microprogram Pointer , (UPP)
Register. In effect, displays the address of the next U WORD
(includes branching).

K2-2, K2-3

TRAP

Indicates that the TRAP signal is present.

SSYN

Unibus Slave Sync (SSYN) is present.

K4-6

MSYN

Unibus Master Sync (MSYN) is present.

K4-4

T bit of the processor status word is present. This bit is used in
program debugging and results in a trap sequence.

KS-2

Carry bit of the processor status word condition code is present
(previous operation resulted in a carry from the most significant bit).

KS-2

Overflow bit of the processor status word condition code (operation
resulted in arithmetic overflow).

KS-2

Zero bit of the processor status word condition code is present
(result of operation was 0).

KS-2

Negative bit of the processor status word condition code is present
(result of operation was negative).

KS-2

MCLKENAB

When active (in direction of arrow) this switch prevents the
automatic reclocking of the CLK flip-flop on TIMING (print K4-2).
The asynchronous restart of the CLK after bus cycles is also
inhibited. The machine halts after each microword and during bus
cycles (including INTR). The IDLE flip-flop is not affected, and
NODAT timeout flag (print K4-6) is disabled.

MCLK

This switch (when moved toward the arrow) clocks the MCLK
flip-flop on TIMING (K4-6) print and provides the timing pulses for
the present microword. The user can follow the flow diagrams one
microword at a time (Chapter 4 of this manual) to determine the
proper indications on the maintenance module and the
programmer's console. Use of this maintenance clock is considered
to be single clock operation.

7-6

Table 7-3 (Cont)
.KMl 1-A Controls and Indicators for KDll-A Overlay
Control
Indicator
MS TOP

Indication

Print Showing
Signal Origin

This switch is used to examine a specific microword in a program.
The address of the microword to be examined is set into the
programmer's console Switch Register bits (08:00) and MSTOP is set
to ON (toward arrow). The program is then started in a normal
manner and continues running until it reaches the microword
address that has been set into the Switch Register. At that time, the
Kl -9 UPP MATCH H signal loads the IDLE flip-flop of TIMING
(print K4-2) to a 1, causing a machine halt. MCLK can continue
operation. Note that MSTOP can only be used at the machine speed
if the previous microword is of a CL2 or CL3. A CLl word does not
allow the UPP MATCH logic sufficient time for comparison. If single
clock operation is being used, all cycle lengths may be used.

If the console is to be used for monitoring operation of the KTl 1-D Memory Management Option and/or the
KEl 1-E Extended Instruction Set and KEl 1-F Floating Instruction Set Options, then the KTl 1-D, KEl 1-E,F
overlay (Figure 7-2) is used and the module is inserted into processor slot EOl. In this case, the 16 indicators at the
end of the overlay are used for the KTl 1-D functions and the 12 indicators near the switches are used for the
KEl 1-E,F functions. Note that none of the switches are operational when the console is used for this purpose. The
functions monitored by the indicators are listed in Table 74 and must be correlated with the information in specific
microwords of the flow diagram.

7.3.1 Functional Description
The .KMl 1-A Maintenance Console consists of 28 indicator lights, four control switches, control switch logic, and 28
indicator driver circuits mounted on a 2-module set.
The 28 indicator driver circuits provide a low output level (activating the lamps) when a high logic level is the input.
The driving circuits have a high input impedance and can be used on fully loaded TTL logic output.
The four control switches and associated control switch logic initiate logic sequences and conditions in the unit
tested by generating three key logic signals (switches S2, S3, and S4) with a grounding control signal (Sl). Switches
S2 and S4 are normally used for clock enable and clock signals, respectively.
7.3.2 Physical Description
The KMll-A Maintenance Console is contained on two modules: Maintenance Board 1 (W130 module) and
Maintenance Board 2 (Wl31 module). The Wl30 module contains the 28 indicator driver circuits and connects the
control switch signals and +5 V between the unit under test and the Wl31 module. The W131 module contains the
indicator lights, the control switches, and the control switch logic. The maintenance console is shown on print
D-BS-.KMl 1-0-MB.
The Wl31 module plugs into the W130 module, which, in turn, plugs into the unit under test. Pin and signal
designations for the Wl31 connector are shown on print KM-3.

7-7

7.3.3 Configurations
Because of the number of functions to be monitored, some PDP-11 units have two slots for use with the KM 11-A. In
these instances, the KMll-A can be used in one slot or the other, depending on what is being monitored; or, two
KMl 1-A consoles can be used so that all functions can be monitored simultaneously. Table 7-5 lists PDP-11 units
tested and includes the number of available slots.
7.3.4 Power
The KMl 1-A receives two voltages from the unit under test. The +5 V power is applied at pin A2 of the W130
connector and is used to drive the W131 control switch logic. Nominal +8 V power is applied at pin Bl of the W130
connector and provides power to the indicator lights. Each indicator driver circuit controls the voltage across its
respective indicator light. The driver circuits a:re driven by the logic power of the signals being monitored.
Note that no +8 V power is available in the KDl 1-A Processor backplane; +5 V power is used for the indicator lights.

0
'

ROM
A

PBA

ROM
B

PBA

ROM

PBA

ROM

PBA

EXP EXP ECIN
OVFL UNFL 00

815

LI..

L.J
'

MSR
01

EPS
(N)

MSR DR09 DROO
00

EPS
CZ)

EPS
(V)

EPS
CC)

KTl 1-D
KEl 1-E.F
Figure 7-2 KTI 1-D, KEl 1-E,F Maintenance Console Overlay
(A-SS-5509081-0-13)
7-8

(

Table 7-4
KMl 1-A Indicators for KTll-D and KEl 1-E, F Overlay
Indicator

Indication

Print Showing
Signal Origin

* PBA (15 :06)

Indicates a logic 1 in the associated bit of the physical bus address.
Note that the physical bus address is the address from the KTl 1-D
and may be different from the address in the Bus Address Register
of the processor.

KT-4

*ROMA,
ROMB

These two lights form a pattern to indicate the appropriate mode
and the space to be used on a memory access. The pattern is listed
below. A 0 indicates the light is off; a 1 indicates it is on.

KT-2

ROMA

ROMB

0
1

Current Mode
Temporary Mode
MTPI/D, Previous Mode
or
not MTPI/D, Current Mode
MFPI/D, Previous Mode
or
not MFPI/D, Current Mode

*ROMC

Indicates presence of ROM bit C which is used to enable clocking of
PS (15:14) current mode into PS (13:12) previous mode for future
controlled access and clocking of T (15: 14).

KT-2

*ROMD

Indicates presence of ROM bit D which is used in conjunction with
the final bus cycle of the KDl 1 instructions for relocation in
destination mode only.

KT-2

BIS

Bit 15 of CPU B Register. In divide, used with DROO to determine
the ALU function to be performed in division loop.

Kl-5

ECIN 00

An external carry-in to the ALU.

KE-5

EXPUNFL

Indicates exponential underflow during EXI 1 of floating point
flows.

KF-4

EXPOVFL

Indicates exponential overflow during EXIl of floating point flows.

KF-4

DROO

Used in conjunction with other bits to indicate various conditions;
e.g., with Bl 5 in divide to determine ALU functions and to
determine need for divisor correction. See EPS(C) for other use.

KE-2

DR09

Used as test for normalization.

KE-2

*These indicators are used only with the KTll-D Memory Management Option; the remaining indicators are used with the KEll-E
EIS and the KEll-F FIS Options.

7-9

Table 7-4 (Cont)
KMl 1-A Indicators for KTl 1-D and KEl 1-E, F Overlay
Indication

Indicator

Print Showing
Signal Origin

MSROO

Bit 00 of MSR Register. Indicates ALU function in FDIV.

KF-2

MSROI

Bit 01 of MSR Register. Indicates ALU function in FMUL.

KF-2

EPS(C)

C bit of extended processor status. In MUL, used with DROO to
determine ALU function in multiply loop.

EPS(V)

Overflow bit of the extended processor status.

KE-6

EPS(Z)

Zero bit of the extended processor status.

KE-6

EPS(N)

Negative bit of the extended processor status.

KE-6

NOTE: The functions described in Table 7-4 describe the general purpose of the indicator. At times, a single
indicator may show a number of functions, depending on the current state of the processor and option.
This is why in order to use the maintenance module properly, the flow diagrams should be followed to
determine the significance of an indication at any one time.

Table 7-5
KMll-A Configurations
Unit Tested

Available
Slots

Remarks

KD 11-A Processor

one slot used for KDl 1-A;
one slot used for KTl 1, KE 11-E, F

KTl 1-D Memory Management

uses KDl 1-A Processor slot
shares overlay with KEl 1

KEl 1-E, F Extended
Instruction Sets

use KD 11-A Processor slot
shares overlay with KTl 1

TMl 1 DECmagtape Control

peripheral controller

DTl 1 Bus Switch
RKl 1-C Moving Head Disk
Drive Control

peripheral controller
overlays labeled:
RKll-1
RKl 1-2

7-10

7.4 KWl 1-L LINE FREQUENCY CLOCK
The KWI I-L Line Frequency Clock is a PDP-I I /40 processor option that provides a method of referencing real
intervals. This option generates a repetitive interrupt request to the processor. The rate of interrupt is derived from
the ac line frequency, either 50 Hz or 60 Hz. The accuracy of the clock period, therefore, is dependent on the
accuracy of this frequency source.
The KWI I-L Line Frequency Clock can be operated in either an interrupt or non-interrupt mode. When the
interrupt mode is used, the clock option interrupts the processor each time it receives a pulse from the line
frequency source. In the non-interrupt mode, the clock option functions as a program switch that the processor can
either examine or ignore. Mode selection is made by the program.
The KWI I-L Line Frequency Clock is installed in slot F03 of the KDI I-A Processor backpanel. Installation requires
that a backpanel wire between pins F03R2 and F03V2 be removed. This places the KWI I-L option in the BG6H
signal line.

7.4.1 General Description
The KWll-L Line Frequency Clock is a single-height module containing an address selector, threshold detector,
interrupt control, and a 2-bit Status Register. A block diagram of the clock is shown in Figure 7-3 with details on
prints D-BS-KWI I-L-0-I and D-CS-M787-0-I of the PDP-11 /40 System Engi,neering Drawings.

~
ADDRESS
SELECTOR

A(ff01)

MSYN
SSYN

u
N
I
B D (os:o1)
u INIT

STATUS
REGISTER

i..

~~NE~UENCY-

THRESHOLD
DETECTOR

l
i..
BR6
BG6 IN
BG6 OUT
SACK
INTR
BBSY
DOG
/'SSYN

INTERRUPT
CONTROL

i..

J
11-019

Figure 7-3 KWI 1-L Block Diagram

When the KWI 1-L is in interrupt mode, the interrupt control section of the option provides the circuits and logic
required to make bus requests, gain bus control, and generate interrupts. Whenever the threshold detector provides a
pulse from the line frequency source, the interrupt control section of the clock initiates a bus request on priority
level 6 (BR6), which is the priority level of the clock.

7-11

The priority logic in the processor recognizes the request and issues a Bus Grant signal if the clock is the highest
priority device requesting an interrupt. The KWl l-L responds with a Selection Acknowledge (SACK) signal. When
the requirements for becoming bus master have been fulfilled, the clock asserts Bus Busy. (BBSY), an Interrupt
(INTR) signal, and an interrupt vector address of 100. The processor generates a Slave Sync (SSYN) signal, then
responds to the interrupt with an interrupt service routine. The interrupt control section of the clock then enters a
rest state until the next initialization.
The 2-bit Status Register in the clock consists of bits 6 and 7 on the data bus line. When bit 6 is set, the clock is in
the interrupt mode; when it is clear, the clock is in the non-interrupt mode. Bit 6 is loaded by a Unibus DATO to the
clock; it is also cleared by Unibus INIT. Bit 7 i~loaded to a 1 by a line clock pulse from the threshold detector or
cleared by a Unibus INIT; it is cleared by any Unibus DATO to the clock.
Bit 7 can be used by the processor to determine which device causes the interrupt. The interrupt service routine
should include a DATI which reads the interrupt monitor bit (bit 7) to serve as a partial check on the origin of the
interrupt vector. Thus, if bit 7 is clear there is an indication to the processor that the clock did not request the
interrupt.
In the non-interrupt mode, the clock performs a more passive function by serving as a program switch .that the
processor can examine or ignore. The interrupt control section is disabled so that the clock cannot assert a bus
request (BR6) and, therefore, cannot go into an interrupt sequence. A programmed DATO must be used to return
the clock to the interrupt mode; programmed DATis must be used to examine the status of the clock. In the
non-interrupt mode, the clock is controlled by programmed instructions from the processor.
7.4.2 Address Selector
The address selector logic of the KWl 1-L clock is permanently wired to respond to incoming address 777546. Input
signals consist of address, BUS A (17:00); Bus Control, BUS Cl; and BUS MSYN (drawing D-BS-KWl l-L-0). BUS
AOO, which is used for word or byte control, is not brought into the clock because the KWl 1-L deals only with full
16-bit words. When the address is decoded by the address selector and BUS MSYN is active, gate E3 output goes
high (drawing D-BS-KWl l-L-01), thereby signaling that the clock has been addressed.
7.4.3 Interrupt Control
The interrupt control section of the KWl 1-L Clock provides the necessary logic for issuing bus requests, gaining bus
control, and generating interrupts. The interrupt logic uses three flip-flops: INTERRUPT REQUEST, FFl, and FF2
(Figure 74). Table 7-6 lists the settings of these flip-flops in relation to the bus states and the signals asserted.
When the clock is not issuing an interrupt request, all three flip-flops are in the 0 state and no signals are asserted on
the bus. The request state is entered when the INTERRUPT REQUEST flip-flop is set by a line clock pulse. This
setting of the flip-flop can occur only when the status bit 6 flip-flop (interrupt enable) is in the 1 state. Setting the
INTERRUPT REQUEST flip-flop generates a BR6 request.
The priority arbitration logic of the processor determines whether priority level 6 is the highest requesting level. If
BR6 is the highest level, then the processor asserts a Bus Grant signal (BG6 IN H) that sets the FFl flip-flop. Signal
BG6 is blocked from being passed on to the next device and the assertion of BR6 is dropped. With flip-flop FFl set
and flip-flop FF2 clear, the Selection Acknowledge (SACK) signal is asserted on th,e bus.
On receiving the SACK signal, the processor drops BG6 IN and flip-flop FF2 is set, provided SSYN and BBSY are
both unasserted. The BBSY and INTR signals are then asserted on the bus, as well as interrupt vector address 100
(BUS D06).
The processor responds to these signals by asserting a Slave Sync (SSYN) signal that clears the INTERRUPT
REQUEST flip-flop. Flip-flops FF 1 and FF2 are subsequently cleared, causing the interrupt control section of the
KWl 1-L Clock to return to the non-requesting state. At the same time SSYN is asserted, the processor enters the
interrupt service routine at vector address 100.
7-12

INTERRUPT
REQUEST

6
BRG L

BUS

DO 6

BUS
INTR L

E7
BUS S SYN H
BG 6 IN H

8
BUS
SACKL

BG 6
OUT

+5V

T
11-0196

Figure 74 Interrupt Request Section, Simplified Diagram

Table 7-6
Interrupt Control Flip-Flops
Interrupt
Request

FFl

FF2

Not requesting

None

Requesting

BR6

Granted

SACK, BG6 OUT inhibited

Master

BBSY, INTR, BUS D06
(vector address)

State

7-13

Signals

7.4.4 Status Register
The Status Register of the KWl 1-L contains the INTERRUPT ENABLE and the INTERRUPT MONITOR flip-flops
(Figure 7-5). Operation of the Status Register logic is controlled by INIT, the line clock pulse, and DATO and DATI
transfers.
The INIT signal is generated by either pressing the START switch on the programmer's console or by issuing a
programmed RESET instruction. The INIT signal clears the flip-flops to initialize the Status Register for a new
operation.
The line clock pulse supplied by the threshold detector is used to set the INTERRUPT MONITOR flip-flop (bit 07).
A DATO and ADDRESS H clear the INTERRUPT MONITOR flip-flop, provided BUS D07 is high, by applying a
signal to the direct clear input of the flip-flop.
In order for DATO and DATI transfers to affect the logic of the Status Register, the address of the KWll-L and
MSYN must be asserted on the bus to provide the ADDRESS H input as shown in Figure 7-5. The ADDRESS H
signal is also used, after a delay, to assert SSYN on the bus.
The combination of DATO and ADDRESS provides a signal to the clock input of the INTERRUPT ENABLE
flip-flop. Depending on BUS D06, the flip-flop is either set or cleared. Thus, the processor can write a bit into this
flip-flop by issuing a DATO and BUS D06=1 for a 1 and a DATO and BUS D06=0 for a 0. The 0 side output of the
INTERRUPT ENABLE flip-flop controls the interrupt function of the clock by holding the INTERRUPT
REQUEST flip-flop in the interrupt control section in a cleared state when INTERRUPT ENABLE is in the 0 state.
A DATI and ADDRESS H provide gating that reads the contents of INTERRUPT ENABLE on BUS D06 and the
contents of INTERRUPT MONITOR onto BUS D07.

ADDRESS H

BUS
C1 L

E13
BUS 5
SYN L

LINE CLOCK 3

11-0198

Figure 7-5 Status Register, Simplified Logic Diagram

7-14

I
I
I
t

I
I

KDl 1-A PROCESSOR
MAINTENANCE MANUAL
EK-KDl lA-MM-001

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