KD11-A Processor Maintenance Manual

This document is a maintenance manual for the KD11-A processor, a core component of the PDP-11/35 and PDP-11/40 computer systems.

The manual provides a comprehensive description of the KD11-A's microprogrammed architecture, which is central to its operation. It explains how the processor executes microwords stored in a Read-Only Memory (ROM) to perform elementary operations and determine the next machine state, often through conditional branching based on internal and external conditions.

The document is organized into key functional areas:

1. Microprogramming: Introduces the concept and structure of microwords and microroutines.
2. Block Diagram Description: Details the processor's main logical elements and interconnections, divided into Interface (Unibus control, programmer's console), Data Paths (Arithmetic Logic Unit, registers), and Microcontrol (ROM, instruction decoding, branching, timing).
3. Microprogram Flow Diagrams: Explains how to interpret the graphical representations of the processor's operational sequences and conditional branching.
4. Logic Diagram Description: Provides detailed explanations of the processor's circuit schematics and wire lists.

Finally, it describes several processor options, including the KY11-D Programmer's Console (user interface), KJ11-A Stack Limit Register (memory protection), KM11-A Maintenance Console (manual control and monitoring), and KW11-L Line Frequency Clock (real-time interrupts).

The manual aims to provide detailed information necessary for understanding, operating, and troubleshooting the KD11-A processor.