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EK-KD11E-TM-001

December 1976

126 pages

Original

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Document:	KD11-E Central Processor Maintenance Manual
Order Number:	EK-KD11E-TM
Revision:	001
Pages:	126
Original Filename:	EK-KD11E-TM-001_KD11-E_Central_Processor_Maintenance_Manual_Dec76.pdf

OCR Text

KD 11-E central
processor
maintenance manual

EK·KD11 E·TM·001

KD 11-E central
processor
maintenance manual

digital equipment corporation • maynard, massachusetts

1st Edition, December 1976

Copyright © 1976 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-IO
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

PDP
RSTS
TYPESET-8
TYPESET-II
UNIBUS

CONTENTS
Page
CHAPTER 1

OVERALL DESCRIPTION

CHAPTER 2

INSTRUCTION SET

2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.5
2.6

INTRODUCTION
ADDRESSING MODES ..
PDP-ll/34 INSTRUCTIONS
INSTR UCTION EXECUTION TIME
Basic Instruction Set Timing
Bus Latency Times
..... .
EXTENDED INSTRUCTION SET
INSTRUCTION SET DIFFERENCES

CHAPTER 3

CPU OPERATING SPECIFICATIONS

CHAPTER 4

DETAILED HARDWARE DESCRIPTION

4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.4.1
4.4.2
4.4.3
4.5
4.5.1
4.5.2
4.5.3
4.5.3.1
4.5.3.2
4.5.3.3
4.5.3.4
4.5.3.5
4.6
4.7

INTRODUCTION . . . .
DATA PATH . . . . . .
General Description
Arithmetic Logic Unit (ALU)
Scratchpad
...... .
B Leg . . . . . . . . . .
ALU Multiplexer (AMUX)
Processor Status Word . .
CONDITION CODES . . . . .
Instruction Categorizing ROM
Byte Multiplexer (BYTE MUX)
C and V Decode ROM . . . . .
Condition Code Signal CC Z H
UNIBUS ADDRESS AND DATA INTERFACE
Unibus Drivers and Receivers
Unibus Address Generating Circuitry
Internal Address Decoder
INSTRUCTION DECODING
General Description
Instruction Register ..
Instruction Decoder ..
Instruction Decoder Circuitry
Double-Operand Instructions
Single-Operand Instructions
Branch Instructions
Operate Instructions
AUXILIARY ALU CONTROL
DATA TRANSFER CIRCUITRY

iii

2-1
2-1
2-4
2-26
2-26
2-30
2-30
2-31

4-1
4-1
4-1
4-5
4-7
· 4-11
· 4-20
· 4-20
4-24
4-24
4-24
4-25
4-25
· 4-25
· 4-25
· 4-25
· 4-29
4-29
4-29
4-30
4-30
4-30
·4-31
4-33
4-34
4-34
4-35
4-39

CONTENTS (Cont)
Page
4.7.1
4.7.2
4.7.2.1
4.7.2.2
4.7.2.3
4.7.2.4
4.7.2.5
4.7.2.6
4.7.2.7
4.7.2.8
4.7.2.9
4.7.2.10
4.8
4.9
4.10
4.10.1
4.10.2
4.10.3
4.11
4.11.1
4.11.2
4.12
4.12.1
4.12.1.1
4.12.1.2
4.12.1.3
4.12.1.4
4.12.1.5
4.12.2
4.12.2.1
4.12.2.2
4.12.2.3
4.12.3
4.12.3.1
4.12.3.2
4.12.3.3
4.12.4
4.12.4.1
4.12.4.2
4.12.5
4.12.5.1
4.12.5.2
4.12.6
4.12.6.1
4.12.6.2
4.12.7

General Description . . . . .
Control Circuitry . . . .. .
Processor Clock Inhibit
Unibus Synchronization
Bus Control . . . . . .
M8264 NO-SACK Timeout Module
MSYN/SSYN Time-Out Circuitry
Bus Errors . . . . . . . .
Parity Errors . . . . . . .
End of Transfer Circuitry
Data-in-Pause Transfer .
Odd Address Detection
POWER FAIL/AUTO RESTART
PROCESSOR CLOCK . . .
PRIORITY ARBITRATION
Bus Requests
Nonprocessor Requests (NPRs)
Halt Giant Requests
SERVICE TRAPS . . . .
General Description
Circuit Operation
MEMORY MANAGEMENT
General
Introduction . .
Programming
Basic Addressing
Active Page Registers
Capabilities Provided by Memory Management
Relocation . . . . . . . .
Virtual Addressing .
Program Relocation
Memory Units .. .
Protection . . . . . . . .
Inaccessible Memory
Read-Only Memory
Multiple Address Space
Active Page Registers
Page Address Registers (PAR)
Page Descriptor Registers
Virtual and Physical Addresses
Constmction of a Physical Address
Determining the Program Physical Address
Status Registers . . . . . . .
Status Register 0 (SRO)
Status Register 2 (SR2)
Mode Description . . . . . .
iv

4-39
4-39
4-39
4-39
4-40
4-41
4-41
4-45
4-45
4-45
4-45
4-47
4-47
4-50
4-52
4-52
4-54
4-54
4-56
4-56
4-56
4-57
4-57
4-57
4-57
4-58
4-58
4-59
4-59
4-59
4-60
4-62
4-62
4-62
4-62
4-62
4-63
4-64
4-64
4-69
4-69
4-70
4-71
4-71
4~73

4-73

CONTENTS (Cont)
Page

4.12.8
4.13
4.13.1
4.13.2
4.13.3

Interrupt Conditions
CONTROL STORE
General Description
Branching Within Microroutines
Control Store Fields . . . . . .

CHAPTER 5

MICROCODE

5.1
5.2

MICROPROGRAM FLOWS
FLOW NOTATION GLOSSARY

4-73
4-74
4-74
,.
4-74
4-76

5-1
5-1

ILLUSTRA TIONS
Figure No.

2-1
2-2
2-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11

4-12
4-13
4-14
4-15
4-16
4-17

4-18
4-19
4-20

4-21
4-22
4-23
4-24
4-25
4-26

4-27

Title
Addressing Mode Instruction Formats
PDP-II Instruction Formats . . . . .
Extended Instruction Set Number Formats
KD I I-E Block Diagram
Simplified KDII-E Data Path
ALU Block Diagram . . . . .
Scratchpad Timing
.....
Scratchpad Address Multiplexer (SPAM)
B Leg Block Diagram
BREG Block Diagram
BX REG Block Diagram
BMUX Block Diagram
B Leg Shift Logic
AMUX Block Diagram
Processor Status Word
Byte Multiplexer
Rotate Instructions
C and R Decode ROM
Unibus Transceiver
Processor Clock Cycle Timing
Unibus Address Logic Block Diagram
Unibus Synchronizer
NO-SACK Timeout Module
SSYN/MSYN Control
Data Transfer Multiplexer
Error Logic
.....
End-of-Transfer Logic ..
Odd Address Detection
BUS AC LO and BUS DC LO Timing Diagram
Processor Clock Circuit
v

Page
2-2
2-25
2-30
4-2
4-3
4-6
4-8
4-9
4-11
4-12
4-14
4-15
4-17
4-21
4-23
4-24
4-26
4-27
4-27
4-28
4-28
4-39
4-42
4-43
4-44
4-46
4-47
4-48
4-49
4-51

ILLUSTRATIONS (Cont)
Page
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
5-1

Priority Arbitration Synchronizer
Priority Bus Control . . . . . . .
Active Page Registers . . . . . .
Simplified Memory Relocation Example
Relocation of a 32K Word Program into 124K-Word Physical Memory
Page Address Register . . . . . . . . . .
Page Descriptor Register . . . . . . . . .
Example of an Upward-Expandable Page
Example of a Downward-Expandable Page
Interpretation of a Virtual Address
Displacement Field of Virtual Address
Construction of a Physical Address
Format of Status Register 0 (SRO)
Format of Status Register 2 (SR2)
Control Store Fields . . . . . . .
KDIl-E Simplified Flow Diagram

4-53
4-55
4-59
4-60
4-61
4-64
4-64
4-66
4-67
4-69
4-69
4-70
4-71
4-73
4-75
5-2

TABLES
Table No.
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14

Title
Addressing Modes . . . . .
Single Operand Instructions
Double Operand Instructions
Program Control Instructions
Miscellaneous Instructions
Condition Code Operators
PDP-l 1/34 Instruction Set
Programming Differences
Standard and Modified Unibus Pin Assignments
Function Units of the KD 11-E Data Path
ALU Functions and Control Signals . . . . . .
Scratch pad Enabling Configurations and Modes
SPAM Input Data Sources . . . . . . . . . . .
SPM Register Utilization
.......... .
Band BX Register Enabling Configurations and Modes
BMUX Enabling Configurations and Modes . . . . .
Processor Status Word Register Bit Assignments
Auxiliary Control for Binary and Unary Instructions
Priority Service Order . . . . .
Vector Addresses . . . . . . .
PAR/PDR Address Assignments
Access Control Field Keys . . .
Relating Virtual Address to PAR/PDR Set

Page
2-3
2-5
2-10
2-14
2-22
2-25
2-27
2-32
3-2
4-4
4-7
4-8
4-10
4-10
4-13
4-16
4-22
4-37
4-52
4-57
4-63
4-65
4-71

PREFACE

This manual describes the KDII-E Central Processing Unit (M7265 and M7266). The user must have
a general knowledge of digital circuitry and a basic understanding of PDP-II computers to completeiy
understand the contents of this manual.
The following related documents may be valuable as references:
PDP-II Peripherals Handbook
PDP-II/34 Processor Handbook
PDP-II/34 System User's Guide (EK-II034-0P-OOI)
KD Il-E Print Set (MPOO043)

CHAPTER 1
OVERALL DESCRIPTION

The KDII-E is a 2-board central processing unit (CPU) that is combined with a memory system,
Unibus terminators, and optional peripherals in a DDll-P backpanel to build a basic PDP-ll/34
computer. The unit connects directly to the Unibus as a subsystem, and is capable of controlling the
time allocation of the Unibus for peripherals, performing arithmetic and logic operations, and decoding instructions. It can perform data transfers directly between I/O devices and memory, do both
single- and double-operand addressing, handle both 16-bit word and 8-bit byte data, and address up to
I28K of Unibus address space via a memory management system.
The KDII-E is program-compatible with both the KDll-A (PDP-ll/35 and PDP-ll/40 computer
systems) and the LSI-II (with the inclusion of the two special LSI-II instructions). It contains the
KTII-D Memory Management System (optional with the KDII-A, not offered with the LSI-II) and
executes the Extended Instruction Set (EIS) instructions, which were optional with the KDll-A and
standard with the LSI-II. The KDll-E does not execute the Floating Instruction Set (FIS).

I-I

CHAPTER 2
INSTRUCTION SET

2.1 INTRODUCTION
The KD ll-E is defined by its instruction set. The sequences of processor operations are selected
according to the instruction decoding. The following describes the PDP-ll/34 instructions and
instruction set addressing modes along with instruction set differences from those of the KDll-A,
KDll-B, and KD11-D.
2.2 ADDRESSING MODES
Data stored in memory must be accessed and manipulated. Data handling is specified by a PDP-11/34
instruction (MOY, ADD, etc.), which usually indicates:
1.

The function (operation code)

A general-purpose register to be used when locating the source operand and/or locating the
destination operand

An addressing mode (to specify how the selected register(s) is to be used)

Because a large portion of the data handled by a computer is usually structured (in character strings, in
arrays, in lists, etc.), the PDP-ll /34 has been designed to handle structured data efficiently and flexibly. The general registers may be used with an instruction in any of the following ways:
1.

As accumulators. The data to be manipulated resides within the register.

As pointers. The contents of the register are the address of the operand, rather than the
operand itself.

As pointers, which automatically step through core locations. Automatically stepping forward through consecutive core locations is known as autoincrement addressing; automatically stepping backward is known as autodecrement addressing. These modes are
particularly useful for processing tabular data.

As index registers. In this instance the contents of the register and the word following the
instruction are summed to produce the address of the operand. This allows easy access to
variable entries in a list.

PDP-11/34s also have instruction addressing mode combinations that facilitate temporary data storage structures for convenient handling of data which must be frequently accessed. This is known as the
"stack. "

2-1

In the PDP-ll/34, any register can be used as a "stack pointer" under program control; however,
certain instructions associated with subroutine linkage and interrupt service automatically use Register
6 as a "hardware stack pointer." For this reason, R6 is frequently referred to as the "SP."
R 7 is used by the processor as its program counter (PC).
Two types of instructions utilize the addressing modes: single-operand and double-operand. Figure 2-1
shows the formats of these two types of instructions. The addressing modes are listed in Table 2-1.

MO:DE

(ci)

1 5

***"

T
DESTINATION ADDRESS FIELD

OP CODE
* =SPECIFIES DIRECT OR INDIRECT ADDRESS
**=SPECIFIES HOW REGISTER WILL BE USED
*** = SPECIFIES ONE OF 8 GENERAL PURPOSE REGISTERS

(a)
**

~P COD~
15

M+E

(Q)

**II

(Q)

MO~E
6

J..

SOURCE ADDRESS FIELD

t
DESTINATION ADDRESS FIELD

* = DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS
**= SPECIFIES HOW SELECTEO REGISTERS ARE TO BE USED
***=SPECIFIES A GENERAL REGISTER
(b)
11-1227

Figure 2-1

Addressing Mode Instruction Formats

2-2

Table 2-1
Mode

Binary
Code

Name

Addressing Modes
Assembler
Syntax·

Function

Direct Modes

000

010

Autoincrement

(Rn)+

100

Autodecrement

-(Rn)

110

Index

X(Rn)

Value X (stored in a word following
the instruction) is added to (Rn) to
produce address of operand. Neither X nor (Rn) is modified.

Deferred Modes

001

@Rnor(Rn)

all

Autoincrement
Deferred

@(Rn)+

Register is first used as a pointer t o
a word containing the address 0 f
the operand, then incremente d
(always by two, even for byt e
instructions ).

101

A utodecrement
Deferred

@-(Rn)

Register is decremented (always b Y
two, even for byte instructions) an d
then used as a pointer to a wor d
containing the address of th e
operand.

111

Index Deferred

@X(Rn)

Value X (stored in the memor Y
word following the instruction) an d
(Rn) are added and the sum is used
as a pointer to a word containing
the address of the operand. Neither
X nor (Rn) is modified.

2-3

Table 2-1
Mode

Binary
Code

Addressing Modes (cont)
Assembler
Syntax *

Name

Function

PC Addressing
2

010

Immediate

Operand follows instruction.

011

Absolute

@#A

Absolute address follows
instruction.

110

Relative

Address of A, relative to the
instruction, follows the instruction.

III

Relative Deferred

Address of location containing
address of A, relative to the instruction, follows the instruction.

* Rn = Register
X, n, A = next program counter (PC) word (constant)

2.3 PDP-ll/34 INSTRUCTIONS
The PDP-Il/34 instructions can be divided into five groups:

1.
2.
3.
4.
5.

Single-Operand Instructions (shifts, multiple precision instructions, rotations)
Double-Operand Instructions (arithmetic and logical instructions)
Program Control Instructions (branches, subroutines, traps)
Operate Group Instructions (processor control operations)
Condition Code Operators (processor status word bit instructions)

Tables 2-2 through 2-6 list each instruction, including byte instructions for the respective instruction
groups. Figure 2-2 shows the six different instruction formats of the instruction set, and the individual
instructions in each format.

2-4

Table 2-2 Single Operand Instructions

Mnemonic
CLR
CLRB
Clear

OP Code
OOSODD*
10S0DD

Operation
(dst)t +- 0

Condition Codes
N: cleared

Description
Contents of specified destination are replaced with zeroes.

Z: set
V: cleared
C: cleared

tv
I

COM
COMB
Complement

OOSIDD
lOSIDD

(dst) +- n (dst)

N: set if most significant
bit of result is 0
Z: set if result is 0
V: cleared
C: set

Replaces the contents of the destination address by their
logical complement (each bit equal to 0 set and each bit equal
to 1 cleared).

INC
INCB
Increment

00S2DD
10S2DD

(dst) +- (dst) + I

N: set if result is less than 0
Z: set if result is 0
V: set if (dst) was 077777
C: not affected

Add 1 to the contents of the destination.

DEC
DECB
Decrement

00S3DD
lOS3DD

(dst) +- (dst)-1

N: set if result is less than 0
Z: set if result is 0
V: set if (dst) was 100000
C: not affected

Subtract 1 from the contents of the destination.

NEG
NEGB
Negate

00S4DD
lOS4DD

(dst) +- -(dst)

N: set if result is less than 0

Replaces the contents of the destination address by its 2's com
plement. Note that i 00000 is replaced by itself.

Z: set if resul t is 0
V: set if resul t is 100000
C: cleared if result is 0

ADC
ADCB
Add Carry

OOSSDD
lOSSDD

(dst) +- (dst) + C

N: set if result is less than 0
Z: set if result is 0
V: set if (dst) is 077777 and
Cis 1
C: set if (dst) is 177777 and
Cis 1

Adds the contents of the C-bit into the destination. This permits
the carry from the addition of the low-order words/bytes to be
carried into the high-order results.

Table 2-2 Single Operand Instructions (Cont)

N
I
0'\

Mnemonic

OP Code

Operation

Condition Codes

Description

SBC
SBCB
Subtract Carry

0056DD
1056DD

(dst) +- (dst)-C

N: set if result is less than 0
Z: set if result is 0
V: set if (dst) was 100000
C: cleared if (dst) is 0 and C
is 1

Subtracts the contents of the C-bit from the destination. This
permits the carry from the subtraction of the low order words/
bytes to be subtracted from the high-order part of the result.

TST
TSTB
Test

0057DD
1057DD

Cdst) +- (dst)

N: set if result is less than 0
Z: set if result is 0
V: cleared
C: cleared

Sets the condition codes Nand Z according to the contents of
the destination address.

ROR
RORB
Rotate Right

0060DD

(dst) +- (dst)
rotate right
one place.

N: set if high-order bit of
the result is set
Z: set if all bits of result
are 0
V: loaded with the exclusiveOR of the N-bit and the
C-bit as set by ROR

Rotates all bits of the destination right one place. The loworder bit is loaded into the C-bit and the previous contents of
the C-bit are loaded into the high-order bit of the destination.

ROL
ROLB
Rotate Left

006IDD
106IDD

(dst) +- (dst)
rotate left
one place.

N: set if the high order bit of
the result word is set
(result < 0); cleared
otherwise
Z: set if all bits of the
result word = 0; cleared
otherwise
V: loaded with the exclusiveOR of the N-bit and C-bit
(as set by the completion
of the rotate operation)
C: loaded with the high order
bit of the destination

Rotate all bits of the destination left one place. The highorder bit is loaded into the C-bit of the status word and the
previous contents of the C-bit are loaded into the low-order
bit of the destination.

Table 2-2 Single Operand Instructions (Cont)

Mnemonic

OP Code

Operation

Condition Codes

Description

ASR
ASRB
Arithmetic
Shift Right

0062DD
1062DD

(dst) +- (dst)
shifted one
place to the
right.

N: set if the high order bit
of the result is set
(result < 0); cleared
otherwise
Z: set if the result = 0;
cleared otherwise
V: loaded from the exclusiveOR of the N-bit and C-bit
(as set by the completion
of the shift operation).
C: loaded from low order bit
of the destination

ASL
ASLB
Arithmetic
Shift Left

0063DD
1063DD

(dst) +- (dst)
shifted one
place to the left.

N: set if high-order bit of the Shifts all bits of the destination left one place. The low-order
bit is loaded with a O. The C-bit of the status word is loaded
(result < 0); cleared
otherwise
from the high-order bit of the destination. ASL performs a
Z: set if the result = 0; cleared signed multiplication of the destination by 2 with overflow
otherwise
indication.
V: loaded with the exclusiveOR of the N-bit and C-bit
and C-bit (as set by the
completion of the shift
operation)
C: loaded with the high-order
bit of the destination

Shifts all bits of the destination right one place. The highorder bit is replicated. The C-bit is loaded from the low-order
bit of the destination. ASR performs signed division of the
destination by two.

Table 2-2 Single Operand Instructions (Cont)
OP Code

Operation

Condition Codes

ASH
Arithmetic
Shift

072RSS

R +- R Shifted
Arithmetically NN
places to right or
left
Where NN = (src)

N: set if result <0; cleared
otherwise.
Z: set if result = 0; cleared
otherwise.
V: set if sign of register
changed during shift; cleared
otherwise.
C: loaded from last bit shift
out of register.

The contents of the register are shifted right or left
the number of times specified by the source
operand. The shift count is taken as the low-order
6 bits of the source operand. This number ranges
from -32 to +31. Negative is a right shift and positive is a left shift. See Paragraph 2.5 for example.

ASHC
Arithmetic
Shift Combined

073RSS

R, Rvl +- R, Rvl
The double word
is shifted NN
places to the right
or left, where NN =
(src)

N: set if result <0; cleared
otherwise.
Z: set if result = 0; cleared
otherwise.
V: set if sign bit changes
during the shift; cleared
otherwise.
C: loaded with high-order bit
when right shift (loaded with
the last bit shifted out of the
32-bit operand).

The contents of the register and the register ORed
with one are treated as one 32-bit word. Rvl (bits.
0-15) and R (bits 16-31) are shifted right or left
the number of times specified by the shift count.
The shift count is taken as the low-order 6 bits of
the source operand. This number ranges from -32
to +31. Negative is a right shift and positive is a
left shift.
When the register chosen is an odd number, the
register and the register ORed with one are the
same. In this case, the right shift becomes a rotate.
The 16-bit word is rotated right the number of bits
specified by the shift count. See Paragraph 2.5 for
example.

SXT
Sign Extend

0067DD

(dst) +- a if N bit
is clear
(dst) +- -1 N bit
is set

N: unaffected
Z: set if N bit clear
V: cleared
C: unaffected

If the condition code bit N is set then a -1 is placed
in the destination operand: ifN bit is clear, then a
a is placed in the destination operand. This instruction is particularly useful in multiple precision
arithmetic because it permits the sign to be extended
through multiple words.

Mnemonic

tv
I
00

Description

Table 2-2 Single Operand Instructions (Cont)
Mnemonic

SWAB
Swap Byte

OP Code

0003DD

Operation

Byte l/Byte 0
Byte O/Byte 1

Condition Codes

N: set if high-order bit of
low-order byte (bit 7) of
result is set; cleared
otherwise.
Z: set if low-order byte of
result = 0; cleared otherwise.
V: cleared
C: cleared

Description

Exchanges high-order byte and low-order byte of the
destination word (destination must be a word
address).

Table 2-3 Double Operand Instructions

OP Code

Operation

MOV
MOVB
Move

OISSDD*
IISSDD

(dst) ~ (src) t

CMP
DMPB
Compare

02SSDD
12SSDD

(src) - (dst)
[in detail.
(src) + (dst) + 1]

Mnemonic

N
I

Condition Codes

Description

N: set if (src) < 0; cleared
otherwise
Z: set if (src) = 0: cleared
otherwise
V: cleared
C: not affected

Word: Moves the source operand to the destination location.
The previous contents of the destination are lost. The source
operand is not affected.
Byte: Same as MOV The MOVB to a resistor (unique among
byte instructions) extends the most significant bit of the low
order byte (sign extension). Otherwise MOVB operates on
bytes exactly as MOV operates on words.

N: set if result < O. cleared
otherwise
Z: set if result = 0; cleared
otherwise
V: set if there was arithmetic
overflow (i.e., operands
were of opposite signs
and the sign of the destination was the same
as the sign of the result);
cleared otherwise.
C: cleared if there was a
carry from the most significant bit of the result:
set otherwise

Compares the source and destination operands and sets the
condition codes which may then be used for arithmetic and
logical conditional branches. Both operands are unaffected.
The only action is to set the condition codes. The compare is
customarily followed by a conditional branch instruction. Note
that unlike the subtract instruction the order of operation is
(src) - (dst), not (dst) - (src).

Table 2-3 Double Operand Instructions (Cont)

Mnemonic

OP Code

Operation

Condition Codes

Description

BIT
BITB
Bit Test

03SSDD
13SSDD

(src) /\ (dst)

N: set if high order bit of
result set; cleared otherwise
Z: set if result = 0; cleared
otherwise
V: cleared
C: not affected

Performs logical AND comparison of the source and destinatio n
operands and modifies condition codes accordingly. Neither
the source nor destination operands are affected. The BIT instruction may be used to test whether any of the corresponding
bits that are set in the destination are clear in the source.

BIC
BICB
Bit Clear

04SSDD
14SSDD

(dst) +- ~ (src)
/\(dst)

N: set if high order bit of
result set; cleared otherwise
Z: set if result = 0; cleared
otherwise
V: cleared
C: not affected

Clears each bit in the destination that corresponds to a set bit
in the source. The original contents of the destination are lost.
The contents of the source are unaffected_

BIS
BISB
Bit Set

OSSSDD
lSSSDD

(dst) +- (src)
/\ (dst)

N: set if high order bit of
result set; cleared otherwise
Z: set if result = 0; cleared
otherwise
V: cleared
C: not affected

Performs inclusive-OR operation between the source and destination operands and leaves the result at the destination
address; i.e., corresponding bits set in the destination. The
contents of the destination are lost.

ADD
Add

06SSDD

(dst) +- (src)

N: set if result 0; cleared
otherwise
Z: set if result = 0; cleared
otherwise

Adds the source operand to the destination operand and stores
the result at the destination address. The original contents of
the destination are lost. The contents of the source are not
affected_ Two's complement addition is performed.

IV
I

+ (dst)

Table 2-3 Double Operand Instruction (Cont)

Mnemonic

OP Code

Operation

Condition Codes

Description

V: set if there was arithmetic
overflow as a result of the
operation (that is, both
operands were of the same
sign and the result was of
the opposite sign); cleared
otherwise.

ADD (Cont)

C: set if there was a carry from
the most significant bit of
the result; cleared otherwise.

IV
I

SUB
Subtract

16SSDD

(dst) ~ (dst)(src) in detail,
(dst) + - (src)
+ 1 (dst)

* SS =source (address mode and register)
t (src) = source contents

N: set if result < 0; cleared
otherwise
Z: set if result = 0; cleared
otherwise
V: set if there was arithmetic
overflow as a result of
the operation (i.e., if
operands were of op·
posite signs and the sign
of the source was the
same as the sign of the
result); cleared otherwise
C: cleared if there was a
carry from the most
significant bit of the
result; set otherwise

Subtracts the source operand from the destination operand and
leaves the result at the destination address. The original contents
of the destination are lost. The contents of the source are not
affected. In double precision arithmetic, the C-bit, when set,
indicates a borrow.

Table 2-3 Double Operand Instructions (Cont)

Mnemonic
MUL
Multiply

OP Code

Operation

Condition Codes

070RSS

R, Rvl +- Rx(src)

N: set if product is <0;
cleared otherwise.
Z: set if product is 0;
cleared otherwise.
V: cleared
C: set if the result is less
than _2 15 or greater than
or equal to 2 15 -1.

Description

The contents of the destination register and source
taken as two's complement integers are multiplied
and stored in the destination register and the succeeding register (if R is even). If R is odd, only the
low-order product is stored. Assembler syntax is:
MULS,R.
(Note that the actual destination is R, Rvl which
reduces to just R when R is odd.)
(See Paragraph 2.5.1 for example).

DIV
Divide

071RSS

R, Rvl +- R, Rvl
(src)

N: set if quotient <0;
cleared otherwise.
Z: set if quotient = 0;
cleared otherwise.
V: set if source = 0 or if the
absolute value of the register
is larger than the absolute
value of the source. (In this
case the instruction is
aborted because the quotient
would exceed 15 bits.)
C: set if divide 0 attempted;
cleared otherwise.

The 32-bit two's complement integer in Rand Rvl
is divided by the source operand. The quotient is
left in R; the remainder is of the same sign as the
dividend. R must be even.
(See Paragraph 2.5.2 for example.)

XOR

074RDD

(dst) +- Rv (dst)

N: set if the result <0;
cleared otherwise.
Z: set if result = 0;
cleared otherwise.
V: cleared
C: unaffected

The exclusive OR of the register and destination
operand is stored in the destination address. Contents
of register are unaffected. Assembler format is
XORR,D.

IV
I

Table 2-4 Program Control Instructions

Mnemonic
BR
Branch

BNE
Branch if not
equal

OP Code

Operation

000400

PC~PC+

xxxt

(2 X offset)

001000

PC~PC+

xxx

(2 X offset)
if Z = 0

001400

PC~PC+

xxx

(2 X offset) if

Condition Codes
Unaffected

Provides a way of transferring program control within a range
of -128 to + 127 words with a one word instruction. It is an
unconditional branch.

Unaffected

Tests the state of the Z-bit and causes a branch if the Z-bit is
is clear. BNE is the complementary operation to BEQ. It is
used to test inequality following a CMP, to test that some bits
set in the destination were also in the source, following a BIT,
and generally, to test that the result of the previous operation
was not O.

Unaffected

Tests the state of the Z-bit and causes a branch if Z is set. As
an example, it is used to test equality following a CMP operation. to test that no bits set in the destination were also set in
the source following a BIT operation, and generally, to test
that the result of the previous operation was O.

Unaffected

Causes a branch if N and V are either both clear or both set.
BGE is the complementary operation to BLT. Thus. BGE
always causes a branch when it follows an operation that
caused addition to two positive numbers. BGE also causes a
branch on a 0 result.

-"""
tv
I

BEQ
Branch if equal

Z=l

BGE
Branch if greater
than or equal

002000

PC~PC+

xxx

(2 X offset) if
NvV=O

Description

Table 2-4 Program Control Instructions (Cont)

Mnemonic

OP Code

Operation

BLT
Branch if less
than

002400
xxx

PC +- PC +
(2 X offset) if
NV= 1

Unaffected

Causes a branch if the exclusive-OR of the N- and V-bits are 1.
Thus, BLT always branches following an operation that added
two negative numbers, even if overflow occurred. In particular,
BLT always causes a branch if it follows a CMP instruction
operating on a negative source and a positive destination (even
if overflow occurred). Further, BLT never causes a branch when
it follows a CMP instruction operating on a positive source and
negative destination. BL T does not cause a branch if the result
of the previous operation was 0 (without overflow).

BGT
Branch if greater
than

003000
xxx

PC+-PC+
(2 X offset)
ifZ v (N¥
V) =0

Unaffected

Operation of BGT is similar to BGE, except BGT does not
cause a branch on a 0 result.

BLE
Branch if less than
or equal to

003400
xxx

PC +- PC +
(2 X offset) if
Z v (N¥V)
=1

Unaffected

Operation is similar to BLT, but in addition will cause a branch
if the result of the previous operation was O.

BPL
Branch if plus

100000
xxx

PC +-PC +
(2 X offset) if
N=O

Unaffected

Tests the state of the N-bit and causes a branch ifN is clear.
BPL is the complementary operation of BM!.

BMI
Branch if minus

100400
xxx

PC+-PC+
(2 X offset) if
N= 1

Unaffected

Tests the state of the N-bit and causes a branch if N is set. It is
used to test the sign (most significant bit) of the result of the
previous operation.

I
..-

Condition Codes

Description

Table 2-4 Program Control Instructions (Cont)

N
I

Mnemonic

OP Code

Operation

Condition Codes

BHI
Branch if higher

101000
xxx

PC+-PC+
(2 X offset) if
C=O

Unaffected

Causes a branch if the previous operation causes neither a carry
nor a 0 result. This will happen in comparison (CMP) operations
as long as the source has a higher unsigned value than the
destination.

BLOS
Branch if lower
or same

101400
xxx

PC+-PC+
(2 X offset) if
CvZ=1

Unaffected

Causes a branch if the previous operation caused either a carry
or a 0 result. BLOS is the complementary operation to BHI.
The branch occurs in comparison operations as long as the
source is equal to or has a lower unsigned value than the
destination. Comparison of unsigned values with the CMP
instruction to be tested for "higher or same" and "higher" by
a simple test of the C-bit.

BVC
Branch if V-bit
clear

102000
xxx

PC+-PC+
(2 X offset) if
V=O

Unaffected

Tests the state of the V-bit and causes a branch if the V -bit is
clear. BVC is complementary operation to BVS.

BVS
Branch if V-bit set

102400
xxx

PC+-PC+
(2 X offset) if
V= 1

Unaffected

Tests the state of V-bit (overflow) and causes a branch if the
V-bit is set. BVS is used to detect arithmetic overflow in the
previous operation.

BCC }
BHIS
Branch if carry
clear
Branch if higher
than the same

103000
xxx

PC+-PC+
(2 X offset) if
C=O

Unaffected

Tests the state of the C-bit and causes a branch if C is clear.
BCC is the complementary operation to BCS.

BCS}
BLO
Branch if carry set
Branch if lower

103400
xxx

PC +- PC +
(2 X offset) if
C=1

Unaffected

Tests the state of the C-bit and causes a branch if C is set. It is
used to test for a carry in the result of a previous operation.

Description

Table 2-4 Program Control Instructions (Cont)

Mnemonic
JMP
Jump

N
I

OP Code

OOOlDD

Operation
PC <- (dst)

Condition Codes
Unaffected

Description
JMP provides more flexible program branching than provided
with the branch instruction. Control may be transferred to any
location in memory (no range limitation) and can be accomplished with the full flexibility of the addressing modes. with
the exception of register mode O. Execution of a jump with
mode 0 will cause an illegal instruction condition. (Program
control cannot be transferred to a register.) Register deferred
mode is legal and will cause program control to be transferred
to the address held in the specified register. Note that instructions are word data and must therefore be fetched from
an even numbered address. A boundary error trap condition
will result when the processor attempts to fetch an instruction
from an odd address.

Table 2-4 Program Control Instructions (Cont)

Mnemonic
JRS
Jump to
subroutine

OP Code

Operation

004RDD

(tmp) +- (dst)
(tmp is an internal processor
register)
.j, (SP) +- reg
(push reg contents onto processor stack)
reg +- PC PC
holds location following JSR; this
address PC +(tmp), now put in
(reg)

N
I

Condition Codes
Unaffected

Description
In execution of the JSR, the old contents of the specified
register (the linkage pointer) are automatically pushed onto
the processor stack and new linkage information placed in
the register. Thus, subroutines nested within subroutines to any
depth may all be called with the same linkage register. There
is no need either to plan the maximum depth at which any
particular subroutine will be called or to include instructions
in each routine to save and restore the linkage pointer. Further,
since all linkages are saved in a re-entrant manner on the processor stack, execution of a subroutine may be interrupted,
and the same subroutine re-entered and executed by an interrupt service routine. Execution of the initial subroutine can
then be resumed when other requests are satisfied. This process (called nesting) can proceed to any level.

JSR PC, dst is a special case of the PDP-II subroutine call
suitable for subroutine calls that transmit parameters.

RTS
Return from
subroutine

0OO20R

PC +- (reg)
(reg) +- SP t

Unaffected

Loads contents of register into PC and pops the top element
of the processor stack into the specified register.
Return from a non-re-entrant subroutine is typically made
through the same register that was used in its call. Thus, a
subroutine called with a JSR PC, dst exits with an RTS PC,
and a subroutine called with a JSR R5, dst may pick up
parameters with addressing modes (R5) +, X (R5), or @X (R5)
and finally exit, with an RTS R5.

Table 2-4 Program Control Instructions (Cont)
Mnemonic
MARK

OPCode
0064NN

Operation
SP~SP+ 2xnn
PC~R5

R5 ~(SP) t
no = number of
parameters

Description

Condition Codes
Unaffected

Used as part of the standard PDP-II subroutine return
convention. MARK facilitates the stack cleanup procedures involved in subroutine exit. Assembler format
is: MARKN
Example:MOV R5,-(SP)
MOV PI,-(SP)
MOV P2,-(SP)

;place old R5 on stack
;place N parameters on
;the stack to be used
;there by the subroutine

MOV PN ,-(SP)
;places the instruction
MOV #MARKN ,-(SP) ;MARK N on the stack
;set up address at Mark
MOV SP,R5
;N instruction
JSR

IV
I

PC ,SUB

;jump to subroutine

At this point the stack is as follows:

OLDR5
PI
PN
MARKN
OLD PC
And the program is at the address SUB which is the
beginning of the subroutine.
SUB:
;execution of the subroutine itself
RTS R5: ;the return begins
This causes the contents of R5 to be placed in the PC
which then results in the execution of the instruction
MARK N. The contents of old PC are placed in R5
MARK N causes: (1) the stack pointer to be adjusted to
point to the old R5 value; (2) the value now in R5 (the
old PC) to be placed in the PC; and (3) contents of the
old R5 to be popped into R5, thus completing the return
from subroutine.

Table 2-4 Program Control Instructions (Cont)
Mnemonic
SOB
Subtract one and
branch if not
equal to 0

Operation

OPCode
077ROO

R+-R-l

plus offset

if this result
othen PC +- PC
- (2 x offset)

Condition Codes

Description

Unaffected

The register is decremented. If it is not equal to 0, twice
the offset is subtracted from the PC (now pointing to the
following word). The offset is interpreted as a six-bit
positive number. This instruction provides a fast, efficient
method of loop control. Assembler syntax is:
SOB R,A
where A is the address to which transfer is to be made if
the decremented R is not equal to O. Note that the SOB
instruction cannot be used to transfer control in the
forward direction.

tv
I

BPT
Break-point Trap

000003

I
lOT
lOT Trap

000004

-l- (SP) +- PS
-l- (SP) +- PC
PC +- (14)
PS +- (16)

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Performs a trap sequence with a trap vector address of 14.
Used to call debugging aids. The user is cautioned against
employing code 000003 in programs run under these
debugging aids.

-l- (SP) +- PS
-l- (SP) +- PC
PC +- (20)
PS +- (22)

N: loaded from trap vector
Z: loaded from trap vector
C: loaded from trap vector

Performs a trap sequence with a trap vector address of
20. Used to call the I/O executive routine lOX in the
paper-tape software system and for error reporting in the
disk operating system.

Table 2-4 Program Control Instructions (Cont)
Mnemonic

OP Code

EMT
Emulator Trap

104000

Operation

t (SP) +-- PS
t (SP) +-- PC
PC +-- (30)
PS +-- (32)

Condition Codes

Description

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

All operation codes from 104000 to 104377 are EMT
instructions and may be used to transmit information to
the emulating routine (e.g., function to be performed).
The trap vector for EMT is at address 30; the new central
processor status (PS) is taken from the word at address 32.
CAUTION
EMT is used frequently by DEC system software
and is therefore not recommended for general use.

TRAP

104400 to
104777

t (SP) +-- PS
t (SP) +-- PC
PC +-- (34)
PS +-- (36)

IV
I
IV

NOTE: Condition Codes are unaffected by these instructions
*DD = destination (address mode and register)
Hdst) = destination contents

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Operation codes from 104400 to 104777 are TRAP instructions. TRAPs and EMTs are identical in operation, except
that the trap vector for TRAP is at address 34.
NOTE
Since DEC software makes frequent use of EMT, the
TRAP instruction is recommended for general use.

Table 2-5 Miscellaneous Instructions
Mnemonic
RTI

Condition Codes

OP Code

Operation

000002

PC +- (SP) t
PSW +- (SP) t

N: loaded from processor
stack
Z: loaded from processor
stack
V: loaded from processor
stack
C: loaded from processor
stack

Used to exit from an interrupt or trap service routine.
The PC and PSW are restored (popped) from the processor stack. If the RTI sets the T-bit in the PSW, a
trace trap will occur prior to executing the next
instruction.

Description

RTT

000006

PC +- (SP) t
PS +- (SP) t

N: loaded from processor
stack
Z: loaded from processor
stack
V: loaded from processor
stack
C: loaded from processor
stack

This is the same as the RTI instruction, except that it
inhibits a trace trap, while RTI permits a trace trap.
If a trace trap is pending, the first instruction after the
RTT will be executed prior to the next "T" trap. In
the case of the RTI instruction, the "T" trap will
occur immediately after the RTI.

MFPI
MFPD

0065SS
1065SS

(temp) +- (src)
,). (SP) +- (temp)

N: set if the source <0;
otherwise cleared
Z: set if the source = 0;
otherwise cleared
V: cleared
C: unaffected

This instruction pushes a word onto the current stack
from an address in previous space. Processor Status
(bits 13, 12). The source address is computed using
the current registers and memory map.

MTPI
MTPD

0066SS
1066SS

(temp) +- (SP) t
(dst) +- (temp)

N: set if the source <0;
otherwise cleared
Z: set if the source =0;
otherwise cleared
V: cleared
C: unaffected

This instruction pops a word off the current stack
determined by PS (bits 15, 14) and stores that word
into an address in previous space PS (bits 13, 12).
The destination address is computed using the current registers and memory map.

IV
I
IV
IV

Table 2-5 Miscellaneous Instructions (Cont)
Mnemonic

OP Code

Operation

Condition Codes

Description

MFPS

1067DD

(DST) .;- PSW
DST Lower
8 bits

N: set if PSW bit 7=1;
otherwise cleared.
Z: set if PS [0:7] =0;
otherwise cleared.
V: cleared
C: not affected

*The 8-bit contents of the PS are moved to the
effective destination. If destination is mode 0, PS
bit 7 is sign-extended through upper byte of the
register, and destination operand is treated as a byte
address.

MTPS

1064SS

PSW .;- (SRC)

Set according to
effective SRC operand
0-3.

*The 8 bits of the effective operand replace the
current contents of the PSW. The source operand
address is treated as a byte address. Note that PSW
bit 4 cannot be set with this instruction. The SRC
operand remains unchanged.
*Because there is no hardware to prevent execution
of these instructions in User mode, it is necessary
for the system software to prevent any reference to
the PSW address by a user.

N
I
N
W

HALT

000000

Unaffected

Causes the processor operation to cease. The console
is given control of the processor. The console data
lights display the address of the HALT instruction
plus two. Transfers on the Unibus are terminated
immediately. The PC points to the next instruction
to be executed. Pressing the CON key on the console
causes processor operation to resume. No INIT
signal is given.

Table 2-5 Miscellaneous Instructions (Cont)
Mnemonic

OP Code

WAlT

000001

RESET

000005

Operation

Condition Codes
Unaffected

Provides a way for the processor to relfnquish use of
the bus while it waits for an external interrupt. Having
been given a WAIT command, the processor will not
compete for bus by fetching instructions or operands
from memory. This permits higher transfer rates
between device and memory, as no processor-induced
latencies will be encountered by bus requests from
the device. In WAIT, as in all instructions, the PC
points to the next instruction following the WAIT
operation. Thus, when an interrupt causes the PC and
PS to be pushed onto the stack, the address of the
next instruction following the WAlT is saved. The exit
from the interrupt routine (Le., execution of an RTI
instruction) will cause resumption of the interrupted
process at the instruction following the WAIT.

Unaffected

Sends INIT on the Unibus for 100 ms. All devices on
the Unibus are reset to their state at power-up.

tv
I
tv

PC (SP)
PSW (SP)

Description

Table 2-6

Condition Code Operators

Mnemonic

Op Code

Instruction

CLC
CLV
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN
SCC

000241
000242
000244
000250
000257
000261
000262
000264
000270
000277

Clear condition code C.
Clear condition code V.
Clear condition code Z.
Clear condition code N.
Clear all condition code bits.
Set condition code C.
Set condition code V.
Set condition code Z.
Set condition code N.
Set all condition code bits.

NOTE
Selectable combinations of condition code bits may
be cleared or set together. The status of bit 4 controls
the way in which bits 0, 1,2, and 3 are to be modified. If bit 4 = 1, the specified bits are set; if bit 4 =
0, the specified bits are cleared.

1. Single Operand Group !CLR ,CLRB,COM,COMB, INC ,I NCB, DEC, OECB, NEG, NEGB, ADC, AOCB, SBC,SBCB, TST,TSTB, ROR, RORB, ROL ,ROLB,ASR. ASRB.
ASL. ASLB. JMP. SWAB)

os.

OP Code

2. Double Operand Group! BIT.BITB.BIC.BICB.BIS.BISB.ADD.SUB)
OP Code

Src

ds'

3.Program Control Group
o. Branch (a II branch instructions)
OP Code

offset

I
15

b.Jump To Subroutine (JSR)

reg

Src/dst

C.Subroutine Return (RTS)
'I-O--I------O-----------O--------------------------~---------,

reg

d. Traps (break point. lOT, EMT, TRAP)
OP CODE

4.0perate Groupe (HALT,WAIT,RTI,RESET)
OP CODE

5.~ondjtion Code Operators (all condition code instructions)

o
1!-12Z6

Figure 2-2

PDP-II Instruction Formats

2-25

2.4 INSTRUCTION EXECUTION TIME
The execution time for an instruction depends on the instruction itself, the modes of addressing used,
and the type of memory being referenced. In the most general case, the instruction execution time is the
sum of a source address (SRC) time, a destination address (DST) time, and an execute, fetch (EF) time.
Instr Time = SRC Time + DST Time + EF Time
Some of the instructions require only some of these times, and are so noted in Paragraph 2.4.1. All
timing information is in microseconds, unless otherwise noted. Times are typical; processor timing can
vary ±1O%.
2.4.1 Basic Instruction Set Timing
Table 2-7 lists the PDP-ll /34 instruction set, together with the timing characteristics and memory
cycles required. The timing requirements for determining instruction execution time are listed below.
Double-Operand (all instructions)
. Instr Time = SRC Time + DST Time + EF Time
Single-Operand (all instructions)
Instr Time = DST Time + EF Time
Branch. Jump. Control. Trap. and Miscellaneous (all instructions)
Instr Time = EF Time
I.

NOTES
The times specified apply to both word and byte
instructions, whether odd or even byte.

Timing is given without regard for NPR or BR
servicing.

If the memory management is enabled, instruction execution times increase by 0.12 f.LS for
each memory cycle used.

All timing is based on memory with the following performance characteristics:
Access Time
(f.Ls)

Cycle Time
(f.Ls)

Core
(MMll-DP)

0.510

1.1

MOS
(MSll-JP)

0.635

0.920

Memory

2-26

Table 2-7 PDP-l1/34 Instruction Set
SOURCE ADDRESS TIME
Source
Mode

Memory
Cycles

Core
(MMII-DP)
p.s

MOS
(MSII-JP)
p.s

0
1
2
3
4
5
6
7

0
1
1
2
1
2
2
3

0.00
1.13
1.33
2.37
1.28
2.57
2.57
3.80

0.00
1.26
1.46
2.62
1.41
2.82
2.82
4.18

Destination
Mode

Memory
Cycles

Core

MOS

Modifying Single-Operand
and Modifying DoubleOperand (Except MOY,
SWAB, ROR, ROL, ASR,
ASL)

0
1
2
3
4
5
6
7

0
2
2
3
2
3
3
4

0.00
1.62
1.77
2.90
1.77
3.00
3.10
4.29

0.00
1.74
1.89
3.15
1.89
3.25
3.35
4.66

MOY

0
1
2
3
4
5
6
7

0
1
1
2
1
2
2
3

0.00
0.93
0.93
2.17
1.13
2.22
2.37
3.50

0.00
0.93
0.93
2.29
1.13
2.34
2.49
3.75

MTPS

0
1
2
3
4
5
6
7

0
1
1
2
1
2
2
3

0.00
0.95
1.13
2.26
1.13
2.26
2.44
3.57

0.00
0.95
1.26
2.51
1.26
2.51
2.69
4.20

MFPS

0
1
2
3
4
5
6
7

0
1
1
2

0.00
0.64
0.64
1.95
0.82
1.95
2.13
3.26

0.00
0.64
0.64
2.08
0.82
2.08
2.26
3.51

Instruction
Double Operand

DESTINATION TIME
Instruction

2
2
3

2-27

Table 2-7 PDP-ll/34 Instruction Set (Cont)
EXECUTE, FETCH TIME
Memory
Cycles

Core

MOS

2.03

2.16

1.83

1.96

1.83

1.96

1
1
2
2

2.03
2.18
2.99
1.99

2.16
2.31
3.12
2.12

MUL
DIV (overflow)

1
1

ASH
ASHC

1
1

8.82*
2.78
12.48
4.18**
4.18**

8.95*
2.91
12.61
4.31**
4.31 **

2
2

3.07
3.37

3.14
3.34

0
2
2
3
2
3
3
4

0.00
1.42
1.57
2.70
1.62
2.80
2.90
4.09

0.00
1.54
1.69
2.95
1.74
3.05
3.15
4.46

0
1
1
2
1
2
2
3

0.00
1.13
1.28
2.42
1.33
2.52
2.62
3.80

0.00
1.26
1.41
2.67
1.46
2.77
2.87
4.18

Destination
Mode

Instruction
Double Operand
ADD, SUB, CMP, BIT, BIC,
BIS, XOR
MOV

I
I

Single Operand
CLR, COM, INC, DEC, ADC,
SBC,TST
SWAB, NEG
ROR,ROL,ASR,ASL
MTPS
MFPS

EIS Instructions (use with DST times)

Memory Management Instructions
MFPI(D)
MTPI(D)
SWAB, ROR, ROL, ASR,
ASL

Non-modifying
Single Operand and
Double Operand

0
1
2
3
4
5
6
7

2-28

Table 2-7 PDP-ll/34 Instruction Set (Cont)
EXECUTE, FETCH TIME

Instruction

MFPI(D)
MTPI(D)

Destination
Mode

Memory
Cycles

Core

MOS

0
1
2
3
4
5
6
7

0
1
1
2
1
2
2
3

0.00
0.98
1.32
2.20
1.18
2.20
2.40
3.59

0.00
l.24
l.44
2.45
l.44
2.45
2.65
3.96

2.18

2.31

1
1
1

l.63
2.38
l.98

l.76
2.51
2.11

Branch Instructions
BR, BNE, BEQ, (Branch)
BPL, BMI, BVC, BVS, BCC,
BCS, BGE, BLT, BGT, BLE,
BHI, BLOS, BHIS, BLO
(No Branch)
SOB (Branch)
(No Branch)

Jump Instructions
JMP

1
2
3
4
5
6
7

1
1
2
1
2
2
3

l.83
2.18
3.12
2.03
3.07
3.07
4.25

l.96
2.31
3.37
2.16
3.32
3.32
4.78

JSR

1
2
3
4
5
6
7

2
2
3
2
3
3
4

3.32
3.47
4.40
3.32
4.40
4.60
5.69

3.44
3.59
4.65
3.44
4.65
4.85
6.06

2
2
3
1
1

3.32
4.27
4.60
2.03
l.68
l.68
lOOms
7.32

RTS
MARK
RTI, RTT
Set or Clear C, V, N, Z
HALT
WAIT
RESET
lOT, EMT, TRAP, BPT

I
I

*Add 200 ns for each bit transition in serial data from LSB to MSB.
** Add 200 ns per shift.

2-29

3.57
4.52
4.98
2.16
1.81
1.81
lOOms
7.7

2.4.2 Bus Latency Times
Interrupts (BR requests) are acknowledged at the end of the current instruction. For a typical instruction, with an instruction execution time of 4 J.l.S, the average time to request acknowledgement would
be 2/.Ls.
Interrupt service time, which is the time from BR acknowledgement to the first subroutine instruction,
is 7.32 /.LS max for core, and 7.7 J.l.S for MOS.
NPR (DMA) latency, which is the time from request to bus mastership for the first NPR device, is 2.5
/.LS max.

2.5 EXTENDED INSTRUCTION SET
The Extended Instruction Set (EIS) provides the user with the capability of extended manipulation of
fixed-point numbers. Use of the EIS instructions does not degrade processor timing or affect NPR
latency. Interrupts are serviced at the end of an EIS instruction.
The EIS instructions are:
Mnemonic

Instruction

OpCode

MUL
DIV
ASH
ASHe

Multiply
Divide
Shift arithmetically
Arithmetic shift combined

070RSS
071RSS
072RSS
073RSS

The number formats are shown in Figure 2-3. Examples of the operation of each instruction are
presented in the paragraphs that follow.

16·BIT SINGLE WORD:

I
32·BIT DOUBLE WORD:

NUMBER

14
HIGH NUMBER PART

15
LOW NUMBER PART

S is the sign bit.

S = 0 for positive quantities
S = 1 for negative quantities; number is in 2's
complement notation
114453

Figure 2-3

Extended Instruction Set Number Formats

2-30

Multiply Instruction - MUL 070RSS
Example: 16-bit product (R is odd)
000241
012701,400
070127,10
1034xx

,CLC
, MOY fl400,Rl
, MUL#lO, Rl
,BCSERROR

Before
(Rl) = 000400

After
(R t) = 004000

;Clear carry condition code
;Carry will be set if
;product is less than
;-2 15 or greater than or ;equal to 215
;no significance lost

Divide Instruction - DIV 071RSS
Example:
005000
012701,20001
071027,2

, CLR RO
, MOY #2oo01,Rl
, DIY #2,RO

Before
(RO) = 000000
(Rl) = 020001

After
(RO) = 010000 Quotient
(Rt) = 000001 Remainder

Arithmetic Shift Instruction - ASH 072RSS
Example: ASH RO, R3
Before
(R3) = 000003
(RO) = 001234

After
(R3) = 000003
(RO) = 012340

Arithmetic Shift Combined Instruction - ASHC 073RSS
Example: Similar to the example for the ASH instruction except that two registers are used.
2.6 INSTRUCTION SET DIFFERENCES
Table 2-8 lists the instruction set differences between the PDP-ll/34 and other PDP-ll machines.

2-31

Table 2-8 Programming Differences
11/05 and 11/10

11/35 and 11/40

11/04

11/34

Contents of Rare
incremented by 2 (or
decremented by 2),
before being used as
the source operand.

Same as 11/05

GENERAL REGISTERS (including PC and SP)

tv
I

OPR%R,(R)+
or OPR%R,-(R)
OPR%R,@(R)+
OPR%R,@-(R)
(Using the same register
as both source and
destination)

Initial contents of R
are used as the source
operand.

JMP(R)+ or JSR
register, (R)+ Gump
using autoincrement)

Contents of Rare
incremented by 2,
then used as the new
PC address.

Initial contents of P
are used as new PC.

Same as 11/40

MOY PC, @#A or
MOY PC, A (Moving
the incremented PC
to a memory address
referenced by the PC)

Location A will contain PC + 2.

Location A will contain the PC of the
move instruction +4.

Same as 11/05

Stack Pointer (SP),
R6 used for referencing.

Using the SP for
pointing to odd
addresses or nonexistent memory
causes a halt (double
bus error).

Odd address or nonexistent memory
references with SP
cause a fatal trap with
a new stack created at
locations 0 and 2.

Same as 11/05

Table 2-8 Programming Differences (Cont)
11/05 and 11/10

111/35 and 11/40

11/04

11/34

GENERAL REGISTERS (including PC and SP) (Cont)

Stack limit fixed at
400 8 overflow (going
lower) checked after
modes 4 and 5 using
R6, and JSR and traps.
Overflow serviced by
an overflow trap. No
red zone.

Stack Overflow

Variable limit with stack Same as 11/05
limit option. Overflow
checked after JSR, traps,
and address modes 1,2,
4, and 6. Non-altering
references to stack data
are always allowed.
There is a 16-word
yellow (warning) zone.

Same as 11/05

Red zone trap occurs if
stack is 16 words below
boundary; PS and PC
are saved at locations
oand 2.

tv
I

W
W

TRAPS AND INTERRUPTS
RTI Instruction

First instruction after
RTI instruction is
always executed.

If RTI sets the T-bit,
Same as 11/40
the T -bit trap is acknowledged immediately after
the RTI instruction.

RTT Instruction

Not implemented

First instruction after
RTT is guaranteed to
be executed.

Same as 11/40

Odd byte of PS can be
addressed without a
trap.

Same as 11/05

Processor status odd
byte at location
777777

Same as 11/40

Table 2-8 Programming Differences (Cont)
11/05 and 11/10

11/35 and 11/40

11/04

11/34

GENERAL REGISTERS (including PC and SP) (Cont)
T-bit ofPS

T-bit can be loaded
by direct address of
PS or from console.

Only RTI, RTT traps
and interrupts can load
the T-bit

Same as 11/05

Same as 11/40

PC contains odd
address

PC unincremented

Same as 11/05

PC contains an
address in nonexistent memory

PC incremented

PC unincremented

Same as 11/05

Same as 11/40

Same as 11/05

Same as 11/05 except
for MOV mode 2 and
MTPI where the
register will be incremented.

Same as 11/04 except for
MOV mode 2 destination
and MTPI where the
register will be incremented.

Interrupt service
routine.

The first instruction
will not be executed
if another interrupt
occurs at a higher
priority.

Same as 11/05

Bus Errors

Table 2-8 Programming Differences (Cont)
11/05 and 11/10

11/35 and 11/40

11/04

11/34

GENERAL REGISTERS (including PC and SP) (Cont)
Priority order of
of traps and
interrupts

Odd address
Time-out
Halt instruction
Trap instructions
Trace trap
Stack overflow
Power fail
Halt from console

Halt instruction
Odd address
Stack overflow (red)
Mem mgt error
Time-out
Parity
Trap instruction
Trace trap
Stack overflow (yellow)
Power fail
Halt from console

Halt instruction
Bus error
Trap instruction
Trace trap
Stack overflow
Power fail
Halt from console
Interrupts
Next instruction fetch

Same as 11 /40
except no red
zone stack overflow

Swab and V-bit

V-bit is cleared.

Same as 11/05

Instruction set

Basic set

Basic set and Mark,
RTT, SOB, SxT, XOR.
EIS adds: MUL, DIV
ASH, ASHC.
FIS adds: F ADD,
FSUB, FMUL, FDIV.
KT11-D adds: MTPI,
MFPI.

Basic set and RTT

Basic set and Mark,
RTT, SOB, SxT, XOR,
MUL, DIV, ASH,
ASHC, MTPI, MFPI,
MTPS, MFPS. (MTPS
and MFPS are new
instructions used for
LSI-11.)

Memory management
violation during a
trap sequence

Does not apply

If a mem mgt violation occurs between
the first and second
push down of the stack
during a trap sequence,
the status of the CPU
before the violation is
placed as the PS on the
the Kernel stack.

Does not apply

If a mem mgt violation occurs between
the first and second
push down of the stack
during a trap sequence,
the status of the vector
+2 of the original trap
is placed as the PS on
the Kernel stack.

MISCELLANEOUS
N
I
W

CHAPTER 3
CPU OPERATING SPECIFICATIONS

Operating Temperature

50 to 50 0 C (41 0 to 122 0 F)

Relative Humidity

20 to 95% (without condensation)

Input Power

+5 Vdc ±5% at 4.5 A (typical) per module (M7265 and M7266)

Physical Size

Two hex modules (8-1/2 X 15 in.)

Interface Requirements

All I/0 signals are available on connectors A and B. These signals are pin-compatible with modified Unibus pinout as shown
in Table 3-1. The bus loading on each of these Unibus lines is
equivalent to one bus load.

Power and Ground Pinouts

+5 V: pins AA2, BA2, CA2, DA2, EA2, EA2
GND: pins AC2, AT1, BC2, BTl, CC2, CT1, DC2, DT1, EC2,
ET1, FC2, FT1

Number of Integrated
Circuits

231 (M7265 = 120; M7266 = 111)

3-1

Table 3-1 Standard and Modified Unibus Pin Assignments

Standard
Signal

Modified
Signal

AAl
AA2
ABI
AB2
ACI
AC2
ADI
AD2
AEI
AE2
AFl
AF2
AHI
AH2
AJI
AJ2
AKI
AK2
ALl
AL2
AMI
AM2
ANI
AN2

INIT L
+5V
INTRL
GROUND
DOOL
GROUND
D02L
DOl L
D04L
D03 L
D06L
D05 L
D08L
D07 L
DlOL
D09L
DI2L
Dll L
DI4L
Dl3L
PAL
DI5 L
GROUND
PBL

INIT L
+5V
INTRL
TEST POINT
DOOL
GROUND
D02L
DOl L
D04L
D03 L
D06L
D05 L
D08L
D07L
DlOL
D09L
DI2L
Dll L
DI4L
Dl3 L
PAL
DI5 L
PI*
PBL

*Pins used by parity control module.

API
AP2
ARI
AR2
ASI
AS2
ATl
AT2
AUl
AU2
AVl
AV2
BAl
BA2
BBI
BB2
BCI
BC2
BDI
BD2
BEl
BE2
BFI
BF2

Standard
Signal
GROUND
BBSYL
GROUND
SACKL
GROUND
NPRL
GROUND
BR7 L
NPGH
BR6L
BG7H
GROUND
BG6H
+5V
BG5H
GROUND
BR5 L
GROUND
GROUND
BR4L
GROUND
BG4H
ACLOL
DCLOL

Modified
Signal
PO*
BBSYL
BAT BACKUP +15 V
SACKL
BAT BACKUP +15 V
NPRL
GROUND
BR7L
+20V
BR6L
+20V
+20V
SPARE
+5V
SPARE
TEST POINT
BR5 L
GROUND
BAT BACKUP+5V
BR4L
INT SSYN*
PAR:DET*
ACLOL
DCLOL

Standard
Signal

Modified
Signal

BHI
BH2
BJI
BJ2
BKI
BK2
BLl
BL2
BMI
BM2
BNl
BN2
BPI
BP2
BRI
BR2
BSI
BS2
BTl
BT2
BUl
BU2
BVI
BV2

AOI L
AOOL
A03 L
A02L
A05 L
A04L
A07L
A06L
A09L
A08L
All L
AlOL
A13 L
Al2L
AI5 L
AI4L
AI7 L
AI6 L
GROUND
CIL
SSYNL
COL
MSYNL
GROUND

AOI L
AOOL
A03 L
A02L
A05 L
A04L
A07L
A06L
A09 L
A08L
All L
AlOL
A13 L
AI2 L
AI5 L
AI4L
AI7 L
AI6 L
GROUND
CI L
SSYNL
COL
MSYNL
-5V

CHAPTER 4
DETAILED HARDWARE DESCRIPTION

4.1 INTRODUCTION
The following paragraphs contain a detailed circuit description of the KD ll-E Central Processing
Unit (CPU), which is used in the PDP-ll/34 Computer. Segments of the CPU, shown in Figure 4-1,
are analyzed separately, using the block diagrams contained in this manual and the KDll-E circuit
schematics.
4.2 DATA PATH
4.2.1 General Description
The simplified KD 11-E data path consists of six function units, as shown in Figure 4-2. Circuit schematics Kl-l through KI-4 (D-CS-M7265-0-1) each contain one 4-bit slice of the data path. Table 4-1
briefly describes the function of each of the six function units.
Data flow through the data path is controlled, directly or indirectly, by the Control Store circuitry on
the control module (M7266). Each Control Store ROM location (microinstruction) generates a unique
set of outputs capable of controlling the data path elements and determining the ALU function to be
performed. Sequences of these ROM microinstructions are combined into microroutines, which perform the various PDP-ll instruction operations.

4-1

I.R.

B MODE (1:0)
~LOAD LR.

I.R.

AUX ALU
CONTROL

DECODE

(K2-5)

(K2-6)

f-T-o}
f-Lo

I--

BUT
DECODE

+:I

PSW MUX
(K1-1, Kl-4

~g~TROL
CLOCK

~l r~

(Kl-l, Kt-2,
KI-4)

(K2-8,K2-9)

BUS
CONTROL

.!--=-6

(Kl-l"KI-4

SPAM

LOAD
I-- PSW

~}CONTROL

D/R

(KI-9)

Plwvr A
PAR

(K 1-8)

(KI-7)

SR0
( Kl-8)

P!A
JDI
ROM
IRS
KT SR0-

A I-- ALU MODE

ALU
~}ALU S(3:00)
(Kt-t-Kl-4)l--c 1N
T

PAR-PORMUX ENAB-

~r.=
KT MUX
(KT-9)

-l + r

CONSTANTS

AMUX

CC LOGIC

(Kl-1-Kt-4)

(KHO, K2-5)

SS MUX

SEX- (Kl-1-Kl-4)

•

~
D/R

VBA
(KI-6)
PB A

CC DATA
SWAP-

L.-.l...o. SIGNALS

SR2

(KI-7)

(Kl-t-KI-4)

AMUX S(I:0)-

PDR

(K2-t, K2-2)

VIA

ERROR
LOGIC

SPM

~--~~

BLEG (1:0)

CONTROL
STORE ROM

CONTROL
STORE
REGISTER
(K2-8, K2-9)

{IO)

B MUX
(Kl-l+KI-4)

REG
CLK

PROC
CLK

i:J

B
REG
(Kl-I-KI-4)

PSW

(KI-5)

(K2-3,K2-7

\: 11tJ
N

- . CCDtTA

ALU
S (3:0)

(K2-6)

REQ
(Kt-I+KI-4)

(K2-5)

M-BRANCH
CONTROL

L -

•

+
H

UNIBUS

L
RELOCATE

BA
(Kl-6)
S

-.1

D/R

1 '"
v
11-3875

Figure 4-1

KDll-E Block Diagram

BUS DATA ....

I--- ENABLE DATA
SSMUX [15:00)

<II

::J

III

iii

::J

I - - SWAP
AUX
CONTROL -

I--BMODE 1

BXMODE 1 -

SWAP+SEX
MUX

PSWMUX

___ SEX

SP
ENAB-

BREG

BXREG
BX MODE 0 -

~L~~

I - - BMODE 0

SCRATCH PAD
MEMORY
(TRI STATE)

~~~

+1 - - - - . .

LOADPSW-

PSW

'--_____...Jt

___ AMUXSI

BLEGO-

___ AMUXSO

BLEG1_

BMUX

AMUX

lL-__

....~..z._..z._.L..

CONSTANTS
(VECTORS.

SP
15:00

ALUS3_
ALUS2-

!L...,

+ POR_.L.----..l-

KTMUX
~--~--~-1r-ENABLE

COMPARATOR

ALUC1N-

:= =:::

KTMUX
(TRISTATE)

VBA
6 12

ALU

~---BUSCONTROL

CO,Cl

VIRTUAL BUS
ADDRESS
(VBA)

t--.... LOAD
~ ACCESS CONTROL

VBA

ALUS1-

ErD

BITS ACFO, ACF 1

I~BA

ALUSO-

.6-12

ALU MODE -l.------,r-----...J

,PROCESSOR
•
MODES
PSW 15, 14, 13, 12

-...L._.L........

rL......

KT ERROR
LOGIC

ADDERS

ERRORS
CONDITION
CODE
LOGIC

I---- NON RESIDENT
1-4--- READ ONLY

1-+-+--- PAGE LENGTH

BA
6:17
VBA
0-5

DEFINITIONS:

SRO - MEMORY MANAGEMENT CONTROL REGISTER "0"
SR2 - MEMORY MANAGEMENT CONTROL REGISTER "2"
PAR - PAG ADDRESS REGISTER
PDR - PAGE DESCRIPTION REGISTER

RELOCATE

KT ERROR
DJSABLE MSYN
THEN TRAP
TO 250
11-4454

Figure 4-2 Simplified KDII-E Data Path

4-3

Table 4-1

Function Units of the KDll-E Data Path

Unit

FunctIon

Arithmetic Logic Unit (ALU)

The heart of the data path is the ALU, which is the logic element that manipulates the data. It is capable of performing 16
arithmetic or 16 logic (Boolean) operations on two 16-bit operands to produce a 16-bit result. The A input comes from either
the scratch pad memory or the memory management system; the
B input comes from the B leg. The ALU output is sent to the
AMUX.

ALU Multiplexer (AMUX)

The AMUX is a 4-to-l mUltiplexer that controls the
introduction of new data and the circulation of available data
through the data path. Input to the AMUX is both external
(from the Unibus data lines) and internal (from the ALU, PSW,
or constants). The AMUX output is sent to the SSMUX.

Processor Status Word Register
(PSW)

The PSW register is a 12-bit register that contains information
on the current processor priority, condition codes (C, V, Z, and
N) which indicate the results of the last instruction, a "trap" bit
(TBIT) which causes automatic traps after each fetch instruction used during program debugging, and both the current and
previous memory management modes (Kernel or User). PSW
input comes from the SSMUX or from condition code logic;
PSW output is sent to the AM UX.

Swap Sign Extend Multiplexer
(SSMUX)

This multiplexer controls the form in which data is output from,
or recirculated into, the data path. The SSMUX can pass the
data unchanged, swap the high and low bytes, sign-extend the
low byte into the entire word, or simultaneously swap high and
low bytes while sign-extending the high byte (which becomes the
new low byte) into the entire word. SSMUX input comes from
the AMUX. SSMUX output goes to either the rest of the computer system (via the Unibus), the other sections of the processor (the control section, via the Instruction register, and the
memory management system), or to other portions of the data
path (the PSW, the B leg, and the scratchpad memory).

B Leg

The B leg of the ALU consists of two 16-bit registers (B and BX)
and a 4-to-l multiplexer (BMUX). Both registers can shift left
or right independently, or together they can perform full 32-bit
shifts. The BMUX selects one of the four functions (BREG,
BXREG, + 1, + 16) and connects to the B input of the ALU.
The B leg is used to store operands for the ALU, to implement
rotate and shift instructions, and to implement Extended
Instruction Set (EIS) instructions. B leg input comes from the
SSMUX. B leg output goes to the B input of the ALU.

4-4

Table 4-1

Function Units of the KDll-E Data Path (Cont)

Unit

Function

Scratch pad Memory (SPM)

This random access memory can store sixteen 16-bit words in
eight processor-dedicated registers and eight general-purpose
(user available) registers. One of the general-purpose registers is
used as a stack pointer, another as the program counter. Input
to the scratchpad memory is from the SSMUX. Output, which
can be buffered and latched to enable reading from one address
and modifying another during the same cycle, goes to the A
input of the ALU and to the Virtual and Physical Bus Address
registers.

4.2.2 Arithmetic Logic Unit (ALU)
The ALU (Figure 4-3) is divided into four 4-bit slices (K1-1, K1-2, K1-3, and K1-4 each contain a
slice), with each slice consisting of one 4-bit ALU chip (74S181) and part of a Look-Ahead Carry
Generator chip (74S182).
ALU Inputs
The A input to each ALU chip comes from one of the scratchpad memory (SPM) registers or from the
KTM UX, as specified by the Control Store microinstruction being performed. (Refer to Paragraph
4.2.3 for details.) The B input comes from the B leg multiplexer (BMUX) logic, and can take the form
of the B register contents, the BX register contents, a constant O,a constant 1, or a constant 16. (Refer
to Paragraph 4.2.4 for details.)

4-5

,-------------------,
LOOK AHEAD CARRY GENERATOR
I
COUT
I
CIN
G
P
C
G
P
C
G
P

K2-8 ALU CIN L

I
I

I
•

A LEG
~0-15
(FROM SPM OR
r<'l
I
MEMORY
lSI
MANAGEMENT)
(J)

~~ACIN
I~

I ~~BS
lSI

B LEG

(J)

iii~ C
l-y'A

(K1-1l
F

ALU
M

r<'l
I

lSI

r;=>

(J)

fIn

iii

F
M

(J)

~
I

<;t(J)

---v

~B
'7
S

ALU

f--

~B
I

~ --,/
~

If)

iii

~0-15

P
G
(K1- 4)
F

ALU
S

I
I

M
10
I

~
(J)

iii

I
I
K2-8 ALU MODE H

If)

ALU S0- S3
(FROM K2-8)

~~ AC

G
P
(K 1-3)

f--

~~ AC

G
P
(K1-2)

ALU

<;t-

(J)

I iii

<;t-

~
I

I
I
I
I
TO AMUX

BITS 0-15

Kl-4
ALU
COUT H

r
~ J
___________________
' - SPECIFI ES
ALU FUNCTION

SPECIFIES
ALU MODE
(ARITHMETIC
OR LOGICAL)

I
I
11-3877

Figure 4-3

ALU Block Diagram

ALU Functions
The function performed by the ALU is controlled by the four Selection bits (S3, S2, SI, SO), the Mode
bit (M), and the Carry-In bit (CIN). Table 4-2 lists the ALU functions of the KDll-E and the corresponding bit patterns for the six control signals.
Table 4-2

ALU Functions and Control Signals

ALU Function

ZERO
A
A plus 1
A minus 1
A minus B
A
B
A plus B
A·B
A·B
A plus B plus 1
A plus A
B
A ~USA plus 1
A-fB

0
0
0
1
0
1
1

1
1
0
1
1
0
1
0

ALU Control Si2nals
CIN
S2
SI
SO
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1

1
0
0
1
1
1
1
0
1
1
0
0
0
0
1

1
0
0
1
0
1
0
1
1
0
0
0
1
0
0

0
0
0
1
0
0
0
1
0
0
0
1
0
0
0

M
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1

4.2.3 Scratchpad
The scratchpad consists of a random access memory that can store sixteen 16-bit words, and can be
used for various functions. Scratchpad operation is divided into four 4-bit slices, with Kl-l, Kl-2, Kl3, and KI-4 (D-CS-M7265-0-1) each containing one slice. The scratchpad address multiplexer circuitry
is shown on K2-4.
Data Input
Data to be written into the scratchpad is channeled from the SSMUX and clocked into the scratchpad
registers.
Addressing the Scratchpad
The address of the scratchpad memory register to be accessed is generated by the scratch pad address
multiplexer (SPAM), located on the control module (K2-4). Depending on the state of the select lines
to the SPAM, the source of the address can be any of the following:
1.
2.
3.
4.

The Control Store ROM (ROMSPA03:ROMSPAOO).
Instruction Register Source Field (IR08:IR06)
Instruction Register Destination Field (IR02:IROO)
Bus Address (PBA03:00)

4-7

Reading from the Scratchpad
If the Control Store circuitry forces a low on the Kl-lO ENAB OR L line at the beginning of a
machine cycle, the tristate outputs of the scratchpad will be enabled. Ninety or 120 nanoseconds after
the cycle begins (allows the scratch pad address to set up), K 1-5 TAP 30 H goes low. allowing data
stored in the selected scratchpad register to be latched in the output buffer SPI5:SPOO lines. This data
will continue to be read during the rest of the machine cycle. (See Figure 4-4.) Table 4-3 shows the
various scratchpad enabling configurations and the modes they select.

TAP 30 H
ENAB GR L

'"..'1- - - - MACHINE CYCLE ----.!-I
L-

1L-______--.1

---1r-

1L-______--=-______

SP WRITE L"I
PROC CLK L.J

READ SOURCE
WRITE INTO
~
SCRATCH PAD
DESIGNATION
REGISTER
SCRATCH PAD REGISTER
LATCH SCRATCH PAD
OUTPUT BUFFERS

A.J

TAP30H~

WJI

TAP 90 H.J
PROC CLK L

14---180 ------.I

NOTE:
Source and Designation Register do not
have to be the same. Register selected
may be changed (See SPA Mux description)
for second half of machine cycle.
11-3878

Figure 4-4 Scratchpad Timing

Table 4-3
OD

CLK

L
X

X
L
X
X
X

X
X
X

X
H
L
H

H
H

Scratchpad Enabling Configurations and Modes
Outputs

OS Mode
OUTPUT STORE
WRITE DATA
READ DATA
OUTPUT STORE
OUTPUT DISABLE

4-8

Data from last addressed location
Data being written (ifOD = L and OS = H)
Data stored in addressed location
High-impedance state
High-impedance state

Latching of Outputs
When the aD (pin 12) and as (pin 13) inputs are both low, the data being read from the scratch pad
that is addressed is latched into the buffers on the output of scratchpad memory (SPI5-00). Once those
outputs are stabilized, they are not affected by any modifications to the scratchpad memory address
lines for the remainder of the cycle.
Clocking the Scratchpad
The REG CLK H clock signal clocks data from the SSMUX lines into the scratchpad register and
writes that data into scratch pad memory. TAP 30 H unasserted, placing a high at the as input (pin 13)
of the scratchpad, is all that is required for a read operation. Both a read and a write can take place
during the same machine cycle. Figure 4-4 shows the scratchpad timing for one machine cycle.
Scratchpad Address Multiplexer (SPAM)
The SPAM (Figure 4-5) generates the four address signals that select the desired scratchpad register, or
word. The SPAM (shown in print K2-4 of D-CS-M7266-0-1) consists of two 74S153 duaI4-line-to-lline data multiplexers, or a total of four 4-to-l multiplexers, all with a common strobe input signal
(GND) and common address input signals (SI and SO). Four data input sources are connected so that,
when the SPAM is addressed and strobed, it generates one 4-bit output, selected from one of the four
sources. Table 4-4 lists the sources of SPAM input data and the address input signal configurations
that select them.

PBA L . -_ _ _ _. , /

lR-SRC

'------,/

lR-DST L . -_ _ _ _. , /

(K2-4)

SPAM

TO
SPM

74S153

CONTROL
STORE ROM L . -_ _ _ _.,,,
'---~---'

K2-9 SPA DST
SEL (1:0) (1) H

K2-9 SPA SRC
SEL (1:0) (1) H

(K2-4)

F I------J

74S157

KI-5TAP30H

Figure 4-5

NOTE:
SPA = 6; forced to 16 for
user mode ROM, lR-SRC,
lR-DST.
11-3880

Scratchpad Address Multiplexer (SPAM)

4-9

Table 4·4 SPAM Input Data Sources
SPAM
Input

Source

Source
Print

Source Operand
Register Selection

Instruction Register Bits 08:06

K2·5

Destination Operand
Register Selection

Instruction Register Bits 02:00

K2·5

General.Purpose Register
Selection from Console

ROM SPA Bits 03:00

K2·10

PBA Bits 03:00

Kl·6

Function

Scratchpad Memory Organization
The scratchpad memory (SPM) is a 16-word-by-16-bit random access read/write memory composed
of four 16-word-by-4-bit bipolar (85S68) memory units (Kl-l through KI-4). The 16-word-by-16-bit
organization of this memory provides 16 storage registers that are utilized as shown in Table 4-5.
Table 4-5
Register
Number

SPM Register Utilization

Description

RO
Rl
R2 ~ General-Purpose Registers
R3
R4
R5 •
R6

(Processor Stack Pointer)

(Program Counter)

RIO

Temporary Storage

Rll

Unused

R12

Temporary Storage

R13

Temporary Storage

R14

Unused

R15

Temporary Storage

R16

Processor Stack Pointer
(Memory Management User Mode)

R17

Temporary Storage

4·10

Scratchpad Outputs

Data outputs from the scratch pad are fed to the ALU as the A leg input and to the memory management system.
4.2.4 B Leg
The B leg (Figure 4-6) of the ALU consists of three components: the B register, the BX register, and the
B leg multiplexer (BMUX). Each of these components is divided into four 4-bit slices, with circuit
schematic prints KI-I, KI-2, KI-3, and KI-4 each containing a slice. Data from the SSMUX can be
clocked into either register. Register contents can be shifted either individually as 16-bit words or
together as a double (32-bit) word.

B MODE 0
B MODE 01

51 50 5R

HOLD

B
REG.
'--(Kl·l+Kl-4)

ClK

5HIFT IN B

B MODE 00

lOAD

+1-3
+16 -

~1 MUX

BIT0

BMODE 011

(Kl.1-Kl-=)

~O51

~ TO
AlC

IVI

BlEG01

51 50 5R

SHIFT
RIGHT
SHIFT
lEFT

74194

PROC. ClK

FROM
55
MUX

LEG011J

BX
REG.

(Kl-1+K1-4)

ClK

I
SHIFT IN BX

SL\
51

sf/J

HOLD

l
H

H SHIFT
RIGHT
SHIFT
l lEFT

lOAD
11- 3881

Figure 4-6 B Leg Block Diagram

4-11

B Register
The B register (B REG) is a general-purpose storage register (Figure 4-7) on the B leg of the ALU,
consisting of four 4-bit bidirectional universal shift registers (74194). The mode control lines of the
four 4-bit registers are connected in parallel, so that the signals K2-8 B MODE 00 Land K2-8 B
MODE 01 L select the function that will be performed by the B register when clocked by Kl-5 PROC
CLK L. Table 4-6 shows the various functions· and the shift configurations that select them.

K2-8 BMODE 00 l }
K2-8 BMODE

{---. 1
SI S0 SR

BITS 12-15

B REG
(KI-4)
74194

BITSI2~
v

BIT 12

ClK

~{---. ! •
BITS 8-11

SI S0 SR

BIT 11

B REG
(KI-3)
74194

BITS 8-11

ClK

K-l0 SHIFT IN 07 H -

TO BMUX

~{~
FROM SS MUX

BITS 4-7

SI S0 SR

BIT 7

B REG
(KI-2)
"14194

BITS 4-7

-V

ClK
KI-5 PROC ClK l

BIT 4

-f

I---

{=il r
SI S0 SR

BITS 0-3

B REG
(KI-1l
74194

-"
-V

ClK

BIT 3
SI S0 FUNCTION
BITS 0-3

HOLD

SHIFT
HOLD
SHIFT
lEFT

lOAD

KI-IOSHIFT IN BH
11- 3882

Figure 4-7

BREG Block Diagram

4-12

Table 4-6

Band BX Register Enabling Configurations and Modes

Mode

Hold

Contents of register do not change.

Shift Right

Contents are shifted right one bit.

Shift Left

Contents are shifted left one bit.

Parallel Load

Data from SSMUX is loaded into B register
and appears at output.

Function (when PROC CLK L goes high)

The B register can be shifted as an 8-bit byte or a 16-bit word. The signal K 1-10 SHIFT IN B determines what is shifted into the B register. When the contents of this register and the BX register are
combined into a 32-bit word, the B register contains the upper 16 bits.
BX Register
The BX register (BX REG) is a general-purpose storage register (Figure 4-8) on the B leg of the ALU,
consisting of four 4-bit bidirectional universal shift registers (74194), similar to the B register. The
mode control lines of the four 4-bit registers are connected in parallel, so that the signals K2-8 BX
MODE 00 Land K2-8 BX MODE 01 L select the function to be performed when the BX REG is
clocked by K 1-5 PROC CLK L. The BX register can be shifted as a 16-bit word or, in conjunction with
the B register, as a 32-bit word. In the latter case, the BX register contains the lower 16 bits of the 32bit word, and the shift right (SR) input of the most significant register in the BX register is connected
to the zero bit of the B register. Table 4-6 shows the various functions and the shift configurations of
K2-8 BX MODE 00 Land K2-8 BX MODE 01 L that select them.
B Leg Multiplexer (BMUX)
The BMUX (Figure 4-9) consists of three 2-to-ll multiplexers and a 4-to-l multiplexer, and is used to
select the proper input to be used as an operand on the B leg of the ALU, The BMUX can select the
contents of either the B REG or BX REG, or can act as a constant generator (constants 16, 1, or 0),
depending on the configuration of signals K2-8 B LEG 00 Hand B LEG 01 H (Table 4-7) and the state
of K2-4 DISAB MSYN + 1 L.

4-13

Kl-1 BREG 00 (1) H

r-{
S1

BITS 12-15

KI-5 PROC ClK l

S0 SR

ex REG

...

(K1- 4 )
74194

BITS 12-15

ClK

~{~ ~.
S1

BITS 8-11

S0 SR

BX REG
(Kl-3)
74194

-)
V

ClK

K FROM SS MUX

~{~
S1

BITS 4-7

K2-8 BX MODE 01 l
K2-8 ex MODE 00 l

BIT 12

-vi

BIT 11
"BITS 8~

BIT 8

S0 SR

BX REG
(K1-2)
74194

TO BMUX

BIT 7
"-

BITS 4 $
BIT 4

ClK

L-

{=il •

=}-

51 S0 5R

BITS 0-3

BX REG
(Kl-ll
74194

ClK

KHO SHIFT IN BX H

BIT 3
BITS 0-3

50 FUNCTION

HOLD

SHIFT
RIGHT
SHIFT
lEFT

lOAD
11-3883

Figure 4-8

BX REG Block Diagram

4-14

(KI-4)

BIT~ B

FROM BX RE GI

B MUX
F BITS 12-15
74157

112-15; A
STB

9
(KI-3)
B
BIT~
-v

B MUX
F BITS 8-11
74157

I 8-1f) A
BiTs
r---

FROM B RE G

K2-8 BLEG 00 H K2-8 BLEG 01 H -

f--f---

STB

TO ALU

I
(Kl -2)

I- --..

BI~

B MUX
F BITS 4-7

l---

BIT 3

~
~
K2-4 DISABLE BIT 0
MSYN + 1 L
BIT 3

BITS

"'-

STB

JID:ii 1"'-

BLEG BLEG
01
00 FUNCTION
L
L a-REG
H BX-REG
L
H
16
L
H
H 1

f---

K2-8 AUX
CONTROL (1) H~
BIT 0

r---

'--

74157

------

f---

( K1-1l

~ C B MUX

f---

F BITS 0-3

-------1\., B

BITS O--t;

74153

BITS o - t A
SI

1
11-3884

Figure 4-9

BMUX Block Diagram

4-15

Table 4-7

BMUX Enabling Configurations and Modes

B Leg
01

BLeg
00

Function

Description

BREG

Passes data from the B register to the BMUX outputs. This is the most common configuration.

BXREG

Passes data from the BX register to the BMUX
outputs. This is used principally for EIS
instructions.

+16

Forces the constant + 16 into the BMUX outputs
to preset a counter that is used for EIS instructions.

Forces the constant + 1 into the BMUX outputs
during operations in which the contents of a register are being incremented or decremented by two.

By asserting DISABLE MSYN + 1 L, this configuration forces the constant 0 into the BMUX
outputs during operations in which the contents of
a register are being incremented or decremented by
one. (The signal K2-S AL U CIN L to the AL U
from the control module provides the one.)

B Leg Shift Capabilities
Each of the four shift registers (74194) that make up each register (B REG and BX REG) has the
capability of being shifted left or right, as indicated in Table 4-6 and Figure 4-10. The B register can be
shifted as an S-bit byte or a 16-bit word; the BX register can be shifted as a 16-bit word or, in conjunction with the B register, as a 32-bit word.
Byte Shifts
If the mode control lines (K2-8 B MODE 00 Land K2-S B MODE 01 L) specify a shift left, B REG
15:00 are shifted one position toward the most significant bit at the clock pulse Kl-5 PROC CLK L
going high. The signal K1-10 SHIFT IN B H is shifted into bit 00 via the SL input. This signal is
generated by the SHIFT MUX (El17 on print K1-10) as a function of the select signals K2-8 SHIFT
MUX 01 Land K2-8 SHIFT MUX 00 L. The shift right input to B REG bits 07:04 comes from the
BYTE MUX (E106 on print K1-1O). Assertion of K2-5 BYTE L (indicating a byte instruction) causes
bit 07 of the B REG to be loaded directly by K2-5 SERIAL SHIFT H; if K2-5 BYTE L is high,
however, B REG bit 07 is loaded from B REG OS. B REG bit 15 is loaded from K1-10 SHIFT IN B H
during a shift right (just as B REG bit 00 is loaded during a shift left), and can be loaded with itself,
K2-5 SERIAL SHIFT H, ground, or BX REG bit 15, depending on the SHIFT MUX. For a shift
right, BX REG bits 15:01 are shifted one position toward the least significant bit, and BX REG bit 15
is loaded with B REG bit 00. Thus, for all right shifts, the BX REG acts as the low-order 16 bits of a
32-bit word made up ofB REG and BX REG. For a shift left, BX REG bits 15:00 are shifted one bit
position toward the most significant bit. BX REG bit 00 is loaded with the signal K1-10 SHIFT IN BX
H, which is generated by the SHIFT MUX. Depending on the configuration of the SHIFT MUX
control lines K2-S SHIFT MUX 00 Land K2-S SHIFf MUX 01 L, the BX REG may be loaded with
any of four possible inputs: Kl-4 ALU COUT H, the output of the EIS overflow detection logic (E98
on print K1-1O), ONE, and ZERO.

4-16

(Kl -10)
B
BYTE MUX
F~-4---+------~

r--+-----i A

K2-5 BYTE L

Kl-10 SHIFT INB H

/' f----I---------'

(Kl-10)

C(2I

K
~2~-~5~S~E_R_IA~L~S_H_IF~T_H____~~__~B0

SHIFT
A0 MUX
741941

~-.-'

(Kl-IO)
+30
Cl
EIS
Fl
OVERFLOW
DETECTION I---------IBI
LOGIC
At
ENAB
CLR
L......::,S.;...1--:;S:;:.0-1

K2-8 ENAB OVX L

I
I
I
I
I

Kl-4 ALU CONT H
K 2-8 SHIFT

K2-5 LOAD IR H

MUX 01 L

K2-2 PROC.INIT L

K2-8 SHIFT MUX 00L
Kl-lO SHIFT IN BX H

/'---+-----'
11 - 3885

Figure 4-10

B Leg Shift Logic

4-17

Specific Shift and Rotate Operations
The shifting requirements for the ASL, ASR, ROL, ROR, ASH, and ASHC instructions are described
briefly below.
I.

Arithmetic Shift Left (ASL) - Shifts all bits of the destination left one place. The low-order
bit is loaded with a O. The C-bit of the status word is loaded from the high-order bit of the
destination. ASL performs a signed multiplication of the destination by 2, with overflow
indication.

Arithmetic Shift Right (ASR) - Shifts all bits of the destination right one place. The highorder bit is duplicated. The C-bit is loaded from the low-order bit of the destination. ASR
performs signed division of the destination by two.

Rotate Left (ROL or ROLB, depending on whether a word or byte operation) - Rotates all
bits of the destination left one place. The high-order bit is loaded into the C-bit of the status
word, and the previous contents of the C-bit are loaded into the low-order bit of the
destination.

Rotate Right (ROR or RORB) - Rotates all bits of the destination right one place. The loworder bit is loaded into the C-bit, and the previous contents of the C-bit are loaded into the
high-order bit of the destination.

Arithmetic Shift (ASH) - Shifts the contents of the register right or left the number of times
specified by the source operand. The shift count is taken as the low-order six bits of the
source operand. This number ranges from -32 to +31. Negative is a right shift and positive
is a left shift.

Arithmetic Shift Combined (ASHC) - Treats the contents of the register and the register
ORed with one as one 32-bit word. Rv 1 (bits 15:00) and R (bits 31: 16) are shifted right or left
the number of times specified by the shift count. The shift count is taken as the low-order six
bits of the source operand. This number ranges from -32 to +31. Negative is a right shift
and positive is a left shift. (When the register chosen is an odd number, the register and the
register ORed with one are the same. In this case, the right shift becomes a rotate. The 16-bit
word is rotated right the number of bits specified by the shift count.)
NOTE
When R is an even-numbered register, Rv 1 will be
the next highest register. If R is an odd-numbered
register, Rv 1 will be the same register (e.g., if R =
R4, then Rvl = R5; if R = R5, then Rvl = R5).

4-18

BMUX Operation
Three 2-to-l multiplexers (74157s) are used to switch B leg bits 15:04. Their select lines are tied in
parallel with each other and with the SO line of the 4-to-l mUltiplexer (two 74153s) used to switch B leg
bits 03:00. The SO line is signal K2-8 B LEG 00 H. Signal K2-8 B LEG 01 H is connected to the enable
lines of the 2-to-l multiplexers and to the S 1 line of the 4-to-l multiplexer. Table 4-7 describes the
enabling configurations and modes for these two select signals, which are logically determined as
follows:
I.

If both K2-8 B LEG 00 Hand K2-8 B LEG 01 H are low, the 4-to-l multiplexer (E8 and E5
on print Kl-l) selects the A input and the 2-to-l multiplexers (E28 on print KI-2, E18 on
KI-3, and E38 on KI-4) select the A inputs; the data from the B REG is switched to the
BMUX output.

If K2-8 B LEG 01 H is low and K2-8 B LEG 00 H is high, the 4-to-l multiplexer selects
input B, the 2-to-l multiplexers remain enabled, and the data from the BX REG is switched
to the BMUX output.

If K2-8 B LEG 01 H is high and K2-8 B LEG 00 H is low, the 2-to-l multiplexers are not
enabled. The 4-to-l multiplexer selects input C, where bit 0 is low and bits 03:01 are connected to K2-8 AUX CONTROL (1) L un asserted, generating a + 16 constant to the B leg.

If both K2-8 B LEG 01 Hand K2-8 B LEG 00 H are high, the 2-to-l multiplexers are still
disabled and the 4-to-l multiplexer selects input D, where bits 03:01 are grounded and bit 00
is connected to K2-4 DISABLE MSYN + 1 L un asserted, generating a constant of + 1 to the
B leg.

If, in 4 above, K2-4 DISABLE MSYN + 1 L is asserted, a constant of 0 is generated to the B
leg.

Constants + 16, + 1, and 0
The purpose of generating the constants + 1 and 0 on the B leg input of the ALU is to aid the processor
to perform autoincrement and autodecrement operations. During either operation, if a word instruction is being performed, the specified register is incremented or decremented by two; if a byte instruction is being performed, the register is incremented or decremented only by one. The actual AL U
operation is:
RESULT = A LEG DATA + B LEG DATA + ALU eIN.
The ALU always uses the K2-8 ALU CIN L signal to increment or decrement the A leg input by one;
thus, the B leg input must provide the constant + 1 or 0 to obtain the correct autoincrement or autodecrement result for both byte and word instructions. A B leg constant of + 1 is generated by enabling
the least significant bit of the BMUX output (bit 00) and forcing all other bits (15:01) to O. To generate
a constant 0, even bit 00 is cleared. The actual constant generated is defined by the state of the K2-4
DISABLE MSYN + 1 L signal, which is determined by the Control Store.

4-19

4.2.5 ALU Multiplexer (AMUX)
The AMUX (Figure 4-11) consists of three 4-to-l multiplexers (74S153s) and one 2-to-l multiplexer
(74S157), each one dedicated to a 4-bit slice of the AMUX. The 2-to-l mUltiplexer (E14 on print KI-3)
switches AMUX bits 11 :08 according to the state of the STB and SO inputs. If the STB input is high,
the multiplexer is disabled, and the output is forced low. If the STB input is low, the multiplexer is
enabled, and the output depends on the state of the SO input and the appropriate data input. Thus, if
the SO input is low, the A data input will be gated through to the AMUX output; ifthe SO input is high,
the B data input will be gated through. Because the 4-to-l multiplexer does not have an enable input,
the output always follows one of the inputs, corresponding to the binary value of select lines S 1 and SO
(Kl-IO AMUX SI Hand Kl-IO AMUX SO H, respectively), as follows:
1.

Unibus Data Function - If both S 1 and SO are low (binary 0), the 4-to-l multiplexers select
input A and the 2-to-l multiplexer selects input A. Thus, each 4-bit slice of the AMUX
switches Unibus data into the data path.

Constant's Function - Certain operations require the introduction of specific numbers into
the data path. (For example, the data path must generate a vector of 24 for a power-fail trap,
or 114 for a parity trap.) Access to these and other numbers is facilitated by storing certain
constants in a read-only memory and presenting them to the constant's input of the AMUX.
If SI is low and SO is high (binary 1), the 4-to-l multiplexers select input B (the constant's
input). Bits 11 :08, which are controlled by the 2-to-l multiplexer, are not used.

ALU Input - If S 1 is high and SO is low (binary 2), the 4-to-l multiplexers select ALU inputs
(input C) and the 2-to-l multiplexer is enabled, also selecting ALU inputs, so that the ALU
lines are selected for all 16 bits.

PSW Inputs - If both SI and SO are high (binary 3), the 4-to-l multiplexers select the PSW
input (input D). The 2-to-l multiplexer is disabled, as bits 11:08 are not used.

4.2.6 Processor Status Word
The Processor Status Word (PSW) register contains information on the current and previous memory
management mode, the current processor priority, a processor trap for debugging, and the condition
code results of the previous operation. The PSW bit assignments and uses are shown in Table 4-8.

4-20

11..-____----. ~ D

~C
-,/

GND

r-v

IL-_ _ __

(K1-4)

AMUX
115:12) F BITS12.15

I-

rvL.::Srll_::-;Sf/)=__----.
(KI-3)

ALU

1'---,,......,.--......

f---vI

AMUX
(11: OS) t---L--'-...J
F BITSS.tl

I-

Sf/)
K1-10 AMUX
s0 H
Kt-l0AMUX
SI H

L..

.--

AMUX
~ B(07:04t BITS4·7

I-

~L
r-

.....

I-

KTOSSMUX

(KI-2)

'--

CONSTANTS

STB

AMUX
S~ Sf/)

FUNCTION

UNIBUS

L
H

H CONSTANT
L
ALU

PSW

IV:S~I;~S~t)~H

I ~

(Kl-l)

'--_....J~

(03: 00)

~ D AMUX

'--_ _ _

...J~

F BITS 0.3

'--_ _ _--,./... B

...

UNIBUS
DATA

I'-------,=l ~1

Sf/)

~-C~
11-3886

Figure 4-11

AM UX Block Diagram

4-21

Table 4-8

Processor Status Word Register Bit Assignments

PSWBit

Name

Use

15: 14

Memory Management
Current Mode

Contain the current memory management modes.

13: 12

Memory Management
Previous Mode

Contain the previous memory management modes.

11:08

Unused

07:05

Priority

Set the processor priority.

Trace

When this bit is set, the processor traps to the trace
vector. Used for program debugging.

Set when the result of the last data manipulation is
negative.

Set when the result of the last data manipulation is
zero.

Set when the result of the last data manipulation
produces an overflow.

Set when the result of the last data manipulation
produces a carry from the most significant bit.

The PSW (Figure 4-12) is a 12-bit register composed of three quad D-type flip-flops (74175s) and one
separate D-type latch. The first of these (E95 on print Kl-l) stores the condition code bits (N, Z, V,
and C), and derives its input from the PSW MUX, a quad 2-line-to-l-line multiplexer (E96 on Kl-1)
according to the state of the SO select line. When high, SO selects the B inputs (SSMUX bits 03:00);
when low, SO selects the A inputs, which come from the condition code logic (print Kl-lO). The
selected inputs are passed to the f-outputs of the multiplexer and into the PSW.

A second quad D-type flip-flop (E97 on KI-2) is used to store the three KDll-E processor priority
bits, which it obtains from SSMUX bits 07:05. A separate 74S74 (E107 on Kl-2) is needed to store the
Trace Trap flag (T-bit), which can be loaded from the KI-2 SSMUX 04 H line.
The third quad D-type flip-flop (E80 on KI-4) stores the bits containing the current and previous
status of the memory management mode. SSMUX bits 15 and 14 provide the input for PSW bits 15
and 14, which are then rerouted through a quad 2-line-to-l-line multiplexer (E90 on KI-4) and multiplexed with SSMUX bits 13 and 12 according to the state of the SO select signal [K2-9 FORCE
KERNEL (1) H] to provide the input for PSW bits 13 and 12. Thus, PSW bits 15 and 14 reflect the
current status of the memory management mode, while PSW bits 13 and 12 indicate the previous
status.
All flip-flops in the PSW are clocked, directly or indirectly, by clocking signal Kl-5 REG CLK L. All
of the enabling signals come from the Control Store.

4-22

SS MUX (15: 14)

PSW (15:14)

.")

I
(K1-4)

PSWU5:12) MEM.MGMNT MODE

c)B

PSW MUX
SS MUX (15:12)

c) A
STB
FORCE KERNAl (I) H
)-/.

(KI-4)
BITS (15:14)

BITS (13:12)
ClR
ClK

lOAD H PSW

(KI-2)

SS MUX (07: 05 )

PSW{o7:05)
PRIORITY

-V

(REG. ClK)'
[ (lOAD PSW lOW)+{ lOAD PSW 12 -Ie. )]

TO
AMUX

ClK

ClR

--.5l
(KI-2)

SS MUX 04

D
PSW04

(REG ClK)· (lOADPSW)

T- BIT

ClK
ClR

Y
SS MUX (03:00)

(Kl-1 )
c)B
PSW MUX

CC lOGIC

(Kl:1 )

c)~TB

C,V,N,Z

ClR

PSW{03:00)

ClK

(AUX CONTROL HlOAD PSW lOW)
PROC INIT l
(REG ClK ). [( lOAD PSW) +
(lOAD PSW lOW)+ (lOAD CC)]
11-3887

Figure 4-12

Processor Status Word

4-23

4.3 CONDITION CODES
The logic necessary for determining the condition codes is shown on sheets KI-IO and K2·5, and can
be subdivided into three parts, each of which is discussed in some detail in this section. Constraints for
each condition code bit are shown in the instruction set specifications (Chapter 2).
4.3.1 Instruction Categorizing ROM
The Categorizing ROM (E67 on sheet K2-5) decodes the instructions in the IR and categorizes them
into eight groups, based on their effect on the carry and overflow condition codes. These groups are as
follows:
Group

Instructions

I
2
3
4

MaY, BIT, BIS, BIC, and non-PDP-II instructions
INC, DEC
CLR, TST, SWAB
ADD,ADC
NEG, CMP, COM
SUB, SBC
Rotate instructions
Unused

5
6

7
8

Three of the four outputs of the Categorizing ROM are used to provide a binary representation of one
of the above instruction categories for the C and Y Decode ROM (EI05 on KI-IO). The fourth output
(K2-5 BYTE L) decodes the fact that the instruction in the IR is a byte instruction and is fed to the
select input of the BYTE MUX (EI06 on KI-IO).
4.3.2 Byte Multiplexer (BYTE MUX)
The BYTE MUX (E106 on KI-I0) is a quad 2-line-to-l-line multiplexer (74S157) that determines the
N condition code bit and the K 1-10 SHIFT IN 07 H signal for the B REG (Figure 4-13). A single select
input (K2-5 BYTE L) selects the A inputs when a byte operation is performed, and the B inputs when
the operation is not a byte.

Kl-3 BREG 08 (llH

(KHO)
f0
BQl

K2-5 SERIAL SHIFT H

Kl-4 ALU 15 H

Kl-2 ALU 07 H

K1-4 SP 15 (1) H

BYTE
MUX
B2 (El06)

KI-2 SP07 (11 H

K1-4 BLEG 15 H

Kl-10 SHIFT IN 07 H

Kl-10 CC N H

745157 f 2

}

K1 -2 BLEG 07 H

TO C + V DECODER
ROM

f3
S0

=
K2-5 BYTE L
11-3888

Figure 4-13

Byte MUltiplexer
4-24

Output signal KI-I0 CC N H assumes the level of KI-4 ALU IS H when the instruction being performed is a word operation, and the level of KI-2 ALU 07 H when the instruction is a byte operation.
Byte operations may be performed on either the high or low bytes of the input word, depending on
whether the processor microcode has already swapped bytes before the condition codes are detected.
F<;Jf shift right operations, the KI-1O SHIFT IN 07 H output assumes the level of the Kl-3 BREG 08
(1) H input when a word instruction is performed, and the level of the K2-S SERIAL SHIFT H output
of the ROT/SHFT ROM (E61 on print K2-S) for a byte operation. The diagrams in Figure 4-14
indicate the operations performed by various instructions.
4.3.3 C and V Decode ROM
The C and V Decode ROM (E1OS on K1-1O) determines the values of the carry and overflow condition
code bits as a function of the instruction being performed (Figure 4-1S). Inputs to this ROM come
from the ROT SHIFT ROM (E61 on K2-S), the PSW [K1-1 CBIT (1) H], the BYTE MUX, and the
Categorizing ROM (E67 on K2-S). Outputs K1-10 CC V Hand K1-1O CC C H are fed via the PSW
M UX (E96 on K 1-1) to the PSW register.
4.3.4 Condition Code Signal CC Z H
Each 4-bit slice of the data path contains an ALU output via a gate (type 881S) reflecting whether all
four of the bits in that slice are ZERO. If the instruction being performed is a byte operation, condition
code signal K 1-10 CC Z H assumes the combined state of signals K1-1 0-3=0 Hand Kl-2 4-7=0 H;
for a word operation, K 1-10 CC Z H assumes the combined state of those signals together with Kl-3
8-11=0 Hand KI-4 12-1S=0 H. Thus, K1-10 CC Z H is asserted if bits 00 through 07 = 0 for a byte
operation and if bits 00 through IS = 0 for a word operation. Assertion of K2-S BYTE L selects byte
operation.
4.4 UNIBUS ADDRESS AND DATA INTERFACE
4.4.1 Unibus Drivers and Receivers
Standard bus transceiver circuits (type 8641) are used to interface the processor data path to the
Unibus address (BUS AOO:A1S) and data (BUS Doo:D1S) lines. These circuits are shown on prints
KI-1 through KI-4, and on KI-6. Figure 4-16 shows the logic diagram for an 8641.
4.4.2 Unibus Address Generation Circuitry
A unique feature of the KDll-E is that KT11-D equivalent memory management capability is built
into the 2-board processor. During Unibus transfers, virtual bus addresses are obtained from the
scratchpad memory (SPM) and the Physical Bus Address (PBA) register, if relocation is not enabled,
and latched in the Virtual Bus Address (VBA) register shown on print Kl-6. Figure 4-17 shows the
actual VBA clock timing, while Figure 4-18 shows Unibus address logic in block diagram form.
If the memory management circuit is not enabled (Kl-8 RELOCATE H is not asserted), the address

that was clocked into the Physical Bus Address register is used as address data for the 8641 transceivers
and driven onto the Unibus address lines.
When the memory management circuit is enabled (Kl-8 RELOCATE H asserted), a selected relocation constant (detailed description in Paragraph 4.12) is added to the contents of the VBA before it is
latched into the BA and driven onto the Unibus.

4-2S

ROR
RORB
WORD:

~15

L-~~________________________________~to

BYTE:

I I
15f
ROL
ROLB
WORD:

CVj15
BYTE:

I I

ntlf8 I71

h;r"---,---,-I:ciJ_ODc,-D--11--,---,-1
15

ASR
ASRB
WORD:

[j;1

1--------'-

VEN
1 E0

------I- c 1---------'

BYTE:

~rl
I
I
1
~
L:!J-'----'-E-V..LE-N-1A-D-ORi-E-SS-'---1--,!O

I
1
l§---''--.l..-OO..LO---lAO-O-REi-S-S-'---1-"'''8
ASL
ASLB
WORD:

~~~---"--.l..-..L~~~~~---"--.l..-..L~~r-O
0
~

BYTE;

~~~~~-L~~I__~~O~~~~~I~I__~~I~~~O
15

ODD ADDRESS

EVEN ADDRESS

11- 39~2

Figure 4-14

Rotate Instructions

4-26

+5V
K2 - 6 I R DECODE (1) L
K2-5 BYTE H

( K2-5)

K2-5 BYTE L

K2-5 I R 15 ( I) H
K2-5 IR 14 (1) H

K2-5 CC CODE 02 H

K2-5 IR 13 (1) H

K2-5 CC CODE 01 H
CATEGORIZING
K2 -5 CC CODE 00 H
ROM

K2-5 IR 12 (1) H
K2-5 IR 10 (1) H

FR~

K2-5 IR 09 (1) H

BYTE MUX

K2-5 IR 08 (1) H

( K1-10)

C+V
DECODE
ROM

Kl-1O CCV H

{
KHO CC C H

K2-5IR 07 (1) H
K2-5 ROT CBIT (1) H
K2-5 IR 06 (1) H
E67

KH CBIT (1) H
El05
11-3889

Figure 4-15 C and R Decode ROM

UNIBUS LINES

11-3891

Figure 4-16 Unibus Transceiver

4-27

LOAD VBA
INPUT TO
DELAY

LOAD VBA

TAP 30 H
TAP 90 H
TAP 120 H
PROC CLK L

-U

::::;U;::30ns

1--180ns-+-240 n s - l
•

SHORT CYCLE

LONG CYCLE11-3900

Figure 4-17

FROM PAR

Processor Clock Cycle Timing

(K1-6)

PAGE ADDRESS FI ElD

ADDER
BITS 17-6

(K1-6)
SA

VSA

(K1-6)
BITS 17-6

DRIVER

ClK
BITS 17-

FROM
B;.:.IT..:S_1;.;.7_-.:.6_ _ _.-J
DATA PATHIL-.-_ _ _ _ _ _ _ _--._ _r--r--r..::.
Kl-8 RELOCATE H
K1-5 lOAD BAR l

(K1-6)

BITS 5-0

DRI VER

TO
UNIBUS

BIT15~BIT17
BIT 14
BIT 13

BIT 16
K2-1 ENAB ADDRS l
11-3892

Figure 4-18

Unibus Address Logic Block Diagram

4-28

4.4.3 Internal Address Decoder
The receiver half of the bus transceivers continually monitors the Unibus address lines. If the processor
is running (HALT RQST L or BUS SACK L are not asserted), these transceivers allow the Internal
Address Decoder circuit (print K 1-1 0) to detect transfers to or from the PSW and memory management registers. Note, however, that the CPU does not allow access to its general registers through their
Unibus addresses while it is running.
While the processor is halted (BUS SACK L is asserted), this decoder circuit enables data transfers
between CPU registers and Unibus peripheral devices. A list of these CPU registers and their Unibus
addresses is shown below; the registers are discussed in Paragraph 4.12.
PSW
RO
Rl
R2
R3
R4
R5
R6
R7

4.5

777776
777700
777701
777702
777703
777704
777705
777706
777707

RIO
R II
RI2
R13
R14
R15
R16
R17

777710
777711
777712
777713
777714
777715
777716
777717

INSTRUCTION DECODING

4.5.1 General Description
Two methods are used to control instruction decoding, one using micro routine selection and the other
using auxiliary ALU control. Dual control is required because of the large number of instructions that
require source/destination calculations. Auxiliary ALU control is evoked whenever the microcode
executes the action X = Y OP B as a result of a specific instruction.
There are two prerequisites to a thorough understanding of the instruction decoding procedure. One is
a knowledge of the microbranching process, and the other is a knowledge of the PDP-II instruction
format.
The following facts pertain to the KDll-E/PDP-ll instruction set:
1.

In general, the PDP-ll operation code is variable from 4 to 16 bits.

A number of instructions require two address calculations; an even larger number require
only one address calculation. There are also a number of instructions that require address
calculations, but do not operate on data.

All op codes that are not implemented in the KD ll-E processor must be trapped.

There are illegal combinations of instructions and address modes that must be trapped.

There exists a list of exceptions in the execution of instructions having to do with both the
treatment of data and the setting of condition codes in the processor status word.

4-29

4.5.2 Instruction Register
Each PDP-II instruction obtained from memory is stored in the 16-bit instruction register (lR). This
register consists of three 6-bit D-type 74174 registers (E55, E65, and E66 on K2-5) and one 74S74 Dtype flip-flop (E33). The purpose of the IR is to store the instruction for the complete instruction cycle
so that the IR Decode and Auxiliary ALU Control circuits can decode the correct control signals
throughout the instruction cycle.
The IR latches data from the SSMUX 00-15 lines on K2-7 LOAD IR L and the leading edge of KI-5
PROC CLK L.
On the trailing edge of K2-9 BUT SERVICE (1) H, all the IR bits except K2-5 IRI5 (1) H are cleared.
[K2-5 IRI5 (1) H is set by the same signal transition.] This means that the IR Decode circuit will see a
conditional branch instruction in the IR after every service microstep. This action prevents the processor from decoding a HLT instruction after an Initialize condition.

If a bus error (BE) occurs while the Control Store output signal Enable Double Bus Error (K2-8
ENAB DBE L) is asserted, the whole IR is cleared (PDP-ll Halt), causing the processor to halt
automatically. Bus errors occurring without the K2-8 ENAB DBE L signal have no effect on the IR.
K2-8 ENAB DBE L is only asserted during certain microwords in the trap sequence to prevent the
possibility of a second bus error occuring (Double Bus Error), which would cause the trap sequence to
be re-entered before it is completed. For example, if R6 (Stack Pointer) were an odd address, the first
bus reference using the stack in the trap routine would cause another trap (Odd Address), a sequence
that could tie up the CPU indefinitely ifnot for the Halt and Double Bus Error facilities. In short, any
bus error during the four memory references of the trap sequence is fatal.
4.5.3

Instruction Decoder

4.5.3.1 Instruction Decoder Circuitry - The Instruction Decode (prints K2-5 and K2-6) and Control
Store (prints K2-7 through K2-1O) circuitry could be thought of as an internal microprocessor that
interprets PDP-II instructions and translates them into a set of microinstructions, each consisting of
40 control signals. These control signals then determine the operation of the data path and Unibus
control circuitry.
A block diagram of this internal microprocessor is shown in Figure 4-1. Note that all outputs of the
Control Store ROMs (K2-7 through K2-1O) are latched in hex D-type registers (74174s).
Nine of these latched signals (K2-7 MPC 08 H through K2-7 MPC 00 H) are fed back to the inputs of
the Control Store ROM as the next microinstruction address (and can then be called the micro-PC).
The wired-OR capability of these lines allows the IR Decode circuitry to force microbranching
addresses on certain enabling conditions. The actual micro branch address will depend on the instruction being decoded, the instruction mode used (modes 0-7), and the operand required (source or
destination).
The IR Decode circuitry is shown on prints K2-5 and K2-6.1t consists of one 512 X 4 ROM, ten 256 X
4 ROMs, and two 32 X 8 ROMs, and 74HOl, 7402, 7400, and 7410 logic gates. The following descriptions are based on instruction types. Complete block diagrams of the microcode flow are available in
the KDll-E pri~t set (drawing D-FD-KDll-E).

4-30

4.5.3.2 Double-Operand Instructions - Double-operand instructions require two address calculations,
one for the source and one for the destination operand. The micro branch to the sequence of microinstructions that determine the source operand is initiated by the Control Store output signal K2-6 IR
DECODE (1) H. When this signal is enabled, the IR Decode ROMs DOP Decode (E68 and E69 on
print K2-6) check the instruction in the IR (op code bits IRI5-12). If the instruction is a doubleoperand type, the ROM outputs are asserted as follows:
K2-6
IR Code OOL

Type

Instruction

K2-7
MPC07L

ROM Outputs
K2-7
Kl-7
K2-7
MPC06L MPC05L MPC04L

MOY (SMO*DMO)
DOP (MOY +SUB)
MOD (SMO*DMO)
(ADD, BIC, BIS)

o
o

SUB (SMO*DMO)

DOP (SMO*DMO)

Illegal Instructions

K2-7
MPC03L

o
o

DOP NONMOD (SMO*DMO)
(CMP, BIT)

NOTE
Ground on the MPC lines represents a logic "I."
Coupled with the microprocessor outputs of the DOP DEC ROM are the outputs of a set of type
74HOI gates on K2-6. These gates, when enabled, place the contents of the source mode field (IRll:09)
of the PDP-II instruction being decoded onto the MPC 00:021ines. These gates are enabled by the K26 SRCH ROM output only when the instruction being decoded is of the double-operand type, the K26 IR DECODE (1) L signal is asserted, and the instruction is not reserved (K2-6 IR CODE 00 L
unasserted).
A summary of the various source microaddresses is shown below:
Instruction
DOP (SMO*DMO)

Source
Mode

Octal
Microbranch Address

0
1
2
3
4
5

110
111
112
113
114
115

6
7

116
117

Reserved DOP

NOTE
A ground on the MPC lines represents a logic 1.
4-31

The DOP DEC ROMs described above are also used to decode the microprocessor address for the
various Control Store destination operand routines. When the K2-7 BUT DEST L input is asserted by
the miscellaneous control field circuitry of the Control Store, the DOP DEC ROMs decode the
instructions, determine whether it is a modifying or nonmodifying instruction, and generate the following micro-PC addresses.
ROM Outputs
K~

MPC07L

MPC06L

MPC05L

MPC04L

MPC03L

Move
==-===-;-=
(SMO*DMO)

Modify
(ADD BIS BIC but
not MOV or SUB)

Nonmodify
(CMP BIT)

SUB

Type
Instruction

The circuitry used to decode the destination mode field of the instruction being decoded is similar to
that described above for microaddressing the source operand routine. A set of 74H01 gates on K2-6 is
used to place the contents of K2-5 IR 05 (1) H through K2-5 IR 03 (1) H on the lines when enabled.
For double-operand instructions, enabiing occurs when the MPC miscellaneous control field asserts
K2-7 BUT DEST L.
ROM E73 on print K2-6 is also considered to be part of the DOP Decoder circuitry. This ROM
decodes all Extended Instruction Set (EIS) instructions, generating the following micro-PC addresses
when K2-6 IR DECODE (1) H is asserted:
Type
Instruction

K2-6
IR CodeOOL

K2-7
MPC07L

ROM Outputs
K2-7
K2-7
K2-7
MPC06L MPC05L MPC04L

K2-7
MPC03L
0

Multiply or Divide
(MUL, DIV)

Arithmetic Shift or
Arithmetic Shift Combined
(ASH,ASHC)

SOP

XOR
Reserved

4-32

0
0

The K2-6 DEST L output of the EIS Decoder ROM (E73) allows the 74HOI (E64) on print K2-6 to
place the contents of the destination mode field of the instruction being decoded onto the micro-PC
(MPCOO-MPC02) lines. This microbranching technique is similar to that described above for microaddressing the source operand routine. Use of the EIS instructions does not degrade processor timing
or affect NPR latency.
4.5.3.3 Single-Operand Instructions - Unlike double-operand instructions, single-operand instructions only require one address calculation to obtain the necessary operand. Complete SOP instruction
decoding is done with the two 256- X 4-bit ROMs (E59 and E58).
The SOP Microbranch ROM (E59) monitors the necessary IR input lines and asserts the correct
micro-PC address on lines K2-7 MPC03-L through K2-7 MPC 06 L when the K2-6 IR DECODE (1) L
signal is asserted and the SOP enable signal K2-5 IR 12-14=0 H is true. The K2-6 DEST L output is
also activated when an SOP instruction is decoded. This signal enables the destination mode monitoring circuitry described in the double-operand instruction decoding section. Microaddresses for
SOP instructions are shown below.
Base
Microbranch
Address

Instruction
SOP Modify
(CLR,COM,INC,DEC)

040

SOP Non-Modify
(TST)

160

NEG

150

Rotate and Shift
JSR
JMP
MARK
SWAB

170
150
020
030

MFPI (D)
MTPI (D)
MFPS
MTPS

100
250
130
120

The SOP Microbranch ROM (E59) is also used to decode JSR instructions. This decoding is performed in the same manner as that for SOP instructions. The K2-6 DMO H input to the ROM is used
to detect the illegal instruction JMP or JSR destination mode O. When this occurs, no micro-PC
address is allowed on the ROM outputs.

4-33

The SOP Decode ROM (E58) monitors the same input signals as the SOP Microbranch ROM. Its
purpose, however, is to decode illegal,reserved, and trap instructions. The three output signals K2-6
IR CODE 00 L through K2-6 IR CODE 02 L are enabled as follows:

Instructions

IR Code
01

1
0

0
1

1
0

0
1

Reserved
I
Illegal
1
(JMP or JSR Mode 0)
EMT
0
Trap
0

The fourth output signal of the SOP Decdoe ROM enables the destination mode monitoring circuitry
described in the double-operand instruction decoding section.
4.5.3.4 Branch Instructions - Conditional branch instructions are completely decoded by the Branch
DEC ROM (E71 on print K2-6). This ROM is enabled when bits IR11:IRI4 are all low and the K2-6
IR DECODE (1) L signal is active. The input lines monitored are the four condition code bits (N, Z, V,
and C) and four IR bits (lRI5, 10,9, and 8). When a branch is decoded, the K2-7 MPC 07 L output
signal is enabled. The branch instruction microcode routine in the Control Store will sign-extend the
branch offset and shift it left one place.
4.5.3.5 Operate Instructions - There are three 256- X 4-bit ROMs in the instruction-decoding circuitry for decoding PDP-II operate instructions. These ROMs are the Reset/Trap Decode, Trap Decode,
and Op Branch ROMs (E62), all found on K2-6.
The Op Branch ROM (E62) monitors IR output lines IROO:IR07. It is enabled when IR08 and IR15
are low and K2-6 IR DECODE (1) L is active. The PDP-II operate instructions are decoded into the
following micro-PC addresses on the ROM outputs K2-7 MPC 00 L through K2-7 MPC 03 L.
Instruction

Microbranch
Address
003
011
007
006
004
014

Reset
RTI/RTT
Set Condition Codes
Clear Condition Codes
RTS
Wait

The Reset/Trap Decode ROM (E53) decodes Reset, RTT, and RTI instructions and activates the
outputs K2-6 START RESET Hand K2-6 ENAB TBIT H accordingly. This ROM also allows the
lower PSW bits (K2-6 DISABLE LOAD PSW H) to be loaded only from the stack when the processor
is operating in User mode (memory management restriction). It also treats a Reset instruction as a
Nap in User mode.

4-34

The TRAP DEC ROM (E52) has the same inputs as the Op Branch ROM. Its purpose is to decode
Halt, reserved, trap, and illegal instructions, and to enable the outputs accordingly. The K2-3 USER
MODE H input also allows this ROM to treat Halt instructions as reserved instructions when operating in the memory management User mode.

Instruction

IR Code
01
1

Reserved
Illegal

BPT

o
o

00
0
1

0
1
1
Enable HLT RQST L

lOT
HALT

4.6 AUXILIARY ALU CONTROL
The AUX Control circuitry on the KDll-E consists of three bipolar ROMs, shown on K2-5.
ROM

Name

32- X 8-bit
256- X 4-bit
256- X 4-bit

DOP(E81)
SOP (E60)
ROT jSHIFT (E61)

These ROMs determine the ALU operation to be performed whenever the microcode executes the
action X -- yap B, where Y designates a scratchpad register and X designates either the B REG or a
scratchpad register.
The AUX DOP ROM (E8l) decodes double-operand instructions, and is enabled by K2-8 AUX
SETUP H. The following table expresses the outputs of this ROM as a function of the instruction
being performed. (B represents the B register, A represents any scratchpad register, and F represents
the ALU output.)

Instruction
MaY (B)
COMP(B)
ADD
SUB
BIT (B)
BIC (B)
BIS (B)
XOR

ALU
Operation
F--A
F --A minus B
F --A plus B
F --A minus B
F --A·B
F --A·B
F --A+B
F--A(±)B

ROM Outputs
Func Code
Func Code
02"
01"

Func Code
03"

1
1
0
1
0
0
0
1

0
0
1
0
1
1
1
1

4-35

0
0
0
0
0
1
1
0

Func Code
00"
1

0
0
0
1
0
1
0

The AUX SOP ROM (E60) decodes single-operand instructions, and is enabled by K2-8 AUX SETUP
H. The following table expresses the ROM outputs as a function of the SOP instruction decoded.

ALU

ROM Outputs
Func Code
Func Code

Func Code

Instruction

Function

03H

02H

OlH

OOH

SWAB
CLR (B)
COM (B)
INC (B)
DEC (B)
NEG (B)
ADC (B)

F+-A
F +-ZERO
F+-A
F +- A plus 1
F +-A minus 1
F +- A minus B
F+-A
plus CBIT (0)
F +-A plus
CBIT (1)
F+-A
minus CBIT (0)
F +- A minus
CBIT (I)
F+-A
F+-B
F+-B
F+-B
F+-B
NjA
F+-A
F+-A
F +- NBIT (0)
F +- NBIT (1)
F+-A
F+-A
F+-A
F+-A

0
0
0
0
0
0

1
0
0
0
0
1

0
0
0
1
1
0

1
0
I
0
1
0

SBC (B)

TST (B)
ROR (B)
ROL (B)
ASR (B)
ASL (B)
MARK
MFPI
MTPI
SXT
MTPS
MFPD
MTPD
MFPS

0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
1
1
1
1
0
1
1
0
1
I
1
1
1

1
0
1
1
1
1
0
0
0
0
1
0
0
0
0

1
1
0
0
0
0
0
1
1
0
0
I
1
I
1

A uxiliary control signals are also necessary for performing rotate and shift operations. The
ROT jSHFT ROM (E61) on K2-5 decodes these instructions and outputs those control signals
required to shift the contents of the B REG. Inputs KI-I BREG 00 (I) H, Kl-IO CC N H, and Kl-I
CBIT (I) H also determine the K2-5 SERIAL SHIFT Hand K2-5 ROT CBIT (1) H signals. The
SERIAL SHIFT H signal is sent to the BYTE MUX (EI06 on KI-IO), where it is used in determining
the K \-10 S HI FT IN 07 H signal used in the B REG shifting operation. K2-5 ROT CBIT (l) H is used
in the calculation of the new carry condition (C and V Bit ROM - EI05 on KI-lO). Note that for all
rotate and shift operations, the AUX SETUP is performed on the B +- B step before each X +- yap B
step previously mentioned. This is done to allow the condition codes to be set up without slowing the
processor.
Table 4-9 summarizes the auxiliary control instructions.

4-36

Table 4-9 Auxiliary Control for Binary and Unary Instructions
Condition Codes

ALU
Function

CIN

Instruction

Nand Z

MOV(B)

Load

Cleared

Not affected

A Logical

CMP(B)

Load

Load like Subtract.

A minus B

BIT(B)

Load

Cleared

Not affected

A. B Logical

BIC(B)

Load

Cleared

Not affected

-A. B Logical

BIS(B)

Load

Cleared

Not affected

A+-- B Logical

ADD

Load

Set if operands are same
sign and result different.

Set if carry ou t.

A plus B

SUB

Load

Set if there was arithmetic
overflow as a result of the
operation (i.e., if operands
were of opposite signs and
the sign of the source was
the same as the sign of the
result; cleared otherwise.

Set if carry.

A minus B

XOR

Load

Cleared

Not affected

A*B

CLR(B)

Load

Cleared (like Add)

Clear

COM(B)

Load

Cleared

Set

INC(B)

Load

Set if destination held
100000 before operand.

DEC

Load

NEG(B)

Not affected

A plus 1

Set if result is 100000.

Not affected

A minus 1

Load

Set if result is 100000.

Cleared if result is 0;
set otherwise.

A minus B

ADC(B)

Load

Set if destination was
077777 and C = 1.

Set if destination was
177777 and C = 1.

A plus CBIT

SBC(B)

Load

Set if destination was
100000.

Set if destination was
o and C = 1; cleared
otherwise.

A minus CBIT

TST(B)

Load

Cleared

A Logical

ROR(B)

Z+--]
1t{15:0])*C=0
N+--C

Unaffected

(0)

B Logical

4-37

Table 4-9 Auxiliary Control for Binary and Unary Instructions (Cont)
Condition Codes
Instruction
ROL(B)

NandZ
Z+-l
If( 14: OO)*C = 0
N+-(14)

Unaffected

ASR(B)

Z+-l
If(15:01) = 0
N+-N

Unaffected

ASL(B)

Z+-l
If(l4:01) = 0
N+-(I4)

SWAB
SXT

Load
Z-Load
N- Unaffected

ALU
Function

C
(15)

CIN

B Logical

o +- (IS)

B Logical

C +- (15)

B Logical

Cleared

A Logical

Cleared

B (7)

MFPI

Load

Cleared

Unaffected

A Logical

MTPI

Load

Cleared

Unaffected

A Logical

MTPS

Z-Set
IfSRC(7)=O
N-Set
If SRC(7)=1

Cleared

Unaffected

A Logical

MFPD

Load

Cleared

Unaffected

A Logical

MTPD

Load

Cleared

Unaffected

A Logical

MFPS

Z-Set
If PS(7)=0
N-Set
If PS(7)=I

Cleared

Unaffected

A Logical

4-38

4.7

DATA TRANSFER CIRCUITRY

4.7.1 General Description
All Unibus data transfers are controlled by the OAT TRAN circuitry on K2-1. This logic monitors the
busy status of the Unibus, controls the processor bus control lines BBSY, MSYN, Cl, and CO, and
detects parity errors (PE), and bus errors (BE).
4.7.2

Control Circuitry

4.7.2.1 Processor Clock Inhibit - All processor data transfers on the Unibus are initiated by K2-8
BUF OAT TRAN (1) H. When KI-5 TAP 30 H goes high, the signal combines with the signal K2-1
EOT L (normally a logic 1 between transfers) to create K2-1 TRAN INH L, shutting off the processor
clock until the transfer is completed.
4.7.2.2 Unibus Synchronization - The synchronizer logic shown in Figure 4-19 (from K2-1) arbitrates
whether the processor or some other Unibus peripheral will control the Unibus. A logic 1 level (+ 3 V)
at the set input of the E31 flip-flop on K2-1 specifies that the bus is presently in use. Each of the inputs
that combine to create this level monitors a specific set of bus conditions.

K2-t DATIP (1) L - - - - - - - - - - - - - - - - ,
K2-t DATIP (0) L - - - - - - - - ,
K2- t BBSY H
K2-2 NPR H

1. . , 0 - - - - - t - - K 2 - t BUS IN USE H
t-

K2-2 NPG (1) H
K2-2 NO SACK L

START
TRAN H

=
K2-8 BUF DAT TRAN (,) H
DE2
Kl-5 TAP 30 H
11-3893

Figure 4-19

Unibus Synchronizer

4-39

NPR
(K2-2 NPR H)

A Unibus peripheral has asserted a nonprocessor request
(NPR) and wishes to gain control of the bus immediately.

BBSY
(K2-1 BBSY H)

Another Unibus peripheral already has control of the bus, and
is asserting a bus busy (BBSY) signal.

NPG
[K2-2 NPG (I) H]

An NPR device has requested control of the Unibus and the
KD ll-E processor has issued a nonprocessor request grant
(NPG). The condition may exist where the NPR device has
already recognized the NPG and has dropped its NPR signal,
while not yet having asserted a SACK or BBSY.

NO SACK L
(K2-2 NO SACK)

A device has requested control of the Unibus. The KD II-E
processor has issued a grant, and the device has returned SACK
L, causing NO SACK L to go high. The condition may exist
where only SACK L remains on the Unibus for a period of time
before the peripheral asserts BBSY.

DATIP (0) L
[K2-1 DA TIP (0) I]

When this input is true, all of the above signals are overridden.
It indicates that the processor is performing a DA TIP
(Read/Modify /Write) operation, and has control of the Unibus
(BBSY asserted). NPR devices may, however, be granted bus
control, but must wait until the processor releases BBSY before
asserting theirs. (DA TIP operations dictate worst-case bus
latencies for NPR devices.)

BUS SSYN L

A data transfer is still being completed; therefore, the processor
must wait before initiating another.

If none of the above Bus-in-U se conditions exist, the K2-8 BUF DAT TRAN (l) H signal sets the E31
flip-flop on K2-1 when KI-5 TAP 30 H goes high, and activates K2-1 START TRAN H to start the
transfer. The RC circuit at the output of E36 eliminates any noise that may result from the synchronizer under worst-case conditions.

4.7.2.3 Bus Control- Once the K2-1 START TRAN H signal is activated, the DAT TRAN circuitry
begins a Unibus data transfer operation by asserting K2-1 ENAB ADDRS L, triggering the following
actions:

Enables the bus address drivers (BUS A 15:AOO on K 1-6).

Enables the BBSY driver (K2-1).

Enables the bus control signals BUS CO and BUS CI, which determine the kind of transfer
being performed.
Cl

Operation

o
o
I

o
1
o

DATI
DATIP
DATO
DATOB

The actual condition of these control lines is determined by K2-8 BUF CO (I) Hand K2-8
BUF CI (1) H.

4-40

Enables the bus data drivers (BUS DOO-BUS D 15) if the operation being performed is a
DATa.

4.7.2.4 M8264 NO-SACK Timeout Module - The M8264 is a quad-height module containing circuitry that asserts BUS SACK L on the Unibus if a device requesting Unibus control does not assert
SA CK within 10 J.Ls after a grant line has been enabled (Figure 4-20).
The grant signals (BUS NPG and BUS BG7 through BUS BG4) are ORed (E3) on the M8264. The
output of the OR gate enables a NAND gate (E6) and triggers a monostable multivibrator (E5). The
signals produced are A NDed (E I) to enable BUS SACK L. The monostable effectively delays (by 10
J.Ls) the assertion of BUS SACK L since it produces a 10 J.LS pulse which prevents the AND gate from
being enabled. BUS SACK L, when asserted, will cause the processor to drop the grant line, which will
in turn cause the M8264 to drop BUS SACK L.
This module prevents the processor from being hung if a grant line is asserted and BUS SACK is not
returned by the device requesting bus control. If the requesting device returns BUS SACK, the M8264
will not assert BUS SACK since the grant line will be dropped before the monostable times out.
As a maintenance aid, a counter is provided (E4) to drive a set of LEDs. The binary counter counts up
one each time BUS SACK is asserted by the M8264 and the number of occurrences is indicated by the
LEOs. The maximum number recorded is 15 before the counter is reset. The counter is cleared and the
monostable multivibrator is reset when BUS DC La L becomes asserted (i.e., upon system power-up).
4.7.2.5 MSYN/SSYN Time-Out Circuitry - Unibus specifications require that the BUS MSYN L
control signal be enabled no sooner than 150 ns after the bus address, data, and control lines have been
asserted. To meet this requirement, the circuitry in Figure 4-21 has been incorporated into the OAT
TRAN logic (K2-1).
The multiplexer (E 10) shown in Figure 4-22 helps adapt the D AT TRAN circuitry to the type of bus
operation being performed (DATI or DATa). Specific functions performed are as follows:
1.

Generates the correct Unibus control signals [K2-1 UBUS CO (1) Hand K2-1 UBUS Cl (1)
H].

Inhibits the detection of parity errors during DATa operations.

Generates an End of Transfer (EaT L) signal as soon as BUS SSYN is returned by an
addressed peripheral.

Delays the assertion of BUS MSYN, using the clock signal Kl-5 ALLOW MSYN H, which
does not become asserted until the Physical Bus Address register has been loaded.
NOTE
This applies only to DATI or DA TIP. During
DATO or DATOB, the bus address is never loaded
in the same micro cycle that does the DATO or
DATOB.

4-41

+5V

BIJS NPG H
BUS BG7 H
BUS BG6 H
BUS BG5 H
BUSBG4H
+5V

P--=---BUSSACKL
RESET

CLR

CUP
~~~~;r--~~--r-------------+5V

+5v----~~-----L----~

GRANT LINE
ASSERTED HIGH

BUS SACK
ASSERTED LOW

______________________;l~·~-------10~S--------~,
®
@)

....

,.--------1 0 ~s-------

--------------------~

~~----~-------

®
BUS SACK L
UNASSERTED
11-4578

Figure 4-20 NO-SACK Timeout Module

4-42

K2-4 DISABLE MSYN +1 l

K2-1 ENAB ABORT H

Kl -8 KT FAULT l - - - c Y

K2-1 MSYN H

K2-2 SACK RET 0) H 2

K2-1 INT MSYN H

K2-1 MSYN (I) l

K2-1 ClK
MSYN H

K2-1 SSYN H
K2-1 START TRAN H

I
K2-1 MSYN (0) H 5

Kl-5 AllOW MSYN H

5
4

K2-1 MSYN (I) H
8

D
E31
C

K2-1 MSYN (I) l

K2-1 MSYN (II)) H

* K2-8 BUF Cl (I) H

C69

K2-8 BUF DAT TRAN (1l H
KI-5 TAP 30H

DE2

2
K2-1 SSYN H

K2-1 TO (Il H
K2-1 TO (1) l

* K2-8 BUF C1 ( 1) H is {Asserted for DATO or DATOB
Unasserted for DAT I or DAT I P
11- 3894

Figure 4-21

SSYN/MSYN Control

K2-1 SSYN H _ _ _4'-1
K2-1 MSYN (0) H _ _.,5
KI-5 AllOW MSYN H EV2

745157
3 B0 ElO
4
F0
2 A0

K2-1 OET PE H

7
R5
470
r--"vvv- + 5

F3 12

'-----'6"-1Bl

K2-1 PARITY ERROR H
K2-1
2
ABORT RESTART l 13

Fl 7

1G'6=---_5"-1A1
K2-1 SSYN H

,-_..:..10"B2

K2-1 SSYN (1) H

74175
CB2
K2-1 UBUS C0 (1) H
E13 R1(O 7
~--"'"IOI
Rl (0)6
K2-1 UBUS C0 (1) l

F2 9

11 A2
STB
15

ENAB EOT H

S0
1-'1---11-----103

K2-5 BYTE H
K2-8 BUF C0 (1) H

K2-8 BUF C 1 (1) H - - - - - - - - - - - - - '

=
K2-8 BUF OAT TRAN (1) H

15 CC1
R3 (1)
K2f-l UBUS Cl (1) H
R3 (0)14
R0(1} 2
R0(0) 3

R2(1l 10
R2(0l 11
ClK

OE2
KI-5 TAP 30 H
11-3895

Figure 4-22

Data Transfer Multiplexer

The RC circuit shown in Figure 4-21 prevents the MSYN flip-flop (E3l) from being clocked until
approximately 150 ns after the bus address and control lines are placed on the bus. Once this latch is
set, BUS MSYN L is activated and the SSYN TIMEOUT one-shot E16 is triggered. When SSYN is
returned by the addressed peripheral, both the MSYN flip-flop (E31) and the SSYN TIMEOUT oneshot are cleared. The processor clock is then freed by the release of K2-l TRAN INH L. If a DATI or
DATIP operation is being performed, that will be clocked into either the scratchpad, B REG, PSW, or
IR on the next low-to-high transition of Kl-5 PROC CLK L.
If a DATO or DATOB operation is being performed, the data bus drivers are disabled after SSYN is
returned from the addressed peripheral but before the MSYN line is unasserted.
4.7.2.6 Bus Errors - Once the SSYN TIMEOUT one-shot is triggered, SSYN must be returned
within 22 J.LS. If SSYN is not returned in this time, E16 times out, setting the TIMEOUT flip-flop
(E32). The output of this latch then generates the signal K2-l ABORT RESTART L and pulse K2-l
ABORT H. K2-l ABORT RESTART L reenables the PROC CLK and K2-1 ABORT H sets the Bus
Error flip-flop (E33). This same pulse that sets the Bus Error flip-flop also clears the micro-PC address
latches (MPCOO through MPC008) on K2-7, forcing the processor to enter the service microroutine on
the next PROC CLK L low-to-high transition.
4.7.2.7 Parity Errors - If a data transfer is being performed with a parity memory (e.g., MSll-1P or
MMII-DP), all parity errors detected by the memory will be reflected back to the KDll-E on the
Unibus lines BUS PA L and BUS PB Lon K2-1 (Figure 4-23).
Control
PA
PB

Error
Description

o
o

No Parity Error
Parity Error on DATI
Reserved for future use
Reserved for future use

1
1

o
1
o
1

Errors detected while performing aDA TIP or DATI [K2-8 BUF Cl (l) H unasserted] will result in the
Parity Error flip-flop (E34) being set when SSYN is returned to the processor. Processor operations
resulting from Parity Error will be discussed further in Paragraph 4.11, Service Traps.
4.7.2.8 End of Transfer Circuitry - To synchronize the DAT TRAN logic with the main KDll-E
processor clock, the End of Transfer (EOT) circuitry (Figure 4-24) has been incorporated into the CPU
(K2-1). During a DATI or DA TIP, an EOT L signal is generated approximately 100 ns after SSYN is
returned to the processor. That EOT L removes the processor clock disabling signal (Paragraph
4.7.2.1), K2-1 TRAN INH L. During a DATO or DATOB, K2-1 TRAN INH L is un asserted immediately when SSYN is returned.
4.7.2.9 Data-in-Pause Transfer - Another circuit included in the DAT TRAN logic detects Data-inPause (DA TIP) transfers and controls the bus control signal BBSY. When a DATIP
(Read/Modify /Write) bus operation is initiated, the flip-flop (E32) is latched, forcing the processor to
hold BBSY L until the DATO portion of the routine has been completed. While BBSY is asserted, no
other Unibus peripheral can seize control of the bus. This feature often determines the maximum bus
latency for NPR devices (K2-1).

4-45

K2-1 DET PE H
BUS PB L
BUS PA L

13 H

PART
OF EIO 12
1414 L

K2-1 ENAB EOT H

E
K2-1 PE (1) H
CT2

*K2-8 BUF Cl (1) H

K2-1 TO (1) L

K2-4 DISABLE MSYN + I L

K2-1 SET BE L

K2-1 BE (1) H
K2-1 BE (1) L

K2-1 ABORT H

6
KI-8 KT FAULT L

3
K2-1 KTE (1) H
EJ2

K2-2 BUT SERVICE L

K2-2 PROC INIT L
* K2-8 BUF Cl (1) H {Asserted for DATO or DATOB
Unosserted for DATI or DATI P
11-3896

Figure 4-23

Error Logic

+5
K2-1 ENAB EOT H

R5
+5
R6

K2-1 SSYN H

6 B

PART K2-1 EOT L
oFE1ot----

K2-1 MSYN (1)H 9

5 A

ST8 s0
15

~K_2_-1~D~E~T~P~E~H~___________
11~E1~10~--~

*K2-8 BUF C1 (1) H

*" K2-8 BUF C1 ( 1) H {ASserted for DATO or DATOB

Unasserted for DAT1 or OAT I P
11-3897

Figure 4-24

End-of-Transfer Logic

4.7.2.10 Odd Address Detection - The circuitry shown in Figure 4-25 is incorporated in the KD 11-E
to detect odd address errors. ROM E78 (print K2-8) monitors the signals K2-8 BUF DAT TRAN (1)
H, K2-5 BYTE H, and KI-6 VBAOO (1) H, and asserts K2-8 DISABLE MSYN L when an odd address
is detected. The multiplexer circuit (E38 on K2-4) forces the processor to always autoincrement or
autodecrement the PC (R7) or the SP (R6) scratchpad registers by two, regardless of the type of
instruction being performed. This is done by preventing the K2-4 DISABLE MSYN + I L signal from
being asserted.
4.8 POWER FAIL/AUTO RESTART
The KD 11-E power fail/auto restart circuitry (K2-3) serves the following purposes:
1.

Initializes the microprogram, the Unibus control, and the Unibus to a known state immediately after power is applied to the computer.

Notifies the microprogram of an impending power failure.

Prevents the processor from responding to an impending power failure for 2 ms after initial
startup.

The actual power fail/auto restart sequences are microprogram routines. The operation of the power
fail/auto restart circuitry depends on the proper sequencing of two bus signals: AC LO and DC LO.
Because of the electrical properties of the Unibus drivers and receivers, the entire computer system
must be powered up for the machine to operate. Therefore, the processor is notified of a power fail in
peripherals, as well as in its own ac source.

4-47

2TOI
MUX
10 E38
K2-3 R6+7 L

K2-4

DISABLE
74S04 MSYN + 1L

I
74S02

KI-5 TAP 30 H -+-----'

K2-8
BUF DAT TRAN (1) H

K2-9 SS 01 H
K2-9 SS 00 H
K2-8 BUF DAT TRAN (1) H
K2-8 AUX CONTROL (1) H

256 x 4
E78

3
4
5
6

KI-6 VBA
00 (1) H

K2-6 MOVE L

-= 7
14

-=
11-3898

Figure 4-25

Odd Address Detection

The notification of power status of any PDP-II system component is transmitted from each device by
the signals BUS AC LO L and BUS DC LO L (K2-3). The power-up sequence (Figure 4-26) shows that
BUS DC LO L is unasserted before BUS AC LO L is unasserted. When BUS DC LO L is not asserted,
it is assumed that the power in every component of the system is sufficient to operate. When BUS AC
LO L is not asserted, there is sufficient stored energy in the regulator capacitors of the power supply to
operate the computer for 5 ms, should power be shut down immediately.
As ac power is removed, BUS AC LO L is asserted first by the power supply warning the processor of
an impending power failure. When BUS DC LO L is asserted, it must be assumed that the computer
system can no longer operate predictably. Memories manufactured by DIGITAL use BUS DC LO L
as a switched signal, turning them off even if power is still available. Time b.t2 (Figure 4-26) is the time
delay between the assertion of BUS AC LO L and the assertion of BUS DC LO L; this time delay must
be greater than 5 ms. This allows for power to be rapidly cycled on and off. According to PDP-II
specifications, upon system startup a minimum of 2 ms run time is guaranteed before a power fail trap
occurs, even if the line power is removed simultaneously with the beginning of the power-up sequence.
After the power fail trap occurs, a minimum of 2 ms run time is guaranteed before the system shuts
down. Given the tolerances permitted in the timing circuitry used in most in most equipment, b.t2 must
be greater than 5 ms.
4-48

)~~---------

+5V

BUS AC LO L

OV _ _ _ _ _ _..J

~--------------~

+3V

BUS DC LO L

--II

OV _ _

-I Dot IINIT

POWER

PDWN

__--II Do t 1>0 ms

I--

150 ms

--l

------~I---.~ H - - - - -

2.2mS-j

--------------------~\~-

~I______

r- 6 .6ms -i

11 - 3950

Figure 4-26

BUS AC LO and BUS DC LO Timing Diagram

When a pending power fail is sensed, a program trap occurs, causing the present contents of PC (R 7)
and the PSW to be pushed onto the memory stack, as determined by the contents of R6 (Stack Pointer
register). The PSW is then loaded with the contents of location 26 8 and R7 with the contents of 248.
Processing is continued with the new R 7 and PSW. The user's program must prepare for the impending power failure by storing away volatile registers and reloading location 248 and 26 8with a power-up
vector. This vector points to the beginning of a restart routine.
When power is restored, the processor loads the PC (R 7) with the contents of location 248 and the
PSW with the contents of location 268. After loading these registers, the user program presumably will
prepare locations 248 and 26 8 for another power failure. If the HLT RQST L input is asserted by an
external switch closure, the processor powers up through locations 248 and 26 8, and halts.
Schematics for the power fail, auto restart, and bus reset logic are on K2-3. One-shot E14 generates a
150-ms processor INIT pulse as soon as BUS DC La L is nonasserted after power is applied to the
processor. At the end of 150 ms, the PUP one-shot (E7) is fired if BUS DC La L is not asserted and the
processor begins the PC and PSW load routine. The PUP one-shot generates a 2-ms pulse, during
which the assertion of BUS AC La L is ignored.
The triggering of the 150-ms INIT one-shot also resets the POWER INIT flip-flop (E24). Setting this
flip-flop forces the Control Store to run the power-up routine beginning at micro-PC address 001. It is
this routine that reads locations 248 and 26 8 for the new PC and PSW.
After PUP has timed out, the assertion of BUS AC La L would fire the one-shot PDWN (E7). Upon
entering the next service microcode state, K2-3 PFAIL H is latched into E19 (K2-2), causing a power
fail trap to be recognized by the microprogram on entering the next service state. Various traps are
arbitrated by the BUT service ROMs (E50 and E51 on K2-3).
If a momentary power failure occurs that causes the assertion of BUS AC La L but does not cause the
assertion of BUS DC La L, the processor will restart when the PDWN one-shot times out, retriggering the INIT one-shot.

4-49

When a Reset instruction is decoded by ROM ES3, the ROM output signal START RESET H is
clocked into the Start Reset flip-flop (ES4 on K2-2). This flip-flop output triggers a 100-ms INIT, after
which the processor continues operation.

4.9 PROCESSOR CLOCK
The processor clock circuitry for the KDII-E is shown in Figure 4-27 and on print Kl-S. A delay line
is used to generate a pulse train, to which the entire processor is synchronized. Because the KD 11-E is
a fully clocked processor, events that result in the alteration of storage registers occur only on defined
edges of the processor clock.
If all clock disable inputs are un asserted, the clock will begin running as soon as +S V is applied. The
length of an operating cycle can be either 180 ns or 240 ns, depending on the nature of the instruction
being performed. Most microinstructions employ the shorter cycle, with the longer one only necessary
when the machine is performing a DATa or DA TaB, or in situations where the condition code must
be determined before an operation can be performed. Long cycles are also used in loading the Bus
Address register when memory management is turned on.

The clock is turned on and off by the gating of the feedback through the delay line. Taps of 120 ns, 90
ns, and 30 ns make it possible to vary the length of the cycle, according to a signal input [K2-8 LONG
CYCLE (1) L] from the Control Store, as the processor clock timing diagrams in Figure 4-17 show.
The indicated jumpers are inserted at WI and W2 in the standard configuration; the overall cycle can
be slowed down slightly (approximately 30 ns) by inserting jumpers at the alternate locations (shown
on K l-S by dotted lines) instead. It is also possible to disable the clock manually and use the manual
clock input; any TTL-compatible waveform may be employed. Multiplexer E94 issues the feedback
signal that, in effect, determines the length of the cycle.
The clock is turned off by the appropriate signal under the following conditions:
1. During a BUS INIT that is not caused by a RESET
2.

During the INIT portion of the power-up routine

During the INIT portion of the power-down routine

4. During a Reset
S.

During the BUT Service arbitration delay

During a priority interrupt

7. While BUS SACK is asserted by an interrupting device (not for NPR transfers)
8.

During bus data transfers

9. After a Halt instruction is executed
10. When the manual clock is enabled

4-S0

3
2

74S157
E94
6
B0
f0
A0

r----------dEl0~2'----_;:=====~w=:;~:;:::;;:-------~~ Bl
1

Kl-5 LOADUBA H
fl

74S04

KI-5 ALLOW MSYN H

5
B2
A2

R30
220

+5V

13
B3
14
A3

I - - - I V V ' - - + 5V

STB
R20
1K

R21
1K

CLK L

KI-5 LOAD BAR L
f3 12
S0

FSI
MAN

f2 9

Kl-8 RELOCATE H

-----'--+--+------

FEI
MAN CLK ENAB L _----L-~--.-!;J

K2-8 LONG CYCLE (1) L E...
V2+_ _ _---.J

---11-Y~- Kl- 5 TAP 120 H

WI
K2-2 PROC.INIT. LFD2 3
K2-1TRAN IN H FCI
K2 BG INIT L
FBI
Kl- 5 TAP 90 H
EM2
Kl-5 TAP 30 H

5
4

KI-5 PROC CLK L

KI-5 REG CLK L

K 1 - 10 ASSERT SSYN L -----'~
KI-5 REG eLK H

11-3899

Figure 4-27

Processor Clock Circuit
4-51

4.10

PRIORITY ARBITRATION

4.10.1 Bus Requests
The KDII-E responds to bus requests (BRs) in a manner similar to that of the other PDP-II processors. Peripherals may request the use of the Unibus in order to make data transfers or to interrupt the
current processor program by asserting a signal on one of the four BR lines, numbered BR4, BR5,
BR6, and BR7 in order of increasing priority. For example, if two devices, one at priority 5 and the
other at priority 7, assert BRs simultaneously, the device at priority 7 is serviced first. Furthermore, if
the processor priority, determined by PSW bits 07:05, is at level 4, only devices requesting BRs at levels
higher than 4, such as BR7, BR6, or BR5, are serviced. Table 4-10 contains the order of priority for all
BRs and other traps.
Table 4-10 Priority Service Order
Priority

Service Order

Highest

Halt Instructions
Odd Address
Memory Management
Error
Time-Out
Parity Error
Trap Instruction
Trace Trap
Stack Overflow
Power Fail
Halt from Console
BR7
BR6
BR5
BR4
N ext Instruction Fetch

Lowest

Because a BR can cause a program interrupt, it may be serviced only after completion of the current
instruction in the IR. A device that requests a program interrupt must, at the appropriate time, place a
vector address on the Unibus data lines. The processor first stacks away the current contents of PSW
and R 7; then a new PSW is loaded from the contents of the vector address plus two and a new PC is
loaded with the contents of the vector address. Further discussion of how the processor handles this
BR routine is contained in the section on Service (Paragraph 4.11).

4-52

Arbitration logic for BRs is contained on print K2-2 and in Figure 4-28. All BRs are received directly
from the Unibus (Unibus receivers EI7), and latched into register E19 (quad D-type latch, 74S174)
when the microprogram enters the next service state [K2-9 BUT SERVICE (1) H is true]. The BR
Priority Arbitration ROM (E29) then determines whether the present processor priority [PSW (7:4)] is
higher than the highest BR received and, if not, which BR received has the highest priority. Arbitration
performed by E29 in the order of priority are shown below.
HLT RQST
PSW7
BR7
PSW6
BR6
PSW5
BR5
PSW4
BR4

K2-2 RESET (1) H
K2-2 AllOW BG H

8 K2-2 BG INH l
x::>-:-:.=.....::....=....:---'-

K2-2 SACK RET ( 1) H

K2-2 NO SACK H
K2-2 ClK BG H

K2-2 BUT SERVICE l

K2-2 NPG (1) H
6

K2-2 BG ENAB H

K2-2 NPG ENAB H

C56
BUS NPR l
AS2
K2-2 RCD INIT H

l
K2-2 NPR H

11
13
K2-2 PROC INIT H

K2-2 RCD INIT L

12
11-3901

Figure 4-28

Priority Arbitration Synchronizer

4-53

If the highest BR received is of a higher priority level than the processor, the corresponding grant
enable ROM output is asserted low (Figure 4-29). With no HLT RQST or trap instruction pending,
the processor clock will be disabled by the K2-2 BG INH L signal. The actual bus grant is not transferred to the Unibus until the Enable BG flip-flop (E12) is set. Grants (both BG and NPG) are
controlled by the synchronizer logic shown in Figure 4-28 and on print K2-2.

This circuitry arbitrates whether a bus grant (BG) or a nonprocessor grant (NPG) will result, depending on which flip-flop input line (set or reset) was deactivated first. The set input K2-2 BUT SERVICE
L will cause the flip-flop to issue the BG ENAB H signal after a delay of 175 ns. Once the flip-flop is
set, the bus grant arbitrated by the BR Priority Arbitration ROM (E29) is channeled onto the Unibus
(bus driver E75). When the requesting peripheral receives BG, it returns BUS SACK L.
Upon receiving BUS SACK L, the processor clears its Enable BG flip-flop, removing the bus grant
from the Unibus, and sets the SACK RET flip-flop to keep the processor clock disabled. Removal of
bus grant causes the peripheral to drop its BUS SACK L (provided that BBSY is unasserted), assert
BUS INTR Land BBSYL, and enable a vector address onto the Unibus data lines. The processor then
deskews the removal of SACK, clears the SACK RET flip-flop (E5), and enables the processor clock
again. Once in operation, the processor clocks the peripheral vector address into the B REG, returns
BUS SSYN L, and begins running the microcode trap routine that branches the processor to the
interrupt handling program determined by the vector obtained.

4.10.2 Nonprocessor Requests (NPRs)
NPRs are a facility of the Unibus that permit devices on the Unibus to communicate with each other
with minimal participation of the processor. The function of the processor in servicing an NPR is to
yield control of the bus in a manner that does not disturb the execution of an instruction by the
processor. For example, the processor will not relinquish the bus following the DATI portion of a
DATIP transfer.
When the reset input of E5 (K2-2 NPR H) becomes un asserted before the set input, and BUS SACK L
is not true, the flip-flop issues K2-2 NPG ENAB H, enabling the BUS NPG H Unibus line and
granting the bus to the DMA device. The requesting device then returns BUS SACK L, clearing the
NPG, and waits until the bus is free (no BBSY).

4.10.3 Halt Grant Requests
The KD Il-E implements what is, in effect, another priority level by monitoring the
HALT jCONTINUE switch on the front panel. When a Halt is detected (HLT RQST L asserted), the
processor recognizes it as an interrupt request (refer to priority levels in Paragraph 4.10.1) upon entering the next service microstate. The processor then inhibits the processor clock and returns a recognition signal (K2-2 HLT G RANT H), causing the console to drop HL T RQST L and assert BUS SACK
L, gaining complete control of the Unibus and the KDll-E.
The user can maintain the processor in this inactive state (Halted) indefinitely. When the HALT switch
is released, the user's console releases BUS SACK L, and the processor continues operation as if
nothing had happened.

4-54

+5
R13
BUS BG7 H

K2-2 BG7 H

DK2
Dl2

R14
BUS BG6 H

K2-2 BG6 H

DM2
DN2

R15
BUS BG5 H

K2-2 BG5 H

DP2
DR2

RI6
BUS BG4 H

K2-2 BG4 H
12

DS2
DT2

K2-2 HLT GRANTH

3
8

K2-2 HlT RQST (1) H
K2-2 ENAB GRANTS H
11
K2-2 ClK BG H

D
E12
ClK
ClR
13

9
8

K2-2 SACK RET(I)H

K2-2 SACK RET (1) l

9
8

K2-2 AllOW BG H
K2-2 NPG (1) H

K2-2 NPG ENAB H
----------------------------~
BUS SACK l

BUS NPG H

CAl
CBl

K2-2 NO SACK l

11- 3902

Figure 4-29

Priority Bus Control

4.11

SERVICE TRAPS

4.11.1

General Description
All interrupts, error traps, and instruction traps are recognized and serviced by the KD ll-E when the
processor enters what is called the service microinstruction state. The functions performed during this
state are most critical to the operation of the processor.

When the service state is entered, all bus interrupts, error traps, and instruction traps realized during
the performance of the last instruction are arbitrated by the service ROMs (E50 and E51 on print K23). Each trap condition is then serviced according to its priority, as listed in Table 4-10.

4.11.2

Circuit 0 peration
The service ROMs (E50 and E51 on print K2-3) service a specific trap by generating a vector address
unique to that trap condition (Table 4-11). Upon leaving the service state, the processor is forced to
push its present program counter (PC) and processor status word (PSW) onto its memory stack and
fetch a new PC from the location specified by the vector address. A new PSW is then obtained from the
next memory location after the vector. The end result of these operations is that the processor is no~'
performing a software subroutine written by the user that could correct or indicate the occurrence of a
specific error.

The various trap conditions that cause the processor to vector are as follows:
Bus Errors

A bus error indicates that the processor has attempted to access
nonexistent memory or odd address (non-byte), or a memory
location that did not return BUS SSYN within 22 J,LS. The detection circuitry for bus errors is described in Paragraph 4.7.2.6 of
this manual.

Stack Overflow Error

Any attempt by the processor to decrement the contents of the
Stack Pointer register (R6) below the 400-location stack limit
(K1-1O 8-15 = 0 H will result in the Stack Overflow flip-flop
(E24 on K 2-3) being set on the next transition of Kl-5 PROC
CLK L. [Note that this does not apply to user stack (R16).]

Parity Error

Parity error detection circuitry is described in Paragraph
4.7.2.7.

Power Failure

The power failure circuitry is described in Paragraph 4.8.

Trace Trap

This trap is program-controlled by the user, allowing him to
insert a processor luser interactive subroutine into his main program. The circuitry is described in Paragraph 4.2.6.

Reserved Instructions
Illegal Instructions
EMT Instructions
Trap Instructions

Signals IR CODE 00 L-IR CODE 02 L are generated by the IR
Decode ROMs on K2-6 for these conditions. Their decoding is
discussed in Paragraph 4.5.3.

Upon entering the service microinstruction state, the service ROMs (E50 and E51 K2-3) monitor any
combination of the above trap conditions which, if true, cause the assertion of microprocessor address
line K2-7 MPC 00 L. While still in the service state, the ROM also generates a specific vector address
(Table 4-11), using outputs K2-3 C2 H, K2-3 C3 H, and K2-3 C4 H, arId channels it onto the processor
AMUX lines to the SSMUX by activating K1-10 AMUX SO H.

4-56

Table 4-11

Vector Addresses

Octal Unibus
Vector Address
004
010

014
020

024
030
034
114
250

Trap Conditions
Time-Out, Odd Address, and Stack Overflow Errors
Illegal and Reserved Instructions
T-Bit Trap (BPT)
Input/Output Trap (lOT)
Power Fail
Emulator Trap (EMT)
Trap Instruction
Memory Parity Errors
Memory Management Errors

Before leaving the service state, the service ROMs also clear the condition that caused the original
trap. This is done either by asserting K2-3 STOV SERV H or K2-3 PF AIL SERV H, or by performing
the steps in the trap service routine. For those traps specified by the IR Code lines, however, it is
necessary to remove the instruction in the IR. This is done through microcode output K2-9 BUT
SER VICE (1) H, which ORs with K2-2 PROC INIT H to generate K2-3 SERV IR H and, hence, K2-3
SER V IR (1) L, removing the trap instruction from the IR. This prevents the processor from looping
on the same trap condition.
For bus requests (BRs), the BUS INTR L control signal is allowed to force K2-7 MPC 00 L during
service, provided that there are no other traps of higher priority. By enabling this line, the processor
will branch to the trap routine. Higher priority BR interrupts are prevented from receiving BG by K29 BUT SERVICE (1) H.
MEMORY MANAGEMENT

4.12
4.12.1

General

4.12.1.1 Introduction - This section describes the memory management unit of the KD11-E Central
Processor. The KD11-E provides the hardware facilities necessary for complete memory management
and protection. It is designed to be a memory management facility for systems where the memory size
is greater than 28K words and for multiuser, multiprogramming systems where protection and relocation facilities are necessary.
4.12.1.2 Programming - The memory management hardware has been optimized toward a multiprogramming environment and the processor can operate in two modes, Kernel and User. When in
Kernel mode, the program has complete control and can execute all instructions. Monitors and supervisory programs would be executed in this mode.

When in User mode, the program is prevented from executing certain instructions that could:
1.
2.
3.
4.

Cause the modification of the Kernel program.
Halt the computer.
Use memory space assigned to the Kernel or other users.
Issue a Reset.

4-57

In a multiprogramming environment, several user programs could be resident in memory at any given
time. The task of the supervisory program would be to: controt the execution of the various user
programs, manage the allocation of memory and peripheral device resources, and safeguard the integrity of the system as a whole by careful control of each user program.
In a multiprogramming system, the management unit provides the means for assigning pages (relocatable memory segments) to a user program and preventing that user from making any unauthorized
access to those pages outside his assigned area. Thus, a user can effectively be prevented from accidental or willful destruction of any other user program or the system executive program.
Hardware-implemented features enable the operating system to dynamically allocate memory upon
demand while a program is being run. These features are particularly useful when running higher level
language programs, where, for example, arrays are constructed at execution time. No fixed space is
reserved for them by the compiler. Lacking dynamic memory allocation capability, the program would
have to calculate and allow sufficient memory space to accommodate the worst case. Memory management eliminates this time-consuming and wasteful procedure.
4.12.1.3 Basic Addressing - The addresses generated by all PDP-II family central processor units
(CPUs) are 18-bit addresses. Although the PDP-II family word length is 16 bits, the Unibus and CPU
addressing logic actually is 18 bits. Thus, while the PDP-II word can only contain address references
up to 32K words (64K bytes) the CPU and Unibus can reference addresses up to 128K words (256K
bytes). These extra two bits of addressing logic provide the basic framework for expanding memory
references.
In addition to the word length constraint on basic memory addressing space, the uppermost 4K words
of address space are always reserved for Unibus I/O device registers. In a basic PDP-II memory
configuration (without management), all address references to the uppermost 4K words of 16-bit
address space (160000-177777) are converted to full 18-bit references with bits 17 and 16 always set to
I. Thus, a 16-bit reference to the I/O device register at address 173224 is automatically internally
converted to a full 18-bit reference to the register at address 773224. Accordingly, the basic PDP-ll
configuration can directly address up to 28K words of true memory, and 4K words of Unibus I/O
device registers.
4.12.1.4 Active Page Registers - The memory management unit uses two sets of eight 32-bit Active
Page registers (shown on print KI-7). An APR is actually a pair of 16-bit registers: a Page Address
register (PAR) and a Page Descriptor register (PDR). These registers are always used as a pair and
contain all the information needed to describe and relocate the currently active memory pages (Figure
4-30).
One set of APRs is used in Kernel mode, and the other in User mode. The choice of which set to be
used is determined by the current CPU mode contained in the processor status word.

4-58

KERNEL ACTIVE PAGE REGISTER

o I----+---i
2 I----+---i
3 I----+---i
4 I----+---i
5 I----+---i
6 I----+----i
7 '--_-.L_ _--'
PAR

PDR

USER ACTIVE PAGE REGISTER

o I----+---i
1

2 I----+---i
3 I----+---i
4 I----+---i
5 I----+---i
6 I----+---i
7 '--_-.L_ _--'
PAR

PDR
11- 1396

Figure 4-30

4.12.1.5

Active Page Registers

Capabilities Provided by Memory Management

Memory Size (words)

124K, max (plus 4K for I/O and registers)

Address Space

Virtual (16 bits)
Physical (18 bits)

Modes of Operation

Kernel and User

Stack Pointers

2 (one for each mode)

Memory Relocation
Number of Pages
Page Length

16 (8 for each mode)
32 to 4096 words

Memory Protection

4.12.2

No access
Read-only
Read/write

Relocation

4.12.2.1 Virtual Addressing - When the memory management unit is operating, the normal 16-bit
direct address is no longer interpreted as a direct physical address (BA) but as a virtual address (VBA)
containing information to be used in constructing a new 18-bit physical address. The information
contained in the VBA is combined with relocation and description information contained in the Active
Page register (APR) to yield an 18-bit BA.

4-59

Because addresses are automatically relocated, the computer may be considered to be operating in
virtual address space. This means that no matter where a program is loaded into physical memory, it
will not have to be "relinked"; it always appears to be at the same virtual location in memory.
The virtual address space is divided into eight 4K-word pages. Each page is relocated separately. This
is a useful feature in multiprogrammed timesharing systems. It permits a new large program to be
loaded into discontinuous blocks of physical memory.
A page may be as small as 32 words, so that short procedures or data areas need occupy only as much
memory as required. This is a useful feature in real-time control systems that contain many separate
small tasks. It is also a useful feature for stack and buffer control.
A basic function is to perform memory relocation and provide extended memory addressing capability
for systems with more than 28K of physical memory. Two sets of Page Address registers are used to
relocate virtual addresses to physical addresses in memory. These sets are used as hardware relocation
registers that permit several users' programs, each starting at virtual address 0, to reside simultaneously in physical memory.
4.12.2.2 Program Relocation - The Page Address registers are used to determine the starting address
of each relocated program memory. Figure 4-31 shows a simplified example of the relocation concept
as implemented by the circuitry on print Kl-6.

CPU

MEM MGMT

VIRTUAL
ADDRESS
(VBA)

RELOCATION
CONSTANT

A' 6400
B'100000
PHYSICAL MEMORY

100000

PHYSICAL ADDRESS ( B A)

PROGRAM A

006400

11- 3906

Figure 4-31

Simplified Memory Relocation Example

4-60

Program A, starting address 0, is relocated by a constant to provide physical address 6400s. If the next
processor virtual address is 2, the relocation constant will then cause physical address 6402 s, which is
the second item of Program A, to be accessed. When Program B is running, the relocation constant is
changed to 100000s . Then, Program B virtual addresses, starting at 0, are relocated to access physical
addresses starting at 100000s. Using the Active Page Address registers to provide relocation eliminates
the need to "relink" a program each time it is loaded into a different physical memory location. The
program always appears to start at the same address.
A program is relocated in pages consisting of from 1 to 128 blocks. Each block is 32 words in length.
Thus, the maximum length of a page is 4096 (128 X 32) words. Using all of the eight available Active
Page registers in a set, a maximum program length of 32,768 words can be accommodated. Each of the
eight pages can be relocated anywhere in the physical memory, as long as each relocated page begins
on a boundary that is a multiple of 32 words. However, for pages that are smaller than 4K words, only
the memory actually allocated to the page may be accessed.
The relocation example shown in Figure 4-32 illustrates several points about memory relocation.
1.

Although the program appears to be in contiguous address space to the processor, the 32Kword physical address space is actually scattered through several separate areas of physical
memory. As long as the total available physical memory space is adequate, a program can be
loaded. The physical memory space need not be contiguous.

Pages may be relocated to higher or lower physical addresses with respect to their virtual
address ranges. In the example shown in Figure 4-32, page 1 is relocated to a higher range of
physical addresses, page 4 is relocated to a lower range, and page 3 is not relocated (even
though its relocation constant is non-zero).

All of the pages shown in the example start on 32-word boundaries.

Each page is relocated independently. There is no reason why two or more pages could not
be relocated to the same physical memory space. Using more than one Page Address register
in the set to access the same space would be one way of providing different memory access
rights to the same data, depending on which part of a program was referencing that data.

PROCESSOR

KT11-D

VIRTUAL ADDRESS
RANGES

PAGE RELOCATION
NO.
CONSTANT

PHYSICAL MEMORY
SPACE

160000 - 177776

1500XX

400000

417776

140000 - 157776

0200XX

320000

337776

120000- 137776

1000XX

250000
150000

- 267776
- 167776

100000 - 11 7776

0200XX

060000 - 077776

0600XX

100000

117776

040000 - 057776

2500XX

060000

077776

3200 XX

020000

037776

4000XX

020000- 037776
000000- 017776

11-1398

Figure 4-32

Relocation of a 32K Word Program into
124K-Word Physical Memory
4-61

4.12.2.3

Memory Units

Block
Page
No. of Pages
Size of Relocatable Memory

32 words
1 to 128 blocks (32 to 4096 words)
8 per mode
27,768 words max (8 X 4096)

4.12.3 Protection
A timesharing system performs multiprogramming; it allows several programs to reside in memory
simultaneously, and to operate sequentially. Access to these programs, and the memory space they
occupy, must be strictly defined and controlled. Several types of memory protection must be afforded
a timesharing system. For example:
1.

User programs must not be allowed to expand beyond allocated space, unless authorized by
the system.

Users must be prevented from modifying common subroutines and algorithms that are resident for all users.

Users must be prevented from gaining control of or modifying the operating system
software.

The memory management option provides the hardware facilities to implement all of the above types
of memory protection.
4.12.3.1 Inaccessible Memory - Each page has a 2-bit access control key associated with it. The key is
assigned under program control. When the key is set to 0, the page is defined as non-resident. Any
attempt by a user program to access a non-resident page is prevented by an immediate abort. Using
this feature to provide memory protection, only those pages associated with the current program are
set to legal access keys. The access control keys of all other program pages are set to 0, which prevents
illegal memory references.
4.12.3.2 Read-Only Memory - The access control key for a page can be set to 2, which allows read
(fetch) memory references to the pages, but immediately aborts any attempt to write into that page.
This read-only type of memory protection can be afforded to pages that contain common data, subroutines, or shared algorithms. This type of memory protection allows the access rights to a given
information module to be user-independent. That is, the access right to a given information module
may be varied for different users by altering the access control key.
A Page Address register in each of the sets (Kernel and User modes) may be set up to reference the
same physical page in memory and each may be keyed for different access rights. For example, the
User access control key might be 2 (read-only access), and the Kernel access control key might be 6
(allowing complete read/write access).
4.12.3.3 Multiple Address Space - There are two complete, separate PAR/PD R sets provided: one set
for Kernel mode and one set for User mode. This affords the timesharing system with another type of
memory protection capability. The mode of operation is specified by the processor status word current
mode field, or previous mode field, as determined by the current instruction.

4-62

Assuming the current mode PSW bits are valid, the Active Page register sets are enabled as follows:
PSW (Bits 15,14) PAR/PDR Set Enabled
00

Kernel mode

}

Illegal (all references aborted on access)

User mode

Thus, a User mode program is relocated by its own PAR/POR set, as are Kernel programs. This
makes it impossible for a program running in one mode to accidently reference space allocated to
another mode when the Active Page registers are set correctly. For example, a user cannot transfer to
Kernel space. The Kernel mode address space may be reserved for resident system monitor functions,
such as the basic input/output control routines, memory management trap handlers, and timesharing
scheduling modules. By dividing the types of timesharing system programs functionally between the
Kernel and User modes, a minimum amount of space control housekeeping is required as the timeshared operating system sequences from one user program to the next. For example, only the user
PAR/PDR sets needs to be updated as each new user program is serviced. The two PAR/POR sets
implemented in the memory management unit are shown in Figure 4-30.
4.12.4 Active Page Registers
The memory management unit provides two sets of eight Active Page registers (APRs). Each APR
consists of a Page Address register (PAR) and a Page Descriptor register (POR). These registers are
always used as a pair and contain all the information required to locate and describe the current active
pages for each mode of operation. One PAR/POR set is used in Kernel mode and the other is used in
User mode. The current mode bits (or in some cases, the previous mode bits) of the processor status
word determine which set will be referenced for each memory access. A program operating in one
mode cannot use the PAR/POR sets of the other mode to access memory. Thus, the two sets are a key
feature in providing a fully protected environment for a timesharing multiprogramming system.
A specific processor I/O address is assigned to each PAR and POR of each set. Table 4-12 is a
complete list of address assignments.
NOTE
Unibus devices (except DMA and programmer's
console) cannot access PARs or PDRs. The internal
address decode logic (print KI-I0) allows only the
processor to access these registers.
Table 4-12

PAR/PDR Address Assignments

Kernel Active Page Registers

User Active Page Registers

No.

PAR

PDR

No.

PAR

PDR

0
1
2
3
4
5
6
7

772340
772342
772344
772346
772350
772352
772354
772356

772300
772302
772304
772306
772310
772312
772314
772316

0
1
2
3
4
5
6
7

777640
777642
777644
777646
777650
777652
777654
777656

777600
777602
777604
777606
777610
777612
777614
777616

4-63

In a fully protected, multiprogramming environment, the implication is that only a program operating
in the Kernel mode would be allowed to write the PAR and PDR locations for the purpose of mapping
user's programs. However, there are no restraints imposed by the logic that will prevent User mode
programs from writing into these registers. The option of implementing such a feature in the operating
system, and thus explicitly protecting these locations from user's programs, is available to the system
software designer.
4.12.4.1 Page Address Registers (PAR) - The Page Address register (PAR), shown on print KI-7 and
1 in Figure 4-33 contains the 12-bit Page Address Field (PAF) that specifies the base address of the
page.

PAGE ADDRESS FIELD
(PAF)
11-1036

Figure 4-33

Page Address Register

Bits 15-12 are unused and reserved for possible future use.
The Page Address register may be alternatively thought of as a relocation constant, or as a base
register containing a base address. Either interpretation indicates the basic function of the Page
Address register (PAR) in the relocation scheme.
The Page Address register (PAR) may be regarded as either a base register containing a base address or
a relocation constant. Bits are fed directly from the SSMUX to an address selected by the PAR/PDR
ADRS MUX (E89 on print KI-7) when enabled by KI-10 PAR & PDR LOW L. The three scratchpad
memories that comprise the PAR (E76, E77, and E78 on print KI-7) are clocked by KI-5 REG CLK
H. The two associated with PAR 03:00 and PAR 07:04 are enabled by KI-10 LOAD PAR LOW L,
while the other (PAR 11:08) is enabled by KI-I0 LOAD PAR HIGH L. Outputs of the PARs are fed
directly to the KTMUX on print KI-9, and can be channeled onto the scratchpad output lines
(SPI5:00) when Kl-IO PAR & PDR L is asserted and Kl-IO KTMUX SO L is unasserted. This allows
the contents of the registers to be accessed by a DATI or DA TIP.
4.12.4.2 Page Descriptor Registers - The Page Descriptor register (PDR) comprises four scratchpad
memories (E79, E86, E87, and E88 on print K 1-7) and contains information regarding page expansion,
page length, and access control (Figure 4-34). Bits are fed directly from the SSMUX to an address
selected by the PAR/PDR ADRS MUX (E89 on print KI-7) and clocked by Kl-5 REG CLK H.

PAGE LENGTH FIELD
(PLF)
WRITTEN INTO
EXPANSION DIRECTION
ACCESS CONTROL FIELD

Figure 4-34

Page Descriptor Register
4-64

Access Control Field (ACF)
This 2-bit field (PDR 02:01) of the PDR describes the access rights to the specified page. The access
codes or "keys" [K 1-7 ACF 2 (l) Hand K 1-7 ACF 1 (1) H from E86] specify the manner in which a
page may be accessed and whether or not a given access should result in an abort of the current
operation. A memory reference that causes an abort is not completed and is terminated immediately.
Aborts are caused by attempts to access non-resident pages, page length errors, or access violations,
such as attempting to write into a read-only page. All memory management traps vector through
location 250 and can be used as an aid in gathering memory management information.
In the context of access control, the term "write" is used to indicate the action of any instruction which
modifies the contents of any addressable word. A "write" is synonymous with what is usually called a
"store" or "modify" in many computer systems. Table 4-13 lists the four ACF keys and their functions. The ACF is written into the PDR under program control.
Table 4-13

Access Control Field Keys

ACF

Key

Description

Function

Non-resident

Abort any attempt to access this non-resident page.

Resident read-only

Abort any attempt to write into this page.

Unused

Abort all accesses.

Resident read/write

Read or write allowed. No trap or abort occurs.

Expansion Direction (ED)
The ED bit located in PDR bit 3 indicates the authorized direction in which the page can expand. A
logic 0 in this bit (ED = 0) indicates the page can expand upward from relative zero. A logic 1 in this
bit (ED = I) indicates the page can expand downward toward relative zero. The ED bit is written into
the PDR under program control. When the expansion direction is upward (ED = 0), the page length is
increased by adding blocks with higher relative addresses. Upward expansion is usually specified for
program or data pages to add more program or table space. An example of page expansion upward is
shown in Figure 4-35.
When the expansion direction is downward (ED = 1), the page length is increased by adding blocks
with lower relative addresses. Downward expansion is specified for stack pages so that more stack
space can be added. An example of page expansion downward is shown in Figure 4-36.
NOTE
To specify a block length of 42 for an upward-expandable page, write the highest authorized block number directly into the highest byte of PDR. Bit 15 is
not used because the highest allowable block number
is 1778 ,

4-65

PAR

PDR

1 000 001 111 000

10 0101001 0000 0110

PLF=51 8 =41 1O =BLOCK N O . - -

ED=O=UPWARDEXPANSION

PAF=OI~

ACF=6= READ/WRITE
NOTE'
TO SPECIFY A BLOCK LENGTH OF 42 FOR AN UPWARD EXPANDABLE
PAGE, WRITE HIGHEST AUTHORIZED BLOCK NO. DIRECTLY INTO HIGH
BYTE OF PDR. BIT 15 IS NOT USED BECAUSE THE HIGHEST ALLOWABLE BLOCK
NUMBER IS 1778
VIRTUAL ADDRESS BLOCK NO> PDR BLOCK NO.-PAGE LENGTH ERROR (PLE)

ANY BLOCK NUMBER
GREATER THAN 4110 (51 8 )

ADDRESS RANGE
OF POTENTIAL PAGE
EXPANSION BY
CHANGING THE PLF

(VA<12:06»

024176
BLOCK 518
024100

AUTHORIZED PAGE
LENGTH = 4210 BLOCKS
OR 0 THRU 518=
528 BLOCKS

I
Figure 4-35

51 8 )

WILL CAUSE A PAGE
LENGTH ABORT.

0170XX
51
0241 XX

START
BLOCKS
END

017276
BLOCK 2
017200
017176
BLOCK 1
017100
017076
BLOCK 0
017000

BASE ADDRESS OF PAGE
11-1030

Example of an Upward-Expandable Page

4-66

r--ACTIVE PAGE REGISTER CONTENTS--1
PAR
1000001111 000

PDR
101010110 0000

110

PAF: 0170 _ _ _....1

PLF: 1268: 8610 - - - - - - - - - - - '
ED: 1: DOWNWARD EXPANSION - - - - - - - - - - - '

TO SPECIFY PAGE LENGTH FOR A DOWNWARD EXPANDABLE PAGE,
WRITE COMPLEMENT OF BLOCKS REQUIRED INTO HIGH BYTE OF PDR.
IN THIS EXAMPLE,A 42-BLOCK PAGE IS REQUIRED.
PLF IS DERIVED AS FOLLOWS:
4210 : 528 ; TWO'S COMPLEMENT: 126 8
VIRTUAL ADDRESS BLOCK NO. <PDR BLOCK NO.- PAGE LENGTH

036776
BLOCK 1778

}

ERROR (PLE)

FIRST BLOCK OF DOWNWARD
EXPANDABLE PAGE

036700
036676
BLOCK 1768
036600
AUTHORIZED PAGE
LENGTH: 4210 BLOCKS

BLOCK

036576
1758
036500

0170XX
126
0316XX
52
0367XX

031676
BLOCK 1268
031600

PAGE BASE
BLOCKS
START
BLOCKS
END

A BLOCK NUMBER
REFERENCE LESS
THAN 1268
(VA <12:06> LESS THAN 1268)
WILL CAUSE A PAGE
LENGTH ABORT.

ADDRESS RANGE
OF POTENTIAL PAGE
E X PANS ION BY
C HAN GIN G THE P L F 1R'.,m.7*:~.,m.7*:~

BASE ADDRESS OF PAGE
11-1031

Figure 4-36

Example of a Downward-Expandable Page

4-67

Written Into (W)
The W bit located in PDR bit position 6 indicates whether the page has been written into since it was
loaded into memory. W = 1 is affirmative. The W bit is automatically cleared when the PAR or PDR
of that page is written into. It can only be set by the control logic (print K 1-7). In disk-swapping and
memory overlay applications, the W bit can be used to determine which pa:ges in memory have been
modified by a user. Those pages that have been written into must be saved in their current form; those
that have not been written into (W = 1) need not be saved, and can be overlaid with new pages, if
necessary.
Page Length Field
The 7-bit page length field (PLF) located in PDR bits 14:08 specifies the authorized length of the page
in 32-word blocks. The PLF holds block numbers from 0 to 177 8, thus allowing any page length from 1
block to 128 blocks. The PLF is enabled by Kl-IO LOAD PDR HIGH L, ~nd written into the PDR
under program control.
PLF for an Upward-Expandable Page
When the page expands upward (ED = 0), the PLF must be set to one less than the intended number of
blocks authorized for that page. Thus, if the number of blocks authorized is 528 or 4210, the PLF is set
to 518 or 41 10 , with block 0 being the page boundary and the first block of the page. A comparator
network (E60 and E61 on print KI-8) compares the virtual address block number (VBA 12:06) with
the PLF to determine whether the VBA is within the authorized page length. If the VBA block number
is less than (A < B) or equal to (A = B) the PLF, the VBA is within the authorized page length. If the
VBA block number is greater than (A > B) the PLF, a page length fault is detected by the hardware
and KI-8 KT FAULT L is issued to the DAT TRAN circuitry on print K2-1, where it generates K2-1
ENAB ABORT H, causing a trap. When the expansion direction is upward, the page length is
increased by adding blocks with higher relative addresses. Upward expansion is usually specified for
program or data pages to add more program or table space (Figure 4-35).
PLF for a Downward-Expandable Page
The capability of providing downward expansion for a page is intended specifically for those pages
that are to be used as stacks. In the PDP-II /34, a stack starts at the highest location reserved for it,
and expands downward toward the lowest address as items are added to the stack. If the page is to be
downward-expandable, the PLF must be set to authorize a page length (in blocks) that starts at the
highest address of the page, which is always block 177 8. The rationale for complementing the number
of blocks required to obtain the PLF is as follows:
Maximum Block No. Minus PLF

Required Length Equals
~

IL'

1778 = 528 = 1258
127 10 = 4210 = 8510

Figure 4-36 contains an example of a downward-expandable page. A page length of 42 blocks is
arbitrarily chosen to match the upward-expandable example shown in Figure 4-35.
NOTE
The same PAF is used in both examples. This is done
to emphasize that the P AF, as the base address,
always determines the lowest address of the page,
whether it is upward- or downward-expandable.

4-68

4.12.5 Virtual and Physical Addresses
The memory management Unibus addressing circuitry is shown on print Kl-6. When memory management is enabled (Kl-8 RELOCATE H asserted), the processor ceases to load Unibus addresses
directly from the scratchpad via the Bus Address register multiplexer latches (E43, E54, and E64).
Instead, addresses are relocated by various constants obtained from the memory management circuitry. (Selected PAR contents are added to the VBA using adders E44, E55, and E65.)
4.12.5.1 Construction of a Physical Address - The basic information needed for the construction of a
physical address (PA) comes from the virtual address (VBA), which is illustrated in Figure 4-37, and
the appropriate PAR set.

APF

ACTIVE PAGE FIELD

DISPLACEMENT FIELD
11-3908

Figure 4-37

Interpretation of a Virtual Address

The virtual address (VBA) consists of:
1.

The Active Page Field (APF). This 3-bit field determines which of eight Active Page registers
(APRO-APR7) will be used to form the physical address (BA). The PAR/PDR ADRS
M UX (E89 on print K 1-7) actually selects the specific PAR.

The Displacement Field (OF). This l3-bit field contains an address relative to the beginning
of a page. This permits page lengths up to 4K words (2 13 = 8K bytes). The OF is further
subdivided into two fields as shown in Figure 4-38.

DIB

BLOCK NUMBER

DISPLACEMENT IN BLOCKS
11-3909

Figure 4-38

Displacement Field of Virtual Address

The displacement field (OF) consists of:
1.

The Block Number (BN). This 7-bit field is interpreted as the block number within the
current page.

The Displacement in Block (DIB). This 6-bit field contains the displacement within the
block referred to by the block number.
4-69

The remainder of the information needed to construct the physical address comes from the l2-bit page
address field (PAF) (part of the Active Page register) and specifies the starting address of the memory
which that APR describes. The PAF is actually a block number in the physical memory, e.g., PAF = 3
indicates a starting address of 96 (3 X 32 = 96) words in physical memory.
The formation of the physical address is illustrated in Figure 4-39.

APF

~.~~

6
BLOCK

NO.

1 VIRTUAL

DIB

ADDRESS

0
ACTIVE PAGE
REGISTER

PAGE ADDRESS FIELD

·0
17

+
PHYSICAL BLOCK

NO.

1------ --I

DIB
I

PHYSICAL
ADDRESS

{DISPLACEMENT IN BLOCKS 1
" -3907

Figure 4-39

Construction of a Physical Address

The logical sequence involved in constructing a physical address is as follows:
I.

Select a set of Active Page registers depending on current mode.

The active page field of the virtual address is used to select an Active Page register (APROAPR7).

The page address field of the selected Active Page register contains the starting address of
the currently active page as a block number in physical memory.

The block number from the virtual address is added to the block number from the page
address field to yield the number of the block in physical memory which will contain the
physical address being constructed.

The displacement in block from the displacement field of the virtual address is joined to the
physical block number to yield a true l8-bit physical address.

4.12.5.2 Determining the Program Physical Address - A l6-bit virtual address can specify up to 32K
words, in the range from 0 to 177776 (work boundaries are even octal numbers). The three most
significant virtual address bits designate the PARjPD R set to be referenced during page address relocation. Table 4-14 lists the virtual address ranges that specify each of the PARjPDR sets.

4-70

Table 4-14 Relating Virtual Address to PARjPDR Set
Virtual Address Range

PARjPDRSet

000000-17776
020000-37776
040000-57776
060000-77776
100000-117776
120000-137776
140000-157776
160000-177776

o
1
2

3
4
5
6
7

NOTE
Any use of page lengths less than 4K words causes
holes to be left in the virtual address space.

4.12.6 Status Registers
Aborts generated by the protection hardware are vectored through Kernel virtual location 250. Status
registers SRO and SR2 are used to determine why the abort occurred. Note that an abort to a location
which is itself an invalid address will cause another abort. Thus the Kernel program must ensure that
Kernel virtual address 250 is mapped into a valid address; otherwise a loop will occur which will
require console intervention.
4.12.6.1 Status Register 0 (SRO) - SRO contains abort error flags, memory management enable, plus
other essential information required by an operating system to recover from an abort or service a
memory management trap. The SRO format is shown in Figure 4-40. Its address is 777572. Circuitry
used to implement the SRO register is shown on print Kl-S.

---.t~

ABORT- NON-RESIDENT
ABORT-PAGE LENGTH ERROR
ABORT-READ ONLY
ACCESS VIOLATION
MAINTENANCE MODE
MODE
PAGE NUMBER
ENABLE MANAGEMENT

SRfiJ

Figure 4-40

I
~

ADDRESS
777572

Format of Status Register 0 (SRO)

4-71

11-3911

Bits 15-13 are the abort flags. They may be considered to be in a "priority queue" in that flags to the
right are less significant and should be ignored. For example, a "non-resident" abort service routine
would ignore page length and access control flags. A "page length" abort service routine would ignore
an access control fault.
NOTE
Bit 15, 14, or 13, when set (abort conditions), causes
the logic (E121 generates KI-8 ERROR H) to freeze
the contents of SRO bits 1 to 6 and status register
SR2. This is done to facilitate recovery from the
abort.
Protection is enabled when an address is being relocated (K 1-8 RELOCATE H is active). This implies
that either SRO, bit 0, is equal to 1 (memory management enabled) or that SRO, bit 8, is equal to 1 and
the memory reference is the final one of a destination calculation (maintenance/destination mode).
Note that SRO bits 0 and 8 can be set under program control to provide meaningful memory management control information. However, information written into all other bits is not meaningful. Only
that information which is automatically written into these remaining bits as a result of hardware
actions is useful as a monitor of the status of the memory management unit. Setting bits 15-13 under
program control will not cause traps to occur. These bits, however, must be reset to 0 after an abort or
trap has occurred in order to resume monitoring memory management.
Abort-Non-Resident
Bit IS is the Abort-Non-Resident bit [KI-8 NR (I) H].1t is set by attempting to access a page with an
access control field (ACF) key equal to 0 or 4 or by enabling relocation with an illegal mode in the
PSW.
Abort-Page Length
Bit 14 is the Abort-Page Length bit [KI-8 PL (1) H]. It is set by attempting to access a location in a
page with a block number (virtual address bits 12-6) that is outside the area authorized by the page
length field (PFL) of the PDR for that page.
Abort-Read-Only
Bit 13 is the Abort-Read-Only bit [KI-8 RO (1) H]. It is set by attempting to write in a read-only page
having an access key of 2.
NOTE
There are no restrictions that any abort bits could
not be set simultaneously by the same access
attempt.
Maintenance/Destination Mode
Bit 8 specifies maintenance use of the memory management unit. It is used for diagnostic purposes.
F or the instructions used in the initial diagnostic program, bit 8 is set so that only the final destination
reference is relocated. It is useful to prove the capability of relocating addresses, in destination mode
only.
Mode of Operation
Bits 5 and 6 indicate the CPU mode (User or Kernel) associated with the page causing the abort
(Kernel = 00, User = 11).

4-72

Page Number
Bits 3-\ contain the page number of reference. Pages, like blocks, are numbered from 0 upward. The
page n umber bit is used by the error recovery routine to identify the page being accessed if an abort
occurs.
Enable Relocation and Protection
Bit 0 is the Enable bit. When it is set to 1, all addresses are relocated and protected by the memory
management unit. When bit 0 is set to 0, the memory management unit is disabled and addresses are
neither relocated nor protected.
4.12.6.2 Status Register 2 (SR2) - SR2 (shown on print KI-9) is loaded with the 16-bit virtual address
(VBA) at the beginning of each instruction fetch but is not updated if the instruction fetch fails. SR2 is
read-only; a write attempt will not modify its contents. SR2 is the virtual address program counter.
Upon an abort, the result of SRO bits 15, 14, or 13 being set will freeze SR2 until the SRO abort flags
are cleared. The address of SR2 is 777576 (Figure 4-41).

16-BIT VIRTUAL ADDRESS

~----------------------------------------------~

Figure 4-41

ADDRESS

. 777576
11-3910

Format of Status Regiser 2 (SR2)

4.12.7 Mode Description
In Kernel mode, the operating program has unrestricted use of the machine. The program can map
users' programs anywhere in core and thus explicitly protect key areas (including the device registers
and the processor status word) from the user operating environment.
In User mode, a program is inhibited from executing a Halt instruction and the processor will trap
through location 10 if an attempt is made to execute this instruction. A Reset instruction results in
execution of a NOP (no-operation) instruction.
There are two stacks, called the Kernel stack and the User stack, used by the central processor when
operating in either the Kernel or User mode, respectively.
Stack limit violations are disabled in User mode. Stack protection is provided by memory protect
features.
4.12.8 Interrupt Conditions
The memory management unit relocates all addresses. Thus, when management is enabled, all trap,
abort, and interrupt vectors are considered to be in Kernel mode virtual address space. When a vectored transfer occurs, control is transferred according to a new program counter (PC) and processor
status word (PSW) contained in a 2-word vector relocated through the Kernel Active Page register set.
When a trap, abort, or interrupt occurs, the "push" of the old PC (old PSW) is to the User/Kernel R6
stack specified by CPU mode bits 15 (14) of the new PSW in the vector (00 = Kernel, 11 = User). The
CPU mode bits also determine the new APR set. In this manner it is possible for a Kernel mode
program to have complete control over service assignments for all interrupt conditions, since the
interrupt vector is located in Kernel space. The Kernel program may assign the service of some of these
conditions to a User mode program by simply setting the CPU mode bits of the new PSW in the vector
to return control to the appropriate mode.
4-73

User Processor Status (PS) operates as follows:
PSW Bits

User RTI, RTT

User Traps,
Interrupts

Explicit
PSW Access

Condo Codes (3-0)

Loaded from stack

Loaded from vector

Trap (4)

Loaded from stack

Loaded from vector

Priority (7-5)

Cannot be changed

Loaded from vector

Previous (13-12)

Cannot be changed

Copied from PS (15, 14)

Current (15-14)

Cannot be changed

Loaded from vector

*
Cannot be changed

*Explicit operations can be made if the processor status is mapped in user space.

4.13

CONTROL STORE

4.13.1 General Description
The Control Store circuit (prints K2-7 through K2-10) consists of twelve 512-word by 4-bit bipolar
ROMs, eight hex D-type flip-flops, and an assortment of multiplexers and gates. This logic operates in
a fashion similar to a microprocessor having 9 address lines and 48 data output lines with a fixed set of
ROM program routines.
Each Control Store ROM location can generate a specific set of outputs capable of configuring the
data path, determining the function performed by the arithmetic/logic unit (ALU), influencing the
o AT TRAN circuitry, or exercising general control over the total KD 11-E operation. The contents of
each location are configured in such a way that sequences of locations can be combined into microroutines that perform the various PDP-ll instruction operations. Each ROM location is, therefore,
considered as a microinstruction or microstep.
4.13.2 Branching Within Microroutines
Each microinstruction in the Control Store specifies the location of the next microstep in a sequence.
After the execution of a microstep, the outputs of ROMs E107, EI08, and E109 are latched into E89
and E91 (microprogram counter latch) to specify the location of the next microstep. Conditional
branching within a microroutine is accomplished by wire-ORing signals generated by external hardware onto the MPC lines when directed by some other Control Store output. Typical wire-O Red
signals include the following:
I nstruction Decode

The microroutines contained in the Control Store are designed
to perform efficiently the operations specified by the various
PDP-II instructions. Specific microroutines are implemented
for specific instructions. The main purpose of the IR Decode
circuitry is to translate the PDP-II instruction in the IR to a set
of bits that can be wire-ORed onto the MPC lines upon request
(IR DECODE L), developing the next control word. A description of the specific addresses for each instruction is included in
Paragraph 4.5.3 of this manual.

4-74

Trap Decode

A routine has also been included in the Micro Store to implement an error routine that pushes and pops the PC and PSW
onto or off the processor stack. Upon request of the Control
Store [K2-9 BUT SERVICE (1) H], the MPC 00 line can be
enabled by the Service ROM (E50), causing a microbranch to
this microroutine.

PWR Restart

Upon performing a power restart, the MPC is cleared by an
Initialize signal (lNIT). The power-up circuitry on print K2-3
then enables the MPC 00 line, forcing the Control Store to perform the power-up routine beginning at MPC address 001.

In general, microsteps are not executed from numerically sequential locations in the Control Store;
therefore, care should be taken in following the flows described in Chapter 5 of this manual.
Figure 4-42 shows the format of all 512 words in the KDll-E Control Store. The fields, the possible
values they contain, and the significance of each value are described below.

1::l:~1

'--y------J
BUS
CONTROL

OVX

DBE

I I

I'-----y----J'--y------J

I~~{~I

CONTROL

ALU
32

MISC
CONTROL

I. LOAD
ILONG I AUX I
BAR . CYCLE. CONT .
\.

MPC
16

SSMUX
CONTROL

AMUX
CONTROL

~----~v~------~

SPA DEST
SEL

FORCE
KERNEL

ROM
SPA
11-4252

Figure 4-42

Control Store Fields

4-75

4.13.3 Control Store Fields
Use the KD Il-E flow diagrams as reference for actual control field bit patterns.
Field

Field Length

Description

MPC

Nine-bit micro-PC address, which specifies the ROM location of the next microstep to be performed.

Miscellaneous

Control

Three multiplexed control lines that generate the following
enable signals:
LOAD IR L - Allows loading of the Instruction register
(print K2-5).
LOAD PSW L - Allows the PSW register to be loaded upon
completion of this microstep (prints K I-I through K 1-4).
LOAD CC L - Allows the condition codes N, Z, V, and C to
be loaded upon completion of this microstep (print KI-I).
BUT DEST L - Enables micro branch to destination operand
microcode sequence (print K2-6).
ENAB STOV L - Enables the stack overflow detection circuit (print K2-3).
LOAD COUNT L - Allows the counter circuit (print K2-1 0)
to be loaded upon completion of this microstep.
CLK COUNT L - Enables the counter clock circuit (print
K2-10).

BUF DATTRAN 1

Enables the data transfer circuitry (print K2-1). Indicates that
the processor is performing a Unibus transfer during this
microstep.

Enables the Unibus control lines BUS CO L and BUS Cl L,
as follows:

Bus Control

Cl (1) H

CO (1) H

Transfer

o
o

DATI
DATIP
DATO
DATOB

I
I

o
1

ENAB MAINT

Enables the memory management maintenance relocation
feature.

LOAD BAR

Allows the Physical Bus Address register (BA on print KI-6)
to be loaded during this microstep.

4-76

Field

Field Length

Description

LONG CYCLE

Forces the processor to perform a longer (240 ns) machine
cycle during this microstep. Typically this is done during bus
DATOs.

AUX CONTROL 1

Enables the Auxiliary Control ROMs during operate instruction microsteps.

ALU S3-ALU SO 5
ALU MODE,
ALU CIN
BLEG 01:00

Determine the operation performed by the 16-bit ALU
according to Table 4-2. These lines are also wire-ORed,
allowing the Auxiliary Control circuitry to determine the
ALU operations according to Table 4-2.

B, BX, OVX,
4
DBE, CONTROL

These multiplexed outputs control the operation of the B register and BX register during each micro step and detect overflow or double bus errors.

SSMUX
CONTROL

Controls the select lines of the SSMUX according to the
following:

Select
Straight
Sign Extend
Swap Bytes
External Data
AMUX
CONTROL

SSOIH

SSOOH

0
0
1

0
1
0

Controls the select lines of the AMUX according to the
following:
Data

AMUXSI

AMUXSO

PSW
ALU
Vector
Unibus

0
0

0
1

BUT BITS

Encoded control lines that select the specific micro branch
condition that can occur during this microstep.

SPA SRC SEL

Controls the select lines of the scratchpad address multiplexer
during the first half of this microstep.
Field Select
ROM
RS
RD
RBA

SELl

SELO

1
1

4-77

Field

Field Length

Description

SPA DSTSEL

Controls the select lines of the scratchpad address multiplexer
during the second half of this microstep.
Field Select
ROM
RS
RD
RBA

SEL 1

SELO

o
o
1

o
1
o

FORCE RSVI

Controls which source register will be selected by the scratchpad address multiplexer. If RS = is an even-numbered register, then RSVI = Register 1. If, however, RS = an oddnumbered register, then RSVI = the same register.

PREVIOUS
MODE

Allows the processor to perform this micro step using the previous memory management mode [PSW (13:12)].

BUT SERVICE

Indicates that the processor has entered the Service microstep. Enables the Service ROM (E50), causing the processor
to recognize any pending errors or interrupts.

Force Kernel

Forces the processor to perform this micro step in the memory management Kernel mode.

ROM SPA

Allows the microinstructions from the Control Store to determine which scratchpad register will be addressed during the
next microstep, unless otherwise specified by the scratch pad
address multiplexer control lines previously mentioned.

4-78

CHAPTER 5
MICROCODE

5.1 MICROPROGRAM FLOWS
A complete set of microinstruction flows is shown in block diagram form in the KDII-E print set.
Figure 5-1 is a simplified version that provides an overview and aids in using the detailed flows. No
attempt will be made in this manual to trace each path of this microcode, but the following examples
should provide an adequate background for the reader.
5.2 FLOW NOTATION GLOSSARY
The block flows should be self-explanatory. To aid in understanding them, the following glossary of
flow notation should be reviewed.
Designation

Definition

Unibus Bus Address lines
Minus the operator
Separator
Initiate DATI operation on Unibus
Plus the arithmetic operator
Program Counter = scratchpad register 7 (R 7)
B register
Instruction register
BX register
Scratch pad register specified by the source portion of the current instruction
[IR (08:06)]
Scratch pad register specified by the destination portion of the current
instuction [IR (02:00)]
Scratchpad register n specified by the Control Store ROM SPA lines
Enable the stack overflow detection logic
Enable the double bus error detection logic.
Initiate DATa operation on Unibus.
Initiate DA TIP operation on Unibus.
ALU function determined by the auxiliary ALU control logic as a function
of the instruction currently in the Instruction register.
Branch on microtest.
Set condition codes (N, Z, V and C) according to the result of operation
being performed by the ALU.
Data being received from the Unibus data lines BUS DOO L through BUS
DIS L.
Source register specified by source portion of current instuction [IR (08:06)]
ORed with a logical 1. Example: If RS is even, RSVI would be the next
highest register (RS = 4, RSVI = 5); if, however, RS is odd, RSVI would be
the same register (RS = 5, RSVI = 5).
Assignment operator.
Indicates that the memory management Maintenance feature is enabled.
Indicates that this microstep is using the previous memory management
mode.

DATI

PC
B
IR
BX
RS
RD
RN
ENAB STOV
ENAB DBE
DATa
DATIP
Rn OP B
BUT
LOAD CC
UDATA
RSVI

MAINT
Previous

5-1

RESTART
FROM
PWR FAIL

~
1
I

FETCH

f
TRAP

WAIT

~
DECODE

MFPI {DJ

MTPS

f--

JMP

RESET

I--

CHANGE PC ~

MOV
rSM0-DM0 ..

I--ASH/ASHC I--

I-

CLEAR CC

f--

MARK

DOP
f- (MOV-SUB) j4MOD
SMf/)-DM0

I-- ROT/SHFT f--

f- RTI I RTT I--

SET CC

j4-

I-

NEG

I--

DOP
f- NON MOD ~
SM0-DM0

I--

r- SM0-DM0 I--

MTPI {DJ I-

MFPS

r- MULl DIV

BRANCH

SWAB

JSR

RTS

I--

SOB

SUB

SOP MOD

MOV DEST
SMC/J-DM0

DOP
SM0-DM0

SOP
NON MOD

L-

DEST

I-

DOP DEST

I-

DOP DEST
NON MOD

MOV-SUB

I
11 -3879

Figure 5-1

KDll-E Simplified Flow Diagram