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DEC-8L-D0BA-D

April 1969

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Document:	KP8L Power Failure Option Functional Description Apr69
Order Number:	DEC-8L-D0BA-D
Revision:	0
Pages:	6
Original Filename:	DEC-8L-D0BA-D_KP8L_Power_Failure_Option_Functional_Description_Apr69.pdf

OCR Text

DEC-8L-DOBA-D

KP8IL

POWER FAILURE
|

OPTION

FUNCTIONAL DESCRIPTION

DIGITAL EQUIPMENT CORPORATION o MAYNARD, MASSACHUSETTS

1st Printing April 1969

KP8|L
POWER FAILURE

crease in the +5V dc voltage, and generate
a low logic level, SHUTDOWN. This

signal sets the KP8/L PWR LOW flag flip-flop
(Drawing D-BS-KP8L-0-1). PWR Low (0)

generates INTRQST (Drawing D-BS-PDP8-L10). Aprogram interrupt occurs if the proces-

FUNCTIONAL DESCRIPTION

INTRODUCTION

The KP8/L Power Failure Option causes an

interrupt signal to the PDP-8/L computer,

allowing computer operation for a fixedtime after a primary power interruption.

With proper programming, an interrupt from

the KP8/L insures data storage of the several

machine registers of interest (accumulator,
link, program counter, etc.) in core memory. When the option is enabled, restoration of power restarts the computer at memory location 0000g, after a suitable delay,
to allow for voltage stabilization. A program subroutine, entered when power returns,
places the previously stored data back in
their proper registers. The option can be
disabled to prevent restart.

The KP8/L Option consists of an M703
Integrated-Circuit module partially con-

trolled by the PDP-8/L G826 Regulator and
Power Detector module. Both modules are
contained within the processor logic frame.

LOGIC DESCRIPTION

The following paragraphs describe the
sequence of events that occurs when power
is interrupted. The basic power-fail programming technique is also described.
When primary power is removed, detection

circuits in the G785 module and G826

module (Regulator and Power Detector,
Drawing D-BS-PDP8-L-13) react to a de-

sor interrupt facility is enabled. The interrupt is effected in the usual manner with a
search subroutine using the octal instruction
6102 (SPL, Skip on Power Low) to enable the
PWR SKIP gate signal to locate the interrupting source. The PWR SKIP gate is enabled
by PWR LOW (1), the power-fail device
selection code (10g, from MBO3 through
MBO8), and the interrogation timing signal

IOP2(1). PWR SKIP generates I/O SKIP

(Drawing D-BS-PDP8-L-10) which allows
entry into the power fail service subroutine
(Figure 1). The service subroutine stores the
contents of the AC, Link, and PC in core

memory. Also, any critical information that

might be lost in a power failure is transferred
first to the AC, and then into core memory
during this subroutine. When a program
interrupt occurs, and the interrupt facility is
enabled, the contents of the PC are automatically stored in location 0000g. Because
location 0000g is used later with the restart
program, this content (PC word) is then relocated in memory. Finally, a JMP instruction to address X is stored in location 0000g,
and the HLT instruction is executed. Address
X is the starting location of the restart program. The HLT instruction must be included
in the power fail service routine following

the instructions that store the contents of the

registersafter all register storage has occurred.

Adequate time for search and execution of

the above subroutine is provided by the 1-ms
single-shot delay activated by the SHUT
DOWN signal.

The activated low output,

STOP OK, inhibits the Regulator Control
of the G826 module from initiating the
normal machine down cycle.

After the 1-ms
the

delay, the STOP OK signal goes high;

PROGRAM
IN OPERATION

POWER
INTERRUPTION

INTERRUPT
ON

YES

ENTER DEVICE

POWER FAIL SUBROUTINE NOT ENTERED.

"SEARCH"

THE REGISTER CONTENTS ARE NOT
SAVED. PROGRAM HAS TO BE MANUALLY

SUBROUTINE

RESTARTED FROM BEGINNING.

SKIP
NO

‘

YES

6102 INST.

THE PROGRAM CONTINUES FLAG CHECKING.

NOTE:

INSTRUCTION;
RESPONSE TO

SKIP THE NEXT SEQUENTIAL

?
‘

INSTRUCTION AND ENTER
KP8/L SERVICE ROUTINE

WITH REAL TIME APPLICATIONS
THE TIME REQUIRED FOR
CHECKING REDUCES THE TIME
FOR THE REAL TIME SERVICE

SUBROUTINE. POSITION KW8/1
INQUIRY NEAR THE BEGINNING.

DCA AC

/INTERRUPT WAS CAUSED BY POWER LOW FLAG

/SAVE AC
RAR

/GET LINK

DCA LINK

/SAVE LINK

MQA

/GET MQ

DCA MQ

/SAVE MQ

TAD 0000g
DCA PC
TAD RESTRT X
DCA 0000g

/GET PC
/SAVE PC
/GET RESTART LOCATION

/DEPOSIT RESTART LOCATION IN 0000g

HLT

Figure 1

Power Fail Service Subroutine

Regulator Control disables the memory voltage;

signals:

KEY ST and KEY ST +EX + DP

and STOP OK and POWER OK combine to

(Drawing D-BS-PDP8-L-2).

insure that the RUN flip~flop is cleared (reset) at the next processor time pulse TP3
(Drawing D-BS-PDP8-1-2).

ing address is forced by RESTART, inhibiting

A 0000g start-

Restoration of primary power initializing

PDP8-L-4).
Figure 2.

the transfer from the PC register to the MA

Program events are shown in

signals throughout the PDP-8/L to clear the
major timing and machine-state flip-flops,

including PWR LOW. Before the computer
can start, a restart signal must be generated.
The integrating 300 mssingle shot delay (draw-

A JMP or JMS instruction must be in

ing D-BS-KP8L-0-1) is enabled when normal

location 0000g because it cannot be

voltages are restored (both SHUT DOWN,

predicted what the PC register will

and STOP OK are high logic levels).

contain when a power failure occurs
since the PC register contents are not
known.

If no

additional power interruptions occur, the

single=shot will time out and try to generate

NOTE

the restart signal after the 300-ms delay .
The microswitch on the M703 module handle
can be set to DISABLE to inhibit this pulse,
orto ENABLE toallowit. When a 1-ms RE-

ENGINEERING DRAWINGS

START pulse is generated, it acts as a KEY

The following drawings D-BS-KP8L-0-1 and

ST signal in activating the manual function
timing generator, by producing the same

D-CS-M703-0-1 pertaining to the KP8/L
Option are contained in this section.

PROGRAM
IN OPERATION

POWER
INTERRUPTION

YES

ION

ENTER DEVICE

“SEARCH"

PROGRAM INTERRUPTED AND
POSSIBLE ERRONEOUS DATA.

SUBROUTINE

UPON POWER RETURN PROGRAM
IS STARTED FROM BEGINNING
PERFORM
6102g INST.

YES

IS PWR LOW
FLAG SET

;

SKIP THE NEXT SEQUENTIAL

CHECK FLAG STATUS OF EACH
DEVICE UNTIL THE
INTERRUPT -REQUESTING
DEVICE IS LOCATED.
SERVICE THE DEVICE

INSTRUCTION AND ENTER
KP8/L SERVICE ROUTINE

DCA AC
RAL
DCA LINK

STORE ANY CRITICAL

INFORMATION THAT

MIGHT
BE LOST WHEN
POWER FAILS
TAD 0000g
DCA PC
TAD K (JMP
X)

DCA 0000g
HLT

POWER
RESTORED

)

KP8/L

NO _~1icRO- SWITCH N\ "ES
ENABLED

PROGRAM MUST BE RESTARTED
MANUALLY. POSSIBLE ALTERATIONS
OF STORED PROGRAM, OR DATA
RESULTING FROM POWER FAILURE
MAY REQUIRE RELOADING OF SOURCE

MA IS ZEROED UPON
RESTART, THE
INSTRUCTION IN
LOCATION 0000g

PROGRAM.

IS PERFORMED

'
LOCATION

0/JMP X

LOCATION X CONTAINS THE
BEGINNING OF THE RESTART
PROGRAM WHICH RESTORES
THE CONTENTS OF LINK, AC,PC,
AND ANY OTHER INFORMATION
STORED BY PWR FAIL SERVICE

SUBROUTINE. CONTINUATION OF

THE PROGRAM AUTOMATICALLY

OCCURS. THE ONLY DOWNTIME
RESULTS FROM LACK OF POWER

CONTINUE
MAIN PROGRAM

Figure 2

Power Restoration Program Events

M733
A38

(SWITCH ON MODULE)

STOP

SIS
INITIALIZE
SHUT DOWN

DISABLE I

ENABLE ee—o

‘

MS @

200

9.,

MS 9Vl

RESTART
-

RESTamT

uz
|e

MB@3 (@)

MB@4

(@)

MB@5

(1)

MBO6

(@)

mBea7

(gl

MB28 (2)

0P 2 (1)
PWR

H2
J2

Lpg

———

PWR

SKIP

—M2

LOW(I}—

D-BS-KP8L-0-1

Power Failure