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EK-KE11E-OP-001
September 1976
24 pages
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Document:
KE11-E and KE11-F Instruction Set Options User's Manual
Order Number:
EK-KE11E-OP
Revision:
001
Pages:
24
Original Filename:
KE11_RefMan.pdf
OCR Text
EK-KE11E-OP-001 KE11-E and KE11-F instruction set options user’s manual digital equipment corporation - maynard, massachusetts 1st Edition, September 1976 Copyright © 1976 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no respon- sibility for any errors which may appear in this manual. Printed in U.S.A. This document was set on DIGITAL’s DECset-8000 computerized typesetting system. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC DECtape DECCOMM DECUS PDP RSTS DECsystem-10 DIGITAL TYPESET-8 DECSYSTEM-20 MASSBUS TYPESET-11 UNIBUS CONTENTS Page CHAPTER 1 'GENERAL DESCRIPTION 1.1 KE11-E EXTENDED INSTRUCTION SET 1.1.1 Purpose . . .. ............... 1.1.2 Configuration . .. ........... 1.1.3 Specifications . . ... ......... 1.2 KE11-F FLOATING INSTRUCTION SET . 1.2.1 Purpose 1.2.2 Configuration 1.2.3 Specifications . . . ................ . .. ........... . .. ... .. e e e CHAPTER 2 INSTALLATION 2.1 KEI1-EPROCEDURE .. ........... 2.2 KE11-FPROCEDURE CHAPTER 3 PROGRAMMING 3.1 ‘KE11-E EXTENDED INSTRUCTION SET ............. . ooooooooooooooooooooooo ooooooooooooooooooooooo Operation . ....... e e e e 3.1.2 Formats ... ... ........... 3.13 Instructions .. ... .......... KE11-F FLOATING INSTRUCTION SET . ., 3.2.1 Operation . ... .. .......... ' 3.2.2 Formats . ....,............ 1-1 1-1 oooooooooooooooooooooooo L @ & L & & e I s DY B s & R e T ¢ I s e I 2 R s T e ¢ S " R s T e T & T @ S » ----------------------- 3-1 ooooooooooooooooooooooo # ' ® 6 6 & & 4 & 4 & s s s s 8 s e « e s s e o ooooooooooooooooooooooo ooooooooooooooooooooooo 3-1 3-1 3-2 3-5 3-5 ----------------------- 3.23 oooooooooooooooooooooooo 324 ----------------------- APPENDIX A 1-1 1-1 ------------------------ . 3.1.1 3.2 ooooooooooooooooooooo ooooooooooooooooooooooo 3-5 3-6 GLOSSARY OF TERMS ILLUSTRATIONS Figure No. Title 3-1 EIS Number Formats ... ..... ... .. 32 EIS Instruction Format . .. ......... 3-3 ASHOperation ... .............. 34 ASHC Operation .. .. ............ 3-5 FIS Number Format . .. ... ........ 3-6 Page ooooooooooooooooooooooo ooooooooooooooooooooooo ooooooooooooooooooooooo ----------------------- ooooooooooooooooooooooo ooooooooooooooooooooooo Table No. 1-1 KE11-E (EIS) Specifications . ......... 1-2 KE11-F (FIS) Specifications . . ........ iii ----------------------- ----------------------- 3-3 34 3-5 3-6 3-6 INTRODUCTION This manual describes the KE11-E Extended Instruction Set (EIS) and KE11-F Floating Instruction Set (FIS) Options to the KD11-A Programmed Data Processor for the PDP-11/40 System. These two options are described in one manual because of their interdependency, in that KE11-F cannot be installed without the KE11-E being first installed. The purpose of this manual is to: 1. Provide an overall understanding of the functions of these options in a PDP-11/40 System. 2. Explain how the KE11-E and KE11-F can be used in software operating systems. In this manual each chapter is split in two with the first half of the chapter presenting information concerning the KE11-E Option and the second half being devoted to comparable information for the KE11-F Option. This organization is intended to facilitate greater ease in use by those customers who utilize only the EIS hardware. Chapter 1 provides an introduction to the options and lists brief specifications. Chapter 2 contains installation information. Chapter 3 contains programming information, listing instructions and illustrating their formats. Detailed descriptions of processor, console, Unibus, and memory logic that interface with these options are provided in the following related documents: PDP-11/40 System Maintenance Manual DEC-11-H40SA-A-D KD11-A Central Processor Unit Maintenance Manual EK-KD11A-MM-001 | CHAPTER 1 GENERAL DESCRIPTION This chapter contains a general description of both the KE11-E and KE11-F Options. Mechanical descriptions are given together with engineering specifications for each option. The chapter is divided in half with the EIS information presented first, followed by comparable information for the FIS hardware. 1.1 KE11-E EXTENDED INSTRUCTION SET The KE11-E Extended Instruction Set is a hardware option to the basw PDP-11/40 Computer System. Itis supplied as a pluggable option to the KD11-A Central Processor. 1.1.1 . Purpose The KE11-E Option expands the instruction set of the KD11-A Central Processor to provide extended manipulation of fixed-point numbers. When installed, it adds the capability of Arithmetic Shift, Arithmetic Shift Combined, Multiply, and Divide. With these additional instructions, the system can multiply and divide signed 16-bit numbers, and can shift signed 16-bit or 32-bit numbers. Condition codes are set in the processor on the result of each instruction. 1.1.2 Configuration The KEI1-E Option consists of one module. The single-hex X 8-1/2 in. M7238 module plugs directly into slot 2 (A—F) of the processor system unit. This is a'dedicated prewired slot such that no other modules need be moved to accommodate its installation. When installed, the module functions as an extension of the basic KD11-A data paths, branch control, and control ROM. Basic timing of the processor is not degraded by use of this module, nor is the NPR latency affected when its instructions are being executed. Interrupts are serviced at the end of each instruction in the standard manner. 1.1.3 Specifications | _‘ Specifications for the KE11-E Option are given in Table 1-1. - Table 1-1 KE11-E (EIS) Specifications Instructions _ Arithmetic Shift (ASH) Arithmetic Shift Combined (ASHC) Multiply (MUL) Divide (DIV) Operations Multiplication and division of signed 16-bit numbers Arithmetic shifting of signed 16-bit or 32-bit numbers 1-1 Table 1-1 (Cont) KE11-E (EIS) Specifications Addressable Registers None in option. Operands fetched from core or processor general registers. Timing Time = SRC Time + EF Time SRC Mode SRC Time 0 0.28 us 1 0.78 us 2 0.98 us 3 1.74 us 4 0.98 us 5 1.74 us 6 1.74 us 7 2.64 us Instr .EF Time MUL DIV 1.2 Notes 8.88 us - 1130 us ASH (right) 2.58 us +0.30 us/shift ASH (left) 2.78 us +0.30 us/shift ASHC (no shift) 2.78 us ASHC (shift) 3.26 us Size Single Hex module (M7238) Power Required +5V, 2.3A +0.30 us/shift KE11-F FLOATING INSTRUCTION SET The KE11-F Floating Instruction Set is a hardware option to the basic PDP-11/40 Computer System. It is supplied as a pluggable option to the KD11-A Central Processor and requires that the KE11-E described above be installed as a prerequisite. 1.2.1 Purpbse The KE11-F Floating Instruction Set (FIS) enables direct operations on single-precision 32-bit words in floating-point arithmetic. Since the KE11-E is a prerequisite to the KE11-F, extended manipulation of fixed-point numbers is available as well. The KE11-F Option further extends the PDP-11/40 instruction set to include Floating Add, Floating Subtract, Floating Multiply, and Floating Divide. As with the KE11-E, condition codes in the Processor Status Register are set on the result of each instruction. The prime advantage of this option is increased speed without the necessity of writing complex floating-point software routines. 1.2.2 Configuration The KE11-F Option consists of one single-quad X 8-1/2 in. M7239 module with the KE11-E Option described above being a prerequisite. This FIS module plugs directly into slot 1 (A—D) also a dedicated prewired slot in the basic KD11-A. No degradation of processor timing or NPR latency is effected by the use of this option. Floating instructions are aborted if a BR request is issued before the instruction is within approximately 8 us of completion, at which time the Program Counter (PC) is adjusted to point to the aborted floating instruction so that the instruction will be restarted upon return from the interrupt. 1.2.3 Specifications Specifications for the KE11-F Option are given in Table 1-2. Table 1-2 KE11-F (FIS) Specifications Prerequisite Instructions KE11-E Extended Instruction Set Option Floating-point Addition (FADD) Floating-point Subtraction (FSUB) Floating-point Multiply (FMUL) Floating-point Divide (FDIV) Operations Single-precision floating-point addition, subtraction, multiplication, and division of 24-bit numbers Addressable Registers ~None in option. Operands fetched from core. Size Single-quad module (M7239) Power Required +5V, 1.1A (typical) Timing Time = Basic Time + Binary Point Alignment Time + Normalization Time Instr Basic Binary Point Normalization Time Time* us Alignment Time Per Shift us Per Shift us FADD 18.78 0.30 0.34 FSUB 19.08 0.30 0.34 FMUL 29.00 —— 0.34 FDIV 46.27 —— 0.34 *Basic instruction times for FADD and FSUB assume exponents are equal or differ by one. 1-3 CHAPTER 2 INSTALLATION 2.1 KE11-E PROCEDURE When the KE11-E is included as part of the initial PDP-11/40 System, the M7238 module is installed prior to shipment. If it is being added to an existing system, proceed as follows: a. Insert the M7238 module in 2(A—-F). b. Remove the jumper (W1) on processor module M7233 (IR DECODE) at location 5(A—F). C. Install the three “over the backTM cables from J1, J2, and J3 of the M7238 module to J1, J2, and J3 respectively of the M7232 (U Word) module at location 3(A—D). 2.2 KE11-F PROCEDURE When the KE11-F is to be added to a system, the KE11-E must also be added. Proceed as follows: a. Perform steps a. through c. above. b. Insert the M7239 module in 1(A—D). c. On the M7238 module, remove the following jumpers: 1. WI from CO2F2 to ground. 2. W2 from A02B1 to ground. 3. W3 from DO2L1 to ground. NOTE If these jumpers are not removed, the KE11-E Option will still execute EIS instructions but will not execute FIS instructions. When the above steps are performed, the KE11-E and KE11-F Options are ready to be checked out using the diagnostic programs supplied with the options. CHAPTER 3 PROGRAMMING This chapter is devoted to general programming informat ion for the KE11-E and KE11-F Options. It provides general descriptions of their operation, the formats and instructions for each. In addition, programming examples are supplied for each option. This chapter is intended merely as an introduction to the programming of this hardware . For more detailed information refer to the pertinent software documentation generated for these options. As with Chapter 1, information has been separated for each option. 3.1 KE11-E EXTENDED INSTRUCTION SET There are no addressable registers in the KE11-E Option. EIS the general processor registers. The result of each operatio operands are fetched from either core memory or from n is stored in the general registers. 3.1.1 Operation When the Arithmetic Shift (ASH) instruction is used, the contents of the selected register is shifted right or left the number of places specified by a count. This shift count is a 6-bit, 2’s complement number which is the least significant 6 bits of the source operand. If the count is positive, the number is shifted left; if it is negative, the number is shifted right. This allows for shifts from 31 positions left to 32 positions right (+31 to -32) although a shift of greater than 16 places loses all significance. A count of O causes no change in the number. When the Arithmetic Shift Combined (ASHC) instruction is used, the contents of the register (R) and the register ORed with 1 (RV1) are treated as a single 32-bit word. Register RV1 represents bits (15:00), register R represents bits(31:16). This 32-bit word is shifted right or left the number of places specified by a count. This shift count is the same as that described for the ASH instruction and permits shifts from +31 to -32. If the selected register odd number, then R and RVI1 are the same. In this case, the right shift becomes a rotate and rotated right the number of bits specified by the count for up to 16 shifts. (R) is an the 16-bit word is When the MULtiply (MUL) instruction is used, the contents of the Destination Register and the source are multiplied as 2’s complement integers. The result is stored in the Destination Register R and the register ORed with 1 (RV1). If the register is odd, only the low-order product is stored. This instruction multiplies full 16-bit numbers. When the DIVide (DIV) instruction is used, a 32-bit dividend in R and RV1 is divided by a 16-bit divisor to provide a 16-bit quotient and a 16-bit remainder. The sign of the remainder is always the same as the sign of the dividend unless the remainder is 0. Overflow is indicated if more than 16 bits are required to express the quotient. In this case, the instruction is aborted. If the content of the Source Register is 0, indicating divide by 0, an overflow is indicated. 3.1.2 Formats The number formats for the KE11-E Option are shown in Figure 3-1. A single word is 16-bits long and a double word is 32-bits long. In the single word, bit 15 is the sign of the number; and in the double word, the sign bit is bit 15 of the high number part. The S bit is O for positive quantities and is 1 for negative quantities. 3-1 /——S|NGLE WORD SIGN BIT 0 15 15 14 Figure 3-1 3.1.3 LOW OPERAND PART l HIGH OPERAND PART [S l 0 15 14 /—-DOUBLE WORD SIGN BIT J 0] EIS Number Formats Instructions The EIS instruction format is shown in Figure 3-2. It is a double operand instruction in which bits (15:09) comprise the Op code, bits (08:06) designate the Destination Register field (RRR), bits (05:03) indicate the Source Address Mode (SSS), and bits (02:00) specify the Source Address Register (SSS). The octal coding is in the form 07XRSS. There are four EIS instructions, as follows: MUL 070RSS MULtiply Operation: R, RV1 < R X(SRC) Condition Codes: N: setif product is < 0; cleared otherwise. Z: setif product is = 0; cleared otherwise. V: cleared C: _ set if the result is less than -2'% or is greater than or equal to 2'°-1; cleared otherwise. The contents of the Destination Register R and source taken as 2°s complement integers Description: are multiplied and stored in the Destination Register R and the succeeding register RV1 (if R is even). If R is odd, only the low-order product is stored. Assembler syntax is: MUL S, R. (Note that the actual destination is R, RV1 which reduces to just R when R is odd.) Example: 16-bit product (R is odd) 000241 , CLC :Clear carry condition code 1034xx , BCS ERROR :Carry will be set if 012701, 400 070127, 10 , , MOV #400, R1 MUL #10, R1 ;product is less than =215 or greater than or -equal to 2! ° :no significance lost After Before (R1)=004000 (R1)=000400 3-2 15 9 [o|1 i i | 8 6 5 0 1|xx XIRRR[S 'ss[ss | 1 L v 1 1 4 OP CODE { 1 e — s] | | SOURCE REGISTER FIELD SOURCE MODE FIELD ¢ % DESTINATION REGISTER FIELD 11-1604 *Note that for the EIS instructions the Source Register is considered the Destination since the answer is stored in that register. The Destination Mode and Register Field are considered to be the source. This is not consistent with other PDP-11 family instruction formats but is used throughout the discussions of the EIS instructions in this manual. Figure 3-2 DIV EIS Instruction Format 071RSS DIVide Operation: R < R, RV1 + (SRC) RV1 « Remainder Condition Codes: N: setif quotient <O; cleared otherwise. Z: setif quotient = 0; cleared otherwise. V: set if source = O or if the absolute value of the register is larger than the absolute value of the source. (In this case, the instruction is aborted because the quotient would exceed 16 bits.) C. Description: setif divide by O attempted; cleared otherwise. The 32-bit 2’s complement integer in R and RV1 is divided by the source operand (SSS). The quotient is placed in R; the remainder is placed in RV1 with the same sign of the dividend. R must be even. Example: 005000 , CLR RO 012701,20001 , MOV #20001,R1 071027,2 , DIV #2, RO Before ASH ' After (R0)=000000 (R0)=010000 Quotient (R1)=020001 (R1)=000001 Remainder 072RSS Arithmetic SHift 3-3 R « R shifted arithmetically NN places to right or left, where NN = low-order 6 bits of Operation: source. set if result < 0; cleared otherwise. Condition Codes: set if result = 0; cleared otherwise. set if sign of register changed during left shift; cleared otherwise. loaded from last bit shifted out of register. Description: The contents of the register are shifted right or left the number of times specified by the shift count. The shift count is taken as the low-order 6 bits of the source operand (SSS). This number ranges from -32 to +31. Negative is a right shift and positive is a left shift (Figure 3-3). Example: ASH RO, R3 Before After (R3)=000003 (R3)=000003 (R0)=001234 (R0)=012340 15 RIGHT SHIFT IF COUNT IS NEGATIVE 15 e[l 0 | LEFT SHIFT A= IF COUNT IS [ feo = POSITIVE 11-1605 Figure 3-3 ASHC ASH Operation 073RSS Arithmetic SHift Combined Operation: R, RVI < R, RVI. The double word is shifted NN places to the right or left, where NN = low-order six bits of source. Condition Codes: Description: N: setif result <O0; cleared otherwise. Z: setif result = 0; cleared otherwise. V: setif sign bit changes during the left shift; cleared otherwise. C: loaded with the last bit shifted out of the register. The contents of the register and the register ORed with 1 are treated as one 32-bit word. RV1 (bits 15:00) and R (bits 31:16) are shifted right or left the number of times specified by the shift count. The shift count is taken as the low-order 6 bits of the source operand. This number ranges from -32 to +31. Negative is a right shift and positive is a left shift (Figure 3-4). When the register chosen is an odd number, the register and the register ORed with 1 are the same. In this case, the right shift becomes a rotate. The 16-bit word is rotated right the number of bits specified by the shift count for up to 16 shifts. 34 ; v | RIGHT SHIFT IF COUNT IS NEGATIVE | Ll L] L4 31 . ele—( ], L4 [ i 2 -l 15 0 lJn-ln’Fi.,l[l,l'lll]C—-o LEFT SHIFT IF COUNT IS ; RV POSITIVE 11-1606 Figure 3-4 3.2 ASHC Operation KEI11-F FLOATING INSTRUCTION SET There are no addressable registers in the KE11-F Option. FIS operands are fetched from core memory and the result of each operation is stored in core memory. Operands are ordered on the stack in Polish Notation (Paragraph 4.2), thereby reducing the number of operations necessary to achieve a result. 3.2.1 Operation For Floating ADD, the A argument from the stack is added to the B argument from the stack with the result stored in the A argument position on the stack. - For Floating SUBtract, the B argument from the stack is subtracted from the A argument on the stack with the result stored in the A argument position on the stack. The Floating MULtiply instruction multiplies the A argument on the stack by the B argument on the stack and stores the result in the A argument position on the stack. The Floating DIVide instruction divides the A argument on the stack by the B argument on the stack and stores the result in the A argument position on the stack. 3.2.2 Formats’ The number format for the KE11-F Option is shown in Figure 3-5. The KE11-F word is 32 bits long with bit 15 of the high argument designating the sign of the fraction. Note that the 8-bit exponent separates the fraction from its associated sign. In floating point, representation of binary numbers is in three parts: a sign bit, an exponent, and a mantissa. The mantissa is a fraction expressed in sign and magnitude format with the binary point positioned to the left of the most significant bit of the mantissa. The mantissa is assumed to be normalized. The MSB of the mantissa is not stored in core because it is redundant. Leading Os are removed by shifting the mantissa left; however, each left shift of the mantissa must be followed by a decrement of the exponent value to maintain the true value of the number. The exponent value represents the power of 2 by which the mantissa is multiplied to obtain the value to be used. 3-5 FRACTION SIGN BIT \ [* FRACTION EXPONENT s 15 14 (EXCESS 2008) LOW ARGUMENT >a HIGH ARGUMENT 7 6 (HIGH PART) FRACTION (LOW PART) 0 15 > 0 Y 23-BIT FRACTION ¥ Rl Y BINARY POINT——/ I 23 Me=1{: Inserted by hardware before operating on operands if exponent field # all zeros. 11-1607 Figure 3-5 FIS Number Format The KE11-F Option stores the exponent in excess 2005 (128, ) notation. As a result, exponent values from -128 to +127 are represented by the binary equivalent of 0 to 255 (octal 0—377). Mantissas are represented in sign magnitude form. The binary radix point is to the left. The results of the floating-point operations are always rounded away from O, increasing the absolute value of the number. If the exponent is equal to O, the number is assumed to be O regardless of the sign bit or fraction value. The hardware generates a clean 0 (32-bit word of all Os) in this case. 3.2.3 Instructions The FIS instruction format is shown in Figure 3-6. It is a double operand instruction in which the low three bits (R,R,R) specify a register that is utilized as a stack pointer for the floating-point operands. The register may be any one of the eight general registers, but some caution must be used if using the PC (R7). 1t is unlikely that the PC would be desirable as a pointer. o 2 3 15 14 |RRR] 1|OOO|XXX [0|1 1 1 I 1l|0 | ] Il ! | N 1 ] lhy__l v STACK OP CODE POINTER 11-1603 Figure 3-6 FIS Instruction Format The operands are located on the stack as follows: (R) = High B Argument (R)+2 = Low B Argument (R)+4 = High A Argument (R)+6 EXP S| 14 15 | HIGH FRACTION| 6 LOW FRACTION 15 = Low A Argument 3-6 0 0 J The floating-point answers are stored as follows: (R)+4 = High Answer (R)+6 = Low Answer The floating-point stack pointer is repositioned to point to (R)+4 (High Answer). The floating-point octal coding is in the form 0750XR. There are four FIS instructions, as follows: FADD 07500R Floating-ADD Operation: [(R) +4 O (R) +6] <« [(R) +4 O (R) +6] + [(R) O (R) +2], if result > 2-128; else [(R) +4 (O(R) +6] <0 Condition Codes: N: (See Note Below) Z: setif result = 0; cleared otherwise. V: cleared C: cleared Description: setif result <O0; cleared otherwise. Adds the B argument to the A argument and stores the result in the A argument position on the stack. A < A+B FSUB 07501R Floating-SUBtract Operation: [(R) +4 D (R) +6] « [(R) +4 O (R) +6] - [(R) O (R) +2], if result > 2-12%, else [(R) +4 OO (R) +6] <0 Condition Codes: N: (See Note Below) Z: setif result = 0; cleared otherwise. V: cleared C: cleared Description: set if result <O0; cleared otherwise. Subtracts the B argument from the A argument and stores the result in the A argument position on the stack. A < A-B FMUL 07502R Floating-MULLtiply Operation: [(R) +4 O (R) +6] <« [(R) +4 O (R) +6] * [(R) O (R) +2], if result >2-128. else [(R) +4, (R) +6] Condition Codes: N: (See Note Below) Z: setif result = 0; cleared otherwise. V: cleared C: cleared setif result <O; cleared otherwise. 3-7 Multiplies the B argument by the A argument and stores the result in the A argument Description: '?® then underflow occurs and the position on the stack. A < A*B. If the result is <27 destination address will contain the A argument. FDIV 07503R Floating-DIVide [(R) +4 O (R) +6] « [(R) +4 O (R) +6] / [(R) O (R) +2], if result > 2-'2°%; Operation: else [(R) +4 O (R) +6] Condition Codes: N: set if result <0; cleared otherwise. (See Note Below) Z: setif result = 0; cleared otherwise. V: cleared C: cleared Divides the A argument by the B argument and stores the result in the A argument position on the stack. If the B argument (divisor) is equal to O, the stack is left untouched. A < A/B. If the result is < 27 '?8 then the destination address will contain Description: the A argument. NOTE If a trap occurs as a function of a floating instruction, the condition codes are reinterpreted as follows: N: set if underflow, cleared if overflow. Z: cleared V: set if underflow, overflow, divide by 0 (error conditions). C: setif divide by 0, otherwise cleared. Traps occur through the vector 244. (R) is reset to point to high B argument on the stack. The arguments are left untouched. 3.2.4 Programming Example gegoge’ CORYRIGHT 1972 BY MAYNARD, DIGITAL EQUIPMENT MASSACHUSETTS, CORPORATIOQN, EXAMPLE OF PDP=11/4@ FLQATING INSTRUCTIQON SET USAGE COMPUTE LARGER ROQT OF QUADRATIC EQUAT]ONI AnXeX « Bax = @ +« 0 + SQRT(B#B ALGORITHM 1S We e We WM W W We WE We We Ve W We e «JTITLE FISEXM ROOTL = (eB e DNV BWNHR ol sl el ol VDN ND N A sample floating-point program is given below. 3-8 = 4eAsC))/(2eA) (F1!S) 19 H ! 20 INITIAL VALUES OF A, PLACED IN MEMQRY } RESULY S NOQRMA[, TERMINATION 22 23 } H 24 ! IF } IMAG., 26 } 28 30 31 32 33 34 35 36 NORMA| peoeon R 3%0 enpaaL geoap2 RooaR3 0200204 R1 R2 R3 a¥%i a%2 a¥%3 R4 zX4 gaoops gopede RS Sp gapeg7 PC 5X8S a%é HALT AT REGISTER } pogeeY 212706 aogasz’ PROGRAM STARTS 42 poo14 216746 MQV B#2,~(SP) MQV Byw(SP) 20020 pepz4 pupee 0oe30 Q34 gepi74- A = G LOCATION HALT DaNE, AT LOCATION 2, 216746 pag4n pop44 QoRa6 51 pops2 R75@26 FMUL pese4de w(SP) MOV, #eF4.,.2,-(SP) MOV Av2,=(SP) 216746 MOV Ay=(SP) papi42 Qa1457 BEQ AZERO P16746 MOV Ce2,=(SP) MOV Cie(SP) 275026 B75026 975016 FMUL FMUL FsuB SP SP BMI MOV IMAG MOV (5P)+,TEMP1+2 JSR R5,SORT R12746 240600 216746 Pedlae 016746 pagiap pagse6 53 oegen 54 gneee pop64 56 L2446 ARP66 212667 onpl13e ogaze 12667 Papl26 oaR7e6 go4a567 gopoaec gaiez 61 eni06 62 goi12 63 64 gp116 65 ee122 66 Pd1L26 SP CLR 52 201924 PROCESSOR STACK STACK TO 1AGAIN Pan166 pagL5p 5¢ 59 IF AT THEN )JB By=(SP) 58 HALT JINITIALIZE MOV 57 A NEGATIVE #STACK,SP pogie 49 ROOTYY, éTART: MOV 41 48 AND AT HERE Be2,=(SP) 47 B, 2%7 MOV 46 IS A, STORED - 230204 216746 PABL76 44 ARE DECLARATIOQONSI P16746 45 1S AND AZERO poaos 43 € ’ 37 49 COMPUTED DISCRIMINANT AND ¢ 27 38 39 - B, LOCATIONS peEg4g1 peg222 210067 eoR114 210167 peR112 216746 pona72 g16746 gapasd 062716 loeeoe }COMPYTE SP (SP)+,TEMP1 BR ,+4 WORD TEMP1 MOV R, TEMP2 MOV RL)TEMP2e?2 ROOTY MOV B#*2,~(SP) MOV By=(SP) ADD #100000,eSpP JFORM B#B 14,0 TO STACK JA TO STACK JHALT JC TO IFORM IF A = 2, STACK AeC JFORM 4,aA0C JFORM BeBed sAaC JBRANCH JSTORE IF DISCRIMINANY JCALL, FORTRAN ISTORE RESULTY }1B TO (DISCRIMINANT) NEGATIVE SQUARE STACK INEGAYE B ON STACK ROOY RQUTINE o132 2R136 go142 ge144 16746 MOV TEMP2%2,=(SP) g16746 MOV TEMP2,=(SP) FADOD SP gape72 gre064d 2750206 P16746 eooe64 216746 0A9e56 po154 216746 gape3e gu1se pe160 216746 pr164 @ni166 2ui17e 275026 go174 pege2?2 75236 12667 peRR42 12667 gepo4n pp2ee ga0000 DONES po2082 goerooe IMAG! po204 gnoede AZERO: MQV CONST#2,(SP) MOV CONST.'(SP) MOV A®2,=(SP) MOV Ay=(SP) FMUL FOIv SP MOV (SP)+,R00T1 MOV (SP)+,R00T1+2 }SOUARE ROOT TO STACK IFORM eB+SQRT )2,@ YO STACK JA TO STACK IFORM 2, %A SP JFORM (wB#SQRT)/(2,%A) JSAVE RESULT HALT HALT HALT Al B¢ c: TEMPY! TEMP2} 040400 CONST: goeape ROOTL: STACK} Po442 200001 BLKW +BLKW BLKW yBLKW +BLKW FLT2 BLKW 1GLOBL, 'BLKHW 1BLKW N } 0206 po2i2 gB21eé po222 pR226 02232 2234 pR236 NN NN H SQRT JEXTERNAL SUBROUTINE i JSTARY OF STACK 1S TOP OF AREA JROOM 100 END 3-10 FOR STACK APPENDIX A GLOSSARY OF TERMS Table A-1 contains a collection of some of the terms used in this manual that may need defining. It does not include all terms, only those that it is thought might be confusing. Listing is in alphabetical order. Table A-1 Glossary of Terms Term Definition ADD Add (instruction) ADR Address ALU Arithmetic Logic Unit ALUM Arithmetic Logic Unit Mode ARGA Argument A (f/f) ASH Arithmetic shift (instruction) ASHC Arithmetic shift combined (instruction) BBSY Bus busy BRQ Bus request BUS Unibus BUS U Bus microprogram BUSY Busy BUT Branch microprogram test CIN Carry-in (ALU) CLK Clock CLKB Clock B Register CLKBA Clock BA Register CLKD Clock D Register CLKOFF Clock off CLR Clear C,V,N,Z (instruction) CON Constant COUT MUX Carry-out multiplexer (ALU) C1 BUS C1 of Unibus DAD Discrete alteration of data DEST Destination DIV Divide (instruction) DMUX Data multiplexer EINSTR Extended Instruction EIS Extended arithmetic instruction set A-1 Table A-1 (Cont) Glossary of Terms Definition Term EPS EUB EUPP Extended Processor Status Extended microprogram bus Extended microprogram pointer EXP Exponent f FADD FC1BUS FDIV FETCH FINSTR FIS Function of Floating add (instruction) Floating C1 Bus Floating divide (instruction) Fetch (Processor State) Floating Instruction Floating instruction set FMUL FSUB FUB Floating multiply (instr ction) Floating subtract (instruction) Floating microprogram bus IR Instruction register Instruction set processor ISP JAMUPP MUL Jam microprogram pointer Multiply (instruction) MUX Multiplexer NO-OP No operation OVFL PC Program Counter PS R(x) RSVD INSTR SALU Processor Status Register Scratch Pad Register Reserved instruction Select arithmetic logic unit SALUM Overflow Select arithmetic logic unit mode SBC Select B constant SERVICE Service SET COND CODES Set condition codes Source field Source field ORed with 1 SF SFvV1 SRC STPM TRAP U UBF UNFL Source (processor major state) Special Trap Pointer Marker User call Microprogram Microprogram branch field U WORD Underflow Microprogram pointer Microprogram word VECT Vector XOR ZB Exclusive OR (V) “Z” bit previous state (flip-flop) UpPP Reader’s Comments KE11-E and KE11-F INSTRUCTION SET OPTIONS MANUAL EK-KE11E-TM-002 Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications. What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well written, etc.? Isit easy to use? CUTOUTONTL :D LINE What features are most useful? What faults do you find with the manual? Does this manual satisfy the need you think it was intended to satisfy? Does it satisfy your needs? Why? Would you please indicate any factual errors you have found. Please describe your position. Name Organization Street Department City State Zip or Country - -~ — — — — — —— —— Do Not Tear - Fold Here and Stapl¢ — — — — — — — — FIRST CLASS PERMIT NO. 33 MAYNARD, MASS. BUSINESS REPLY MAIL NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES G DR AN Postage will be paid by: T L] Digital Equipment Corpora.tion Technical Documentation Department A — 146 Main Street Maynard, Massachusetts 01754 ] IR N
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