Digital PDFs

XX-95BDE-B1

2000

15 pages

Original

3.6MB

Document:	ITS Hardware Memo 2
Order Number:	XX-95BDE-B1
Revision:	0
Pages:	15
Original Filename:	ITS_Hardware_Memo_2.pdf

OCR Text

word are stored in an associative register (AR), keyed by the
virtual page number plus a bit for USER versus EXEC pages.

another reference occurs to the same virtual page, the necessary
information will be found in the AR, without reference to the
page table in memory.

The main group of associative registers.

is called the A memory and consists of sixteen independent AR's.
A four-bit counter (RBC) determines which AR is to be stored
into when a new page table reference is made.

The counter ad

vances after each refill and acts like a ring buffer pointer .

2.3. 1 BAND C MEMORIES
In addition to the A memory, two more groups of sixteen AR's ,
called the Band C memories exist.

These are keyed by a single

five-bit key for each of the sixteen AR's.

The key selects USER/

EXEC pages, and associates a sixteen-page block of virtual memory.
A contiguous 16K of virtual memory is mapped into sixteen separate
pages.
The effect of this is invisible to the mapping process.

The

addition of the Band C memories

merely diverts page refills for

a specific area of virtual memory.

They might be used to shade

the A memory from the addresses generated by the instruction
fetches or reference to a group of data tables.

Since the A, B,

and C memories provide 48K of mapping information contained in
hardware associative registers, only programs with unusually

large working sets need incur any overhead referencing the page
tables.

2.4 AGING
The paging box contains a four-bit program loaded register.

When

ever a reference is made to a page word for refilling an AR, bits
5-8 of the page word in core are updated to the current age.

This

is a method of enabling the executive to differentiate between
recently referenced pages versus those that have fallen out of the
working set.

3.0 LOAD PAGE MEMORY
L ?Hif

L?l!tf/

LPn
5 P f'v/

/~2

AlJt

(JEIEKA1E..
/tVTEfflJ?(

An instruction (Op code

12~,~~~,,)

has been added to the

PDP -l~ .

This instruction transfers eight words in a block pointed to by
the effective address (absolute) to or from the paging device.
Load Page Memory (LPM

1~2,~~~,,)

transfers from memory to the

paging device, and store Page Memory (SPM

1~2,~4~, ,)

in memory the same eight words of state information.

wr it es back

3.1 STATE BLOCK
~

.21
I

5'1

(;-AG£

lli Ii

JPC

FLAGS

Ore

HARe. )(

I1AR

QUAil

.{--f=A/JI. T J TATIJS

V13X' /

-{-OFA 17-J.O-x- DlJ,f1-

lJf}:f 02

+-lJlJRL

ZJ131( J

ACP

<-- OFA ,2/-).r )(

fc---.-BK

I i

)(

{-RBC

)<
ope

(

171

IfJ

8"1

8'1

j)8~L

/0 I

I,,I
!J

I I. / I I

I 1 I

WDl
5-8 - Age - quantity stored in Age field (5-8, 23-26) of
page word when referenced to refill AR.
9-17 - FAULT ADDRESS - virtual address referenced at time of
page fault.

Bit 9 is a "one" if reference was USER

address, 10-17 correspond to MA 18-25.
WD2
5-17 - PC Flags - saved at the beginning of every instruct ion
(except when Priority Interrupt is in progress) .
5 - AR OVF (bit ~ of PC word)

6 - AR CRY~ (bit 1)
7 - AR CRYl

(2)

8 - AR FP OVF

(3)

J
1

•

9 - BYTE interrupt (4)

10 - EX USER (5)
11 - EX lOT USER (6)
12 - PURE (7) Indicates instruction fetches must be made
from Read Only pages.
13 - not used
14 - One Proceed (9) indicates that an interrupt will
occur at the end of this instruction exec u tion.
15 - not used.
16 - FXU (11)
17 - DCK (12)
18-35 - OLD PC - The contents of the Program Counter saved
at the beginning of all instructions (except PI in
progress).

Used to restore state of machine after

a page fault.
WD3
11-14 - Ring Buffer Couter - register that points to next AR
in A memory to be refilled.

Not reloaded by LPM, but

reset to ~.
15 - EXEC - if a "one" then the MAR address is a USER address
16-17 - MAR condition
~~

- Never compare

- Only the instruction fetches

•

- write

11 - Any reference
18-35 - Memory Address Register (MAR) - a register that points
to a location which will generate an interrupt when
referenced (if the condition is correct).

Does not

function for fast memory references that occur through
AC field or Index register field.
WD4
7-17 - status bits
(2~~~)

7 -

One Proceed - set after inst ructi on e x e c u t ion

with One Proceed bit on in PC (bit 9).
set if inst ruction interrupted.

Does not

Set after UUO

even if transfers to EXEC mode.
(l~~~)

8 -

Fault - set if any page fault condition

occurred.

Not set if interrupt on fault inhibited

(XCTR) •
(4~~)

9 -

PG NXM - set if page table references or LPM,

SPM reference caused non-ex-mem.
l~

(2~~)

DBL - descriptor base length exceeded.

11 -

(l~~)

- Write attempted into Read Only page.

12 -

(4~)

- Write into Read/Write/First.

13 -

(2~)

- PURE code attempted instruction fetch from

impure page.
14 -

(l~)

- No access

15 -

(4) - EXR - enable mapping for EXEC addr ess es
above

4~~/~~~.

16 -

(2) MAR - MAR interrupt occurred.

17 -

(1) QUAN - quantum overflow.
counting of the quantum timer.

This bit inhibits
Carried into by QT IB .

18-35 - Quantum Counter that counts except when machine is
PI in progress.

1 MHZ.

WD5
5-9 - Bits 21-25 of Output Fault Address (OFA).
address of the reference that faulted.

The mapped

Corresponds to

FA 9-17.
1~-16

- DBRLI - Length of first DBR in words.

A zero indi

cates no entries.
17-35 - DBRI - pointer to USER ~-4~~/~~~ page table.
pointer - full 19-bit address.
WD6
6-9 - Bits
1~-16

17-2~

of OFA.

- DBRL2

17-35 - DBR2 - USER

4~~/~~~-777/777

WD7
1~-16

- DBRL3

17-35 - DBR3 - EXEC

4~~/~~~-777/777.

Absolute

WD8
7-11 - B key selects 16K block associated with B memory.
7 - "one" - USER address
8-11 - corresponds to MA 18-21
12-16 - C key
12 - "one" - USER addresses
13-16 - MA 18-21
17-35 - AC Pointer - contains address (absolute 19 bit) of
block of 16 words that are to be referenced in pla ce o f
fast memory when mapping addresses less than

with

an XCTR instruction.

3.2 LPMR, LPMI
Bit 11 of the AC field of an LPM instruction causes all associative
registers to be cleared
l~

(LPMR Load Page Memory and Reset) .

Bit

sets the Memory Protect Flag and causes and interrupt (LPMI

Load Page Memory and Interrupt) .

4.1 FAULT HANDLING
Page reference faults (such as NO ACCESS) abort the execution o f
the current instruction.

In all cases the instruction is terminated

before the contents of core or fast memory are affected.

By re

storing the program counter to point at the fault instruction, the
state of the process before the fault is preserved.

All faults

(plus MAR, QUAN, One proceed, and PAGE NXM) set the Memory Protect

Flag (bit 22 of CONI APR 1 ) and request an interrupt on the
processor channel.

4.1 .1 OLD PROGRAM COUNTER
The contents of the Program Counter (plus MISC Flags) are pre
served in the OPC register at the beginning of every instruction
not PI in progress.

The flags are also loaded at ITl to reflect

the change in the Byte Increment Suppression Flag during ILDB,
and IDPB.

Thus, if the instruction that generates the fault trans

fers or skips before the fault is detected, the orig ina l PC i s made
available.

4.1.2 FAULT PAGE NUMBER
The eight-bit page number plus a 'e.it that
references,

a "one" for USER

"zero" for EXEC references is saved when a fault

occurs.

4.1.3 OUTPUT FAULT ADDRESS
MA bits 17-25 that were result of mapping an address which
faulted (due to protection bits).

Useful for testing A,B, and

C memories •

• . 1.4 PI TRAP MODE

The PDP-l~ normally checks for interrupt request after the fetch
for the instruction (or indirect word).

After a fault it is

n e cessary to avoid further instruction fetches which may cause
more faults or change the OPC.

A special mode called PI TRAP mode

is entered after the fault occurs.

Interrupt requests are de

tected before the beginning of the instruction.

This mode must

stay in effect through interrupt on channels higher than the
processor.

When the interrupt routine recognizes the request and

clears the Memory Protect Flag, PI TRAP mode is turned off.

5 . 1 EXECUTE RELOCATED
3 '1 10 II 1;( 10 PI
$
~

:I:~/K
J
, '

/¢J

11 ",.

AlJ;f

' I

~ l?:)/AlT£,f TO IIV5TtfI/CTIO;1/
1~3)

XCTR (OP code

identical to XCT, except ACll, AC12 control

the enabling of mapping on Write and Read references of the instruc
tion executed.

If AC12

a "one" then all Read refere nce s after

the effective address computation are mapped as if in USER mode
(DBRI and DBR2).
mapped.

If ACll is a "one" then the Write references are

References to the AC's by AC Field and Index Field are

not mapped.

Bit

of the AC Filed of the XCTR instruction inhibits

the generation of a MEM PROT interrupt.
tion is skipped.

Instead the next instruc

If traps are inhibited by this bit, the Fault

bit in the Status word (bit 5) is not set, but bits
set according to the type of fault.

1~-14

are

5 .1.2 AC POINTER
Locations below 2¢ which are relocated during an instruction
being XCTR'd are not mapped to Fast memory or USER pages.

stead a 19-bit pointer in the State Word (ACP) is used to specify
the location of a 2¢ word block that contains addresses ¢-17.
(AC memory or absolute location ¢-17 depending on the Fast memory
enable switch on the machine.) .

6.1 MEMORY ADDRESS REGISTER (MAR)
All memory add~ fed to the paging device are compared agai ns t
an eighteen bit register, the MAR.

A three bit condition (bits

15-17 of MAR word) enable addresses equal to the MAR t o set the
MEM PROT Flag.

Bit 15 is a "one" for USER mode addresses, a "zero"

for EXEC addresses.
~l

Bits 16-17 are decoded:

¢¢ - never interrupt,

- only if address is referenced to fetch an instruct ion (not

executed by SCT however), l¢ - if location is being written into,
11 - under any condition.

The MAR interrupt does not abort the

instruction and doesn't set the FAULT bit (8) of the status word.
The PI TRAP mode is asserted, however, and the processor will
interrupt before the next instruction and the OPC register wil l
contain a pointer to the instruction that generated the interrupt.
USER addresses referenced by means of the XCTR instruction will
be compared against the MAR.

6 .2 JUMP PROGRAM COUNTER (JPC)
In USER mode, any instruction that causes a transfer wi ll save
the contents of the program Counter at the beginning of that in
struction in the JPC register.

This register is not updated when

in EXEC mode.

6.3 QUANTUM COUNTER (QT)
An eighteen bit counter (WD4 bits 17-35) increments at IMHZ rate
except when the processor is PI in progress (or the PI s y stem i s
turned off).

When the counter sets bit 17 it stops a n d se ts the

MEM PROT Flag (PI TRAP mode is not turned on) •

6.4 PURE PROCEDURE
Bit 7 of the PC word is the PURE bit.

It is saved and restored

along with the other bits in the left half of the PC.

Trapping

to EXEC mode (Interrupt or UUO) will clear this bit after it is
stored.

If this bit is on, then instruction fetches which address

pages other than READ ONLY will fault.
the status word is set.

The PURE CODE bit (13) of

This bit can be turned on or off in

USER mode by JRST 2. ,

6.5 ONE PROCEED
Bit 9 of the PC word is the One Proceed bit.

When the current

instruction increments the PC or transfers, then the One Proceed
bit is cleared, and if it was set an interrupt is generated.

MEM

PROT

set and Bit 7 of the PAGING STATUS word is set.

mode

entered and an interrupt should occur before the next i n

struction.

PI TRAP

Instructions that are interrupted out of before adva n c

ing the PC will not clear this flag.

A UUP that transfers to EXEC

mode will interrupt after the JSR to the system UUO handlers.

The

system should simulate the interrupt after the execution of the
call.

6.6 PAGE NON-EX-MEM
NXMs detected during the fetch of a page word wi l l set t h e Pa ge
NXM bit ( 9 ) and the Processor NXM and MEM PROT flags.

The in

st ruction wil l continue with a zero fetched if a Read was reque s t e d.
NXM's detected during an LPM or SPM instruction will set the Page
NXM bit and the processor MEM PROT Flag.

6.7 PARITY ERRORS
Page table references and words referenced by LPM are checked for
parity error by the processor.
Parity Error Flag.

The error will set the processor

Currently, however, the parity stop s wit ch

will halt the machine only on the reference that caused the page
table reference.
processor.

LPM and SPM parity errors will not halt the