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EK-780EH-RM-001

November 1984

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Document:	MS780-EF HJ Memory Options Mantenance Advisory
Order Number:	EK-780EH-RM
Revision:	001
Pages:	48
Original Filename:	EK-780EH-RM-001_MS780-EF_HJ_Memory_Options_Mantenance_Advisory_Nov84.pdf

OCR Text

EK-780EH-RM-001

MS780-E /F
and MS780-H/J

Memory Options
Maintenance

Advisory

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, November 1984

The information in this document is subject to change without notice

and should not be construed as a commitment by Digital Equipment
Corporation. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.

Printed in U.S.A.

The manuscript for this book was created using DIGITAL Standard
Runoff. Book production was done by Educational Services
Development and Publishing in Nashua, NH.

The followingare trademarks of Digital Equipment Corporation:
™

EO OG80
DATATRIEVE
DEC

DECmate

DECnet
DECset

DECsystem-10

DECSYSTEM-20

~—

DECtape
DECUS
DECwriter

DIBOL

Rainbow
RSTS
RSX

UNIBUS

MASSBUS
PDP

VAX
VMS

Professional

Work Processor

P/OS

INTRODUCTION .

....

«6

«©

1.1

DESCRIPTION.

1.2

FEATURES

1.2.1

MS78@-E Memory Option.

....

.«

1.2.2

MS78@-H

PHYS

ICAL

Memory

Option.

TOPOLOGY

1.4

MODULES.

1.5

MISCONFIGURATION

LED

....e...e..«e

1.6
1.7
1.8

SOFTWARE REQUIREMENTS. .« « « « «© « «
MAINTENANCE PHILOSOPHY ......e
THROUGHPUT AND ACCESS TIMES. ... .

CHAPTER 2

MEMORY ADDRESS SPACE ......e.

CHAPTER 3

CONFIGURATION REGISTERS.

.....

3.1

3.2

3.3
3.4
3.5

«
«6
«©

«
«©
©

ew
«© «
© « ¢

CHAPTER 4

SYSTEM BLOCK DIAGRAM.

4.1]
4.2
4.3

BASIC ARRAY CYCLE. .....ee « e
CONFIGURATION REGISTER AND ROM CYCLE
SUBSYSTEM CONTROL AND DATA PATHWAYS.

.......

CHAPTER 5

POWER SUPPLY REQUIREMENTS.

...

CHAPTER 6

DIAGNOSTICS.

APPENDIX A

DIAGNOSTIC USE OF REGISTERS,

MODULE LEVEL FAULT ISOLATION.

i111

MRR RPP eee
'
OW WO DR WDD

CHAPTER 1]

t~
!
ew)

CONTENTS

FIGURES

Configuration Registers .

WW
1
fb

MS788-E/H Block Diagram

mh fA
t
AW UT

fp
'
ly NO

Power Connections

SBI

....

Interface Block Diagram

Memory Controller Block Diagram

Access and Cycle times (in SBI Cycles)

tJ NO

Title

Ww WwW UJ

Table No.
a)
t
_

TABLES

Memory Array Power Requirements

be bp
rt
OU

Module Location Diagram .
MS78@-E/H Assembly Locations.

bh be pu

Whe

Title

!
a

Figure No.

anne Ge GS GES Gee GE Ge ew eee oe ae eee ee oe ee ee oe

Fold PHOT we cme ee cee ee es ee wee ee ee ee oe ae oe ee ee ee ee eee on

ames Ge me Gee ES ae eS Se eS et ee == Do Not Tear — Fold Here and Staple

SOSHRE0

No Postage
Necessary
if Mailed in the

United States

BUSINESS REPLY MAIL
FIRST CLASS

PERMIT NO. 33

MAYNARD, MA.

POSTAGE WILL BE PAID BY ADDRESSEE

Digital Equipment Corporation

Educational Services/Quality Assurance
12 Crosby Drive, BU/E08

Bedford, MA 01730

INTRODUCTION

CHAPTER1
INTRODUCTION
1.1

DESCRIPTION

The

MS78@0-E/F

and

MS788-H/J

VAX-11/788 or VAX-11/785.

are

new

memory

options

for

the

The MS78@-E/F uses 64K MOS RAM chips to

increase the amount of memory available on a single array module
to one megabyte.
The MS78@-H/J uses 256K MOS RAM chips to

increase the amount of memory available on a single array module
to four megabytes.
The MS78@-E/H replaces the MS78@-C memory and
is made up of an SBI

which

can

accommodate

access
16

arrays,

MS78@-E/H assemblies.
a

backplane,

(M8375),

interface and two memory controllers,

SBI

to eight
and

arrays.

single

each of

backplane

the memory can be expanded

two

can

full

An assembly or memory subsystem consists of

interface

board

(M8376),

two

controllers

and an even number of M8373 array boards for the MS78@-E

Or M8374 array boards for the MS78@0-H.
The memory

controllers

internally

interleaved

in the MS78@-E/H assembly.

there is only one controller.
When
assembly iS expanded in two-megabyte
(MS788-H)

increments.

External

interleaving

single

(normal)

when

there

are

two

is noninterleaved when

internally interleaved, the
(MS78@8-E) or eight-megabyte

megabyte

the

MS78@-E

four

same

type

megabytes in the MS78@-H can be added only when the memory is
noninterleaved and there is only one controller in the assembly.

and

size,

and

when

possible with a memory of

both

memories

have

only

one

the

controller.

External interleaving is software controlled; the other forms of
interleaving are hardware controlled.
The MS78@-E or MS78@9-H

cannot be interleaved with an MS78@-C memory.

More than one type of memory can be on a system; however, mixed
types cannot be interleaved with one another.
Each type must have
separate address spaces.
The MS78@0-F refers

to array expansion

refers to array expansion of the MS78Q@Q-H.

the MS788-E,

and

MS786-J

INTRODUCTION

FEATURES

1.2.1

MS78@-E Memory Option
Memory Type:

64K MOS

N channel

RAM.

Memory size:
a.

One megabytes per array

Up to 16 arrays per MS78@-E assembly

Up to two MS78@6-E assemblies per CPU

only two)

Error correction

(VMS now Supports

(ECC):

Single-bit error correction

Double-bit error detection

Memory configurations:
4-Mbyte system expansion, controllers, and

MS780-EA

MS780-EB

248 V,

Cc.

MS78Q8-EC

2-Mbyte system expansion, controllers, and
power

MS78@-ED

248 V,

MS786-FA

2-Mbyte expansion

MS780-FB

4-Mbyte expansion

MS780-FC

6-Mbyte expansion

MS78@-FD

l-Mbyte expansion

MS786-FF

18-Mbyte expansion

power

58 Hz version of MS78@0-EA

58 Hz version of MS78@-EC

1-2

INTRODUCTION

1.2.2

MS788-H Memory Option
Memory Type:

256K MOS

N channel

RAM.

Memory size:
a.

Four megabytes per array

Up to 16 arrays per MS780-H assembly

two MS78@-H assemblies

only two)

Error correction

per

CPU

(VMS

now supports

(ECC):

Single-bit error correction

Double-bit error detection

Memory configurations:
a.

MS780-HA

16-Mbyte
system
and power

expansion,

controllers,

MS780-HB

248 V,

MS786-HC

8-Mbyte system expansion, controllers, and
power

MS78@-HD

248 V,

MS780-JA

~8-Mbyte expansion

MS789-JB

16-Mbyte expansion

MS788-J5C

32-Mbyte expansion

MS786-JD

4-Mbyte expansion

MS788-JF

408-Mbyte expansion

5@ Hz version of MS78@-HA

5@ Hz version of MS78@-HC

1-3

INTRODUCTION

PHYSICAL TOPOLOGY
locations

(refer

to Figure 1-1).

Board

MS78@-E/H assembly location

Power connections (refer to Figure 1-3).

(refer

to Figure 1-2).

MODULE UTILIZATION MS780 E/F, H/J

M8373/M8374 1MB/4MB
19 M8373/M8374 1MB/4MB
M8373/M8374 1MB/4MB
7 M8373/M8374 1MB/4MB
M8373/M8374 IMB/4MB_
15 M8373/M8374 1MB/4MB
14 M8373/M8374 1MB/4MB
13 M8373/M8374 1MB/4MB
12 M8375
UPPER CONTROLLER
11 M8376
SBI INTERFACE
M8375
LOWER CONTROLLER
| M8373/M8374 1MB/4MB
M8373/M8374 1MB/4MB
M8373/M8374 1MB/4MB
M8373/M8374 1MB/4MB
M8373/M8374 1MB/4MB
M8373/M8374 1MB/4MB
M8373/M8374 IMB/4MB
|M8373/M8374 1MB/4MB
M9040
SBI TERMINATOR

oe]

a"
(OTD [SI 00 [CO] O

we]

om)

we)

ee)

— NIGH &

O-NWAWON

ARRAY
NUMBER

SN OORPWN — ©

OPTIONAL IF NOT INSTALLED
USE BLANK MODULE 7014103

PART NO. 3614746-01
MKV84-2600

Figure l-1l

Module Location Diagram

INTRODUCTION

KA780

oo
=

MS780E/H

- z\z

Zz
=

MS780

E/F
H/J

POWER
SUPPLY

TIME-OF-YEAR CLOCK BATTERY
MEMORY BATTERY BACKUP
(OPTION)
869

LSI-11

POWER CONTROLLER
VAX-11/780 SYSTEM CABINET

EXPANSION CABINET

FRONT VIEW
MKV84-1432

Figure 1-2

MS780-E/H Assembly Locations

1-5

INTRODUCTION

J18

J15
J14

J16

S17

7
lf)
GC)
—

J19

J20

H7100
POWER SUPPLY

OP)

OUTPUT |.

+5 RET
(GND)

BUS

POWER

FAIL

J41O

OVER TEMP
O

J5IO
O

TK-10000

Figure 1-3

Power Connections

INTRODUCTION

1.4

MODULES
1.

SBI

interface

(M8376)

One SBI

Decode

Two configuration registers

Data latches

Gd.

Arbitration logic

Control

DBUS (data)
controller

ABUS

interface

board

per

assembly.
This board handles the interactions between the
SBI and the memory.
It contains:

Memory

logic

(A and B)

(registers E and F)

logic
from

(address)

the

SBI

from SBI

controllers

interface

(M8275)

the

memory

to-memory controller

There

are

two

memory

controllers
per
assembly, each of which can access up to
eight memory arrays.
Each controller contains:
a.

Input/output buffer data

Command/address buffer latches

ECC logic

Two configurations registers

Refresh and initialization logic

Controller microsequencer

DBUS (data)
interface

MBUS (data)
arrays

ABUS

from the

from

(address)

the

latches

(C and D)

memory

controller

continuation to memory arrays

1-7

the

SBI

memory

INTRODUCTION

CAUTION

DO NOT place a controller module (M8375)
in slot ll, the location for the SBI

interface module.

this

is done,

-5V

will
be
applied
to
a
chip on
the
controller module and may short out the
chip.

MS78@-E Array modules (M8373) -- Each array module is
arranged in a matrix of 256K address bits by 39 data bits

to produce a one-megabyte array using 64K RAMs.
The 39
bits are made up of a 32-bit longword and 7 ECC bits.

Logic on the array module consists of:
a.

Address MUX

Input data buffers

Output data MUX

ad.

MBUS

MS78@-H

arranged

data

(data)

from array to memory controller

Array modules

bits

a matrix

produce

(M8374)

Each

one megabyte

array module

address

four-megabyte

bits

array using

256K

RAMS.
The 39 bits are made up of a 32-bit longword and 7
ECC bits.
Logic on the array module consists of:

Address MUX

Input data buffers

Output data MUX

ad.

MBUS

(data)

from array to memory controller

MISCONFIGURATION LED

There is an LED on the
is a misconfiguration.
conditions are met:

SBI interface module that liohts if there
The LED lights when any of the following
|

The number of arrays to which each of the two controllers
have access 1s not the same.
For example, if the lower
controller
has
access
to
four
megabytes,
the
upper
controller must also have access to four megabytes.

The arrays are not in consecutive slots.
The arrays have different RAM types.

1-8

INTRODUCTION

1.7

SOFTWARE REQUIREMENTS
1.

VMS Version 3.2 or higher
higher for the MS78@0-H.

for

VMB.EXE Version 3 or higher
(33 blocks)).

(shipped with VMS Version 3.28

the

MS78@-E

and

4.@

MAINTENANCE PHILOSOPHY

The MS78@-E/H maintenance philosophy is the same as that for the

VAX-11/78@
itself,
which
is
module
replacement.
The
Microdiagnostic should provide problem isolation to the board
level.

Should a memory controller failure occur, the MS78@-E/H is capable

of running

in a degraded mode with one controller and

its arrays.

Because the memory detects and corrects sSingle-bit errors, array
modules with such errors should not be replaced until a double-bit
error occurs.

1.8

THROUGHPUT AND ACCESS TIMES

Table 1-1 lists the access times
system for each command type.
A

distinction

made

between

and

Byte

throughput

Writes

and

for

Full

the

memory
:

Writes

(for

both
longword
and
quadword
Writes);
they
involve
different
procedures at the memory controller level and below, and therefore

have different cycle lengths.

In addition, Read accesses that result in single-bit errors
followed by a correction routine that extends their access

are
and

Access

the

cycle times.
Categories of
are included in the table.
time

is defined

Read

cycles

with

correctable

from the SBI point of view.

errors

interval
(in
increments
of
208-ns
SBI
cycles)
from
the
command/address beginning transmission on the SBI (bus T@ time) to
the time that requested data is enabled onto the bus (also T@).
Cycle

time

the

interval

between

commands

the

same

type,

controllers

with

repeated at the maximum rate the memory system can sustain without
returning a BUSY to any requester.
In interleaved modes, it is
assumed

that

the

command

stream

accesses

both

approximately
equal
probability,
with
no
more
than~
three
This takes full
consecutive commands to the same controller.
advantage of the system's interleave capability.

1-9

INTRODUCTION

Table 1-1

Access and Cycle Times
|

Command

Access
Cycle (Interleaved)

Cycle

(Noninterleaved)

Extended Read
Access
Cycle (Interleaved)

Cycle (Noninterleaved)
Longword Write (Byte)

Access
Cycle (Interleaved)
Cycle (Noninterleaved)
Longword Write (Full)
Access

Cycle

(Interleaved)

(Noninterleaved)

Extended Write

(Byte)

Access
Cycle (Interleaved)

Cycle

(Noninterleaved)

Access

Extended Write
Cycle
Cycle

(Full)

Single Error

No
Error

Longword Read

(Interleaved)
(Noninterleaved)

(in SBI Cycles)

lst Word

3
2*

4
2.5

2nd Word

3,4
3*

4,5
3.5

3,5
3

2*
4

2.5
5

3.5

3%
4

Error in
Each Read

Single

4,6
4

5
4

* SBI-limited.
At these cycle times, memory throughput is limited
to the maximum rate the SBI can sustain.

1-18

MEMORY ADDRESS SPACE

CHAPTER 2
MEMORY ADDRESS SPACE
The
28-bit
SBI
address
field
defines
268,435,456
longword
addresses,
which
are
divided
into
two
sections
by
the most
Significant bit.
The lower half is reserved for
memory
and
the
upper
half
is
reserved
for
I/0 space.
For memory alone, this

represents over 134 million longwords, or 512 Mbytes.

The user has access to the phySical address

space

using

the

30-bit
byte
address space available at the console.
Since NEXUS
addresses are longword addresses, the system converts the physical
byte address (3@-bit) to the SBI longword address (28-bit).
From the console, addresses from 08800800 to
1FFFFFFF
are
legal
physical
addresses to memory.
Addresses from 20000000 up are I/0

space.

For information on the

relationship

Backplane Interconnect,

in the VAX Hardware Handbook

address

and

the SBI

longword

address,

between

the

see Chapter

physical

16,

byte

Synchronous

(EB-17281).

CONFIGURATION REGISTERS

CHAPTER 3
CONFIGURATION REGISTERS

oe
e

m& GC) OF

The MS78@-E/H memory uses Six addressable registers (refer to
Figure 3-1).
They are addressed by six consecutive longword
addresses (hex console addresses) beginning at:

20002000
200040808
20006000
20088808

if
if
if
1f

the
the
the
the

memory
memory
memory
memory

is
is
is
is

backplane-jumpered
backplane-jumpered
backplane-jumpered
backplane-jumpered

to
to
to
to

TRIl.
TR2.
TR3.
TR4.

Register A 1s located on the SBI interface board (M8376).
Its
primary function is fault and status information.
It also reports

memory size, RAM type, and interleave mode.
Register

partially

controller boards.

The

upper

the

half,

interface
on

the

and

partly

interface,

stores

the
the

starting address of the system and is on battery-backup, so a warm
Start should not require rewriting.
The lower half is duplicated
on each controller.
Writing the bits in the lower half of the
register causes the bits to be written on both controllers.
Register C, on the lower
upper controller (1), are

controller (@), and Register D, on the
identical in bit assignments and are for

ECC status and diagnostics.

Registers

and

are

interface which store,

two

longword

respectively,

data

the

latches

lower

of a quadword write data.
These two registerS
and read from to verify SBI transfers.

and upper

the

SBI

longword

can be written

The following is a list of the registers and their addresses,

assuming that the TR level of the MS78@-E is l.

wooow»

Address
20082008
20002004
20002008

20002010, 20002018, 2ooozeic |Ms Col .
20002014
Duet Sport

3-1]

CONFIGURATION REGISTERS

ee
NOT

09 08 07

Y
MEMORY SIZE

USED

05 04 0302

uo aes O
ADAPTER RAM
[

CODE

TYPE

INTERLEAVE

MODE

INTVL MODE WRITE ENABLE
CNTR O MISCNFG
CNTR 1 MISCNFG

MISCONFIGURE
CNTR OPAR ERR
CNTR 1PARERR
ERROR SUMMARY
NOT USED
POWER UP
POWER DOWN
TRANSMIT FAULT

SBI MULTIPLE TRANSMIT FAULT

SBI INTERLOCK SEQUENCE FAULT
NOT USED

SBI WRITE SEQUENCE FAULT
SBI PARITY FAULT
TK-10078

28 27

NOT USED

19 18

_—

START ADR

15 1413 12 1110 0908 07 06

NOT USED

JU’

DIAGNOSTIC ECC BITS

NOT USED
“= REF RESH LOCK

DIAGNOSTIC MODE SELECT
——__————- FORCE DBUS PAR ERR
INIT & BATTERY STATUS
START ADR WR EN
TK 10077

™

Figure 3-1

Configuration Registers

(Sheet

1 of 2)

CONFIGURATION REGISTERS

gn Gro ley

C= Cower Onrays.
D=

REGISTERS C AND D)

UL) PEL

Cota ©

2000X008 AND 2000X00C

31 30 29 28 27

11 10 09 08 07 06

—

ERROR ADR
ERROR LOG REQUEST

Lich ERROR RATE
LNHIBIT. CRD
FORCE MICROSEQUENCER PAR ERR

YW.

—

ERR SYNDROME/CHECK BITS
MICROSEQUENCER
PARITY ERROR

LoNOT USED
LeRD FLAG
Ls FLAG

TK-10079

REGISTERS E ANDF 2000X0I0 AND 2000X0I4
31

TK-10080

Figure 3-l

Configuration Registers (Sheet 2 of 2)

3-3

CONFIGURATION REGISTERS

3.1

Jem a S7PO-C

Table 3-1 lists the bit functions and their meanings.
Table 3-1
Bits

Function

SBI Parity

Fault

An SBI information path parity error
has occurred.

Read-only.

SBI Write

Failure of a Write command to be

Fault

Data Format command.

Sequence

used)

followed immediately by a Write

(not

SBI Interlock
Sequence

An Interlock Write command was
preceded by an Interlock Read

SBI Multiple

Received ID is not the same as the

Transmit Fault

Memory was the transmitter when the
error occurred.
Read-only.

25,24

(not

Read

Power Down

A power-down sequence is underway.
Clear when bit 22 is set.
Read/write 1 to clear.

Power Up

A power-up sequence is underway.

Fault
27

Transmit Fault

used)

Reads as

Read-only.

zero.

command.

Read-only.

sent ID.

Read-only.

zeros.

Clear when bit 23 is set.
Read/write

(not

used)

Error Summary

not

Reads

1 to

clear.

zero.

Set if any of the following are set:

Internal parity errors

(Reg.

bits 19, 18; Reg. C bit 7).

Misconfigure warning
17, 16, 15).

(Reg. A bits

Error log request (Reg. C bit 28).
Cleared only when all the above
bits are clear.

CONFIGURATION REGISTERS

Table 3-1

Bits

Function

Description/Interpretation When Set

CNTR

Read data

1 PAR ERR

from the upper controller

to interface had parity error.

data

is sent on SBI with corrected

parity and RDS tag
errors).

CNTR @ PAR ERR

Bad

(double-bit

Read/write 1 to clear.

Same as bit 19 but for the lower
controller.

Misconfigure

CNTR 1 MISCNFG

CNTR @ MISCNFG

14:9

Memory Size

In internally interleaved mode,

set

by an unequal number of arrays with
each controller.

Misconfiguration in upper controller

memory.
Illegal array arrangement
(no arrays or no controller).
Read-only.
Same as

bit 16 but

controller.

for

the

lower

Memory system capacity from 1 megabyte
(GB8B8008Z)

64 megabytes

(lillll).

Capacity is a function of RAM size,
interleave mode,

array boards.
Interleave Mode

Write

735

Enable

Adapter Code

When set,

number

Count is binary.

permits write to bits <2:9>

Fixed set of bits identifying the

MS786-E subsystem.

Read-only.

Bits 7:5 read

Identifies sizes of RAMS on arrays.

RAM Type
Bits

the

which establish interleave mode.
Write-only.
Reads as @.

as @11.

4:3

and

Misconfigured; no array boards in

8
1
1

1
QB
1

256K RAMS (4-Mbyte arrays) (future).
Misconfigured; both array types in

backplane.
|
64K RAMS (ToMbyte arrays).
backplane.

3-5

CONFIGURATION REGISTERS

Table 3-1

(Cont)

Bits

Function

Description/Interpretation When Set

2:0

Interleave

Mode indicated according to the following:

0
9
G

8B
1
8B

86
mH QD

Bits

Noninterleaved lower controller

Noninterleaved upper controller
External

interleaved

(software).

External

Internal two-way interleaved

(software).

these
bits
appropriate

(hardware)

controller

Upon power-up,
configuration

interleaved

lower

(hardware)

upper controller
(hardware).

are
set
according
to
the
hardware
to -the
number and position of memory

controllers present.
Bits are read/write (write-only if bit #8 is
set).
If
there are
two
MS780-Es,
bit
@@ must be set by the
software for external interleaving.
changed;
if
they
are
changed,
result.
|

Bits @1 and @2
must
not
be
a
misconfiguration error will

3.2

Jam

-¢

Table 3-2 lists the bit functions and their meanings.
Table 3-2
Bits

Function

31:28

(not used)

27:19

START ADDR

zeros.

Specifies the memory system starting

address in 1-Mbyte

increments.

VMS

software controlled.
Read/write.
Write when bit 14 is set.

18:15

(not used)

Read aS zeros.

START ADR WR EN.

Enables writing to bits 27:19.

Write-only.

alin

SPrng
I

3-6

CONFIGURATION REGISTERS
Table 3-2

Bits

Function

Description/Interpretation When Set.

13:12

INIT and
Battery
Status

Indicates if memory is coming up from a
cold start and is initializing the
memory, or if valid data is preserved
in the memory arrays.

Bits

Initialization in progress (memory
written with zeros and BUSY to any
SBI commands).

Memory contains valid data.

Initialization completed, no valid
data in memory.

Invalid combination.

Force DBUS PAR’
ERR

When set, Read Data from the controllers
to the SBI interface hasS an error and a
Read Data Substitute is forced.
Register
access is unaffected.
Read/write.

16:9

Diagnostic

There are three diagnostic modes that

Mode Select

exercise various controller functions
and four data paths and their latches.

Read/write.

Bits

1
1

g
1

Normal operation.

Diag. Mode 1 -- Verifies check bit

generation logic and controller data path.

Diag. Mode 2 -- Verifies ECC logic.
Diag. Mode 3 -- Verifies check bit MOS RAMs.

Refresh Lock

Controller cannot execute read/write
cycles when set.

(not

Reads aS

6:0

Diagnostic

used)

ECC Bits

zero.

Loaded with substitute ECC bits in
conjunction with diagnostic modes.

3-7

CONFIGURATION REGISTERS

3.3

REGISTERS C AND D

These registers
controller

are

(slot

(slot 12).

18)

the

and

Same.

the

lower

The function of these registers is primarily for error

logging.

Table 3-3 lists the bit functions and their meanings.

Table 3-3

Registers C and D Bit Functions

Bit

Function

Description/Interpretation When Set

Force

Causes the wrong parity across the 56

PAR ERR

field.

Microsegquencer

Inhibit CRD

High Error

27:11

Read/write.

Prevents single-bit errors from sending

CRD with read data on the SBI.
Error
log requests (bit 28) and CRD error (bit
9) are still set by a single-bit error.
Indicates a second error has been detected

before the first was serviced and cleared.

Error Log

Notification of an error on a memory read.

Error ADR

Memory address to the page level of the

Request

Details of the error are logged
bits. |

error.

in other

Valid only if bit 28 is set.

Read-only.

27
26:24
23322

21:11

or 19:11

RDS Flag

Controller Select
Array Select
Array Bank Select
RAM Page Address

RAM Page Address

CRD Flag

(256K RAMS)
(64K RAMs)

Multiple-bit error detected.
to

Sets bit 7.

Rate

Bits:

PROM bits of the microsequencer data

(future)

Read/write 1

clear.

Single-bit error detected and corrected.
Read/write 1 to clear.

3-8

CONFIGURATION REGISTERS

Table 3-3

Registers C and D Bit Functions

(Cont)

Bit

Function

Description/Interpretation When Set

(mot used)

Reads aS zero.

Microsequencer
PAR ERR

Detected parity error across the 56-bit PROM
data.
Read/write 1 to clear.

6:8

ERR Syndrome/

Stores 7-bit error syndrome or 7 check bits,

3.4

Check Bits

depending on the diagnostic mode set in
Register B.
Read-only.

REGISTERS E AND F

These are the two data latches on the SBI interface board and
may
be
addressed
as
registers
for diagnostic purposes.
After they
have been written to, they may be read from, causing
data
to
be
output

onto

the

internal

DBUS

(data

and sent back onto the SBI through

the

bus also called

SBI

transceivers.

procedure accomplishes a data wraparound within the
controllers need be present.

3.55

the

BUS

interface.

IF)

This
No

PHANTOM REGISTERS

above
addresses,
legal
two
There are two phantom registers, or
may be written to or read from without
that
F
E and
Registers
affecting memory arrays and

result in normal

interface bus cycles.

of the fact that three bits were
reSult
the
is
presence
Their
When
needed to allow legal access to six registers (A through F).
three

bits

These

two

are

used,

eight addresses became available,

having two more legal addresses does no harm,
Register F.

they

are

and

since

included.

phantom addresses are valid for Register E but not for

3-9

SYSTEM BLOCK DIAGRAM

CHAPTER 4
SYSTEM BLOCK DIAGRAM
4.1.

BASIC ARRAY CYCLE

Figures

4-1,

circuit

blocks.

subsystem,

4-2,

showing

and

the

4-3 are block diagrams of

major

A more

signal

thorough

pathways

description

may be found in the MS78@-E and
Technical Description (EK-78@EH-TD).

and

functional

Memory

Subsystems

MS780-H

the MS786-E/H

their

operation

The SBI interface receives commands through its Interface 8646 SBI
transceivers.

- decoded

Command

to determine

and

its

address

information

applicability

latched

and

the memory system.

(These commands are transferred by the information field of the
SBI, B <31:88>).
Command and address information is stored in the

one-deep command/address latch if it is empty. Tests (valid array
address, valid tag and function, and good parity)
are then
performed, and if all tests are positive, the latch is closed
(considered

full)

and

MEM

controller

has

the MEM GO logic.
Each

command/address

asserted

capacity

information

and

for

the

controller

two-deep

associated

data.

from

storage
If

neither

buffer is full, MEM GO causes the deSignated controller to start a
memory cycle immediately at the addressed array board.
If one is

full (a cycle is underway), the command is loaded into the other,
If both
and the SBI interface is again ready for new commands.
are

full,

the

interface

waits

controller becomes available.

with

the

latched

command

until

the

CONTROLLER

GOT

IT,

It refuses new commands on the SBI,

sending back a BUSY confirmation.

The

controller

clearing
latch.

MEM

accepts

and

new

reopening

commands

the

SBI

with

interface

command/address

All memory cycles start as a read of the selected array.

If the command is a Write, the correct write pulse (or pulses for
a gquadword write)
is generated by the controller, and the data

word plus ECC bits are stored in the array RAMS.
If the command

Read,

the data and

the selected array and checked

detection logic.
the controller.

ECC bits are returned

for errors

in the controller

from

error

Good data is passed to the data output latch on

4-]

SYSTEM BLOCK DIAGRAM

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4-6

SYSTEM BLOCK DIAGRAM
In the meantime,

time

the

the SBI interface has been
are

arbitration

controller),

the

satisfied

chip

controller

and

data

(ARB OK

DATA

RDY

out

latch

is passed on to the SBI at the next cycle.

4.2

for’

SBI

received

from

the

data

assumption that data is on its way from the arrays.

When two conditions

bdcl1lel

arbitrating

is’7

returned

enabled

and

from

the

CONFIGURATION REGISTER AND ROM CYCLES

The SBI interface
also
contains
logic
to
check
the
received
address for access to ROM or configuration register space (REG/ROM

ADDRESS DECODE).
When a valid Read command has been decoded,
the
selected
register or ROM output is enabled and the requested data
is made available to the 8646 bus’
transceivers.
Simultaneously
underway.
When ARB OK comes back,

transmitted on

during

SBI

the

cycle.

Arbitration
is
the data can be

commands can load new data into the registers.
4.3

Write

Valid

SUBSYSTEM CONTROL AND DATA PATHWAYS

The three basic elements of the memory subsystem communicate
one another

largely over

three buses:

Between the SBI interface and

ABUS,

DBUS,

with

and ARY BUS.

the two memory controllers,

the ABUS

sends all command/address information to the controllers for array
reads and writes.
This is primarily a one-directional bus,
which
is
always
enabled for maximum speed in initiating memory cycles.

Within

the ABUS,

(Extended

Cycle

perform.

The

the command

Type).

takes only two

lines:

RD/WR and

In conjunction with MEM GO and the mask

bits, these define the varieties of cycles the controllers are
address,

two

controller
and

for

other

ABUS lines are for address: 18 for RAM

bank select,

select.

EXT

three

for board

select, and

one

for

(Some of these lines will be implemented when

if 256K RAMS are used.)

All data transfers between the SBI interface and
the
controllers
and
within
the
SBI interface (REG/ROM accesses) make use of the

32-bit DBUS.
This bidirectional bus sends data
other depending on the phase of the SBI clocks:
1.

From T@

controllers

T2,

can

From T2 to T@,

ath

enabled.

from

the

controller outputs can be

Gata back to the

the SBI.

the

one

way

interface

enabled

the

send

Interface 8646 inputs for transmission on

T2 to T@ time slot.

4-7

SYSTEM BLOCK DIAGRAM

Between

controller

bidirectional

wide

data

(32 data

internal

data

and

its

eight

(maximum)

arrays,

path is designated as ARY BUS.
ECC

bits).

Within

path is known as MBUS, which

the

It is 39 bits

controller,

the

is also 39 bits wide.

On Write cycles, one of the controller input data latches

source of 32-bit data to the MBUS.

the

On the MBUS, there is also ECC

logic which generates the seven check bits
based
on
that
data.
The
MBUS passes them to the array on the check-bit portion of the

MBUS.

back

again,

On Read cycles,

its

controller.

tests the

integrity.

one array is enabled and

Good

returned

data

The

check

passes

sources

bits

the

data

ECC logic examines the MBUS data
bits,

from

and

the

rules

MBUS'

back to the DBUS

through the data output latches for transmission to the SBI.
Address and control

one-directional

and

lines

are

and

RAM SIZE

and

(64K or 256K).

array Slots are occupied

from

always enabled.

Signals used by the controller

PRESENT

arrays

and

permit

the

controller

Each array sources two

SBI interface:

These

are

signals

calculation

MEMORY

identify which

memory size for the SBI interface address test logic.

the

total

POWER SUFPLY REQUIREMENTS

CHAPTER 5
POWER SUPPLY REQUIREMENTS
The MS78@0-E/H requires

a new power

supply with

additional

+5V

power regulator that replaces the +12V regulator used in operating

the MS788-C memory.
The resulting power supply has three +5V
voltage regulators, two of which produce 25 amps and are battery

backed up and one which produces 58 amps and is not backed up.
The memory array requires

only

+5V

power

for

operation.

Table 5-1 lists the power
active and standby states.

requirements for this array
The active state is defined

minimize the power required from the battery backup supply, the
+5V voltage plane has been partitioned into two separate planes
called +5VB and +5V.
Only the +5VB needs to be battery backed up
to maintain data integrity in the event of power failure.

fastest possible operation which is continuously
6@0-ns cycles.
The standby state is defined as
refresh cycles that occur only once per 12.5 usec.
Table 5-1

accessing
operation

the
the

with
with

Memory Array Power Requirements

Active

Standby

Typical

Maximum

Typical

Maximum

MS780-H
MS78@-H

+5VB
+5V

2.50A
O6.75A

3.70A
O.90A

1.33A
O.75A

1.75A
G.90A

MS780-E
MS78@-E

+5VB
+5V

2.89A
G@.75A

3.29A
G.9GA

1.21A
@.75A

1.63A
G.98A

The

in
as

tolerance on both +5V Supplies

voltage aS well as dc variations.

5-1

is +5%.

This

includes

ripple

~ DIAGNOSTICS

CHAPTER 6
DIAGNOSTICS
The only diagnostic designed explicitly for the MS78@8-E/F and the
MS78@-H/J memory 1S ESKAR, or Micro3.
It is run like any other

microdiagnostic.

Below is an example of running Micro2 and Micro3.

Micro2 does not test the MS78@-E and so produces the following:
>>O>T
ZZ-ESKAB V14.@
3D,3E,

CPU TR = @8080019G
MS780-E 64K CHIP AT TR @@000001
MAX ADDRESS+1l= @0280809
DW780 AT TR @08B00B3

RH78@0 AT TR @BGBGRBH8
RH78@ AT TR @8BEBBE9
NO MEMORY CNTRLLRS
DEP CNTRLLR ADDR IN RC@ AND TY LO
?ERROR:

lICA

TEST:

TRACE: @8,
FALLING MODULES:

@17D

SUBTEST:

M8214,

MIC>

6-1

(Micro2 recognizes MS78@-E
memories but fails when it
tries to test them.)

9801
(Not a module in
MS780-E/H.)

the

DIAGNOSTICS

Running Micro3 with
>>>T
ZZ-ESKAB

the MS788-E produces the following results:

V14.@

ESKAR-V2.9
3D,3E,
CPU TR - @800001B
MS78@E 64K CHIP AT TR @80060001
LOWER CNTRLLR
MAX ADDRESS+]1= 65190000
UPPER CNTRLLR
MAX ADDRESS+1= 90180000
DW788 AT TR @B8B8B03
RH/788 AT TR @8600GBB8
RH78@ AT TR @88BGBB9
3F,40,41,42,43,44,45,46,47,48,49,4A,4B, aC, 4D,4E,4F,58,51,52
MS780- EF IO BASE ADDRESS = 28082000
LOWER CONTROLLER MAX ADDR + 1 = @81000G8
BOARD NUMBER = @@0098800
NUMBER OF CRD ERRORS = @0000000
MS78@0-EF IO BASE ADDRESS = 200620090
UPPER CONTROLLER MAX ADDR + 1 = GOB1GB0GG
BROAD NUMBER = @¢6@880000
NUMBER OF CRD ERRORS = @80000900

53
MS78G-E 64K CHIP AT TR G009G001

M8376
ROMS OK
54,55,56,57,58,59,
STARTING FPA TESTS
5A,5B,5C,5D,5E,5F,68,61,62,63,64,65,66,
END OF PASS @¢6@1
|
MIC>

Upon detection
failing module.

error,

Micro3

6-2

prints

the

number

the

DIAGNOSTICS

Running Micro3 with the MS78@-H produces the following results:
>>>T
ZZ-ESKAB

V14.9

ESKAR-V2.0
(ETKAR-V3.@ FOR THE VAX 11/785)
3D,3E,.
CPU TR - G@89009010
MS78GH 256K CHIP AT TR 88000001
LOWER CNTRLLR MAX ADDRESS+l= 66490000
UPPER CNTRLLR MAX ADDRESS+t1l= 99400000
DW788 AT TR 90000003
RH786 AT TR GGGGG008
RH788 AT TR GB9G0B09
3F,40,41,42,43,44,45,46,47,48,49,4A,4B,4C,4D,4E,4F,50,51,52
MS78G-E/H IO BASE ADDRESS = 20092008
LOWER CONTROLLER MAX ADDR
1 = 09490000
BOARD NUMBER = @GG00000
NUMBER OF CRD ERRORS
g@0000G0
MS78G-E/H IO BASE ADDRESS
29002000
UPPER CONTROLLER MAX ADDR + 1 = 99400090
BOARD NUMBER = 66000000
NUMBER OF CRD ERRORS
GOGCGHBG

53,
|
MS78@-H 256K CHIP AT TR @@@00001
M8376
ROMS OK
54,55,56,57,58,59,
STARTING FPA TESTS
5A,5B,5C,5D,5E,5F,60,61,62,63,64,65,66,
END OF PASS @@1l
MIC>
Upon

detection

error,

Micro3

prints

modules that could produce such an error.
NOTE ETKAR is V3.8 and ESKAR is V2.@.

6-3

the

number(s)

the

DIAGNOSTICS
There are a number of Simple things that can be done on the system
to verify or detect problems.
NOTE

Before performing these exercises, be sure to

turn
cache
off by typing >>>D 1D 18900.
If
this is not done,
Read
commands will
read
cache, not memory.

Read and write to
For example,
SBI

registers on the SBI interface

reading and writing the data latches

interface board

(Registers E and F)

amount of logic on that board.

without

the

(M8375):

controller

boards

example with no controllers:

test a

Below

the

with

significant

This may be done
present.

on_

1iS~—

>>>E 20082080 /N: 3

20002000

P
P
P

20082004
20002008
2000200C

>>>D/Q 20002619
>>>E/N:5

@G8188E68

@OO0FFFF
@OOFFFFFF
QOOFFFFFF

!REG A

!REG B
!REG C
!REG D

!@ DEPOSITED

20802800

YEXAMINE

20082000

QO@188E68

P
P
P
P
P

208082004
280002008
20860280C
200820108
20002014

988000008
880980008
9880008009
@8880008
@8800008

(lower

LATCHES

REGS A - F

!BITS SET -— ERROR SUMMARY,
!MISCONFIGURATION

!DATA LATCH
!DATA LATCH

(REG E)
(REG F)

Read and write to registers on the controllers
Register C

DATA

the arrays each controller addresses.

controller
12)
slot

slot

18)

and

(M8375):

have a few bits that can be
record
errors
written, but their primary function is_
to

(upper

controller

associated

with

better test of its logic is
memory arrays.

6-4

read

and

write

the

DIAGNOSTICS

Read and write to memory arrays:

Here 1S a way to test mask functions and
For example:
and reads.

extended

writes

>>>E B
P

8000800008

O8000000

88800800

SOBB0000F

@80800000

ABB00FOF

>>>D/B @ F
POE @
P
>>>D/B 1 F
>>>E @
P

>>>D/W 2 FOFO
>>>E BO

@§8000000

FOFOOFOF

@OBECERCLH

BLBBULBO

>>>D/L B B
>>>E @
P

>>>D/Q @ FFFFFFFFFFFFFFFF
>>>E/Q @
P

@0000000

FFFFFFFFFFFFFFFF

Effectively, these exercises have tested most of the
used in the memory.
Errors will be apparent.

6-5

logic

DIAGNOSTICS
Moving controllers:
If Micro3 identifies a

controller

problem

(M8375),

the

problem can be followed by exchanging the positions of the
two controllers, rerunning the diagnostic,
and
verifying
that

the failing controller

For example, move

the board

is indeed the failing module.

slot

and

place
the
board
in
slot 12 in slot 18.
Then rerun the
Giagnostic.
The
failing
module
should
have
moved,
eliminating the possibility of a problem other than on the
module.

APPENDIX A

APPENDIX A
DIAGNOSTIC USE OF REGISTERS,
MODULE LEVEL FAULT ISOLATION
This appendix describes various diagnostic modes available for
use.
This information is being supplied to allow exploration of
other more sophisticated methods of diagnosis.

A.1_

REGISTERA

and

the

ORed

result

plus

the error summary bit requested by VMS.
internal

misconfiguration

warnings

bit 20 to read a

zero.

bit

parity errors

(Register

plus

bits

(Register

16,

and

A bits

bit

15),

7),

and

error log request (Register C bit 28).
Bit 2@ cannot be directly
cleared because all contributors must be individually cleared for

A.2

START ADDress is present in Register B bits 27:19 during powerup.
The start address may be respecified by loading bits 27:19 with

another address.
The MS788-E minimum starting address increment
is one megabyte.
The MS78@-H minimum starting address increment
is four megabytes.
Bits 15:@8 of Register B are on the memory
controllers.
Any bit asserted represents an OR of that bit

contained in both memory subsystems.

both controllers.

FORCE

DBUS

PAR ERR

asserted on all three boards.
On
bad
returns
controller
addressed

A Write to these bits writes
(bit

11),

when

written,

subsequent Read cycles,
data
Read
parity with

the
for

transmission to the RDS tag.
It should also set Register A bits
19 or 18, depending on which controller was addressed.

APPENDIX A

Bits 18:99 set up diagnostic modes for controller and memory array

testing.
1.
2.

Diagnostic Mode 6 -- Bit 18

operation.

bit

Normal

Diagnostic Mode 1 -- Bit 10 = @, bit 9 = 1:
Verifies
the
check
bit
generation logic.
A Write to memory arrays is
performed normally, but the check
bits,
in
addition
to
being stored on the array with data, are also written into

Register C bits @6:088.
A subsequent Read
to Register C
can recover the seven check bits and verify the generating
logic.
Reads and Byte Writes are normal.

Diagnostic Mode 2 -- Bit 186 = 1, bit 9
=
@:
Tests
the
error
correction logic.
Writes are performed normally;
Read commands take the
32
data
bits
from memory
but,
instead
of
using
the
seven
check bits stored with the

data, substitutes seven bits of Register
B
(6:06).
By
loading
these
to
appropriate
values for a known 32-bit
longword stored

sSingle-bit

in memory,

error

correction cycle,

altered

longword

complementing

sent onto

that

the

selected

the SBI with

the

expected

Diagnostic Mode 3 -- Bit 10 = 1, bit 9 = 1:

Writes

are

normal.

cause

determination by the ECC logic and a

can be checked to see
flipped.

the substituted bitS can

Reads,

bit.

The

has_

been

a CRD flag,

bit

ECC

and

bypass.

data passes through the

controller
without’
the
normal
error
checking
and
correction.
This gives direct access to data as it is on
the

arrays.

longword

are

In addition,

the check bits stored

with

written into Register C bits 86:88 on every

Read.
This permits the diagnostic to effectively
the full 39 bits as they are stored on the arrays.
Register B bit 8 is a refresh lock bit.
controller

the

perpetually

busy

with

While

examine

set,

the

refresh cycles and cannot

execute a commanded Read or Write.
In
this
state,
a
pair
of
extended
Write cycles loads up the full set of input data latches
of the controller.
The latches are
tested
by
loading
them
as
described,
and
then
clearing
the refresh lock bit.
The Writes
Should then take place and a set of

Read

addresses verifies that the data is intact.

commands

the

same

APPENDIX A

The controller data rewrite latch is exercised
by
commanding
an
extended
Byte
Write
(mask not equal to 1111 on both longwords).
The data already at the addressed location which is to be retained
(not
written
over) passes through the rewrite latch before being
rewritten.
The locations (two longwords) should be prewritten
so
is returned and can be checked by Read commands
data
known
that
later.
Finally extended Read commands fill both data out
latches
and should be used to test them.

A.3

REGISTERS C AND D

Attempted access to Register C or
interleave

mode,

possibly to

that

incompatible

a nonexistent controller,

with

results

a normal register cycle for both Read and
Write
commands.
Data
returned
on
a
Read is not valid.
This is also true for the two

phantom register locations above Registers E and F.

In Registers C and D, bit 31 forces
a
controller
microsequencer
parity
error,
if
set.
This should result in bit 7 of the Same
register being set as well as the Register A error Summary bit.

Bit 30, if set, prevents single-bit errors from

flag
with
Read
data on the SBI.
The error log
and the CRD error (bit 9) are still set, however.

(bit

29)

set

the

CRD

request (bit 28)
High Error Rate

anew single- or multiple-bit error occurs

before the previous one has been cleared.

Error Log
Request
(bit
detectable
data
errors.
Read,

sending

28)
is
set
by
any Read
cycle
with
Although
Byte Writes involve a memory

they do not set this bit,

the RDS flag

(bit 18), or the

CRD

flag
(bit 9).
In the event of a sSingle-bit error detected during
a Byte Write, the error is corrected but no
record
is
kept.
A

multiple-bit

error

being rewritten into
subsequent
Read
to

results

in the bad data,

including

check bits,

memory
exactly as
it
was
read
out. A
the location discovers the error and logs it

properly.

Error Address
(bits
multiple-bit errors.

27:11)
are loaded following single- or
If
it was filled with the location of a

single-bit error and a multiple-bit error follows before the first
was
logged,
the
multiple-error
address overwrites the original
original
the
keeps
errors
two
Any other sequence of
address.
of the error address field are not valid
contents
The
address.
unless bit 18

(RDS)

or bit 9

(CRD)

is set.

MS780-E/F AND MS780-H/J

Readers Comments

MEMORY OPTIONS MAINTENANCE
ADVISORY

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