Digital PDFs

YG-C04UC-00

April 1988

175 pages

Original

8.7MB

Document:	Q-Bus IO Modules
Order Number:	YG-C04UC-00
Revision:	0
Pages:	175
Original Filename:	YG-C04UC-00_Q-Bus_IO_Modules_Apr88.pdf

OCR Text

SOCORED
SCORED
SOCOREO
SOO
SCORED
SOCORE0
SCORED
Q-BUS

1/0-MODULES

IDVIS-A,

IDV1S-B,

IDV1S-C,

IDV1S-D,

ITAVIS-A,

IAVIS-AA,

IAV1S-B.

IAV1S-C,

IAViS-CA

MODULES

Computer Special Systems

NOTEBOOK

IL
|

- 35

|
|
il

I
I
L

DATE

APRIL

REVISION

J
|

YG-CQ4UC-9¢

NUMBER-~

I
|

NUMBER

DOCUMENT

|
]|

YG-CP4UB-Bp

PROGRAM

NUMBER

SET

||
|
|
|

DRAWING

JAN

NUMBER

|
I

OPTION

4.3.

SECTION

1928
1988
Q-BUS

1/0-MODULES

IDVIS-A,

IDV1S-B,

IDV1S-C,

TAVIS-A,

IAViS-AA,

IAV1IS-B.

TAV1S-CA

MODULES

IDV1S-D,
IAVIS-C,

Computer Special System:
MUNICH

Digital Equipment Corporation 1988
ALL RIGHTS RESERVED

The information in this document is subject to change without notice and should be construed as a
commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.

Book production was done by Computer Special Systems Documentation Services.

The following are trademarks of Digital Equipment Corporation:

rag

DEC
DECmate
DECset

DECwriter
DIBOL
MASSBUS
PDP
P/OS

RSX
Scholar
ULTRIX
UNIBUS
VAX

DECSYSTEM-20
DECUS

Rainbow
RSTS

VT
Work Processor

DECsystem-10

Professional

VMS

CONTENTS

INPUT

(M5026-P0)
| l
bolod
POWOAIAA ARR We

Buffer

Status

(DAT)

DESCRIPTION

tol

(CSR)

OPTO

Site
Consideration
Interconnection

Initial

OPERATION

General

Operation

AND

OUTPUT

(M6029-—P0)

GENERAL
DESCRIPTION
SPECIFICATION
INSTALLATION

ISOLATED

2-14

16-BIT

NNN

Theory of Operation
Mode of Operation
User Input Signals
.
Interfacing
to the IDVv1S- A

W NO
m™

and

rr i

Data

(MOD)

bb
Nr

Input

Control

PROGRAMMING.

AND

General
.
Mode Register

FUNCTIONAL

WN FF

NO BO
EE NNNNNNNNDNDNLO
rl

Site Considerations
Interconnections
Initial Operation

ISOLATED

PH
GB BW

OPTO

PROGRAMMING.

BIT

rPrRwWOOO~AIAYAANIWeE

PPP

Vot'!td

RRP

i
| PRP
re |

Class
°

hb
m Wh

102,

FE
WH FF

& FH BH WWWWDN
MONON

OPERATION

Fe
WWD

Standard

GENERAL
DESCRIPTION
SPECIFICATION
INSTALLATION

IDV1S-B

DEC

Module
Family Diagnostic
for LSI 11 Processors
Module Diagnostics
for MicroVAX- Processors
Maintenance
Philosophy

IDVIS-A

(per

I/O-Connector

> bo

Environment

User

on |

2
System Enclosure.
and Configuration Rules
Checkout on Micro-PDP11
and Checkout on MicroVAX

CUR Ww)

Module
Format
BA2Z00-Series
Installation
Installation
Installation

HH HBWNE
AHHH
S&S
OnIN

}-~—

Oi On

O1 mm WN
IOV

PRR
b>

RP RPP RPP PPP

OVERVIEW

MAINTENANCE

NO
WWW
W W W
WW

CHAPTER

SET

GENERAL
:
ADDRESS
AND VECTOR ALLOCATION
MODULE
IDENTIFICATION
.
COMMON
INSTALLATION
PARAMETERS

WN
N
NI NNNNNNNNNNNNN

CHAPTER

MODULE

1
PPE

CHAPTER

(DAT)

(M8005-P0)
HWE

HAHAH

(DAT)

RPWOWWO

DESCRIPTION

OATANAAN

PROGRAMMING.

General
.
Mode Register
(MOD)
Output Data Register

Theory of Operation
User Output Signals
.
Interfacing
to the IDVIS- C
ISOLATED

D/A

CONVERTER

(A6007-P0)

O1 &

WN Fe

m™

DESCRIPTION

IAVIS-A/AA

WN Fe

(CSR)

Theory of Operation
Mode of Operation
Calibration
Analogue Output Signals”
Interfacing
to the IAV1S-B
CHANNEL

GENERAL
DESCRIPTION
SPECIFICATION
INSTALLATION

UO
OF OT UN)

FUNCTIONAL

PROGRAMMING

AND

General
.
oe
ew
Mode Register
(MOD) —
DAC Data Register
(DAT)
Control
Status Register

WW Fe

OPERATION

Site Consideration
Interconnection
Initial Operation

O11 On

WN Fr

GENERAL
DESCRIPTION
SPECIFICATION
INSTALLATION

Site
Considerations.
Interconnection

Initial

Operation

|
i i es
b> O © © U1 U1 U1 U1 WF

4—-CHANNEL

A/D

CONVERTER

(A410-P0/PA)

AND

OUTPUT

HAHAHA AHHH
AS
| Ptod@bt
t ot
dd

RELAY

Site Consideration
Interconnection
Initial Operation

FUNCTIONAL
WN Fr

WWWDNe
HW

WN Fk
WNhNr

b&b
NUNN

HBWWWWDYPF
PARP
NAB
NUN

16-BIT

OPERATION

Dd
WW

DESCRIPTION

Theory of Operation
User Output Signals
.
Interfacing
to the IDV1S- B

IAVIS-B

(MOD)

i
| & LHL
| Lr i t

Ww WN
WN Fk

&
&
mmo

Wy WY WW
W W
SS

Data

GENERAL
DESCRIPTION
SPECIFICATION
INSTALLATION

OF
OV OV OV
OV OV

CHAPTER

IDV1S-C

O?’

O71 ON O71 OF

OT OF O1 OF U7

UI OF O1 OF

OT UO

CHAPTER

Output

FUNCTIONAL

Aae

CHAPTER

Mode

Wd Fe
m

FUNCTIONAL

Status

WN Fr
&
Mm

MULTIPLEXER

~S) ~1

botedtod

IAV1S- C

FIVE

CHANNEL

GENERAL
DESCRIPTION
SPECIFICATION
INSTALLATION
WN Fr

Site

(M7197-P0)

Considerations.

INTERCONNECTIONS

Initial

OPERATION

Wh FF

General

WN Fe

1
2

WWWWWNRrR FP

NNMWNNNNNNNR
FRR R

COUNTER

Operation

AND

PROGRAMMING

Mode Register
(MOD)
oe
Status And Command Register
(SCR)
Counter Control Register
(CCR)
Interrupt Register
(INR)
Programming The Counter Module. .
Status And Command Register
(SCR)
Status Assignment
.
Command Interpretation
.
Counter Control Register
(CCR)
Application Examples
.
Event Counting
Pulse Duration Measurement
Output Signal Generation
Frequence Output Generation

l
te

DESCRIPTION

WN Fr

{

PROGRAMMING

Theory Of Operation
Analogue
Input Signals
.
Interfacing To The IAV1S--C/CA.

Jans
SY) YJ) YS) YS) SY) ~Y)

YS ~~
SN
YI
YY

WW
&

AND

General
Programming “The

SJ SI SY)

OPERATION

Inns

EXPANSION

Site Considerations
Interconnection
Initial Operation

CO
OO
WWWWWW
MO
WO
WO
MO
WMO

KBHHHABHBWWWWD PF
KH

ODDO

CHANNEL

6-10
6-10
6-12
6-13
6-13
6-15
6-15
6-15
6-18
6-19
6-22

GENERAL
DESCRIPTION
SPECIFICATION
INSTALLATION

IDV1S—D

HAH

(CSR)

Theory Of Operation
Mode Of Operation
A/D Converter
Calibration
.
Analogue
Input And Control
Signals
Interfacing To The IAVIS-A/AA

FUNCTIONAL

EHP

(DAT)

Reqister

DESCRIPTION

(AQ029-P0/PA)

MOoOO

PROGRAMMING

NOWWWOWOOWOADNUIUI
UWI WF

&
& & Kh
Mmmm

Control

~~]

OV OV OV OV OV OV OV OV OV OD OD

ADC-Data

ITAVIS-C/CA

CHAPTER

AND

General.
2 8 ee
Mode Register
(MOD)

CHAPTER

OPERATION

8.4.2.3.5
8.4.2.3.6
8.4.2.3.7

Pulse Output Generation
UP/DOWN Counting
Concatenated Counter Channel

8.5

FUNCTIONAL

APPENDIX

Q-BUS

I/O

APPENDIX

FIELD

TEST

8.5.
8.5.2

8-32
8-33
8-35

DESCRIPTION

8-36

Theory Of Operation
2 ee
ee
ww
ww
we)
User Input Signals
.........
6.6...
MODULE

SET

OPTION

6836
8-39

LIST

EQUIPMENT

FIGURES

NMP

KAANANANANAA

_
-

Address
Selection
Vector Selection
I/O-Connector Dimensioning
I/O-Connector
Pin Arrangement
2 ee
IDV1S-A Simple Block Diagram
(M5026-P0)
Selecting
IDV1S-A Device Address
Selecting
IDV1IS-A Interrupt Vector
IDV1IS-A Physical
Layout M5026-P0
IDV1S-A Mode Register
.
2 ee
IDV1IS-A Input Data Buffer
IDV1S-A Control
Status Register A Interrupt
Generation
IDV1IS-A Application Circuits
(M5026- -PO)
IDV1S-B Simple Block Diagram
(M6029-P0)
Selecting
IDVIS-B Device Address
IDV1S-B Physical
Layout M6029-P0
IDV1IS-B Mode Register
2
IDV1S-B Output Data Register
.
IDV1S-—-B Application Circuits M6029- PO.
IDV1S-C Simple Block Diagram M8005-P0
Selecting
IDV1S-C Device Address
IDV1S-C Physical
Layout M8005-P0
IDV1S-C Mode Register
2
IDV1S-C Output Data Register
2 ee
ee
IDV1S-—C Application Circuits
(M8005-P0)

IAVIS-B

Simple

Block

Diagram

(A6007-P0)

Selecting
IAV1IS-B Device Address
IAV1S-B Physical
Layout
(AGOOT-PO)
IAVIS-B Mode Register
oe
IAV1S-B DAC Data Register
IAV1S-B Control
Status Register
IAVIS-B DAC-Circuit
(A6007-P0)
..

Connection

the

IAV1S-B,

(A6007-P0)

IAVIS-A Simple Block Diagram A410-P0
Selecting
IAV1IS-A/AA Device Address
Selecting
IAVIS-A/AA Interrupt Vector
IAVIS-A/AA Physical
Layout
(A410-P0/PA)
ITAVIS-A/AA Mode Register
oe
ee
IAVIS-A/AA ADC Data Register

.
.

1-3
1-4
1-9
1-10
2-2
2-4
2-5
2-6
2-9
2-9

2-10
2-14
. 3-2
. 3. 3. 3. 33-1
. 4» 4. 4» 4. 44—j

MINIMUMS
& HHH BW WW WW

WwW

—
~
—
_
_
~
-

WNORFPONANNHNDUMNIARWNRP
DAMN
HBWNHR DOH WN FO

1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
2-6
2-7

5—
5
5

RPrRWOOAINDONABWNHRKRWNEF
FO
OO
©

{

OOMWDWOOMO
@®O ~) ~~~ OAO)
MADDOW
Om

IAVIS-A/AA
Generation
IAVIS-A/AA

Control
ADC

Status

Circuit

Interrupt

(A410-P0/PA)

Single-Ended Analogue
Input
Isolated Differential
Input
IAVIS-C/CA Simple Block Diagram
Connecting the MUX Cable
1
Selecting
IAV1S-C Channel Address”
.
IAV1S-C/CA Physical
Layout A029-P0/PA
IDV1IS-D Simplified Block Diagram
(M7197-P0)
Minimum Input Pulse Duration Time
2
Selecting
IDV1S-D Device Address
.
Selecting the IDV1S-D Interrupt vector
IDV1S-D Physical
Layout M7197-P0
IDV1S-D Mode Register
.
IDV1S-D SCR Status and Command Register.
IDV1S-D Counter Control Register
IDV1S-D Register Assignment
Diagram of all Subordinate
Registers
Status Register Bit Assignments
Frequency Output Control Register Bit Assignments
Channel Mode Register Bit Assignments
Output Control Logic
Counter Output Waveforms
UP/DOWN Counting Controlled By Gate- Signal
Concatenation Counter . .
2
IDV1S—-D Simple Block Diagram
(7197-P0)
Test Connector Adapter Cable
.
Digital
I/O Test Connector
Analogue
Input Test Connector
Analogue Output Test Connectors
Five Channel Counter Test Connector

RPWNRNRNRWNER
NORrROIARWNF

SAANAAUAAAAMaNIMNaIMNINS

BWWNNNE

FEF

TABLES

Module
Identification Codes
.
IDV1S-A MOD Register Bit Assignments
CSR

Bit

Assignment

IDV1S-A Connector Jl Pin Assignment
(M2026-P0)
IDV1IS-B MOD-Register
Bit Assignments
.
.
IDV1S-B Connector Jl Pin Assignment M6029- -PO
IDV1S-C MOD-Register
Bit Assignments
..
IDV1S-C Connector
Jl Pin Assignment M8005- -PO
IAV1S-B MOD Register Bit Assignments
.
IAVIS-B CSR Register Bit Assignment
IAV1IS-B D/A Coding Tables
2
IAV1IS-B Connector Jl Pin Assignment “A6007- -PO
IAVIS-A/AA MOD Register Bit Assignments
IAVIS-A/AA CSR Register Bit Assignment
IAVIS-A/AA ADC Coding Tables
.
IAVIS-A Connector
Jl Pin Assignment “A410- PO.
IAVIS-AA Connector
Jl Pin Assignment A410-PA
IAVIS-C Connector Jl Pin Assignment
(A029-P0)
IAV1IS-CA Connector
Jl Pin Assignment
(A0Q29-PA)

“4-10
5-20
6-12
6-14
6-17
6-20
6-21
7-10
7-11

WN FR
®&
On

Counter
Register
Set
MOD Bit Assignment
INT Bit Assignment
Command Summary
Data Pointer Command

8-12
8-13
8-17
8-20
8-24

prevent

einen

only

electrical

with

SELV(

Warning!
shock

safety

extra

Warnung!
elektrischen
Schlag

low

voltage)

energy

hazards,

vermeiden,

sind

heits-Kleinspannungsstromkreise

(SELV)

circuits

TBTS

(tres

basse

Atencion

nur

Sicher-

anzuschlieffen(IEC435).

Avertissement!
Pour
eviter
on
choc
électrique
ou
transfer
d’énergie
mettre
en
contacte

les

interface

equipment(IEC435).

tension

peligro!

Para impedir un choque electrico
solo
circuitos
de
baja
tension
seguum

des
dangers
de
seulement
avec

securité)IEC435.

se debe
norma

conectar
IEC435.

Varoitus!
Sahkoiskujen valttamiseksi
liita ainoastaan
turvallisuuspienjannite
(SELV)
laitteita
(IEC435).
For

att

far

undvika

endast

utrustning

Varning!
elektrisk
chock

SELV

(Saker

anslutas

(IEC435).

extra

eller

lag

annan

fara

spanning)

Waarschuwing!
Om een elektrische
schok te vermijden,
alleen aan
veiligheids
lage
spanning
stroomcircuik
(SELV)
aanslniken
(IEC435).
Attenzione!
Per prevenire
scosse elettriche
o pericoli
di fulminazione
Sl
raccomanda
di utilizzare
solamente apparecchiature
o
strumenti
a bassissima
tensione di sicurezza
(IEC435).
For

der

Advarsel!
personskade
eller

forebygge

kun

tilsluttes

For aa
hindre
tilknytt dette

spenning.

ekstra

Advarsel!
elektrisk
sjokk
utstyret kun mot

(IEC435

spenning

anden

isoleret

eller
utstyr

lavere

skade,

lavspendings-udstyr.
annen_
skade,
med ekstra lav

enn

42.4

Volt)

CHAPTER
MODULE

1.1

SET

OVERVIEW

GENERAL

This manual
includes
information on a series of boards
that
are
I/O
options
for MicroVAX and MicroPDP11
Q-bus processors,
based
on BA200-series
system enclosures.
Each board may
be
used
by
itself on the Q-bus,
but typically each is used with one or more
of the other boards
to create a small
I/O system.
These boards are especially appropriate
for use
noisy
environment,
since
most
I/O
circuits
isolated from the computer power.
This
allows
mode voltage
for the field signals.
The

family

IDV1S-A
IDV1S-B
IDV1S-C
IAV1S-B
IAVIS-A
IAVIS-AA
IAV1IS-C
IAV1S-CA
IDV1S-D

includes

the

following

in
are
a

modules:

16-BIT
OPTO
ISOLATED
INPUT
16-BIT
OPTO
ISOLATED
OUTPUT
16-BIT
RELAY
OUTPUT
4-CH
ISOLATED
D/A CONVERTER
4/12
CHANNEL
A/D CONVERTER
16 CHANNEL
A/D CONVERTER
16-CHANNEL
FLYING
CAP.
MULTIPLEXER
16 CHANNEL
EXPANSION
MULTIPLEXER
FIVE
CHANNEL
COUNTER
MODULE

electrically
electrically
high
common

(M5026-P0)
(M6029-P0)
(M8005-P0Q)
(A6007-P0Q)
(A410-P0)
(A410-—-PA)
(A029-P0)
(AQ29-—PA)
(M7197-P0)

The IAV1S-C/CA
is
an
add-on
option
to
the
IAVIS-A/AA
A/D
converter.
The 16 channels of the IAV1S-A can be expanded with
several
IAV1S-C
multiplexer
boards
for
a
higher
number
of
analogue
inputs.
NOTE

The

Q-bus

IxV1S

module

enclosure

compatible

standard
Q-bus
I/O-connectors.

family
the

for

software

Ixvll

enclosures,

the

and

module
but

BA200

series

functionally

family

have

for

different

MODULE
RELATED

SET

OVERVIEW

1-2

LITERATURE

The following
provide added
——~
——-

Page

manuals provide Q22-bus
signal
specifications
and
information on other Q-bus options
respectively:

BA2xx Enclosers
Microcomputer
Products Handbook
Microsystems
Handbook
MicroVAX CPU Module User’s Guide
MicroVAX II Technical
Manual

MicroVAX

Systems

These manuals
office.
FCC/FTZ

USER

are

Maintenance

available

Guide

through

your

local

DIGITAL

sales

STATEMENT

This equipment generates,
uses,
and
may
emit
radio
frequency
energy.
The equipment has been type tested and found to comply
with the limits
for a
Class
A
computing
device
pursuant’
to
Subpart

Part

FCC

rules,

which

are

designed

provide

reasonable protection against such radio frequency interference.
Operation
of
this
equipment
in
a residential
area may cause
interference
in which case the user at his own expense
will
be
required
to
take
whatever measures may be required to correct
the interference.

MODULE

SET

OVERVIEW

1.2

ADDRESS

AND

facilitate

Page

VECTOR

the

the
registers
of
manner and arranged

use

ALLOCATION

the

ADDRESS

The

boards

described

all
the
boards
are
in the same sequence.

Per module,
there are always
address
range
reserved even
digital
output boards).
The first
used
by
recognize

structured

this

manual,

the

same

four word addresses
from
the
if only two are required
(e.g.

I/0
the

which
handler

is
to

range

RANGE

device

~ 160000

octal

address

177770

octal.

set

switches

within

The I/O boards described here should be
configured
with
addresses
in the following
standard device address
range:
modules
modules
Each
four

without
interrupt
171000
with interrupt 171400
to

Address

Selection

#12

#«+11—~«1f

| X

fixed

Standard
Figure

| X

Switched

Addresses:
1-1:

Address

171000
171400

to
to

Selection

their

to 171370
171770

range covers an address possiblity of 32(dec.)
boards
registers are reserved per module
(Figure
1-1).

<—

1-3

171370
171770

8 @

| x

| X

| x|

progr.

(without
interrupt)
(with interrupt)

when

MODULE

SET

OVERVIEW

VECTOR

RANGE

Page

The interrupt vector
of 0 to 770 octal
in

address
is
increments

set by switches
of 10 octal.

within

the

1-4

range

Those modules with interrupt
capability should be located
in the
standard
address
range
from
171400
to 171770.
If the vector
bits 3 to 8 are switched to the same
position
as
the
address
bits,
a
vector
range of 400 to 770 octal
is available
(Figure
1-1).
This

vector

modules,

interrupt

Vector
15

range

means

because

two

capability.

vectors

(decimal)
are

vectors

reserved

for

and

every

(decimal)

module

with

Selection

o |

| 0

x |

<——_—_——
Standard

Figure

Vectors:

1-2:

400

Vector

switched

| %

-——— ><

progr.

0
>

770

Selection

NOTES

The recommendations
for address and vector
ranges’~
and
the
factory
configured
addresses and vectors
in this
manual
refer
to
XXDP-diagnostic
(MicroPDP11)
requirements
of
the
Ixv1lS module
set.
The addresses
assigned by the XXDP
diagnostic
should
be
used _ for
RSX11 handler
software
too.

The MDM diagnostic
on MicroVAX
needs
other
addresses
and
vectors
which have to be assigned in the floating
device address
range
if auto-configuration
is
used
to
run
the
diagnostic.
See
the
standard
address
configuration
rules or use a configuration
program
to
assign the correct
floating device addresses.
The same
addresses
and
vectors
which
are
assigned
for
MDM
diagnostic
should then be used for the VMS handler.

The

IDVIS-B,

IDV1S-C,

interrupt
vectors,
dummy vectors
for
diagnostic.

but
the

IAVI1S-B

it may
device

modules

be necessary
handlers
or

not

have

to select
for
MDM

MODULE
1.3

The

type

Mode

SET

OVERVIEW

MODULE

module

1-5

IDENTIFICATION

set

can

Page

can

recognized

identified

(MOD).

This
identification
software
to identify
module.

Every

module

used
in
the
diagnostic
and
function and register
structure

driver
of each

is
the

bit

(octal)

the

software.

code

The identification
function groups:

code

divided

000

037

Digital

Input

Modules

040

0Q77

Digital

Output

Modules

100 to 107
"OR"-ed with
110 to 170

Analogue
Input Controller
connected
to
Analogue
Input Multiplexer

200

207

Analogue

Output

300

377

Special

Modules

the

high-byte

into

the

following

Board

Controller
(five

channel

The identification
codes of the
listed in the following table.

module

An installation protocol
of the
with the test program,
provided

modules present can be
obtained
that the standard address
range,

which

described

chapter

1.2,

family

counter)

used.

described

here

are

MODULE

SET

OVERVIEW

Page

1-6

+-----------! Identif.
!Code
(oct.)
+——----------!

+~-----------!
Module
! Designation
4+————--------!

+——-—-——-—----—---+ - -- - - - -- ------ +
!
!
! Description
!
4+—--------~---------- --- +
!
!

004

!
!

040

042

! IDV1S-A
16

M6029-PQ

IDV1S-B

IDV1S-C

M8005-P0

Bit

Opto

Isolated

Input

Opto

Isolated

Output

Relay

100*

A410-PQ

100*

A410-PA

! IAV1S-—AA

110*

t
{

110*

200

!
!

Channel

!
!

IAVIS-C
16 Ch. Flying

AQ29-PA

!
!

IAV1S-CA
16 Channel

A6007-P0

IAV1IS-B

AQ29-P0O

Channel

A/D

4/12

IAVIS-A

Ch.

A/D

Converter

D/A

1-1:

Module

Identification

the

code.

-PA

versions

and

thus

are

they

Multiplexer
Multiplexer!
Converter

Codes

variations

have

the

same

!
|

the

!
!

NOTE

modules

{
300
M7197-P0
! IDV1S-D
!
!
! Five Channel
Counter Module
+----—-------- +——-----—------- 4—-----—--—------------Table

Expansion

Isolated

Converter

Cap

Output

!
!

M5026-P0

-PO

identifier

!
!
t

!
!

!
!
+

MODULE
1.4

SET

OVERVIEW

COMMON

Page

INSTALLATION

PARAMETERS

All modules described
in this manual
parameters
for both installation and

1.4.1

Module

1-7

have
use.

the

following

common

Format

The module
size is
a
quad-high
module
format
with
a
flush
bulkhead
handle
for
the BA200
series Q-bus
system enclosures.
The module handle
provides
Electro-Magnetic
Conduction
(EMC)
shielding
that complies with FCC regulations.

1.4.2
The

BA200-series
IXV1S

enclosure.

modules
The

System

Enclosure

have

enclosure

installed

has

6-slot

BA200

12-slot

series

Q-bus

backplane
and one or two modular power
supplies.
The backplane
implements
the Q22-bus on AB rows
of
each
slot.
The
CD
interconnect
is implemented
in all 12 slots.
MicroVvAx
systems use
the
DC
rows
of
slots
1
through
3
for
their
high-speed memory interconnects.

1.4.3

Installation

and

Configuration

Rules

The installation and configuration of the
modules
have
to _ be
made according to the standard
rules for BA200 series enclosures
and Q-—bus backplanes.
Installation
instructions
e.g.
can be found in the DEC
manuals
MicroVAX CPU Module User Guide and Microsystems
Handbook.
Detailled
information about the installation of
the
individual
modules
can
be
found
in the particular module description
in
this manual
in the chapter
"Installation".
NOTE

The IxvV1S
When
you
recessed

modules
use
a

handle

are
flash

module,

filler
plate
between
regulation.
The filler
70-24071-01.

flash
handle

you

must

handle
module

install

the
modules
plate
part

modules.
next to a
a

metal

to meet
number

FCC
is

MODULE

SET

1.4.4

Installation

All

OVERVIEW

modules

can

Page
Checkout

tested

1-8

Micro-PDPll

with

the

same

diagnostic

Print Configuration
Table
The printout
can be checked
of this description.

with

Table

1-1

Internal
Logic Test
This test checks
the internal
registers
modules.
This
will also test modules
there are any installed.

program

CZIXV??
(except
the
IDV1S—-D
which has to be tested with the
diagnostic
CZIDV??).
The following program sections
can be used
to
check
for
correct
installation
of
one or several
of the
modules.

Further
test possibilities
diagnostic
listing.

1.4.5

Installation

and

Following
types:

MDM

diagnostics

GGSKMIDA

for

IDV1S-A

GGSKMIDB
GGSKMIDC
GGSKMIDD
GGSKMIAA
GGSKMIAA
GGSKMIAB

for
for
for
for
for
for

IDVLS-B
IDV1LS-C
IDV1S—-D
IAV1IS-A,
ITAV1IS—-C,
IAV1S-B

The
the

are

given

Checkout

can

used

(See

chapter

of
with
1-5

chapter

1-3

the
selected
interrupts
if
and

the

MicroVAX

for

the

individual

groups

and

module

Note)

IAVIS—AA
IAV1S—-CA

diagnostics
are divided
user through operation.

into

several

will

NOTE

The options
in the diagnostic
are
The
Ixv1S
options
are
the
enclosures versions and software
the Ixvll.

named
Ixvll.
BA200
series
compatible
to

lead

MODULE

SET

1.4.6

User

OVERVIEW

Page

1-9

I/0O-Connector

The user 1I/O-connector
is integrated
in the module handle.
Each
module
has
the
same 50-pin D-type
subminiature male connector
(plug).
See figure
1-3 I/O-Connector
Dimensioning.
The
module
connector
has
a
slide
latch
assembly
to
lock
the
cable
connector.

Plug

Assembly

(Pin

Contacts)

66.93
.

52.81
[—

Jderveccesecceccccccs

eeeevneeveneene

eee

7eeererrrerrreorerer?

Figure

1-3:

61.41

I1/0O-Connector

jf
~N

Z
__|

—

Dimensioning

The maximum preferred cable connector depth from the surface
of
the
module
handle
is 40.6 mm.
A cable connector depth greater
than those will abut on the
inside
of
the
system
enclosure,
preventing
skins/doors
from closing.
For example,
the shielded
cable clamp assemblies
from ITT/Cannon DD115386-92
or
oDD19977-4
or equivalent
can be used.
Versions
of the 50-pin
I/O-connector
are
available
for
flat
cable
or
discrete
wire
connection.
For FCC requirements
the
user cable and the connector have
to
be
shielded.
The
wire
shield has to be connected
to the connector Gnd/handle Gnd.
Users which need single wire connections
can
use
the
H3031-A
screw
terminal.
To
connect
this
screw
terminal
to a Ixvl1S
module,
the
adapter
cable
2G-E10OJA-OE
(0.5
m_
tIlength)
Or
equivalent
have
to
be used.
The pin arrangement
on the screw
terminal
1s identical
to those of the internal board
connector,
see Figure 1-3.
In

Figure

1-3

"TI/O-Connector

I/O-connector
plug
receptacle
assembly

assembly is shown
(cable connector)

Arrangement",

the

form handle
front
iS mirror
image.

module

view.

SET

Page

OVERVIEW

1-10

MODULE

——

L(A

V/O-Connector

Slide Latch

Assembly

® 5 @

®5e

@ ~ ©
@ @ ©

® Oe
« ©
@)

(4)
@)

50 Position

D- Connector

1-4:

AABB

30
31
32

JJ
KK
LL

0
mn

39
40

N—__@——
~[ YJ]

Figure

RP
S
r

2423

—~__

12
13
14
15

(Pin Contacts)

I/0-Connector

Module Handle

ar
a

Front View

Arrangement

Internal

Board

for

Plug Assembly

(8)

- &
@) (5)

@?)

Assignments

43
50

UU
VV

pnt

used

Reference
Connector

MODULE

SET

OVERVIEW

1.4.7

Environment

Operating
Relative

Page

(per

DEC

Temperature

Lower
1000

102,

Class

degrees

10%

90%

noncondensing.

Humidity

Airflow

Standard

1-l1l

celsius

Sufficient airflow must be
provided to limit the temperature
rise across the module
to:
<10 degrees
celsius
for inlet
temperature below 55 deg.
celsius
the

feet

Normally,

enclosure,

maximum

temperature

(300

which

fitted

the

modules

altitude

should

with

degree

celsius

above

8000

mounted

fans.

feet

for

(2400

DEC.

every
m).

standard

NOTE

These
are
temperature
lifetime
of

the
design
limits.
Lower
limits will serve to increase
the
the module.

1.5

MAINTENANCE

This

chapter

refers

are

software

compatible.

the

IxVll
is the
standard
Q-bus
module
set
for BA200
series

IxVll-module

set

enclosure
version.
enclosures.
Both

diagnostics.

NOTE
The

testconnectors

IxVll-modules

used

needed

adapter

modules.

for

cable

and
the

install

which

described

are

the

for

Appendix

(see

Appendix

Ixvl1S-modules

2G-E10SA-OL

used _
too,

testconnectors

The

The
IxVl1S
is the
module
families

but

the

have
B)

the

IxVl1S

MODULE

SET

OVERVIEW

1.5.1

Module

Family

Page

Diagnostic

for

LSI

1-12

Processors

The module
set described
is tested
by
the
diagnostic
CZIXV??
"IDV11/IAV11
I/0
Module
Family"
DIAG
(except the Five Channel
Counter Module M7197,
in which case
the
Five
Channel
Counter
DIAG
CZIDV??
has
to be used).
Each module
contains
one LED,
which is on when the module
is being tested.
There are four diagnostic
program sections which may be used for
field tests.
-

Print Configuration Table
With this routine,
one module or
a
set
of
modules
can
be
identified
with the device address,
the module
identification
code and its selected operation mode.
The
standard
address
range should be used on this test.

Internal
Logic Test
This test section performs detailed
accessible
part of the device.

Device

I/0

tests

each

separately

Tests

Some test equipment
is necessary
in this
test
section.
The
"Digital
I/O Test Connector"
for the digital
I/O modules,
the
"Analogue
Input Test Connector"
for the analogue
input modules
or
one
of
the
"Analogue
Output
testconnectors"
for
the
analogue
output modules.
The test connectors
are described
in
Appendix B "Field Test Equipment".
I/O Line Check
Specifically
selectable
tests allow the user to read or
write
the
user
interface
of the chosen device.
User lines can be
set or monitored
for the digital
I/O modules.
This
test
can
be
used
to
calibrate
the analogue
I/O modules.
Calibration
procedures
of
the
analogue
modules
are
described
in
the
individual module descriptions.

The
the

use of the
diagnostic

diagnostic
listing.

and

test

description

are

included

MODULE

SET

OVERVIEW

1.5.2

Module

Diagnostics

The
different
diagnostics:
GGSKMIDA
GGSKMIDB
GGSKMIDC
GGSKMIDD
GGSKMIAA
GGSKMIAA
GGSKMIAB

Page

modules

for
for
for
for
for
for
for

for
can

IDV1S-A
IDV1S-B
IDVI1S-C
IDV1S-D
IAVI1S-A,
IAV1S-C,
IAV1S-B

1-13

MicroVAX-—Processors
be

tested

with

following

MDM

The

are

IAV1S—-AA
IAVIS-CA

The diagnostic
programs
are
divided into six groups:

equally

structured.

the Configuration
Procedure
that verifies
that the addressed
device
for the selected program

the

correct

the Verify Mode Functional
Tests
which
are
testing
the
module-functionality
manual
intervention of the operator

without

the Verify
which
is
together

Mode Exerciser
using
all
verify

module

mode

tests

functional

tests

the Service Mode Functional
Tests
which are testing the modules
completely and require
connect
test equipment,
as described
in Appendix B
the
Service
Mode
Exerciser
which
simulates
the
intense

normal
the

system

Service

which allow
dialog mode

conditions

Mode

the

Utilities

operator

use

the

test

module

functions

NOTE

To run MDM
diagnostic
in
onto
configuration,
other
addresses
and vectors have to be assigned
as used in this manual,
see chapter 1.2.

under

MODULE

SET

OVERVIEW

1.5.3

Maintenance

Module
replacement
recommended
spare
"Shipping List").

Page

1-14

Philosophy

is the
parts

suggested maintenance
technique.
The
are the complete boards
(see Appendix
NOTE

Before
starting any
system
checkout
that
may
affect
field
Signals
produced
by
the
I/0
modules,
for example
running
the
diagnostics,
contact
the customer and take appropriate
safety
precautions.

CHAPTER
IDV1IS-A

2.1

GENERAL

BIT

OPTO

ISOLATED

INPUT

(M5026-P0)

DESCRIPTION

The IDV1S-A is an isolated digital
input
module
(M5026-P0)
for
the
Q-bus.
It
accepts
up
to
16
single optically
isolated
inputs used for
monitoring
voltages
where
noise
immunity
or common mode
rejection
is important.
The 16 bit
data are read by programs
and transferred to
the
processor
or memory.
The input line
and
generates
Signal)
and/or

bit 15 is selectable
for interrupt by program
an
interrupt
at the leading edge
(ON-going
at the trailing edge
(OFF-going
signal).

The standard
input range is 24 to 42 Vdc.
In
this
range,
the
input
switching delay can be changed by a programmable
contact bounce eliminator
to three different values.
In addition,
a programmable
low level
input
range
for
speed,
low
power
5
Vdc signals and usable
for TTL or
inputs
is selectable.
|

IDV1S-A

——-

FEATURES

16 single optically isolated
inputs
interrupt
capability on input line bit 15
interrupt
generating
signal
edge is programmable
programmable
contact bounce eliminator
standard input range from 24 to 42 Vdc
programmable
low level
range for 5 Vde signals
module
identification
code
readable by program

low
MOS

IDVIS-A

BIT

OPTO

ISOLATED

INPUT

(M5026-—P0)

(Bit

Page

only)

Interrupt
Circuit
x

INTERR.
~
|

Lud

(1 of

—

16)

C1
oe

(-)

W—

[

WW,
O-

Figure

2-1:

]

JT ~~

Contact

Bounce

Eliminator

IN2

(+)

IDV1S-A

Simple

Block

Diagram

(M5026-P0)

DATA
READ

N
—

co
\

2-2

IDVIS-A

2.2

BIT

OPTO

ISOLATED

INPUT

Page

(M5026-P0)

SPECIFICATION

Module

Designation

M5026-—-P0

Identification

004
octal
(identification
code
when
reading
the MOD
register)

Module

Quad high Module
enclosures)

Power
Bus

Requirements

(for

BA200

5,0 Vdc at 720mA +52
1

Load

INPUT

No.

Size

DC-Load;

AC-Load

CIRCUITS

Digital

Inputs

Standard

Input

Range

Contact

Bounce

two

wire

optocoupler

Vde

2,6

inputs
5,2mA;

ON voltage
11V minimum;
OFF voltage
4,2V maximun;
Max.
input voltage
42V
Default

debounce

delay

millisec

+30%;
programmable
to
+60%
or 10 msec +20%

Low

Min ON-voltage
is 4,2 Vdc at
0,46mA;
max.
input frequency
is 50Hz on 50% ‘duty cycle;
Max.
input voltage
42V

Input

Level

Range

(Software

selectable)

Hysteresis
Isolation

Approx.
Voltage

Interchannel

BUS

Isolation

microsec

for

both

input

Inputs to Computer
or peak ac

Gnd

1000

ranges

250

Vdc

0,55V

500

Eliminator
(Software
selectable)

peak

Vdc

INTERFACE

Addressing

Interrupt

Vector

Switch
to 770

Priority

Level

BR4

Switch selectable
over the 4K I/0
address
range;
occupies
a 4 word
address with one word unused
selectable
octal

(jumper

from

selectable

000

level

2-3

IDVIS—-A

2.3

BIT

OPTO

ISOLATED

INPUT

(M5026-P0)

Page

2-4

INSTALLATION

2.3.1

Site

Considerations

The IDVIS-A has two bus interface
connectors
that
plug
into
a
Q-bus
slot.
These connectors have signals which are defined
in
the Q-bus
specification.
The interrupt priority of
the
module
is
determined
by
the
position on the Bus
(position dependent
configuration).
The
closer
a
device
is
located
to
the
processor,
the higher
its priority.

2.3.2

Interconnections

Interfacing
the IDV1S-A to the user’s device
is done via the
50
pin
D-type male connector.
A 50 conductor
flat cable or a user
made twisted pair cable may be used for field
connection.
The
pin
assignment
and
the
signal
description
can
be found in
chapter
2.5.
General

informations

physical

2.3.3

requirements

Initial

Selecting

the

about

the

Device

Address

are

given

user

Chapter

I/0O-connector

1.4.6.

and

the

Operation
IDV1S-A

The
device
address
is
the
I/O
address
assigned
to
the
MOD-register.
The
device
address
is
selected via a 10-pole
Switch
(Figure
2-4).
The switches allow the device
to
be
set
within
a
range
of 160000 octal to 177770 octal.
The standard
address
range for this
module
is
from
171400
to
171770
in
increments
of 10 octal
(Figure 2-2).

}14

111471

12/1

§ =

OFF

2-2:

918

615

1totetastt4+dx

Si0

Figure

rogica) I. OFF
ogical

OFF
S8

Selecting

IDV1S-A

342

Factory

}

Device

configured

within Standard
jddress Range

(171400 to 171770)

Address

IDVIS-A

Selecting

BIT

OPTO

the

ISOLATED

IDV1S-A

INPUT

Interrupt

(M5026-P0)

Vector

interrupt vector.
The
a 6-pole
switch
(Figure
in
increments
of
10

For

standard

vectors,

the

111

Should
have
(Figure 2-2).
identical
for

Logical
Logical

switches

9 = OFF

X¥

Factory

configured

within Standard
Vector Range

(400 to 770)

Figure

2-3:

(Figure

the
same
position as the address
switches
1
This
means
that
the
address
and
vector
address bits 3 to 8.

1 = ON

Selecting

IDV1S-A

2-5

Address

The IDV1S-A is capable
of generating one
interrupt
vector address
can be set via
2-4) within the range of 0 to 770
octal
octal.
vector

Page

Interrupt

Vector

2-3)

to 6
are

IDV1IS-A

BIT

OPTO

Hh @ Qe

ISOLATED

INPUT

(M5026-P0)

Page

2-6

P%ae

TOwis

Meo.

E115

M5026

- PO
<<

Maint.

fg ft

1/0

me!

Connector

oer

Device

Be
=

FO
Wu

}tqvaes

et]

v4
|

Address

ens

Switch

Cer

{

|OIEB
ie

PAB

iB—

Vector Switch

LED

O mann

fee

|
Figure

Plastic

Jr
2-4:

IDVIS-A

Physical

Layout

M5026-P0

Filler

Panel

IDV1IS-A

Selecting

BIT

the

OPTO

ISOLATED

Interrupt

The standard
interrupt
request
level,
BIRQ5

BR5

BR6.

INPUT

Request

(M5026-P0)

Page

2-7

Level

request level
or BIRQ6,
can

is
be

4
(BIRQ4).
selected via

A
the

higher
jumpers

Whenever
the BIRQ4 on the module
is changed to a
higher
level,
no
other
modules,
which have a lower
request level,
should be
installed on the bus closer
to
the
processor.
The
interrupt
priority
of
the
IDVIS-A
is
position
dependent and does not
monitor higher
request levels.

2.4

OPERATION

2.4.1

AND

PROGRAMMING

General

This chapter presents
a
detailed
registers
(see figure 2-5).
Four
assigned to the register
set.
171XxX0

Mode

171XxX6

unused

171XX2
171Xx4

description
consecutive

Input Data Buffer
Control
Status Register

They can be read
their address.

loaded

uSing

any

of
bus

the
IDV1S-A
addresses
are

(MOD)

(DAT)
(CSR)
~

instruction

which

refers

signal
issued
by
one
of

by
the

Initialization

The mnemonic
INIT
the
processor.
Following:
~
-—
-

refers to the initialization
Initialization
is
caused

issuing a programmed RESET instruction
depressing
the start switch on the processor
console
the occurrence
of a power-up or power-down
sequence

The

MOD

and

CSR

registers

are

then

initialized.

IDV1IS-A

Operation

BIT

OPTO

ISOLATED

INPUT

(M5026-P0)

Page

2-8

Modes

All variable
operation modes of the IDVIS-A,
e.g.
the low level
input
range,
contact
debouncing
and the interrupt
generating
Signal edge,
are program selectable.
They are described
in
the
CSR-bit description and in chapter
2.5.

2.4.2

Mode

(MOD)

The MOD register
is generally used to identify the
module
with
its
identification
code and to select operation modes.
If this
register
is not
used
by
the
user
program,
the
module
has
standard parameters
as shown in the following bit description.

$——
!

Bit!

Name

= +

Description

}~---4—--~-~-~-~~- $—-—------~-- +--+

15!
to !

68 !

;
!
!

!
!

rt
!
!
!
!
!
f
!
!

only)

!
!
!

!
!
|

RTl

RTO
f
!(read/write)!
!
!
!
!
!
!
!
!
!
!
!
{

6 !

!
!

LLS
!
i(read/write)!
t
!
!

1s!

!
!

IDENT

!(read
{

IDENT
to

LED

!
!

Identification Bits 7-0
The module
is identified

bits.
004

The

octal

M5026
(in

has

high

the

byte).

code

!
!

Low Level
Input Range Select
Setting this bit enables
the 16
input lines to the 5 volt input

range. Otherwise the
range of 24 to 42Vdce

standard input!
is selected. !

!
!
!

Input

for

con-

purposes.

Response

Time,

the

tact bounce eliminator
circuits of !
the 16 input lines.
!
bin.
Q not selectable
!
1 response
time 500 microsec
!
2 response time
5 millisec
!
3 response
time
10 millisec
!
After
INIT the bit RT1
(5 millisec)!
is selected.
!
!

LED

indication

for

test

$- -—
Table

these

+
2-1:

IDV1IS-A

MOD

Bit

Assignments

IDV1S-A
MOD

BIT

171XX0

OPTO

Mode

12
11
IDENT

ISOLATED

+10

98197

R/W

=
=
=

All
and

bits
read

R/WZ

Read Only
Write Only
Read/Write

R
W
R/W

(M5026-P0)

read/write

2-5:

IDV1S-A

2.4.3

Input

Data

Mode

Buffer

14]

Figure

13 | 12

2-6:

Input

IDAT
{ 11

| 12

Data

IDV1S-A

R/W

zero

GP
R/T
R/W

with

"1"

are unused
zero

(DAT)

The input data buffer
is
a
16-bit
monitors
the data of the input lines
171XX2

2-9

| | 6

not described
or written
as

Figure

DAT

Page

rLe{s|@l3i[2|i|e

NOTE:

INPUT

read
only
to 15.

Buffer

| 8

|
| 7

READ

ONLY

Input

| 6

Data

IDAT
| 3

Buffer

| 2

Pi!

that

IDV1S-A

2.4.4

BIT

OPTO

Control

and

ISOLATED

Status

INPUT

(M5026-P0)

14
Line

(EI)
15

$e
'Bit!
Name
!
Description
!
IR15
!(read/write
!
to zero)
!
!

114
!

!
EI
!
!(read/write)!

Enable

113
!

!
ELE 15
!
(read/write)!

Enable
the
from input

Leading
line 15

f12

Enable

Trailing

{

1
!
i

in
is

the
also

+
!

ee $——-—-—--------- --- -- - - -- -- - - - -- - = ---- ---+ !

'15
!
!
!
!

2-10

(CSR)

The input line 15 (IN15)
enabled
using
bit
CSR-register
to
generate
an
interrupt.
monitored
in the input data buffer bit 15.

Page

|
!
!
!
!

Interrupt
request from the input line 15.!
IR15 is set on the edge of the input
:
signal
according to the state of the bits!
ELE15 and ETE15.
IR15 produces an inter!
rupt on vector XX0 when EI is set.
!

Interrupt

for

IR15.

{

ETE

!(read/write)!

!
TST
'(write
!

!
I

IR
!
only)!
!

the

signal)

from

Edge
(ON-going
to set IR1L5.

input

Edge

line

signal)!

(OFF-going
to

set

IR15.

2-2:

CSR

171XX4

IR
15

|EI

R/WZ

CSR
-

Control

Bit

Status

[ELE | ETE
15 | 15

TST
IR

R/W

Interrupt

Test the Interrupt Request Bit IR15.
!
Writing the TST IR sets the Bit IR15 to !
test the internal
Interrupt Function.

+—-—-----~--—-------- - - - Table

Assignment
Register

Generation

Interrupt |

NOTE:

Figure

Read Only

W
=
Write Only
R/W
=
Read/Write
R/WZ =
read/write
to zero
All bits not described are
read or written as zero.
2-7:

IDV1IS-A

Control

Generation

with a
unused

Status

"1"
and

Interrupt

IDV1S-A
2.5

BIT

OPTO

FUNCTIONAL

2.5.1

Theory

ISOLATED

INPUT

(M5026-P0)

Page

2-11

DESCRIPTION

Operation

Figure 2-1 shows a simple block diagram
of
the
board
is
addressed via the bus address
lines.
to select
its
device
address
and
interrupt
according to the rules in chapter 2.3.
The 16 digital
input data
are
They can be read by program via

IDVI1S-A.
The
It has switches
vector
address

entered
through
connector
the input data buffer
(DAT).

Jl.

Each input enters
via
an
optical
isolator.
Following
each
isolator
iS
a
contact
bounce eliminator
circuit
to provide a
high noise
immunity.

2.5.2

Mode

Standard

Input

Operation
Range

The standard
input range for
Vdc.
This
range is selected
Low

Level

Input

all 16 digital
after INIT.

inputs

Range

This range can be selected by program with the mode register bit
LLS
(Bit
3).
It is possible
to use low voltage and low power
Signal
sources,
e.g.
TTL and MOS at this input mode.
However,
the signals may only have a very low frequency.
See chapter
2.2
"Specification".
Contact

Bounce

Eliminator

The contact bounce
eliminator
circuit takes an input signal
a
bouncing
contact
and
generates a clean digital
signal
clock periods after the input
is
stabilized.
The
clock
operation
is
derived
from a programmable
R-C oscillator.
R-C oscillator
can be programmed via the MOD-register
bits

and
RT1l
millisec.

for
the
After

bounce
delays
500 microsecs,
5 millisecs
INIT,
the
5 msec
delay
is selected.

and

from
four
for
The
RTO

IDV1S-A

BIT

Interrupt

OPTO

Input

ISOLATED

Line

INPUT

(M5026-P0)

enable
enable
IR15.

the
the
only

occurs

2.5.3

Input

Signals

The IDV1IS-A has a
A flat cable or a
field connection.

bits
ina

leading edge or ON-going
signal
to set IR15.
trailing edge
or
OFF-going
signal
to
set

An interrupt
set.

User

2-12

The input line 15 can be programmed with the CSR
ELE 15
and
ETE 15,
such
that
an input change
flip-flop
(CSR bit IR15)
as follows:
ELE15
ETE15

Page

via

bit

IR15

when

50-pin D-type male connector
user made twisted pair cable

(CSR

bit

for user
could be

14)

inputs.
used for

For a logical
"1" input,
the minus voltage has to be supplied
the
INX/1l
input
pin
and
+ voltage
at the INX/2
input pin
drive the light emitting diode of the optocoupler.

at
to

For the correct electrical
"Specification".

2.2

signal

requirements,

see

chapter

NOTE

The +5V output on Pin 2 and 38
used for DIGITAL manufacturing

are
normally
purposes.

IDV1S-A

BIT

OPTO

ISOLATED

+——-—------- 4———------------!
I/O
!
!Connector!
!
Pin
!
Signal Name
!

INPUT

(M5026-P0)

Page

+—-—------- 4+—-—--------------! = =I/0
!
!Connector!
!
Pin
! Signal Name
|

+
!
!
!
!

+------—

4+————------------ +——-———---- 4+——----—--—--—~—------ !

!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37

!
!INO/2
(+
!IN1/2
!IN2/2
fIN3/2
LIN4/2
!IN5/2
!IN6/2
LIN7/2
!IN8/2
!IN9/2
!IN10/2
!IN11/2
!IN12/2
!IN13/2
!IN14/2
!IN15/2(+
!

!
!

43
45

+—-—---———
Table

2-3:

Bit

0) !

Bit

15)!

44
46

+——-—------------- +------Connector

{

!
i
!
!
!
!
!
!
!
!
!
!
!
!

!
t

IDV1S-A

(Maint.)

!INO/1
(- Bit 0) !
!IN1/1
!
fIN2/1
!IN3/1
!
lIN4/1
!
!INS/1
!
!IN6/1
!
!IN7/1
!
!IN8/1
!
fIN9/1
!
{IN10/1
!
!INI1/1
!
!IN12/1
!
!IN13/1
!
!IN1I4/1
!
fINI5/1
(-Bit 15)!
!
!
!+5Vde Out(Manuf.!

{
!

'+5V

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

!'Gnd

only)

t
!

!
!

4+—-—---------—----- +
Assignment

(M5026-P0)

2-13

IDVIS-A

2.5.4

BIT

OPTO

Interfacing

ISOLATED

the

INPUT

Standard
~~
~

==
to

circuits
IDV11-A

"T"=high

+24

user

Circuits
For

Page

IDV1S-A

In the following,
some typical
IDVIS-A inputs are shown:
User

(M5026-P0)

Input

Range

INX/1
_

(-)

+24 to 42Vdc

Input

ee.

|
INX/2

=]ow

>
=
42Vdc

"4"=high

2-8:

Low

Level

“—

V
IDVIS-A

Input
J

7406

+5Vde

Figure

INX/2

———_——_>

For

INX/1

+24

Application

Range

INKL
Nase

Circuits

the

INX/1

"4"

drive

Circuits

“a
LAS
|

NX/e

42Vdc

which

(M5026-P0)

CHAPTER
IDV1S-B

3.1

GENERAL

16-BIT

OPTO

ISOLATED

OUTPUT

(M6029-P0)

DESCRIPTION

The IDV1S-B
is an isolated digital
output module
(M6029-P0)
for
the Q-bus.
It provides
16 single optically isolated dc outputs.
The
latched
field
outputs
are
two-wire
open-collector/
open-emitter
switches
used for controlling
relays,
indicators,
semiconductor

process
The
and

must

switches

etc.,

maintained.

where

isolation

from

16-bit output data are written by program in
the output data register
can be read back.

IDV1S-B

FEATURES

- 16 single optically isolated outputs
—- two wire connection per output
~-~ capable of driving up to max.
42 Vde at 130mA
—- read/write
output data register
- module
identification
code readable by program

the

word

controlled

or _

byte

IDV1LS-B

16-BIT

OPTO

ISOLATED

OUTPUT

(M6029-P0

)

Page

USER-CONNECTOR

Ld
(1

DATA

_
—_—

16)

(+)

, | |

“VF |
_ |

OUT2

OT)

3-1:

READ

WRITE

OUT1

Figure

3-2

WV
IDV1IS-B

Simple

Block

Diagram

(M6029-P0)

IDV1S-B
3.2

16-BIT

OPTO

ISOLATED

OUTPUT

(M6029-P0)

Page

SPECIFICATION

Module

Designation

M6029-P0

Identification

040 octal
code when

(software
identification
reading the MOD register)

Module

Quad

Module

(for

440mA

+5%

Size

Power
Bus

9,0
Load

high
Vde

DC-load;

1,4

BA200

CIRCUITS

No.

Outputs

16 two-wire darlington
coupler dc outputs

Output

Voltage

Max.

Output

Current*

(Ptot

150

Saturation

Voltage

Vce
(sat)
= Typical
Ic 50mA (max.
1 V)

Switching

Speeds

ON-Time
OFF-Time

Isolation

Voltage

Interchannel
Logic

BUS

"1"

Isolation

Output

Derate
2
above 25

opto-

Vdc

130mA

(at

enclosures)

AC-load

OUTPUT

3-3

Vce

typ.
typ.

5V,

120

6
=

milliwatts)
0,85V

microsecs
microsecs
100

ohm)

Output to Computer Gnd
1000 Vdc or peak AC
250

Vde

Transistor

peak
ON

AC
(conducting)

mW/ degrees
centrigrade
degrees
centigrade
ambient

INTERFACE

Addressing

Switch selectable
over the 4K I/0
address
range,
occupies a four
word address with two words unused

IDV1LS-B

3.3

The

OPTO

ISOLATED

OUTPUT

(M6029-P0)

Page

3-4

INSTALLATION

3.3.1

Q-bus

16-BIT

Site

Consideration

IDV1S-B

has

slot.

two

bus

These

interface

connectors

have

connectors
signals

that

defined

specification.
The module
can be plugged
into
Q-bus
backplane
according
to
the
rules
of
configuration.

3.3.2

any
the

plug
by

the

slot
Q-bus

into

Q-bus

of
a
system

Interconnection

Interfacing
the IDV1S-B to the user’s device
is
done
via_
the
50-pin
D-type
male
connector.
A 50-conductor
flat cable or a
user made twisted pair cable may be used for
field
connection.
The
pin
assignmnent
and
the
signal description are shown in
chapter
3.5.
General
information
about
the
user
1I/0O-connector
and
the
physical
requirements
are given in chapter
1.4.6.

3.3.3

Initial

Selecting

the

The
device
MOD-register.
switch

(see

Operation
IDV1S-B
address
The

figure

Device

Address

is
the
I/O
address
assigned
device
address
is
selected via

3-3).

The

switches

allow

the

device

to
the
10-pole
address

to
be
set within a range of 160000 octal to 177770 octal.
The
standard address
range for this module
is from 171000
to
171370
octal
in increments
of 10 octal.

Logical

Figure

OFF
ON

3-2:

OFF|

6ON.

«ON.

«OFF.

S10

Selecting

Factory

configured

within Standard
Address Range
(171000 to 171370)

IDV1S-B

Device

Address

IDV1S-B

| ®

IOVS
-B

ISOLATED

OPTO

16-BIT

OUTPUT

Page

(M6029-P0 )

3-5

ef}

1 D29
-PC,

M6029 Maint.
LED
0

1/0
Connector

A. BI

1
1

“we

==f f IEIE
a,
S

EUUI mM I

rfified “
Device

Address

Switch

o
qe
TT.

Plastic

Figure

3-3:

IDV1S-B

Physical

Layout

Filler

M6029-P0

Panel

IDV1S-B
3.4
3.4.1

16-BIT

OPERATION

OPTO

ISOLATED

AND

PROGRAMMING

OUTPUT

(M6029-P0)

Page

3-6

General

This chapter presents
a
detailed
resgisters
(see figure
3-4).
Four
asSigned
to the register
set.
171XxX0
L71XX2
171XxX4
171XX6
They can be read
their address.

description
consecutive

Mode Register
Output Data Register
unused
unused
or

loaded

uSing

any

of
bus

the
IDVI1S-B
addresses
are

(MOD)
(DAT)

instruction

that

refers

signal
issued
by
one
of

by
the

Initialization

The mnemonic
INIT
the
processor.
following:
—~

refers to the initialization
Initialization
is
caused

issuing a programmed RESET instruction
depressing
the start switch on the processor
console
the occurrence
of a power-up or power-down
sequence

The MOD and the DAT
output lines are set

then
initialized.
(transistor OFF).

All

IDV1S-B

16-BIT

3.4.2
The
its

Mode

OPTO

ISOLATED

OUTPUT

(M6029-P0)

Page

(MOD)

MOD register
is generally used to identify the
module
identification
code and for maintenance
purposes.

4— — -—-—'Bit!
15
!to
! 8
!
'

LED

{

fi!

0 !

Identification Bits 7-0.
!
The module
is identified by these !
bits.
The M6029 has the code
!
040 octal
(in high byte).
!

LED

indication

for

test

Bits

0-1

purposes. !

+
!

!
!
!
!
!

!(read/write)!

{

Description

+-----------------------------------

— — — - —
Name

!
IDENT 7
!
to
!
IDENT 0
!(read only)

Response

Switching

Time

time

the

output

!
!(read only)
! circuits
(diagnostic
feature).
{
!
!
! RTO is always
set since the ON or !
!
!
! OFF time could be up to 500 micro-!
!
!
! sec.
RT1l is always
zero.
!
+—-—-—-—-—-——~----— -- -- - - - -- -+
Table

3-1:

MOD

171XX0

71/645

IDV1S-B

MOD-Register

—-

Mode

414

+10

IDENT

|4]3]2

09
{1

;07

R
W

R/W
All
and

Figure

3-4:

=
=

Bit

O05

LED

READ ONLY

NOTE:

Assignments

O02

R/W

=
Read/Write
bits
not described
are
read
or write
as zero

Mode

O01
1

00
RT

| 0
R

Read Only
Write Only

IDV1S-B

3-7

unused

with

IDV1IS-B

3.4.3

16-BIT

Output

OPTO

Data

ISOLATED

The output data register
can
be
written by word
the contents
of the
DAT
Circuits.
DAT

171XX2

ODAT
{14 | 13 f12]41

OUTPUT

3-5:

is a 16-bit
read/write
or byte.
The read back
and
not
the
status

Output

Data

[1019

| 8

IDV1S-—-B

Page

|} 7]6]5

ODAT
}413

READ/WRITE
Output

3-8

(DAT)

READ/WRITE
Figure

(M6029-P0)

Data

IDV1S-B

3.5

3.5.1

16-BIT

OPTO

FUNCTIONAL

Theory

Figure
3-1
addressed
DIL switch
in chapter

ISOLATED

OUTPUT

(M6029-P0)

Page

3-9

DESCRIPTION

Operation

shows a simple block diagram
via the Q-bus address
lines.
to select its device address
3.3.

of the IDVI1S-B.
It
is
The board has a 10-pole
according to
the
rules

The output data are loaded in the 16-bit output
register
(DAT).
The
DAT
outputs
drive
the
darlington
optocouplers.
The
collector
and emitter of the darlington
switches
goes
to
the
field
connector
Jl.
Each of these switches
is protected
from
inductive
spikes by a clamp diode across
its output.
The
new

output data
data to the

3.5.2

User

remain unchanged
DAT-register.

Output

unless

the

processor

Signals

The IDV1S-B has a 50-pin D-type male connector
Signals
to
the user.
A flat cable or a user
cable may be used for field connection.
A logical
"1"
(conducting).

output

For the correct
"Specification".

outputs

means

electrical

the

darlington

signal

for
made

output

requirements,

switch
see

NOTE

The +5V output on
Pin
38
is
used for DIGITAL manufacturing

the
output
twisted pair

normally
purposes.

chapter

ON
3.2

OUT10/1
OUT11/1
0oUT12/1
OUT13/1
OUT14/1
OUT15/1(+

Bit

15)

eommw

Oem

g§=—8

@€-

O-

eum

ecm

emnw

9-8

Bit

eo=—nw
O-w
@-e

OW
OF

o-—w

e-mw

oun

ome
+

3-2:

IDV1S-B

Connector

only)

(Manuf.

O-7%

Out

O-2

145Vdc
Gnd

ORF

te
me
me
meme

Table

@-8

6-5

|
l
l
|
|
|
|
{
|
|
i
|
|
|

OTP

ome

OUTO/1
OUTL/1
OUT2/1
OUT3/1
oUT4 /1
OUTS /1
OUT6/1
OUT7/1
OUTS /1
OUT9/1

OQ-~—=

he
hUcemw
lem
lem
lO
Ue
UOT
OR
OF
OW
OT
OT
OT

15)

6 F

OUT15/2(-Bit

Name

O€——

'
!

O-—=
@e-ww

Signal

Connector.!

Bit

3-10

|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|

hl OF

ome
ome
me
Ome
ome
ome
ome
ome
Ome
me
Ome
ome
ome
ome
ome
me

OUT10/2
ouT11/2
OUT12/2
0UT13/2
ouT14/2

(-—

ome

OUT0/2
OUT1/2
OUT2/2
OUT3 /2
OUT4 /2
OUTS /2
OUT6/2
OUT7/2
OUT8 /2
OUTI9/2

Page

(M6029-P0)

I/O

het

ome

'Connector.

@o-e

ome

I/0

OUTPUT

ome

ISOLATED

OTF

+————-—
-— -—--— —

OPTO

16-BIT

fone

IDV1S-B

Assignment

M6029-P0

IDV1IS-B

16-BIT

OPTO

ISOLATED

3.5.3

Interfacing

In the
driven

following,
some
from the IDV1S-B

IDV11-B

Output

(M6029-P0)

typical
outputs,

user
circuits,
are
shown.

Circuit
/

User
=>

Input

which

Circuits

>—_—_-—-——_———

to +42Vd

(+)

~
“

OUT L

Page

Relay

OUTX/2

OUTX/ 1

Soe

OUTX/2

UTA

42Vdc

Relay

{

88
"T"=Low

OUTX/2.

OUTX/1

FeO

"4"=High

OUTX/2.

Figure

3-6:

IDV1S-B

3-11

IDVI1S-B

OUTX/1

the

OUTPUT

Application

Circuits

M6029-P0

can

CHAPTER
IDV1S-C

4,1

GENERAL

16-BIT

RELAY

4
OUTPUT

(M8005-P0)

DESCRIPTION

The IDV1S-C is a relay output module
(M8005-P0)
for
the
Q-bus.
It
provides
16
latched
reed contact outputs.
The outputs are
two-wire normally open contacts,
used for controlling
solenoids,
relays,

process
The
and

—~
—-

etc.,

maintained.

where

isolation

from

16-bit output data are written by program in
the output data register
can be read back.

IDV1S-C

——-

indicators,

must

the

word

FEATURES:

16 normally open reed contact outputs
two-wire
connection per output
capable of driving up to 42 volt dec (or peak ac)
Pmax.
30W/42VA
contact protection
read/write
output data register
module
identification
code readable by program

1A;

controlled

byte

IDV1S-C
4,2

16-BIT

RELAY

Page

(M8005-P0)

Designation

Identification

Module

M8005-P0
042

octal

Quad

high

when

Size

9,0

Power
Load

OUTPUT

CHARACTERISTICS

No.

Outputs

(identification

reading

Vde

+5%

(for

BA200

760mA

2,1

AC-Load

two-wire

reed

code

MOD

Module

DC-Load;

the

contact

enclosures)

outputs

Contact

Form

SPST normally open
Contact with contact

protection

Contact

Resistance

Typ.

the

output

Switching

Voltage

ac)

maximum

Switching

Current

0,2
volt

ohm
de

across
(or

maximum;

expectancy
30W

(dc)

Response

Time

Typ.

millisec

>100

000

Isolation

Voltage

Interchannel

Isolation

42VA

000

Vde

Switching

Rate

400

maximum

Logic

Output

Contact

closed

BUS

"1"

operations

peak

pins

0,2A,

life

(ac)

Output to computer
Or peak ac
250

above

derated.

Wattage

Expectancy

peak
Note:

Maximum

Life

4-3

SPECIFICATION

Module

Bus

OUTPUT

Gnd

0,2A/12V

1000

Vdc

INTERFACE

Addressing

Switch
selectable
over
4K
4 word
addresses
of which
words
are unused

I/O
two

area,

IDV1S-C
4.3

16-BIT

RELAY

OUTPUT

(M8005-P0)

Page

4-4

INSTALLATION

4.3.1

The

Q-bus

Site

IDV1S-C

Consideration

slot.

has

two

bus

These

interface

connectors

have

connectors

that

signals

defined

specification.
The module
can be plugged into
Q-bus
backplane
according
to
the
rules
of
configuration.

4.3.2

plug

any
the

the

slot
Q-bus

into

Q-bus

of
a
system

Interconnection

Interfacing
the IDV1S-C to the users’s device
is
done
via
the
50-pin
D-type
male
connector.
A 50-conductor
flat cable or a
user made twisted pair cable may be used for
field
connection.
The
pin
assignment
and
the
signal
description are shown in
chapter
4.5.
General

information

physical

4.3.3

requirements

Initial

Selecting

about

are

the

given

user

1I1/0-connector

chapter

1.4.6.

and

the

Operation

the

IDV1S-C

Device

Address

The
device
address
is
the
I/O
address
assigned
to”
the
MOD-register.
The
device
address
is
selected via a 10-pole
Switch
(see figure
4-3).
The switches allow the device
address
to
be
set within a range of 160000 octal to 177770 octal.
The
standard address
range for this module
is from 171000
to
171370
octal
in increments
of 10 octal
(See Figure
4-2).

15114

124711

615

rt.

1+} ofo!t!o]yxtt}xXx | x

OFF

Si0

Logical

1 = OFF

Logical # =

Figure

4-2:

Selecting

IDV1S-C

$2.

Device

1 = 0

Factory configured
within Standard

Address Range

(171000 to 171370)

S1
Address

IDV1S-C

16-BIT

RELAY

OUTPUT

(M8005-P0)

Page

4-5

it Sa.
}OvisS
-C¢

IM BOTS
- Pg

M8005

-PO

Maint.

Device

Address

Switch

cle

{

PUUYY

OFF

1/0
Connector

RTRLEREE
ER A2 dE Hd

LED

samt

be)
EET
FREER

Plastic

Filler

Panel

REL AY
eee

Figure

4-3:

IDV1S-C

Physical

Layout

M8005-P0

IDV1S—-C

4.4

4.4.1

16-BIT

OPERATION

RELAY

AND

OUTPUT

(M8005-P0)

Page

4~—6

PROGRAMMING

General

This
chapter
presents
a
detailed
description
registers
(see
figures
4-4
to
4-6).
Four
addresses
are assigned to the register
set.
171XxX0

Mode

171XxX4
171XxX6

unused
unused

171XX2

They can be read
their address.

Output

Data

loaded

using

any

of
the
IDV1S-C
consecutive
bus

(MOD)

(DAT)

instruction

that

refers’

signal
issued
by
one
of

by
the

Initialization

The mnemonic
INIT
the
processor.
following:
~
~

refers to the initialization
Initialization
1s
caused

issuing a programmed RESET instruction
depressing
the start switch on the processor
console
the occurrence
of a power-up or power-down
sequence

The MOD and the DAT
output lines are set

then
initialized.
(contact open).

All

IDV1IS-C

16-BIT

4.4.2
The
its

Mode

RELAY

OUTPUT

(M8005-P0)

Page

(MOD)

MOD register
is generally used to identify the
module
identification
code and for maintenance
purposes.

fm
tBit!

Name

{---—+—-—-—----------- ta

'15 !
IDENT 7
!to !
to
! 8 !
IDENT 0
!
!(read only)
!

!
!
!
!

1
!

!
LED
!
!(read/write)!
!

Description

nnn nn nnn nn

Table

4-1:

MOD

171XX0

LED

indication

1
0
only)

!
!
!
!
!
!

for

test

purposes. !

—-

Mode

12
+11
IDENT

°10

08/107

O06
LED

3it2}i fo

R/W
All
and

4-4:

=
=

R/W

Bit

Assignments

O02

Read Only
Write Only

=
Read/Write
bits
not described
are
read
or write
as zero

IDV1S-C

!
t

MOD-Register

R
W

Response Time Bits 0,1
!
Switching time of the 16 output
!
circuits
(diagnostic
feature).
!
RT1 is always
set since the ON or !
OFF switching time could be up to !
5 msec.
RTO is always
zero.
!
+

READ ONLY

Figure

rrr

IDV1S-C

7ie6 {sts

NOTE:

+
!

Identification Bits 7-0.
!
The module
is identified by these !
bits.
The M8005 has the code
!
042 octal
(in high byte).
!

fi!
RT
1 QQ!
RT
!(read
!
{
!
!
!
!
!
4—-~— -—
—

4-7

Mode

unused

1_ | 0
R

with

IDV1S-C

4.4.3

16-BIT

RELAY

Output

Data

OUTPUT

(M8005-P0)

Page

(DAT)

The output data register
can
be
written by word
the contents of the
DAT
Circuits.

is a 16-bit
read/write
or byte.
The read back
and
not
the
status

DAT

Data

171XX2

| 14

| 13]

Output

ODAT
| 11]

1079

READ/WRITE

Figure

4-5:

IDV1S-C

ODAT
4{3

READ/WRITE

Output

4-8

Data

IDV1S-C
4.5

4.5.1

16-BIT

RELAY

FUNCTIONAL

OUTPUT

(M8005-P0)

Page

4-9

DESCRIPTION

Theory

Operation

Figure
4-1 shows a simple block diagram of the IDVI1S-C.
It
is
addressed
via
the
LSI-11
bus address
lines.
The board has a
10-pole DIL switch to select its device address according to the
rules in chapter
4.3.
The

output

data

The
new

output data
data to the

4.5.2

User

are

loaded

the

16-bit

output

(DAT).

The DAT outputs drive the relay coil.
Both sides of the SPST-NO
read contacts
go to the
field
connector
Jl.
Each
of
these
contacts
is
protected
from
inductive
loads
by a RC-network
across
its output.

Output

The IDV1S-C
Signals
to
cable could
A

logical

remain unchanged
DAT register.

unless

the

processor

Signals

has a 50-pin D-type male connector
the user.
A flat cable or a user
be used for field connection.

"1"

output

outputs

means

For the correct electrical
"Specification".

the

reed

signal

contact

requirements,

for
made

closed.
see

NOTE

The +5V output on
Pin
38
is
used for DIGITAL manufacturing

the
output
twisted pair

normally
purposes.

chapter

4.2

IDV1S-—C

16-BIT

RELAY

OUTPUT

+--------- 4+—-—-—-——-—
!
I/O
!
Signal Name
!Connector!
!
Pin
t
+—-—------- $e eee
!
1
!Gnd
!
3
!
(Bit Q)
5
!OuUT0/2
!
!
7
fouTl/2
!
9
LOUT2/2
!
11
!OUT3 /2
!
13
!ouT4/2
!
15
!OuUT5/2
!
17
!OUT6/2
!
19
LOUT7/2
!
21
!OuUT8 /2
!
23
!OuT9 /2
!
25
!OUT1O/2
!
27
!ouTi1/2
t
29
fouT12/2
!
31
!OUT13/2
t
33
!ouT14/2
(Bit 15)
!
35
!OuUT15/2
!
37
!
!
39
!
41
!
!
t
43
!
!
45
!
!
4‘]
!
t
49
!
+-------- +

Table

4-2:

IDV1S-C

Connector

(M8005-P0 )

Page

+——----—---— +—-—--—-------~------- +
I/O

!Connector!
Signal Name
!
Pin
!
4+——-~——---—- 4+———-~——---~—-—-—-----—--!
2
!
!
4
!OUTO/1
(Bit 0)
!
6
!OUT1/1
!
8
{OUT2Z/1
10
!OUT3/1
!

!
!
!
!
!
!
!
!

{
!

!
!

'ouT4 /1

14
16

!OUT5/1
!OuUT6/1

{
20
!
22
!
24
!
26
28
!
!
30
!
32
!
34
!
36
38
!
!
40
{
42
{
44
!
46
!
48
30
!
+—----—---Jl

!OUT7/1

!
!

!OuT8/1
!
!OuT9/1
!
!OuUT1O/S1
!
!OUT11/1
!
!OuUT12/1
!
!ouT13/1
!
!OouUT14/1
!
fOUT15/1
(Bit 15)
!
!
!
!+5Vdc Out
(Manuf.!
! Gnd
only)!
!
!
!
!
!
!
!
!
!
!
4+——--—--—--—-—-—-----—--- +

Assignment

M8005-P0

IDV1S-C

16-BIT

RELAY

OUTPUT

4.5.3

Interfacing

In the
driven

following,
some
from the IDV1S-C

IDV11-C
+5V

typical
outputs,

OUTX/1

Page

user
circuits,
are shown.

User

Circuits

which

can _

Vdc

0,1pF

Lamp

472.

OUT L ——

OUTX/2.

OUTX/1

OUTX/2

max.

Vdc

DC
Motor

max.

|>—

OUTX/1

Vdc

Relay/
Solenoid

OUTX/2-

Figure

4-6:

IDV1S-C

4-11

IDV1S-C

Output
T

—

the

(M8005-P0)

Application

Circuits

(M8005-P0)

1
-

CHAPTER
IAVIS-B

5.1

The

GENERAL

IAVIS-B

converter

4—CHANNEL

ISOLATED

D/A

CONVERTER

(A6007-P0)

DESCRIPTION

module

four

channel

(A6007-P0)

group

for

the

isolated

Q-bus.

digital

It offers a choice of voltage and current outputs.
outputs
are
self-powered
and
selectable
by
a
O-20mMA or 4-20mA.
Each
data
word

DAC has a double buffer
resolution.
The
DAC
format.

The double buffer
the
DAC’s
with
requires
this.

DAC
an

registers
external

analogue

The
current
mode-plug
for

provides
12-bit input
written by program in

can be simultaneously latched to
control
signal,
if the process

The digital
data and the control
signals are transmitted
to
the
four
DAC’s
through
optical
couplers
that isolate
the analogue
circuits
from the computer.
The
analogue
power
for
the
DAC
Circuits
is produced by an isolated DC/DC converter
(see figure
5-1 IAV1S-B Block Diagram).

IAVIS-B

Features

- Four group isolated D/A converters
- 12 bit resolution
- Voltage
output 0 to +10V
—- Current output,
selectable
for 0 to 20mA or 4 to
- Software
identification of open 20mA outputs
—- Input signal
for simultaneous
latching of the
DAC registers
-~ Module
identification
code readable by program

20mA

IAVIS-B

4—CHANNEL

ISOLATED

CONVERTER

(A6007-P0)

CONTROL

VY QUT

I OUT

DATA
ISOLATORS
|
|

VY QUT

VOUT

1 OUT

I OUT

CONTROL
ISOLATORS
|

V OUT

I OUT

ISOLATED

5-1:

IAV1S-B

5-2

Figure

Page

USER
CONNECTOR

DAC-REGISTER
LOGIC

CONTROL
LINES

D/A

Simple

BC/DC
F$—a,
CONVERTER
}——
- 15)

Block

Diagram

(A6007-P0)

IAV1S-B
5.2

4-CHANNEL

ISOLATED

D/A

CONVERTER

Page

(A6007-P0)

5-3

SPECIFICATION

Module

Designation

Identification

A6007-P0
200

octal,

Size

Quad

Power

+5Vde

when

Load

code

the

MOD

high

Module

(for

BA200

+5%

enclosure)

Bus

(identification

reading

1,5A

DC-Load;

1,4

AC-Load

(group

isolated)

OPERATIONAL

Analogue

Outputs

Resolution

12-Bit

part

binary

4096)

DAC

Digital

Inputs

12-Bits

encoded

DAC

Digital

Storage

Write Only Register
Word Operation

Response

Time

between
(serial

Isolation

Voltage

Analogue Outputs
Gnd 500 Vdc

4
0

3,9 microamp
4,88 microamp

CURRENT

Range

(plug

OUTPUT

Offset
Load

Computer

CHARACTERISTICS

selectable)

Maximum

1 and 150 microsecs
load sequence of DAC)

Resistance

to
to

20mA;
20mA;

LSB
LSB

Adjustable

per

channel

500

Ohm

Gain

Accuracy

Adjustable

per

Gain

Temp.

FSR/degree

celsius

0,4

microamps/degree

celsius

LSB

maximum

LSB

maximum

Offset
Integral

Coefficient

Temp.

Coefficient

Non-linearity

Differential

Non-linearity

ppm

IAV1S-B

4-CHANNEL

ISOLATED

D/A

CONVERTER

Monotonicity

Slew

1,2

Rate

VOLTAGE

OUTPUT

Bits

LSB

2,4

Current

Accuracy

Offset
Gain

Temperature

Integral

Coefficient

Non-linearity

Differential

Non-linearity

Adjustable

per

channel

Adjustable

per

channel

FSR/Degrees

ppm

1,5

LSB

maximum

1,5

LSB

maximum

Slew

Rate

0,6

BUS

INTERFACE

Addressing

+10V

5mA (Short circuit
protected
to Ground)

Monotonicity

Gain

Output

milliamps/microsec

CHARACTERISTICS

Range

Maximum

Page

(A6007-P0)

Bits
V/microsec

Switch

I/O

celsius

selectable

address

area,

4 word
addresses
word unused.

over

occupies

with

5-4

IAV1S-B
5.3

4-CHANNEL

ISOLATED

D/A

CONVERTER

(A6007-P0)

Page

5-5

INSTALLATION

5.3.1

The

Q-bus

Site

Consideration

IAV1S-B

slot.

has

two

bus

These

interface

connectors

have

connectors
signals

that

defined

Specification.
The module
can be plugged into
Q-bus
backplane
according
to
the
rules
of
configuration.

5.3.2

any
the

plug
by

slot
Q-bus

into

Q-bus

of
a
system

Interconnection

Interfacing
the IAV1S-B
to the user’s device
is
done
via _ the
50-pin
D-type
male
connector.
A 50-conductor
flat cable ora
user made twisted pair cable may be used for
field
connection.
The
pin
assignment
and
the
signal
description are shown in
chapter
5.5.
General
information
about
the
user
I1/0O-connector
and
the
physical
requirements
are given in chapter
1.4.6.

5.3.3

Initial

Selecting

Operation

the

IAV1S-B

Device

Address

The
device
address
is
the
I/O
address
assigned
to
the
MOD-register.
The
device
address
is
selected via a 10-pole
Switch
(see figure
5-3).
The switches allow the device
address
within a range of 160000 octal to 177770 octal
to be set.
The

standard

address

16114

1247

OFF

|
|
OFF

S10

171000

1
;
Logical
Logical

Figure

171370

wT"
"0"

= ON
= OFF

5-2:

range

for

increments

Selecting

this

module

OFF

S$]

IAV1S-B

Device

octal

recommended

(see

Figure

Factory configured
within Standard
Address Range
(171000 to 171370)

Address

5-2).

from

IAVIS-B

4-CHANNEL

“Selecting

the

ISOLATED

Current

Output

The current output
20-pin DIL plug.

mode

Pin
Pin

1
11

1
1

plug
plug

to
to

The IAV1IS-B is
2Z0mA outputs.

new

pin
pin

D/A

for

CONVERTER

The state of this
MOD-register.

all

socket
socket

four
4
0

necessary.

plug

can

Page

5-6

Modes

to
to

normally shipped with
If the voltage or the

calibration

(A6007-P0)

See

DAC’s
20mA
20mA

output
output

the
4 to

calibration
20mA outputs

chapter

identified

selected

5.5.3.

software

of
are

0
to
used,
in

the

IAV1S-B

ISOLATED

4-CHANNEL

D/A

CONVERTER

Page

(A6007-P0)

5-7

Van

TAVIS
-B

AGOLT
~ PS

_———
— Offset -

ADJUST
OFFS

Adjust

3
7
|

Gain
Adjust

ennww
Deo-wuf

Maint.
LED

PALE

Pos

L.
=

p
C

ame
=

a.
pe

COE
=
>
Lone
UU.

r tke

1/0
Connector

rt.

A6007

- PO
<x

Current

Offset Plug
|

E38 Device

Address

4 to
9

20mA
2fmA

]

Posll=

Filler

Plastic

Figure

5-3:

IAVIS-B

Physical

Layout

Switch

v1
Pos

A NA LOS
OUTPUT

(A6007-P0)

Panel

IAVIS-B

4-CHANNEL

OPERATION

5.4
5.4.1

ISOLATED

AND

D/A

CONVERTER

(A6007-P0)

5-8

PROGRAMMING

General

This chapter presents
a
detailed
description
register
(see
figures
5-4
to
5-6).
Four
addresses
are assigned to the register
set.
171XX0
171XX2
171XX4

Mode Register
DAC Data Register
Control
Status Register

171XX6

These
their

Page

(MOD)
(DAT)
(CSR)

unused

can be read
addresses.

loaded

of
the
IAV1S-B
consecutive
bus

using

any

instruction

that

refers

signal
issued
by
one
of

by
the

Initialization

The mnemonic
INIT
the
processor.
following:
~
~
—-

refers to the initialization
Initialization
is
caused

issuing a programmed RESET instruction
depressing
the start switch on the processor
console
the occurrence
of a power-up or power-down
sequence

The

MOD,

Operation

DAT

and

CSR

registers

are

then

initialized.

Modes:

The
can
can

current output mode of the four DAC’s
is the
be changed by a DIL-plug on the module.
The
be selected between 0 to 20mA and 4 to 20mA.

The

position

20mA

When

output

the

current

COFS-bit

range

mode

plug

(current

selected.

readable

output

only mode which
current outputs

offset)

the

set,

MOD

the

IAVIS-B

4-CHANNEL

Execution

ISOLATED

D/A

Check

Load

Write

that

the

channel

DAC

conversion

READY

data

CONVERTER

(A6007-P0)

Page

Conversion

A digital-to-analogue
the following
steps:
-

D/A

flag

address

The DAC data are now
the
DAC
circuit.
microsecs,
the READY
loaded again.

the

bit

DAT

is
set

CH0,1

performed

for

the

for

each

desired

transferred by an internal
load
During
this
time
of
between
is cleared and the DAT register

DAC

cycle
1
and
cannot

150
be

DAC

IAV1IS-B

5.4.2
The
its

4-CHANNEL

Mode

ISOLATED

D/A

CONVERTER

(A6007-P0)

Page

(MOD)

MOD register
is generally used to identify the
module
identification
code and for maintenance
purposes.
$—-—
'Bit!

Name

with

+
!

Description

115
!
IDENT 7
!to
!
to
IDENT 0
! 8 !
!
!(read only)
!
!
! 6 !
LED

!
!
!
!
!
!

Identification Bits 7-0.
The module
is identified by these
bits.
The A6007 has the code
200 octal
(in high byte).

t
!
:
!
!
!
!

!
!
!
!
!
!
!

Current Output Offset
!
This bit reads the position of the!
current output configuration plug.!
If COFS is set,
the 4 to 20mA
!
output
range of all four DAC’s
is !
selected.
Otherwise
the 0 to
!
20mA range
is on.
!

| --—+—-—-—-—-—------— pa nnn
rrr

!
!

LED

!( read/write)!
!
!

COFS
!(read only)
!
!
!
!
!
!

+— -—-— -— - —

indication

5-1:

MOD

171XX0

purposes.

IAV1S-B

MOD

Mode
+11

«+10

#09

R
W
R/W
All
and

5-4:

=
=
=

bits
read

O08 | 07

06
LED
R/W

Bit

Read Only
Write Only
Read/Write

not described
are
or write
as zero

IAV1S-B

!
!
!
!
!
!

!
!

READ ONLY

Figure

test

PD ENG
7 J6{s5talt3i{etilo

NOTE:

for

- — — - - - -

Table

5-10

Mode

Assignments

COFS
R

unused

IAVIS-B

4-CHANNEL

5.4.3

DAC

Data

ISOLATED

D/A

CONVERTER

(A6007-P0)

Page

5-11

(DAT)

The DAT register
is a 12-bit write only register.
It
can
only
be
loaded by word instruction.
After loading the DAT register,
the data is transferred
to DAC
circuits
by
an
internal
load
sequence.
The data code for the DAC’sS is binary code.
Refer to
the Coding Table
in chapter
5.5.
DAT

171XX2

NOTE:

R
W

R/W
All
and

Figure

5-5:

DAC

Data

(MSB )
DA DAT
(LSB)
11 | 10 | 09 | 08] 07| 06 | 05 | 04 | 03 | 02 | 01| 00
WRITE ONLY

=
=

Read Only
Write Only

=
Read/write
bits
not described
are
read
or write
as zero

IAV1S-B

DAC

Data

unused

IAV1IS-B

4-CHANNEL

CSR

byte

16-bit

format.

Table

eum
eum
eum
OT
@=F
O-™B
CO-—
OC]

Open

Line

done

when

the

READY

6-8

@-0

O-3

DAT-register

emmw

the

oun

can be
again.

OPL
is set
channel
is

means

that
or

!
!
FNCT
!( read/write)
|

IAV1IS-B

than

LSB.

20mA

Outputs

when
the
addressed
not
connected.
This

the

not

20mA output
detected if

5-2:

write

DAT
set

broken

!
4

READY
is cleared
for between
1 and
150 microsecs
after
the DAT has
been
loaded.
The
next write
to the

eum

only)

!
!

OPL

!(read
!

Ready

QO-8

5 !

!
!
!

only)

!
!
!

Channel Address
Binary addressing of the DAC’s
which should be loaded via the
DAT-—register.

O-m

READY

!(read

!
!
!
'

20mA

used.

output
In

range,
OPL
the output

the

is
is

line
0

6-8

0-3

only
greater

eo=mnw

CHA

channel

O-=D

{

CHA

!( read/write)

the

CHA-bits

O-B

the

O-P

addressed by
the system.

@O-;

! 8

Channel
Available.
This
bit
is set when

O-D

!
!
!
!
19 !

only)

eo=w

in
It can be
written
are described
in Table

read/write
register.
The
bit definitions

C-—=>

!(read

The Function Bit is present as TTL
output signal.
It has non-internal
meaning.
This bit is unused and
for future expansion.

CSR

5-12

(CSR)

Name

| ~--4+——--—~~-—~-~--~
'15 !
CHAVAI
!

Page

Bit

Assignment

eum

{Bit!

(A6007-P0)

€-—0

word
5-2.

Status

CONVERTER

@-8

The

Control

D/A

5.4.4

ISOLATED

IAV1S-B

4—CHANNEL

CSR

171XX4

uh
avall

ISOLATED

Control

R/W

R
W

=
=

All
and

bits
read

R/W

Figure

Status

5-6:

CONVERTER

(A6007-P0)

Ipeapy| §=— | OPL JFNCT
CH
1 | 0

NOTE:

D/A

|R/W

Read Only
Write Only
Read/Write

not described
are
or write
as zero

IAV1S-B

Control

Status

unused

Page

5-13

IAVIS-B
5.5

4-CHANNEL

FUNCTIONAL

5.5.1

Theory

ISOLATED

D/A

CONVERTER

(A6007-P0)

Page

5-14

DESCRIPTION

Operation

Figure
5-1 shows a simple block diagram of the IAV1S-B.
It
is
addressed
via
the
LSI-11
bus address
lines.
The board has a
10-pole DIL switch to select its device address according to the
rules
in chapter
5.3.
The four DAC’s are monolithic
12-bit multiplying D/A converters,
which
are
isolated
from the computer with opto couplers
and a
DC/DC

converter.

The DAC-data are stored in four 12-bit
registers
on the
Side.
These
registers
are permanently updated to the
double buffer
registers
of the DAC-IC’s by a sequential
load logic.
Each DAC-IC
is loaded in two
loaded
to
the
DAC
input
LSB’s,
all 12 bits are gated

computer
internal
register

steps.
First
the
8
MSB’s_
are
latch and after loading the other 4
to the DAC holding
register.

A comparator
on each DAC-current
output
circuit
monitors’
the
-IOUT
line.
The
comparator
gives
an
"Open Line"
signal
to
CSR-register when the voltage
at this
output
is
greater
than
-11,2V
(see figure
5-7).
To detect open lines
in the 0 to 20mA
Output Range,
at least 5 LSB must be set.
The four DAC circuits have separate voltage and current outputs,
but
they
cannot be used at the same time.
The calibration per
channel
can only be done
either
for
voltage
or
for
current
outputs,

but

not

for

both.

IAVIS-B

4-CHANNEL

ISOLATED

D/A

CONVERTER

(A6007-P0)

( 1 of 4 identical

VREF

—
1S0LATORS

Page

GAIN

DATA

—
CONTR

DAC

__k.

OUT1

CURRENT

Lo | -vout

CONVERTER

)

0 to +10

LATCH

DGND

ADJUST

RFB

VREF

circuits

5-15

= AGND

lo | +iouT

—- (1)

OUT

SRL

——
Current
Offset

+15]

Plug

| -15

OFFSET ADJUST

—_

OFF
+15
+

|
|
|

Figure

(1):

5-7:

-15V

NOTE

Comp.

(-11,2V)

RL max for the
The equivalent

IAV1S-B

+5V
( common

current
voltage

DAC-Circuit

for

outputs
is then

(A6007-P0)

all

four

DAC's

is 500
10V at

)

ohm.
20maA.

OPEN LINE L

O|LDISL

IAVIS-B

5.5.2

4-CHANNEL

Mode

Current

Output

ISOLATED

D/A

CONVERTER

1
1

Page

5-16

Operation
Modes

The current outputs
for all four
20-pin DIL plug in two modes.
Pin
Pin

(A6007-P0)

plug
plug

to
to

pin
pin

DAC’s

can

4
0

20mA
20mA

output
output

1 socket
11 socket

to
to

selected

The current offset plug is always
installed on
the
board
(See
figure
5-3)
and its position
is readable by the COFS-bit
in the
MOD register.

DAC

Latch

Control

With the input signal
holding
registers
can

Latch Disable
(L DIS L), all
be latched simultaneously.

Normally,
the L DIS L-signal
is not used and
not
the
user and the DAC holding
register
is directly
programmed
load instruction.
If
to

the external
L
high
(min 150

the

DAC

latches

are

loaded

outputs

DIS L signal
1s
microsecs),
the

will

simultaneously

changed

four

DAC-IC’s

connected
loaded by

by
the

connected and changed from low
contents of the four DAC input
into

the

same

DAC’s,

time.

and

therefore

IAV1S-B

D/A

4-CHANNEL

Converter

The DAC
code.

ISOLATED

D/A

CONVERTER

(A6007-P0)

Page

5-17

Coding

registers

are

The analogue
outputs
ranges listed
in the

loaded

with

12-bit

(4096

states)

operate
in
unipolar
operation
following coding tables.

binary
with

the

+—---—---—--------- - +
! Scale
!
Full Scale Range
!
Binary Coding
!
!
!0 to +10V!0
to 20mA!4
to 20mA!
MSB
LSB
!
{!----—---- +—-—--------— +—-—------- 4+——------- 4+——--—-----—--------- !
! FS-1LSB!
9.9976
! 19.995
! 19.996
! 111 111 111111!
! 374 FS ! 7.5000
! 15.000
! 16.000
! 110 000 000 000 !
! 1/2 FS ! 5.0000
! 10.000
! 12.000
! 100 000 000 000 !
11/4
FS ! 2.5000
! 05.000
! 08.000
! 010 000 000 000 !
! 1 LSB
! 0.0024
! 00.005
! 04.004
! 000 000 000 001
!
! ZERO
! 0.0000
! 00.000
! 04.000
! Q00 000 Q00 000
!
!

+—-—- —- - - -—

- - - - --

+—---——-——-—------- !
Current to voltage Conversion with RL 500 ohm (1)
fe

!
!
!
!
!
!

19.995
15.000
10.000
05.000
00.005
00.000

+— - -—-—-—
NOTE

Table

20mA

!
'

!0
1

!
!
!
!
!->!
!
!
!
!
!
!
!

eee

-10V !

9.9976
7.5000
5.0000
2.5000
0.0024
Q.0000

!
!
!
!
!
!
!

(1):

5-3:

eee

!
!
!
'
!
1

19.996
16.000
12.000
08.000
04.004
04.000

!
!
!
!
!->!
!
!
!
$$!
!
!

- - -

20mA!

+
!

!-2

-10V!

9.998
8.000
6.000
4.000
2.002
2.000

!
!
!
!
!
t
!

= +

This table shows the equivalent voltage when
the
current
outputs are supplied
with 500
ohm resistors,
as described
in chapter
5.5.3
"Calibration".

IAV1S-B

D/A

Coding

Tables

IAVIS-B

5.5.3

4-CHANNEL

ISOLATED

D/A

CONVERTER

(A6007-P0)

Page

5-18

Calibration

It is only possible
to calibrate
either
the
voltage
output
or
the
current
output.
The IAV1S-B
is normally shipped with the
calibration of 0 to 20mA outputs.
If the user wants
to
change
the
0 to 20mA current output to 4 to 20mA or to voltage
output,
a new calibration
is necessary.
The calibration
is
done
with
the
diagnostic
software,
see example
in the diagnostic
software
description.
The trim potentiometers
for the calibration adjustment
of the
4
channels
can
be
found in the installation
section,
Figure
5-3
IAV1S-B Physical
Layout
(A6007).

Calibration

Equipment

Digital

Test connector
assembly
(see Appendix B) or
ohm
resistor
(preferably
a 0,01%
resistor
number
13-09985-00).

The

DVM

voltmeter
should

have

measure

the

accuracy

voltage

0,01%.

and

current

outputs.

a
Precision
with the DEC

500
part

IAV1IS-B

Principle

Voltage

4-CHANNEL

ISOLATED

D/A

CONVERTER

Output

Load the DAC with
trimpot until
the

Step

Load the DAC with all 12 bits
trimpot
until
the
digital
(FS-1LSB).

Output

Step

Adjust the offset
indicates
0,000V.

at 1.
Adjust
the
GAIN
voltmeter
shows +9,997V

resistor
together with the digital
voltmeter
outputs
(+IOUT/-IOUT)
of the channel which is

Load the DAC with
offset trimpot as
a.

all 12 bits at 0.
digital voltmeter

Adjustment

Attach the 500 ohm
on
to the current
to be calibrated.
1:

5-19

Adjustment

Step

Page

Calibration

Step

Current

(A6007-P0)

all 12 bits
follows:

4 to 20mA output
: Offset
to 4.000mA or -2.000V

adjust

20mA

between
between

output

Offset

0.000mA
and
0.002mA
0.000V
and -0.001V

with all 12
as follows:

"1"

Load
GAIN

the DAC
trimpot

bits

4 to 20mA output
: GAIN
to 19.996mA or -9.998V

adjust

O to 20mA output
: GAIN
to 19,995mA or -9,997V

adjust

and

adjust

the

and

adjust

the

IAV1IS-B

5.5.4

4-CHANNEL

Analogue

ISOLATED

Output

D/A

CONVERTER

(A6007-P0)

Page

5-20

Signals

The IAVIS-B analogue
output voltage and
current
signals
leave
the board via a 50-pin D-type male connector.
A flat cable ora
user made twisted pair cable could be used for field connection.
Each DAC has
a
separate
current
and
voltage
output
and
a
corresponding
analogue
ground pin.
For the correct electrical
analogue
output
Signal
requirements,
see
chapter
5.2
"Specification".
The input signal Latch Disable
(L DIS L)
is
powered
from
the
isolated
analogue
power.
If
this
signal
is
used,
its
corresponding
return line is ANA Gnd.
The Function
(FNCT L) output
is a TTL-output which is
set
from
the
FNCT-bit
in
the
CSR_
register.
This
line is not field
Supported,
it is only used for test purposes.
The digital +5V output on pin 38 is protected by a 1A pico
fuse
and is normally used for DIGITAL manufacturing purposes
only.
+-—---- +—-——--—--—-—---------- +—----— $e
! I/O !
Signal
! I/O
!
Signal
!Conn.!
Name
!Conn.!
Name
! Pin !
! Pin
!
+----—- +——----———--—--~-—--------- +----- +——-—--—-------

+
!
!
!
+

!
!
{

!
!
!

!-vyoUT2

!-I0uTO

!
f
:
!
:

11 !-vouT3
13 !
15 !
17!
19!

{

!
!
'

25
27
29

f
!

Analogue Gnd!
for Voltage
!

4
6
8

!+VOUTO
!+VOUT1
!4+VOUT2

)

f
!
'
!'
f

12
14
16
18
20

!
!
!
!
!+IOUTO

) Outputs

)

!-IOUTL

!-IOuT2
!-IOUT3
!

35 !

!L
!

)
)

1 10

Current

Outputs
CHO

f
!

CH3

39
!FNCT
41!
43
|
45
!
49

‘ANA

!
!

!DIG
!

+ Voltage
Outputs
CHO to CH3

)

Analogue

)

Outputs

)

{$4+I0UT2

32
34

)

!+I0UT3
!
!

!
!
!
!
'

)
>
)

$4+I0UT1

26
28
30

!
!

!+VvouT3

!
!
f

!
1

DIS

2 3!

)
>

31!
33 !

!
!

!
!
tf
,

3!
5 !-vouToO
7 !-VOUTI1

Gnd

+5V

40
!Gnd
42
!
44 $3!
46
!
48
!
fr 50
!

for

Gnd!

Current !

!
!
!
!

!
!
!

!
!
Out

(manuf.
only)

!
!

t
!
t
!
!
!

+—----— +—--------~-~---------- +—----—— 4+—-—-~-----—-~—----—-------- +

Table

5-4:

IAV1S-B

Connector

Assignment

A6007-P0

IAVIS-B

5.5.5

4-CHANNEL

Interfacing

ISOLATED

the

D/A

CONVERTER

(A6007-P0)

Outputs

(0 to t0V)

Analogue

+ VOUT

+15

inputs
are
outputs.

Instrument

ar,

- VOUT

;

Slo,

Anal.

Gnd

Differential
Input

(0 to 10V)

+ VOUT

aa
|

’

|
)

+15
- VOUT

|
|

Current
9

Single-Ended
Input

Output

:
+

IQUT

é,
f

\
x

IOUT

(|
\

R
)

ots

—

Differential

Input

Re max.

Figure

5-8:

Connection

the

5-21

IAV1S-B

In the following,
some typical
analogue
instrument
shown which may be connected
to the IAV1S-B analogue

ITAV11-B

Page

IAV1S-B,

(A6007-P0)

= 500s.

CHAPTER
IAV1IS-A/AA

6.1

GENERAL

CHANNEL

A/D

6
CONVERTER

(A410-P0/PA)

DESCRIPTION

The IAV1IS-A/AA
modules
for the

are
16
Q-bus.

channel
analogue-to-digital
The two board versions are;

IAVIS-A

Channel

A/D-Converter

4/12

converter

(A410-P0)

12 channel
single-ended
inputs
with
analogue
semiconductor
multiplexers.
4
Channel
isolated,
differential
flying
Capacitor
inputs,
which are used for analogue
field
signals
where
a
high
degree of isolation
from common mode voltages
must be maintained.
The 4 channel
flying
capacitor
inputs
are selected by a reed-relay multiplexer.
IAV1IS-AA

Channel

The
IAVI1S-AA
semiconductor

A/D-Converter

has
only
multiplexer,

16
like

(A410-PA)

single-ended
the 12 channels

inputs
with
of IAVI1S-A.

The IAV1S-A or IAVIS-AA are expandable
by
multiplexer
boards,
such as the IAV1S-C or IAVIS-CA expansion multiplexer boards,
up
to 128 channels
in any combination.
Analogue
to digital
conversions
are started by
program
command
Or
an
external
trigger.
After
the conversion on the selected
channel
is done,
the DONE-flag
is set and an interrupt occurs.
NOTE

All

general

refers
to
IAVIS—AA,

information

the
IAVIS-A,
but
if not otherwise

this

is also
noted.

description

valid

for

the

IAV1S-A/AA

CHANNEL

A/D

CONVERTER

(A410-P0/PA)

Page

6-2

FEATURES
o

For

4 potentially
free,
true differential
flying
channels
12 single-ended
solid state
input channels

For

16
channel
non-isolated

For

—-

12-bit
resolution
Unipolar
(0 to +10V)

~
——-~

External
trigger
input
Expandable
by multiplexer
boards up to maximum of 128
Module
identification
code readable by program
both
A/D-converter
versions
can
be
installed
combination with the IAV1S-C and IAV1IS-CA multiplexer

IAVIS-A

only

IAV1S-AA

both

software

capacitor

input

only
single-ended

solid

state

analogue

inputs

versions

programmable

bipolar

gains

(+10V)

input

10,

range

20,

50,

100,

200

channels
in
any
versions

IAVIS-A/AA

CHANNEL

A/D

(A410-P0/PA)

CONVERTER

Page

6-3

CH ADR 0-6
MUX

CONVERT

BOARD

ANA

BUS

INTERRUPT

CONNECTOR

LOGIC

CONTROL
CONTROL
USER

CONVERT

CONNECTOR
Flying

Ji
+ ANA

LOGIC

LINES

Cap.

(1 of 4)”
- ANA

GAIN
IN

ANA IN
(1 of 12)
ANA RTN

NOTE:

Figure

JIN

SELECT

RANGE SELECT
(0 to +10V or t10V)

OUT

ANALOGUE
MUX

In the
IAVI1S-AA
(channel
0
to
inputs,
like the

6-1:

IAVIS-A

version
3)
have
other 12

Simple

Block

(A410-PA)
these
only semiconductor
channels.

Diagram

A410-P0

4
channels
multiplexer

IAVIS-A/AA
6.2

CHANNEL

A/D

CONVERTER

(A410-P0/PA)

Page

6-4

SPECIFICATION
Parameter

Module

IAVILS-A

Designation

A410-P0

IAV1S-AA

AR410-PA

Identification

Board

100

Quad

Size

Power

(for

BA200

{

enclosures)

Cap-

{

(switch

selected)

Conversion

Unipolar

Flying

t
!
t
t

able

Gains

ome

cee

ee cee

Programm-

cap.

@-—=

+10V;

chan. !

8,5 msec.
per
channel
(115 Hz)

!
|

Software

Bipolar

Time

@o-m

12-Bit

Coding

Output

16 solid state
Single-ended
inputs
(non isolated)

Connector
for Mux-Board allows
up to 112 extended channels

Resolution

AC-load

oun

12 solid state
Single ended inputs!

Expansion

1,6

abilities

DC-load;

4 potentially
free,!
true differential
flying cap.
inputs

oom

MOD

> ay

Module

identification

the

1+5vdce + 5% at 1,3A !+5Vdc + 5% at 1,25A

No. of Analogue
Channels

high

Load

A/D

(software

reading

o—m

Bus

octal

when

!
i

+10V;

binary

offset

code

binary

code

N.A.

:
!
!

Solid State Channels:
typ.
4Qmicrosec.
at gain
typ.
l0OQmicrosec.
at gain

1 to 10
20 to 200

1, 2, 5, 10,

200,

20,

50, 100,

t
ee

coe

es we

ITAVIS-A/AA

CHANNEL

Parameter

A/D

CONVERTER

(A410-P0/PA)

IAVIS-A

Page

TAV1S—-AA

System Accuracy
(Bipolar Mode)

!
!
'
!
!
|
t
!

Linearity
Input

Gain

|
|
!

Gain Temperature
Coefficient

Offset

Temperature

Coefficient

1
!

Warm-up

Time

Input

Protection

Input

Filter

Common Mode and
Crosstalk Rejec.

Isolation

Interchannel

Voltage

|
!

!
|

NOTE:

Flying

LSB

megohm

LSB

gain

max.

ppm/degree

20
>

celsius

ppm/degree

celsius

minutes
!

and

!
!

LSB

{

Isolation

100

{

max.

Gain 200 + 5 LSB
In unipolar mode the system accuracy
deviates between gain 10 and 200 by
1 to 2 LSB from values given for
bipolar mode.
Note,
that the above are
specified
for a system calibration at
gain l.

Impedance

+ 25V at power ON
15V at power OFF
|

First order low
pass filter,
cut
off frequency
2,95 Hz

!
!
f
!

N.A.

100 dB
50 Hz

typ.

!
!

N.A.

1000

Inputs

Vde

250

Vde

Comp.

Gnd!

peak

AC!

N.A.
I

N.A.

Capacitors

inputs

Channels

only

6-5

IAV1S-A/AA

CHANNEL

Parameter

A/D

CONVERTER

(A410-P0/PA)

IAVILS-A

Page

IAV1LS-—AA

|
!
!

Interrupt

Vector

!
!
!

Priority

Level

Switch selectable
over
I/O address erea.
Four
with one word unused.

the 4 k
word address

Switch

from

000

selectable

Done

XX0;

BR4;

Jumper

Error

XxX4

770

octal

6-6

IAV1IS-A/AA

6.3

CHANNEL

A/D

CONVERTER

(A410-P0/PA)

Page

6-7

INSTALLATION

6.3.1

Site

Considerations

The IAV1IS-A/AA has two bus interface
connectors
that plug into a
QO-bus
slot.
These connectors
have signals defined by the Q-bus
specification.
The
interrupt
priority
of
the
module
1s
determined
by
the
position
on
the
Bus
(Position Dependent
Configuration).
The closer a device
is to
the
processor,
the
higher
its priority.

6.3.2

Interconnection

Interfacing
the IAV1S-A/AA to the user’s device
is done via
the
50-pin
D-type
male
connector.
A 50-conductor
flat cable or a
user made twisted pair cable may be used for
field
connection.
The
pin
assignment
and
the
signal
description are shown in
chapter 6.5.
General
information
about
the
user
1I1/0-connector
and
the
physical
requirements
are given in chapter 1.4.6.
Connection of a IAVIS-C/CA multiplexer board to
the
IAV1S-A/AA
is
done via the 26 pin connector
J2 and a T-type
flat cable,
as
described
in the multiplexer
description.

6.3.3

Initial

Selecting

Operation

the

IAV1S-A/AA

Device

Address

The
device
address
is
the
I/0
address
assigned
to
the
MOD-register.
The
device
address
is
selected via a 10-pole
Switch
(Figure 6-4).
The switches allow the device
address
to
be set within a range of 160000 octal to 177770 octal.
The standard address
range for this module
is
from
171400
to
171770
in increments
of 10 octal.
15 | 14

12 | 11

«69

{

X |

Logical
Logical

Figure

1
@

6-2:

PTET

OFF OFF

S10

tT td

Selecting

ET do

X ~~

§3

$2.

IAV1S-A/AA

Device

Factory

configured

within

Standard

(171400

Address

Range

Address

171770}

IAVIS-A/AA

Selecting

the

CHANNEL

A/D

IAVIS-A/AA

CONVERTER

Interrupt

(A410-P0/PA)

Vector

Page

6-8

Address

The IAVIS-A 1s capable of generating two interrupt vectors
(DONE
and ERR INTERRUPT).
The interrupt vector address
can be set via
a 6-pole
switch
(Figure
6-4) within the range of 0 to 770
octal
in increments
of 10 octal.
For

standard

vector,

the

vector

switches

(Figure

should
have
the
same
position as the address
switches
1
(Figure 6-2).
This means that the address and
the
vector
identical
at the address bits 3 to 8.

15]

#127

#10

«9

Factory configured
within Standard
Vector Range
(400 to 770)

|
Logical
Logical

Figure

1 = ON
9 = OFF

6-3:

Selecting

ON
|

X
|

IAV1S-A/AA

|
|
S2_

xX
|

0
0

St!

Interrupt

Vector

6-3)

to 6
are

IAV1S-A/AA

A/D

CHANNEL

TAVIS
-A

Aan

PaesS
=

abaust

»
=>

Coo

| @mana|

Maint.
LED

PALBIP

1/0
Connector

=
—~

4
Wiwe

t10V <———>0 to+10V
Bipolar/Unip Switch

iter

Adjust

Gain

AY
q_s«d’

fwwe

eteritent

qnueed

Nevice

«>

ONfeteeetead

OFF

Offset

Address

)

Switch

Vector
e

PGA

Switch

IE |

—
=

mits

- PX

A410

—

__—

-~
r

01 Maint. Led

Gf} ——F—
NL

Te)
fo)

6-9

Page

(A410-P0/PA)

CONVERTER

MUX
MUX
Connector
Plastic

Filler

Panel

Lo:|
ray

Ae
|

ANALOG
IWPUT

Figure

6-4:

IAV1S-A/AA

peed)

* NOTE: The

Physical

PGA

Offset

Layout

factory

calibrated

(A410-P0/PA)

IAV1IS-A/AA

Selecting

the

CHANNEL

A/D

Interrupt

The standard
interrupt
request
level,
BIRQ5
BR5 or BR6.

CONVERTER

Request

(A410-P0/PA)

Page

6-10

Level

request level
or BIRQ6
can

is
be

4
(BIRQ4).
selected via

A
the

higher
jumpers

Whenever
the BIRQ4 on the module
is changed to a
higher
level,
no
other
modules
should be installed on the bus closer to the
processor which have
a
lower
request
level.
The
interrupt

priority

monitor

Selecting

the

IAV1S-A/AA

higher

request

levels.

the

Analogue

Input

position

dependent

and

does

not

Range

The unipolar
(0 to +10V)
and the bipolar
(+10V)
input
be selected by a single DIL-switch,
see figure 6-4.

range

may

The IAV1S-A is normally shipped and calibrated
in
the
Bipolar
Input
Range.
The
switch
position for the input
range can be
read by the program in the MOD-register
bit 4 (BIP).
If BIP
is
set,

the

bipolar

range

selected.

However,
if the input range has to be changed,
a
is necessary.
See chapter
6.5.3
"Calibration".

6.4

6.4.1

OPERATION

AND

calibration

PROGRAMMING

General

This chapter presents
a
detailed
registers
(see Figure 6-5).
Four
assigned to the register
set.

description
consecutive
:

171Xx0

(MOD)

Mode

171XX2

ADC-Data

171XxX6

unused

171XX4

new

Control

They can read or
their address.

Status

written

using

of
bus

the
IAVIS-A
addresses
are

(DAT)

(CSR)
any

instruction

that

refers

IAVIS-A/AA

CHANNEL

A/D

CONVERTER

(A410-P0/PA)

Page

6-1l

Initialization

The mnemonic
INIT
the
processor.
following:
—~
—-

refers to the initialization
Initialization
1s
caused

MOD

and

Operation
The
is
the

CSR

registers

are

then

initialized.

Modes

unipolar
the only
module.

(0 to +10V)
and bipolar
(+10V)
mode which can be changed by a

The position of the
input
range
switch
MOD-register.
Normally,
the IAV1S-A is
in the bipolar
input range.

Execution

analogue

steps:

~
-

by
the

issuing a programmed RESET instruction
depressing
the start switch on the processor
console
the occurrence
of a power-up or power-down
sequence

The

signal
issued
by
one
of

A/D

digital

analogue
input range
Single DIL switch on

is
readable
in
the
shipped and calibrated

Conversion
conversion

performed

the

Check that the DONE flag is not Set.
Load the channel
address and the gain for the desired
in the CSR register.
Set the A/D START bit for internal
start or the
EET
the external
trigger
in the SCR register.

the

end

converter

data

the

can

conversion,

read

the

from

DONE

the

DAT

flag

set

following

channel
bit for
and

the

If Interrupt Enable
(IE)
is set,
an interrupt occurs by
setting
the
DONE
flag.
Reading the DAT register
clears DONE and a new
conversion can be started.

6.4.2

The
its

Mode

6-12

Page

(A410-P0/PA)

CONVERTER

A/D

CHANNEL

IAV1S-A/AA

(MOD)

with

module
is generally used to identify the
MOD register
purposes.
maintenance
code and for
identification
enn +
!

fom re
(Bit!
Name
!
Description

! —-—--—+——-—-—-------— errr

!
!
!
!

IDENT 7
115 !
to
!to !
! 8 !
IDENT 0
!(read only)
!

!
LED
!
!(read/write)!

f
!
!

4 !

!
!
!

BIP

!'(read
!
!
!

Table

6-1:

MOD

171XX0

!
'
!

the Bipolar/Unipolar
Switch on the
board.
If BIP is set,
the bipolar
range
(+10V)
is selected.

Input

Range

monitors

bit

This

the

position

!
!
!
!

rrr +

IAV1S-A/AA

Mode
11

IDENT
443
4)

R
W
R/W

=
=
=

All
bits
Zero.

6-5:

Assignments

O09

O08 | 07

406

LED

BIP

R/W

unused

and

read only
write only
read/write
not

Bit

MOD

Figure

{

Bipolar

!
!

only)

NOTE:

byte). !

purposes

test

for

indication

LED

these !

Identification Bits 7-0
is identified by
The module
bits.
The A410 module has
(in high
the code 100 octal

described

IAV1S-A/AA

Mode

are

O03

02 ~~
|

read

O01

00
|

written

IAVIS-A/AA

6.4.3

CHANNEL

ADC-Data

A/D

CONVERTER

(A410-P0/PA)

Page

6-13

(DAT)

The DAT register
is a 12-bit
read only
register.
It
contains
the
converted
data after an analoque-to-digital
conversion has
been performed.
Reading the DAT register
clears
the
DONE
and
ERR-flags
in
the
CSR
register.
The data code for the ADC is
binary code in unipolar
range
(0 to 10V)
and offset binary
code
in bipolar
range
(+10V).
Refer to the coding table chapter
6.5.

DAT

171XX2
|

- ADC

Data
(MSB )

11 |

| 09| 08

AD DAT

| 07| 06
READ

NOTE:

R
W
R/W

=
=
=

read only
write only
read/write

Figure

6-6:

6.4.4

Control

IAVIS-A/AA

Status

{| 05| 04

171XX4
14
13

AVAL | 6

CHA3 |

ADC

Data

(CSR)

pone | Ie | ERR | EET

GAIN1

R/w {| R | R/W

R/W

Interrupt

Generation

| 0

R/W

INTERRUPT

DONE

ERR

NOTE:

R
W
R/W

Figure

6-7:

=
=
=

It can be
written
in
are described
in table

—

read only
write only
read/write
IAVIS-A/AA
Generation

(LSB)

All bits not described are
unused and read or written
as zero.

Control
Status Register
120011
10 = 9
8
7
6
4

| 01|

ONLY

The CSR is a 16-bit
read/write
register.
word
or
byte
format.
The definitions
6-2.
CSR
15

| 03 | 02

(VECTOR

1
|

A/D

{START
W

XX)

VECTOR
+4
>

All bits not described are
unused and read or written
as zero.
Control

Status

Interrupt

CHANNEL

A/D

!(read

only)

3
2

!
!

GAIN
GAIN

2
1

A/D

!(write
!

6-2:

START

only)!

IAV1IS-A/AA

om
On
eo-w
9-5
O- 7
eum

and

internal

to start
input is

set

when

start

External

enables

START

Binary
1,

! A/D
!

A/D

8-8
6

conversion

bit.

Trigger

the

EXTRIG-Input

This

also

coded
10,

Conversion
bit

provided

CSR

signal

the A/D conversion.
EXTRIG-—
then wired-OR to the A/D
TTL

output

! These bits show the
! currently addressed
!

6-5

o-u

DONE

O-=2=

for

O-32

EET

GAIN 0
!(read/write)!

bit

external

Enable

Error

1
!

Enable

is made and following conditions
are present:
- DONE-flag
is set
- an A/D conversion
is currently
taking place.
ERR is cleared when the DAT register
is read.

ERROR-flags

EET

INIT.

This

!(read/write)!

6-8
oumm

@-—2

Interrupt

read

6@-——»@

ERR

conthe
DAT

o-—=

!(read/write)!

of a
when

e-e

{

the
end
cleared

ou-w

{

Done

at
is

set
It

0-2

6 !

Conversion

DONE
is
version.

O-2=

8-2

only)

! A/D

O-=82

!(read

should

conversion.

ecw

DONE

A/D

O@=@

!(read/write)!

eaw

Address
Bits
6-0
of the
channel
which

eum

Channel
Address

CHA

9-08

e=m2

CHA

from

20,

signal.

O55

OCB

Gain for the
channels.

0-7

50,

for

100

the

and

levels!

200.

@2c8

14 !

eo=m

system

eww

available.
This bit is set when the
addressed channel
is in the
(diagnostic
feature).

o—

! Channel

—_

only)!

O-—8

CHAVAI

(read

6-14

O-w

Page

——-+4+------------ +

15 !

(A410-P0/PA)

can

that

Start

start

DONE

Bit

6-28

Name

CONVERTER

conversion

not

present.

Assignment

@-——=

Bit!

o—=

IAVIS-A/AA

IAVIS-A/AA
6.5

CHANNEL

FUNCTIONAL

6.5.1

Theory

A/D

CONVERTER

(A410-P0/PA)

Page

6-15

DESCRIPTION

Operation

Figure 6-1 shows a simple block diagram of the
IAVI1S-A/AA.
Tt
is
addressed
via
the
Q-bus
address
lines.
The
board has
Switches
to select
its
device
address
and
interrupt
vector
address according
to the rules in chapter 6.3.
The 16 analogue
input channels are entered
The channels
0 to 3 are isolated by flying
a
relay
multiplexer
at
the
IAVIS-A/AA
semiconductor
analogue
multiplexer
is
non-isolated
channels.

through connector Jl.
capacitor
inputs with
version
only.
A
used
for
all
other

The selected analogue
input signal goes to the internal
analogue
bus
and
to
a digitally programmable
gain amplifier.
A sample
and hold amplifier
samples
this
signal
a
definate
time
and
Switches
to
hold-state
during the conversion cycle of the A/D
converter
(see figure 6-8).
The
ADC
is
a
12-bit
successive
approximation
analogue
to
digital
converter
ina
28 pin DIP
package.

6.5.2

Mode

Operation

Unipolar/Bipolar
The full
unipolar

Range

scale input range
0
to
+10V
or

Uni/Bi-switch
register.

Input

position

Changing

the

can

is
selectable
bipolar
+10V

input

read

range

by the

requires

by
a
input

BIP-bit
a

new

DIL-switch
voltage.

the

to
The

MOD

calibration.

ITAV1IS-A/AA

CHANNEL

A/D

Prog. Gain
Amplifier

CONVERTER

(A410-P0/PA)

Sample/Hold
Amplifier

A/D
Gain

ANA BUS

awe

Page

Xn deer IN

|
|

BIP OFF
|

GAIN 1
————

REFOUT

Uni/Bip.
Switc

Dit Py

HOLD

GAIN

Converter

Adjust

Offset
Adjust

+15

6-16

start

CSR_

-15

CONVERT

Figure

6-8:

IAVI1S-A/AA

Programmable

Gain

The

gain

can

ADC

programmed

Circuit

with

for
the
levels
1,
2,
5,
10,
20,
takes
a longer
conversion
time.

three
50,
For

(A410-P0/PA)

bits

100
and
details,

the

200.
see

The different
conversion
times
required at flying
semiconductor
multiplexers
or at higher gains
is
the IAV1IS-A hardware.
&

A higher
gain
specification.

capacitor
controlled

or
by

ITAVIS-A/AA

A/D

CHANNEL

Converter

A/D

CONVERTER

(A410-P0/PA)

6-17

Coding

The A/D converter produces
the 12-bit
(4096
which are listed in the following tables.
Unipolar
+—- - - - - !
{

Page

Operation Code
- - - - - - !
!
Scale

!
!

Range
to +10V

!
!

states)

Binary

MSB

binary

Coding

LSB

codes

+
!
!

{—-—-—-——--—----— +---------- +—-----------— +———---- - !

!
!
!
!
!
!
!
!
$--

Full

Pos.!

Zero

Bipolar

1
!
!
!
!
!

Operation

4+—-— —-— —-—!
!

!
!

!
!
!
!
!
!
!
!

+9.9976
47.5000
45.0000
+2.5000
40.0024
0.0000

111
110
100
010
000
000

111
000
000
000
000
000

!
#111!
Q00 !
000
!
000
!
O01
!
000
!
!
+

#111
000
000
000
000
000

Code

~~ -- - - - - - - -

Range
+10V

Scale

{

!Full Pos.
!
!
1
!
!
!
!
!
Zero
!
!
!
!
!
!
!
!Full Nega.!

!
!
!
!
!
f!
!
!

+FS-1LSB
+3/4 FS
+1/2 FS
+1/4 FS
+1 LSB
ZERO

+
t

+FS-1LSB
+3/4 FS
+1/2 FS
+1 LSB
ZERO
—1 LSB
-1/2 FS
-FS+1LSB
-FS

!
!
!
!
!
!
!
!
!
!

!
!

Offset
MSB

Binary

Coding
LSB

+9.9951
47.5000
+5.0000
§+0.0049
0.0000
-0.0049
-5.0000
-9.9951
-10.0000

!
!
!
!
!
!
!
!
!
!

+
!
!
!

111
111
110
100
100
O11
010
000
000

#1211
000
000
000
000
#2111
000
000
000

#111
000
000
000
000
#111
000
000
000

#111
!
000
!
000 !
O01
!
000 !
#111
!
000 !
O01
!
000
!
t

+—---------------~-- - - - - - - 5-

$—-—-—----—--—--------- - -- - - - - - - - - - - - - = +
!'Gain Bits!
!
Full Scale Range
t
mV/LSB
!
!
2.1.0
! Gain!
Unipolar
!
Bipolar
! Unipolar
! Bipolar
!
'(binary) !
!
!
!
!
!
}~-—------— +----- +———--------- +—-—-—-------- +-—-—-------- +—-——------— !
!
!
!
!
i
!
!
!
0
!
1!
0 to +10V
! +- 10V
!
2.4414
!
4.8828 !
1
!
2!
0 to +5V
! +- 5V
P
61.2207
!
2.4414 !
!
2
!
5 ! 0 to +2V
f +- 2V
f
860.4882
!
0.9765
!
!
3
!
10 ! 0 to +1V
! +- 1V
!
0.2441
!
Q.4882 !
!
4
! = § 20 ! 0 to +0.5V
! +- 0.5V
!
0.1220
!
0.2441
!
!
5
'
650 ! 0 to +0.2V
! +- 0.2V
!
0.0488
!
Q.0976
!
!
6
! 100
! 0 to +0.1V
! +- 0.1V
!
0.0244
|!
Q.0488
!
!
7
! 200
! 0 to +0.05V!
+- 0.05V
!
0.0122
!
Q.0244
!
t

$——-————-—Table

-- - - - - - - 6-3:

IAV1IS-A/AA

+
ADC

Coding

Tables

IAVIS-A/AA

6.5.3

Converter

A/D

CHANNEL

A/D

CONVERTER

(A410-P0/PA)

Page

6-18

Calibration

The IAVIS-A/AA
is
normally
shipped
and
calibrated
for
the
bipolar
input
range.
If the input range is changed to unipolar,
a new calibration
is necessary.
The calibration
is
done
with
the
diagnostic
software.
There
are two tests available,
the
"Dynamic"
and
the
"Calibration"
test.
The
latter
contains
operator
instructions
(see
the
example
in
the
diagnostic
software
listing).
Calibration

Equipment

Precision

voltage

The analogue
used.

Starting

the

reference

input

test

source

connector

with

accuracy

(see

Appendix

of
B)

0,01%
can _

Calibration

Put the precision
analogue
inputs.

voltage
reference
source at one or more of the
Use gain 1 only for the following procedures.

>10

warm-up

Bipolar

time

minutes

required.

Adjustment

Step

Offset Adjust
Enter -9.9951V
(-FS+1LSB).
Adjust the
offset
trimpot
so
that
the
printout of the conversions
is mainly on
-9.9951V or 0001 octal code.

Step

Gain Adjust
Enter +9.9902V
(FS-2LSB).
Adjust the gain
that
the
printout
of
the
conversions
+9.9902V or 7776 octal code.

trimpot_
is mainly

so
on

Unipolar

Adjustment

Step

Offset Adjust
Enter +0.0024V
(1LSB).
Adjust
the
offset
trimpot_
that
the
printout
of
the
conversion
is
mainly
+0.0024V or 0001 octal code.

so
on

Step

Gain Adjust
Enter +9.9952V
(+FS-2LSB).
Adjust the gain trimpot'
that
the
printout
of
the
conversion
is
mainly
+9.9952V or 7776 octal code.

so
on

IAVIS-A/AA

NOTE:

CHANNEL

A/D

CONVERTER

(A410-P0/PA)

Page

6-19

If the ADC
is
used
at
one
gain
only,
it
can
he
calibrated
more
precisely
if
the
steps
of
the
calibration procedure
are done in this gain.
The table
"A/D
Converter
Input Ranges"
can be used to calculate
the full
scale
range
and
the
LSB
value
for
this
calibration.

Precalibration

the

PGA

Offset

(for

factory

use

only)

Connect
the Analogue
(Pin
BB
to Pin AA)
volts +10 microvolt.
calibration.

Bus on the MUX-connector
to Analogue Ground
and adjust the voltage at TP1l with RV3 to 0
The program must be
stopped
during
this

6.5.4

And

Analogue

Input

Control

Signals

The analogue
input signals enter the board
through
male
connector
Jl.
A
flat cable or a user made
cable could be used for field connection.
At

the

IAVIS-A

channel

isolated,

and
12
channel
semiconductor
connected to input connector
Jl.
channel
semiconductor
single-ended

differential

the
50-pin
twisted pair

flying

single-ended
inputs
The
IAVIS-AA
has
inputs.

capacitor

can
only

be
16

The flying capacitor
channels
(channel
0 to 3)
at
the
IAVIS-A
are
differential
inputs.
They have one side of the generating
source connected
to the positive
(+IN)
and
the
other
side
to

negative

(-IN)

input

The single-ended
source connected
(IN)

and

shown

the

For correct
chapter
6.2

other

Figure

pins

inputs
to the
side

6-9.

shown

have one side
semiconductor
connected

electrical
analogue
"Specification".

Figure

6-10.

of
the
analogue

analogue

input

signal

user’s
analogue
multiplexer
input

return

(ANA _

RTN)

requirements,

see

ITAV1IS-A/AA

Control

CHANNEL

A/D

CONVERTER

(A410-P0/PA)

Page

6-20

Signals

The external
trigger
input signal
(EXT TRIG L) is
a
TTL
input
which generates
a conversion
start at the trailing edge of a low
pulse
if the enable
external
trigger
bit
(EET)
in
the
CSR
register
is set.
EXT TRIG L is then a wired-or
to the internal
start function.
The external
trigger enable
(EET L) is a TTL outpt'
signal.
monitors
the
EET-bit
in the SCR register.
When the EET-bit
set,
the EET L output signal has a low level.

It
is

The +5V output on
normally used for

Pin 38 is protected by a 1A pico fuse
DIGITAL manufacturing purposes only.

The signals
in
applications.

MUX-board
1s
only

MUX-boards,

the
J2

such

the

and

connector
J2
are
not
for
user
used
to connect
standard analogue

IAVI1S-C.

+---——— +—-—-—-—----—---—~------- +-----— 4+—-——-—-—-—----—-----—---- +
! I/O !
Signal
! I/O
!
Signal
!
!Conn.!

Name

f!Conn.!

Name

! Pin
!
f Pin
!
t
+----- 4+————~—-—-—-—-—-—-—-—--—--—---— +—----- +—---—--—--------------- +
f
1!
to
2!
!
rf
3
sf
f
4
!+INOQ(+Ana Inp.
Ch 0)!
!
5
!-INO(-Ana
Inp.
Ch 0)!
6
!+4IN1
!

!-IN1

!RTNS5

t'RTN7
IRTN8

!
!

1+IN2

!IN6

!IN8
!IN9

!
!

f
!
!

9
11
13

!-IN2
!
!-IN3(-Ana
Inp.
Ch 3)!
!RTN4(Ana Ret Ch 4)
!

10
12
14

%!$+IN3(+Ana Inp.
Ch 3)!
!IN4(Ana
Inp.
Ch 4)
!
#!IN5
!

!RTN6

!IN7

!
!
!
!
!

23
25
27
29
31

!
!

19
21

35
37
39

!RTNY
!RTN10
YRTNI1
!RTN12
!RTN13

‘!RTN14

%¢RTNI5(Ana
‘EET L
'EX

TRIG

Ret

15)!

! 41
!
! 43
!
! 45
!
! 47
!
!
! 49
+—----— $—-—-——--—-—-—---------Table

6-4:

IAV1S-A

Connector

20
22

!
!
!
!
!

24
26
28
30
32

!IN10
!INil
!IN12
!IN13
!INnl14

36
38

!Gnd
'$4+5V

!
{
!

%!IN15(Ana

!Gnd

Inp.

Out(Manuf.

15)!

only)!

! 42
!
! 44 3!
! 46
!
f 48
!
f 50
!
+----- +—-——-----—---—--------Jl

Assignment

A410-P0

!
!
!
!
!
!
!
+

CHANNEL

A/D

+----- +—-------------- $e
! T/O
!
Signal
!Conn.!
Name
! Pin
!
+----- $——
ee
tf 3 !
!
5 % 'w¢RTNO
(Ch 0)
!
7
!RTN1L
A
!
9
%IRTN2
N
! 11
!RTN3
A
! 13
!RTN4
L
! 15
!RTN5
O
! 17
%¢RTN6
G
! 19
‘!RTN7
! 21
‘!RTN8
R
! 23
!RTNI
E
! 25
!RTN1O
T
! 27
¢tRTN11
U
! 29
!RTN12
R
! 31
!RTN13
N
! 33
!RTN14
! 35
!RTN15
(Ch 15)
! 37
!EET L
!

6-5:

Page

1IN14

(Ch

!IN1L5

!'Gnd

'+5V

Out

15)
(Manuf.

{

! 39
‘!EX TRIG L
f 41
!
! 43 !
! 45
!
! 47
!
! 49
!
!
t
+-—--— $n
ee
Table

(A410-P0/PA)

CONVERTER

Qorrap

yHaquvwvawH

IAV1IS-A/AA

IAV1S-AA

!Gnd

ee
Connector

!
!
t
!
!
+

Assignment

A410-PA

6-21

IAVIS-A/AA

6.5.5

CHANNEL

Interfacing

Single-Ended

Inputs

Single-ended

inputs

A/D

CONVERTER

The

IAV1S-A/AA

may

two

(A410-P0/PA)

types,

grounded

Page

6-22

floating.

A grounded
input signal
is
referenced
to
the
ground
of
the
instrument
that is producing
the signal
(figure 6-9).
Since the
instrument may be located some distance
from the computer,
there
may be some voltage difference between the instrument ground and
the computer
ground.
The voltage
seen by the IAVIS-A is the sum
of
this
unwanted
ground
difference
voltage
and the desired
Signal voltage.
A floating
signal voltage
is measured with respect
that
is
not
connected
toground.
Examples
of
analogue
input are shown in figure 6-9.
The return line of a floating signal
IAVIS-A analogue
return
(ANA RTN).

must

There
1S a return connection provided
to the Input Connector
Table.

for

each

Differential

to
a
point
this type of

connected
channel.

the
Refer

Inputs

Figure 6-8 illustrates
the differential
input
mode.
The
same
noise
voltage
exists
in the power distribution ground systen,
except that the generation device ground is
connected
directly
to
the
negative
input of the receiving differential
amplifier.
Because
the instantaneous
noise voltage
is common to the + and inputs,
it is cancelled out of the final amplifier
output.

Shielded

Input

Lines

The effects of electrostatic
coupling on the input
signals
can
be
decreased by using shielded
input cables.
This is important
if the device or source has
high
impedance.
To
prevent’
the
Shield
from
developing
a
ground loop and conducting current,
connect
it to ground at the source end only.

IAVIS-A/AA

Twisted-Pair

CHANNEL

Input

A/D

CONVERTER

(A410-P0/PA)

Page

6-23

Lines

The effects
of magnetic
coupling on the
input
signals
can
be
decreased
for
floating
single-ended or differential
inputs by
using twisted-pair
input cables.
The inductive noise on the two
lines
match,
IAVIS-A.

making

the

combined

effect

With
ground-referenced,
single-ended
twisted-pair
inputs has no effect.

zero

inputs,

the

input

use

the

IAV1S-A/AA

CHANNEL

A/D

CONVERTER

(A410-P0/PA)

TAV1S-A/AA

Floating User
Instrument

Semiconductor
Input MUX
|

;

~~
(

RTN

NSA

RTN
Grounded User
Instrument
7

|_|

Figure

6-9:

Nae,

Single-Ended

Analogue

Input
IAV1S-A

Floating User
Instrument

Flying

MUX

Cap

—~

/\
QL?
-IN
+

+IN
Grounded User
Instrument

me"

—

}

onde
_—=
=

Figure

6-10:

Isolated

Differential

Input

Page

6-24

CHAPTER
IAV1IS-C/CA

7.1

GENERAL

CHANNEL

EXPANSION

MULTIPLEXER

DESCRIPTION

The IAV1IS-C/CA are expansion multiplexer
analogue
inputs
for Q-bus systems.
The

two

IAV1IS-C

board

channel

16 channel
flying capacitor multiplexer
a high degree of isolation of the field
voltage must be maintained.

board.
signals

versions

Channel

The IAV1S-C
is a
It is used where
from common mode
IAV1S-CA

(A029-P0/PA)

with

are:

Flying

Channel

boards

Cap.

Expansion

Exp.

MUX

Multiplexer

(A029-P0)

(A0Q29-PA)

The IAV1S-CA is a 16 channel
semiconductor
It is used where a large number of low cost
to be maintained
in the field.

multiplexer
board.
analogue
inputs have

Both
multiplexer
versions
have
the
same
software-and
input
connector
compatible.
IAV1S-CA can be installed in any combination

PC-board
and
are
The
IAV1S-C
and
with the IAV1S-A or

IAVIS-AA

A/D-Converters.

Up
to
seven
A/D-Converter

multiplexer
via a T-type

boards
can
be
connected
flat cable assembly.

NOTE

All

refers

general
to

the

information
IAVI1S-C,

IAVIS-CA
version,
differentiated.
The

but

same

this

also

not
applies

description

valid

for

the

explicitly
IAVIS-A.

the

IAVIS-C/CA

CHANNEL

EXPANSION

MULTIPLEXER

(A029-P0/PA)

Page

7-2

FEATURES

o
-

For
16

IAV1S-C

only

channel

true

differential,

analogue
inputs.
The
relays
are
decoupled
semiconductor
multiplexers
to

For

16
channel
single-ended
(non-isolated).

For

~
-

Input Range +10V
Up to seven IAVI1S-C’s can
converter
for expansion up

~
-

The

IAVIS-CA

both

potential

free,

from
the
increase
the

flying

analogue
bus
by
system reliability.

only
solid

state

analogue

channel

address

multiplexer

combination

be
to

bank

connected
to
128 channels.

each

IAV1S-C/CA

board

with

the

versions

IAVIS-A

can

A/D-Converter

Channel

Sts
To

the

IAVIS-A
A/O

- 6

ANA

BUS

User
Inputs

Connector

ANA

J1
Oo

Anal.

MUX

OUT

----

SEL

(1 of 16)

ANA

RTN

IAV1S-C
Version

User
Inputs

Connector
TY

+ ANA

J1
_

Flying

Cap.

(1 of 16)
+

CH.

SELECT

.
- ANA

7-1:

IAV1IS-C/CA

Simple

Block

Diagram

A/D

selectable

installed

versions.

Comp.
wo”
_
=

AaB

[3
TAVIS-CA

Address

CONVERT

Converter
_

Version

ADDR

IAV1IS-A
is

MUX
Connector

Figure

inputs

versions

by switches.
Only +5V power is used from the Q—-bus backplane.
Module
identification
readable by program.

both

capacitor

any

IAVIS-C/CA

7.2

CHANNEL

EXPANSION

MULTIPLEXER

Page

SPECIFICATION

PARAMETER

Module

1! A029-PO

IAV1S-C

IAVIS-CA

Designation

Identification

Board

Power

!
!

(this

code

or’d

Identification

the

Code)

Quad

high

One

!
!

octal

A/D-Converter

{

Prerequisite

Load

1
!

Size

1 AQ29-PA

Bus

(A029-P0/PA)

200

5 Vde
mA

T-type

(for

Bus

Load

BA200

Conductor

5 Vde

(power
|

enclosures)
Flat

Module

Cable

only)

OPERATIONAL:
!

No.

Analogue

Inp.! !

!
I

16 potential
free
Flying capacitor
inputs

Expansion
Capabilities

!
!
!
!

Conversion

Time

typ.

{

16 single-ended
inputs
(non-isolated)

Up to seven A0Q29-P0/A029-PA
multiplexer
boards may be connected
to the A410-P0/A410-PA A/D-Converter
modules
!
8,5 millisec.
! typ 40 microsec.

7-3

IAVIS-C/CA

CHANNEL

PARAMETER

EXPANSION

MULTIPLEXER

IAVIS-C

Input

Range

System

Accuracy

Input

Filter

0,03%

!
!

Isolation

Voltage

Isolation
Input

Mode

Crosstalk

Ratio

order

filter,

of f frequency
2,95 Hz

Vdc.

and

Rejection

!
!

means
Refer

Not
to

10V

0.02%

FSR

cut

N.A.

!
!

peak

!
!
!

N.A.

AC!

N.A.

!
‘

25V

across the + inp.
pins per channel
typ.
100
50 Hz

NOTE:

low

250

N.A.

First

pass

FSR

!
!

IAV1IS-CA

Inputs to Computer
Gnd 1000 Vdc or
peak AC

Protection

Common

10V

!
!
!
!

Interchannel

7-4

(A029-P0/PA)Page

!
|

max.

and

25V

+ 15V

power

ON,

OFF

!
j
{
!
f

Applicable
the

IAVIS-A/AA

A/D-Converter

specification

(A410-P0/PA)
for the accuracy at higher gains.
performance
can decrease
at gains above 10, up
several multiplexer boards are installed.

The
to 2

system
LSB if

IAVIS-C/CA

7.3

CHANNEL

EXPANSION

MULTIPLEXER

(AQ29-P0/PA) Page

7-5

INSTALLATION

7.3.1

Site

Considerations

The IAV1S-C
slot.

has

The

module

two

only

The Q-bus interrupt
on the module.

7.3.2

interface
supplied
and

connectors
with

+5V

DMA-grant

that

power

plug

from

daisy-chain

the

lines

into

Q-bus

backplane.
are

hardwired

Interconnection

Interfacing
the IAV1S-C to the
user’s
device
is
done
via_
the
50-pin
D-type
male
connector
Jl.
A flat cable or a user made
twisted pair cable could be used for field
connection.
The
pin
assignment and the signal description are shown in chapter 7.5.
General
information about the user I/O-connector
and the
physical
requirements
are given in chapter 1.4.6.
Connecting the IAV1S-C to the IAVIS-A A/D converter module
another
multiplexer
board is done via the 26-pin connector
a T-type
flat cable as shown in Figure 7-2.
The cable
is
connected
from pin A to pin A between the connectors.

or
to
J2 and
always

Note that
IAV1S-C’s
should
always
be
installed
in
the
same
backplane
where
the IAVIS-A
(A/D converter)
is located.
Special
MUX interconnection
cables should be made as short as possible.
A/D

Converter

MUX

Board

A410

Ag29

MUX
#

Board

Ap29

(LU Ls

32
A_|

w
Figure

7-2:

Connecting

the

MUX

Cable

IAV1S-C/CA

7.3.3

CHANNEL

Initial

Each IAV1S-C
multiplexer.

EXPANSION

MULTIPLEXER

(A0Q29-P0/PA)Page

7-6

Operation
has

input

channels

which

are

accessed

The channels
are addressed by the address bits CHA6 to
CHAO
in
the
IAVIS-A
A/D converter.
This is a channel
address
range of
128 decimal
channels.
Channel
0 to 15 is always used by the A/D
converter
board.
The following 7 address banks of 16 channels
each can be selected by a DIL-Switch on the IAV1S-C
board
(see
figures 7-3 and 7-4).
The selected channel
address
second bank upwards,
so that
0 to channel n is possible.

-4- FA
unused |

Figure

7-3:

/&— Channel Address Switch

CHA

| 3

banks should
correspond
from_
the
a closed address
range from channel

{

Selecting

Logical

Logical
Bank
Bank
to

Bank

9 =

OFF

% reserved
1
|
7 Banks
7

IAV1IS—-C

for

IAV1S-A

for

IAV1S -C

Channel

only

Address

IAV1S-C/CA

CHANNEL

(AQ029-P0/PA)Page

MULTIPLEXER

EXPANSION

7-7

Channel
Switch

want

A029-

Address

Maint.
LED

asic

|=
fe
—

bu we

1/0

lef

Connector

ey)

@ ed

MUX
Connector

Plastic

Filler

Pane!

ANALOG

INPUT

Figure

7-4:

IAVIS-C/CA

Physical

Layout

A029-P0/PA

IAV1S-C/CA

7.4

CHANNEL

OPERATION

7.4.1

The

AND

EXPANSION

MULTIPLEXER

(A029-P0/PA)Page

PROGRAMMING

General

IAViIS-C

the

IAV1S-C

channel

A/D

expansion

multiplexer

converter.

The IAV1S-C has
no
internal
registers.
channels
are
controlled by the register

Its
set in

converter.

add-on

(decimal).

by
may

7.4.2

The

first

Programming

The

Each IAV1S-C can be
channel addresses:
Bank

Bank

Bank
Bank
Bank

5
6
7

the
IAVIS-A.
be used for one

Ch
Ch
Ch

)

Ch
Ch
Ch

95
111
127

to
to
to

Ch
Ch

reserved

bank

(CHO

CH15)

channels

IAV1S-C

selected
15

address

address bits
range of 128

The next 7 address banks of
or more IAV1S-C MUX-boards.

80
96
112

channel

option

analogue
input
the IAVIS-A A/D

The IAV1S-C
(Board A029)
is selected by the channel
CHA6
to
CHAQ.
This
gives
a
channel
address’
used
each

7-8

)

=)
=)

)

DIL

for

switch

for

IAV1S-A

only

The

IAV1IS-C

the

IAV1S-A

the

first

module

the

can

expand

A/D

converter

this

channels

following

order.

Programming
the IAV1S-C
is done
by
the
register
set
of
the
IAVIS-A A/D converter module.
Refer to chapter
6.4.
"Operation
and Programming"
of the IAVIS-A Option Description.
When a channel
register,
the
bank is in the

address
from
CH AVAI bit
system.

a IAV1S-C
indicates

MUX board is
set
if this channel
or

in
CSR
channel

Reading the MOD registers
indicates which MUX
board
type
(MUX
board
identification
code)
is installed at the desired channel
address.
The IAVIS-C has an identification
code
of
10
octal.
This
code is OR’d to the IAVIS-A identification
code by reading
the MOD register
(result 110 octal).

IAV1IS-C/CA

7.5

CHANNEL

FUNCTIONAL

EXPANSION

MULTIPLEXER

(A0Q29-P0/PA)Page

7-9

simple block diagram of
via
the
MUX connector

the IAV1S-C.
It
J2 to the IAV1S-A

has
A/D

DESCRIPTION

7.5.1

Theory

Operation

Figure
to
be

7-1 shows a
connected

converter.

The IAV1S-C channels are selected by the
channel
CHA6 to CHAO in the CSR register of the IAVIS-A.

address

bits

The 16 analogue
input channels
are entered through connector
Jl.
The
inputs
of
the
IAV1S-C
(A029)
are flying capacitor
inputs
which are switched by a reed relay
multiplexer.
These
relays
are
additionally
decoupled
from the A/D converter
analogue bus
by semiconductor
multiplexers.
The
inputs
of
the
IAV1S-CA
(AQ29-PA)
have only semiconductor multiplexers.
The analogue
input signal
goes
to
the
analogue
converted
according
to the selected gain or input
IAV1IS-A to a 12 bit binary word.

7.5.2

Analogue

Input

bus
and
range by

is
the

Signals

The analogue
input signals enter the
module
male
connector.
A flat cable or a user made
could be used for field connection.

through
a
50-pin
twisted-pair
cable

All analogue
inputs
of
the
IAV1S-C
(A029-P0)
are
isolated
differential
inputs.
They
have
one
side
of the generating
source connected
to the positive
(+IN)
and
the
other
to
the
negative
(-IN)
input
pins.
For
correct electrical
analogue
input signal
requirements,
see chapter
7-2 "Specification".
The inputs of the IAV1S-CA are single-ended nonisolated
inputs.
They have one side of the generating
source connected
to the ANA
IN and the other
(Gnd on grounded
instruments)
to
the
ANA
RTN
pins.
Note:

Both multiplexer versions have the same pin assignment
the 16 channels
on the input connectors
Jl,
see Tables
and 7-2.
In application,
an IAVIS-CA can be installed
an

IAV1S-C

rejection

and

interchannel

isolation

from

isolation,

computer

common

Gnd

mode

not

for
7-1
for

voltage

required.

IAVIS-C/CA

CHANNEL

EXPANSION

MULTIPLEXER

(A029-P0/PA)

+—-—--------- $e
$-—--------- $n
e
- +
! I/O
! Signal
! I/O
! Signal
!
!Connector
! Name
!Connector
! Name
!
! Pin
!
! Pin
!
!
4+—-—-—-------- toe
rr
fa
rrr ree
+
!
61
!
fo
62
!
!
f
63
!
r
64
!'+IN 0 (Ch 0)
!
ee)
!-IN 0 (Ch 0)
!
6
!+IN 1
+
!
f
7
!-IN 1
f = «68
!+IN 2
A
!
a,
f{-IN 2
A
! 10
f+IN 3
N
t
! il
!-IN 3
N
! 12
'+IN 4
A
t
! 13
!-IN 4
A
! 14
'+IN 5
L
!
! 15
!-IN 5
L
! 16
!+IN 6
0
t
! 17
!-IN 6
O
! 18
!+IN 7
G
t
! 19
!-IN 7
G
! 20
!+IN 8
!
! 21
!-IN 8
! 22
I+IN 9
I
!
f 23
!-IN 9
I
1 24
!+IN 10
N
!
f 25
!-IN 10 N
! 26
!+IN 11
P
t
! 27
!—-IN 11 P
! 28
'+IN 12
U
!
! 29
!-IN 12 U
! 30
!+IN 13
T
!
! 31
!-IN 13 T
! 32
'+IN 14 S§
t
! 33
!-IN 14 S
1 34
!+IN 15 (Ch 15)!
f 35
'-IN 15 (Ch 15)!
36
!
t
! 37
!
! 38
!
!
! 39
!
! 40
t
!
! 41
t
! 42
!
!
1 43
!
1 44
!
!
! 45
!
! 46
!
t
1 47
!
! 48
!
!
!
! 50
t
!
1 49
t
!
t
t
$——----—- toe
en ee
+-——- teen
ee
+
Table

7-1:

IAV1S-C

Connector

Assignment

(A029-P0)

Page

7-10

31
33

!ANA

!ANA
!ANA

!ANA

! 37
!
! 39
!
! 41
!
! 43
!
! 45
!
! 47
!
! 49
!
!
!
+-—----— for
Table

7-2:

RTN

13
14

15(Ana

15)!

rrr
IAV1S-CA

Connector

!
!

32
34

IN
IN
IN
IN

7
8
9
10

!ANA

!ANA
!ANA

IN
IN
IN
IN

Inp

! 38
!
! 40
t
! 42
!
1 44
!
! 46
!
! 48
!
! 50
!
!
!
+—--—-—— fn ee
Pin

Assignment

@-—
@-—=
@-8
O-——=
O-F
OF
OF
O-==
0-7
O-™

11
12

14
15(Ana

eo=—m

!ANA
!ANA
!ANA
!ANA

O72

!
!

Ret.

!ANA
!ANA

18
20
22
24

3
4
5
6

O-2

RTN
RTN

26
28

!
!
!
!

IN
IN
IN
IN

O-F

RTN

10
11

!ANA
!ANA
!ANA
!ANA

8-7

6
7
8
9

10
12
14
16

O-F

RTN
RTN

RTN
RTN
RTN
RTN

!
!
1
!

O-7F

!ANA
!ANA

2
3
4
5

O-B

!
!

25
27

O-F

!
!

RTN
RTN
RTN
RTN

Ret.ch

+-—-—---4—-------- f
62
!
f
64
!ANA IN Q (Ana Inp.
Ch 0)
!
6
!ANA IN 1
t
68
!ANA IN 2

15)

O-F

!ANA
!ANA
!ANA
!ANA

(Ana

O-=

17
19
21
23

69
11
13
15

0
1

t+
$——-—---—----!
6T70 !
Signal
! Conn.!
Name
!
Pin
!

(A0Q29-PA)

O- =

!
!
!
!

!
!
!
f

RTN
RTN

7-11

O-™

fe
!
!
!ANA
!ANA

Page

O-@

+-----f 6
f
63
P
65
f
067

nnn

(A029-P0/PA)

6-7

+------ fr
rr
!
=6©I/70 ! Signal
! Conn.!
Name
!
Pin
!

MULTIPLEXER

O-=

EXPANSION

O-7

CHANNEL

0-7

e-em

IAVIS-C/CA

IAV1S-C/CA

7.5.3

CHANNEL

Interfacing

The
IAVIS-C
or
analogue
inputs
necessary to use

EXPANSION

The

MULTIPLEXER

IAVIS-CA
multiplexer
boards
as
the
IAV1S-A A/D-Converter
the multiplexers.
the
the

Refer
Refer

IAVI1S-C
IAV1S-CA

Differential
Single-Ended

Page

7-12

IAVIS-C/CA

Some guide lines how to interface
in
Chapter
6
"Interfacing
to
description.
to
to

(A029-P0/PA)

Inputs
Inputs

for
for

have
the
same
board,
which
is

analogue
inputs are
given
IAVIS-A"
in
the IAV1S-A

CHAPTER
IDV1S-D

8.1

GENERAL

FIVE

CHANNEL

8
COUNTER

(M7197-P0)

DESCRIPTION

The
IDV1S-D
counter
module
16-bit-counters,
which
can be

(M7197-P0)
programmed

consists
count
up

of
five
or down
in

binary code.
Counter
channels may be concatenated
to
form
an
effective
counter
width
of
up to 80 bits.
Both hardware
and
software gating of each counter
is available.
The count
inputs
may
be
controlled
by
either
external
signals
or
internal
programming.
Outputs of each counter provide pulses
or
levels
to
external
pins
and
may be enabled to generate
internal
interrupts
to the
Q-Bus
(e.g.
in the case of counter-overflow).
A
programmable
time
reference
may
be
used
for
external
internally timing
control and can
be
selected
as
the
count
source
for
each
counter.

All

inputs

are

available

voltage
ranges,
compatibility
for

variety

any

inputs

SW
to

to be selected,
selected.

with

industrial

opto

for
reliable
industrial
high speed lab application.

programmable
be

the

selected

rising

operating

modes

falling

edge

any

counter,

isolation
needs

allow,

active

for

signals

for

and

two

MTL

example,
L

levels

IDV1S-D

FIVE

CHANNEL

IDV1S-—-D

FEATURES

independent

external

and

5 source
are high

and 5 gate opto isolated
or low level
input range

5 source and 5
Signals at TTL

gate non-isolated
level

non-isolated

TTL

programmable

non-isolated

interrupt

—

programmable

bit

(M7197-P0)

—-

—- internal

COUNTER

counters

controlled

gating

output

capability

for

up/down

oscillator

Page

for

signals

frequency

source

internal
concatenating
to one 80-bit counter

high flexibility
in
active
signal
level

five

selecting
or edge

input

signal

(frequency)

under/overflow

counting

—-

frequency

(over/underflow)

output

counter

input signals,
which
switch selectable
high

TTL

each

binary

16-bit
gate

and

code

counters

count

sources,

8-2

IDV1IS-D

FIVE

CHANNEL

COUNTER

User

Count

Source

Ext.

(M7197-P0)

Page

8-3

Connector

1:57
SRC+1

O-

SRC-|

SRC

TTL}

Gate

1:5:
Gate+|

Gate-|

O-

Gate

TIL]

SOURCE

GATE

O-

1:5

Ne a

Int.

Fl
~
.
| CCDS

Frequency
Scaler

,
Oscillator

User

Source

1:5

Gate

1:5

————+} Input

Freq.

F1:F5

Programmable

TTL

Open.Collector ;

TTL

Open,Collector

4 bit FOUT

Divider

Multiplexer

One

Int.

Source

us|

ys,

Gate

“|

F1:F5'

Ned

Freq.
TOUT

Programmable

Source/Gate
Multiplexer

Counter

Control

Signal

ini
Mode

Gate

Counter Output
Under /Overf low

16 bit

Counter

(1£N5)

only

depicted

f
Source

Channels

Counter

five

Frequency

Lo | FouT

Connector

| Load /H01¢

Operation

from

|
the

Counter

remaining

Channels

iii |

Interrupt
Interrupt

Enable

Mask

Requests

Contro}
4

Qa-Bus

Figure

8-1:

IDViS-D

Simplified

Block

Diagram

(M7197-P0)

Output

Outputs

IDV1S-D
8.2

FIVE

CHANNEL

COUNTER

(M7197-P0)

Page

8-4

SPECIFICATION

GENERAL

Module

Designation:

M7197-P0

Identification:

300 octal
(identification
code
when reading SUR Register)

Module

Quad

Power

Size:

Requirements:

Bus

Load:

BUS

INTERFACE

high

enclosures)
9,0
1
2

DC
AC

Vde

Module

+5%

(for

BA200

900mA

Load
Loads

Addressing:

Switch selectable
over 4K word
I/O address
range;
occupies
a 4 word address

Interrupt

Vector:

Switch
000 to

Priority

Level:

BR4
(jumper
selectable
levels
5 and 6) support only position
dependent
configurations

selectable
770 octal

from

IDV1S-D

FIVE

CHANNEL

COUNTER

(M7197-P0)

Page

8-5

OPERATIONAL
Modes

(Individually programmable
for
of the five counter
channels).

Range:
0-65535
(16 bit for each counter
channel,concatenated up to 80 bits by
using additional
counter
channels).

Count:

Features:

each

up/down programmable
one of 16 input sources
is
software
selectable
for each
channel
start/stop by software
or by
external
gate signal
(active

gate

level

over

(high

—-

Time:

internal
provides
accuracy

error

and

underflow

maximum frequency of input source
on the selected external
input.
—-

low)

gate source
selectable)
overflow and underflow
detection
automatic
reload on counter

time reference
(5 MHz)
timing capability with
of +l count + timebase

(<100

PPM)

depends

start/stop by software or by external
gate signal
(level and gate source
selectable)
overflow and underflow detection
automatic
reload on counter over or
underflow

IDV1S-D

FIVE

External

CHANNEL

Input

COUNTER

isolated
GATE
1
-

Specified

Input

Low
High

Range:
Range:

Isolation

Interchannel

general
5)
for

Voltage

The
voltage
input
dedicated
switches
Chapter
8.3.3).

12
20

purpose
use aS

(active

high

24
42

at
at

to
to

Vde
Vdc

range
is
for
each

Voltage

Inputs
to
peak ac

Isolation

200

Vdc

connector,
are limited

Input

Frequency

150

KHz

further

8-2)
*

NOTE:

8-6

input
signals
(SOURCE
count source and/or gate
level):
8
7

to
to

18mA
19mA

individually
Source/Gate

However,

Max.

Page

Signals

10 opto
1 - 5,
source.

Level
Level

(M7197-P0)

The IDV1S-D has a filtered user
conform with FTZ requirements.

selectable
input
(refer

Computer

Gnd

peak

due

200

the

Vdc

I/O

by
to
or

user

both
isolation voltages
to 300 Vdc or peak ac.

for

24V

input

voltages,

I/O-connector

Connector
Electrical
Specifications:
Operation Voltage
(Isolation Voltage)
Dielectric with standing Voltage
Capacity per Filter

200
600
375

voltage

refer

(for

Figure

Vde or peak
Vdc or peak
pF + 20%

AC
AC

IDV1S-D

FIVE

CHANNEL

COUNTER

(M7197-P0)

Page

8-7

Figure
8-2 shows
the
minimum
input
pulse
duration
time
(maximum input frequency)
for both input voltage
ranges.
t

.
win

max.

Input

Frequency
(58%

(worst case)

7 +

Low Lever /

High

Range

3 4

169+

Figure

8-2:

Minimum

non-isolated
5),

isolated

Input

Level]

1pa-

Input Voltage

cycle)

5 +

duty

(KHz)

each

general

#38

(for activ

high

level)

Input

input

Pulse

signals

logical

purpose

Duration

(SOURCE

conjuction

input

Signals.

Level:

TTL

level,

Minimum Input Pulse
Duration Time:

700

(Max.

Input

7.0

MHz

External

Output

levels

Frequency:

TTL

Time

inverted

isolated

50%

one

GATE
the

duty

signal

cycle)

Signals

1 general purpose
timing
reference
signal
(FOUT),
by the Frequency Output Control
Register
(refer to
all

output

opto

inputs.

5 general
purpose output
signals
(OUT 1 - 5),
referring
corresponding
counter
overflow
output
in
order
to
special
timing signals
(pulses,
square wave,
etc.).

For

TTL

signals:

non-isolated
TTL level
activ low
open collector

to
the
generate

programmable
Figure 8-7).

IDV1S-D
8.3

FIVE

CHANNEL

COUNTER

(M7197-P0)

Page

8-8

INSTALLATION

8.3.1

Site

Considerations

The IDV1S-D has two bus interface
connectors
that
plug
into
a
Q-bus
slot.
The signals are totally compatible with the Q-bus
Specification.
The
interrupt
priority
of
the
module
is
determined
by
the
position
on
the
Bus
(position dependent
configuration).
The
closer
a
device
is
located
to
the
processor,
the higher
its priority.

8.3.2

INTERCONNECTIONS

Interfacing
the IDV1S-D to the user’s device
is done via the
50
pin D-type male connector.
A flat cable or a twisted pair cable
may be used for field connection.
The pin
assignment
and
the
Signal
description
can
be
found
in
Table
8-6
(See chapter
8.5.2).
General

information

physical

8.3.3

about

requirements

Initial

Selecting

are

the

given

user

I/O-connector

chapter

1.4.6.

and

the

Operation

the

IDV1S-D

Device

Address

1 |9

X |

Logical ® = OFF oy

OFF

sip

;Logical

Figure

]

8-3:

Selecting

IDV1S-D

6}
X

Device

e-—
<
o]SO

]

N-

#219

“<<

#12411

W—

| 14

>
—

The
device
address
is
the
I/O
address
assigned
to
the
MOD-register.
The
device
address
is
selected via a 10-pole
Switch
(Figure 8-5).
The switches allow the device
to
be
set
within
a
range
of 160000 octal
to 177770 octal.
The standard
address
range
for this
module
is
from
171400
to
171770
in
increments
of 10 octal
(Figure 8-3).

Factory configured
within Standard
Address Range
(171489 to 171779)

Address

IDV1S-D

FIVE

Selecting

CHANNEL

the

COUNTER

IDV1IS-D

(M7197-P0)

Interrupt

Vector

Page

Address

The IDV1S-D
is capable of generating one
interrupt
vector address
can be set via
8-5) within the range of 0 to 770
octal
octal.

DP; Pj

1 = ON:

Logical

OFF

so
Figure

8-4:

Selecting

the

6S4)

|
$2)

IDV1S-D

address

WwW

9/1

the

«19

and

1
p

Q
P|

Factory configured
within Standard
Vector Range
><
hr

{11

#12

that

|} 14

bits

Logica]

means

address

This

for

8-3).

(Figure

identical

interrupt vector.
The
a 6—pole
switch
(Figure
in
increments
of
10

vectors,
the vector
switches
1 to
6
(Figure
the
same
position as the address
switches
1

For standard
should
have

8-9

(499

Interrupt

to 729)

Vector

vector

8-4)
to 6
are

IDV1S—D

FIVE

CHANNEL

COUNTER

(M7197-P0)

Page

8-10

1OviS
-D

M7197
= PO

Address

M7197-

maint

Device

.-\93

1/0

1/0
Connector

Plastic

Filler

COUN:
TER

Figure

8-5:

IDV1S-D

Physical

Layout

M7197-P0

Panel

IDV1S—-D

FIVE

Selecting

the

CHANNEL

COUNTER

Interrupt

(M7197-P0)

Page

8-11

Request Level

The standard
interrupt
request level
is
4
(BIRQ4).
A
higher
request
level,
BIRQ5 or BIRQ6,
can be selected via the jumpers
BR5 or BRO
(Figure 8-5).
In addition,
the IDV1S-D should not be
installed
closer
to
the processor unit than any module with a
higher
interrupt level
than itself.
Whenever
the BIRQ4
on
the
module
is
changed
to
a higher
level,
no other modules,
which
have

the _

bus

Each isolated
input signal
(SRC
15,
Gate
15)
has
Switch dedicated to it (see Figure 8-5)
to select either
the
level or the high level
input
voltage
range
(switch
no.

one
low
1

closer

lower

the

Selecting

the

corresponds

etc.).
voltage
the low

request

level,

Voltage

Range

processor.

channel

no.

should

External

switch

installed

Isolated

no.

Inputs

channel

no.

The "OFF"
switch position selects
the high
level
input
range
(20
to 42 V).
The "ON" switch position
selects
level
input voltage
range
(12 to 24 V).

IDV1S-D
8.4

FIVE

CHANNEL

COUNTER

OPERATION

AND

PROGRAMMING

four

registers

8.4.1

For

(M7197-P0)

Page

General

operation,
fm

Address

!
!
!

171XxX0
171XxK2
171XxX4

!
!
!

are

available,

listed

below.
+

{————--———-—— 4+———————-———-—————
— - — -— +

171XxX6

Mode
Register
Status
and Command
Register
Counter
Control
Register

Interrupt

(MOD)
(SCR)
(CCR)

!
!
!

(INR)

+——————-——--—-———
- -—-——- -- -

Table

8-12

8-1:

Counter

Set

INITIALIZATION

The

INIT

MOD

and

refers

processor.

INR

initialized

INIT.

caused

one

programmed

RESET

instruction

switch

power-up

power-down

sequence

CCR

registers

(and

the

are

Initialization

Issuing

Depressing

The

order

the

occurrence
initialize

Ssubregisters,
see
has to be applied.
8.4.2.1.2).

initialization

start
of

the

SCR

Figure
For
a

and

signal

the

The

mnemonic

issued

following.

processor

the

console

8-13)
a master
reset command
detailed
description,
see

their

sequence
chapter

IDV1S-D

FIVE

8.4.1.1

Mode

The

Mode

used

its

+—-—- —- -—- —!

CHANNEL

COUNTER

test

MNEMONIC

Page

8-13

(MOD)

identification

for

(M7197-P0)

generally

code.

purposes.

used

addition,

- - - — - - Bit!

identify
LED

the

module

indication

can

= +

Function

{ --—-------—
! IDENT 7
!
to
! IDENT 0
!

+—-—--—+4+----—-—---------- - ! 15 ! Identification Bits 7 - 0
! to ! The module
is identified by theses bits
!
8 ! (read only bits).
M7197 has the code
!
! 300 octal.

!
!
!
!

LED

!
!
!
!

+—--—-—--—~--——----

If this bit is set,
a LED residing on
module will
indicate a special mode
(i.e.
test purpose)
to the user.
The LED is cleared by INIT.

- - - -

Table

MOD

8-2:

MOD

Mode

L71XX0

Figure

#13

Bit

#12

5 | 4

]

#211

| 3
2

«419

not

LED
7 R/W]

| @

jused

Read Only Bit
Read/Write
Bit
8-6:

IDV1S-D

!
!
!
!
!
t

!
!
!
t

+
Assignment

‘IDENT

the!

Mode

|
1

;
1

not

used

|
1

]

IDV1S-D

FIVE

CHANNEL

8.4.1.2

Status

The 8 bit
register:

SCR Status
commands

And

status

For

SCR

Status

COUNTER

detailed

Command

bits

and

are

Command

shown

SC
221

R/W

Read
=

a
multifunctional
writing
into this

reading.

refer

Only

Bit

Figure

8-7:

paragraph

not used
tT

Read/Write

8-14

(SCR)

1 and

see Note

when

this

wixyg

Page

and Command Register
is
are
interpreted
when

description

8.4.2.1.

(M7197-P0).

sc}

sc | sc

|Sc | Sc | Sc ]Sc
4 | 8A

|Sc | Sc

R/W

Bit

IDV1S-D

SCR

Status

and

Command

Note

The SCR
used.
read aS

Note

In order to avoid
programming
errors,
the
following
operations
are
not
allowed
for
Status
and Command
register
(SCR)
and for
the
Counter
Control
register
(CCR):
-

Write

Read
(Bit

is not cleared by INIT.
Bits
They
should
only be written
one or zero.

Byte

Instructions

Modify Write
Instructions
Set,
Bit Test,
etc.)

8 to 15
are
not
to one and may be

IDV1IS-D

FIVE

8.4.1.3

Counter

The Counter
addressing

Mode

CHANNEL

COUNTER

Control

(M7197-P0Q)

Control
register
window
referring

registers

1-5,

Load

Page

8-15

(CCR)

of
the
Counter
Module
is
an
to sixteen subordinate
registers:

registers

1-5,

Hold

registers

1-5

(one

set
of registers
for each counter
channel)
and to the Frequency
Output Control
register
(independent
for all counter
channels).
Note that the CCR is not cleared by INIT.
For detailed
8.4.2.2.

information

CCR

Control

Counter

these

registers

paragraph

p
Counter

171XX4
see

R =
R/W

refer

Note

Control

R/W

Read Only Bit
= Read/Write
Bit

Figure

8-8:

IDV1S-D

Note:

In order
to
avoid
programming
errors,
the
following
operations
are
not
allowed
for
Status
and
Command
register
(SCR)
and
for
the
Counter
Control
register
(CCR):
—-

Write

Read
(Bit

Byte

Counter

Control

Instructions

Modify Write
Instructions
Set,
Bit Test,
etc.)

IDV1S-—D

FIVE

8.4.1.4

Interrupt

MAS]

i7ixxe

CHANNEL

,' 5

LES

R/W{/not used

R =
R/W

[EN

COUNTER

(M7197-P0)

[EN | EN|EN

8-16

writing

(INR)

R/W

Page

[EN | yy

IR IR

not used

2 #1

IR | IR

R/W

Note

zero;

Read Only Bit
= Read/Write
Bit

Figure

8-9:

Note:

The
one

IDV1S-D

bits IR1 - 5 can
is not possible.

Assignment

only

written

IDV1S—-D

INR

FIVE

Interrupt

CHANNEL

COUNTER

(M7197-P0)

Page

8-17

"Interrupt Request Bits"
One of these bits is set by the high
to low transition of the corresponding
counter output signal
(OUT 1-5)
(i.e.
in

Note
the

case

that

counter

the

under/overflow).

INT

bit

corresponding

also

Enable

set.

only

Bit

set

(ENI1-5)

Note that in order to get the interrupt
functionality
for counter under/overflow
the counter output signal OUT N has to be
achieved by setting the appropriate
bits
of the counter mode
register
(CM 0 - 2,
see Figure 8-10),
i.e.
to "activate
low
OUT pulse"
(CM 0 — 2 =001).
The Interrupt
request bit can be cleared
under program control by writing to
zero
(hardwired implemented bit clear
functionality).
Writing a one has no
influence
as no cleared bit will be set.
"Interrupt Enable Bit"
These bits can be set and cleared by
program.
Only if the Enable Bit is set,
can the corresponding
IR Bit be set.
Previous

not

set

enable

counter

the

bit.

over/underflows

bit

when

setting

will

the

"Master Enable"
Setting an interrupt
request bit will
only generate an Q-Bus
interrupt
if the
Master Enable bit 1s set.
This bit is
cleared by the first interrupt generated
to the bus
(interrupt granted signal)
and has to be set again
(interrupt
service
routine)
before
further bus
interrupt
requests
can be generated.
It
has no influence
on the dedicated
channel
interrupt
request bits
(IR 1-5).
In order to ensure
that no interrupt
requests are lost,
a bus interrupt
is
generated even if an IR bit has been set
before the MAS EN bit is set.
NOTE:
Table

8-3:

INT

Bit

All

Assignment

bits

are

cleared

INIT

IDV1S—D

8.4.2

FIVE

CHANNEL

Programming

COUNTER

The

(M7197-P0)

Counter

Page

8-18

Module

Figure
8-10 is a more detailed diagram of the counter
registers
and the subordinate
registers
of the Status and Command
register
and of the Counter Control
register.

’

Mode

(MOD)

Status

and

Command

=
a

Lid

>
°

(SCR)

~' Set Data
” Command

Pointer

Control

Counter

;
(CCR)
Register

Data

Port

MUX

—t

|.
ss

| Counter

| counter

Interrupt

ya:

Counters
Load and

(INR)

1 Freq,

Figure

shown

8-10:

above,

Sub-registers

channel

plus

Diagram

the

one

all

Counter

Load,

Frequency

Subordinate

Control
Hold

Output

Sub-register,
reflected
in
the
Pointer’
command,
which
has
to be

Command
register
8.4.2.1.2).

before

Mode

Reaist

1 Hold

oad

2, 3, 4,5 Mode,
Hold Registers

Output

(CCR)

Control

CCR,
is
entered

accessing

Load

control

Reg,

Registers

and

cep

[| Couounter

1 Mode

the

refers

CCR

(see

each

a ’Set
Status

Data
and

defined
by
into
the

for

The

Paragraph

IDV1S-D

FIVE

8.4.2.1

CHANNEL

Status

8.4.2.1.1

And

Status

COUNTER

(M7197-P0)

Command

Sc
15

—

Figure

#11

#16 «9

(SCR)

Status

sc} sc | sc} scl
s|7
16/5

}

not used
8-11:

8-19

Assignment

By reading the Status and
Command
Shown in Figure 8-11 are displayed:

Page

Bit

OUT 5

the

sc | sc]
14
13
OUT 4

sc]
12

OUT 3.

bits

scl sc
11/9

OUT 2

Status

not

ouT 1 USE?

Assignments

The bits SC1-5
reflect the over/underflow output signal of
each
counter
channel
(OUTI1-5).
Note that these bits are set to one
while the corresponding output
signal
is
in
the
active
low
state.
The
state
of
these bits changes
immediately with the
change of the counter outputs.
They have a
different
function
to
the
bits
IR1-5
of
the
Interrupt
register
(INR) where an
active
state is stored until
they are written
to
zero
by
the
software

read

(or

one

cleared

zero.

INIT).

All

bits

not

used

(0,

6-15)

may

IDVIS-D

FIVE

8.4.2.1.2
Table
under
other

CHANNEL

Command

COUNTER

(M7197-P0)

Page

8-20

Interpretation

8-4 shows all the useful
commands
that
can
be
written
program
control
to the Status and Control
register.
No
codes should be used to avoid uncalculated operations.

SC{SC
71
61
QO} OO!

|SC

{SC

|SC

4SC

|SCE

|SC

COMMAND

DESCRIPTION
Pointer

O1X5)

X41

X34

X21

Set

Data

S84;

one

CCR

Subregister

1)85)1

$83)

S82!

Arm

counting

for

all

selected

counters

9);S5;}S4!S83]

S82!

Load

contents

Load

into

@}|

@|S5{S4!

$3}

S82}

Disarm

and

1485}

}S3 4 S82]

Save

S85}

{S83}

S82]

Disarm

21)

1{N4}

N24

Set

@;)

@|N4]N2)N1

@|N4/N2]N1

Pl}

2}oaqyor;

Table

8-4:

al]

Save

all

selected
all

TOUT

selected

Clear

TOUT

Step

counter

(901

bit

N (991

N 101)
N 191)

Initialisation

Command

]

Initialisation

Command

counters

N 191)

Master

counters

iyoitoif}ii

selected

counters

selected
bit

all

Reset

Summary

Five of the above listed
command
types
are
used
for
direct
software
control of the counting process and they each contain a
o-bit S field.
Each bit in the S field corresponds
to
one
of

the

five

When an S
selected

counter

channels

(Sl=Counter

S2=Counter

etc.).

corresponds
to
§
field
has

the
no

Channels.
Simultaneous
actions on multiple
counter
channels
allowed,
so a software
synchronisation
can be achieved.

are

influence),

bit is one,
the specified operation
counter
channel
(a
zero
in
the
SO

one

Note,
that the bits 8
one
for all commands
(see Figure 8-10)

command

can

influence

to 15 of the SCR register
written to the Status and

several

counter

should be set to
Command Register

IDV1S-D

Arm

FIVE

Counter,

CHANNEL

Disarm

COUNTER

(M7197-P0)

must be armed before
selected
(refer
to

the

gate

condition

When

Disarm

Load

command

the count
up in the

Disarm

valid

Out

counter
(OUT N

before

the

entered

channel

Disarm
command
to be armed
and

counter

starts.

while

number)

the

counter

will
not
be
affected
until
becomes
inactive
with
the
next

source).
This ensures
OUT N active
state.

Command is used to load the
of
the corresponding
Load
see Figure
8-10).
The Load
counter
is disarmed.

and

Disarm

immediately

sub-register

Save

If
no
chapter

that

the

counter

the

OUT N
active

never

Counter

The Load
contents
the CCR,
when the

The

must

output

active
state,
the
becomes
inactive

edge of
latches

counting
can
commence.
the
mode
description,

the
counter
starts
counting
until
the
If a gate
is selected,
the
counter
has

under/foverflow

8-21

Counter

A counter
gate
is
8.4.2.2),
occurs.

Page

Save

Counter

and

save

selected counter
with
the
register
(a sub-register
of
command should only be used

Save
the

the

CCR,

command

counter
see

will

value

Figure

disarm

into

8-10).

the

Hold

counter

and

Command

By applying the SAVE command,
the contents
of
the
appropriate
counter
channel
(as
specified
in the S field)
is transferred
into the associated hold register.
The
transfer
takes
place
without
interfering
with
any
counting
that may be underway.
This command allows an accumulated
count
to
be
preserved, _ so
that it can be read by the host at some later time.

Set

Output

The Set Output command sets the counter output signal OUT
n
in
an
active
state
(active low TTL level;
corresponding
SC bit of
the SCR register
is set).
Note that the Set Output command
can
only
be
used
if
TOUT
toggle
is selected
in the Counter Mode
register
(see Figure 8-13).

IDV1S-D

Clear

FIVE

CHANNEL

COUNTER

(M7197-P0)

Page

8-22

Output

Clear Output command clears the
OUT N
signal
in
an
inactive
state
(TTL
high
level;
the
corresponding
SC bit of the SCR
register
is cleared).
Note that the Clear
Output
command
can
only
be
used
if
TOUT
toggle
is selected
in the Counter Mode
register
(see Figure 8-13).

Step

Counter

The selected
counter
is
incremented
or
depending on its operating configuration.
take effect even on a disarmed counter.

Initialisation

Command

Initialisation

decremented
by
The Step command

Command

one
will

Both commands
should always be entered after power-up and
after
using
the
Master Reset command before
starting the programming
of the Counter Module.

Master

The

Master

reset.

Load
Mode

Reset

disarms

command
all

and Hold registers
registers.

has

the

and

enters

counters,

Following
either
a
power
Initialisation
Commands
1
command should be applied to

are

the

OUT

active

state.

same

enters

function

005400

zero

(octal)

the

power-up

the

Counter

Master

up
Or
software
reset,
and
2 should be entered.
The
all the counters
to clear any
Please

note,

that

Master

Mode,

the
Load
that

Reset

selects down counting
(all Mode
registers
are
set
to
005400
(octal)),
so
before
entering
a
Load
command to all counter
channels,
either
the Load registers have to
be
loaded
with
a
value
other than zero,
or the counter mode has to be changed to
up counting;
otherwise unerratic
errors would occur,
as zero
15
not allowed to be loaded into a down counter
(refer to paragraph
8.4.2.2 Load Register).
The Set
Data
Pointer
command
should
also
be
set to a legal value
in order to set the internal
data
pointer,
since
reset does not initiate
it.

IDV1S-D

FIVE

The command
routine
RESET

CHANNEL

COUNTER

sequence

listed

(M7197-P0)

below

Page

shows

one

possible

8-23

reset

MOV
MOV
MOV
MOV

#177777,
#177750,
#177757,
#177401,

SCR
SCR
SCR
SCR

»>Master
Reset
Initialization
Command
1
sInitialization
Command
2
;Set
Data
Pointer
to Mode

MOV

#5450,

CCR

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

#177402,
#5450,
#177403,
#5450,
#177404,
#5450,
#177405,
#5450,
#177537,

SCR
CCR
SCR
CCR
SCR
CCR
SCR
CCR
SCR

;Select
"Upcounting"
for
Channel
1
*;The
same
for
Channel
2 to
:
:
:
:
:
;
:
s;Move
all
Counter
Channels
;a legal
value

Note that an active
INIT signal on the
Reset command to the Counter module.

Q-Bus

Channel

generates

Master

IDV1S-D

Set

FIVE

Data

CHANNEL

COUNTER

(M7197-P0)

Page

Pointer

This command is used to control
the Data Port
multiplexer
Figure
8-7),
by selecting the internal
register which is
accessible
through the Counter Control
register
(CCR).
Table

8-5

shows

Command

how

use

the

Set

Data

Pointer

0
Q
0
0
0

Q
0
Q
0
0

0
0
0
1
1

Q
1
1
0
0

1
0
1
0
1

Channel
Channel
Channel
Channel
Channel

1
2
3
4
5

Mode
Mode
Mode
Mode
Mode

0
0
0
0
0

1
1
1
1
1

0
0
0
1
1

0
1
1
0
0

1
0
1
0
1

Channel
Channel
Channel
Channel
Channel

1
2
3
4
5

Load
Load
Load
Load
Load

1
1
1
1
1

0
0
0
0
0

0
0
Q
1
1

0
1
1
0
0

1
Q
1
0
1

Channel
1
Channel
2
Channel
3
Channel4
Channel
5

Hold
Hold
Hold
Hold
Hold

Frequency

Output

uSing

Data

one

X2 = Xi

Pointer

Command

the

Printer

Data

Sub-register
of
the
Counter
8.4.2.2)
is preaddressed
for
a

Control

(CCR).

(see
be

Selected CCR
Sub-register

Bits

8-5:

command.

Table

8-24

commands

listed

Control

8-6,

Table

Control
register
(CCR,
refer
to
direct
access
through
the
Counter

Note that in order to correctly address
the subordinate
register
of
the
Counter
Control
register,
the
contents
of the Data
Pointer
register have to
be
updated
immediately
before
each
access
to the Data and Mode
register.
This includes a reloading
of the Data Pointer Command even if the same subregister
in
the
Data and Mode
register
is addressed again.

IDV1S-D

8.4.2.2

FIVE

CHANNEL

Counter

COUNTER

Control

(M7/197-P0)

As already
mentioned,
each
Load
register,
a
16-bit

Page

8-25

(CCR)

counter
channel
Hold
register

consists
and
a

of a
16-bit
16-bit
Mode

register.
These
registers
and
the
Frequency
Output
Control
register are reflected
in the Data and Mode
register
(see Figure
8-7),
preaddressed by the Command and Status Register
(Set
Data
Pointer command).
Load

The Load register
is used to control
the effective period of the
general
counter.
Any 16-bit value may be written into the load
register but it is not recommended that it be loaded
with
zero
or
one if down counting
is selected
(for up counting,
it should
not be loaded with 177777).
The contents of the
Load
register
are
transferred
into the counter by the Load command
(refer to
chapter 8.4.2.1.2
"Command Interpretation").
The
contents
is
reloaded

Hold

into

the

counter

each

counter

under/overflow.

The 16-bit Hold
register
can
be
used
to
store
accumulated
counter
values
for
later
transfers
to
the
host processor.
Transfers of the counter contents
into
the
Hold
register
are
done by using the DISARM AND SAVE or the SAVE command
(see Table
8-4 Command Summary).

IDV1S-D

FIVE

Frequency

CHANNEL

Output

COUNTER

Control

(M7197-P0)

Page

8-26

The 16-bit Frequency Output Control
register
is
an
additional
register
controlling
the FOUT reference
signal which is provided
to the user cable
for external
timing control.
The bits MM4
to
MM7
of
the
Frequency Output Control
register
(see Figure 8-9)
select
between
fifteen
different
sources
(F1-F5
: internal
timing
Signal
defined
by
the
internal
5
MHz
clock,
SRC1-SRC5
: input
sources
of
the
five
counter
channels,
GATE1-GATE5
: gate
inputs
of
the
five counter
channels),
the
bits MM8 to MM11 specify the dividing
ratio for the
4-bit
FOUT
Divider and bit MM12 disables
the FOUT signal
if it is set.
After
set

power

zero

FOUT
PPP

up,

all

(FOUT

the

bits

On,

the

Time

MHz

= Divide

Reference

divided

DIVIDER —————_——

-—————_——

FOUT

by 16

GORA

SOURCE
= Fl

=
=
=
=
=

Divide
Divide
Divide
Divide
Divide

by
by
by
by
by

2
3
4
5

PZG1
PR1P
OZ1l
P1pe
Pipl

= SRC
= SRC
= SRC
= SRC
= SRC

Qlll
1992
1991
1918
1911
11@f%
11@1
1118
1111

=
=
=
=
=
=
=
=
=

Divide
Divide
Divide
Divide
Divide
Divide
Divide
Divide
Divide

by
by
by
by
by
by
by
by
by

7
8
9
18
1]
12
13
14
15

flll
1898
1f01]1
1@1@
1911
1199
1191
1118
1111

=
=
=
=
=
=
=
=
=

MM13MM12

= 5MHz
1
2
3
4
5

$11p = GATE 1

}MM14|

are

selected).

9221
Q@Z1p
@Z1l
Q1pe
P1fl

9119 = Divide by

MM15

|MM11)MM1@)|

MM9

IMM8

=|MM7 | MM6 | MM5

GATE
GATE
GATE
GATE
Fl =
F2 =
F3 =
F4 =
F5 =

2
3
4
5
5MHz
Fl «
Fl ¢
Fl +
Fl +

16
256
4,996
65,536

|MM4

|MM3

)}MM2 MM1

——

iMMQ

L——

FOUT

GATE

Q@ =

FOUT

p
should always be

written

zero

= FOUT Off

Figure

8-12:

should

always

be written

to one

should

always

Frequency

Output

written

zero

Control

Bit

Assignments

IDV1S-D

Mode

FIVE

CHANNEL

(M7197-PQ)

COUNTER

Page

The 16-bit
counting,

read/write
Channel Mode
register
controls
output
and
source
select
functions of

channel.

The counter mode of each channel
is defined
Counter Mode
register
(see Figure 8-13).

SOURCE

SELECTION

PPPP

= TC

N-1

= SRC

PPP]

SRC

6511
P1G2Z
@lgl
#1l@
@1ll

=
=
=
=
=

SRC 3
SRC 4
SRC 5
GATE 1
GATE 2

1921
1P19
191]
11

=
=
©
=

GATE
GATE
Fl =
=

4
5
5MHz

=
=

F4
F5

Fl
Fl

G218

1920

= GATE

=
=

corresponding

— COUNT CONTROL

26e

‘

+
4,996
+ 65,536

Should

always

(Note 1)

be written
&

on falling

Count

1 = Count

Down

ote

edge
~

~~...

CM15|CM14!}

@ =

to:

Ih .

® = count on rising edge

CM13CM12

|CM11

CHENG

CM8

|CM7 | CM6

|ICM5

|CM4

|CM3 | CM2

|CM1

|CMQ

GATING

CONTROL

P92 = No Gating
B21 = Active High

Level

(Note 1)

OUTPUT

192
1f1
118
111

Figure

8-13:
l.

=
=
=
=

TC N-]

Mode

Active level assignment
signal,
the
levels
inverted.
The CM5
written

The Channel
is
channel
result.

bit is
to one

@21

= Active

199
1p]
11
111

=
=
=
=

Bit

Output

LOW

P1p = OUT Toggle
$11 = Illegal

Active High Level GATE N
Active Low Level GATE N
Tlega)
Illegal

Channel

CONTROL

P22 = Inactive

f1P = Active High Level GATE N+l
911 = Active High Level GATE N-]

Notes

gating,
counter

SOURCE POLARITY
1 = count

the

the
one

]

ple ES Fl.
1118
1111

8-27

OUT

Illegal
Active HIGH
Illegal
Illegal

OUT

_
-

}

Pulse

- Pulse

Assignments

corresponds
to isolated
input
of
nonisolated
inputs
are

cleared after
when defining

power up and
should
the counter mode.

Mode
register
should only be loaded when the counter
disarmed,
otherwise
erratic counter operations may

IDV1S-D

FIVE

Output

CHANNEL

COUNTER

(M7197-P0)

Page

Control

The counter mode bits CM0 to
CM2
specify
the
(refer to Figures 8-13 and 8-14).
configuration

COUNTER
OUTPUT

—}

OUT/ or
QUT TOGGLED
SELECT

H-——»

output

control

INVERTING
—POUTN
>O-——— gut x
DRIVE
(activ low

SONTROE

TC N
INTERNAL
L____s CONNECTION To
ADJACENT

Figure

8-28

8-14:

TO STATUS
L____srecIster

COUNTER

Output

high)

Control

Logic

One available
output mode is called OUT Pulse.
The timer output
OUT
becomes
active
(low
or high may be selected)
at the next
count when the counter
is at 0001 for down
counting
or
177777
(octal)
for
up-counting.
The OUT N pulse width is defined by
the period of counting
source.
Figure 8-15
shows
this
timing
assuming
an active high source polarity,
counter armed,
counter
decrementing and a reload value of K (K is the contents
of
the
Load register and is reloaded after each counter overflow).

PULSE OUT MODE
(HERE ACTIV HIGH
PULSE

YR OIA

QO OME

SELECTED)

MODE

8-15:

Counter

Output

\e
/

QUT TOGGLED

Figure

OME

Waveforms

IDV1S-D

FIVE

CHANNEL

The other output
OUT N
to toggle
of a pulse.

COUNTER

form,
OUT N
a flip-flop

(M7197-P0)

Page

8-29

toggled,
uses the trailing edge
of
to generate an output level
instead

Note that if the reload value K is 1 for down-counting or 177777
(octal)
for
counting
up,
the
OUT N signal will drive active
regardless
of whether
the counter
is disarmed or gated off.
As
long
as
this
value
is
reloaded
by the Load register,
OUT N
remains active.
Note that the corresponding
Status
set
while
the OUT signal
is in an
is zero while the OUT signal
is in

bit of the
SCR
register
active low state,
and that
the high state.

is
it

Please
remember
that the counter
is always
in a repetition mode,
a
counter
once
armed
(and gated on) will never stop and will
always be reloaded from the Load register
on
counter
overflow
(reaching

—-

disarmed

Count

the

value

gated

0001

off.

Source

177777

(octal))

until

the

counter

Control

Bit CM3 is used to select
selected after power-up).
—-

Count

and

down

counting

(down

mode

Selection

Channel Mode bits CM8 to CM11 specify the source used
as
input
to the counter.
Bit CM12 controls
the polarity for all sources.
One of sixteen count sources can
be
selected:
five
internal
frequencies
are
available
(defined
by the 5MHz internal
time
base),
five different
input
signals
(SRC1-5)
and
five
gate
Signals

(Gate

1-5),

supplied

from

the

user

connector.

The

16th

available
input is an internal
timer-—-output signal
(TC N-1)
from
the
adjacent lower-numbered
counter
(the counter
5 output wraps
around to the counter 1 input).
This
option
allows
internal
concatenating
up
to
80 bits.
The internal TC signal provides
the inverted level of the external OUT signal
for use as _ source
(or gate)
input.

IDV1S-D

FIVE

Gating

CHANNEL

COUNTER

(M7197-P0)

Page

8-30

Control

Bits CM13 to CM15 specify the hardware
gating options:
If
"no
gating"
is selected,
the counter will proceed unconditionally as
long as armed.
A level active gate allows
counting
only
when
the
gate is in the active level.
If the gate becomes
inactive,
the counter
stops and will
start at the same
count
value
when
the gate is active again.
Up to three gate inputs are available
for one counter
(not at the same time),
but only one can be used
for

low

to the
inputs

level

active.

Note,

isolated
input
are inverted.

signal,

active

the

level

assignment

levels

corresponds

the

non-isolated

A 001 code in this field selects
the internal
timer
output
of
the adjacent
lower numbered counter as a gate
(TC N-1 always has
the opposite
level to that of the external OUT signal,
refer
to
Figure
8-14).
This
code
can
be used to generate
a counting
"window"
by the adjacent
lower numbered counter
channel
(TC5
is
wrapped around to channel
1).

8.4.2.3

Application

8.4.2.3.1

Event

Examples

Counting

The following
interrupt
to

describes
a
counter
set-up
for
the host processor
after counting a

generating
an
defined number

generate
Source l.

interrupt

been

external

pulses.

this

after

example,

five

counter

pulses

channel

have

The disarmed counter
channel
1
(e.g.
after
Sequence,
refer
to
paragraph
8.4.2.1.2)
is
loading the Channel
1 Mode register with 000441
counting of the rising edge of Source 1 with no

low

pulse

selected.

The

Load

1 _

should

counted

Master
Reset
initialised
by
(octal)
to
down
gating or active

written

then

the
channel
1
interrupt
request
is
enabled
by setting the
EN1-bit and MAS EN-bit in the
INR.
After
entering
the
load
command
for
channel
1
(177501
octal)
in
the SCR,
the Load
register value of 5 is transferred
to the counter
channel.
By
entering
the
Arm
command
for channel
1 (177441 octal)
in the
SCR,
channel
1 starts down-counting
the rising edges
of
Source
1.

After

four

pulses

from

Source

the

counter

value

reached.
With the next source edge,
instead of counting down to
zero
(no legal value
for down-counting),
the counter
reloads
the
value of the load register
(in this case 5)
and
generates
one
active
low OUT pulse
for the period of one count.
With the high
to low transition of the OUT signal
(counter underflow from
one
to five),
the IR1 bit in the Interrupt
register
(INR)
is set and

IDV1S-D

FIVE

CHANNEL

COUNTER

(M7197-PQ)

Page

8-31

an interrupt
request
1S generated
to the LSI bus.
The
counter
continues
counting
until
it
is
disarmed.
To avoid further
interrupts
on
counter
underflows,
the
counter
module
automatically clears the Master Enable bit in the INR.
However,

in the
interrupt
disarmed
and
the

service
IR1
bit

routine,
the
counter
in the
INR cleared.

8.4.2.3.2

Duration

Measurement

To allow
channel
(e.g.
5
example,

Pulse

time measurement of
can
be
set
up
to
MHz),
which is gated
the

Mode

channel

should

an
external
pulse,
one
counter
count the internal
reference
clock
by the external pulse Signal.
For
of

channel

which

counts

MHz

while the signal on Gate 2 input iS in an active high state,
has
to
be
loaded
with 105450
(octal)
and the Load register
set to
zero.
After applying the Load
and
the
Arm
command
to
this
channel,
the counter
starts up counting
immediately with the low
to high transition of the Gate 2
input.
The
counter
channel
stops
counting
when the Gate 2 input becomes
inactive
(high to
low transition of the external pulse).
The count value
(number
of
5
MHz
clock edges)
is shown in the Channel
1 Hold register
after applying either the Hold or the Hold and Disarm command to
the
counter
channel.
Note that the counter continues
counting
if further pulses on the gate
input
occur
and
if
no
Disarm
command is issued to the counter channel.
However,
before disarming the
counter
and
reading
the
count
value,
an interrupt
is required to recognize
the end of the gate
pulse
(high to low transition).
This interrupt can be generated
by uSing an additional
counter channel
(e.g.
channel
2), and by
counting the falling edges of Gate 2 input or when the system is
initialised
to
down
counting,
preloaded with 1 and interrupt
enabled on counter underflow.
Basically,
this channel
operates

the

same

manner

the

event

counting

application

described

in paragraph 8.4.2.3.1
except that a preload by writing the Load
register
to
one
is not allowed
for down counting.
Therefore,
the Load register has to be loaded with the value of two
and
a
Step
command
has
to
be
applied
between
the
Load
and Arm
commands,
stepping the counter value down from 2 to 1.
The next
active
input edge
(here the falling edge at the end of the pulse
on Gate 2) causes an underflow on channel
2 (reload to the
load
value of 2) and an interrupt
then identifies
the end of the gate
input pulse.
In response
to the interrupt,
the
host
processor
has
to
disarm
both
channels,
reading the Hold register value
after applying the Hold command to channel
1
and
getting
the
Final
result by dividing the counter
1 Hold value by 5MHz.

IDV1IS-D

FIVE

8.4.2.3.3

CHANNEL

Output

COUNTER

Signal

(M7197-P0)

Page

8-32

Generation

In addition to using
the
FOUT
signal
for
generating
output
frequencies
(defined by the Frequence Output Control Register),
any of the counter overflow outputs OUT N are able
to
generate
output
pulses
at
defined time intervals.
Counting one of the
five internal
reference
frequencies
(Fl - F5)
and
loading
the
counter
channel
with the preloaded value of ’n’
(down counting
selected)
would generate
an active high
or
active
low
output
pulse on the OUT signal
(depending on whether
the active high or
active low TOUT pulse mode
is
selected
in
the
Counter
Mode
register).

8.4.2.3.4

Frequence

Output

Generation

Frequence Generation on the FOUT signal
is
controlled
by
the
Frequence
Output
Control
register.
To get a quarz controlled
output
frequence,
one
of
the
internal
reference
frequencies
available
Fl -—- F5 should be used as FOUT SOURCE
(refer to Figure
8-12).
Due to the fact
that
the
FOUT
divider
can
only
be
programmed
to
values between 1 and 16, only a limited
range of
FOUT frequencies
is available
for the user.

8.4.2.3.5

Pulse

In addition to
output signals
of

external

user

Output
the
OUT 1

Generation

FOUT
signal,
the
- 5 can be used for

devices.

counter

counter
over/underflow
timing control purposes

channel,

preloaded

with

the

active

high

would

value
of
‘’n’
and programmed
to down counting,
would underflow
every
'n’ clock edge.
Depending
on
the
output
control
mode
defined
in
the Channel Mode register
(refer
to Figure
8-13)
on
counter

underflow,

the

OUT

signal

would

becomes

active
low for one clock cycle
(depending on whether
the active
high OUT pulse or active low OUT pulse
is selected);
e.g.
for
the
count
source
of F2=5 MHz divided by 1b and with a load of
100

(decimal),

OUT

pulse

1.6

microseconds

generated
every
160
microseconds.
In
selection
of the OUT
toggle mode for the Channel Output control,
the
level
of
the
output
is
changed every underflow,
so that an output frequency
with 50% duty cycle
is generated
(in this example with a
period
cycle of 320 microseconds).

IDV1S-D

FIVE

Please

note,

CHANNEL
that

Supported

the

8.4.2.3.6

UP/DOWN

COUNTER
only

(M7197-P0)

the

software

driver

active

for

Page

the

low

OUT

pulse

IDV1S-D.

mode

8-33
is

Counting

Normally,
up/down counting should be no problem for the
channel
module:
one counter
is initialized
for down counting and armed.
For changing count direction,
use the bit
CM3
in
the
Channel
Mode

First,

the CM3 bit has to be
again.
This
method
by software and so no

the

counter

channel

has

For an introduction
to the highly versatile use of
mode,
the
application
should
be
shown with the
controlled by the hardware
gate
(see Figure 8-16).

Gate

Input
N:

Signal

SRC

Gate

N >

Gate
Counter

|
Figure

8-16:

the
counter
up/down mode

SRC_N

SRC

disarmed,

changed and the counter has
to
be
armed
has the disadvantage
that it is controlled
accurate
gating can be simulated.

Counter

gate

level

low

up counting

Counter

N-1:

gate

level

.
high

OUT

N-1

up counting

N Module

UP/DOWN

_
Counting

Controlled

Gate-Signal

IDV1IS-D

FIVE

CHANNEL

COUNTER

In
this
application,
up-counting,
only
one
of the gate signal.
To
application

with

one

(M7197-P0)

Page

8-34

using
two
counter
channels,
both
counter
is active depending on the level
get
the
same
count
value
as
in
an

counter

working

and

down,

of the contents
of
both
counters
has
to
be
software.
The
advantage
of
this
arrangement
control
of the up/down mode by a
hardware
gate,
counts can be lost.

the

difference

calculated
by
is the direct
so
no
input

Note that there are problems when one gate edge and
one
active
input signal
edge occur at the same time,
because one input edge
may count both counters
or none,
so the
count
may
be
counted
twice
or
lost.
To avoid this problem,
the arrangement
can be
changed so that only one counter
is
gated,
the
second
should
The final
result can be calculated by subtracting
always count.
the double value of the gated counter
from
the
value
of
the
non-gated

counter.

this

case,

count

lost

because

one

counter
is always
counting and the second counter
may
get
the
raising
edge
of
the input signal or not,
so the insecurity
in
the counting value
is only one
(allowed by input and
gate
edge
at the same time)
instead of two by gating two counters.

If the
16-bit
may be
number

count value of these pseudo up/down counters exceeds’
the
range,
the counters may be concatenated up to 32-bits or
extended by
a
software
counter
(software
counts’
the
of interrupts
that occur on counter overflow).

IDV1S-D

FIVE

8.4.2.3.7

CHANNEL

COUNTER

Concatenated

(M7197-P0)

Counter

Page

8-35

Channel

Concatenated
counter
channels are
a
high
number
of events
(which
enable a high resolution
for time
generation.

typically used either
to count
exceed the 16 bit range)
or to
measurement
or
output
signal

To
simplify
concatenation,
the
counter
module
provides
an
internal
TC signal
from
the
low
order counter,
which can be
selected as count source
(or as gate control
signal)
in the high
order counter’s
Counter Mode
register.
Thus,
although any two counter
channels
can be concatenated with
external
strapping
(note the level of the TC and OUT signal,
see
Figure 8-14).
Usually,
adjacent counter
channels
are
used
to
enable
the use of this internal TC signal.
In count
up
concatenation,
both
the
high
and
low
ordered
counter’s
Load
registers
should
be cleared to zero.
The low
order counter channel will start counting from 0
and
increment
through
177777
(octal).
On the next active
source edge,
the TC
output of the low
order
counter
channel
becomes
active
and
increments
the high order counter
channel
(the low order counter
channel
reloads
Q from Load register).
This

counter

configuration

Input

Gate

Figure

8-17:

Signal

SRC

N-1

Gate

N-l

SRC

Counter

shown

Figure

8-17.

|
| =

Counter

N-1:

Module

Concatenation

up counting
Load

Reg.

counting

Load

Reg.

TC
= @

= @

Counter

IDV1S-D
8.5

CHANNEL

FUNCTIONAL

8.5.1
This

FIVE

Theory
chapter

COUNTER

Counter

Chip

8-36

Operation

provides

Counter

Page

DESCRIPTION

Channel

(M7197-P0)

module.

The

detailed
block

description

diagram,

shown

the

Figure

Five

8-15

gives a brief technical
overview of the counter
components.
The
engineering
drawing
set
should be available
to the reader
for
detailed consideration of each component described
in
the
next
paragraphs.

The kernel of the Five Channel
Counter Module
is
the
AM
9513A
System
Timing
Controller.
This VLSI
counter
chip includes
the
logic groups of counters
1-5,
8-bit Command
register,
bus buffer
and

Mux,

16-bit

Counter

Frequency

Scaler

and

the

4-bit

FOUT

Divider.
Programming of the timer chip is
done
by
using
the
data
and control port
(referring to the registers
SCR and CCR),
which consists
of 16 data bits and the
timing
control
signals
CS,

C/D,

and

WR.

The counter
chip is provided with a 5MHz clock signal,
in
order
to
get
time
measurement
capability.
The
time reference
is
generated by a 10MHz crystal
(divided by two to get 5 MHz
clock
source).
The same crystal
controls
the Read/Write
control
logic
and a Glitch
rejection logic.
Due to the fact that the OUT 1
5
signals
(output
signal of the AM 9513A corresponding
to the
counter over/underflow detection on each channel)
may
generate
Signal
spikes
when
programming
the AM9513A chip.
A synchron
implemented glitch
rejection logic is added to each OUT
signal,
in
order
not
to
generate
undesired
interrupt
request
(if
enabled).

IDV1S-D

FIVE

COUNTER

CHANNEL

(M7197-P0)
ie)

Page

8-37

OPTO
ISOLATION
FOUT

125

SOURCE

GATE 1+5

So
CLO
5MHz

FOUT

5
16-BIT COUNTER |
FREQUENCY
F 145
SCALER

OSCILLATOR

———

| 4-BIT COUNTER

BUS BUFFER V
AND MUX 9 |S

|
COUNTER
——

CHIP

——_—

“
7

COUNTER 3 LOGIC GROUP

id ——+4 OUT 3

za
=

COUNTER 1 LOGIC GROUP
~

|
abe
19MHz

INTERNAL TRI-STATE BUS
D p...15 H

_~—_—_

—_

——_—

——e

—_—

——e

SELECT [INTERRUPT ENABLE
REGISTER (INR)
|

DIVIDER

p——>

CLOCK
1QMHz
: —5MHz

IDENTIFICATION —\
CODE 7 --

MOD

CHANNEL
5 ENABLE

MASTER
)1 ENABLE

REG.

QUARTZ
1p MHz

IR 145

INTERRUPT
«
m7
REQUEST
FLIPFLOPS
(INR)

LED (7
-F
SELECT
-

4°

VECTOR
REGISTER SELECT
-

BUS TRANSCEIVER
DC 995
—

Figure

ADDRESS
SWITCHES

READ/WRITE
CONTROL LOGIC

BDIN
5

BoouT|
LST

8-18:

BDAL
Q...15
JL

IDV1S-D

Simple

ct:
11

Block

CLOCK
19MHz

| INTERRUPT CONTROL
LOGIC

arepLy

BIRO 46

\ |

BIAKI

BIAKO

BUS

Diagram

Js.
\

(7197-P0)

4
—_———

——

Ls QUT 4

!
—_—————

OUT 5

COUNTER 2 LOGIC GROUP

16-BIT MASTER
MODE REGISTER

COUNTE2 4 LOGIC GROUP

8-BIT
STATUS
REGISTER

6-BIT
3-BIT
DATA
COMMAND
| REGISTER| | POINTER

——s
KY

SELECT

COUNTER 5 LOGIC GROUP
7

rete

FOUT DIVIDER

______

OUT 2
OUT 1

IDV1S-D

FIVE

Interface

Bus

CHANNEL

COUNTER

(M7/7197-P0)

Page

8-38

Interfacing
the internal
Tri-state
bus
DQ0-15
(the
AM
9513A
counter
chip
requires
access by a Tri-state bus)
to the Q-bus
data/address
BDAL 00-15 is done by four DC0Q05
chips,
which
in
addition
compares
the bus address
to the switch selected module
address.
The interrupt vector
(switch defined)
is also provided
on the LSI bus.
Additional
read/write
control
logic
(LSI/MSI
implementation)
provides
timing control
for read/write
access to the module.
In
order to meet the AM 9513A timing
requirements,
the REPLY signal
(read/write
acknowledge)
is delayed by a clocked delay element
(implemented as part of the "Glitch Rejection"
logic).

Interrupt

Capability

Each of the five output signals OUT 1 - 5 (over/underflow signal
for
each
counter
channel)
clocks
one interrupt
request
(IR)
flipflop.
The IR flipflops
are set only
if
the
corresponding
bit
in
the interrupt enable
register
is valid.
If one or more
IR flipflops
are set,
a Q-bus
interrupt will be generated.
The
prerequisite
"Master
Enable"
bit in the interrupt
register
is
set.
The interrupt
control
logic handles
the
Q-bus
interrupt
sequence and if interrupt
is granted it resets the master enable

bit,

further

User

Signal

Each

counter

interrupts

are

disabled

until

the

interrupt

service
routine
enables
them by setting the master enable bit
again.
Every
internal
pending
interrupt
request
(one
IR
flipflop
is set) immediately generates
a Q-bus
interrupt
request
when setting the master enable bit.
It is recommended
that
the
interrupt
service
routine
scans every internal pending
interrupt
request
(INR
register)
before
enabling
new
Q-bus
interrupt
requests
(set master enable bit).

Interface
input

signal

(Source

supplied
by
a NAND Schmitt Trigger
of the non-isolated
and the isolated

Gate

gate,
a logical
conjunction
user input signal.

The opto coupler providing
isolated
input signal
is
calculated
for
a
wide
input
range,
which
has,
additionally,
two input
ranges which can be switched.
A minimum input current of
6,7mA
is
required
in
order to switch a maximum collector
current of
0,8mA,
so the maximum input voltage
is
limited
by
the
power
dissipation

0,4

watt

for

each

input

resistor.

IDV1S-D

8.5.2

FIVE

User

CHANNEL

Input

COUNTER

(M7197-P0)

Page

Signals

The IDV1S-D has a 50-pin D-type male connector
for user
A
flat
cable
or a user made twisted pair cable should
for field connection.
Table

8-6

shows

8-39

the

assignment

the

User

inputs.
be used

Connector

foo
t-te eee
$+------ +----------- +
! I/0
! Signal
!
I/0
! Signal
!
! Conn
{ Name
f Conn
! Name
!
! Pin
!
!
Pin
!
!
!
!
!
t
!
+——------- +——----—------- +—-—------- 4—-—-—-—-------- +
!
1
!SOURCE 1 +
!
2
!SOURCE 1 - !
t
3
{SOURCE 2 +
!
4
{SOURCE 2 - !
t
5
!SOURCE 3 +
t
6
!SOURCE 3 - !
!
7
!SOURCE 4 +
!
8
!SOURCE 4 - !
!
9
{SOURCE 5 +
!
10
!SOURCE 5 - !
!
11
!GATE
1 +
!
12
!GATE
1- !
t
13
{GATE
2 +
!
14
'GATE
2!
15
!GATE
3 +
!
16
!GATE
3 - !
!
!
17
!GATE
4 +
!
18
!GATE
4-!
!
19
!GATE
5 +
!
20
!GATE
5 - I
21
{GND
!
22
!GND
!
!
23
!SOURCE TTL 1 !
24
GATE TTL 1 !
!
!
25
!SOURCE TTL 2 !
26
'GATE TTL 2 !
!
27]
!SOURCE TTL 3 !
28
'GATE TTL 3 !
!
29
!SOURCE TTL 4 !
30
!'GATE TTL 4 !
!
31
{SOURCE TTL 5 !
32
!GATE TTL 5 !
!
33
{OUT 1
:
34
!OUT 2
!
t
35
!OUT 3
!
36
!OUT 4
!
t
37
!OUT 5
!
38
!FOUT
!
!
39
!GND
!
40
!GND
!
41
!
!
42
t
!
!
!
43
!
!
44
!
{
!
45
!
!
46
!
!
!
477
!
!
48
!
!
!
49
!
!
50
!
!
!
!
!
!
!
$o-- +--+-----~--- oma
+
Table

8-6

IDV1S-D

Connector

Asssignment

(M7197-P0)

APPENDIX
Q-BUS

I/O

The following
Shipping
included
in each option.

Ordering

can

done

The test equipment
shipments,
but can

is
be

MODULE

SET

OPTION

List

shows

which

option

name

not a part
ordered by

of
the

the
user

LIST

components

single

parts

are

only.

option
or
module
separately.

A-2
Page
LIST
OPTION
SET
MODULE
I/O
Q-BUS

nels
|

t
|

|
|

PELTED
|

[ye

OO}

LAAHS

{

jd.

ETEPLULELEL

Slo}

Oo],

{

Sl=| =) =] Z/2/ 2] SZ] 2
=

NOILVIHVA / ALILNVYND

yoyQauu0)

uoldg

1S8j

jnduj

sanpow

LAS
snboyeuy

AINGOW

OF!

ATLL

SNd-O

VEOOW-9Z

lz
02
61
BI
Lt
QI
Gk
rh
C}
cl

VZ00OW-D2
VO-SLAVI-GG
09-SLAVI-dG
Od-2009V-da
Vd-0lPV0-da
Od-0lPv0-da
Od-/61ZW-da
Od-S008W-ad
0d-6209W-dd
0d-9z20SW-aa

00-ONP0D-DA

sng-o

00-V1603-92

O/|

JO}UUOD jsaj| pseog CO/| [eltbiq
VO-SEAVI 10} Bulmesg
OO-SLAVI 40) buimesq
OE-SLAVI 40} Buimesg
VV-SLAY] Jo} Duimerg
OV-SLAVI Jo} Buimesg
O0-SLAGI 40} Buimerg
OO-SLAI 40} Burmeiq
O8-SLAI 40) Bulmeig
OV-SIAGI Jo} Burmesq
uondussaq

pieog XW

6
8
Ll

adAj-)

Vd-620V
Od-620V
Od-ZO009V

uolsuedxy

aINPOW! XNW uolsuedxy jauueYyD 9g}
aiInNpPOW XNW ‘dxg ‘dey
Buidj4 jauueyy 94
BINPOW J8HS@AUOD Y/q payejosy jauueyyp

Vd-OlPV

aiqeg

jJauUPUy OL

JaWaAUOH

Od-OlPV

G/yY

Q|INPOW

ainpowy Jajunog jauueyD

Zi/p

Od-L61ZW

e
Z
|

jeuUeYDs

Od-S008W
Od-6209W
0d-920SW

WLIDIG

‘ON LHVd/ ‘ON DMC

JajuN0D

ginpoyW

LNAWdINOA

ONIddlHS

INDO nding Aejey 1g 94
aINPOW jNdinQ payejos; oj}dO Ig 9}
ainpoyw jndu; payejos; oydO ug 9

NOILdIHOSAG
LSI]
NOILVYOdHOO

A-3
Page
LIST
OPTION
SET
MODULE
I/O
QO-BUS

V-LAQYI

6
AO
¢
LAAHS

NOILVIYVA / ALILNVND

SSO

(| 9}ON eas

| 8]ON 9as

woJj}
paJepso
oq

OSXH

ued)

pod

10}

oN
Jeulwsa,

oNsoubelg

sett

OOS Aq paljadans

(ddd)
OSL
Qd
IIXVAOIW
UIXVADJIW)
sJulog Op XZ
jeulWue

OSHL

OSXH

wsG'Q)

189}
SO]

JNdiInQ

LAS

+4QaxxX
+dOXX
WOW
WOW
Maso
Jo\depy

abeyoA anboyeuy
juaung = anboyeuy

SJOJD9UUOD|ISA| JO} ajqey
sojdepy
Jo}NauUoy) Sa} Ja}UN0D jauUeYD AAI
Jo}O9UUO)
JO}N9UUOD

NOI LdlWOSAd

JINGOW

O/T

SNE-O

FILL

Ed-SOVAZ «
Gd-SOVAZ »
€0-90VNZ .
GO-90VNZ «
q-LE0EH
00-Vf0103-D2
10-VSOL3-D2
VE00WN-D2
V600W-92
VVOOW-92

Ge
re
gE
FAS
Le
0€
62

82
le
92
G2
v2
€Z

ON LYVd/ ON DMG | 0

ISI] ONIddlHsS
NOILVHOdHOO LNAWdINDA TWLIDIC

APPENDIX
FIELD

For

the

IXV1l1

and

IXV1S

TEST

EQUIPMENT

industrial

I/O

module

sets,

some

equipment
is
available
for
easier checkout of the module
Circuits
in the field.
This test equipment may be used with
without
the diagnostic
tests.
The
following
equipment
will
calibration adjustment using the
-

—-

For

the

be
needed
diagnostic

digital-to-analog-converter

Digital

voltmeter

For

analog-to-digital-converter

the

High-quality

(DVM),

dc-voltage

The diagnostic programs
IxVl1l- and IxvlS-modules
Part

Number

ZYAQ5-P5
ZYA05-P3
ZNA0Q1-C5

ZNAQ1-C3

accuracy

source,

to
carry
program.

I/0
or

out

options.
0.01%

available
are:

option.
to

lOov,

from

accuracy
SDC

Name

ProceSSOr

Medium

XXDP+
XXDP+
MDM

PDP
PDP
MicroVAXII

TK50
RX50
TK50

MDM

test

MicrovVAXII

RX50

for

0.01%
testing

the

FIELD

TEST

EQUIPMENT

Page

B-2

The following
test connectors
can also be used on
IxVll-modules
when
bulkhead
panels are installed and on IxvlS-modules
(BA200
series enclosure versions)
which have only a 50 pin D-connector.
For
both
the
adaptercable
2G-E10SA-OL
has
to be used which
reconverts
from the 50 pole D-type
connector
to
the
40
pole
module
connector
standard
of
the test connectors
(see figure
below).

List

Test

Part

Number

Connectors

Test

2G-MO02A
2G-M003A
2G-MO09A
2G-MQ0OAA
2G-MO0BA

TEST

Connector

Type

Digital-I/O
test
Analog-input
test
Analog-voltage-output
test
Analog-current—-output
test
5-channel-counter
test

CONNECTOR

ADAPTER

CABLE

The
adapter
cable
2G-E10SA-OL
is
needed
to
install
the
testconnectors
(described
in
Appendix
8B) on the IxV1S module
family
or
on
IxVlil-modules
with
50-pole
male
D-connector
Bulkhead Panels.
The adapter
cable
reconverts
the
50-pole
D-connector
to
the
40-pole module
connector
standard of the test connectors.

©)

3—Peetl s
~—L

I
|

po
5

——

2822 =g/g

ofe|
| 8
0 °5
080

oe
026

028

820) | 47

= ee)

Figure

B-l:

| |

OI
‘a
i

Test

a} 8)

a
Connector

Adapter

Cable

FIELD

TEST

DIGITAL

This
Jl

The
for

EQUIPMENT

I/O

test

the

TEST

B-3

CONNECTOR

connector

digital

function
input or

Page

may

I/O

of the
output

plugged

modules

directly

M5026-P0,

the

M6029-P0

I/O

and

connector

M8005-P0.

test connector
is
automatically
configured
modules when the connector
is installed.

With output modules,
the LED’s 0 to 15 monitor
the desired
bits
in
the
modules’
output
data
register
(DAT)
and the output
Circuit.
If a bit in the DAT register
is set to "1",
the
same
LED has to light up.
With input modules,
the LED’s 0
on-board
switch
(see
figure
inputs.
Reading the input data
data pattern.
The
digital
I/0
functions
of
the
electrical
circuit

test
connector
only
checks
digital
I/O
circuits,
but
specification.

COMPONENTS
16

2G-MBB2A

CD12

a ele

——

raD6

724K6

test

module.

volt.

Digital

connector

Therefore,

=
|
|
|
|

F3
7496

I/O

Test

supplied

the

to the
Adapter Cable
of the modules
M5@26-PB, M6~29-PP

and M8Q@5-P¢

|
|
|

qb 15)

The

principal
the whole

ARRANGEMENT

q O08!

B-2:

the
not

LED's

Figure

to 15 can
be
switched
by
the
B-1)
for even inputs and for odd
register
should
give
the
same

I/O

Connector

with

circuits

+5Vdc

are

from _

only

the

checked

testing
with

FIELD

TEST

ANALOGUE

EQUIPMENT
INPUT

Page

TEST

CONNECTOR

This test connector may be used for the analogue
A410-PQ0
and
AO29-PO0
(and
its
variations)
to
channels with an external
calibration
source.
There are 3 pins on the connector
figure B-2),
where the calibration

COMPONENTS
,Even/Odd

Analogue

Input

Channels

IN EVEN.

ANA

IN 900

[BA

J3
ANA RIN 2

__]
|

ofw2 }0

|
|

o{W 1 }o

—» to

the

Adapter

|
|
|

Figure

2G-MPP3A

“Analogue

Return

B-3:

VW UU

for

Analogue

all

Input

channels.

Test

Cable

of the modules
A41Q-P2 and Af29-PZ

input
modules
supply the 16

printed
circuit
board
source
can be connected.

ARRANGEMENT

/|
ANA

B-4

Connector

(see

FIELD

TEST

ANALOGUE

There are
A6007-P0.
a digital

EQUIPMENT

OUTPUT

TEST

B-5

CONNECTORS

two test connectors
for
the
These connectors may be used
voltmeter
for module checkout

The voltage
output
0 to 10V output.

Page

test

analogue
output
module
for easier
connection of
or calibration.

connector

has

used

check

the

The current output test connector
0 to 20mA or 4 to 20mA outputs.

has

used

check

the

NOTE

The four
analogue
outputs
can
only
be
calibrated
and
used for one of the three
output
ranges:
either
for 0 to +10V,
0 to
20mA or 4 to 20mA.

FIELD

TEST

EQUIPMENT

Page

Voltage

Output

Test

Connector

2G-MPPIA
(p

+19V)

ANA

OUT

ANA

OJT 6416

——

CH
9D @

]

the

Adapter Cable

|
|

—

ANA OUT CH 2 6

(ANA

the

A6fB7-PP

module

ANA RETURN ©

a
vvuU

Current

Output

Test

Connector

2G-MPPAA
(@

-10V

or -2 to -10V)

ANA

OUT

CHD

ANA

OUT

Gnd)

ANA OUT CH2 ©

(ANA

€

—

, | J

ANA OUT

CH 3 ©

ANA

RETURN ©

VV UU

Load

Figure

B-4:

Analogue

Output

Resistors

Test

500

ohm,

0,01%

Connectors

to the

Adapter Cable

of the- module
A6QB7-PP

B-6

FIELD

TEST

EQUIPMENT

FIVE

CHANNEL

This

test

Page

COUNTER

connector

TEST
is

Counter
Module
diagnostic
tests.

B-/7

CONNECTOR

intended

(M7197-P0 )

used

order

for

the

Five

perform

Channel

loopback

Note that the test connector
is a prerequisite
for
testing
the
counter
module
with the diagnostic;
without
the test connector
plug,
only a sub-set of the module
functionality can be tested.
For correct operation,
the loopback
connector
with an external voltage of 21V to 24V.

has

NOTE

The counter
test connector
installed
upside
down.
connector
PC-board must be

2G-M0O0BA
has
to
The
"SIDE2"
of
pointing upwards.

COMPONENTS ARRANGEMENT
VIEW ON SIDE 1

BLACK

———
esae

Mpp

|
|

|
t

EXT
on

J <

GNO

|
2

EXT
RED

_/
kc

Figure

B-5:

12 m

Five

Channel

21-24V

1
|

Counter

Test

Connector

be
the

supplied

Q-BUS
I/0-MODULES
IDV1S-A, IDV1IS-B, IDV1S-C,IDV1S-D,
IAVIS-A,IAVIS-AA,
IAV1S-B,IAVIS-C,
IAVIS-CA
MODULES

READER'S

COMMENTS

YG—C04UC-00

(c)Maintenance
(d)Programming

Did

manual

meet

your

Please
rate the manual on
(Circle your
response.)
Accuracy
Clarity
Completeness
Table of Contents,
Index
Illustrations,
examples
Overall
ease of use

your

Yes(

the

following

Excellent

) No(

categories.

Good

Fair

Poor

What

things

did

you

most

about

this

manual?

What

things

did

you

least

about

this

manual?

Please

list

and

describe

Page

Description/Location

Name
Street
City
State/Country
Postal
(ZIP)
Code

THANK

Please

errors
of

you

specify.)

) Why?

any

found

the

Error

Job Title
Company
Department
Telephone Number
Date

YOU

send

FOR

to:

YOUR

COMMENTS

Digital

AND

improve

response.)

(e)Training
(f)Other
(Please

needs?

SUGGESTIONS.

Equipment

GmbH

Dept.:
CSS/Sustaining
Freischuetzstr.
91
D-8000 Muenchen 81

Unacceptable
RPP PP

the

(Circle

efforts

NNNNN WH

(a)Installation
(b)Operation/use

manual?

W Ww

this

use

our

you

did

How

W101
UT 1

help

PRP

Your comments
and suggestions
will
the quality of our publications.

manual.

SOS 000

Computer Special Systems