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EK-78032-UG-PRE

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Document:	MicroVAX 78032 32-Bit Central Processing Unit User's Guide
Order Number:	EK-78032-UG
Revision:	PRE
Pages:	408
Original Filename:

OCR Text

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iCro

EK-78032-UG-PRE

78032

ral Processing Uni
User's Guide

B
EK-78032-UG-PRE

MicroVAX 78032

32-Bit Central Processing Unit
User's Guide

PRELIMINARY

Preliminary, June 1985

Copyrlght Gl 1985 by Dlgxtal Equipment Corporation
All

nghts

Reserved

The material in this document is for
subject to change without notice.

informational purposes and

Digital Equipment Corporation assumes no
errors which may appear i1n this manual.

The

following

Digital
DEC
DECnet

trademarks of

Logo

DECUS
DECsystem-10
DECSYSTEM-20

DECwriter
DIBOL

are

Edusystem
LAS

”

|
|

Equipment

MINC-11
OMNIBUS
CS/8

TOPS-10
TOPS-20
ULTRIX
|

PDP
-

PDT

RSTS
RSX

for

Corporation:

MASSBUS
MicroVAX
Mi1croVMS

Digital

responsibility

UNIBUS
VAKX
VAXZLN

- MS
7T

"8032
781372

:s
any

CONTENTS
.

CHAPTER

INTRODUCTION

1.1
1.2

GENERAL

ARCHITECTURE

DESCRIPTION
FUNCTIONAL OVERVIEW

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1-1
1-4

2.1
INTRODUCTION .
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2.2
DATA TYPES . .
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2.2.1
BYte. v i it e e e e e e e e e e e e e e e el 2=2
2.2.2
Word . . . . . .« . .
c v e e e e e e e e e . 22
2.2.3
Longword . & & v v 4 4 e
e e e e e e e e e e e . 2-3
2.2.4
Quadword . .
.
« ele
e e e e s e e e 2 e . 2-4
2.2.5
Variable Length th Fie ld
e o e e s e e o o o . 2-4
2.2.6
Character String . . . . v v v v v v « o« o« o« « . 2-6
2.2.7
Floating Point .
N
2.2.7.1
F floating
« e
e
2.2.7.2
D floating . . .
c e+ e
e e e e e e « & . . 2-8
2.2.7.3
G _floating . . . . v 0 h e 0 e e e e e e
.. 29
2.3
REGISTERS
. . . .
R
. .
2-10
2.3.1
Non-Priviledged Reglster
6
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. .
2-10
2.3.1.1
General Registers
. . . . . .
e+« e« « .
2-10
2.3.1.2
Processor -Status Word
.
e e e e e .
212
2.3.2
System Registers . . .
e e e
..
2-12
2.3.2.1
System Control Block Base R@glster
e e e .
2-12
2.3.2.2
Process Control Block Base Regxster
c e o« .
2-12
2.3.2.3
Interrupt Registers
. . . . . . . . . . . .
2-14
2.3.2.4
Memory Management Registers
. . . . . .. .
2-14
2.3.2.5
Processor Status Longword
e
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2-14
2.3.3
Processor Registers
. .
.
« « « « .
2-16
2.3.3.1
MicroVAX 78032 CPU Spec1f1c Reglsters
. . .
2-19
2.3.3.1.1
Interval Clock Control And Status Register
2.3.3.1.2

(ICCS)

Console

SAVPSL)

Saved

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Reglsters

.
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2.4
MEMORY MANAGEMENT
. . . . ¢ v v v v
2.4.1
Virtual Address Space
. . . . . .
2.4.1.1
Process SpPace
. . ¢ v ¢ v 4 o «
2.4.1.2
System Space . . . . . ¢ . 4 .
2.4.1.3
‘Virtual Address Fermat e e e e
2.4.1.4
Page Protection
. . . .. . .
2.4.2
Memory Management Control
« e
2.4.3
Access Control .
. . . .
« ¢ e e
2.4.3.1
Processor Modes
. . . . . . . .
2.4.3.2
Protection Code
. . ¢v & v v v
2.4.3.3
Length Violation . . .
c + e«
2.4.3.4
Access Control Violation
e+
2.4.3.5
Access Across A Page Boundary
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SAVPC

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2-24
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2-26
2-26
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2-28

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CONTENTS

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Address Translation
. . . . .
2.4.4
2-28
Page Table Entry (PTE) . . .
.
2.4.4.1
2-29
2.4.4.1
Protection Check Before Valld Che”k
2-30
2.4.4.1
Changes To Page Table Entries
.
2-30
2.4.4.2
System Space Address Translation.. .
2-30
Process Space Address Translation
2.4.4.3
2-33
2.4.4.3
PO Region Address Translation
2-33
Pl Region Address Translation
.
.
.
.
.
2.4.4.3
2-34
2.4.5
Translation Buffer . . . .
2-36
.
Translation Buffer Invalldate Slngle Reglster 2-37
2.4.5.1
2.4.5.2
Translation Buffer Invalidate All Register
2-38
Memory Management Faults .
2.4.6
.
.
.
2-38
.
EXCEPTIONS AND INTERRUPTS
. .
.
2.5
2-39
2.5.1
Processor Interrupt Priority Levels (IPL)
2-38
2.5.2
Processor StatuUS .«
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2.5.3
Interrupts .
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2.5.3.1
2-41
2.5.3.2
Device Interrupts -- Levels 10-17 (Hex)
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2-41
2.5.3.3
Software Generated Interrupts -- Levels 01
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Reserved Operand Exception . .
Instruction Execution Exceptions

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Emulated Instruction Fault . .
- Extended Function Fault
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Breakpoint Fault . . . . « « .
Tracing
. .
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System Fallure Exceptions
. . .
Kernel Stack Not Valid Abort .
Interrupt Stack Not Valid Halt

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Reserved Addressing Mode Fault

Memory Management Exceptions . .
Access Control Violation Fault
Translation Not Valid Fault
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Exceptions . . . .
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Arithmetic Traps/?aults
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Integer Overflow Trap . . .
Integer Divide By Zero Trap
Subscript Range Trap . . . .
Floating Overflow Fault
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Floating Divide By Zero Fault
Floating Underflow Fault . . .

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Software Interrupt Request Register
Interrupt Priority Level Register
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(Hex)

Interrupt

oo OrOorOrOTOToOTOTOTOTOTOYOTOTONUOYUYT
AN

Urgent Interrupts - Levels 18- 1F (Hex)

2-42
2-42
2-42
2-42
2-43
2-44
2-44
2-46
2-47
2-48
2-48
2-48
2-48
2-48
2-49
2-50
2-50
2-51
2-51
2-51
2-51
2-51
2-51
- 2-52
2-52
2-52
2-53
2-53
2-53

' CONTENTS (Cont)

2.5.4.6.3

2.5.8

CHAPTER

Check

And Memory Read/Write

Abort
. . . 4 4 4 0 e .
Contrast Between Exceptions And
Serialization Of Exceptions And
Initiate Exception Or Interrupt

2.5.5
2.5.6
2.5.7

Machine

~ System Control Block

(SCB)

« + + ¢
Interrumts
Interrupts
. . . « .

2.5.8.1
2.5.8.2
2.6
2.6.1
2.6.2
2.6.3
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.8.1
2.8.2

System Control Block Base (SCBB)
VECLOTS
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PROCESS STRUCTURE
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Process Context
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Process Structure Interrupts c o o
STACKS . . .
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Stack Resxdency
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Stack Alignment
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~Stack Status Bits
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Accessing Stack Registers
. . . .
RESTART PROCESS
. . . ¢ ¢ ¢ v v ¢« ¢«
Console Entry Protocol . . . ¢« v v
Console Exit Protocol . . . . . .

INSTRUCTION

SET

4.1

INTRODUCTION

4.1.1

4.1.2
4.1.3
4.2
4.3
4.3
4.5
4.6
3.7

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2-61
2-63
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2-67
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2-69
2-69
2-70
2-71
2-72
2-73

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FORMAT AND ADDRESSING MODES

3.1
INSTRUCTION FORMAT e
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3.1.1
Assembler Radix Notation . . . .
3.1.2
Operating Code . . . & v v 4 4 ¢
3.1.3
Operand TYPE .+ « « « « o« o o o «
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-ADDRESSING MODES . . . .
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General Mode Addressxng
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- General Register Address Modes
3.2.1.2
Program Counter Addressing . .
3.2.2
Branch Addressing
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CHAPTER

Error

Operati:on Description Notation
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INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS
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ADDRESS INSTRUCTIONS . . .
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VARIABLE LENGTH BIT FIELD INSTRUCTIONS «
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CONTROL INSTRUCTIONS . ¢ ¢ v ¢
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PROCEDURE CALL INSTRUCTIONS
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MISCELLANEOUS INSTRUCTIONS
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3-2
3-3
3-3
3-6
3-6
3-35
3-44

4&-1

4-2

. 4-3
. 4-6
4-33
%-35
4-43
4-64
1-72

CONTENTS (Cont)

4.8

QUEUE

INSTRUCTIONS

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4-83

4-83
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4-111
4-124
4-124
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4-125
4-125
4-125
1-127

4-151

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4.8.1
Absolute Queues
. . .
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. . . . .
4.8.2
Self-relative Queues . . .
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4.9
CHARACTER STRING INSTRUCTIONS
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OPERATING SYSTEM SUPPORT INSTRUC“IONS
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FLOATING POINT INSTRUCTIONS
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Representation .
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Non-zero Floating Point Numbers
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Floating Point Zero
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Reserved Operands
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ACCUTECY « &
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Instruction Descriptions .
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EMULATED INSTRUCTIONS WITH MICROCODE ASSIST

CHAPTER 5

CHAPTER

BUS TRANSACTIONS

5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.3.1
5.3.2
5.3.3
5.4
5.5
5.5.1
5.5.2
5.5.2.1
5.5.2.2

INTRODUCTION .
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BUS CYCLES . . « v v ¢ o v ¢ o o o o
CPU Read Cycle . . . ¢ ¢ ¢ ¢ v v v
CPU Write Cycle
. . .
e o o o
Interrupt Acknowledge Cycle
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DMA Cycle
. . .
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EXTERNAL PROCESSOR CYCLES
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External Processor Read Cycle
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External Processor Response Cycle
External Processor Write Cycle . .
MEMORY ACCESS PROTOCOL &+ v ¢ v 4 4«
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EXTERNAL PROCESSOR PROTOCOLS . . . .
FPU Protocol . . . « ¢ v v ¢« ¢« ¢« v
Register Protocol
. . . v v v v «
Read From Processor Register
c
Write To Processor Register
. .

6.1
6.2
6.3

INTRODUCTION . .
DATA/ADDRES
BUS
S
BUS CONTROL
. .

6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8

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DESCRIPTION

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Address Strobe (X§)
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Data Strobe (DS) . . . . .
Byte Masks (BM<3: 53) . e
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Ready (RDY)
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Error (ERR)
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External

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DC CHARACTERISTICS . . . . . . . .

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Interval Timer (INTTIM
General Interrupts (IR

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INTERRUPTS

7.7

ERRORS

BUS

MEMORY SUBSYSTEM

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7.5
7.6

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HALTING THE PROCESSOR

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RESET/POWERUP

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7.3

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INTRODUCTION
POWER

INTERFACING

SUMMARY

PIN DESCRIPTION

6.10

.
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6.8.2
6.9

Power (vdd)
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Ground (Vss) . . . . . .
Back Bias Generator (Vbb)

CLOCKS

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(DMR)

(DMG)

SUppLIES

DMA Request

- DMA Grant

APPENDIX A

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Interval Timer (fNTTIM)

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7.7.2
7.7.3

Interrupt Request (IRQ&3:
Power Fail (PWRFL)
.

Clock In (CLKI)
Clock Out (CLKO)
TEST (TEST)
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7.7.1

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7.2

(CS<2:O»)

INTERRUPT CONTROL

7.1

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DMA CONTROL

Control Status

6.6
6.6.
6.6.
6.7
6.7.1
6.7.2
6.7.3
6.8
6.8.1

6.5,

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SYSTEM CONTROL i
Reset fifigfiT)
Halt (HALT)

6.4
6.4.1
6.4.2
6.4.3
6.5
6.5.
6.5.

CONTENTS (Cont)

Cjcle,

A-12

CONTENTS

APPENDIX B
B® l
B.2
B.3
B.4

INSTRUCTION SET SUMMARY

INTRODUCTION » » L] . ~
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INSTRUCTION SUMMARY
. . .
FLOATING POINT INSTRUCTION

C.1l
C.2

C.3

APPENDIX

’d

SUMMARY

'EMULATED INSTRUCTION WITH MICROCODE ASSIST
SUWARY

APPENDIX C

(Cont)

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CONSOLE ENTRY
IWTRODUCTION

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AND EXIT
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ROUTINES

CONSOLE ENTRY AND EXIT ROUTINE
MEMORY MANAGEMENT SIMULATION .

MECHANICAL

SPECIFICATIONS

D.1

PACKAGING

FIGURES

xTitle

Interval Clock and Control Status Reglster.
Console Saved Reglsters .
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Virtual

Address

Space

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L4
L

NOWUERENDHF
OO NOWATUTIdE = LWONDNJOTWN

NN NN NN
P OO
DND |
{
ro
|
|
'T
|
R
N
R
NN

Processor Status Word . .
Processor Status Longword

MicroVAX 78032 CPU Proarammlng Model

L
&
L

*®

‘s

]

L4
&

Longword Data Type. . . .
Quadword Data Type. . . .
Variable Length Bit Field
Variable Length Bit Field Specifier .
Variable Length Bit Field Across Reglsters.
Character String Data Type
F_floating Data Type. . . . » . s e *
D _floating Data Type.
G floatlng Data Type. . .

’”

.
.

.
«

.
.

Byte Data Type.
Word Data Type.

Bus Connections . .
MicroVAX 78032 CPU Blmck Dlaqramu

Address Space . . . . . .

Page

1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17

No.

Figure

FIGURES:

3-26

‘

&
*

[
]
.
[
L
L

L4
*
.
L4
&
&

(R2)[R5]

Increment Word.

CLRL (R4)+[R5] Clear Longword . . . :
11X

*
*
L]
*
.
L
.
*
L
*
&
L4
.

0w
.

»
.

L4
&

”

Mode Operand Specifier Farmat
MOVB B~5(R4),3"3(R3) Move Byte.
.
Displacement Deferred Mode Operand Specxfler
INCW @B~5(R4) Increment Word.
Index Mode Operand Specifier Format .

INCW

Longword.

Move

MOVL S~49,R4
stplacement

A TN

G
_floating Operand

£R

MOVL(R1l)+,R2 Move Longword.
Autoincrement Deferred Operand Specmfzer Forma
MOVW @(R1l)+,R2 Move Word.
Autodecrement Mode Operand Specifier Format
MOVL -(R3),R4 Move Longword .
Literal Mode Operand Specifier Fmrmat
Short Literal Format. . . .
Examples of Short Literals. .
R
Floating Literal., . . .
Ffloating and D_
flmatan Operand

Autoincrement Mode Operand Specxfzer Format

Far ma

&
*
*

ctt.{"l’ttvfiatoqc

*
.

Clear Quadword
.

ff s

(R4)

Opcode Formats.. . . . . .
Register Mode Operand Spefiifie ol
MOVW R1,R2 Move Word
'
Reglst@r DeferredMode Op@rand Sp@cxfm@r

CLRQ

Stack Selection . . . . . . .
MicroVAX Instruction: Fmrmat

Process Control Block Base (PCIB) Reqlst
Process Control Block (PCB)
.
AST Level Reglster. A AN

&
e
&

&
s

‘

@ *

*
&

[]

Page Table Entry. . . . . .
System Mapping Registers. .
System Virtual to physlcal Address Translatl on
P0 Region Mapping Regxsters
PO Virtual to Physxcal Address Tramslatzon.
Pl Region Mapping Registers
Pl Virtual to Physical Address Translatxon,
Translation Buffer Invalidate Single Register
Translation Buffer
I‘nvalidate All Register. .
Software Interrupt Summary Register * .
|
Software Interrupt Request Register
Interrupt Priority LevelRegister .
Stack After Arithmetic Exception.
Fault Parameter Block . . .
~Machine Check Stack Parameters.
- System Control Block Base Register.

[

‘
L]

‘~

‘.

. .

£4

I B1

N NN N RN -t
(O8N
b b
WO
WN
un = W N
O W
~J oy U W N !
o
|
29

&n&uauugugau&ggb&gflgzauéunstaua&u&ngggnxtaaj

2- 38

2-31
2-32
2-33
2-34
2-35
2-36
2-37

2-30

2-27
2-28
2-29

Address

2~2%

2-26

Virtual

Map Enable Register

2-18

2-19
- 2-20
2-21
2=22
- 2-23
2-24

Title

*’I};

Figure No.

(Cont)

Format

3-29

FIGURES

(Cont)

Title

Page

»
»
TM
TM
.
TM

TM
.
*
*
*
@
«
*
*
-

L]
L4

.
.

L4
*
.

‘—rt
'Y

L
&

»
Y

*
*

.
*

&
&

&
*

L]
]

L]
*
.

L]
"

[]
&

T
Y
Y Y
|
[
i
=
|

[]
L

*
.

EQ'Q

R
N

o
o
o
o

&
*

CPU Read TIimMINg . + + « o o « =
CPU Write Timing. . . .« « .+ .
DMA Timing. . .
‘
External Processor Read/?espwnse Tlmlng
X

]
&
L
[&
*

[

[]

.
&
%
&
.
[]
*

128KB"¢

i}':t*:l?xlxléfii

CLKI Tlmxmg

Pin‘Assignments*'.

Supply Decoupling . .
Memory Subsystem with 32KB PROM ad
Power

MicroVAX 78032

External Processor Write Cycle. .
MicroVAX 78032 Memory Organization
Read From Processor Regilister.
. .
Write To Processor Register . .
.

3-30

B
B
T
AR DR DU D
B
R

DMA Cycle . « v v v v v v o
1
External Processor Read/ReSpmnse Cycle
-

c&;ittt&k{;&ttt

Character String Control Block. . .
Stack After Change Mode Instruction
Emulated Instruction Argument List.
MicroVAX 78032 Bus Connections. . .
MicroVAX 78032 Microcycle . .
CPU Read Bus Cycle. . . . . . .
CPU Write Bus Cycle . . . . .

U
WN
O

A
I
!

ol
el S o

[

&
L

~i
LI

Relative D&f@rr@d Mode Operand Speczfxer F

MOVL @~X2050,R2 Move Longword . . .
Branch Addressing Operand Specifier Frormat
. .
. .
Entry Mask.
Stack Frame . . . . . . » . .
CALLG Stack Frame .
.
CALLS Stack Frame .
.
Queue
Header.
Empty
Queue With Address B Insarted
Queue With Address Inserted at Head
Queue With Address Inserted at Tail
Queue With Address B Removed. . . .
Empty Queue .
e
.
Queue With Address B Inserted TS S
|
Queue With Address A Inserted at Head
Queue With Address C Inserted at Tail . .

t‘#&QC!‘##GQiQQQ!

Format.
. . . .
Format.
. . ‘

Longword.

Move

I~#6,R4

Absolute Mmde Operand Specifier
"CLRL 2#°674533 Clear Longword .
RelativeMode Operand Specifier
.
MOVL ~X2016,R4 Move Longword.

3-33
3-34
3-35

Immediate Mode Operand Specifier Format

MOVL

.
AP
e
.

3-31
3-32

Clear Word . . . . .
CLRL a#“XlOl2[R2} Clear Mongwmrd
CLRQ 2(R1)[R3] Clear Quadword . .
MOVL @~X14(R1)[R3],R5 Move Lohgword

CLRW#
- (R2)[R4]

CLRW @(R4)+[R5] Clear Word. . . « « « o « . .

3-27
3-28
3-29
3-30

Figure No.

FIGURES (Cont)
Title

O
.

A-15

A-13

A
. .

Surface Mmunt
Socket Mount.

Pin CERQUAD,
Pin CERQUAD,

68
68

: Refle‘t Tlmlngw

';;External Processor Write/Command Timing

N -~

(fifliy

A
-6

Page

- Figure No.

D-3

TABLES

Title

Page
-

&
&
&
&
@&
&€
&
8
&
&
&

s
&
&€
&
&
*
&
=

TM
-

L
.

®
-

L
L

*
.

L]
*®

&
&

L
L

$
L
[

|
L]
L

L]
-

L4
&

[]
&
L

Timing.

A-10
A-12-

Reset

o e

External Processor Cycle T: mlng

6-11

Control

Access

3=-35

Memory

MicroVAX 78032 Pin Summary.
. .
"CLKI Timing
.
CPU Read Cycle, CPU erte Cycle~Tmxng
DMA Cycle Timing. . . . . . .
. R

2-72

Instruction Operation Symbols .

Addressing Modes.

.
e

.
w

.
e

Program Counter

. .
‘e

2-13
2-15
=17
2=

;

Restart Codes . . v v + v v & o + .
Summary of General Register Addressmng Mmdes
Summary of Program Counter Addressing Mmdes

Floating Literals . .
Index Mode Addressxng

.
L
L4
L
L4
»
*
&
*
&

*
-

&
L

]

*
L

*
*

L]
&

L
-

D@scrxptlmn of Process Control Block.
Stack Pointer Selection .. . . . . .
Stack Pointer Registers . . . .. . .

Internal Processor Registers. . . . .
Virtual Address Bit. Description . .
‘Map Enable Register Bit Descrlptxmnr
Protection Codes. . .« « v v « . .
Page Table Entry Bit Description.
Interrupt Priority Levels . .
. . . .
Summary of Exceptions . . . . . . . .
Arithmetic Exception Type Codes . . .
Fault Parameter Word Bit Descriptions
System Control Block Vectors. . . . .

Descriptions

Bit

Longword

[]

Status

[]

Processor

Processor Status Word Bit D@ficriptians

T
W

R
N

) RN
PR
O0IE WWWWWNN

RN RN RN RO R NN N

Table No.

||
R
UV

A-14

PREFACE

This user's guide is intended
to
familiarize
the
reader
with the
hardware
and
software
characteristics
of the MicroVAX 78032 32-bit
Central Processing Unit chip.
It 1s assumed that the reader
has
had
experience
with microprocessor
design.
Familiarity
with
the VAX
archltecture will also be helpful.
o
e
Chapter 1, Introduction - Provides
brief
functional
description
of
microproceesor,

the reader
with
an
overview
and
the MicroVAX 78032 CPU single chip
|

Chapter 2, Architecture - Describes the
implementation
of
the
VAX
architecture
by
the MicroVAX
78032
CPU.
It covers such areas as:
data types, registers, memory management, stacks,
interrupts,
faults
and @xceptzons, and the restart process.

Chapter 3 Instruction Formats
and
Addresglng
Modes Provides
a
detailed
description
of the instruction formats and addr9531ng modes
used by the MicroVAX 78032 CPU.
Chapter 4, Instruction Set - Describes
the
instruction set
for the
MicroVAX
78032 CPU and its companion floating point unit (FPU).
This
chapter also describes the emulation process for the VAX
instructions
that are not directly implemented in the CPU or its cmmpanlon FPU.

Chapter 5, Bus Transactlmns - Describes the
various
bus
cycles
and
external processor/register protocols used by the MicroVAX 78032 CPU,.

Chapter 6,
78032

Pin Description - Descrzb@s the functxon of

each

MicroVAX

CPU pin.

Chapter 7,

Interfacing - Provides

interfacing external

logic

some

'intrdductory information

the Micr@VAx 78032 CPU

Appendix A, DC and AC Characteristics
and d@talled timing information.

- Provides power,

environmental,

Appendix B, Instruction Set Summary - Provides a summary
of
the
VAX
instructions
implemented
by
the
MicroVAX
78032 CPU and 78132 FPU.
This appendix also summarizes the 1instructions that recelive
emulation
a551stance

from

the CPU.

‘]Apmendlx C, Consmle Entry and Exit Routines exit and memory management emulation routines,

Appendix D, Mechanical Specifications for the

two different packages

that

X11

Sample

Provides

console

package

entry,

dimensions

the MicroVAX 78032 CPU comes

1in.

- CHAPTE1
R

T
ION
INTRODUC
1.1

GENERAL DESCRIPTION

The MicroVAX 78032 Central Prmcessxng Unit
32- bxt mlcrwprmcessmrw

(CPU)

1is

a single

Its principal desxgn f@atures'are:

e
-

Instruction set, data type, and memory
with the VAX-11 supermmnicomput@r.

4 Gbyte virtual address space,

management

1 Gbyte physical

chip

compatibility

address space.

@ 32-bit internal and external data paths.
e

High performance

@ On

chip,

tightly

'~ management.

1integrated,
e

On chip clock generator and

Simple external interface.

The MicroVAX 78032 CPU

architecture.

demand

paged

virtual

interrupt controller.

implements a compatible subset

Visible machine

memory

state

consists

the

VAX-11

sixteen general

purpose registers,
a processor status word, and
eighteen
privileged
registers.
The
1instruction
set
architecture supports
all
304
native-mode VAX instructions.
Of these, 175 are
implemented
in
the
MicroVAX 78032
CPU, and 70 in the MicroVAX 78132 Floating Point Unit

(FPU).
The remaining 59 instructions may be implemented via
software
emulation, of which 27 are assisted
by ‘microcode. All VAX data types

~are supported.

Of these, six areimplemented
in

the

MicroVAX

78032

CPU:
byte, word, longword, and quadword integers; variable length bit
fields; and variable length character stringa,w Three are
*mpl@mented
in
the
MicrovAX 78132 FPU:
single precision, double precision, and
extended double precision floating point numbers.
The remaining
data
tyvpes are supported via software emulation.
|

INTRODUCTION

The memory
management
architecture
memory
management.
Virtual
memory

provides
demand
paged
virtual
is ¢ Gbyte, divided into four 1

Gbyte regions of 2**21 512 byte
pages
each:
PO,
Pl,
system,
reserved (Figure
1-1).
The PO and Pl reglons are intended for

and
user

programs and are mapped through double level page tables, that is, the
page
tables
reside in system virtual address space and can be paged.
The system region 1s used for
the
operating
system
and
1is
mapped
through
a
single
level
page table.
Four hierarchical access modes

(kernel, executive,

most
only,

space

privileged.
or no access

is 1 Gbyte,

Input/Output

(I/0)

supervisor,

zZach 512
from each

divided

user)

are provided,

into 512 Mbyte

devices

other

for memory,

special

VIRTUAL ADDRESS SPACE

uses

and 512 Mbyte

(Figure

kernel

the

for

1-1),.

PHYSICAL ADDRESS SPACE

00000000

MEMORY

REGION

with

byte page can be set for read/write, read
of
the
four
modes.
Physical
address

SPACE
b

]

1FFFFFFF

20000000

1/0
-

SPACE

IFFFFFFF

[}

40000000

3FFFFFFF

P1
REGION

TFFFFEFF
80000000
SYSTEM
REGION

BFFFFFFF

1 C0000000

RESERVED

REGION

FFFFFFF
MA 10415

Figure 1-1

Address'Space'

The MicroVAX 78032
CPU
provides
a
simple
and efficient
external
interface
which
minimizes
support devices
without impacrting
performance (Figure 1-2).
The primary
communications
path
is the
muitiplexed
Data
and
Address Bus (DAL<31:00>).
This bus is used zo
transmit address from and data to and from the
MicroVAX 78032
CPU.

The

Address

information

(BM<3:0>)

Control

Strobe

for

control

Status

information

(AS)

addresses

byte

(CS<2:0>)

and

data

and Data Strobe (DS)

and

data,

selection

within

lines and Write

(WR)

direction.

Bus

1-2

signals provide

respectively,

the

The

Byte

timing

Masks

32-bit
DAL bus.

signal

provide

cycles

are

The

status

terminated

INTRODUCT
ION
~asynchronously when external logic asserts either Ready (RDY) or Error
(ERR).
The
timing
of read
and
write bus cycles permit standard
dynamic

RAMs

prefezch

be interfaced

buffer,

‘instruction
operations.

together

fetches

and

data

<cycle

slips.

four-byte

writes

write

with

permit

Ra<30>

ROV
|
DS

b———m-

——

—
AS

DAL<31:00> K

gfss

BA<31:.00> )

MicroVAX 78032

CENTRAL PROCESSING

N DATA

UNIT

TRANSCEIVERS

, {

WB_ >
DBE

- /| MicrovAax 78132
¥

—

»|

RESET

***ZZ:Z::q CLKI

£5<2:0> |yt

CLKOF:::TMM

FLOATING

—

EPS

—

CS<2.0>

CLKO

MR.12666

Figure

1-2

Bus Connections
1-3

other
|

ERR |

INTERRUPT | —| PWRFL
|

elght-byte

buffer,

overlapped

[ —| FACT

‘

'without

witn

INTRCDUCT
ION
1.2

FUNCTIONAL OVERVIEW

The MicroVAX 78032 CPU utilizes a pipelined,
implementation.
e

The data
general

The principal

are

microprogrammed

shown

Figure

32-bit

ALU

barrel

shifter

for

arithmetic

and

for

logical

and

bit

shifts

operations,

field

and

operations.

32-bir

The
memory
registers

management
wunit
(M
Box)
contains
three
address
(two
for
data,
one
for instructions),
a
fully
associative, eight
entry,
ctranslation
buffer
wutilizing
least
recently used (LRU) replacement,
and access checking logic.

The

instruction decode logic
(I Box)

The

DAL

and

three

Interface

rotators,

the

instruction

consists

external

consist
of
s

memory

operations

and specifier

data.

read

and

write
logic,

microprogram,

which

The

Store

The Microsequencer contains
subroutine return stack, and

the
the

The IPLA auxilia
ROMry
is an

instruction lookup table

Control

19 bits

e The

contains

the

1600 39-bit microwords.

information

Interrupt

logic

for

each

control

microprogram
PC,
microprogram
conditional microbranch logic.

implemented

synchronizes

and

The Clock logic generates
double

frequency

the

internal

source.

<containing

instruction.

priéritizesu

external
1interrupt
inputs
(halt,
power
fail,
inputs for four levels of vectored interrupts).

external

PLAs.

control

sequencer,

buffer.

consists of

éightwbyte

decode

and the write

32-birt

1-3.

path (E Box) contains the
16
architecturally-specified
registers,
20
scratch
registers
used by microcode, a

prefetch buffer

sections

the

seven

clock

tick,
u

and

phase clocks

from

Essentially
all
sections of
the = MicroVAX
78032
CPU
operate
independently
and concurrently.
While the E Box is executing a data
path
operation,
the Control
Store
ls
accessing
the
next
microinstruction
the
; Microsequencer is calculating the address of the
following microinstruction;
the M Box can be translating
an
address:
the
I
Box
can
be
decoding an instruction
or operand specifier and
prefetching

‘initiating

further

instruction

completing

data;

external

the

access.

DAL

Interface

can

INTRODUCTION
4

NTERRUPT

|
PRIORITY
LEVEL
———'E::"
M SYNCHRONIZER

TH
DATAPA
BUS

?flfifiET: H'fiéfix

\BOX

-l P

ALU WITH

)

ROTATOR |

NPUT

ADDRESS

| CONTROL ~

RONISTRUCTION
ON
m;mmsmuc

CONTROL STORE

e—ef (eNGTH REGISTERS |
'

| LENGTH COMPARATOR

OORESS REGISTERS

(TMA

NoorroL

| wite INCREMENTER |

TBAWBUS

TRANSLATION
BUFFER: TAGS
PAGE TABLE

}

ENTRIES

—

| VIRTUAL

| ADDRESS BUS

L PHYSICAL

yAaooResseus

MmuxoRriver

Figure 1-3

’

CLOCK GENERATOR

‘ EXTERNAL CONTROLS
AND STROBES

MicroVAX 78032 CPU Block Diagram
|
(8]

memawfi |

DRIVERS|

y ¢/

~
1 MUX
—
L \_ T
INTERNA
DATA AND

%fi“
5B
, &%

AW
g%

LATCHES
WITH INPUT
TLA
hd

‘

;

]

- | { OUTPU
orivers

BARREL SHIFTER

ADDER

EBOX
CONTROL

LATCH AND
1 BIT SHIFT

mmgp .

It
MUX

| (ADDRESS BUS

SCRATCH PADS

- | tADDRESS

_LATCH

GPRS AND

WRITE

4ADDRESS
STACK

WADDRESS -

Riakcii-. 200
3 BUS|

w
i
| «TRAP ORBOX |

EBOX INPUT MUX

[ JUMP nADDRESS!

MICROSEQUENCER
CONTROL

Moty

,‘

[

¥N‘$TRU(’:WON
’ Y 'LT 1 DECODE

/ENTRY-POINT tADDRESSES
uBRANCH OFFSET!

‘41%‘5?%67;0& |
| 0ECODE LOGIC §

ALIGNMENT MUX

INTERRUPT§ | PRIORITIZER |powerrail
CONTROL | |

,
" READ DATA LATCH

TOP

e HALT

AND

INTERRUPT

|2
3

VCHA@TER 2m o
ARCHITECTURE

2.1

INTRODUCTION

This chapter describes the MitroVAx 78032 Central

implementation
of the VAX architecture.
the following major s@mtlans*
|
®

Prmcesaing‘,Unit’s

This chapter
|

is divided
|
|

into

Data Types

e Registers
e

Memory

Management

Exceptions

and

Interrupts

° §PrQCst Structure
u.'Staaks

e Restart Process |
The MicroVAX 78032 CPU instruction
discussed in Chapter
3 and Chapter

2.2

DATA TYPES

The

MicroVAX

78032

CPU

supports

formats
¢,

and
|

nine

data

instruction

types:

set

byte,

are

word,

longword,
quadword,
character string, variable length bit field,
through the aompanlmn lermvax 7!132 FPU, F flma*xng, D floating,
G floatxng
|

and
and

ARCHITECTURE

2.2.1

Byte

A byte 1s 8 contiguous bits starting
The bits are numbered from the right

on an addressable bvte
0 through 7, Figure 2-1

boundary.

[

BYTE

A
[

|
MR-11634

Figure 2-1

Byte Data Type

A
byte
1s
specified
by
arithmetically,
a
byte
1is
increasing significance going

1ts
address
A.
a
twos
complement
0 through 6 and bit

unsigned 1nteger with bits of

increasing

value

When
interpreted
integer with bits of
7 the sign bit.
The

of
the
integer
1is
1in
the
range -128 through 127.
For the
purposes of addition, subtraction, and comparison, VAX-1ll instructions
also
provide
direct support
for the interpretation of a byte as an
7.

The

2.2.2

value

the

unsigned

integer

significance going

the

rang
0 through
e

through
255.

Word

A word is 2 contiguous bytes starting on an arbitrary
byte boundary.
The bits are numbered from the right 0 through 15, Figure 2-2.

WORD

;

00
(A

N
MR-11638%

Figure 2-2

Word Data Type

ARCHITECTURE

A word 1is specified by
1its
address
A,
the
address
of
the
byte
containing
bit
0.
When lnterpreted arlthmetlcally, a word 1s a twos
complement integer
with
bits
of increasing significance ~going
@
]wthrough
l4 and .bit 15 the sign bit.
The value
of the integer is in
" the range -32,768 through
32,767.
For
the
purposes of
addition,
subtraction
and
comparison,
VAX-ll instructions also provide direct
support for the interpretation of a word as an unsigned
integer
with
bits
of 1ncreasxng sanlfxcance going O through 15,
The value of the
~unsigned integer is in the range 0 through 65,535.

'2.2.3

Longword

A longword is
4
boundary.
2-3.

The

contiguous bytes

bits are

starting
on an

numbered ‘rmm

the

arbltrary ‘byte

rlght 0 through

31,

Figure

LONGWORD
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrror
a

MR-116386

Figure

2-3

Longword Data Type

A longword is specified by its address A,
the address
of
the
byte
containing
bit
0.
When 1nterpreted arzthm@txcally, a longwmrd is a
twos complement irteger with bits of increasing significance
going
O

~ through 30
~the range

and

bit

“addition, '~subtract10n,
provide direct

unsigned

the sign bit.

-2,147,483,648 through

The value of

2,147,483, 647

and comparison,

‘For

VAX- llu

support for the 1nt@rpretatlmn

the

integer

the

purposes

instructions
longword

also
an

integer with bits of 1ncreaszng $lgm1f1cance going 0 through
31.
The value of the unsigned integer
1is
in
the
range
0
through
4,294,967,295.

2-3

ARCHITECTURE

2.2.4

Quadward,

A quadword is
boundary.
2-4.,

The

contiguous

bltS are

bytes

numbered

startlnq on

from the

an *arbltrary byte

rlght

uhrough

63, Figure

QUADWORD

31
AN
I

00
A

R
T

D
T

A
T

D
I

D
B

D
N

DN DO A

TR N

TR U

NNWG MY N

NN O

I
T

[rrrrrorrrrrrrrrr

TSN

T A N0 e A

SV MR R T O

avg

32
MR-11637

Flgure

2~4

Quadword Data Type

A quadword is speclfled by its address A,

the

address

the

byte

containing
bit 0.
When znrerpreted armthm@tlcally, a8 quadword is a
twos complement 1nteqer with bits of increasing 51gn1f1cance
going
O
through
62
and bit 63 the sign bit.
The value of the integer is in
the range -2**63 to 2**63-1.
|
|

2.2.5

Variable

Length Bit

Field

A variable bit field
is 0 to 32 contiguous
bits located arbitrarily
with respect to byte boundaries.
A variable bit field is specified by
3 attributes: the address A of a byte, a bit position P which is the
starting location of the field with respect to bit 0 of the byte at A,
and a size S of the field.
The
specification of
a
bit field
is
xndlcated
by the following where the field is the shaded area, Figure
2-5.

VARIABLE LENGTH BIT FIELD

P45 P+S-1

PP1_

FFFFFFFFFFFFFFFFFFFFFFFFFFFFF|

S-1

00
A

00
M#-11639

Figure

2-5

Variable
2-4

Length

Bit

Field

ARCHITECTUR!

For bit strings in memory, the position is in the range -2**31 through

2**31-1
and is conveniently viewed as a signed 29-bit byte offset and
a 3mbit bitmwithin~byte fl@ld Flgure 2~6~

O
8

I I
:

N N

=T
O N

TI1 T 17T
BYTE OFFSET

0302

SN
NR
|
O

N B
I

T
BWB

MP-13396

Figure 2-6

Variable Length Bit Field Specifier

The sign extended 29-bit byte offset is added to the address A and the
resulting
address
specifies the byte in which the field begins.
The
3-bit bit-within-byte field encodes the starting position
(0
through
7)
of
the
field
within that
byte. The VAX-11 field instructions
provide direct support for the interpretation of a field as
a
signed
or unsigned integer.
When 1nt@rpret@d as a signed integer, it is twos
complement with bits of increasing significance going 0
through
§-2;
bit
S-1
1s
the
sign bit.
When interpreted as an unsigned 1nteger,
bits

1nqreasan

has a value

sanlfxcance

1identi callv equal

go from 0

S-1.

field of

size

A varxamle bit fleld may be antalned in 1 to 5 bytes,

From a

management
point of view only the minimum number of aligned
necessary to contain the field are actually ref@ranced

memory

longwords

For bit flelds in reqxsters, the pmfimtlmn is in the ~range
0
through
31.
The
position operand specifies the starting position (0 through
31) of the field in
the
register.
A variable bit
field
may
be
contained
in
2 registers if the sum of position and size exceeds 32,
~Figure 2-7.

P P-1

P+S

P+S-1
MR-13387

Figure 2-7

Variable Length Bit Field Across Registers

- ARCHITECTURE

2.2.6 Character String
A character string 1s a contiguous sequence
of
character string

bytes

in memory.

the address A of the
is specified by two attributes:
the string, and the length L of
the
string
in
bytes.

first byte of
The format of a character string 1s shown in Figure
of a string is'in the range 0 through 65,535.

2-8.

CHARACTER STRING

‘A

Figure 2-8

A+

00
A+l
|

| Mfi..flma

Character String Data Type

2-6

The

length

ARCHITECTURE

Flmating Point

2.2.7

,‘The MicroVAX 78032 CPU supports tnhe

f@ll@Wlng

floating

pmxnt

~ types through the MicroVAX 78132 Flmatlng Poxnt Unit.

2.2.7.1

F floating

Figure

boundary.
2-9,.

F_FLOATING
15
14
ofe

The

bits

are

arbitrary

labeled from the rxght 0 through 31

data

An F _floating datum is 4 cmntlgumms bytes‘ starting
byte

FRACTION

1A+2

Figure 2%9

F _floating Data Type

An F_floating datum is specified by its address A, the address of
the
byte
containing bit
0.
The
form
of
an F flmatlnq datum 1s sign
magnitude with bit 15 the sign bit, bits 14:7
an
excess
128
binary
- exponent, and bits 6:0 and 31:16 a normalized 24-bit fraction with the
redundant most szgnxflcant fraction bit not repres@nted
Within
the
~ fraction,
bits of increasing significance go from 16 through 31 and 0
~through
6. The 8-bit exponent field encodes the values 0 throuqh 255.
~An exponent
value of 0
together with a sign bit of 0, is taken to

~indicate that the F_floating
datum has a value of 0.

~of

Expanent

values

1 through 255 1nd1cate true blsary @xpmn@nts of -127 through +127.

'An exponent value of 0, tmgather with a sign bit of 1, is
taken
as
reserved.
Floating
pmlnt instructions processing a reserved operand,
take a reserved operand fault. The value of an F _floating datum is in

the

approximate

range .29*10**-38 through 1.7*10**38.

of an F_floating datum

typically 7 decimal dmgxts.

approximately

one

part

1in

The precision
2**23,

1i.e.,

, ARCHITECTURE
2 2 7.2

D_floating

A D_floating datum is 8 contiguous bytes starting on an arbxtrary byte
boundary.

The

2-10.

bits

are

labeled from the right 0 thrwugh 63,

D_FLOATING
15

|
R

]

|
i

07
|

o
i

‘

FRACTION

)

|
i

EXPONENT

Figure

Flgure 210

MR-11841

Dflmatlnq Data Type

A Dfloatxng datum is specified by its address A, the address of the
‘byte containing bit 0. The form of a D floating datum is identical to

‘an F_floating datum except

fraction

bits.

go 48 through 63,

for

additional

Within the fraction,
32

through 47, 16 through 31,

‘exponent
conventions, and approxzmate range of
Dfloating asF floatan
The precxslmn
of

approxxmately one part

in 2**55,

i.e.,

2-8

low significance

bits of 1ncrea51ng significance
and

through 6.

The

values is the same for
D floating datum fzs

typlcally 16 decxmal dlglts.

ARCHITECTUR!

2.2.7.3

G_floating

A G_floating datum is 8 contiguous bytes starting on an arbitrarv byte
boundary.

The

2-11.

bits

are labeled from the right 0 through 63,
|

14
|

G_FLOATING
|
!

EXPONENT

FRACTION

(A+2

FRACTION

:A+4

FRACTION
]

]

}

|
A

|
|

:A+6

63
‘

Figure

48
:

MR-11642

Figure 2-11 'Gmfloating Data Type
A G_floating

datum

specified

its

address

the

address

the

byte
containing
bit
0.
The
form
of
a
G floating datum is sign
magnitude with bit 15 the sign bit, bits 14:4 an
excess
1024
binary
exponent, and bits 3:0 and 63:16 a normalized 53-bit fraction with the

redundant most

significant fraction bit

not

represented.

Within

the

fraction, bits of increasing significance go 48 through 63, 32 through
47, 16 through 31, and 0 through 3.
The ll-bit exponent field encodes
the
values
0
through
2047.
An exponent value of 0 together with a
- sign bit of 0, is taken to indicate that the G floating
datum
has
a
value
of
0.
Exponent values of 1 through 2047 indicate true binary
exponents of -1023 through +1023.
An exponent value
of
0,
together
with
a
sign
bit
of
1,
1is
taken
as
reserved.
Floating
point
instructions processing a reserved operand
take
'a
reserved
operand
fault.
The
value
of a G_floating datum is in the approximate range
.56*10**-308 through .9*10**308.
The precision of a G floating
datum
ls approximately one part in 2**52, i.e., typically 15 decimal digits.

ARCHITECTURE

2.3

REGISTERS

The MicroVAX 78032 CPU's register set 1s divided into two sections, as
seen
1n Figure 2-12.
The.general registers and Processor Status Word

(PSW)

are

2.3.1

Non-Priviledged Registers

registers

accessible

are

reserved

non-privileged

for

system

software.

The non-privileged registers consist of
reglsters and the processor status word

2.3.1,1
The

sixteen
(PSW).

sixteen

32-bit

general

storage,

registers.

Four

the

frame

registers,

accumulators,

these

registers

pointer,

the

general

purpose

have

base

R15,

specific

stack

can

registers,

uses:

pointer,

and

used
as

the

for

index

argument

the program

Argument
contains
argument

Pointer - R12 is
the
argument
pointer
(AP).
The
the base address of a software data structure called
list, which is maintained for procedure calls.

2. Frame Pointer- R13 is the frame pointer (FP).
~

remaining

32-bit

through

counter.

the

General Registérs -

temporary

pointer,

software;

the base
address
of
a software data structure
frame, which is maintained for procedure calls¢

The

called

AP
the

contains
the

stack

Stack Pointer - R1l14 1s the stack pointer (SP)
The
SP
contains
the
address of the top of the processor defined stack.
There are
five
stack
pointers,
one
for
each
operating
mode
(kernel,
executive,
supervisor, and user) of the processor and one for use
by
the
system
when
handling
interrupts.
The
stack
pointer
currently
1n
wuse
1is
determined
by
the
operating mode of the
processor.
The operating mode i1s selected
by
the
current
mode
bits and the IS bit of the Processor Status Longword (PSL).

Program Counter

contains

A registers
with

the

special
exception

accumulator,

R15

address

1is

the

program

the

instruction

function does
of

the

temporary

not

limit

PC.

The

general,
however,
most
software
argument pointer, or frame
pointer
designated.

does

for

counter

its

PC
as

not

byte

use

cannot
an

(PC).

that
Dbe

1index

wuse

purposes

the

The

program.

function,

wused

stack

other

In
pointer,

than

those

ARCHITECTURE

When a register is used to contain data, the data
1is
stored
1in
the
same
format
that
1t
would
be
stored in memory.
If a quadword or
double floating datum 1s stored in a register, it is
actually
stored

in two adjacent registers, Rn and R[n+l}.

Writing a byte or a word to

a register writes only bits <7:0>
or bits
<15:0>
remaining bits of the register are unaffected.

APPLICATIONS

respectively,
|

PROGRAMMING

GENERAL REGISTERS

l’

“

KsSP

‘R4

ESP

SsP

R10

L
SYSTEM

PCBB

Psw

PROGRAMMING

PROCESS CONTROL REGISTERS

sCsB

PC
PROCESSOR STATUS WORD

R11_

[

_R8
RO

USP

INTERRUPT REGISTERS

SIRR

]

[

SISR__

]

MEMORY MANAGEMENT REGISTERS

peR

]

PILR

sen

]

MAPEN

]

[

'SLR

__Isp

]
|

PROCESSOR STATUS LONGWORD
L[|

psw

MR-10414

Figure

2-12

MicroVAX

78032

CPU Programming

Model

the

ARCHITECTURE

2.3.1.2 Processor

Status

Word

The Processor Status Word (PSW) contains the condition codes and
trap
enable
flags
for
the
MicroVAX
78032
CPU,.
The
PSW
1is
the
non-privileged portion of the Processor Status
Longword
(PSL).
The
lower
16
bits
of the PSL contain the PSW.
The format of the PSW is
"shown 1n Figure 2-13 and the function of
each
bit
1is
described
in
Table 2-1.

mBZ

Figure

2.3.2

2-13

Processor

.PSW

Status Word

System Registers

The system registers are processor (privileged) registers for
system
software
for
process
control,
interrupt
control,
management mapping and control, and processor status.

2.3.2.1

System Control

Block

Base

use
by
memory

The

System Control Block Base register (SCBB)
contains
the
physical
address
of
the
system
control
block (SCB).
The SCB contains the

vectors

the

SCB

2.3.2.2
The

for servicing interrupts
refer to Section 2.5.8.

Process

Control

Block

and

Base

exceptions.

For

a
|

description

Process Control Block Base register (PCBB) contains
the
physical
address
of
the
Process
Control
Block (PCB).
The PCB contains the
hardware context of the current process.
For a description of the PCB
refer to Section 2.6.

ARCHITECTURE

Table

2-1

Processor

Status

Word Bit

Descriptions

Descrxptlon
‘mmwmmmm

m»mmmmmm“mmmmmwwmmmmmmmmwwmwwmmwmmmmmwmmmwmmmmmm‘mmmmmmwmmmmmw

- Must

Be Zero

(MBZ).

Trap Enable Flags - these bits are used
to occur under special circumstances.

DV - Decimal overflow trap enable;
software
in the

emulation of

cause

traps

used by emulation
decimal

instructions.

FU -

Floating underflow fault enable; when set, this
bit causes
a floating underflow fault after an
instruction that produced a floating result too
small in magnitude to be represented.

Integer overflow trap enable; when set, this bit
causes an integer overflow trap after an instruction that produced an integer result that could

not

correctly represented

T - Trace bit; when set,
to occur

03:00

after

Condition Codes

the

space

bits

the next

contain

1nstructlon,

information on

result of the last processor arithmetic or
operation.
The bits are setas follows:

N =1
Z =1
V =1

provided.

this bit causes a trace trap

execution cf

these

logical

1f the result was negative.
if the result was zero.
1f the operation resulted in an arithmetic
~overflow.
C =1 1f the operand resulted in a carry out of or
borrow into the MSB (most significant bit).

the

ARCHITECTURE

2.3.2.3

Interrupt éegisters -

The Software Interrupt
Summary
(SISR),
Software interrupt
Reqgquest
(SIRR)
and
Interrupt
Priority
Level
(IPL)
registers
are used tocontrol the interrupt system of the processor,
They
«Keep
track
of
lnterrupt
requests,
current
1nterrupt
priority
level,
and
the
lnterrupt stack pointer.
The function of these registers is described
in Section 2.5.3.
|

2.3.2.4

Memory Management

Registers

The Map Enable Register (MAPEN), System Base
Register
Length
Register
(SLR),
PO
Base Register (P0OBR), PO

(POLR),

Base Register

(P1BR),

and Pl

Length

(SBR),
System
Length Register

are

used
to
enable
the
on
<chip
virtual memory management unit and to
access the page table entries (in memory) used
to
translate
wvirtual
~addresses into physical addresses.
The function of these registers is
described 1n Section 2.4.

2.3.2.5

Processor

Status

Longword

The Processor Status Longword
the

processor.

The

lower

Processor Status Word (PSW).
privileged and
accessed
by

(PSL)
16

contains

bits

status

the

PSL

The
upper
16
system software

information

are

the

bits
of
the
PSL
are
when the processor is in

the kernel mode.
Table 2-2 describes the function of each bit
PSL and Figure 2-14 shows the configuration of the PSL.

31302928 272625242322 2120

' MBZ

mMBZ

L PN A

vA
l

’

FPD

1615

IPL
1.1

[

e e o

PROCESSOR STATUS WORD

TS U

.PSL
A

MBZ
MR-11800

Figure

2-14

Processor

Status

-about

non-privileged

Longword

the

ARCHITECTURE

Table 2-2
Bit

Processor Status Longword Bit Descriptions

Description

be zero.

Must

Trace Pending

(TP)

- Forces a trace trap when set at

the beginning of any instruction.
Set by the
processor if the T bit in the PSW 1s set at the
beginning of

instruction.

29:28

Must§be

First Part Done (FPD) - Set when an exception or
interrupt occurs during an instruction that can be
suspended. If FPD 1s set when the processor returns
from an exception or interrupt, 1t resumes the
interrupted instruction where it left off, rather
than restarting the instruction.

26
~

25:24

zero.

Interrupt Stack

executing on the

20:16

15:00

stack.

(CUR MOD)

- The access mode of

the currently executing process:
=
=
=
=

Kernel
Executive
Supervisor
User

Previous Access Mode

(PRV MOD)

- Loaded from CUR MOD

by exceptions and Change Mode instructions, cleared
by interrupts, and restored by a Return From

Exception or
21

- Set when the processor

interrupt

Current Access Mode
0
1
2
3

23:22

(IS)

Must

Interrupt

(REI)

instruction.

zero.

Interrupt Priority Level

(IPL)

greater

IPL.

- Contains the current

processor priority in the range 0 to 1F (hex).
The
processor will only accept interrupts on levels
than

the current

Processor Status Word (PSW) - Contains non- pr1v1leged

processor

status.

ARCHITECTURE

2.3.3.

The

Processor

VAX

Registers

architecture

uses

number

processor

(privileged)

registers.
Some
of
these registers are implemented in the MicroVax
78032 CPU and some can be implemented in external logic
and
accessed
by
the
MicroVAX
78032 CPU.
These registers are explicitly accessed
only by the Move to Processor Register (MTPR) and Move from
Processor
Register
(MFPR)
instructions.
The processor registers are listed in
Table 2-3.
Each of the processor registers
the following categories:

listed

Table

2-3

falls

1into

one

implemented by the MicroVAX 78032 CPU as specified by
the VAX Architecture
implemented by the MicroVAX 78032 CPU uniguely
passed to external logic via the external processor
reglister protocol;
1if not implemented externally,
read as zero, no-oped on write
access not allowed (reserved operand fault)

ARCHITECTUR!

Table

~Number

(Decimal)
0
1
2
3

2-3

Internal

Processor Registers

Mnemonic

Type

Scope

Init

rw
r'w
rw
rw

proc
proc
proc
proc

-----

Kernel Stack P01nter
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer

Interrupt
reserved
reserved
reserved

KSP
ESP
SSP
USP
ISP
----

rw
----

8
S
10
11
12
13
14
15
16

P0 Base Regilister
P0 Length Register
Pl Base Register
Pl Length Register
System Base Register
System Length R&qmster
reserved
reserved
Process Control Block Base

POBR
POLR
P1BR
P1LR
SBR
SLR
--PCBB

rw
rw
rw
rw
rw
r'w
--rw

System Control

SCBB

IPL
ASTLVL
SIRR
SISR
IPIR
CMIERR
- ICCS
. NICR
ICR
TODR
CSRS

rw
rw
W
rw
rw
r
r'w
W
r
rw
rw

CSRD

4
5
6

18
19
20
.21
22
23
24
25
26
27
28

Stack

Pointer

Block

Base

Interrupt Przorlty Level
AST Level
|
Software Interrupt Request
Software Interrupt Summary.
Interprocessor Interrupt
CMI Error Register
Interval Clock Control
Next Interval Count
Interval Count
Time Of Year
Console Storage Receiver

cpu
-

Cat
1
1
1
1

-----

1
<
4
*

proc
proc
proc
proc
Cpu
cpu
--proc

-------

1
1
1
1
1
1
1
4
1

cpu

Cpu
proc
cpu
cpu
cpu
cCpu
cpu
cpu
cpu
cpu
cpu

yes
yes
-~
ves
-yes
----

1
1
1
1
4
1
2
3
3
3
3

cpu

Status

Console Storage

Receiver

Data

Console
Status
Console

Storage

Transmitter

CSTS

cpu

Storage Transmitter

CSTD

cpu

Data

32
33
34
35
36
37
38

Console Receiver Status
Console Receiver Data
Console Transmitter Status
Console Transmitter Data
Translation Buffer Disable
Cache Disable
‘Machine Check Errar summary

RXCS
RXDB
TXCS
TXDB
TBDR
CADR
MCESR

rw
r
rw
W
r'w
rw
rw

cpu
cpu
cpu
Ccpu
cpu
cpu
Ccpu

-----=
---

3
3
3
3
3
3
3

Cache

CAER

cpu

Error

wwmmmmwwmmmmmwmmmmmmmmmmmmMwmmm*mmmmmwwwmmwmmwmmmmmmmmmmmmmmmmwmmmwflmmm

ARCHITECTURE

Table

2-3

Internal

Processor

Registers

(Continued)

Number

(Decimal)
40

Mnemonic

ACflelerator

41
42

Control/Status
Saved ISP
Console Saved PC
Console Saved PSL
WCS Address
WCS Data
reserved
Console

43
44
45

46
17
48
19

50
51
52
53
54
55
56
57
58

59
60
61

62
63
64:127

Type

Scope

Init

ACCS

cpu

SAVISP

cpu

SAVPC
SAVPSL
WCSA
WCSD
-

r
r
rw
rw
- -

Ccpu
cpu
cpu
Cpu
;-

------

2
Z
2
4
4
4

-Cpu
cpuy
cpu
cpu
cpu
cpu
cpu
cpuy
cpu
cpu
cpu
cpu
cpu
proc
Cpu
cpu
--

--==
------yes
------= ---

1
3
3

reserved
|
--SBI Fault/Status
SBIFS
rw
SBI Silo
~
SBIS
r
SBI Silo Comparator
|
SBISC
rw
SBI Maintenance
SBIMT
rw
SBI Error Register
SBIER
rw
SBI Timeout Address
SBITA
r
SBI Quadword Clear
SBIQC
Y
IO Bus Reset
IORESET w
Memory Management Enable
MAPEN
rw
Trans. Buf. Invalidate All
TBIA
W
Trans. Buf. Invalidate Single TBIS
W
Translation Buffer Data
TBDATA
rw
Microprogram Break
- MBRK
rw
Performance Monitor Enable
PMR
rw
System Identification
-~ .SID
r
Translation Buffer Check
TBCHK
W
reserved
“
--

Legend:
r
W

read

write

read/write

cpu

process

proc

Init

specific, loaded by LDPCTX
system-wide, not affected by LDPCTX

1initialized

power-up

chip

Cat

reset

the

restart

process

3
3
3
3
3
3
1
1
1

3
3
3
1
1
3

ARCHITECTURE

2.3.3.1

MicroVAX 78032 CPU Specific Registers -

The implementation specific processor registers are:
Interval
Clock
Control
and
Status
(ICCS),
Console
Saved
Interrupt Stack Pointer
(SAVISP), Console Saved PC (SAVPC), and Console
Saved
PSL
(SAVPSL).
These are described in the following paragraphs.

2.3.3.1.1

Interval Clock Control And Status Register (ICCS) -

"The ICCS register controls the
contains
a
single
bit,
bit
timer interrupt.
Bit <6>
interrupts are enabled at

interval timer (INTTIM) interrupt.
It
<6>, to enable or disable the interval

1s read/write.
When
set,
IPLl6; when clear, interval

are disabled.
Bits <31:7,5:0> read as zero and are
Bit <6> 1s cleared by RESET.
Figure 2-15 shows the

JSLISL

IS,

RU U

B
N

=
O

S T

ignored on writes.
ICCS register.

070605
N

1nterval
timer
timer interrupts

B OO O

:1CCS

MR-13390

Figure

2-15

Interval

Clock

and Control

Status

ARCHITECTURE

2.3.3.1.2
The

console

Console Saved Registers
saved

registers

processor
registers
pointer, PC, and PSL,
The

SAVISP

and

(SAVISP, -SAVPC,

(SAVISP,

SAVPC,

SAVPSL)

used
to record the value
respectively, at the time

SAVPC

registers

are

used

SAVPSL)

save

are

Llimited

1life

of the interrupt stack
a chip restart occurs.
the

interrupt

stack

pointer and the PC, respectively.
The SAVPSL register is used to save
the contents of the PSL, MAPEN,.and the restart
code.
Figure
2-16
shows
these registers.
Refer to Section 2.8 for a description of how
these registers are used.

1L
L

NN R

SAVED INTERRUPT STACK POINTER

:SAVISP

SAVED PROGRAM COUNTER
|
.
e
bty

:SAVPC

bbb

ety

00
B

Lot

R B

161514
F1 1

T1T T

PSL <31:16>

1T T T

71711

00
1

1711

RESTART CODE

1T 11

PSW

1711

:SAVPSL

MAPEN
MR-13391

Figure

2-16

Console

2-20

Saved Registers

ARCHETECTGR
2.4

MEMORY MANAGEMENT

Memory management consists of the hardware and software which
control
the
allocation
and
use
of
physical
memory.
Typically,
in
a
multiprogramming system, several
processes
may
reside
in
physical
memory at
the same
time.
The
MicroVAX
78032 CPU uses
memory

protection and multiple address spaces to ensure that
not affect other processes or the operating system.

one process

will

To further improve
software
reliability,
four
hierarchical
access
modes
provide
memory
access
control.
They are, from most to least
privileged:
kernel, executive, supervisor, and user.
Protection
1is
specified
at
the
individual page
level,
where
a
page
may
be
~lnaccessible, read-only, or read/write for each
of
the
four access
modes.
Any location accessible to one mode is also accessible to all
more privileged modes.
For each access mode any location that can - be
written can also be read.
When memory management is enabled, the CPU generates virtual addresses
when
a
program
1is executed.
However, before these addresses
can be

used to access instructions and data, they
must
be
translated
into
physical
addresses.
Memory management software must maintain tables
of mapping information (page tables) that keep track of where each 512
byte
wvirtual
page
1is
located in physical memory.
The CPU utilizes
this mapping information
when
it
translates
virtual
addresses
to
physical addresses.

Memory

management

protection
Memory

and

management

Provide

Allow data

Provide

Contribute

memory
meets

large

the

several

address

structures

convenient
to

scheme

mapping

for

programs

with

Programs

run

both

the

MicroVAX

instructions

and data.

memory

78032

CPU.

sharing of

instructions

and data.

reliability.

A virtual memory system provides
to

one gigabyte.

and efficient

software

provides

goals:

space

that

mechanisms

hardware

large

address

limited

space,

memory

execute 1n an environment
termed
a
process.
system for the MicroVAX 78032 CPU provides each
4 billion byte virtual address space.
|

memory

yet

allows

configurations.

The

wvirtual

process

with

a
|

Memory management divides virtual address space into
two
equal
size
spaces,
the
system
address space and the per-process address space.
The system address space is the same for all processes.
It
1s
wused
for the operating system, which may be written as callable procedures.
Thus all system code can be available to all
other
system
and
user
code
via
a
CALL instruction,
Each
process
has its own separate
process address space.
However, several processes may have access
to

2-21

ARCHITECTURE

the same page, thus providing controlled sharing.

2.4.1

vVirtual Address Space

A virtual address is a 32
bit
wunsigned
integer
specifying
a
byte
location
1in
the address space.
To the programmer memory is a linear
array of 4,294,967,296 bytes.
The virtual
address
'space
1is
broken
into
512
byte
wunits
termed
pages.
Each page may-be relocated and
protected.

Memory management provides the mechanlsm to map the active part of the
virtual address space to the available physzcal address space.
Memory
management also
provides
page
protection
between
processes.
The
operating
system
controls
the
wvirtual-to-physical
address mapping
tables, and swaps the inactive but used parts of the
wvirtual
address
space onto the external storage media.
,
~

The virtual address space 1s divided into two parts.
The
half
with
the
lower
addresses,
known
as "per-process space,” is distinct for
each process
running
on
the
system.
The
half with
the
higher
addresses,
known
as
"system
space,"
1s
shared by all processes.
Figure 2-17 shows the division of virtual address space.
00000000

LENGTH OF PO REGION IN PAGES-

(POLR)
PO
REGION

3FFFFFFF
40000000 |

PO REGION GROWTH DIRECTION

P1 REGION GROWTH DIRECTION

REGION

LENGTH OF P1 REGION IN PAGES

(2**21-P1LR)
JFFFFFFF

80000000

,
LENGTH OF SYSTEM REGION IN PAGES

(SLR)

SYSTEM
REGION

SYSTEM REGION GROWTH DIRECTION

BFFFFFFF
C0000000

RESERVED

REGION

FFFFFFFF
MA-11603

Figure

2-17

Virtual

2-22

Address

Space

ARCHITECTURE

2.4.1.1

Process Space

Addresses OOOOOOOOw7FFFFFFF (hex)
of virtual address space are

called

"per-process
space”.
The per-process space is divided into two equal
parts, the program reglon (PO
region)
and the control
region
(Pl
region).
Each process
has
a
separate address trans.lation map for
per-process space, so the per-process spaces of all processes
can
be
cmmpletely dlS]anted
The
address
map
for
per-process space 1s

~context switched

(changed)

~changed.

2.4.1.2

System Space

when the process running on the

system

Addresses 80000000~ wFFFFFFF (hex) of virtual address space are
<called
"system
space".
All processes use the same address translation map
for system space, sO system space 1s shared among all processes.
The
address map for system space 1s not context switched.

2.4.1.3

Virtual Address Format

The MicroVAX 78032 CPU generates a 32-bit
instruction

and

operand

1i1n

memory.

virtual

address

for

the process executes,

each
the

processor translates each virtual address to a physical address.
The
format
of
a virtual address i1s shown in Figure 2-18 and described 1in
Table

2-4.

When bit 31
is zero,

is one,

the address

the address
is

is in the system space.

When

in the per-process space..

bit

Within the per-process space, bit 30 distinguishes between the program
and
control
regions.
When
bit
30
1is
one, the control region 1is
referenced, and when it is zero, the program region is referenced.

|
|S

i G

VPN
O

0908

BYTE NUMBER
N

| NS N

MR- 11804

Figure

2-18

Virtual

Address

ARCHITECTURE

Table

Field
VPN

2-4

Virtual

Address

Bit

Bits

Descrlmtlon

<31:09>

Virtual

Page

specifies

Descriprtion

Number

the

This

field

virtual

page

referenced.
Virtual address space
contains 8,388,608 pages of 512 bytes

each.

Bits <31:30> of

the VPN are used to

select the region cf virtual
space being referenced.

Value of
BltS

BYTE NUMBER

<08:OO>V

mmmmmemmmmww

Independent

bytes)

may

PO
|

Protection

1its

Pl
System
Reserved

number

within

mmmmmwmmmmmm

Page

Referenced

Byte§Number - This field specifies the

byte

mmmm”mmmmwmm

2.4.1.4

Regian

<31:30>

0
1
2
3

address

the

page.

mmmmmmmmmmmm

mmmmw“mwmmmm

mmmmmmmmflmw

location

protected

virtual

according

address

its

space,

use.

Even

page

(512

though all

system space 1s shared, in that a program may
generate
any
address,
the program may be prevented from modifying or even accessing portions
of system space.
A program may also be prevented
from
accessing
or
modifying portions of process space.

2.4.2

Memory Management

Control

The action of translating a virtual address into a physical address is
controlled
by
the
setting of the Memory Mapping Enable (MME) bit in
the Map Enable
(MAPEN)
register.
The
format
of
the
Map
Enable
Register 1s shown 1in Figure 2-19 and described in Table 2-5.

2-24

ARCHITECTURE

|
IR

NS N

NS SN NN

[

OSSN

0100

NN S

AR R

NN NN NN N

NN N

AU N

NN N

MME
MR-11608

Figure

Table 2-5
Field

2-19

Map Enable Register

Map Enable Register Bit Description

Bit

MBZ

<31:01>

- MME

<00> .

Description
Must

Zero

Memory‘Management Enable - used to

~enable and disable memory management.
MME
= 1
MME
= 0

2.4.3

Enabled
Disabled

Access Control

Access control is the function of validating whether a particular type
of
memory
access
1is to be allowed to a particular page.
Every page
has associated with it a protection code that specifies for each
mode
whether

not

read

write

references are allowed.

address is checked to make certain that
region of virtual address space.

2-25

in the PO,

Pl,

Also,

each

or system

ARCHITECTURE

2.4,3,l

Processor Modes

There are four hierarchical modes used for protection by the
78032

CPU.

The

modes

the

order

most

least

privileged

MicroVAaX
are:

Kernel
- used by the kernel of theoperating system for page

management,

scheduling,

Executive

used

Supervisor

User

used

for

used

for

etc.

such

level

I/0

the

drivers.

operating

services

code,

system

command

utilities,

The mode at which the
current mode field of

2.4.3.2

many

for

user

and

each page

calls.

interpretation.

compllers,

debuggers,

processor is currently running is stored
the Processor Status Longword (PSL).

Protection Code

Associated with

service

the
‘

in virtual

address

space

1is

protection

code
that
protection
within the

1is
located in
the
page table entry for that page.
The
code allows a choice of protection for each processor mode,
following limits:

for each

Access

processor mode

access.

read/write,

read

only,

If a
also

If a processor mode has write
modes also have write access.

processor mode has
have read access.

can

read

access

then

access

all

then

The protection codes are listed in Table 2-6.

more privileged modes

all

privileged

ARCHITECTURE

Table

code

2-6

Protection Codes

decimal

bilnary

mnemonic

A
- -

0000
0001
0010
001l
0100
0101
0110
0111l
1000
1001
1010
1011

0
1
2

5
6
7

8
9
10
11
12
13
14
15

1100
1101
1110
1111

—

current mode
K

unpredictable

uw
EW
ERKW
ER

RW
RW
RW
R

RW
RW
R
R

RW
-

SW
SREW
SRKW

"RW
RW
RW

RW
RW

RW
R
R

-~
R
R

URSW
UREW

RW
RW

RW
R

URKW

R
=
RW =

access

read only
read/write

cwnmx

Legend:
-

= Kernel

= Executive
= Supervisor
=

User

access

reserved

all

access

ARCHITECTURE

2.4.3.3

Length Violation

Every valid virtual address
lies
within
bounds
determined
by
the
addressing
region
(PO,
Pl,
or
System)
and
1its associated length
register (POLR, PlLR, or SLR).
Virtual
addresses
that
are
outside
these bounds w1ll

2.4.3.4

Access

cause

antrol

length v101atlon.

Violation

access control violation fault
occurs
if
an 1illegal
access
is
attempted,
as
determined .by
the
current
PSL
mode and the page's
protection field, or if the address causes a length violation.

2.4.3.5

Access AcCross A Page Bouhdary§~

If an access is made across a page boundary, the order
pages
are
accessed
1s
unpredictable.
However, for
access control v1olat10n always takes precedence
over
not valid.

2.4.4

The

Address

action of

memory

in
which
the
given page an

translation

Translation

translating

management

a virtual

address

controlled

the

a physical
setting

address

the

Memory

Management Enable (MME) bit in the MAPEN register.
When MME is
a
0,
memory mapping disabled, bits<29:00> of the virtual address become the
physical address and there is no page protection.
This means that all
accesses
are
allowed
1in all modes.
When MME is a 1, memory mapping
enabled, address
translation
and
access
control
are
on
and
the
processor
uses
the following to determine whether an intended access
l1s allowed:

The wvirtual address,
intended access

which is used to index a page‘table,

The

type

The current privilege
kernel level for page

(read or write),

and

level from the Processor Status
table mapping references.

Longword,

the

If the access is allowed and the address can be mapped, the result
physical

1is

The

intended access

read.

read

The

write.
followed

address

corresponding

is READ

1intended

If
by

the

operation
the

the

specified

if the operation

access

write)

WRITE

the

2-28

access

address.

performed

operation

performed

intended

virtual

modify

specified

performed

(that
a

is,

WRITE.

ARCHITECTURES
If an operand is an address operand, then no reference is made.

means the page does not need to be accessible or even exist.

2.4.4.1

Page Tabl@ Entry (PTE) -

The MicroVAx 78032 CPU uses a*?age
virtual

This

addresses

shown in Figure 2-20

3130

Table

V| PROT Mle
L

00
N

L1l

(PTE)

The page

table

translate
entry

in Table 2- 7

2726252423222120
L

Entry

addresses.

and described

physical

|
N

PFN
N

00
N

BN BN

yfit.il'k!l‘lll;lmiiill,l

OWN
|

MR.11608

Figure 2-20 Page Table Entry

Table 2*7'§Page Table Entry Bit Description
Field

Bit
~

Descriptimn

'Valid bit - Governs the validity of the
modify (M)

field.

PROT

30:27

bit

V =1

and

the page

for valid;

Vv =

frame

0 for

number

not valid.

Protection field - Describes the protection
for

the page.

This

field

always valid.and

is used by the hardware even when V = 0,
M

Modify bit - This bit is set (= 1) if the
‘page has already been recorded as modified.
M =0 1f the page has not been recorded as
modified.
Used only if Vv
= 1.

Must

- OWN

24:23

-0

22:21

PFN

20:00

zero.

~§.Owner bits - reserved.
Must be

zero.

Page Frame Number - The upper 21 bits of the

physical address of the base
Used only if v = 1.

2-29

the page.

(PFN)

ARCHITECTURE

2.4.4.ltl

Protection Check

Before Valid Check

The page table entry is defined

2.4.4.1.2

Entries

having a

wvalid

blt

that

only

controls
the
valldlty of the modify bit and page frame number field.
The protection field is defined as always being valid and
1is
checked
first.
|

Changes

Page Table

The operating system changes PTEs as part
functions.

changes

For

the PFN

example,

1its

MicroVMS sets and clears

fléld as pages

are

swapped

1in

memory

and

memory

management

the valid bit

out

and

physical

The software must guarantee that each PTE 1s always consxstent
within
itself.
Changxng
a
PTE one field at a time may result in incorrect
system operation.
An
example
would
be
to
set
PTE<V>
with
one

instruction before establishing PTE<PFN> with another instruction.
An
interrupt routine between the two instructions
could
use
a
virtual
address
that
would
be
mapped
by
memory
management
wusing
the
~inconsistent PTE.
Software can solve this problem by building
a
new
PTE

reglster

and

then moving the

51ngle instruction such as Move

Long

new PTE

the

page

table

with

(MOVL).

Multiprocessing
processor,
be

note

makes
the
problem
more
complicated.
Another
1t
another CPU or an I/0 processor, can reference the
page tables that the first CPU is changing.
The second processor
always
read consistent PTEs.
In order to guarantee this, first
that PTEs are longwords, longword-aligned.
Then two requirements

must

same
must

met:

Whenever the software modifies a PTE in more

The hardware must
guarantee
that
a
longword,
longword-aligned
write
1s an atomic operation.
That is, a second processor cannot
read (or write over) any of the first processor s partial results,

must
use
instruction,

2.4.4.2

System

a
longword,
such as MOVL.

Space Address

longword-aligned,

Translation

A virtual address with bits <31:30> = 2
system virtual

address

than

one

byte,

write-destination

is defined as

address

space.

System virtual address
which
1s
defined
by

space 1s mapped by the System Page Table (SPT),
the
System Base Register (SBR) and the Sys:em
Length Register
(SLR),
Figure
2-21.
The
SBR
contains
the
base
physical
address
of the the System Page Table.
The SLR contains the
2-30

ARCHITECTURE

size of the SPT in longwords,

that

15, the

number

Page

Table

Entries.
The
Page Table Entry addressed by the System Base Register
maps the first page of system virtual address space, that is,
virtual
| byte address 80000000 (hex).

Figure 2-22 illustrates the translatxmn of a system v1rtual address to

a physical

address.

- The algorithm to generate
virtual address is:

a phy51cal

address
-

from

system

" SYs_pa w;(SBR+4*SVA<29;9?)420:00$‘SVA<08:OO}
313029
|

{MBZ|
.

|
rT

|
T

PHYSICAL LONGWORD ADDRESS OF SPT

NURS UR TNOSN N

NS T

OV T

TSI

TN O

020100
RO

MBZ| :SBR

]

2221

)NI O T

LENGTH OF SPT IN LONGWORDS
S

OO N

RO SANE N

TN U

l :SLR A

A
MR-11609

Figure,2w2l'System”Mappihg'Registers

region

ARCHITECTURE

‘

313029

SVA:

(SYSTEM VIRTUAL
ADDRESS)

2
|

/I L

AN N

0908

[

BYTE

EXTRACT AND

CHECK LENGTH

23122

02|0100

rrrrrrrrrrrr

ADD

SBR:

rTr

PHYSICAL BASE ADR OF SPT

A NN N

NS TG N

0 l

YIELDS

0100

rTrrrrrrrrrrrr

0100

rTrrrrrrrrrrrrT

~ PHYSI
ADRCAL
OF PTE
TN

FETCH

3130

PTE:

l’

2120
A

NN TN NN

CHECK ACCESS

AN B

PFN

NN AN U

THIS ACCESS CHECK

IN CURRENT MODE

29
|

09|08

]

PHYSICAL ADR OF DATA:
N

rTrTrTrirroT

MR 11810

Figure

2-22

System Virtual
to Physical

Address Translation

ARCHITECTURE

Process Space Address Translation -

2.4.4.3

A virtual address with bit <31> = 0
1s
an
address
virtual address space.
Process space 1s divided into

separately mapped regions.
If virtual
address
- address is in region PO. If virtual address bit
'
'is in region Pl.

2.4.4.3.1

The PO

PO Reglmn Addreas Translatxmn

r@gxmn of v1rtual

(POPT),
which
Length Register

virtual

address space

in
two

the
process
equal sized,

bit
<30>
=
0,
the
<30> = 1, the address
|
:

1is mapped by

the PO Page

Table

1is defined by the P0) Base Register (POBR) and the PO
(POLR), Figure 2-23.
The
POBR
contains
the
system

address

the

Page

Table.

The

POLR contains

the

size

the POPT in longwords, that is, the number of Page Table Entries.
The
Page Table Entry addressed by the PO Base Register maps the first page
of the PO region of th@ v1rtual ‘address space, that is,
virtual
byte
addr@ss 0.
Flgure 2-24 1llustrates
physical address.

the translatlmn of

The algmrlthm to generate a physzcal
address 1is:
PVA PTE
PTE_PA

a PO

address

virtual

from a PO

address

region

= POBR+4*PVA<29:09>
= (SBR+4*PVA PTE<29:09>)<20:00>'PVA PTE<08:00>

PROC_PA = (PTE PA)wzo 00>'PVA<08:00>

313029
T

[T
T TT T

NS T

l 2 |
[N

BLASL

TN T

020100

SYSTEM VIRTUAL LONGWORD ADDRESS OF POPT

TN TS O

NS NN

22 21

. DL

T TT TT T

NN N

‘

RN N

UUN N

TT T

SN (NN NNV ANE O

NN N N B

LENGTH OF POPT IN LONGWORDS
eN T

‘Figure 2-23

TT T

PO Region Mapping Registers

2-33

00
|

:POBR

:POLR
MR-116811

wvirtual

ARCHITECTURE

PVA:

313029

(PROCESS VIRTUAL

[ I AN N

0 |

ADDRESS)

SUATTT

D A

L
N N

0908

FrrrTrrrriy

BYTE

EXTRACT AND
|

CHECK

i
1T

23|22

LENGTH

1117717

rrrrrrrrrrrrrr1r

OO T

IO I

11111

ADD

POBR:

02|0100

0100

rrrrrrrrrrrrrrrrrrrrrrr1rr1orrr1

- SYS VIRT BASE ADR OF POPT
S

WY s O 1

YIELDS

31
|

|
rrr

TETI

T
T T

TSN

TT T

0100

rrrrrrrrrrrrrrro

SYS VIRTUAL ADR OF PTE

0 ‘|

[

]

0 l

W0 OO O

FETCH BY SYSTEM SPACE

TRANSLAT!ON ALGORITHM,
INCLUDING LENGTH AND
.

;

3130

KERNEL MODE ACCESS CHECKS

2120

- 00

‘!t'ili!l!lIfli!!lllli‘!llll!l!t

PTE:

PFN

N TN
T S0

OT (N T

CHECK ACCESS

Ty s T TS W

THIS ACCESS CHECK
IN CURRENT MODE

NN
N
DNO

|
S DO
AN AN N

|
BN AN

09|08

BN R

¢
B

PHYSICAL ADR OF DATA:
,

O
Y O

T
MA-11612

Figure 2-24

2.4.4.3.2
The

(P1PT),

region

PQO Virtual to PhysiCal'Address“Translaticn

Region Address
of

which

virtual

1is

Translation
-

address

defined

space

mapped
by

the

by the Pl Base Register (P1BR)

Page

Table

and the Pl

Length Register (PlLR), Figure 2-25.
Because Pl space
grows
towards
smaller addresses, and because a consistent hardware interpretation of
the base and length registers 1s desirable, P1BR and PlLR describe the
portion
of
Pl space that 1s NOT accessible.
Note that PlLR contains
the number of nonexistent PTEs.
P1BR
contains
the
system
virtual
address
of
what
would be the PTE for the first page of Pl, that is,
virtual byte address 40000000 (hex).
The
address
in
Pl1BR
1is
not
necessarily
a
wvalid system virtual address, but all the addresses of
PTEs must be valid system virtual addresses.

2-34

ARCHITECTURE

Flgure 2-26 illustrates the Pl virtual
translation.

address

- The algorithm to generate a physxcal address

physical

frmm a Pl

~address is:

PVA_PTE = P1lBR+4*PVA<29: 09>

PTE "PA =

region

(SBR+4*PVA PTE<29:09>)<20: 00> PVA PTE<(08:00>

pROC PA = (PTE PA)<20:00>'PVA<08:00>

' ,

NN N

AL
T

AN O

TN N

(B G

(NN U

mez
N

SN SN

221

SN N

|
T

NN TN N

)

S G

TG WY N

!'li’ll’tlil“‘(~

|l .

) SN

SYSTEM VIRTUAL LQNGWORQ ADDRESS
OF P1PT

A
O

lMEZI :P1BR
A

,!lililitltiiiiii‘

_ LENGTH OF P1PTIN LONGWORDS

lltlltlil!lli

I :P1LR
MRA-11613

Figure 2-25
Pl Region Mapping Registers

2-35

address
wvirtual

ARCHITECTURE

313029

PVA:

(PROCESS VIRTUAL

ADDRESS)

0908

TN
I N

D B

BYTE

‘

EXTRACT AND

31
‘

23|22

SEN SSOS N

02/0100

A SN

TT T

orrTTT

{

0100
1

T
T T

\ [

i’

Q l

SYSVIRTUAL ADROFPTE

AN N (N

YIELDS

rT1T TT T

SN SN RN M

[

SYS VIRT BASE ADR OF P1PT

ADD

! T '

DN A

P1BR:

CHECK LENGTH

0100

0 l

FETCH BY SYSTEM SPACE
TRANSLATION ALGORITHM
INCLUDING LENGTH AND

KERNEL MODE ACCESS CHECKS

3130

PTE:

2120
DR

AN D

PEN

CHECK ACCESS

NN BN UNDN

i’

| LI

00
B

THIS ACCESS CHECK
IN CURRENT MODE

29
v

09|08

Fr1T

1T
1T

T
T

17T

PHYSICAL ADR OF DATA:
Pt

bbbt

]

MR 11614

Figure

2.4.5

2-26

Translation

In order to
pages,
the

helps

Physical

Address Translation

Buffer

save actual memory references when repeatedly
MicroVAX
78032
CPU has a fully associative,

translation
buffer
successful
wvirtual
pages.

Virtual

save

that
contains
page
table
address translations and page

memory

Control

references when
the

repeatedly

translation

buffer

referencing

entries
status.

eight

entry

the

same

(PTE)
for
This buffer

referencing
is

done

—through

registers:
the Translation Buffer Invalidate Single
(TBIS)
and the Translation Buffer Invalidate All (TBIA) register,
When

the

(LDPCTX)
(that is,

process

context

loaded

wusing

the

Load

Process

two

Context

instruction, the translation buffer is automatically updated
the process virtual address translations
are
invalidated).
2-36

ARCHITECTURE

However,
when software changes any part of a valid PTE for the system
or current process region, it must invalidate any
translation
buffer

entry

moving

TBIS register.

software

virtual

Section

address

2.4.5.1
|

the corresponding page to

gives

changes
a system page

table

description

entry

that maps

the

TBIS
|

any part

the current process page table, all translation buffer entries for the
affected process pages must be
1invalidated.
This
can
be
done
by
moving
an
address
in each of
the
affected
pages
1into the TBIS
register, or by invalidating the entire translation buffer by moving a
0
1into the TBIA regzster.
Section 2.4.5.2 gives
a description of the
TBIA

The translation buffer

does

not

store

invalid

PTEs.

Therefore,

software 1s not required to 1nvalidate translation buffer entries when
making changes for PTEs that are already invalid.

When the location or the size of the system map 1is changed (SBR,
the entire

translation buffer must be cleared.

SLR)

Whenever memory management is disabled (MME = 0) the contents
of
the
translation
buffer
are
unpredictable.
Therefore,
before enabling
memory management at processor initialization time, or any other time,
the entire translation buffer must be cleared
This 1s done by moving
a 0 into the TBIA register.
.
o
"

2.4.5.1

Translation Buffer Inv&lidate;single Register -

The TBIS register

1s used to invalidate

single

PTE

entries

1in

the

translation buffer. This is done by system software writing a virtual
address into the TBIS register, Figure 2-27.
The MicroVAX
78032 CPU

will
1invalidate
the
translation
buffer entry that maps the page 1in
virtual memory accessed by tha vxrtual address wrltten into
the
TBIS
regxst@r.
e
'l

1Tl

r1rrrrrrrrrrrrrrrrrrrrrrTTTTTTTM
VIRTUAL ADDRESS

TN W

WS WS WO AN RN NRONE AN AN A

TRONE NN WO NN U

:TBIS
N

NN A

AN O

AN
. MR-11606

Figure

2-27

Translation

Buffer

Invalidate

Single

~ ARCHITECTURE

2.4.5.2

Translation Buffer Invalidate*All Register -

The TBIA register

used

clear

the

entire

translation

buffer

1invalidating all the PTE's in the translation buffer.
This is done by
software moving a 0 into the 0 into the TBIA
register,
Figure
2-28.
When a 0 1s written into
invalidate all the PTE's

the TBIA register the MicroVAX
in the translation buffer,

rrrrrTrrTrrrrrr

MBZ
S

SO S

TTT

:TBIA
O

RN N

o
MR-116807

2.4.6

Figure 2-28

CPU will
B

TTT

"
N

78032

Translation Buffer Invalidate All Register

Memory Management

Faults

Two types of faults are associated with memory mapping and protection:
translation not valid and access control violation.
A translation
.not
~valid fault is taken when a
read
or
write
reference
is
attempted
through
an’ invalid
PTE
(PTE<31> = 0).
An access control violation
fault 1s taken when the protection field of the PTE indicates that the

intended page

Note

reference
in the

specified

access mode would be

illegal.

that these two faults have separate vectors in the system control
block.
If both
access
control violation (ACV) and translation
not
valid (NV) faults occur, the access control
violation fault takes

precedence.
An
access
control violation fault is
virtual address referenced is beyond the end of
the

table.

Such

"length

violation"

1is

also taken if the
associated - page

essentially

the

same

referencing a PTE that specifies "No Access" in its protection
field.
To
eliminate
the
need
to
recompute
the
length
check,
a length
violation indication
is stored in the fault parameter
block.
For
a
description of the fault parameter block refer to Section 2.5.4.2.

ARCHITECTURI

2.5 EXCEPTIONS AND INTERRUPTS
At certain times during the operation of a system, events
within
the
system
require the execution of particular pieces of software outside

the explicit flow of control.
The
processor transfers
control
by
forcing a change in the flow of control from that explxcmtly 1nd1cated
in the currently executing prwc&ss.

Some of the events are relevant prlmarlly to the currently
executing
process,
and
normally
invoke software in the context of the current
process.
The nmtlfxcatxtn mf such events 1s termed an except10n~'
Other events are przmarmly'r@levamt to
other
processes,
or
to
the
‘system
as
a
whole, and are
therefore
serviced
in a system-wide

context.

The notification process

for

these

events

1is

termed

interrupt,
and
the system-wide context 1s described as "executing on
the interrupt stack" (IS).
Further,
some
interrupts
are
of
such
urgency
that they require high-priority service, while others must be
synchronized with
‘independent
events.
To
meet
these
needs,
the
processor has priority
logic
that
grants lnterrupt service to the
highest priority event at any point in time.
The priority
associated
with an interrupt is termed its interrupt prlorlty l&vel (IPL).

=2.5.1

Processar Interrupt Prlmrxty Levels

(IPL)

‘Th@ VAX architecture has 31 1nt@rrupt prxmrlty l@vels
(I@L), ‘divided
into
15 software levels (numbered, in hex, 0l to OF), and 16 hardware
- levels (10 to 1F, hex).
User appiications, system calls,' and
system
services
all
run at process level, which may be thought of as IPL 0.
Higher numbered interrupt levels have higher priority,
that
1is, any
requests at an interrupt level higher than the processor's current IPL
-~ will interrupt immediately but requests at a lower or equal level
are
deferred.
The interrupt
in Table 2-8.

levels

1mplemented by

the chrmVAX 78032 CPU are

listed

ARCHITECTURE

Table 2-8

Intérrupt Priority Levels

IPL levels (hex)
1F

- 1D

170
16
:
l6
x
18
14
10 - 13
01
- OF

2.5.2

1nterrupt condxtzon
unused

|
-

PWRFL
|

~
S
'

unused

”

asserted

IRQ<3>
asserted
INTTIM
asserted
IRQ<2>
asserted
IRQ<1> asserted
IRQ<0>
asserted

unused
software

znterrupt

request

ProcesSOr Status

When ‘an exceptlion or an
must
be
preserved so
normally.
This 1s done

interrupt is serviced,
that
the
1nterrupted
by automatically saving

the
processor
status
process
may continue
the
Program
Counter

~(PC) and
the
Processor
Status
Longword
(PSL).
These
are later
restored with the Return
from
Exception
or
Interrupt instruction
(REI).
Any other status required
to correctly resume
an interruptable

instruction 1s stored
in the general registers.
Process context
such
as
mapping
1information is not saved or restored on each interrupt or
exception.
Instead,
1t
1s
saved: and
restored
only when process
context switching
1is performed.
C ey
RS
lls

2;5‘3 Interrupts
The processor arbitrates interrupt
requests
according
to
priority.
Only
when
the
priority
of an interrupt reqguest 1s greater than the
current IPL (bits <20:16> of the Processor Status Longword)
will
the
processor
raise
the
IPL
and
service
the
1interrupt request.
The
lnterrupt service routine 1s entered
at
the
IPL
of
the
interrupt
‘request, or at IPL1l7 1: the vector supplied by the interrupting device
Has bit <00> = 1,
|
|
Interrupt
requests
can
come
from
devices,
controllers,
or
the
processor
1itself,
Software
executing
1n kernel mode can raise and
lower the priority of the processor Dby executlng MTPR src,#IPL,
where
Src contains the new priority desired.

ARCHITECTURE

The
instructions.
‘The processor servmces xnterrupt requests between
points
interrupt requests at well defined
processor also services
the
instructions such as
iterative
long,
~during the execution of
For these instructions, in order to avoid saving
string instructions.
additional instruction state in memory, interrupts are initiated when
the
instruction state can be completely contained in the registers,
PSL,

and PC.

‘

The following events cause interrupts:
1.

Interrupt frmm‘a perzpheral device recexved on IRQ<3:0>
- 17 hex)
,
|

(IPLI&

to
|

2*; HALT (nonwmaskable)

3. Power fail (IPL1E hex)
4. ~Intérval timer (IPL16 hex)
|
5. Sdftware interrupt invoked by MTPR src, #SIRR (IPLOl to OF hex)
6.

AST dellvery when REI reatmres a PSL with mode greater',than or|
|

equal to ASTLVL (IPL 02 hex)

Each devmce has a separate 1nterrupt vector
location
1n the system
control block
(SCB).
Thus interrupt service routines do not need to
poll devices 'in order to
determine
which
device
interrupted.
The
vector address for each devzce is determined by hardware.

In order to reduce interrupt overhead, no memory mapping
information
'is changed when an interrupt occurs.
Thus the instructions, data, and
contents of the interrupt vector for an interrupt service routine must
be in the system addrefig spaceor present in every process at the same
address.

2.5.3.1
The

VAX

Urgent Interrupts -- Levels 18-1F (Hex)
architecture

has

priority

levels

for wuse

urgent

conditions 1including
serious
errors (e.g., machine check) and power
fail.
Interrupts on these levels are initiated by the processor
upon
detection
of
certain
conditions.
Some of these conditions are not
Lnt@rrupts, but are exceptions that are run at IPLIF (hex).

2.5.3.2 Device interrupts -- Levels 10-17 (Hex) The VAX architecture has 8 prioricty
levels
for
wuse
Dby
peripheral
devices.
Of these 8 priority levels the MicroVAX 78032 CPU implements
four, levels 14 through__l7
(hex) .
The
processor
recelves
device

interrupt requests via IRQ<3:0> and INTTIM.
2-41

ARCHITECTURE

2.5.3.3

Software

Generated

Interrupts
--

Levels

01-0F

(Hex)

The proc
has
es
15 interr
soupt
r levels
for
use
by
levels
are
01 through OF (hex).
These interrupts

software

to generate software

2.5.3.4

Interrupt

The

Control . -

hardware interrupt

PWRFL,
and INTTIM
Asserting any
of
generated

registers

2.5.3.4.1

the

are

used

controlled

30ftwaré.
These
are used by systeminterrupts.
~

system

controlled
by

the

IRQ<3:0>,

inputs to the processor along. with
the input
pins
results
1in
an
hardware

Software

control

Interrupt

level

the

given

1in

software

Table

interrupt

Summary Register

HALT,

three registers.
interrupt being
2-8.

The

system.

three

The Software Interrupt Summary Register
(SISR),
Figure
2-29,
1is
a
privileged
register
that
records
pending software interrupts.
It
contains 1's in the bit positions corresponding
to
levels
on
which
software
interrupts are pending.
All such levels, of course, must be
lower than the current processor IPL,
or
the
processor
would
have
taken the requested interrupt.
”
|

1615

;

IR EDiCBYA9.8,7)6,5,4)3,2)1]

'SISR

MBZ
MR-11615

Figure 2-29

2.5.3.4.2

Software~1nterrupt Request Register -

~The software
write-only

interrupt

SOftWare Interrupt Summary Register

interrupt

four
bit
reguests.

request

privileged

(SIRR),

used

Figure 2-30,
for

making

1is

software

ARCHITECTURE

0403

QGNOHEQ
.

TS0

CHEE S

OO O

I
MAR-11616

Fxgure 2-30

Software Interrupt Request Register

Executing MTPR src,#SIRR requests an interrupt at the level specxfled
by src<3:0>,
Once
a software xnterrupt request is made,
it will be
cleared by the hardware when the interrupt is taken. If
src<3:0>
|is
greater than the current IPL, the interrupt occurs before execution of
the followlng instruction.
If src<3:0> is less than or equal ‘to
the
current
IPL,
the interrupt will be deferred until the IPL is lowered
to less than src<3 0% and there is no higher level interrupt pendlng

2.5.3.5

Interrupt Priority Level Register ~

Writing to the IPL, Figure 2-31, with the MTPR instruction
will load
the
processor priority
field
1in the Program Status Longword (PSL),
that is, PSL<20:16> is loaded from IPL<4:0>. Reading
from
IPL
with
+he MFPR
instruction will read the processor priority field from the

D D

B
D

DO D

PSL.

0504

1
1 1

IGNORED, RETURNS 0

E‘i

Q‘

(TR

OO T

IPL

TR I

!‘

PSL<20:16>
MA-11617

Figure 2-31

Znterrupt ?riority Level Register

nter”upt serv1ce routines must follow the disc ipline
of not

lowering

IPL
below their
initial
level.
If they dm,
an interrupt at an
intermediate level could cause
the stack
nesting
to
be
Improper.
‘Actually,
a service routine could lower the IPL 1f it ensures that no
intermediate levels could interrupt.
However, this
would
result
in
unreliable code.

ARCHITECTURE

2.5.3.6
As

Interrfipt Example -

example, assume

interrupt

the

processor

running

then

IPL

IPLS5,

requests at IPL3 IPL7,
IPL16
(hex).
Finally

executlion

is:

sets

1in

and

and IPLS9. Then a devxce interrupt
IPL
is
set
back
to IPLS
The
|
|

o’

state

after

(initial)
MTPR #8,#IPL
MTPR #3,#SIRR
MTPR #7,#SIRR
MTPR

#9,#SIRR

1nterrupts

device interrupts

device service routine REI
- IPLY service routine REI
MTPR

#5,#IPL

and the
granted

changes

IPL

request for
1mmed1at@ly

2.5.4

routine

arrives

sequence

at
of

SISR

PSL

(hex)

{hex)

stack
-

-0

8
8

0
8

0
0

8
9

88
88

0
8,0

9,8,0

S
8

88
88

8,0
0

5,0

° 8

immediately
service

IPL7 service routine REI
initial IPLS service routine
- REI back to IPLO and the
request for 3 1is granted

IPL3

IPL

software

event

response

then posts

REI

3
0

Exceptions

Most exception service routines
execute
at
IPL
0
1in
response
to
exception
conditions
<caused
by software.
A variation from this are
serious system failures, which raise the IPL to the highest level (1F,
hex)
to
minimize
processor
lnterruptlon
until
the
problem
1is
corrected.
Exception service routines
are
usually
coded
to
avoid
exceptions; hawever,’nested exceptions can occur.
A

trap

exception

condition

that

occurs

the

end

the

instruction
that caused the exueptlon.
Therefore the PC saved on the
stack 1s the address of the next instruction that would normally
have
been
executed.
Software
<can
enable
and
disable some of the trap
conditions with a single instruction.
|

ARCHITECTUR!

A fault 1s an exception condition that occurs during
an
instruction,
and
leaves
the
registers
and memory in a consistent state such that

elimination of the fault condition and restarting the instruction will
give correct results.
Note that faults do not always leave everything
as it was prior to the faulted instruction; they onlv
restore
enough
to allow restarting.
Thus, the state of a process that faults may not

be the same
point.

that mf

a process

that

was

1interrupted

the

same

An abort 1s an exception condition that occurs during an 1instruction,
leaving the value of registers
and memory unpredictable, such that the
instruction cannot
necessarily be
correctly
restarted,
completed,
simulated,
or
undone. After an instruction aborts, the PC addresses
the
opcode
of
the
aborted
instruction.
The
following
are

unpredictable:
)

’

destxnatlon operands (1nclud1ng 1mp11ed operands, such as
of -the stack in an JSB instruction)
‘

the

top

ng
by operand specifier | evaluation (includi
registers smodified
® specifier
|
for 1mplxed mperands)
@
-

the PTE<M> bit 1n PTES',that
map destination
operands,
1if
the
operands
could have been written but were not written, and PTE<M>
was

clear

before

condition codes

PSL<FPD>

PSL<TP>

the

instruction

Except where otherwise noted in the description of the abort,
of the PSL, other registers, and memory are unaffected.
The

MicroVAX

summarized

78032

CPU

in Table 2-9.

recognizes

six

types

the

rest

exceptions,

ARCHITECTURE

Table 2-9
exception class

Summary of

instances
W

arithmetic

integer overflow trap
integer divide by zero trap
subscript range trap
floating overflow fault
floating divide by zero fault
floating underflow fault

traps/faults

memory

Exceptions

management

exceptions

access control violation fault
translation not valid fault

operand reference
exceptions

reserved addressing mode

lnstruction
exceptions

reserved/privileged instruction fault
emulated instruction fault
extended function fault

execution

reserved

operand

breakpoint
tracing

exception

system failure
exceptions

~trace

fault or

abort

fault

memory read error abort
memory write error abort
kernel stack not valid abort

interrupt stack not
machine check abort

2.5.4.1

fault

Arithmetic Traps/Faults

valid

halt

The various exceptions that occur as the result of
an
arithmetic
or
conversion
operation are mutually exclusive and are assigned the same
vector 1n the SCB.
Each indicates
that
an
exception
had
occurred
during
the
instruction
and
last
that
the
1instruction
has
been
completed (trap)
or
backed
up
(fault).
A
code
wunique
to
each
exception
is then pushed on the stack as a longword.
The stack
type
after an arithmetic exception 1s shown 1in
Figure
2-32.
Table
2-10
lists the type codes.

ARCHITECTUR

TYPE CODE

:SP

PC OF NEXT INSTRUCTION TO EXECUTE®
PSL

*SAME AS THE INSTRUCTION CAUSING EXCEPTION IN CASE OF FAULT
MR-13394

Figure 2-32

Table 2-10
type

Stack After Arithmetic Exception

Arithmetic Exteptimn Type Codes

code

exception type

(hex)
|

TRAPS

1
2
7

integer overflow
integer divide by zero
subscript

range

FAULTS

9
A

2.5.4.1.1

floating overflow

floating divide by zero
floating underflow

Integer Overflow Trap

An integer overflow trap is an exception that indicates that the
last
instruction
executed
had an integer overflow setting the V condition
code and that integer overflow
was -enabled
(IV set).
The
result
stored
1is
the low-order
part of the correct result.
N and Z are set
accordin
to the
g stored result.
The type code pushed on the stack
1is
1.
Note
that the instructions
RET, REI, REMQUE, REMQHI, REMQTI, and
BISPSW do not cause overflow even if they set V.
Also note
that the
EMODx floating point instructions can cause integer overflow.

2-47

ARCHITECTURE

2.5.4.1.2

Integer

Divide

lnteger divide by zero

last
instruction
stored is equal to
code pushed on the

2.5.4.1.3

By ‘Zero

trap

Trap

1s an exceptlon

that

i1ndicates

that

the

executed
had
an integer zero divisor.
The result
the dividend and condition code V is set.
The type
stack is 2.
|

Subscript Range Trapfiw

A subscript range trap is an exception that indicates
that the
last
instruction was an
INDEX
instruction with a subscript operand that
failed the range check.
The value of the subscript operand
is
lower
than
the low operand or greater than the high operand.
The result is
stored in indexout,
and
the
<condition
<codes
are
set
as
if
+he
subscript were within range. The type code pushed on the stack is 7.

2.5.4.1.4

Floating

Overflow

- A floating overflow fault
instruction

executed

representable

exponent

Fault

is an exception that

resulted
for

the

exponent

data

type

indicates
greater

after

that

than

the

last

largest

normalization

and

rounding.
The
destination
was unaffected
and the saved condition
codes are unpredictable.
The
saved
PC
points
to
the
1instruction
causing the fault.
In the-case of a POLY instruction, the instruction
1s suspended with FPD set.
The type code pushed on the stack is 8.

2.5.4.1.5

Floating

A floating
the
last

divide

2.5.4.1.6

Floating Underflow Fault

Divide

By Zero

Fault

by zero fault is an
1instruction
executed
had

exception

that
1indicates
that
a
floating
zero divisor.
The
quotient operand was unaffected and
the
saved
condition
codes
are
unpredictable.
The
saved
PC
points to the instruction causxng the
fault.
The type code pushed on the stack 1is 9

A floating underflow fault is an exception
that
indicates
that
the
last
instruction
executed
resulted
in
an expone
less nt
than the
smallest representable exponent for the data type after
normalization
and
rounding
and that floating underflow was enabled (FU set).
The
destination operand is unaffected and the saved
condition
codes
are
unpredictable.
The
saved
PC
polnts to the instruction causing the
fault.
In
the
<case
of
a
POLY
1instruction,
the
instruction
1is
suspended with FPD set.
The type code pushed on the stack is 10.

2-418

ARCHITECTUR!
2.5.4.2

Memory Management Exceptions -

The two exceptions
that
occur
as
a
result
of
memory
management
operations - use
separate vectors
1n
the SCB but
push
the
same
information onto the stack.
The information pushed on
the
stack
1is
" called the fault parameter block and is shown in Figure 2-33.
The same parameters are stored in the fault parameter block

for

both

types
of
memory management fault.
The first parameter pushed on the
kernel stack after the PSL and PC is a virtual address that 1s located
in
the same page as the wvirtual address that caused the fault.
Note
that a process space reference can result in'a
system
space
virtual
reference

for
the
PTE.
If
the
reference
to the per-process PTE
faults, the virtual address that
1s saved
1s
the
process
virtual
address
and a 1l is stored in bit 1 of the fault parameter word.
The
second parameter pushed
on the kernel stack
s
the
fault
parameter
word and contains

information

related to

the type of memory management

violation, PTE reference, and type
of
memory
access
(read,
write,
etc.).
Table
2-11 gives a description of the bits used in the fault
parameter word.

|M| PlL

|:spP

SOME VIRTUAL ADDRESS IN THE FAULTING PAGE

PC OF FAULTING INSTRUCTION
PSL AT TIME OF FAULT
MRA-13420

Figure

2-33

Fault

Parameter Block

ARCHITECTURE

Table 2-11
Bit

Field

<31:03>

<2>

Fault Parameter Word Bit Descriptions

Descrlptlon

Unused.

Write or Modify
indicate
modify.
access

<1l>

that
This

was

that

the

process

- this bit

this bit
occurred

page

table
This bit

is set
during

Access
control

elther

length

can

set

indicate
to
virtual

with

the

associated

faults.

reference

the

Control

Violation

violation

fault

Fault

exception

indicating

that

the

attempted a referencqfiot allowed for the access mode at which

Translation Not

translation

process

to
the

the process was operating.
Software may
restart
changing the address translation information.

2.5.4.2.2

is set

intended access was a write or
is 0 1f the programs intended

Length Violation - this bit is set to 1 to indicate
that an Access Control Violation was the result of
a
length violation rather than a protection violation.
This bit is always 0 for a Translatlon Not Valid
Fault.

t’i

access

process

fault

address.
protection

2.5.4.2.1

read.

PTE Reference

<(0>

Intent

the
bit

not

valid

attempted a

Valid

fault

reference

Fault
an
a

the

process

after

exception

page

for

which

indicating
the

valid

page table was not set.
Note that if a process attempts to
a
page
for
which
the page table entry specifies both Not
Access Violation, an Access Control Violation Fault occurs.

that
bit

the
the

reference
Valid and

ARCHITECTURE

2.5.4.3

Operand Reference Exceptibns -

2.5.4.3.1

Reserved Addressing Mode Fault -

A reserved addressing mode fault is an exception
1indicating
that
an
operand specifier attempted to use an addressing mode that 1is not
allowed in the situation in which
1t
occurred.
No
parameters
are
pushed.

2.5.4.3.2

Reserved Operand Exceptlon -

A reserved operand exception 1indicates that an operand accessed has
a
format
reserved for future use by DIGITAL.
No parameters are pushed.
This exception always backs up the PC to point
to
the
opcode.
The
exception
service
routine
may
determine
the
type
of
operand by
examining the opcode using the stored PC.
Note that only the
changes
made
by instruction fetch and because of operand specifier evaluation
may be restored.
Therefore, some instructions
are
not
restartable.
These
exceptions are labeled as ABORTs rather than FAULTs.
The PC is
always restored properly unless the instruction attempted to modify it
in a manner that results in unpredictable results.

2.5.4.4

2.5.4.4.1

Instruction Execution Exceptions -

Reserved/Privileged Instruction Fault -

A reserved/privileged

instruction

fault

occurs

when

the

processor

encounters
an
opcode
that
is
not
specifically
defined,
or that
requires higher privileges than the current mode.
No
parameters
are
pushed.
Opcode FFFF (hex) will always fault.

2.5.4.4.2

Emulated Instruction Fault -

An emulated instruction fault occurs when an opcode that has microcode

assistance
for instruction emulation 1s encountered by the processor.
Section 4.12 describes microcode assistance for emulated instructions.

ARCHITECTURE

2.5.4.4.3
An

Extended

extended

user

(hex),

Function

instruction

executed.

which

stack.

2.5.4.4.4

fault

All

the XFC

Breakpoint

Fault

occurs

opcodes

instruction.

Fault

breakpoint fault is an exception
instruction (BPT) is executed.
No

proceed

restores

from
the

sets T 1n the
breakpointed
this
point,

instruction,
resume.

(i.e.,

PSL<T>

both

was set

trace
trace

Tracing

opcode

the

reserved

user

start

the

with

are pushed on

that
occurs
when
the
parameters are pushed.

PSL saved by the
BPT
instruction completes,
the
tracing
program
that

No parameters

debugger

contents

1its

the

tracing

location

the

breakpoint

program

and

the BPT),

normal

the

BPT,

When
the
occur. At
the
BPT

(usually clear),

breakpointing

time of
and

state

typically

containing

fault,
and
resumes.
a trace exception will
can
again
re-insert

original

tracing

both the BPT restoration
processed by the trace handler.

2.5.4.5

breakpoint,

restore

Note

.exception

original

when

reserved

trace

are

1in

then on

and

progress

the

exception

trace
should
~

trap

1s an exception that
occurs
between
instructions
when
enabled.
Tracing
1is
wused
for
tracing
programs,
for
performance evaluation, or debugging purposes.
It is designed so that
one
and
only one trace exception occurs before the execution of
each
traced instruction.
The saved PC on a trace is
the
address
of
the
next
instruction that
would normally be executed.
If a trace fault
and a memory management fault occur simultanecusly, the order
in which
the
exceptions
are
taken
1is unpredictable.
The trace fault for an

instruction

takes precedence over

all

ensure

one

order

that

exactly

other

trace

exceptions.
occurs

per

instruction

despite
other
traps
and
faults,
the
PSL contains two bits, trace
enable (T) and trace pending (TP).
Instead of the
PSL<T>
bit
being
defined
to
produce a trap after any other traps or aborts at the end
of an instruction, the trap effect is implemented by copying PSL<T>
to
a
second
bit (PSL<TP>)
that
1is
actually
used
to generate
exception.
PSL<TP> generates a fault before any other
processing
the start of the next instruction.

the
at

ARCHITECTUR!

2.5.4.6

System Failure Exceptions -

2.5.4.6.1

Kernel Stack Not Valid Abort -

‘Kernel stack not valid abort is an exception that indicates
that
the
kernel stack was not valid while the processor was pushing information
onto the kernel
stack
during
the
1nitiation
of
an
exception
or
interrupt.
Usually this is an indication of a stack overflow or other
executive software error. The attempted exception is transformed into
an
abort
that
uses
the
1interrupt
stack.
No extra information 1is
pushed on the interrupt stack
in addition to PSL and PC.
Bits
<1:0>

of
the
-exception
vector
should
be
1, if they are 0, 2, or 3, the
operation of the processor
1s
UNDEFINED.
Software
may
abort
the
process
without
aborting
the
system.
However, because of the lost
information, the process cannot be continued.
If the kernel stack
1is
not wvalid
during
the
normal execution of an instruction (including
CHMK or REI), the normal memory management fault 1s initiated.

2.5.4.6.2

Interrupt Stack Not Valid Halt

An interrupt stack not wvalid halt is an exception that indicates
that
the
interrupt
stack
was
not
valid while the processor was pushing
information onto

exception

the

interrupt

interrupt.

stack

during

further

the

1nitiation

interrupt

requests

are

_acknowledged.
The processor leaves the PC, the PSL, the ISP, and
the
reason
for
the
halt in privileged registers (SAVISP, SAVPC, SAVPSL)

and initiates the restart process,

2.5.4.6.3

see Section 2.8.

Machine Check And Memory Read/Write Error Abort

A machine check or memory read/write error abort
1indicates
that
the
processor
detected an internal error in itself or a memory read/write

bus error

be
equal
processor

(ERR asserted).

Bits <1:0> of

to 1l; 1f they are equal
1s UNDEFINED.

to 0,

the exception

The parameters pushed on the stack are shown

vector

should

the operation of

in Figure 2-34.

the

ARCHITECTURE

BYTE COUNT (000GO00C HEX)

'SP

MACHINE CHECK CODE

MOST RECENT VIRTUAL ADDRESS

INTERNAL STATE INFORMATION

PSL

MR 13395

Figure 2-34

Méchine Check Stack Parameters

ARCHITECTURE

parameters

are:

(hex):

impossible microcode state (FSD)
impossible microcode state (SSD)
undefined FPU error code O
undefined FPU error code 7
undefined memory management status

(LI

| N

IO | I

machine check code

The

(TB miss

]

| I

(M =

<28:24>
<23:20>
<19:16>

contents

(possibly

<7T:0>

<31:0>

<l4>

current

<31:0>

internal state
1information:

PC:

current

contents

current
current
current

contents
contents
contents

bit
delta PC at
PC

VAP

<31:0>

the

current

incremented by 4¢)

the

start

of
of
of
of

ATDL

time of
of

the

instruction
PSL:

status

flows)

virtual

]

process PTE address in PO space
process PTE address in Pl space
undefined interrupt ID code
read bus error, VAP 1is virtual address
read bus error, VAP s physical address
write bus error, VAP 1s virtual address
write bus error, VAP is physical address

most recent
address:

flows)

undefined memory management

contents

PSL

|
the exception
current

ARCHITECTURE

2.5.5

Contrast

Between

Exceptions

And

Interrupts

- Exceptions and interrupts are very similar.
When either is initiated,
both
the processor status longword (PSL) and the program counter (PC)
are
pushed
onto
the
stack.
However
there
are
seven
important
differences:
1.

An exception
instruction

computing

condition
while
an

system

that

instruction.

exception

process

that

serviced

is caused by the execution of
the
current
interrupt is caused by some activity in the

may

condition

produced

the

xndependently

1ndependent

usually

serviced

exception

from

the

of .

the

condition,

currently

the

current

context

while

running

the

interrupt

process.

The IPL of the processor 1s usually not changed when the processor
initiates
an
exception,
while
the IPL is always raised when an
interrupt is initiated.

Exceptxon service
while
1interrupt
stack.

routines
service

usually execute on
routines
normally

a per-process
execute

stack
per-CPU

Enabled exceptions are always initiated immediately no matter what

the
processor
IPL
processor IPL drops

1s,
while
1interrupts are held off until
below the IPL of the requesting interrupt.

Most exceptions can not be disabled.
causing
event
occurs
while
that
exception
1is
1initiated
for
that

subsequently.
whose

This

occurrence

However,

includes overflow which
indicated

exception
1is
event
even
condition

the

exception

disabled,
no
when
enabled

the only exception
code

(V).

kernel

interrupt
condition occurs while it is disabled, or the processor
ls at the same
or
higher
[IPL,
the
condition
will
eventually
lnitiate
an 1nterrupt when the proper enabling conditions are met
1f the condition is still present.
7.

The

mode

field

interrupt,
but
on
of the exception.

the

PSL

exception

always

indicates

set

the mode

the

time

ARCHITECTUR

2.5.6

Serialization Of Exceptions And Interrupts

The

sequence

interrupts

and

which

exceptions

recognition

takes

1is:

place

simultaneously

Machine

Arithmetic exceptions.

Console Halt

Interrupts
priority.

Trace

fault

Start

instruction execution or restart

2.5.7
The

occurring

check exception.

higher

priority

(only one per

(IPL)
”

than

the

<current

processor

instruction).
suspended

instruction.

Initiate Exception Or Interrupt

following

78032

CPU

description of
Sec*Lon 4.1.3.

operation describes
when

the

1nitlating

notation

used

the

action

taken

exception

to describe

the

interrupt.

the

operation

MicroVax
For

refer

Operatlon:

tThe notation PSL<xxx>
SP 1s used to refer
'to
'in

the SP appropriate
the PSL.

the mode

xxx

specified

{disable interrupts};
|
tmpl <- SCB(vector];
!get
if tmpl<l:0> EQLU 3 then {UNDEFINED};
if tmpl<l:0> EQLU O AND {machine check or

correct

vector

kernel stack not valid}! then {UNDEFINED}:
if tmpl<l:0> NEQU 0 AND {CHMx} then {UNDEFINED};
if tmpl<l:0> EQLU
2 then {UNDEFINED};
if PSL<IS> EQLU 0 then~
!switch stacks
|
begin
PSL<CUR_MOD> SP

SP;

1f tmpl<l 0>EQLU 1l then
|

end;
tmp2

else
SP <-

!'save

old

ISP;

|
new _mode
SP;

'kernel

unless

PSL;

PSL<CM,TP,FPD,DV,FU, IV T,N,Z2,V,C>

!cleanout

PSL

t hen

PSL<PRV_MOD>

'kernel
|

{1nterrupt}

mode

CHMx

ARCHITECTURE

else
PSL<PRV_MOD>
PSL<CUR_MOD>

-(SP)

PSL<CUR

MOD>;

<- new_mode;

'kernel

<- tmp2;

'on a

-(SP) <- PC;
{push parameters

any};

mocde

unless

CHMx

fault or abort,

the

!'saved condition codes are
lunpredictable as backed up

!'if

necessary

'1f

kernel

stack not

valid

lexception occurs while
'pushing

tmp2,

!parameters

{interrupt}

other

!'PSL <- tmp2 before
initlating exception

then

PSL<IPL>

PC,

then

new_ IPL

else
1f tmpl<1l:0>

!set

new

IPL

EQLU

PSL<IPL>

then

31;

1f tmplfil 0> EQLU 1 then PSL<IS>
PC <- tmpl<3l:2> ' 0<1l:0>;

{enable interrupts};
if {PSL<IPL> LEQU 15}

AND

SISR<PSL<IPL>>

'1F

(hex)

'otherwise keep old
'longword aligned

{PSL<IPL> GEQU

(;

!clear

then
SISR

bit for

!software interrupt
!being initiated

Condition Codes
N
vV

<<<-

0;
0;
0;

(1f

vector<l:0>

code

1):

Exceptions:

interrupt
kernel

stack

not

valid halt

valid

abort

Description:

The handling is determined by the contents of a longword vector in the
system
control
block
which 1s indexed by the exception or lnterrupt
being processed.
If the processor is not executing on
the
interrupt
stack,
then
the
current
stack
pointer
1s saved and the new stack
pointer 1s fetched.
The old PSL is pushed onto the new stack.
The PC
1s
backed
up
(unless this is an interrupt between instructions or a
trap) and 1s pushed onto the new stack.
The PSL is
set
to
a
xnown
state.
IPL
1s
changed
1f
this
1s
an
1interrupt
or if it is an
exception with vector<l:0> code 1.
Any parameters are pushed.
Zxcept
for
1i1nterrupts,
the
previous
mode 1n the new PSL 1s set to the old
value

longword

the

current

indicated

mode.

Finally,

the

vector<3l:2>.

2-58

the

changed

point

the

ARCHITECTUR

Notes:

Interrupts are disabled during

the vector<l:0>

code

1is

invalid,

the behavior

undefined.

On
a
fault
or
1interrupt,
the
saved
condition
unpredictable;
they
are
only
saved
to the extent

ensure correct completion of
4.

this segquence.

After

abort,

the

following

codes
are
necessary to

instruction when resumed.

are unpredictable:

a.
|

Destination operands, including implied operands
top of the stack during a JSR instruction.

Registers modified by operand specifier evaluation,

Condition codes.

PSL<FPD>,

PSL<TP>,

- f.

registers modified

referencing

such

implied operands.

including

The page table entry Modify bit for
pages
mapping
write
modify type
operands.
The
Modify
bit
will be set if
instruction modified the page.
If
the
1instruction
did
modify the page, the Modify bit is unpredictable.

After
an
abort,
the
PC
instruction
which aborted,
in
a
way that
produces
registers,
other
bits
of
unaffected by an abort.

the

or
the
not

pushed
on
the
stack
addresses
the
unless the instruction modified the PC
unpredictable
results.
The
other
the
PSL,
and the rest of memory are
.

5. After an abort or fault or interrupt that pushes a
PSL
with
FPD
set, the general registers except PC, SP, and FP are unpredictable
unless the instruction description specifies a setting.
If FP
is
the destination in this case, then it is also unpredictable.
On a
kernel stack not valid abort, both SP and FP are unpredictable.
6.

If the processor gets an Access Control Violation or a Translation
Not Valid
condition
while attempting to push information on the
kernel stack, a kernel stack not valid abort
1is
initiated.
The
additional
1information,
1if
any,
associated with
the original
exception is lost.
However, the PSL and
PC
are
pushed
on
the
interrupt
stack with the same values
the kernel stack,
and
the
IPL
1s
vector<l:0>
for
the
kernel
stack

operation

the

processor

as would have been pushed on
changed
to
1F
(hex).
If
not
wvalid
abort
1is Q, the
undefined.

2-59

ARCHITECTURE

If the processor gets an Access Control Violation or a Translation
Not

valid

ISP,

PC,

while

condition

interrupt stack,
and

attempting

the processor

PSL

to push

information on

1s halted and only the state of

1s ensured to be correct.

The

PSL

and

the

have

the values that would have been pushed
on the interrupt stack.

The value of PSL<TP> that is saved on the stack is as follows:
clear
clear

fault
trace

clear (1f FPD set)
from PSL<TP> (if after
traps, before trace)
unpredictable

interrupt

abort
CHMx
BPT,b XFC

from PSL<TP>
from PSL<TP>
clear

reserved
instruction

clear

trap

The value of
following:

fault
trace

interrupt
abort

trap

CHMx
BPT,

XFC

reserved
instruction

that

1is

saved

the

stack

points

instruction faulting
next 1nstruction to execute
i.e., instruction at the beginning
of which the trace fault was taken
instruction interrupted or
next instruction to execute
instruction aborting or
detecting kernel stack not wvalid
(not ensured on machine check)
next instruction to execute
next lnstruction to execute
BPT, XFC instruction

reserved

lnstruction

the

ARCHITECTUR

2.5.8
-

System Control

Block

The System Control Block 1is
exceptions
and
interrupts
routines.

2.5.8.1

(SCB)
a

table contalnlnq
are dispatched to

the
wvectors .by
which
the appropriate service

System Control Block Base (SCBB) -

The SCBB 1s a privileged register containing the phy51cal address
the System Control Block, which must be page-aligned, Figure 2-35,

313029

09 08

e
r e rrrrrrrryrrrrrrrrorirrrd

Imsz|
N

PHYSICAL LONGWORD ADDRESS
OF SCB
N

NN N

VNN DT UOE UO AN T

NN N

MBZ
N

| -SCBB

MR 11818

- Figure

2.5.8.2

Vectors

A vector

an
exception
event.
Table

2-35

System Control

Base

longword

or
2-12

the

SCB

that

interrupt
occurs
lists the vectors

exceptions.

Bits

<1:0>

used

interrupting
of

the

vector

Service this event on the kernel stack unless
the lnterrupt stack, in which case service on

Service this event on
exception, the IPL is

This code
process,

results
see

the

processor

to
determine how to
contained in the SCB.

Separate vectors are defined for each

class
of
follows:

Block

the interrupt stack.
raised to lF (hex).

This code results in
process, see Section

this

Z2.8.

the MlcroVAx
2.8.

2-61

78032

CPU

and

each

interpreted

already running on
the interrupt stack.

1n the MicroVAX 78032 CPU enterlnq

Section

the

device
are

when

service

entering

event

the

restart

the

restart

ARCHITECTURE

Table

2-12

System Control

Block

Vectors

Vector

(hex)

Name

Q0
unused 04
machine check
|
08
~
kernel stack not wvalid
0C
power fail
10
reserved/privileged instruction
14
extended instruction
!
18
reserved operand
1C
reserved addressing mode
20
access control violation
24
~ translation not valid
)
28
trace pending (TP)
2C
breakpoint instruction
30
unused
34
arithmetic
38-3C
unused
@
40
CHMK
14

48
1C
50-80
84
88
8C
90CO
C4
C8
CC

DO-FC

CHME

abort
abort
interrupt
=

faulc/abort
fault
fault
fault
faultfault
-

trap/fault
-

trap

‘

CHMS

unused

trap

trap
trap

interrupt
ilnterrupt
lnterrupt
lnterrupt
interrupt
-

level 1
level 2
level 3
levels 4-15
timer

unused

emulation
emulation

fault
fault

CHMU

unused
software
software
software
software
interval

Type

start
continue

100-1FC adapter vectors*
200-3FC device vectors*
mmmmmmmmmmmmwmmmmwmmammm

fault
fault

Interrupt
interrupt

mwwmmwwmmwmmmmmmmmmwm“ww

—wmmmmm

*Used by the
MicroVAX 78032 CPU
to
directly vector
interrupts
from
the
external
bus.
The
vector is
determined
from
bits <9:2> of the value supplied by
external hardware.
If
Dbit <0>
of
this value is 0,
then the new IPL is
forced to 17 (hex).
Only device
vectors
1n
the
range of 100 to 3FC (hex) should be
used.
Except
Dby
devices emulating console storage
and terminal devices.

ARCHITECTUR!

PROCESS STRUCTURE

2.6

A process 1s the basic entity that may be scheduled

the

MicroVax

78032 CPU.
It consists of an address space, a hardware context, and a
"software context.
The hardware :-ontext 1s defined by a data structure
called
the
process
control block (PCB), which contains images of 14
general registers, the processor status longword
(PSL),
the
program
counter (PC), the four per-process stack pointers, the process virtual
memory deflned by the base and length registers (P0OBR, POLR, P1BR, and
P1LR),
and
several
minor
control
fields.
When
a process 1s not
executing, its hardware context
1s
stored
1n
the
process
control
block.
In
order
for
a process to execute, the majority
of the PCB
must be moved into processor reglsters:
while
a
process
1is
being
executed,
some
of
1ts
hardware
context
1s
being
updated in the
processor reglsters.
|
|
Saving the contents of the privileged registers
1in
the
PCB
of
the
currently executing process and then loading a new set of context in
the privileged registers from another PCB is termed context switching.
Context switching occurs as one process after anmther ls scheduled for
execution,

2.6.1

Process-. Context

The process control block

for

the

currently

executing

process

1is

pcinted
to
by
the contents of the process control block base (PCBB)
register, an internal privileged register, which rmntalns the physical
address of the PCB.
Figure 2-36 shows the PCBB register.
The process
context

control

collected

block contains

into

compact

all of

form

the

for ease

switchable

movement

process
and

from

the privileged internal registers.
Although in any
normal
operating
system
there
s
additional
software
context for each process, the
following description is limited to that portion of the the PCB
known
to
the
hardware.
Figure 2-37 shows the PCB and Table 2-13 describes
1ts

contents,

313029
LI

MBZ

020100

PHYSICAL LONGWORD ADDRESS OF PCB

msz|

:PcsB

O
MA-11820

Figure

2-36

Process Control

Block Base

2-63

(PCBB)

ARCHITECTURE

00
KSP

:PCB

ESP

SSP

usP

+12

+16

+20

| R2

+24

+28

+32

+36

+40

+44

+48

+52

R10

R11

+60

AP (R12)

+64

FP (R13)

+68

+72

PSL

+76

POBR

MBZ

AST T vz
-

PME

+56

‘

+80

POLR

+84

P1BR

MB8Z

+88

P1LR

+92

NOTE: THE PME FIELD IS UNUSED.
MR-11619

Figure

2-37

Process

Control

Block

(PCB)

ARCHITECTURE

Table 2-13
Longword

Bits

Description of Process Control Block

Mnemonic

<31:0>

KSP

- Description

Kernel Stack Pointer.
stack

pointer

Dbe

current access mode
is

and IS

<31:0>

ESP

- <31:0>

SSP

<31:0>

USP

<31:0>

RO-R11,

General

AP,FP

AP,

4-17

Executive

Contains

used when

field

in the

the
the

PSL

Stack

Pointer,

Contains

Supervisor Stack

Pointer.

Contailns

the stack pointer to be used when
current access mode field in the

the
PSL

the stack pointer to be used when
current access mode field in the
1s 2.
|

the
PSL

User

the

Stack

Pointer.

Contains

registers RO

through R11,

'stack
pointer
to
be
used when the
current access mode field in the
PSL
1s 3.

FP.

<31:0>

Program Counter,

<31:0>

PSL

Program Status Longword.

<31:0>

POBR

Base

reglister

describing
from

for

page

process virtual

2**30-1.

<21:0>

POLR

Length

<23:22>

MBZ

Must be

zero.

for

page

located by POBR.
Describes
length of page table.

2-65

table

addresses

table

effective

ARCHITECTURE
Table

' Longword

2-13

Description

Bits

Mnemonic

Process

Control

Block

Description

mmmmmmwmmflmmmmmmw

wwwmwmmmmmew%mwwmm

<26:24>

(Continued)

wwmmmwwwmwmmmwmm—-

ASTLVL

“Mw%mmm~mmmmmmmmm

Contains

access

mode

(established by software)

number

the most

privileged access mode for
which
an
Asynchronous
System
Trap
(AST)
.is
pending.
Controls the triggering
of
the AST delivery interrupt during REI
.
lnstructions.
ASTLVL

Meaning

AST
mode

pending
for
0 (kernel)

access

AST

pending

access

mode

3
|

for

(executive)

AST
mode

pending
for
2 (supervisor)

access

AST

pending

mode

access

for

(user)

5-7

Reserved

pending

AST

DIGITAL

<31:27>

MBZ

Must

<31:0>

P1BR

Base
reglister
for
page
table
describing
process virtual addresses
from 2**30 to 2**31-1.

<21:0>

PlLR

Length

zero.

for

page

located by P1BR.
Describes
length of page table.

<30:22>

MBZ

Must

<31>

PME

Unused.

2-66

zero.

table

effective

ARCHITECTURE

A process must be executing

in kernel mode to alter

1its

POBR,

PI1BR,

POLR,
PIlLR,
or ASTLVL.
It must first store the desired new value in
the memory image
of the PCB then move the
value
to
the
appropriate
privileged
register.
This protocol results from the fact that these
are read-only fields (for the context switch 1instructions) in the PCB.
The ASTLVL field of the PCB is contained
1n
a
processor
privileged
register when the process is running.
Figure 2-38 shows the format of
the AST Level Register.

731

0302
NI U

D
D O N

IGNORED; RETURNS 0
T O
Y N A O Y N

”
O

ASTAl

(READ/WRITE)
MR-13392

Figure

2.6.2

2-38

Asynchronous System Traps

AST

Level

(AST)

Asynchronous system -traps are a technique for notifying a

process

events
that are
not
synchronized with its execution and initiating
processing for asynchronous events
with
the
least
possible
delay.
This
delay
1in
delivery
of
the
AST may
be due to either process
non-residence or an access mode mismatch.,
The efficient handling of
AST's
requires
some
hardware assistance to detect changes in access
mode (current access mode in PSL).
A
process
1in
any
of
the
four

execution
access
modes (kernel, executive, supervisor, and user) may
receive AST's; however, an AST for a less privileged access mode
must
not
be
permitted
to
interrupt execution in a more protected access
mode.
Since outward access mode transitions occur
only
1in
the
REI
instruction,

comparison of

the current

access mode

field

is made with

a privileged register (ASTLVL) containing the most
privileged
access
mode
number
for
which an AST 1s pending.
If the new access mode 1is
greater than or equal
to
the pending
ASTLVL,
an
IPL
2
software
interrupt is triggered to cause delivery of the pending AST.

2-67

- ARCHITECTURE

2.6.3

Process

Two

the

process

They

Structure

software

?tructure

Interrupts

interrupt

priority

levels

software.

are

reserved

REI

that

for

are:

(IPL
2) - AST delivery interrupt.
This

interrupt

PSL<CUR_MOD>
AST

may

now

1is

GEQU
be

triggered
ASTLVL

and

delivered

for

indicates
the

currently

process.

(IPL 3)

that

detects

pending

executing

- Process scheduling

interrupt.

This

interrupt is only triggered by software to allow
the software running at IPL3
to
cause the currently
executing
process
to
be
blocked
and
the highest
priority executable process to be scheduled.

2.7

STACKS

Stacks,

also

important

used for:

Saving

the

subroutine,

e
e

called

pushdown

feature of

lists

the MicroVAX

last-in/first-out

78032

CPU's

queues,

architecture.

general

for

Saving PC, PSL,
and exceptions,

registers,

restoration

1including

exit.

and general registers at the
and during context switches.

C(Creating storage space
recursive routines.

for

temporary

use,

PC,

time

for

any time, the processor is either in a process context
four
access modes (kernel, executive, supervisor, or
interrupt stack bit (IS) of
the
PSL
=
0)
or
1in
the

interrupt

privileges.
these
five

(R14)

service

context

(IS

There is
a stack pointer
states.
Any
time
the

stored

the process

context

that

operates

(SP)
associated
processor changes

stack pointer

for

entry
of

At
of

are

They

are

interrupts

nesting

and
user

in
and

one
the
system-wide

with

kernel

with
each
states, the

the

old

of
SP

state

and
loaded from the one for the new state.
The process context stack
pointers (KSP=kernel, ESP=executive, SSP=supervisor, and USP=user
) are
stored in the hardware PCB with a copy of the current stack pointer 1n
the SP (R14) register.
The
stack
pointer
values
1in
the
PCB
are
accessed

whenever

stack

pointer

2-68

switched.

ARCHITECTURE

2.7.1

Stack Residency

resident
. The user, supervisor, and executive stacks do not need to be
stack
process
allocate
or
in
bring
can
kernel
The
memory.
physical
in

pages as address translation not valid

faults

occur.

However,

the

kernel stack for the current process and-the interrupt stack (which is
‘
process independent) must be resident and accessible.

Translation not valid and access control violation faults occurring on
references
to
either
the
kernel
or
interrupt
stack
are serious
failures from which recovery is impossible.
1If either of these faults
occur
on a
reference
to the kernel stack, the processor aborts the
current sequence and initiates a kernel stack
not
valid abort.
If
either of
these
faults occur
on a reference to the interrupt stack,
the processor halts.

2.7.2

Stack Alignment

- Except on CALLx instructions, the hardware makes no attempt
to
align
the
stacks.
For
best
performance the stack should be aligned on a
longword boundary and allocated in longword increments.

'2.7.3

Stack Status Bits

The interrupt stack bit (IS) and current mode bits
status

longword

currently

(PSL)

in use as given

specify

which

in Table 2-14.

the

processor

of the five stack pointers is

The processor does not allow the current
mode
to
be
non-zero
when
IS = 1.
This
1s
achieved by clearing the mode bits of the PSL when
taking an interrupt or exception, and by causing
a
reserved operand

fault

return from exception or interrupt

(REI) attempts to load a

PSL in which both IS and the current mode are non-zero.
Table 2-14

Stack Pointer Selection

mmw“mmmmmmw“wmmmmmm“ww

1
0
0

Q*
0
1

ISP
KSP
ESP

0
0

2
3

SSP
USP

*Hardware will only allow a mode of 0 when the
2-69

ISP 1s selected.

ARCHITECTURE

The stack to be used when
servicing
an
interrupt
or
exception
selected
by
the
IS bit of the PSL and the contents of bits <1:0>
the vector for the service routine as shown in Figure 2-39.

is
of

VECTOR <1:0>=

0 I KSP l ISP l

PSL<IS>

: | ISP

l ISP I
MR-13363

Figure

2.7.4

Accessing

The MicroVAX
access

specified
process

lists

78032
each

stack
stack

instructions
Block

Base

the

Stack

CPU

implements
even

pointers

the

Table

are

and

2-15

the

their

Stack

the

Pointer

mode.
PCB,

This means,

contain

valid

Pointer

Because

the

per

the

and

MFPR

MTPR

Process Control

ISP

1
2
3

Table

Registers

allow

access

address.

KSP
ESP
SSP
USP

always

the

related privileged

Mnemonic

Stack Pointer
Executlve Stack Pointer
Supervisor Stack Pointer
User Stack Pointer

registers

current

PCB.

must

Kernel

Stack

privileged

stored

Stack Pointer

Interrupt

Selection

These

for

hardware

(PCBB)

pointers

pointer,

stack

Stack

Registers

stack

access

2-39

2-15

ARCHITECTURE

RESTART PROCESS

2.8

' The Restart process of the MicroVAX 78032 CPU is initiated when one of
|

the

following happens.

The

The HALT pin is asserted.

A HALT instruction is executed with the processor
in kernel mode.

The hardware

1s asserted.

kernel software

environment

becomes

corrupted.

severely

The restart process saves the current values of the PC, PSL, lnterrupt
stack
pointer,
MAPEN<(O>, and the restart code, 1n 1internal processor
registers:
SAVISP, SAVPC, and SAVPSL.
See
Section
2.3.3.2
for
a
description of these registers.
NOTE

SAVISP, SAVPC, and SAVPSL are
limited
1life
1internal
processor registers and must be saved in memory before
re-enabling the memory management unit
or
using
any
emulated

The

instructions.

restart process sets the state of

proc reg SAVISP

proc

reg SAVPC

proc reg SAVPSL

saved

the processor as

follows:

interrupt stack pointer

saved PC

saved PSL<31:16,7:0>
saved MAPEN<0O>
saved restart code

in SAVPSL<31:16,7:0>
in SAVPSL<15>
in SAVPSL<14:8>

stack pointer at time of restart

PSL
PC

(NOT stack pointer specxfled by PSL<26:24>)
= (041F0000 (hex)
=
20040000 (hex)

ICCS
SISR
ASTLVL

=
=
=

MAPEN

all else

After setting

0
(reset only)
0
(reset only)
4
(reset only)
undef ined

the state of

the

processor

the

restart

process

will

start
executing
user
code
at physical address 20040000 (hex).
The
code there can execute MFPR's to read the saved PC, PSL and
1nterrupt
stack
pointer,
establish a new interrupt stack and start the console
routine.
Since memory management 1s disabled, and the current mode of
the

processor

1is

kernel,

the console
2-71

routine has

full privileges

ARCHITECTURE

examine

and or

console

modify

the

internal

routine
may require an area
variables.
The console routine entry

the

The

following

sections.

reason

for

entering

that

saved

code

restart

code

and

exit

the

processor,

memory for scratch
protocols are described

restart process is given
by
SAVPSL<14:8>.
Table 2-16 gives

2-16

Restart

The

good

the

restart

list

the

Codes

condition

2
3

HALT asserted
initial power on,

interrupt

stack

V
|
RESET asserted

not

valid

during

3
00 ~Jd ]

machine check during machine
not valid exception
HALT instruction executed in
SCB vector bits<l:0> = 11
SCB

ACV

—

CHMx
ACV

2.8.1
The

known

the

codes.

Table

state
of

Console

console

internal
state

must

Save
USP

Entry

the

entered

TNV

limited

during

with

kernel

stack

the

state

Because

these

valid

for

enable

until these
for console

current

stack

mode

not

valid

exception

Protocol

processor
careful
not

Save the
SAVISP,.

kernel

bits<l:0> = 10
executed while on interrupt stack
or TNV during machine check exception

the

vector

registers.

instructions
the protocol

swap

exception

check

are

the

stack

life

saved

registers

1in

the

a limited
time
only.
The
wuser
memory management or use any emulated

registers are moved
entry is as follows:

1life

processor

limited

1internal

pointer.

registers

This

1f necessary, that is, store
of the current process contrcl

isvdone

the SP
block.

memory.

SAVPC,

to
the

Therefore,

SAVPSL,

complete
KSP,

ESP,

and

stack
SSP,

stack swap needs to
be
performed
if
the
Drocessor
was
running on
the
interrupt
stack
when
the
restart process
entered.
This is
because
the
MicroVAX
78032
CPU
stores
non-interrupt
stack
pointers
in
the PCB.
If the IS bit of
saved PSL 1s clear (=0), the console
routine
must
complete

2-72

not
was
the
the
the

ARCHITECTUR

stack
swap
Dby storing the saved value of SP into the appropriate
location of the PCB, if one exists.
The location in the PCB
that
the
SP
1s
to be Stored in is determined by the CUR MOD field of
the saved PSL.
If the IS bit of the saved
PSL
1is
set
(=1),
a
stack

swap does

not

have

be performed.

Set up the console stack pointer.

Begin

the

console

routine.

A typical console entry
Appendix C of

2.8.2

this

Console

user's

Exit

routine

and

guide.

description

can

found in

Protocol

Exiting from the console depends on two things:
1.

If memory management is to be enabled, the
environment
to
which
the
console is exiting must have a valldly mapped 1nterrupt stack
with at least two spare
longwords
at
the
bottom.
The
user's
console
code
will
have
to verlfy this by sxmulatlng the memory

management

resident
stack 1s
2.

process,

thereby

proving

The REI which restores the PC
longword
that
contains
the
- the MAPEN register.

The

protocol

for

Push

saved

the

interrupt

exiting

stack.

from

and PSL

Enable memory mapping,

Exit

via

that

the

interrupt

and
points
to valid physical memory.
If the
not valid, the exit sequence must be aborted.

the

onto

stack

interrupt

and PSL must be in the same phy51cal
instruction that sets the MME bit 1in

console

the

(mapped)

follows:

bottom

the

“

SAVED

appropriate.

REI,.

A typical consocle exit routine with memory management
be found in Appendix C of this user's guide.

simulation

can

CHAPTER

INSTRUCTION FORMAT AND ADDRESSING MODES

3.1

INSTRUCTION FORMAT

The VAX
may
be

1nstruction set has a variable length instruction format which
as
short
as one byte and as long as needed dependlng on the
type of instruction.
The general format of a VAX instruction is shown
in
Figure
3-1.
Each instruction is made up of an opcode followed by
zero to six operand
specifiers.
The
number
and
type
of
operand
specifiers
1is dependent on the opcode.
All operand specifiers are of
the same format, an address mode plus additional information wused
to
locate
the
operand.
This additional information contains up to two
register designatmrs
and addresses,
data,
or
displacements.
The
operand
usage
1s determined implicitly from the cpcmde and 1s called
the operand type.
It includes both the access type and the data type.

OPCODE (1 OR 2BYTES)

OPERAND SPECIFIER 1

OPERAND SPECIFIER 2

) )

{

B
AR
b

{

—"

OPERAND SPECIFIER 3

OPERAND SPECIFIER 6

MR-11601

Figure 3-1

MicroVAX Instruction Format
3-1

INSTRUCTION

3-1.1

FORMAT

AND

ADDRESSING

MODES

Assembler Radix Notation

The radix of the assembler
1is
number
1in assembler notation,

~“X.

For

example,

the

"MOVW #3456,-(SP)" as
a hexadecimal number,

3.1.2

Operating

Each
VAX
specifies

decimal.
To
it is required

assembler

(hex).

Figure

}

|
‘

]

OPCODE

|
|

|
}

operating
code
(opcode)
which
be performed.
The opcode may be
the

TWO BYTE OPCODE:

3456

contents
of
the
byte
long if the value of the byte
shows the opcode format.

3-2

ONE BYTE OPCODE:

‘

the

Code

1nstruction
contains
an
the
desired
operation to

lnterprets

a decimal number.
If it is to be interpreted
it would be written "MOVW '#°X3456,-(SP)".

one or two bytes long, depending
on
address
A.
The opcode 1s two bytes

address A

express
a
hexadecimal
to precede the number by

]

OPCODE
|

]

}

{

FD
-

MA-11802

Figure

3-2

Opcode

Formats

at
at

INSTRUCTION FORMAT AND ADDRESSING MODE:
3.1.3

Operand Type

The
operand
type
specifies
how
the
operand
asscciated
with
an
instruction 1is used.
Information prqvided~by the opcode includes the
~data type of each operand and how 1t 1s accessed.

Anoperand may be accessed in one of 6 ways.
1.

Read - The specified operand is read-only.

Write

Modify - The
modified, and

Address - Address calculation occurs until the actual
address of
the
operand
1s obtained.
In this mode, the data type 1indicates
the operand size to be used in address calculation.
The specified
operand is not accessed directly, although the instruction may use
the address to access that operand.

Variable bit field base address - If just R[n] is
specified,
the
field
1is in general register R[n] or in R[(n+l1]'Rn, that is R[n+1]
concatenated with
R(n].
Otherwise
address
calculation
occurs

- The

specified operand

1s write-only.

specified
operand
1s written.

read,

may

until the actual address of the operand is obtained.
specifies the
base
to
which
the
field
position
applied.

3.2

may

not

This address
(offset)
1is

Branch - No operand is accessed.
The operand
specifier
1is
the
branch displacement.
In this specifier, the data type indicates
the size of the branch displacement.

ADDRESSING MODES

Addressing modes can be divided into
two
mode
addressing
and
branch addressing.
modes 1s given in Table 3-1 and Table 3-2.
follows.

3-3

basic
categories,
general
A summary of the addressing
A description of each mode

INSTRUCTICN

FORMAT

AND

Table 3-1
-

ADDRESSING MODES

Summary of General Register Addressing Modes

Mode

(hex)

Name

0-3

literal

Assembler

Notation

index

S~#literal
i[Rx]

autodecrement

3
9

autoincrement
autoincrement
deferred
w

byte displacement
byte displacement
deferred

word displacement

word

deferred

displacement

longword displacement
longword displacement

deferred

rmw a v

yyyyy

deferred
E

Access

Indexable

yyyfy

(Rn)

VYV

(Rn) +
3(Rn)+
|
B~d(Rn)
@B”~d(Rn)

Y
Yy

YYVYY
VY YY
|

P
P

¥y
y

ux
ux

Y Y
YY
|

D
4
PV

W~d(Rn)

@W~d(Rn)

YYYYY

L~d(Rn)

YYVYY

@L~d(Rn)

YYYY

mmmwmmmmmmmmmmme~mmnmm

Assembler

Notation

modify
write

a
v

1
d
Rn

address
field

Rx
B

=
=

general
byte

word

longword

read

Results:

=
=

yes,

f
-

=
=

reserved address mode
logically impossible

program

u
ug

=
=

unpredictable
unpredictable for quad, D/G_floating,
or field if pos + size > 32
unpredictable 1f index reg = base reg

always

valid

counter

address

mode

fault

addressing

3-4

Syntax:

any 1indexable address
displacement
general register, n =

wmmmmmmwmmmm

Legend

r
=
m
=
W=

mmmmd&mmmmmm-mmmwm»fl“

Access:

=
o=

-(Rn)

mmmmmwmmmwwmmMmmmmmmwm

Addressan

mode

0
0

to
to

15
14

‘

INSTRUCTION FORMAT AND ADDRESSING MODES
4

Table

3-2

Summary of

Program Counter

Assembler

Mode

Name

8
>
A
B

C
D

5
F

Immediate
|
absolute
byte relative
byte relative
deferred
|
word relative
word relative
|
deferred
longword relative
longword relative
deferred

AddreSSLng
-

-~
-

Access

Notation

rmwa v

indexable

I"~#constant
¢#address
B~address
éB"~address

Yy
Y
Y
Y

U Uuyy
VYVYY
YVY VY
Y YV Y

Y
¥y
y
%

|
W~address
W~address

Y Y Y VY Y
Y Y YYY

¥
4

L~address
L~address

Y Y Y VY Y
Y YYVYY

Yy
%

Legend

Access:

r
m

Addressing Modes

Assembler

read
modify

=
=
o=

write

=
=
=

a
v

=
o=

address
field

Rx
B

=
=

word

longword

1
d

Notation

any indexable
displacement
general

yes,

reserved

valid address mode

p
u
ug

=
=
=
=

logically impossible
program counter addressing
unpredictable
unpredictable for quad, D/G_floating,
or field if pos + size > 32
unpredictable 1f 1ndex reg = base reg

address

mode

fault

3-5

address mode

~general
byte

Results:

always

Syntax:

INSTRUCTION

3.2.1

FCRMAT

AND

ADDRESSING

MCDES

General Mode Addressing

3.2.1.1

General

The general register address modes use one
or
more
of
the
general
registers,
depending on the instruction and data type, to contain the
operand(s) or information required to 'locate the operand(s) to be used
by the specified instruction.
Register

Assembler

Mode

(Figure

Syntax:

3-3)

Specifier:

MR-13642

The operand is the contents of register n (or
R{n+1]

concatenated with Rn

D floating,
Operand

Figure

3-3

and

certain

for gquadword,

field

operations):
'!1f

R{(n+1]'Rn

!if

Operand

one

two

Specifier

registers

Format

Description:
With

Since

they are

mode, any
and
the

hardware

speed
advantages
varlables.

when

the

operand

general
is

registers may be used
contained in the selected

reglisters within
wused

for

the processor,

operating

they

freguently

as simple
register.

provide
accessed

Special Comments:
This mode can be used with operand specifiers
using
read,
write
or
modify
access
but
cannot
be
used
with
the
address access type;
otherwise, an illegal addressing
mode
fault
results.
The
program
counter
(PC)
cannot
be
wused
1in this mode.
1If the PC is read, che
-

3-6

INSTRUCTION

value

is unpredictable;

executed

if the PC is

written,

FORMAT

the

AND

the next operand specified is unpredictable.

ADDRESSING

1instruction

Similarly,

if PC is used in register mode for a write-access operand which
two adjacent registers, the contents of RO are unpredictable.

takes

The stack pointer (SP) cannot be used in
this
mode
for
an
operand
which
takes
two
adjacent
registérs since that would imply a direct
reference to the PC and the results are unpredictable.

MODE:

INSTRUCTIOfi FORMAT 'AND ADDRESSING MCDES
Example:

Instruction

Format:

MOVE WORD

INSTRUCTION

MOVW R1,R2

Instruction moves

data

from

l6-bit

word

R2.

BEFORE INSTRUCTION EXECUTION

‘

clotalol3zlal]li]2

olJojJolojlolololo

AFTER INSTRUCTION EXECUTION

COA03|4

1|2

Ojojolo

3141} 1

MACHINE CODE: ASSUME STARTING LOCATIONOOOO 3000
00003000

OPCODE FOR MOVE WORD INSTRUCTION

00003001

OPERAND SPECIFIER, SOURCE: REGISTER MODE 1

00003002

OPERAND SPECIFIER, DESTINATION: REGISTER MODE 2
MR-13399

Figure

This

example,

Figure

mode.

The

content

causes

the

significant

least

half

3-4,

3-4

MOVW R1,R2

shows

Move Word

a Move Word

instruction

using

of Rl is the operand.
The Move Word instruction
significant half of Rl to be transferred to the least

R2.

The

3-8

upper

half

unaffected.

INSTRUCTION FORMAT

AND

ADDRESSING MODES

Régister Deferred Mode (Figure 3-5)

(Rn)

Assembler Syntax:

Mode Specifier:

MR.13643

Figure 3-5

Description:

The register deferred mode provides one level of

1indirect

addressing

The PC may not be used in
register deferred mode.
If
address
of
the
operand
1is
unpredictable
and the next
executed
or the next operand 1is unpredictable.

1t
1s
the
instruction
‘

over register mode; that is, the general register contains the address
of the operand rather than the operand itself.
The deferred modes are
useful when dealing with an operand whose address is calculated.
Special Comments:

3-9

INSTRUCTION

FORMAT

Example:

AND

ADDRESSING

Instruction

DEFERRED

Format:

MODES

MODE,

CLEAR

QUAD

INSTRUCTION

CLRQ

(R4)

BEFORE INSTRUCTION EXECUTION
ADDRESS

00001010

SPACE -

00001010

00001011

00001012

00001013

00001014

34.

00001015

00001016

00001017

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE

00001010

00001011

00001012

00001013

00001014

00001015

000010186

00001017

“

| 00001010

MACHINE CODE: ASSUME STARTING LOCATIONOOO0O3

000

00003000

00003001

64
R

OPCODE FOR CLEAR QUAD INSTRUCTION
——————

OPERAND SPECIFIER FOR REGISER DEFERRED MODE.R4
MR-13400

Figure

3-6

CLRQ

(R4)

Thls example,
Figure
3-6,
Register
Deferred Mode.
R4

Instruction

seven

bytes

specifies

are to

Clear

Quadword

shows
a
Clear
Quad
instruction
using
contains the address of the operand.
The
that the byte at this address plus the following
cleared.

3-10

INSTRUCTION FORMAT AND ADDRESSING MODES
Autoincrement Mode (Fighre 3-7)

Assembler Syntax:

~ (Rn)+
3

Mode Specifier:

MR-13644

Figure 3-7

Autoincrement Mode Operand Specifier Format

Description:

In autoincrement mode addressing, Rn
contains
the
address
of
the
operand.
After
the
operand
address is determined, the size of the
operand (which is determined by the instruction) in bytes (1 for byte,
2
for
word,
4
for
longword
or
F _floating,
and
B8 for guadword,
D floating, or G_floating) is added to the
contents
of
Rn
and
the
contents
of
Rn
are
replaced by the result.
This'mode provides for
automatic stepping of a pointer through sequential elements of a table
of
operands.
Contents
of
registers are incremented to address the
next sequential location.
The autoincrement mode 1s especialily useful
for array processing and stacks.
It will access an element of a table
and then step the pointer to address the next operand
1n
the
table.
Although
most useful for table handling, this mode 1is general and may
be used for a variety of purposes.
Special Comments:

If the PC is used as the general register,
this
addressing
designated
immediate
mode and has special syntax (refer to

mode)
.

mode
1is
immediate

INSTRUCTICON

FORMAT

Example:

AND

ADDRESSING

MODES

- AUTOINCREMENT MODE,

Instruction

Format:

MOVL

MOVE

LONG

INSTRUCTION

(R1)+,R2

This

instructicn

longword

will

data

(32

move
bits)

BEFORE INSTRUCTION EXECUTION

ADDRESS

SPACE

00001010
00001011
00001012
00001013

‘

11
22
33

> OPERAND

00001015

. 00001010 ]

[ 00000000 W]

00001014

SOURCE OPERAND ADDRESS = 000001010

AFTER INSTRUCTION EXECUTION
ADDRESS

SPACE

00001010

00001012
00001013

00001015

00001014 |

00001014

33221100
|

MACHINE CODE: ASSUME STARTING LOCATION 3000

00003000

00003001

00003002

OPCODE FOR MOVE LONG WORD INSTRUCTION

AUTOINCREMENT MQDE. REGISTER R1
REGISTER MODE. REGISTER R2

MR Z400

Figure

3-8 MOVL(R1)+,R2

This
example,
Figure
3-8,
shows
autoincrement mode.
The content of
source

are

operand.

Since

transferred

lnstruction

specifies

the

R2.

operand

a
Rl
is

Move
is the
a

then

longword data
3-12

Move

32-bit

Longword

Long
instruction
effective address
longword,

incremented

type.

four

by four

using
of the
bytes

since

the

" INSTRUCTION FORMAT AND ADDRESSING MODE!

Autoincrement Deferred (Figure 3-9)
Assembler Syntax:

Mode Specifier:

@(Rn)+
S

MR-13645

Figure

3-9

Autoincrement

Deferred Operand Specifier

Format

Description:

In autoincrement deferred addressing, Rn contains a
which
1s a pointer to the operand address.
has been determined, four is added to
the

longword address

After the operand address
contents
o©of
Rn
and
the

contents
of
Rn
are
replaced with the result.
used since there are four bytes in an address.

The quantity

four

Special Comments:
If the PC is used as the general register, this
addressing
designated absolute mode (refer to absolute mode).

3-13

mode

1is

INSTRUCTION FORMAT AND ADDRESSING MODES

Example:

AUTOINCREMENT

Instruction

Format:

DEFERRED MODE,

MOVE WORD

INSTRUCTION

ADORESS
SPACE

00001010

00001011

OPERAND ADDRESS

MOVW

3(R1)+,R2

BEFORE INSTRUCTION EXECUTION

00001012

00001013

00001014

00001015

33221100

33221101

33221102

33221103

00000000

33221100

AFTER INSTRUCTION EXECUTION
R1

00001014 | |

O0005F34

MACHINE CODE: ASSUME STARTING LOCATION 00003000

00003000

OPCODE FOR MOVE WORD INSTRUCTION

00003001

AUTOINCREMENT DEFERRED MODE, REGISTER R1

00003002

MR-13402

Figure

3-10

MOVW @(R1l)+,R2

Move Word

This example,
Figure
3-10,
shows
a
Move
Word
instruction
using
autoincrement
deferred
mode.
The contents of Rl is a pointer to the
operand address.
Since a word length instruction
1is
specified,
the
byte
at
the
effective address and the byte at the effective address
plus one are loaded into the low-order half of register R2; the
upper
half
of
R2
1s not altered.
Rl is then incremented by four since it
points to a 32-bit address.
‘
3-14

INSTRUCTION FORMAT AND ADDRESSING MODES
Autodecrement Mode (Figure 3-11)
Assembler Syntax:

-(Rn)

Mode Specifier:

MA 13646

Figure 3-11 Autodecrement Mode Operand Specifier Format
Description:

In autodecrement
mode the contents of Rn are decremented and then used
as
the
address of the operand.
The size of the operand, in bytes (1
for byte, 2 for
word,
4
for
longword
or
F _floating,
and
8
for
quadword, D _floating or G_floating) is subtracted from the contents of
Rn and the contents of Rn are replaced by the result.
The updated
Rn
contains the address of the operand.
Special

Comments:

The PC may not be used in autodecrement mode.
of
the
operand is unpredictable and the next
the next operand is unpredictable.

3-15

If it 1is,
the
address
instruction executed or

INSTRUCTION

FORMAT

AND

ADDRESSING MODES
*

Example:

AUTODECREMENT MODE,

Instructlion

Format:

MOVL

MOVE

LONG

INSTRUCTION

-(R3),R4

BEFORE INSTRUCTION EXECUTION
ADDRESS

SPACE
o0o00to1a

00001015 |

00001017 |

cCE

R3
1)

00001016 | 54

00001018

00000000

CES43210

AFTER INSTRUCTION EXECUTION
*

00001014

cEesa3210

MACHINE CODE: ASSUME STARTING LOCATION 0000300

. 00003000
00003001

00003002

OPCODE FOR MOVE LONG INSTRUCTION
AUTOINCREMENT MODE, REGISTER R3

REGISTERMODE, REGISTER R4

MAR-13403

Figure

3-12

MOVL

-(R3),R4

This example,
autodecrement
the data type
longword is
address

fetched

Move

Longword

Figure
3-12,
shows
a
Move
Long
instruction
using
mode.
The contents or R3 are decremented according to
specified in the opcode (four in this example because
wused).
The updated contents of R3 are -hen used as the
of the operand.
The instruction
causes
the
operand
to
and loaded into R4.

3-16

INSTRUCTION FORMAT AND ADDRESSING MODES
4

Literal Mode (Figure 3-13)

S~# literal

Assembler Syntax:

Mode Specifier:
o

’ l o)

0 I

. 0,1,2, or 3

(depending on literal value specified)

]

LITERAL

MR-13404

Literal Mode Operand Specifier Format

Figure 3-13

Description:

Literal mode addressing provides an efficient means of specifying
integer constants in the range from 0 to 63 (decimal). This is called
short literal.
Literal values above 63 can be obtained by
immediate
(autoincrement mode using the PC) although immediate mode is
mode
choose between
the assembler will
For predefined values,
longer.
For short literal operands, the
immediate modes.
and
literal
short
format is shown in Figure 3-14.
to

zero.

Bits 7 and 6, however,

are always set

MODE SPECIFIER

MR-134085

Figure

The following example,
literals are 14,

30,

3-14

Short

Figure 3-15

46,

and 62.

Literal Format

shows

some

short

literals;

the

INSTRUCTION

FORMAT

AND

ADDRESSING

MODES

apg

I .

I ‘

0 RANGE OTS%OPg 1SSP1E(§ZIHER =0

3019

l o

9 l

RA&GE OrMODE g’rfg‘”m =1

4614

l o

o I

RANGE OF MODE igsgmm =2

6210

Cor

RANGE OF MODE zgr;:gmea =3

o | 1

o I

MR-13406

Figure 3-15
Floating
For

6-bit
where

Examples of Short Literals

point literals as
operands of data type

well as short literals
can
be
expressed.
F_floating, D floating, and G _floating, the
composed of
two
~3-bit
fields, Figure
3-16,

literal field is
EXP is exponent and

FRA

04
|

fraction.

]

EXP
]

00
I

FRA
]
MR-13407

Figure

3-16

Floating

The EXP and FRA fields are used to form an
operand
as
shown
F_floating operand.

1in

Figure

3-17.

Bits

Literal

waloating

63:32

are

not

D_floating

present

. INSTRUCTION FORMAT AND ADDRESSING MODES
L]

128 + EXP

FRA

0 |

00
0

A2 ‘

:A+4

A+6
MR *3408

Figure 3-17 F_floating and Dmfloating Operand
The EXP and FRA fields are used to form a G_floating operand as
in

Figure

15
0

3-18.

shown

o
.

1024 + EXP

01
FRA

00
0

A+2

At+d

‘

A+6

MR-13409

Figure

3-18

G_floating Operand

3-19

INSTRUCTION

FORMAT

Table 3-3
literals.

AND

gives

ADDRESSING MODES

the

numbers

. SRR AR

SN O U= WO

S SNk R St ~—-——+mm [—

Table

1/2

9/16
1/8
2 1/4
1 1/2
1

5/8
1/4

that

3-3

can

Floating

11/16
1 3/8

1/2

3/4

5 1/2
11
22
44
88

3-20

represented

Literals

13/16
1 5/8
3 1/4
6 1/2
13
26
52
104

floating

INSTRUCTION FORMAT' AND ADDRESSING MODES

Example:

LITERAL MODE, MOVE LONG .INSTRUCTION

InStructiOn Format:

MOVL S"#9,R4

BEFORE INSTRUCTION EXECUTION

[mmmmm
AFTER INSTRUCTION EXECUTION
R4

00000008|

MACHINE CODE:

ASSUME STARTING LOCATION 00003000

~ OPCODE FOR MOVE LONG INSTRUCTION

00003000
00003001
00003002

LITERAL
9
REGISTER MODE, REGISTER R4

MR-13410

Figure

3-19

MOVL S~#9,R4 Move

Longword

This example, Figure 3-19, shows a Move Long instruction using literal

mode.

The

instruction.

literal

transferred

3-21

result

the

INSTRUCTION FORMAT AND ADDRESSING MODES
Displacement Mode

(Figure

Assembler Syntax:

Mode

3-20)

D(Rn)

B~"D(Rn)
W D(Rn)
L"D(Rn)

Specifier:

A
C
E

Byte displacement
Word displacement
Longword displacement

(byte displacement)
(word displacement)
(longword displacement)

DISPLACEMENT

08 07

|
DISPLACEMENT

04 03

BYTE

04 03
C

08 07

DnspiACEMENT
00

04 03

WORD

DISPLACEMENT

MR-13647

Figure

3-20

Displacement

Mode Operand Specifier

Format

Description:
In
displacement
mode
addressing,
the
displacement
(after
sign-extended
to
32
bits
1if
it is a byte or word) is added
contents of register Rn and the result is the operand address.

being
to the

The MicroVAX architecture provides for an
8-bit,
16-bit, or
32-bit
offset.
Since
most
program
references occur within small discrete
portions of the address space, a 32-bit offset is not always necessary
and
the
8and
16-bit
offsets
will result in the saving of space

(fewer bits are required).

()

[f the PC 1is used
as
the
general
register,
relactive mode (refer to relative mode).

-22

this

mode

<called

INSTRUCTION

FORMAT AND

ADDRESSING MODES

Example: DISPLACEMENT MODE, MOVE BYTE INSTRUCTION
Instruction Format:

MOVB B“S(R4),B“3(R3)

BEFORE INSTRUCTION EXECUTION
ADDRESS

' SPACE

00001015 |

| oooor012

00001016
00001017
00001018
00001019

| o0o002020
,

|
00002021
00002022 |
|
00002023

AFTER INSTRUCTION EXECUTION
00001015
00001016
00001017
00001018

00001012

|
|

| 00002020 |

00002021
00002022

00002023

<— OPERAND

MACHINE CODE: ASSUME STARTING LOCATION 00003000
90
A4
05
A3

|
|
|

OPCODE FOR MOVE BYTE INSTRUCTION
SIGNED BYTE DISPLACEMENT, REGISTER R4
SPECIFIER EXTENSION (DISPLACEMENT OF 5)
SIGNED BYTE DISPLACEMENT, REGISTER R3
SPECIFIER EXTENSION (DISPLACEMENT OF 3)

MR-13411

Figure 3-21
This example,

Figure

MOVB B~5(R4),B~3(R3) Move Bvte

3-21,

shows

Move

Byte

1instruction

using

displacement mode.
A displacement of 5 1s added to the contents of R4
to form the address of the byte operand.
The operand is moved to
the
address formed by adding the displacement of 3 to the contents of R3.

3-23

INSTRUCTION FORMAT AND ADDRESSING MODES
Displacement

Assembler

Deferred Mode

Syntax:

(Figure

¢D(RnN)

2B"D(Rn)
sW*D(Rn)
iL~D(Rn)
Mode

3-22)

Specifier:

B
D
F

- Byte displacement deferred
- Word displacement deferred
- Longword displacement deferred

(byte displacement deferred)
(word displacement deferred)
(longword displacement deferred)

08 07
|

DISPLACEMENT

00
BYTE

—

04 03

08 07

04 03

DISPLACEMENT

;

DISPLACEMENT

WORD

08 07
|

DISPLACEMENT

DEFERRED

04 03

DEFERRED

DISPLACEMENT

LONGWORD
Rn

DISPLACEMENT
DEFERRED
MR-13648

Figure 3-22

Displacement Deferred Mode Operand Specifier Format

Description:
In
displacement
deferred
displacement
(after being sign-extended to
is added to the contents of the register Rn
longword address of the operand address.

If the PC 1s used

relative deferred mode.

the

general

3-24

mode
addressing,
the
32 bits if a byte or word)
and
the
result
1is
the

this

mode

called

INSTRUCTION FORMAT AND ADDRESSING MODE:
4

Example:

DISPLACEMENT DEFERRED MODE,

Instruction Format:

INCREMENT WORD

INSTRUCTION

INCW 2B~5(R4)

BEFORE INSTRUCTION EXECUTION
R4

00001017

i R

00001018
00001019
00001020

| OPERAND
ADDRESS
e

68244288

68244289 | 57 } OPERAND

5713 OPERAND

INCREMENT

5714 NEW OPERAND

AFTER INSTRUCTION EXECUTION

68244288

68244289

MACHINE CODE: ASSUME STARTING LOCATION 00003000

00003000

OPCODE FOR1 INCREMENT WORD INSTRUCTION

00003002

SPECIFIER EXTENSION REGISTER R3 PLUS SIGN

00003001

SIGNED BYTE DISPLACEMENT, REGISTER R4

MR 13412

Figure 3-23

INCW 23B~5(R4)

Increment Word

This example, Figure 3-23, shows an Increment Word
displacement

deferred

~of R4 and the result
operand.

The operand

mode.

is the longword address
of
of

5713

instruction

using

The gquantity
5 is added
to the contents

is incremented

the

5714,

address

the

INSTRUCTION

FORMAT

Index Mode

Assembler

Mode

AND

ADDRESSING

(Figure

3-24)

Syntax:

Specifier:

MCDES

i[Rx]

PRIMARY OPERAND

[e e e e o

|
:'

it o e e e s e

ey
mspmcgmsm

BASE OF¢
OPERAND
BASE

0403

0807

-5

MR-13649

Figure

3-24

Index Mode Operand Specifier

Format

Description:
The operand specifier consists of at
least two
operand
specifier
and a base operand specifier.
specifier contained in bits 0 through 7 includes

(Rx)

and a mode specifier of 4.

The address of

bytes
a
primary
The primary operand
the
index
register

the primary operand

determined by first multiplying the contents of the index register
Rx
by the size of the primary operand in bytes
(1 for byte, 2 for word, 4
for longword
or
F_floating, and
8
for
quadword,
D floating,
or
G_floating).
This value is then added to the address specified by the
base operand specifier (bits 15:8), and the result
1is
taken
as
the
operand address.
Index mode
arrays.

address

addressing
The

base
calculation

permits
address

the

very general
of

base

the

operand

the
1index registers are taken as
logical index is converted into a

the
contents
in bytes.

the
|

index

array

and
is

efficient

determined

specifier.

accessing
by

The

the

operand

contents

a logical index into the array.
The
real (byte)
offset
by
multiplying

the

size

the

primary

operand

Specifying register, literal, or
1index mode
for
the
base
operand
specifier will result in an illegal addressing mode fault.
If the use
of
some particular specifier
1is
illegal
(causes
a
fault
or
unpredictable behavior), then that specifier is also illegal as a base
operand

specifier

Special

Comments:

index

mode

under

the

same

conditions.

INSTRUCTION FORMAT AND ADDRESSING MODES

The following restrictions are placed
on index register Rx:
1.

The PC cannot be used as an index register.

If the base operand specifier is
for
an addressing
mode
which
results
1in
register
modification
(autoincrement, autoincrement
deferred, or autodecrement), the same register cannot be the index
‘register. If it is, the primary operand address is unpredictable.

addressing mode

If it is, a reserved

fault occurs.

Table 3-4 lists the various forms of index mode addressing
available.
The names
of the addressing modes resulting from index mode addressing
are formed by adding indexed
to the
addressing mode
of
the
base

operand
specifier.
index register 1s Rx.

The

general

Table 3-4
Mode

Index Mode AddressingV
|

Assembler Notation

Autoincrement

Indexed

(Rn) [Rx]

- (Rn)+[Rx]

Autoincrement Deferred
Indexed

~ @(Rn) +[Rx]

Absolute Indexed

@#address[Rx]

Autodecrement Indexed

-(Rn) [Rx]

Byte, Word, Longword
Displacement

B~D(Rn) [Rx]

Indexed

W~D(Rn) [Rx]
L~D(Rn) [Rx]

Byte, Word, Longword

@B“D(Rfi)[Rx]

Displacement
Indexed =

Deferred

3W~D(Rn) [Rx]
3L~"D(Rn) [Rx]

It is
important to note
that
the
operand
address
(the
address
containing the
operand)
1is first evaluated
ané
then
the
1index
specified by the index register 1s added to
the
operand
address to
find the indexed address.
To 1llustrate
of 1ndexed addressing follows.

3-27

this,

example of

each

type

INSTRUCTION FORMAT AND ADDRESSING MODES
Example
#1l:
INSTRUCTION

Instruction Format:

DEFERRED

INDEXED

MODE,

INCREMENT

WORD

INCW,(RZ)[RSJ

BEFORE INSTRUCTION EXECUTION

ADDRESS
SPACE

00001012 | o4

00001013

00001014
50001015

| ocoooto12
~

316

00000003

16 X 2 BYTES| ES P PER| WORD -= 6
00001012

00001018
00001019

;

| |
‘
| [ OFERAND

00001018

AFTER INSTRUCTION EXECUTION

00001018

00001012

00000003

00001019

MACHINE CODE: ASSUME STARTING LOCATION 00003000

00003000

00003001

00003002

OPCODE FOR INCREMENT WORD INSTRUCTION
INDEX MODE, REGISTER RS
REGISTER DEFERRED MODE, REGISTER R2

MRA-13413

Figure

3-25

INCW

(R2)[R5]

Increment

Word

This example, Figure 3-25, shows an Increment Word
instruction
using
register
deferred
index
addressing.
The
base operand address is
evaluated.
This location is :indexed by 6 since the value (3)
1in
the
index register is multiplied by the word data size of two.

3-28

INSTRUCTICON FORMAT AND ADDRESSING MODE:

Example #2:

AUTOINCREMENT INDEXED MODE, CLEAR LONGWORD INSTRUCTION

Instruction Format:

CLRL (R@)*[RS]

BEFORE INSTRUCTION EXECUTION

ADDRESS

000010A6

000010A7

Q00010A9

' 00001012

> OPERAND

000010AS8

| INDEX = 25, X 4 BYTES PER
LONGWORD = 94,4

R
—

ADDRESS OF OPERAND

AFTER INSTRUCTION EXECUTION

JOO010A6

000010A7

}8888

000010AG

|
|

OPCODE FOR CLEAR LONGWORD INSTRUCTION

INDEX MODE. REGISTER RS

AUTOINCREMENT MODE, REGISTER R4

MA-13414

Figure 3-26

CLRL

(R4)+[R5] Clear Longword

This example, Figure 3-26, shows a Clear Long
instruction using
the
autoincrement indexed addressing mode.
The base operand address is in
'R4.
This value is indexec
by the quantity in RS
multipiied
by
the
data
size, in bytes. This location, plus the next three, are cleared
since a longword instruction 1s specified.
|
|

3-29

INSTRUCTION

FORMAT

Example

#3:

AND®

ADDRESSING

MODES

AUTOINCREMENT DEFERRED

Instruction Format:

INDEX MODE,

CLEAR WORD

INSTRUCTION

CLRW 3(R4)+([R5]

BEFORE INSTRUCTION EXECUTION
ADDRESS

SPACE

00001012

00001013

00001014

00001015

00001012

00000005

(N
/

Ano

516 X 2 BYTES PER WORD = 0000000A

Egg%%gg

“MN‘“ 06082143

0000000A

06082140

ADDRESS

SPACE

06082140

| 22

0608214E

: } OPERAND

0608214F

AFTER INSTRUCTION EXECUTION

06082140
0608214E

00001014
'

0608214F

MACHINE CODE: ASSUME STARTING LOCATION 00003000

00003000

OPCODE FOR CLEAR WORD INSTRUCTION

00003002

AUTOINCREMENT DEFERRED MODE, REGISTER R4

00003001

INDEX MODE. REGISTER RS

MRA-13415

Figure 3-27

CLRW 2(R4)+[R5] Clear Word

‘This example, Figure 3-27, shows a Clear Word
instruction
using the
autoincrement
deferred indexing mode.
R4 contains the address of the
operand address.
The index value A is
obtained
by
multiplying
the
contents
which is

of
2.

<the
1index
register,
[R5], by the data
The calcuword
lated
address is cleared.

size,

bytes,

INSTRUCTION FORMAT AND ADDRESSING MODE:
. *

Example #4: AUTODECREMENT INDEXED MODE, CLEAR WORD INSTRUCTION
Instruction Format:

CLRW -(R2)[R4]

BEFORE INSTRUCTION EXECUTION
ADDRESS

0000101 A

I 00001016 I

00000003

316 X 2 BYTES PER WORD = 6(INDEX)

0000101C
00001010

00001016
00000002

DECREMENT BY 2

1014
0000
000 0006

INDEX VALUE

O000101A

INDEXED OPERAND ADDRESS

OPERAND ADDRESS

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE

00001014

00001018 |

| oooot01a | | 0000003. |
~

0000101C
00001010

MACHINE CODE: ASSUME STARTING LOCATION 00003000

00003000
00003001
00003002

OPCODE FOR CLEAR WORD INSTRUCTION
INDEX MODE, REGISTER R4
AUTOINCREMENT DEFERRED MODE REGISTER R2
MR-13416

Figure 3-28

CLRW -(R2)[R4] Clear Word

using
ctionmente
Clearts Word
d
by
are decre
e,t Figure
exampl
of R2 instru
‘This
Thea conten
mode. shows
indexed 3-28,
cremen
autode

by
edform
ipli
R4, iss mult
ter,content
regis
index
The
.
bytes
in
size
data
the
two,
to
R2
of
the
to
added
is
result
the
and
size
data
the
the operand address.
bytes are cleared.

ion is specified, two
ruct
r word inst
Since a clea
;
|
:

3-31

INSTRUCTION FORMAT AND ADDRESSING MODES
_Example #5:

ABSOLUTE INDEXED MODE, CLEAR LONGWORD INSTRUCTION

Instruction Format:

CLRL

34°X1012[R2]

BEFORE INSTRUCTION EXECUTION
R2

1026

00000005 |

1027

1028

51 X4 =14,4

1029

00001012

00000014

AFTER INSTRUCTION EXECUTION

00001026

1026

1027

1028

QGGOOOQS

1029

MACHINE CODE: ASSUME STARTING LOCATION 00003000
00003000
00003001

OPCODE FOR CLEAR LONGWORD INSTRUCTION
INDEX MODE, REGISTER R2

00003002

ABSOLUTE MODE

00003003

Y anse openan

MR 13417

Figure

3-29

CLRL

@#7X1012
Clear Longword
[R2]

This example, Figure 3-29, shows a Clear
Longword
instruction
using
absolute
1indexed
mode.
The base of 00001012 is indexed by R2 which
contains 5.
Since a longword data type is specified,
5x4
=
14(16),
which
becomes
the
index
value.
This
wvalue
1s added to 00001012
ylelding 00001026.
This is the operand address, and
four
bytes
are
cleared since a longword data type has been specified.

INSTRUCTION FORMAT AND ADDRESSING
MODES

Example #6: DISPLACEMENT INDEXED MODE, CLEAR QUADWORD INSTRUCTICN

Instruction Format:

CLRQ 2(Rl)[R3},

BEFORE INSTRUCTION EXECUTION
ADDRESS

0000402A

SPACE

516 X 8 BYTES PER QUAD WORD

= 281

(INDEX)

“®16

CONTENTS OF R1

BYTE DISPLACEMENT

OPERAND ADDRESS

INDEXED OPERAND ADDRESS
AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE

|
|

&88888888!

MACHINE CODE: ASSUME STARTING LOCATION

00003000

OPCODE FOR CLEAR QUAD WORD INSTRUCTION

|
|
-

INDEX MODE. REGISTER R3
REGISTERDEFERRED MODE. REGISTER R1

MR-13418

Figure.3w30

CLRQ Z(Rl)[RBJ Cleaeruadwmrd

1nstruction using
This example, Flgure 3-30, shows a Clear Quadword
displacement indexmode. The byte displacement of two is added to the
this
The index which is calculated as 28 is added to
content of Rl1.
quadword
a
(since
lmcatlmns
seven
This location and the next
address.
instruction

is specified) are cleared.
3-33

INSTRUCTION FORMAT AND ADDRESSING MODES
Example
#7:

DISPLACEMENT DEFERRED

Instruction Format:

INDEX MODE,

MOVE LONG

INSTRUCTION

MOVL 3~X14(R1)[R3],R5

BEFORE INSTRUCTION EXECUTION

ADDRESS

SPACE

00001012

| oooo1012

00001013

R3
[5o00000

00001014

00001015

416 X 4 BYTES PER LONGWORD
= 101 gINDEX

]

T
| 00000000 |

gggg:ggi

00000014

00001012

CONENTS OF R1

00001028

00001026

ADDRESS OF OPERAND ADDRESS

DISPLACEMENT

00001029

33222

44332221

44332222

44332223

4433221
1
‘

00000010‘

44332224

44332225

;

44332221

OPERAN
| D ADDRESS
'

INDEX

INDEXED OPERAND ADDRESS

- OPERAND

AFTER INSTRUCTION EXECUTION
|

| 00001012
.

| 00000004
RS

67452301

MACHINE CODE: ASSUME STARTING LOCATION
00003000

00003000

00003001
00003002
00003003
00003004

43
81
14
55

N—/

Figure 3-31

| OPCODE FOR MOVE LONGWORD INSTRUCTION
INDEX MODE. REGISTER R3
SIGNED BYTE DISPLACEMENT, REGISTER R1
SPECIFIER EXTENSION
REGISTER MODE, REGISTER R5

MR-13419

MOVL @“Xl4(Rl)[R3],RS Move‘Longwmrd

This example,
Figure
displacement deferred

3-31,
shows
a
Move
Long
instruction
wusing
indexed addressing.
The displacement of 14 1is
added to the contents
of Rl yielding 00001026.
The contents
of
=this
location are the operand address, 44332211.
This quantity is added to
the index yielding the
indexed
operand
address
of 44332221, The
contents

this

address

are

moved

into RS.

3-34

INSTRUCTIONVFORMAT AND ADDRESSING MODE!
3.2.1.2

Program Counter Addressing -

1in

is the program counter
addressing

modes.

(PC).

It can also

The processor

increments

used

the program

counter as the opcode,
operand
specifier,
and
immediate
data
or
addresses
(of the instruction) are evaluated.
The amount that the PC
is
1incremented
1s
determined
by
the
opcode,
number
of
operand
specifiers,

and

so on.

;The PC can be used with all of the addressing modes except register of
index
mode,
since
in
these
two
modes
the results
will
unpredictable. Table 3-5 lists the addrefislng modes that use
the
as a general register.
ENERTETR SO
|
|

Table 3-5
Mode

Name

Program Counter Addressing Modes

;

Afisamblar"

Immedlate

Absolute

Functlmn

I #Qperand
|

- Constant
|

3#Location

Byte Relative

B~G(PC)

operand f@llmws address:

mode

‘Absolute addrass
-

dDisplacement*is added to current
value

Word Relative

W~G(PC)

Longword Relative.

L"G(PC)

Byte Relative

aB~G(PC)

Word Relative

obtain

IW~G(PC)

Longword Relative
Deferred

3L~"G(PC)

3-35

operand

Displacement is added to current
of

to give

operand

Deferred

folltws address

mode

address

Deferred

be
PC

the

address

the

INSTRUCTION FORMAT AND ADDRESSING MODES
Immediate Mode

(Figure

3-32)

Assembler Syntax:

[~4operand

Mode Specifier:

;

CONSTANT

_04 03

F o

SIZE DEPENDS
ON CONTEXT
MRAR-1559%

Figure

3-32

Immediate Mode Operand

Specifier

Format

Description:
This mode is autoincrement mode when the PC is

reglster.
The contents of
-are 1mmedlate data.

the

locatiocn

used

follmwlng

the

general

addre551ng mode

INSTRUCTION FORMAT AND ADDRESSING
MODE:
L

Example:

I[MMEDIATE MODE,

Instruction Format:

MOVL

MOVE LONG INSTRUCTION
I”#6,Ri

2388328

BEFORE INSTRUCTION EXECUTION

' OPCODE FOR MOVE LONG INSTRUCTION

OPERAND SPECIFIER AUTOINCREMENET PC (IMMEDIATE)

' IMMEDIATE DATA

00001014
00001015

000010186
00001017

&sssg

AFTER INSTRUCTION EXECUTION

IMMEDIATE

MA-13420

Figure»3w33‘§MOVL'I”#6,R4 vae”Langword
This example,
Figure
3-33,
shows
a
immediate
mode.
The
immediate data
and operand specifier
are moved to R4.

3-37

Move
Long
1instruction
using
(00000006) following the opcode

INSTRUCTxON FORMAT AND ADDRESSING MODES
Absolute Mode

(Figure 3-34)

Assembler Syntax:

Mode Specifier:

c#location

‘

08 07

ADDRESS

04 03

F
'MR-15596

Figure

3-34

Absolute Mode Operand Specifier

Format

Description:

This mode is autoincrement
deferred
using
the
PC as
the
general
register.
The contents
of
the
longword following
the
operand
specifier 1s the operand address.
This is interpreted as an
absolute
address
(an
address
that remains constant no matter where in memory
the

assembled

instruction

executed)

3-38

INSTRUCTION FORMAT AND ADDRESSING MODE!
&

Example: ABSOLUTE MODE, CLEAR LONG INSTRUCTION
Instruction Format:

CLRL 3$#°X674533

BEFORE INSTRUCTION EXECUTION
ADDRESS

OPCOQE FOR CLEAR LONG INSTRUCTION

OPERAND SPECIFIER, AUTOINCREMENT BEF&RMEQ PC (AflSULUTE)

1} OPERAND mmmg |

00674533
00674534

00674535

00674536

AFTER INSTRUCTION EXECUTION

00674533

00674534

00674535

00674536

MR-13421

| Figure§3w35 ;CLRL @#~674533 ClearVLongWQrd
This example, Figure 3-35, shows a Clear
Longword
1instruction
using
the absolute addressing mode.
This instruction causes the location(s)
following the operand specifier to be taken
as
the
address
of
the
operand,
and
1s
00674533
1in
this
case.
The
longword
operand
associated with this address is cleared.
3-39

INSTRUCTION FORMAT AND ADDRESSI
MODE
NG
S
Relative

Mode

Assembler

Mode

(Figure

Syntax:

Specifier:

3-36).

B°D

Byte

W”D

displacemént

Word

LTMD

displacement

- Longword

A C E -

(byte)
(word)
(longword)

displacement

0807

»
DlSPLACEMENT

Efi
[

0403

PO
A

0807

VD’SPLACEMENT
"

E
F | |BYT
DISPL
ACEMENT

0403

€ P | DISPLACEMENT

0807

0403

|LonGwORD

MR-15597

Figure 3-36 VRelative Mode Operand Spec
ifier Format
Description:

This mode is displacement
mode
with
the
PC
wused as
the
general
register.
The
displacement
which
follows the operand specifie
r is
added
to the PC, and the sum becomes
the address of the operand.
This
mode
1is
wuseful
for
writing
position
independent
code
,
sinc
e
the
location referenced is always
fixed relative to the PC,

INSTRUCTION

FORMAT

AND

ADDRESSING

MODE.
&

Example:

RELATIVE MCDE, MOVE LONGWORD INSTRUCTION

Instruction Format:

MCOVL ~X201l6,R4

BEFORE INSTRUCTION EXECUTION
|

- PO~

ADDRESS

SPACE

OPCODE FOR MOVE LONG

DISPLACEMENT MODE WITH PC
,

t.# DISPLACEMENT = 1000
REGISTER MODE. REGISTER R4

00001016

00002016

LONG WORD

(

OPERAND

AFTER INSTRUCTION EXECUTION
|

00860077
MR-13422

Figure

This

example,

relative

the

Figure

mode.

to obtain

The

3-37

MOVL "X2016,R4

3-37,
word

shows

following

the address

the

a
the

PC.

Move

Longword

Long

operand

instruction

specifier

using

added to

In this example, the PC is pointing to
location
00001016
after
the
first
operand
specifier
1is evaluated.
The word following the first
opcode and first operand specifier is 00001000 and is added to the PC.
The
result
1s
00002016s6.
This
value represents the address of the
longword operand (00860077).
The operand is then
moved
to
register
R4.
The PC contains 00001017 after instruction execution.
3-41

INSTRUCTION FORMAT AND ADDRESSING‘MODES
Relative

Assembler

Mode

Deferred Mode

Syntax:

(Figure

3-38)

3B”D
WTMD

Byte
Word

¢L”D

displacement deferred
displacement deferred
Longword displacement deferred

Specifier:

_0807

rUlSPLACEMENT
~

‘

0807
DISPLACEMENT
v
T

rfi

0403

0403
D

- DISPLACEMENT

|DISPLACEMENT
DEFERRED

00 .o .o
F

—

|DISPLACEMENT
DEFERRED

LONGWORD
DISPLACEMENT
DEFERRED
MR-15598

Figure 3-38

Relative Deferred Mode Operand Specifier Format

Description:
This -mnode is similar to relative mode, except
that
which
follows
the
addressing mode is added to the
the longword address of the address of the operand.
mode 1s useful when processing tables of addresses.

3-42

the
displacement
PC and the sum is
This
addressing

INSTRUCTION FORMAT AND ADDRESSING MODE;
L

‘Example:

RELATIVE DEFERRED MODE,

Instruction Format:

MOVE LONG

INSTRUCTION

MOVL @“X2050,R2

BEFORE INSTRUCTION EXECUTION
PC

00002000

00002001

00002002

BYTE DISPLACEMENT FROM PC

AMOUNT OF DISPLACEMENT

00002003

MOVE LONG OPCODE
|

l 00000000 l
|

CALCULATION

00002050

00002051

00002003

| \ operanp

00002050

[ ADDRESS

00002052

00002053

00006000

‘

00006001

50006002

OPERAND

00006003

AFTER INSTRUCTION EXECUTION

01234567
MRA-13423

Figure 3-39
‘This example,
00002050
would

128

Figure

3-39,

represents
the
selected

(decimal)

MOVL @~X2050,R2 Move Longword

by the

shows

address of
assembler

addressable bytes.

Move

Long

the operand.

since

the

instruction

where

A byte displacement

displacement

When the displacement

1is

within

evaluated,

the program counter is pointing to 00002003.
The displacement
of
4D
ils
added
to
the
current
value
of
the
PC to give the address of
00002050.
The contents of this address are then used as
the
address
of the operand (00006000) and the operand is moved to R2.
3-43

" INSTRUCTION FORMAT AND ADDRESSING MODES

3.2.2

Branch Addressing

In branch displacement addressing the byte
sign-extended
to
32 bits and added to the

The

updated contents of the PC
beyond the operand specifier.

Branch

Addressing

(Figure

Assembler Syntax:

| A

Mode

Specifier:

are

the

word

updated

address

displacement

content

the

first

the

PC.
byte

3-40)

None

07____

DISPLACEMENT

BYTE DISPLACEMENT

fi
|

00
DISPLACEMENT
WORD DISPLACEMENT
MR-15599

Figure

3-10

Branch Addressing

Operand

Specifier

Format

Description:
In branch displacement addressing, the
sign-extended
to 32 bits and added to
The

the

updated
operand

contents

of
specifier.

The
assembler
addressing
1is
address and not

Branch

(CMP)

results

the

notation
for
byte
and
word
branch
displacement
A,
where
A
is
the branch address.
Note the branch
the displacement is used.

instruction

compare

the.
PC 1s

byte or
word
displacement
is
the updated contents of the PC.
address of the first byte
after

are

most

and are used
compare.

frequently

used

cause different

after

1instructions

actions depending on

Llike

the

INSTRUCTION

Example #1:

FORMAT

AND -ADDRESSING

MODE.

UNSIGNED BRANCH

This example causes a branch to location NOT 1if C is
not a digit
outside the

(i.e., C is treated as an unsigned number
range 0 through 9).

CMPB C,#~A/0/
'
BLSSU NOT

;Compare C and ASCII
;of digit 0.
|
~

CMPB C,#~A/9/

BGTRU NOT

Example

#2:

BRANCH

less

than an

representation

:Branch to location NOT if greater than
;an unsigned 9.

BIT

BBS #2,B,X

:Branches

BBSC #2,B,X
‘

BLBS B,
X

:Branch to location NOT
;unsigned 0.
|

;Compare C and ASCII
;of digit 9.
|

representation

<2>

in B

is set

(=1)

sBranches to X 1if bit <2>
rand bit 1s then cleared.

in B

set

(=1)

is set

(=1)

*Branches

to X

bit

<0> of

CHAPTER

INSTRUCTION SET

1.1

INTRODUCTION

This chapter describes the instructions used
by
CPU. =
The
MicroVAX
78032
CPU
1implements
a
instruction set.
The instruction set is divided
major

the
MicroVAX
78032
subset
of
the
VAX
1into
the
following

sections:

Integer

Address

Variable

Control

Procedure call

Miscellaneous

Queue

Character string

Operating

Floating point

Emulated instructions with microcode assist

A concise
Appendix

arithm@tic and

list of

length bit

logical

field

system support

instructions

and opcode

assignments

appears

1in

INSTRUCTION

SET

4.1l.1

Instruction

Within

each major

combined
1into
description is

Descriptions
section,

groups
composed

instructions

which

are

and described together.
of the following:

closely

The

instruction

are

group

The

format of each instruction in the group.
This gives the
name
and
type
of
each instruction operand specifier and the order in
which 1t appears in memory.
Operand specifiers from left to right
appear 1n increasing memory addresses.

The

operation

The

effect

condition

group

name.

Exceptlions
generally

specific
possible

addressing mode,

not

listed.

The

opcodes,

group.

The

the
all

T-bit,

instruction.
instructions

Exceptions

(e.g.,

memory management

mnemonics,

Optional

Operand

codes.

to
for

opcodes

A description

notes

Operand

instruction.

English

the

Specifier

specifiers

given

are

<name>.<access

which
or

are

reserved

etc.)

are

and names

are

illegal

violations,

4.1.2

the

each

hex.

the

instruction

the

instruction.

instruction

and

programming

examples,

Notation

described
type><data

the

following

way:

type>

where:

Name 1s a suggestive name
instruction.
The name is

Access

type

letter

for the operand in
often abbreviated.

denoting

type:

the

operand

context

specifier

Calculate

the

operand.

Address

effective
is

address

returned

of
a

the

access

specified

longword

which is the actual instruction operand.
Context
of address calculation is given by <data type>:
l.e. size to be used in autolncrement, autodecrement,
and indexing.
1-2

INSTRUCTION

Operand specifier 1s a
No operand reference.
Size of branch displacement
branch displacement.
is given by <data

type>.

Operand is read, potentially modified and written.
Note that this is NOT an indivisible memory
Also note that if the operand is not
operation.
actually modified, it may not be written back.
However, modify type operands are always checked
for both read and write accessibility.

Operand

read only.

Calculate the effective address of the specified
operand.
If the effective address is in memory,
the address is returned in a longword
which is the actual instruction operand.
of address calculation 1s given by <data

If the effective address
in Rn or R(n+1]'Rn.

Operand

is Rn,

Context
type>.

the operand

1s write only.

Data type isa letter denoting the data type of the operand:
D

byte

word

L
N
®

longword
quadword

F floating
D floating

G _floating

first data type specified by

instruction

second data type specified by instruction

1.1.3

Operation Description Notation

control
sequence of
The operation of each instruction is given as a
Table 4-1 describes the symbols used when
and assignment statements.
describing an operation.

SET

INSTRUCTION

SET

Table

4-1

Instruction

Operation

Symbols

Description
m‘mwmm*mmq—pm.gm

w-flmmMMMM““mmmm

mmumwmmmmmmmm—um

mmmwwm

addition
subtraction, undry minus
multiplication
division (quotient only)
exponentiation
concatenation

Rn or
rPC,
or

R[n]

SP,

FP,

PSW

PSL

(x)
(x)+

is replaced by
1s defined as
contents

the

contents

the

memory

processor
location

R13,

status
status

whose

word

long

word

address

x decremented
at

R14,

is x
of memory location whose address is x:
1ncremented by the size of operand referenced

contents

-(x)

the contents of register R15,
or R1lZ2 respectively
the contents of the processor

contents

size

memory

operand
location

referenced

whose

address

a modifier which delimits an extent from bit
position x to bit position y inclusive
<x1l,x2,..,%xn> a modifier which enumerates bits x1,x2,...,xn
arithmetic parentheses used to indicate precedence
{ }
AND
logical AND
|
OR
logical OR
XOR
logical XOR
NOT
logical (ones) complement
LSS
less than signed
LSSU
less than unsigned
LEQ
less than or equal signed
LEQU
less than or equal unsigned
EQL
-equal signed
EQLU
equal unsigned
NEQ
not equal signed
NEQU
not equal unsigned
<X:y>

GEQ

greater

than

GEQU

equal

signed

greater

than

equal

GTR

unsigned

greater
greater

than

signed

than

unsigned

GTRU

SEXT(x)
ZEXT(x)
REM(x,vy)
MINU(x,vy)
MAXU(x,v)

X 1s sign
needed

extended

size

operand

X 1s zero extended to size of operand needed
remainder of x divided by y, such that x/y
and REM(x,y) have the same sign
minimum unsigned of x and y
maximum unsigned of x and vy

INSTRUCTICON

The following conventions are used when describing the operation of an
instruction.

Other than that caused by

(

)+,

or -(

and

the

advancement

No operator precedence

assumed,

All arithmetic, logical, and relational operators are
defined
1in
the
context
of
their
operands.
For
example " "+"
applied to
floating coperands means a floating add, while "+" applied to
byte
operands
1is
an integer byte add.
Similarly, "LSS" 1is a floating
comparison when applied to floating operands, while
"LSS"
1is
an

PC,
only
operands
or portions of operands appearing on the
side of assignment statements are affected.

(<=)
has
the
explicitly by { }.

integer

byte

lowest

comparison

other

precedence.

when

applied

than

that

Precedence

byte

.is

left

replacement

1indicated

operands.

Instruction
operands
are
evaluated
according
to
the
operand
specifier
conventions.
The order 1in which operands appear in the
instruction description has no effect on the order of evaluation.

Condition codes are in general affected on
the
wvalue
of
actual
stored
results,
not
on "true" results (which might be generated
internally
to greater precision).
Thus, for example, two positive
integers

can

overflow, as
a
negative
positive.

added

together

and

the

sum

stored,

because

a negative value.
The condition codes will
value
even
though
the
"true"
result
1s
:

1ndicate
<clearly

SET

INSTRUCTION

4,2

SET

INTEGER ARITHMETIC AND

ADAWI

Add

Aligned

LOGICAL

Word

INSTRUCTIONS

Interlocked

Format:

opcode

add.rw,

sum.mw

Operation:
tmp

{set

sum

add;

interlock}:
<-

sum

{release

tmp;

interlock}:

Condition Codes:
N

sum

LSS

sum

EQL

0;
O0;

V <-

{integer overflow};

C <-

{carry from most

significant bit};

Exceptions:
reserved

operand

ilnteger overflow

fault

Opcodes:

ADAWI

Add

Aligned Word

Interlocked

Description:
The addend operand is added to the sum operand and the
replaced
by the result.
The operation is interlocked

sum operand
is
against similar

operations on
other
processors
in
a
multiprocessor
system.
The
destination
must
be
aligned
on a word boundary, i.e., bit 0 of the
address of the sum operand must be zero.
If it
1s
not,
a
reserved
operand fault 1s taken.
Notes:

Integer overflow occurs if the input operands to
same
sign and the result has the opposite sign.
sum operand 1s replaced by the low order bits of

If the addend and the sum operands
condition codes are unpredictable.

overlap,

the

On
the

add have
the
overflow, the
true result.

result

and

the

INSTRUCTION

Add

ADD

Format:

2 operand

opcode add.rx, sum.mx

‘

opcode addl.rx, addZ.r%, sum.wx 3 operand

Operation:
§12 operand

sum <- sum + add;

sum <- addl + add2?;

'3 operand

N<NZ

Condition Cocdes:

<- sum LSS 0;

sum EQL O;

{carry from most significant bit};

{integer overflow};

Exceptions:

integer overflow
Opcodes:

80
81
AQ
Al

ADDB2
ADDB3
ADDW2
ADDW3
ADDL2
ADDL3

Add
Add
Add
Add

Byte
Byte
Word
Word

2
3
2
3

Operand
Operand
Operand
Operand

Add Long 2 Operand
Add Long 3 Operand

Description:

In 2 operand format, the addend operand is added to the sum operand
In 3 operand format,
and the sum operand is replaced by the result.
and the sum
operand
2
the addend 1 operand is added to the addend

is replaced by the result.
operand

Notes:

Integer overflow occurs if the input operands to the add have the same
On overflow, the sum
sign and the result has the opposite sign.
result.
true
the
of
bits
order
low
the
by
operand is replaced

SET

INSTRUCTION

SET

ADWC

Add

With

Carry

Format:

opcode

add.rl,

sum.ml

Operation:
sum

O<NZ

Condition

sum

add

C;:

Codes:
<-

sum

LSS

sum

EQL

0O:

{integer overflow};

{carry

from most

significant

bit};

Exceptions:
lnteger

overflow

ADWC

Add With

Opcodes:

Carry

Description:
The

contents of
added
to
the
result.

the

condition

code

sum

operand

and

the

bit

and
sum

the

addend

operand

replaced

low

order

are

the

bits

Notes:

The

additions

sum

operand

the

operation

I
Qo

On overflow, the
the true result.

the

replaced

are

the

performed

simultaneously.

INSTRUCTION

Arithmetic Shift

ASH

Format:

opcode cnt.rb, src.rx, dst.wX
Operation:

dst <- src shifted cnt bits;
Condition Codes:

N <- dst LSS 0;
Z <- dst EQL 0;

Vv <C

{integer overflow};

Exceptlions:
integer overflow
Opcodes:

ASHL

ASHQ

Arithmetic Shift Long

Arithmetic Shift Quad

Description:

The source operand is arithmetically shifted by the number of bits
specified by the count operand and the destination operand 1s replaced
A positive count
by the result. The source operand is unaffected.
least significant
the
into
J's
operand shifts to the left bringing
in copies
bringing
right
the
bit. A negative count operand shifts to
bit. A O
ant
signific
most
the
of the most significant (sign) bit into
unshifted
the
with
operand
count operand replaces the destination
source operand.
Notes:

Integer overflow occurs on a left shift if any

the

sign

operand.

5
3.

bit

position

differs

bit

shifted

1into

from the sign bit of the source

cnt GTR 64 (ASHQ) the destination
orL)
If cnt GTR 32 (ASH

operand

~is replaced by 0.

If cnt LEQ -31 (ASHL) or cnt LEQ -63 (ASHQ) all the

destination
operand.

operand

are

copies

1-9

the

bits

the

sign bit of the source

SET

INSTRUCTION SET

BIC

Bit

Clear

Format:

opcode

mask.rx,

dst.mx

opcode

mask.rx,

src.rx,

dst.wx

operand

Operation:

dst

AND

{NOT mask}:

operand

dst

src

AND

{NOT mask}:

operand

Condition

Codes:

dst

LSS

dst

EQL

Exceptions:
none

Cpcodes:

3A
8B

BICB2
BICB3

Bit
Bit

Clear
Clear

Byte
Byte

BICWZ2

Bit

Clear

Word

BICW3

Bit

Clear

Word

BICL2

Bit

Clear

BICL3

Long

Bit

Clear

Long

Description:
In

operand

complement

format,
the

the

mask

destination

operand

and

operand

the

1s ANDed
with
the
ones
destination operand 1s replaced

by the result.
In 3 operand format, the source
the ones complement of the mask operand
and the
replaced by the result.

operand 1s ANDed
with
destination operand is

INSTRUCTION SET
BIS

Bit Set

Format:

opcode mask.rx,

dst.mx

opcode mask.rx, src.rx, dst.wx

operand

3 Operénd

Operation:

dst <- dst OR mask;

2 operand

dst

src

OR mask;

operand

Condition Codes:
N

<<-

dst

Z
vV

dst

LSS
EQL

O0;

Exceptions:
none

Opcodes:

BISB2

Bit Set Byte 2 Operand

89
A8
A9
C8
CS

BISB3
BISW2
BISW3
BISL2
BISL3

Bit
Bit
Bit
Bit
Bit

Set
Set
Set
Set
Set

Byte
Word
Word
Long
Long

3
2
3
2
3

Operand
Operand
Operand
Operand
Operand

Description:
In 2 operand format, the mask operand is
ORed
with
the
destination
operand
and
the destination operand is replaced by the result.
In 3
operand format, the mask operand is ORed with the source
operand
and
the destination operand is replaced by the result.

INSTRUCTION

SET

BIT

Bit

Test

Format:

opcodé

mask.rx,

Src.rx

Operation:
tmp

Condition

src

AND

mask;

Codes:

tmp

LSS

Z
V

<<=

tmp
0;

EQL

Exceptions:
none

Opcodes:

93
B3
D3

BITB
BITW
BITL

Bit
Bit
Bit

Test
Test
Test

Byte
Word
Long

Description:
The mask operand 1s ANDed with the
unaffected.
The only action 1s to

source
affect

operand.
condition

Both operands
codes.

are

INSTRUCTION

Clear

CLR

quaat:
opcode dst.wx
Operation:

dst <- O;§
Condition Codes:
N
2
vV

<<<-

0;
1;
0;

Exceptions:
none

Opcodes:

CLRB

Clear Byte

B4
D4

CLRW
CLRL

Clear Word
Clear Long

‘

CLRF

Clear

CLRQ
CLRD
CLRG

Clear Quad
Clear D_floating
Clear G_floating

F_floating

| Description:
The destination operand

replaced by 0.

Notes:

CLRx dst

equivalent

to MOVx

S"#0,dst,

but

byte

shorter.

SET

INSTRUCTION

SET

CMP

Compare*

Format:

odpcode

srcl.rx,

src2.rx

'Qperation:
srcl

src?2;

O <NZ

Condition Codes:
<<-

srcl

LSS
EQL

src2;
src2;

LSSU

src2:

Exceptions:
none

Opcodes:

91
Bl

CMPB
CMPW

Compare
Compare

Byte
Word

CMPL

Compare

Long

Description:
The

source

action

i1s

operand

compared

affect

the

condition

with

the

codes.

source

operand.

The

only

INSTRUCTION

CVT

Convert

Format:

opcode

src.rx,

dst.wy

Operation:

dst

conversion of

src;

Condition Codes:
N
2

<<-

dst
dst

V <C

LSS

EQL

{integer overflow};

Exceptions:
integer overflow
Opcodes:

93
98
33

CVTBW
CVTBL
CVTWB

Convert
Convert
Convert

Byte
Byte
Word

to Word
to Long
to Byte

F6
F7

CVTLB
CVTLW

Convert
Convert

Long
Long

to Byte
to Word

CVTWL

Convert Word to Long

Description:
The source operand 1s converted to the data type
of
the
destination
operand
and
the
destination
operand
1is
replaced
by
the result.
Conversion of a shorter
data
type
to
a
longer
1s
done
by
sign
extension;
conversion of longer to a shorter 1s done by truncation of

the higher

numbered

(most

significant)

bits.

Notes:

Integer overflow occurs 1f any truncated bits of
the
source
are not equal to the sign bit of the destlination operand.

operand

SET

INSTRUCTION

SET

DEC

Decrement

Format:

opcode

dif.mx

Operation:
dif

4dif

N<NZ

Condition Codes:
<<<<-

dif LSS 0;
dif EQL 0Q:
{integer overflow};
{borrow

into

most

significant

bit}:

Exceptions:

integer

overflow

Opcodes:

DECB

DECW

DECL

Decrement Byte
Decrement

Word

Decrement

Long

Description:

One 1s subtracted from
operand 1s replaced by

the
difference
the result.

operand

and

the

difference

Notes:

Integer
overflow
occurs
1if
the
largest
decremented.
On
overflow, the difference
the largest positive integer.

DECx

dif

equivalent

SUBx2

S"#1,dif,

negative
operand is

but

byte

integer
replaced

shorter.

" INSTRUCTICN SET

Divide

DIV

Format:

opcode divr.rx,

2 operand

guo.mx

opcode divr.rx, divd.rx,

quo.wx

3 operand

Operation:

quo <- quo / divr;
quo <- divd / divr;

!'2 operand
'3 operand

Condition Codes:
N<NZ

<- quo LSS 0;

<- quo EQL O0;
<- {integer overflow}
<-

{divr

EQL 0};

Exceptions:
integer overflow
divide by zero
Opcodes:

86
87
A6
A7
Cé6
C7

Divide
Divide
Divide
Divide
Divide
Divide

DIVB2
DIVB3
DIVW2
DIVW3
DIVL2
DIVL3

Byte
Byte
Word
Word
Long
Long

2
3
2
3
2
3

Operand
Operand
Operand
Operand
Operand
Operand

Description:

In 2 operand format, the quotient operand is divided
by
the
divisor
operand
and
the 'quotient
operand
1s replaced by the result.
In 3
operand format, the dividend operand 1is divided by the divisor operand
and the guotient operand 1s replaced by the result.
Notes:

Integer overflow occurs
integer
in

Note

divided by -1.

and

only

©On overflow,

the

largest

operands

negative

are affected as

INSTRUCTION

SET

If the divisor operand is 0, then in 2 operand format the quotient
operand
1s not affected; in 3 operand format the quotient operand
1s replaced by the dividend operand.
:

INSTRUCTION

Extended Divide

EDIV

Format:

opcode divr.rl, divd.rg, quo.wl,

rem.wl

Operation:

quo <- divd / divr;
rem <- REM(divd, divr);

N <NZ

Condition Codes:
<- guo LSS 0;
<- quo EQL O0;

{integer overflow}

{divr EQL 0};

Exceptions:
integer overflow
divide by zero
Opcodes:

Extended Divide

EDIV

Description:

the gquotient
The dividend operand is divided by the divisor operand;
is replaced by the quotient and the remainder operand ls
operand
replaced by the

remainder.

Notes:

~D)

The division is performed such that the remainder operand
it

is 0)

has the same sign as the dividend operand.

(unless

the quotient
then
0,
1is
On overflow or if the divisor operand
and the
operand,
1is replaced by bits 31:0 of the dividend
operand
remainder operand is replaced by 0.

INSTRUCTION

SET

EMUL

Extended

Multiply

Format:

opcode

mulr.rl,

muld.rl,

add.rl,

prod.wq

Operation:

prod
Condition

{muld

mulr}

SEXT(add):

Codes:

prod

LSS

prod

EQL

Exceptions:
none

Opcodes:

EMUL

Exténded Multiply

Description:

The multiplicand operand
is
multiplied
by
<hé
multiplier
operand
giving
a
quadword
result.
The addend operand 1is sign-extended to
a
quadword and added to the result.
The product operand is replaced
by
the final result.

INSTRUCTION

Increment

INC

Formart:

opcode sum.mx

Operation:
sum <-

sum

N<NZ

Condition Codes:

<<<<-

sum LSS 0;
sum EQL C;
{integer overflow};
{carry

from most

significant

bit};

Exceptions:
integer

overflow

Opcodes:
36

INCB

INCW

Increment Word

Increment

Byte

INCL

Increment

Long

Description:

One

is added to

the sum operand and the sum operand

replaced by the

result.
Notes:

Arithmetic overflow occurs if
incremented.
On
overflow,
largest negative lnteger,

INCx sum

is equivalent

the
the

largest
positive
1integer
1is
sum
operand 1s replaced by the
|

to ADDx2 S"#1l,sum,

but

1 byte shorter.

SET

INSTRUCTION SET
Move Complemented

MCOM

Format:

opcode

src.rx,

dst.wX

Operation:

dst <- NOT src;
N<NZ

Condition Codes:
<<-

dst LSS
dst EQL

0;
O0;

Exceptions:
none

Opcodes:

92
B2
D2

MCOMB
MCOMW
MCOML

Move Complemented Byte
Move Complemented Word
Move Complemented Long

Description:

replaced by

IV 35N

The destination operand
source operand.

the

ones

complement

the

INSTRUCTION

MNEG

Move

Negated

Format:

opcode src.rx, dst.wx
Operation:
dst

-src;

Condition Codes:
N <Z <-

V <C <-

dst
dst

LSS 0O;
EQL O;

{integer overflow};
dst NEQ 0;

Exceptions:

Vinteger overflow
Opcodes:

MNEGB

AE
CE

MNEGW
MNEGL

Move Negated Byte
Move
Move

Negated Word
Negated Long

Description:
The destination
operand.

operand

replaced by

negative

the

source

Notes:

Integer overflow occurs 1f
the
negative
integer
(which
has
overflow, the
destination
operand

operand

the

largest

positive
counterpart).
Oon
'
replaced
by
the
source

operand.

MNEGx src.rx,dst.wx 1s
1s one byte shorter

@QUIV&LEflt

SUBx3

src.rx,S"40,dst.rx,

but

SET

INSTRUCTION

MOV

SET

Move

Format:

opcode

src.rx,

dst.wX

Cperation:
dst

src;

Condition Codes:
N

dst

LSS

Z
vV

<<-

dst
0;

EQL

0Q:
|

Exceptions:
none

Opcodes:

90
BO
DO

MOVB
MOVW

Move
Move

MOVL

Move

Byte
Word
Long

MOVQ

Quad

Mowve

Description:
The destination

operand

replaced

the

source

operand.

INSTRUCTION

Move Zero-Extended

MOVZ

Format:

opcode src.rx,

dst.wy

Operation:

dst

<- ZEXT(src);

Condition Codes:
N
Z
vV

<<<-

0;
dst

EQL

Exceptions:
none

rOpcodes:
SB
9A
3C

MOVZBW
MOVZBL
MOVZWL

Move Zero-Extended Byte to Word
Move Zero-Extended Byte to Long
Move Zero-Extended Word to Long

Description:

For MOVZBW, bits
source
operand;
<7:0>

the

<7:0> of the destination operand are replaced by
the
bits
<15:8> are replaced by zero.
For MOVZBL, bits

destination

operand are

replaced by

the

source

operand;

bits
<31:8>
are
replaced
by
0.
For
MOVZWL,
bits <15:0> of the
destination operand are replaced by the source operand;
bits
<31l:16>
are

replaced by

SET

INSTRUCTION

SET

MUL

Multiply

Formati
opcode

mulr.rx,

prod.mx

opcode

mulr.rx,

muld.rx,

prod.wx

Operation;

operand

prod

prod <- muld

mulr;

* mulr;

operand

'3 operand

Condition Codes:
N

prod

LSS
EQL

0;
O;

V <-

{integer overflow};

Exceptions:

integer

overflow

Opcodes:
84

MULBZ2

Multiply

Byte

MULB3

Multiply

Byte

Operand

MULWZ2

Multiply

Word

Operand

MULW3

Multiply

Word

Operand

C4
C5

MULLZ2
MULL3

Multiply
Multiply

Long
Long

2
3

Operand
Operand

format,

the

product

Description:

In 2

operand

multiplied

the

multiplier operand and the product operand is replaced by the low half
of the double length result.
In 3 operand
format,
-he
multiplicand
operand
1s
multiplied
by
the
multiplier
operand
and the product
operand 1s replaced by the low half of the double length result.
Notes:

Integer

not

overflow

equal

occurs

the

sign

the

high

extension

half

the

low

double

half.

length

resuit

INSTRUCTION

Push Long

PUSHL

Formart:

opcode src.rl
Operation:

<- src;

-(SP)

Condition Codes:
src LSS 0;
src EQL 0;

N <Z <vV

Exceptlions:
none

Opcodes:

PUSHL

Push Long

Describtion:
‘The longword source operand is pushed on the stack.
Notes:

PUSHL is‘eQUivalent to MOVL src,-(SP), but is 1 byte shorter.

SET

INSTRUCTION

SET

ROTL -

Rotate

Long

Format:

opcode

cnt.rb,

src.rl,

dst.wl

Operation:

dst <- src rotated cnt”bits:

Condition Codes:
N

dst

LSS

dst

EQL

OQ;

Exceptions:
none

Opcodes:

ROTL

Rotate

Long

Description:
The

source
operand
1is
rotated
logically
by
the
number
of
bits
specified by the count operand and
the destination operand is replaced
by the result.
The source operand 1s unaffected.
A
positive
count
operand
rotates to the left.
A negative count operand rotat
es
fo
the
right.
A 0 count operand replaces the
destination
operand
with
the
source

operand.

INSTRUCTION
SET
SBWC

Subtract With Carry

Format:

pcode

sub.rl,

dif.ml

Operation:
dif

dif

sub

N<NZ

Condition éodes:

<<-

dif LSS
di1f EQL

0;
0;

{integer

{borrow

overflow};
into most significant

bit};

Exceptions:
integer

overflow

SBWC

Subtract

Opcodes:

With Carry

Description:
The

are

subtrahend

subtracted

replaced by

operand

from

the

and

the

contents

difference

result.

operand

the

and

condition

the

code

difference

bit

operand

‘

Notes:

On overflow, the difference
bits of the true result.

The

subtractions

the

operand

operation

are

replaced

performed

the

low

order

simultaneously.

INSTRUCTION

SET

SUB

Subtract

Format:

opcode sub.rx, dif.mx
opcode

sub.rx,

2 operand

min.rx,

dif.wx

operand

Operation:
dif

dif

sub;

operand

dif

min

sub;

operand

N <N
Z

Condition Codes:
<<-

dif
dif

LSS
EQL

{integer

{borrow

0;
O;
overflow};
into most significant

bit};

Exceptions:
integer

overflow

Opcodes:

32
83

SUBBZ2
SUBB3

Subtract
Subtract

Byte
Byte

SUBW3

Subtract

C2
C3

SUBL2
SUBL3

Subtract
Subtract

SUBW2

2
3

Operand
Operand

Word

Operand

Long
Long

2
3

Operand
Operand

Subtract Word

2 Operand

Description:

In 2 operand format,
difference
operand

the subtrahend operand
is
subtracted
from
and
the
difference
operand
1is replaced by

result.
In 3 operand format, the
subtrahend
operand
from the minuend operand and the difference operand is
result,

the
the

1is
subtracted
replaced by the

Notes:

{al

Integer overflow occurs 1:f the input operands to the subtract
are
different
signs
and
the
sign
of
the
result
1is
the sign of
subtrahend.
On overflow, the difference operand is
replaced
by
low order bits of the true result.

of
the
<the

INSTRUCTION

Test

TST

Format:

sSrc.rx

opcode

Operation:

src

Condition Codes:
N <Z <-

src
src

C <-

LSS
EQL

0;
0;

Exceptions:
none

Opcodes:

95
BS
D5

TSTB
TSTW
TSTL,

Test
Test
Test

Byte
Word
Long

Description:

. The condition codes are affected according to the value of the
operand.
Notes:

TSTx src

is equivalent

to CMPx src,S"#0,

but

1is

byte

shorter.

source

SET

INSTRUCTION

SET

XOR

Exclusive OR

Format:

opcodé mask.rx, dst.mx

2 operand

opcode mask.rx, src.rx, dst.wx

3 operand

Operation:

dst

XOR mask;

‘dst <- src XOR maék;

'3 operand

Condition Codes:
N

Z
vV

<<<-

dst
dst

operand

‘
LSS
EQL

0;
0;

0;
C;

Exceptions:
none

Opcodes:

8C
8D
AC
AD
CC
CD

XORB2
XORB3
XORW2
XORW3

Exclusive
Exclusive
Exclusive
Exclusive

OR Byte
OR 3Byte
OR Word
OR Word

2
3
2
3

XORL2
XORL3

Exclusive OR Long
Exclusive OR Long

2
3

Operand
Operand
Operand
Operand
Operand
Operand

Description:
In 2 operand format, the mask operand is XORed
with
the
destination
operand
and
the destination operand is replaced by the result.
In 3
operand format, the mask operand is XORed with the source operand
and
the destination operand is replaced by the result.

INSTRUCTICN

4.3

INSTRUCTIONS

ADDRESS

- MOovA

Move Address

Format:

opcode

src.ax,

dst.wl

Operation:
dst

Src;

Condition Cod es.

VvV

dst
dst
<- Q:

LSS
EQL

0O;
O;

Exceptlions:
none

Opcodes:

MOVAB

MOV AW

MOVAL

MOVAF
MOVAQ
MOVAD
MOVAG

Address Byte.
Address Wword
Move Address Long
Move Address F _floating
Move Address Quad
Move Address D floating
Move Address G floating
Move

Move

Description:
operand.
The
replaced
by
The destination operand
1s
context
1n which the source operand is evaluated 1s gilven by the data
replaces
the
The
operand
address
type of the instruction.
destination operand is not referenced.

SET

INSTRUCTION

SET

PUSHA

Push

Address

Format:

opcode

Src.ax

Operation:

-{SP)

src;

Condition Codes:
N
Z
vV

<<=
<-

src
src
0;

LSS
EQL

0;
0;

Exceptions:
none

Opcodes:

SF
3F
DF
7F

PUSHAB
PUSHAW
PUSHAL
PUSHAF
PUSHAQ
PUSHAD
PUSHAG

Push
Push
Push
Push
Push
Push
Push

Address
Address
Address
Address
Address
Address
Address

Byte
Word
Long
F_floating
Quad
D floating
G floating

Description:
The source operand 1s pushed on
source
operand
1s
evaluated
instruction.
The operand whose

the stack.
1s
given
address 1s

The context in
which
the
by
the
data
type
of the
pushed is not referenced.

Notes:

PUSHAx

src

1is

equivalent

to MOVAx

src,-(SP),

but

byte

shorter.

INSTRUCTION SET
4.4

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

A variable length bit field is specified by 3 operands:
1.

A longword position operand.

A byte field size operand which must be in the range J through

to locate
A base address (relative to which the position is usedan opera
nd of
from
The address 1is obtained
the bit field).
d
operan
of
ces
instan
address access type. However, unlike other
ated
design
be
may
mode
specifiers of address access type, register
in the operand specifier. In this case the field is contained 1in

or a reserved operand fault occurs.

register
the register n designated by the operand specifier (or ned
in a
contai
is
{ield
the
If
n).
n+1 -concatenated with register
a
have
must
d
operan
on
positi
the
register and size 1is not zero,
fault
operand
d
reserve
a
or
31
vaiue in the range 0 through
|

occurs.

In order to simplify the description of the variable cedbitwithfield
the
instructions, a macro FIELD(pos, size, address) 1s introdu

following expansion (if size NEQ 0):

FIELD(pos,

size, address)

(address + SEXT(pos<31:3>})%{size - 1} + pos<2:02:pos<2:0>>

tif address not specified by register mode

{R[n+1]'Rni<{size - 1} + pos:pos>

|if address specified by register mode and pos + size
i

'GTRU 32

Rn<{size - 1}

+ pos:pos>

'if address specified by register mode and pos + size
'LEQU

The number of bytes referenced by the contents ( ) operator
above

1s:

1 -

i{i{size - 1} + pos<2:0>! / 8}

Zero bytes are referenced if the fleld size 1s O.

'INSTRUCTION SET
CMP

Compare

Field

Format:

opcode

pos.rl,

size.rb,

base.vb,

src.rl

Operation:

tmp

size

tmp

NEQU 0 then
else 0;

size

NEQU

else
tmp

then
0;

SEXT(FIELD

(pos,
{CMPV
ZEXT(FIELD (pos,
ICMPZV

size,

base))

size,

base))

base

operands

src;

Condition Codes:
N

tmp

LSS

src;

tmp

EQL

src;

tmp

LSSU

src;

Exceptions:
reserved

operand

Opceodes:
EC

CMPYV

Compare

Field

CMPZV

Compare

Zero-Extended

|
Field

Description:
The

field

compared

specified
with

with

the

source

sign

position,
operand.

extended

s
compared
with
the
zero
affect the condition codes.

size,
For

field.

extended

For

and

CMPV,

the

CMPZV,

field.

source

the

The

operand

source

only

is
1s

operand

action

Notes:

reserved

da.

sSize

pos GTRU 31,
reglsters,

operand

GTRU

fault

occurs

if:

32.
size

NEQ

and

the

field

1is

contained

the

INSTRUCTION

reserved

unpredictable.

operand

fault,

the

condition

codes

are

SET

INSTRUCTION

SET

EXT

ExXxtract

Field

Format:

opcode

pos.rl,

size.rb,

base.vb,

dst.wl

Operation:

dst

size

NEQU 0 then
else Q;

SEXT(FIELD(pos, size,
'EXTV
»

base))
|

dst

size

NEQU

ZEXT(FIELD(pos,

base))

Condition

else

then
0:

size,

VEXTZV

Codes:

dst

LSS

dst

EQL

Exceptions:

reserved operand
Opcodes:
EE

EXTV

Extract

Field

EXTZV

Extract

Zero-Extended

Field

Description:
For

EXTV,

the

destination

operand

replaced

the

sign

extended

field
specified by the position, size, and base operands.
For EXTZV,
the destination
operand
1is
replaced
by
the
zero
extended
field
specified
by
the
position,
size
and
base
operands.
I[f the size
operand 1s 0, the only action is to replace
the
destination
operand

with

and

affect

the

condition

codes.

Notes:

reserved

operand

size GTRU 32.

pos GTRU 31,
reglsters.

fault

size

NEQ

occurs

and

if:

the

field

1is

contained

1in

the

INSTRUCTICN

On a reserved operand fault, the destination operand
and the condition codes are unpredictable.

is unaffected

SET

INSTRUCTION

SET

Find

Firsrt

Format:

opcode

startpos.rl,

size.rb,

base.vb,

findpos.wl

Operation:

state
1f

size

{FFS}

NEQU 0
begin

then

0:
:

tmpl

FIELD(startpos,

tmp2

while

{tmpl<tmp2>

{tmp2

LEQU

tmpl

<f{indpos

end

NEQ

size,

state}

{size

base):

AND

1l}}

tmp2;

tmp2

+ 1;
startpos

else

findpos
Condition

else

startpos;

Codes:

{bit

V.<-

not

found};

Exceptions:
reserved

operand

Cpcodes:
EB

FFC

FFS

Find
Find

First
First

Clear
Set

Description:

A field specified by the start position, size, and
base
operands
1is
extracted.
The
field
1is tested for a bit in the state indicated by
the instruction, starting at bit 0 and extending to the nignest blt in
the
£field.
If
a
bit
in
the
1indicated
state is found, the find
position operand is replaced by the position of the
bit,
and
+the
2
condition
code
Dbit
is cleared.
If no bit in the indicated state is
found, the find position operand is replaced by the position (relative
to

the

and

find
the

base)

of a bit one position to the left of the specified field,
Z condition code bit is set.
If the size operand
1is
0,
the
position
operand is replaced by the start position operand, and
condition code bit is set.

the

INSTRUCTION

Notes:

A reserved operand fault occurs 1f:
a.

size GTRU 32.

startpos GTRU 31, size NEQ 0, and the field
the

1is

contained

position

operand

1is

reglisters.

reserved

operand

fault,

the

find

unaffected and the condition codes are unpredictable.

SET

INSTRUCTION

SET

INSV

Insert

Field

Format:

opcode sra;r , pos.rl, size.rb, baSe.vb‘
Cperation:

if
Condition

size

NEQU

then

FIELD(pos,

size,

base)

src<{size-1}:0>;

Codes:

2Z:

Exceptions:
reserved

operand

Opcodes:

INSV

Insert

Field

Description:
The field
replaced
1s 0, the

specified by
the
position,
size,
and
by bits size-1:0 of the source operand.

instruction

has

effect.

base
If the

operands
1is
size operand

Notes:

reserved

size

pos GTRU 31,
registers.

operand

GTRU

fault

occurs

if:

32.
size

NEQ

and

the

field

On a reserved operand fault,
the field
condition codes are unpredictable.

1is

contained

unaffected

the

and

the

INSTRUCTION SET
4.5

CONTROL

INSTRUCTIONS

Add Compare

~ACB

and Branch

Format:

opcode

limit.rx,

Operation:
-

index.mx,

displ.bw

;

index

{{add GEQ 0}

add;

AND

{index

LEQ

limit}}

{{add LSS 0} AND {index GEQ limit}}

add.rx,

SEXT(displ);

then

Condition Codes:
N
Z
V
C

<<<<-

1index LSS O0;
1ndex EQL O0;
{integer overflow};
C;

Exceptions:
integer

overflow

ACBB
ACBW
ACBL

Add Compare
Add Compare

Cpcodes:

9D
3D
F1l

Add Compare

and Branch Byte
and Branch Word
and Branch Long

Description:
The addend operand 1s added to the index operand and the index operand
1s
replaced
by
the
result.
The index operand
is compared with the
limit operand.
If the addend operand
1is
positive
(or
0)
and
the
comparison 1s less than or equal, or 1f the addend is negative and the
comparison
1s
greater
than
or
equal,
the
sign-extended
branch
displacement is added to PC and PC is replaced by the result.

INSTRUCTION

SET

Notes:
)

ACB efficiently implements the general FOR or
DO
loops
in
level
languages,
since the sense of the comparison between
and limit 1s dependent on the sign of the addend.

high
index

On 1integer overflow, the index operand
1is
replaced
by
the
low
order
bits
ot
the
true
result.
Comparison
and
branch
determination proceed normally on the updated index operand.

INSTRUCTION

Add One and Branch Less Than or Equal

AOBLEQ

Format:

opcode

index.ml, displ.bb

limict.rl,

Operation:

index <- index + 1;
if

index LEQ limit then PC <PC + SEXT(displ);

Condition Codes:
N <Z <-

1ndex
1ndex

V <<-

LSS 0;
EQL 0;
{integer overflow};

Exceptions:

integer overflow
Opcodes:

AOBLEQ

Add One and Branch Less Than or Equal

Description:

One is added to the index operand and the index operand is replaced by
the result.
The index operand is compared with the limit operand.
If
it is less than or equal, the
sign-extended
branch
displacement
1is
added to PC and PC is replaced by the result.
Notes:

Integer overflow occurs if the index operand before
addition
largest
positive integer.
On overflow, the index operand is
by the largest negative integer, and the branch 1s taken.

1s
the
replaced

SET

INSTRUCTION

SET

AOBLSS

Add

One

and

Branch

Less

Than

Format:

opcode

limit.rl,

index.ml,

displ.bb

Operation:

index <1f index

index + 1;
LSS limit then PC
PC + SEXT(displ);

N<NZ

Condition Codes:
<<<<-

1ndex
1index

LSS
EQL

{integer

0:
O0:
overflow};

Exceptions:
integer

overflow

AOBLSS

Add One and Branch Less Than

Opcodes:

F2.

Description:
One

added

the

index

operand

and

the

index

operand

the result.
The index operand is compared with the limit
it 1s less than, the sign-extended branch displacement is
PC and PC 1is replaced by the result.

replaced
operand.

added

by
If
the

Notes:

Integer

overflow

occurs

the

index

operand

before

addition

the

largest
positive integer.
On overflow, the index operand is replaced
by the largest negative integer, and, unless the limit operand is
the
largest negative 1integer, the branch is taken.

INSTRUCTION

SBranch on

(condition)

Format:

opcode displ.bb

Operation:

‘

1f condition then PC <- PC + SEXT(displS:

Cohdition Codes:

‘

N <- N3
2

Exceptions:
none

Opcodes:

Condition

{N OR Z}

EQL O

BGTR

(N OR Z}

EQL

Z EQL

BLEQ
|

Z EQL

N EQL

19
1A

N EQL 1
{C OR Z}

EQL O

BLSS
BGTRU

{C OR Z}

EQL

BLEQU

BNEQ,
BNEQU

BEQL,

BEQLU
BGEQ

Branch on Greater Than
(signed)
|
Branch on Less Than or Equal
(signed)
|
Branch on Not Equal (signed)
Branch on Not

Equal

Branch on Equal

Unsigned

(signed)

Branch on Equal Unsigned
Branch on Greater Than or
Equal (signed)
Branch on Less Than (signed)

Branch on Greater Than
Unsigned

Branch Less Than or Equal

Unsigned
1C
1D
1E

Vv
V
C

EQL
EQL
EQL

O
1
O

EQL

BVC
BVS
BGEQU,
|

Branch on Overflow Clear
Branch on Overflow Set
Branch on Greater Than or
Equal Unsigned

3CC

Branch

BLSSU,
3CS

Carry

Clear

Branch on Less Than Unsigned
~Branch on Carry Set

SET

INSTRUCTION

SET

Description:
The condition codes are tested and if the condition indicated
instruction
1s met, the sign-extended branch displacement is
the PC and PC is replaced by the result.

by
the
added to

Notes:

The

VAX
conditional
branch
flexibility
1in
branching
but

branch instruction.
The
as 3 overlapplng groups:
l.

Overflow

and

Carry

-instructions
permit
considerable
require
care in choosing the correct
conditional branch instructions are best seen

Group

BVS

EQL

BVC

EQL

BCS

EQL

BCC

EQL

These 1nstructions are typically used to check for overflow
(when
overflow
traps
are
not enabled), for multiprecision arithmetic,
and for other special purposes.
|

Unsigned Group
BLSSU

These
where

Signed

EQL

BEQLU

EQL

BNEQU

EQL

BGTRU

EQL

{C OR Z}

instructions
the

EQL

typically

operands

are

treated

and character

string

integer
as

and

wunsigned

field

instructions

integers,

instructions.

address

Group
BLSS

BLEQ

{N OR Z}

BEQL

EQL

BNEQ

EQL

BGEQ

EQL

{N OR Z}

These instructions

point

EQL

BGEQU

BGTR

where

{C OR Z}

instructions,
3.

BLEQU

the

operands

instructions,

EQL

EQL O

typically
are

being

integer

treated

and decimal

string

and

signed

field

instrucrtions

integers,

instructions.

flcating

INSTRUCTION SET
Branch on Bit

?Qrmat:
opcode pos.rl,

base.vb, displ.bb

Operation:

teststate = if {BBS} then 1 else O0;
if FIELD(pos, 1, base) EQL teststate then
PC <- PC + SEXT(displ);
Condition Codes:
Ny

Exceptions:

reserved operand
Opcodes:

EQ
E1l

Branch on Bit Set
Branch on Bit Clear

BBS
BBC

Description:

The single bit field specified by the position and base operands is
If it is in the test state indicated by the instruction, the
tested.
sign-extended branch displacement is added to PC and PC is replaced by
the

result.

Notes:

A reserved operand fault occurs if pos GTRU

the

bit

contained in a register.

reserved

unpredictable.

operand

fault,

the

condition

codes

are

INSTRUCTION

SET

Branch

Bit

(and

modify

without

interlock)

Format:

opcode

pos.rl,

base.vb,

displ.bb

Operation:

teststate = if {BBSS or BBSC} then 1 else 0:
newstate = if {BBSS or BBCS} then 1 else 0:
tmp <- FIELD(pos, 1, base);
FIELD(pos, 1, base) <- newstate:
1f tmp EQL teststate then
PC

Condition

SEXT(displ);

Codes:

Exceptions:
reserved

operand

Opcodes:

E2
E3

BBSS
BBCS

Branch on
Branch on

Bit
Bit

Set and Set
Clear and Set

BBSC

Branch

Bit

Set

BBCC

Branch on

Bit

Clear

and

Clear

and Clear

Description:

The single bit field specified by the position and
base
operands
is
tested.
If 1t 1s in the test state indicated by the instruction, the
sign-extended branch displacement is added to PC and PC is replaced by
the
result.
Regardless
of
whether the branch is taken or not, the
tested bit is put in the new state as indicated by the instruction.
Notes:

A reserved operand fault
contained in a register.

2.
-

occurs

On a reserved operand fault,
the
condition codes are unpredictable.

pos

GTRU

field

1is

and

the

unaffected

bit

and

+he

INSTRUCTION

The modification of the bit is not an interlocked operation.
BBSSI

and BBCCI

for

interlocking

4-51

instructions.

See

SET

INSTRUCTION SET
BB

Branch on Bit

Interlocked

Format:

opcode pds.rl,
L

base.vb,

displ.bb

Operation:

teststate =
newstate

{set

{BBSSI}

then

else O0:

teststate;

interlock};

tmp <- FIELD(pos, 1, base);
FIELD(pos, 1, base) <- newstate;
{release interlock}:
1f tmp EQL teststate then
PC <- PC + SEXT(displ);

Condition Codes:
N

2Z:

Exceptions:
reserved operand

Opcodes:

BBSSI

Branch on Bit Set

BBCCI

Branch on

Bit

and Set

Clear

Interlocked

and Clear

Interlocked

Description:
The single bit field specified by the position and
base
operands
1is
tested.
If 1t 1s 1n the test state 1indicated by the instruction, the
sign-extended branch displacement
1is
added
¢to
the
PC
and
PC
is
replaced
by the result.
Regardless of whether the branch 1s effected
or not, the tested bit is put in the new state
as
1indicated
by
the
instruction.
If
the
bit is contained in memory, the reading of the
state of the bit and the
setting
of
1t
to
the
new
state
1s
an
ilnterlocked
operation.
No
other
processor or /0 device can do an
interlocked access on the bit during the interlocked operation.
Notes:

A reserved operand fault
contained in a register.

occurs

pos

GTRU

and

<the

Dbit

1is

INSTRUCTION

" On a reserved operand fault,

the

condition codes are unpredictable.

field

Except for memory interlocking BBSSI
BBCCI

is equivalent

to BBCC.

This instrtiction is designed
processors or devices.

Example:

To
1S:

implement
BBSSI

support

"busy waiting”
bit,base,1l$

wunaffected

equivalent
interlocks

and

the

BBSS

and

with

other

SET

INSTRUCTICN

SET

BLB

Branch

Low

Bit

'Format:
opcode
Operation:

src.rl,

displ.bb

teststate = if {BLBS} then 1 else 0:
1f

src<0> EQL teststate then
PC <- PC + SEXT(displ);

Condition Codes:
N

Exceptions:
none

Opcodes:

E8
ES

BLBS
BLBC

Branch
Branch

on
on

Low Bit
Low Bit

the

source

Set
Clear

Description:
The

low bit

the

(bit

test

state

branch displacement

1ndicated

added

operand
by

the

tested

instruction,

and PC

and
the

replaced by

equal

sign-extended

the

result.

INSTRUCTION

- Branch

" BR

Format:

opcode displ.bx
Operation:

PC <- PC + SEXT(displ);
Condition Codes:
N

FARS

<=V,

Exceptions:
none

Opcodes:

11
31

BRB
BRW

Branch With Byte Displacement
Branch With Word Displacement

Description:

The sign-extended branch
replaced by

the

result.

displacement

and

1is

SET

INSTRUCTION
SET

BSB

‘

Branch To Subroutine

Format:

" opcode displ.bx
Operation:

-(SP)

PC;

SEXT(displ);

C@ndition‘Codes:
N

Exceptions:
none

Opcodes:

10
30

BSBB
BSBW

Branch
Branch

to
to

Subroutine With Byte
Subroutine With Word

Displacement
Displacement

Description:
PC 1s pushed on
displacement is

the stack as a
longword.
The
sign-extended
added to PC and PC is replaced by the result.

branch

INSTRUCTION SET
Case

CASE

Format:

opcode selector.rx, base.rx, limit.rx,
displ{0].bw,...,

displ(limit].bw

Operation:

tmp <- selector - base;
PC <- PC + 1f tmp LEQU limit then
SEXT(displ(tmp]) else {2 +

* ZEXT(limit)};

N<NZ

Condition Codes:

<<-

tmp LSS
tmp EQL

tmp

LSSU

limit;
limit;
limit;

Exceptions:
none

Opcodes:

CASEB

Case Byte

CASEL

Case

CASEW

Case Word
Long

Description:
The base operand
1s
subtracted
from
the
temporary
1s
replaced by the result.
The
the limit operand and if it 1s less than or

selector
operand
and
a
temporary 1s compared with
equal unsigned,
a
branch
"displacement
selected by the temporary value is added to PC and PC 1is
replaced by the result.
Otherwise, 2
times
the
sum
of
the
limit
operand
and
1 is added to PC and PC 1s replaced by the result.
This
~causes
PC to
be moved
past
the
array
of
branch
displacements.
Regardless
of
the
branch taken, the condition codes are affected by
the comparison of the temporary operand with the limit operand.
Notes:

After operand evaluation,
instruction.

of displ(0].

The

is pointing

branch displacements

at displ{0],

are

relative

not
the

the

address

INSTRUCTION

SET

The selector

signed or

and

base

unsigned

operands

integers.

can

both

considered

either

INSTRUCTION

Jump

JMP

Format:

opcode dst.ab
Operation:

PC <- dst:
Condition Codes:
N

Z
V

<=
<=

Exceptlions:
none

Opcodes:
17

JMP

Jump

Description:

PC is replaced by the destination operand.

SET

INSTRUCTION

SET

JSB

Jump

Subroutine

Format:

opcode

dst.ab

Operation:

-(SP)

<- PC:

dst;

Condition
N

Codes:
<-

Z <- Z;

Exceptions:
none

Opcodes:
l6

JSB

Jump

Subroutine

Description:

PC is pushed on the stack
destination operand.

longword.

replaced

the

Notes:

Since

the operand specifier

destination

calls

with

2 (SP)+.

operand
the stack

conventions

before
used for

cause

the

saving PC, JSB can
linkage.
The form

evaluation
be
of

used
such

for coroutine
a call 1s JSB

INSTRUCTION

Return from Subroutine

RSB

Format:

opcode

‘

Operation:

PC <- (SP)+;
Condition Codes:
N

Exceptions:
none

Opcodes:

RSB

Return From Subroutine

Description:

is replaced by a

longword popped from the stack.

Notes:

RSB is used to return
and JSB instructions.

RSB

is equivalent

from subroutines called by

to JMP 3(SP)+,

but

the

1 byte shorter.

BSBB,

BSBW

SET

INSTRUCTION

SET

SOBGEQ

Subtract

One

and

Branch

Greater

Than

Equal

Format:

opcode

index.ml,

displ.bb

Operation:

index <-

index -

index GEQ 0 then PC <PC + SEXT(displ);

Condition Codes:
N
Z

V
C

<<<<=

1ndex LSS 0;
1ndex EQL 0O:
{integer overflow};
C;

Exceptlions:

integer

overflow

Opcodes:
F4

SOBGEQ

Subtract

One

and

Branch

Greater

Than

Equal

Description:
One 1s subtracted from the index operand
and
the
index
operand
is
replaced by the result.
If the index operand is greater than or equal
to 0, the sign-extended branch displacement is added to PC and
PC
is
replaced by the result.
Notes:

Integer overflow occurs if the index operand before subtraction is the
largest
negative integer.
On overflow, the index operand is replaced
by the largest positive integer, and the branch is taken.

INSTRUCTION SET

Subtract One and Branch Greater Than

SOBGTR

Format:

opcode

index.ml, displ.bb

Operation:

‘index <- index - 1;

index GTR 0 then PC <PC + SEXT(displ);

Condition Codes:
N <Z <-

V <C

1ndex LSS 0O;
index EQL O0;

{integer overflow};

Exceptlions:

integer overflow
Opcodes:

SOBGTR

Sgbtract One and Branch Greater Than

Description:

One is subtracted from the index operand
and
the
1ndex
operand
1s
replaced
by
the result.
If the index operand 1S greater than 0, the
sign-extended branch displacement is added to PC and PC 1s replaced
by
the

result.

Notes:

Integer overflow occurs if the index operand before subtraction 1s the
largest
negative 1nteger,
On overflow, the index operand 1s replaced
by the largest positive integer, and the branch 1s taken.

INSTRUCTION SET

4.6

PROCEDURE CALL

INSTRUCTIONS

calling
Three instructions are used to implement a standard procedure
Two instructions implement the CALL to the procedure; the
interface.
a
The CALLG instruction calls
third implements the matching RETURN.
list actuals in an arbiltrary location.
argument
the
procedure with
The CALLS instruction calls a procedure with the argument list actuals
Upon return after a CALLS this list 1is automatically
on the stack.
Both call instructions specify the address of
removed from the stack.
The entry polnt 1s
the procedure being called.
of
the entry point
the
followed by
assumed to consist of a word termed the entry mask
RET
a
executing
by
terminates
The procedure
procedure's instructions.
instruction.

The entry mask, Figure 4-1, specifies the procedure's reglster use and
cverflow enables:

MBZ

REGISTERS

L
MR-13424

Figure

4-1

Entry Mask

trap
the
longword bouhdary and
On CALL the stack is aligned to a
consistent
to a known state to ensure
in the PSW are set
enables
Integer overflow enable and decimal
behavior of the called procedure.
overflow 2nable are affected according to bits 14 and 15 of the entry
The
1is <cleared.
Floating wunderflow enable
mask respectively.

registers R1ll through RO specified by bits 11 through 0 respectively
In
1instruction,
are saved on the stack and are restored by the RET

preserved
always
and AP are
FP,
SP,
PC,
addition,
instruction.
RET
instructions and restored by the

Dby the CALL

language
software
The
subsystems, comply with the procedure calling software standard.
RZ2
range
the
in
registers
all
that
requires
procedure calling standard
RI
and
RO
mask.
the
in
appear
must
procedure
the
in
through R11l used
the
with
complies
tnat
procedure
called
any
by
preserved
are not

All external procedure CALLs generated by standard DIGITAL
1inter-module CALLs to major VAX
all
and
processors,

procedure calling

standard.

In order to preserve the state,

the CALL instructions form a structure

This contains the
on the stack termed a call frame or stack frame.
and several
saved registers, the saved PSW, the register save mask,
the CALL
which
& longword
1includes
also
frame
The
control Dbits.
condition
VAX/VMS
the
instructions clear: this is used to implement
+-64

INSTRUCTION

At the end of execution of the CALL instruction,
facility.
handling
The RET 1lnstruction uses
FP contains the address of the stack frame.
the contents
of
FP
to find the stack frame and restore state.
The
condition handling facility assumes that FP always points to the stack
frame.

The stack frame has the format shown in Figure 4-2.

,
SPA

0‘

0>
MASK{% 1:0>

CONDITION HANDLER (INITIALLY 0)
SAVED

BSW<14ES

SAVED AP

SAVED FP

SAVED PC

SAVED RO {. . )

SAVED R11 {.: )

(O TO 3 BYTES SPECIFIED BY SPA, STACK POINTER ALIGNMENT)
S = SETIF CALLS; CLEARIF CALLG.
Z = ALWAYS CLEARED BY CALL. CAN BE SET BY SDFTWAHE TO FORCE
A RESERVED OPERAND FAULT ON A RET.
|
MR-13425

Figure

Note that the
saved
(PSW<T>) are cleared.

4-2

condition

Stack

<codes

Frame

and

the

The contents of the frame PSW<3:0>
at the time RET

become

the

condition

codes

resulting from

saved

trace

1is

executed

the

execution

procedure.
Similarly, the content of the frame PSW<i1> at
RET is executed will become the PSW<T> bit.

enable

will

of <he

the time

the

SET

INSTRUCTION SET
- CALLG

Call

Procedure

With

General

Argument

List

Format:

opcode

arglist.ab,

dst.ab

Operation:

falign stackt};
{create stack frame};

{set arithmetic exception enables};
{set

new values of AP,FP,PC};

Condition Codes:
N
Z

<<-

0;
0;

Exceptions:

reserved operand

Opcodes:

CALLG

Call Procédure with General Argument List

Description:

SP 1s saved in a temporary and then bits 1:0 are replaced by 0 so that
the
stack
1s
longword aligned.
The procedure entry mask is scanned
from
bit
11
to
0O
and
the
contents
of
registers
whose
number
corresponds
to
set
bits
1n
the
mask
are
pushed on the stack as
longwords.
PC, FP, and AP are pushed on the stack as longwords.
The
condition
codes are cleared.
A longword containing the saved two low
bits of SP in bits 31:30, a 0 in bit 29 and bit 28, the low 12 bits of
the procedure entry mask 1in bits 27:16, a 0 in bit 15 and PSW<1l4:0> 1in
bits 14:0 with T cleared is pushed on the
stack.
A
longword
0
1is
pushed
on
the
stack.
FP 1s replaced by SP.
AP is replaced by the
arglist operand.
The trap enables in the
PSW
are
set
to
a
known
state.
Integer
overflow and decimal overflow are affected according
to bits 14 and 15 of the entry mask respectively;
floating
underflow
1s
cleared.
T-bit
1s
wunaffected.
PC
1s
replaced by the sum of
destination operand plus 2, which
transfers
control
to
the
called
procedure

stack

after

the
CALLG

byte

beyond
instruction

the

entry mask.
The
executed is shown

appearance

Figure

of the
4-3.

INSTRUCTICON

SP
‘FP

STACK FRAME

(O TO 3 BYTES SPECIFIED BY SPA)
MR- 13428

Figure

4-3

CALLG Stack

Frame

Notes:

If bits 13:12 of the entry mask are

not

the

The procedure calling standard.-and the condition handling facility
require
the following register saving conventions.
RO and Rl are
always available for function return values and are never saved 1in
the
entry mask.
All registers R2 through Rl1l which are modified

fault

occurs.

reserved

unpredictable.

—operand

in the called procedure must

fault,

reserved

condition

be preserved
in the mask.

- 1-67

operand

codes
:

are

SET

INSTRUCTICON
SET

CALLS

Call

Procedure

with

Stack

Argument

List

Format:

opcode numarg.rl, dst.ab
Operation:

{push arg count};

{align stack};
{create stack frame};
{set arithmetic exception

enables}:
{set new values of AP,FP,PC};

Condition Codes:
N

<<=

Z
V

Exceptions:
reserved

operand

Cpcodes:
FB

CALLS

Call

Procedure

With

Stack

Argument

List

Description:
The numarg operand is pushed on
the
stack
as
a
longword
(byte
0
contains
the
number of arguments, the high order 24 bits are used by
DIGITAL software).
SP 1s saved in a temporary and then bits 1:0 of SP
are
replaced
by
0
so
that
the
stack
1is
longword aligned.
The
procedure entry mask is scanned from bit 11 to bit 0 and the
contents
of
registers
whose
number
corresponds
to set bits in the mask are
pushed on the stack.
PC, FP, and
AP
are
pushed
on
the
stack
as

longwords.

The

«condition

codes

are

cleared.

longword containing

the saved two low bits of SP in bits 31:30, a 1 in bit 29, a 0 in
bit
28,
the low 12 bits of the procedure entry mask in bits 27:16, a 0 in
bit 15 and PSW<14:0> in bits 14:0 with T
cleared
1is
pushed
on
the
stack.
A
longword
93 1is pushed on the stack.
FP is replaced bv SP.
AP 1s set to the value of the stack pointer after the
numarg
operand
was

known

pushed

state.
according
to

the

Integer

stack.

The

overflow
and 15 of

trap enables in the PSW are
and
decimal
overflow
are
the entry mask; respectively,

set

affec:-ed
floating

bits 14
underflow 1s cleared.
T-bit is unaffected.
PC is replaced by the sum
of
destination
operand plus 2, which transfers control to the zalled
procedure at the byte beyond the entry mask.
The
appearance
of the
1-68

INSTRUCTION SET
stack after CALLS is executed is shown in Figure 4-4,

:SP
~
:FP

STACK FRAME

(O TO 3 BYTES SPECIFIED BY SPA)
N

N LONGWORDS OF ARGUMENT LIST

:AP

MR-13427

Figure

4-4

CALLS

Stack

Frame

Notes:

If bits 13:12 of the entry mask are

not

On
a
reserved
unpredictable.

the

Normal use is to push the arglist onto
prior
to
the
CALLS.
On return, the
stack automatically.

The procedure calling standard and the condition handling facility
require
the following register saving conventions.
RO and Rl are
always availlable for function return values and are never saved in
the
entry
mask. All registers R2 through Rll which are modified
in the called procedure must be preserved 1n the entry mask.

fault

occurs.

operand

fault,

0, a

reserved

condition
|

operand

codes
B

are

the stack in reverse
order
arglist is removed from the

- INSTRUCTICN SET

RET

Return

from

Procedure

Format:
opcode

Operation:

{restore SP from FP};
{restore registers}:
{drop stack alignment}:
{if CALLS then remove arglistj};
{restore PSW}:

N<NZ

Condition Codes:
<-

tmpl<3>;

<<<-

tmpl<l>;

tmpl<2>;
tmpl<0>;

Exceptions:
reserved

operand

Opcodes:

RET

Return

from Procedure

Description:
SP 1is
bits

replaced by FP plus 4.
A longword
containing
stack
alignment
in
bits 31:30, a CALLS/CALLG flag in bit 29, the low 12 bits of
the procedure entry mask in bits 27:16, and a saved PSW in
bits
15:0
ls popped from the stack and saved in a temporary.
PC, FP, and AP are
replaced by longwords popped from the stack.
A register restore
mask
1s
formed
from
bits 27:16 of the temporary.
Scanning from bit 0 to
bit 11 of the restore mask, the contents of registers whose number
1is
indicated
by
set
bits
1in the mask are replaced by longwords popped
from the stack.
SP is incremented by 31:30 of the temporary.
PSW
1is
replaced by bits 15:0 of the temporary.
If bit 29 in the temporary 1is
1 (indicating that the procedure was
called
by
CALLS),
a
longword
containing
the
number
of
arguments is popped from the stack.
Four
times the unsigned value of the low byte of this longword is added
to

and

repiaced

the

result.

1-70

INSTRUCTION SET
Notes:

if tmpl<l5:8> NEQ O.
1. A reserved Operandvfault occurs
condition
the
fault,
operand
2. On a reserved
unpredictable.

codes

are

3. The value of tmpl<28> is ignored.

and

The procedure calling standard
assume

that

condition

handling

facility

procedures which return a function value or a status

code do so in RQ or RO and Ri.

5. If FP<l:0> is not zero, the results are unpredictable.

INSTRUCTION

4.7

SET

MISCELLANEOUS INSTRUCTIONS

BIC?SW

- Bit Clear PSW

Format:

opcode

mask.rw

Operation:
PSW

N<NZ

Condition

PSW AND

{NOT mask}:

Codes:
<-

AND

{NOT

AND

{NOT

AND

{NOT

AND

{NOT

mask<3>}:
mask<2>}:
mask<l>}:
mask<Q>}:

Exceptions:
reserved

operand

Opcodes:

. B9

BICPSW

Bit Clear PSW

Description:

PSW 1s ANDed with the ones
replaced by the result.

complement

the mask operand

and

PSW

Notes:

reserved

operand

fault

fault,

occurs

the

PSW

mask

<15:8>

not

affected.

1-72

not

=zero.

INSTRUCTION SET
BISPSW

Bit Set PSW

Format:

opcode mask‘fw
Operation:

PSW <- PSW OR mask;

N<NZ

Condition Codes:
<-

mask<3>;

mask<«<2>:

¥V OR mask<l>;

C OR mask<(>;

Exceptions:
reserved

operand

Opcodes:

BISPSW

Bit Set PSW

Description:

PSW

ORed with

the mask operand and PSW

replaced by

the

result.

Notes:

A reserved operand fault occurs
reserved operand fault, the PSW

mask<l5:8>
1s
not affected.

not

=zero.

INSTRUCTION

SET

BPT

Breakpoint

Fault

Format:

opcode

Operation:
PSL<TP>

{breakpoint

fault};

!push current

PSL on stack

Condition Codes:

N <-

!condition codes

cleared after BPT

fault

Exceptions:
none

- Opcodes:

BPT

Breakpoint

Fault

Description:

This instruction is
used,
debugging facilities.

together

1-73

with

the

T-bit,

implement

INSTRUCTION SET

Halt

HALT

Format:

opcode

Operation:’

If PSL<current _mode> NEQU kernel then

{privileged instruction fault}
)

else

{halt the processor};

Condition Codes:
N <- 0;
Z <- 0;

!If privileged instruction fault
'condition codes are cleared after

C <- 0;

!contains condition codes prior to HALT.

'V <-

N <-

Z
vV

<<=

Z;
V:

'the

fault.

PSL saved on stack

!'If

processor

halt

Exceptions:

privileged instruction
Opcodes:

HALT

Halt

Description:

If the process is running in kernel mode,
the
processor
Otherwise, a privileged instruction fault occurs.
Notes:

This opcode is0 to trap many branches to data.

halted.

INSTRUCTION

SET

INDEX

Compute

Index

Format:

opcode

subscript.rl,
size.rl,

low.rl,

indexin.rl,

high.rl,

indexout.wl

Operation:

indexout
<- {indexin + subscript} *size;

if {subscript LSS low} or {subscript
then {subscript range trapi};

GTR high}

Condition Codes:
N <Z <V <-

1ndexout
indexout

LSS
EQL

0;
O:

Exceptlions:

subscript

range

Opcodes:

INDEX

Compute

Index

Description:

The

indexin operand

added

the

subscript

operand

and

the

sum

can result

from

multiplied
by
the size operand.
The indexout operand is replaced by
the result.
If the subscript operand is less than the low operand
or
greater than the high operand, a subscript range trap is taken.
Notes:

arithmetic

exception

other

than

subscript

range

this
instruction.
Thus no indication is given if
in either the add or multiply steps.
If overflow

overflow occurs
occurs
on
the

add
step the sum is the low order 32 bits of the true result.
If
overflow occurs on the multiply
step,
the
indexout
operand
1is
replaced
by
the low order 32 bits of the true product of the sum
and the subscript operand.
In the normal use of this instruction,
overflow cannot occur without a subscript range trap occurring.
2.

The
of

index instruction is useful in index calculations
for
arrays
the
fixed
length
data
types (integer and floating) and for
index calculations for arrays of bit
fields,
<character
strings,
and
decimal strings. The indexin operand permits cascading INDEX

1-76

SET
INSTRUCTION

instructions for multidimensional arrays. For one-dimensional bit
field arrays it also permits introduction of the constant portion
of an index calculation which is not readily absorbed by address
The following example shows some of the uses of
arithmetic.
INDEX.

Example:
The COBOL

statements:

A-ARRAY.

B PIC X(25).

A PIC X(25) OCCURS 15 TIMES INDEXED BY I.
|

MOVE A(I) TO B.

to:
are equivalent

I(R11l), #~X0l, #~XOF, %#~X19, #~X00, RO

INDEX

#~X19, A-25(R11)[RO], B(R1ll)

MOVC3

The

statements:

FORTRAN

A(11:24),

INTEGER*4
=

AD)

are equivalent

PASCAL

to:

I(R11), #11, #24,
#1, A-44(R11)[RO]

INDEX
MOVL

The

#1,

#0,

statements:
var

are equivalent

INDEX

MOVZBL

integer;

arrayl(ll..24] of

to:

I,#11,#24,#1,#0,R0

#1,A-44[RO]

integer;

INSTRUCTIO
SET
N
s

MOVPSL

Move from PSL

Fdrmat:
opcode

dst.wl

Operation:

dst
Condition

PSL:

Codes:

Exceptions:
none

Opcodes:
DC

MOVPSL

Move

from

PSL

Description:
The

destination

operand

replaced

PSL.

INSTRUCTICON SET

No Operation

NOP

Fmrmat:‘
opcode

Operation:
-

none

| Condition Codes:
N

Exceptlions:
none

;Opcodes:§
01

"NOP

No Operation

Description:
No operation is performed.

INSTRUCTION

SET

POPR

PQp Registers

Format
:
opcode

mask.rw

Operation:

for tmp <- 0
if mask<tmp>
Condition

step 1 until 14 do
EQL 1 then R{tmp] <-

(SP)+:

Codes:

Exceptions:
none

Opcodes:
BA

POPR

Pop

Registers

Description:

The contents of registers whose number
corresponds to set bits in
the
mask
operand
are replaced by longwords popped from
the stack.
Rn is
replaced if mask<n> is set.
The mask is scanned from bit 0 to bit
14.
Bit 15 is ignored.

1-80

INSTRUCTION

PUSHR

Push Registers

Format:

opcode mask.rw
- Operation:

for tmp <- 14 step %l until 0 do
if mask<tmp>

EQL

then -(SP)

R[tmpl;

Condition Codes:
N

Exceptions:
none

Opcodes:

PUSHR

Push Registers

Description:
The contents of registers whose number corresponds to set bits in
the
mask
operand
are
pushed on the stack as longwords.
Rn is pushed if
mask<n> 1s set.
The mask is scanned from bit 14 to bit 0.
Bit 15
is
ignored.
Notes:

The order of pushing is specified
so
that
the
contents
of
higher
numbered
registers
are
stored
at
higher
memory
addresses.
This
results 1in, say, a quadword datum stored in adjacent registers
being
stored by PUSHR in memory in the correct order.

4-81

SET

INSTRUCTION

SET

XFC

wExtended Function Call

Format:

opcode

Operation:
{XFC

fault};

ug
ws

wmg

<-.

OO OO0

Condition Codes:

"Exceptions:
none

Opcodes:

XFC

Extended Function Call

Description:
This

1instruction provides

instruction

for

user

set.

1-82

defined

extensions

the

INSTRUCTION
SET

4.8

QUEUE INSTRUCTIONS

A queue is a circular, doubly linked list whose entries are
specified
by
their
addresses.
Each queue entry links
to two others via a pair
of longwords.
The first longword 1s the forward link:
it specifies
the

location

VAX

supports

two

backward

link:

self-relative.

the

succeeding

specifies
the
distinct

An absolute

entry.

location of

types

second

longword

the preceding entry.
links:

absolute,

link contains the absolute address of

entry that it points to.
A self-relative
from
the present
queue entry.
A queue
link it uses.
B

4.8.1

The

the

and

the

link contains a displacement
is classified
by the type of

Absolute Queues

Absolute queues use absolute addresses as links.
linked by a pair of

Queue

longwords.

entries are
,

The first (lowest
addressed) longword
1is
the
forward
link:
the
address of the succeeding queue entry.
The second (highest addressed)
longword
1s the backward link:
the address of
the
preceding
queue
entry.
A queue 1s specified by a queue header which is identical to a
pair of queue linkage longwords.
The forward link of
the
header
is
the
address of the entry termed the head of the queue.
The backward
link of the header is the address of the entry termed the tail of
the
queue.
The forward link of the tail points to the header.

Two general operations
can

performed

queues:

entries and removal of entries.
Generally entries
removed only at the head or tail of a queue.

insertion

can be

Figures 4-5 through 4-9 illustrate some queue operations.
An
queue 1s specified
by its header at address H as shown in Figure

Figure 4-5
at address
tail), the

empty
4-5,.

If an entry
the head or

inserted or

“HA4

MR- 13428

Empty Queue Header

B 1s inserted into an empty
queue is as shown in Figure

4-83

queue
4-6.

(at

either

INSTRUCTION

SET

‘Figure
If

queue

entry

shown

4-6

address
in

Queue With Address
is

Figure

inserted

the

:B+4

MR 13429

Inserted

head

4-7.

the

k]|

THd

3
N

-2

N
-1 3430

Figure
Finally,
appears

if
as

4-7

éntry

shown

Queue With Address
at

address

Figure

4 8.

4-84

Inserted

inserted at

the

Head
tail,

the

gueue

INSTRUCTION SET

‘

H+4

00
B

31
N

A+4

H
:

00
00

;

)
C

‘Bl

‘C+4

00
MFT 380

Figure 4-8

Queue With Address Inserted at Tail

Follmwxng the above steps in reverse Order glves the effect of removal

at the tail and removal at the head.

If more
than~ l, process can
perform operations
on
a
gueue
simultaneously,
1insertions
and removals should only be done at the
head or tail of the queue.
If only 1 process (or 1 process at a time)
can perform operations on
a queue, insertions and removals can be made
at other than the head or tail of the queue.
In
the
example
above

with
the queue containing entries A,B, and C, the entry at address B
can be removed and the gqueue appears as shown in Figure 4-9.

INSTRUCTION SET

| l

,m.

A+4

00
H

C+4

- 31

Q0
WR Y342

Figure
The

reason

tail
are
operations
present

for

the

4-9

above

Queue With Address
restriction

that

always
valid
because
the queue
elsewhere in the queue depend
on

and

may

become

performing operations
on

invalid

the

queue.

another

Removed

operations

header is
specific
process

the

head

always present;
entries
being

is simultaneously

Two
instructions
are
provided
for
manipulating
absolute
queues:
INSQUE
and
REMQUE.
INSQUE
1inserts
an entry specified by an entry
operand
1into
the
queue
following
the
entry
specified
by
the
predecessor
operand.
REMQUE removes the entry specified by the entry
operand.
Queue entries can be on
arbitrary
byte
boundaries.
Both
INSQUE

and

REMQUE

are

implemented

1-86

non-interruptible

instructions.

INSTRUCTION

4.8.2

Self-relative Queues

links.
Self-relative gqueues use displacements from queue entries as
Queue entries
are linked
by a pair of longwords. The first® longword
(lowest addressed) is the
forward Llink:
the displacement
of
the

succeeding
queue entry from the present entry.
The second longword
(highest addressed) is the backward link:
the displacemént
of
the

preceding queue entry from the present entry. A queue 1s specified by
a queue header, which also consists of two longword links.

Figures 4-10 through 4-13 show &xamples§0f queue operations.

An empty

queue
1is
specified
by 1its header
at address
H. Since the queue is
empty, the self-relative links must be zero as shown in Figure 4-10.

Figure

4-10

"‘w

Empty Queue

If an entry at address B is inserted into an empty

queue

the head or tail),
the gqueue is as shown 1n Figure 4-11.

;

‘

B—H

8~H

H+4

H=8

H-8

B+4

00
RS

Figure 4-11

Queue With Address
B Inserted

1-87

(at

either

SET

INSTRUCTION
SET

I[f

queue

entry

shown

address

Figure

inserted

4-12.

the

head

gueue,

the

0
A=H

B~H
3

the

0
8- A

H - A

H—-8

A-B

B+4

0
MM-T 3435

Figure

Finally,
appears

if
as

4-12

Queue With Address

entry at address C
in Figure 4-13.

Inserted

inserted

the

Head

tail,

shown

A=H

l H

C=H
N

l
|

‘H+4

8—A

H - A

31'

c-8

A-B

8+4

H=-C

B-C

C+a

0
MR IENE

Figure

4-13

Queue With Address

1-88

C Inserted

Tail

the
|

queue

INSTRUCTION SET

l
the above steps in reverse order gives the effect of remova
Following
|
at the tail and removal at the head.

insert at
Four operations can be performed on self-relative queues:
tail.
from
remove
head, insert at tail, remove from head, and
ating
cooper
"allow
to
Furthermore, these operations are interlocked
without
processes 1n a multiprocessor system to access a shared list aligne
d.
rd
quadwo
be
additional synchronization. Queue entries must
to
used
1is
ism
mechan
access
A hardware supported interlocked memory
read the queue header. Bit 0 of the queue header is useded.as Ifa
secondary interlock and is set when the queue is being access
d instruction encounters the secondary 1interlock
queue
an interlocke
e
set, it terminates after setting the condition codes to indicat
bit
ck
interlo
ry
seconda
the
If
queue.
the
to
to gain access
failure
is not set, then the interlocked queue instruction sets it during its
This prevents
operation and clears it at instruction completion.
same queue.
the
on
ng
ons
operati
cti
from
tru
ins
other interlocked queue

1-89

INSTRUCTI
SET
ON

INSQHI

Insert

Entry

into

Queue

Head,

Interlocked

Format:

opcode

entry.ab,

header.aq

Operation:

must have write access to header
!header must be quadword aligned

tmpl

'header

(header){interlocked};

cannot

!acquire

equal

!tmpl<2:1>

1f tmpl<0>
begin

EQLU

then
|

hardware
must

entry

interlock

zero

(header) {interlocked} <- tmpl;!release hardware interlock
{set condition codes and terminate instruction};

end;
else
begin

(header){interlocked}
If

can be completed}
1f

!without
!
!
!also,

begin

following

causing
entry

header +
check for

tmpl
quadword

{release secondary interlock}:

{backup instructiont;
{initiate fault};

end;

then

addresses

end;

else
begin

hardware

interlock
interlock

can be

a memory management

{insert entry into queue};
{release secondary interlock}:

end;

secondary

'release

{all memory accesses
!check

tmpl v 1;!set

alignment

written

exception:

INSTRUCTION SET

Condition Codes:

if {insertion succeeded} then
begin

N <- 03

Z <= (entry) EQL (entry+4);

Vv <- 0;

~tfirst entry in queue
T

C <- 0;
~end;
|

else

begin

N <-

Z <= 0;

VvV

C <- 1;

tsecondary interlock failed
|

~end;

Exceptlions:

reserved operand
Opcodes:

. INSQHI Insert Entry‘intm Queue at Heéd,~;nterlocked

Description:

‘The entry specified by the entry operand 1is inserted

1into

the

Qqueue

following the header. If the entry inserted was the first one in the
queue, the condition code Z-bit 1is set; otherwise it is cleared. n The
1is
The 1insertio
is ° a non-interruptible operation.
insertion
removals
or
ns
insertio
ked
‘interlocked to prevent concurrent interloc
at the head or tail of the same queue by another process even inthea
Before performing any part of
multiprocessor environment.
operation, the processor validates that the entire operation can be
completed. This ensures that if a memory management exception occurs,
the queue is left in a consistent state. If the instruction fails to
acquire the secondary interlock, the instruction sets condition codes
and terminates.

4-91

INSTRUCTION

SET

Notes:

Because

the
kernel mode

insertion is non-interruptible,
can share queues with interrupt

The

INSQHI,
INSQTI,
REMQHI,
and
implemented
such
that
cooperating
multiprocessor
may
access
a
shared
synchronization.

processes

service

INSERT:

list

INSQHI

...

;Wwas

ryes

BCS

INSERT

CALL

WAIT(...)

are
in
a
additional

without
“

used:

BEQL

REMQTI
instructions
software
processes

To set a software interlock realized with a queue,
can._be

running
routines.

queue

the

following

empty?

;try

inserting

;no,

wait

again

1$:

During access validation, any access
which
results
1n a
memory
management exception
lnsertion is not started.
A reserved operand fault occurs if
that
1s
not
quadword
aligned

(header)<2:1>

1f header

is not

equals

zero.

entry.

cannot
be
even though

entry or header i1s
(i.e.
<2:0>
NEQU

A reserved operand

The queue

4-92

not

fault

altered.

completed
the queue
*

an
0)

address
or
if

als
" occurs
o

INSTRUCTION

INSQTI

Insert Entry into Queue at Tail, Interlocked

Format:

"Gpcode

entry.ab, header.aqg

Operation:

tmpl <-

'must have write access to header
theader must be quadword aligned
'header cannot be equal to entry

(header){xnterlocked}

tacquire hardware
'tmpl<2:1> must

1f tmpl<0>
begin

EQLU

interlock

zero

then

(header) {interlocked} <- tmpl~'release hardware interlock
{set condition codes and terminate instruction};

end;
else

begin
(header){lnterlocked}
If

<- tmpl v 1l;!set secondary
'release

hardware

interlock

1nterlock

{all memory accesses can be completed} then
tcheck 1f the following addresses can be written
'without causing a memory management exception:
P

!
talso,

begin

entry

header + (header + &)
|
check for quadword alxgnment

{insert entry

into queue};

{release secmndary interlock};

end;

else

|
b@gln
{release secondary

interlock};
{backup instruction};
{initiate fault};

end;
end;

1-93

SET

INSTRUCTION SET

Condition Codes:

{insertion succeeded}
begin

*
else
|

(entry)

C <end;
”

EQL

then
:

(entry+4);

'first

entry in queue
.

begin
N
Z

<<-

0:
0;

C <end;

!secondary

1interlock

failed

Exceptions:
reserved operand
Opcodes:

INSQTI

Insert

Entry

into Queue

at Tail,

Interlocked

Description:

The entry specified by the entry operand is inserted

into

the

queue

preceding
the header.
If the entry inserted was the first one in the
queue, the condition code Z-bit is set; otherwise it is cleared.
The
insertion
1s
a
non-interruptible
operation.
The
1insertion
1is
interlocked to prevent concurrent interlocked insertions
or
removals
at
the
head
or
tail of the same gueue by another process even in a
multiprocessor
environment.
. Before
performing
any
part
of
the
operation,
the
processor
validates that the entire operation can be
completed. This ensures that 1f a memory management exception occurs,
the
queue 1s left in a consistent state.
If the instruction fails to
‘acquire the secondary interlock, the instruction sets condition
codes
and terminates.

INSTRUCTION

. Notes:
1.

Because the insertion is non-interruptible, processes' running

The

kernel mode can share gqueues with

INSQHI,

INSQTI,

implemented
such
multiprocessor
may
synchronization.

REMQHI,

lnterrupt

and

service

REMQTI

routines.

instructions

in
~

are

that
cooperating software
processes
in
a
access
a
shared
list
without
additional

To set a software 1nterlack realized with a ‘queue,
can be used:

INSERT: INSQTI ...
- BEQL

8CS
CALL

INSERT
WAIT(...)

;was queue empty?
syes

stry 1nsert1ng
~sno, wait

aqaxn

the

following

1$:

During access validation, any access
which
<cannot
be
completed
results
1n
a
memory
management exceptlon even though the queue
insertion 1s not started.

A reserved operand fault occurs if entry, header, or (header+4) is
‘an address that is not quadword aligned (i.e.
<2:0> NEQU 0) or ‘if
(header)<2:1> 1s not zero.
A reserved operand fault
also
occurs
if header equals entry.
The queue is not altered.

SET

INSTRUCTION

SET

INSQUE

Insert Entry

in Queue

Format:

opcode

entry.ab,

pred.ab

Operation:
If

{all memory accesses can be completed}
begin
(entry) <- (pred);
(entry + 4) <- pred:
((pred) + &) <- entry;
(pred) <- entry;
end;

'forward link of entry
!backward link of entry
!backward link of successor
'forward 1ink of precdecessor
|

else

”

then

begin

{backup instruction};
{initiate fault}:

end:;

Condition Codes:

(entry)

LSS

(entry+4);

g<* (entry) EQL (entry+4);
g z: ?éntry) LSSU (entry+4);

tfirst entry in qéeue

Exceptions:
none

Opcodes:
OE

INSQUE

Insert

Entry

in_Queue

Description:
The entry specified by the entry operand is inserted
into
the
Qqueue
following
the
entry
specified
by
the predecessor operand.
If the
entry inserted was the first one in
the
queue,
the
condition
code
Z-bit
1s
set;
otherwlse
it
1s
<cleared.
The
1nsertion
1is
a
non-interruptible
operation.
Before
performing
any
part
of
<+he
operation,
the
processor
validates that the entire operation can be
completed.
This ensures that if a memory
the queue 1s left 1n a consistent state,.

management

exception

occurs,

INSTRUCTION

Notes:

Three types of insertion can be performed by. appropriate choice of
predecessor operand:

Insert at head

INSQUE
b.

Insert

entry,h

1s queue head

tail

INSQUE
entry dh+4
sh is queue head
(Note "@" in this case only)

Insert after arbitrary predecessor
INSQUE

entry,p

1s predecessor

running
Because the insertion is non-interruptible, processes
kernel mode can share queues with interrupt service routines.

The INSQUE and
REMQUE
1instructions
are
1mplemented
such
that
cooperating
software processes in a single processor may access a

shared list without additional synchronization if

the

and removals are only at the head or tall of the queue.

To set a software interlock realized with a queue,
cah

be used:

INSQUE

BEQL

CALL

...

WAIT(...)

the

1insertions

following

;Was queue empty?
:yes

;no,

wait

1$:

During access validation, any access
which
cannot
be
completed
results
1n
a
memory
management exception even though the gqueue
insertion

not

started.

1-97

SET

INSTRUCTION

SET

REMQHI

Remove Entry f rom Queue at Head,

Interlocked

Format:

opcode

header.aqg,

addr.wl

Operation:
'must have write access to header
'header must be quadword aligned

tmpl

'header

(header){interlocked};

1f tmpl<0>
begin

cannot

equal

address

addr

!acquire hardware interlock
'tmpl<2:1> must be zero

EQLU
1 then
|

(header) {interlocked} <- tmpl;!release hardware interlock
{set condition codes and terminate instruction};

end;
else
begin

|
-

(header){interlocked}
If

{all

tmpl
v 1;!set

lalso,
begin

check

{if

for

gquadword

alignment

{remove entry from queue};
{release secondary interlock};

end;
else

begin
{release

secondary interlock}:
{backup instructiont;
{initiate fault};

end;

secondary

interlock

~!release hardware interlock
memory accesses can be completed} then
'!check 1f the following can be done without
!causing a memory management exception:
!write addr operand
tread contents of header + tmpl {if tmpl NEQU 0}
!write into header + tmpl + (header + tmpl)
tmpl

NEQU

INSTRUCTION

Condition Codes:

{removal succeeded}
begin

|
else

then

Z <vV <-

(header) EQL O;
!queue empty after removal
{queue empty before this instructiont;

C <end;

begin
N <- 0;
Z <- 0;
vV <- 1;
C <- 1;
end;

|
|

!did not remove anything
!secondary interlock failed
|

Exceptions:
reserved operand

Opcodes:
5E

REMQHI

Remove

Entry

from Queue

Head,

Interlocked

Description:

I[f the secondary interlock
is clear, the
queue
entry following
the
header
1s
removed from the queue and the address operand is replaced
by the address of the entry removed.
If the queue was empty prior
to
this
1nstruction
or 1f the secondary interlock failed, the condition
code V bit
1s
set;
otherwise
1t
1s
cleared.
If
the
1interlock
succeeded
and
the queue 1s empty at the end of this instruction, the
condition code Z-bit is set; otherwise it is cleared.
The removal
1is
interlocked
to
prevent concurrent interlocked insertions or removals
at the head or tail of the same queue by another
process
even
in
a
multiprocessor
environment.
The removal
1s
a
non-interruptible

operation.

Before performing any part of

the operation,

the processor

validates
that
the
entire operation
can be completed.
This ensures
that 1f a memory management exception occurs, the queue is left
1in
a
consistent
state.
If the instruction fails to acquire the secondary
interlock, the instruction sets condition codes and terminates without
altering the queue.

4-99

SET

INSTRUCTION SET
Notes:

Because the removal is

non-interruptible,

kernel mode can share gqueues with

The
INSQHI,
implemented

following

1S:

running

1in

-INSQTI,
REMQHI,
and
REMQTI
instructions
are
such
that
cooperating
software
processes 1n
a

multiprocessor
may
synchronization.

To release

processes

lnterrupt service routines.

access

software

can be

used:

shared

interlock

list

realized

without

with

...

sremoved last?

BEQL

ryes

3CS
CALL

1$
ACTIVATE(...)

stry removing again
:Activate other waiters

'REMQHI

additional

queue,

the

2S:

To remove entries until

the queue

is empty,

the

following

can

used:

1$:

2S5

REMQHI

...

BVS

process

removed

BCS

queue

empty

sanything

removed?

; NO
entry
7

;try removing again
|

During access validation, any access
which
cannot
be
completed
results
1in
a
memory
management exception even though the queue
removal

not

started.

A reserved operand fault occurs if header or (header +
(header))
is an address that is not quadword aligned (i.e.
<2:0> NEQU 0) or
if (header)<2:1> 1s not
zero.
A
reserved
operand
fault
also
occurs 1if
the
header
address operand equals the address of the
addr operand.
The queue is not altered.

4-100

INSTRUCTION

REMQTI

Interlocked

Remove Entry from Queue at Tail,

Format:

opcode

header. aq, addr.wl

Operation:

'must have write access to header
'header must be quadword aligned
'header

tmpl <- (header){lnterlocked}
if tmpl<0>
begin

EQLU

cannot

equal

address of

'acquire hardware
'tmpl<2:1> must

addr

interlock
zero

then

(header) {interlocked} <- tmpl;!release hardware interlock
{set condition codes and terminate instructionj};

end;
else
begin

(header) {interlocked}

<- tmpl v 1l;!set secondary interlock
'release hardware

{all memory accesses can be completed}
tcheck

1if

the

'write

addr operand

following can be done without

lcausing a memory management

exceptlcn

'read contents of header + (header + %)
!
{if tmpl NEQU 0}
'write into header + (header + 4)

(header + 4 +

talso,

check

(header + 4))

{remove entry from queue};

{release secondary interlock};

end:
else
begin

{release secondary interlock};
{backup instructiont;
{initiate fault};

end;
|

1-101

{if tmpl NEQU 0}

for quadword alignment

begin

end;

interlock

then

SET

INSTRUCTICN

SET

Condition

Codes:

{removal succeeded}

then

begin
N

Z
V

<<-

(header + 4)
{queue empty

EQL 0;'!queue empty after remova
before this instructiont};
‘

end;
else

begin
N
Z

<<-

0;
0;

'!did

not remove anything
!secondary 1interlock failed

<--1;
end;

Exceptions:
reserved operand

Opcodes:
SF

REMQTI

Remove

Entry

from Queue

Tail,

Interlocked

Description:
[f the
header

secondary interlock is clear, the
queue
entry
preceding
the
1s
removed from the queue and the address operand is replaced
by the address
of the entry removed.
If the queue was empty prior
to
this
1instruction
or if the secondary interlock failed, the condition
code V bit
1s
set;
otherwise
it
1is
cleared.
If
the
interlock
succeeded
and
the queue is empty at the end of this instruction, the
condition code Z-bit is set; otherwise it is cleared.
The removal
1is
interlocked
to
prevent concurrent interlocked insertions or removals
at the head or tail of the same queue by another
process
even
in
a
multiprocessor
environment.
The
remcval
1s
a
non-interruptible
operation.
Before performing any part of the operation, the processor
validates
that
the
entire operation can be completed.
This ensures
that 1f a memory management exception occurs, the queue is left
in
a
consistent
state.
I[f the instruction fails to acquire the secondary
interlock, the instruction sets condition codes and terminates without

altering

the queue.

INSTRUCTION

Notes:

1.
2.

3.
|

Because the removal

non-interruptible,

kernel mode can share queues with

processes

1lnterrupt

service

running

routines.

The
INSQHI,
INSQTI,
REMQHI,
and
REMQTI
instructions
are
implemented
such
that
cooperating
software
processes
'In
a
multiprocessor
may
access
a
shared
1list
without
additional
synchronization.
|

To release
following

1$:
|

can

software

REMQTI
BEQL

BCS
CALL

used:

interlock

...
29
1$
ACTIVATE(...)

realized

with

queue,

the

rremoved last?
ryes
;try removing again
;Activate other walters

To remove
used:

1S:

entries
|

REMQTI

until

the queue

...

process

removed

;

;try

BCS

the

removing

again

cannot

empty

which

header,

memory
started.

reserved operand

(header

entry

During access validation, any access
1n
a
1s not

can

; NO

results
removal

following

;anything removed?

BVS

queue

empty,

(header

fault

management

occurs

4)+4)

1is

completed

exception even though

1if

an address

(header

that

the gueue

4),

is not gquadword

aligned (i.e.
<2:0> NEQU 0) or if (header)<2:1> is not
zero.
A
reserved
operand
fault also occurs if the header address operand
equals the address of the addr operand.
The gqueue is not altered.

+-103

SET

INSTRUCTION

SET

REMQUE

Remove

Entry

From

Queue

Format:

opcode

entry.ab,addr.wl

Operafiion:
if

{all memory accesses
begin

((entry+4))
((entry)+4)
addr
|

<<-

entry;

can be

completed} then

(entry); !forward link of predecessor
(entry +4);'!backward link of successor

end;

else

begin

{backup instruction};
{initiate faultt};

end;

Condition Codes:
N

(entry)

LSS

(entry+4);

(entry)

EQL

(entry+4);

entry

(entry)

EQL

'queue

(entry+4);

LSSU

'no

empty

entry

remove

(entry+4);

Exceptions:
none

Opcodes:
oOF

REMQUE

Remove

Entry

from Queue

Description:
The queue entry specified by the entry operand
1is
removed
from
the
queue.
The
address
operand is replaced by the address of the entry
removed.
If there was no entry
1in
the
queue
to
be
removed,
the
condition code YV bit is set; otherwise it is cleared.
1If the queue is
empty

the

end

this

instruction,

the

condition

otherwise
1t
ls
<cleared.
The
removal
operation.
Before performing any part of the
validates
that
the
entire operation can be
that 1f a memory management exception occurs,
consistent state.

1-104

1is

code

Z-bit

set:

non-interruptible

operation, the processor
completed.
This ensures
the gqueue is left
in
a

INSTRUCTION

Notes:

choice

Because the removal is
non-interruptible,
processes
running
kernel mode can share queues with interrupt service routines.

1in

Three types of removal can bé
entry operand:

performed

suitable

Remove at head
REMQUE

<¢h,addr

sh 1s qUeue header

2. Remove at tail

REMQUE
3.

<h+4,addr

;h 1s quehe header

Remove arbitrary entry
REMQUE

‘entry,addr

;

The INSQUE and
REMQUE
1instructions
are
1mplemented
such
that
cooperating
software processes 1n a single processor may access a
shared list without additional synchronization if
the
1insertions
and removals are only at the head or tail of the queue.

To release
following

software

can be

REMQUE
BEQL

CALL

used:

...
1$

interlock

ACTIVATE(...)

realized

with
'

queue,

the

;gqueue empty?
;yes

;Activate other waiters

15:

To remove entries until the gqueue

is empty,

the

following

can

used:

1S:

REMQUE

...

ranything removed?

BVS

EMPTY

Hsle

;

During access validation, any access
which
<annot
bDbe
<completed
results
in
a
memory
management exception even thougn the queue
removal

not

started.

SET

INSTRUCTION

4.9
A

SET

CHARACTER

character

STRING

string

INSTRUCTIONS
specified

unsigned
word
operand
character string in bytes.

operands:

which

specifies

the

length

the

The address of the lowest addressed byte of the character
string.
This is specified by a byte operand of address access type.

Each of
through

the character string instructions uses
general
registers
RO
RS5
to
contain
a
control
block
which maintains
updated
addresses and state during
the
execution
of
the
1instruction.
At
completion, these registers are available to software to
use as string
specification operands for a subsequent instruction
on
a
contiguous
character
string.
During the execution of the instructions, pending
interrupt conditions are tested and if any is found, the control
block
ls
updated,
a
first
part
done
bit
is
set
in
the PSL, and the

instruction

resumes

Figure

interrupted.

transparently.

After

The

4-14.

the

format

interruption,

the

control

block

LENGTH 1

1instruction
is

shown

ADDRESS 1

RO
. R1

LENGTH 2

. R2

ADDRESSz

. R3

: R‘S
MR 13437

Figure

4-14

Character

String Control

The

fields

to
The

Dbe processed in the first and second string
fields ADDRESS 1 and ADDRESS 2 contain the

LENGTH

and

oyte
to
be
respectively.

processed

Memory

faults

access

specified

because

LENGTH

will

the

not

memory

contain

first

occur

reference

1-106

when

the

and

occurs.

Block

number

bytes

operands
address

second

zero

remaining

respectively.
of
the
next

string

length

operands

string

INSTRUCTION

Move Character

‘MOVC

Format:

opcode len.rw,

srcaddr.ab,

opcode srclen.rw,

dstlen.rw,

dstaddr.ab

fill.rb,

srcaddr.ab,

dstaddr.ab

operand

5 operand

Operation:

tmpl <- len;
tmp2 <- srcaddr;
tmp3 <- dstaddr;
if tmp2 GTRU tmp3 then
begin
while tmpl NEQU 0
begin

(tmp3)

Rl <R3 <end

else

begin
tmp4

tmpl
tmp2
tmp3
end;
tmp?2;
tmp3;

tmpl;

tmp2 <- tmp2
tmp3 <- tmp3

while

<<<-

(tmp2);

tmpl
tmpd
tmp3

+
+

+ ZEXT(tmpl);
+ ZEXT(tmpl):

tmpl NEQU 0 do
begin
tmpl <- tmpl
tmp2 <- tmpl
tmp3 <- tmp3

(tmp3)

end;
RO
R2
R4
RS

<<<<-

- 1;
- 1;
- 1;

(tmp2l);

end;

Rl <- tmp2
R3 <- tmp3

1;
1;
1;

+ ZEXT(tmp4);
+ ZEXT(tmp4);
:

0;
0;
0;
0;

1-107

operand

SET

INSTRUCTION

SET

tmpl <- srclen;
tmp2 <= srcaddr;

tmp3 <- dstlen;
tmpé <- dstaddr;
:f tmp2 GTRU tmp4
begin

while

{tmpl NEQU 0}
begin

tmpl <tmp2 <tmp3 <tmp4d <end;
tmp3 NEQU
begin

(tmp4)

tmp3
tmpd
end;
Rl <R3 <end

<<-

AND

{tmp3 NEQU 0}

(tmp2);

tmpl
tmp2
tmp3d
tmpé4
0

+
+

1;
1;
1;
1;

fill;

tmp3
tmp4

1;
1;

tmp2l;

tmp4;

else

begin

tmp5

<- MINU(tmpl,

tmpé

tmp2
tmp4
while

<<-

tmp3;

tmp2
tmp4

+
+

tmp3 GTRU
begin
tmp3 <tmp4 <-

(tmp4)
while

end;
tmp3 NEQU
begin
tmpl <tmp2 <tmp3 <tmp4 <-

(tmpd)

Rl
R3

<<-

end;
tmpl;

R2
R4
RS

<<<-

0;
0;
0;

end;

tmp2
tmpd

operand

then

(tmpd)

while

‘

+
+

tmp3);

ZEXT(tmp3);
ZEXT(tmp6);
tmpl

tmp3d

tmpé4

1;
1;

fill;

tmpl
tmpl
tmp3
tmp4

(tmp2);

ZEXT (tmp5);
ZEXT (tmp6);

INSTRUCTION

SET
*

NON<NZ

NA<NZ

Condition Codes:
IMOVC3

<<-

srclen LSS dstlen;
srclen EQL dstlen;

srclen LSSU dstlen;

!IMOVCS

Exceptlions:
none

Opcodes:

28
2C

MOVC3
MOVC5

Move Character
Move Character

3
£

Operand
Operand

Description:

In3 operand format, the destination string specified
by
the
length
and
destination
address
operands
1s
replaced by the source string
specified by the length and source address
operands.
In
S
operand
format, the destination string specified by the destination length and
destination
address
operands
1s
replaced
by
the
source
string
specified
by
the
source length and source address operands.
If the
destination string is longer
than
the
source
string,
the
highest
addressed
bytes
of the destination are replaced by the fill operand.
If the destination string i1s
shorter
than
the
source
string,
the
highest
addressed
bytes
of
the
source
string are not moved.
The
operation of the instruction 1s such that overlap of
the
source
and
destination strings does not affect the result.

+-109

INSTRUCTION

SET

Notes:

After

execution

MOVC3:

one

RO
= 0
R1

address

byte

beyond

the

source

string

R3 = address of one byte beyond the destination string.

R4 = 0
RS

After execution

MOVCS:

number of unmoved bytes remaining in
RO is non-zero only 1if source string
than destination string

address of one byte beyond the last
ln source string that was moved

address

one

byte

beyond

the

source string.
is longer

byte

destination string

MOVC3 1s the preferred way to copy dne block of memory to another.

MOVCS with
a block of

a 0 source length operand is the
memory with the fill character.

preferred

way

fill

INSTRUCTION

SET
4

4.10

OPERATING SYSTEM SUPPORT INSTRUCTIONS

CHM

Change Mode

Purpose:

Request services of more privileged software

Format:

opcode

code.rw

Operatlon*

tmpl <- {mode selected by mpcode (K=0,
tmp2 <- MINU(tmpl, PSL<CUR_MOD>);

E=1, S=2, U=3)};
'maximize privilege

tillegal

tmp3

<- SEXT

(code);

{PSL<IS> EQLU 1}

then HALT;

PSL<CUR_MOD> SP <- SP;
tmpé4 <- tmp2 SP;

tmp4-12 with mode=tmp2);

'check new stack access

{access control violation} then
{initiate access violation fault};
{translation not wvalid} then
{initiate translation not wvalid fault};

{initiate CHMx exception with new_mode=tmp2
and parameter=tmp3

using 40+tmpl*4
using

tmp4

(hex)

the

Mode
Mode
Mode

to
to
to
to

as SCB mffsat

new SP

and not storing SP again};

Condition Codes:

N <- 0
Z

Exceptlions:
halt

},«A

Mode

Kernel
Executive
Supervisor
User

Change
Change
Change
Change

}.‘-1

CHMK
CHME
CHMS
CHMU

- Cpcodes:

BC
BD
BE
- BF

stack

save old stack pointer
tget new stack pointer

PROBEW (from tmp4-1 through
if

from I

INSTRUCTION

SET

Description:

Change Mode instructions allow processes to change
in
a
controlled
manner.
The
1nstruction only

their
access
mode
increases privilege

pointers;

(i.e.,

decreases

change

mode

the access mode).

also

results

change

stack

the

old

pointer
1is
saved,
the new pointer is loaded.
The PSL, PC, and code
passed by the instruction are pushed onto the stack of the
new
mode.
The saved PC addresses the instruction following the CHMx instruction.
The
<code
1s
sign
extended.
After
execution,
the
new
stack's
appearance 1s as shown in Figure 4-15,

SIGN EXTENDED CODE

'SP

PC OF NEXT INSTRUCTION

OLD PSL

VMR 13438

Figure

4-15

Stack After

Change Mode

Instruction

The destination mode selected by
the
opcode
is
used
to
obtain
a
location
from
the System Control Block.
This location addresses the
CHMx dispatcher for the specified mode.
If the vector<l:0> code
NEQU
0 then the operation is UNDEFINED.
Notes:

usual

for

faults,

any

fault
saves
PC, PSL,
the instruction except
2.

software

customers.

convention,

Access

and
for

Violation

leaves SP as it
any pushes onto

negative

codes

are

Translation

was
the

at the
kernel

reserved

Not

Valid

beginning
stack.
to

CSS

and

INSTRUCTION

Return from Exception or Interrupt

REI

Format:

Opcode

Operation:

tmpl
tmp2
if

<<-

'Pick up saved PC

(SP)+;
(SP)+;

'and PSL

{tmp2<CUR_MOD> LSSU PSL<CUR_MOD>} OR
{tmp2<IS> EQLU 1 AND PSL<IS> EQLU 0} OR
{tmp2<IS> EQLU 1 AND tmp2<CUR_MOD> NEQU 0} OR
{tmp2<IS> EQLU 1 AND tmp2<IPL> EQLU 0)} OR

{tmp2<IPL> GTRU 0 AND tmp2<CUR_MOD> NEQU 0} OR
{tmp2<PRV_MOD> LSSU tmp2<CUR _MOD>} OR

{tmp2<IPL> GTRU PSL<IPL>} OR
{tmp2<PSL_MBZ> NEQU 0}

if PSL<IS> EQLU

then

{reserved operand

ISP <-_SP

!save old stack pointer

else

PSL<CUR_MOD>
SP <-

then

tmp2<TP> <-

PSL<IS> EQLU O
begin

then

PSL<TP>

EQLU

fault};

SP;

!'TP <- TP or

stack TP

PC <- tmpl;
PSL <- tmp2l;

SP <- PSL<CUR_MOD>
SP;
if PSL<CUR_MOD> GEQU ASTLVL
then {request interrupt

{check
{clear

!'switch stack
tcheck for AST dellvery
at IPL 2};

end;

for software interrupts};
instruction look-ahead}

N<NZ

Condition Codes:
<<<<-

saved
saved
saved
saved

PSL<3>;
PSL<2>:
PSL<1>;
PSL<0>;

Exceptions:
reserved operand
Opcodes:
02

REI

Return

from Exception

1-113

Interrupt

SET

INSTRUCTION

SET

Description:
‘A

longword

PC.

1s popped from the current stack and held
in
second longword 1s popped from the current stack

temporary PSL.
stack
pointer
to the new PSL
privilege
AST

a
and

temporary
held in a

Validity of the popped PSL is
checked.
The
current
1s saved and a new stack pointer is selected according
CUR MOD and
IS
fields.
The
level
of
the
highest
1is

checked

pending AST can be delivered.
being
executed
instruction look

at
the
ahead in

against

the

current

Execution

time
of
the
the processor

mode

resumes with

the

see

whether

instruction

exception
or interrupt.
is reinitialized.

Any

Notes:

The exception or interrupt
restoring
any
registers
Staqu

usual

for

conditions

faults,

for

the

any

stack

service routine
1is
responsible
saved
and removing parameters from
"

Access

pops

Violation

restore

1-114

the

Translation

stack pointer

Not

and

for
the

Valid

fault.

INSTRUCTION

LDPCTX

Purpose:

Load

Process

restore

Context

and memory management

context

Format:

opcode

Operation:
1f

PSL<CUR MOD>

NEQU

then {privileged instruction fault};
{invalidate per-process translation buffer entries}:
'PCB is located by physical address in PCBB
RO <- (PCB+16):;
R1 <- (PCB+20):
R2 <- (PCB+24);
R3 <- (PCB+28);
R4 <- (PCB+32):
RS <- (PCB+36);
R6 <- (PCB+40):
R7 <- (PCB+44):
R8 <- (PCB+48):
R9 <- (PCB+52):
R10 <- (PCB+56);
R11 <- (PCB+60);
AP <- (PCB+64):
FP <- (PCB+68);
tmpl <- (PCB+80)
if {tmpl<31:30> NEQU 2} OR {tmpldl 0> NEQU 0}
POBR

{UNDEFINED}
;

tmpl;

i1f (PCB+84)<31:27> NEQU 0 then {UNDEFINED}:
if (PCB+84)<23:22> NEQU Q0 then {UNDEFINED};
POLR <- (PCB+84)<21:0>;
if (PCB+84)<26:24> GEQU 5 then {UNDEFINED!};
ASTLVL <- (PCB+84)<26:24>:
tmpl <- (PCB+88);
tmp2 <- tmpl + 2**23;
if {tmp2<31:30> NEQU 2} OR {tmp2<l1:0> NEQU 0}
{UNDEFINED}
;
P1BR

tmpl;

if (PCB+92)<30:22> NEQU 0
PILR <- (PCB+92)<21:0>;
if (PCB+92)<30:22> NEQU 0
1f

PSL<IS>

then

{UNDEFINED};

then

{UNDEFINED};

EQLU 1 then
begin
ISP <- SP;

{interrupts off};
PSL<IS>

{interrupts
1-115

on};

then

SET

INSTRUCTION

SET

end;

(SP)
-(SP)
-(SP)

<<<-

(PCB)
(PCB+76);
(PCB+72):

get new KSP
lpush PSL
push PC

Condition Codes:
N

2Z:

VvV

Exceptlions:

reserved operand
privileged instruction
Opcodes:

LDPCTX

Load

Process

Context

Description:
The Process Control Block is
specified
by
the
privileged
register
Process Control Block Base.
The general registers are loaded from. the
PCB.
The memory management registers describing the
process
address
space
are
also
loaded
and
the
process entries in the translation

buffer are cleared.
PC

and

PSL

subsequent

are

REI

Execution

moved

from

the

is switched

PCB

the

the kernel

stack,

stack.

suitable

1nstruction.

for

The

use

Note:

software

ASTLVL

with

Lnterrupt.

LDPCTX

does

Those

not

effects

affect

SISR

ASTLVL occur

request

only during

REI.

To guarantee correct
REI 1instruction.

To
be

operation,

LDPCTX must

guarantee correct operation, a LDPCTX on
executed with interrupts disabled.

the

followed

kernel

stack

must

INSTRUCTION

SET
+

SVPCTX

Purpose:

Save Process Context

save

reglster context

Format:

~opcode

Operation:
1f

PSL<CUR MOD>

NEQU

then

iprivileged instruction fault};

'PCB 1s located by physical
(PCB+16) <- RO:
(PCB+20) <- R1l;
(PCB+24) <- R2:
(PCB+28) <- R3;
(PCB+32) <- R&;
(PCB+36) <- R5:
(PCB+40) <- R6;
(PCB+44) <- R7;
(PCB+48) <- R8:
(PCB+52) <- R9;
(PCB+56) <- R10:
(PCB+60) <- R1l1l;
(PCB+64) <- AP:
(PCB+68) <- FP:
(PCB+72) <- (SP)+;
(PCB+76) <- (SP)+;
If

PSL<IS>

EQLU 0 then
begin
PSL<IPL> <- MAXU(1,

(PCB) <- SP;
{interrupts off};
PSL<IS>

<ISP;

{interrupts on};

end:

Condition Codes:
N:

Exceptions:
privileged

address

instruction

Opcodes:

4-117

1n PCBB

'pop
!pop

PC
PSL

PSL<IPL>):
!save

KSP

INSTRUCTION

SET

SVPCTX

Save

Process

Context

Description:

The

Process Control

Process
Control
PCB.
The PC and

popped

and

when

stored
clear,

activated,
and
lnterrupt stack.

Block

i1s

specified

Block Base.
The
PSL currently on

1in

then

IPL

the
IS

general
the top

PCB.
set,

SVPCTX

the

1is maximized with

the

privileged

instruction

1interrupt

registers are saved into
of
the
current
stack

because

stack

the

the
are

executed

pointer

switch

the

Notes:

The

map,

ASTLVL,

they

are

rarely

and PME
changed.

contents

Thus,

of the PCB are
not writing them

Between

not saved because
saves overhead.

the SVPCTX instruction that saves state
for
one
process
and the LDPCTX that loads the state of another, the internal stack
pointers may not be referenced by MFPR or MTPR instructions.
This
implies
that
interrupt
service
routines
invoked at a priority
higher than the lowest one used for
context
switching
must
not
reference the process stack pointers.

1-118

INSTRUCTION

SET
]

MTPR

Move To Processor Register

Format:

~o§c0de src.rl, procreg.rl
Operation:

if PSL<CUR _MOD> NEQ 0 then {reserved

instruction fault};
PRS[procreg] <- src;
Condition Codes:
N
Z
vV
C

<<<<-

src

LSS
EQL

src

0;
0O;

'1f

replaced

not

'1f

replaced

Exceptlions:
reserved
reserved

operand fault
i1instruction fault

Opcode:
DA

MTPR

Move To

Processor

Description:
Loads

the

source

operand

specified

contains

the

regilster-specific

specified

procreg.

processor

side

The

source

1into

procreg operand
number.

the

Execution

processor

longword
may

have

effects.

Notes:

1.
-

A reserved instruction fault occurs 1f
attempted 1n other than kernel mode.

A reserved operand fault occurs on a move to a read only register,
or
1f
the
register
does
not exist.
However,
if a register is
implemented only as a PCB location, a reserved operand fault
does
not

occur.

1instruction
-

execution

1Ls

ON
INSTRUCTISET
MFPR

Move From Processor Reglster

Format:

opcode

Operafiiqh:

procreg.rl,

dst.wl

PSL<CUR MOD> NEQ 0 then {reserved
instruction fault};
dst <- PRS[procregl;
Condition Codes:

N <- dst

LSS 0;

EQL

dst

N <= N;
Z

tif destination

replaced

'if destination

not

replaced

2Z;

Exceptions:
reserved operand fault
reserved instruction fault

Opcode:

MFPR

Move

From Processor Reglster

Description:

The destination operand is replaced by the contents of
the
processor
register
specified
Dby
procreg.
The
procreg operand is a longword
which contains the processor
reglster
number.
Execution
may
have
register-specific

side

effects.

Notes:

1.
2.

A reserved

attempted

instruction

in other

fault occurs

than kernel mode.

1nstruction

executlon

A reserved operand fault occurs
on
a
move
from
a
write
only
register,
or
1if
the
register
does
not
exist. However, 1f a
register is implemented only as a PCB location, a reserved operand
fault

does

not

occur.

4-120

INSTRUCTION

PROBEx

PROBE

ACCESSIBILITY

Purpose:

verify

that

arguments

Format:

opcode

mode.rb,

can

accessed

len.rw,

base.ab

Operation:

probe_mode <- MAXU
condition codes <-

(mode<l1l:0>, PSL<PRV_MOD>)
{accessibility of base} and
{accessibility of {base+ZEXT(len)-1}}
using

probe mode

Condition Codes:
N

Z <Vv <=

if
0;

{both accessible}

then 0

else

Exceptions:
translation
not valid
Opcodes:
0C
0D

PROBER
PROBEW

Probe Read Accessibility
Probe Write Accessibility

Description:
The PROBE 1instruction checks the read or write
accessibility
of
the
first
and
last
byte
specified
by
the
base
address and the zero
extended length.
Note that the bytes
1in
between
are
not
checked.
System software must check all pages between the two end bytes if they
will be accessed.
The protection 1s checked
against
the
larger
(and
therefore
less
privileged)
of
the modes specified in bits <1:0> of the mode operand
and the Previous Mode field of the PSL.
Note that probing with a mode
operand
of
0
1s
equivalent
to
probing
the mode
specified
1in
PSL<previous-mode>.
|
Example:

MOVL

4(AP) ,RO

PROBER

#0,4%4, (RO)

;Copy the address of first arg so
; it can't be changed.
;Verify that the longword pointed

that
to

SET

INSTRUCTION

SET

;

the

;

first

arg

;Note that the
; already have

;Branch

read

the

mode.

arg list 1tself
been probed

either byte gives

must

BEQL

violation

MOVQ

8 (AP),RO

;Copy

PROBEW

#0,R0, (R1)

sVerify that the buffer described by the

;

could be

access

violation,

;

an access

length and address of buffer args

that

they

; 2nd and

can’'t

change.

3rd args could be written by

;
the previous access mode.
;Note that the arg list must already
; have been probed and that the 2nd arg
+
must be known to be less than 512.

BEQL

violation

sBranch

;

either byte gives an access

violation.

Flows:

The

following flows describe the operation of PROBE
on
each
of
the
virtual
addresses
1t
1s
checking.
Note
that
probing an address
returns only the accessibility of the page(s) and
has
no
effect
on
their
fault

residency.
However, probing a process address may cause a page
in the system address space on the per-process page tables.

Look up the virtual address in the translation buffer.
If
found,
use the associated protectlon field to determine the acce531b111ty
fi

and EXIT.

Check for length violation for System or
per-Process
address
as
appropriate.
If length violation then return No Access and EXIT.

If System virtual address, form physical address of PTE, fetch the
use
the protection field to determine the accessibility and

PTE,

EXIT.

For

per-Process

reference

for

the

virtual

address,

must

virtual

memory

PTE.

Look up the virtual address of
the
PTE
1in
the
translation
buffer,
form
the physical address of the PTE 1f found, fetch
the
PTE,
use
the
protection
field
to
determine
the
|

accessibility and EXIT.

Check the

violation.

System
If

virtual

1length

address

wviolation,

then

the PTE

for

length

return No Access

and

EXIT.
@

Page Table EZntry

for

the page contalning

PTE.

1-122

the per-process

INSTRUCTION

If the protection field of Tl indicates no
access
(not
readable
by
kernel),
then
return No Access and EXIT.
access to a page of PTE's conserves storage space for
a
full of no access PTE's.

even
A no
page

e. If the valid bit
in Tl is 0, then take a Translation Not Valid
Fault

and

EXIT.

per-process page

This

tables.

case allows

for the demand paging of
.

Finally, calculate the physical address of the per-process PTE
from
the
PFN
field of Tl, fetch the PTE, use the protection
field to determine the accessibility, and EXIT.

Notes:

If the Valid bit of

the examined Page Table Entry

set,

Page

Table

‘unpredictable
whether the
Modify bit of the examined Page Table
Entry i1s set by a PROBEW.
If the Valid bit 1s clear,
the
Modify
bit

not

changed.

Except for l,§above, the

A length violation gives a status of

On the probe of a process virtual address, if the valid bit of the
system
Page
Table
Entry is 0 then a Translation Not Valid Fault
occurs.
This allows for the demand paging
of
the
process
page

PTE<31>,

mapping

wvalid

tables.

bit

the probed address

the

ignored.

Entry,

"not-accessible.”

On the probe of
a process virtual address, 1f the protection field
of
the system Page Table Entry indicates No Access, then a status

of "not-accessible" is given.
Thus, a single No Access Page Table
Entry
in the system map is equivalent to 128 No Access Page Table

Entries

in the process map.

SET

INSTRUCTION

.11

"These

SET

FLOATING

POINT

INSTRUCTIONS

instructions are

implemented

1n hardware only

the

optional

floating point unit (MicroVAX 78132 FPU) is present in the system.
If
the optional floating point unit is not present the MicroVAX 78032 CPU
will execute a reserved operand fault for any of these instructions.
The MicroVAX
operate
on

Chapter 2).

4.11.1

architecture
F floating,

includes floating
point
1instructions
D floating,
and
G floating &ata types
|
'

that
(see

Representation

Mathematically,
form

floating

point

number may be

defined

having

the

(+ or -) (2%*R)*f,
where K 1s an
non-vanishing

integer
number,

condition

and
f
K and f

1s
are

a
non-negative
fraction.
For
a
uniquely determined by i1mposing the

1/2

LEQ

LSS

The fractional factor, £, of
normalized.
For the number

the value of

the number is
then
said
to
be
zero, f must be assigned the value
indeterminate.

binary
0, and

The MicroVAX
floating
point
data
formats
are
derived
from
this
mathematical
representation
for
floating
point
numbers.
Single
precision, or F_floating, data 1s 32 bits long.
Double precision,
or
D floating,
and
extended range double precisicn, or G _floating, data
is 64 bits long.
Sign magnitude notation 1s used
and
the
following
paragraphs describe 1ts use.

4.11.1.1

Non-zero

Floating

Point

Numbers

The most significant bit of the floating point
0 for positive, and 1 for negative.

data

the

sign

bit:
’

The fractional factor f
1s
assumed
normalized,
so
that
1i1ts
most
significant
bit
must
be
1.
This 1 is the "hidden" bit:
1t is not
stored 1in the data word, but of course the haraware restores .t before
carrying
out
arithmetic operations.
The F_floating, D flcocating, and
G floating data types use 23, 55 and 52
bits,
respectively,
for
f£,
which,
with
56 bits, and

the hidden
53 bits for

bit, imply
arithmetic

effective significance
operations.

bits,

INSTRUCTION

SET
L]

for

the

F_floating

the storage

and

exponents

from

-128

For

reasons

255.

D_floating data

the

exponent

+127

could

given

below,

types,

eight

bits

in excess

128

are

reserved

notation.

Thus

represented,

biased

biased EXP

form,

(true

exponent

-128), is reserved for floating point zero.
Thus, for the
and
D_floating data types, exponents are restricted to the
to +127 i1nclusive, or in excess 128 notation, 1 to 255.

0
of

F_floating
range -127

In the G_floating data type, eleven bits are reserved for the
storage
of
the
exponent
1in excess 1024 notation.
A biased exponent of 0 is
reserved for floating point zero.
Thus, exponents are
restricted
to
- -1023 to +1023 inclusive (in excess notation,
1 to 2047).

4.,11.1.2

Floatinq Point Zero -

Because
of

the

hidden

bit,

the

fractional

factor

not

available

is the format
the result is

generated
zero.

distinguish
between zero and non-zero numbers whose fractional factor
ls exactly 1/2.
Therefore VAX reserves
a sign-exponent field of 0 for
this purpose.
Any positive floating point number with biased exponent
of 0 1s treated as if it
were
an
exact
0
by
the
floating
point
instruction
set.
In particular, a floating point operand, whose bits
are
all

all 0's,
floating

4.11.1.3

is treated as zero, and this
point instructions for which

Reserved Operands -

A reserved

operand
is defined to be any bit pattern with a sign bit of
one
and
a
biased exponent
of zero.
All floating point instructions
generate a fault if
a
reserved
operand 1is
encountered.
Since
a
reserved
operand
has
a biased exponent of 0, it can be (internally)
generated only 1f overflow occurs.

4.11.2

Accuracy

A floating point instruction is defined to be
exact
if
1its
result,
extended
on
the right by an infinite sequence of zeros,
is identical
to that of
an
1infinite
precision
calculation
1involving
the
same
operands.
The
prior
accuracy of the operands is thus ignored.
For
all arithmetic operations, except DIV, a zero operand implies that the
instruction
1is
exact.
The same statement holds for DIV if the zero
operand i1s the dividend.
But
if
it
1is
the divisor,
division
is
undefined and the instruction faults.
Note

that

arithmetic

ln
chopping
the
stored.
Chopping
(D_floating),
or

result

exact

non-zero

infinite
precision result to the
is defined to mean
that
the
24
53
(G_floating)
high order bits
1-125

bits

are

lost

data length to be
(F _floating),
56
of the normalized

INSTRUCTION SET
fractional

discarded.
"rounding"
chopped

1.
2.

factor

result

The
first
bit
bit.
The value of

result

are

stored;

the

rest

lost
1n
chopping
a
rounded
result

bits

are

the
the

follows:

If the rounding bit is one, the

rounded

If the rounding
1dentical.

rounded and chopped

result

the

1s referred to as
1s
related
to

incremented by an LSB
bit
|

i1s

zero,

(least

the

result 'is

significant

bit).

the

chopped

results

are

The VAX architecture implements rounding so
as
to
produce
results
identical to the results produced by the following algorithm.
Add a 1
to the rounding bit, and propagate the carry, 1f 1t occurs.
Note that
a
vrenormalizaticn may be requ: red after rounding takes place; 1f this
happens, .the new rounding bit will be zero,
so
1t
can
happen
only
once.
The
following summarizes the relations among chopped, rounded

and true
1.

(infinite precision)

a stored

result

results:

1s exact

rounded value = chopped value = true value.
2.

stored

result

not

exact,

its magnitude

1s:

always less than that of the true result for chopping.

always less than that
rounding bit 1s zero.

greater than
rounding

bit

that of the
1s

one.

the

true

1-126

result

result
|

for

rounding

the

rounding

11f

the

INSTRUCTION
SET

4.11.3

Instruction Descriptions

Add Compare and Branch

ACB

Format:

opcode limit.rx,

add.rx,

index.mx, displ.bw

Operation:

index <-

1ndex

+ add;

{{add GEQ 0} AND {index LEQ limit}} OR
{{add LSS 0} AND {index GEQ limit}}

then

PC <- PC + SEXT(displ);

Condition Codes:
N <Z <vV
C

<<-

index LSS
1ndex EQL

0:
O0;

0;
C;

Exceptions:

floatihg overflow

floating underflow
reserved operand
Opcodes:

4F
6F
4FFD

ACBF
ACBD
ACBG

Add Compare and Branch F_floating
Add Compare and Branch D_floating
Add Compare and Branch G_floating

Description:

The addend operand is added to the 1ndex operand and the index operand

is
replaced by
the
result.
The index operand 1s compared with the
and the
0)
(or
is positive
If the addend operand
limit mperand
and the
negative
1s
is less than or equal or if the addend
comparxson
branch
sign-extended
the
than or equal
1s greater
comparison
result.
the
by
replaced
is
PC
displacement is added to PC and

4-127

INSTRUCTION

SET

Notes:

ACB efficiently implements the general FOR or
DO
loops
1in
level
languages
since
the sense of the comparison between
and limit i1s dependent on the sign of the addend.

high
index

index

floating

operand

underflow,

if
unaffected.

replaced by
normally..

and

the

and

the

reserved

condition

index

set,

fault

occurs

<clear,

the

and

branch

the instruction takes

operand

codes

comparison

On floating overflow,
fault

fault,

are

unaffected.

the

index

unpredictable.

+-128

and

index

the

operand

determination

operand

floating

proceed

overflow
:

wunaffected

and

INSTRUCTION SET
=

ADD

Add

Format:

opcode add.rx,

sum.mx

opcode addl.rx,

add2.rx,

2 operand

sum.wx

3 operand

Operation:

sum <-

sum +

add;

operand

sum <-

addl

+ addZ;

operand

Condition Codes:
N <Z <vV

C <-

sum LSS
sum EQL
0;
0;

0;
O0;

Exceptions:

floating overflow
floating underflow
reserved operand
Opcodes:

40
41
60
61
10FD
41FD

ADDF2
ADDF3
ADDD2
ADDD3
ADDG2
ADDG3

Add
Add
Add
Add
ADD
ADD

F_floating
2
F_floating 3
D_floating 2
D floating 3
G_floating 2
G _floating 3

Operand
Operand
Operand
Operand
Operand
Operand

Description:

In 2 operand format, the addend operand is added to
the
sum
operand
and
the
sum operand is replaced by the rounded result.
In 3 operand
format, the addend 1 operand is added to the addend 2 operand and
the
sum operand is replaced by the rounded result.
Notes:

On a reserved operand fault,

the sum operand is unaffected and the

On floating underflow, if FU i1s set, a fault occurs

condition codes are unpredictable.

operand
1is
wunaffected.
If
FU
1s
replaced by 0 and no exception occurs.
1-129

<clear,

the

and

the

sum operand

sum
1s

INSTRUCTION

SET

On floating
unaffected,

overflow, the instruction faults; the sum
and the condition codes are unpredictable.

+-130

operand

INSTRUCTION

CLR

Clear

Format:

opcode dst.wx

Operation:

‘

dst <- 0;

Condition

Codes:

<- 1;

Exceptions:
none

Opcodes£
D4
7C

CLRF

CLRG,
CLRD

Clear F floating

Clear
Clear

G floating,
D floating

Description:

The destination mperahd ls replaced by 0.

4-131

SET

INSTRUCTION SET

Compare

CMP

Format:

opcode srcl.rx,

src2.rX

Operation:
srcl

src2:

Condition Codes:

N <- srcl LSS src2;
Z <- srcl EQL src?;
vV
C

<<=

0;
0

Exceptions:

reserved operand
Opcodes:

51
71
51FD

CMPF
CMPD
CMPG

Compare F_floating
Compare D floating
Compare G _floating

Description:

The source 1 operand is compared with the source 2 operand.
action is to affect the condition codes.

The

only

Notes:

On a reserved operand fault, the condition codes are unpredictable.

1-132

INSTRUCTICN

Convert

cvT

Format:

opcode

src.rx,

dst.wy

Operation:

dst

<- conversion of

src;

Condition Codes:
N <Z <-

dst
dst

V <-

LSS
EQL

0;
0;

{integer overflow};

Exceptions:

integer overflow
floating overflow
floating underflow
reserved operand
Opcodes:

CVTWF

CVTBF

Convert Byte to F floating

CVTLF

CVTBD

- 4C

CVTWD

Convert Word

Convert

Long

Convert

Byte

Convert Word

6 E

CVTLD

Convert

1CFD

CVTBG

Convert

4DFD

CVTWG

4EFD

CVTLG

Long

F_floating

F _floating

Dfloating
D floating
to D floating
to

Byte to G floating
Convert Word to G_floating
Convert Long to G floating

4-133

SET

INSTRUCTION
SET

48
49
1A
4B

68
69
A
6B

Convert
Convert
Convert
CVTFL
CVTRFL Convert

F _floating to Byte
F _floating to Word
F floating to Long
Rounded F_floating

Long

Convert
Convert
CVTDL
Convert
CVTRDL Convert

D floating to Byte
D _floating to Word
D _floating to Long
Rounded D _floating

Long

G _floating to Byte
G floating to Word
G _floating to Long
Rounded G _floating

Long

CVTFB

CVTFW

CVTDB

CVTDW

48FD
49FD

CVTGW

4AFD

CVTGL

4BFD

CVTRGL

Convert
Convert
Convert
Convert

56
99FD

CVTFD
CVTFG

Convert
Convert

F _floating
F _floating

to
to

D floating
G_floating

CVTDF

Convert

D _floating

F floating

33FD

CVTGF

Convert

G _floating

F _floating

CVTGB

Description:
The source operand is converted to the data type
of
the
and
operand
the
destination operand is replaced by the
form of the conversion 1s as follows:
CVTBF

exact

CVTBD

exact

CVTBG

exact

CVTWF

exact

CVTWD

exact

CVTWG

exact

CVTLF

rounded

CVTLD

exact

CVTLG
CVTFB

exact

CVTDB
CVTGB

CVTFW

CVTDW
CVTGW
CVTFL

CVTRFL
CVTDL
CVTRDL

CVTGL
CVTRGL

truncated
truncated
truncated
truncated
truncated
truncated
truncated
rounded
truncated
rounded
truncated
rounded

1-134

destination
result.
The

INSTRUCTION SET
CVTFD
CVTFG

CVTDF
CVTGF

exact
exact

rounded
rounded

Notes:

Only CVTDF and CVTGF can result in a floating overflow fault;
the
destination
operand
1is
wunaffected
and
the condition codes are
unpredictable.

Only converts with a floating point source operand can result
reserved
operand
fault.
On
a
reserved
operand
fault,
destination operand is unaffected
and the
condition
codes
unpredictable.

’

can

result

in a
the
are

Only converts with an integer destination'operand

Only CVTGF can result in floating underflow.
If
FU 1s
set,
a
fault
occurs and the destination operand is unaffected.
If FU 1s
clear, the destination operand 1s
replaced
by
0
and
no
fault

integer overflow.
On integer overflow, the destination operand
replaced by the low order bits of the true result.

occurs.

1-135

1in
1is

INSTRUCTION SET

DIV

Divide

Format:
opcode

divr.rx,

Qquo.mx

opcode

divr.rx,

divd.rx,

quo.wx

operand

Operation:
quo

quo

divr;

quo <- divd / divr;
Condition

operand

'3 operand

Codes:

quo

LSS

Z
vV

quo

EQL

Exceptions:

floating overflow
floating underflow
divide by zero
reserved

operand

Opcodes:
16
47

DIVF3

66
67
~
46FD
47FD

DIVD2
DIVD3
DIVG2
DIVG3

DIVF2

Divide F_floating
Divide F floating
Divide D floating
Divide D floating
Divide G floating
Divide G floating

Operand

3
2

Operand
Operand

3
2
3

Operand
Operand
Operand

Description:
In

operand

and

format,
the

the

gquotient

quotient

operand format, the
operand and the quotient

operand

divided

replaced

dividend operand is
operand is replaced

the

divisor

rounded

result.
divided
by
the
divisor
by the rounded result.

Notes:

On a reserved operand fault, the gquotient
and the condition codes are unpredictable.

+-136

operand

1is

unaffected

INSTRUCTION

SET
L

On floatling underEIOW, if FU 1is
quotient

operand

1is

wunaffected.

set,

fault

occurs

FU is clear,

operand is replaced by 0 and no exceptlon occurs.

and

the

the gquotient

On floating overflow, the instruction faults; the quotient operand
is unaffected, and the condition codes are unpredictable.

On divide by zero,
affected as

in 3.

the quotient operand and

above.

condition

codes

are

INSTRUCTION SET

EMOD

Extended Multiply and Integerize

Format:

EMODF

opcode

mulr.rx,

mulrx.rb,

opcode mulr.rx,

mulrx.rw,

EMODG:

“

muld.rx,

int.wl,

fract.wx

muld.rx,

int.wl,

fract.wx

Operation:
int <- integer part
fract <- fractional

of muld * {mulr'mulrx};
part of muld * {mulr'mulrx};

Condition Codes:
N

Z
V

<<<<-

fract LSS 0;
fract EQL O0;
{integer overflow};
0;

Exceptions:
integer overflow
floating underflow
reserved operand

Opcodes:

EMODF

Extended Multiply

and

Integerize

F_floating

EMODD

Extended

and

Integerize

54FD

EMODG

Extended Multiply and

Multiply

floating

Integerize G_floating

Description:
The multiplier extension operand is concatenated with
the
multiplier
operand to gain 8 (EMODF and EMODD) or 11 (EMODG) additional low order
fraction bits.
The
low
order
5
bits
of
the
1lée-bit
multiplier
extension
operand
are
1gnored
by
the
EMODG
instruction.
The
multiplicand operand is multiplied by the extended multiplier operand.
The
multiplication is such that the result 1s eguivalent to the exact
product truncated (before normalization) to a
fraction
field
of
32
bits
1n
F_floating, 64 bits in D floating and G floating.
Regarding
the result as the sum of an i1integer
integer
operand 1s replaced by the

and fraction
integer part

fraction

rounded

operand

replaced

the

result.
1-138

of
of

the
the

fractional

same sign,
result and

part

the
the

the

INSTRUCTION

SET
L]

Notes:

On a reserved operand fault,

- operand are unaffected.

The

the integer operand and the

condition

codes

are

fraction

unpredictable.

On floating underflow, 1f FU
1s
set,
a
fault
occurs
and
the
integer
and
fraction
parts are unaffected.
1If FU is clear, the
integer and fraction parts are replaced
by
0
and
no
exception
occurs.
'

On integer overflow, the integer
order bits of the true result.

Floating
overflow
1s
1indicated
by
1integer
integer overflow is possible in the absence of

The signs of the integer
overflow results.,.

Because
the fraction part
1is
rounded
lnteger
part,
1t
1s
possible
that
operand

and

operand

fraction

$-139

are

replaced

the

low

overflow;
however
floating overflow.
same unless

1integer

after
separation
the
value of the

of
the
fraction

INSTRUCTION

SET

MNEG

Move

Negated

Format:

opcode

src.rx,

dst.wx

Operation:
dst

-src;

Condition Codes:
N

dst

VvV

- C

0;
0;

Z <- dst

LSS

EQL 0:

Exceptlions:
reserved

operand

Opcodeé:
52

MNEGF

Move Negated

F_floating

MNEGD

Move

52FD

MNEGG

Negated

floating

Move Negated G_floating

Description:
The destination operand
operand.

replaced

the

negative

the

source
’

Notes:

On a reserved operand fault, the destination operand
the condition codes are unpredictable.

4-140

unaffected and

INSTRUCTION
L]

MOV

Move

Format:

opcode

Operation: dst

s rc.rx,

dst.wx

|
<-

s rc;

Condition Codes:
-

dst

Z
vV

<<<-

dst
0:
C;

LSS
EQL

0
0O

Exceptions:
reserved

operand

Opcodes:

50"

MOVF

Move

MOVD

SOFD

Move D floating

MOVG

Move

G_floating

floating

Description:

The destination

operand

replaced by

the source operand.

Notes:

the

reserved

condition

operand

codes

fault,

are

the

destination

unpredictable.

+-141

operand

unaffected

and

SET

INSTRUCTION

SET

Multiply

MUL

Format:

opcode

mulr.rx,

prod.mx

opcode mulr.rx,

muld.rx,

prod.wx

operand

Operation:
prod

prod
* mulr;

prod

muld

'3 operand

mulr;

operand

Condition Codes:
N

prod

LSS

prod

EQL

Exceptions:

floating overflow
floating underflow
reserved operand
Opcodes:
44
45
64
65
44FD

MULF2
MULF3
MULD2
MULD3
MULG2

45FD

MULG3

Multiply F flcating
Multiply F floating
Multiply D floating
Multiply Dfloating
Multiply G floating

Multiply G floating

2
3
2
3
2
3

Operand
Operand
COperand
Operand
Operand
Operand

Description:
In 2
operand
format,
the
product
operand
1s
multiplied
by
the
multiplier
operand and the product operand 1s replaced by the rounded
result.
In 3 operand format, the multiplicand operand
1i1s
multiplied
by
the
multiplier operand and the product operand 1s replaced
by the
rounded

result.

Notes:

the

reserved
condition

operand

codes

fault, the product
are unpredictable.

1-142

operand

unaffected

and

INSTRUCTION

SET
*

On floating underflow,
product
operand

if FU

set,

fault

occurs

operand
1s
unaffected.
If
FU
1s
<clear,
is replaced by 0 and no exception occurs.

On floating overflow,
is unaffected,

and the

the

instruction faults;

condition codes

1-143

and

the

the product
’

the product

are unpredictable.

operand

INSTRUCTION

SET

Polynomial

opcode

Evaluation

arg.rx,

degree.rw,

tbladdr.ab

Operation:

tmpl <1f tmpl
tmp2 <-

tmp3

degree;
GTRU 31 then
tbladdr;

RESERVED OPERAND

FAULT;

{(tmp2)+};

ltmp3 accumulates the partial result
|
'tmp3 1s of type x
wnile tmpl GTRU 0 do
begin
!computation loop
tmp4 <- {arg * tmp3};
! tmp4 accumulates new partial result.
'tmp3 has old partial result.
'Perform multiply, and retain the 31 (POLYF) or

t63

(POLYD,

POLYG)

most significant

bits of

the

fraction

!by truncating the unnormalized product. (The most
!significant bit of the 31 or 63 bits
|
'in the product magnitude will be zero
tif the product magnitude is LSS 1/2 and GEQ 1/4.)
'Use the result 1in the following add operation.
tmpd <- tmp4d
+ (tmp2);
|
|
'Align fractions, perform add, and retain the
t31 (POLYF), 63 (POLYD, POLYG) most significant bits of
tthe fraction by truncating the unnormalized result.
tnormalize, and round to type X.
tCheck for over/underflow only after the combined
'multiply/add/normalize/round sequence.
1f OVERFLOW then FLOATING OVERFLOW FAULT
1f UNDERFLOW then
begin
1f FU EQL 1 then FLOATING UNDERFLOW FAULT;
tmp4 <- 0;
tforce result to 0;
end;
tmpl

tmpl

tmp3

tmp4;

tmp2

end;
1f POLYF

tmp2

{size of data

type}l;

'update partial

then

begin
RO <- tmp3;
R1 <- 0;
R2 <- 0;
R3 <- tmp?;
end;
POLYD or POLYG then
begin
+-144

result

tmp3

INSTRUCTION

R1' RO
R2 € R3 & R4 & RS & end:

Condition Codes:
N <Z <-

RO
RO

Vv <=
C <=

LSS
EQL

0;
O

Exceptions:
floating overflow
floating underflow
reserved operand
Opcodes:

POLYF

Polynomial Evaluation F floating

55FD

POLYG

Polynomial Evaluation G_floating

POLYD

Polynomial

Evaluation

floating

Description:

The

table

address

coefficients.

polynomial
specified
addresses.

The

operand

points to

table

of
polynomial
order
term of the
by the table address operand.
The
table
1is
order coefficients
stored
at
1increasing

<coefficient

1is pointed to
lower
with
The data type of

the

highest

the coefficients 1s the same as the
data
1s carried out by
type
of
the
argument
operand.
The
evaluation
Horner's method and the contents of RO (R1'RO for POLYD or POLYG)
are
replaced by the result.
The result computed
1is:

if d = degree

and

arg

result = C{O]*x**0

The unsigned
word
degree
coefficient to participate

;

+ x*(C[1]

+ x*(C{2]

operand
specifies
in the evaluation.

$-145

...

x*C(d]))

the

highest

numbered

SET

INSTRUCTION

SET

Notes:
-

- .

After

execution:

POLYF
RO

= result
=0
= 0
= table address

Rl
R2

POLYD

RO
Rl
R2
R3
R4
RS

floating

POLYG

fault:
= 0, the
restored

instruction faults and all
to their original state.

If PSL<FPD> = 1, the instruction is

suspended

POLYF

saved
~

degree*4

= high order part of result
= low order part of result
= 0
= table address + degree*8 +
=0
= 0

[If PSL<FPD>
effects are

‘b.

the general

.
'partial

tmp3

'one
R1

registers

result

causing

follows:

after

iteration

relevant

and

side

state

prior

the

the overflow/underflow

arg

R2<7:0> = tmpl
!number of iterations remaining
R2<31:8> = implementation specific
R3 = tmp?
!points to table entry causing exception
POLYD
R1'RO

and POLYG
= tmp3

!partial

lone
R2<7:0>

tmpl

result

causing

!number

after

iteration

[f the unsigned word degree operand
reserved
operand,
the
result
1s

either

the

argument

fault

or C[0]

the

the overflow/underflow

lterations

remaining

R2<31:8> = implementation specific
R3 = tmp2
!points to table entry
RS'R4
= arg

operand

prior

|
causing

|
exception

i1s 0 and the argument is not a
ClO].
If cthe degree is 0, and

reserved

operand,

reserved

occurs.

If the unsigned word degree
operand fault occurs.

operand

greater

than

31,

reserved

INSTRUCTION

On a reserved operand fault:

1is either the degree
if PSL<FPD> = Q, the reserved operand
operand, or some
argument
the
or
31),
(greater than
operand
|

coefficient.

if PSL<FPD> = 1, the reserved operand is a coefficient, and R3

The state of the saved condition codes and the other registers
If the reserved operand is changed and the
is unpredictable.

is pointing at the value which caused the exception.

the condition codes and all
contents of
preserved, the fault is able to be continued.

floating

iteration

wunderflow
the

after

the rounding

registers

are
|

any

coperation

computation loop, a fault occurs 1f FU 1is set.

=zero
replaced Dby
If FU is clear, the temporary result (tmp3) 1s
be
may
result
final
In this case the
and the operation continues.
non zero if underflow occurred before the last iteration.

On floating overflow after the rounding operation at any iteration
of the computation loop, the instruction terminates with a fault.

If the argument is zero, the result is C[0]. Additionally, 1if one
of the coefficients in the table (other than C[0]) is a reserved
operand, whether a reserved operand fault occurs is unpredictable.

Example:

To compute P(x)
where C0 = 1.0,

POLYF

= CO + Cl*x + C2*x**2
and C2 = .25
Cl = .5,

X, #2,PTABLE

PTABLE:

.FLOAT

JFLOAT
JFLoaT

0.25
0.5
1.0

+C2
' Cl
:CO

SET

INSTRUCTION

SET

SUB

Subtract

Format:

opcode

sub.rx,

dif.mx

operand

opcode

sub.rx,

min.rx,

dif.wx

operand

Operation:

dif <- dif mVsub:

2 operafid

dif

min

sub;

operand

Condition Codes:

N <- dif LSS 0;

Z <vV <=
C <-

dif
0;
03

EQL

Exceptions:

floating
floating

overflow
underflow

reserved

operand

Opcodes:
42
43
62
63
42FD
43FD

SUBF2
SUBF3
SUBD2
SUBD3
SUBG2
SUBG3

Subtract
Subtract
Subtract
Subtract
Subtract
Subtract

F_floating
F_floating
D floating
D _floating
G _floating
G _floating

2
3
2
3
2
3

Operand
Operand
Operand
Operand
Operand
Operand

Description:
In 2 operand format,
difference
operand

the
and

subtrahend operand
is
subtracted
from
the
the
difference
1is
replaced by the rounded
result." In 3 operand format, the
subtrahend
operand
1is
subtracted
from the minuend operand and the difference ome"and 1s replaced by the
rounded result.

Notes:

©On a reserved operand fault, the difference
and the condition codes are unpredictable.

1-148

operand

unaffected

INSTRUCTION

SET
L4

on flaatihg underflow, 1f FU
difference
operand is

set,

fault

occurs

operand 1s unaffected.
If FU is clear,
replaced by 0 and no exception occurs.

On floating
owverflow,
operand 1s unaffected,

the
and

1instruction
the

condition

4-149

faults;
codes

are

and

the

the difference

the
difference
unpredictable.

INSTRUCTION SET

TST

Test

Format:

opcode

sSrc.rx

Operation:
src

Condition Codes:
N

Z
vV

<<<=
<-

src

src
0;
0;

LSS
EQL

Exceptions:
reserved operand
Opcodes:

S3FD

TSTF

Test

TSTG

Test G_floating

TSTD

F_floating

Test

floating

Description:

The condition codes

are

affected according

the value of

the

source

operand.
Notes:

reserved operand

fault,

the

condition codes

1-150

are unpredictable.
L

INSTRUCTION
1

EMULATED INSTRUCTIONS WITH MICROCODE ASSIST

1.12

The MicroVAX 78032 CPU provides microcode assistance for emulation
system software of the following instructions:

LOCC,

SCANC,

SPANC,

MOVP, CMPP3, CMPP4, ADDP4%, ADDPG,

SUBP4,

SUBPS6,

<creates

argument

The emulation‘process consists of the following steps if

the

Character

MATCHC,

string:

CMPC3,

Decimal string:

MULP, DIVP,

CMPCS.

ASHP,

MOVTC,

MOVTUC, SKPC,

CVTPL, CVTLP,

Cyclic redundancy check: CRC.

Edit:

CVTPS,

CVTSP, CVTTP,

EDITPC.

The pracesser processes the operand specifiers,
list,

and takes an emulated instruction fault.

FPD bits of

the PSL are clear.

and

Evaluate the operand specifiers in order of
1instruction
stream
occurrence.
Save
the address for address and write access type;
read the operand and save 1t

CVTPT.

for read access type.

Build the argument list on the
exception
stack.
The
exception
stack,
Figure
4-16, contains 10 longword parameters (in addition
to
the
PC
and
PSL
to
be
restored
on
returning
from
this

‘exception).

4-151

SET

INSTRUCTION

SET

,
OPCODE

:SP

OLD PC

SPECIFIER #1

SPECIFIER #2

SPECIFIER #3

SPECIFIER #4

SPECIFIER #5

SPECIFIER #6

SPECIFIER #7

SPECIFIER #8

NEW PC

SAVED PSL

MR-13388

Figure

4-16

Emulated

Instruction

Argument

List

The

opcode parameter contains the opcode of the instruction to
be
emulated.
The
old
PC points to the location of the instruction
causing the
exception.
The
specifier
parameters
contain
the
address
of
the
operand
or
the
operand
itself.
For
a
.rx
speclfier, the parameter is the operand value;
for
.wx
and
.ax
specifiers,
the
parameter is the operand address.
A register is
denoted by a reserved system space address
corresponding
to
the
one's
complement
of
the
reglster
number.
The
parameter
corresponding to a specifier that does not exist is unpredictable.
The

new

causing

the

Initiate
an
instruction
in the saved
T

was

set.

points

the

instruction

exception.

following

the

instruction

exception
in
current
mode
through
the
emulated
vector using C8 (hex) as the SCB offset.
The FPD bit
PSL is clear.
The TP bit in the saved PSL is set
if
The

TP,

IV,

DV,

4-152

and

condition

code

bits

the

INSTRUCTION

SET
%

new PSL are cleared.

All other bits

from their previous state.

in the new PSL are

unchanged

If FPD is set, a suspended emulated
1instruction
fault
1s
taken
in
current mode through the vector at SCB offset CC (hex). No parameters
are pushed onto the stack.
The TP bit in the saved PSL is
set
1f
T

was

set.

All

points to the
DV,
bits

other bits

the

saved PSL are unchanged.

instruction causing the exception.

The FPD,

The

FU and condition code bits in the new PSL are cleared.
in the new PSL are unchanged from theilr previous state.

4-153

saved PC

TP,

All

IV,

other
|

CHAPTER
BUS

5.1

TRANSACTIONS

INTRODUCTION

This chapter describes the bus cycles used by the MicroVAX 78032
The

processor

will

perform

bus

cycle

for one of

the

CPU.

following

reasons:

1. Reading or writing
device.

Transferring information from
or
to
an
externally implemented processor register.
shows

the

bus

by reading

to memory or
|

Acknowledging

5-1

interrupt

from or

Figure

information

connections

the device

used by

interrupt

external

A microcycle is the basic timing unit for a bus cycle.

vector.

processor

the MicroVAX

is
defined
as four cycles of CLKO, Tl through T4,
5-2.
A bus cycle may be one or more microcycles.

peripheral

78032

shown

or
|

CPU.

microcycle

in Figure

BUS

TRANSACTIONS

( ——| FATT

ERR

——»| PWRFL

INTERRUPT

— INTTIM

CONTROL

BM<3.0>

. —* [RQ<3.0>

~g§<3fi> >

DMA

Sali

RDY e

‘{~mmm*'DMfi

CONTROL

<+«—

BMG

>
-

DAL<31:00>

ADDRESS
LATCH

AL<L3:

MicroVAX 78032

—
AS

}

'
BA<31:00>
:>>
31:

CENTRAL PROCESSING
UNIT

TRANSCEIVERS <30 3190 >
DATA

<31:00>

‘

DBE

D8t

———

>
Y

FLOATING
=

»|

POINT

EPS

RESET

CS<2:0>

CLKI

UNIT

CLKO
EPS
R
CS<2:0>
CLKO

MR-12666

Figure

‘7””

5-1

MicroVAX

MICROCYCLE

78032

Bus Connections

olo—

MICROCYCLE

-} T

CLKO

MR T
Y

Figure

5-2

MicroVAX

5-2

78032

Microcycle

BUS

TRANSACTIONS

BUS CYCLES

5.2

The MicroVAX
78032
CPU
wuses
read,
write,
DMA,
and
interrupt
acknowledge bus cycles
for
the transfer of information between the
processor, memory, and I/0 devices.
Each
of
these
bus
cycles
1s
:

described in the following paragraphs,

- 5.2.1

CPU Read Cycle

The'processor uses a CPU read cycle (Figure 5-3) to input

1information

from
memory or an 1/0 device.
A CPU read cycle requires a minimum of
2 microcycles and may be extended for slower memory or I[/0 devices.
The

first microcycle of

control
is

1information.

a CPU

read

During the

latched into the processor.

is used

to output

the

address

last microcycle of a CPU read,

and

data

The sequence
of events for a CPU read is as follows:
1.

The physical

(longword)

address

is driven onto DAL<29:02>

by the

processor,

WR is unasserted and CS<2:0> are asserted as requ1red to

3.,

BM<3:0> are asserted as required.

the type of

read cycle being performed.

1indicate

4. AS is asserted to indicate that the address is valid
and
can
be
latqggd
for
demultiplexing.
AS also qualifies CS<2:0>, BM<3:0>,
and

WR.

DS is asserted to indicate that the bus is
free
to
receive
the
requested
information.
TDBE is also asserted at this time and can
be used to cmntrml the DAL bus transceivers.

the

request@d data can be placed on

the bus and be valid during

T3
of
the
next
microcycle, external logic asserts RDY, and the
next microcycle is the last one for this bus cycle.
If RDY is not
asserted
by the end of the current microcycle,
be extended by at least one microcycle.

If a bus error occurs,

ERR

external

takes precedence over RDY.

read, the processor

ignores

the bus cycle will

logic responds by

asserting

ERR.

If ERR is asserted during a data

the data on

DAL<31:00>,

extends

the

bus cycle by one microcycle and initiates a machine check.
1If ERR
is asserted during
an
instruction
read
(CS<2:0>
=
100),
the
processor stops prefetching; when the instruction buffer is empty,
the processor will attempt to fetch the next instruction byte with
a data read cycle,

BUS TRANSACTIONS
»
3

The
the

assertion of either RDY or ERR results
current bus cycle.

The requested data

1is

latched

1into

1in

the

completion

and

processor

deasserted.

AS and DBE are deasserted, ending the bus cycle.

MICROCYCLE

| s

CLKO

>.._._..<

ADORESS

)

DAL~31:00>

CATA

\\\

> J//
OBE
|

el 70 ,/;/f’
|

X
!

ADY
———
RR

| ,//"/ R RGP
— S

e // s //,M” /:’;t

’;

/{// : 7//f%///l/;;;/
/f

j:,//|

o ‘M/:;/ Ry 7 #

s
/:/ I,f,’,,f",//# e

,fl/,f o

%’

j’,”/{j

‘
]

‘

SAMRLING
WINDOW

s f/ s

P
;fi/{

s /e
oy

) e
w77

S
e

L /:/ A

SAMPLING

WINDOW

;

[Ee————

BM<3:0>

Figure 5-3

CPU

5-4

Read

Bus

Cycle

- P et

3US

5.2.2

The

TRANSACTIONS

CPU Write Cycle

processor

uses

CPU

write cycle

(Figure

35-4)

output

information
to memory or an [/0 device.
A CPU write cycle requires a
minimum of 2 microcycles and may be extended for slower memory or
I,0
devices.

The first microcycle of a CPU write is used to output
control
information.
During the last microcycle of
data 1s valid and can be written.

the address
a CPU write,
|

and
the

The sequence of events for a CPU write is as follows:

The physical (longword) address is driven onto DAL<29:02>
processor.

WR is asserted and CS<2:0> are asserted as required.

BM<3:0> are asserted as required indicating which byte(s)

3AS is asserted to indicate that_the address is valid
latc%g@

and

5.
6.

for

demultiplexing.

are

and

AS also qualifies CS<2:0>,

can

BM<3:0>,

DBE is asserted and can be used to control DAL bus transceivers.
The processor drives data onto

~indicate
If

that

the data

can

the

is valid.

written during

DAL

the

bus

and

asserts

microcycle,

external

logic asserts
RDY and the next microcycle is the last one for this
bus cycle.
If RDY is not asserted
by
the
end of
the
current

a bus

the

bus
|

error occurs,

and the processor
over

<cycle

will

external

logic

extended
v

responds

initiates a machine check.

the

least

one

asserting

ERR

the

completion

TERR takes precedence

RDY.

The assertion of either RDY or ERR results

the

WR.

~microcycle,
microcycle.

current

bus

cycle.

DS is deasserted to

indicate that the data is going to be

from

the

DAL

bus

processor.

AS and DBE are deasserted,

ending the bus cycle.

removed

TRANSACTIOCNS

MICROCYCLE

! T4

! T2

MICROCYCLE

I 13

i T4

|
CLKO

t T2

g T4

R
|

!
i

‘

DAL 3100

ADDRESS

X:}(

DATA

|
1

“/,/”

;

AN
!

|
f
!
l

|
|

cé 20 -

8M 30 -

v:X(

t
!

7 4{////////@”/

“"I{/ d

!
.

SaweLinG

s, R
o

%//X,////W///f/fff/%/yy//

e
g

)

SAMPLING

)

i
A

saweuing

|
B

]

BUS

Figure

5-4

CPU Write

5-6

Bus

Cycle

BUS

5.2.3

TRANSACTIONS

Interrupt Acknowledge Cycle

An interrupt acknowledge cycle is used
to
acknowledge
an
interrupt
request
from
an
I/0 device, and to read
a vector.
The structure of
this cycle

the

same

a CPU

read cycle

(Figure 5-3).

The first microcycle of an interrupt
acknowledge
<cycle
1is wused
to
output
the
IPL, in hex, that is being acknowledged.
During the last
microcycle
the
1interrupt
vector
from
the
interrupting
device
is
latched into the processor.
|
The sequence
follows:

of events

for

interrupt

acknowledge

cycle

1is

The prmcessmr places the IPL,

WR is unasserted and CS<2:0> are asserted to lndlcate an Lnterrupt

BM%fi:G% are all asserted.

4.,

AS is asserted to

DS is asserted to
indicate
that
the
bus
1is
free
to
receive
incoming
data.
DBE is also asserted at this time and can be used

acknowledged
on DAL<04:00>.
10 (longword access).

hex,

the

are zero

interrupt

valid.

indicate that the IPL

3AS also qualifies CS<2:0>,

control

the

External
logic
DAL<09:02> and

DAL

bus

the

RDY

bus

and WR.

DAL<04:00>

is not asserted by the

cycle will

DAL<15:10,01> MUST be driven to a
accordance
with the set-up times

diagrams

level on

BM<3:0>,

respands
by
placing
the
interrupt
vector
the
normal
processing/Qbus
processing
flag

the
first
microcycle,
one microcycle.

end

extended by at

wvalid
high
specified in

on
on

least

or
low
level
in
the detailed timing

1in Appendix A.

If an error occurs, external logic asserts ERR and
the
cancels the cycle and ignores the data on the DAL bus.

The interrupt vector
is latched

into

the

processor

deasserted.

transceivers.

DAL<00> and asserting RDY.

béing

and DAL<31:30>

acknowledge cycle.

DAL<29:05>

AS and DBE are deasserted ending the bus cycle.

processor

and

TRANSACT IONS

5.2.4

DMA Cycle

is wused by the processor to relinquish
A DMA cycle (Figure 5-5)
control of the DAL bus and related control signals upon request from a
DMA device or another processor.

a DMA cycle is as follows:
The sequence of events for

DMA device requests use of the bus by asserting DMR.

The

The
the

processor

DMA

request.

current

samples the DMR line during
each
microcycle,unless
bus cycle is a read lock cycle, to see if there is a

The - processor three-states DAL<31:00>,
then asserts DMG to
CS<2:0> ‘and
and
the DAL bus.

AS, DS, DBE,
grant

WR,

BM<3:0>,

the DMA device use of

When the requesting device is finished using the bus, it deasserts
The requesting device
S, DS, DBE, and three-states DAL<31:00>.
deasserts DMR and the MicroVAX 78032 CPU takes control of the bus.

/\ SN

Té

NN\

t T3

: I T2

NS\

t T4

l TM

UAL

g{l

S
.
€S

m——".

[

)

3100

" and

jf/f’

BUS

((

Figure

5-5
5-8

DMA Cycle

BUS TRANSACTIONS

EXTERNAL PROCESSOR CYCLES

5.3

communicate

The processor uses the external processor cycles to

external

with

processor or externally implemented processor registers.,

The external processor protocols are described in Section 5.5.

It is important to note that AS, DBE, DS, and BM<3:0> are not used and

External processor
are not asserted during external processor cycles.
must be drivenDAL<31:00>
that
means
This
32-bits.
cycles are always
cycles.
read
all
for
level
to a valid

5.3.1

External Processor Read Cycle

The processor uses an external processor read cycle
(Figure
5-6)
to
input
information
from an
external processor or external processor
registers. An external processor read cycle takes one microcycle and
can not be extended.

The sequence of events for an external processor read 1s as follows:

CS<1:0> are asserted as
sustained high.

required

and

CS<2>

precharged
»

and

2. WR is not asserted for a read cycle.
3.

EPS is asserted to indicate an external processor bus cycle and to
qualify CS<2:0> and WR.

The external processor places the

requested

1information

DAL.

the

The requested information is latched into the processor and EPS is

The external processor
~ending the bus cycle.

deasserted.

removes

1ts

information

from

the

DAL,

BUS TRANSACTIONS

MICROCYCLE

]

DAL 31:00.-

\_
/

DATA

EPS.

NN \

CS- 10>

WA L1624

External Processor Reéd/Response Cycle

Figure 5-6

BUS

''5.3.2

TRANSACTIONS

External Processor Response Cycle

(Figure 5-6)
The processor uses an external processor response cycle
from an
signal
information and a completion or confirmation
input
to
external
An
register,
external processor or external processor
processor response cycle takes one microcycle and can not be extended.

The sequence of events
follows:-

for

external

CS<1:0> are asserted as

WR is not asserted for a read cycle.

EPS is asserted to

CS<2>

required and

‘1.

sustained high.

processor

response

1is

precharged

and

indicate an external processor bus cycle and to

‘qualify CS<2:0> and WR.

The external processor places the requested
1information on
the
- DAL, and optionally drives CS<2> low with an open drain driver.
|

The requested information is latched into the processor and EPS is

The external processor removes its information from

deasserted.

deasserts CS<2>,

5.3.3

if asserted,

the

ending the bus cycle.

DAL and

External Processor Write Cycle

The processor uses an external processor write cycle (Figure
©5-7)
to
output
information
to
an
external
processor or external processor
register.
An external processor write cycle takes one microcycle
and
can not be extended.

The sequence of events for an external processor write is as follows:
1.

CS<1:0> are asserted as

WR is asserted for a write cycle.

TEPS is asserted
to indicate an external processor bus cycle and to
|
qualify CS<2:0> and WR.

The processor drives the information onto the DAL.

EPS

sustained high.

deasserted

information,

ending

and

the

required

the

bus

and

external

cycle.

CS<2>

precharged

processor

reads

and

the

BUS

TRANSACTIONS

l
l
DAL-31:00-

""<

MICROCYCLE

} T3

|
!

_/
|

mrmrr
r
e
:\\\“3\?\;~“~:~?->‘\“:‘~3§\\%§x
Q«Q\rN
\m’w’:‘\x\"«N‘«j‘";\}\
) \\\
.,RN,
“}\“\ T, S, t\\\f\\?\
R

Figure 5-7

External Processor Write Cycle

BUS

5.4

MEMORY ACCESS PROTOCCL

The

28-bit

address provided

the

processor

DAL<29:02>

TRANSACTIONS

1is

LONGWORD
address
which uniquely identifies one of up to 268,435,456
32-bit memory locations.
To
facilitate
byte accesses
within
the
32-bit memory locations four byte masks, BM<3:0>, are used.
There are

no restrictions
on data alignment, with the exception of
the
aligned
operands
of ADAWI and the 1interlocked gueue instructions.
With these
exceptions, any data item, regardless of size, may be placed
starting
at any memory address.
|
Memory is viewed as four parallel
eight-bit banks,
each
of
which
receives
the
longword address DAL<29:02>.
Each bank reads or writes
one byte of the data bus (DAL<31:00>), when its associated
byte
mask
signal 1s asserted.
This is illustrated in Figure 5-8.

BM<3>
A

o 8 BITS

)

BM<2>
A )

8 BITS

L 54

BM<1>
A i

8 BITS

BM<0>
A

8 BITS

]

DAL<29:0>—e ___

—

DALL23:16 >

DALL15:08>

DAL<07:00>

DAL<31:24>

|
|

MR-11627

Figure

5-8

MicroVAX

78032

Memory Organization

BUS TRANSACTIONS

Any CPU read or CPU write falls into one of the following <categories:
word ’‘access across
longword,
word access within a
bvte access,
access.
longword
unaligne@
aligned longword access,
‘iéngwords,
accesses,
lqngyord
successive
two
as
treated
are
accesses
(Quadword
with no optimization.) Byte accesses, word accesses within a longwerd,
Word accesses
longword accesses require one bus cycle.
and aligned
accesses,
longword
and wunaligned
boundary,
which cross a longword
The exact signal usage is shown in Table 5-1.
require two bus cycles.

requiring more than one bus
It is important to note that accesses
with no computation 1n between.
cycle are performed sequentially,
an wunaligned
However, DMA grants may occur between the bus cycles of
reference.

Table 5-1

At ess Type

(yitle

Byte

Word

within

DAL~31:30+

DAL<Y9: 02~

ALY 02~

tongwous

lwngwatrd

A«ZY

gl Ubs

——

A~sl:U~--11

BM 2 -

AT :0-=00

it oA u=TU

As ) U-sUX

A~1:U-=00

A1 u-=01

9]~

]

Arv g

A~ 10+

Unal igned

11}

A<29:.02-

‘

tongword
o

Avd

2. U8 -

JA<T .U~

Uuadwoird

dicenses

aligned

jounyword

DAL~JdYV:
30
= 11
lungwutd access
each

BM~0
-~

tiu}

tungeaot iy

Nute:

BM~ 1 Ue=10

[A<Y: 0>

A———————

BM« 3

A2yt
JA< V:lle

Al rgiied

Memory Access Control

unaliygned

aie

perfurmed

actesses

tor
and

atid

using
an

A~1:U-=0]
A« 1:0-=1u

A~l:U-=11

QYU

twu

lungword

unaligned

the
Fiist aligned
DAL<3V1:3u> = 10 tor
dicess.

1ungwouitl

it
aur

aCcesses.

Quadwurd

aciess

An
uses

Acl:U-=01

A«<i1:-=10

A~1:0-311

aligned
two

guadwdil
d

unaligned

lungword access
and
the
tirst cycle
the second aligned lunywuird decess and

actL@ss

louongword

o fF
the

uses

two

accesses.

ealh unal igned
secund ycle of

BUS

TRANSACTIONS

EXTERNAL PROCESSOR PROTOCOLS

5.5

The external processor protocols
allow the
MicroVAX
78032
CPU
to
communicate
efficiently
with
one
one
or more external processors.
There
are
two
distinct
external
processor protocols:
one
for
communicating with
the
optional MicroVAX 78132 Floating Point Unit,
the second for communicating with external processor register logic.

5.5.1

FPU Protocol

The optional MicroVAX 78132 Floating Point Unit (FPU) functions
under
the
control of the processor.
When the CPU receives a floating point
instruction
1t
passes
the
opcode and
operands
to
the FPU for
processing.
The
CPU
waits
for the FPU to finish and then requests
status information and any results.
The FPU protocol 1s as follows:

Command Transfer - The processor performs

external

processor

write
cycle to transmit a command to the FPU. During this cycle,
CS<1l:0> = 00 (FPU command), and the opcode of the
floating _point
instruction is placed on DAL<08:00>.

2. Operand Transfer
- The VAX opcode determines the number
and
data
type
of operands to be transferred from the processor to the FPU.
‘The processor performs one or more external processor write cycles

transfer

the

CS<1:0> = 01
be

3.
|

operands.

(data tranfifer)

transferred

During these cycles“Wfi 1s asserted,
data
to

and DAL<31:00> contain the
.

Operand Processing - While
the FPU 1is processing the operands, the
processor
polls
for
operation
completion by executing external
processor

response

enable

cycles.

4.,

Status Transfer
When
the
FPU
has
finished
processing
the
operands,
1t
responds
to
the
next external processor response
enable cycle by
placing status
1information
on
DAL<05:00>
and
driving
CS<2>
low.
The processor responds to CS<2> being driven
low by reading the status information on DAL<05:00>.

Result Transfer
initiate

one

the result
deasserted,
the data

and
the

data

- After
or

reading

the status code,

more external

processor

the processor may

read cycles

transfer

operands(s),
1if
any.
During
these
cycles WR
is
CS<1l:0> = 01 (data transfer), and DAL<31:00> contain
be

transferred.

type of

The VAX opcode determines

the mperand(s) to be

processor.

5-15

transferred

the

from the

number

FPU to

BUS TRANSACTIONS

1 5.5.2

The external processor register protocol
permits
external
logic
to
implement
processor
register
functions
that
are a part of the VAX
Architecture but are not implemented in the MicroVAX 78032 CPU.
Refer
to
Table 1-3 for a list of the processor registers implemented by the
MicroVAX 78032 CPU.
The processor
will
wuse
one
of
the
following
protocols
when
an
MFPR
or
MTPR
1instruction
1is
used to access a
register

not

contained

5.5.2.1

Read From Processor

This sequence
~used

read

(Figure
data

the

5-9)

from

processor.

is performed when an

one

the

through 39, 48 through 55, or 59
register protocol 1is as follows:

The processor

1initiates

write

CS<1:0>

cycle

the

specify

walts

the

one

following

through

61.

MFPR

1instruction

1is

processor

registers:

The

from

read
|

transaction with an

the

(non-FPU command),

DAL<05:00>
contain
instruction.

number.

DAL<31> =

The processor

The processor executes an external

number

processor

external
During

(read

o>rocessor

this

cycle,

specified
|

and

the MFPR

cycle.

processor

response

cycle

read
the
register
data.
If CS<2> 1s driven low by the external
logic,
the
data
on
DAL<31:00>
1is
the
result
of
the
MFPR

instruction.

Otherwise,

the processor

returhs

zero as

the

result.

%fi*

BUS

MICROCYCLE

TRANSACTIONS

MICROCYELE

CLKO

DAL<TT 00>

(

READ DATA

>-—.

!
/

]

;

‘ <O

‘\\W\

i
.

“;K”‘“‘}K\

M ¥ 2

]

‘

CS<2>

A \

- COMMAND
EXTERNAL PROCESSOR
NON-FPU
CYCLE

waw.

NO-OP

EXTEANAL PROCESSOR READ RESPONSE CYCLE

}

Figure

5.5.2.2

This

5-9

Read From Processor Register

Write To Processor Register

sequence

(Figure

5-10)

is performed when an MTPR

used
to
read data from one of the following processor
thrmugh 39, 48 through 55, or 59 through 61.
The
move
register protocml 1s as fallmws:

instruction

registers:
25
to
processor

The processor initiates the transactlon with an external processor
write
cycle
to
specify the register number.
During this cycle,
CS<1:0> = 10 (non-FPU command), DAL<31> = 0 (write register),
and
DAL<05:00>
contain
the
register
number
specified
by the MTPR
instruction.

The processor executes an external processor write cycle to
write
the
register data.
During this cycle, CS<1l:0> = 01 (write data),
and DAL<31:00> contain the data smec1f1ed in the MTPR lnstructlmn.

The next
cycle.

not

guaranteed

(9}

cycle

another

external

processor

BUS TRANSACTIONS

MICROCYCLE

T3 t

{

CLKO

DAL<31.00>

)

<ifig;3v?§gmuma%>

< WRITE DATA

]

[

CRECHQ>

>————

k|
—

EXTERNAL PROCESSOR NON-FPU
COMMAND CYCLE

ek
wes
e

CsS<2>

EXTERNAL PROCESSOR WRITE CYCLE

WY 7668

Figure

5-10

Write To

Processor

Reglster

'CHAPTER 6
PIN DESCRIPTION

6.1

INTRODUCTION

This chapter describes the function performed
MicroVAX 78032 CPU.

each

The pins are divided into 8 groups:

Data/Address bus
Bus control

System control

Interrupt control

DMA cmntrdl
Power supply
Clocks
Test

Figure 6-1 shows the pin assignments of the MicroVAX 78032 CPU.
NOTE

During the pin descriptions references will be made to
the different bus cycles executed by the MicroVAX
For a description of these bus <cycles
78032 CPU.
refer to Chapter 5, Bus Cycles.

the

DESCRIPTION

wil
|
33533538
88
8FE
88
L8
s

"SESECCECCEECCEELCS

rrrrrrtra

[ 6059 5857 56 55 54 53 52 51 50 49 48 47 46 45 44

VDD —{ 61

43 }— vss

DALO6 — 62

DALO5 — 63

42 — pAL22

r"“““““”””“”“j

' DALO4
— 64

DALO3
—] 65

DAL02
—] 66
DALO1 —| 67

DALOO
—{ 68

Vss — 1

41 }— DAL23
40 — DAL24

39 — DAL2S

38 f— DAL26

37 — DAL27

MicroVAX 78032

36 — DAL28

35 |— DAL29

TEST—{ 5

'
‘'

33 }— DAL31
32 — VDD

IRQ1 — 6

|
I
n

31— vss

30 — AS

vDD
— 2

PROCESSOR CHIP

'RO3 — 3
IRQ2 — 4
IRQO—]7

PWRFL — 8

— T T T
———

34 — DAL30

”

29 — DpS

28 }— 5BE

ves —9

\J0 1112 13141516 17 1819 20 21 2223 24 25 26 )— CcLKO

TT T

EEEEEEEEREEEFEREY

”xmwwmmnwmfi‘t[éul"mnn
<
,
n nn wn

]

MR 10297

MicroVAX

78032

6-1

Figure

Assignments

DESCRIPTION

DATA/ADDRESS BUS

6.2

The Data/Address Bus (DAL<31:00>) is

used

for

the

time-multiplexed

32-bit

bus

of address, data, and interrupt information.

transfer

The information carried on DAL<31:00> is determined by the type of bus
During the first part of a CPU read or CPU
cycle being executed.
write cycle DAL<31:00> carries the following address information:

DAL<31:30> - indicates the lenqth of the memory operand.
Operand Length

DAL<30>

DAL<31>

mmw

wm“mmmmmwwmwmmwmmMmmmmmmwmwmmmmm

Longword
Quadword

s the memory
DAL<29:02> - contains the longword addresof
operand.

DAL<29> is used to distinguish a

memory space address from an I/0 space
address.

Address Space

DAL<29>
0

Memory

1/0

DAL<01:00> - are undefined. BM<3:0> determine which byte(s)
of the longword address are to be used. Refer
|
C
to Section 5.4, Memory Access Protocol, for
”

an explanation.

During the first part of an interrupt acknowledge cycle, DAL<(Q04:00>
carry the interrupt priority level (IPL), in hex, of the interrupt
being acknowledged. During the second part of a CPU read or interrupt

acknowledge

vector.

cycle,

DAL<31:00>

receive incoming data or an interrupt

a CPU write bus
During the second part of

are used to transmit outgoing data.

cycle,

DAL<31:00>

In addition to the transfer of information between the CPU and memory,
I1/0 devices, etc., the DAL bus is used to exchange information between
external processors (i.e., FPU) and externally implemented processor
The information present on the DAL bus for these bus
‘reglisters.
cycles is described in Section 5.5.

6.3

3US CONTROL

There are 10 pins associated with bus control:

BBE, BDY, and ERR.
the

A§, DS,

BM<3:0>,

WK,

The function of each of these pins is described 1in

following paragraphs.

PIN DESCRIPTION

6.3.1

Addreés"Strobe (AS)

AS is used to provide
logic.

This signal

notifies

external

executed.

timing

and

control

notifies external

logic

information

logic

that

the

following

WR - direction of transfer

C(CS<2:0> -

BM<3:0> - bytes of DAL bus that contain valid data

type of

bus

logic

1interrupt

should

latch and/or decode

indicate

Data Strobe

priority

level

and
|

(IPL)

bus cycle

cycle

AS is negated to

6.3.2

is being

are valid.

- valid address or

signals

DAL<31:00>

External

external

The assertion of AS marks the beginning of a bus cycle,

part

that a bus cycle

these signals

the end of a bus cycle.

during
as

second

required.

(DS)

DS is used to provide timing information for
the
transfer
of
data.
During
a
CPU read or interrupt acknowledge cycle, the CPU asserts
DS
to

indicate

that

DAL<31:00>

notify external

i1s

free

receive

1incoming

data.

When

the data

from

specify which byte or bytes of

the

the
CPU
has received and latched the incoming data, it deasserts
DS.
During a CPU write cycle, DS is asserted by the CPU to
indicate . that
DAL<31:00>
contain
wvalid outgoing data.
DS is deasserted by the CPU
logic

that

the CPU

about

remove

DAL<31:00>.

6.3.3

Byte Masks (BM<3:0>)

The four byte mask lines, BM<3:0>,

DAL bus contain valid data during the second part of a CPU read or CPU
write cycle.
During a CPU read cycle, the byte masks
1indicate
which
bytes
of
the DAL bus are latched by the CPU.
During a CPU write bus

cycle,

the byte masks

valid data.

indicate which byte(s)

the

BM<3:0> are valid when AS is asserted.
Byte Mask
bit asserted

Data valid on

BM<

DAL<31:24>

BM<2 >
BM<1>
BM<0 >

DAL<23:16>
DAL<15:08>
DAL<07:00>

DAL

bus

contain

PIN DESCRIPTION

NOTE

-a CPU read or external processor
During

read/response

cycle, all bits of the selected byte(s) must be driven
to a valid state, except for an interrupt acknowledge
o
cycle when only bits<15:00> must be driven.

6;3.4

Wwrite (WR)

WR specifies whether data for the current cycle is to be transferred
CPU will drive data onto
ed,
the
WR is assert
to or from the CPU. When
the DAL bus. When WR is not asserted, the CPU 1is ready to receive
data from the DAL bus. WR can be used to control the directlion input

EPS

external logic to enable external DAL
signal in conjunction with WR provide

bus
the

of external DAL bus transceivers.
asserted.

6.3.5

WR is

valid when

Data Buffer Enable (DBE)

BBE can be used by
This
transceivers.

necessary control signals for external bus transceivers.

. 6.3.6

Ready (RDY)

RDY is asserted by external logic to normally end the current CPU
During a CPU read or
read, CPU write, or interrupt acknowledge cycle.

interrupt acknowledge cycle,

the

assertion

TRDY

indicates

that

external logic will place the requested data on the DAL bus as
the
During a CPU write cycle,
specified in Table A-2 and Figure A-2.
on the DAL bus
assertion of RDY indicates that the information placed
by the CPU will be received as specified in Table A-2 and Figure A-3
the current bus cycle and proceeds. At the conclusion of the
finishes
current bus cycle (AS deasserted), external logic deasserts RDY

6.3.7

Error (ERR)

to indicate that an error (i.e., Dbus
- ERR is asserted by external logic
during the current CPU read, CPU
occurred
timeout or parity error)

or interrupt acknowledge
. write,

cycle.

The assertion of

ZRR

has

priority over RDY and results in the current bus cycle being extended.

of the extended bus cycle (ASdeasserted),
At the conclusion
logic

deasserts ERR.

external

For a description of how the MicroVAX 78032 CPU

to Section 7.6.
handles errors refer

6-5

PIN DESCRIPTION

6.3.8

External Processor Strobe

EPS provides timing and control
transactions.
ls

beginning

When

EPS

and:

DAL<31:00>

WR is valid

CS<2:0>

1is

are

ready

(EPS)

information

is asserted,

receive

for

external

processor

an external processor bus cycle
|

contains

valid

information

valid

EPS is deasserted at the end of the external processor cycle.
explanation

6.4

external

transactions

6.4.1

pins associated with system
The
function
of
each
of
paragraphs.

Reset

For

RESET,
HALT,
is described in

and
the

Section

5.3.

A description

the

6.4.2

Halt (HALT)

HALT

asserted

macroinstructions
Execute
current

-control:
these pins
|

(RESET)

RESET is asserted by external

reset

by
by

logic to force the CPU to a known state.

sequence

external

the

CPU.

given

logic

When HALT

Section

halt

the

asserted

the

7.3.

execution

and DAL<0S:00> =

111111,

The CPU will enter the restart process with a
(HALT asserted),

see Section 2.8.

CPU will:

external processor write cycle at the conclusion
macroinstruction,
During
this
cycle,
CCS<1:0>

(non-FPU command)

SYSTEM CONTROL

There are
- CS<2:0>,
following

refer

restart

code

of
=

the
10

HALT
1s an edge sensitive signal that is sampled every microcycle,
is
synchronized internally, and generates a non-maskable interrupt.
HALT
must be asserted an minimum of two
microcycles
to
gquarantee
it
is

sampled.

another

HALT must be deasserted a minimum of

halt

request

will

recognized.

two microcycles before

6.4.3

DESCRIPTION

gontrml Status (CS%2:O>)*

The three control status lines are used in

conjunction

with

and

either AS or EPS
to define the type of operation in progress for the
current bus cycle.
CS<2:0> are valid when AS or EPS is asserted.

During a read,JWrite, or interrupt cycle (AS asserted), WR and CS<2:0>
following meaning:

have the

D¢ b

reserved
reserved
reserved
interrupt acknowledge
read (instruction)
read lock

S« e

‘read (data,
read (data,

modify intent)
no modify intent)

o ol o

Y o

reserved
reserved
reserved
reserved
reserved
write unlock
reserved
write (data)

read,
During an External Processor
asserted),
CS<2>
1is
always high.
meaning:

write,

response

CS<1:0>

ccocrr

VI DS

WO W

cycle

(EPS

WR and CS<1:0> have the following

GO SN

- W

——

reserved
read data
reserved
response enable

write command
write data
write command
reserved

(FPU)
(non-FPU)

PIN DESCRIPTION

6.5

INTERRUPT CONTROL

There are 6 pins associated with interrupt control:
and

TINTTIM.

The

function of each of these pins

follmw1ng paragraphs.

6.5.1

Interrupt

Request

IRQ<3:0>,

DWRFL,

1is descrxbed in the
w

(IRQ<3:0>)

These four lines are used by external logic to send interrupt reguests
to
the
CPU.
If
the
interrupt
request
1s
at a higher interrupt
priority level (IPL) than the current IPL of
the
CPU,
an
interrupt
acknowledge
bus
<cycle will be executed.
Each line has the following
interrupt priority level (IPL):
|
|

IRQ
O

Interrupt Priority
Level (hex)

Line
S

G, WO

TRQ<3>

YDA

IPL16

TRO<OS

IPL1S

TSSOSO

OIS

IPL1S

[RQ<3:0> are level sensitive,

are sampled during every microcycle,

and

to_

fail

are
synchronized
1nternally..
For
a
handling process refer to Section 7.7.

description

condition,
The
that uses vector
fail
interrupt

interrupt

logic

1internally.

microcycles to guarantee
minimum

recognized.

two

notify

the

CPU

power

assertlon; of PWRFL
results in an interrupt at IPL1E
0C (hex) in the system control block (SCB).
A
power
1is not acknowledged with an interrupt acknowledge bus

DPWRFL
is edge sensitive,

synchronized

PWRFL

1s sampled every microcycle,

must

is sampled.

microcycles

before

and

be asserted an minimum of two

PWRFL must
another

halt

deasserted

request

For a description of how PWRFL is used refer

7.7.1.

6.5.3

the

Power Fail (PWRFL)

PWRFL allows external

cycle.

WIS

IPLL7

TRQ<Z2>

TRQ<L>

6.5.2

SIAT,

will

Section

Interval Timer

INTTIM allows external

rollover.
that uses

(INTT.M)
logic

to notify the CPU of

The
assertion
of INTTIM
vector CO (hex) in the SCB.

1interval

timer

results 1n an interrupt at IPLl6
An interval timer interrupt
1is

not
acknowledged
with an interrupt acknowledge bus cycle.
TINTTIM is
edge sensitive, is
sampled
every
microcycle,
and
1is
synchronized
6-3

PIN DESCRIPTION

'NTTIM must be asserted an minimum of two microcycles to

~internally.

guarantee it is sampled.

INTTIM must be deasserted a minimum

request will be recognized.
microcycles before another halt
is used refer to Section 7.7.2.
description of how INTTIM

two

For a

DMA CONTROL

6.6

There are 2 pins associated with
-

function

each

paragraphs.

DMA

pins

control:

described

DMR

and

1in

the

DMG.

The

following

(DMR)

DMA Regquest

6.6.1

these

DMR is asserted by external logic to notify the CPU that it would like

take

of the DAL bus and related control signals.

control

level sensitive,

1is

synchronized.

DMA Grant

6.6.2

sampled

every

microcycle,

and

1is

(DMG)

DMG is asserted by the CPU 1in respwnseto 5”§ _When DMG
the CPU three-states DAL<31:00>, AS, WR, DS, DBE,
CS<2:0>.

When external

AS,

DS,

DBE,

6.7

SUPPLIES

DMR is

internally

and

DMR

logic

and

beginning the next bus cycle.

1is flnlshed using the bus,

is asserted
BM<.
, and

deasserts

the CPU responds by deassertlng‘fiflfi and

There are 9 pins associated with power:

4 for +5

VDC

(vdd), ¢

for

VDC .to

the

Thére~are 4 pins called Vss, which provide a ground reference for

the

ground
(Vss),
and 1 for the back bias generator (Vbb).
The function
of each of these pins is described in the following paragraphs.

6.7.1

Power

(vdd)

There are 4 pins called vdd, which are used to ifiput

MicroVAX 78032 CPU.
+5 VDC is supplied by external c1rcu1try and must
be maintained to within +/-95%.

6.7.2

Ground

(Vss)

6-9

PIN DESCRIPTION

MicroVAX
78032 CPU.
for external logic.

" 6.7.3

These pins

connected

the

chip

the

ground

reference

back

bias

generator.

This

CLOCKS

There a 2 pins assocliated with clock
function
of
each
of
cthese
pins
paragraphs.
~

6.8.1

Back Bias Generatdr (Vbb)

The Vbb pin 1s the output of
pin MUST NOT be connected.

6.8

are

Clock

signals:
CLKI
and
CLKO.
The
1is
described
in
the
following

(CLKI)

CLKI receives the output
timing to the CPU.

a TTL

oscillator,

which

provides

basic

6.8.2 Clock Out (CLKO)
CLKO supplies

6.9

TEST

This pin
MicroVAX

a timing output

half

the

frequency of

CLKI.

(TEST)
is used by
78032 CPU.

chip manufacturing for
internal
For normal use this pin MUST be

testing
of
the
tied to ground.

6.10

DESCRIPTION

PIN DESCRIPTION SUMMARY

the

MicroVAX

78032

- CPU.

Table 6-1

MicroVAX 78032 Pin Summary

Pin No.

Signal Name

I/0

Functzon

DAL<31:00>

1/0

(Tlmewmultlplexed) During the’ flrst part

33“42

45-59

62-68

interrupt acknowledge cycles, provides

address information on DAL<29:02> and
. length information on DAL<31:30>. During
During the second part of a read or
interrupt acknowledge cycle, receives
data driven by memory or I/0 devices.
During the second part of a write cycle,
provides data from the MicroVAX 78032.

A strobe that indicates
WR, BM@?:U%,

CPU read cycles, CPU write cycles,

CS<2:0>,

and DAL<31:00> are valid.

A strobe that indicates that DAL<31:00>:
-- Are free to receive data during a
It
r&ad;cycle or interrupt cycle.
is deasserted to signal that the
data has been received.

-- Contain valid data during a write
write cycle.
It 1s deasserted to
fiata 1s about to
the
that
signal
be removed.

12-15

BM<3:0>

DBE

1/0

Specify which bytes of the DAL contain

Specifies the direction of data transfer

valid data.
Used as an
testing purposes only.

the

1input

for

DAL.

Asserted by the MicroVAX 78032 CPU to
enable external DAL transceivers.

~PIN

DESCRIPTION

Table

6-1

Pin No.

Signal

RDY

MicroVAX

Name

I/0

78032

ERR

RESET

the MicroVAX
-- during a

HALT

CS<2:0>

I/0

bus

error,

parity

e.g.,

the

MicroVAX

tial

state.

execution

Indicate

the

8
9

INTTIM

I
I

memory

known

used

ini-

halt

bus

cycle,i.e.,
access,

read/modify/write,

used as an input during
processor response cycles.

interrupt request

interrupts.

A maskable
fail

A maskable
system

macroinstructions.

instruction

Four maskable

power

acknowledge.

for device

PWRFL

CPU

interrupt
of

type

access,

CS<2> 1s
external

78032

non-maskable

data

IRQ<3:0>

indicate

Asserted by external logic to initialize

interrupt

3,4

logic to

non-existent

error.

lock/unlock,

6,7

to notify

cycle that requested data is present
on the DAL
during a write cycle that the data
on the DAL has been received

the

24-26

logic

78032 CPU that:
read cycle or 1nterrupt

Asserted by external
a8

(Continued)

Asserted by external

Summary

Function

lines

interrupt used to signal a

condition.
interrupt

clock

tick.

used

signal

DMR

[

Asserted by external
a DMA cycle.

Asserted by the MicroVAX 78032 CPU to

EPS

acknowledge

DMA

logic

request

regquest.

Asserted by the MicrovVax 783032 CPU to
coordinate external processor transactions.

Table 6-1

"Pin No.

DESCRIPTION

MicroVAX 78032 Pin Summary (Continued)

Function

[/0

Signal Name

ww«“mmMMMMMWMMMMHMMMWM“MMWMW““mmmmmmmmmmmmmmmmmwwwwwmwmmmmmwmwmmwmmmfimmm

2,32,

+5 volt supply

VDD

44,61

1,31,

VSS

CLKI

A double frequency clock input that

Clock output at

Output of on-chip back bias generator.

43,60

CLKO

VBB

TEST

Ground reference§
provides

CLKI.

Must

chip

Can

not

Reserved.

timing.

half the frequency of

used

as system clock.

connected.

Must be tied to ground.

CHAPTER

INTERFACING

7.1

INTRODUCTION

This chapter provides
the
examples for interfacing to
covered are:
e

Power

Power-Up/Reset

Memory

Bus

Interrupts

7.2

wuser
with
some
general gquidelines
and
the MicroVAX 78032 CPU.
Some of the areas
|

Subsystem

Errors

POWER

The MicroVAX 78032 CPU requires a single +5 V
supply.
There
are
8
pins
associated
with
the
power
supply, four VDD pins and four VSS
pins.
The VDD pins are connected
to
+5
V
and
the
VSS
pins
are
connected to ground.
Decoupling and grounding with the MicroVAX 78032
CPU 1s very
1important.
Decoupling
the
power
supply
1is
done
by
connecting a capacitor between each VDD pin and its associated VSS pin
as shown in Figure 7-1.
The
recommended
value
of
the
decoupling
capacitor
is 10 uf Tantalum +1,-10%.
The ground pins (VSS) should be
tied to the common point ground for the power supply.
The ground pins
should
be tied together at the chip.
NOTE

All
all

VDD pins must
VSS pins must

be connected
be connected

to the +5 V
to ground.

supply

and

INTERFACING

The MicroVAX 78032 CPU

internally generates

which
1s
brought
out on the VBB pin.
this voltage, therefore the VBB pin must

1ts own

\{SSX

|
4

+5V ©&

[

rfiO

44\

VSS)

k -

voltage
filter

VCCX

4?&

+5 vV O

negative

It 1s not necessary
NOT be connected.

° SV
1

MicroVAX
78032
icr

7 1

wfi

+7]

.,
2

VCCI

O +5V

o~
31

‘

vSsi

_
ALL CAPACITORS
10 uF TANTALUM, +1 =10%

Figure

7.3

7-1

MRA.12664

Power Supply Decoupling

RESET/POWER-UP

The MicroVAX 78032 CPU is reset at any time by pulling the
low as

follows:

When power

is first applied,

minimum
of
3
msec
makes
certain
that
beginning operation.

the RESET pin must be held low for

after VDD has reached a stable
all
on
<chip
voltages
are

RESET must be held low for a minimum

asserted after VDD has been at

+4.75 V

When RESET 1s asserted the processor
enters
the
Restart Process.
Refer
of

the

Restart

RESET

3.0

for more

wusec

than

pin
a

+4.75 V.
This
stable
before

1if

RESET

3 msec.

stops executing instructions
and
to Section 2.3 for an explanation

Process.

During reset/power-up the MicroVAX 78032 CPU initializes 1ts
1internal
lcgic and checks to see if the optional MicroVAX 78132 FPU is present.
It checks for the FPU Dby:
7=2

INTERFACING

Performing an external processor command cycle.

Issuing a valid instruction to the FPU via an

This synchronizes

the FPU with the CPU.

external

processor

‘

Transferring data to the FPU using

processor
external
After waiting a period of time, performing an
verifies whether or not the FPU 1is
This
cycle.
response/enable

command cycle.
data cycle.

external

processor

write

present.

7.4

HALTING THE PROCESSOR

The MicroVAX 78032 CPU is a dynamic

disabling
two

1its CLKI

part

and

cannot

halted

input. The MicroVAX 78032 CPU is halted in one of

ways:

1. ’Execution of a HALT instruction 1in kernel mode.
2.

Assertion of the HALT pin.

Either one of these actions causes the execution of
macroinstructions
The initiation
entered.
be
to
process
restart
the
and
suspended
to be
of the restart process is under control of
the processor microcode.
The
microcode
saves
the
processor state and passes control to user
code beginning
at
physical
address
20040000
(hex).
For
a more
detailed explanation of the restart process refer to Section 2.8.

Assertion of the HALT pin results in the execution of
a
non-maskable
interrupt by the CPU.
HALT is edge sensitive and must be asserted for
a minimum of two . microcycles to guarantee 1ts being sensed
by the
CPU

and be deasserted for a minimum of two microcycles before another HALT
will

recognized.

7.5

MEMORY SUBSYSTEM

Figure 7-2 shows an implementation of memory subsystem
with
32KB
of
PRCM
and
128KB
of Static RAM (SRAM).
This susbsytem consists of an

address latch, address decode logic,
logic,

32KB of PROM,

read/write

and 128KB of SRAM.

control logic,

RDY

The longword address is latched in the LS373
transparent
latches
Dby
AS.
The
address is decoded by the LS138 decoder.
The output of the
decoder 1is used to select the PROM or one of the four banks
of
SRAM,
The
byte(s)
to
be
accessed
within
the
longword
are selected by

BM<3:0>.

Note that this system does not do a unique address decode.
-y
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INTERFACING

BUS ERRORS

7.6

nted
Recognition of bus errors (e.g. bus timeout, parity) 1s 1impleme
logic
l
externa
the
occurs,
When a bus error
in external logic.
When ERR 1is
notifies the processor of the error Dy asserting ERR.

asserted one of three things happen:

If the bus cycle is a CPU read or write, as determined by CS<2:0>,
the current bus cycle 1is extended one microcycle and then| the

- processor performs a machine check.

1is

cycle

If the bus

instruction

prefetch

(I-stream

read)

when the prefetch buffer 1is empty, the
prefetching 1is halted.
If
the instruction with a data read.
fetch
to
try
will
r
processo
‘an error occurs again the processor will perform a machine check.

If the bus cycle 1is an IAK cycle; the processor ends the bus cycle

and ignores the

interrupt.

If the assertion of ERR results in a machine check, it is up to the
executing program to determine the type of error from information
pushed on the stack and in external logic. Refer to Section 2.5.4.6.3
for a description of the parameters pushed on the stack for a machine
check.

7.7

INTERRUPTS

The MicroVAX

78032

CPU

recognizes

hardware

interrupts.

interrupts are Powerfail, Interval Timer, and IRQ<3:0>.

7.7.1

These

Ppowerfail (PWRFL)

The powerfail interrupt can be used to implement a power fail routine
rhat 1is located at vector O0OC hex in the SCB or as a high priority
Because
interrupt (IPL1lE) with an internally generated vector (0C).
the vector 1is generated by the CPU, there is no external ilnterrupt
acknowledge cycle associated with this interrupt.

powerfail interrupt is initiated by the assertion of the PWRFL

pin.

SWRFL is edge sensitive and must be asserted for a minimum of two
" microcycles to guarantee its being sensed by the CPU and be deasserted
for a minimum of two microcycles before another powerfail interrupt
will

recognized.

‘

INTERFACING
7.7.2

Interval

Timer

(INTTIM)

The interval timer
interrupt
allows
external
logic
interval
timer
rollover
with
a
vector of CO hex in
interrupt could also be used as an IPL16 interrupt with
generated
vector
(CO0).
Because the vector 1is
there 1s no external interrupt acknowledge cycle
ilnterrupt.

An interval

timer

interrupt

initiated

to
signal
an
the SCB.
This
an
internally

generated by the
associated with

the

assertion

CPU,
this

the

INTTIM
pin.
INTTIM
is
edge
sensitive
and must be asserted for a
minimum of two microcycles to guarantee its being sensed
by the
CPU
and
be
deasserted
for
a
minimum of two microcycles before another
interval timer interrupt will be recognized.
For

compatibility
with Digital's MicroVMS, ULTRIX, and VAXELN software
100 Hz oscillator should should be used for the INTTIM input.

7.7.3

General

The MicroVAX

devices.

Interrupts

78032

CPU

(IRQ<3:05>)

has

four

interrupt

levels

for

use

by peripheral

interrupt
is requested by a device asserting one of the

four interrupt lines (IRQ<3:0>) of the processor.
The processor
will
arbitrate
the
interrupt
and
then
perform an interrupt acknowledge
cycle to acknowledge the highest pending interrupt, if
it
is
higher
than
the
current IPL of the processor.
The interrupting device must
then

When
the

provide

interfacing
user

has

If more
scheme

interrupt

the

processor

and

assert

to the interrupt mechanism of the MicroVAX
consider the following requirements:

than
must

vector

devices

are

implemented

used,

external

some

type

External logic has
acknowledge cycle.

to decode

CS<2:0>,

External

logic

the

External

logic has to supply a vector to the CPU and

This

vector

lnterrupt
If

the

has

decode

offset

routine.

vector

provided

the
CPU
will
lnterrupt.

For a description
Section 5.2.3.

set

its

IPL

into

78032

logic.

A5,

and

level,

the

SCB

hex,

for

the

interrupting device

IPL

IPL17

(hex)

for

RDY.

priority

interrupt

DAL<04:00>.

assert

location

has

before

CPU

EDOY.
of

DAL<Q0>
servicing

the

1,
the

interrupt

acknowledge

bus

cycle,

refer

INTERFACING

In its simplest form the MicroVAX 78032 CPU will accept four different
one for each interrupt level.. To expand this capability the
devices,
such as a daisy chain,
logic,
user must provide prioritization
vectored interrupt controller,

etc.

APPENDIX

DC AND AC CHARACTERISTICS

A.1 DC CHARACTERISTICS

|
AOO

Storage Temperature Range
Active Temperature Range

ang<<nNnN

I
N
wmowum

Absolute Maximum Ratings

Supply Voltage

Input or Output Voltage Applied

Maximum Power Dissipation

to +125 C
to +70 C
to +7.0 V
to +7.0 V
Watts

Electrical Characteristics
+70

Specified Temperature Range
Minimum Air Flow Over Chip
Specified Supply Voltage Range

Test Conditions

Temperature =
o v
vdd
+4,75 V

100 linear ft/min
+4,75 V to +5.25 V

Vss

——

},-J

+70

—

——-

(except

noted)

AND

CHARACTERISTICS

Symbol

Parameter

Vih

High level
voltage

Vil

Voh

Vol

Iils

Iil

input

Low level
voltage

input

High level
voltage

output

High

level

Low

Condition

0.8

2.4

‘

Ioh

Iol = 2.0 mA

Ioh

0.2

Iol

1.0

3.2

Vin =

0.4

-10

0 < Vin

-10

0.4 < Vin < vdd

700

Iout

0.4

output

2.6

- 400

100

output

(EPS only)

Input leakage
current (CS<2>)
Input

Test

(EPS only)

level

voltage

Units

Low level output

voltage

Max

2.0

voltage

Vohe

Vole

Min

leakage

vdd

current

Iol

Output

leakage

current

Idd

Active

Cin

Input

“

supply

current

capacitance

A.2

A-7

through

A-1

Figures

apply

associated timing tables.

‘

CHARACTERISTICS

AC CHARACTERISTICS

The following notes

AND

their

and

for the timing parameters are stated in terms of the CLKI
Formulas
CLKI period = tCIP = P.

period.

All times are in nanoseconds except where noted.

AC characteristics are measured with a purely capacitive load of
100 pf. Times are valid for loads of up to 100 pf on all pins.

AC highs are measured at 2.0 volts and AC lows at 0.8 volts except

AC low at 0.6 volts.
AC‘high for §§§ is measured at 2.2 volts and

S = the number of slipped microcycles during a bus cycle.

the
The sampling window is used to sample

for

signals:

ERR,

RDY,

and

DMR is qualified by

being asserted.

following

asynchronous

RDY _and ERR are qualified by AS

DMR.

being

deasserted.

effect of these signals on the current bus cycle 1s as follows:

The

The bus cycle will conclude at the end of the current
(and NOT ERR) is asserted throughout the
if RDY
microcycle
sampling window while AS is asserted.

If ERR is asserted throughout the sampling window while &S5
asserted,

the

<current

microcycle becomes an extension cycle

and the bus cycle ends after the next microcycle.

If RDY or Efifixéo through

window while

is asserted,

transition

the result

during

the

sampling

is indeterminate.

DMR is sampled at every microcycle boundary.

1f DMR is asserted throughout the sampling window, and

3AF

window,

3AS

has not locked the bus the next
the CPU
and
asserted,
not
of a DMA cycle.
beginning
the
be
will
microcycle

If DMR is asserted

asserted,

and

the

throughout
CPU

has

the

not

sampling

locked

the bus, the first

microcycle after the end of the current bus cycle will be
beginning of

the

a DMA cycle

A DMA cycle will conclude at the end of the current microcycle
if DPMR is deasserted throughout the sampling window.

AND AC

A.2.1

CHARACTERISTICS

CLKI Timing

Table

A-1

CLKI

Timing

SYMBOL

DEFINITION

tCIF

Clock In fall time

tCIH

Clock In high-

tCIL

Clock In !ow

(CIP

Clock Period

tCIR

MIN

MAX
4.5

250

Clock In rise time

je—1C|

4.5

H—wte

CIR

tCIF —

o—
G| —o
MR-11621

Figure

A-1

CLKI

Timing

A.2.2

CHARACTERISTICS

CPU Read Cycle, CPU Write Cycle

Table A-2
SYMBOL

CPU Read Cycle, CPU Write Cycle Timing

DEFINITION

tAAS

”"

MIN

Address set up time to AS

MAX

NOTES

2P . 28

assertion

tASA

AND

Address hold time after AS

2P - 15

assertion

tASHC

AS rising through 2.0V to

P - 23

tASLC

AS falling through 0.8V to

P .20

AS assertion to DBE and

3P - 15

tASDB

tASDI

CLKO rising through 0.8V

DS (read) assertion

AT assertion to read data valid

tASDSO

AS assertion to DS assertion

tASDZ

AS and DBE deassertion to

(write)

‘

3P + 20
|

11P - 30 + 8PS
5P - 15

5P + 20

2P - 20

data 3-state

tASHW

AS deassertion width

tASLW

AS assertion width

12P - 15 - 8PS

tASW‘:B

AS assertion to beginning of

(6P - 45) - 8PS

RDY. ERR. and DMR sampling

window

6P + 10 + 8PS
|

tASWR

WR. BM<3:0-. CS<2:0> hold

P - 20

BM<3.0 set up time before

2P . 25

CLKO rising through 2.0V to

P -7

1BMAS
tCASH

time from AS deassertion
AS assertion

AS rising througn 0.8V

AS assertion to end of RDY.
ERR. and DMR sampling window

tASWE

AND

CHARACTERISTICS

Table

SYMBOL

tCASL

A-2

CPU

Read

Cycle,

Write

Cycle

Timing

DEFINITION

MIN

MAX

CLKO rising through 2.0V to

P .9

AS falling through 2.0V
tCDI

CPU

CLKO rising through 2.0V to

(Continued)

NOTES

P-5

read data valid

tCDO

Write data hold time from

CLKO rising through 2.0V

P - 15

tCF

CLKQO fall time

tCH

CLKQO high

2P - 25) x .5

tCL

CLKO low

(2P - 25) x .5

tCP

CLKQ period

tCR

CLKO rise time

12.5

300

12.5
4

tCW8B

T4 CLKO rising through 2.0V
to beginning of RDY.

3P - 415

ERR,.

~and DMR sampling window
tCWE

T4 CLKO rising through 0.8V
to end of RDY.

ERR. and DMR

sampling window

tDBLW
tDOC

DBE assertion width

9P - 20

Write data set-up time to

3P - 42

8PS

CLKO rnising through 0.8V
tDODS

Write data set-up time to DS

3P - 30

assertion

tDSAS

OS deassertion to AS and

P -

OBE deassertion
tDSD

Read data hoid time after DS

deassertion

tDSDI

DS assertion to read data valid

8P - 35

8PS

DC AND

Table A-2

SYMBOL

1DSDO
tDSDZ

CHARACTERISTICS

CPU Read Cycle, CPU Write Cycle Timing (Continued)

DEFINITION

MIN

Write data hold time from DS

deassertion

MAX

NOTES

3P - 20

DS deassertion to read data

3P - 20

3-state

tDSHW

DS deassertion width

tDSLWI

DS assertion width (read)

8P - 20 - 8PS

tDSLWO

DS assertion width (write)

6P - 20 -~ 8PS

tWEDI

Sampling window end to

5P - 25

read data valid

tWRAS

WR. CS<2:0> set up time before

3P - 35

AS assertion

Notes:

Read data is valid early enough if tASD! or tDSDI or tCDI is satisfied.

Reguirements for the beginning of the sampling window are satisfied if either tASWB or tCWB is
satisfied.

Reguirements for the end of the sampling window are satisfied if either tASWE or tCWE is satisfied.

AND

AC CHARACTERISTICS

tlCASH
SLC

DAL-31.00>

ADDRESS

- oy o

}

e LASHC \

DATA

‘

TASHW

tAAS—=

fe—Ilag
o

\R
-

—

tOSHW

tgsg

~10§DZ —= |

ASDI

tasiw

—

tosoi

A< o iasoz
/

—~

*—4——‘mm

tosLwi

Mtasaa(MIN} —+=
:

toBLwW

—LASDB (MAX)

‘

—

%*mms
wn

Cs-20 -

T
oY

ERR

.
I

r-tASWE

LASWE
o

]

;

e 2] SAMPLING

//,« “

WINDOW

}“cwa‘i
——

SAMPUING

wInDow

/:f,/f‘:;/f"//j///

WVEDI
L

{

tewe

WINDOW
SAM

PLI

SAMPLING
WINDOW

Figure

A-2

CPU

Read Timing

DC AND AC CHARACTERISTICS

NS
\F \_ NNV

CLKO

‘CA&H"‘"“‘%

{ o tASLC
‘

j
ADODRESS

DAL<31:0C>

!.-—--—-—- S

F—»(Aflsw

——
m\

/ i

- IDOC =

WtASA"“J
tASLW

4
'

tospo

;

‘m%k

'ASDSQ (MAX) -

AT
_//F

“

;

‘DLW —

7 —e o LASWR

o1 'ASDB (MAX) ——
A

WHR

%4%';"‘%"%‘:”“%“%‘* N '“‘%“«"f““\\\\f\\\\
o

N\:«,\%

\:\“

Em_..x

\\:

WR“S

o LASDE (MIN}

—at fo TASHC

DATA

*—tASDSO (MIN)

M//f

%-—— (cDo

,
‘

——

————

—

‘/// /K R
i V//

/f/’

”/",w’j‘

Cs-2:02

i“amma*

;
O

IS L

"
AT

LASW

;

L St S
SISy S /
g ,f<71;.'f§f’f’5§’f§"« R ,“/,%/”?M{
j;‘i;’if‘fi~ffx;:‘«/:i{"‘/;/ fl ///‘
‘i

OMAR

)

SAMPLING

WINDOW

A o

v op 5

Sl/ A

,
A

4I
A
A

A A // St o A
o
ftfff’f:ifj»;;f ’fj’“’/’é’é ”%f?” s //At;ffj’fffA
, j;,;»f;»f'f : ’5'/ e4

i——~— lews

ICwWE -——————J

s D0

SAMPLING
WINDOW

Figure A-3

CPU Write Timing

S Y
IERT

DC AND AC CHARACTERISTICS
A.2.3

DMA Cycle

Table

A-3

DMA Cycle

Timing

SYMBOL

DEFINITION

MIN

tASG

AS and DBE deassertion to

4P - 25

DMG assertion

tCGH

CLKO rising through 2.0V to

P.7

tDMRG

DVR tc DMG latency

OMRGU

,; DMR to DMG latercy with

- 10P - 25

28P

ODMG deassertion to externai

DMG assertion to DMR deassertion

DMG rising through 2.0V to

P - 25

OMG falling through 0.8V to

P - 23

CLKO rising through 0.8V

CLKOQ rising through 0.8V

DMG minimum assertion width

{

(N - 2) x 8P)

requested.

tGLW

+ 8PS

6P - 45 =+

such that no more DMA cycles are |

tGLC

- 20

4P - 20

device three-state of DALS.

tGHC

0P - 25 +

(N - 2) x 8P)
tGSZ

ODMG assertion to three-state

of AS, DS. DBE.
and BM<3:0>
tGZ

NOTES

0P - 20 - 16PS

‘0P - 25

bus unlocked

tGDMR

P .7

DMG falling through 2.0V

tGDALZ

MAX

CLKO rising through 2.0V to

DMG rising through 0.8V

tCGL

=10

WR. CS.2:0>

DMG deassertion to external

3P - 20

device three-state of A3, DS,

DBE. WR. CS<20.-. and BM 3.0

Notes:
N
two

the

number of microcycies that 3

DMA

grant iasts.

micrecycles.

At the conclusion of a DMA grant the external
external bus drivers are put in the

nigh

DMA

grant :s issued for a minimum of

logic MUST deassert AS. DS.

impedance state.

and

DBE

before the

DC AND AC CHARACTERISTICS

OMR

] T4

IOMRG IOMGRU

(|
})

'GDMR"

{{

e
(G DAL 2 el

ASG

Wtazw

z¢
—e G52

'_/

IGLW

{(
DAL 3104

‘5‘\

OMG

- ‘GHC

§ —-j

;

{{

(

)]

BM- 3.0

cS-20
WR

—

(

1))

\
R

Figure A-4

DMA Timing

AR %

]

AND

AC CHARACTERISTICS

A.2.4

External

Processor

Processor
Read/Response
Write/Command Cycle

Table

A-4

External

Enable

Processor

Cycle

Cycle,

External

Timing

SYMBOL

DEFINITION

MIN

MAX

{CEP

CLKO falling through 0.8V to

P.5

P+ 19

Write data valid set up time

P. 35

EPS assertion to external

3P - 40

2P - 20

tDOEPH

EPS falling through 2.2V

to EPS deassertion
tEPCSL

processor assertion

tEPCSZ

of CS«2>

EPS deassertion to CS<2> threestated by externai processor

tEPDI

EPS assertion to read data valid

tEPF

EPS fall time from 2.2V to 0.6V

tEPHDO

Write data hoid time from

2P - 25

EPS falling through 0.6V to

P-25

EPS deassertion

tEPLC

CLKO falling through 2.0V

4P - 40
10

tEPLWI

EPS assertion width (read)

4P - 20

4P + 20

tEPLWO

EPS assertion width (write)

5P - 20

5P . 20

WR and CS<1:0> hoid time from

P - 20

tEPWR

EPS deassertion
- tEPZ

EPS deassertion to read data

3P - 20

three-state

tWREP

WR and CS<{1:0> set up time
before EPS assertion

2P - 35

EPS

‘

/ tepr—e

'wngpr....i

CHARACTERISTICS

tcep

DAL<31:00>

AND

—7

e LEP)} it

DATA

|
tepz

e LEP LW (MAX)

\w—-—mtamw: mm;——j/’
g

77777
-— 'EPCSL —

s oA
]

—
MR YISIY

Figure A-5

External Processor Read/Response Timing

CLKO

-1l

tCeP

—

DAL<3IT:00>

)

IEPF —m

€PS

>
S—

"WREP

EPLC

EPHOO

EPLWO (wmmw/
i e LE DWWR

0
/”ff’
2 ,fj/?

m“\\
*%fi%Qfi
S
“‘“‘“7”\\?:\;%;:“‘%}& \::N%K?\\g

CS<2:@>

IDOEPH =

tEPLWO (MAX)

DATA

P 1IR3

Figure A-6

External Processor Write/Command Timing
A-13

AND AC

CHARACTERISTICS

A.2.5

Reset

Timling

Table

A-5

Reset

Timing

SYMBOL

DEFINITION

MIN

tRES

RESET deassertion to first
CLKO pulse if RESET is

3P -

MAX

NOTES

3P + 85

deasserted synchronously

Number of CLKO periods from
RESET deassertion until first
DAL activity

t(RESGH

32 periods

REGET assertion to DMG. EPS
|

deassertion

'{RESH

BESET assertion to AS. DS, DBE.

WR deassertion

tRESW

RESET assertion width after
|

tRESWB

VDD

150

1.0 usec

tRESC

100

3.0 msec

4.75V

RESET assertion width if VDD has

3.0 usec

already been at 4.75V for 3 msec

when RESET I1s asserted

tRESZ
|

RESET assertion to DAL 31:00",
BMC3:0>, CS<2:0> three-state

Notes:

When RESET is asserted. DMG and EPS are brought high and held high by their ouput drivers.
When RESET is asserted. AS. DS. DBE. and WR are put in the high impedance state and brought

Whe RESET is asserted BM<3.0> and CS<2:0> are put in the high impedance state.

nigh

by low current internal

pull-ups.

DC AND AC CHARACTERISTICS

‘

CLKO
)]

1))

'RESW
R

ot
1}

IRESZ el

\f-—

DAL < 31:00>

{

1))

rt%

{{

)

OMG

‘

LRESGH

v
tRESH

A3, B3

UNKNOWN
)

{{

1))
it

/'&

)]

h
A TS

Figure A-7

Reset

}ié

3.0

‘

UNKNOWN

20>
<

(9]

C8
BM

Timing

- APPENDIX B

INSTRUCTION
SET SUMMARY
8.1

INTRODUCTION

This section provides a summary of the VAX-1l instructions
implemented
by
the MicrovAX
78032
CPU, the floating point instructions supported by the
floating point unit, and the emulated instructions that are assisted by the

MicroVAX 78032 CPU's microcode.

The. standard notation for operand specifiers
<name>.<access

type><data

is:

type>

where:

Name is a suggestive name for the operand in the
instruction.
It
1is
the capitalized name of a
for implied operands.

context
of
the
register or block

Access type

speciflier

is
a letter

denoting

the

operand

access

|
T
I
T
VO I

oyte

| NN | A

letter denoting

D floating
F _floating
G floating

same as a,

write only operand

1 AN T B

1is a

"Rn",

the data

longword
quadword

type

if not

field

Data

CxE <O ~AO MMOQD

address operand
branch displacement
modified operand (both
read only operand

word

30w

type.

(used only

multiple

longwords
B-1

read and written)
-

otherwise R[{n+1]'Rn
|

type of

the operand.

implied operands)

(used only

implied operands)

INSTRUCTION SET

SUMMARY

Implied operands, that
instruction,
but
not
braces {}.

'The abbreviations

The

not affected
cleared
set

0
1

abbreviations
rsv

iov
idvz

=
=

fov
fuv
fdvz
dov
ddvz
sub
prv

for condition codes are:

conditionally set/cleared

*
S

is, locations
that
are
accessed
by
the
specified
1in
an
operand, are denoted by

=
=
=
=
=
=
=

for exceptlions

are:

reserved operand fault
1nteger overflow trap
integer divide by zero

trap
floating overifilow fault
(floating underflow fault
floating divide by zero fault
decimal overflow trap
decimal divide by zero trap
subscript range trap
privileged instruction fault

Opcode values are given in hexadecimal.

INSTRUCTION

B.2

The

SET

SUMMARY

INSTRUCTION SUMMARY

following

MicrovVAX

OP
9D

78032

is a summary of

Mnemonic & Arguments

implemented

Description
Add compare and branch byte

NZVC
ot

TelY

Add compare and branch long

ACBW limit.rw. add.rw, index.mw.

Add compare and branch word

1oV

Add aligned word interlocked

T T T
Tttt

displ.bw

ADAWI add.rw. sum.mw

ADDB2 add.rb. sum.mb

Add byte 2-operand

ADDB3 addt.rb. add2.rb. sum.wb

Add byte 3-operand

ADDL2 add.rl. sum.mi

ADDL3 add1i.rl, add2.rl. sum.wi

Add long 2-operand

Add long 3-operand

1oV

ADDW2 add.rw. sum.mw

Add word 2-operand

iov

ADDW3 aad?t.rw. add2.rw. sum ww

Add word 3-operand

ADWC add.rl. sum.mi

Add with carry

T T

AOBLEQ limit.rl. index.mi.

Add one and branch on less or equal

iov

dispi bb

AOBLSS limitrl. index.mi, displ.bb

ASHL cnt.rb. src.rl. dst.wil

ASHQ cnt.rb. src.rg. dst.wq

Arithmetic shift quad

BBC pos.ri. base.vb. dispi.bb.

Branch on bit clear

~
|

Add one and branch on less

iov

Arithmetic shift left

T
|

iov

rsv

‘field.rv}

BBCC pos.rl. base.vb." dispi.bb.

Branch on bit clear and ciear

rsv

field.mvi

BBCCI pos.rl. base.vb. dispi.bb.

Branch on bit clear and clear

[field.mv;

interlocked

BBCS pos.rl. base.vb. displ.bb.
ifield.mv?

EQO
E4

Branch on bit clear and set

BBS pos.rl. base.vb. displ.bb,

field.rv}

Branch on bit set

rsv

BBSC pos.rl. base.vb. displ.bb.

Branch on it set and clear

rsv

BBSS pos.ri. base.vb. displ.bb.

Branch on bit set and set

rsv

BBSS! pos.rl. base.vb. displ.bb.

Branch on bit set and set

rsv

{field.mv}

interlocked

BCC{=BGEQU]} displ.bb

Branch on carry clear

...

BCS{=BLSSU]} displ.bb

Branch on carry set

BEQL{=BEQLU]} displ.bb

Branch on equal

BGEQ displ.bb

Branch on greater or equal

BGTR dispi.bb

‘Branch on greater

BGTRU displ.bb

(field.mv)

field.mv])

the

Exceptions

ACBL limit.rl, add.rl. index.mli,

displ.bw
3D

instructions

ACBB limit.rb. add.rb. index.mb.
displ.bw

the VAX-1ll

CPU.

R
-

Branch on greater unsigned

BICB2 mask.rb. dst.mb

Bit clear byte 2-operand

BICB3 mask.rb. src.rb. dst.wb

Bit clear byte 3-operand

BICL2 mask.ri, dst.mi

Bit clear long 2-operand

T 0

BICL3 mask.rl, src.ri. dst.wil

Bit clear long 3-operand

Mnemonic & Arguments

Description

BICPSW mask.rw

Bit ctear processor status word

Bit ctear word 2-operand

BICW3 mask.rw, src.rw, dst.ww

bit clear word 3-operand

BISB2 mask.rb, dst.mb

Bit set byte 2-operand

BI1S83 mask.rb. src.rb. dst.wb

Bit set byte 3-operand

BISL2 mask.rl. dst.mi

Bit set locng 2-cperand

BISL3 mask.rl. src.rl. dst.wi

Bit set long 3-operand

BISPSW mask.rw

Bit set processor status word

BISW2 mask.rw, dst.mw

Bit set wora 2-operand

BISW3 mask.rw, src.rw, dst.ww

8it set word 3-operand

Bit test byte

BITB mask.rb. src.rb
8ITL mask.rt. src.rl

BITW mask.rw. src.rw

Bit test word

BLBC src.rl. gispl.bb

Branch on low bit ciear

€8

BLBS src.ri. displ.bb

Branch on low bit set

BLEQ aispl.bb

Branch on less or equal

BLEQU displ.bb

BLSS displ.bb

BNEQ{ =BNEQU! displ.bb

Branch on less or equal unsigned
Branch on less
:
Branch on not equal

BPT [{-(KSP).w":

Break point fauit

BRB displ.bb

Branch with byte disptacement

BRW displ.ow

Branch with word displacement

BS8B8 displ.bb. {-(SP).wi}

Branch to subroutine with byte

BSBW displ.bw. (<(SP).wi}

displacement
granch to subroutine with word

BVC displ.bb

BVS dispi.bb

Branch on overflow set

CALLG arglist.ab. dst.ab. «(SPyw"!

Call with general argument list

CALLS numarg.rl, dst.ab. -(SPLw"!

Call with argument list on stack

CASERB selector.rb, base.rb, limit.rb.

Case byte

O
O
OO

8it test long

rsv

000

Exceptions
rsv

BICW2 mask.rw, dst.mw

OoP

SUMMARY

INSTRUCTION SET

displacement

o
o ¢

8ranch on overflow clear
rsv

rsv

displ.bw-list

CASEL selectar.rl, base.rl. limit.ri,

Case long

displ bw-list

CASEW selector.rw. base.rw. limit.rw.

Case word

CHMU param.rw. [-(ySP).w"}

Change mode to user

—-

CLRQ dst.wq

Clear quad

CLRW dst.ww

Clear word

Clear long

Clear byte

CLRB dst.wb
CLRL dst.wi

Where y = MINU(x.PSL<{current _mode>)

O o

Change mode to supervisor

CHMS param.rw, [-(ySP).w"}

Change mode to kernel

O OO

Change mode to executive

CHMK param.rw, {-(ySP).w"}

CHME param.rw, {-{ySP).w"!

=10

el eNeNe

displ.bw-list

‘field.rvi}. src.ri

Compare long
Compare field

- Compare wmd

CMPW srct.rw. src2.rw

CMP2ZV pos.rl. size.rb. base.vD.

Compare zero-extended field

SET

Exceptions

CMPV pos.rl. size.rb. base.vb.

Compare byte

rsv

O O

OO0 0O«

Description

Mnemonic & Arguments
CMP8 srct.rb, src2.rb
CMPL srct.ri. src2.ri

+ O

INSTRUCTION

rsv

‘field.rv}, src.ri

32
97

DECB dif.mb

Decrement long

DECL dif.mi
DECW dif. mw

DIVB2 divr.ro. quo.mb

Divide byte 2-operand

DIVB3 divr.rb. divd.rb. quo.wb

Dwvide byte 3-operand

Cé

DIVL2 divr.ri, quo.mli

Divide long 2-operand

Decrement word

OIVL3 divr.r, divd.rl. quo.wl

Divide long 3-operand

DIVW2 divr.rw. quo.mw

Divide word 2-operand

DIVW3 divr.rw, divd.rw. quo.ww

Divide word 3-operand

EDIV divr.rl, divd.rq. quo.wi. rem.wi

Extended divide

EMUL muir.rl, muld.rl, add.rl.prod.wq

Extended muitiply

EXTV pos.rl. size.rb. base.vb.

Extract field

-y

0 00O

Decrement byte

OO0

1oV
TeYY}

CVTLW sre.rl, dst.ww
CVTWB src.rw, dst.wb
CVTWL src.rw, dst.wi

1oV

CVTLB src.rl, dst.wb

Convert byte to word
Convert long to byte
Convert long to word
Convert word to byte
Convert word to long

Convert byte to long

1oV

000000

CVTBL src.rb. dst.wi
CVTBW src.rb. dst.wl

10V, 1dvz
1oV,

10V, 1avz
1oV,

EXTZV pos.ri. size.rb. base.vb,
‘tield.rvi, dst.wi

. dvz
rsv

Extract zero-extended field

rsv

Find first clear bit -

rsv

Find first set bit

rsv

FFC startpos.ri. size.rb. base.vb.
‘tield.rv}, findpos.wl

FFS startpos.rl. size.rb. base.vb.
field.rv}. findpos.wi

prv

Increment byte

10V

INCL sum.mi

increment iong

1oV

INCW sum.mw

Increment word

INDEX subscript.rl. low.rl. high.ri.

index caiculation

Halt (kernel mode only)

INCB sum.mb

sub

HALT -(KSP).w"!

rsv

40O

rsv

size.rl, indexin.rl. indexout.wl

INSQHI entry.ab. header.aq

Insert at head of queue. interlocked

INSQTI entry.ab. header.aq

Insert at tail of queue. interlocked

INSQUE entry.ab. pred.ab

Insert into queue

INSV src.ri, pos.rl, size.rb.

Insert tield

base.vb. ifield.wvl
17

JMP dst.ab

Jump

JSB dst.ab. [-(SP).wil}

Jump to subroutine

idvz

0V, idvz

tield.rvi. dst.wi

idvz

oV, iavz

rsv

SUMMARY

INSTRUCTION SET SUMMARY
oP

Mnemonic & Arguments

Description

LDPCTX (PCB.r*. -(KSP).w"}

Load process context

Exceptions
rsv.

prv

(kernel mode onty)

MCOMB src.rb. dst.wb

MCOML src.rl. dst.wi

Move complemented long

MCOMW src.rw. dst.ww

Move compiemented word

]]

MFPR procreg.ri, dst.wi

Move complemented byte

Move from processor register

prv

(kernel mode only)
Move negated byte

Te)Y}

Move negated long

MNEGW src.rw. dst.ww

IOV

MOVAB src.ab. dst.wi

Move negated word

1oV

MOVAL{ =F' src.al. dst.wl

Move address of iong

MOVAQ{
=D =G} src.aq. dst.wil

Move address of quad

MOVAW src.aw. dst.wi

MQOVEB src.rb. dst.wb

Move byte

MQVC3 len.rw. srcaddr.ab. dstaddr.ab.

Move character 3-operand

{RQO-5.wi}

MOVCS srclen.rw. srcaddr.ab. fill.rb.

Move address of word

Move character S-operand

OO0

DE
7E

Move address of byte

000

MNEGB src.rb. dst.wb
MNEGL src.rl, dst.wi

MOVPSL dst.wi

Move long

MOVQ src.rq. dst.wq

Move processor status longword
Move quad
Move word

MCVW src.rw. dst.ww

MQOVZBL src.rb. dst.wi

MQOVZBW src.rb. dst.wb

MOVZWL src.rw, dst.ww

MTPR src.rl. procreg.rt

Move zero-extended byte to long
Move zero-extended byte to word
Move zero-extended word to long

Move to processor register

OO0

“MOQVL src.rl. dst.wi

00
oC

_Qstlen.rw, dstaddr.ab. {RO-5.wi}

rsv.

MULB2 muir.rb. prod.mb

MULB3 muir.rb. muid.rb. prod.wb

Multiply byte 3-operand

MULL2 mulr.ri. prod.mi

O OO0

1oV

Multiply long 2-operand

MULL3 mulr.rl, muid.rl. prod.wl

Muitiply long 3-operand

(kernel mode only)

Multiply byte 2-operand

NOP

POPR mask.rw,

PROBER mode.rb. len.rw. base.ab

Probe read access

Probe write access

PROBEW mode.rb. len.rw. base.ab
PUSHAB src.ab. {-(SP).wi}

PUSHAL[ =F} src.al. [-(SP).wl}

Push address of long

PUSHAQ{ =D =G} src.aq, [-(SP).wl}

Push address of gquad

No operation

[(SP)
- r"!

Pop registers

Push address of byte

PUSHAW src.aw, {-(SP).wi}

Push address of word

ln)

PUSHL src.ri.

Push long

PUSHR mask.rw,

{-(SP).w"!

Push registers

Return form exception or interrupt

IQV
1oV

Multiply word 3-operand
4§

Multiply word 2-operand

MULW3 mulr.rw, muid.rw. prod.ww

000000

MULWZ2 mulr.rw. prod.mw

rsv

prv

Mnemonic & Arguments

Description

REMQHI header.aq. addr.wi

Remove from head of queue.

REMQT header.aq, addr.wi

o
Z

INSTRUCTION

Exceptions
rsv

interlocked

Remove from tail of queue.

- rsv

interiocked

REMQUE entry.ab. addr.wi

Remove from gqueue

RET {(SP)+.r"}

Return form procedure

ROTL cnt.rb. src.ri. dst.wil

Rotate long

.
rsv

RSB {(SP)
+ .ri}

Return from subroutine

S8WC sub.ri. dif.mi

Subtract with carry

SOBGEQ index.mi. displ.bb

IOV,

Subtract one and branch on greater
or equal

SOBGTR index.mi. displ.bb

Subtract one and branch on greater

SUBB2 sub.rb. dit.mb

1oV

Subtract byte 2-operand
Subtract byte 3-operand

SUBB3 sub.rb. minrb. dif.wb

SUBL2 sub.rl. dif.mi

SUBL3 sub.rl, min.ri. gif.wl

Subtract long 2-operand
Subtract long 3-operand

oV
1oV

SUBW2 sub.rw. dif. mw

SUBW3 sub.rw. min.rw. dif. ww

Subtract word 2-operand
Subtract word 3-operand

SVPCTX {SPY+.r*. PCB.w"!

Save process context

TSTB src.rb

TSTL src.ri

Test long

TSTW src.rw

Test word

oV
]

Cc2

XFC {unspecified operands;

Extended function call

XORB2 mask.rb. dst.mb

Exclusive or byte 2-operand
Exclusive or byte 3-operand

XORB3 mask.ro. src.rb. ast.wb

XQORL2 mask.rl. dst.mi

XORL3 mask.rl. src.ri, dst.wi

XORW2 mask.rw. dst.mw

Exclusive or long 2-operand
Exclusive or long 3-operand
Exclusive or word 2-operand

XORWS3 mask.rw. src.rw. dst.ww

Exclusive or word 3-operand

OO0 00000000

ikernel mode only)
Test byte

SET SUMMARY

prv

INSTRUCTION

B.3

SET

FLOATING

SUMMARY

POINT

INSTRUCTION

SUMMARY

instructions are implemented in. hardware 1f
the
optional
MicroVax
[f the MicroVaAX
1n the system.
Floating Point Unit (FPU) is present
V
78132 FPU 1s not present 1in the system a reserved
willl
operand
fault
be
taken and system software may emulate these instructions.

These

Add compare and branch D _floating

ACBF limit.rf, add.rf. index.rf

Add compare and branch F_floating

ACBG limit.,rg, add.rg, index.rg

ADDF3 add1.rf. add2.rf. sum.wf

Add F _floating 3-operand

40FD

ADDG2 add.rg, sum.mg

Add G _floatung 2-operand

41FD

ADDG3 add1.rg, add2.rg. sum.wg

Add G _floating 3-operand

CMPD src1.rd. src2.rd

Compare D _floating

CMPF srct.rf, src2.rf

Compare F _floating

51FD
6C

Compare G _floating

CMPG src1.rg, src2.rg
CVvTBD src.rb. dst.wd
CVTBF src.rb. dst.wf

4CFD

CVTBG src.rb. dst.wg

Convert oyte to G_floating

CVTDB src.rd. dst.wb

CVTDF src.rd. dst.wf

Convert D _floating to byte
Convert O _floating to F_floating

CVTDL src.rd. dst.wi

CVTDW src.rd, dst.ww

CVTFB src.rf. dst.wb

CVTFD src.rf, dst.wd

99FD

CVTFG src.rf, dst.wg

CVTFL src.rf, dst.wi

CVTFW src.rf, dst.ww

48FD

CVTGB src.rg, dst.wb

33FD

CVTGF src.rg. dst.wf

4AFD

CVTGL src.rg. dst.wl

49FD

CVTGW src.rg. dst.ww

CVTLD src.rl. dst.wd

Convert byte to D _floating

Convert byte to F_floating

Convert D _floating
to long
Convert D _floating to word
Convert F_floating to byte
Convert F _floating to D _floating
Convert F_floating to G _floating
Convert F_floating to to long
Convert F_floating to word
Convert G _floating to byte
Convert G_floating to F _floating

Add D _floating 3-operand
Add F _floating 2-operand

ADDD3 addtl.rd. add2.rd. sum.wd

ADDF2 add.rf. sum.mf

61
40

O O

Add D _floating 2-operand

Tt O 00000000V

Add compare and branch G _floating

- ADDD2 add.rd. sum.md

“

Convert G _floating to to long

Convert G _floating to to word
Convert long to D _floating

Convert long to F_floating

CVTLG src.rl. dst.wg

Convert long to G_floating

Convert word to D _floating
Convert word to F_floating

CVTWD src.rw, dst.wd
CVTWF src.rw, dst.wf

4DFD

CVTWG src.rw, dst.wg

Convert word to G _floating

Convert rounded D _floating to long

CVTRODL src.rd. dst.wi
CVTRFL src.rf, dst.wi
CVTRGL src.rg, dst.wi
DIVD2 divr.rd, quo.md

DIVD3 divr.rd, divd.rd. quo.wd

Dwvide D _floating 3-operand

OIVF2 divr.rf, quo.mf

Divide F _floating 2-operand

OIVF3 divr.rf, divd.rf, quo.wf

Divide F _floating 3-operand

46FD

DIVG2 divr.rg. quo.mg

Divide

47FD

DIVG3 divr.rg, divd.rg. quo.wg

Divide G _floating 3-operand

EMODD muir.rd. muirx.rb. muld.rd.

Extended modulus D _floating

G _floating 2-operand

int.wl, fract.wd

B-8

0O OO0

Divide D _floating 2-operand

OO O

4BFD

Convert rounded F _floating to long
Convert rounded G _floating to long

60
4D

CVTLF src.ri, dst.wf

4EFD

OO 000

4FFD

Description

ACBD limit.rd. add.rd, index.rd

Mnemonic & Arguments

ee e ole ool e e leoNeNeNoNoNoNoNoNeoRoNoNeoReoNeoNoNeoNoRNoNo oo Ro Re) sNeNeoRelNelNeNeo e

opP

78132

Exceptions
rsv,

fov. fuv

rsv.

fov, fuv

fuv

rsv,

fov.

rsv.

fov, fuv

rsv.

fov, fuv

ISV, fov. fuv
rsv.

fov. fuv

rsv,

fov. fuv

rsv.

fov. fuv

rsv

rsv.

IOV

rsv.

fov

rsv,

IOV

rsv,

iov

rsv
rsv
rsv,

TolY

rsv,

Te)Y]

rsv.

1oV

rsv.

fov. fuv

rsv.

1QV

rsv.

IQV

rsv,

Te)Y;

rsv.

10V

rsv,

fov, fuv,

rsv.

fov, fuv, fdvz

favz

rsv,

fov, fuv. fdvz

rsv.

fov,

rsv.

fov. fuv. fdvz

rsv.

fov, fuv, tavz

rsv.

fov.

fuv.

fdvz

To)Y,

INSTRUCTION SET

orP
34
-

54FD

Mnemonic & Arguments
EMQODF muir.rf. muirx.rb. muid.rf,

SUMMARY

Description
Extended moculus F _floatng

NZVC
T T Q

Exceptions
rsv, fov. fuv, 10v

Extended modulus G _floating

rsv. fov. fuv. iov

int.wl, fract.wf

EMODG muir.rg. muirx.rw, muid.rg.

int.wl, fract.wg

MNEGD src.rd. dst.wd

Move negated D _fleating

rsv

32
52FD

MNEGF src.rf. dst.wf
MNEGG src.rg. dst.wg

Move negated F _floating
Move negated G _floating

00
T
00

rsv
rsv

T Q

MOVD src.rd. dst.wd

Move D _floating

rsv

50
50FD

MQVF src.rf. dst.wf
MOVG src.rg. dst.wg

Move F_floating
Move G _floating

0 Q0 -

rsv
rsv

MULD2 muir.rd. prod.md

Multiply D _floating 2-operand

835
14

MULD3 mulr.rd. muld.rd, prod.wd
MULF2 mulr.rt. prod.mf
|

Muiltiply D _floating 3-operand
Multiply F_floating 2-operand

" "0 0
7 "0 0
.00

MULF3 muir.rf. muid.rt. prod.wt

Muitiply F_floating 3-operand

44FD

MULG2 mulr.rg. prod.mg

Multiply G _floating 2-operand

70 0

rsv. fov. fuv

45FD

MULG3 muir.rg. muld.rg. prod.wg

Muiltiply G _floating 3-operand

T 0 0

rsv, fov. fuv

POLYD arg.rd. degree.rw. table.ab

Evaluate polynomial D _floating

35
55FD

POLYF arg.rt. degree rw. table.ab
POLYG arg.rf. degree.rw. table.ab

Evaluate polynomial F _floating
Evaluate polynomial G _floating

SUBD2 sub.rd. dif. nd
sSuBD3 sub.rd. min.rd. dif.wd

42
43

12FD

rsv, fov. fuv

rev. fov. fuv
rsv. fov. fuv
rsv. fov. fuv

rsv. fov. fuv

00
"0 0

rsv. fov. fuv
rsv. fov, fuv

Subtract D _floating 2-operand
Subtract D _floating 3-operand

*
0 0
00

rsv. fov, fuv
rsv. fov, fuv

SUBF2 sub.rf. dit.mt

Subtract F _floating 2-operand

rsv. fov. fuv

SUBF3 sub.rf. min.rf. dif.wf

Subtract F _floating 3-operand

rsv. fov. fuv

SUBG2 sub.rg. dif.mg

Subtract G _tloating 2-operand

rsv. fov, fuv

43FD SUBG3 sub.rg. min.rg. dif.wg

Subtract G _floating 3-operand

rsv. fov. fuv

TSTD src.rd

Test D _floating

rsv

33
33FD

TSTF src.rf
TSTG src.rg

Test F_floating
Test G _floating

0 0
*
00

rsv
rsv

INSTRUCTION SET SUMMARY

78032

1nstructions

CPU
by

WITH

MICROCODE

provides
system

ASSIST

microcode

SUMMARY

assistance

for

emulation

the.

software.

Mnemonic & Arguments

Description

ADDP4 addlen.rw, addaddr.ab.

Add packed 4-operand

MicroVAX

these

INSTRUCTION

The

EMULATED

8.4

Exceptions
rsv.

dov

Add packed 6-operand

rsv.

dov

Arithmetic shift and round packed

rsv.

dov

sumien.rw. sumaddr.ab

ADDP6 addilen.rw, addtaddr.ab.

add2ien.rw, add2addr.ab,
sumlen.rw, sumaddr.ab

ASHP cnt.rb. srclen.rw, srcaddr.ab,
round.rb. dstlen.rw. dstaddr.ab

CMPC3 len.rw. srcladdr.ab.

Compare character 3-operand

- src2addr.ab

CMPCS srctlen.rw. srctaddr.ab.
fill.rb. src2len.rw., src2addr.ab

CMPP3 len.rw. srctaddr.ab.
src2addr.ab

CMPP4 srcllen.rw. srcladdr.ab.

Compare character 3-operand

Comparé packed 3-operand
Compare packed 4-operand

src2len.rw, src2addr.ab

CRC tbl.ab. inicrc.rt. strien.rw.

Calculate cyclic redundancy check

stream.ab

36
08

CVTLP src.rl. dstlen.rw. dstaddr.ab
CVTPL srclen.rw. srcaddr.ab. dst.wi

Convert long to packed
Convert packed to long

CVTPS srclen.rw. srcaddr.ab,
dstlen.rw. dstaddr.ab

CVTSP srclen.rw. srcaddr..
dstlen.rw. dstaddr.ab

CVTPT srclen.rw. srcaddr.ab.

rsv,

dov

Convert packed to leading separate

rsv.

dov

Convert leading separate to packed

rsv. -dov

Convert packed to trailing

rsv.

dov

Convert packed to trailing

rsv.

dov

Oivide packed’

rsv,

dov . ddvz

Edit packed to character string

rsv.

dov

rsv,

dov

tbladdr.ab. dstlen.rw, dstaddr.ab

CVTTP srcien.rw. srcaddr.ab.

tbladdr.ab. dstlen.rw, dstaddr.ab

DIVP divrien.rw, divraddr.ab.
divdlen.rw. quolen.rw, guoaddr.ab

EDITPC srclen.rw. srcaddr.ab.
pattern.ab. dstaddr.ab

LOCC char.rb. len.rw. addr.ab
MATCHC objien.rw. objaddr.ab.

Locate character
Match characters

srclen.rw, srcaddr.ab

MQOVP len.rw, srcaddr.ab. dstaddr.ab
MQOVTC srclen.rw. srcaddr.ab. fill.rb.

Move packed

Move transiated characters

tbladdr.ab, dstlen.rw. dstaddr.ab

MOVTUC srclen.rw. srcaddr.ab. esc.rb.

Move translated until character

zmaddr.ab. dstien.rw, dstaddr.ab

MULP muirlen.rw, muiraddr.ab.

muldlen.rw. muldaddr.ab. prodien.rw.

Multiply packed

prodaddr.ab

SCANC len.rw, addr.ab. thiaddr. ab.

Scan for character

mask.rb

SKPC char.rb. len.rw. addr.ab

Skip character

Mnemonic & Arguments

Description

SPANC len.rw, addr.ab. tbladdr.ab.

Soan characters

v C
4

o Z

INSTRUCTION

SET

Exceptions

mask.rb

SUBP4 sublen.rw, subaddr.ab.

Subtract packed 4-operand

rsv.

dov

Subtract packed 6-operand

rsv.

dov

diflen.rw, difaddr.ab

SUBPS sublen.rw. subaddr.ab,
minien.rw. minaddr.ab. diflen.rw,

difaddr.ab

‘

SUMMARY

APPENDIX C

CONSOLE ENTRY AND EXIT ROUTINES

C.1l

INTRCDUCTICN

This appendix contains an example of a console entry and exit routine and a
routine for simulating the memory management process. - These routines are
written

C.2

in VAX-1l1l Macro.

CONSOLE ENTRY AND EXIT ROUTINE

The
The following are routines for entering and exiting the console.
1in
d
describe
s
as
proces
console typically would be entered from the restart
the
saves
routine
Section 2.8 of this user's guide. The console entry
volatile 1internal registers and process state, performs a stack swap 1f
necessary, sets up the console stack pointer and calls the main console
The console exit routine is a mirror of the entry routine and
routine.
restores the saved state of the processor back to the running state.

CONSOLE

ENTRY

AND

ROUTINES

Exafiple of a Console Entry and Exit Routine

Include

files:

These

S
E

;

SPRDEF

;

files

are

used to define
PSL fields.

.TITLE

EXIT

SPSLDEF

part

MicroVMS

the processor

and

can

registers

and

the

; Define processor registers

; . Define PSL

fields

MACROS:

.macro

mtpr pic

moval

src,r0

src,dst

mtpr
.endm

r0, #dst
mtpr pic

.macro

mcheck dst

movab

dst,machine_check
cont

.1f blank dst
clrl
machine check cont
.1f false

This macro

calls

the

routine

that

wEd

wEe

.external machine check cont
.endm
mcheck

.macro
pushl
pushal
pushal
calls

poke
data,dst
#19.
data
dst
#3,memory

.external memory
. endm
poke

simulates memory management

ENTRY

AND

EXIT

Equated Symbols:

PSLSV_CURMOD
PSLS$S_CURMOD

;

(I |
AN [ N

x60

~d9.

| O

{ S

| O

~d10
~d1l
~d12
~d13
~d16
~d17
~d32
~d34
~d38
~d4l
~d42
~d43
~d55
~d56

LN | N

PRS_SBR
PRS_SLR
PRS_PCBB
PRS_SCBB
PRS_RXCS
PRS_TXCS
PRS_MCESR
PR$_SAVISP
PRS_SAVPC
PRS_SAVPSL
PRS_IORESET
PRS_MAPEN

~d8

PRS_POBR
PRS_POLR
PRS_P1BR
PRS_PILR

k_parity.error
kK_bus.timeout

> o

scb_a write timeout

scb a mcheck

CONSOLE

MicroVAX special
MicroVAX special
MicroVAX special
Bus init

saved isp reg
saved pc reg
saved psl reg

~d24
~d2

declare
the psects

’

.psect
.psect

$$$$$0boot,page
$scb$,page

;
;

main code psect for
scb 1s located here

start

ROUTINES

CONSOLE

ENTRY

AND

ROUTINES

$scbs

the

console

;

SCB must

scb

Console

Program SCB.

.psect

EXIT

.align
SCB::

. long
. long
. long
. long
. long
. long
. long
. long
long
. long
.long
. long
. long
. long
. long
. long
. long
. long
. long
long
long
long
long
long
long
long
long
long
»

L ]

.long
»

. long
long
long
long
.long
long
long
. long
-

. long
. -0Ng
. Long
. long
. long
. long
. long
. long

' page

scb_int 00+l

;

#00

machine check detect+l

scb_int 08+1
; #08
scbmzntm0c+l
; #0C
scb_int 10+1
; #10
; #14
scb int 14+l
reserved operand_int+l

scb_int Ic+l

;

scb_int_ 24+1
scb_int_28+1
scb_int_2c+l
scb_int_30+1

;
;
;
;

scb_int 20+1

scb_int 34+1
scb_int 38+l
scb_int_3c+l
scb_int 40+l
scb_int_ 44+l

scb_
1ntm48+l
scb_int 4c+l

scb_int S50+1.
scb_int_34+1
scb_int 58+1
scb_int 5c+l
wrlte tlmeout
scb_int 64+l
scb_int 68+1
scb_int_6c+l
scbmlntm70+l
scb_int _74+1
scb_int_78+1
scb int7c+l

scb_int 80+1

scb_int 84+1
scb_int 88+l
scb_int 8c+l
scb_int 90+1
scb_int_ 94+l
scb_int 98+l
scb_int 9c+l
scb_int _al+1
scb_int_ a4+l
scb_int_ a8+l
scb_1int_ac+l
scb_int_pbO+l

;

;
;
;
;
;

;
;

#1C

#20

#24
#28
#2C
#30
#34
#38
#3C
#40
#44

#48
#4C

; #50
; #54
; #58
; #5C
1nt+l
; #64
; #68
; #6C
; 470
; #74
; #78
; #7C

;

;
;
;
;
;
;
;
;
;
;
;
;

#80

#84
#88
#8C
#90
#94
%98
#9C
#AQ
AL
#A8
#AC
%BO0

aligned.

Unused.
MCHK
; #04
KSP 1nvalid.
Power failure.
Reserved/priv lnstr.
XFC instr.
; #18
Reserved oprnd.
Reserved addr mode.
"
Access violation.
Trans invalid.
Trace pending.
BPT

Compatibility mode
Arithmetic
Unused
Unused
CHMK.
CHME
CHMS
CHMU

SBI

SILO

Corrected Mem Read
SBI Alert
SBI Fault

;

#60

Unused

Write timeout
«

Unused
Unused
Unused
Unused
Unused
Unused
Unused
Software
Software
Software
Software
Software
Software
Software
Software
Software
Software
Software
Software
C-4

level
level
level
level
level
level
level
level
level
level
level
level

1.
2.
3.
4.
3,
t.
7,
8,
9,
10.
11.
12.

scb intdg+1l
scb

int dc+l

scb int eO+l

scb int e4+l
scbhb int e8+1

scb_int_ec+l

scb_int_£0+l
scb_int_f4+l

scb int Tf8+1
T fc+l
scb int_

NS
RS
e s
wF WE we

'scb_int_cc+l
scb int _dO+1
scb int dé+1

WS NS

scb int c4+1
scb_int_c8+1

e WS

int

scb

c0+l

#B4
#B8

#BC

#CO
#C4
#C8
#CC
#D0
#D4
#D8
#DC
#E0
#E4

4E8

4#EC
#F0
#Fa

#F8
#FC

scb int b8+1
scb int bc+l

b4+l

scb_int

NS WG

. long
. long
. long
.long
. long
. long
. long
. long
. long
. long
. long
.long
. long
. long
.long
. long
.long
. long
. long

N e

CONSOLE ENTRY AND EXIT ROUTINES

Software level
Software level
Software level

13.
14,
15.

Interval timer.
Unused
Emulation start.

Emulation continue.
Unused
Unused

Unused

CSS
CSS
CSS
CSS

Console
Console
Console
Console

TUSS8
TUS8
Transmit.
Receilve.

CONSOLE

ENTRY AND

ROUTINES

;

get

the

right psect

+
+

3$S55550boot

CONSOLE

.psect

EXIT

all

starts

right

here.

HUE

UEF

We get here on a halt condition. The system has been
brought to a stable/known state by microcode, and the
volatile system registers have been saved away in known
MicroVAX registers.
This code copies the saved registers
to our private scratch RAM,
The GPR's are saved as well.
[t 1s assumed that the RAM is at a known address and good.
processor

state

follows:

savpc

The

savpsl

Savisp
Sp

=
=

saved pc
saved psl

"real"
=

UE
%S

saved mapen

pC
psl

=
=

20040000
041F0000

sisr
iccs

=
=

??2?
??2?

astlivl

?2?2?

error

code

time of
|

error

(except RESET = 4)

(except
(except

RESET
RESET

=
=

0)
0)

The

saved

VALID

FOR

CBE

1isp
stack pointer

console

MANAGEMENT

now

limited
A

LIMITED

MUST

entered

life
BE

with

internal

TIME

LEFT

ONLY.

the

state

registers.
1IN

DISABLED,

the

PARTICULAR,

AND

processor

THIS STATE

ONLY

MEMORY

SUBSET

THE

TME

INSTRUCTION SET CAN BE USED (no emulated instructions)
before the saved values are moved to permanent memory.

CODE

HALT

MAPPE N

R14

#pr$_savpc,saved_pc

movz bl

#prS$_savpsl,saved psl

mova 1

saved _psl+l, saved
saved _psl+l
sSp, temp
saved regds, sp

pusn r
cmpz v

-1
#0,#7,saved _halt, #3

save all the regs
see 1f this 1s a RESET

bneqg

;

no,

mova 1

ram_stack _end+<10%*4>, saved

the

and

take

saved pc
saved 1sp
saved psl

save
save
save
move

halt

TMS

clrb
mov
1l

#prs _savisp, saved 1sp

wme

mfpr
mfpr
mipr

SP
RO

WTM

[SP

PSL

save

wNg

CONSOQLE:

save sp,
point at

isp

C-6

saved

i1t

halt

out

code

the

for now
end of saved

ISP

;

ves,

mappen

saved psl
reg

space

real

use

end

our

stack

CONSOLE ENTRY AND EXIT ROUTINES

5S:
Set

;

new

ram_stack,sp

moval

up on known ok

stack

save

SCBB

;

update

from before

?SP

trap

#pr$_scbb,saved_scbb
#prsS_pcbb,saved_pcbb
#0,#7,saved_halt, #3
6S
saved pcbb

bbs

#26.,saved psl,isp_ok

save
save

#pslSs_curmod, -

wN»
S
e

saved pcbb rl
#psl$v_curmod, -

~
&

movl
extzv

br if we were running on ISP
get pcb addr handy,
get current mode as well,
for stack swap

saved psl,r2

(rl)(r2],rl

temp,(rl)

get addr of ?SP cell
and copy SP there - was
saved 1in temp

movl

moval

6S:

users scb
users pcb

see 1f this is a RESET
no, so PCBB is real
yes, so PCBB is undefined,
set 1t to O

mfpr
mfpr
cmpzv
bneg
clrl

wNs

PCBB

;

set

~
&

isp_ok:
save

RXCS
TXCS

prs txcs,rl

movl

rl, saved txcCs

bbcc
mepr

#6,rl1,8%
rl,#prsmtxcs

mfpr

get

term

and save
clear IE

#pr$_rxcs,rl
rl,saved rxcs
#6,rl,7$
rl,#prs$_rxcs

mfpr
movl
bbcc
mtpr

get

of
of

term

and save
clear IE

IE bit
IE bit

-s

;

;
+

status

it
1f

away
set

status

1t
1f

away
set

8S:
; setup

trappers

call

the

console

#0,console main

W
WE

calls

scb,pr$_scbb
ram pcb,prs$_ pcbb

mtpr_pilc
mtpr_pic

mcheck

and

;

SCB
PCB

;
;

disable mcheck trapper
i.e., mchecks are fatal
set up the scb
set up the pcb
we are up, go flqure out
what to do

CONSOLE

’

ENTRY

AND

now externalize
.external
.external
.external
.external

EXIT

all

ROUTINES

the

externals

need

saved_pc,saved_psl,saved_isp,temp

saved _regs,saved_regs_ end
saved_pcbb, saved_scbb, ram_pcb
ram stack,ram stack end savmd
.external console main,saved halt
.external machlnemflheckmflont

rxcs,saved_txcs

CONSOLE

ENTRY

AND

EXIT

ROUTINES

+
s+

CONSOLE EXIT

;

:
;

This code is a mirror of CONSOLE, and restores the
saved state back to the running state.

.entry
console exit,"m<r2,r3,r4,r5,r6,r7,r8,r9,rl0,rll>
mtpr
#°xff,#pr$_mcesr
; clear machine check error
mcheck
508§
; 1f anything goes wrong, go back
movl
poke

saved isp,r?2
saved psl,-{(r2)

bneg

50S

poke

saved pc,-(r2)

;

put pc on stack

tstl
bneq

r0
50§

;
;

any errors?
ves, back we

movl

r2,temp

;

save

mtpr
mtpr
mcheck
mtpr

saved rxcs,#pr$_rxcs
saved_txcs, #pr$_txcs

;
;
;
;

restore terminal status
restore terminal status
disable mcheck trapper
set up the scb

;
;

set up the pcb
point at start of

;

space

;

restore all

tstl

mtpr
moval

popr
bbc

saved_scbb, #pr$_scbb
saved pcbb, #prs_pcbb
saved_regs_end,sp

$-1

movl

temp, Sp

map_on

mcheck
ret
~.align
|

mtpr

;

#7,saved halt,console_rei

brb

MAP ON:

get the stack pointer
put PSL on stack

;
;
:
;
;
;
;
;
;
;

50§$:

;
;

long

#l,#prS$S_mapen

the PSL and PC must be put on
the lnterrupt stack, prior to
the REI, if MAPEN 1s also on,
then the stack must be mapped,
and the PSL and PC put back on
the mapped stack...the poke
macro calls a routine that
handles the problems of
dealing with the mapped stack
any errors?
yes,

back

stack

restore

;

the

saved sp

saved

(IE)
(IE)

reg

registers
to

sys not mapped,

skip

;
;

mapping.
goto long word

;

turn

;
;

disable mcheck trapper
if we fail, go back to

;
;
;
;
s

1n order for the enable of
MAPEN to work, i1t MUST be 1in
the same longword as the REI,
thus this .align long is
MOST critical

;

Mapping

aligned map

on.

turned
on

user,.

CONSQOLE ENTRY AND EXIT ROUTINES

CONSOLE REI::

rel

;

and back to user

C-10

CONSOLE

. now externalize all the externals we need
.external savedpc,saved_psl, saved 1sp

_regs, saved _regs_ end
.external saved

;

(@]

_pcbb, saved scbb, ram_pcb
.external saved
_rxcs,saved txcs
ved
stack,sa
ram_
.external

ENTRY

AND

EXIT

ROUTINES

+
é*,

machine check_detect

functional description:
This sequence is the error trapper.
This sequence runs when a
machine check oc¢urs.
If machine check_cont is not 0 the reason
for the machine check is moved to r0 and then an REI to the
machine check cont address is executed.
If machine_check_cont
is 0 the trap is handled as an unexpected scb interrupt.
inputs:

machine_ check cont:

check

stack

= address of

the continuation code or O

outputs:

machine

wsk

CONSOLE ENTRY AND EXIT ROUTINES

machine

check

code

|
i

WME

.align

long

movl
addl
mov 1
reil

4(sp),r0
(sp)+,sp
machine check cont, (sp)

machine_check_cont
unfielded scb_int

#°xff,#pr$_mcesr

tstl
begl

mtpr

machine_check_detect:

clear machine check
change return PC?
unexpected error 1if
continue addr
load reason
pop stack

actually change
continue

error

return PC

,f
,+

‘write timeout

reserved operand

CONSOLE ENTRY AND EXIT ROUTINES

This sequence runs when a write timeout or reserved operand occurs.

functional description:

inputs:

PC/PSL are on

the

stack

= address to continue at or O

outputs:

machine check_cont

error

code

.align

long

write timeout_int:
reserved_operand_int:

mov 1

machine check_cont, (sp)

movl
rel

#k _bus.timeout,r0

beql

unfielded scb_int

;reset PC

;yunexpected error 1f no
;ycontinue

;set code
done

addr

+
+

unfield
scb ed
_int

functional

description:

This routine is
booting. System

executed

if
halted.

unwanted

SCB

interrupt

occurs

inputs:

scb

interrupt

stack

outputs:

rQO
rl

has scb offset for unfielded
r0 1is undefined
has sp at time of trap

scb

wyg

WME

- CONSOLE ENTRY AND EXIT ROUTINES

.align

long

unfielde
scb int:
d
sp,rl

movl
halt

interrupt

otherwise

during

CONSOLE ENTRY AND

.align
scb_1int 00:

movl
brw

scb_int 04:

mov
1l
brw

scb_int 08:

movl
brw
.align
movl
brw

scb_int Oc:

scb_int 10:

scb_int 1l4:

scb_int 18:

.align

.align
movl
brw
.align
movl
brw

.align
movl
brw

.align

scb_int lc:

movl
brw

scb_int 20:

movl
brw
.align
movl
brw

scb_i1nt 24:

.align

scb_int 28:

movl
brw

scb_int 2c:

movl
brw

scb_int_30:

scb_int_34:

scb_1nt 38:

scb_int 3c:

.align

.align
movl

brw
.align
movl
brw
.align
mov
1l
brw
.align

long
#7x0,r0
unfielded scb_int
long
#°x4,r0
unfielded
scb int
long
#°x8,r0
unfielded _scb_int
long
|

#°xc,r0
unfielded_scb_int
long

#°x10,r0
unfielded scb_int
long

#°x14,r0
unfielded_scb
int
long
|

#°x18,r0

unfielded
scb int
long

#~xlc,rQ
unfielded scb_int
long

#~°x10,r0
unfielded scb_int
long
#°x14,r0
unfielded scb_int
long
#°x18,r0
unfielded_scb_int
long
#~xlc,r0

unfielded_scb_int
long

#°x10,r0
unfielded _scb_int
long
#°x14,r0

unfielded scb_int
long

#°x18,r0

brw

unfielded scb_int
long
$~x1lc,r0
unfielded
scb int

.align

long

movl

EXIT

ROUTINES

CONSOLE ENTRY AND EXIT ROUTINES

scb_int 40:

movl
brw

scb_int 44:

1l
mov

scb_int 48:

.align long
#°x14,r0
unfielded scb_int
brw
.align long
movl’
#°x18,rQ
unfielded scb_int
brw
.align

scb_int _4c:

movl
brw

scb_int_50:

movl

.align
brw

.align

scb_int_54:

movl
brw

.align

scb_int_58:

mov
1l
brw

.align

scb_int_5c:

movl
brw

scb_int 60:

movl
brw

scb_int_64:

movl
brw

.align

scb_int 68:

scb_int 6c:

scb_int_70:

scb_int _74:

scb_int_78:

scb_int 7c:

movl
brw

long
#~xlc,rQ

unfielded scb_int

long
#~x10,r0

unfielded scb_int

long
#°x14,r0

unfielded scb_int

long
#°x18,r0

unfielded scb_int

long

#°xlc,r0
unfielded scb_int
long

#~x10,r0
unfielded scb_int

long
#°x14,r0

unfielded_scb_int

long

#~x18,r0
unfielded scb_int

.align
mov
1l
brw

long

.align

long
#~x10,r0

movl
brw
.align
movl
brw

$~xlc,r0
unfielded scb_int

unfielded_scb_int

long

#~x14,r0
unfielded scb_int

.align

long

1l
mov
Drw
.align
1l
mov
brw

long

.align
scb_int _80:

#~x10,r

unfielded scb_int

mov
1l

#°x18,r0
unfielded scb_int

#~xlc,r0
unfielded scb_int
long
#~x10,r0

CONSOLE ENTRY AND EXIT ROUTINES
brw

.align

movl
brw

scb_int_84:

.align

long

.align
movl
brw
.align
movl
brw

scb_int_94:

scb_int_98:

.align

movl
brw

scb_int_Sc:

scb_int_a4:

scb_int a8:

scb_int_ac:

scb_int _bO0:

scb_int_bé:

unfielded scb_int
#~xlc,r0

unfielded_scb_int

long

#~x14,r0

unfielded_scb_int

long
#°x18,r0

unfielded scb_int

long

#°xlc,r0

unfielded_scb_int

.align long

mov
1l
brw

#~x10,r0

unfielded_scb_int

.align

long
#~x14,r0

.align

long
#~x18,r0

.align

long

movl
brw

unfielded scb_int
|

unfielded scb_int

movl
brw

#~xlc,rQ
unfielded_scb_int

.align
movl
brw

long

#~x10,r0
unfielded_scb_int

.align ‘long
#°x14,r0

movl
brw

.align

scb_int b8:

movl

scb_int_bc:

i
mov
brw

scb_int_cO:

unfielded _scb_int

.align long
mov
1l
#7x10,r0
unfielded_scb_int
brw

scb_int 90:

scb_int_a0:

#°x14,r0

long
#~x18,r0

‘movl
brw

scb_int_8c:

long

.align
movl
brw

scb_int_88:

unfielded scb_int

brw

unfielded_scb_int

long

$~x18,r0
unfielded_scb_int

.align

long

.align
movl
brw

long

4~xlc,r0
unfielded scb_int

$~x10,r0

unfielded scb_int
C-17

CONSOLE ENTRY AND EXIT
.align

scb_int cé4:

movl
brw

scb_int c8:

mov
1l
brw

scb_int _cc:

movl

.align

.align
brw

.align

scb_int _do0:

movl
brw

scb_int d4:

mov
1l
brw

scbflintmdB:
scb_int dc:

.align

.align
movl
brw

.align
movl

brw

scb_int _e0:

scb_1int_e4:

scb_1nt_e8:

.align
movl

brw
.align
movl
brw

.align
mov
1l
brw

RCUTINES

long
#°x14,r0
unfielded
scb int
long

#~x18,r0
unfielded scb_int
long
g~xlc,r0
unfielded
scb int
long
#°x10,r0
unfielded _scb_int
long
#~x14,r0
unfielde
scb int
d
long
#°x18,r0
unfielded
scb int
long
#°xlc,r0
unfielded
_scb _int
long
#~x10,r0
unfielded
scb int
long
#~x14,r0
unfielded_scb
int
long

$~x18,r0

scb_int ec:

mov
1l
brw

unfielded scb_int
long
#~xlc,r0
unfielded
scb int

.align

long

scb_int £0:

movl

scb_int f4:

scb_int f8:

scb_1int fc:

.align

brw
.align
movl
brw
.align
movl
brw
.align
movl

brw
. END

#°x10,r0
unfielded scb_int
long

#~x14,r0
unfielded scb_int
long

#°x18,r0
unfielded
scb int
long

$~xlc,r0

unfielded scb_int

CONSOLE

EXIT

BOOTRAM - MicroVAX BOOT RAM

Abstract:

BOOTRAM.
. .provides
space 1n RAM

initial setup of scratch

This sequence defines the scratch area in RAM used by the
ROM code.
This sequence uses preallocated space 1in RAM, an
alternative is to search for known good RAM and define it
as

the scratch

are

for

ROM.

Environment:

Mode=Kernel

|
|

+
+

.TITLE
%

ENTRY AND

.psect

BOOTRAM,

WRT,

PAGE

.align page
ram_start::

.blkl

.align

saved rxcs::

saved_txcs::
saved halt.:
saved_isp:
saved scbb :
saved _pcbb::

saved regs end

saved regs::
saved _pc::
saved psl
temp:

;process

control

block

for

.blkl

;

save rxcs

.blkl

15.

.blkl
.blkl
.blkl

1
1
1

;

save GPR's starting here

.blkl

128.

;

mini

long

.blkl
.blkl
.blkl
.blkl
.blkl

1
1
1
1
1

;
;
;
;
»

;
;
;

rom code

contains 0 or addr to xfer
after a machine check

“-aE

machine check cont::
.blkl

128

ram_pcb::

IE bit here

save txcs [E bit here
save salted halt code/mapen here
save salted isp here
save scbb here
save pcbb here
|

save salted pc here
save salted psl here
temp scratch cell for SP

rammstackmend::
ram_stack::

ram_end::

.end

stack to use while

in rom code

ROUTINES

CONSOLE

C.3

ENTRY

AND

EXIT

ROUTINES

MEMORY MANAGEMENT SIMULATICN

When memory management

enabled

when

exiting

from

the

console,

the

environment
that the console exits to must have a validly mapped interrupt
stack with at least to spare
longwords
at
the
bottom.
These
routines
simulate
read/writes
to physical memory with memory management on or off.
These routines are called by the poke macro in the console exit routine.

Example of MicroVAX Memory Management

Simulation

Include

files:

SPTEDEF
SVADEF
SPRDEF

~+
+
;

SPSLDEF

MACROS:

TME

.TITLE

.macro
mcheck dst
.1f blank dst
clrl
machine check cont
.1f false
movab
dst,machine
check cont
|
.endc

.external machine_check
cont
.endm
mcheck
.macro

push_mcheck

movl

machine_check cont,-(sp)

.endm

push_mcheck

.macro

pop mcheck

.external machine_check
cont

movl

(sp)+,machine_check
cont

.external machine check cont
.endm pop mcheck

Define PTE fields
Define virtual address fields
Define processor registers
Define

PSL

fields

Equated Symbols:

CONSOLE ENTRY AND EXIT ROUTINES

| B

success

err_acc_vio
err_bad_addr
err_len _vio
err_trans_nv

err_nxm

~d8
~d9
~d10
~dll
~d12
~d1l3

~d24
~d2

declare

the psects

‘e

PSL$V_CURMOD
PSL$S_CURMOD

| N

| B

PR$S POBR
PRS_POLR
PR$S_P1BR
PRS_P1LR
PRS_SBR
PR$_SLR

100
101
103
104
105

.psect

Smemman,page

:
»

’

main code psect
management

for memory

CONSOLE ENTRY AND EXIT ROUTINES

; get

the

right

psect

Smemman

PROBE
arguments

.psect

are

Virtual address
Physical address

<1>

Read/Write

indicator

read,

write)

WTME

WME

R2
R3
R4

This routine translates a virtual addresses to a physical
address.
If write intent, and MAPEN, then also sets the M bit
in PTE.

RNE

returned

(filled

in)

status

success

err_acc_vio
err_len vio

=
=

1
2

err_trans_nv

|
|

return

arguments are
R2
unchanged
R3
Physical address
R4
unchanged

.entry
movl

probe,

r2,rl

;

get

movl

Vaddr

ré,r2

;

get

quals

extzv
9s:

"m<R2>

;

get

caseb

|, rQ,#0,#2

;

.word
.word
.word

10§-S$
20$-95
30$-95

;
;
;

PO
Pl
SO

ferr_acc_vio,r0
408$

;
;

assume
err

mov 1l
brb

#30,#2,rl1,r0

PO/P1l/S0/S1 dispatch
to

correct

failure

calls

#0,get _pO0_Vaddr

;

map

brb

408

;

join

20S:

calls
brb

#0,get
pl Vaddr
408

;
;

map a pl addr
Joln common

30S:
40S:

calls
movl

#0,get_sys Vaddr
rl,r3

;
;

map a sys addr
return paddr

ret

a p0

addr

common

length

checker

GET_SYS_VADDR
arguments

CONSOLE ENTRY AND EXIT ROUTINES

are

Virtual

returns

RO = status
=

(

indicator

= success,

physical address

(0 =

read,

1 = write)

else err)
success

regs

are used

i1in

this

routine

follows

R3
R4

= BOFF (byte offset within page)
= VPN
(virtual page number, or VPN

PTE_Addr)

scratch

address

<1> Read/Write

.entry GET_SYS_VADDR, "m<R3,R¢%, R6%

mov 1l

#err acc _vio,r0

push_mcheck
mcheck
20S$

first

get the byte offset and VPN
extzv
extzv

check

page

#pr$_slr,re
ré,re
20§
#2,r4,r4
|
#prs sbr re
ré6,rd

bgeg

208

(r4) ré

bbc
bisl

$#1,r2,108
#1@26.,(r4)

extzv
rotl
bisl

#0,#21.,r6,rl
$#9.,rl,rl
r3,rl

clrl
r0
pop_mcheck
ret

;

assume failure
any problem

access

violation

;
s

offset

;
;

get
ls

pte

;
;
;
;

error

page

within page

number

range

mfpr
cmpl
bgequ
rotl
mfpr
addl

mov 1l

20S:

#0,49.,rl,r3
#9.,#21.,rl,r4

;
;

;
;
;
;
;

;

length

(in ptes)
the

table?

now 1s offset to pte in table
get sbr base address
got the pte address
and the pte
br 1f valid bit not set.
do we have write intent?
ves, set the Modified bit
get <29:9> of physical address
now is 1n place
and i1s correct physical
address
signal success

ENTRY AND

EXIT

ROUTINES

GET_P0O_VADDR
are

arguments

WS
WS

Virtual

address

<1> Read/Write

indicator

read,

1 = write)

returns

status ( 0 = success, else err)
physical address 1 f success

regs

are used

this

routine

follows

WME

RO
R1

CONSOLE

R3
R4
R6

= BOFF
= VPN
=

(byte offset within page)
(virtual page number, or VPN *

or PTE_ Addr)

scratch

;

clrl
calls

10$:

mov 1l

%S
~
e

number

get

l1s pte
no

the

#prS pOlr,ré6
r4é,reé
208$
#2,r4,r4
#prS pObr,ré6
ro,r4

now translate

mov 1l

access

range

mfpr
cmpl
bgequ
rotl
mfpr
addl

;

offset within page
page

page

check

length
so

(in ptes)
the

table?

error

now 1s offset to pte in
get pObr base address
got the pte address

table

system virtual pte addr to physical

r2,-(sp)

r2
#0,get_sys_vaddr

:
;

(sp)+,r2

;

tstl
bneg
mov 1l
movl

ro0
20S
rl,r4d
(rd),ré6

;
;
;
;

bgeq

208

;

bbc
bisl

$41,r2,10$
#1226.,(r4)

:
;

extzv
rotl
bisl

#0,#21.,r6,rl
#9.,rl,rl
r3,rl

:
:

save r2
say nNo write access
translate the pte address
restore r2
did 1t translate?
no,

return

error

physical address of pQ pte
and the pte
br 1f valid bit not sert.
do we have write intent?
yes, set the Modified bit
get <29:9> of phy addr
now 1s 1n place
and 1s correct physical
address

;

#0,#9.,rl,r3
#9, ,#21,,rl,r4

extzv
extzv

and VPN

the byte offset

any problem

get

failure

violation

first

assume

.entry GET_PO_VADDR, "m<R3,R4,R6>
movl
#err_acc_vio,r0
;
push _mcheck
mcheck
20§

CONSOLE

20S:

clirl

pop_mcheck

; signal success

ret

C-25

ENTRY

AND

EXIT

ROUTINES

Pl VADDR
GET_
are

arguments

WE
s

Virtual

indicator

(0 = read,

1 = write)

RO
R1

status ( 0 = success, else err)
physical address 1f success

used

= BOFF

R4 = VPN
R6

regs

this

routine

follows

(byte offset within page)

(virtual page number,

or VPN * 4,

or PTE_Addr)

scratch

are

returns

address

<1> Read/Write

'CONSOLE ENTRY AND EXIT ROUTINES

.entry GET Pl VADDR,"m<R3,R4,R6>
movl
ferr_acc_vio,r0
;

20S

blssu

ré,ro

$prS _plbr,ré6
re,ré

rotl

#2,r4,r4

addl

mipr

208

cmpl

extzv
#9.,#21.,rl,rd
check page range
mfpr
4prS pllr,ré6

NE Wy

;

first get the byte offset and VPN
extzv
#0,4#9.,rl,r3

;

mcheck

push _mcheck

assume

failure

any problem

violation

1s an access

offset within page
page number

get length (in ptes)
ls pte in the table?
no

error

now is offset

to pte

get plbr base address
got

the pte

1n table

address

+ now translate the system virtual pte addr to phySical
movl

20§:

208

;

r2
#0,get _sys_vaddr
(sp)+,r2
rQ

movl
mov 1l
bgeq
bbc
bisl
extzv
rotl
bisl
clrl

rl,ré
(r4),r6
208
#1,r2,10S
#1@26.,(r4)
40,#21.,r6,rl
#9.,rl,rl
r3,rl
rQ

bneq

10S:

r2,-(sp)

clrl
calls
movl
tstl

pop _mcheck
ret

save

;
;
:
;

Say no write access
translate the pte address
restore r2
did 1t translate?

;
:
;
+
:
:
»
+
+

physical address of pl pte
and the pte
br 1f valid bit not set.
do we have write intent?
yes, set the Modified bit
get <29:9> of physical address
now 1s 1n place
and 1s correct physical address
signal success

no,

return

error

status code to rQ
clrl

done:

return success

-y

ENTRY AND EXIT ROUTINES

exits

CONSOLE

failure

return

err

failure

return

err

ret

acc_vio:

movl

‘ret
nxms

movl
ret

gerr_acc_vio,r0
|

ferr nxm,r0
'

CONSOLE

ENTRY

AND

EXIT

ROUTINES

;

MEMORY

;

arguments

are

4(ap)

;

Physical/Virtual

8(ap)

;

12(ap)

Address

Data

address

read/write

;

<0>

;

Physical/Virtual

<1l>

Read/Write

;

<4:2>

Data
0

err

;

byte

;

word

;

err

;

long

This

;

interface

routine

;

The

;

read

;

returned

RMEMORY

and

does

not

really

the

real

memory

access

routine

does

arguments

4(ap)

8(ap)

;

Data

12(ap)

unchanged

return

read

success

err_acc_vio

mov 1l

mov 1l
calls

10S:

virt)

write)

self,

routine,
IO

only

RMEMCRY.
to

memory

(both

written.

memory, “m<R2,R3,R4,R5>

4(ap),r2

a8(ap),rS

12(ap),r4

bbs

#0, rmemory
#1,r4,103

movl

r5,28(ap)

ret

read,

status

;

.entry

unchanged

;

mov 1

physical,

are

;

much

physical/virtual

write).

length

;

indicator

;

get

Addr

;

get

write

Data

1n case we want

;

get quals

;

now go do the real work
1f write, no need to write
back data
return data

;
;
;

C-28

ENTRY AND EXIT

RMEMORY
arguments

CONSOLE

R2
RS

are

:
s
:
;

Physical/virtual address
Data to read/write
-

<0>
<1l>

Physical/Virtual
(0 = physical,
Read/Write indicator
(0 = read,

<4:2>

Data length
0 = err
1l

= word

1 = virt)
I = write)

byte

3 = err

;
;

long

;
:

This routine does physical/virtual
and write)

;

returned

;
;
;
;
;

return

;

arguments

IO to memory.

(both

read

are

R2
‘unchanged
RS
Data read or written.
R4
unchanged
status
in RO
success
= 0

err_acc_vio

;
;
;
;
;
;
;
:
;
;

register usage while
in this routine....
r0 = status or SCRATCH
r2 = original virtual address
r3 = Physical address to pass to memio or SCRATCH
réd = Qual (original or temporary)
r5 = data to read or write
r6 = DL for total access
r7 = DL for page 2
r8 = data accumulator
r9 = original r5

32S:
31$:
;

are

.entry

rmemory,” m<R2,R3,R4,R6,R7,R8,R9>

movl

rs5,r9

movl
blbs
brw
bbc

r2,r3
r4,31$
30S
#7.,saved_halt, 328

doing

a virtual

1o,

extzv
extzv
decl

#0,#9.,r2,rl
#2,43,r4,r6
rl

addl?2

ro,rl

see

; assume we want phyio
; all ok 1if doing phyio
; br 1f phylo
; 1f mapen off, V is P, ok
we

span
!
»

get
get
——

y
r

C-29

page

now

boundary

low 9 bits of address
data length
1

1s VA<S:0>+DL-1

too.

ROUTINES

bbc

#9.,rl1,208

now have

a virtual

access

bicl3

#~cS511.,rl,r7

incl
calls

r7
#0,probe

tstl
bneq
addl

rd
25$
re,r2
40, probe

;

that

spans

the access is legal to both parts,
seperate Vio's one for each page
subl3
insv
calls
tstl

r7,r6,rl
rl,#2,#3,r4
#0, rmemory
rQ

bneqg

25§

subl3
addl
rotl
subl3.

r7,r6,rl
rl,r2
#3,rl,rl
rl,#32.,rl

rotl
1nsv

rl,r9,r5
r7,#2,#3,r4

calls

30, rmemory

ashl
subl3
ashl
bisl

#3,r7,r3
r3,#32.,r3
r3,r5,r5
r8,rS

r5,r8

tstl

bneqg

WE
HE
NG

save number of bytes on
second page-1
now 1s correct
|
see 1f access 1s legal to
first page
any

errors?

WS
WEH

yes, return the error
now point to last byte
see 1f access 1s legal
last page
put the first Vio addr

now we split

get
set

;

page 1

Vio

any

;

save

;

WS
WS
NS
NS
WH
WS
R

the

the Vio

DL for part
up qual for

now

recurse

yes,

errors?

return

to
back

error

1
the

i1nto

access

to do page one's

the error

the partial data

get DL for part 1 again
point to first byte of part 2
get number of bits 1in part 1
number of bits to left shift
data
r5 1s now data for part
2
set up qual for the access
page 2
now recurse to do page two's
Vio
number of bits in part 2
now number of bits to shift by
shift part two to where it
belongs and set 1n the low
bytes

are done

40 ,probe

simple Vio,

any

25§

translation

a page boundary

return

calls

address

yes,

20S$:

span page boundary

ret

25S$:

branch

errors?

movl

does not

any

r0
255

re,r2

tstl
bneq

subl

calls

HRE

;

ROUTINES

CONSOLE ENTRY AND EXIT

now

do probe

errors?

; ves, return the error
else

now have phyio

to do

: so fall through and do irt.

retS:

calls

mcheck
ret

#0,memio

.external saved_halt

-y

30S:

CONSOLE ENTRY AND EXIT ROUTINES

go do the IO
turn off the trapper

AND

EXIT

ROUTINES

ENTRY

MEMIO
are

Physical

<1>

Read/Write

<4:2>

Data

address

Data

read,
1 =

write)

err

byte
word
word+byte
long

This

routine

does

the

actual

read/write

to physical

memory

returns

RO
R3
R4
RS

=
=
=
=

status ( 0 =
Unchanged

success,

else

err)

Unchanged

Data

s uccess

indicator

1 ength

= LN
O

arguments

CONSOLE

nxm

extzv

#2,43,rd4,rl

#1,r4,100S8

error is
get data
dispatch
go

20S

movw

brw done

RE
ME

write

out

write

out

write
shift
write

out first byte
the data for next
it out

write

err

pushl
movb
rotl

r5
r3
r5,(r3)+
#-8.,r5,rS

pushl

writew
writeW+writeB
writel

movw

r5,(r3)

.~y

30%:

r5,(r3)

err

writeB

popl

r3
rS

popl

brw done
140S:

mov 1l
brw done

r5,(r3)

service

writer

r5,(r3)

brw done

correct

movb

10S

rl,#0,#4
30$-9S
10$-9§
20$-9S
30$-9§
40$-9%
acc_vio

9S:

caseb
.word
.word
.word
.word
.word
brw

nxm
length
to read

bbc

mcheck

MEMIO,O0

.entry

out

part

110$:

1405-1095

acc _vio

err

readB

130$-10S§
110$-109S
120$-109%
1305-109S

rl,#0,#4

caseb
.word
.word
.word
.word
.word
brw

-~y

100S:
109S:

CONSOLE

correct

readw
readW+readB
readlL
err

movzbl
(r3),rS
brw done

read data

1208

movzwl
(r3),rS
brw done

read data

130S:

pushl
movzwl
movzbl
rotl
bisl

popl

(r3)+,r5
(r3),r3

read data

#16.,r3,r3

r3,rS
r3

brw done

140S:

movl
(r3),rS
brw done

.END

read data

ENTRY

reader

AND

EXIT

RCUTINES

APPENDIX

MECHANICAL

'D.1

SPECIFICATIONS

PACKAGING

The MicroVAX 78032 CPU is available
in two
different
packages;
surface
mount
and
socket
mount.
Figures
D-1
and D-2
give
the
mechanical
specifications for these packages.

MECHANICAL

SPECIFICATIONS

MINIMUM CLEAR

LEADFRAME ZONE

800

:m? {

xfimfir~”m

l
cU“*

|
.

—
.020 MIN

.120 MAX

Figure

D-1

Pin CERQUAD,

| 184 maX
V”Un

—

.180 MAX

.030 MIN

MR-128670

Surface

Mount

MECHANICAL SPECIFICATIONS

MINIMUM CLEAR

LEADFRAME ZONE

PIN 1 INDENT

.050

(

|o—

.120 MAX

; .164 MAX

;

m$|

042 MAX

=
>
P

{

ool

010 MIN

MR-12404

Figure D-2

68 Pin CERQUAD, Socket Mount

INDEX

Aborts, 2-45
kernel stack

not valid, 2-53
machine check, 2-53
memory read/write error, 2-53
reserved operand, 2-51
Absolute mode addressing, 3-38
- Absolute queues, 4-83
AC characteristics, A-3
CLKI timing, A-4
CPU read, CPU write, A-5
DMA, A-10
external processor
read/response, A-12
external processor
wrlte/command A-12
reset, A-14
ACBB add compare and branch byte,
4-43
ACBD add compare and branch
D floating, 4-127
ACBF add compare and branch
F floating, 4-127
ACBG add compare and branch
Gfloating, 4-127
|
ACBL add compare and branch long,
4-43
ACBW add compare and branch word
4-43
ADAWI add aligned word
interlocked, 4-6
ADDB add byte, 4-7
ADDD add D floating, 4-129
ADDF add F_floating, 4-129
ADDG add G
_floating, 4-129
ADDL add long, 4-7
Address instructions, 4¢-33

Address strobe (AS),

6-3

add one and
than or equal,
AOBLSS add one and
than, 4-46

Back bias generator (VBB), 6-10
BBC branch on bit clear, 4-49
BBCC branch on bit clear and
clear, 4-50
BBCCI branch on bit clear and
clear interlocked, 4-52
|
BBCS branch on bit clear and set,
4-50
BBS branch on bxt set, 4-4°9
BBSC branch on bit set and clear,
4-50

BBSS branch on bit

set and set,

4-50
BBSSI branch on bit set and set
interlocked, 4-52
BCC branch on carry clear, 4-47
BCS branch on carry set, 4-47
BEQL branch on equal (signed),
4-47
BEQLU branch on equal unsigned,
4-47
BGEQ branch on greater than or

equal

Address translation, 2-28
PO region
Pl region
process space, 2-33
system space, 2-30
Addressing modes, 3-3
ADDW add word, 4-7
ADWC add with carry, 4-8
AOBLEQ

Arithmetic traps/faults, 2-46
'ASHL arithmetic shift long, 4-9
ASHQ arithmetic shift quad, 4-9
- Assembler radix notation, 3-2
AST level (ASTLVL) register, 2-67
Asynchronous system traps (AST),
2-67
Autodecrement mode addressing,
3-15
Autoincrement deferred mode
addressing, 3-13
Autoincrement mode addressing,
3-11

(signed),

4-47

BGEQU

branch on greater than
equal unsigned, 4-47
BGTR branch on greater than

(signed),

BGTRU

branch

less

4-45
branch

less

4-47

branch on greater than
unsigned, 4-47
BICB bit clear byte, 4-10
BICL bit clear long, 4-10
BICPSW bit clear psw, 4-72
BICW bit clear word, 4-10
BISB bit set byte, 4-11
BISL bit set long, 4-11
Index-1

BISPSW bit

set psw,

4-73

BISW
BITB
BITL
BITW
BLBC

bit set word, 4-11
bit test byte, 4-12
bit test long, 4-12
bit test word, 4-12
branch on low bit clear,
4-54
|
*
BLBS branch on low bit set, 4-54
BLEQ branch on less than or equal

(signed),
BLEQU

branch

unsigned,

4-47
less

than or

equal

4-47

BLSS branch on less than (signed),
4-47
BLSSU branch on less than

CHMK
CHMS

change mode
change
¢d-111

mode

kernel,

supervisor,

4-111

CHMU change mode to user, 4-111
CLKI timing, A-4
Clock in (CLKI), 6-10
Clock out (CLKO), 6-10
Clocks, 6-10
CLRB clear byte, 4-13
CLRD clear D _floating, 4-13,
4-131
|
CLRF clear F_floating, 4-13,
4-131
|
CLRG clear G_floating, 4-13,
4-131
CLRL clear long, 4-13
CLRQ clear gquad, 4-13
CLRW clear word, 4-13

unsigned, 4-47
BNEQ branch
on not equal (signed),
4-47
BNEQU branch on not equal
CMPB compare byte, 4-14
unsigned, 4-47
CMPD compare D floating, 4-132
BPT breakpoint fault, 4-74
CMPF compare F_floating, 4-132
Branch addressing, 3-44
CMPG compare G_floating, 4-132
BRB branch with byte displacement,
CMPL compare long, 4-14
4-55
CMPV compare field, 4-36
BRW branch with word displacement, - CMPW compare word, 4-14
4-55
CMPZV compare zero-extended field,
BSBB branch to subroutine with
4-36
byte displacement, 4-56
Console entry protocol, 2-72
BSBW branch to subroutine with
Consocle exit protocol, 2-73
word displacement, 4-56
Console saved registers (SAVISP,
Bus control ‘signals, 6-3
SAVPC, SAVPSL), 2-20
Bus cycles, 5-3
Control instructions, 4-43
CPU read, 5-3
Control status (CS<2:0>), 6-6
CPU write, 5-5
CPU read cycle, 5-3
|
|
DMA, 5-8
CPU read, CPU write cycle timing,
interrupt acknowledge, 5-7
A-5
Bus error handling, 7-4
CPU write cycle, 5-5
BVC branch on overflow clear,
CVTBD convert byte to Dfloating,
4-47
4-133
BVS

branch

overflow

- Byte masks (BM<3:0>),

set,

6-4

4-47

CALLG call procedure with general
argument list, 4-66
CALLS call procedure with stack
argument list, 4-68
CASEB case byte, 4-57
CASEL case long, 4-57
CASEW

case

word,

Character string
4-106
CHME change mode
4-111

¢-57

instructions,
to executive,

CVTBF convert
4-133

byte

F_floating,

CVTBG

convert
-133

byte

G_floating,

CVTBL

convert byte to long,
convert byte to word,
convert D floating to
-133

CVTBW
CVTDB

4-15

4-15
byte,

CVTDF convert D flocating
F floating, 4-133

CVTDL convert
4-133

D _floating

long,
|

CVTDW convert
4-133

D floatlng

word,

Index-2

INDEX

variable length bit field, 2-4

CVTFB convert F_floating to byte,
4-133

CVTFD convert F float1ng
D floating, T4-133
CVTFG convert F_floating
G floating, 4-133
CVTFL convert F_floating
4-133
|

to
:
to’long,

word, 2-2

Data/address bus, 6-3
DC characteristics, A-1
DECB decrement byte, 4-16
DECL decrement long, 4-16
DECW decrement word, 4-16
Displacement deferred mode

CVTFW convert F_floating to word,
4-133

CVTGB convert G _floating to byte,
4-133

addressing, 3-24
Displacement mode addressing,
3-22
divide byte,

&4-17
divide D floating,
divide F_floating,
divide G
_floating,

CVTGF convert G _floating to
F floating, T 4-133
CVTGL convert G _floating to long,

DIVB
DIVD
DIVF
DIVG

CVTGW convert Gmflmating to word,
4-133
CVTLB convert long to byte, 4-15
CVTLD convert long to D_floating,

DIVW divide word, 4-17
DMA control signals, 6-9
DMA cycle, 5-8
DMA cycle timing, A-10

4-133

|
4-133
F_floating,
CVTLF convert long to

DIVL divide

long,

4-17

4-136
4-136
4-136

DMA grant (DMG), 6-9
DMA request (Ufifi) 6-9

4-133

long to G_floating,
4-133
|
|
word, 4-15
to
long
convert
CVTLW
CVTRDL convert rounded Dfloating
CVTLG convert

to long, 4-133

CVTRFL convert rounded F_floating

to long, %-133

CVTRGL convert rounded G _floating
to long, 4-133
|
CVTWB convert word to byte, 4-15
CVTWD convert word to D_floating,

4-133

CVTWF convert word to F_floating,
4-133
|
CVTWG convert word to G_floating,
4-133
CVTWL convert word to long, 4-15

DAL<31:00>,
Data buffer
Data strobe
Data types,

6-3
enable (DBE),
(DS), 6-4
2-1
byte, 2-2
,
character string, 2-5

EDIV extended divide, 4-1°9
EMODD extended multiply and
integerize D floating, 4-138

EMODF extended multiply and
integerize F_floating,

EMODG extended multiply and

4-138

integerize G_floating, 4-138
EMUL extended multlply, 4-20
Emulated instructions with
microcode assist, 4-151

Error (ERR), 6-5

Exceptions, 2-44
access control violation fault,
2-50
breakpoint fault, 2-52
emulated instruction fault,

|
6-5

2-51

extended function fault, 2-52
floating divide by zero fault,
2-48
floating overflow fault, 2-48
floating underflow fault, 2-48
integer divide by zero trap,

2-47
integer overflow trap, 2-47
interrupt stack not valid halt,

floating point, 2-7
D floating, 2-8
F_floating, 2-7

|
2-53
kernel stack not wvalid abort,
2-53

G floating, 2-9
longword, 2-3
quadword, 2-4

Index-3

INDEX

machine check and memory
read/write error abort,
2-53
reserved addressing mode fault,
2-51
|
|
reserved

operand

exception,

2-51
reserved/privileged

‘
instruction

fault, 2-51
subscript range trap, 2-48
translation not valid fault,
2-50
Exceptions and interrupts, 2-39
contrast

between,

initiation of,
processor

serialization of,

2-57

Halt

EXTZV

extract

4-38

Faults,
access

2-45

4-38

zero-extended

control

extended
floating
floating
floating

field,

2-46
violation

2-50
breakpoint, 2-52
emulated instruction,
function,
divide by

(ACV),

2-51
2-52
zero, 2-48

(HALT),

4-124

with,

5-15

addressing,

3-6

3-35

3-6

6-9

6-6

HALT halt instruction,
Halting the processor,

A-12

field,

numbers,

counter,

(VSS),

(TNV),

clear, 4-40
set, 4-40
accuracy, 4-125
instructions,

5-15

timing,

extract

mode

4-75
7-3

Immediate mode addressing,
INCB increment byte, 4-21
INCL increment long, 4-21
INCW increment word, 4-21

INDEX

compute

2-51

instruction,

valid

communicating

Ground

Exteigii processor strobe (EPS),
Exte?ggl processor~write cycle,
Exte?gii processor write/command
cycle

FPU,

program

register protocol, 5-15
External processor read cycle,
5-9
|
External processor read/response
cycle timing, A-12
External processor registers,
reading and writing, 5-15
External processor response cycle,

EXTV

not

2-50
FFC find first
FFS find first
Floating point
Floating point
4-124
Floating point

General

5-9
read cycle, 5-9
response cycle, 5-11
write cycle, 5-11
External processor protocols,
5-15
protocol,

2-51

translation

mode,

2-51

reserved/privileged

2-40

Executive mode, 2-26
External processor cycles,

FPU

addressing
operand,

2-56

2-57

status,

reserved
reserved

index,

3-36

4-76

Index mode addressing, 3-26
INSQHI insert entry into queue

at
head, interlocked, 4-90
INSQTI insert entry into queue at
tail, interlocked, 4-93
INSQUE insert entry in queue,
4-96
Instruction descriptions, 4-2
Instruction execution exceptions,
2-51
Instruction format, 3-1
Instruction set summary, B-1
INSV 1nsert field, 4-42

Integer arithmetic and
~
1nstructions, 4-6

logical

Interrupt

acknowledge

Interrupt

control

Interrupt
Interrupt

handling, 7-5
priority level

(IPL),

Interrupt

2-43

request

Interrupts,

cycle,

signals,

(IRQ<3:0>),

2-40

control of, 2-42
device interrupts, 2-41
software interrupts, 2-%1

overflow, 2-48
underflow, 2-48
Index-4

5-7

6-8

" INDEX
urgent interrupts, 2-41
Interrupts, hardware, 7-5

MOVAB

general (IRQ<3:0>), 7-6
interval timer, 7-5

JMP
JSB

jump, 4-59
jump to subroutine,

6-8

4-60

'LDPCTX load process context,
4-115

Literal mode addressing, 3-17
Map enable register
MCOMB move
4-22

byte, 4-33
D floating,

(MAPEN),

move

4-33
MOVAG move
4-33

address

F_floating,

2-24

complemented byte,
'

MCOML move complemented long,
4-22
MCOMW move complemented word,
4-22
|
Mechanical specifications, D-1
Memory access protocol, 5-13
Memory management, 2-21
access control, 2-25
address translation, 2-28
faults, 2-38
memory mapping enable, 2-24
page protection, 2-26
translation buffer, 2-36
violations, 2-28
access, 2-28
length, 2-28
Memory management exceptions,
2-48
fault parameter block, 2-48
Memory subsystem, 7-3
Microcycle, 5-1
|
MME bit, 2-24
MNEGB move negated byte, 4-23
MNEGD move negated D floating,
4-140
MNEGF move negated F_floating,

move address long, 4-33
MOVAQ move address quad, 4-33
MOVAW move address word, 4-33
MOVB move byte, 4-24
MOVC move character, 4-107
MOVD move D_floating, 4-141
MOVF move F _floating, 4-141
MOVG move G _floating, 4-141
MOVL move long, 4-24
MOVPSL move from psl, 4-78
MOVQ move quad, 4-24
MOVW move word, 4-24
MOVZBL move zero-extended byte
long, 4-25
MOVZBW move zero-extended byte
word, 4-25
MOVZWL move zero-extended word
long, 4-25

MULB
MULD
MULF
MULG
MULL
MULW
NOP

multiply byte, 4-26
multiply D floating,
multiply F _floating,
multiply G_floating,
multiply long, 4-26
multiply word, 4-26
no operation,

4-140
MNEGL move
MNEGW move

negated long,
negated word,

4-79

P0 base register (POBR), 2-33
PO length register (POLR), 2-33
Pl base register (PlBR), 2-34
Pl length register (PLLR), 2-34
Packaging
socket

negated G_floating,

4-142
4-142
4-142

OPcode format, 3-2
Operand reference exceptions,
2-51
Operand specifier notation, 4-2
Operands, types of, 3-3
Operating system support
instructions, 4-111

4-140

MNEGG move

4-23
4-23

address G_floating,

MOVAL

Kernel made, 2-26

Machine check, 2-53

address
address

1-33
MOVAF

powerfail, 7-5
Interval clock control and status
register (ICCS), 2+19

Interval timer (TNTTTH)

move

MOVAD move

mount,

D-3

surface mount, D-1
Page table entry (PTE), 2-29
making changes to, 2-30
Pin summary, 6-11
Index-5

to
to
to

INDEX

POLYD polynomial evaluation
D floating, 4-144
PCLYF polynomial evaluation
F_floating, 4-144
POLYG polynomial evaluation
G_floating, 4-144
POPR pop registers, 4-80
Power, 6-9, 7-1
Power (VDD), 6-9

Power

fail

(PWRFL),

general,

2-10
argument pointer,

frame

program

stack

context,

Process

space,

structure,

Process

structure

counter,
status

6-8

process

control

status

(PSL),
system

2-14

control

return

from

2-68
Processor
levels (IPL), 2-39
Processor modes, 2-26
executive
kernel

base

2-12

exception

REMQHI

remove

head,
REMQTI

entry

remove

tail,
REMQUE

entry

remove

entry

Processor registers, 2-16
MicroVAX 78032 specific, 2-19
Processor status longword (PSL),
2-14
Processor status word (PSW), 2-11
PUSHAB push address byte, 4-34
PUSHAD push address D floating,
4-34
PUSHAF push address F_floating,
4-34
PUSHAG push address G_floating,
4-34
PUSHAL push address long, 4-34
PUSHAQ push address quad, 4-34
PUSHAW push address word, 4-34
PUSHL push long, 4-27
PUSHR push registers, 4-81

(RESET),

gqueue,

6-6

codes, 2-72
process, 2-71
restart codes, 2-72
RET return from procedure,

Restart

ROTL
RSB

rotate
return

long,
from

4-70

4-28

subroutine,

4-61

Saved interrupt stack pointer
register (SAVISP), 2-20, 2-71
Saved processor status longword
register (SAVPSL), 2-20, 2-71
Saved program counter register

(SAVPC),

SBWC

2-20,

subtract
Self-relative

SCBGEQ
SOBGTR

2-71

with carry, 4-29
queues, 4-87

subtract

one

than

subtract

greater

Restart

greater

4-83

4-101

from

4-104

Reset timing, A-14
Reset/power-up, 7-2

gqueue

4-98

from queue

interlocked,

Reset

6-5

from

1interlocked,

supervisor

(RDY),

longword

block

user

Ready

base

2-12

(SCBB),

block

(PCBB),

2-14
2-14

interrupt, 4-113
Relative deferred mode addressing,
3-42
Relative mode addressing, 3-40

2-63
interrupts,
|
interrupt priority

1instructions,

2-11

word,

control,
for memory management,

2-22

Queue

2-10

system, 2-12
for interrupt

2-63

Process

2-10

pointer,

processor

Power supply decoupling, 7-1
PROBER probe read accessibility,
4-121
PROBEW probe write accessibility,
4-121
Procedure CALL instructions, 1-64
Process

pointer,

one

than,

and

branch

equal,

and

4-63

Software interrupt request
register (SISR), 2-42
Software interrupt summary
register (SISR), 2-42
Stack registers, access of,

Index-6

4-62

branch

2-70 -

INDEX

Stacks, 2-68
alignment,
residency,

2-69
2-68
selection, 2-69
status, 2-69
SUBB subtract byte,

4-30
SUBD subtract D floating,
SUBF subtract F_floating,
SUBG subtract G_floating,
SUBL subtract long, 4-30
SUBW subtract word, 4-30
Supervisor mode, 2-26
Supplies, power, 6-9
SVPCTX save
4-117

process

System base register

(SBR),
2-61

System control block base
2-61

User

context,

System control block,
register,

4-148
4-148
4-148

2-30

(scbb)

System control signals, 6-6
System failure exceptions, 2-53
System length register (SLR),
2-30

System space,

Translation buffer invalidate
single register (TBIS), 2-37
Traps, 2-44, 2-46
integer divide by zero, 2-47
integer overflow, 2-47
subscript range, 2-48
TSTB test byte, 4-31
TSTD test D floating, 4-150
TSTF test F _floating, 4-150
TSTG test G_floating, 4-150
TSTL test long, 4-31
TSTW test word, 4-31

2-23

Translation buffer invalidate all
register (TBIA), 2-37

Index-7

2-26

Variable length bit field
instructions, 4-35
Vectors,
2-61
Virtual address, 2-23
Virtual address space, 2-22
Virtual address, the translation
of, 2- 28

Write

Test (TEST), 6-10
Tracing, 2-52

mode,

(WR),

6-5

XFC extended function call, 4-82
XORB exclusive OR byte, 1-32
XORL exclusive OR long, 4-32
XORW exclusive OR word, 4-32