MicroVAX 78032 32-Bit Central Processing Unit User's Guide

This document is a Preliminary User's Guide for the MicroVAX 78032 32-Bit Central Processing Unit (CPU), produced by Digital (DIGITAL). It aims to familiarize readers, particularly those with experience in microprocessor and VAX architecture, with the hardware and software characteristics of this single-chip microprocessor.

The guide covers:

• Introduction and Functional Overview (Chapter 1): Provides a general description of the MicroVAX 78032 CPU, highlighting its key features such as VAX-11 compatibility, 4 Gbyte virtual and 1 Gbyte physical address space, 32-bit internal/external data paths, high performance, on-chip memory management, clock generation, interrupt control, and a simple external interface.

• Architecture (Chapter 2): Details the implementation of the VAX architecture by the MicroVAX 78032 CPU. This includes:

  • Data Types: Descriptions of byte, word, longword, quadword, variable length bit fields, character strings, and floating-point types (Ffloating, Dfloating, G_floating, supported by the MicroVAX 78132 Floating Point Unit).
  • Registers: Explanation of non-privileged registers (general purpose, Processor Status Word) and privileged system registers (e.g., System Control Block Base, Process Control Block Base, Interrupt Registers, Memory Management Registers, Processor Status Longword).
  • Memory Management: Comprehensive details on virtual address space, demand-paged virtual memory, page protection, address translation (Page Table Entries, Translation Buffer), and associated faults (access control violation, translation not valid, length violation).
  • Exceptions and Interrupts: Differentiates between exceptions and interrupts, outlines interrupt priority levels (IPLs), and describes various types of traps, faults, and system failure exceptions.
  • Process Structure: Covers process context, asynchronous system traps (ASTs), and process structure interrupts.
  • Stacks: Explains stack residency, alignment, and how stack pointers are managed.
  • Restart Process: Describes the CPU's reinitialization procedure.

• Instruction Format and Addressing Modes (Chapter 3): Provides a detailed description of the variable-length instruction formats and the various addressing modes used by the MicroVAX 78032 CPU, including general register modes, program counter addressing, immediate, literal, displacement, and index modes, along with their deferred and relative variations.

• Instruction Set (Chapter 4): Presents the full instruction set, categorizing them by function (integer arithmetic/logical, address, bit field, control, procedure call, miscellaneous, queue, character string, operating system support, and floating point). It clarifies which instructions are implemented in hardware on the CPU (175), by the companion FPU (70), and which are supported via software emulation (with microcode assist).
• Bus Transactions (Chapter 5): Details the bus cycles used by the MicroVAX 78032 CPU for communication (CPU read/write, interrupt acknowledge, DMA, external processor cycles) and the protocols involved.
• Pin Description (Chapter 6): Describes the function of each pin on the MicroVAX 78032 CPU, grouped by their roles (Data/Address bus, bus control, system control, interrupt control, DMA control, power supply, clocks, and test).
• Interfacing (Chapter 7): Offers introductory information and guidelines for interfacing external logic to the MicroVAX 78032 CPU, focusing on power, reset/power-up, halting the processor, memory subsystem, bus errors, and interrupts.

Additionally, the document includes Appendices with DC and AC electrical characteristics, detailed timing information, a comprehensive instruction set summary, sample console entry and exit routines written in VAX-11 Macro, and mechanical specifications for the CPU's packaging.