Digital PDFs

XX-F2408-3E

February 1975

104 pages

Original

3.3MB

Document:	PDP11 Arch Enhance Strategy
Order Number:	XX-F2408-3E
Revision:
Pages:	104
Original Filename:	PDP11_Arch_Enhance_Strategy_75.pdf

OCR Text

E MEMORANDUM
TO:

DATE:

DISTRIBUTION

February 1 3 , 1975

FROM: Dave Nelson
DEPT:

11 P l a n n i n g / A r c h i t e c t u r e

EXT: 4 5 0 9
SUBJ:

LOC:

8-5%

ML5/ 6 7

PROPOSAL FOR PDP-11 1/0 ARCHITECTURE

I p r o p o s e t h a t t h e a t t a c h e d s p e c i f i c a t i o n be a d o p t e d i n f u t u r e i m
t a t i o n s of t h e PDP-11 a r c h i t e c t u r e .

For background i n f o r m a t i o n , r e f e r e n c e i s made t o S e c t i o n I ( I / O Systems)
and S e c t i o n I1 ( I n t e r r u p t System) o f t h e 1/22/75 v e r s i o n of t h e PDP-11
A r c h i t e c t u r a l Enhancement S t r a t e g y p u b l i c a t i o n .

Many d i s c u s s i o n s have been h e l d w i t h p e o p l e i n Software E n g i n e e r i n g ,
P e r i p h e r a l E n g i n e e r i n g , Micro P r o d u c t s , Communications E n g i n e e r i n g ,
Hardware E n g i n e e r i n g , and R/D, a l l o f whom have c o n t r i b u t e d i n v a r i o u s
ways.
The a t t a c h e d document a p p e a r s somewhat r e v o l u t i o n a r y i n t h a t some new
t e r m i n o l o g y i s i n t r o d u c e d . I believe, however, t h a t t h i s t e r m i n o l o g y
i s n e c e s s a r y i f w e wish t o realize t h e f u l l p o t e n t i a l o f t h e approach
and a v o i d some of t h e p a s t m i s t a k e s .
I ' d a p p r e c i a t e w h a t e v e r comments you have, and I ' l l be h o l d i n g some de-

s i g n review s e s s i o n s s h o r t l y .
Regards.
DN:elb
D I S T R I R UT I ON

P h i l Arnold
Jega Arulpragasam
Vince B a s t i a n i
Gordon B e l l i
Jim Bell
Ron Brender
J.ack Burness
Roger Cady
Dick C l a y t o n
S k i p Coombe
Dave C u t l e r
Bruce D e l a g i
B i l l Demmer

Tom Fava
Robin F r i t h
Lorrin G a l e
Mike Garry
Andy G o l d s t e i n
John Holman
John Hughes
Chuck Kaman
J u l i u s Marcus
Craig Mudge
Clay N e i l
J i m O'Loughlin
Ralph P l a t z

Larry P o r t n e r
Bob P u f f e r

Maurice Richeson
A 1 Ryder

G r a n t Saviers
B i l l Strecker
S t e v e Teicher

Nate T e i c h h o l t z
Mike T o m a s i c
Pete van Roekens
L a r r y Wade
S t u Wecker
G a r t h Wolfendale

PDP-11 I / O PHILOSOPHY

Some d i s c u s s i o n r e g a r d i n g t h e p h i l o s o p h y and i n t e n d e d d i r e c t i o n of
t h e PDP-11 i s w a r r a n t e d as an i n t r o d u c t i o n t o t h e proposed c o n c e p t s
and t h e i r m o t i v a t i o n s .

With t h e i n t r o d u c t i o n o f t h e 11/70 and ll/Q machines, t h e PDP-11 a r c h i t e c t u r e w i l l s p a n a greater performance r a n g e t h a n any o t h e r computer,
w i t h t h e p o s s i b l e e x c e p t i o n of t h e IBM 3 6 0 . However, t h i s performance
r a n g e i s p r i m a r i l y r e s t r i c t e d t o t h e i n s t r u c t i o n set a r c h i t e c t u r e .
The 1/0 a r c h i t e c t u r e i s so d i r e c t l y c o u p l e d t o t h e p h y s i c a l e x i s t e n c e
of t h e U N I B U S , b o t h e x t r e m e s o f t h e performance r a n g e have had t o make
compromises.
I t i s t h e r e f o r e a goal of t h i s proposal t o introduce
c o n c e p t s i n t o t h e PDP-11 1/0 s t r u c t u r e t h a t :
1. r e l y , t o a lesser d e g r e e , on t h e UNIBUS; and
2 . are amenable t o a b r o a d e r performance r a n g e f o r

( a ) low-performance I / O
( b ) high-performance

f o r micro-11s

1/0 f o r large 11s

The f o l l o w i n g diagram i n t u i t i v e l y c h a r a c t e r i z e s some of t h e i n t e n t s
of t h i s p r o p o s a l ; namely, t o d e r i v e a machine s t r u c t u r e which i s cond u c i v e t o a l l p o s s i b l e p a t h s shown.

PROCESS,
PDP
/f

INTERRUPT

\/o
I

MOTIVATION

T h i s p r o p o s a l i n t e n d s t o p r o v i d e a c o n s i s t e n t and comprehensive approach
t o t h e f o l l o w i n g areas:

F a s t Machine C o n t e x t S w i t c h i n g
A mechanism i s p r o v i d e d t h a t r a p i d l y s a v e s and restores

machine r e g i s t e r s when a p r o c e s s i s s w i t c h e d .
2.

Higher 1/0 Performance
The a r c h i t e c t u r e is more conducive t o d e s i g n i n g s e l f o p t i m i z i n g 1/0 s y s t e m s t h a t i n c r e a s e high-end performance
and b e t t e r manage UNIBUS bandwidth.

Low 1/0 C a p a b i l i t y
The a r c h i t e c t u r e w i l l a l l o w u s t o d e v e l o p l o w c o s t 1/0

s y s t e m s f o r NON-UNIBUS l o w end 11s.
4.

CPU Microcode 1/0
Higher performance a t lower cost i s a t t a i n a b l e f o r comm u n i c a t i o n s and i n t e r m e d i a t e s p e e d p e r i p h e r a l s , by
u t i l i z i n g c e n t r a l p r o c e s s i n g resources f o r I / O f u n c t i o n s .

1/0 Page and Trap Vector Space
T h e 1/0 p a g e , now f u l l y o c c u p i e d , w i l l c o n t a i n d e s c r i p t o r
r e g i s t e r s which " f l o a t " i n t h e a d d r e s s s p a c e . Device r e g i s t e r i n f o r m a t i o n w i l l be a c c e s s e d t h r o u g h memory l o c a t i o n s ,

and t h e t r a p v e c t o r s w i l l b e program a s s i g n e d .

OVERVIEW

The c o n c e p t of a process i s i n t r o d u c e d t o d e s c r i b e b o t h PDP-11 programs and 1/0 f u n c t i o n s . Processes are u n i q u e l y d e f i n e d by 32 b i t

p r o c e s s d e s c r i p t o r s which, i n t u r n , are l o c a t e d i n memory s p a c e by
1 6 b i t p r o c e s s numbers.
' -

Processes are d e f i n e d t o be p r o c e d u r e s w i t h c o n t e x t which serves t o
d i s t i n g u i s h between t h e d e s c r i p t i v e i n f o r m a t i o n ( c o n t e x t ) needed t o
c h a r a c t e r i z e t h e p r o c e s s , and t h e p r o c e d u r a l i n f o r m a t i o n ( a c t u a l
mechanism, such as CPU, microcode, c o n t r o l l e r , 1/0 p r o c e s s o r , e t c . )
r e q u i r e d t o c a r r y o u t t h e p r o c e s s . S p e c i f i c a l l y , w i t h r e g a r d t o I/O,
the architecture requires software t o e s t a b l i s h only the descriptive
i n f o r m a t i o n , and t h u s i s a b l e t o accomodate wide v a r i a n t s i n t h e act u a l mechanisms and implementation t e c h n i q u e s t h a t perform t h e 1/0
function.

I n terms of c u r r e n t PDP-11 d e f i n i t i o n s , t h e p r o c e s s d e s c r i p t o r i s a
g e n e r a l i z a t i o n of t h e Program S t a t u s word and Program Counter. The
p r o c e s s number f o r i n t e r r u p t s e r v i c e r o u t i n e s i s a g e n e r a l i z a t i o n
of t h e t r a p v e c t o r a d d r e s s . PDP-11 c o n t e x t i s t h e g e n e r a l r e g i s t e r s ,
KT map, e t c . , and 1/0 c o n t e x t i s c o n t a i n e d i n t h e CSRs l o c a t e d i n t h e
I / O page.

PROCESS DESCRIPTOR FORMAT
The 3 2 bit Process Descriptor has the following format:

TYPE

FUNC

STATUS

LOC

TYPE ( 2 bits) - Process Type
00,01,10
11
FUNC ( 3 bits)

- PDP-11 process (Kernel, User, Spvr.)
- I/O process

- Function

-- previous mode and register select for PDP-11
processes

-- function code for 1/0 processes
E (1 bit)

- Extended Context

-- used to select interpretations of LOC
STATUS ( 8 bits)

-- priority level and condition codes for PDP-11
processes

-- word count for non-extended 1/0 processes

-- status bits for.extended 1/0 processes
LOC (16 bits)

- Address Location

-- Program counter (virtual Kernel space) for
non-extended PDP-11 processes

-- Location of context block for extended PDP-11
processes

-- Buffer Address (physical) for non-extended 1/0
processes

-- Location of context block for extended 1/0 processes

CONTEXT BLOCKS
For e x t e n d e d P D P - 1 1 p r o c e s s e s , t h e c o n t e x t block has t h e f o r m a t :
( P R E V I O U S MAP)

- address of p r e v i o u s KT-11 r e g i s t e r image

( C U R R E N T MAP)

- address of c u r r e n t KT-11 r e g i s t e r image
( i f zero, a u t o l o a d i n g is s u p p r e s s e d )

RO-R6
PC

- general registers
- program c o u n t e r
( v i r t u a l K e r n e l space)

For e x t e n d e d I / Q p r o c e s s e s , t h e c o n t e x t block h a s t h e f o r m a t :
PLINK

- p r o c e s s number o f n e x t p r o c e s s
(normally t h e t r a p v e c t o r address)

DEVCTX - d e v i c e c o n t e x t (word c o u n t , b u f f e r address, e t c . )

PROCESS NUMBERS

S i n c e Process D e s c r i p t o r s r e s i d e i n memory a d d r e s s s p a c e , one can
c o n s i d e r t h i s s p a c e an enormous Process D e s c r i p t o r Table, whereby
t h e l o c a t i o n of a l l d e s c r i p t o r s i s s p e c i f i e d by a 1 6 b i t i n d e x c a l l e d
t h e p r o c e s s number. Processes are invoked by t h r e e d i s t i n c t mechan-

isms:
1.

An 1/0 p r o c e s s D e s c r i p t o r , l o c a t e d i n t h e 1/0 page, is

invoked by CPU s e t t i n g r e g i s t e r b i t s . The p r o c e s s numb e r i s t h e address of device r e g i s t e r ( P D ) .
2.

o r a n 1/0 Process D e s c r i p t o r , l o c a t e d i n l o w
c o r e ( t r a p vector s p a c e ) , i s invoked by an i n t e r r u p t req u e s t v i a t h e UNIBUS. The p r o c e s s number i s t h e t r a p
vector address.

A PDP-11 p r o c e s s ( p o s s i b l y an 1/0 p r o c e s s on f u t u r e ma-

A PDP-11

c h i n e s ) , located i n program a r e a , i s invoked a t software
l e v e l by e x e c u t i o n of an R T I .
The p r o c e s s number i s i n
R 6 , and t h e p r o c e s s d e s c r i p t o r i s on t o p of t h e s t a c k .
The l o c a t i o n of process d e s c r i p t o r s i s t h e r e f o r e c o r r e l a t e d t o t h e
mechanism t h a t carries o u t t h e p r o c e s s . For example, 1/0 p r o c e s s e s
can e i t h e r b e performed by e x t e r n a l c o n t r o l l e r s ( i n which case t h e y
r e s i d e i n 1/0 p a g e ) , o r t h e y can b e performed by CPU microcode ( i n
which case t h e y r e s i d e i n t r a p v e c t o r a d d r e s s s p a c e ) .

1/0 Process D e s c r i p t o r s f o r e x t e r n a l l y c o n t r o l l e d
processes

PDP Process D e s c r i p t o r s f o r s o f t w a r e l e v e l p r o c e s -

SPACE
VECTORS

ses
PDP and 1/0 P r o c e s s D e s c r i p t o r s f o r CPU c o n t r o l l e d

processes

LINKED PROCESSES
I n g e n e r a l , processes are l i n k e d t o g e t h e r i n a series of l i s t s whereby p r o c e s s e s i n any g i v e n l i s t are performed s e r i a l l y .
This e n s u r e s
o r t h o g o n a l i t y among p r o c e s s e s t h a t comprise a l i s t , and s e r v e s t o res o l v e d a t a c o n t e n t i o n and s y n c h r o n i z a t i o n problems d i s c u s s e d l a t e r .
The l i s t s t r u c t u r e o n l y a p p l i e s t o 1/0 p r o c e s s e s and i s c h a r a c t e r i z e d by t h e f o l l o w i n g :

-- f o r e x t e n d e d c o n t e x t p r o c e s s e s , t h e f i r s t l o c a t i o n i n t h e
c o n t e x t b l o c k c o n t a i n s t h e p r o c e s s number f o r t h e following process.

-- f o r non-extended c o n t e x t p r o c e s s e s , t h e p r o c e s s number f o r
t h e following process i s the current process plus four
( 4 bytes)

\
.-

000 0 0

HARDW~RE
C€SSOR 5

QROC€sS

1/0 PROCESS FOR AN EXTERNAL DEVICE/CONTROLLER

Process D e s c r i p t o r s f o r e x t e r n a l d e v i c e s r e s i d e i n t h e 1/0 page.
F o r t h e e x t e n d e d c o n t e x t case (normal f o r e x t e r n a l d e v i c e s ) , t h e
d e s c r i p t o r c o n t a i n s t h e a d d r e s s o f t h e c o n t e x t b l o c k which c o n t a i n s
t h e d e v i c e r e g i s t e r s ( a d d r e s s , c o u n t , e t c . ) and t h e n e x t ( l i n k e d )
p r o c e s s number. The l i n k e d p r o c e s s number w i l l n o r m a l l y b e t h e t r a p
v e c t o r a d d r e s s which locates t h e p r o c e s s d e s c r i p t o r ( P s , P c ) of t h e
i n t e r r u p t service r o u t i n e .

PDP-11

Interrupt
I

Process

I n t h i s s p e c i f i c case, t h e i n i t i a t i n g PDP-11 r o u t i n e would invoke t h e
1/0 p r o c e s s by i n i t i a t i n g t h e p r o c e s s d e s c r i p t o r l o c a t e d i n t h e 1/0
page ( s i m i l a r t o c u r r e n t a p p r o a c h ) . The 1/0 process, once i n i t i a t e d ,
c o n t i n u e s u n t i l t h e 1/0 i s t e r m i n a t e d , a t w h i c h p o i n t i t asserts t h e
p r o c e s s number ( t r a p a d d r e s s ) o f t h e i n t e r r u p t s e r v i c e r o u t i n e on t h e
CPU.
I t s h o u l d b e n o t e d t h a t a s i m i l a r 1/0 p r o c e s s d e s c r i p t o r c o u l d
r e s i d e down i n t h e t r a p v e c t o r s p a c e and o p e r a t e under c o n t r o l of
CPU microcode i n a manner e q u i v a l e n t t o 1/0 p r o c e s s e s o p e r a t i n g under
c o n t r o l of e x t e r n a l d e v i c e c o n t r o l l e r s .

1/0 PROCESS CONTROLLED BY CPU MICROCODE

Many b l o c k t r a n s f e r d e v i c e s , such as a f l o p p y d i s k , may have c o n t r o l l e r s which, due t o c o s t , are d e s i g n e d t o i n t e r r u p t on a per-word
b a s i s , e a c h i n t e r r u p t p e r f o r m i n g t h e d a t a s t o r a g e and memory i n c r e ment. O t h e r d e v i c e s , p r i m a r i l y communication d e v i c e s , a r e r e q u i r e d
t o i n t e r r u p t on a p e r - c h a r a c t e r b a s i s i n o r d e r t o manage message prot o c o l s , c o n t r o l characters, b u f f e r management, e t c .
T h e c u r r e n t p r a c t i c e of i n t e r r u p t i n g t h e CPU f o r these r e l a t i v e l y
t r i v i a l r e a s o n s causes u n a c c e p t a b l e b u r d e n s on t h e CPU a n d , conseq u e n t l y , u n a c c e p t a b l e levels of performance. I t i s t h e p u r p o s e of
t h i s p r o p o s a l t o d e f i n e t h e a r c h i t e c t u r a l r e l a t i o n s h i p s between those
f u n c t i o n s t h a t can b e done more e f f i c i e n t l y by CPU microcode and
t h o s e f u n c t i o n s which r e q u i r e PDP-11 i n t e r r u p t s e r v i c e r o u t i n e s .

The p r o c e s s - s t r u c t u r e d a r c h i t e c t u r e d i s c u s s e d h e r e i n p r o v i d e s an i n t e g r a t e d approach t o a l l 1/0 p r o c e s s e s , r e g a r d l e s s of w h e t h e r t h e y
are implemented by CPU microcode o r an e x t e r n a l c o n t r o l l e r .
Further,
t h e d e s c r i p t o r s f o r a l l CPU f u n c t i o n s are of t h e same form, r e g a r d less of w h e t h e r t h e y a r e PDP-11 p r o c e s s e s o r 1/0 f u n c t i o n s .
For CPU-controlled 1/0 f u n c t i o n s , w e w i l l , i n g e n e r a l , have t h e f o l -

lowing e v e n t s :

I n i t i a t i n g PDP-11 r o u t i n e s t a r t s t h e device.

The d e v i c e t r a n s f e r s d a t a (1 word o r c h a r a c t e r ) and
g e n e r a t e s an i n t e r r u p t r e q u e s t t o t h e CPU.

The CPU h a n d l e s t h e r e q u e s t i n microcode l o g i c , s t o r e s
t h e d a t a i n memory, and d e t e r m i n e s i f a PDP-11 s e r v i c e

r o u t i n e is r e q u i r e d (word c o u n t e x p i r e s , s p e c i a l c h a r a c ter, etc.).
4.

The CPU e x e c u t e s a PDP-11 i n t e r r u p t s e r v i c e r o u t i n e when
conditions require.

Initiating

,Address

of p r o c e s s d e s c r i p t o r i n 1/0 page

PDP-11

Process

Unibus t r a p v e c t o r
Trap a d d r e s s of ISR

PDP-11 AUTO CONTEXT SWITCH

t y p e p r o c e s s d e s c r i p t o r s can be i n t h e e x t e n d e d c o n t e x t f o r m a t
i n which t h e l o w o r d e r 1 6 b i t s c o n t a i n s t h e v i r t u a l a d d r e s s i n K e r n e l
space of t h e p r o c e s s e s c o n t e x t block.
C o n t e x t s w i t c h e s f o r t h e s e processes a r e performed a u t o m a t i c a l l y by t h e CPU, and can b e invoked by
e i t h e r (1) t h e a s s e r t i o n of an i n t e r r u p t by a d e v i c e , o r ( 2 ) t h e exe c u t i o n of an R T I i n s t r u c t i o n ( u s e d f o r t a s k s c h e d u l i n g , as w e l l as
interrupt dismissal).

PDP-11

PDP-11 c o n t e x t c o n s i s t s o f a l l e i g h t g e n e r a l r e g i s t e r s and t h e s e t
of KT-11 map r e g i s t e r s whose a d d r e s s i s l o c a t e d i n t h e c o n t e x t b l o c k

( a u t o l o a d i n g of map r e g i s t e r s can b e s u p p r e s s e d by s p e c i f y i n g z e r o
a s t h e map a d d r e s s ) .
When a c o n t e x t s w i t c h i s i n v o k e d , t h e c u r r e n t c o n t e x t i s s a v e d i n
t h e c u r r e n t p r o c e s s e s ' c o n t e x t b l o c k , and t h e new c o n t e x t i s l o a d e d
from t h e new p r o c e s s e s ' c o n t e x t b l o c k . T h i s d e v i a t e s somewhat from
t h e " s t a c k " p h i l o s o p h y o f s a v i n g c u r r e n t c o n t e x t on t h e new p r o c e s s e s
s t a c k , h a v i n g t h e d i s a d v a n t a g e of p r o v i d i n g maximum s t a c k s p a c e f o r
t h e maximum l e v e l o f n e s t i n g .

The c u r r e n t p r o p o s a l , however, r e q u i r e s t h a t it b e i m p o s s i b l e f o r an
e x t e n d e d p r o c e s s ( o n e which h a s a c o n t e x t b l o c k ) t o i n t e r r u p t a none x t e n d e d p r o c e s s , s i n c e t h e new p r o c e s s would l o a d r e g i s t e r s w i t h new
v a l u e s w i t h o u t h a v i n g s a v e d t h e o l d v a l u e s . Consequently, t h e r u l e s
f o r d e t e r m i n i n g which p r o c e s s e s can t a k e advantage of a u t o c o n t e x t
s w i t c h i n g must b e i n a c c o r d a n c e w i t h t h e t a s k ' s p r i o r i t y .
The f o l l o w i n g diagram g e n e r a l i z e s t h e r e l a t i o n between p r i o r i t y l e v e l
and t h e c o n t e x t s w i t c h i n g mechanism. Here, M d e n o t e s s w i t c h i n g by
microcode, P d e n o t e s s w i t c h i n g by Erogram ( u s u a l l y s a v i n g o n l y a p a r t
o f t h e r e g i s t e r s ) , and H d e n o t e s s e l e c t i n g a d i f f e r e n t s e t o f hard-

ware r e g i s t e r s .
The f i r s t l e t t e r i n t h e p a i r i s f o r t h e g e n e r a l
A t any
r e g i s t e r s , and t h e second l e t t e r i s f o r t h e map r e g i s t e r s .
g i v e n t i m e , t h e complete system must c o r r e s p o n d t o a s i n g l e p a t h conn e c t i n g MM ( b o t h microcode) t o HH ( b o t h hardware r e - s e l e c t ) .
MM

These c o n s t r a i n t s s a t i s f y t h e general i n t e n t i o n t o (1) a u t o s w i t c h
t a s k s running a t l o w p r i o r i t y l e v e l s , ( 2 ) p a r t i a l l y switch intermediatel e v e l t a s k s under program c o n t r o l , and ( 3 ) a u t o m a t i c a l l y s w i t c h hardware r e g i s t e r sets f o r h i g h - p r i o r i t y t a s k s .

COMPATIBILITY

The o p e r a t i o n of a PDP p r o c e s s , non-extended c o n t e x t , i s b i n a r y c o m p a t i b l e w i t h e x i s t i n g machines. F u r t h e r m o r e , i t i s p o s s i b l e t o mix
e x t e n d e d and non-extended p r o c e s s e s i n t h e same environment (following the rules previously discussed).
The p r o c e s s s t r u c t u r i n g of 1/0 mechanisms i s c o m p a t i b l e w i t h e x i s t i n g p e r i p h e r a l s . There are no m o d i f i c a t i o n s r e q u i r e d f o r CSR
a d d r e s s e s , t r a p v e c t o r a d d r e s s e s , o r UNIBUS c h a r a c t e r i s t i c s .
Furthermore, e x t e n d e d 1/0 d e v i c e s can b e added t o and can c o - e x i s t w i t h
e x i s t i n g hardware.
The 1/0 a s p e c t s of t h e a r c h i t e c t u r e are p h y s i c a l l y u n r e l a t e d t o t h e
PDP-11 program a s p e c t s ( a l t h o u g h , l o g i c a l l y , t h e y d i r e c t l y r e l a t e i n s o f a r as t h e y b o t h have c o n t e x t which i s a c c e s s e d i n s i m i l a r ways,
e t c . ) . Consequently, a d v a n t a g e i n t h e 1/0 area c a n b e r e a l i z e d w i t h o u t t h e n e c e s s i t y o f implementing microcode f e a t u r e s i n t h e CPU, and
vice versa.

EXTENDABILITY
A major goal of the proposed architecture i s the ability to extend 1/0
functions to allow (1) a higher performance optimized system for highend machines, and (2) a cost-effective lower performance system for
low-end machines. To do this, we make a clear distinction between
(1) the descri tive information required to generically describe the
1/0)
2
(
&
c
n
u
f
procedurzl information required to specify mechanisms and alqorithms that per orm the 1/0 function. Specifically,
the architectire requires software to establish only the descriptive
information, allowing wide variations in the actual 1/0 mechanisms
that handle the 1/0 functions in accordance with varying performance
requirements.

Simple Controllers
Optimized Controllers
I/O Processors
CPU Microcode

(MECHANISMS)

1.- Blocks

uProcess
Descriptors

(DESCRIPTIVE
INFORMATION)

In this way, it becomes possible to extend the architecture to include
wide variations of performance requirements on future PDP-11 systems.

MEIENIN I N T E R O F F I C E M E M O R A N D U M
TO :

SUBJ:

Distribution

DATE:

January 22, 1975

FROM:

Dave Nelson

DEPT:

11 Architecture/Planning

EXT :

4509

LOC:

ML5/E67

PDP-11 ARCHITECTURAL ENHANCEMENT STRATEGY

This document is intended to focus on several architectural
areas of PDP-11 systems which require improvements due to
changes in technology, application, or competition.
The contents presented here generally falls into two
categories:

1. Architectural modification/maintenance required
for systems of current capability as a result of
technology improvements, including:
a.
b.
c.
d.
2.

Faster context switching.
WCS applications.
ASCII console.
Serial multidrop bus.

Architectural enhancements required to significantly
improve system capabilities and performance,
including:
a.
b.
c.
d.

Virtual address space extension.
Higher performance 1/0 system.
Mapping hardware for virtual memory.
Configurations for multiprocessing.

Considerable effort has been expended trying to categorize
and compare the architecture of competitive machines,
including the extent to which their operating software
supports their architecture. Particular attention has been
paid to MODCOMP, DG, HP, and INTERDATA.
At the same time, the structures of large scale machines have
been analyzed in order to predict and evaluate architectural
enhancements that will effect minicomputers in 3-5 years:
in particular, MULTICS (virtual address space extension),
IBM and Burroughs (high performance 1/0 systems, and virtual
memory).

-2-

Emphasis has been placed on virtual address space extension
and problems relating to the 1/0 system. Secondary areas include the interrupt system, writable control store, and
multiprocessing.
That the 11 is becoming limited by its current virtual address
space is a foregone conclusion. Several approaches to virtual
address space extensions are included; however, recommendations
which take into account compatibility, cost, and other architectural alternatives, are not yet fully developed.
Problems relating to the 1/0 architecture have not received
as much attention, but it is likely that no single aspect of
the PDP-11 is causing more problems: configurations of multiple controllers won't work (due to UNIBUS overruns);
high-speed peripherals are being purposefully slowed down by
sector interlacing; multiple controllers are being designed
(UNIBUS and MASSbus) for the same peripherals; interfaces to
MASSbus are expensive; overall performance is low: increasing
data rates and configuration sizes are making things worse and
worse.
Preliminary analysis of these problems leads one to conclude
that: 1) The UNIBUS has adequate performance capability if
intelligently controlled by an 1/0 processor; and 2) we need
a serial bus for low-performance peripherals.

PDP-11 ARCHITECTURAL STRATEGY

1/0 SYSTEM

1.1
1.2
1.3
1.4
1.5

11.

Simulation Results
Serial System Bus

INTERRUPT SYSTEM
11.1
11.2
11.3
11.4

111.

1/0 Busses
1/0 Processor
Block Multiplexor Channel

Found Description
Interrupt
Return from Interrupt
Compatibility and Extendability

VIRTUAL MEMORY SYSTEMS
111.1 Some Characteristics of VM
111.2 Advantages of VM to Digital
111.3 Memory Mapping Hardware

IV.

VIRTUAL ADDRESS SPACE EXTENSION
IV.l
IV.2

Linear Address Space Specification
Segmented Address Space Specification

PDP-11 INSTRUCTION SET

VI.

WRITABLE CONTROL STORE

VII.

MULTIPROCESSING CONFIGURATIONS

VIII.

ASCII CONSOLE

SECTION I

1/0 SYSTEM

PDP-11

1/0 SYSTEM

Overview
The a r c h i t e c t u r e of t h e P D P - 1 1

1/0 system h a s remained e s s e n t i a l l y unchanged s i n c e t h e i n c e p t i o n of t h e P D P - 1 1 / 2 0 ,
over
f i v e y e a r s ago.
S i n c e t h a t t i m e , the P D P - 1 1 h a s grown t o supp o r t l a r g e o p e r a t i n g systems i n a p p l i c a t i o n s r e q u i r i n g h i g h
performance 1/0 t h r o u g h p u t ; and a t t h e same t i m e , t h e c o s t o f
low-end systems h a s dropped t o t h e p o i n t where t h e UNIBUS i s
no l o n g e r c o s t - e f f e c t i v e f o r many of i t s i n t e n d e d u s e s .

This s e c t i o n d e a l s s p e c i f i c a l l y t o t h e f o l l o w i n g :

The P D P - 1 1 h a s no d a t a c h a n n e l i n g c a p a b i l i t y which
would a l l o w g a t h e r w r i t e and s c a t t e r r e a d o p e r a t i o n s .
Consequently, o p e r a t i n g systems a r e u n a b l e t o l o a d
t a s k s to/from fragmented memory. S i m i l a r l y , t h e l a c k
of command c h a i n i n g o p e r a t i o n s p r e c l u d e s t h e l o a d i n g
of programs to/from fragmented d i s k .

The UNIBUS, a s c u r r e n t l y u s e d , h a s become o b s o l e t e :
I t is an o v e r k i l l f o r m o s t slow-speed d e v i c e s ( L P , C R ,
t e r m i n a l s ) ; t h e r e f o r e , it i s n o t c o s t - e f f e c t i v e .
I n add i t i o n , it h a s i n a d e q u a t e bandwidth t o e f f e c t i v e l y
h a n d l e c u r r e n t mass s t o r a g e d e v i c e s ( R P , RS, R K ) . The
magnitude of t h i s problem i s best i l l u s t r a t e d by o u r
c u r r e n t p r a c t i c e of b u i l d i n g high-speed p e r i p h e r a l dev i c e s , and t h e n h a v i n g t o s l o w them down (by 2 o r 3
sector i n t e r l a c i n g ) i n o r d e r t o u s e t h e m on a UNIBUS.

While t h e UNIBUS a p p e a r s t o have i n a d e q u a t e bandwidth
f o r o u r high-speed p e r i p h e r a l s , t h e a l t e r n a t i v e o f
b u i l d i n g m u l t i p l e s p e c i a l high-bandwidth memory b u s s e s
( 3 l a 11/70) for 1/0 c o n t r o l l e r s d o e s n o t appear t o be
c o s t - e f f e c t i v e , c o n s i d e r i n g t h e m a r g i n a l performance
g a i n t h a t i s r e a l i z e d i n a c t u a l systems. Multiple highspeed c o n t r o l l e r s may e l i m i n a t e d a t a o v e r r u n s , b u t t h e y
d o n ' t a p p r e c i a b l y i n c r e a s e performance, and a s such,
price-performance competitive p r e s s u r e s w i l l force us
t o abandon t h i s b r u t e force approach i n favor of one
which more e f f i c i e n t l y u t i l i z e s the I / O f a c i l i t y .

The use of a high-speed s e r i a l b u s f o r c o r r e c t i n g u n i t
r e c o r d p e r i p h e r a l s and t e r m i n a l s w i l l a f f o r d s i g n i f i c a n t
a d v a n t a g e s i n i n t e r f a c e c o s t s , cable c o s t s (over l o n g

d i s t a n c e s ) , f l e x i b i l i t y i n configurations, g r e a t relia b i l i t y , and b e t t e r s e r v i c e a b i l i t y . A s e r i a l b u s can
be used a s a systems b u s i n s m a l l , i n e x p e n s i v e a p p l i c a t i o n s ( m i c r o p r o c e s s o r , t e r m i n a l s , LP, f l o p p y ) ,
p r o v i d i n g minicomputer c a p a b i l i t y w i t h some a c c e p t a b l e
loss i n performance.

Competition
1/0 systems a r e d i f f i c u l t t o compare and e v a l u a t e b e c a u s e of
wide v a r i a t i o n s i n c o n c e p t s and o b j e c t i v e s . The 1/0 a r c h i t e c t u r e s of H-P, MODCOMP, DG, INTERDATA, and IBM have b e e n compared
a g a i n s t f e a t u r e s which a r e judged t o be m o s t i m p o r t a n t f o r h i g h performance, g e n e r a l - p u r p o s e , multiprogramming systems. Some
of t h e s e f e a t u r e s i n c l u d e :
DG

H-P

MOD

INT
7/3 I

IBM

PDP-11

IOP-11

f r a g m e n t e d memory
1/0 ( d a t a c h a i n i n g )

f r a g m e n t e d d i s k 1/0
(command c h a i n i n g )

simultaneous block
transf e r

channel optimization

(1)

(21

(41
Y

(3)

(5)

(1) Does h a v e AUTO-DRIVER,

implemented v i a CPU microcode, l i m i t e d

performance.
(2) NO c o n c u r r e n c y on s o m e mpxr c h a n n e l ; can h a v e m u l t i p l e channels.
( 3 ) R e s t r i c t e d b y UNIBUS bandwidth, u n c o n t r o l l e d .
( 4 ) MASSbus systems w i t h wide band memory a c c e s s o n l y .
( 5 ) I n c l u d e s d e v i c e o p t i m i z a t i o n and r e q u e s t o p t i m i z a t i o n ,

described herein.

THE FOLLOWING PAGES DESCRIBE THESE FEATURES
I N MORE D E T A I L

Data General ECLIPSE

M map

M .map

K ( # O : 63)

Features:

1/0 is transferred to/from VIRTUAL mem space

(allows fragmented memory).

Simple operation: Address and word count pair for
each of up to 64 devices.

Disadvantages:

o Although the MAP allows memory fragmentation, there
is no command chaining that would allow disk
fragmentation.

Like the PDP-11 1/0 is asynchronous and uncoordinated.
The sum of
device transfer rates is limited by
peak bandwidth of the bus.

o Any optimization is purely software controlled.

o All 1/0 goes thru same map:

restricted to 32K.

Hewlett Packard 3000

K(#O:63,Direct)

Pio; (#0:15,Selector)

K(#O)

Features :
o

All 1/0 classified into 3 distinct categores.

- Direct for terminals, unit record, etc.
- MPXR for intermediate speed disks, high speed
unit received.
- Selector for high speed mass storage.
o

MPXR and SELECTOR are programmable (ala IBM 360)

and capable of command and data chaining.
Disadvantaqes:
o

Channel programs cannot cross device controllers.

Devicc: control 1 crs cannot connect to multiple channels
( t h e r e f o r e , V ~ I - yl j tt1.e optimization is possible).

SELECTOR channel is busy for duration of a single

No memory management support, except via chaining
data.

channel program - little optimization possible.

MODCOMP IV

I K

io; (#0:7,Multiplexor)

K.dma (not used)

Features :

o Up to 16 subchannels, programmable with data
chaining facility.
o

Memory is paged with 256 word block size, so that
constructing a channel program for a fragmented
memory is straight forward.

o DMA provided via separate memory ports.
Disadvantages :

o No command chaining facility.
o Only one channel program per device controller.
Cannot easily optimize devices across multiple
requests.

INTERDATA 7/32

K (#0:2 55 , M u l t i p l e x o r )
K (#O: 1 5,S e l e c t o r )

Features :

MPXR performs w o r d and l i m i t e d block t r a n s f e r s under

program c o n t r o l .
o

SELECTOR, c o n t r o l l e d v i a MPXR,

c a n perform h i g h
s p e e d b l o c k t r a n s f e r s , d i r e c t l y t o DMA p o r t .

channel converts i n t e r r u p t devices i n t o
block t r a n s f e r .
"AUTO-DRIVER"

Disadvantaqes :
0

N o r e a l c h a n n e l c a p a b i l i t y f o r SELECTOR o r MPXR

d e v i c e s : no c h a i n i n g c a p a b i l i t y ; no memory management.

Sum of a l l d e v i c e r a t e s c a n n o t exceed MPXR bandwidth

(no b u r s t mode c a p a b i l i t y ) .

Only one d e v i c e a c t i v e on SELECTOR; c h a n n e l busy f o r
d u r a t i o n of r e q u e s t ; c h a n n e l o p t i m i z a t i o n must be
done i n software.

No l a r g e block t r a n s f e r on MPXR, e x c e p t u s i n g
AUTO-DRIVER, which i s low performance.
Only one
c h a n n e l program per d e v i c e .

IBM 370

4(#0:191)

io: (Block Multiplexor
Pio; (Selector)

K(#O: 191)

Features:

64 subchannels operating under control of unique

channel programs - complete chaining capability.

o Channel is busy only for duration of transfer.
Arbitration is done at device level in real time,
transparent to channel program. This optimizes
channel utilization over 360 MPXR approach which
arbitrated channel activity in software.
Disadvantages:

is done to/from physical memory requiring the
exec to construct a channel program from memory
maps.
1/0

o A controller/device can only be connected to a single
channel program. Consequently, optimization of 1/0
requests from independent tasks is complex --- probably
not feasible.
o

Each device forces burst mode, utilizing 100% of
channel regardless of its data rate.

Current PDP-11

M.map -Pc

-T

Features:

Simple operation: Address and word count pairs for
each device.

o All device types run on the same multiplexor bus.
Disadvantaqes:

o No capability for block transfer to/from fragmented
memory and fragmented mass storage devices.

The sum
of all device transfer rates is limited by the
bandwidth of the UNIBUS.
1/0 is asynchronous and uncoordinated:

Proposed PDP-11 with IOP-11

M.map .-

[f;

io;

M.map

-Pi0;(#0 :15,Multiplexor)

K-

K.map (#O: 15)-K
K.map(#O:15)

-K

Features:
0

1/0 transfers to/from virtual addresses.
There can be an arbitrarily large number of maps,
each for a different 1/0 process, no data chaining
required.

1/0 transfers to/from virtual disk addresses by
means of disk segmentation maps, eliminating need
for command chaining.

IOP controls positional and rotational optimization
by multiplexing all 1/0 processes across all 1/0
devices. Channel is busy only for duration of
transfer.

Bandwidth permitting, IOP will schedule multiple
MASS busses in accordance with device data rates to
maximize bandwidth utilization.

IOP will translate virtual block transfers into
multiple physical block transfers and perform them
in parallel.

IOP will allow UNIBUS to perform word multiplexing
operations and block multiplexing operations
concurrently.

Summary of Conclusions

Two preliminary conclusions are derived from the studies to
date: (1) It is possible to protect Digital’s substantial
investment in the UNIBUS over the next 3-5 years and immediately
obtain a significant increase in system performance if we control
the bus as a block multiplexor ,(by using an 1/0 processor
with no hardware changes to bus or devices) and do away with
sector interlacing, and ( 2 ) Design a serial bus as a more
cost effective interface to low speed devices.
While an 1/0 processor will not substantially improve
performance (only 50”/0), it will allow us to build large, high
performance systems using the UNIBUS (unmodified bus and
interfaces) and that the 1/0 systems on these configurations
will perform better than machines built around high bandwidth
memory/massbus connections (11/70). Further performance
gain over present UNIBUS systems is realized by (1) Eliminating sector interlacing which will reduce transfer time for
multiple sector transfers, and ( 2 ) Performing multiple
physical requests for the same logical request in parallel.

1.1

1/0 Busses

Figure 1.1 shows the data rate of several PDP-11 busses
(memory, massbuss, UNIBUS, etc., as a function of the cost
of a typical interface. Superimposed on this graph is the
data rates of several typical peripherals from which we
conclude that the UNIBUS is a performance overkill (and not
very cost effective) for line printers, card readers, and
floppies. A l s o , the UNIBUS cannot adequately handle the
data rates of high speed disks, requiring buffering and
sector interlacing to effectively slow them down. A l s o
plotted, is the data rate of the UNIBUS when controlled by
an 1/0 processor, or when configured as a block multiplexor
channel, which are described in sections 1.2 and 1.3.

I. 2

1/0 Processor Architecture

T h i s section describes the a r c h i t e c t u r e of a microprogrammed
1/0 processor capable of performing complete data channel
operations between main memory and UNIBUS o r MASSBUS mass

storage peripherals.
The 1/0 processor is designed t o multiplex a variable number
of concurrent 1/0 requests i n a manner which optimizes
p o s i t i o n a l and r o t a t i o n a l latency, and overlapped seeks.
Each of t h e variable number of requests i s described as
independent t r a n s f e r s from independent v i r t u a l spaces: both
main memory and d i s k memory a r e v i r t u a l i z e d using memory
maps having the s t r u c t u r e of t h e KT-11 segmentation u n i t ,
and t h e FILES-11 r e t r i e v a l pointer window, respectively. The
disk map i s a simple l i s t of f i l e segments and as such, it i s
adaptable t o a v a r i e t y of f i l e s t r u c t u r e s .
Multiple 1/0 processors can be configured t o perform
multiple simultaneous 1/0 t r a n s f e r s . A s i n g l e 1/0 processor
could be microprogrammed t o control multiple c o n t r o l l e r s ,
giving t h e functional equivalent of multiple 1/0 processors.
The concepts a r e shown t o be extendable t o unit-record and
communication devices.

FORMAL DESCRIPTION

O r i g i n a l PDP-11/20 had a PMS* diagram l i k e :
Here, a l l a d d r e s s e s between
Pc & Mp, and between P1i0,
M & Ms are p h y s i c a l
(Eo mapping). M, = d i s k .

With KT-11 memory map o p t i o n , we can c o n s i d e r e a c h p r o c e s s , i,
h a v i n g i t s own s e t of map r e g i s t e r s , s o t h a t w i t h memory management
we have

A f i r s t l e v e l enhancement o v e r t h e above would be t o allow A
PI r) t o o p e r a t e through a MAP3 so that memory management i s s e e n
s y k e t r i c a 1 l . y - between Pc and P1i0 :

w6P i

* B e l l & Newell, C0rn.p S t r . P 15.

A second l e v e l improvement w o u l d a l l o w PI/O t o o p e r a t e on Ms
t h r u a MAP'k, where W P ' k t r a n s l a t e s v i r t u a l block addresses i n t o
p h y s i c a l BLOCK addresses ( a n a l a g o u s t o t h e l o g i c which c u r r e n t l y
e x i s t s i n FILES-11) :

T h i s makes Pc symmetric t o PI/o,

and Mp symmetric t o Ms.

Now, i f we l e t

and

then

which is same as o r i g i n a l PDP-11,

w i t h v i r t u a l Mp,

Ms.

What are t h e a d v a n t a g e s ?

. Advantages
of
are well known t o u s .
They a l l o w us t o a d d r e s s above 32K, and t o map g l o b a l ,
r e e n t r a n t areas, e t c , e t c .
a l l o w us t o fragment p h y s i c a l
. Advantages of [mRCai\r e s T]would
r i c t i o n u n d e r RSX-11D) and t r a n s f e r
memory ( c u r r e n t l y
t o Ms w i t h o u t p r o c e s s o r
intervention.
the e q u i v a l e n t of d a t a c h a i n i n g .

(e)

That is, i t allows

of [%.-MAe'%]
would a l l o w us t o e f f i c i e n t l y frag. Advantages
ment d i s k ( c u r r e n t l y done i n FILES-11, p u r e l y s o f t w a r e ) .

A s above, we c o u l d t r a n s f e r fragmented d i s k areas w i t h o u t
p r o c e s s o r i n t e r v e n t i o n . T h i s a l l o w s the equivailent of
command c h a i n i n g .

. Advantages
o f i n t e g r a t i n g b o t h maps i n PI/ a l l o w d i r e c t
t r a n s f e r between memory and d i s k w i t h a r b i? rary f r a g m e n t a t i o n .

Advantages o v e r t r a d i t i o n a l d a t a c h a n n e l s ( o f f e r e d by MODCOMP
and 1 n t e r d a t a ) a r e ( 1 ) maps are related t o p r o c e s s e s and f i l e s ,
and t h e y a l r e a d y e x i s t , ( 2 ) n3 data c h a n n e l programming, and
s t o r a g e e l e m e n t s are symmetric.

The t o t a l l o g i c i n v o l v e d i n MAP3 and MAP'k i s shown i n f i g u r e 1.
C u r r e n t l y , t h e v i r t u a l M map e x i s t s e x c l u s i v e l y i n hardware
(KT-11).
e
A l s o , c u r r e n t l y the v i r t u a l M, map e x i s t s e x c l u s i v e l y i n
s o f t w a r e ( FILES-11)

What i s proposed i s a hardware/software trade o f f w i t h i n each
map scheme t o o p t i m i z e t o t a l performance.

The fundamental q u e s t i o n r e l a t i n g t o t h e implementation of the
pro,posed a r c h i t e c t u r e i s : what p o r t i o n s o f the o r g a n i z a t i o n s h o u l d
reside i n hardware o r software, Pc o r PI/o, and what are t h e i n t e r face r e l a t i o n s between them?

1/0 ARCHITECTURE AND OPTIMIZATION
Formally, we have shown t h e fundamental 1/0 p r o c e s s t o be
r e p r e s e n t e d by

where j r e p r e s e n t s a v i r t u a l memory t r a n s f o r m a t i o n f o r p r o c e s s j ,
and k r e p r e s e n t s a v i r t u a l memory ( d i s k ) t r a n s f o r m a t i o n f o r f i l e k.
T o g e t h e r , t h e p a i r ( j , k ) d e s c r i b e s me o f several 1/0 p r o c e s s e s
which may be i n o p e r a t i o n a t a n y g i v e n t i m e .
That i s , i n general,
f o r P p r o c e s s e s and F f i l e s , w e can have:

Here, we have used the term I/O P r o c e s s , IOP k, t o d e n o t e a
p a r t i c u l a r (j,k) p a i r r e p r e s e n t i n g 1/0 between iwo p a r t i c u l a r
v i r t u a l spaces.
I n g e n e r a l , t h e n , we could have a n a r b i t r a r y number o f IOP
p r o c e s s e s ( n o t t o be confused w i t h Pc p r o c e s s e s ) a t any given ilk
t i m e . A p a r t i c u l a r d e v i c e c o n t r o l l e r could be d e s i g n e d t o h a n d l e
a l i m i t e d number of IOP S, s a y up t o 8. (The v a r i a b i l i t y of t h i s
number a l l o w s a w i d e r a i i e o f implementation Q s i m p l e d e v i c e s
could be l i m i t e d t o 1; complex could have 16, e t c ) .

The m i n i m u m c o n t e x t a s s o c i a t e d w i t h a n I o P j k p r o c e s s i s :

The q u e s t i o n remains as t o what p o r t i o n o f t h i s c o n t e x t should
r e s i d e i n memory, under management of Pc, and wnat s h o u l d reside
i n t h e d e v i c e c o n t r o l l e r , under management of PI/o.
One p o s s i b l e hardware/software a l l o c a t i o n o f c o n t e x t i s t o have
c o n t r o l b l o c k s i n memory ( s e t up i n i t i a l l y by s o f t w a r e ) whose
p h y s i c a l a d d r e s s i s loaded i n t o a c o n t r o l l e r r e g i s t e r .

I
The 1/0 p r o c e s s o r ( d e v i c e c o n t r o l l e r ) would t h e n compute and
maintain the following t a b l e :

- E

bt 5P
I
I

I L

P O S I T I O N A L AND R O T A T I O N A L LATENCY O P T I M I Z A T I O N

We have d e s c r i b e d a n a r c h i t e c t u r e whereby t n e 1/0 p r 3 c e s s J r
i s g i v e n a number of 1/0 r e q u e s t s t a p e r f o r m i n p u t :)r : ) u t p u t
between a r b ’ t r a r i l y fragmented mem3ry and d l s k . Each r e q u e s t i s
independent of o t h e r s , a n d a t y p i c a l 1/0 p r x e s s \ ) r c < i u l d b e
designed t o h a n d l e up t a 16 r e q u e s t s a t any gIven t 5 m e .
N o w , s i n c e a l l r e q u e s t s a r e i n d e p e n d e n t , and s i n c e t h e i r d i s k
d a t a i s p o s s i b l y fragmented, t h e 1/0 p r x e s s o r can be designed t:,
m u l t i p l e x all r e q u e s t s s a as t o o p t i m i z e p o s i t i o n a l and r o t a t i o n a l
l a t e n c y , and perform overlapped seeks f o r m u l t i - d e v i c e c o n t r o l l e r s .

We d e f i n e an index, np, which i d e n t i f i e s 1/0 r e q u e s t s
0

where we have a r b i t r a r i l y r e s t r i c t e d t h e number of c m c u r r e n t
r e q u e s t s t o 16.

F a r a m u l t i p l e d e v i c e , moving head d i s k c o n t r 3 l l e r , t h e 1/0
p r o c e s s o r could be microprogrammed t 3 p e r f a r m t h e fDll:,wing
sequences a t t h e c3mpletion of each s e c t o r .
Sector
end

I n i t i a t e overlapped

Update c m t e x t af
r e q u e s t , np, t h a t
L
* u s c 3m D l e t e d
Accept new np
r’3m P,.

if any

Scan c o n t e x t t a b l e of

a l l n p s , and c h w s e
optimized r e q u e s t f a r
next s e c t a r peri.od. AlsJ,
d e t e r m i n e i f overlapped
seek a r e r e q u i r e d
I

Sectcw End

IMPLEMENTATION
- A PPROA
___-- CH

I n g e n e r a l , 1/0 d e v i c e s f a l l j.nt3 one o f t h e f,>ll.,wing c a t e g : ) r i e s :
mass s t o r a g e (randam .ir s e q u e n t i a l o c c u r s )
u n i t recDrd ( p r i n t e r s . r e a d e r s , e t c . )
communication ( t e r m i n a l s , synchrmlius lines,
multidrop, e t c . )

All d e v i c e s i n these c a t e g a r i e s could be implemented u s i n g
similar 1/0 micro p r o c e s s o r s w i t h w r i t e a b l e cDntrD1 s t o r e . MemDry
t r a t l s l a t i o n ( v i r t u a l M _3 P h y s i c a l M _3 P h y s i c a l Ms
V i r t u a l Ms)

has been d i v i d e d i n t o g i s t i n c t c m t e x ! ? b l x k s , s o t h a t

. mapping D f primary memory i s t h e same i n a l l c a s e s
. mapping D f secondary memary space i s d e v i c e t y p e dependent:
f o r mass s t a r a g e , w e map f i l e segments; for communications
d e v i c e s , we map ontD l i n e s ; f D r u n i t r e c o r d and magtapes,
we d m t t map a t a l l .

That i s , one m i c r o p r o c e s s o r approach w i t h w r i t e a b l e c o n t r o l
s t o r e could p r o v i d e c h a n n e l c a p a b i l i t y f o r most a l l d e v i c e t y p e s .

A
Y

Y
bJ

1.3

Performance of Block Multiplexors

Section 1.3 is a preliminary design of an 1/0 processor
designed to optimize data channeling activity on medium scale
11 systems. This section compares the theoretical data used
by IBM to design their Block Multiplexor Channel (IBM Systems
Journal, Vol. 11, # 3 , 1972), with a theoretical study of
DECsystem-10 performance (Turner, Stone, Disk Throughput
Estimation, 1071), and actual measurements on CS-2 (Turner).
The IBM data agrees well with ours (less than 50% variation
in total throughput as a function of Q lengths, number of
devices, channel architecture, etc.), and sufficient confidence has been attained in their applicability to PDP-11
systems to draw the following preliminary conclusions:
1.

In terms of performance, IBM's Block Multiplexor
Channel is equivalent to an 1/0 processor, although
the architectual approaches are quite different.

1/0 processors don't help matters as much as we

tend to think they would. On PDP-11 scale systems,
we might increase throughput by 50%. However, for
certain applications, and systems (demand paging),
throughput could increase 100%.
3.

But, an 1/0 processor is considerably better than
multiple MASSBUS controllers, even when the MASSBUS
is programmed for overlapped seeks. IBM data show
that a single Block Multiplexor Channel (performing
one 1/0 operation at a time) can outperform eight
MASSBUS type controllers, on a system with 64 devices.

The UNIBUS, under control of an 1/0 processor, can
run similarly to IBM's Block Multiplexor Channel at
a rate greater than a million words per second which
is more than any of our mass storage devices.
Consequently, mi arbitrarily large configuration of
RS04's, RP04's, etc., all connected to the UNIBUS

(unmidified) can out perform the same configuration
connected by up to eight MASSBUS controllers having
wideband (non UNIBUS) access to memory.
An 1/0 processor (separate micro controller, or integrated
into CPU microcode) is a more cost effective way of managing
mass storage devices than are m u l t i p l e MASSBUS's controlled
by software. The UNIBUS, on an 11/40 size machine, has
sufficient horsepower to out perform the largest configuration
( 4 MASSBUSSES)of the PDP-11/70.

. ..._’,.
Figure 4

Sirnulotion results using o wriable number ot IBM 3336-like uevices on o

Figure 5

Simulotiop results using IBM 3330-like devices evenly di*tribu?d
vorioble number of channels

’,.

arnong a

1.4

Simulation of 1/0 System

Current efforts include a digital simulation of the PDP-11
1/0 system. These results will measure:
1.

Performance gain for I / O processor and multiple
controller configurations.

Effects of mixing device types on the same MASSBUS
controller.

Throughput as a function of request que length for
for typical configurations.

Configurations and activities that characterize
data late conditions.

This section will be included when specific results are
obtained.

1.5

Serial Bus

The serial multidrop bus is intended to provide:
1.

A low cost systems buss for small processors at
an acceptable performance level.

A cost effective means of connecting multiprocessor
systems.

A means of connecting large numbers of terminals.

4. A cost effective bus for unit record peripherals
for medium and large scale 11's.
Figure 1.5.1 shows the organization of the bus arbitrator
in relation to each node. The arbitrator is a processor with
a buffer memory used for communication among nodes. Transfers
to and from node zero uniquely bypass the buffer memory, and
as such, node zero may be used to connect the central processor
in a hierarchial system.
Figure 1.5.2 shows the variety of interconnections possible
with the serial bus protocol. Multidrop nodes can connect
to remote multidrop nodes, a low cost dedicated interprocessor link ( I P L ) , or to microprocessor based computer
systems.

i
V

SECTION I1

INTERRUPT SYSTEM

11.

INTERRUPT SYSTEM
Overview
The use of a stack for saving and restoring machine
registers in the PDP-11 interrupt system works well
for small single user un-mapped operating systems.
In large mapped memory systems, running multiple
processes, however, some improvements could be made
to reduce the time overhead of saving and restoring
machine context.
Presented here is an architectural description which
contains many desired attributes for such systems,
while retaining a significant level of compatability
with existing machines.
Competition and Motivation
The motivations for this section include the following:
1.

Both Modcomp and Data General have announced machines
which incorporate interrupt features which are of
superior performance to the PDP-11. These features
include switching of register blocks and memory
maps in hardware.

The existing KT-11 architecture is inadequate for
(a) Larger virtual addresses, (b) More efficient
memory allocation, (c) High performance demand
paging. Improved memory management architecture
will require different techniques for changing the
memory mapping context. These changes explicitely
affect interrupt processing.

Operating Systems which are process structured
( R S X - 1 1 D ) impose a high degree of context switching
among processes with significant overhead. Context
switching and interrupt servicing are highly related
and require an integrated approach.

The PDP-11 architecture does not lend itself toward
high speed communications and interrupt processing.
Interrupt-by-character devices run with excessive
overhead, and while the attached proposal does not
directly deal with this problem, it does provide the
groundwork. Further to this point is the growing
requirement for hardware managed 1/0 functions such
as command and data chaining.

11.1

Formal Description

Formally, a computer system operating in complex environment
can best be described in terms of "processes" (rather than
programs and variables, etc.). A process is defined as a
"procedure with context" where procedure denotes the machine
time-sequence structure, and context denotes the processes
state. Context infers different things in different environments, but in terms of the hardware processor, context
generally refers to the general registers, map registers,
and Program Status Word.
Emerging from the concepts of processes is the process number.
Symmetry behooves us to treat all processes alike (except for
priority), and therefore, since a process can be anything from
a FORTRAN program to an interrupt service routine, the process number serves to distinguish them from within the system.
In the simplest sense, process numbers should be used as an
index into a table of context vectors. Each vector contains
a pointer to a context block which holds the machine state
for the process.
Interrupts in such a system are simply effected by asserting
a new process number on the CPU, which, upon arbitrating the
priority of the requested and running processes, may choose
to invoke a context switch to the new requested process.
Now, specific to the proposed PDP-11 interrupt system, the
process number, P, is used as an index into the CONTEXT
VECTOR TABLE (origined at physical location zero) to obtain
the CONTEXT VECTOR, CVP. Currently, these locations are the
trap vectors which contain the new PC, PS. Under the new
definition, however, these locations would contain the
physical address of the CONTEXT BLOCK (a mode bit in the PS
could control this redefinition and thereby retain full
compatibility)

Referring to figure 11.2, MAP contains the location of the
memory map registers (KT-11. registers or equivalent). SP and
PC contain virtual addresses of the processes stack pointer
and program counter, etc.
A new register located in the 1/0 page would be assigned to

hold the CURRENT CONTEXT VECTOR, CCV. Upon interrupt, the
processor would save t h e existing context in the current
processes CONTEXT BLOCK, load the context addressed by the
CONTEXT VECTOR, and put the old CCV on the new processes stack.
A return from interrupt (RTI or RTT), or a fake (software
generated) RTI, would pop the old CCV off the stack and
restore the context of the old process.

11.2

11.3

11.4

Interrupt:
a.

Store context in block addressed by CCV.
as CCVOLD.

Save CCV

Load CCV from CONTEXT VECTOR TABLE indexed by
process number (currently the trap address).

Load machine context from block addressed by CCV.

Push CCVOLD onto new stack.

Return from Interrupt:
a.

POP CCVOLD from current stack.

Store machine context into block addressed by CCV.

Load CCV with CCVOLD.

Load machine context from block addressed by CCV.

Compatibility and Extendibility:

Compatibility with existing peripherals is retained.
Compatibility with existing software is controlled by a
single mode bit. Modifications to existing software to take
advantage of improvements are minor.
Implementation logic is similar in that both modes involve
retrieval of vectors, pushing and popping variables onto Stacks,
etc. Block or cache loading is, of course, new.
The concept naturally extends to scheduling of software
tasks, thereby reducing the time/core overhead of loading/
restoring machine registers for every context switch.
Admittedly, this is a small portion of a tasks context, but
would serve to speed up switching significantly.
The architecture allows f o r high performance implementations
which would "cache" the machines registers from context blocks,
thereby saving and restoring only those registers which were
used by a process.
The architecture allows for low performance implementations
which would treat the machine registers as ordinary memory,
thereby reducing the number of internal CPU registers.

The a r c h i t e c t u r e allows f o r a simplified implementation
whereby all memory and machine r e g i s t e r s a r e accessed through
a common cache. Access frequencies of the general r e g i s t e r s
would n a t u r a l l y r e t a i n them i n t h e f a s t access locations,
and performance could be retained by disabling memory updating on all r e g i s t e r addressing modes.

I
I

An. Improved I n t e r r u p t System f o r - t h e

PDP-11

Nelson

Appendix A

The PDP-11 i s i n need o f some hardware enhancements i n t h e 1/0 a r e a
t o f a c i l i t a t e command and d a t a channing ( l i k e d a t a c h a n n e l s ) , and
h i g h speed communications c h a n n e l s .
B u t , w e s h o u l d s t o p t h i n k i n g of
d a t a c h a n n e l s a s some k i n d o f unique p r o c e s s o r s . R a t h e r , w e s h o u l d
c o n s i d e r t h e g e n e r a l 1/0 f u n c t i o n a s simply a n o t h e r p r o c e s s w i t h i n
t h e system. C u r r e n t l y t h e s e 1/0 p r o c e s s e s are o u r i n t e r r u p t s e r v i c e
r o u t i n e s , b u t t h e y a r e t o o slow f o r much o f t h e 1/0 b e c a u s e t h e y r u n
a t macro l e v e l . A b e t t e r approach i s t o run t h e h i g h t h r o u g h p u t , .
s h o r t , i n t e r r u p t r o u t i n e p r o c e s s e s a t micro l e v e l w i t h t h e d e v i c e
c o n % e x t s t o r e d a t t h e macro l e v e l . Advantages o f t h i s approach
i n c l u d e h i g h e r t h r o u g h p u t and t h e a b i l i t y t o b u i l d transfer-by-word d e v i c e s
and program them a s NPR d e v i c e s . W e have a l o t t o l e a r n i n t h i s
a r e a , b u t i n many s u b t l e ways, t h e i d e a o f p r o c e s s e s h a v i n g t h e i r
machine s t a t e c o n t a i n e d i n memory and a d d r e s s a b l e by a p r o c e s s
number p r o v i d e s a s t r u c t u r a l framework t h a t r e l a t e s w e l l t o t h e
g e n e r a l 1/0 problem.
The f o l l o w i n g d e s c r i p t i o n o f an asynchrounous l i n e c o n t r o l l e r i s
g i v e n by way o f example and i s n o t i n t e n d e d a s a s e r i o u s p r o p o s a l .
The communication d e v i c e d e s c r i b e d i s an asynchrounous l i n e m u l t i p l e x o r
t h a t g e n e r a t e s a BR r e q u e s t f o r each c h a r a c t e r .
I n o r d e r t o minimize
t h e overhead o f p r o c e s s i n g each c h a r a c t e r , i t i s d e s i r e d t o implement
a micro l e v e l c o n t r o l l e r t h a t b u f f e r s a l l c h a r a c t e r s i n s e p a r a t e l i n e
b u f f e r s , and g e n e r a t e s an i n t e r r u p t when any CTRL c h a r a c t e r i s encountered.
The s o f t w a r e h a n d l e r i s d e s i g n e d t o s e t up b u f f e r s and p r o c e s s c o n t r o l
characters.
I n d o i n g s o , i t l o a d s t h e a d d r e s s of a t a b l e of b u f f e r
The m i c r o p r o c e s s o r would
p o i n t e r s i n t o Ro and t h e n e x e c u t e s an R T I .
be programed t o s t o r e e a c h c h a r a c t e r r e c i e v e d i n t o t h e a p p r o p r i a t e l i n e
buffer.
T h i s i s accomplished i n microcode by i m p l i c i t l y e x e c u t i n g t h e
e q u i v a l e n t of :
l i n e (RO), ~1
ch, S ( R 1 ) +
R1, l i n e ( R o )
c h , CTRL
exit
( g e n e r a t e macra i n t e r r u p t )

MOV

MOV
MOV
BIT
BEQ

; g e t address of buffer
;store i n buffer
;update address
;test character
:exit

S i n c e t h e above i n s t r u c t i o n s a r e p r o c e s s e d a t micro l e v e l w i t h o u t
h a v i n g t o undergo a macro l e v e l c o n t e x t s w i t c h , t h e c h a r a c t e r p r o c e s s i n g
r a t e i s comparable t o an NPR c o n t r o l l e r .
An a d d i t i o n a l advantage i s
t h e a b i l i t y t o g e n e r a t e macro l e v e l i n t e r r u p t s f o r c o n t r o l c h a r a c t e r s ,
where h i g h e r l e v e l p r o c e s s i n g i s r e q u i r e d .

I
I

SECTION I11

VIRTUAL MEMORY SYSTEMS

I11

V i r t u a l Memory

The i d e a of u s i n g a b a c k i n g store ( d i s k ) t o p r o v i d e
a v i r t u a l memory (VM) environment h a s been around f o r a b o u t
15 years.
S i n c e t h e l a t e 1 9 6 0 ' s , more t h a n 200 r e s e a r c h
p a p e r s h a v e been p u b l i s h e d on t h e s u b j e c t , and of t h e 50
p a p e r s p u b l i s h e d i n I B M ' s Systems J o u r n a l s i n c e 1 9 7 1 , n o less
t h a n 1 0 (20%) h a v e been devoted t o VM. The a d v a n t a g e s
and d i s a d v a n t a g e s of VM a r e becoming w e l l u n d e r s t o o d , and
t h e r e a r e growing i n d i c a t i o n s t h a t mini-computer manuf a c t u r e r s (Modcomp, Data G e n e r a l ) w i l l be implementing VM
i n t h e n e a r f u t u r e , a s evidenced by t h e i r r e c e n t l y announced
memory management a r c h i t e c t u r e s .
The p u r p o s e of t h i s s e c t i o n i s t w o f o l d : f i r s t , to
f o c u s a t t e n t i o n on t h e p o t e n t i a l t h a t VM o f f e r s n o t o n l y
a s RSX-11D s i z e s y s t e m s , b u t a l s o f o r RSX-11M and R T - 1 1
s i z e s y s t e m s , and second, t o expose t h e i n a d e q u a c i e s of
o u r c u r r e n t KTll memory management h a r d w a r e f o r u s e i n
VM systems.
Contained h e r e i n i s a proposed memory management u n i t which i s claimed t o be better s u i t e d f o r demand
p a g i n g a s w e l l a s p h y s i c a l and v i r t u a l memory a l l o c a t i o n .
I t i s a l s o c h e a p e r t o b u i l d , f a s t e r i n performance, and
a d a p t a b l e t o b o t h s m a l l 1 6 - b i t machines a s w e l l a s l a r g e
3 2 b i t machines.

111. 1

Some Characteristics of VM Systems

Virtual memory (VM) systems can be characterized with
respect to real memory (RM) systems by distinguishing levels
of capability from levels of performance. In this sense, we
consider "capability" to be the types of functions that the
system can perform without regard to the rate at which it
does it. By the same token, we consider the machines "performance" to be the raw speed of the machine without regard
to its capability. Given this, we can compare the relative
levels of capability and performance that can be attained
by VM and RM machines as a function of the system's real
memory size.

41
U

This simplified comparison shows that whereas the
capability of an RM system varies significantly as a function
of core (while its performance is constant), the capability
of a VM system is constant as a function of core (while its
performance varies). The key point here is that it is easier
and more cost-effective to build systems whose capabilities
are independent of the amount of core. The marketing and
engineering departments of Digital have become overly preoccupied with the significance of the amount of core memory
in its relation to functional characteristics. Rather than
treating real memory as just another level in an integrated
memory hierarchy, we continue to perceive it as a hard resource/facility which is critically related to functional
capability.

111. 2

4+,

Advantages of VM to Digital

It is tempting to suggest that VM offers the advantage
of reducing software development costs, since programs
could be written without regard to physical memory size.
While this is true to some extent, it is important to note
that a considerable portion of the research done in VM
systems has been concerned with effects of program structure
and program structuring techniques aimed at offsetting the
performance degradation inherent in VM systems. It has
become clear that virtual memory is far from "transparent",
and that in order to recover the performance loss, the software engineering effort required to appropriately structure
programs will likely be comparable to the effort we currently
expend in coping with real memory overlaying techniques.
The primary advantage that VM gives us is the option to
structure programs rather than the necessity to do so. This
option allows us to write large, highly capable programs
which are either (a) unstructured with low performance, or
(b) highly structured for high performance or some intermediate level depending on the intended frequency of use.
Thus, under VM, one applies program structuring techniques
in order to achieve a performance level, rather than a
capability level. On the other hand, under RM, large
program capability, and therefore performance, is impossible
without some degree of program structuring (overlaying).

111.

Memory Management Unit

There have been numerous research studies published
regarding the optimization of various parameters for
virtual memory performance. Generally speaking, the results
of these studies show that the performance of VM systems is:
(a) Very sensitive to program structure characteristics
(b) Moderately sensitive to page size
(c) Slightly sensitive to page replacement technique
Performance is generally optimized when the page size
is comparable to the characteristic program structure size.
Unstructured programs favor a smaller page size, whereas
highly structured programs favor a larger page size. IBM
studies have shown that as long as the program is structured
in accordance with the page size, then larger page sizes are
disproportionately preferred (Hatfield, Journal of R/D).
While there are variations in optimized page size
values, there is general agreement that the KT-ll/D page
frame ( 8K bytes) is too large, and that a more appropriate
value is 1K-2K bytes. Figure 111. 1 compares the address
translation logic of the KT-ll/D and a proposed KT-ll/X.
It should be noted that the smaller 1K page size of the
KT-ll/X is sufficiently small so that physical memory can
also be allocated in 1K sizes. This ability to allocate
physical space in the same size as virtual space not only
simplifies system software, but also eliminates the complexity and latency required for the extra addition that's
currently required the KT-ll/D.
Conclusion
Virtual memory on PDP-11 systems should be considered as
part of a 2-3 year systems strategy. While changes in
memory and backing store technologies may change some
parameters of VM, the basic concepts and economies of
memory hierarchies will long be with us.

SECTION IV

VIRTUAL ADDRESS SPACE EXTENSION

IV.

VIRTUAL ADDRESS SPACE EXTENSION

There is little doubt that a major restriction of the PDP-11
is its limitation of program size to 3 2 K words.
Competively, the PDP-11 does not compare favorably as evidenced
by the following chart:
HP

MOD IV

INT

IBM

PDP-11

Virtual address space
(bytes1

96K(I)

64K

256K(2)

224

64K(3)

I & D separation

221

224

222

Physical address space 1 1 2 8 K

2 5 6 ~ 512K

1. Program segments restricted to 3 2 K , data segments to
Operating system features segmentation which allows
subroutine segments to coexist in separate address
spaces.
65K.

Includes factor of two for I&D space separation.
that in practice, this is not attainable.

Note

Excludes I&D space separation because it is unsupported.

This section contains descriptions of two approaches to virtual
address space extension: segmented and linear.

SECTION IV.1

LINEAR ADDRESS SPACE SPECIFICATION
(To Be Included)

IV.2

Segmented VAX Overview

Attached is a preliminary specification for extending virtual address
space for the PDP-11. The concepts and content of this document was,
to a large extent, extracted from previous work done by Craig Mudge
and Bill Strecker, and to some extent incorporates the combined advantages of both proposals.
It should be clear that this is a specification for an architecture,
and not an implementation. Some freedoin has therefore been exercised
in creating two segment modes (1 KT compatible, and another with improved
paging characteristics) that may be implemented as either in combined
form, as seperate options, or excluding one or the other entirely. The
combined architecture serve to show their comparisons and differences,
and also serves to introduce compatibility whenever required.
The assumptions used in designing the extension logic were those presented
in the September 13th memo from Craig Mudge, with sane relaxation on the
assumption of KT-11 compatability. Accordingly, some attempt has been
made to clarify the motivation and advantages of a smaller page size than
that presently used on the KT. Additional motivation for the smaller
page size is the good possibility of the paging architecture being applied
to small 11/05 systems, whereby protection would be implemented by a single
segment*page table, thereby not only allowing for better protection on RTll
s h e systems, but also providing the ability for these small systems to
run within a segment on the larger 32bit machines.
The total effort involved in extending the address space of the PDP-11
extends far beyond the effort required to design and build the basic machine. Effects on operating systems, compilers and linkers are significant
if implemented in their full potential. The section dealing with these
effects and related implications of the full implementation will be presented later.

* Previously called 'chapter' by Mudge, 'segment' by Strocker. The
term segment is not consistent with KTll documentation by more consistent
with usage in the computer industry.

PDP 11/VX SPECIFICATION
Overview
The PDP 11 architecture explicitly involves the use of the
general registers for all memory reference address modes.
This characteristic suggests a natural means for extending
the virtual address ability of the machine by simply extending the width of each register to say 32 bits. The concatenation of each register with its extension forms a 32
segmented address space with a logi a1 capability of 2
segments each having a length of 2l' bytes. The PDP 11/VX
central processor is capable of executing existing programs
residing within a segment with additional instructions provided for
control and data transfer among segments.

dit

The translation of the virtual address to the physical address
is managed by the contents of segment tables which point to
page tables whosecontents in turn point to memory locations.
This clasical segmentation /paging architecture combines the
advantages of program construction and protection afforded by
virtual address space segmentation, as well as the advantages
of physical memory allocation and demand paging. The PDP 11/VX
architecture allows for both K T l l compatible segments of lengths
up to 8K bytes, as wellas segments having a smaller fixed size
of 1K bytes.
Appropriate mode bits have been added in the processor status
register (PS) to provide compatibility with existing software
particular concern has been given to interrupt and trap sequences,
as well as segment and page fault recovery techniques. (to be
supplied)
Correlations between expected functional performance/capability
and related implications on the operating systems, canpilers,
linkers and additional hardware requirements are analyzed (to
be supplied).

Formation of t h e V i r t u a l Address

S i n c e a l l P D P - 1 1 memory r e f e r e n c e i n s t r u c t i o n s s p e c i f y one
of the g e n e r a l r e g i s t e r s , the v i r t u a l a d d r e s s i s formed by
c o n c a t e n a t i n g the c o n t e n t s of the e x t e n d e d r e g i s t e r w i t h
the c o n v e n t i o n a l P D P - 1 1 e f f e c t i v e a d d r e s s .
Referencing
f i g u r e 1, the e x t e n d e d r e g i s t e r c o n t e n t s s p e c i f i e s the
segment number and t h e P D P - 1 1 e f f e c t i v e a d d r e s s s p e c i f i e s
the o f f s e t w i t h i n t h e segment.
T h e a d d r e s s f o r m a t i o n can be e x p r e s s e d more f o r m a l l y by

using t h e following notation:
R = 16 b i t g e n e r a r r e g i s t e r as i n t h e c u r r e n t PDP-11
R S = 1 6 b i t e x t e n s i o n of R c a l l e d the segment r e g i s t e r
= concatenation operator

Re = Rs 0 R
= 3 2 b i t extended r e g i s t e r
( ) = c o n t e n t s of

The o p e r a t i o n of the e i g h t a d d r e s s i n g modes i s as f o l l o w s :

mode

operand a d d r e s s 2

R c o n t a i n s operand

A = (Re)

A = (Re)
(R) = (R)

A = ( R s ) O ( (Re))

R = R + A

(R) = (R)
A = ( R s ) o ((Re))

H =

(Rs) 0 (R)

E x i s t i n g PDP-11 i n s t r u c t i o n s w i l l p r o v i d e p r o c e s s i n g of d a t a
and c o n t r o l o f programs w i t h i n a segment. A d d i t i o n a l i n s t r u c t i o n s a r e d e f i n e d t o p r o v i d e d a t a t r a n s f e r and c o n t r o l among
segments.
Load Long ( L L )
opcode: @7 5 R SS
o p e r a t i o n : The 2 word s t a r t i n g a t t h e l o c a t i o n s p e c i f i e d
by SS are used t o l o a d t h e extended r e g i s t e r s p e c i f i e d b y P.
The word p o i n t e d t o by SS i s used t o l o a d t h e segment r e g i s t e r and t h e n e x t word i s used t o load t h e g e n e r a l r e g i s t e r .
I f SS i s of t h e form J3R ( i . e . m o d e @) t h e n t h e e x t e n d e d r e g i s t e r s p e c i f i e d by R i s loaded w i t h c o n t e n t s o f t h e e x t e n d e d
r e g i s t e r s p e c i f i e d by R ' .
The v a l u e of b f o r a u t o i n c r e m e n t
modes Is 4.
I n immediate mode t h e n e x t two words i n l i n e w i t h
t h e n e x t two words i n l i n e w i t h t h e LL i n s t r u c t i o n are used t o
load t h e extended r e g i s t e r .
S t o r e Long (SL)
opcode: $7 6 R DD
o p e r a t i o n : T h e extended r e g i s t e r s p e c i f i e d by R i s l o a d e d
i n t o t h e 2 words s t a r t i n g a t the l o c a t i o n s p e c i f i e d by SS.
The format of t h e 2 words i s a s i n t h e LL i n s t r u c t i o n .
If
DD i s of t h e form @R' t h e n t h e e x t e n d e d r e g i s t e r s p e c i f i e d
by R ' i s loaded w i t h t h e e x t e n d e d r e g i s t e r s p e c i f i e d by R.
I n a u t o i n c r e m e n t and autodecrement modes the v a l u e of A i s
4.

Jump t o S u b r o u t i n e Long (JSL)
opcode: 10 7 R DD
o p e r a t i o n : The 2 word d e s t i n a t i o n s p e c i f i e d by DD i s s a v e d
i n an i n t e r n a l r e g i s t e r .
( I f DD i s of form flR an i l l e g a l
i n s t r u c t i o n t r a p o c c u r s . ) Two w o r d s are pushed on t h e s t a c k .
The f i r s t i s t h e l o w 16 b i t s of t h e e x t e n d e d r e g i s t e r s p e c i f i e d by R ,
The second word c o n t a i n s t h e segment r e g i s t e r speci f i e d by R .
The c o n t e n t s of t h e r e g i s t e r s p e c i f i e d by R are
r e p l a c e d by t h e c o n t e n t s of t h e ( e x t e n d e d ) PC.
The c o n t e n t s o f
t h e PC a r e t h e n r e p l a c e d by t h e c o n t e n t s of t h e i n t e r n a l r e g i s t e r .
R e t u r n from S u b r o u t i n e Long (RSL)
opcode: Jdfl 562 1R
o p e r a t i o n : The c o n t e n t s of t h e ( e x t e n d e d ) PC a r e r e p l a c e u by
t h e c o n t e n t s of t h e extended r e g i s t e r s p e c i f i e d by R.
The
c o n t e n t s of t h c extended r s g i s c e r s p e c i f i e d by R a r e r e p l a c e d
by t h e t o p two words popped from the s t a c k . The f i r s t word
popped r e p l a c e s t h e c o n t e n t s of t h e segment r e g i s t e r s p e c i f i e d
by R; The second word popped r e p l a c e the c o n t e n t s of t h e
g e n e r a l r e g i s t e r s p e c i f i e d by R.
Jump Long (JL)
opcode :
o p e r a t i o n : The c o n t e n t s of t h e PC a r e r e p l a c e d by t h e c o n t e n t s
of t h e d o u b l e word a d d r e s s e d b y DD.

Virtual to Physical Address Translation
There exists two independent motivations for the design of the
address translation logic:
(1) First, the desirability for system and application programs
to be logically divided into independent segments
whereby control over protection, linking, sharing and executability
can be affected at the segment level irrespective of the manner in
which physical memory is allocated and associated.
(2) Second, the desirability for the operating system to physically divide memory into small pages whereby control over memory
allocation, mapping and replacement (demand paging or virtual memory)
can be affected at the physical page level irrespective of the manner
in which the system and application programs are segmented.

Thus, segmentation relates to virtual address management, while
paging relates to physical address management. The requirement
that they co exist within the same architecture has determined
the translation logic described herein.
To a large extent, the design of the KT-11 memory management
unit does not reflect the above motivations (the 4K page size
is too large, and the 32 word block size is too small). Nevertheless, architectural compatibility has been retained while at
the same time, an operational mode (called page mode) has been
provided which adequately meets the above motivations, thereby
eliminating several KT deficiencies. This mode allows for more
efficient allocation of memory and provides the possiblity of
implementing demand paging (virtual memory) by reducing the page
size to 512 words. Since the mode distinctions are applied at
the segment level, both KT and page mode segments can be combined
within a process running on a fully implemented system. Compatibility between the modes relating to access control, statistics
gathering bits, etc., has been applied wherever possible.
Figure 1 has been sectioned into three areas to schematically
describe the address translation mechanism: (1) the logic which
currently exists on the P D P - 1 1 with KTll (enclosed in dashed lines),
(2) the additional logic required for 32 bit segmented address (upper
left), and (3) the additional logic to reduce the page size to that
comensurate with the requirements to facilitate improved physical
memory allocation and demand paging.
The translation of the physical address is accomplished by using
the segment field as an index into a segment table (origined at
a physical location specified by a base register, STBR). The
segment table entry contains access bits, residency bit, KT mode
bit, segment length, and a pointer to the origin of the segment's
page table (origined on an eight word boundary).
The offset of the virtual address contains a page field (3 bits
for KT mode, 6 bits for page mode) and a displacement. The page
field is used as an index into a page table which contains statistics bits, a residency bit, and pointer to the physical page. The
displacement field is used as an index into the physical page to
locate the addressed word. The detailed format of each register
is shown in figure 2.

Note t h a t the c o n t e n t s of the segment t a b l e s r e l a t e t o segment
l e v e l access c o n t r o l , and the c o n t e n t s of the page table r e l a t e s
t o p h y s i c a l memory management.
Note f u r t h e r t h a t these table reside i n p h y s i c a l memory, and are
l o g i c a l l y a c c e s s e d f o r e v e r y memory r e f e r e n c e .
The a c t u a l number
of c o r e a c c e s s e s p e r memory r e f e r e n c e i s s o l e l y a f u n c t i o n of implem e n t a t i o n , t h e r e b y s a t i s f y i n g t h e g o a l of common a r c h i t e c t u r e implem e n t a b l e o v e r a b r o a d range of performance l e v e l s .

Compat i b 1it y

I n o r d e r t o g u a r a n t e e t h a t e x i s t i n g u s e r programs w i l l r u n on
t h e 11/VX machine ( i n an a d d r e s s s p a c e o t h e r t h a n segment z e r o ) ,
a b i t i n t h e Program S t a t u s r e g i s t e r , PS<08), i s a s s i g n e d t o
s p e c i f y X o r non-X mode. When the X m o d e b i t i s s e t , t h e c o n t e n t s
of a l l e x t e n d e d r e g i s t e r s i s t a k e n from R 7 ( P C ) . T h i s a l l o w s an
e x t e n d e d program t o c a l l a non-extended s u b r o u t i n e by a normal

JSR i n s t r u c t i o n .
To e n s u r e t h a t system programs a r e c o m p a t i b l e , a n o t h e r s p a r e b i t
PS
i s used t o c o n t r o l the s t a c k i n g and u n s t a c k i n g o f PCX on
i n t e r r u p t s and RTI, r e t u r n from i n t e r u p t . A l l i n t e r r u p t s are
r e t u r n e d t o P r o c e s s @,Segment$. The i n t e r r u p t v e c t o r h e r e , i n
p a r t i c u l a r PS <09>, c o n t r o l s the s t a c k i n g and u n s t a c k i n g of PCX.

fiqurr 2,

SECTION V

PDP-11 INSTRUCTION SET

(To Be Included)

SECTION V I

WRITABLE CONTROL STORE
( T o B e Included)

SECTION VI1

MULTIPROCESSING CONFIGURATIONS

VII.

MULTIPROCESSING CONFIGURATION

Preliminary Price/Performance Analysis For Multiprocessor
Configurations
-

Preliminary analysis shows that it makes more sense
to consider tightly coupled multiprocessor systems to be
based on large PDP-11/40 and PDP-11/45 systems rather than
small PDP-11/05 systems. The reasons for this involve the
cost of the MCll and DAll with respect to the cost of the
processor, and the fact that a large number of processors
will l i k e l y require memory configurations exceeding 28R.
E o t h the PDP-11/40 and the PDP-11/45 processors are
sufficiently fast so that we can assume that the primary
limitation in processing rate is imposed by the speed of
the UmIBUS accessing memory. Therefore, if we assume that
the processing rate is directly proportional to the rate
of memory accesses, and that each processor randomly accesses
each of M memory banks (true for interleaved memories), then
the effective throu hput of a system comprised of N processors
can be shown to be:

This expression for system performance has been computed
for several configurations and divided by system price to
obtain price/performance values. I have attached several
figures which graphically represent these results. Figure 1
is a plot of Equation 1 showing lines of constant throughput
ratio as a function of the number of processors and the number
of parallel memory banks. Figure 2 shows the system throughput (in units of single processors) as a function of the number
of memory banks, indicating that in configurations where the
number of processors equals the number of memories, the system

,
' r ,

throughput is approximately 60% that of the theoretical maximum. Figure 3 shows a plot of the number of effective CPU's
as a function of the number of actual CPU's for various
memory configurations, operating in both bank and interleaved
modes (Interleaved memory is accomplished by using the least
significant memory address bits as bank addresses, whereas
bank mode is accomplished by using most significant address
bits as bank addresses. In the case of the former, memory
addresses from processors are randomly distributed; whereas
in the case of the latter each processor can execute a program
which is local to each memory bank.).
Figure 4 shows the
price/performance ratio for various multiprocessor configurations as a function of typical single-processor system price.
As is seen, large price/performance gains are realized in large
system configurations. In Figure 5 , w e plotted the same price/
performance data as a function of the total multiprocessor
system price. Comparison of Figures 4 and 5 shows that for an
eight-processor system, a factor of 2 increase in price performance is attained from a $300,000 system whose single-processor
configuration would be priced at roughly $150K.
These price/performance calculations account f o r the
current retail prices for PDP-11/40 systems, and for the
current retail prices for the DA11-F and MC11. In addition,
the performance degradation due to delays imposed by the MCll
is accounted for. Memory contention was computed under the
assumption of random accesses which is a worst case assumption
for interleaved memories. An additional 50% gain in price/
performance can be realized by assuming that processors execute
programs which are local to 16K banks.
A further significant increase in price/performance can
be realized with the use of MOS memory. In this case, the
scheduling algorithm would be designed to schedule particular
processors to tasks which reside in that processor's highspeed memory, requiring that the scheduler be aware and take
advantage of the PDP-11/45 high-speed memory bus. I would
estimate that a 4 CPU system which utilizes this technique
would havo a price/performance ratio approaching 3 : l relative
to a single-processor system selling in the area of S150K.

Regards.

DLN/ehb

attachments
'"Efficiency of a Multi-Contr:l
May, 1970 (report available)

Path Processor," D. L. Nelson

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Figlire 1.

System Throughput Improvement R a t i o

saturation point
f o r N=16 processors

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F .I&ura 2 , Systern Throughput
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A YECON0 ADVANTAGE
OF T H E
MULTIPRUCESSOH S Y S T E M
XS
M O ~ U L A W ' Y , dV MOOULARITY I 3 MEANT T H F 4 8 I L I T V 7 0 C O N F I G U R C
SVSTEMS ;JHICH YPAN A
k I b E RANGE O F
CENTRAL P N C J C F S S I N 6
PERFORMANCE W I T H
ONLY A S I N G L E P R O C E b S O R f 3 E 3 I G N 0 OEC WPS
ALREADY A C h I F v E D SUCH MODULARITY
I& I T S RFAL-TIHE
SYSTFM
SOFTWARE AND
I T IS APPROPWIATE T H A T I T U O E S THE SAMC- T H I N h
FOR THE: R E A L - T I M E HAROWARE S V S T E M S ,

A T H I R U ADVANTAGE I 3 T Y E REOUkfDANrY I h
THF
CENTRAL
PROC€SSING
CAPABILITY,
S).rOULO
AT
L E A S T O N E OF T H I
P R O C E $ S O R S R F M A I N O P E K A T I V F , THE F A I L U R f r OF THE O T H t R 3 W I L L
NOT
CAUSE
THE
SlSTEM
T O CEASE.
F U V C T I O N I h G €.NTIkl.I'Lv,
A V A I L A B I L I T Y 4!;
AN I V ~ O R T A h t ~A S F E C f
CF
OF
THk
M U L T I m C O M P U T E H SYSTFFIS
WHICH
D t C CURRENTLY
S H I P S , ANO A
TRULY MULPIPROCE3SING SYSTEM CAN BE E X P € C f E D T O P R O V I D E bOMt
80QT OF "FAIL-SOF7"'
CAPABILITY,
THE H E A k T OF THE P o P m l 1 MULTIPROCESSOR SYSTEM IS SHAfiEU
MEMORY,
S I N C E THE PROCESSORS RUN I N AN AkONYMOlJS M O D E ,
S Y S T E M F U N C T I O N S ARE EXECUTED W I T H EQUAL E A S E R Y F I T H F k
P R O C E S S O R RUNNIFJG REENTRANT PROGRAMS F R O M THE C O M M O N MEMORY,
AS MPNV TASKS AS P R O C E S S O R S M A Y R €
RUNNING
SIMllLTANtOUSLYp
W I T H E A C H PHOCESSOH HANOLING I T S O k r J I N T E f ? R U P T Y AND I/G
PflOCESSING,
O U P L I C A T E C O P I E S OF S Y S T F M P H O G R A M Y AHE NOT
NEEOEO S I N C E PR6CESSClR L O C K S H A V F 0 F E N AnnFD SO A S T O
PREVENT ON!! PHOCFSSOR P R O M I N T E f i F E P H I N G W I T H ANOTHER W H I L t
C R I T X C A L SYSTEM TARLES A H € b E I N G M O D I F I F D ,
THESE LOCKS
RE[JU1RL ONLY SMALL CHANGES T O THE S T A N I l A R O SOPtWAriE 30 THAT
THE G R O W T H Ilu E X E C U T I V E SIZE IS Y t G L I G I b L E ,

USING C O M M O N T A S K &NO P A U T I T I O N D E S C R T P T O R T A R L E S i
THE
IkDIVIOUAI,,
P H Q C E 8 S O R S WILL E A C H BE A 8 L L T O Er(LCU1E ALL USER
T A S K S AND E X F C U T I Y E REQUESTS,
ALTHOUGH I/O O E V I C E 3 WILL R E
P H V S I C A L L Y C O N N E C T t b T O ONE P H O C E S S O R O R
ANJOTHEM, T H I S
C O N N E C T I O N k I L L 81: TRAN3PARENT T O THt: U S E Y T A S K S # H E S U L T I N G
I N THE L O G I C A L SHARING OF ALL I/O n t V I C E S ,

SECTION VI11

ASCII CONSOLE

VIII.

ASCII CONSOLE

This section represents the collective efforts of the ASCII
Console Committee represented by Small, Medium, Large
11 Engineering, 8 Engineering, and Field Service.
The Committee produced an architectural specification which
all planned consoles will meet (11/05, 11/44*, 11/85, 8A*,
Field Service). Each machine need implement only a subset
of the specification (varying from all to none at all). The
primary purpose of the specification, therefore, is to remove
redundant implementations of common functions.
The Committee did not determine which functions should or
should not be implemented on specific machines. Rather, this
is a function of relevant product managers for the particular
machines, and is based on marketing, cost, and implementation
considerations that clearly lie outside of the Committees
charter and domain.
Some specific issues, relating to consoles, which were not
reconciled include:
A.

Whether or not ASCII console machines should be capable
of remote maintenance (11/05 will have serial consoles
which cannot be controlled remotely).

Whether or not ASCII consoles should facilitate remote
console control in a network for the purpose of remote
program loading, etc.

The alternatives to the use of the ESC character in our
present terminal oriented software.

Consequently, even though the Committee has successfully
removed all apparent redundancies and has provided a consistent framework which relates to all known console functions,
the Committee did not (nor did it try) to reconcile the
diverse product philosophies that will continue to affect
our strategies in the areas of networks, terminal oriented
software, and remote maintenance.

Cancelled

IYTRODUCTION:

THE PUNPOSE OF T H I S S P E C I F I C A T I O N I 3 T O D E F I N E A 3E;HIAL L I N E
SYNTAX AND A B A S I C A S C I I COMMAND SET FOR THE I M P L E f l E N T A T I O N OF A
CPU CONTROL D E V I C E REPLACING THE L I G H T S AND SwITCHE.9 C O N T R O L
THE HESERVED ASCII COMMANDS ARE INTENDED T O PROVIDE A
PANEL,
CORE OF GENERIC OPERATIONS WHO3E PROPERTIES APPLY TO M O S T DEC
PROCESSORS,
P R O V I S I O N I S MADE T O EXPAND T H I S SET I N AN ORD€RLY
FASHION FOR EACH S P E C I F I C CPU OESIGN,
I T I S EXPECTED THAT EACH
CON8OLE IMPLEMENTATION WILL PROVIDE A DlESIGN O t S C R I P T I O N THAT
REFERENCES THE EXACT CPU REGISTERS INVOLVED AND ANY H E S T H I C T I O N S
TWAT HAY APPLY, AATHLR THAN THE GENERAL D E S C R I P T I O N INCLUDED
HITH THE COMMANDS I N T H I S S P E C I F I C A T I O N ,
I N NORHAL OP€RATION A S C I I CONSOLE COMMANDS AH€ MULTIPLEXED

OVER A S E R I A L L I N E SHARED WITH PROGRAM I / O ,
THE PROTOCOL
O F F I N E S THE SEQU€NCE FOR A R B I T R A T I N G THE L I N E MULTIPLEXOR V I A
THE D A T A STREAM (ALTERNATE MODE),
A HARDWARE S N I T C H M A Y ALSO
BE PROVIDE0 WHICH CAN D I S A B L E A R B I T R A T I O N AND FORCE THE DATA
STREAM T O E I T H E R THE CONSOLE OH PROGRAM 110 CONTROLLER,
THE
S E R I A L L I N E PROTOCOL DEFINED HERE A P P L I E S ONLY T O EXCHANGES
WITH THE A S C I I CONSOLE L O G I C .
THE CONSOLE APPEARS TNANSPARENT
EXCEPT FOR THE ESCAPE SEQUENCE WHEN THE L I N F I S I N ALTkRNATE

YODE.

l e 3 E R I A L L I N E PHOTOCOL:
THE S E R I A L L I N E SYNTAX FOR CONSOLE COMMAND I N P U T AND RESPONSE
IS DEFINED I N T H I S SCCTXON,
THE PROTOCOL IS INDEPENDENT OF L I N E
I N F U L L DUPLEX
SPEED OR F U L L DUPLEX/HALF DUPLEX OPERATION,
OPERATION EACH CHARACTER IS ECHOLO AS HECEfVEOp EXCEPT WHFHE
DEFINED OfHEl?wISE BY T H I S SPECIfICATIOfU,
I N HALF D U P L t X
NO CHARACTER IS ECHOED,

1.1 COMMAND FORMAT:
THE COMMAND I N P U T F O R M A T I S AN AHBITHARY NUMBER OF O C T A L D I G I T S
TERMINATED R Y A COMMAND CHARACTER OR COMMAND " S P E C I A L 3 E Q U E ~ C E " e

1.2

I
,----

COMMAND RESPONSE:

THE COMMAND RESPONSE CONSISTS OF: TH€ ECHO OF THE COMMIND
CHARACTER(3) ( F U L L DUPLEX L I N E 0 N L Y ) I THE TRANSLATION OF ANY
NON-PRINTING COMMAND T O A P R I N T A B L E RESPONSEI THE RESPONSE
D A T A (A8 R E Q U I R E D I I AND THE COMMAND ACKNOWLEOG€ ( A S C I I 0 4 8 1 ,
NOTE1 COMMAND. ACKNOWLEDGE
SYMBOL r g n ,

IS REPRESENTCD BY TI4E WFART

M U L T I P L E RESPONSE:

I F A S I N G L E STIMULUS IS REQUIRED T O TRANSMIT SEVERAL
RESPONSES ( A N OUTPUT MACRO), THEN EACH SECONDAWY RESPONSt
MUST BE PRECEDED BY THE ASSOCIA1t;D COMMAND CHARACTER ON
E I T H E R A HD OR FD L X h E e EXAMPLEI ON DETECTION OF A
PROGRAMMED HALT THE NOHNAL HALT RESPONSE MIGHT BE FOLLOWED
0Y A CPU STATUS R[IQUEST COMMAND ( S T ) AUTOflATICALLY,
EX:

*Hfl00010OST12440

l e 2 e l OCTAL D A T A OR NOh~DFSXGNATED A S C I I CHARACTER:
THE O C T A L D I G I T S 0-7 ( A S C I I 68-67) ARE USED FOH NUMERIC O A T A
ONLY,
THE LOW-OHDER THREE B I T S OF THESE CHARACTERS ARL
S H I F T E D I N T O THE RIGHT END OF THE TEMPORARY DATA REGISTER,
THE HIGH OCTAL D I G I T OF T H I 8 REGISTER I S L O S T ,

ANY UNASSIGNED A S C I I CHARACTER I S TREATED A S A "NO-OPERATIONt'
BY THE CONSOLE L O G I C I NOP CHARACTERS M A Y OCCUR ANYlrlHkRE I N
THE COMMAND I N P U T STHEAICII

1.2.2

COMMAND RXTH NO DATA RESPON9El

THE COMYAND I S ACKfUOWLEDG€D A T COMPLETION BY THE TRANSMISSION

OF A SPACE CHARACTER ( A S C I I 1 4 8 1 ,

1.2.3

COMMAND WITH D A T A RESPONSE:

O C T A L DATA I S OUTPUT FOLLOWED BY THE COMMAND 4CKNOWLkDGE
AT COMPLETION,

1 e 2 r 4 ILLEGAL COMMAND1

AN ILLEGAL OPEHATION WILL RESULT I N THE T R A N S M I 8 S I O N OF
A QUESTION M A R K (rscxr 0 7 7 ) FOLLOWEDB Y THE C O H M A W
ACKNOWLEDGE.
EX1

10clr0LlO

1,2,S R E C E I V E LINE ERROPI
THE CHARACTER I N ERROR I S TRANSMITTED W I T H CORRECT P A R I T Y
AND F R A M I N G (FULL DUPLE% 0NLY)r THEN A PLUS SIGN (ASCII U 5 3 )
I 3 TRANSMITTED FOLLOWED BY THE ACKNOWLEDGE.
EX1

EX:

l(d0d@+O
10BOL+o

CFD LINE @.ERROR CHAR t C H 0 )
(HD LINE LmLOC C O P Y OF X M T CHAR)

2,
h

RESERVED CHARACTER38

THIS S P E C I F I C A T I O N E X P L I C I T L Y D E F I N E S TME COMMAND A C T I O N AND
RESPONSE FOR C E R T A I N OF THE A 9 C I I CHARACTERS USED A3 S I N G L k CHARACTER COMMANDS,
CONSOLES IMPLEMENTED UNDER THE TFHMS OF
T H I S J P E C I F I C A T I O N M A Y NOT USE THESE CHAHACTERS F O R ANY
OTHER CONTROL FUNCTION,
I F A PARTICULAR COMMAND CANNOT BE
IMPLEMENTED, T H A T CHARACTER I 9 70 8 E TREATED AS A "NOOPERATION" CNOP) BY THAT CONSOLE,
P R O V I S I O N FOR THE I M P L E MENTATION OF 4 D D I T I O N A L CQU-SPECIFIC COMMANDS 19 MADE THROUGH
THE USE OF THE DOLLAR S I G N ( A S C I I 0 4 4 ) COMMAND D E F I N t O RELOW,
ALL OTHER S I N G L E CHARACTER COMMANDS A S t I M P L I C I T L Y RESERVFD
FOR FUTURE BASIC COMMAND SET EXPANSION,
2,1

ABBREVIATIONS:

2,lal

ADDRESS REGISTER C A R ) I
REGISTER C O N T A I N I N G THE ADDRESS FOR START,€XAMfN€ AND
DEPOS!T OPERATIONS,
EX: P D P / l l ~ B U S ADDRESS REGISTER,
PDP/B=CP MEMORY ADDRES9 R E G I S T t R ,

2.1,2

DATA D I S P L A Y L I N E 8 (DO):
INTERNAL REGISTERS OR MULTIPLEXORS DEFINED BY THE
E X 1 PDP 1 1 / 4 5 O I S P L A Y OATA
CPU DESIGN S P E C I F I C A T I O N ,
MULTIPLEXOR OUTPUT,

2 e l m 3 DEPOSIT FLAG ( D E P I I
R / W STORE B I T THAT I S SET T O ONE TO I N D I C A T E THE PREVIOUS
COMMAND WAS A DEPOSIT OPERATION,
USE0 T O CAUSE A
DEPOSIT-STEP FOR SEQUENTIAL DEPOSIT OPERATIONS,
2e1.4

E F F E C T I V E ADDRESS ( E A 1 1
THE E F F E C T I V E ADDRESS 19 THE CONTENTS OF THE ADDRFSS
REGISTER J U S T I F I E D T O THE NEXT LOW-ORDER CPU STOHAGE
WORD,
THE E F F E C T I V F ADDRESS I S USED T O PERFORM
S T A R T r D E P O S I T AND EXAMINE OPERATIONS,

2 m l e 5 EXAMINE FLAG ( E X M I I
R/W STORE B I T THAT I S SET T O ONE TO I N D I C A T E THE PREVIOUS
COMMAND WAS AN EXAMINE OPERATION,
USED T O CAUSE AN
EXAMINEmSTEP FOR SEQUENTIAL t X A M I N t OPkRATIONS,
2.1,6

O C T A L FLAG ( O C T ) :
R/W STORE B I T THAT I S SET T O ONE T O I N D I C A T E THE LAST
CHARACTER kAS AN OCTAL DATA CHARACTER.
USED TO CLEAR THE
O C T A L T Y P E - I N REGISTER ON THE F I R S T DATA CHAAACTkR
FOLLOWING ANY U9E OF THE REGISTER CONTtNTS,

2e1.7

OPEN FLAG ( 0 P N ) t
R/W STORE B I T THAT I S SET T O ONE T O I N D I C A T E THAT A
UskD T O
MEMORY OR R E G I S T k R LOCATION HAS BEEN EXAMINED,
PERFORM AN I M P L I E D DEPOSIT OF USER I N P U T DATA,

2 e l m 8 PROGRAM COUNTER ( P C I I
REGISTER THAT CONTAIN3 THE ADDRESS OF CURRENT P R O G R A M
EXECUTIOh,
EX1
P D P / l l ~ C O N T E N T S OF R7, PDP/BsCONTENTY
CP MEMORY ADDRESS HEGISTER,

2,1,9

SERIAL OUT (80):
THE S E R I A L L I N E FROM THE A S C I I CONSOLE TO THE CONTROLLING
DEVICE,
M A Y BE A LOCAL TELEPRINTER OR RLYOTE V I A DATA

2 , l o l B SWITCH HEGISTER ( S N ) :
REGISTER USED T O D R I V E THE CPU SWITCH HEGISTER L I N E S ,

2,1,11 TEMPORARY DATA REGISTER CTMP):
REGISTER USED T O PACK O C T A L TYPE-INS,
LOW-ORDER THREE
M I T S OF O C T A L D A T A CHARACTERS ARE S H I F T E D I N T O THE
RIGHT
O C T A L POSITION
AND THE LLFT O C T A L D A T A P O S I T I O N
IS LOST,

2.1.12
C O N D I T I O N A L ACTION [I:
THE ACTION ENCLOSED BY THE BHACKETS IS C O N D I T I O N A L L Y
EXECUTED D t P E N D I h G ON SOME C O N D I T I O N S P E C I F I E D BY A
NOTE,
2 o l o l S CONTENTS OF L O C A T I O N 0 8
I N D I C A T E S A REFERENCE T O THE CONTENTS OF THE REGISTER
OR MEMORY LOCAT!ON ENCLOSED BY THE PARENS,

2,1,14

TRAN8PER DATA * * I
I N D I C A T E S T H E DATA SOURCE ON THE LEFT 13 TRANSFEHRED
T O THE D E S T I N A T I O N ON THE RIGHT,

202 CPU CONTROL P R I M I T I V E S 8
THE FOLLOWING COHYANOS ARE SENT T O THE A S C I I CONSOLE T O
CONTROL THE OPERATION OF THE PROCESSOR,
THESE C O M M A N O S
ARE INTENDED T O REPRODUCE THE LEVEL OF C O N T R O L PROVIDED
BY THE L I G H T S AND SWITCHES CONTROL PAYEL,

ADDRESS REGISTER CONTENTS ARE UNPACKtD TO THE S E H I A L OUT,

2,2,2

C(103) CONTINUE:

C4U3ES CPU T O RESUME EXSCUTING INSTRUCTIONS A T THE ADDRESS
S P E C I F I E D BY THE PROGRAPI COUNTER,
UNCONDITIONALLY R E S E T S
THE HALT F F TO PERMIT CONTINUOUS EXECUTIONI
,---.

2,2.3

D(104)

DEPOSIT;

THE CONTENTS OF THE TEMPORARY REGISTER ARE 9TOHED I N THE
E F F E C T I V E ADDRESS REFERENCED BY THE ADDRESS REGISTER,
THE
SECOND AND SUCCESSIVE COMMANDS WILL DEPOSIT I N SEQUENTIAL
LOCATIONS,
I F THE CONTENTS OF THE TEMPORANY REGISTER
ARE NOT ALT€RED BY N€W O C T A L O A T A , THE PREVIOUS CONTENTS
HILL B E USED,
[ E A + l a> EA 1 # l
(TMP) >> EA
0
OCT;
0 *> OPNl

COND W l :

2,2,4

E(105)

0 >+ EXM)

1 a s DEP

OEP.1
EXAMINE:

THE CONTENT3 OF THE E F F t C T I V E ADDRESS REPEHENCLD BY THE
ADDRESS REGISTER ARE UNPACKED T O THE S E R I A L OUT,
THE
SECOND AND SUCCES3IVE EXAMINE COMMANDS WILL EYAMINE
SEQUENTIAL LOCATIOFtS,
[ E A + l >> EA I #l
(EA)
SO
0 >+ O C T i
1 >* OPNl

1 * a EXM;

0 sa DEP

CON0 # i t EXMm1

CAU8ES CPU T O STOP EXECUTING INSTRUCTIONSo WHEN HALT
COMMAND' I 8 COMPLETED THE CONTENTS OF THE PROGRAM
COUNTER ARE UNPACKED T O THE S E R I A L OUT,

CAU8ES A S Y S T E H RESET,
ANALOGOUS T O PDP/8 C L t A R
OPERATION OR P D P / l l STAPT W I T H HALT SWITCH ON,
FOLLOWING THE I N I T I A L I Z E THE PROGRAM COUNTLR I S

UNPACKED T O THE S E R I A L OUT.

** so

(PC)
0

** O C T l

** OPNl

+* E X H l

0 *> OEP

L ( l 1 4 ) LOAD ADORESSI

2.2.7

LOADS THE CONT€NTS OF THE TEMPORARY REGISTER I N T O
ADDRESS REGISTER,
(TMP) *+ AR
0
OCTt 0

** O P Y l

** EXM)

** DEP

MC115) READ DATA DISPLAY#

2.2.8

THE STATE OF THE D A T A DISPI.AY REGISTER OR MULTIPLEXOR
13 UNPACKED TO THE S E R I A L OUT,
T H I S COMMAND PROVIDES
A MEANS OF REAOING THE CONTENTS OF CPU ERROR OR
OPERATIONAL INFORMATION R E G I S T t R S k I T H A 9 I N G L E COMMANO
CHARACTER*

N ( 1 1 6 ) EXECUTE NEXT I N S T R U C T I O N I

2.2.9

CAUSES THE CPU T O t X E C U T E A SINGLE I N S T R U C T I O N AND THEN
HALTI
THE HALT F F IS FORCED 9ET B Y T H I S COHMAND,
AT
COMPLETION OF THE COMMANO THE CONTENTS OF THE PROGRAM
COUNTER ARE OUTPUT T O THE S E R I A L OUT,

2o2.10

R(122) READ S N I T C H REGISftRt

SWITCH REGI8TEf4 C O N T t N T S ARE UNPACKED T O

2.2011

THE S E R I A L OUT,

S(1231 STARTI

CAUSES A SYSTEM AESET AND TRANSFERS THE CONTENTS OF TFE
ADDRESS REGISTER TO THE PROGRAM COUNTER,
T H I S COMMAND
ALWAY3 RESETS THE HALT FF T O PERMIT THE CPU T O R E G I N
EXECUTING INSTRUCTIONS FOLLONING TME RE8ETe

2.2012

w(127)

IruRITt SWITCH R E G I S T E R I

THE CONTENTS OF THE TEMPORARY R E G I S T t R ARE T H A N S F E H R t b
T O THE SWITCH REGISTER.

(TMP)
S)u
0
OCTl 0

** O P N l

@ * a EXM)

** DEP

2.3

CPU M A C R O COMYANDSI

THE FOLLOWING COMMANDS ARE CRE4TCD BY C O M R I N I N G THE
P R I M I T I V E COMMANDS I N T O SEQUENCES AND D E F I N I N G A S I N G L E
THESE MACROlS M A Y
CHARACTER TO INVOKE THE SEQUENCE,
N O T ME DUPLICATED BY TRANSMITTING THE S4ME SEQUENCE O V E R
THE SERIAL L I N E ,
THE M A C R O 8ET PROVIDCS A HIGHEH L E V E L
SYNTAX S I M I L A R T O THE ON-LINE DEBUGGING TECHNIQUE FOUNO
I N P D P / 1 1 SYSTEM SOFTW4RE. I N ADDITION, THE COMM4NDS
WIVE BEEN D E F I N E D I N SUCH A W4Y THAT THE SHARING OF THE
S E R I A L L I N E BETWEEN THL CONSOLE AND P R O G R A M 110 IS MAD€
R E L A T I V E L Y TRAkSPARENT T O TME USER,

G(107) G o t

2.3.1

CAUSES THE S E R I A L L I h E T O SWITCH TO PROGRAM 110 MODEi
THEN JTARTS PROGRAM EXECUTION AT THE ADORE83 I N THE
TEMPORARY REGISTER,
T H I S COMMAND IS ANALOGOU3 T O T H t
START PRIMITIVE,
SEOI Z p Lt S
0 >> O C T )
0 a s OPNt

2.3.2

P(120)

0 s* E X M )

+> DEP

PHOCECDi

CAUSE9 PROGRAM T O RESUME EXECUTION 4ND SNITCHES L I N E
T O PROGRAM 1/0 MOOE.
THE HALT SWITCH I S FORCED RESET
T O P E R M I T CONTXNUOIIS EXECUTION SIMILAR TO TWE CONTINUE
PRIMITIVE,

SEQ: 2, c
fd >> O C f t

0 >* O P N l

E X A V I N E S THE LOCATION
TEMPORARY H€GISTER.

EXMI

0 *> OEP

AT TH€ E F F t C T I V E ADDHESS I N T H t

DePosxta A N Y O C T A L D A T A ENTERED SINC~ THE LOCATION
OPENED, THEN CLOSES THE LOCATION.
I f N O LOCATION
OPEN THEN A LINE FEED IS 8ENTo

2.3.5
4

LF(013)

WAS

OPEN SEQUENTIAL L O C A T I O N I

D E P O S I T S ANY O C T A L DATA ENTERED S I N C E THE LOCATION W A S
OPENED, THEN CLOSES THE L O C A T I O N .
THE NEXT SEQUENTIAL
LOCATION IS TH€N OPENED AND f H € AOORCSS ANU CONT€NTS
ARE SENT T O THE S E R I A L OUT.

2.3.6

~ ( 1 3 6 ) OPEN PREVIOUS LOCATION:

DEPOSITS A N Y OCTAL DATA ENTERED S I N C E THE L O C A T I O N W A S
OPENED, THEN CLOSES THE LOCATION,
THE P R E V I O U S
SEQUENTIAL LOCATION 19 f H € N OPENED AkD THE ADOHESS AND
CONTENTS ARE SENT TO THE S E R I A L OUT.

CONO ~ 1 :0 ~ ~ 8 1
COND rr21 0 ~ ~ 8 1

2.4

CONSOLE CONTROL COMMANDS:

THE FOLLOWING COMMANDS ARE USED T O CONTROL THE A S C I I
CONSoLf LOGIC,
A9 W I T H THE CPU COMMAND S E T , ALL UNIMPLEMENTE0 COMMANDS MUST RE TREATED A S NOP19,

THE CONSOLE L O G I C M A Y BE CONNECTED 3IMULTANEOUSLY TO A
LOCAL TELEPRINTER AND A COMMUNICATIONS D E V I C E USED FOR
R E M O T E CONSOLE A C T I V I T Y ,
THE REMOTE/LOCAL S N I T C H ENABLE8
E I T H E R PORT T O O R I G I N A T E CONSOLE COMMANDS EXCLUSIVELY,

2,401 S(044)

S P E C I A L SEQUENCE8

THE DOLLAR S I G N I S U8€D A9 THE F I R S T CHARACTER I N A TbO
(OR MORE) CHARACTER SEQUENCE FOR PROCESSOR-bEPtNDFNT
COMMANDS,
THE COMPLETE SEQUfNCE I S TREATED A S A S I N G L E
ANY CONTROL FUNCTION NOT PHOVIOED
CONSOLE OR CPU COMMAND,
FOR E X P L I C I T L Y I N T H I S S P E C I F I C A T I O N MUST 8E IMPLEHENTED
A S A SPECZAL SEQUEFtCEr
ANY CHARACTER EXCEPT THE NUMERICS (0bB-067) M A Y BE USED
(FOLLOWING THE S ) T O D E F I N E S P E C I A L SEQUENCE COMMANDS,
THE NUMERICS R E T A I N THE SAME O E F I N I N T I O N AS I N THE
RESERVED CHARACTER SET AND PAY BE USE0 T O SUPPLY D A T A
FOR A S P E C I A L SEQUENCE COMMCND,

EX:
\

2.4.2

S T FOR READ CPU STATUS D I S P L A Y

@ ( 1 0 0 ) CLEAR O C T A L INPUT:

T H 1 3 COMMAND I S U S t b TO CLEAR THE O C T A L T Y P E - I h HEGISTER,
THERE I S NO RUB-OUT P R O V I S I O N AND THL ENTIWE I N P U T NUMtIEH
MUST BE HE-TYPED,

204.3

ZC132) 8ET 3 L I OPERATION8

SWITCHES THE A S C I I OATA STREAM TO THE PROGRAM S E S I A L
L I N E CONTROLLER.

2.4.4
-..

THE CONSOLE ESCAPE SEQUENCE SWITCH€$ THE A s C I I DATA
THE ESCAPE SEQUENCE
STREAM T O THE CONSOLE L O G I C ,
CHARACTERS ARE NOT ECHOED AS RECEIVED ( F D ) AND A H €
NOT PASSED TO THE PROGRAM,
WHEN THE ESCAPE SEQUENCE I 3
COMPLETE AN "*CONM MLSSAGE IS SENT TO T H t L I N E ,
IF
T H E CHARACTER FOLLOWING THE ESCAPE I S NOT TH€ CONSOLk
SWITCH CHARACTER, THAN B O T H CHARACTERS ARF THANSFEHRED
T O THE RUNNING PROGRAM I N A "BURSTfl,
2.4.5

ESC 0 (33~061d) ESCAPE T O CONSOLE!

0-7

(60-67)

OCTAL DATA1

THE OCTAL D I G I T S ARE USED T O TRANSFER B I N A K Y DATA OVER
T H t THREE LOW-ORDER B I T S OF I N P U T D I G I T S
THE S E R I A L L I N E ,
A R k S H I F T E D T O THE LOW OCTAL D I G I T OF THE TEMPORARY
REGISTER,
THE H I G H OCTAL D I G I T 18 LOST,
CONSOLE RESPONSES
ARE UNPACKED I N T O O C T A L D I G I T S FUR TRANSMISSION OVER THE
SERIAL LINE.
2.4.6

~ C ( 0 0 3 ) I N I T I A L I Z E CONSOLE MODE!

CAUSES THE CONSOLE TO E X I T F R O M "LOGINt' MODE O H " S P E C I A L
SEQUENCE" MODE,
RETURNS ALL CONSOLE FLAGS TO A NOHMALIZtO
STATE AND M A Y BE DEFINED T O I N I T I A L I Z E CONYOLE CONTROL
OPTION REGISTERS.
2.4.7
\

~ E ( 0 0 5 ) READ CPU 101

CONSOLE RESPONDS WITH A UNIQUE ALPHA-NUMERIC SEQUENCE
ASSIGNED T O THE PARTICULAR CONSOLE IMPLFMENTATION,

EX! ~ E 0 0 1 1 4 5 / 0 0 4 5 @ 3 -REPRESENTING

AN 11/45 CPU
AND DATE* 74-323 C J U L I A N )

2.4.8

L-

~ L ( 0 1 4 ) S f T L O G I N MOOLI

T H I S COMMAND LOGICALLY CONNECTS TWE LOCAL TELEPRINTER
CHARACTERS M A Y
S E R I A L 1 / 0 TO THE REMOTE E I A I N T t R F A C E ,
BE EXCHANGED BETHEEN THE L O C A L TELEPRINTER AND THE R E M O f t
SYSTEM,
THE CONSOLE WILL IGNORE ALL CHARACTERS EXCHANGED
OVER THE L I N E U N T I L THE L I N E WASTER SENDS THE I N I T I A L I Z E
CONSOLE COMMAND T O E X I T L O G I N MODE,
2.4.9

~ T ( 0 2 4 ) TEST S H I F T R E G I S T E R I

CdN30I.E L O G I C TRANSMITS A SYNCH SEQUENCE C O N S I S T I N G OF THE
COMMAND ECHO (FD L I N E ) , A NULL CHARACTER AND 4 RUBOUT. * THE
S H I F T REGISTER OPERATION IS THEN V E R I F I E D k3Y TRANSMITTING A
MORD OF A L L ZEROS FOLLOWED BY A W O R O OF ALL ONES T O THE S E H I A L
OUT.

3 . ERRORS:
T Y E CONSOLE LOGIC
DETECTS T W O c L A a s E s OF ERROR: ~ 1 4 0 s ~
THAT RESULT FROM A USER COMMAND AND THOSE DFTECTED BY
THE CONSOLE L O G I C INDEPENOENT OF U S t R A C T I V I T Y .
3.1 COMMAND EXECUTION ERRORS1
COMMAND EXECUTION LRRORS ARE DETLCTED I N CONSOLE M o r ) € AND
DO NOT ALTER THE S T A T E OF THL CPU,
THE RLSPONSE T O A
COMMAND EXECUTION ERROR I 3 A S I N G L E CHARACTER FOLLONLD
BY 4 COMMAND ACKNOWLEDGE ( A S C I I 164@),

3.1.1

PC077) I L L E G A L :

COMMAND COULD NOT BE I N I T I A T E D BtCAUSE OF A CPU OR
CONSOLE CONDITION.
EX1 DEPOSIT WHILE CPU HUNNING
OR THE I N P U T OF NUMERIC I3 AS DATA,

3.1.2

+ ( 0 5 3 ) L I N E ERROR:

COMMAND dAS RECEIVED WITH A FRAMING, OVERRUN O H
P A R I T Y ERROR AND ABORTED,
CONSOLE DESIGN S P E C I F I C A T I O N
SYOULD D E T A I L WHICH ERRORS ARE DETECTED.

3.1.3

Ir(04J) CPU RESPONSE

TIME-OUT:

THE CONSOLE MUST PROVIDE AN INTEHNAL TIME-OUT FOR
CPU COMMAND T H A T STOPS CONSOLE A C T I V I T Y U N T I L THE
RESPONDS,
I F THE CPU F A I L S T O RESPOND A TIME-OUT
TYk COMMAND I S ABORTED AND THE CONSOLE RETURNS T O

ANY
CPU
OCCUHS,
THE READY S f A T t .

302 OPERATION ERRORS8
THE CONSOLE L O G I C DETECTS C E R T A I N ERRORS I N PROGKAM OP
COMMUNICATION L I N E OPERATION,
THESE ERRORS RESULT I N A
MESSAGE WHICH I S NORMALLY D I R E C T t D TO THE S E R I A L L I N E
MASTER,
ALL AUTOMATIC RESPONSES AHE PRECEDED W I T I I AN
ASTERISK, THE S E R I A L L I N E MUST BE L E F T I N THE SAME STATE
(CONSOLEIPROGRAM I/O)
AS VrHEN THE EHROR WAS DETECTED.

3.2.1

PROGRAMMED HALT:

I F THE PROGRAM EXECUTES A H A L T p THE NORMAL HALT MESSAGE
I S P R E F I X E D WITH AN ASTERISK 4ND SENT T O THE 3 t R I 4 L OUT.
TH€ MESSAGE GOES T O T H t CONSOLE MASTER DETERMINED BY THE
REMOTE/LOCAL SWITCH,

3.202 CAHRIER L O S T I

WHEN THE CON30LE IS I N REMOTE O P L R A T I O N AND CAHRIER HA9
UEEN R E C E I V f O FROM A REMOTE STATION, LOSS OF CARRIER
N I L L FORCE THE L I N E T O "LOGIN'' MOOE AND SEND 4 MESSAGE
T O THE L 0 C A L TkLEPHINTER.
THE MESSAGE MUST B E G I N
WITH " * C A R n AND 8 E TERMINATED BY AN ACKNOWLEDGL CODE
(QJ401, NON-SPACE CYARACTERS M A Y BE APPENDED T O THE
" * C A R " FOR C L A R X T Y ,

3o2.3

WATCH DOG T I M E R ERROR:

THE CONSOLE L O G I C M A Y C O N T A I N A ON€-SHOT WHICH IS
RETRIGGEAEO UNDER CPU P R O G R A M CONTROL,
THE T I M E - O U T
ERROR MUST BE ENA8LED/DISABLED UNDER S E R I A L L I N E C O N T R O L .
If THE TIMER I S ENABLED AND THE RUNNING PROGRAM F A I L S T O
UPDATE, THEN AN ERROR MESSAGE I S SENT T O T H t S E H I A L L I N t
MASTER,
THE ME8SAGE M U S T B E G I N M I T Y ' ' * W ' '
4ND BE TERMINATED
BY AN ACKNOWLEDGE C O D E ( e 4 0 ) .
A D D I T I O N A L NON-SPACE CHARACTLRS
M I Y BE APPENDED T O THE " * W H F O R C L A R I T Y ,
THCL S E R I A L L I N E
IS L E F T I N PROGRAM 1 / 0 MODE,

ENfEHeOt 11-19=74
BY:

STEVE SKELTON

PROTOCOL SUMMAWY

1 DCSCRIPTION

CHAR

11-19-74

CIFSPONSE

*<*COHVFNT+++

(AIGOpNL
POINL

‘ - ”

C P U CONTHOL P R I H I T I V E 3 8
DISPLAY ADDRESS
CONTINUE

DEPOSIT

EXAMINE
HALT
1 N I T I A L I L E CPU
L O A 0 ADDfiESS
R E A D O A T A DISPLAY
NEXT
R C A D SWITCH HEGISTER
START
WRITE SWITCH REGISTER

A
*C
*O

*E
H
*I
*L
Y
*N

H
*S
IrJ

CPU CONTROL M A C R O 8 8
PROCEED
OPEN L O C A T I O N
CLOSE LOCATION
OPEN NEXT LOCATION
OPEN PREV L O C I T I O N
i

tAJ/[DJO

CRp

tAI/tbIo

LF OPN P R E V L O C

3 P E C I b L SEQUENCE
CLEAR OCT4L DATA
8ET PPOG 1 / 0 MODE
3 C T CONSOLC MOO€
OCTAL D 4 T 4

INITIALIZE CONSOLE
‘ 1

[A]/[D]O

ii
E

NLo

CONSOLE CONTROL COMMANDS1

1
r”

*CR
*LF

Z I LI S t NL
Z I C I NL
LI A I E
(TMP)
E A r CLOSE
C R , LF OPN NXT L O C

REA0 CPU I D

SfT L O G I N MODE
--J
TEST

S H I F T REGISTER
ERRORS8

ILLEGAL
CINE ERROR
.WESPONSE TIME-OUT
PROGRAM HALT
C A R R I E R LOST
WATCH DOG T I M E H ERROR

ILLEGAL

U?Q

ACTION

L*O

F R A M E , P A P I T Y i ClVEHWUN
NO CPU RESPOhSt:

DUO

NLt*H(AIQ

NLp*CARo
NLp*WO

REMOTE O P E H I T I O N ONLY
NO P H O G A C T I V I T Y

NOTES 1) o.CONS0l.F
ACKNOkLEDGE ( A S C I I Lo401
2 ) t laADOI?ESS [ A l p OR 0 4 f A [Ol €KCHANG€
J ) NLmNEW L I N E I C R p L F )
4 ) *.ILLkGAL
WhEN CPU IS RUNNING