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1970

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Document:	A new Architecture for Mini-Computers - The DEC PDP-11
Order Number:	XX-A3AB5-C5
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Pages:	19
Original Filename:	New%20Architecture%20PDP11%20SJCC%201970%20c.pdf

OCR Text

Reprinted from AFIPS - Conference Proceedings, Volume 36
Copyright @ by AFlPS Press
Montvale, New Jersey
07645

A new architecture for mini-computersThe DEC PDP-11
by G. BELL,* R. CADY, H. McFARLAND, B. DELAGI, J. O’LAUGHLINandR. NOONAN
l?i&l
Equipment Corporation
Maynard, Massachusetts

and
W. WULF
Carnegit+Mellon University
Pittsburgh, Fcriiisylvnnia

INTRODUCTION
The mini-computer** has a wide variety of uses: communications controller; instrument controller; largesystem pre-processor ; real-time data acquisition
systems . . .; desk calculator. Historically, Digital
Equipment Corporation’s PDP-8 Family, with 6,000
installations has been the archetype of these minicomputers.
I n some applications current mini-computers have
limitations. These limitations show up when the scope
of their initial task is increased (e.g., using a higher
level language, or processing more variables). Increasing
the scope of the task generally requires the use of
more comprehensive executives and system control
programs, hence larger memories and more processing.
This larger system tends to be at the limit of current
mini-computer capability, thus the user receives
diminishing returns with respect to memory, speed
efficiency and program development time. This limita-

tion is not surprising since the basic architectural
concepts for current mini-computers were formed in
the early 1960’s. First, the design was constrained by
cost, resulting in rather simple processor logic and
register configurations. Second, application experience
was not available. For example, the early constraints
often created computing designs with what we now
consider weaknesses :
1. limited addressing capability, particularly of

larger core sizes
2. few registers, general registers, accumulators,
index registers, base registers
3. no hardware stack facilities
4. limited priority interrupt structures, and thus
slow context switching among multiple programs
(tasks)
5. no byte string handling

6. no read only memory facilities
7. very elementary 1/0 processing

* Also a t Carnegie-Mellon University, Pittsburgh, Pennsylvania.
** The PDP-11 design is predicated on being a member of one (or more) of the micro, midi, mini, . . ., maxi (computer name) mark&.

We will define these names as belonging to computers of the third generation (integrated circuit to medium scale integrated circuit
technology), having a core memory with cycle time of .5 2 microseconds, a clock rate of 5 10 Mhz ..., a single processor with interrupts and bually applied to doing a particular task (e.g., controlling a memory or communications lines, pre-proceasing for a larger
system, process control). The specialized names are defined as follows:
maximum addressable
primary memory (words)
miW0

mini
midi

8K
32 K
128 K

processor and
memoty coat
(1970kilodollars)

word

length
(bits)
8

-5

657

---

processor
slate
(WWW

dutn types

2
2-4

4-16

integers, words, boolean vectors
vectors (Le., indexing)
double length floating point
(occasionally)

658

Spring Joint Computer Conference, 1970

8. no larger model computer, once a user outgrows a

particular model
9. high programming costs because users program
in machine language.
I n developing a new computer the architecture
should a t least solve the above problems. Fortunately,
in the late 1960’s integrated circuit semiconductor
technology became available so that newer computers
could be designed which solve these problems a t low
cost. Also, by 1970 application experience was available
to influence the design. The new architecture should
thus lower programming cost while maintaining the
low hardware cost of mini-computers.
The DEC PDP-11, Model 20 is the first computer
of a computer family designed to span a range of functions and performance. The Model 20 is specifically
discussed, although design guidelines are presented
for other members of the family. The Model 20 would
nominally be classified as a third generation (integrated
circuits), 16-bit word, 1 central processor with eight
16-bit general registers, using two’s complement
arithmetic and addressing up to 216 eight bit bytes of
primary memory (core). Though classified as a general
register processor, the operand accessing mechanism
allows it to perform equally well as a 0-(stack),
1-(general register) and 2-( memory-to-memory) address
computer. The computer’s components (processor,
memories, controls, terminals) are connected via a
single switch, called the Unibus.
The machine is described using the PMS and ISP
notation of Bell and Newel1 (1970) a t different levels.
The following descriptive sections correspond to the
levels: external design constraints level; the PMS
level-the
way components are interconnected and
allow information to flow; the program level or ISP
(Instruction Set Processor)-the
abstract machine
which interprets programs; and finally, the logical
design level. (We omit a discussion of the circuit
level-the PDP-11 being constructed from TTL integrated circuits.)

memory word length for the Model 20 is 16 bits,
although there are 32- and 48-bit instructions and 8and 16-bit data. Other members of the family might
have up to 80 bit instructions with 8-, 16-, 32-and
48-bit data. The internal, and preferred external
character set was chosen to be 8-bit ASCII.
Range and performance

Performance and function range (extendability)
were the main design constraints; in fact, they were
the main reasons to build a new computer. DEC
already has (4) computer families that span a range*
but are incompatible. I n addition to the range, the
initial machine was constrained to fall within the
small-computer product line, which means to have
about the same performance as‘a PDP-8. The initial
machine outperforms the PDP-5, LINC, and PDP-4
based families. Performarce, of course, is both a
function of the instruction set and the technology.
Here, we’re fundamentally only concerned with the
instruction set performance because faster hardware
will always increase performance for any family.
Unlike the earlier DEC families, the PDP-11 had to
be designed so that new models with significantly
more performance can be added to the family.
A rather obvious goal is maximum performance for
a given model. Designs were programmed using benchmarks, and the results compared with both DEC and
potentially competitive machines. Although the selling
price was constrained to lie in the $5,OOO to $lO,OOO
range, it was realized that the decreasing cost of logic
would allow a more complex organization than earlier
DEC computers. A design which could take advantage
of medium- and eventually large-scale integration was
an important consideration. First, it could make the
computer perform well; and second, it would extend
the computer family’s life. For these reasons, a general
registers organization was chosen.
Interrupt response

DESIGN CONSTRAINTS
The principal design objective is yet to be tested;
namely, do users like the machine? This will be tested
both in the market place and by the features that are
emulated in newer machines; it will indirectly be
teated by the life span of the PDP-11 and any offspring.

Since the PDP-11 will be used for real time control
applications, it is important that devices can communicate with one another quickly (Le., the response
time of a request should be short). A multiple priori’ty
level, mted interrupt mechanism was selected; additional priority levels are provided by the physical
position of a device on the Unibus. Software polling is

Word lf?ngth
The most critical constraint, word length (defined
by IBM) was chosen to be a multiple of 8 bits. The

* PDP-4,7,9, 15 family; PDP-5, 8, 8/S, 8/I, 8/L family; LINC,
PDP-8/LINC, PDP-12 family; and PDP-6, 10 family. The
initial PDP-1 did not achieve family status.

The DEC PDP-11

unnecessary because each device interrupt corresponds
to a unique address.
Software
The total system including software is of course the
main objective of the design. Two techniques were
used to aid programmability: first benchmarks gave a
continuous indication as to how well the machine
interpreted programs; second, systems programmer
continually evaluated the design. Their evaluation
considered : what code the compiler would produce;
how would the loader work; ease of program relocability; the use of a debugging program; how the
compiler, assembler and editor would be coded-in
effect, other benchmarks; how real time monitors
would be written to use the various facilities and
present a clean interface to the users; finally the ease
of coding a program.
Modularity
Structural flexibility (sometimes called modularity)
for a particular model was desired. A flexible and
straightforward method for interconnecting components
had to be used because of varying user needs (among
user classes and over time). Users should have the
ability to configure an optimum system based on cost,
performance and reliability, both by interconnection
and, when necessary, constructing new components.
Since users build special hardware, a computer should
be easily interfaced. As a by-product of modularity,
computer components can be produced and stocked,
rather than tailor-made on order. The physical structure is almost identical to the PMS structure discussed
in the following section; thus, reasonably large building
blocks are available to the user.
Microprogramming
A note on microprogramming is in order because of
current interest in the “firmware” concept. We believe
microprogramming, as we understand it (Wilkes, 1951),
can be a worthwhile technique as it applies to processor
design. For example, microprogramming can probably
be used in larger computers when floating point data
operators are needed. The IBM System/360 has
made use of the technique for defining processors that
interpret both the System/36O instruction set and
earlier family instruction sets (e.g., 1401, 1620, 7090).
I n the PDP-11 the basic instruction set is quite straightforward and does not necessitate microprogrammed

659

interpretation. The processor-memory connection is
asynchronous and therefore memory of any speed can
be connected. The instruction set encourages the user
to write reentrant programs; thus, read-only memory
can be used as part of primary memory to gain the
permanency and performance normally attributed to
microprogramming. In fact, the Model 10 computer
which will not be further discussed has a 1024-word
read only memory, and a 128-word read-write memory.

Il nderstandability
Understandability was perhaps the most fundamental constraint (or goal) although it is now somewhat
less important to have a machine that can be quickly
understood by a novice computer user than it was a
few years ago. DEC’s early success has been predicated on selling to an intelligent but inexperienced
user. Understandability, though hard to measure, is
an important goal because all (potential) users must
understand the computer. A straightforward design
should simplify the systems programming task; in the
case of a compiler, it should make translation (particularly code generation) easier.
PDP-11 STRUCTURE AT THE PMS LEVEL*
Introduction
PDP-11 has the same organizational structure as
nearly all present day computers (Figure 1). The
primitive PMS components are : the primary memory
(Mp) which holds the programs while the central
processor (Pc) interprets them; io controls (Kio) which
manage data transfers between terminals (T) or secondary memories (Ms) to primary memory (Mp); the
components outside the computer a t periphery (X)
either humans (H) or some external process (e.g.,
another computer) ; the processor console (T. console)
by which humans communicate with the computer
and observe its behavior and affect changes in its
state; and a switch (S) with its control (K) which
allows all the other components to communicate with
one another. I n the case of PDP-11, the central logical
switch structure is implemented using a bus or chained
switch (S) called the Unibus, as shown in Figure 2.
Each physical component has a switch for placing
messages on the bus or taking messages off the bus.
The central control decides the next component to

* A descriptive (blockdiagram) level (Bell and Newell, 1970) to
describe the relationshipof the computer components: processors
memories, switches, controls, links, terminals and data operators.

660

Spring Joint Computer Conference, 1970

h u u n umer
procesmor

secondary

terminals
Tele-

e.&,

periphery

h u u n uaer

or
other process

Convantionel block d i a g r r

'€us *Ot.tIon

Figure 1-Conventional

lines of the hierarchical structure common to present
day computers. The single bus makes conventional
and other structures possible. The message processes
in the structure which utilize S(Unibus) are:
1. The central processor (Pc) requests that data
be read or written from or to primary memory
(Mp) for instructions and data. The processor
calls a particular memory module by concurrently specifying the module's address, and the
address within the modules. Depending on whether the processor requests reading or writing,
data is transmitted either from the memory to
the processor or vice versa.
2. The central processor (Pc) controls the initialization of secondary memory (Ms) and terminal (T)
activity. The processor sets status bits in the
control associated with a particular Ms or T, and
the device proceeds with the specified action
(e.g., reading a card, or punching a character into
paper tape). Since some devices transfer data
vectors directly to primary memory, the vector
control information (i.e., the memory location
and length) is given as initialization information.
3. Controls request the processor's attention in the
form of interrupts. An interrupt request to the
processor has the effect of changing the state of
the processor; thus the processor begins executing
a program associated with the interrupting
process. Note, the interrupt process is only a
signaling method, and when the processor interruption occurs, the interruptee specifies a unique
address value to the processor. The address is a
starting address for a program.
4. The central processor can control the transmission
of data between a control (for T or Ms) and
either the processor or a primary memory for
program controlled data transfers. The device
signals for attention using the interrupt dialogue
and the central processor responds by managing
the data transmission in a fashion similar to
transmitting initialization information.

block diagram and PMS diagram
of PDP-11

use the bus for a message (call). The S (Unibus)differs
from most switches because any component can pommunicate with any other component.
The types of messages in the PDP-11 are along the

Unibu. control p a c k p d w i t h Pc

Figure 2-PDP-11

physical structure PMS diagram

The DEC PDP-11

5. Some device controls (for T or Ms) transfer data
directly to/from primary memory without central
processor intervention. In this mode the device
behaves similar to a processor; a memory address
is specified, and the data is transmitted between
the device and primary memory.
6. The transfer of data between two controls, e.g., a
secondary memory (disk) and say a terminal/T.
display is not precluded, provided the two use
compatible message formats.
As we show more detail in the structure there are,
of course, more messages (and more simultaneous
activity). The above does not describe the shared
control and its associated switching which is typical of
a magnetic tape and magnetic disk secondary memory
systems. A control for a DECtape memory (Figure 3)
has an S('DECtape bus) for transmitting data between

M~(#o:~; 'DECtape)

S 'DECtape bus;

concurrency: 1

Figure 4-Conventional

hierarchy computer structure

components (options). I n Figure 5 the Unibus characteristics are surpressed. (The detailed properties of the
switch are described in the logical design section.)

Extensions to increase performance
The reader should note (Figure 5 ) that the important
limitations of the bus are: a concurrency of one, namely,
only one dialogue can occur a t a given time, and a
maximum transfer rate of one 16-bit word per .75psec.,
giving a transfer rate of 21.3 megabits/second. While
the bus is not a limit for a uni-processor structure, it is
a limit for multiprocessor structures. The bus also
imposes an artificial limit on the system performance
when high speed devices (e.g., T V cameras, disks) are

Kio ( 'DECt a p e

.+,

Unibbs

661

i T Teletype; Model 33.35 ASR;
f u l l duplex; 10 char/sec;
char set: ASCII; 8 b i d c h a r

- T paper tape; reader;

Figure 3-DECtape

[

100 char/sec; 8 bitichar

eontrol switching PMS diagram

- T paper tape; punch;

[

100 char/.cc;

a single tape unit and the DECtape transport. The
existence of this kind of structure is based on the
relatively high cost of the control relative to the cost
of the tape and the value of being able to run concurrently with other tapes. There is also a dialogue at the
periphery between X-T and X-Ms which does not use
the Unibus. (For example, the removal of a magnetic
tape reel from a tape unit or a human user (H) striking
a typewriter key are typical dialogues.)
All of these dialogues lead to the hierarchy of present
computers (Fig. 4). I n this hierarchy we can see the
paths by which the above messages are passed
(Pc-Mp; Pc-K; K-Pc; Kio-T and Kio-Ms; and Kio-Mp;
and, at the periphery, T-X and T-Ms; and T.console-H).

8 bidchar

-l4 secondary/r; fixed head disk;

[

16 b/u; 32768 u; i . r a t e ; 66 ps/u;

t.access: 0 - 3 4 msec.
(60 c y c l e clak)-L(60
c y c l e line)-

Model 20 implementation

Figure 5 shows the detailed structure of a uniprocessor, Model 20 PDP-11 with its various

Figure 5-PDP-I

I structure and characteristics PMS diagr.am

662

Spring Joint Computer Conference, 1970

Figure 8 shows a multiprocessor system with two
central processors and three Unibusses. Two of the
Unibus controls are included within the two processors,
M
M
and the third bus is controlled by an independent conS
trol unit. The structure also has a second sixitch to
allow either of two processors (Unibusses) to access
common shared devices. The interrupt mechanism
a. 1 port
allows either processor to respond to an interrupt and
similarly either processor may issue initialization
information on an anonymous basis. A control unit is
S needed so that two processors can communicate with
I
one another; shared primary memory is normally used
b. 4 port
to carry the body of the message. A control connected
to two Pc's (see Figure 8) can be used for reliability;
either processor or Unibus could fail, and the shared
Figure 6 - 1 and 4 port memory modules PMS diagram
Ms would still be accessible.

transferring data to multiple primary memories. On a
larger system with multiple independent memories the
supply of memory cycles is 17 megabits/second times
the number of modules. Since there is such a large
supply of memory cycles/second and since the central
processor can only absorb approximately 16 megabits/
second, the simple one Unibus structure must be
modified to make the memory cycles available. Two
changes are necessary: first, each of the memory modules
have to be changed so that multiple units can access
each module on an independent basis; and second, there
must be independent control accessing mechanisms.
Figure 6 shows how a single memory is modified to have
more access ports (i,e., connect to 4 Unibusses).
Figure 7 shows a system with 3 independent memory
modules which are accessed by 2 independent Unibusses. Note that two of the secondary memories and
one of the transducers are connected to both Unibusses.
It should be noted that devices which can potentially
interfere with Pc-Mp accesses are constructed with
two ports; for simple systems, the two ports are both
connected to the same bus, but for systems with more
busses, the second connection is to an independent bus.

Higher performance processors
Increasing the bus width has the greatest effect on
performance. A single bus limits data transmission to
21.4 megabits/second, and though Model 20 memories
are 16 megabits/second, faster (or wider) data path
width modules will be limited by the bus. The Model
20 is not restricted, but for higher performance processors operating on double word (fixed point) or triple
word (floating point) data two or three accesses are
required for a single data type. The direct method to
improve the performance is to double or triple the
primary memory and central processor data path
widths. Thus, the bus data rate is automatically
doubled or tripled.
For 32- or 48-bit memories a coupling control unit
is needed so that devices of either width appear isomorphic to one another. The coupler maps a data

r? Pc

T...

MP -1
c

f...

UJ...

... I

&...T...

&ne

initialiuticm

P,c K('Unibus)

T...

ye...

data'ttansfers

and interrupt
rssages

'K.('Unibur)
*S('UnLbus Multiple bua ,to s-le
bue coupler;
f r a : 2 hibum; to: 1 Unibus)
'
I
( 'Rocassor to processor coupler)
4&(duplex)

Figure 7-Three Mp, 2 S('Unibus) structure PMS diagram

Figure 8-Dual' Pc multiprocessor system PMS diagram

The DEC PDP-11

request of a given width into a higher- or lower-width
request for the bus being coupled to, as shown in
Figure 9. (The bus is limited to a fixed number of
devices for electrical reasons; thus, to extend the bus
a bus repeating unit is needed. The bus repeating
control unit is almost identical to the bus coupler.) A
computer with a 48-bit primary memory and processor
and 16-bit secondary memory and terminals (transducers) is shown in Figure 9.
In summary, the design goal was to have a modular
structure providing the final user with freedom and
flexibility to match his needs. A secondary goal of the
Unibus is open-endedness by providing multiple busses
and defining wider path busses. Finally, and most
important, the Unibus is straightforward.

THE INSTRUCTION SET PROCESSOR (ISP)
LEVEL-ARCHITECTURE*

Introduction, background and design constraints
The Instruction Set Processor (ISP) is the machine
defined by hardware and/or software which interprets
programs. As such, an ISP is independent of technology
and specific implementations.
The instruction set is one of the least understood
aspects of computer design; currently it is an art. There
is currently no theory of instruction sets, although
there have been attempts to construct them (Maurer,
1966), and there has also been an attempt to have a
computer program design an instruction set (Haney,
1968). We have used the conventional approach in
this design: first a basic ISP was adopted and then
incremental design modifications were made (based on
the results of the benchmarks).**

* The word architecture has been operationally defined (Amdahl,
Blaauw and Brooks, 1964) as “the attributes of a system as seen
by a programmer, i.e., the conceptual structure and functional
behavior, as distinct from the organization of the data flow and
controls, the logical design and the physical implementation.”
** A predecessor multiregister computer was proposed which
used a similar design process. Benchmark programs were coded
on each of 10 “competitive” machines, and the object of the
design was to get a machine which gave the best score on the
benchmarks. This approach had several fallacies: the machine
had no basic character of its own; the machine was difficult to
program since the multiple registers were assigned to specific
functions and had inherent idiosyncrasies to score well on the
benchmarks; the machine did not perform well for programs other
than those used in the benchmark test; and finally, compilers
which took addvantage of the machine appeared to be difficult
to write. Since all “competitive machines” had been hand-coded
from a common flowchart rather than separate flowcharts for each
machine, the apparent high performance may have been due to
the flowchart organization.

663

Although the approach to the design was conventional, the resulting machine is not. A common classification of processors is as zero-, one-, two-, three-, or
three-plus-one-address machines. This scheme has the
the form:
op 11, 12, 13, 14
where 11 specifies the location (address) in which to
store the result of the binary operation (op) of the
contents of operand locations 12 and 13, and 14 specifies
the location of the next instruction.
The action of the instruction is of the form:

11 t 12 op 13; goto 14
The other addressing schemes assume specific values
for one or more of these locations. Thus, the oneaddress von Neumann (Burks, Goldstine and von
Neumann, 1946) machines assume 11 = 12 = the
and 14 is the location following that of
the current instruction. The two-address machine
assumes 11 = 12; 14 is the next address.
Historically, the trend in machine design has been
to move from a 1 or 2 word accumulator structure as
in the von Neumann machine towards a machine with
accumulator and index register(s).* As the number of
registers is increased the assignment of the registers to
specific functions becomes more undesirable and
inflexible; thus, the general-register concept has
developed. The use of an array of general registers in
the processor was apparently first used in the firstgeneration, vacuum-tube machine, PEGASUS (Elliott
et al., 1956) and appears to be an outgrowth of both
1- and 2-address structures. (Two alternative structures-the
early 2- and 3-address per instruction
computers may be disregarded, since they tend to
always access primary memory for results as well as
temporary storage and thus are wasteful of time and
memory cycles, and require a long instruction.) The
stack concept (zero-address) provides the most efficient

Ms...

T...

coupler;

Figure 9-Computer

with 48 bit Pc, Mp with 16 bit Ms, T
PMS diagram

* Due in part to needs, but mainly technology which dictates how
large the structure can be.

664

Spring Joint Computer Conference, 1970

access method for specifying algorithms, since very
little space, only the access addresses and the operators,
needs to be given. I n this scheme the operands of an
operator are always assumed to be on the “top of the
stack”. The stack has the additional advantage that
arithmetic expression evaluation and compiler statement parsing have been developed to use a stack
effectively. The disadvantage of the stack is due in
part to the nature of current memory technology. That
is, stack memories have to be simulated with random
access memories, multiple stacks are usually required,
and even though small stack memories exist, as the
stack overflows, the primary memory (core) has to be
used.
Even though the trend has been toward the general
register concept (which, of course, is similar to a two
address scheme in which one of the addresses is limited
to small values), it is important to recognize that any
design is a compromise. There are situations for which
any of these schemes can be shown to be “best”. The
IBM System/360 series uses a general register structure, and their designers (Amdahl, Blaauw and Brooks,
1964) claim the following advantages for the scheme:
1. Registers can be assigned to various functions:
base addressing, address calculation, fixed point
arithinetic and indexing.
2. Availability of technology makes the general
registers structure attractive.
The System/360 designers also claim that a stack
organized machine such as the English Electric K D F 9
(Allmark and Lucking, 1962) or the Burroughs B5000
(Lonegran and King, 1961) has the following disadvantages :

registers concurrently. A set of truly general purpose
registers should also have additional uses. For example,
in the DEC PDP-10, general registers are used for
address integers, indexing, floating point, boolean
vectors (bits), or program flags and stack pointers. The
general registers are also addressable as primary
memory, and thus, short program loops can reside
within them and be interpreted faster. It was observed
in operation that PDP-10 stack operations were very
powerful and often used ((accounting for as many as
20% of the executed instructions, in some programs,
e.g., the compilers.)
The basic design decision which sets the PDP-11
apart was based on the observation that by using
truly general registers and by suitable addressing
mechanisms it was possible to consider the machine as
a zero-address (stack), one-address (general register) ,
or two-address (memory-to-memory) computer. Thus,
it is possible to use whichever addressing scheme, or
mixture of schemes, is most appropriate.
Another important design decision for the instruction
set was to have only a few data types in the basic
machine, and to have a rather complete set of operations for each data type. (Alternative designs might
have more data types with few operations, or few data
types with few operations.) In part, this was dictated
by the machine size. The conversion between data
types must be easily accomplished either automatically
or with 1 or 2 instructions. The data types should
also be sufficiently primitive to allow other data types
to be defined by software (and by hardware in more
powerful versions of the machine). The basic data
type of the machine is the 16 bit integer which uses
the two’s complement convention for sign. This data
type is also identical to an address.

1. Performance is derived from fast registers, not the

way they are used.
2. Stack organization is too limiting and requires
many copy and swap operations.
3. The overall storage of general registers and stack
machines are the same, considering point #2.
4. The stack has a bottom, and when placed in
slower memory there is a performance loss.
5. Subroutine transparency is not easily realized
with one stack.
6. Variable length data is awkward with a stack.

A formal description of the basic instruction set is
given in Appendix 1 using the ISPL notation (Bell
and Newell, 1970). The remainder of this section will
discuss the machine in a conventional manner.

We generally concur with points 1, 2, and 4. Point 5 is
an erroneous conclusion, and point 6 is irrelevant (that
is, general register machines have the same problem).
The general-register scheme also allows processor
implementations with a high degree of parallelism since
instructions of a local block all can operate on several

The primary memory (core) is addressed as either
216 bytes or 215 words using a 16 bit number. The
linear address space is also used to access the inputoutput devices. The device state, data and control
registers are read or written like normal memory
locations.

PDP-11 model 20 instruction set (basic instruction set)

Primary memory

The DEC PDP-11

General register

The general registers are named: R[O:7](15:0)*;
that is, there are 8 registers each with 16 bits. The
naming is done starting (at the left with bit 15 (the
sign bit) to the least significant bit 0. There are synonyms for R[6] and R[7]:
Stack Pointer/SP(15:0) := R[6](15:0)
used to access a special stack which is used to
store the state of interrupts, traps and subroutine calls
Program Counter/PC(15:0) := R[7](15:0)
points to the current instruction being interpreted. It will be seen that the fact that PC is
one of the general registers is crucial to the
design.
Any general register, R[O:7], can be used as a stack
pointer. The special Stack Pointer (SP) has additional
properties that force it to be used for changing processor
state interrupts, traps, and subroutine calls (It also
can be used to control dynamic temporary storage
subroutines.)
In addition to the above registers there are 8 bits
used (from a possible 16) for processor status, called
PS(15.0) register. Four bits are the Condition Codes
(CC) associated with arithmetic results; the T-bit
controls tracing; and three bits control the priority of
running programs Priority (2: 0). Individual bits are
mapped in PS as shown in Appendix 1.

665

powers of two (shift). Since the address integer size is
16 bits, these data types are most important. Byte
length integers are operated on as words by moving
them to the general registers where they take on the
value of word integers. Word length integer operations
are carried out and the results are returned to memory
(truncated).
The floating point instructions defined by software
(not part of the basic instruction set) require the
definition of two additional data types (of length two
and three), i.e., double word (d.w.) and triple (t.w.)
words. Two additional data types, double integer
( d i ) and triple floating point (t.f. or f ) are provided
for arithmetic. These data types imply certain additional operations and the conversion to the more
primitive data types.
Address (operand) calculation

There are two data lengths in the basic machine:
bytes and words, which are 8 and 16 bits, respectively.
The non-trivial data types are word length integers
(w.i.); byte length integers (by .i); word length boolean
vectors (w.bv), i.e., 16 independent bits (booleans) in
a 1 dimensional array; and byte length boolean vectors
(by.bv). The operations on byte and word boolean
vectors are identical. Since a common use of a byte is
to hold several flag bits (booleans), the operations can
be combined to form the complete set of 16 operations.
The logical operations are: “clear,” “complement,”
“inclusive or,” and “implication” (x 3 y or i x v y).
There is a complete set of arithmetic operations for
the word integers in the basic instruction set. The
arithmetic operations are : add, subtract, multiply
(optional), divide (optional), compare, add one, subtract one, clear, negate, and multiply and divide by

The general methods provided for accessing operands
are the most interesting (perhaps unique) part of the
machine’s structure. By definiqg several access methods
to a set of general registers, to memory, or to a stack
(controlled by a general register), the computer is able
to be a 0, 1 and 2 address machine. The encoding of
the instruction Source (S) fields and Destination (D)
fields are given in Fig. 10 together with a list of the
various access modes that are possible. (Appendix 1
gives a formal description of the effective address
calculation process.)
It should be noted from Figure 10 that all the common access modes are included (direct, indirect, immediate, relative, indexed, and indexed indirect) plus
several relatively uncommon ones. Relative (to PC)
access is used to simplify program loading, while
immediate mode speeds up execution. The relatively
uncommon access modes, auto-increment and autodecrement, are used for two purposes: access to a
stack under control of the registers* and access to
bytes or words organized as strings or vectors. The
indirect access mode allows a stack to hold addresses
of data (instead of data). This mode is desirable when
manipulating longer and variable-length data types
(e.g., strings, double fixed and triple floating point).
The register auto increment mode may be used to
access a byte string; thus, for example, after each
access, the register can be made to point to the next
data item. This is used for moving data blocks, searching for particular elements of a vector, and bytestring operations (e.g., movement, comparisons, editing).

* A definition of the ISP riotat,ion used here may be found in
Appendix 1.

*Note, by convention a stack builds toward register 0, and when
the stack crosses 4008, a stack overflow occurs.

Data types and primitive operations

Spring Joint Computer Conference, 1970

666

s ('11

Id1

10 9

(

4
d.

the result is placed at Destination/D. For single
operand instructions (unary operators) the instruction
action is D t u D; and for two operand instructions
(binary operators) the action is D + D b S (where u
and b are unary and binary operators, e.g., 1,- and
- , x , /, respectively. Instructions are specified
by a 16-bit word. The most common binary operator
format (that for operations requiring two addresses)
is shown below.

'bit

bit

1
dr

resister specification I[r]
defer ( i n d i r e c t ) mddress b i t
10
11

-- e (00

R[r];

I[r]; next I[r] +eiil

N r l . Rtrl -.I,

n a t 112)
indexed with next word)

12 11

The following access d e s cen be specified:

6 5

0 direct-to a register. I[=]

1 indir.ct-to

a 1egisc.r.

I[=] for address of data

- use r e g i s t e r as address. then
3 l u t o ~ ~ ~ ~ ~ n i e ~ : ' ~(pop)
~ 6 i- sdte fae ~
r
4 auto dacrmment via ragistmr (push) - d e c r e m t register. then u u

2 euto increment via r e g i s t e r (pop)

r e g i s t e r as addrass
5 auto decre-nt
indirect

- decrement register. then

The other instruction formats are given in Figure 12.

use r e s i s t e r as the

Instruction interpretation process

address of the addream of data

- next f u l l is the data
- next f u l l is the address of dete
d i r e c t indexed - use next f u l l
indexed w i t b .[TI
address of data
i n h n d uith l[r]
d i r e c t indexed - i n d i r e c t - uae next f u l l

2 i r r d i a t e date

3 d i r e c t data
6

wrd

(FPC)

(rPC)

wrd

ward

as tba

addresm of tb. address of data
6 r e l a t i v e access

- next f u l l w r d p l u s ?C is the address (FK)

7 r e l a t i v e i n d i r e c t access

next f u l l vord plus ?C is the address of the

address of data (rR)
'address i n c r a t l a i value is 1 or 2

The instruction interpretation process is given in
Figure 13, and follows the common fetch-execute
cycle. There are three major states: (1) interruptingthe PC and PS are placed on the stack accessed by
the Stack Pointer/SP, and the new state is taken from
an address specified by the source requesting the trap
or interrupt; (2) trace (controlled by T-bit)-essentially one instruction a t a time is executed as a trace

Figure 10-Address ca1culatio.n formats

This addressing structure provides flexibility while
retaining the same, or better, coding efficiency than
classical machines. As an example of the flexibility
possible, consider the variations possible with the most
trivial word instruction MOVE (see Figure 11). The
MOVE instruction is coded BS, it would appear in
conventional Paddress, 1-address (general register)
and 0-address (stack) computers: The two-address
format is particularly nice for MOVE, because it
provides an efficient encoding for the common operation: A t B (note, the stack and general registers are
not involved). The vector move A[I] t B(1) is also
efficiently encoded. For the general register (and
1-address format), there are about 13 MOVE operations that are commonly used. Six moves can be
encoded for the stack (about the same number found
in stack machines).
Instruction formats

There are several instruction decoding formats
depending on whether 0, 1, or 2 operands have to be
explicitly referenced. When 2 operands are required,
they are identified as Source/S and Destination/D and

Figure 1 1 - W n g

for the MOVE instruction to compare with
conventional machines

The DEC PDP-11

B h r y arithmetic aod l o g i c a l o p e r a t i m a :
form: D t S b D
example:

Breach ( r e l a t i v e ) operators:
BEP (:

10 000 000

brop

001

0 ooo l o o

I D

n[sr] m sC.ck. emter subroutine a t D + PC

lie. o p e r a t i m a :

Iop code 1

form: ST c f
e u q l e : W T (:
'lot.:

031s) (2 + (PC c P C + o f f s e t ) ) :

PC c D + Pc

Jump t o a u b r o u t h :
save

I offact]

brop

- -

- D) - megab

(CC,D t Il X 2); s h i f t l e f t

2 brop c m d i t l m lprs (PC +FC + o f f a e t ) ;

example:

form:

(:-uop=OOoo1oiiOO) + (CC,D +

ASL (:~uop=OOO00110011)

Jup:

I D 1'

Lrll

D t u D;

examples:

form:

I S

ADD (:=bo~=0010) + (CC.D t m s ) ;

Utury arithmetic aod l o 8 i c a l operation:
form:

bor

instructim

them i n a t r u e t i m a are a11 1 word.

0) + (IUII + 0 ) ;

D and/or S M y each require 1

a d d i t i o n a l i m d i a t e data or addream word.

Thus i o a t r u c t l m . can

be 1 , 2, or 3 wrds I-.

Figure 12-PDP-11 instruction formats (simplified)

667

trap occurs after each instruction, and (3) normal
instruction interpretation. The five (lower) states in
the diagram are concerned with instruction fetching,
operand fetching, executing the operation specified by
the instruction and storing the result. The non-trivial
details for fetching and storing the operands are not
shown in the diagram but can be constructed from the
effective address calculation process (Appendix 1). The
state diagram, though simplified, is similar to 2- and
3-address computers, but is distinctly different than a
1 address (1 accumulator) computer.
The ISP description (Appendix 1) gives the operation of each of the instructions, and the more conventional diagram (Fig. 12) shows the decoding of instruction classes. The ISP description is somewhat incomplete; for example, the add instruction is defined as:
S); addition
ADD (:= bop = 0010) + (CC,D t D
does not exactly describe the changes to the Condition
Codes/CC (which means whenever a binary opcode
[bop] of OOlOz occurs the ADD instruction is executed
with the above effect). I n general, the CC are based
on the result, that is, Z is set if the result is zero, N if
negative, C if a carry occurs, and V if an overflow was
detected as a result of the operation. Conditional
branch instructions may thus follow the arithmetic
instruction to test the results of the CC bits.

Examples of addressing schemes
Use as a stack (zero address) machine
Figure 14 lists typical zero-address machine instructions together with the PDP-11 instruct,ions which
perform the same function. It should be noted that
translation (compilation) from normal i n k expressions
to reverse Polish is a comparatively trivial task. Thus,
one of the primary reasons for using stacks is for the
evaluation of expressions in reverse Polish form.
Consider an assignment statement of the form
D-A+B/C
which has the reverse Polish form
DABC/+

and would normally be encoded on a stack machine
aa follows
load stack address of D
load stack A
load stack B
load stack C

/
Figure 13-PDP-11 instruction interpretation process
state diagram

Store

668

Spring Joint Computer Conference, 1970

for performing the same operations. The most useful
instruction is probably the MOVE instruction because
it does not use the stack or general registers. Unary
instructions which operate on and test primary memory
are also useful and efficient instructions.

p l u . addrams valru A m .tack
load stack from -y
by s t u k

address specified

l w d stack from rmory locatim A
stor. stack a t -wry

d d r a s s specified

by stack

store stack u -ry

locatim A

duplicate top of s t u k

+ , add 2 top data of s t m k t o a t u k
-,X. f ; subtract. u l t i p l y , divida

Extensions of the instruction set for real (floating point)
arithmetic

-;negate top data of stack
clear top data of mtuk

v; “inclu.ive orn 2 top data of stack “end“
2 top data of stack

-;c a p l e r n t top of s u c k
test top of .tack ( s e t branch indieatore)

brmcb m W i c a t o r
Jtap mconditioly1

add addremeed l o c a t i m A t o top of stack
(not cfor stack r c h i n c ) equivalent
to: 1o.d stack, add -p
top 2 stack data

resat stack locatim t o n
A,

“md“ 2 top stack data

‘Stack pointer I u s been arbitrarily wed as register 110 for t h i s example.

Figure 14-Stack

computer instructions and equivalent
PDP-I1 inst,ructions

However, with the PDP-11 there is an address method
for improving the program encoding and run time,
while not losing the stack concept. An encoding improvement is made by doing an operation to the top
of the stack from a direct memory location (while
loading). Thus the previous example could be coded
as :
load stack B
divide stack by C
add A to stack
store stack D
Use as a one-address (general register) machine

The PDP-11 is a general register computer and
should be judged on that basis. Benchmarks have
been coded to compare the PDP-11 with the larger
DEC PDP-IO. A 16 bit processor performs better
than the DEC PDP-10 in terms of bit efficiency, but
not with time or memory cycles. A PDP-11 with a 32
bit wide memory would, however, decrease time by
nearly a factor of two, making the times essentially
comparable.

The most significant factor that affects performance
is whether a machine has operators for manipulating
data in a particular format. The inherent generality
of a stored program computer allows any computer by
subroutine to simulate another-given enough time
and memory. The biggest and perhaps only factor
that separates a small computer from a large computer
is whether floating point data is understood by the
computer. For example, a small computer with a
cycle time of 1.0 microseconds and 16 bit memory
width might have the following characteristics for a
floating point add, excluding data accesses:
programmed :

250 microseconds

programmed (but special normalize
and differencing of exponent
instructions) :

75 microseconds

microprogrammed hardware :

25 microseconds

hardwired :

2 microseconds

It should be noted that the ratios between programmed and hardwired interpretation varies by
roughly two orders of magnitude. The basic hardwiring
scheme and the programmed scheme should allow
binary program compatibility, assuming there is an
interpretive program for the various operators in the
Model 20. For example, consider one scheme which
would add eight 48 bit registers which are addressable
in the extended instruction set. The eight floating
registers, F, would be mapped into eight double length
T w Address Commuter
B to A

A c B; transfer

-. /

A +A*;

add

A c -A; ncaata
A c A v 8 ; ineluaive or
A c- A; DOC

Jwp mcaditimed
Test A, and trmatcr t o 8

Use as a two-address machine

Figure 15 lists typical two-address machine instructions together with the equivalent PDP-11 instructions

Figure 1.3-Two

address computer instructions and equivalent
PDP-11 instructions

The DEC PDP-11

(32 bit) registers, D. I n order to access the various
parts of F or D registers, registers FO and Fl are
mapped onto registers RO to R2 and R3 to R5.
Since the instruction set operation code is almost
completely encoded already for byte and word length

binary ops
bop'

data, a new encoding scheme is necessary to specify
the proposed additional instructions. This scheme adds
two instructions: enter floating. point mode and execute
one floating point instruction. The instructions for
floating point and double word data would be:

floating point/f

and double word/d

FMOVE
FADD
FSUB
FMUL
FDIV
FCMP

DMOVE
DADD
DSUB
DMUL
DDIV
DCMP

FNEG

DNEG

/
compare

669

unary ops
uop'

LOGICAL DESIGN OF S(UN1BUS) AND PC
The logical design level is concerned with the physical implementation and the constituent combinatorial
and sequential logic elements which form the various
computer components (e.g., processors, memories,
controls). Physically, these components are separate
and connected to the Unibus following the lines of the
PMS structure.

Bus control

Most of the time the processor is bus master fetching
instructions and operands from memory and storing
results in memory. Bus mastership is determined by
the current processor priority and the priority line
upon which a bus request is made and the physical
placement of a requesting device on the linked bus.

Unibus organization
Figure 16 gives a PMS diagram of the Pc and the
entering signals from the Unibus. The control unit for
the Unibus, housed in Pc for the Model 20, is not
shown in the figure.
The PDP-11 Unibus has 56 bi-directional signals
conventionally used for program-controlled data transfers (processor to control) , direct-memory data transfers (processor or control to memory) and control-toprocessor interrupt. The Unibus is interlocked; thus
transactions operate independent of the bus length
and response time of the master and slave. Since the
bus is bidirectional and is used by all devices, any
device can communicate with any other device. The
controlling device is the master, and the device to
which the master is communicating is the slave. For
example, a data transfer from processor (master) to
memory (always a slave) uses the Data Out dialogue
facility for writing and a transfer from memory to
processor uses the Data I n dialogue facility for reading.

Figure 16-PDP-11 Pc structure

670

Spring Joint Computer Conference, 1970

The assignment of bus mastership is done concurrent
with normal communication (dialogues).
lj nibus dialogues

Three types of dialogues use the Unibus. All the
dialogues have a common protocol which first consists
of obtaining the bus mastership (which is done concurrent with a previous transaction) followed by a
data exchange with the requested device. The dialogues
are: Interrupt; Data I n and Date In Pause; and Data
Out and Data Out Byte.
Interrupt

Interrupt can be initiated by a master immediately
after receiving bus mastership. An address is transmitted from the master to the slave on Interrupt.
Normally, subordinate control devices use this method
to transmit an interrupt signal to the processor.
Data in and data in pause

These two bus operations transmit slave's data
(whose address is specified by the master) to the
master. For the Data I n Pause operation data is read
into the master and the master responds with data
which is to be rewritten in the slave.

memory holds most of the 8-word processor state
found in the ISP, and the 8 bits that form the Status
word are stored in an %bit register. The input to the
adder-shift network has two latches which are either
memories or gates. The output of the adder-shift
network can be read to either the data or address
parts of the Unibus, or back to the scratch-pad array.
The instruction decoding and arithmetic control are
less regular than the above data and state and these
are shown in the lower part of the figure. There are
two major sections: the instruction fetching and
decoding control and the instruction set interpreter
(which in effect defines the ISP). The later control
section operates on, hence controls, the arithmetic
and state parts of the Pc. A final control is concerned
with the interface to the Unibus (distinct from the
Unibus control that is housed in the Pc).

CONCLUSIONS
In this paper we have endeavored to give a complete
description of the PDP-11 Model 20 computer at four
descriptive levels. These present an unambiguous
specification a t two levels (the PMS structure and the
ISP), and, in addition, specify the constraints for the
design at the top level, and give ths reader some idea
of the implementation a t the bottom level logical
design. We have also presented guidelines for forming
additional models that would belong to the same
family.

Data out anddata out byte

These two operations transfer data from the master
to the slave at the address specified by the master.
For Data Out a word at the address specified by the
address lines is transferred from master to slave. Data
Out Byte allows a single data byte to be transmitted.
Processor logical design
The Pc is designed using TTL logical design components and occupies approximately eight 8" X 12"
printed circuit boards. The organization of the logic is
shown in Figure 17. The Pc is physically connected to
two other components, the console and the Unibus.
The control for the Unibus is housed in the Pc and
occupies one of the printed circuit boards. The most
regular part of the Pc, the arithmetic and state section,
is shown at the top of the figure. The 16-word scratchpad memory and combinatorial logic data operators,
D(shift) and D(adder, logical ops), form the most
regular part of the processor's structure. The 16-word

ACKNOWLEDGMENTS
The authors are grateful to Mr. Nigberg of the technical publication department at DEC and to the
reviewers for their helpful criticism. We are especially
grateful to Mrs. Dorothy Josephson at CarnegieMellon University for typing the notation-laden
manuscript .

REFERENCES
1 R H ALLMARK

J R LUCKING
Design of an ardhmdic unit incorporathng a nesting stme
Proc IFIP Congress pp 694-698 1962
2 G M AMDAHL G A BLAAUW F P BROOKS J R
Architecture of the IBM Syatem/360
IBM Journal Research and Development Vol8 No 2 pp
87-101 April 1964
3 C G BELL A NEWELL
Computer structures
McGraw-Hill Book Company Inc New York In press 1970

The DEC PDP-11

4 A W BURKS H H GOLDSTINE J VON NEUMANN
Preliminary discussion of the logical design of an electronic
compding instrument, Part I I
Datamation Vol 8 No 10 pp 36-41 October 1962
5 W S ELLIOTT C E OWEN C H DEVONALD
B G MAUDSLEY
The design philosophy of Pegasus, a quantity-production
Computer
Proceedings I E E E Pt,. B 103 Supp 2 pp 188-196 1956
6 F M HANEY
Using a computer to design computer instruction sets
Thesis for Doctor of Philosophy degree College of
Engineering and Science Department of Computer Science
Carnegie-Mellon University Pittsburgh Pennsylvania May
1968

671

7 W LONERGAN P KING
Design of the B6000 system
Datamation Vo17 No 5 pp 28-32 May 1961
8 W D MAURER
A theory of computer instructions
Journal of the ACM Vol 13 No 2 pp 226-23.5 April 1966
9 S ROTHMAN
R/W 40 data processing system
International Conference on Information Processing and
Auto-math 59 Ramo-Wooldridge (A division of Thompson
Ram0 Wooldridge Inc) Los Angeles California June 1959
10 M V WILKES
The best way to design an automatic calculating machine
Report of Manchester University Computer Inaugural
Conference July 1951 (Manchester 1953)

APPENDIX 1
DEC PDP-11 instruction set processor Description (in ISPL*)
The following description is not a detailed description of the instructions. The description m i t s the trap behavior of
unimplemented instructions, references to non-existent primary memory and io devices, SP (stack) overflow, and power
failure.
Primary Memory State
M/Mb/Memory [0 :216- 13(7 :0)
(byte memory)
M~[O:2~~-1](15:0) : = M[0:216-1](7:0)
(word memory mapping)
Processor State (9 words)
(word general registers)
R/Registers[O:7)(15:0)
SP(15:O) : = R[6](15:0)
(stack pointer)
PC(15:O) : = R[7](15:0)
(program counter)
*ISP NOTATION
Although the ISP language has not been described in publications, its syntax is similar to other languages. The language is inherently
interpreted in parallel, thus to get sequential evaluation the word “next” must be used. Italics are used for comments. The following
notes are in order:
a : = f(. .)
equivalence or substitution process used for name and process substitution. For every occurrence of
~,f(. .) replaces it.

a+(.

. .)

Replacement operator; the contents in register a are replaced by the value of the function.

an array of words of two dimensions 2 and 4096; each word has 16 bits denoted 15, 14, 13, . . ., 1, 0

(a:b),

Denotes a range of characters a, a

Ic:d

Array designation c, c

a+b;

equivalent to ALGOL if a then b

“next”

sequential interpretation

+ 1. . . .,b to base n. If n is not given, the base is 2.

+ 1, . .., d

instruction declaration, e.g.,
ADD (: = bop = 0010)
(CC, D +D S)

defines the “ADD” instruction, assigns it a value, and gives its operation. ADD is executed when
bop = 001%.Equivalent to:
ADD+(CC,D+D+S)
where
ADD: = (bop = 0010) bop has been previously declared

concatenation, consider the combined registers as one

I -/subtract/negate I X/multiply I //divide I A /and I v /or I d / n o t I @/exclusive or I =/equal/> /greater
than I 2 I < I 5 I # I modulo I etc.)

operators: = (+/add

672

Spring Joint Computer Conference, 1970

PS(15: 0)
Priority/P(2:0) : = PS(7:5)

CC/Condition,Codes(3:0)

: = PS(3:O)

Carry/C : = CC(0)
Negative/N : = CC(3)
Zero/Z : = CC(2)
Overflow/V : = CC(1)
Trace/T : = ST(4)
Undefined(7:O) : = PS(15:S)
Run
Wait

Instruction Format
(Bit assignments used in the various instruction formats)
i/instruction( 15:0)
bop(3:O) : = i(15: 12)
uop(15:6) : = i(15:6)
brop(15:8) : = i(15:S)
sop(15:6) : = i(15:6)
s/source(5:0) : = i ( l l : 6 )
sm(0:l) : = s(5:4)
:= s ( 3 )
sd
sr
: = s(2:O)
d/destination(5:0) : = i(5:O)
dm(0:l) : = d(5:4)
dd
: = d(3)
dr(2:O) : = d(2:O)
offset(7iO : = i(7:O)
address, increment/ai

Data Types
by/byte(7:0)
w/word( 15:0)
byJbyte.integer(7 : 0 )
w.i/word.integer(15:0)
by.bv/byte.boolean,vector (7 :0)
w.bv/word.boolean,vector(l5:0)

(processor state register)
(under program control; priority
level of the process currently being
interpreted a higher level process
m a y interrupt or trap this. process)
(under program control; when set,
each instruction executed will trap;
used for interpretive and breakpoint debuggin.g)
( a result condition code indicating
an arithmetic carry from bit 16 of
the last operation)
( a result condition code indicating
last result was negative)
( a result condition code indicating
last result was zero)
( a result condition code indicating
an arithmetic overjlow of the last
operation)
(denotes whether instruction trace
trap i s to occur after each instruction i s executed)
(unused)
(denotes normal execution)
(denotes waiting for an interrupt)

(binary operation code)
( u n a r y operation code)
(branch operation code)
(shijt operation code)
(source control byte)
(source mode control)
(source defer bit)
(source register)
(destination control byte)

(signed 7 bit integer)
(implicit bit derived f r o m i to denote
byte or word length operations)

(signed integers)
(boolean vectors (bits))

The DEC PDP-11

673

(*double word)
(*triple word)
(*triple floating point)

d/double, word (31 :0)
t/triple,word(47:0)
f/t.f/triple.floating, point (47:O)
Source/S and Destination/D Calculation
(
S/Source(l5:O) : = ( sd
(sm = 00) -+ R[sr];
(sm = 01) A (sr # 7) -+ (M[R[sr]]; next R[sr] +- R[sr]
ai);
(sm = 01) r\ (sr = 7) -+ (MCPC]; PC +- PC
2);
(sm = 10) -+ (Rcsr] t R[sr] - ai; next M[R[sr]]);
(sm = 11) A (sr # 7) -+ (M[M[PC]
RCsr]]; PC t PC 2 ) ;
(sm = 11) A (sr = 7) -+ (M[M[PC]
PC]; PC t PC
2));
sd -+ (
(sm = 00)-+ M[R[sr]];
(sm = 01) A (sr # 7) -+ (M[M[R[sr]]];
next R[sr] + R[sr]
ai);
(sm = 01) A (sr = 7) -+ (M[M[PC]]; PC t PC
2);
(sm = 10) -+ (R[sr] t R[sr] - ai; next M[R[sr]]);
(sm = 11) A (sr # 7) -+ (M[M[PC]
R[sr]]; PC + PC 2);
PC]]; PC t PC
2))
(sm = 11) A (sr = 7) -+ (M[M[M[PC]
-+

+
+

(direct access)
(register)
(auto increment)
(immediate)
(auto decrement)
(indexed)
(relative)
(indirect access)
(indirect via register)
(indirect via stack, auto decrement)
(direct absolute)
(indirect via stack, auto increments)
(indirect, indexed)
(indirect relative)

( T h e above process dejines how operands are determined (accessed) from either memory or the registers. The various
length operands, Db(byte), Dw(word), Dd(doub1e) and Df(jloating) are not completely dejined. The SourcelS and
DestinationlD processes are identical. I n the case of j u m p instruction a n address, D', i s used-instead of the word in
1ocation M [CI]. )
Instruction Interpretation Process
1 Interrupt,rqs
A Run A Wait -+ (i t MCPC]; P c t Pc
2;
next instruction, execution ; next
T -+ (SP t SI'
2; next
M[SP] t PS;
SP t SP 2; next
M[SP] t PC;
PC t M[148]
ST +- MC1681))

(fetch)
(execute)
(trace bit store state)

Interrupt,rq[j]
A (CC[j]
SP t SP 2; next
MCSP] t PS;

> CC) A Run

(T t 0;

(interrupt)
(store state and PC enter new process). The locations M [ f ( j ) ] are:
reserved instruction = M[lO]
illegal instruction = M[4]
stack overflow = M[43
bus errors = Mc4-J)

SP t SP 2;
MCSP] t PC
PC MCf(j)l
PS + M[f(j)
21)
Instruction Set and the Execution Process
+
-

( T h e following instruction set will be defined briefly and i s incomplete. I t i s intended to give the reader a simple understanding of the machine operation.)
Instruction,execution : = (
MOV(: = bop = OOOl) -+ (CC,D t S);
MOVB(: = bop = 1001) --+ (CC,Db t Sb);

* not hardwired or optional

(move word)
(move byte)

674

Spring Joint Computer Conference, 1970

Binary Arithmetic: D + D b S;
ADD(: = bop = 0110) -+ (CC,D + D+s) ;
SUB(: = bop = 1110) -+ (CC,D + D - S);
CMP(:=bop = 0 0 1 0 ) - + ( C C t D - S ) ;
CMPB(: = bop = 1010) -+ (CC + Db - Sb) ;
MUL(: = bop = 0111) + (CC,D + D X S);
DIV(: = bop = 1111) -+ (CC,D + D/S) ;
Unary Arithmetic D + u S;
CLR(: = UOP = 0508) -+ (CC,D + 0) ;
CLRB(: = UOP = 10508) -+ (CC,Db +0);
COM(: = UOP = 0518) -+ (CC,D + 7D);
COMB(: = UOP = 10518) -+ (CC,Db + ,Db);
1);
INC(: = UOP = 0528) + (CC,D t D
INCB(: = UOP = 10528) -+ (CC,Db t Db
1);
DEC(: = UOP = 0538) -+ (CC,D + D - 1);
DECB(: = UOP = 10538) + (CC,Db + Db - 1);
NEG(: = UOP = 0548) -+ (CC,D + - D) ;
NEGB(: = UOP = 10548) + (CC,Db + -Db)
ADC(: = UOP = 0558) -+ (CC,D + D
C);
C);
ADCB(: = UOP = 10558) + (CC,Db + Db
SBC(: = UOP = 0568) -+ (CC,D + D - C);
SBCB(: = UOP = 10568) (CC,Db + Db - C) ;
TST(: = UOP = 0578) -+ (CC + D);
TST(: = UOP = 10578) -+ (CC + Db) ;

Shift operations: D + D x 2";
ROR(: = sop = 0608)-+ ( C O D t COD/2(rotate] ;
RORB(: = sop = 10608)+ (CODb + CODb/B{rotate));
ROL(: = sop = 061s) -+ ( C O D t C O D X 2Irotate));
ROLB(: = sop = 10618)-+ (CODb + CODb X 2(rotate));
ASR(: = SOP = 0628) + (CC,D + D X 2);
ASRB(: = sop = 10628) -+ (CC,Db + Db/2);
ASL(: = SOP = 0638) -+ (CC,D + D X 2);
ASLB(: = SOP = 10638) -+ (CC,Db + Db X 2);
ROT(: = SOP = 0648) -+ ( C O D + D X 2');
ROTB(.: = sop = 10648) -+ ( C n D b + D X 2') ;
LSH(: = sop = 065,J -+ (CC,D t D X 28(logical));
LSHB(: = sop = 10658)+ (CC,Db +- Db X 2'(logical]);
ASH(: = SOP = 0668) + (CC,D + D X 2") ;
ASHB(: = SOP = 10668) + (CC,Db + Db X 2');
NOR(: = sop = 067,) -+ (CC,D + normalize(D));
(R[r'] t normalize,exponent(D)) ;
NORD(: = sop = 1067,J -+ (Db + normalize(Dd) ;
R[r'] t normalize,exponent(D)) ;
SWAB(: = sop = 3) -+ (CC,D + D(7:0, 15:8))
Logical Operations
BIC(: = bop = 0100) -+ (CC,D t D + D A -,S);
BICB(: = bop = 1100) -+ (CC,Db + Db V ,Sb);
BIS(: = bop = 0101) + (CC,D +- D V S) ;
BISB(: = bop = 1101) -+ (CC,Db + Db v Sb);
BIT(: = bop = 0011) -+ (CC t D A S) ;
BITB(: = bop = 1011) -+ (CC t Db A Sb);

(add)
(subtract)
(word compare)
(byte compare)
(*multiply i f D i s a register then a
double length operator)
(*divide, i f D is a register, then a
remainder is saved)
(clear word)
(clear byte)
(complement word)
(complement byte)
(increment word)
(increment byte)
(decrement word)
(decrement byte)
(negate)
(negate byte)
(add the carry)
(add to byte the carry)
(subtract the carry)
(subtract from byte the carry)
(test)
(test byte)
(rotate right)
(byte rotate right)
(rotate left)
(byte rotate left)
(arithmetic shift right)
(byte arithmetic shift right)
(arithmetic shift left)
(byte arithmetic shift left)
(rotate)
(byte rotate)
(*logical shift)
(*byte logical shift)
(*arithmetic shift)
(*byte arithmetic shift)
(*normalize)
(*normalize double)
(swap bytes)
(bit clear)
(byte bit clear)
(bit set)
(byte bit set)
(bit test under mask)
(byte bit test under mask)

The DEC PDP-11

Branches and Subroutines Calling: PC t f ;
JMP(: = SOP = OOO18) --+ (PC + D’);
BR(: = brop = 0116)+ (PC + PC offset);
BE&(: = brop = 0316)+ (Z -+ (PC + PC offset));
BNE(: = brop = 0216)+ ( lZ
(PC + PC offset));
BLT(: = brop = 0516)
( N @ V --+ (PC + PC offset));
BGE(: = brop = 0416) + (N = V + (PC + PC offset));
BLE(: = brop = 0716)+ (2 V (N @ V) + (PC t PC offset));
BGT(: = brop = OCi16) --+ (7(Z V (N @ V)) + (PC e PC offset));
BCS/BHIS(: = brop = 8716) -+ (C + ( P c + PC offset));

---f

+
+

+
+
BCC/BLO(: = brop = 861s)
(,C + ( P c P c + offset));
BLOS(: = brop = 8 3 1 ~+
) (C A Z
(PC PC + offset));
BHI(: = brop = 8Z16)+ (( -,C V Z) + (PC + PC + offset));
(PC PC + offset));
BVS(: = brop = 851~) (V
BVC(: = brop = 8416)+ ( lV + (PC PC + offset)) ;
BMT(: = brop = 8 l U ) (N
(PC + PC + offset));
BPL(: = brop = 801a) (,N
(PC PC + offset)) ;
-+

---f

--+

JSR(: = SOP = 00408)+ (
SP t SP - 2; next
MCSP] + Rcsr];
R[sr] t PC;
PC t D);
RTS(: = i = 0002W8) + (
PC t RCdr];
RCdr] t MCSP];
S P t S P + 2);

675

( j u m p unconditional)
(branch unconditional)
(equal to zero)
(not equal to zero)
(less than (zero))
(greater than or equal (zero))
(less than or equal (zero))
(less greater than (zero))
(carry set; higher or same (unsigned))
(carry clear; lower (unsigned))
(lower or same (unsigned))
(higher than (unsigned))
( OVerJEow)
( n o overfZow)
(minus)
(Plus)
( j u m p to subroutine by putting
R[sr], PC on stack and loading
RLsr] with PC, and going to subroutine at D )
(return from subroutine)

Miscellaneous processor state modification :
RTI(: = i = Z8) + (PC t MCSP];
SP t SP 2 ; next
PS tMCSP];
S P t S P 2);
HALT(:=i=O)+(RuntO);
WAIT(: = i = 1) + (Wait + 1);
TRAP(: = i = 3) --+ (SP t SP 2; next
MCSP] t PS;
SP t SP 2; next
M[SP] t PC;
PC
M[348];
PS + MC123);
EMT(: = brop +(
SP c SP 2; next
M[SP] t PS;
SP t SP 2; next
MCSP] t PC;
P C + M[308];
PS + MC328-J) ;
IOT(: = i = 4) + (see TRAP)
RESET(: = i = 5) + (not described)
OPERATE(: = i(5: 15) = 5) --+ (
i(4) + (CC e CC V i(3:O));
~ i ( 4+
) (CC t CC A i(3:O)));
end Instruction,execution

+
+

(return from interrupt)

(trap to M[S&] store status and
PC)
(enter new process)
(emulator trap)

( I / O trap to M[208])
(reset to external devices)
(condition code operate)
(set codes)
(clear codes)