A New Architecture for Mini-Computers - The DEC PDP-11

This document, "A New Architecture for Mini-Computers - The DEC PDP-11," published in the AFIPS Conference Proceedings, Volume 36, by G. Bell, R. Cady, H. McFarland, B. Delagi, J. O'Laughlin, R. Noonan, and W. Wulf, introduces the DEC PDP-11 computer. The paper discusses the limitations of existing mini-computers in the late 1960s, such as limited addressing capabilities, few registers, lack of hardware stack facilities, slow context switching, no byte string handling, and elementary I/O processing, which were largely driven by cost constraints and a lack of application experience.

The PDP-11 is presented as a new architecture designed to overcome these limitations by leveraging advancements in integrated circuit technology and incorporating insights from 1970s application experience. It aims to lower programming costs while maintaining low hardware costs. The PDP-11 is described as a member of a computer family intended to span various market segments, from micro to maxi.

Key design features and goals highlighted include:

• Modularity and Flexibility: The architecture is designed to be modular, allowing users to configure systems based on cost, performance, and reliability, and to easily interface with special hardware.
• Word Length: Chosen to be a multiple of 8 bits, with the Model 20 having a 16-bit word length.
• Range and Performance: The design aims for extendability to accommodate future models with significantly more performance.
• General-Register Architecture: A general-register organization was chosen to enhance performance and extend the family's life.
• Understandability: A straightforward design to simplify systems programming tasks.
• Unibus: A central switch (bus) that allows all components to communicate with each other, enabling conventional and other structures.
• Instruction Set Processor (ISP): The abstract machine defining the computer's behavior, described using PMS (Processor-Memory-Switch) and ISP notation.
• Addressing Modes: A flexible addressing structure that allows the machine to be viewed as a zero-, one-, or two-address computer.
• Data Types and Operations: A focus on a few basic data types (byte and word integers) with a comprehensive set of operations.
• Interrupt Handling: A multiple priority level, nested interrupt mechanism for efficient real-time control applications.
• Software Considerations: Techniques to aid programmability, including benchmarks and evaluation by systems programmers.

The paper details the PDP-11's structure at the PMS level, the Unibus organization, instruction interpretation, and various instruction formats. It also discusses how the PDP-11 can be used as a stack, general-register, or two-address machine, and touches upon extensions for real (floating point) arithmetic. The logical design and bus control are also explained, highlighting the Unibus's bi-directional signals and interlocked operation. The document concludes by summarizing the PDP-11 Model 20's description at four levels and presenting guidelines for forming additional family models.