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XX-609F2-4F
February 1970
4 pages
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Document:
PDP11 Brochure
Order Number:
XX-609F2-4F
Revision:
Pages:
4
Original Filename:
PDP11_Brochure_1970Feb.pdf
OCR Text
digital equipment corporation The PDP-11 is Digital Equipment Corporation’s response to industry demands for a ra(fically new concept in computer In addition to this unique architecture, the PDP-11 combines speed, a powerful order code, and many real-time hardware features into a compact, modular, low-cost computer which offers the user unique flexibility in program applications. It is a total system concept which incorporates features found in DEC’s highly successful large computer system, the PDP-10. The newest DEC system draws on the company’s experience with large, medium, and small scale computers—with more than 7,000 installations of DEC computers worldwide!! Expertise gained in systems such as the PDP-8, PDP-9, PDP-10, PDP-12, PDP-14, and PDP-15 computer lines was applied to the design of a new “minicomputer” architecture with its vastly improved processor logic and register configuration. Much of the power of the PDP-11 is derived from its wide range of addressing capabilities. Addressing modes include list sequential addressing, full address indexing, full 16-bit word addressing, 8-bit byte addressing, stack addressing, and direct addressing to 32K words. Variable length instruction formatting allows a minimum number of bits to be used for each addressing mode — resulting in the efficient use of program storage space! design. The first two models in the series incorporate 16-bit processors so that DEC computer users can now choose the most suitable system solution from the widest possible range of computers (12-bit, 16-bit, 18-bit, and 36-bit) and related equipment available today. In refining the architecture for the PDP-11’s advanced design, DEC provided for such typical demands imposed on the central processor as: * Addressing capability, which has been markedly improved * Multiple general registers; accumulators, index registers, and pointers * * Hardware stack facilities Priority structures and rapid context switching in priority interrupt situations Byte string handling Read-Only memory facilities 1/0 Processing Using the latest developments in integrated circuit technology and packaging to dissolve many of the logic design constraints previously imposed by circuit costs, the new PDP-11 has been given considerably more freedom and latitude in the structure of its central processor. The computer architecture will thus be able to lower overall programming costs as well as maintain the low hardware cost expected of “minicomputers.” The UnibusTTM a unique feature of the system, provides the framework for a family of computers which is easily maintainable and expandable. The PDP-11 has adapted this modular approach to allow custom configuring of systems, easy expansion, and easy servicing. Systems are built from basic building blocks called System Units, which are completely independent subsystems, connected only the the pluggable Unibus and necessary power connections. Additional units can be mounted easily in many combinations within the PDP-11 hardware and connected to the system in the field. As with previous DEC systems, the PDP-11 comes with a complete package of user-oriented software. This includes: * Absolute assembler providing object and source listings * * * * String-oriented editor Debugging routines capable of operating in a priority interrupt environment Input/Output handlers for standard peripherals Relocatable integer and floating point math library SUMMARY OF PDP-11 FEATURES UNIBUS MODULAR CONSTRUCTION OF THE PDP-11 The PDP-11 relies on a highly efficient, single, high-speed UnibusTM: for data transfer between the central processor, memory and other devices such as Teletype, disk, line printer, DECtape or analog-to-digital converter. Physically, each Unibus functional subsystem is composed of printed circuit modules plu%ged into connector blocks on frames called System Units. System Unit subassemblies, such as 4K of core, easily fit side by side into a compact mounting box. A mounting box can contain a power supply. CP, 12K core and two small peripheral controllers. The Unibus, a single cable carrying 56 signals, plugs from one System Unit to another as does the power from the power supply. There is no fixed wiring between System Units. Unibus construction With the Unibus concept, devices are modular subsystems physically and electrically attached to the Unibus in parallel. In this configuration, instructions may operate directly upon information in device registers, and data transfers from input to output devices can bypass the processor completely. Because of device-memory identity on the Unibus, 1/O instructions are not required. 1/0 is accomplished by word or byte moving instructions in a manner exactly analogous to moving data from one core cell to another. A new dimension is added to 1/0 operation by allowing all instructions to be used with /0 activity (Compare, Bit Set, Bit Test, Add, etc.). allows: * True physical and electrical modularity * Extreme flexibility in original system configuration and field expansion * * Ease of repair and minimum down time Low-cost construction without sacrificing device modularity The PDP-11 is a 16-bit computer with a universal bus called a Unibus allowing networks of memories and peripherals to be used in virtually any combina- tion. HARDWARE INTERRUPTS The central processor recognizes four levels of hardware interrupt. Within each major level there are sublevels. Many devices may thus be attached on each level with the device closest to the central processor given priority over the other devices on the same level. The hardware interrupt priority levels are interleaved by programmable central processor priority levels, thus allowing the running program to select the priority of allowable interrupts. Additional speed and power are added to the interrupt structure through the use of the PDP-11 fully vectored interrupt scheme. With the vectored interrupts, the device identifies itself and a unique interrupt service routine is automatically selected by the central processor without device polling. The device’s interrupt priority and the service routine priority are independent. This allows dynamic adjustment of system [\;ehavior in response to real-time conditions. All. PDP-11 processors, memories and peripherals are electrically and mechanically modular subsystems supported in System Units which are simply plugged together to form a computer tailored to user needs. THE KA11 CENTRAL PROCESSOR The KA1l central processor, connected to the Unibus as a subsystem, controls Unibus allocation between devices and performs arithmetic operations and instruction decoding. It contains eight high-speed general-purpose registers which are used as arithmetic accumulators, index registers, autoincrement and autodecrement registers. The instruction com- plement of the PDP-11 utilizes the flexibility provided by these general-purpose registers to provide over 400 powerful hard-wired instructions. These instructions, recognizing that most data in a program is structured in some way, exist in a table, in a stack, a table of addresses or perhaps a small set of frequently used variables local to a limited region of program. The PDP-11 handles these common data structures with addressing modes specifically designed for each kind of access. In addition, addressing for unstructured data is general enough to permit direct random access to all of core as well as the writing of relocatable code. The PDP-11 addressing modes include direct register addressing, sequential addressing, full address indexing, and two levels of deferred addressing. The resultant code is highly bit-efficient and each instruction is capable of accomplishing significantly more operations than is possible in any other computer of this size and cost. The basic order code of the PDP-11 utilizes both single address and double address instructions applicable to either words or bytes. The order code features such instructions as: MOV A, B This instruction incorporates, in one statement, the operation of moving the contents of location A to location B. Locations A and B each may be a high-speed register or memory location or a device register on the Unibus. Addresses A and B may be full 16-bit addresses allowing the programmer complete freedom of movement within the full address range of the machine which is 32K words or 65K bytes. Memory, although it is 16 bits parallel, is byte addressable. Another example of the PDP-11’s code efficiency is: ADD A, B Any two addressable locations may be added together and the result placed in one of the argument locations using the above command without “Load” and “Store” instructions. The plug-in console board with modular construction is supplied in the basic 11/20 configuration. In addition to aiding programming, console contributes to ease of maintenance on the PDP-11. STACKS The PDP-11 central processor has special last-in, first-out “StackTM handling capability. Words may be “pushed” onto a stack or “popped” off a stack with simple instructions. DIRECT MEMORY ACCESS Any number of DMA devices may be attached to the Unibus with the priority level among them determined by their placement along the bus. No expensive multiplexers are required. Maximum priority over all is given to DMA devices allowing memory data storage or retrieval at memory cycle speed. Latency is minimized by the organization and logic of the Unibus which allows direct memory access during the execution of instructions. POWER FAIL AND RESTART Power fail and restart are standard features of the PDP-11. With these functions, the system senses power failing and traps the processor to a location at which the user has placed a vector to a power fail routine. SPECIFICATH)N‘S PHYSICAL ‘ ".Increments of 1024 words available Tal)le Top |Modet o L ' 256 words of Read/Write 2.0 microsecond cycle : ' tlme, 1.0 microsecond access time core ma “added with each 1,024 words of Read L ‘Diménsions: 11 mehes high, 20° mches wulc,, 24 mches deep = Memory . We@t. 100 lhs. (appmxnmate) (Increments of ‘1 ,024-word Read O ' Dimensions:10% inches| ory, are interchangeable with 4,096-word increments of Read/Wnte Memory) , 19 inches ‘wide, 23 N - inches dee wrthtflt lock chassis’ shdesfor_ Dlrect Memory Access:. staridard 197rack ‘Rate; 83,000 words?'seeond i Welglfi:_glllhs(appronmnte) ‘ - DECtacl:lbl)net (available with or mtbout progammers " Maximum latency3.5 microseconds for hlghest priority device* = e . Multiple device capabihty without multlplexer Dimensions: 715’2 inches high, 22 inches wide, 39 ~ inches deep including Unibus Data Rate: stabilizer feet * Weight: 150 Ibs,.(approximate). Table size: 20 inches deep, 19 mches wule 27 --inches above floor + 1,300,000 words/second ' Automatnc Priority Interrupts: Four main hardware levels with any number of sublevels Response time: 7.2 microseconds including storage of the current program counter and status word and establishment of the new program counter - ELECTRICAL Processor power reqmrements Restore time: 4.5 microseconds including restoring of program counter and status word ‘ ) Power Fail and Restart: Included in standard product Ground and+3 volts General Registers: Intemal circuit potamals Eight high-speed flip-flop re sters within central processor. Used as accumulators, 16-bit indexreglsters and autoincrement or autodecrement . +5 volts, 15 volts ers. All registers may serve as stack pointers. Reglster 6 is used as the processor stack pointer. Register 7 is the program counter. FUNCTIONAL Rzad/Wnte Memory v Cycle time:. " "Access tune Word length: o 1.2 microseconds500 nanoseconds 16 blts Instructions: - Over 400 hard-wired instructions through use of general register address modes w Core memory size: 4,096 L - expandable to 28,672 " Access time: Word length: 500 nanoseconds 16 bits * x 'PDP-11/20 COMPLETE SYSTEM CONFIGURATIONS Two main configurations of systems are offered: . . $10,800 - avail: - nucroseoonds Box, raek»meuntable w/tllt slules. (Also in‘tabletopvemon) - Power Supply (fitsin" KY11-A 1.2 and word addressable to 65,576 bytes or 32 68 words Humidity: 20 - 95% KA11 — Central Processor MM11-E - 4K words, Read/Write memory - Two levels of deferral Machine directly byte ‘ Envn-onmental (Processor) Temperature: 10°- 50° C Read Only Memory Available: Mounting Memory, - with or without 256 words of Read/&nte Mem- Rack-Mourited Model: : » PDP-l 1/10 DEDICATED CONTROLLER$7,700 KA1l — Central Processor MR11-A — 1K ‘words, 500 microsecond access time, Read-Only memory MW1l-A — 256 words, 2.0 microseconds, : Read/Write memory . Mounting Box, rack-mountable w/tilt slides. (Also © — Console (F’ifloperator console) * avai in tabletop version.) -Power Supply (fitsin Mounting Box) ASR-33 — Teletype KY11-B — Turn Key Console “Both systaemsmelnde L PowetFall and. Rzfltart ,*Fullpmflty t. stmcmre and nmltnlevnce DMA $OUETE % Both may ‘useMRII-A Read Only and MMILE ‘Read/Write Memory
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