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Document:	AD01-D Analog to Digital Conversion Subsystem Manual Part 1
Order Number:	XX-414E1-24
Revision:
Pages:	15
Original Filename:	AD01-D%20manual%20part-1.tif

OCR Text

DEC-11-HADB-D

ADO1-D
analog-to-digital
conversion

subsystem manual

DIGITAL EQUIPMENT CORPORATION « MAYNARD, MASSACHUSETTS

1st Printing April 1971

2nd Printing October 1971
3rd Printing (Rev) June 1972

The material in this manual is for informational purposes and is subject to change without

notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS
Page

Page

CHAPTER 1

CHAPTER 3

GENERAL INFORMATION

OPERATION AND PROGRAMMING
3-1

1.1

Introduction

1-1

3.1

Introduction

1.2

Purpose

1-1

3.2

Address Format

3-1

1.3

Functional Description

1-1

3.3

CSR Format

1.4

Physical Description

1-1

3.4

DBR Format

3.5

Interrupt Structure

3-2
3-2

1.5

Specifications

1.5.1

Environmental

1-2

3.6

External Clock Control

1.5.2

Power Requirements

1-2

3.6.1

EXT IN

1.5.3

Packaging

1-2

3.6.2

EXTIN A

3-2

1.5.4

Performance Parameters

1-2

3.6.3

External Clock Timing Considerations

3-3

1.6

Reference Documents

1-2

CHAPTER 4

CHAPTER 2

INSTALLATION AND ADJUSTMENTS

2.1

Installation Planning

2-1

2.2

Environmental Requirements

2-1

2.3

Configurations

2-1

2.3.1

Channel Expansion

2-1

2.3.2

Bipolar Option AHOS

2-1

2.3.3

Sample and Hold Amplifier Option AH04

2-1

234

Unibus Connections

2-1

2.3.5

Multiplexer Channel Connections

2-1

2.3.6

External Clock Connection

2-1

Installation Procedure

2-1

2.5

Option Installation

2-2

2.6

Adjustment Procedure

2-2

PRINCIPLES OF OPERATION

4.1

Introduction

4-1

4.2

Block Diagram Analysis

4-1

4.3

Detailed Circuit Analysis

4-3

4.3.1

Multiplexer

4-3

4.3.2

Scaling Amplifier

4-3

4.3.3

A/D Converter

4-3

4.3.3.1

Unipolar with Wide Aperture

4-3

4.3.3.2

Unipolar with Narrow Aperture

4-3

4.3.3.3

Bipolar with Wide Aperture

4-3

4.3.3.4

Bipolar with Narrow Aperture

4-3

4.3.4

Timing

4-3

4.3.5

Bus Interface

4-3

CHAPTER 5

MAINTENANCE

2.6.1

Power Supply Adjustments

2-2

5.1

ADO1-D MainDEC-11-D6AB Diagnostic Program

2.6.2

Timing Adjustment

2-3

5.2

Preventive Maintenance

5-2

2.6.3

A/D Converter

2-3

5.2.1

Preventive Maintenance Tasks

2.6.3.1

A812

2-3

5.3

Corrective Maintenance

2.6.3.2

A862 (AHOS Option)

2-4

5.3.1

Preliminary Investigation

5-2

2.6.4

Sample and Hold A405 (AHO4 Option)

2-4

5.3.2

System Troubleshooting

5-2

2.6.4.1

AHO04 Option Only

2-4

5.3.3

Logic Troubleshooting

5-2

2.6.4.2

AHO04 with AHO5 Option Only

2-5

534

Circuit Troubleshooting

5-3

2.6.5

Switched-Gain Amplifier A220

2-5

5.3.5

Validation Tests

2.6.6

Multiplexer Setup

2-5

5.3.6

Recording

5-4

2.6.7

External Sync

2-6

5.4

Test Equipment

5-4

CONTENTS (Cont)
Page
5.5

Module Handling and Repair

5-4

5.6

CHAPTER 6

5-4
ENGINEERING DRAWINGS

APPENDIX A

10-BIT UNIPOLAR CALIBRATION CHART

APPENDIX B

11-BIT BIPOLAR CALIBRATION CHART

ILLUSTRATIONS
Figure No.

Title

Art No.

1-1

ADO1-D Configuration

11-0331

2-1

Option Configuration Diagram

11-0343

2-2

A812 A/D Converter

11-0332

2-3

A862 A/D Converter

11-0333

2-4

A405 Sample and Hold

11-0334

2-5

A220 Switched-Gain Amplifier

11-0335

3-1

Address Format

11-0336

3-2

CSR Format

11-0337

3-3

DBR Format

11-0338

3-4

External Clock Timing

11-0339

4-1

ADO1-D Block Diagram

11-0342

4-2

Timing Generator Circuit

11-0340

4-3

ADO1-D Interrupt Logic

11-0341

5-1

IC Location

15-0430

5-2

IC Pin Location

15-0430

Page

3-3

TABLES
Table No.

Title

Page

1-1

ADO1-D Module Complement

1-1

2-1

Channel, Module, and Pin Number Cross-Reference List

2-2

Power Supply Adjustments

2-2

2-3

Timing Adjustments

2-4

3-1

CSR Bits

3-1

Table No.

Title

Page

3-2

Output Notations

5-1

Test Equipment Required

5-4

5-2

Spare Parts List

5-4

6-1

ADO1-D Engineering Drawings

6-1

3-2

CHAPTER 1

GENERAL INFORMATION

1.1

INTRODUCTION

1.4 PHYSICAL DESCRIPTION

The ADO1-D Analog-to-Digital Conversion Subsystem is a peripheral device used with the PDP-11 Computer

The ADO1-D Analog-to-Digital Converter Subsystem can be configured and modified according to application

Systems in data acquisition and control applications. Refer to the PDP-11 Unibus Interface Manual for infor-

needs. All logic, options, and a Type H727 A/B Analog Power Supply are housed in a single, 5-1/4 in., rack-

mation relevant to the architecture of the computer and peripheral devices.

mountable assembly. Insertion slots for the multiplex switch modules, bipolar option, and sample and hold

option are prewired to simplify field installation and modification. Only simple jumper wire changes are required.
The module complement and optional modules for the ADO1-D are listed in Table 1-1; the location of each
1.2

PURPOSE

The ADO1-D operates under computer or external clock control as a highly flexible analog input device to digitize

module is shown in Figure 1-1. Logic power for the ADO1-D is supplied by a separate H716 Logic Power Supply,
which can be rack mounted. Operation with an input voltage of 115V requires an H727-A power supply and the
system is designated ADO1-DA; an input voltage of 230V requires an H727-B and the system is designated

analog inputs connected to directly addressable, multiplex switch modules. As many as eight multiplex switch

ADO1-DB. If rack mounting of the subsystem is desired, DEC offers a 19-in. industrial Type H950 Cabinet with

modules can be implemented. Each module can service four individual analog inputs.

a blower fan and front and rear doors.
Table 1-1

The basic ADO1-D provides 10-bit digitization of unipolar, high-level analog signals with a nominal full-scale range

ADO1-D Module Complement

of OV to +1.25V,+2.5V,+5.0V or +10V. These four ranges are program-selectable and are achieved by a selectable gain amplifier. Options are available for digitization of bipolar analog signals and for sample and hold applications.

Type/Part No.

Name

Quantity

Al24

Four Input Multiplex Switch

Al24%*

Four Input Multiplex Switch

8 (max)

Location
B16
Al17-A20
B17-B20

1.3

FUNCTIONAL DESCRIPTION

The ADO1-D comprises
a.

An expandable solid-state input multiplexer

A programmable input range selector

c.
d.

A high-speed A/D converter
The computer interface logic.

A220

Selectable Gain Buffer Amplifier

A862 (AHO05)*

Bipolar A/D Converter

AB13 (AB12)

A405 (AHO4)*

Sample and Hold

AB15

A708

Dual Voltage Regulator
10-Bit A/D Converter

1
1

A24
AB1?2
Al0

A812

Al6

G736

Request

Jumper

M105

Address Selector

Ml111

Inverter

M112

NOR Gate

]

M113

10 2-Input NAND Gates

Ml161

Binary to Octal/Decimal Decoder

B10

M206

Six Flip-Flops

AB6

M302

Dual Delay Multivibrator

AB11, B8

M501

Schmitt Trigger

AB2?2

word from the computer selects the input range and multiplexer channel and starts the conversion. Other novel

M617

6 4-Input NOR Buffers

The interface logic includes two registers to store control and status information and data. The ADO1-D is accessed and controlled by a control and status word with a Move (MOYV) instruction. A single control and status
features of the interface logic are the ability to place the ADO1-D in an interrupting or noninterrupting mode

M782

Interrupt Control

and to select an external clock. In the interrupting mode, the ADO1-D can issue an interrupt when conversion

M783

Unibus TM

AB5S

is done or when an error condition is produced by starting a new conversion before the previous conversion is

M784

Unibus Receivers

M785

Unibus Transceivers

M908

Connector

AB21

complete. The noninterrupting mode enables the converter to approach its maximum throughput rate under

program control. After the conversion is complete, the data is easily transferred from the ADO1-D to the computer by programming another MOV instruction.

Drivers

*Denotes optional modules.

TM Unibus is a trademark of Digital Equipment Corporation.
1-1

1.5

SPECIFICATIONS

1.5.1

Environmental
Temperature:

Humidity:

0°C to +55°C, operating

MIM|[M[M|M
1{717]2]1
o|s|8]|o0]1
slel5/a]l3]6]3
clec

-25°C to +85°C, storage

M{M|{M[M|M|M|M|[M|M /°'/

3]|6]|1]3

* BIPOLAR

1.5.3

115V/230V £ 10%

Input frequency (ac):

47 Hz to 63 Hz, single phase

Power dissipation:

<75W

OPTION
AND HOLD

*x% MULTIPLEX

2 36 6 36 3¢ 36

5-1/4 in.

Width:

19 in.

Depth:

12 in.

Weight:

AMPL

SWITCH

3¢ 3¢ |36 30 3¢

Alalalalalm

ANALOG
PS.

4|4|4|4|4]|8

% ¥ K3 % HDE Ik K X X

OPTION

AHO4

MODULES

ADO1-D Configuration

Input impedance:

1000 M2 in parailel with 20 pF

Input isolation:

Enhancement mode MOS FET switches, off when

151b

unselected or power off

Analog input connections:

Plug-in cable modules

22 ws, including channel and gain selection with or

Channel selection:

6-bit address

without sample and hold option. Bipolar option

(program-selectable)

adds 7 us.

Conversion aperture:

17.5 us,

24 us with Bipolar Option AHOS5, or

Overload capability:

+20V on all ranges without damage

Cross-Channel attenuation:

78 dB, dc to 80 Hz for 20V p-p signals,

100-£2 source impedance

0.1 us with Sample and Hold Option AH04
Input gain:

Sample and Hold
Acquisition:

5 us to 0.01% of full-scale step change

Aperture:

100 ns

input channels:

4 minimum (expandable to 32 in groups of 4)

Input voltage range

REFERENCE DOCUMENTS

The following documents are essential to understand the PDP-11 Computer System:
PDP-11 Handbook

(program-selectable)

PDP-]1 Unibus Interface Manual

Unipolar:

0V to 1.25V, +2.5V, +5.0V or +10.0V, full-scale

Bipolar:

OV to £ 1.25V, £ 2.5V, £+ 5.0V or = 10.0V, full-scale

System accuracy:

2-bit code

(program-selectable)

1.6

Number of analog

11-0331

Performance Parameters
Conversion time:

A
7
0

t{1]1|1[1]9

¥*%

Figure 1-1

Height:

AHOS5

(plus separate power supply)

1-2

Packaging
Size:

1.5.4

2l2|2|2|2|o0

912|5|3|6|2|2|7]|1]2]|A8862

%% SAMPLE

Input voltage (ac):

M|g|s|8|o|1]|0]1]|6]|0

Power Requirements

ola|4a|a]|a|8]|1
|

Lz 4717|721

AlA|A|lA|A|M|M
211
|[1]|1]9]5
2(2|2(2]|2]0o]o0

(3)

1.5.2

M{G[M]|A
117138
1]13|o]1
11622

1|1

to 90 % without condensation

PDP-11 Maintenance Manuals
The following diagnostic program is required to test the performance of the ADO1-D:

+ 0.1% of full-scale

ADO1-D MainDEC-11-D6AB

+ 0.125% of full-scale with Sample and Hold Option AH04

A-SP-ADO1-D-12 Acceptance Procedure

CHAPTER 2

INSTALLATION AND ADJUSTMENTS

2.1

INSTALLATION PLANNING

2.3.4

Unibus Connections

The ADOI-D is a Type 1943 rack-mountable assembly, which can be installed in the Type H950 Equipment

Only one BC11-A Cable is required to connect the Unibus from the computer to the ADO1-D. This cable must

Cabinet. The Type 1943 Assembly has the following dimensions:

be inserted into slot ABO1 on the logic assembly. If the ADO1-D is the last peripheral device on the Unibus,

Width:

19 in.

Depth:

12 in.

Height:

5-1/4 in.

The associated H716 Logic Power Supply mounts on the rear door of the cabinet.

2.2

ENVIRONMENTAL REQUIREMENTS

Terminator Module M930 is inserted in slot ABO2; otherwise, this slot is used to connect the Unibus to another
peripheral device using another BC11-A Cable.

2.3.5

Multiplexer Channel Connections

The input connections to the multiplexer switch modules are wired to two M908 Connector Modules located in
slots AB21 of the logic assembly. The analog signals to be converted should be carried on user-supplied twisted
pairs of wires (shielded if necessary). These twisted pairs should be soldered to the appropriate split lugs on the

The ADO1-D and PDP-11 operate in identical environments; the environmental limitations are listed in

M908 Modules. The assigned channel numbers and the associated pin numbers on the M908 Modules are identi-

Chapter 1.

fied in Table 2-1.

2.3

2.3.6

CONFIGURATIONS

External Clock Connection

The basic ADO1-D Subsystem consists of a 5-1/4 in. rack-mountable logic assembly and a H716 Logic Power

As with the multiplexer channel connections, external clock input connections to the timing circuits of the ADO1-D

Supply. A physical description of the ADO1-D and associated options is presented in Chapter 1. The following

are also wired to the M908 Connector Module located in slot A21. If an external clock is to be used in an ADO1-D

paragraphs summarize the requirements for installing and configuring the ADO1-D.

installation, the clock signal should be carried on user-supplied twisted pairs of wires (shielded if necessary). The

twisted pair should be soldered to split lugs A1 and B1 or A2 and B1 on the M908 Connector Module in slot A21.
2.3.1

Channel Expansion

Eight prewired insertion slots are provided in the logic shelf for the multiplex switch modules. The slots are A17
through A20 and B17 through B20 (see Figure 1-1). When expanding the channel capacity, modules must be
added in the A level before the B level, progressing from slot 17 toward slot 20.

2.3.2

Bipolar Option AHOS

2.4

INSTALLATION PROCEDURE

The installation procedure for the ADO1-D Analog Subsystem is as follows:
Step

Procedure

Unpack the equipment from the shipping container(s) and inspect the unit(s) for
damage. Damage claims should be made to the DEC district supervisor.

To accommodate A/D conversion of bipolar analog voltages, Bipolar Option AHO5 must be installed in the ADO1-D

NOTE

logic assembly. The option consists of a replacement Bipolar A/D Converter Module, A862.

DEC Field Service personnel should be available for consulta-

tion on potential problems.

The replacement A/D converter occupies two insertion slots while the A812 10-Bit A/D Converter occupies only
one. The insertion slot is prewired to accept either A/D converter without wiring changes (see Figure 1-1).

Remove the tape that secures the modules and cables in the ADO1-D Assembly
and varify that the modules and connectors are seated in the proper connector

2.3.3

slots (refer to drawing D-MU-ADO 1-D-02).

Sample and Hold Amplifier Option AH04

If skewless sampling of analog signals is desired, Sample and Hold Amplifier Option AHO4 must be installed in

Mount the ADO1-D Assembly in the assigned location (H950 Equipment Cabinet),
using the appropriate hardware.

the ADO1-D logic assembly. The option consists of a single module designated the A405 Sample and Hold Module.
A prewired insertion slot located at AB15 (see Figure 1-1) on the logic assembly is reserved for the module.

(continued on page 2-2)

Table 2-1

Step

Procedure

Channel, Module, and Pin Number Cross-Reference List
A124 Multiplex Switch

Channel No.

Perform the acceptance checkout of the AD01-D logic and analog circuits using the
MainDEC-11-D6AB Diagnostic Program and A-SP-ADO1-D-12 Acceptance Procedure.

M908 Connector Module

Module Slot

Hot Pin

Gnd Pin

If, at any time, the ADO1-D is not within its stated specifications (accuracy), perform

Cl1

the adjustment procedure in Paragraph 2.6. When this adjustment is complete, perform

Slot

Adjustment should not be necessary because all potentiometers are sealed at the

Al7

A21

factory after adjustment.

Fl1

The ADO1-D options necessitate some changes in the back panel wiring. All information regarding the wiring for

each option configuration is given in Figure 2-1. Add and/or delete wires according to this diagram when install-

ing options.

Al8

A21

M?2

the acceptance tests again.

2.5

2.6

A20

17
18

Cl
D2

D1
E)

B17

A21

B21

B18

12
B21

S2 -

\'A!

B19

B20

B21

EXT IN

A21

EXTIN A

The adjustment procedure for the ADO1-D depends on the particular option configuration. If a given option is
not included in the ADO1-D, disregard the corresponding adjustment procedure. To achieve accurate calibrations,

perform the adjustments in the following sequence.

ADJUSTMENT PROCEDURE

Nk
W
=

OPTION INSTALLATION

2.6.1

Power Supplies
Timing

A/D Converter (A812 or A862)
Sample and Hold A405

Switched-Gain Amplifier A220
Multiplexer Setup
External Sync

Power Supply Adjustments

Table 2-2 summarizes the necessary information for adjusting the power supplies in the ADO1-D.

Table 2-2
Power Supply Adjustments

Supply

Voltage*

H716

+5V +£ 0.25V

AO03A2

+15V +£0.1V

A24V?2

A24T2 (GND)

Install the logic power supply and chassis subassembly in the assigned location

20V + 0.1V

A24N?2

Determine where Unibus is terminated and connect fBCl 1-A Cable to last device. If
the ADO1-D is the last device on the bus, install the Terminator Modules M930 in

slot ABO2 of the ADO1-D.

POWER MATE — Top Left
(Blue Case)

Connect the H716 Logic Power Supply Cable from the power supply to the left
end panel of the ADO1-D Subsystem where noted.

DELTRON — Bottom Right
(Black Case)

(refer to drawing D-UA-H716-B-0 for ADO1-DA or drawing D-UA-H716-D-0 for

POWER MATE — Top Right
(Blue Case)

Procedure

ADO1-DB).

Adjustment Location

A03C2 (GND)

H727
Step

A24T2 (GND)

DELTRON — Bottom Left

(Black Case)
*Voltage measurement can be made with EDC null meter and DEC 10:1 Divider (refer to Table 5-1).

EOC H

M302

|F2

o—0

BO8

INA09

‘

BIZE2

A/D DONEL

[Ai

A220

INPUT

/
A16

SIGN

¥
ANALOG

AO9

AOS8

1))

O- -~

ASZ

A405

AV2

/]/]/ d A
AB15

A
[01 A0S
e

A0S

10 BIT [H

BM2 —( | ;\T“BJZ

AB12

Lot

fc’ N
®

VAN

A/D

BI3FH

AB862

i1 BIT
A/D

fEZ

AO9

A
BASIC | 220

B16

A220

AHO4

A405

AHOS |

A220
2229

AHOS5

na0s

AHO4

A862

A220

O- ~-

B.D.F

[KZ
¢

0---

A09

Power Supply Adjustments

A708

-15V +£0.1V

A24S?2

From

AQ9A1

AQ8DI1

AQ09C1

AO8E1

AQ9D1

AO8F1

AQ9F1

AO8H1

AQ9E2

A08J1

AQ09J1

AO8K1

AQ9H?2

AO8L1

AO9L1

AO8MI1

AQ9K?2

AO8N1

AQ9NI1

AQO8P1

A15S2

A15V2

A08D?2

A08DI1

AOS8E?2

AOQO8E]1

AO8F2

AOQO8F1

AO8H2

AO8H1

A08J2

A08J1

AO8K?2

AO8K1

AOS8L?2

AOQO8LI1

AO8M?2

AO8M1

AO8N?2

AO8N1

AQO8P2

AO8P1

B13E2

AOQOSA1

BI13F2

AOQ05SA1

A05C2

AOSE]1

BOS8F?2

AQ9V1

A15E2

BI15M2

B15J2

A15U02

Option Configuration Diagram

2.6.2

Table 2-2 (Cont)

Voltage*

Bl
P2

Figure 2-1

.M
M2

AO9
M1}

sl
o-2-

AO9

A,C,F

[H
o2 >c
=

[J! >A(§

B,E,G

ALE

O- -~

JUMPERS
CONFIG. | MODULES |
E S

A24

o_?.l

Q- =~

AHOS5
AB13

AB12
EOC H—

Supply

Aezl l 5 dAau2

| AOSA

SIGN

- JUUUUUUUUU U U

BI3F2
e

Jumper

Timing Adjustment

The timing of the ADO1-D can be adjusted while running the WAS-IS TEST (SA 270g) of the diagnostics with
Adjustment Location

No Adjustment

A24T2 (GND)
*Voltage measurement can be made with EDC null meter and DEC 10:1 Divider (refer to Table 5-1).

inhibit printout option. The required timing adjustments are summarized in Table 2-3.

2.6.3 A/D Converter
2.6.3.1

A812 — The following adjustment should be performed while running the Display Conversion Loop

(SA 220g) of the diagnostic program.

2-3

Table 2-3

Timing Adjustments

Module

Slot

M302

All

S us

M302

All

0.5 us

M302

Bll

0.5 us

M302

B1l

0.1 ps

M302

BO8

1 us/AHOS only

M302*

BO8

OFFSET —
|

Time

CLOCK

2.5 us
0.1 us with AHOS

(COMPONENT SIDE)
11-0333

*External sync signal is required to set this single-shot, because it derives output signal

Figure 2-3

from Ext Syncinput.

2.6.3.2
NOTE

A862 A/D Converter

A862 (AHOS Option) — The following adjustment procedure uses the WAS-IS TEST and the Display

Conversion Loop of the diagnostic program. Adjust the A862 A/D Converter as follows:

The procedure should be performed with the A220 and A405
NOTE

Modules removed from their insertion slots.

The procedure should be performed with the A220 and A405
Modules removed from their insertion slots.
Step

Procedure
Step

Extend A812 Module using two W982 Extender Modules.

Set EDC to 5 mV and connect to B12V2.

Adjust comparator sensitivity potentiometer (see Figure 2-2) for 000 000g

Procedure

Start the WAS-IS TEST (SA 2708) with inhibit printout bit 13 = 1.
Connect scope to B13F1 and adjust clock potentiometer (conversion time)
to obtain a 24-us positive pulse (see Figure 2-3).

to 000 001 g on console DATA indicators. (Adjust for 001 7778 to 001 7768

Stop program and restart at Display Conversion Loop (SA 220g).

if AHO4 is installed.)

Connect EDC to A13J2 and A13F2 (GND). Set EDC to +5 mV + 2 mV.

Set EDC to +9.9853V.

Adjust reference potentiometer for 001 777g to 001 776g on console DATA

Adjust offset potentiometer for 000 000g to 000 001g on console DATA
indicators. (Adjust for 001 7778 to 001 7768 if AHO4 is installed.)

indicators. (Adjust for 000 000g to 000 001 g if AHO4 is installed.)

2.6.4

Sample and Hold A405 (AHO04 Option)

The adjustment procedure of the A405 Module depends on the ADO1-D option configuration. Two procedures
are outlined below. One procedure applies to systems that have only the AHO4 Option (Sample and Hold); the
other procedure applies to systems that have both the AHO4 and AHOS (Bipolar) Options.

AHO4 Option Only — Adjust the A405 Module as follows:
NOTE

The procedure should be performed with the A220 Module re-

moved from its insertion slot.

COMPARATOR
3

SENSITIVITY

(ADJUSTMENT
REQUIRES

Step

Procedure

EXTENDERS)

Ensure that all proper jumpers (except those marked G) are installed (see Figure 2-1).

Figure 2-2

A812 A/D Converter

11-0332

Ensure that split lugs A and B on the A405 Module are connected (see Figure 2-4).

(COMPONENT SIDE)

Start Display Conversion Loop (SA 220g) of the diagnostic program.

ADJUST

REFERENCE

2.6.4.1

Connect EDC to A15S2 and A15F2 (GND). Set EDC to -5 mV.
(continued on Page 2-5)

Procedure

Step

Adjust bias potentiometer (see Figure 2-4) on A405 Module for 001 776g to

Step

001 7778 on console DATA indicators.
O
9

Add jumper wire G to back panel wiring.

Turn on computer power and set EDC to 9.9853V.

Stop program and turn off computer power.

Restart Display Conversion Loop (SA 220g).

Ensure that Module A220 is installed in slot A16 and that Module A124 is installed
in slot B16.

Connect EDC to A16P2 and A16F2 (GND). Set EDC to +600 uV.

Start the Display Conversion Loop (SA 220g) of the diagnostic program with a gain
of 8 (SW6 and SW7 =1).

Adjust input offset potentiometer (Figure 2-5) on A220 Module for 000 001g to
000 000g on the console DATA indicators.

Adjust offset coarse potentiometer on A405 for 001 776g to 001 777g (or
as close as possible) on console DATA indicators.

Procedure

Adjust offset fine potentiometer on A405 for 001 776g to 001 777g on console

Set EDC to 0.625V and verify that DATA indicators display the following readouts
with specified gain settings:

DATA indicators.

~ SW6

Data (£1 bit)

2.6.4.2

AHO4 with AHO5 Option Only — Adjust the A405 Module as follows:
Step

000100

Procedure

Ensure that split lugs A and B on the A405 Module are connected (see Figure 2-4).

Connect EDC to A15S2 and A15F2 (GND). Set EDC to +5 mV.

Ensure that all proper jumpers are installed (see Figure 2-1).

Start the Display Conversion Loop (SA 220g) of the diagnostic program.

Adjust bias potentiometer (see Figure 2-4) on A405 Module for 000 001g to

SW7

Gain

000200g

000400

001000g

000 000g on console DATA indicators.

INPUT __/

OFFSET

(COMPONENT

SIDE)
11-0335

O
BIAS

Figure 2-5

JUMPER

/
O
A
B

O
C

SPLIT

LUGS

2.6.6

(COMPONENT SIDE)
11-0334

2.6.5

Multiplexer Setup

Set up multiplexer as follows:

OFFSET COARSE — 1>

Figure 2-4

A220 Switched-Gain Amplifier

A405 Sample and Hold

Switched-Gain Amplifier A220

Adjust the A220 Switched-Gain Amplifier as follows:

Verify that A124 Multiplexer Switch Modules are installed in the following slots:
CHOO

CHO3

Slot A17

CHO4

CHO7

Slot A18

CHO8

CHI11

Slot A19

CH12

CHI15

Slot A20

CHI16

CH19

Slot B17

CH20

CH23

Slot B18

CH24

CH27

Slot B19

CH28

CH31

Slot B20

2-5

If the G735 Test Card Module is available, perform the following procedure:

2.6.7

External Sync

NOTE

The G735 Module produces eight distinct voltage levels when
fed from the EDC. The first level, fed to channels 0, 10g, 20g,

!Before connecting the external sync to the ADO1-D, associated
jumpers must be removed. These jumpers are:

30g is equal to the input level from the EDC. Each successive
level is half the previous one and appears on the next channel,
except that the last level is ground. Jumper X should be con-

nected on the module for testing the ADO1-D.

EXT IN — A22R2 to A22C2
,

EXT IN A-— BOSB?2 to BOSN2
‘

After connecting the external sync (refer to Table 2-1), theiEXTEST and EXFAST Diagnostic Subroutines can

be run to verify proper operation of the ADO1-D under conétrol of external sync.
Step

Procedure

Insert the G735 Module in slot AB21.

Connect EDC to the tabs at the handle end, and set EDC to +10V.

Set the SR on the console to 270g and press start.

‘

i"’p

Load the initial channel of the multiplexer to be tested in DATA bits 00g through 04g,
then press CONT. The program will halt.

Load the number of channels to be tested in DATA bits 00g through O4g, then press

CONT. The program will again halt.

Set the SR to all Os and press CONT. The program should run. After one complete

]

pass, the Teletype bell will sound.
7

Set bit 06 of the SR to 1. The following table is printed:

Channel

Initial Value

Final Value

CHOO

1777

CHO1

1000

CHO2

0400

CHO3

0200

CHO4

0100

CHOS5

0040

CHO6

0020

CHO7

0000

CH37

0000

0000
NOTE

If differences between initial values and final values of more

than one count occur, check the multiplexer channel in
question. It may be noisy and should be replaced.

c¢.

If the G735 Module is unavailable, perform the following procedure:

Step

Procedure

With the program running the Display Conversion Loop (SA 220g) check each multiplexer channel by moving the EDC to the proper input pins in slot AB21.

Verify the correct results on the DATA indicators of the computer.

CHAPTER 3

OPERATION AND PROGRAMMING

3.1

INTRODUCTION

HIGH

BYTE

LOW BYTE

Operation of the ADO1-D is controlled entirely by the PDP-11 Computer program. AllI/O and control
programming is done by issuing the normal memory reference instructions. The nature of the program depends

on the system application and the familiarity of the programmer with the particular application and the PDP-11

MULTIPLEXER CHANNEL

DONE

GAIN

’

SELECT

A/D

START

instruction set.
ENABLE

3.2

REQUEST

ENABLE
11-0337

ADDRESS FORMAT

The ADO1-D is assigned two bus addresses:

Figure 3-2

776770g for the control and status register (CSR)

776772g for the data buffer register (DBR).

All information flows between the proCessor and the ADO1-D through these registers. The address format is

Table 3-1

shown in Figure 3-1.

BIT

CSR Bits

EXTENSION .
S

CSR Format

t
y

PROGRAM ADDRESS

Bit

Description

ERROR(ER) — indicates device has been issued a START command during the time
between Start Conversion and Read ADDB. Cleared by INIT. Set by CONVERT

BYTE

command if error condition is present. Cleared under program control when new

~— POINTER

Gain and MUX Channel data is loaded.

11-0336

NOTE
Figure 3-1

Address Format

The main purpose of the Error Bit is to indicate timing problems that could occur if an external clock is starting conver-

3.3

sions at certain intervals and conversions are being made un-

CSR FORMAT

der program control between the external clock pulses.

The operating condition of the ADO1-D is established by transferring a 16-bit control word or an 8-bit control

byte from the processor to the CSR. The status of the ADO1-D can be determined by transferring the contents

Unused.

of the CSR to the processor and testing the status bits. The CSR format and bit assignments are illustrated in

13-08

MULTIPLEXER CHANNEL (MC) — Selects 1 of 64 multiplexer channels. Loaded

Figure 3-2. The purpose and description of each bit in the CSR is presented in Table 3-1.

3.4

DBR FORMAT

On command, the ADO1-D digitizes the unipolar analog voltage of the selected channel into a 10-bit binary code,
using the successive-approximation technique. The bipolar option permits conversion of bipolar analog voltage

under program control. Cleared by INIT.

DONE (DN) — Indicates state of converter. Reset by INIT. Set by A/D Done. Reset

by reading ADDB. Read only.
(Continued on page 3-2)

3-1

Table 3-1 (Cont)

Table 3-2

CSR Bits

Output Notations

Bits

Description

Analog Input Voltage*

INTERRUPT ENABLE (IE) — Allows interrupts on A/D Done or Error. Set under

Bipolar

1760008

- 5.0

---

1770008

0.0

0000008

GAIN SELECT (GS) — Selects gain for programmable gain amplifier. Loaded under

+5.0

001000g

program control. Cleared by INIT.

+9.9902

0017778

Unused.

4-3

Unipolar

-10.0

program control. Cleared by INIT.

05-03

PROGRAMMABLE PRIORITY REQUEST SELECT (PS) — Allows selection of bus

*For 10V full-scale input range. Divide by appropriate gain factor for the input

request line under program control. When w bus requests are made at level 7.,

ranges.

When bit 02 = 1, bus requests are made at a level determined by bus grant jumper

socket on G736 Module. Set under progranfcgntrol.# Cleared by INIT.

EXTERNAL CLOCK ENABLE (EE) — Allows converter to be controlled by external
input. Loaded under program control. Cleared by INIT.

3.6

A/D START — Start conversion. Loaded under program control. Cleared by INIT.
Cleared by A/D Done (Write Only).

into an 11-bit two’s complement code with an extended sign format. The digitized analog voltage is stored in the

DBR when the conversion is done. A single move instruction can then be programmed to gate the contents of the
DBR onto the Unibus. The data format for unipolar and bipolar operation is illustrated in Figure 3-3. Table 3-2
relates the octal representation of the data word to the input analog voltage to highlight differences between
unipolar and bipolar operation.

EXTERNAL CLOCK CONTROL

The ADO1-D contains two inputs for external control of the conversion process: EXT IN and EXT IN A.

3.6.1

EXTIN

The EXT IN signal is brought into the converter on the M908 Analog Input Module in slot A21, pins A1 and B1

(B1 is EXT common). Input signal conditioning is provided by the M501 Schmitt Trigger circuit. The upper and
lower thresholds are set at 1.7V and 1.1V. Input signal swing is limited to £20V. Input standards are as follows:

Signal swing: +20V
Loading:
0

MSB

‘

UNIPOLAR

2.7 KS2 to +5V or 1.8 mA at GND

LSB

OPERATION

Before connecting EXT IN to the ADO1-D, the jumper wire
15

MSB

BIPOLAR

LSB

OPERATION
11-0338

Figure 3-3

from A22R2 to A22C2 should be removed.

DBR Format

b
e

3.6.2

SIS

EXTINA

The EXT IN A signal is brought into the converter on the M908 Analog Input Module in slot A21, pins A2 and

B1 (B1 is EXT common). This input is T2L compatible. Triggering is accomplished by a level change from high

to low or a pulse to low, the duration of which is = 50 ns. The fall time of the input trigger should be < 400 ns.
3.5

INTERRUPT STRUCTURE

Input standards are as follows:

The ADO1-D utilizes the interrupt structure of the PDP-11 System to inform the processor that the A/D conver-

Signal swing:

sion is done or to indicate that an error condition exists. The interrupt logic in the AD0O1-D can be enabled or

Timing:

Level — high to low fall time < 400 ns
Pulse — high to low, duration = 50 ns

disabled under program control. Bit 06 of the CSR is assigned to enable the interrupt logic. If the interrupt logic
is enabled, one of two priority levels can be selected by the program. Bit 02 is assigned to select the priority level

T2L logic levels

Loading:

2-1/2 unit loads

Priority level 7 is enabled when bit 02 is reset, and the priority level established by the bus grant jumper socket
on the G736 Module is selected when bit 02 is set. Bus grant jumpers are available for priority levels 4, 5, and 6.
When the ADO1-D is shipped from the factory, jumper plug S408778 for priority level 5 is installed in the G736

Module.

NOTE

Before connecting EXT IN A to the ADO1-D, the jumper wire
from BOSI 2 to BOSN?2 should
....

3-2

3.6.3

External Clock Timing Considerations

Figure 3-4 is a timing diagram that shows the operation of the ADO1-D under external clock control. In the external mode, time is not allowed for the switched gain amplifier to settle, thereby initiating a conversion at the

time the external signal is applied. Thus, the user must allow at least 5 us for settling of the input amplifier, if
necessary.

UPPER

LOWER
THRQFHOLD

THRESHOLD

1.7V

EXTERNAL INPUT SIGNAL

M501

VTHL

OUTPUT

PULSE OUTPUT FROM
STANDARD PULSE WIDTH SS

CHECK ERROR COND

START TIMING

FOR NEXT

CONVERSION
HOLD

START

CONVERTER

START

CONVERTER

SET ERROR CONDITION FLAG

A/D

DONE

BIT

PULSE

ADCR

READ

ADDB

(

A/D DONE

W/AHOS

TIME
IN us
11-0339

Figure 3-4

External Clock Timing