Digital PDFs

EK-0PIOS-UG-005

November 1980

453 pages

Original

16MB

Document:	IO Subsystem User Guide
Order Number:	EK-0PIOS-UG
Revision:	005
Pages:	453
Original Filename:	EK-0PIOS-UG-005_IO_Subsystem_User_Guide_Jul80.pdf

OCR Text

INDUSTRIAL
PRODUCTS
mDmDomo

I/O SUBSYSTEM
USER GUIDE

EK-OPIOS-UG-OO5

I/O SUBSYSTEM
USER GUIDE

digital equipment corporation • maynard, massachusetts

1st Edition, November
2nd Edition, October
3rd Edition, April
4th Edition, March
5th Edition, July

Copyr~ght

1977
1978
1979
1980
1980

0 1977, 1978, 1979, 1980 by Digital Equipment Corporation

All Ri g hts Re se rved
The material in this manual is for informational
purposes and is subject to change without notice.
Di~,ital
Equipment
Corporation
assumes
no
responsibility for any errors which may appear in
this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECUS
DIGITAL
Dig i tal Logo
PDP
UNIBUS
VAX.
OS/8

DECnet
DECsystem-10
DECSYSTEM-20
DECwriter
DIBOL
Ed usystem
OMNIBUS

lAS
MASSBUS
PDT
RSTS
RSX
VMS
VT

CONTENTS
Page

CHAPTER 1

GENERAL INFORMATION

1. 1
1.2
1. 3
1. 3. 1
1. 3. 2
1. 3. 3
1.4
1.4.1
1. 4. 2
1.4.3
1. 4. 4
1. 5

Sc 0 pe ••••••••••••••••••••••••••••••••••••••••••••• 1-1
General Description ••••••••••••••••••••••••••••••• 1-1
Equipment Description ••••••
1-3
Hardware Configurations . . . . . . . . . . . . . . . . . . . . . . . . 1-4
S t a nd a r d Eq u i pm en t •
1-9
Optional Equipment ••••••••••••••••••••••••••• 1-12
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1-16
Ph Ysic a 1
•••••••••••••
Environmental
•••••••••••••••••••••••••••• 1-16
Power Requirements ••••••••••••••••••••••••••• 1-16
Performance •••••••••••••••••••••••••••••••••• 1-16
Applicable Documents
1-18

CHAPTER 2

SITE PREPARATION AND PLANNING

2. 1
2. 2
2.3
2.4

2.5
2.6
2. 7
2.7.1
2.7. 2
2.7.3
2.7.4

SeQ pe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Considerations ••••••••••••••••••••••••••••
Site Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Effect of Environment on System Reliability •••••••
Power Requirements ••••••••••••••••••••••••••••••••
System Ground •••••••••••••••••••••••••••••••••••••
System Configuration ••••••••••••••••••••••••••••••
System Configuration Diagrams •••••••••••••••••
Cabinet Space Requirements
•••••••••••••••••
Cable l.engths •••••••••••••••••••••••••••••••••
AC Power Connections ••••••••••••••••••••••••••

CHAPTER 3

INSTALLATION

3.1
3.2
3. 2. 1
3. 2. 2
3.3
3. 3. 1
3. 3. 2
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4
3. 3. 3
3.3.3.1
3.3.3.2
3.3.3.3
3. 3. 4
3. 3. 5

Introduction •••••••••••••••••••••••••••••••••••••• 3-1
Unpacking and Inspection •••••••••••••••••••••••••• 3-1
Un pa c king ••••••••••
3-1
Inspection •••••••••••••••••••••••••••••••••••• 3-3
Installation of I/O Subsystem ••••••••••••••••••••• 3-3
3-4
Cabinet Installation ••••••••••••••••••••••
Intercabinet Connections (Expanded System)
3-4
Ground Strapping Connections •••••••••••••• 3-7
Remote Power Connections
••••••••••••••• 3-7
D-bus Connections ••••••••••••••••••••••••• 3-7
DC Power Connections ••••••••••••••••••••• 3-10
Expanding an Existing System ••••••••••••••••• 3-11
Adding New Cabinets •••••••••••••••••••••• 3-11
Adding H334 Chassis to Existing System
3-11
3-13
Adding New Modules to Existing System
3-16
Connecting to Pr imary Power ••••••••••••
Optional NEMA-12 Enclosure Installation •••••• 3-20

••••••••••••••••••••••

•

... . .... . .. ........... .. . . .. .

iii

••••••••••••••••••••••••••

2-1
2-1
2-1
2-1
2-2
2-2
2-2
2-2
2-5
2-5
2-6

3.3.5.1
3.3.5.2
3.3.5.3
3.3.5.4
3.3.5.5
3.4
3. 4. 1
3.4.2
3. 5
3. 5. 1
3. 5. 2
3.6
3.7
3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.9
3. 9. 1
3.9.2

3.9.4

NEMA Enclosure Descriptions ••••••••••••••
Maximum Power Dissipation •••••• ~ •••••••••
Air Purging ••••••••••••••••••••••••••••••
NEMA Enclosure Installation •••• ~ •••••••••
NEMA Enclosure Field Wiring ••••••••••••••
Checkout Procedures ••••••••••••••••••••••••••••••
Cabinet Power Check ••••••••••••••••••••••••••
Operational Check ••••••••••••••••••••••••••••
System Configuration Procedures ••••••••••••••••••
Configuring the System for Operation •••••••••
Screw Terminal Configuration ••••••••••• ~ •••••
Configuration Records ••••••••••••••••••••••••••••
System Restrictions .............................. .
Fie 1 d Wi ring ••••••••••••••••••••••••••••••• '.•••••
General Wire and Cable Characteristics .~ •••••
Analog Signal Wiring ••••••••••••••••••• » • • • • •
Digital Signal Wiring ••••••••••••••••••••••••
Gr 0 un ding •••••••••••••••••••••••••••••• " •••••
Installing Field Wiring ••••••••••••••••••••••
Installation of Processor Interface •••••••• ~ •••••
LSI-II Based Subsystem Installation (IP300) •••
UNIBUS IOCM Based Subsystem Installation
(IPl10)
UNIBUS to LSI-II Bus Converter Based
Subsystem Installation (IPll) ••••••••••••••••
LSI-II Based Subsystem (IPV10) •••••••••••••••

CHAPTER 4

PROGRAMMING INFORMATION

4. 1
4.2
4. 2. 1
4.2.1.1
4.2.1.2
4.2.1.3
4. 2. 2
4. 2. 2. 1
4.2.2.2
4.2.2.3
4.3
4.3.1
4. 3. 2
4. 4
4. 4. 1
4.4.2
4.5
4. 5. 1
4.5.2
4.5.3
4.5.4

Seo pe

I/O Transfers ••••••••••••••••••••••••••••••••••••
Programmed I/O Transfers •••••••••••••••• ~ ••••
Interrupt I/O Transfers ••••••••••••••••••••••
Device Priorities ................................ .
I/O Subsystem Pr iorities ••••••••••••••••
I/O Pr i 0 r it Y •••••••••••••••••••••••••••••
Configuration Requirements ....................... .
Subsystem Requirements •••••••••••••••••••••••
I/O Requirements •••••••••••••••••••••••• ~ ••••
Trap Conditions ••••••••••••••••••••••••••••••
So f t wa re Re s tr i c t ion s ...................... •••

CHAPTER 5

PRINCIPLES OF OPERATION

5.1

Scope

•

3.9.3

•

•••••••••••••••••••
Device Registers and Address Assignments ......... .
Ad d res s As s i g nm en t s ••••••••••••••••• ~ • • • • • • • •
Subsystem Addresses ••••••••••••••••••••••
I/O Addressing Rules ••••••••••••
Interrupt Vector Addresses •••••••••••••••
Register Formats ............................. .
t)

••••••••••••••••••••••••

••••••••

lOR ••••••••••••••••••••••••••••••••••••••
IAR ••••••••••••••••••••••••••••••••••••••
CSR ••••••••••••••••••••••••••••••••••••••

0• • • • •

••••

3-20
3-24
3-26
3-27
3-29
3-30
3-30
3-30
3-30
3-30
3-36
3-38
3-39
3-41
3-41
3-41
3-41
3-42
3-42
3-45
3-45
3-45
3-47
3-47

4-1
4-1
4-1
4-1
4-1
4-2
4-2
4-4
4-4
4-4
4-5
4-5
4-5
4-5
4-5
4-5
4-6
4-6
4-6
4-6
4-6

.. . .. .... . ... ... ....... . ..... ... .. . . . . . . . ... 5-1
iv

5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.5
5.5.1
5.5.2
5.5.3
5.6
5.6.1
5.6.2
5.6.2.1

Functional Description •••••
System Configurations ••••••••••••••••••••••••••••
LSI-11 Bus Based Subsystem
M7958 and M7959 D-bus Cycles •••••••••••••••••
M7958 and M7959 Interrupts •••••••••••••••••••
M7958 and M7959 Maintenance Mode ••••••••••••
UNIBUS Based Subsystem •••••••••••••••••••••••••••
M8719 D-bus Cycles •••••••••••••••••••••••••••
M8719 Interrupts •••••••••••••••••••••••••••••
M8 7 19M a i n ten a n c e Mo de. • • , • • • • • • • • • • • • • • • • • • •
System Power Supplies ••••••••••••••••••••••••••••
H7870 Power Supply •••••••••••••••••••••••••••
H7872 Power Supply •••••••••••••••••••••••••••
H7872 Detailed Description •••••••••••••••

CHAPTER 6

FUNCTIONAL I/O MODULES

6.1
6.2
6.3

Introduction •••••••••••••••••••••••••••••••••••• 6-1-1
Module Interfaces ••••••••••••••••••••••••••••••• 6-1-1
Numbering Conventions ••••••••••••••••••••••••••• 6-1-1
M50l0 32-Bit Nonisolated DC Sense ••••••••••••••• 6-2-1
M50ll l6-Bit Change of State Input •••••••••••••• 6-3-1
M50l2 l6-Bit Isolated DC Input •••••••••••••••••• 6-4-1
M50l2-YA l6-Bit TTL Compatible Input •••••••••••• 6-5-1
M50l3 8-Bit AC Input •••••••••••••••••••••••••••• 6-6-1
M50l4 Dual Input Counter •••••••••••••••••••••••• 6-7-1
M50l6 Quad Input Counter/Prescaler •••••••••••••• 6-8-1
M503l l6-Bit Isolated Change of State Input •••••• 6-9-1
M60l0 32-Bit DC Output Module •••••••••••••••••• 6-10-1
M6010-YA 32-Bit TTL Compatible Output Module ••• 6-11-1
M60ll l6-Bit One Shot Output ••••••••••••••••••• 6-12-1
M6012 8-Bit Isolated DC Output Module •••••••••• 6-13-1
M60l3 8-Bit AC Output Module ••••••••••••••••••• 6-14-1
M6014 Dual Output Counter •••••••••••••••••••••• 6-15-1
M60l5 l6-Bit Retentive DC Output Module ••••••••• 6-16-1
Analog Input Subsystem - General ••••••••••••••• 6-17-1
M0l4 A/D Converter Module •••••••••••••••••••••• 6-18-1
A156 Analog Multiplexer •••••••••••••••••••••••• 6-19-1
A157 Wide-Range Analog Multiplexer ••••••••••••• 6-20-1
A020 High Common Mode A/D Converter ••••••••••••• 6-21-1
ATR16 Isothermal Screw Terminal Assembly ••••••• 6-22-1
A630 Four-Channel D/A Converter •••••••••••••••• 6-23-1
A631 Four-Channel 12-Bit Isolated
D/A Converter •••••••••••••••••••••••••••••••••• 6-24-1
BC40L Signal Conditioning Screw
Terminal Assembly •••••••••••••••••••••••••••••• 6-25-1
A158 RMS Input Multiplexer ••••••••••••••••••••• 6-26-1

CHAPTER 7

SERVICE PROCEDURE

7• 1

Se 0 pe ••••••••••••••••••••••••••••••••••••••••••••• 7 -1

7.2
7.3
7.4

Required Equipment and Materials •••••••••••••••••• 7-1
Spares •••••••••••••••••••••••••••••••••••••••••••• 7-1
Adjustments ••••••••••••••••••••••••••••••••••••••• 7-2

•••••••••••••••••••••

5-1
5-1
5-4
5-4
5-8
5-12
5-12
5-16
5-20
5-25
5-25
5-27
5-29
5-29

7.5.3.1
7.5.3.2

H7870 Power Supply Adjustment •••••••••••••••••
H7872 Power Supply Adjustment •••••••••••••••••
Corrective Maintenance ••••••••••••••••••
Maintenance Features ••••••••••••••••••••••••••
Maintenance Tips ••••••••••••••••••••••••••••••
Basic Failure Analysis Procedure ••••••••••••••
Quick Checklist •••••••••••••••••••••••••••
Diagnostic Check

APPENDIX A

MNEMONIC DEFINITIONS

APPENDIX B

FLOATING VECTOR ASSIGNMENTS

APPENDIX C

USER FORMS

7.4.1
7.4.2
7.5
7. 5. 1
7. 5. 2
7. 5. 3

•••••••••

7-2
7-4
7-4
7-4
7-6
7-8
7-8
7-8

FIGURES
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6
1-7
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32

Title

Page

Processor I/O Interface ••••••••••••••••••••••••••• 1-2
IP300 - LSI-II Based Subsystem (current version) ••• 1-5
IP300 - LSI-II Based Subsystem (older version) •••• 1-6
IPl10 - PDP-II Based Subsystem (current version) ••• 1-7
IPll - PDP-II Based Subsystem (not recommended
for new systems) •••••••••••••••••••••••••••••••••• 1-8
IPVl10 LSI-II Based Subsystem ••••••••••••••••••••• 1-9
H960-C Expansion Cabinet ••••••••••••••••••••••••• 1-10
IP300 LSI-II Based Configurations ••••••••••••••••• 2-3
UNIBUS or Serial Bus Based Configurations ••••••••• 2-3
LSI-II Based Minimum Configuration •••••••••••••••• 2-3
Expanded I/O Subsystem •••••••••••••••••••••••••••• 2-5
Cabinet Space Requirements •••••••••••••••••••••• 0. 2~6
AC Power Distribution and Control •••.••••••••••••• 2-7
Plugs and Receptacles (861) ••••••••••••••••••••••• 2-8
Installation Flow Diagram ••••••••••••••••••••••••• 3-2
Standard H960-CA Cabinet with Expanded
I/O Subsystem ••••••••••••••••••••••••••••••••••••• 3-5
I/O Subsystem Front View •••••••••••••••••••••••••• 3-6
Cabinet Filler Strips ••••••••••••••••••••••••••••• 3-7
Remote Power Connections •••••••••••••••••••••••••• 3-8
D-bus Intercabinet Connections •••••••••••••••••••• 3-9
Typical DC Power Connections ••••••••••••••••••••• 3-11
Example of I/O Expansion ••••••••••••••••••••••••• 3-12
Terminal Strip Installation •••••••••••••••••••••• 3-14
Ground Wire Fastening •••••••••••••••••••••••••••• 3-15
Module and Screw Terminal Configurations ••••••••• 3-16
Termination Cable Installation ••••••••••••••••••• 3-17
Plastic Cover Installation ••••••••••••••••••••••• 3-18
H7870 Power Supply Conversion •••••••••••••••••••• 3-19
H7872 Power Supply Conversion •••••••••••••••••••• 3-20
I/O Subsystem Rear Mounting Dimensions ••••••••••• 3-21
NEMA-12 Enclosure •••••••••••••••••••••••••••••••• 3-22
Typical Disconnect Operating Handle •••••••••••••• 3-23
NEMA-12 Type Enclosures •••••••••
3-24
Cabinet Power Versus Site Temperature •••••••••••• 3-26
Typical NEMA-12 Cabinet Installation ••••••••••••• 3-28
Typical Control Wiring ••••••••••••••••••••••••••• 3-29
M87l9 UNIBUS I/O Control Module •••••••••••••••••• 3-32
M87l9 Address and Vector Selectors ••••••••••••••• 3-33
M7858 I/O Control Module ••••••••••••••••••••••••• 3-34
M7958 Address and Vector Selectors ••••••••••••••• 3-35
M7959 I/O Control Module ••••••••••••••••••••••••• 3-36
M7959 Address and Vector Selectors ••••••••••••••• 3-37
H333 Module Chart •••••••••••••••••••••••••••••••• 3-38
H334 Module Chart •••••••••••••••••••••••••••••••• 3-39
Functional I/O Module Chart •••••••••••••••••••••• 3-40
I/O Cable Connector Interface •••••••••••••••••••• 3-42
0

vii

••••••••••••••••

3-33
4-1
4-2
4-3
4-4
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22

5-23
5-24
5-25
6-2-1
6-2-2
6-2-3

6-3-1
6-3-2
6-3-3
6-4-1
6-4-2

6-4-3
6-5-1
6-5-2

6-5-3
6-5-4
6-6-1
6-6-2
6-6-3
6-7-1
6-7-2

Processor Interface Configurations ••••••••••••••• 3-46
4-2
Ty pic a 1 Ad d res s As s i 9 nm en t: s . . . . . . . . . . . . . " . . . . . . . .
lOR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
I A R Fo rm at ••••••••• " •••••••••••••••••••••••••••••
4-3
CSR Fo rma t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
I/O Subsystem ••••••••••••••••••••••••••••••••••••
5-2
IOCM Applications ••••••••••••••••••••••••••••••••• 5-3
DA TA I ••••••••••••••••••••••••••••••••••••••••••••
5-5
Ad d res sin g ......................................... .
5-4
Da ta In pu t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7
DATAO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9
Da t a au t put ••••••••••••••••••••••••••••••••• <. • . •
5-10
DATAl with Modified D-bus Cycle . . . . . . . . . . . . . . . . . . . 5-11
Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Interrupt Timing ••••••••••••••••••••••••••••.
5-14
Ma i n ten a n c e Mo de. • • • • • ••
5-15
Maintenance Cycle Timing ••••••••••••••••••••••••• 5-16
DATA I Cycle Timing •••••••••••••••••••••••••.
5-17
Addressing ••••••••••••••••••••••••••••••••••••••• 5-18
Da ta In put . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
DATA a Cycle Timing •••••••••••••••••••••••••••••• 5-21
DATA Ou tput •••••••••••••••••••••••••••••••••••••• 5-22
DATI with Modified D-bus Cycle ••••••••••••••••••• 5-23
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
I/O Subsystem PDP-II Based Interrupt Timing •••••• 5-25
Maintenance Mode (M=l in CSR) •••••••••••••••••••• 5-26
Maintenance Cycle Timing .~ ••••••••••••••••••••••• 5-27
H7870 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
H7872 Power Supply Block Diagram •••••••••
5-29
H7872 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Module M5010, 32-Bit Nonisolated DC Sense,
S i mpI if i ed Bloc k Di ag ram . . . . . . . . . . . . . . . . . . . . . . . . . 6-2-2
M5010 32-Bit DC Sense Module •••••••••••••••••••• 6-2-4
Ad d res s Se 1 ec t ion Sw i tc h ........................ . 6-2-4
16-Bit COS Input Module M5011, Simplified
Block Diagram ••••••••••••••••••••••••••••••••••• 6-3-2
M5011 16-Bit COS Input •••••••••••••••••••••••••• 6-3-5
Address Selection Switch •••••••••••••••••••••••• 6-3-6
Module M5012, 16-Bit Isolated DC Input Module,
Simplified Block Diagram •••••••••••••••••••••
6-4-1
M5012 16-Bit Isolated DC Input . . . . . . . . . . . . . . . . . . . 6-4-4
Address Selection and Interrupt Enable •••••••
6-4-4
M5012-YA 16-Bit TTL Compatible Input Module,
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5-1
M5012-YA 16-Bit TTL Compatible Input Module •• '0 •• 6-5-4
M5012-YA Address Selection and Interrupt
Enable Switch •••••••••••••••••••••••••••••••••
6-5-4
M5012-YA Typical TTL Fi eld In te r face •••••••••.
6-5-6
Module M5013 8-Bit AC Input Simplified
Block Diagram ••••••••••••••••••••••••••••••••.
6-6-2
M5013 AC Input Module ••••••••••••••••
6-6-4
Address Selection and Interrupt Enable •••••••••• 6-6-4
M5014 Counter Module, Block Diagram ••••••••••••• 6-7-2
M5 0 1 4 Co un t e r Mo d u 1 e •••••• <. . . • • • • • • • . . . . . . . . . . . . 6-7-3

.....................0....
<

• • • •

•••••••

<..

viii

••••••••••

6-7-3
6-7-4
6-7-5
6-7-6
6-7-7
6-7-8
6-7-9
6-7-10
6-7-11
6-7-12
6-7-13
6-7-14
6-8-1
6-8-2
6-8-3
6-8-4
6-8-5
6-8-6
6-8-7
6-8-8
6-9-1
6-9-2
6-9-3
6-10-1
6-10-2
6-10-3
6-11-1
6-11-2
6-11-3
6-11-4
6-12-1
6-12-2
6-12-3
6-12-4
6-12-5
6-13-1
6-13-2
6-13-3
6-14-1
6-14-2
6-14-3
6-14-4
6-15-1
6-15-2
6-15-3
6-15-4
6-15-5

Anticoincidence Circuit ••••••••••••••••••••••••• 6-7-5
Anticoincidence Timing •••••••••••••••••••••••••• 6-7-5
54-13585 Daughter Board Block Diagram ••••••••••• 6-7-8
E~ect:ical and Logical Interface Simplified
CIrcuIt ••••••••••••••••••••••••••••••••••••••••• 6-7-9
Frequency and Time-Base Select Circuit ••••••••• 6-7-10
Counter Operating Modes •••••••••••••••••••••••• 6-7-12
Co un te r Enable (Co un te r A Shown) ••••••••••••••• 6-7-13
Address Selection Example •••••••••••••••••••••• 6-7-14
M5014 Isolated High Level Input Application •••• 6-7-17
M5014 Isolated Low Level Input Application ••••• 6-7-17
M5014 Nonisolated TTL Input Application •••••••• 6-7-18
Function Selector Switches - Usage Summary ••••• 6-7-20
M5016 Quad Input Counter/Prescaler
Block Diagram ••••••••••••••••••••••••••••••••••• 6-8-2
Counter Circuit ••••••••••••••••••••••••••••••••• 6-8-3
Reg ister Information ............................. 6-8-4
M5 01 6 Qu a d Co un t e r / Pre sea 1 e r •••••••••••••••••••• 6 - 8 - 5
Address Selection Example ........................ 6-8-6
Co un ter 0 Isolated Low Level
Input Application ••••••••• e • • • • • • • • • • • • • • • • • • • • • 6-8-7
Counter 2 Nonisolated Input Application ••••••••• 6-8-8
Function Selector Switches e • • • • • • • • • • • • • • • • • • • • • 6-8-8
M5031 16-Bit Isolated COS Input Module
Simplified Block Diagram •• e • • • • • • • • • • • • • • • • • • • • • 6-9-2
M5031 16-Bit Isolated COS Input ••••••••••••••••• 6-9-4
Address Selection Switch •••••••••••••••••••••••• 6-9-5
M6010 32-Bit DC Output Module, Simplified
Block Diagram •••••••••••••••••••••••••••••••••• 6-10-2
M6010 32-Bit DC OUtput •••• e • • • • • • • • • • • • • • • • • • • • 6-10-4
Address Selection Switch ••••••••••••••••••••••• 6-10-5
M6010-YA 32-Bit TTL-Compatible Output
Module, Block Diagram •••••••••••••••••••••••••• 6-11-2
M6010-YA 32-Bit TTL-Compatible Output Module ••• 6-11-4
M60l0-YA Address Selection Ex.ample ••••••••••••• 6-11-5
M6010-YA Typical TTL Field Interface ••••••••••• 6-11-7
M6011 16-Bit One-Shot Output Simplified
Block Diagram •••••••••••••••••••••••••••••••••• 6-12-2
Timer Selection Switches ••••••••••••••••••••••• 6-12-4
Anticoincidence Timing Diagram ••••••••••••••••• 6-12-5
M60ll 16-Bit One Shot Output ••••••••••••••••••• 6-12-7
Address Selection Switch ••••••••••••••••••••••• 6-12-8
M6012 8-Bit Isolated DC Output Module •••••••••• 6-13-2
M6012 8-Bit Isolated DC Output ••••••••••••••••• 6-13-4
Address Selection Switch ••••••••••••••••••••••• 6-13-5
M6013 8-Bit AC Output Module ••••••••••••••••••• 6-14-2
Output Switch and Control Oscillator ••••••••••• 6-14-4
M6013 8-Bit AC Output •••••••••••••••••••••••••• 6-14-5
Address Selection Switch ••••••••••••.••••••••••• 6-14-6
M6014 Dual Output Counter, Block Diagram ••••••• 6-15-2
M6014 Counter Module ••••••••••••••••••••••••••• 6-15-3
Daughter Board Block Diagram ••••••••••••••••••• 6-15-4
Frequency and Duty Cycle Select •••••••••••••••• 6-15-5
Output Control (for A Counter) ••••••••••••••••• 6-15-6

6-15-6
6-15-7
6-15-8
6-15-9
6-16-1
6-16-2
6-16-3
6-16-4
6-16-5
6-17-1
6-17-2
6-17-3
6-17-4
6-18-1
6-18-2
6-18-3
6-18-4
6-18-5
6-18-6
6-18-7
6-18-8
6-18-9
6-19-1
6-19-2
6-19-3
6-20-1
6-20-2
6-20-3
6-20-4
6-20-5
6-20-6
6-21-1
6-21-2
6-21-3
6-21-4
6-21-5
6-21-6
6-21-7
6-21-8
6-21-9
6-21-10
6-21-11
6-21-12
6-21-13
6-21-14
6-21-15
6-22-1
6-22-2
6-22-3
6-22-4

Output Control Timing ••••••••••••••••••••••••.• 6-15-6
Address Selection Example •••••••••••••••••••• ~. 6-15-7
M6014 Typical TTL Interface •••••••••••••••••• ~ 6-15-10
Frequency and Duty Cycle Selectors ••••••••••• '. 6-15-12
M6015 Retentive DC Output Block Diagram ••••••.'. 6-16-2
Single Output Circuit (Simplified) ••••••••••• ~. 6-16-3
M6 01 5 1 6 - Bit Re ten t i v e DC 0 u t put ..............'. 6 -1 6 - 5
Address Selection Switch ••••••••••••••••••••• ~. 6-16-6
Power Failure Modes ••••••••••••••••••••••••••.• 6-16-9
Analog Input Subsystem ••••••••••••••••••••••• ~. 6-17-2
Sample Program Flow Diagram ••••••••••••••••••.,. 6-17-7
Crosstalk Measurement Configuration •••••••••• '. 6-17-12
Analog Subsystem Handshaking ••••••••••••••••• ~ 6-17-13
Module A014 A/D Converter, Block Diagram ••••• ~. 6-18-2
A014 A/D Converter Module •••••••••••••••••••• ~. 6-18-3
Chan n elSe 1 e c t Co n t r 0 1 ••••••••••••••••••••••• '.. 6 -1 8 - 4
Multiplexer Select ••••••••••••••••••••••••••• ~. 6-18-4
Successive Approximation, Flow Diagram •••••••.• 6-18-6
A/D Converter Section Simplified
Circuit Diagram ••••••••••••••••••••••••••••••.• 6-18-7
Analog Subsystem Timing •••••••••••••••••••••• ". 6-18-8
I/O Control ••••••••••••••••••••••••••••••••••.• 6-18-9
A014 Module - Address, S END, and Manual
Test Selection •••••••••••••••••••••••••••••••• 6-18-11
A156 Analog Mul ti pI exer, Block Di ag ram ••••••• ~. 6-19-2
A156 Analog Multiplexer Module ••••••••••••••••• 6-19-4
Mu 1 tip 1 ex era nd Mo de Se 1 e c t ion ••••••••••••••• I'. 6 -1 9 - 5
A157 Wide-Range Analog Multiplexer ••••••••••••• 6-20-2
Channel Select and Auto-Zero Control ••••••••• ~. 6-20-3
Auto-Zero Timing ••••••••••••••••••••••••••••••• 6-20-5
Auto-Zero Circuit •••••••••••••••••••••••••••• ~. 6-20-5
Wide-Range Analog Multiplexer •••••••••••••••••• 6-20-6
Multiplexer and ATR16 Power Select ••••••••••• '.• 6-20-7
A020 Block Diagram ••••••••••••••••••••••••••••• 6-21-2
A020 A/D Converter Module ••••••••••••••••••••.• 6-21-4
Simplified Dual Slope Converter •••••••••••••••• 6-21-4
Dual Slope Converter Time Voltage
Relationships •••••••••••••••••••••••••••••••••• 6-21-5
A0 2 0 Da ug h t e r Bo a rd. • • • • • • • • • • • • • • • • • • • • • • • • • •• 6 - 21 - 6
Isolated, Selectable Range Integrating
Co nv e r te r ••••••••••••••' •••••••••••••••••••••••• 6-21-7
Conversion Cycle Timing (60 Hz Timing Shown)
6-21-9
A020 Module Switch Functions •••••••••••••••••• 6-21-13
Full Scale Range A Selections ••••••••••••••••• 6-21-15
Full Scale Range B Selections ••••••••••••••••• 6-21-16
Analog Input Configuration •••••••••••••••••••• 6-21-17
Source Unbalance •••••••••••••••••••••••••••••• 6-21-23
A020 Frequence Response ••••••••••••••••••••••• 6-21-25
Shielded Input •••••••••••••••••••••••••••••••• 6-21-26
Input Filter •••••••••••••••••••••••••••••
6-21-27
ATR16 Chassis Assembly ••••••••••••••••••••••••• 6-22-2
ATR16 Block Diagram •••••••••••••••••••••••••••• 6-22-3
Isothermal Assembly •••••••••••••••••••••••••••• 6-22-4
Temperature Transducer Circuit ••••••••••••••••• 6-22-4
0

••••

6-22-5
6-22-6
6-22-7
6-22-8
6-22-9
6-22-10
6-22-11
6-23-1
6-23-2
6-23-3
6-23-4
6-23-5
6-23-6
6-23-7
6-23-8
6-23-9
6-23-10
6-24-1
6-24-2
6-24-3
6-24-4
6-24-5
6-24-6
6-24-7
6-24-8
6-24-9
6-25-1
6-25-2
6-25-3
6-25-4
6-25-5
6-25-6
6-25-7
6-26-1
7-1
7-2

Ground Wire Fastening •••••••••••••••••••••••••• 6-22-5
Rear Mounting Dimensions ••••••••••••••••••••••• 6-22-6
2-Wire I/O Connections (A157 or A020) •••••••••• 6-22-7
3-Wire I/O Connections (A020 only) ••••••••••••• 6-22-7
Transducer Output Connection Options ••••••••••• 6-22-8
ATR16 Application •••••••••••••••••••••••••••••• 6-22-9
ATR16 Typical Characteristics ••••••••••••••••• 6-22-11
A630 DAC Module, Block Diagram ••••••••••••••••• 6-23-1
DAC Data Reg isters ••••••••••••••••••••••••••••• 6-23-2
A630 Four-Channel DAC, Module Block Diagram •••• 6-23-3
DA C Ci r cui t •••••••••••••••••••••••••••••••••••• 6 - 23 - 6
Status Bit Sl •••••••••••••••••••••••••••••••••• 6-23-8
Reference Supply •••.••••..••.•.••••••••.•.••••• 6-23-9
A630 DAC Module ••••••••••••••••••••••••••••••• 6-23-10
A630 Address Selection Example •••••••••••••••• 6-23-11
Voltage Reference and Current Mode Switches ••• 6-23-13
Calibration Resistor and Meter Lead Placement •• 6-23-14
A631 DAC Block Diagram ••••••••••••••••••••••••• 6-24-2
A631 DAC Data Registers •••••••••••••••••••••••• 6-24-3
DAC Circuit •••••••••••••••••••••••••••••••••••• 6-24-5
Isolated Power Options ••••••••••••••••••••••••• 6-24-7
Reference Circuit •••••••••••••••••••••••••••••• 6-24-8
A631 DAC Module •••••••••••••••••••••••••••••••• 6-24-9
A631 Address Selection Example •••••••••••••••• 6-24-10
Reference Voltage Selector Switches ••••••••••• 6-24-15
Re sistor and Me ter Lead PI acement Fo r
Current Mode Calibration •••••••••••••••••••••• 6-24-15
BC40L Screw Terminal Assembly ••••••.••....••••• 6-25-2
BC40L Circuits with Jumpers •••••••••••••••••••• 6-25-3
BC40L Cable Installation ••••••••••••••••••••••• 6-25-4
BC40L Simplified Schematic ••••••••••••••••••••• 6-25-6
Channel Number and Component Identifications ••• 6-25-7
Application Examples •••••••••••••••••••••••••• 6-25-10
Application Examples •••••••••••••••••••••••••• 6-25-11
A158 Block Diagram ••••••••••••••••••••••••••••• 6-26-1
Power Supply Adjustments •••••••••••••••••••••••••• 7-3
I/O Subsystem Trouble Analysis Flowchart •••••••••• 7-5

TABLES
Table No.
1-1
1-2
1-3
1-4
3-1
3-2
3-3
4-1
6-1-1
6-2-1
6-3-1
6-4-1
6-5-1
6-6-1
6-7-1
6-7-2
6-8-1
6-8-2

Page

Title

Subsystem Configurations Standard Equipment ••••••• 1-3
System Designations ••••••••••••••••••••••••••••••• 1-4
r10dule Descriptions •••••••••••••••••••••••••••••• 1-13
J~ppl icable Documents ••••••••••••••••••••••••••••• 1-19
System Power Supply Usage •••••••••••••••••••••••• 3-10
Type A Screw Terminal 16/32-Bit (BC40A) •••••••••• 3-43
~rype B Screw Terminal 8-Bit (BC40B)
•••••••
3-44
CSR Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
D-bus Interface Connector Pin Assignments ..
6-1-2
110dule M5010 I/O Pin Connections •••••••••••••••• 6-2-5
Module M5011 I/O Pin Connections ••••••••••
6-3-6
11odu1e M5012 I/O Pin Connections •••••••••••••••• 6-4-5
Module M5012-YA I/O Pin Connections •••••••
6-5-5
110dule M5013 I/O Pin Connections •••••••••••••••• 6-6-5
r10dule M5014 I/O Pin Connections (J31) ••••••••• 6-7-16
110d ule M5014 Fi eld I/O Screw
~rerminal Connections ••••••••••••••••••••••••••• 6-7-19
110dule M5016 I/O Pin Connections •••••••••••••••• 6-8-6
Module M5016 Field I/O Screw
're r min a 1 Co nne c t ion s •
6 - 8- 9
Module 5031 I/O Pin Connections ••••••••••••••••• 6-9-6
Module M6010 I/O Pin Connections ••••••••••••••• 6-10-5
110dule M6010-YA I/O Pin Connections •••••••••••• 6-11-6
On e Sh 0 t Ti m i ng Ra ng e .......................
6 -12 - 3
110dule M6011 I/O Pin Connections ................ 6-12-8
Module M6012 I/O Pin Connections ••••••••••••••• 6-13-5
110dule M60l3 I/O Pin Connections ••••••••••••••• 6-14-7
Module M6014 I/O Pin Connections ••••••••••••••• 6-15-8
110dule M6014 Field I/O Screw
~r e r min a 1 Co nne c t ion s . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -1 5 -11
M6015 I/O Pin Connections •••••••••••••••••••••• 6-16-6
116015 Field I/O Screw Terminal Connections ...... 6-16-7
Heg ister Byte Address Assignments •••••••••••••• 6-17-3
J~/D Channel Number Reg ister •••••••••••••••
6-1 7-4
r1ultiplexer Number Registers . . . . . . . . . . . . . . . . . . . . 6-17-4
J~/D Status Reg ister ••
6-1 7-5
Gain Codes ••••••••••••••••••••••••••••••••••••• 6-17-6
Crosstalk Error Measurements •••••••••••••••••• 6-17-12
Offset Binary Encoding ••••••••••••••••••••••••• 6-18-7
Module A014 I/O Pin Connections ................ 6-18-12
~rype A Screw Terminal 16/32 Bit (BC40A)
••••••• 6-18-13
A156 Operating States •••••••••••••••••••••••••• 6-19-3
Module A156 I/O Pin Connections •••••••••••••••• 6-19-6
110dule A156 Screw Terminal Connections ••••••••• 6-19-7
Gain Codes •••••••••••••
6-20-3
Module A157 I/O Pin Connections ................. 6-20-8
BC40A Screw Terminal Configuration ••••••••••••• 6-20-9
Da taRe g i s t e r s •••••••
6 - 2 1-1 0
i\bsolute Magnitude Code ••••••••••••••••••••••• 6-21-18
II

6-9-1
6-10-1
6-11-1
6-12-1
6-12-2
6-13-1
6-14-1
6-15-1
6-15-2
6-16-1
6-16-2
6-17-1
6-17-2
6-17-3
6-17-4
6-17-5
6-17-6
6-18-1
6-18-2
6-18-3
6-19-1
6-19-2
6-19-3
6-20-1
6-20-2
6-20-3
6-21-1
6-21-2

•

••••••••••••••••••••

•

••••••

•••••

•

••

••••

.....

••

•••••••••••••••••••••••

•

xii

•

••

6-21-3
6-21-4
6-21-5
6-22-1
6-22-2
6-23-1
6-23-2
6-23-3
6-23-4
6-23-5
6-24-1
6-24-2
6-24-3
6-25-1

Least Significant Bit Values •••••••••••••••••• 6~21-19
Module A020 Screw Terminal Connections •••••••• 6-21-20
Module A020 I/O Pin Connections ••••••••••••••• 6-21-21
ATR16 Power Swi tches ••••••••••••••••••••••••••
6-22-8
A/D Converter Characteristics ••••••••••••••••• 6-22-10
Voltage Output Bit Weights ••••••••••••••••••••
6-23-7
Current Output Bit Weights .G • • • • • • • • • • • • • • • • • •
6-23-7
Current Output Bit Weights ••••••••••••••••••••
6-23-8
Module A630 I/O Connections
6-23-12
Module A630 Screw Terminal Connections •••••••• 6-23-15
Bit Va 1 ue s ...................................... 6 - 24 - 6
Module A631 Screw Terminal Connections •••••••• 6-24-11
Module A631 I/O Connections ••••••••••••••••••• 6-24-12
Terminal Identification •••••••••••••••••••••••• 6-25-8

B-1

Priority Ranking for Floating Vectors ••••••••••••• B-1

xiii

••••••••••••••••••

CHAPTER 1
GENERAL INFORMATION
1.1

SCOPE

This manual provides a complete description of the I/O Subsystem,
including physical and functional level descriptions, installation
instructions, programming information, and maintenance procedures.

1.2

GENERAL DESCRIPTION

The I/O Subsystem is a cabinet-mountable subsystem that monitors
and/or controls industrial operations and equipment. The subsystem
is a highly flexible input/output device capable of interrogating
and driving digital and analog systems. The device interfaces with
the LSI-II or any other PDP-II family computer. It provides
real-time monitoring and control capability with minimal computer
overhead. Applications range from simple monitoring functions to
control of complex closed-loop systems. Environmental monitoring
and control, batch mixing, material handling, quality control, and
testing are but a few of the many applications for which the I/O
Subsystem is suited.
Because of the modularity of the device and the various types of
I/O modules offered, the I/O Subsystem is adaptable to many
different applications. The subsystem may contain a few or as many
as 80 I/O modules that are available to perform the following
functions.
Inputs
DC voltages
AC vol tag es
Change of state
Contact closure
A/D conversion
Event counting
Frequency measurement
Each I/O module
data.

handles

one

Outputs
DC swi tchi ng
AC switching
One-shot dc switching
D/A conversion
Pulse trains

bytes

(eight

bits)

Ilo

Communication between the I/O modules and the processor is via a
control module that interfaces their respective buses (Figure
1-1). These modules and buses are defined as follows.

H333 I/O Bus (O-bus)
This bus is etched on the lower half of the printed circuit
backplane in the I/O area of all module chassis. All I/O modules
and the I/O control module interface with this bus when plugged
into the backplane connectors.

LSI-II Bus
The LSI-li bus is included only in the H333 chassis. It is etched
on the upper half of the chassis backplane for all module
positions and on the lower half for the first
four module
posi t ions. Thi s bus inter faces wi th all LSI-Il opt ion mod ule s
including the I/O control module.
1-1

PROC:ESSOR
(LSI-111 OR PDP-11)

_ _ _ _- - . . . - - - - - - 1 ' - - -_ _ _ ~

I/O
NO.1

0-8US

", ~
~

,=:to

, ~
,.._.w.._,

r-~-_.

:'----~!

L ___ JI

I/O
NO. 80

~-----------------------r__----------------------J
I/O DATA
TO/FROM PROCESS
MA-0147

Figure 1-1

Processor I/O Interface

M87l9 I/O Control Module
The M87l9 interfaces with the UNIBUS via its etched edge
connector, and with the D-bus via a cable connector on the
opposite edge of the module. This module performs the data routing
and control functions that prev ide communication betwc~en the I/O
modules on the D-bus and the processor on the UNIBUS.
M7959 I/O Control Module
The M7959 interfaces with the LSI-II bus via its Htched edge
connector, and with the D-bus via a cable connector on the
opposite edge of the module. This module performs the data routing
and control functions that prov ide communica t ion between the I/O
modules on the D-bus and the processor on the LSI-II bus.
M7958 I/O Control Module
Th e M7 9 58 in t e r fa c e s wi t h t he LSI -11 bus 0 n the to p h a I f 0 f i t s
etched edge connector and with the D-bus on the bottom half. This
module performs the data routing and control functions that
provide communication between the I/O modules on the D-bus and the
processor on the LSI-II bus.
I/O Modules
All I/O modules interface with the D-bus via an etched edge
connector and with the I/O application via a cable connector on
the module.

1-2

1.3
EQUIPMENT DESCRIPTION
S tan dar d e qui pm en t
for a sub sys tern depend s
configuration
(Table 1-1). Optional equipment
application.

on the
depend s

c ho sen
on the

The re are fo ur bas i c hardwa re config ur a t ion d esig nato r s IP 110,
IPV10, IP300, and IPll (Table 1-1). All systems fall into one of
these four categories. The fifth character in the designation will
vary depending on the software provided. These software categories
are identified in Table 1-2.
NOTE
IPllS is a designation that was used to
denote IP1l2 systems shipped in early
1979. In this manual, all references to
IPllfll and IP1l2 apply equally to IPllS
systems.
Table 1-1

Subsystem Configurations
Standard Equipment
IP3fl1fl1 IPll

H960-C
H333
H334
M7958
M7959
M87l9
H7870
H7872
*
DLVll-F
RXVll-B
LSI-II
MSVll-DD
REVll-A
TEVll
DWll-A

Cabinet A or B (115 or 230 Vac)
Chassis A or B (115 or 230 Vac)
Chassis E or J ( 115 or 230 Vac)
I/O control module
I/O control module
I/O control module
Power suppl y (part of H333-A or -B)
Power supply ( part of H334-E or -J)
Term ina 1
Se rial line unit
Dual floppy disk and controller
Mi c rocomputer
28K memory
LSI-II terminator, boot module
LSI-II terminator module
UNIBUS to LSI-II bus converter module

X
X

X
X
X
X
X
X
X

Optional Equipment

H332
BC40A
BC40B
BC40L
ATR16

Expansion cabinet A or B (115 or 230 Vac)
Expansion chassis A, B, E, J, or X
(A, E = 115 Vi B, J = 230 Vi X = nonpowered)
Screw terminal mounting rack
16/32-bit screw terminal strip
8-bit screw terminal strip
16/32-bit terminal strip for user mounted components
Isothermal screw terminal assembly

1-3

*Choice of LA36, VT52, or VT100

H960-C
H334

IPllfll IPVlfll

Table 1-2

System Designations

Hardware
Only

With Software
RSX-IIM
RSX-llS
RSX-IlM+

IPl10

IPl12 *

IPV10

IPV12

IPV14

IP300

IP302

IP304

IPll

RTll
IPl14

IPl13

*IPl12 designator applies also to the old IPllS systems.
1.3.1
Hardware Configurations
The I/O Subsystem is available in the following configurations.
IP300 Subsystem
The IP300 is an independent, standalone
s ubsystern wi th its own bui 1 t- in LS I-II mic rocomputer. The computer
and its per i pheral s can occupy the first five mod ule posi tions in
the card cage. Figures 1-2 and 1-3 show the basic I/O Subsystem
components, the LSI-II computer, and their locations in the master
chassis.
IPl19 Subsystem - The
computer via a control
Interface with the I/O
of the control module
subsystem chassis.

IPl10 (Figure 1-4) operates with a PDP-II
module that plugs directly into the PDP-II.
modules on the D-bus is via a cable from JI
to the D-bus input connector of the first

IPll Subsystem - The IPll operates externally to a PDP-II host
computer via a UNIBUS to LSI-II bus converter module. Interface is
by a cable that plugs into a backplane-to-cable adapter at the I/O
Subsystem end and into the bus converter module at the PDP-II end.
Figure
1-5
shows
the
I/O
Subsystem
components
and
the
backplane!-to-cable adapter locations in the master cha.ssis. IPll
systems are recommended for replacement or expansion purposes
only. New PDP-II based designs should be implemented with an IPl10
config ur cltion.
IPVl9 Subsystem - The IPVl0 (Figure 1-6) operates wi th an LSI-II
computer (e.g., a PDP-ll/03 or PDP-II/23) via a control module
t ha t pI ug s d ire c t I y i n to t he LSI -11 • In t e r fa c e wit h the I/O
modules on the D-bus is via a cable from Jl of the control module
to the D-·bus input connector of the first subsystem chassis.
Expanded Subsystems - Any of the above subsystems can be expanded
beyond the initial chassis. Up to seven chassis can be added to
the subsystem; each accommodates ten additional I/O modules.

1-4

LSI-11 BUS

G7272

H7870

POWER SUPPLY

+12 V

876

O<U>00@0
DC
ON

LTC GND RUN

EN +6 V
HLT

H333 CHASSIS

LSI-11 BUS

D-BUS

M A-3094

Figure 1-2

IP300 - LSI-II Based Subsystem
(Current Version)

1-5

( ~----------------~~,--------

878

O(l00@0

+12 V

DC
ON

LTC GND RUN

EN +5 V
HLT

H333 CHASSIS

MA··0227

Figure 1-3

IP300
LSI-II Based Subsystem
(Older Version)

1-6

M8719
I/O
__--~~--__~~M CONTROL
MODULE

~--l

I/O MODULES

UNIBUS
SPC SLOT

H7872 POWER SUPPLY

&12

<W 0 [3

H334 CHASSIS
MA-2996

Figure 1-4

IPl10 - PDP-11 Based Subsystem
(Current Version)

1-7

M9401
CABLETO
BACKPLANE
ADAPTER
MODULE

-j

+-< <!!''-+___________ _

L..-_ _ _ _ _

LSI-l1 BUS CABLES
TO BUS CONVERTER MODULE

'"
(

H7870
POWER SUPPLY

+12 V

8 6 5

O(l00@0
DC
ON

LTC GND RUN

EN +5 V
HLT

H333 CHASSIS
LSI-11 BUS

D-BUS
MA-0228

Figure 1-5
IPll - PDP-II Based Subsystem
(Not Recommended for New Systems)

1-8

M7959

I/O
----~~--~~~ CONTROL

MODULE

I/O MODULES

LSI-11 BUS
QUAD SLOT

D-BUS
EXPANSION
CONNECTOR

H7872 POWER SUPPLY

V<t>

® 0 [3

H334 CHASSIS
MA-2996A

Figure 1-6
1.3.2

IPVl10 LSI-II Based Subsystem

Standard Equipment

H960-C Cabinet - This 19-inch cabinet is standard with the IP300
subsystem and is recommended for the IPll and IPIIS. The cabin.et
has four units* of mounting space and comes equipped with an 8161
power controller and a blower, assembly (Figure 1-7). The H960"""CA
and H960-CB versions are 115 ~nd 230 Vac, respectively.
H333 Chassis - The H333 chassis comprises the H7870 power supply,
t.he module enclosure, and the M7958 I/O control module. The
enclosure has quad-height spaces for eight I/O modules and the
LSI-II modules (Figure 1-2). A dual-height space is provided for
the LSI-II bus terminator/boot module, and just below it is a
connector for expansion of the O-bus to additional chassis.
The LSI-11 bus and the O-bus ·are etched on the backplane of the
enclosure. The LSI-11 bus occ~pies the top half of the backplane
for all module positions and the bottom half for the LSI-11
positions. The O-bus is etched only on the bottom half of the
*A unit is any H333, H334, or H332 chassis.
1-9

eight I/O and IOCM positions. The M7958 interfaces with both
buses, but the I/O modules, which use only the lower half of their
etched edge connectors, interface only with the D-bus.
H334-E/J Chassis - The H334-E/J chassis comprises the H7872 power
s uppl y and the mod ul e enclosur e. The enclosur e has quad-he ig ht
spaces for ten I/O modules and connectors for input and output of
the D-bus which is etched on the C and D connectors of the
enclosure backplane.
H7870 Po~rer Supply - The H7870 power suppl y, used in both the H333
and the H334-A/B chassis, generates the dc operating voltages (+12
and +5 Vdc) required by the I/O Subsystem.

AIR FLOW

SCREW
TERMINAL
CHASSIS

I/O SUBSYSTEM
CHASSIS

861
POWER
CONTROLLER

MA-0157

Figure 1-7

H960-C Expansion Cabinet

1-10

H7872 Power Supply - The H7872 power supply is used in the H334
chassis only; it provides +12 Vdc for the I/O modules.
M7958 I/O Control Module - The M7958 is a quad-height module that
mounts in the H333 chassis and originates the D-bus. This module,
which bridges the two backplane buses, accepts LSI-II signals and
generates D-bus signals for routing data to and from the I/O
mod ules.
M7959 I/O Control Module - The M7959 is a quad-height module that
mounts in a quad slot in an LSI-II processor; it originates the
D-bus. A BC08R cable carries the D-bus to the I/O module chassis.
This module accepts LSI-II bus signals and generates D-bus signals
for routing data to and from the I/O modules.
M8719 UNIBUS I/O Control Module - The M87l9 is a quad-height
module tha t moun ts in a quad SPC slot in a PDP-II processor; it
originates the D-bus. A BC08R cable carries the D-bus to the I/O
module chassis. This module accepts UNIBUS signals and generates
D-bus signals for routing the data to and from the I/O modules.
LA36 Terminal - The LA36 DECwriter II is a medium sized, low cost,
interactive data communication terminal. It is designed as an
input/output device that can be used as a system command console
or as a remote commun ica tion term inal. The LA36 in ter faces wi th
the LSI-II bus via a cable to the DLVll-F (M8028) module.
VT52 Terminal (DECscope) - The VT52 is an upperASCII video terminal whose display holds 24
characters.

and lowercasie
1 i ne s 0 f
80

VT100 Terminal - The VT100 is DIGITAL's latest video terminal with
many new features not included in the VT52.
RX0l Di sk - The RX0l Floppy Di sk System is a com pac t, low cost,
mass storage subsystem, capable of storing up to 256,256 bytes per
drive in an industry-compatible format. The RX0l disk interfaces
with the LSI-II bus via the RXVll (M7946) module.
LSI-II Microcomputer - The LSI-II is a l6-bit microcomputer with
much of the speed and power of a minicomputer. As implemented in
the I/O Subsystem, the microcomputer occupies the first position
and hal f 0 f the second pos it ion on the LSI -11 bus; the KDll-H
(processor module) being first and an MSVll-DD (memory module)
second.
DWll-A UNIBUS to LSI-II Bus Converter Module - In the IPll, which
operates
with an
external
PDP-II
instead of the
LSI-II
microcomputer, its LSI-II bus must be adapted to the UNIBUS. This
function is performed by the bus converter module which resides on
the UNIBUS.
The module mounts in an SPC slot in a UNIBUS
processor. Interface with the LSI-II bus is via a cable to the
M940l (cable-to-backplane adapter module) which occupies a

1-11

dual-height module position on the LSI-II bus in the I/O
Subsystem. It is not recommended that the DWII-A based system
(IPl1) be used in new applications.
1.3.3
Optional Equipment
The following options may be purchased with the I/O Subsystem.
8334 Chassis - This chassis extends the D-bus to accommodate any
I/O modules in addition to those in the first chassis. Each H334
chassi s accommoda tes ten I/O mod ules. Ther e ma y be a s many as
seven chassis for a total of 70 I/O modules in addition to those
in the first chassis. The D-bus is etched on the lower half of the
H334 chassis backplane, which also includes cable connectors for
extendinq the D-bus from one chassis to another. There are five
versions of the H334 chassis: H334-A, -E, and H334-B, -J are for
115 Vac and 230 Vac, respectively. Version H334-X is nonpowered.
Versions -A, -B, and -x are for expansion or replacement purposes;
versions -E and -J are recommended for new designs. The rules for
using powered and nonpowered chassis in a particular appl ication
are discussed in Chapter 3.
8332 Screw Terminal Mounting Chassis - This chassis is mounted in
the cabinet directly above an I/O module chassis; it: holds the
screw terminal assemblies which are mounted directly above each of
the I/O modules.
Each chassis accommodates up to ten screw
terminal assemblies.
BC40 Screw Terminal Strips
These assemblies connect the
customer's I/O 1 ines to the I/O modules via convenient screw
terminals. Each assembly consists of a 34 screw terminal barrier
strip and an I/O cable connector mounted on a printed circuit
board. 1~he assemblies mount in the screw terminal chassis, one
above each I/O module, and connect to them via preassembled cables
supplied with the screw terminal assemblies. The BC40A is for 16and 32-bit modules; the BC40B is for eight bit modules. The BC40L
has a n E~ x t r a 1 a r g e p r in ted c i r cui t boa r d for the use 1:- wh 0 nee d s
space to add custom ci rcui ts, such as fil ters, attenuators, etc.
It is equipped with turret terminals for easy component mounting.
ATR16 Isothermal Screw Terminal Assembly
The ATR16 connects
thermocouple field wiring to an analog input subsystem. It accepts
up to 16 thermocouple inputs and provides a single ambient
temperature reference output.
I/O Modules
I/O modules provide the interface between the
process and the D-bus. Connection to the D-bus is via the bottom
two sections of the four-section, etched-edge connector. (The top
two sections are not functional on I/O modules.) Connection to the
process is via a cable connector on the opposite edge of the
board. 1'able 1-3 provides a brief description of available I/O
modules. (A more complete description is found in Chapter 6.)
These modules are optionally selected by the customer to suit his
particular application.

1-.12

Table 1-3

Module Descriptions

Module No.

Description

M50l0

Nonisolated,
32-bit, dc sense input
module, input range is from -30 V to
+55 V

M50ll

Nonisolated, 16-bi t, dc change-of-state
input module with optional interrupt
capability, input range is from -30 V to
+55 V

M50l2

Optically-isolated, l6-bit, dc input
module
with
optional
interrupt
capability
Module has individual input indicators on
field side of isolation
Input range is from -55 V to +55 V

M50l2-YA

TTL compatible version of the M50l2
without the input activity indicators

M50l3

Transformer-isolated, a-bit, ac input
module
with
optional
interrupt
capability
Module has individual input indicators on
field side of isolation
Inputs are protected from overvoltage
transients by MOVs
Nominal input is 120 Vac, 47 to 63 Hz

M50l4

Dual l6-bit presettable up-counters, with
internal frequency and time bases, for
pul se
wid th
event
counting
or
measurement
Accommodates isolated or nonisolated, low
or
TTL
field
level,
h ig h
level,
connections

M50l6

Quad, a-bit up-counters with presettable
overflow level,
for
prescaling
and
counting applications
Accommodates isolated or nonisolated, low
level or high level inputs

M5031

Optically-isolated,
l6-bit,
change-of-state
input
module
optional interrupt capability
Input range is from -55 V to +55 V

M60l0

Nonisolated, 32-bit, dc output module
with zener-protected Darlington output
swi tches

1-13

dc
with

Table 1-3
Module No.

Module Descriptions (Cont)
Description
Outputs
max imum

are

rated

250

rnA

and

M60l0·-YA

TTL compatible version of the M60l0 with
outputs rated at 40 TTL unit loads

M60ll

Nonisolated, 16-bit, one-shot module with
zen e r - pro t e c ted
Da r 1 i ng ton
0 u t put
switches
Outputs are rated at 250 rnA and 55 V
maximum
Ou t put tim i ng is selectable from 100
microseconds
to
is
5 second s
and
crystal-controlled

M60l2

Optically-isolated, 8-bit, dG output
module with zener-protected Darlington
output swi tches
Module has i.ndividual output indicators
on field side of isolators
Ou tput cur rent rat ing is 1 :A pl~ r output
up to a maximum of 4 A per module
Maximum field voltage is 55 V

M60l3

Transformer-isolated, 8-bit, ac output
module
Has individual output indicators on field
side of isolation
Outputs have MOVs for protection against
overvoltage transients and a current
rating of 2 A per output up to a maximum
of 8 A per module

M60l4

Dual, counter controlled, output pulse
generators
Frequency is selectable from 10 kHz to
0.2 Hz; duty cycle from 10% to 80%
Has sign/direction and enable outputs
All outputs are nonisolated and high
level or TTL compatible

M60l5

Optically-isolated, 16-bit, retentive, dc
output module with zener-protected power
FET 0 utput swi tches
Ou tputs are grouped in four ~I roups 0 f
four
Groups are isolated from ground and from
each other
Ou t put cur r ,e n t rat i n g i s 0. 2 5 Ape r
output

1-14

Table 1-3
Module No.

Module Descriptions (Cont)
Description
Output states are retained during a
computer power failure as long as the
user furnished field power supply is
present

A014

A/D converter 12-bit, with built in
multiplexer
to
accommodate
16
single-ended
or
eight
differential
inputs
Input .capabil ity can be expanded to 240
single ended or 120 differential by using
expansion multiplexer
modules
(A156
and/or A157)

A020

Big h common mod e A/ D con v e r t e r , f 0 l"
applications requiring isolation from
high
common
mode
voltages,
14-bit
magni tude pI us sign, built-in multiplexer
accommodates six tee n 2 -w ire 0 r e i g h t
3 -wi re inputs

A156

An expansion multiplexer that provides an
additional
32
single-ended
or
16
differential high level input channels
for the A014 A/D converter
Seven A156 multiplexers may be used to
provide up to 224 additional analog
inputs to the A014

A157

An expansion multiplexer that provides
prog rammable gain for low 1 evel field
inputs to the A0l4 A/D converter
Ac c e p t s 1 6 d iff ere n t i a l i n pu t s t hat can
be independently programmed for any of
e ig ht d i ffe rent gains between 1 and 1000
A total of seven A157s can be used to
provide up to 112 programmable gain
inputs for the A014

A630

Fo ur independent 10-bi t D/A converters
with current and voltage output options
Voltage outputs are 0-10.23 V at 15 mA;
current outputs are 0-20 mA or 4-20 mA

A631

Four isolated 12-bit D/A converters with
current or voltage output options
Outputs are group isolated from computer
ground
Voltage outputs are 0 - 10.2375 V at 5 mA;
current outputs are 0 - 20.475 mA
See
A631 section
in
Chapter
6
for
configuration
constraints
when
using
multiple A631 modules in current mode.
1-15

1.4

SPECIFICATIONS

1.4.1
Physical
Chassis Dimensions
H333
H334
H332

Chassis ~reight
H333
H334-A or -B
H334t-E or -J
H334-X
H332

40 cm X 48.26 cm X 27.28 em
(15.75 in X 19 in X 10.74 in)
40 cm X 48.26 cm X 27.28 em
(15.75 in X 19 in X 10. 74 in)
40 cm X 48.26 cm X 27.15 em
(15.75 in X 19 in X 10.69 in)
19. 5 kg
18.14 kg
8.62 kg
5.44 kg
7.71 kg

(43 1 b)
(40 Ib)
(1 9 1 b)

(12 lb)
(1 7 1 b)

1.4.2
f~nvironmental
The I/O Subsystem meets the requirements of DEC Standard 102 for a
class C E~nv ironment.
Temperature
Operatj~ng

+5 0 to 50 0 C (41 0 to 122 0 F)

ambient

(in DEC cabinet)
No noper ating
Humidity
Operating

Nonoperating
1.4.3
Power Requirements
In put vol tag e
Input cur ren t
H7870
H7872
Input frequency
Input power
H7870
H7872
Rid e t h r 0 ug h

10% to 95% relative h8midity
Max im urn we t b ul b : +32 C (89. 6 0 F)
Minimum dew point: +2° C (35.6 0 F)
10% to 95% relative humidity
100-127 or 200-254 Vac
4.2/2.5 A maximum
1.4/10 0 A max im urn
50 or 60 Hz +3 Hz
500 W max imum
170 W max im urn
If the input voltage is at or above
115
or
230
Vac,
it
may
be
interrupted for as lonq as three
cycles
without
affecting
the
subsystem.

1.4.4
Performance
Operational modes

Programmed I/O
Program interrupt

1-16

Number of digital
I/O bits (max imum)

256
320
2032

H333
H334

Subsystem
Chassis
D- bus 1 eng th

System configuration

8 max imum
15 m (50 ft)

max imum
I/O word selection

Directly addressable by byte,
I/O
module
addresses
are
switch-selectable

Maintenance features

Each module
type
has a
unique generic code that
enables checking of system
configuration.

Maintenance
interrupts
enable checking of interrupt
log ic.

Maintenance mode test checks
for data integrity of D-bus.

Output
back.

1•

Ad d res s 0 f h i g he s t p rio r i t Y
interrupting
module
is
available
at
time
of
interrupt service.

Priority is determined by
proximity to control module,
not by module address (on
multibyte I/O modules, lower
byte address has highest
interrupt priority).

Interrupts

module

data

reads

D-bus Cycle times
(nom inal)

DATAl
DATAO
DATAIO

Computer interface

The
interface is direct to
LSI-II
bus
or
UNIBUS
and
indirect to UNIBUS with DWll-A
bus converter.

Power Supply (H7870)
Input

4.8 microseconds
3.9 microseconds
6.0 microseconds

115 Vac, 47-63 Hz

or
230 Vac, 47-63 Hz

1-17

+ 5 Vd c reg u 1 a ted, 1 4 }\ max i mum
+12 Vdc reg ul ated, 6 1~ max imum

Outputs

NOTE

+5 V and +12 V combined loading
are not to exceed 122 w.
Features

Line time clock, switch-enabled
Power sequencing siqnals
OK/DC OK) for LSI-II
Swi tchable
indicator

HALT/ENABLE

(PWR

LSI-II RUNNING indicator
Cool i ng

Two fans provide 92 CFM for the
power supply and LSI-ll. The I/O
modules are cooled by
convection.

Heat dissipation

1706 Btu/hr maximum e}(:clusive of
heat dissipation due to field
input circuits
NOTE
Heat dissipation is a function
of the type and number of I/O
modules in use.

Power Supply (H7872)
Input

115 Vac, 47-63 Hz
or
230 Vac, 47-63 Hz
1~

Output

+ 1 2 Vd c r eg u I a ted,

Features

DC ON i nd i c a to r

Cool i ng

Single fan provides 46 CFM for
cooling the power supply.

Heat dissipation

560 BTU/hr maximum exclusive of
heat d issi pa tion due to field
input circuitry.

max i mum

NOTE
Heat dissipation is ,a function
of the type and number of I/O
modules in use.

1.5
APPLICABLE DOCUMENTS
Table 1-4 I ists documents appl icable to the I/O Subsystem.

1-18

Table 1-4

Applicable Documents

Title

Number

Description

Microcomputer
Handbook

EB-0658376

General handbook containing
LSI-II family hardware,
operation, processor, and
software information (H)*

861 Power
Controller
Maintenance
Manual

EK-861AB-MM

Operation and maintenance
of the 861 power controller

Digital Site
Preparation
Guide

EK-CORP-SP

(M,

A general site preparation
guide for equipment marketed by
Di g i tal Equi pmen t Co rpo ra tion
(H)

LSI-II User
Manual

EK-LSIII-TM

Contains hardware descriptions
and system information that
enables the user to interface
LS I-II componen ts. (H) *

DWII-A Unibus to
EK-DWIIA-IN
LSI-II Bus
Converter
Installation Manual

Contains hardware descriptions
and system information that
enables the user to effectively
utilize the DWII-A (H, S)*

DEC STD 102

Defines the environmental
conditions to which products
marketed by Digital Equipment
Corporation must conform (L)

PDP-II Peripherals
Handbook

EB-0596176

A general handbook containing
descriptions, specifications,
interfacing, and programming
information on PDP-II
peripherals and options (H)*

I/O Subsystem
Acceptance
Proced ure

A-SP-H333-0-7

A procedure used by field
service, after installation,
to ensure that the I/O
Subsystem is operational

I/O Subsystem
Diagnostic

MD-II-CVPCAD-0 A test program that helps field
service personnel isolate
faults quickly

(M)
(S)
(H)

In Microfiche Library
Ships with device on hard copy (when not part of
Microfiche Library)
Available on hard copy

1-19

(L)

Limited distribution

These documents can be ordered from:
Dig i tal Equi pment Cor pora tion
Accessories and Supplies Group
Cotton Road
Nashua, NH 03060
Attn: Documentation Products
Telephone: 1-800-258-1710

For information concerning Microfiche Libraries, contact:
Dig i tal Equi pment Co rpo ration
Micropublishing Group
BU/D2
Bedford, MA 01730

1-20

CHAPTER 2
SITE PREPARATION AND PLANNING
2.1

SCOPE

This chapter contains site preparation and planning information
for I/O Subsystems. Included are recommended physical, electrical,
and
environmental
requirements
that
facilitate
equipment
installation and maintenance, and optimize system performance.
The reader is referred to specific paragraphs in the Digital Site
Preparation Guide for most system requirements; however, some
information for I/O Subsystems in particular is included here.

2.2

GENERAL CONSIDERATIONS

Successful installation of an I/O Subsystem requires thorough
planning and preparation of the proposed site. In particular, the
reader is referred to the following paragraphs in the Digital Site
Preparation Guide.
1.1
1. 1. 1
1. 1. 2

2.3

Introduction
Selecting a Si te
Developing a Site

SITE PLANNING

Refer to the following paragraphs in the Dig ital Si te preparation
Gu ide.
1.5.1
1.5.5
1.5.5.3
1.5.6
1.5.7

2.4

Space Requirements
Fire and Safety Precautions
Da ta Protection
Securi ty
Operational Requirements

EFFECT OF ENVIRONMENT ON SYSTEM RELIABILITY

The computer area environment substantially affects overall system
reliability. Temperature cycling and thermal gradients induce
temporary or permanent microscopic changes in materials that can
affect performance and/or endurance. High temperatures tend to
increase the deterioration rate of most materials. High absolute
humidity (dew point) causes moisture absorption that can result in
dimensional and handling changes in paper and plastic media (line
printer paper, cards, paper tape, 'magnetic tape, etc.).
Static electricity and airborne dust are hazardous to system
reliability. Low humidity allows static electricity to build up,
while high dust levels clog filters and reduce the effectiveness
of the cooling system. Dust also reduces magnetic tape life and
increases head wear, causing data errors in all moving magnetic
storage media (drums, tapes, and disks). Vibration also causes
slow degradation of mechanical parts, and when severe may cause
errors on disks and drums.
Hardware log ic errors can be caused by radio frequency pulses
conducted through power ma ins or radiated through space. Such

2-1

pulses could come from nearby radar installations, broadcasting
stations, or welding operations. Pulses can also come from arcs
that occur when static electricity is discharged, or from arcing
relay or motor contacts.
An y 0 raIl 0 f t he abo vee n vir 0 nm en ta 1 fa c to r scan be so ur c e s 0 f
eventual
system or component
failure.
For more detailed
information on these factors, refer to the following paragraphs in
the Digital Site Preparation Guide.

1.8
1.9
1.10
4.6.1
Chapter 5

Vibration
Lighting
Cleanliness
Static Electricity
Temperature and Humidity

2.5
POWER REQUIREMENTS
Power requirements vary according to the system configuration
selected, as discussed in Paragraph 2.7.4. Information on power
requirements in general is found in Chapter 2 of the Digital Site
Preparation Guide. Particular attention is called to the following
pa r ag raphs.
2.1
2.3
2.11

Introduction
Power Wiring and Color Coding
Powe r Co ntroll er

2.6
SYSTEM GROUND
The importance of good system grounding practices cannot be
overemphasized. Refer to Chapter 3 of the Digital Site Preparation
Guide for information on grounding and in particular to the
followinq paragraphs.
3.1
3.2
3.3
3.4

Introduction
Safety Log ic Ground
Common Grounding Practices
Grounding Requirements

2.7
SYSTEM CONFIGURATION
Although I/O Subsystem configurations differ according to
individual customer requirements and options, a study of the
following
typical
site
requirements
provides
sufficient
information for proper site planning.
2.7.1
System Configuration Diagrams
The I/O Subsystem diagrams in Figures 2-1 through 2-4 illustrate
typical small and large system configurations as wl~ll as the
physical location of cabinet-mounted components.

2-2

H960
CABINETS

TERMINAL

SCREW
TERM

H333
CHAS 1

H334
CHAS 2

H334
CHAS 4

H334
CHAS 6

H334
CHAS 8

RX01

SCREW
TERM

H334
CHAS 3

H334
CHAS 5

H334
CHAS 7

I I

I
MASTER
CABINET

I I
EXPANSION
CABINET 1

I I

I I
EXPANSION
CABINET 3

EXPANSION
CABINET 2

LSI-11 BASED
TYPICAL LARGE
I/O SUBSYSTEM

I
EXPANSION
CABINET 4
MA-0223

Fig ur e 2-1

IP300 LSI-II Based Configurations

H960
CABINET
SCREW
TERM

CHAS 1

~--MINIMUM SYSTEM

FIRST CHASSIS IS
1 - - - " " 1 H333 FOR DPM50 OR I P11

H334 FOR IP110 OR IPV10
ALL OTHERS ARE H334

LSI-11 (IP11)
SERIAL (DPM50)
OR
D-BUS (IP110
OR IPV10)

H960
CABINETS
SCREW
TERM

LSI-11 (IP11)
SERIAL (DPM50)
OR
IJ-BUS (IP11 0
OR IPV10)

SCREW
TERM

CHAS 1

CHAS 3

CHAS 5

CHAS 7

SCREW
TERM

CHAS 2

CHAS 4

CHAS 6

CHAS 8

MASTER
CABINET

EXPANSION
CABINET 1

I l
EXPANSION
CABINET 2

TYPICAL
-LARGE
SYSTEM

J
EXPANSION
CABINET 3
MA-0193

Figure 2-2

UNIBUS or Serial Bus Based Configurations
2-3

FRONT - - - . .

~-.-or---------TERMINAL
CHASSIS
(H332)

H333 CHASSIS

----

I ==II i I__--~ ~

f----

RX01
DUAL FLOPPY

8611?OWER
CONTROLLER

MA-0158

Figure 2-3

LSI-II Based Minimum Configuration

2-4

FRONT~

J-1

P
p ~

D--~

REAR

0
0 ---~

CHASSIS 1
(H333}

SCREW
TERMINAL
CHASSIS
(H3321

.------ -

8 Oem
(3 1.50")

0
~ 0

40em
5
(l

T")

..-------I

SCREW
TERMINAL

L.--- CHASSIS
(H3321

- --

CHASSIS 2
(H3341

861 POWER

I
I

"1
1

CONTROLLER

MA-0159

Figure 2-4

Expanded I/O Subsystem

2.7.2
Cabinet Space Requirements
Once the system configuration has been established, space
requirements can be determined by studying Figure 2-5 which shows
space requirements for single. and multicabinet installations. In
add i t ion t o t he s pa c e r e qui red for the e qui pm en t cab i net $ ,
provision must be made for other si te requirements, as discussed
in Paragraph 2.3. Careful consideration should also be given to
providing space for possible future expansion.
2.7.3
Cable Lengths
DEC cabinet interconnecting caples are of standard length and are
factory installed. If the cabinets must be shipped separately
because of shipping or receiving restrictions, the cabinet
interconnecting cables should be protected from damage by a
protective cover that does not present a safety hazard to
operating personnel.

2-5

18-7/32 in.
(46.3 emJ

55-2'7/32 in.
30in.
(76.2 em)

(141.8emJ

7-5/8 in.
(19.37enl_)_ _

I-

TYPICAL
LARGE CONFIGURATION
M,lI.-0182

Figure 2-5

Cabinet Space Requirements

2.7.4
j\C Power Connections
A 3-wi re cable, 4.6 m (15 ft) long connects the si te source power
to the 861 power controller in the bottom of the H960 cabinet. All
DEC-supplied cabinets used with I/O Subsystems include an 861
power controller and a single ac power cable. Power is distributed
to the equi pment wi thin the cabinet from the power controller
(Figure 2-6) •

The customer site must supply one outlet for each cabinet. In most
systems, it is conven i en t to prov ide a separa te load cen ter 0 r
circuit breaker panel for the system and to connect each
receptacle to its own circuit breaker. Applicable plugs and
receptacles are shown in Figure 2-7.

2-6

H960
DEC CABINET

POWER CONTROL BUS
FROM H7870 IF IP300
OR DPM50 SYSTEM
FROM CPU IF IPV10
OR IP110 SYSTEM

CABINET
FAN

..---

UPPER

I CHASSIS

I
---

I
H7870 OR H7872
POWER
SUPPLY

r
L

--'

r--

LOWER

CHASSIS

H7870 OR H7872
POWER
SUPPLY

SITE
POWER
SOURCE

POWER
CABLES

861
POWER
CONTROLLER

4.57M (15FT.) CABLE

AC
OUTLET

"SWITCHED"
RECEPTACLES

MA-0199

Figure 2-6

AC Power Distribution and Control

2-7

L5- :30R
(0) "5 VAC, SINGLE PHASE, 24 AMPS
(SOCKET VIEW OF FEMALE RECEPTACLE)

NEUTRAL OR PHASE
NEUTRAL P'REFERREO)

r;;;:s~

(GREENl~~HASE OR NEUTRAL

FRAME GROUND

L6-20R
(b) 2:30 VAC, SINGLE PHASE, 16 AMPS

CONNECTOR

N EMA NO.

115VAC

Receptacle

L 5·30R

Single phase

Plug

L 5·3OP

Receptacle

L 6-20R

Plug

L 6-2OP

POWER SOURCE

230 VAC
Single phase

POWER CONTROLLER
861·C

861·6

__ 1 - - ._ _ _ L -

\\-4081

Figure 2-7

Plug sand Re c e pt a c 1 e s (861)

2-8

CHAPTER 3
INSTALLATION
3.1
INTRODUCTION
The information in this chapter is supported by illustrations and
references to existing documentation relevant to integral units of
an I/O Subsystem. It provides the user with information required
to install and ensure proper operation of the I/O Subsystem.
Fig ure 3-1 is an install ation flow d iag ram that prov ides a quick
reference for locating procedures via paragraph numbers that apply
to the installation of the particular system purchased.
3.2
UNPACKING AND INSPECTION
The
following
information
applies
to
all
systems
configurations available as documented in this chapter.

and'

NOTE
The customer must not unpack the system
unless a DIGITAL representative is
present; to do so voids the warranty.
3.2.1
Unpacking
If the shi pment must be moved from the receiv ing area, make sure
that doorways and passageways are wide enough to accommodate
cab i net pa 11 e t s b e for e a t t em p tin g to m0 vee qui pm en t to i t $
selected location. Regardless of where unpacking and inspection i$
done, containers must not be removed from the pallets until the
shipment has been examined for possible damage. (Reimbursement for
damaged goods removed from the pallet is difficult.)
Perform the following unpacking procedure.
1.

Make sure that all containers are sealed. If any
container is open, notify the customer and record it on
the Installation Report or Field Service Report.

Check the shi pment against the packing list to make sure
that the correct number of containers has been received
and that they are the correct ones. If shi pnent is
incorrect, notify the customer and the Branch Service
Manager or the Branch Supervisor. The customer should
check with the carrier to locate any missing items.

Check all containers for external damage. Look for dents,
protrusions, holes, and smashed corners. Notify the
customer of any damage and record it on the Installation
Re po r tor Fi e 1 d Se r vic e Re po r t •

Open each container beginning with the one marked "OPEN
ME FIRST." Locate the packing slip and check the contents
of each container against its respective slip. Identify
any missing items on the Installation Report.

reshipnent

considered,

3-1

retain

packing

materials

s uc has foam fill e r sand pI as tic in se r t s .. In any cas e ,
retain the plastic (antistatic) bags in which any
individual modules are shipped.

YES

PERFORM STEPS

3.2.1. 3.2.2.
3.3.1. 3.3.4

YES

PERFORM STEPS

3.2.1. 3.2.2.
3.3.3.1. 3.9

YES

PERFORM STEPS
[

3.2.1. 3.2.2.
3.3.3.1. 3.3.4

YES

~)ERFORM STEPS

~.2.1. 3.2.2. 3.3.3.2

I/O MODULES
BEING ADDED
PERFORM STEP

3.3.3.3

PERFORM STEP

MA·0149

Figure 3-1

Installation Flow Diagram

3-2

3.2.2
Inspection
Perform the following inspection procedure.
1.

Inspect the outside of the equipment and/or cabinet(s)
for damage such as scratches, broken switches, broken
stabilizer feet, etc.

Inspect the interior of the equipment and/or cabinet(s)
fo r d amag ed components such as swi tches , i nd ica tors,
etc., or for loose and broken cable connections. Make
sure that all modules are securely seated in their
connec to r s.

Notify the customer of any damage found and record it in
the Ins tall a t ion Re po r t • No t i f y the Bra n c h S e r vic e
Manager immediately of any serious damage found.

Inspect each cabinet and free-standing peripheral to
make sure that it contains the items identified on the
keysheet or transfer sheet. Check the ECO REV level and
serial numbers against the keysheet or ECO status sheets.
Record any missing items, incorrect serial numbers, or
incorrect revision levels on the Installation Report.

When inspection has been completed, the equipment and the
cabinet(s)
can be removed from the shipping pallet.
Remove the cabinet(s) as directed below.
a.

Unbolt the cabinet(s) from its shipping pallet. The
bolts are located on the lower supporting side railt
and can be reached from the inside of the cabinet.

Rai se the
casters.

Use wooden blocks and planks to form a ramp from the
pallet to the floor and carefully roll the cabinet(s)
onto the floor.

Remove the four screws that secure the power supply
in place in any powered H333 or H334 chassis. These
screws are for shi-pping only and must be removed to
allow access to the power supply.

stab il i zing

feet

above

the

1 evel

0 f

the

3.3
INSTALLATION OF I/O SUBSYSTEM
This section covers installation of the I/O Subsystem and
procedures for expanding an existing system. A full complement of
related documents is included with the system shipment. The system
may utilize additional functional I/O modules by adding H960
cabinets and H334 expansion chassis. Each H334 provides mounting
space for up to ten functional I/O modules. A maximum of seven
H334 expansion chassis can be added to a subsystem.

3-3

CAUTION
Before removing or replacing an I/O
module or IOCM, turn off the power
switch for the entire I/O subsystem (not
just the single chassis). Failure to do
so invariably damages the module.
3.3.1
Cabinet Installation
If the system being installed is a
it will consist of the following.

single cabinet configuration,

H96'~-C cab inet
H333 chassis if the system is an IPll or IP300
H334 chassis if the system is an IPV10 or IPl10

Opt:Lons
H332 screw terminal cage
BC40 screw terminal assemblies
ATR16 isothermal screw terminal assemblies
H334 chassis
I/O mod ul es
Other cabinet-mounted peripherals
Connections within the H960-C cabinet are completed prior to
system shi pmen t. Po si t ion the cab inet in its pro per location and
adj ust the 1 evel ing feet to make sure that all 1 evel ing feet are
res t i ng firm 1 yon th e floor. A s t a nd a r d H96 0 -C A c ab i n €~ t i s s ho wn
in Figure 3-2.
3.3.2
Intercabinet Connections (Expanded System)
If a larqer system is purchased, additional cabinets and equipment
are required as indicated in Paragraph 3.3. A lar'ger system
includes all parts listed in Paragraph 3.3.1, plus the following.
One to four H960-C cabinets
One to seven H334 chassis
Up to seven H332 screw terminal cages
Filler strips and hardware
When th1e unpacking and inspection procedures described in
Paragraph 3.2 have been completed and the equi pment has been moved
to its selected location, proceed to the following steps.
1.

Remove the side panel from the master cabinet. If the
expansion cabinet(s}
is
to
be
installed
as
the
configuration in Figure 3-3, remove the right side panel.
NOTE
Expansion cabinets do not have side
panels. The panel removed from the
master cabinet is installed on the last
expansion cabinet in the configuration.

3-4

FRONT~
/R:::EW
I

, _ _ TERMINAL

.--.;....---;-

..--------

o
o

80cm

CHASSIS
(H332)

FIRST 1/0

J--+- CHASSIS
_____- -

(H333 OR H334)

----

CHASSIS

0 ___~'H""

1
L~J_'~_ I~~O_"""""_~_---''-''--''''

(3'1°"1:

MA-3097

Figure 3-2

Standard H960-CA Cabinet with Expanded I/O Subsystem

The expansion cabinet(s} has two filler strips attached
(Fig ure 3 -4) tha t are pI ac ed between any two adj ac en t
cabinets. Remove the socket-head screws and Kep nuts
( four pe r fill e r s t rip) ho 1 din g e a c h fill e r s t rip t 0 the
expansion cabinet.

Move the master cabinet and the first expansion cabinet
together and place filler strips between them, one at a
time.
Insert
the
socket-head
screws
through
the
respective holes in the cabinets and fillers.

Fasten the Kep nuts onto the screws and tighten securely.

Adj ust the 1 evel ing feet unt il both cab inets ar e 1 evel
and all leveling feet are resting firmly on the floor.

Continue
the
above steps
until
all cabinets are
connected. Install the side panel removed in step 1 on
the exposed side of the last cabinet.

3-5

FRONT VIEW
TYP. MAXIMUM CONFIGURATION

MASTER
CABINET

FAN ASSM.
H
332

FRONT

MINIMUM
CONFIG.

FAN

H332

CHASSIS #1

CHASSIS #2

CHASSIS #4

CHASSIS #6

H332

CHASSIS #3

CHASSIS #5

H332

REAR

- -

FAN

EXPANSION
CABINETS

H332

FAN ASSM.
H
332

REAR

I
CHS

I
I

0"1

r""
.J

I
I

861

OTHER CABINET
MOUNTED PERIPHERALS
H332's (Optional)

J
MASTER
CABINET

H332

CHASSIS #7

861
PWR

PWR CNT'l

PWR

* ADDITIONAL SPACE FOR

•

H332

CHASSIS #8

.1 .1
#2

.1 .1
#3

I-

Fig ure 3-3

EXPANSION CABINETS

.1
#4

1~
.1

FRONT

------

NOT USED
IN CAB. #4

~----

I
I
I

---------t...1
MA-0214

I/O Subsystem Front View

MA-0160

Figure 3-4

Cabinet Filler Strips

3.3.2.1 Ground Strapping Connections
Establ ish system frame
ground in all cabinets by connecting all adjacent cabinet frames
together, using the grounding straps provided. Exercise the
grounding practices referenced in Chapter 2 of this manual and
described in the Digital Site Preparation Guide (EK-CORP-SP).
3.3.2.2 Remote Power Connections - All cabinet power controller$
must be interconnected by a remote swi tching control bus. Th i s
enables power to all cabinets to be turned on or off from a single
control point. Refer to Figure 3-5 for instructions. All H7870 and
H7872 power supplies must be controlled by the master power
switch.
3.3.2.3 D-bus Connections - Each expander is provided with a 180
cm (6 ft) BC08R shielded cable for interconnecting the D-bus
between all cab inets. Fig ure 3 -6 shows a max imum config ur at ion and
illustrates how the cables are connected.
The top/bottom
orientation of the cable connectors, as determined by the position
of the striped cable wire, must be consistent throughout. The I/O
modules in the H333 and H334 chassis are positioned in right to
left sequence. If any slot between two I/O mod ules is empty, a
daisy-chain continuity module (M9019) must be inserted in
connectors C and D of that location to maintain continuity of the
D-bus.

3-7

RED

BlK
GRN

CONTROL BUS
CONNECTOR

MATING CABLE CONNECTOR
(ONE END OF REMOTE SWITCHING CONTROL BUS)

[-r;==:===-=-~=O=SW=:'T=:;=CH'='EO=====-=--'T[~PO=W-=ER=-CO=-NT=R~L 86\~===RE"=O=TE==LO=C=AL=====--=-=---"T-C=-=--=UN=SW='T=Ci1=E"=o==:;---,

-(:~:')-(':)T)(':;:) GS~:') ~;~lm\:'M' ~ f : f ~ ~ (~©

O~O (.;.)C.:t)
[~------------__--~--_'~----__- -

[

®@@@

To install remote switching power control bus:
1.

Plug one end into any unused power control connector on the 861 power controller panel, shown
above, and plug the other end into any unused connector in the 861 controller in the next cabinet.

When all controllers have been bused together in this manner, bus the one in the master cabiret to
the H333 front panel power control connector (IP300 and DPM50 systems), or the CPU pJwer
control connector (IP11, IP11 0, and IPV10 SYSTEMS).

TO CPU
(CONTROL POINT FOR
IP11, IP110, OR IPV10)

REMOTE SWITCHING
POWER CONTROL BUS

~~ D

EX.

~
FRONT OF H333 CHASSIS
(CONTROL POINT FOR IP300 AND DPM50)

Figure 3-5

MA-0200

Remote Power Connections

3-8

FRONT VIEW MAXIMUM CONFIGURATION

H332

H332
SCREW
TERM .... ,,'
.",

---- -~~-'--;';33
•

H332

H334

~~
,',.

I
I
II

H332

CHASSIS

H332

~"--'

--'OlJT

:'r

H334/,'
IN ,/,/
,-'

1f:.>·OUT

H332

:
I

//
~

H334

.4 ill OUT

H334 I I
IN ....',/

H332

II IN

_IN
.OUT

•
IN
_OUT

H332

1/
~I H334//
' ,

. . IN
OOUT

"r-------- -

I~,;;~'

~IJ>OUT

I/O MODULES
I/O
. . - - - - - -.....
" - - - -____,, CNrL
14{,3 12 11 10 9
8
6
4

H334

'tf!i~gttttl

D-BUS

w
I

\.0

BC08R D-BUS CABLE
MAXIMUM LENGTH = 15_2 M (50FT.)

NOTE: IF AN EMPTY
SLOT EXISTS
BETWEEN TWO I/O
MODULES THEN:

BACKPLANE CHASSIS 1
H333

7
4
5
3
8
BACKPLANE CHASSIS 3

DAISY CHAIN
CONTINUITY
BOARD MUST
BE INSERTED

I/O MODULES
BC08R CABLE
D-BUS

9
CONN
TOP

MASTER
J1 (OUT)

CONN
TOP

D~DJ1(JNI
\~LE
.

}
=

PROPER
CONNECTION

TOP

~J1(INI}=
J1(OUTI~

MASTER

H334
IMPROPER
CONNECTION

FOR PROPER INSERTION

TOP
MA-0229

Fig ure 3-6

D-bus Intercabinet Connections

3.3.2.4 DC Power Connections - In the standard configuration, dc
power to the module chassi s
(+12 V, +12 VB, and +5 V when
required)
is provided by the H7870 and H7872 power supplies
included in the H333 and H334 chassis, respectively. Alternate
configurations use only the H7870 power supply.
Standard .3nd alternate power supply configurations for all I/O
Subsystems are listed in Table 3-1. The table shows that an H333
chassi s occupies the first po si t ion in all I/O SubsystE!ms except
the IPl10 and IPV10. The H334 chassis occupies all subsequent
positions and the first position of an IPl10 or IPV10 system. In
all systems the chassis are numbered one through eight.
The H334 -x chassi s doe s not incl ude a power suppl y and must be
powered by connecting it to a powered chassis. A 3-conductor, 1.8
m (6 ft) Gable (Figure 3-7), is provided for this purpose. Figure
3-7 shows a typical power interconnection configuration.
Table 3-1

System Power Supply Usage

Standard Configurations

239 V

Posi tjlQD

Chassis

1 2 3 4 567 8

H7870

H333-A

H7870

H333-B

H7872-A

H334-E

H7872-B

H334-J

X X X X X X X

H7872-A

H334-E

H7872-B

H334-J

X X X X X X X X

IP300
or
IPll
IPl10
and
IPV10

System

115 V
Power
Supply

Power
Su.pply

Alternate Configurations
115 V

System
IP300

IPll

IPl10
and
IPV10

Power
Supply

Chassis

Power
Supply

H7870
H7870
None

H333-A
H334-A
H334-X

H7870
H7870
None
H7870
None

239 V

PositioD

Chassis

1 2 3 4 567 8

H7870
H7870
None

H333-B
H334-B
H334-X

H333-A
H334-A
H334-X

H7870
H7870
None

H333-B
H334-B
H334-X

H334-A
H334-X

H7870
None

H334-B
H334-X

3·-10

X
X

H333 CHASSIS
H7870 PS
POWERS LSI-11 OPTIONS
AND FIRST 8 I/O MODULES

BDZi~~11la 8 8 8 ~ ~
I

+5 B

+12 B +12 V GND

I
I
I
I

CABLE

+5 V

//
/
H333A (B) CHASSIS #1

LEVEL

COLOR

LENGTH

+12 B

ORANGE

SHORT

+12 V

ORANGE

MID L

GND

BLACK

LONG

~~~

I I Ibid I I Iolor1

Trrl'rn III

CHASSIS #2

CHASSIS #4

"T1Trrn II

I
I

+12 B +12 V GND

:
~ <W ~
L_~

EACH NONPOWERED H334 IS PROVIDED WITH A 6 FT POWER INTERCONNECT CABLE_

WHEN INSTALLING THE POWER INTERCONNECT CABLE MAKE SURE THAT THE +12 V AND +12 B
WI RES ARE NOT INTERCHANGED.
MA-3000

Fig ure 3-7

Typical DC Power Connect ions

3.3.3
Expanding an Existing System
This section covers installation of new cabinets and
chassi s.

additional

3.3.3.1
Adding New Cabinets - To add new cabinets to an existing
system, remove system power and follow the procedures in
Paragraphs 3.2 through 3.3.2.4.
3.3.3.2
Adding H334 Chassis to Existing System - The information
in this section and the cabinet installation procedure in
Paragraph 3.3.2 provides enough information for expansion to at
maximum configured system.

3-11

If there is space available for adding a new chassis in the
original cabinet, but not enough module slots, the customer may
order a number of H334 chassis and I/O modules. He may also
buy screw terminal assemblies to accommodate the H334 field
wiring ..
The follolwing proced ure d esc r ibes the method for install ing an
additional H334 chassis and screw terminal assembly in the unused
mounting space of an existing system.
1.

F~emove

system power.

Hemove the two pop-out panel s and the moun ting hardwa re
from the front lower half of the expansion cabinet. These
panels may be discarded.

~lount

the H332 screw terminal cage and
in the cabinet (Figure 3-8) •

the H334 chassis

EXPANSION
CABINET #1
(See Figure 3-3)
H332 SCREW

~TERMINAL

I~I================:

DOORS

POWERED
H334A(B)
CHASSIS #1

~ 4 SCREWS/SIDE WITH SPACERS

;11
e

H33'SCREW
- - TERMINAL CAGE

AVAILABLE
SPACE

80cm
(31.50")

NOTE: BOTH SCREW
TERMINAL & EXP
CHASSIS EQUIPPED WITH DOORS (REPI.ACE
POP OUT PANELS)
MA-0161

Figure 3-8

Ex ampl e
3-12

0 f

I/O Ex pansion

NOTE
For shipping purposes only, the power
supplies are secured in place with four
screws through the bottom of the H334
chassis.
Remove the screws at this time
to allow access for future servicing.
4.

Install the BC40A and/or BC40B screw terminal strips
(Figure 3-9). Some installations substitute BC40L screw
terminal strips in place of BC40As in order to provide
space for user mounted components. The BC40L and its
installation are described in Chapter 6.

Install the D-bus cable as described in Paragraph 3.3.2.3
and shown in Fig ure 3 -6.

Install the dc power harness as described
3.3.2.4 and shown in Figure 3-7.

Fasten the ground lug to the equipment rack side rail
with the 10-32 X 1/2 inch screw, 10-32 Kep nut, and No.
10 external tooth lockwasher provided. The lockwasher
must be placed under the ground lug and the nut fastened
securely to ensure good contact with the equipment ground
t h r 0 ug h the pa in t (F i g u r e 3 -1 0) •

Paragraph

3.3.3.3
Adding New M9dules to an Existing System - Perform th~
following steps and insert the I/O modules into the H334 chassis •.
CAUTION
I/O Subsystem modules utilize CMOS
devices and require special handling to
prevent damage from static charges. Each
new module is in an antistatic plastic
envelope to protec t i t from stat ic
voltages. Do not remove the module from
the pI astic envelope until just before
installation. Hold the module by its
handle while removing
it from
the
envelope, manipulating its switches, and
plugging it into its assigned location.
Do not touch the module's contact
f ing er s, components, 0 r the pr in ted
wiring. If the module must be placed on
a bench momentarily, place it on the
plast ic envelope. The plast ic envelope
should not be discarded since it may be
necessary to repackage the module for
reshipment. Warranty repairs will not be
performed on modules returned without
the plastic envelope.

3-13

FOR I/O MODULES:
•
•

•

NOTE THAT TERMINAL STRIP
IS· MOUNTED SO THAT COMPONENTS
ARE TO THE LEFT OF THE PC BOARD
MOUNTED
TERMINAL
STRIP

M6012 - 8 BIT OUT
Mo013 - 8 BIT IN
M6013 - 8 BIT OUT

INSTALL

BC40B
TYPE B TERM.

INSTALL

FOR ALL OTHER
110 MODULES

I
I

BC40A
TYPE ATERM.
STRIP

~TERMINAL STRIP LOCATIONS

w
I

I-'
~

SIDE 1

MOUNTING NUT
MA-0242

Fig ure 3-9

Terminal Strip Installation

I
I

EXTERNAL TOOTH
~
LOCK WASHER----~

I
I

GROUND

~I
LUG-~

KEPNUT~
Figure 3-10

®
I

MA-3142

Ground Wire Fastening

Assign an address to each I/O module. Each module
contains one or more switches which must be set in
accordance with the I/O Subsystem address assignment
pI an. Swi tch impl emenat ion is not ident ical fo reach
module type; therefore, the individual module data sheets
in Chapter 6 must be consulted to determine the correct
selection procedure.

Make sure that fuses and LEDs are properly seated in
their sockets. If an LED has become unseated, reinstall
it with the cathode toward the dot etched on the printed
circuit board. Do not force it past the stop in the
socket.

Refer to Figure 3-11 and make sure that the terminal
strip types and respective I/O modules are inserted into
corresponding slot locations.

Install te rm inat ion cable s bet ween J 1 connec tor s on I/O
modules and Jl connectors on terminal strip boards
(Figure 3-12).

A plastic cover is supplied for each terminal str i p.
These plastic covers must be installed following field
wiring to ensure the safety of operating personnel.

A plastic cover is suppl ied for both the screw te rmina 1
assembly and the H334 chassis (Figure 3-13). Again, for
the safety of operating personnel, the plastic cover for
the screw terminal assembly must be mounted after the
field wiring is done and the individual strip covers have
be e n ins tall e d • Th e pIa s tic co v e r for the H3 3 4 c has sis

3-15

can be
installed when all I/O modules and the i r
termination cables have been installed, and acceptance
procedures run.
EXAMPLE:

BC40A
TYPE A TERM. STRIP
CORRESPONDING
M6010 - 32 BIT INPUT
1/0 MODULE

SCREW
TERMINALS

_LOCl

INSERT MODULE WITH
COMPONENTS TO THE
RIGHT
M6010

H334
CHASSIS

ADR
SELECT
C=:JE41
COMPONENT
SIDE

MA-0230

Figure 3-11

Module and Screw Terminal Configurations

3.3.4
CC1nnecting to Primary Power
Before connecting to system primary power perform the following.
1.

Check each 861 power controller to make sure that its
power matches that required at the site.
The 861-B
[' e qui res 180 - 2 70 V, 4 7 - 6 3 Hz; the 8 6 1 -C r e qui res 9 0 -1 3 5
V, 47 -63Hz.

Chec k the H333 mod el desig nat ion to make sure that its
power matches si te power and the 8 6 1 po we r c () n t roll e r •
The H333-A requires 100-127 V, 47-63 Hz; the H333-B
requires 200-254 V, 47-63 Hz. If necessary, model B can
be reconfigured to work on model A voltages and model A
reconfigured for B voltages.

tJlake sure that each powered H334 chassis matches the
power requirements of the site. The H334-A and -B
designations have the same meaning as for
the H333
chassis. H334-E and -J designations are analogous to the
H334 -A and -B, except tha t they deno te an H7872 powe r
supply instead of an H7870.

3-16

TERMINAL STRIP LOCATION 1

~
~

N
L1J

-I

FRONT

-I

~4_"'!=3

IP"

,,'/

"" 49,50

'II,

''''
1111
1111

1111
1111

-I
-I
-l

lUI

1111
1111

-l

..,

J1 CONN ON
SIDE 1 OF TERM.
BOARD

,
I

I
I

..,I

[~;

1,2

1111

-I
-I
-I

&..,

JII,

-I

_-STRIPE AT TOP

I
I
I

-.
.,
--

' ....

"".....
~_I
I
I
I
J1 1

lUI
-i

r -....

INSERT
CABLE-FREE SIDE
OF CABLE CONN. FLUSH
TO TERMINAL BD.

lUI
1111
1111
1111
1111
1111
1111
1111

-I
-l

-I
-I

NOTE:
CABLE COLOR IS
GREY FOR BC40A
PINK FOR BC40B
H332 SCREW
TERMINAL CHASSIS
H334 CHASSIS

I/O MODULE LOCATION 1

INSERT
CABLE
FREE CABLE
CONN.
FLUSH
TO I/O
MODULE

STRIPE ON
BOTTOM

I/O MODULE
COMPONENT SIDE

50,49

2,1

FRONT

MA-0239

Figure 3-12

Termination Cable Installation

3-17

DOOR HINGES (2) ~

/:'

PLASTIC COVER

SCREW
PHL PAN H[I
#6-32 X
.31LG
(4)

•

SET PLASTIC COVER OVER CHASSIS
AND SECURE WITH HARDWARE PROVIDED.

•

CHASSIS SHIPPED WITH HINGED DOOR
WHICH REPLACED POP-OUT PANELS.
MA-024C'

Figure 3-13

Plastic Cover Installation

The H333 chassis contains an H7870 power supply. The H334
chassis contains either an H7870 or an H7872 power
s u pp 1 Y • In t e rna 1 j urn pe r sse 1 e c t 115 V 0 r 2 30 V 0 pe rat ion
in each case. Figures 3-14 and 3-15 show thE! required
jumper configuration for each voltage selection.
4.

Make sure that the H333 chassis is equipped with a
console/backplane interface cable (70-11411-lA). The
backplane end of this cable may be observed between slots
4 and 5 of the chassis. If for any reason this cable is
disconnected, it must be reinstalled with the orientation
shown in Figure 3-14.

To connect the
folIo wi ng steps.

subsystem

pr imary

power,

proceed

wi th

the

Set the 861 power controller REMOTE, LOCAL ON/OFF switch
to off. Plug each powered chassis into one of the 861
switched circuit outlets in its respective cabinet.

Plug the ac line cord from each cabinet into the primary
power receptacle. Power controller indicators should come
on.

3•

Se t the c i r cui t
position.

b rea ke r

3-18

s wi t c h

0 naIl

8 61 s

th eon

CONSOL/BACKPLANE INTERFACE CABLE
(70-11411-1AI USED ONLY ON H333 MASTER ~
TOH333
CHASSIS. PROPER CONNECTOR ORIENTATION
BACKPLANE
IS KEYED BY OMISSION OF PIN 4 ON BOTH ENDS.
/"

TERMINAL STRIP

",'" '"
LOCATION OF CONNECTOR ON
THIS PC BOARD MAY VARY

",,,,"

115V
MALE PLUG
(SINGLE PHASEI

R
xl. . .

~GROUND

NEUTRAL

G.)

OR RETURN ~W

POLES

116V.15AMP

230 V. 16 AMP

~~GROUND

'c:-)

'-/-"':"""""PHASE

TYPE OF
SERVICE

230VJUMPER
CONFIGURATION

230V
MALE PLUG
(SINGLE PHASEI

POWER CONFIGURATIONS
RECEPTACLE
DEC
HUBBEL
HUBBEL
PART NO
PART NO

FUSE

POWER SUPPLY
JUMPER
CONFIGURATION

5-15 P

90-08938

5266-C

12-05351

5262

6.25 A
250 V SB

1-2.3-4

6-15 P

90-08863

5666-C

12-11204

5662

3A
250 V SB

2-3

WIRES
NEMA"

PLUG
DEC

MA-0176

Figure 3-14

H7870 Power Supply Conversion

3-19

,,
,,
,

}

115
VAC

',t---'~:=----t

}

230
VAC

POWER CONF IGURATIONS
TYPE OF
SERVICE

POLES WIRES
NEMA
- - - - - - c---- ~----

115V,15AMP

r--230 V, 15 AMP

RECEPTACLE

PLUG

Figure 3-15

DEC
DEC
HUBBEL
HU BB EL.
PART NO.
PART NO.
--.. - -- ._._•.. _.......1-------- --".

FUSE

POWER SUPPLY
JUMPER
CONFIGURATION

2A
12-05351
5262
3-4,5-6
250 V SB
f - - - - f---- 1 - - - - -f - - - 1 - - - -f - - - - 1.5 A
12-11204
4-5
5662
6-15 P 90-08853 5665 -C
250 V SB
5-15 P 90-08938

5 266- C

MA-3001

H7872 Power Supply Conversion

3.3.5
Optional NEMA-12 Enclosure Considerations
If site environmental conditions dictate, the I/O Subsystem may be
installed
in
a
NEMA
(National
Electrical
Manufacturers
Association)
type-12 industrial enclosure. The chosen NEMA
enclosure must be at least 30.5 cm (12 in) deep. Figure 3-16 shows
the mounting hole dimensions and spacing required. An important
part of choosing such an enclosure is careful consideration of the
power versus temperature constraint.s as discussed in a later
parag raph
Co

NEMA enclosures are available in a variety of sizes to accommodate
v a r yin g nee d s • Tw 0 t Ypes t hat are e s p e cia 11 y mad E~ for I /0
subsystem service are described below. For information about
ordering these enclosures or any custom enclosures refer to
DIGITAL brochure number ED01315-126.
3.3.5.1
NEMA Enclosure Descriptions - The enclosures descr ibed
here are NEMA type 12 standard industrial enclosures that have
been especially designed for I/O subsystem service. As such, they
conform to National Electrical Manufacturers Association (NEMA)
type 12 (industrial use) specifications. That is, they are
3-20

intended for indoor use to protect the enclosed equipment against
fibers, flyings, lint, dust, and dirt; and from light splashing,
seepage, dripping, and external condensation of noncorrosive
liquids. Note that there are other NEMA specifications that
add ress d if feren t env i ronments; and sui tabl e enclos ure s can be
obtained to meet these requirements.

t
I

14.2 CM MIN.
(5.6'"

TO UNIT ABOVE OR BELOW

10-32 HARDWARE

+----*T
+1

I'PLACES

26.67CM TYP.
(10.5'"

+_ _ _ _
I

44.3 CM
(17.43")

•

5.0 CM MIN.
(2.0") - - - - .
TO UNIT ON EITHER SIDE

H332, H333, H334
MOUNTING DIMENSIONS
(MIN DEPTH CABINET IS 30.5 CM (12", NEMA)
MA-0148

Figure 3-16

I/O Subsystem Rear Mounting Dimensions

These enclosures (Figure 3-17)
are two-door floor-mounted
cabinets. They are 6 feet tall, 5 feet wide, and one foot deep.
They are mounted on one foot high floor stands, and are
constructed of 12 gauge steel. Doors are equipped with neoprene
gaskets that are attached with oil resistant adhesive and steel
retaining str ips. Three-po int latching mechanisms, operated by
oil-tight, key locking handles, hold the doors securely in place.
Fans circulate internal air to reduce temperature gradients inside
the enclos ure. There are fi t t i ng s at the to p and bo t tom 0 f the
enclosure that allow the use of compressed air to aid in heat
removal or to keep the internal atmosphere cleaner than ambient.
All enclosures have holes in the sides, top, and bottom that will
me e t m0 s t wi r in g i n s tall at ion r e qu i rem en t s. Wh e n en c los u res are
delivered, these holes are sealed with oil and dust-tight plugs.
The user unplugs only those holes needed for his installation.

3-21

DISCONNECT

CABLE

PORTSll--~--------___

'CJ
FAN

MA-47BO

Figure 3-17

NEMA-12 Enclosure

Each enclos ure con ta ins a three-pol e po we r disconnect that is
attached via a rod through the door to its operating handle on the
front of the enclosure. For the safety of operating personnel, the
handle is interlocked so that the door cannot be opened unless the
switch is in the off position. This safety feature can be negated
by authorized maintenance personnel via a concealed release screw
(Figure 3-18) •
For the protection of plant maintenance personnel, the switch
handle can be padlocked in the off position to prevent its being
operated during maintenance of external equipment. A simple field
alteration allows the switch to be padlocked instead in the on
position, for applications that require that feature.
The significant difference between the two types of enclosures is
in the chassis-mounting hole pattern on the rear panel, as
disc ussed below.

3-22

PADLOCK
BAR

CONCEALED

MA-4781

Figure 3-18

Typical Disconnect Operating Handle

Option 1 - This enclosure (Figure 3-19) is intended for use with
I/O subsystems that use the standard BC40 screw terminals. Its
rear panel hole pattern provides for the mounting of two module
chassis and two H332 screw terminal chassis. It has one vertical
and one horizontal cable race.
Option 2 - This enclosure (Figure 3-19) is intended for use with.
I/O subsystems that require ATR16 isothermal screw terminals. Its'
rear panel hole pattern provides for either one module chassis and
ten ATRl6 chassis, or one module chassis, one H332 screw terminal
chassis, and eight ATRl6 chassis. It has two vertical cable races.
Power Controller Option - Power to all I/O subsystem chassis and
to the enclosure fans must be controlled from a single point as
discussed in Paragraph 3.3.2.2. In addition, the user must provide
filtering of the incoming ac that is used to power the I/O
subsystem. The use of an 861 power controller (or equivalent) in
each NEMA enclosure is recommended to satisfy these requirements.
These controllers have switched outlets for all ac powered devices
in an enclosure, and include a suitable ac line filter.

3-23

Multienclosure systems have their control bus connectors bussed
together and to a master control point, which is used to turn on
the entire system at once. The 861 power controller can be
installed on the bottom left side of the enclosure.

, . - - - - - A I R FITTINGS

~
c:::

III
III

-DISCONNE CTS

III D

111_
I-CABLE RA c E s -

I
0

0
0

o •

o 0

0
0

.~
0

0
0

o 0

c---FANS

0Cu

t;;;J

U
G

DC
L

OPTION 2

OPTION 1

Figure 3-19

110

I\IA-4782

NEMA-12 Type Enclosures

3.3.5.2
Maximum Power Dissipation - When planning a NEMA-12
enclosure installation, the user must take into consideration the
fa c t t hat the max i m urn allow a b 1 e am b i e n t t em per a t u r e a t the
enclosure locat ion can be less than what it wo uld be for a
standard DEC cabinet installation (i.e., 50 0 C). This is because,
in the absence of an air purge, heat produced by th,~ enclosed
equipment becomes trapped inside the enclosure and can only escape
by conduction through the walls of the enclosure. 1\ standard
cabinet, on the other hand, has a flushing fan that continuously
circulates the ambient air. For a given site ambient temperature
therefore, the temperature rise inside a NEMA-12 enclosure will be
higher than that inside a standard DEC cabinet.

3-24

A complete description and evaluation of all the factors
contributing to the temperature rise inside the enclosure is
beyond the scope of this document. However, for the enclosures
under consideration, a useful approximation of the amount of this
temperature rise is
boT = 1.67

Wh ere

P
A

bo T

d iff ere n c e bet we e n
temperatures (0 C)

ins ide

Power dissipation of all equipment in the enclosure
(watts - if power is in BTU/hr, use 0.488 instead of
1.67)

The unobstructed
enclosure (sq ft)

outside

and

0 u t sid e

surface

area

am b i e n t

the

The surface area of the enclosure (6'X5'Xl') is 82 sq ft. If it is
installed with the rear panel against a wall, the effective area
i s red uc ed to 5 2 s q ft.
The circulating fan increases heat transfer efficiency so that the
maximum temperature at critical locations inside the enclosure can
be 60 0 C (128. 3 0 F) •
The following example demonstrates what this means to the user.
The cabinet is installed against a wall, and the max imum ambient
0
temperature at the intended site is expected not to exceed 38
C
0
(100.4
Fl. Transposing the above formula gives
Pmax

=
=

0.6 A (T l - T 2 )
0.6 X 52 (60 - 38)
686 watts

where Tl and T2 are respectively the maximum temperature allowed
at critical locations inside the enclosure, and the maximum
temperature anticipated at the site.
0

At a site where the amb ien t temper at ure can reach 38
C, thi s
means that the total power dissipation of all equipment in the
enclosure must not exceed 686 watts. When calculating the total
power contr ibution of all the dev ices in the enclosure, remember
to include the power used by the fan (53 W). In the above example,
after allowing 53 W for the fan, there would remain 633 W (686-53)
for I/O Subsystem power.

3-25

Th ere 1 at ion sh i pis s ho wn by c ur v e (a) 0 f Fig ur e 3 - 20 , wh i chi s a
plot of maximum allowed enclosure power versus maximum ambient
temperature 0 f the si te. Curve (a)
is for the case where the
enclosure is installed against a wall, reducing the effective
surface alrea to 52 sq ft.
Curve (b) is for the case where the
enclosure is free standing so that its entire 82 sq ft surface
area can radiate heat effectively. Note that these curves are only
1 inear approx imat ions 0 f wha t occ ur s in thi s enclos ure wi th a
typic al I/O Subsystem install at ion. They sho uld no t bl= used for
other than I/O Subsystem install at ions, or 0 ther enclos ures .

3000

2500

en....
....
«

0:
LU

?!:
0
a..

....
LU

1500

~~:~8: S~.FT

_..

K~52SQFT~~
"'
~

1----I-

-- ~ ......

:;:)

1 - - - f--P=0_6A6T

-1---+-

'" '"

- - >---

1------ - . - - - ---.-t-----t-.

2000

'--..--

1000

«
2

''" "'""'"
....

f - - - - f - - - - - . - - - - - 1----.--

500
f------- f - - - -

- - - - -_._- 1 - - - - -1 - - -

'" "

- . - --

o
o

- - --

MAXIMUM SITE TEMPERATURE (0C)
MA-4783

F'igure 3-20

Cabinet Power Versus Site Temperature

3.3.5.3 Air Purging - Pipe fittings (1/2 in) are provided at the
top and bottom of the enclosure for the installation of compressed
air. Co mpr e sse d air can be us e d to ma in t a ina po sit i v e c 1 e a n air
pressure to el iminate dust.
It can also be used for cool ing.

3-26

3.3.5.4

NEMA Enclosure Installation
WARNING
NEMA type enclosures of this size are
heavy and unstable. They must be bolted
down or otherwise secured before opening
the doors or THEY CAN TIP OVER.

When planning the installation of a multienclosure system, mak~
sure that the enclosures are placed close enough together to allow
the D-bus cable to reach from one chassis to the next in arll
adjacent enclosure. The five inch holes in the side of the
enclosure can be used for this purpose, but the D-bus should not
be exposed to the plant environment. It is recommended that
conduit be used to join the enclosure.
When the enclosures have been unpacked and inspected, move them to
the i r final locat ions, bol t them to the floor thro ug h the hoI es
provided in the enclosure feet, and proceed as follows.
1.

Connect all enclosures together with at least a number 12
AWG ground wire. Fasten these wires to the studs provided
in the enclosure rear panel (Figure 3-21). Fasten them in
the same manner as the chassis ground lugs (Paragraph
3. 3 • 3 • 2 , s t e p 7 ) to ens u r e g r 0 un d con tin u i t Y bet we e ri.
enclos ures •

Install a power controller in a sui table location wi thin
each enclosure. The user must provide hardware to secure
the controllers in place.

Place the H333, H332, and ATR16 chassis in their assigneq
locations and fasten with the 10-32 X 1/2 inch screw$
(prov ided wi th the chassis) to the tapped holes in the
enclosure's rear panel. Attach each chassis ground lug tq
studs provided on the rear panel in the manner discussed
in Paragraph 3.3.3.2, step 7. ATR16s should be mounted on
spacers (prov ided) for max imum thermal isol ation.

Remove the ac pI ug from the 15 foot cable attached to the
powe r con troll er, cut the cable to 1 eng th, and connec t
the black and white wires to two of the bottom contacts
of the disconnect switch (Figure 3-21). Connect the green
wire to one of the ground studs.

Remove the safety cap from the disconnect's top contactst
connect the enclosure ac input to these contacts, and
replace the safety cap. Connect the ground wire to one of
the ground studs.

Co nn e c t a po we r cor d to th e fan t e r min a 1 s t rip (F i g u r e
3-21).
Plug the other end into one of the power
controller switched outlets.

3-27

DECDATAWAY
AND I/O
I=IELD WIRE

C::= _ _....J

[::J

OPTION 2
CABINET

MA-4784

l~ig ure

3 -21

Typical NEMA-12 Cabinet Installation

'7.

PI ug any H333 or H334 chassis power cord into a swi tched
outlet on the 861 power controller.

Connect all enclosure power controllers together with a
power control bus (Figures 3-5 and 3-22). Connect the
main control point chassis to the power controller in its
cabinet. Wire the spare disconnect contacts of all
enclosures in series.
Connect the one in the first
enclosure to pin I of the control bus. Connect the one in
the last enclosure to pin 3 of the control bus (Figure
3-22). This enables turning the system on and off when
the doors are opened via the power switch on the front of
the main control chassis. When the doors are closed, all
disconnect switches must be turned on to turn on the
system. Anyone will turn it off.

3-28

MASTER
SINGLE
WIRE

POINT

MA·4785

Figure 3-22
9.

Typical Control Wiring

Interconnect all module chassis with the D-bus cables
provided witll each H334 chassis (Figures 3-6 and 3-21).
The
BC08R-06
cables
provided
for
a
DEC cabinet
installation are six feet long (the cable number suffix
designates the length). Longer cables may be specified if
necessary. Cables are available in 8, 9, 10, 12, 15, 18,
25, and 30 foot lengths.
NOTE
A restriction here is that the combined
length of all D-bus cables in a system
must not exceed 59 feet.

10.

Connect to primary power as described in Paragraph 3.3.4.

3.3.5.5 NEMA Enclosure Field Wiring - General I/O subsystem field
wiring considerations are discussed in later paragraphs. The NEMA
enclosures discussed above have two features that make the task
easier. First, the user has a choice of several cable ports that
allow entry from the top, bottom, or sides. Second, there are
cable races wi th snap-on covers to simpl ify the routing of the
enclosure's internal wiring.

3-29

3.4

CHECKOUT PROCEDURES

3.4.1
Cabinet Power Check
The following procedure for applying system power ensures that all
861 power controllers, all H7870 and H7872 power supplil:s, and the
po wer control bus are ope rat ional •
1.

Remove all I/O modules from all subsystem chassis.

Set each power controller REMOTE, LOCAL ON/OFF switch to
LOCAL ON. All cabinet fans should be operating.

3•

Tu r non all H78 70 and H78 72 po we r s u pp 1 i e s.
front panel dc indicators should come on.

Turn off the I/O subsystem master power switch. (This may
be either the H333 chassis power switch or, if the system
is an IPl10 or an IPV10, the PDP-II CPU power switch.)

5,.

Set the REMOTE, LOCAL
controllers to REMOTE.
chassis should be off.

6,.

Turn on the system master power swi tch.
chassis should come on.

7,.

Check the dc voltages at the test points provided on the
front panels of all H7870 and H7872 power supplies.
Voltages should be within +3% of their nominal values. If
adjustment is necessary, refer to Chapter 7. Note that
the nominal value of the 5 V supply is 5.1 V.

Turn off the system master power switch and reinstall the
modules that were removed in step 1.

9..

When all modules have been
maste r po we r swi tch on.

ON/OFF swi tch on
DC power to all

installed,

Po we r

s u pp 1 Y

all 8 6 1 po we r
H333 and H334

DC power

turn

the

all

system

3.4.2
Operational Check
Equipment. operation is checked by running the Field Test Program
and by per fo rm i ng the Acce ptanc e Proc ed ur e (A-SP -H3 3 3 -0-7). If
multiple I/O modules are used, the rules for address selection
given in Paragraph 4.2.1 must be followed before starting the
Acceptance Procedure. For instructions on how to run the tests,
refer to the Acceptance Procedure and the documentation included
with the software.
3.5

SYSTEM CONFIGURATION PROCEDURES

3.5.1
Configuring the System for Operation
After installation and checkout of the new equipment by DIGITAL
Fi eld Se rv ice, the customer can beg in to conf ig ure the system. To
accomplish this, proceed as follows.

3-30

Use the information contained in the I/O module data
sheets in Chapter 6 for each type of module included in
the system.

Determine how the I/O modules will be organized on the
D-bus, i.e., in what slot each module is to be installed,
and the address to be assigned to each module. Then
remove the modules from their present slots, select the
addresses, and reinstall them in the desired order.
I/O module address assignment is independent of the
module's location on the D-bus, but is subject to th~
rules stated in Chapter 4, Paragraph 4.2.1.2. Although
address and location are independent, location does
determine priority for the interrupting type modules. It
is highest for modules closest to the control module on
the D-bus.
NOTE
When an I/O Subsystem is shipped with
mod ul es installed, the organi zation 0 f
the
mod ules
in
the
chassi s i s
standard ized for manufactur ing and may
require reorganization to suit the needs
of the customer.

3a.

The M8719 UNIBUS I/O control module is the bus interface
module for IPl10 subsystems. It must be configured for
its assigned priority level, device address,
and
interrupt vector. The priority level is changed by
replacing the priority plug located on the module. The
M8719 normally has a priority level of six; however, thi~
c an be chang ed for spec ial appl icat ions. Dev ice add ress
and interrupt vector are selected via switch packs E49
(for address) and E18 (for vector) on the module. The
locations of the priority plug and switch packs is showril
in Figure 3-23. The use of these switches for selecting
device address and vector is illustrated in Figure 3-24.·

3b.

The M7958 I/O control module is the bus interface module
for IPll, IP300, and DPM50 subsystems. It must be
configured for its assigned device address and interrupt
vec tor.
Thi s i s done vi a the swi tch packs E34 (for
address) and E7 (for vector) on the module. The location
of these switch packs is shown in Figure 3-25. The use of
these switches for selecting the device address and
vector is illustrated in Figure 3-26. One of the switches
on E34 is used for initialize select. This switch should
be on.

3-31

~,--------------------------------------------------------------.--~

J 1

A1
B1
C1

E18
V1

VECTOR
SELECT

A'I

u.
u.
0

Z
0

STATUS
INDICATORS

c::J +5 V
c:::J +12 V
c:::J DEV SEL

XE31

NO.6
PRIORITY
PLUG

c::::J INTR
c::::J TIMEOUT

E49

ADDRESS
SELECT

~~
NE3
z
o

u.
u.

L-L.L.-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _V1
__

MA-3270

Figure 3-23

M87l9 UNIBUS I/O Control Module

3-32

~ [

SELECTED
INTERRUPT VECTOR

[ [ 0

V
HARD WIRED ZERO
1 = OFF
0= ON

E18

OFF

NOT USED

'NOTE THAT THE ON/OFF SENSE OF
THE INTERRUPT VECTOR SWITCHES
ON TH IS MODULE IS OPPOSITE TO
THAT OF THE ADDRESS SWITCHES

SELECTED
DEVICE ADDRESS

1 = ON
0= OFF

234
E49

[, [0[0 [, [0I
OFF
ON

12 11 10 9

SUBSYSTEM 1 = OFF = ADDRESS 17100
SUBSYSTEM 2 = ON = ADDRESS 171400
ADDITIONAL SUBSYSTEMS USE
FLOATING ADDRESSES
Vr------~

-------

Figure 3-24

M87l9 Address and Vector Selectors

3-33

MA-2999

~..,...,..-------"---A1
81
C1

VECTOR
SELECT
ON
E7

OFF 111111111

V1 _

STATUS
INDICATORS
V1

c::::J +6 V
CJ +12V
CJ DEVSEL
c::J INTR
c::J TIMEOUT

ADDRESS
SELECT

A'I

'" ION
OFF

(III IIIi'D
t

INITIALIZE
SELECT
V1_

Fl---o

MA,019'I

Figure 3-25

M7958 I/O Control Module

3-34

SELECTED
INTERRUPT VECTOR

~_0

___0
_____
0__1

~1_o

o~1 ~I__

____o_____

o ________

0
1.

------'

V
HARD WIRED ZERO

12345678

O~~

11 11
12

I, I, I+
1a 1a

3456

, = ON
0= OFF

78 1

I L NUOT

'--_____J

SED

SELECTED
DEVICE ADDRESS

'-------..v,...---'

~ I

THE ADDRESS MATCH IS
ENABLED BY BBS7 L
(I/O OPERATION WHEN
THESE BITS ARE TRUE

E34

SUBSYSTEM 1 = OFF = ADDRESS 171000
SUBSYSTEM 2 = ON = ADDRESS 171400

}

ADDITIONAL SUBSYSTEMS USE FLOATING ADDRESSES

234

II
5

ON
OFF

, = ON
0= OFF

_ _ _ _ _ _ _ _ _---1
NOTUSED------------~

INITIALIZE SELECT = ON - - - - - - '
MA-2997

Figure 3-26

M7958 Address and Vector Selectors

3-35

3c,.

'1he M7959 I/O control module is the bus interface module
for IPV10 subsystems.
It must be configured for its
assigned device address and interrupt vector .. This is
done via swi tch packs E7 (for address) and E12 (for
vector). The location of these switch packs is shown in
Figure 3-27. Their use is illustrated in Figure 3-28.

3.5.2
Screw Terminal Configuration
If the BC40A, BC40B, and BC40L screw terminal assemblieB are used
to connect the I/O modules to the customer field wiring, ensure
that the I/O modules are not now connected to the wrong type of
screw terminal assembly. This could happen as a result of the
customer reorganizing modules in the chassis. The BC40A and BC40L
screw terminals are for 16- or 32-bit modules; the BC40B is for
8 - bit mod u 1 e s • I f n e c e s sa r y, r e po sit ion the s c r e w term ina 1
assemblies.
>-!:-rr-.-----.--------------.-.-A1
81

E5~

ADDRESS
NOT
SELECT -USED

~
ON 1

E70FFIIIIIIIII

I
V1

mloNOFF t[lO II ~J
~
VECTOR
SELECT

NOT
USED

STATUS
INDICATORS

c::J +5 V
c::J +12 V
c::J DEV SEL
c::J INTR
c::J TIMEOUT

8
V1

A1
J1

VV
V1

Figure 3-27

M7959 I/O Control Module

3-36

SE LECTED
INTERRUPT VECTOR - - - _ I 0

I I'

E12

ON
OFF 11111,10101,10

8 1

I
SELECTED
DEVICE ADDRESS

• 1

[] I

V
THIS ADDRESS MATCH IS
ENABLED BY BBS7 L
(I/O OPERATION) WHEN
THESE BITS ARE TRUE

, = ON
0= OFF

I LNOT
USED

V
HARD WIRED ZERO
1

1
E7

ON
OFF

, = ON
0= OFF

}
SUBSYSTEM 1 = OFF = ADDRESS 17'000
SUBSYSTEM 2 = ON = ADDRESS 171400
ADDITIONAL SUBSYSTEMS USE FLOATING ADDRESSES

MA-2997A

Figure 3-28

M7959 Address and Vector Selectors

3-37

3.6

CONFIGURATION RECORDS

The cust.omer should keep a record that describes his I/O
Subsystem. Three types of forms for simplifying this task are
included in Appendix C. Sample copies of the forms are included in
Fig u res 3 - 29 t h r 0 ug h 3 - 3 1 •
The H333 module chart (Figure 3-29) allows the customer to record
a complete map 0 f the chassis, incl ud ing the I/O mod ules, the
IOCM, and any LSI option modules present. The page num.ber column
is a cross reference to the functional I/O module page containing
more detailed information about the individual modules. This chart
should be attached to the inside chassis front door.
The H334 module chart (Figure 3-30) fulfills a similar function
for each H334 chassis present. One of these forms should be filled
out for each chassi s and attached to the insid e chassi s front
door.
CUT ALONG DOTTED LINE

" - - - - - - - - - - - - - - - - - - - - -- - -, - --l
I

I
I
I
I
I

CHASSIS NO.

V--

SLOT

I
3

LSI-11
BUS

D-BUS

MODULE
ADDRESS

MODULE
TYPE

PAGE
NO

MUX
NO

FUNCTION

P~501

Kbl/-H
000000-

X
X

NsV!1};l /fi1Il.7
Rxv/{

X
X

bLI/1J-F

~<v

t::J~

~ryct7d..

q7'd..7d

X
X

~/d.7d.

X
X
X

... VV/U'nO'!:t
.J)1,sK

,o~

,0
V

(if>

lI.~':J

CoafinuifLI

,?-~<f

c#'

Jt,j7Q58 /J.lQOD
N5010

TiL,m; YJOlJ
{]n n+i f1U l-}-y

l!.onhnui+4

X
X

f.1BO/~_ f--

-7 ]XL in /-__386 DC- j (] 33-(df
q
A~in /___~

M5013

X
X

ttl £0013
1-1(0013

ftc.. ouf I-B
fa J4Q.. auf q-/ro

MCoOIO

M (001/

s
9
10
11

1'-15010,-- f--

f1~ jn q..-lro

f¢v11-A

:ti.!- ouf /-3:).
'tC- ouf -4 J-S;;
/30Yf/TtLrW1

L __________________________

I
I
I
~

MA-0234

Figure 3-29

H333 Module Chart

3-38

,-- - - - --------------------------l
I

CHASSIS NO.

SLOT

MODULE
TYPE

.- --

MODULE
ADDRESS

MUX
NO.

PAGE
NO.

FUNCTION

---

M5011

M5010

fvl5013

M~012

1710Z0

J)C in 97-112

171010
17/0/6
771054

DC in '5-96---

AC in 17-2+

_._,.,--

"~-"-

Dc out 33-1/-0
.-

~~\..C(;.

,,~c;,.

~\0\O
\ot uc;,'lJ.

6\"1-(,
Q0t'

see j).Q

________

_ _ ..J

CUT ALONG DOTTED LINE
MA-0235

Figure 3-30

H334 Module Chart

The functional I/O module chart (Figure 3-31) enables the customer
to record all pertinent information about a particular module,
such as type, generic code, addresses, bit use, interrupt options,
etc. After completing the form it should be assigned a page number
and put into a notebook. The page number should be recorded on the
chassis module chart as a cross reference. The customer should
duplicate this chart if site requirements exceed the number
supplied in Appendix C.

3.7

SYSTEM RESTRICTIONS

To
ensure proper operation,
limitations should be observed.

the

following

I/O

Subsystem

O-bus cables must not exceed 15 m (50 ft)

Vacant slots between I/O modules must have M90l9
continuity modules plugged into the C and 0 connectors of
tho se slots.

The I/O Subsystem is subject to the software restrictions
stated in Chapter 4.

3-39

total length.

'rhe M7958 must be the 1 ast opt ion on the LS I-ll bus.

~rhe

rrhe M7959 does not implement the LSI-ll/23 multiple
priority interrupt protocol.
Any LSI-ll options that
require this protocol must be placed closer to
the
LSI-ll/23 processor than the M7959.

M7958 can only be used
in slot 5 or 6.

PAGE NO. _ _

in the H333 chassis and only

-"'8"----__.

MODULE TYPE

~10 _ _ _ BYTE _ _1__

GENERIC CODE

_....:....'--<-+----",_ _ __

BYTE ADDRESS

----'O""'--""'O'--+L--___ SINGLE SHOT TIMING

MUX NO.

CHASSIS NO.
SLOT NO.

_-=0__ FIELD POWER

COMMON

lif

~_ _ _

ISOLATED

[]

-----~--

f{III

.-<-N,,..,.!<--L-A>--------

MODULE LOCATION:

POINT

--------------BIT FUNCTION REMARKS

INTR.
ENAB.

N/A

Low f}re5,5ure boiler #1

Hiqh
., pressl.1(e bOiler # /

Over t~boiler -#"-/ - - - - Turhlne # 2__-»2eed 0 K.
Low fuel Inain -ranl

Aux. fuel ON
50are - - - - -

06
07

II/A

Control roam

door unlocJed

ADDITIONAL COMMENTS

.l3oiler #-/ pressure 0/50 011 ana/oJ channel 73.
2. On low I'vel call 555-2368 lOr del/very.
I

MA-3271

Figure 3-31

Functional I/O Module Chart

3-40

3.8
FIELD WIRING
Pro pe r fie 1 d wi r in g pr act ice sen sur e m1 n 1 mum in t e r fer en c e from
outside sources. The techniques and restrictions discussed in this
section will help to reduce outside interference.
3.8.1
General Wire and Cable Characteristics
In general, field wiring should utilize stranded, tinned-copper
wire to ensure flexibility and high oxidation resistance. The
dielectric strength of the
conductor insulation should be 600 V
or greater. Twisted pairs should be utilized throughout to
minimize noise pickup and crosstalk. Typical wire sizes that might
be used
for
field wiring are listed below, along with the
resistance exhibited by each.
AWG
Number
14
16
18
20

Resistance (Ohms)
(per 1000 ft)
2.5
4.0
6.4
10.2

Twisted pairs may be arranged concentrically to form cables. All
lays and pairs should be twisted in the same direction for.
g rea t est fIe x i b iIi t Y • Cab 1 e s s h 0 u 14M bee n cas e d i n Pol yv i n y 1
Chloride (PVC), polyethylene or Teflon
insulation at least 0.034
inches thick (beflon should be used if the ambient temperature
will exceed 105 C).
3.8.2
Analog Signal Wiring
Uniform twisting and a high turns/foot ratio are desirable for
analog signal wiring. Twisted pairs should be bundled together
only if all signals have similar amplitude and frequency
characteristics. Wire resistance must be considered as part of the
load for current-output analog signal wires.
NOTE
Analog wi ring and dig i tal wi ring should
not be run together and should not be
run near ac wiring.
3.8.3
Digital Signal Wiring
Multiple input signal wires can be twisted together with a single
ground wire in the same cable. The number of signals cabled in
this manner should be limited to the number of input points on a
given I/O module. Input and output signal wires can be mixed in
the same cable tray, but high level output wires should not be
pI aced in the same c able wi th input wi res. In terrupt type input
wires should be run as twisted pairs only.

TMTeflon is a registered trademark of E.

3-41

I. DuPont.

3.8.4
Grounding
Ideally, all grounds should be separated into categories: power
grounds, logic grounds, and analog grounds. Each ground category
should be run directly to a ground electrode and tied to it at one
point only. As a practical matter, this may not be feasible, but
at the very least, a division should be made between analog and
dig ita I g' round s •
3.8.5
Installing Field Wiring
The customer's devices may be connected to I/O Subsystem modules
by fastening the field wiring to the optional screw tE~rminals or
by con neG t i ng i t d ire c t I Y to his 0 wn 5 0 - pin Be r g t YP€! con n e c to r
which is plugged directly into the I/O module. When selecting this
connector, ensure that it does not have exposed wiring on the
surface that comes into contact with the module. This could result
i n sho r t c i r cui t son the pr in ted c i r cui t etc h (F i 9 ur e 3 - 3 2). To
ensure that proper practices are followed when installing field
wiring, the user should review the field wiring
information
contained in paragraphs 3.8 through 3.8.4 before procE!eding with
the following installation.

(~:---c::===

MODULE P. C. BOARD

___ ~ I

' - P. C. CONNECTOR

CABLE CONNECT - SURFACE
MUST
NOT HAVE ANY EXPOSED WIRING THAT
WILL SHORT TO THE P. C. ETCH.
MA-0217

Figure 3-32
field

I/O Cable Connector Interface

Bring the
cabinet.

wiring

through

2..

Guide the wiring along the channel formed by the cabinet
vertical supports and clamp it securely into place.

Fasten the field wiring to the screw terminals. Ensure
that the wiring configuration for each is corrE~ct for the
I/O
module
being
interfaced.
Screw
terminal
configurations for the most common digital I/O modules
are shown in Tables 3-2 and 3-3; others are included with
the module descriptions in Chapter 6. Knowinq the type
module being used in a particular slot enables the
customer to select the correct configuration. Module
number s are listed at the top 0 f the col umn correspond ing
to its required wiring configuration. Before connecting
the field wire, ensure that the proper t.ype screw
terminal has been installed for each I/O module as
described in paragraph 3.3.3.3.
3-42

the

bottom of

the

H960

Table 3-2
Type A Screw Terminal l6/32-Bit (BC40A)
I/O Module Field Termination Configurations
M50l1/M6011

M5010/M6010/M60l0-YA
Field
Bit No.
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
Field
Com'mon
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

Screw
Terminal
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

{1718
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Field
Bit No.
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
Field
Common
Not Used

,
Not Used

Screw
Terminal
No.

M5012/M5012-YA/M5031
Field
Bit No.

1
2

4
5
6
7
8
9
10
11
12
13
14
15

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

+
+
+

06
07

If)

{1718

Not
Used
+
10

12
13
14

+
-

Screw
Terminal
No.
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
If)

{1718
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

NOTE
Two 8-position jumper strips are provided with the BC40A. These
can'be used to common the + or - terminals for the M5012 module on
a per-byte basi s. They can al so be used wi th the M5012-YA to
common the + terminals for connection to a user-furnished +5 V TTL
supply.

3-43

Table 3-3
Type B Screw Terminal 8-Bit (BC40B)
I/O Module Field Termination Configurations
M50l3/M60l3

M60l2
Field
Bit No.
FIELD +
00 { SWITCH
FIELD FIELD +
01 { SWITCH
FIELD FIELD +
02 { SWITCH
FIELD FIELD +
03 { SWITCH
FIELD -

Not used

1
2

3
4
5

6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21

Screw
Termin.al No.

Field
Bit No.

Screw
Terminal No.

LINE
00 { SWITCH
NEUT
LINE
01 { SWITCH
NEUT
LINE
02 { SWITCH
NEUT
LINE
03 { SWITCHNEUT

2
3
4
5

6
7
8

9
10
11
12
13
14
15
1fi

Not used

FIELD +
04
{ SWITCH
FIELD FIELD +
05 { SWITCH
FIELD FIELD +
06 { SWITCH
FIELD FIELD +
07 { SWITCH
FIELD -

23
24

25
25
27
28
29
30
31
32
33
34

NOTES:
1. M6012 -- All "Field +"
terminals are common.
2. M5013/M6013 - All "Line"
terminals are common.

17
18
19
20
21
22

LINE
04 { SWITCH
NEUT
LINE
05 { SWITCH
NEUT
LINE
0f)
SWITCH
{
NEUT
LINE
07 { SWITCH
NEUT
terminals
terminals

3-44

are
are

25
2f1

27
28
29
30
31
32
33
34

common.
common.

All

"Field

All

"Neutral"

3.9
INSTALLATION OF PROCESSOR INTERFACE
The I/O subsystem can interface with either the LSI-II bus or the
PDP-II UNIBUS. Four interface configurations are possible.
1.
2.
3.
4.

IP300
IPl10
IPll
IPV10

LSI-II
UNIBUS
UNIBUS
LSI-II

bus interface
interface
interface
bus interface

The procedure for implementing each of these interfaces is given
below. The user should disregard the three procedures not relevant
to hi s system.
3.9.1
LSI-Il Based Subsystem Installation (IP300)
To configure the IP300, plug the LSI-II modules into the first
four and the fourteenth slots of the H333 chassis, (Figure 3-33) ~
The standard configuration includes the following modules.
1
1
1
1
1

KDII-H
MSVll-DD
RXVll
DLVll-F
REVll-A

Processor quad-height
Memory dual-height
Floppy disk control unit dual-height
Serial line unit dual-height
Boo t/ te rm inato r d ual- he ig ht

The user is advised that any LSI-II configuration different than
the above is subject to the restrictions of the LSI-II bus as
covered in the LSI-II User Manual. In addition, the I/O Subsystem
imposes the following LSI-II restrictions.
1.

LSI-II options are restricted to the first
fourteenth slots of the master chassis.

five and

the

A vacant slot between LSI-II modules must have G7272
continuity modules plugged into the A and C connectors of
that slot.

Memory refresh must be performed by the MSVll-DD memory,
not by the REVll-A or the processor.

3.9.2
UNIBUS IOCM Based Subsystem Installatio'n ~~,IPll0)
The M87l9 UNIBUS IOCM goes into the C, D, E, and F's~ctions of any
SPC slot in a PDP-II backplane. When configurili-g" a system,
remember that the interrupt priority depends on the prior~ty plug
number (Figure 3-23) and the proximity to the processor on the
UNIBUS. It is recommended that the M87l9 be set at priority six
(priority plug no. 54-08780-00), and located further from the CPU
than any mass storage interfaces so that the relatively long I/O
subsystem cycle time does not interfere with the mass memory,
causing data late errors to occur. The M87I9 is shipped from the
factory with a priority level six plug.
To configure an IPl10, plug one end of the BC08R D-bus cable
(provided) into the D-bus input connector of H334 chassis number
one (Figure 3-33). pI ug the other end into Jl of the M87l9 at the
UNIB US.
3-45

G7272
CONTINUITY
REV11 A

LSI·11 BUS

MODULES

RXV11

KD11·H

~ ==~ =-~ ==: ==~ =~ : ==~ ==~ ==: ==~ =:~\ t\
12

O®OO@0

H333 CHASSIS

DLV11

D·BUS

MSV11-DD

BC08R D-BUS CABLE FROM J1
< ; _ OF M8719 (UIOCM) AT UNIBUS

(IP110) OR J1 OF M7959 AT
\~SI.ll BUS (IPV10I

I PV 10 0 RIP 11 0

~[t~l~ililililililililil~
~ ~ ~ ~ ~
~ ~

= = = = = =; = = =1

D-BUS

@ (@) 0

H334 CHASSIS

T EV 11

~ 0 [3

LS 1- 11 BUS

i ______'_

P1_1 __________ _

[~~~~~]~~~~~~~1~~~~~:::~~~~~~~~~~~~~~4~-O~3

TO
DW11A

k 1-'-.

D-BUS-

0 @OO@0

H333 CHASSIS

MA-2998

Figure 3-33

Processor Interface Configurations

3-46

3.9.3
UNIBUS
to
LSI-II
Bus
Converter
Based
Subsystem
Installation (IPII)
For an IPII subsystem, install the DWII-A bus converter module in
the UNIBUS. This unit must mount in the C, D, E, and F sections of
an SPC slot. For further information about this module, refer to
the DWII-A UNIBUS in the LSI-II Bus Converter User Manual
(EK-DWIIA-IN) •
Next, install the M9401 backplane to cable adapter module and the
TEVII terminator module in the locations shown in Figure 3-33 .•
Finally, install the LSI-II bus cable by plugging one end of eacr
cable into the DWII-A at the UNIBUS and the other ends into the
cable adapter module.
3.9.4
LSI-II Based Subsystem (IPV10)
To configure an IPVl0 subsystem, install the M7959 IOCM in an
empty quad slot of an LSI-II computer (e.g., a PDP-II/03 or
PDP-ll/23) , plug one end of the BC08R D-bus cable (provided) into
JI of the M7959, and plug the other end into the D-bus input
connector of H334 chassis number one (Figure 3-33).

3-47

CHAPTER 4
PROGRAMMING INFORMATION
4.1
SCOPE
This chapter contains general programming information
Subsystems. The following topics are discussed.
4.2
4.3
4.4
4.5
4.6

for

I/O

Device Registers and Address Assignments
I/O Transfers
Device Priorities
Programming Requirements
Sample Programs

More detailed information on programming in general may be
by referring to the appropriate processor handbook.

found

4.2
DEVICE REGISTERS AND ADDRESS ASSIGNMENTS
The programmer is concerned with only three types of registers for
the I/O Subsystem:
one CSR ( con t r 0 1 and s tat us r eg i s t e r) ,
one I AR (i n t err up t i ng add res s r eg i s t e r) ,
and as many IORs (input output reg ister) as
subsystem may require, up to a maximum of 254.

the

par ticul ar

There can be a total of 256 registers for the subsystem,
assigned a unique address in the processor's address space.
4.2.1

each

Address Assignments

4.2.1.1 Subsystem Addresses - The I/O Subsystem address range can
be 171000 to 171377 or 171400 to 171777 depending on whether ther~
are one or two subsystems. Additional subsystems would use
floating addresses. Subsystem address selection is made on the I/O
control module as explained in Chapter 3. The remainder of this
chapter refers to addresses as if the subsystem address was
171000.
4.2.1.2 I/O Addressing Rules - Each subsystem is assigned 40:0
octal· addresses in the processo r' s address space for I/O use.
These addresses are selected by switches on the individual I/O
modules and range from 171000 through 171377. A typical mapping of
address assignments is shown in Figure 4-1. When assigning these
addresses to speci fic I/O modules, the following rules must be
adhered to.

Add ress bytes 1 71376 and 1 71377 ar e reserved
and CSR, respectively.

4-1

fo r

the

IAR

A single byte module may be assigned any byte
except those reserved for the IAR and the CSR.

A two byte module must be assigned two consecutive
address bytes beginning with an even address.

A four byte module must be assigned
bytes beg inning wi th an address that
fo ur.

The rules for assigning addresses to modules with more
than four bytes are consistent with the above rules.
OCTAL
ADDRESS

four
ends

address

consecutive
in zero or

OCTAL
ADDRESS

171001

1 ADDRESS I/O'S

171003

171002

006

004

007

006

011

010 . - - 2 ADDRESS I/O

013

012

016

014 }

017

016

...... 4 ADDRESS I/O

372

373
J..----+_

376

374

171377

1'71376

LAST TWO ADDRESSES ARE
RESERVED FOR IAR & CSR
MA-0146

Fig ur e 4-1

Typical Add ress Assig nmen ts

4.2.1.3 Interrupt Vector Addresses - The first I/O Subsystem will
vector through memory locations 000234 and 000236. Additional
subsystems will use floating vectors (refer to Appendix B).
4.2.2
Register Formats
Figures 4-2 through 4-4 show the reg ister formats
describes the functions of the CSR bits in detail.

4-2

and

Table 4-1

ADDRESSES
171000-171375
07

MA -0143

Figure 4-2

lOR Fo rmat

ADDRESS 171376
07

IAR
CONTAINS ADDRESS OF INTERRUPTING
MODULE WITH HIGHEST PRIORITY.
MA-0144

Figure 4-3

lAR Format

ADDRESS 171377
07

FLAG

MAINT

INTR.
ENABLE

TEST

DISABLE

CLR

GENERIC

RIF
MA-0145

Figure 4-4

4-3

CSR Fo rmat

Table 4-1
Bit
07

Description
Flag bit=l indicates that the subsystem requires
se rv ice.

(F)

Read onl y
06

(E)

Re ad/wr i tE~
05

CSR Bit Descriptions

(M)

Re ad/wr i tE~

Enable bit=l enables the subsystem interrupt.
If F=l
and E=l and the processor status allows interrupts,
the processor will be interrupted.
Maintenance bit=l forces a maintenance interrupt if
E=l.
If M=l, then F=l.
M is cleared when the CSR
has been read with R=l.
Reading an lOR with M=l
results in data equal to the address of that lOR,
whether or not there is a module installed with that
address.

04
(D)
Read/wr i tE~

Disable bit=l sets the I/O disable mode on all
applicable I/O modules.
Clearing the D-bit
automatically sets the C-bit.

Test bit=l sets the I/O test mode on all applicable
I/O modules.

(T)

Read/wr i te
02

(G)

Read/wr i te
01

(C)

Write only
00

(R)

Generic bit=l causes an I/O module to respond with
its identity code instead of normal data.
Clear bit=l causes the subsystem to reset without
requiring a reset instruction; self-clearing.

RIF (reset interrupt flag) bit=l causes the I/O
module being read to reset its internal interrupt
flag. RIF is cleared when the I/O module or the CSR
is addressed.
_ - - 1 -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Read/wr i tE~

4.2.2.1 lOR - The I/O registers (lOR) are 8-bit registers that may
contain field, address, status, or test information, to or from an
I/O modul1e, depend ing on the type of I/O module involved in the
transaction. For a more detailed discussion, consult th(~ specific
I/O module descriptions in Chapter 6.
4.2.2.2 IJ~R - The interrupting address register (IAR) contains the
address of the interrupting I/O module with the highest priority.
The IAR is an 8-bit register at byte address 171376.
If the IAR
is read when there is no interrupting I/O module, the processor
will trap through address 000004.
Therefore, the IAR should be
read only after an interrupt.
4.2.2.3 CSR
The control status register
(CSR)
is an 8-bit
read-wr i te reg i ster tha t mon i tor s the status and con trol s the
operation of the subsystem.
It is located in the last byte
address in the subsystem's address space.
The function of each
bit is explained in Table 4-1.
The CSR occupies address 171377.

4-4

4.3
I/O TRANSFERS
The I/O Subsystem operates by programmed I/O transfers and
interrupt-driven transfers.
In a typical application, there might
be a programmed status monitoring mode and also an asynchronous
mode in which the controlled system interrupts the processor for
immediate service.
4.3.1
Programmed I/O Transfers
Programmed I/O transfers may be used to input or output 8-bit data
or status bytes to or from the I/O mod ules. By incl ud ing the
device's address as the effective source or destination address,
the user selects the input or output operation.
4.3.2
Interrupt I/O Transfers
Some of the input modules on the I/O Subsystem D-bus may initiate
an interrupt type transfer by causing the subsystem to interrupt
the processor.
The module does this when its internal Flag bit is
set.
If priority conditions allow, the processor suspends
operation of its present (background)
program to service the
subsystem.
The subsystem has a hard-wired vector associated with
i t t ha t i t 0 u t put s t o t h e pro c e s so r •
Th i s v ec to r i san ad d res s
pointer, which allows automatic entry into the I/O Subsystem's
s e r vic e r 0 uti n e s t 0 red in the pr 0 c e s so r' s mem 0 r y •
Pa r t 0 f t his
service routine must include instructions to reset the module's
interrupt Flag bit.
This is known as RIFing the module and is
done by reading the module with the RIF bit in the CSR set.
4.4

DEVICE PRIORITIES

4.4.1
I/O Subsystem Priorities
Since the I/O Subsystem is an LSI-II bus device, it is subject to
priority rules on that bus.
That is, the device electrically
closest to the processor has the highest priority.
In addition to
bus priority, there is also the processor priority arbitration to
consider.
As explained in Chapter 1, the subsystem may be
connected to a PDP-II so the arbitration is not necessarily that
of the LSI-II.
The reader
is referred to the appropriate
processor handbook for details of its priority arbitration.
When
used with the UNIBUS PDP-II, the subsystem typically interrupts at
priority level 6.
4.4.2
I/O Priority
When the I/O Subsystem has acquired control of the LSI-II bus, one
of its I/O modules on the D-bus is serviced.
The interrupt
control line is daisy-chained along the D-bus, creating a priority
structure within the I/O Subsystem such that the I/O module
electrically closest to the subsystem's I/O control module has the
highest priority.
This module will be serviced and its address
will be in the IA R ( in t err up t i ng ad d res s r eg i s t e r) •
Th e I AR
contains the address of the highest priority module with an
interrupt pending.
There is no inherent relationship between the

4-5

address of an I/O module and its physical proximity to the I/O
control module.
Therefore, it is possible to establish the
subsystem interrupt priority without regard to t h E~ mod u 1 e s '
addresseE:.
Note, however, that the maintenance interrupt is
always the highest priority interrupt.

CONFIGURATION REQUIREMENTS

4.5

4.5.1
Subsystem Requirements
At installation time, the subsystem must have its address and
vector s\yitches (on the I/O control module) set to the proper
octal addresses as discussed in Paragraph 4.2 and in Chapter 3,
Paragraph 3.5.1.
This must be done before the system can be
operated.
4.5.2
I/O Requirements
All I/O modules have one or more switches which must be set to
select speci fic addresses, interrupt flags, or operat.ing modes.
Proper s\I/itch settings may be found by referring to the specific
I/O modules in Chapter 6.
It is first necessary to determine
which modules should have the highest priority for interrupts so
locations for plugging the modules into the O-bus can be assigned.
The highest O-bus priority is obtained by the I/O module
electrically closest to the I/O control module; the module
furthest away has the lowest priority.
4.5.3
Trap Conditions
The following cond-i tions
location 000004.

cause

the

processo r

tr ap

throug h

At tempt ing to wr i te the IAR

Attempting to read the IAR when there is no interrupting
module

Attempting to read a nonexistent I/O module address when
M=0

I n ad d i t ion, s om e PO P -11 s t rap t h r 0 ug h 1 oc a t ion 0 0 " 0 0 4 i fan
attempt is made to read or write a word with an odd address.
4.5.4
Software Restr ictions
Th e folIo wi ng res t ric t ion s are
the I/O Subsystem.

e f fec t i v e

for

pr 0 gram S

0 pe rat i ng

At least 20 microseconds must elapse between setting the
C-bit (bit 1) of the CSR and next addrHssing the
subsystem.

The time from setting the subsystem interrupt (Fl ag bi t)
to the time the interrupt service routine reads the IAR
must be at least 30 microseconds.

4-6

The time from clearing a module interrupt (RIFing the
module)
to the time the software enables additional
subsystem interrupts, tests the F-bit of the CSR, or
reads the IAR, must be at least 30 microseconds.

At least 200 ms must elapse after initial system power up
before any I/O module is accessed by the software.

Sample Program Number 1
This is a general interrupt routine that:
1.
2.
3.
4•
5.

Acquires the address of the interrupting module
RIFs the mod ul e
Performs the required service
Ch e c k s for fur the r in t err up t s
Returns to the main program.
VECTOR:234
R0=%0
IAR:171376
CSR:171377

START:

MOV

#START,@VECTOR

iSET INTERRUPT ROUTINE
iADDRESS

MOV

#340,@VECTOR+2

iSET CPU PRIORITY TO 7 SO
iTHAT SAME MODULE WILL
iNOT INTERRUPT AGAIN

MPTS #0

iENABLE CPU INTERRUPT

BISB #100,@CSR

iENABLE I/O SUBSYSTEM
iINTERRUPT

WAIT

iWAIT FOR INTERRUPT

MOVB @IAR, R0

iGET CONTENTS OF IAR iLOW BYTE OF INTERRUPTING
iMODULE'S ADDRESS

BIC

#177400,R0

iCLEAR THE HIGH BYTE OF R0

ADD

#171000,R0

iADD IAR HIGH BYTE

4-7

- R0 NOW
iCONTAINS COMPLETE ADDRESS
iOF INTERRUPTING MODULE

BISB :ff:1,@CSR
TSTB @R0

iSET RIF BIT
iREAD MODULE - READING
iMODULE WITH RIF BIT SET
iWILL RIF THE MODULE

OTHER WORK
TEST GENERIC CODE
READ MODULE
. PROC ES S, ETC.

TSTB @CSR

iGET CONTENTS OF CSR

BMI

iIF F=l SERVICE NEXT
iINTERRUPT

START

iRETURN FROM INTERRUPT

{ RTI

iPERFORM INTERRUPT SERVICE

Sample Program Number 2
Th i s pr 0 (;:J ram ta ke s the con ten t s 0 f R0 , 0 u t pu t s i t to an 0 ut pu t
module, and then reads and prints the contents of that module's
output register. Subroutine PRINT will print the contents of R1.
R0=%0
R1=%l
ADOUT:

l71XXX

START:

MOV B

BIC

iPUT CONTENTS OF R0 I~ OUTPUT
iREGISTER
@ADOUT,Rl iPUT CONTENTS OF OUTPUT REGISTER
iIN R1
:ff:177400,R1 iCLEAR HIGH BYTE OF R1

JSR

PC, PRINT

MOV B

R0,@ADOUT

iPRINT THE CONTENTS OF Rl

Sample Program Number 3
This subroutine monitors the contents of an input rE!gister
when its contents exceeds five clears an output register.
calling instruction is: JSR R0,START
R0=%0
ADIN: 171304
ADOUT:171305
START:

MOV

:ff:5,R0

iSET CONTENTS OF R0=5

FIRST:

CMPB

@ADIN,R0

iCOMPARE INPUT TO QUANTITY 5

BGT

FINAL

iIF CONTENTS OF INPUT REG)5
iCLEAR OUTPUT REG

FIRST

iIF NOT)5 COMPARE AGAIN
4-8

and
The

FINAL:

CLRB

@ADOUT

;CLEAR OUTPUT REG

RTS

;RETURN TO MAIN PROGRAM

4-9

CHAPTER 5
PRINCIPLES OF OPERATION,
5.1
SCOPE
This chapter provides a functional description of the I/O
Subsystem. Overall system operation, and deta i led discuss ions 0 f,
the control modules are included .. The reader should be familiar,
with the LSI-II and other PDP-II processors as well as the,
introductory
material
presented
ln
Chapter
1.
Detailed
descriptions of I/O modules are included in Chapter 6.
5.2
FUNCTIONAL DESCRIPTION
The I/O Subsystem is a program-controlled industrial control
subsystem. It is capable of monitoring and controll ing complex
industrial processes on a real-time basis. To accomplish this, the
subsystem performs the following operations.
1.

It transfers status information from the I/O addresses to
the processor. (This type of transfer is called a DATA!.)

It transfers control data from the processor to the
addresses. (This type of transfer is called a DATAO.)

It generates service requests to the program in response
to interrupts from the I/O mod ules • (These requests are
called I/O interrupts.)

I/O

In addition to these basic functions, the subsystem is capable of
performing various software-initiated maintenance functions for
testing its own performance.
5.3
SYSTEM CONFIGURATIONS
The I/O Subsystem comprises a control module and a number of I/O
mod ules that interface wi th it on a common data bus called the,
D-bus. A block diagram showing this configuration is shown in
Figure 5-1. The number and type of I/O modules is a variable that
is a function of the particular application.
There are three types of I/O control modules: M7958 and M7959 for:
LSI-II Bus based I/O subsystems, and M8719 for UNIBUS based I/O
subsystems. The difference between the three modules is bes~
visualized by examining Figure 5-2, which illustrates an
application of each.
Note that the M7958 and M7959 modules perform identical logical
functions. The difference between the two is mechanical. The M795a
interfaces with the two buses in an H333 chassis via its printed
circuit etched edge connector. The M7959 interfaces with the
LSI-II bus in an LSI-II computer chassis via its printed circuit
etched edge connector and with the D-bus via a cable.
The third I/O control module, the M8719, interfaces with the
UNIBUS in a PDP-II chassis via its printed circuit etched edge
connector, and with the D-bus via a cable.

5-1

PROCESSOR BUS

TO PROCESSOR

.---r----~----,~

1/0

rI MODULEl
..a....I..
1/0

TO PROCESS

UPTO 81>
1/0 MO[IULES

FROM PROCESS

MA·0219

Figure 5-1

5-2

I/O Subsystem

IP300

H333

LSI-11
MICROCOMPUTER

D-BUS
I NTE RCON N ECT
CABLE

D-BUS
INTERCONNECT

IPV10
LSI-PDP-11/03

D-BUS
INTERCONNECT

IPll0
PDP-11

M8719

-U-N-IB---U~S~~ I/O
CONTROL
MODULE

MA-478G

Figure 5-2

IOCM Applications

5-3

I/O subsystems using the M7958 I/O control module have space for
78 I/O modules when fully expanded. Up to 80 I/O modules are
possible in the other two systems.
The following paragraphs contain separate descriptions of LSI-II
bus based and UNIBUS based systems. The reader may omi t that
description not pertinent to his application.
5.4
LSI-II BUS BASED SUBSYSTEM
In an LSI-II based subsystem, either the M7958 or the M7959 is the
I/O control module of Figure 5-1. As is shown in the figure, all
I/O modules reside on the D-bus, under control of the M7958 or the
M7959, and prov ide inputs from, or outputs to, the process. The
control module interfaces with both the D-bus and the LSI-II bus.
The major difference between the two buses is that the LSI-II bus
is 16 bits wide and the D-bus is only 8 bits. The D-bus also has
its own unique timing. These differences are provided for by the
control module, which derives D-bus timing and data control
signals
from standard
LSI-II bus
signals.
The
following
discussions of data transactions should aid in underst.anding the
operation of the M7958 and M7959 I/O control modules. The reader
should note that while the timing and data path of the LSI-II bus
and the D-bus differ, the data transfer protocols are identical.
5.4.1
"7958 and M7959 D-bus Cycles
The timing signals that control the I/O module data transactions
on the D-bus constitute the D-bus Cycle. Derivation of a DATAl
D-bus Cycle is shown in Figure 5-3. The first three signals at the
top of the figure are the normal signals initiated by the
processor when executing a DATAl. The remainder of the sequence
involves signal s internal to the I/O Subsystem. ThE! order 0 f
signal sequence is indicated by arrows in the figurie. If this
timing diagram is related to the ,block diagrams of E'igu)ces 5-4 and
5-5, the functions performed during the sequence can be better
visualized. In these figures, data paths are indicated by
cross-hatching, and the relevant control signals by bold lines.
The D-bus Cycl e breaks down in to three parts: SETUP TIME, SYNC
TIME, and DATA TIME. The cycle is initiated by the ADRO EN
( add res sou ten a b 1 e) s i 9 n a 1 wh i c h s tar t s the S ETU P TIM. E ph as e 0 f
the cycle. SETUP TIME is defined by a delay which is part of the
control circuitry in the IOCM; it allows sufficient time for
settling of address data on the D-bus. At the end of this delay, D
SYNC (D-bus sync) is asserted, causing the address~d I/O module to
activate its internal MY ADDRESS signal. (MY ADDRESS is the signal
produced by an I/O module's control circuits when it recognizes
its address on the bus; it is the module's data transaction
enabl ing signal.) The second part of the D-bus Cycle (SYNC TIME)
is controlled by another delay circuit in the IDeM. This delay
allows a t least min imum time fo r the I/O mod ul e to prepare to
transmit the appropriate data byte.

5-4

LSI-11
BUS

BSYNC

BDIN

ADDRESS
REG

DEVICE
SELECT

ADRO EN

DBUS

D-SYNC

ODIN

DRPLY

BRPLY

I
!
'--------' '--...,--/\.'----------'
I

SETUP TIME
1300 nsec

SYNC TIME
200 nsec'

NOMINAL

DATA TIME

\,--------------~~---------------~I
D-BUS CYCLE
MA-0211

Figure 5-3

5-5

DATA!

LSI-II BUS

FROM

r-~r--.-;;-~-;----------------------------------------------~~~~~~~~ PROCE$OR

r-tit
I

I ~ ~ ~~ ~
iii

I
I
I
I
I

::l

iii

CONTROL

I-

I
0"'1

D-BUS

I I
I I
I I
I I
I I
I I

--....,
(,)

I-

::>

z
Ci

I I

~ CI >
e z ,.:
"Ci
a:
e 0 e

Figure 5-4

MODULE

I
I IL_ _ -.JI IL __ ..JI

I
I
I
I

FIELD INPUTS

FIELD OUTPUTS

--,

roT~/O

Addressing

MA-0204

I
I
I
I

I/O CONTROL MODULE
(lOCM)

CONTROL

I
I
I
I

L...
lJ1

I
-..J

~----~~--~~~~~~~;~--~-->
--. ._L-, r-_L-,
I I
I
I I
I I
I IL _ _ ..JI IL __ -.JI
I I
r

I OTHER I/O
MODULE

I I
I I
I I

OUTPUT

I I
FIELD INPUTS

Figure 5-5

I OTHER I/O

MODULE

I
I
I
I

~U~
FIELD OUTPUTS

Data Input

MA·0202

At the end 0 f thi s delay, D DIN (D-bus Data In) is asserted
tell in g the s e 1 e c ted mod ul e top u t i t s d a t a o n t he D- bus. Th e
module does this and replies by asserting D RPLY. Upon receiving D
RPLY, the IOCM puts the D-bus data on the LSI-II bus, and asserts
B RPLY indicating to the processor that it has done so. The
processo 1::" accepts the data and neg ates B DIN i nd icating tha t the
LSI-II bus cycle is ending. The negation of B DIN causes the IOCM
to negate D DIN, which causes the module to negate D RPLY. When
the IOCM receives the negation of D RPLY, it negates B RPLY on the
LSI-II bus. The processor then negates B SYNC on the LSI-II bus
freeing -the bus for the next processor transaction. The negation
of B SYNC causes the IOCM to negate D SYNC, freeing thl~ D-bus for
the next I/O transaction.
For a DATAO, the device selection part of the cycle is the same as
for a DATAI~ however, after B SYNC is asserted, the LSI-II removes
the add rl~ss from the bus, repl ac ing it wi th data. The IOCM does
the same on the D-bus (Figures 5-6 and 5-7). The LSI-II waits for
the bus data to settle and then asserts B DOUT, telling the IOCM
that the data is valid. The IOCM waits because the D-bus is slower
than the LSI-ll bus and then asserts D DOUT telling the addressed
module to clock in the data. When the module has aC'cepted the
data, it asserts D RPLY, which the IOCM transmits to the LSI-II as
B RPLY. The LSI-II then negates B DOUT, causing the sequential
negation of D DOUT, D RPLY, B RPLY, B SYNC, and D SYNC as in a
DATAl cycle, and freeing both buses for subsequent transactions.
Some instructions cause the processor to ini tiate a DA~~AIO cycle.
In this case the D-bus Cycle has four parts: SETUP TIME, SYNC
TIME, and two DATA TIMEs for read ing and immed iatel y re\vr i ting the
same address.
A modifi.ed D-bus Cycle occurs when the program reads the
subsystem's IAR (interrupting address register). The IAR is read
at the beginning of the interrupt routine when the main program is
interrupted. (The IAR contains the address of the highest priority
interrupting module on the D-bus.) The difference between the
modified and ordinary D-bus Cycles is that D SYNC is inhibited in
the modified cycle (SYNC TIME) and D ADDR is asserted instead.
When D DIN occurs (DATA TIME), the module puts its address instead
of data on the D-bus and the program reads the address of the
interrupting module at the IAR address. Modified D-bus Cycle
timing is shown in Figure 5-8.
5.4.2
M7958 and M7959 Interrupts
Some input modules can interrupt the processor for servi.ce if, for
example, one of its field inputs changes state. If a change 0 f
state occurs, the module's flag flip-flop is set and initiates an
interrupt sequence by putting the D INTR signal on the D-bus. This
signal is daisy-chained along the D-bus and ORed wi th any D INTR
signals from other modules. The interrupt control line (D INTR
INH) is also daisy-chained along the D-bus. It ensures that if
there is more than one module with an interrupt pending, the one
that is serviced first is the one with the highest priority (the
module physically closest to the IOCM on the D-bus) •
5-8

LSI-11
BUS

--<

)(~____________D_A_T_A____________-J)~--------~

ADDRESS

B SYNC

B DOUT

ADDRESS
REG.

DEV SEL

ADRO EN

D-BUS

o SYNC

R DOUT

o DOUT
FIELD
OUTPUTS

o RPLY

B RPLY

)

SETUP TIME
1300 nsec
NOMINAL
\.

"------'

SYNC TIME
1450 nsec
NOMINAL

.......,..

DATA
TIME
)

D-BUS CYCLE
MA-0212

Figure 5-6

5-9

DATAO Timing

~~r-~~.-,--,~

LSI-ll BUS
____________________________________________

FROM

~~~~~~~~PROCESSOR

r
II ~

iii

I
I
I

11.
II:

I
I

CONTROL

I
I
I

L..

Ln
I

D-BUS

I--'
~

I I
I I
I I
I I

---,
0

~ z

..(!I

>0..

c c' II:
c

Figure 5-7

I
Da ta Ou tput

MODULE

I I
I I

MODULE

I IL _ _ --1 L __ -.JI
I
I

FIELD OUTPUTS

r;;T;'/~ -, roT;;-I/~ --,

I I

I I
I I

LSI-11 BUS

BSYNC

BDIN

ADDRESS
REG

-----+---C

IAR

ADDRESS

~~------------------+----~-+~------~-

DEVICE SEL _ _ _ _ _ _~__.
AND CIA

ADRO

ODIN·

D-BUS

D~PLY

BRPLY
1300 nsec
NOM.

I
I

\~-----------' '----...----'
SETUP
TIME
\~

DATA
TIME

_ _ _ _ _ _ _ _ _, ,____________- J )

MODIFIED
D-BUS CYCLE
MA-0203

Figure 5-8

DATA! with Modified D-bus Cycle

5-11

When the D INTR signal is received by the IOCM, it initiates the
LSI-II interrupt sequence by setting the flag bit in the CSR
(control and status register). This constitutes an I/O Subsystem
interrupt request, and will be serviced if the enable bit in the
CSR has been set by the prog ram and the processo r sta tus allows
i nterr upts. The signal s involved in the LSI -11 interrupt sequence
(B RPLY, B IRQ, and INTERRUPT VECTOR) are shown in Figure 5-9
along with I/O Subsystem interrupt signals (FLAG, D INTR, D RPLY,
and R IF). Th e in t err up t
r e que s t/ a c kn 0 wI ed g e seq u en c E~ for the
LSI-II is covered in the Microcomputer Handbook.
When the prog ram addresses the inte r r upt ing mod ul e a fter the RIF
bi t in the CSR has been set, the mod ul e' s internal interrupt
flip-flop will be reset. The timing diagram in Figure 5-10 will
aid the reader in following the interrupt timing.
5.4.3
M7958 and M7959 Maintenance Mode
The IOCM has a maintenance mode that is activated when the program
sets the M bit in the CSR. In this mode, the usual D-bus Cycle is
not initiated when an attempt is made to read an I/O address. The
address is put on the D-bus but D SYNC does not occur and there is
no D RPLY. When the IOCM puts the O-bus data on the LSI-II bus,
the program reads back the address. This mode allows a diagnostic
program to check the D-bus data lines for errors.
If the IOCM is in maintenance mode, it causes the CSR's F bit to
be set. If the E bit is also set, subsystem interrupts are enabled
and one occur s if the processo r sta tus allows. The M bit may be
cleared by writing M=0 in the CSR or by reading the CSR with R=l.
Figures 5-11 and 5-12 show the signals, data paths, and timing of
the maintenance cycle.

5.5
UNIBUS BASED SUBSYSTEM
In a UNIBUS based subsystem the IoeM is the M8719. As shown in
Figure 5-1, all I/O modules reside on the D-bus under control of
the IOCM and provide inputs from or outputs to the processor. The
IOCM int.~rfaces with both the D-bus and the UNIBUS. The major
differences between the two buses are that the UNIBUS has 16 data
lines and the D-bus has 8, and that the UNIBUS has separate
address lines and the D-bus uses the same lines for addresses and
data. The D-bus also has its own unique timing. These differences
are provided for by the IOCM, which derives D-bus timing and data
control signals from the standard UNIBUS signals. The following
discussion of data transactions should aid in understanding the
operation of the M87l9.

5-12

r-~r-,,-,~~~

lSI-ll BUS
______________________________________________

TO
~~~~~~~PROCESSOR

I
I
I
I
I
I
I

iii

;;;
<I:

iii

CONTROL

L.
U1

I
~

D-BUS

--....,

I I
I I
I I
I I
I I
I I

IOTHERUO

IOTHERlro

MODULE

I I
I
I I
I IL_ _ ..JI IL__ ....JI

I
I
I
I

INPUT

~~---FIELO INPUTS

FIELD OUTPUTS

Figure 5-9

l"-----.--_-----.-_>
r-- L -, r-_L-,

Interrupt Signals

I/O SUBSYSTEM INTERRUPT SEQUENCE
FIELD COS

FLAGFF~
CSRFLAG~
LSI-"

INTERRUPT SEQUENCE
MODIFIED D-BUS CYCLE
OCCURS HERE

B D I N - - - -____,r~~

LSI-11 BUS------1J~{:~~~-(~::A~
IAR DA.TA = MODULE ADDRESS

RIF-----------------------------.------~____________ ,~'

MA-015fi

Figure 5-10

Interrupt Timing

5-14

lSI-"

FROM

BUS

I
I
I
I
I
I
I
I

iii

«
iii

>"a:

III

u
z
>-

til
III

CONTROL

"u
a:
....

o
o
~
o

L...
Ul

I
~

....

---,

,.:

>"-

OUTPUT

Figure 5-11

OTHER I/O

OTHERUO

MODULE

I I
I
I IL _ _ -.1I IL __ ..JI

I
I
I
I

~U~
FIELD OUTPUTS

I I

I I
I I
I I
I I
I I
I I
FielD INPUTS

Maintenance Mode

MA-0204

LSI-11
r:..---~
BUS ---~~DDR-=-'i

B::~: -----j.~

-----l----~-

BRPLY
ADDRESS
REG

----+----.:..t

ADDRESS

~----------DEVICE
SELECT
D-BUS----~

ADDRESS
MA-2991

Figure 5-12

Maintenance Cycle Timing

5.5.1
M8719 O-bus Cycles
The tim ing sig nal s tha t control the I/O mod ul e data transac tions
on the D-bus constitute the D-bus Cycle. Derivation of a DATAl
D-bus Cycle is shown in Figure 5-13. The first four signals at the
top of the figure are the signals initiated by the processor when
executing a DATAl. The remainder of the sequence involves signals
internal to the I/O Subsystem. The order of signal sequence is
indicated by the arrows in the figure. If this timin~1 diagram is
reI at ed t o t h e b 10 c k d i ag r am s 0 f Fig u res 5 -1 4 and 5 -1 5 , the
functions performed during the sequence can be better visualized.
In these figures, the active data paths are indicated by
cross-hatching and the relevant control signals by bold lines.
The D-bus Cycle breaks down into three parts: SETUP TIME, SYNC
TIME, and DATA TIME. The cycle is initiated by the r1SYN (master
sync) signal which starts the SETUP TIME phase of the cycle. SETUP
TIME is defined by the 1500 DLAY signal which is produced by the
IOCM control circuitry; it allows sufficient time for settling of
address data on the D-bus. At the end of this delay, D SYNC (D-bus
SYNC)
is asserted, which causes the addressed I/O module to
act ivate its internal MY ADDRESS signal. (MY ADDRESS is the name
of the signal produced by an I/O module control circuit when it
recogni:2:es its address on the bus; it is the module's data
transact.ion enabling signal.) The second part of the D-bus Cycle
(S YNC TIM E) i s con t roll ed by a no the r del a y c i r cui t ( 21~ 0 0 DLA Y) i n
the IOCiM. This delay allows at least a certain minimum time for
the I/O module to prepare to transmit the appropriate data byte.
At the end of this delay, D DIN (D-bus Data In)
is asserted
tell ing the selected mod ule to put its data on the D-bus. The
module does this and replies by asserting D RPLY. Upon receiving D
RPLY, the IOCM causes the D-bus data to be put on the UNIBUS data
lines, and asserts BUS SSYN to indicate to the processor that it
has done so. The processor accepts the data and negates MSYN to
indicatE~ that it has done so. The negation of MSYN causes the IOCM
to neg ate D DIN, ind ica ting to the mod ul e that the data has been

5-16

UNIBUS
CNTL Cl
UNIBUS
ADDR

\
y

ADDRESS

MSYN

",----

UNIBUS
DATA
SSYN

DATA,;

->..

7
~i

r---

DEVICE
SELECT

- q

DATI

-q

'-- ~
~

500 DLAY

)

000 DLAY

D-BUS

'--I

ADDRESS

D SYNC

DATA

/
r--i,-

'-..

'-l
I

D DIN
DRPLY

'-I
1

RPLY

~'--y-I\

SET UP
TIME

SYNC
TIME

((
J

-=---J:TA
TIME

1 4 - - - - - - - D - B U S CYCLEMA-2995

Figure 5-13

DATA I Cycle Timing

5-17

~ z

0 ~

-~
E

[

r-:

o 0
0«000::.

CONTROLI~

r--

~
0::.

0::.
I-

~ INPUT

I ;:.

GATES

I~REG
JOUTPUT

10=

~
r=

CONTAOL

~III;

F~ ~N:~;S I

I NTR ll+--+_E_NA-<B'Y'L...~

r CNTL I

____-..J

OUTPUT MODULE

OUTPUT
CKTS

-I

I I
•

INPUT
CKTS

I I
I

INPUT MODULE

t I I

I I I I I

FIELD INPUTS

FIELD OUTPUTS

MA-2989

Figure 5-14

5-18

Addressing

I\..

UNIBUS

~ ~

~
,.

BUS TRANSCEIVERS

/').

" ~

DEC

I--

:::J ~

(/l-(/l-

coxcox

:::J-:::JO

..!...... ...J

VECT r D IN
MPX

SEL

CSR

MPX

,~~,
!r~

~
~
~

I~IIIIIIIIIIIIIIIIIIII

<3 ~
r:1oa:
o 0

0
0

a:
0
0

I-:::J

:..:: ...J
c..
...J

~'7

tI..

tI.

z
>(/l

0
0

<2:

u..

CONTROL~ ~

I-:::J

I
INPUT
GATES

I--

INTR
CNTL

t:J

r-:

c..

c::i a:
0

>...J

CONTROL

1<=

6-r
j.--

INPUT MODULE

+I I I +

INPUT I

GATES

ENABL...~
I-~

OUTPUT
CKTS

Z
0
0

FLAG

U
I

-I

a: a:
I--

c.r~~~PUTI f

OUTPUT MODULE

<3 >...J
c::i

(/l

:::J

o 0 a: 0
Z I-- a:
Iz
>- 0 ~ ~
(/l
o 0 0

r-: a:c..
<2:

:::J

(/l

CONTROL

<2:

D GATE

.:~

~~
(/l

(/l

:::J

~
~

- - - - TO OTHER I/O MODULES

I-:::J
0

<2:

(/l
(/l

co co

[lit

....

~ D-BUS

:::J

M8719

u co

(/l

r--

BUS
RX

t:J

;,
BUS
TX

D OUT
MPX

VECT

7 ~

7'1;

CSR

z :..:: a:
>- U I--

~
(/l

INPUT
CKTS

I I I I I
FIELD INPUTS

FIELD OUTPUTS

MA 2987

Figure 5-15

Data Input

received. The module then removes the data from the D-bus and
neg ate s D R PLY, causing the IOCM to negate D SYNC, and freeing the
D-bus for the next I/O transaction. The IOCM simultaneously
freeing
the UNIBUS for
the next processor
negates
SSYN
transaction.

5-19

If the cycle is a DATO instead of a DATI, the sequence is almost
the same as before. The difference is that the DATA TIME part of
the cyclE~ involves D DOUT instead of D DIN, resul ting in a data
t ran sm iss ion in the 0 p po sit e d ire c t ion ( from the UN I BUS t o t h e
fie 1 d 0 u t put s). Th i s s e qu en c e i s d e pic ted in Fig u r e E: 5 -1 6 and
5-17. In a DATO, dev ice selection is the same as in a DATI;
however, after D SYNC is asser ted, the IOCM wa its fo r the I/O
mod ule address to be recogni zed from the D-bus, and replaces it
with data from the appropriate byte of the UNIBUS. The IOCM waits
for the data to settle, and then asserts D DOUT causing the
selected module to clock the data into its register. The module
indicates that it has accepted the data by asserting D RPLY. This
causes the IOCM to assert SSYN on the UNIBUS, indicating to the
pro c e s so :r t hat the d a t a has bee n a c c e pte d • Th e pro c e s so r
acknowledges by negating MSYN, which causes the IOCM to negate D
DOUT, indicating that the D-bus Cycle is ending. The module then
negates D RPLY, causing the IOCM to negate D SYNC, freeing the
D-bus for the next I/O transaction. The IOCM simultaneously
negates SSYN,
freeing
the UNIBUS for
the next processor
transaction.
The I/O :subsystem has no destructive read registers; therefore,
the protocol for a DATIP is exactly the same as that for a DATI.
A modified D-bus Cycle occurs when the program reads the
subsystem's IAR (inter rupt ing add ress reg i ster). The IAR is read
at the beginning of the interrupt routine when the main program is
interrupted. (The IAR contains the address of the highest priority
interrupting module on the D-bus.) The difference bE~tween the
modified and ordinary D-bus Cycles is that D SYNC is inhibited in
the modified cycle (SYNC TIME) and D ADDR is asserted instead.
When D DIN occurs (DATA TIME), the module puts its address on the
D-bus ins.tead of data, and the program reads the address of the
interrupting module at the IAR address. Modified D--bus Cycle
tim i ng i s s ho wn in Fig u r e 5 -1 8 •

5.5.2
M8719 Interrupts
Some modules can interrupt the program for priority service if,
for example, one of its field inputs changes state. If a change of
state occurs, the module's flag flip-flop is set and initiates an
interrupt sequence by putting the D INTR signal on the D-bus. This
signal is daisy-chained along the D-bus and ORed wi th any D INTR
signals from other modules. The interrupt control line (D INTR
INH) , which is also daisy-chained along the D-bus, ensures that if
there is more than one module with an interrupt pending, the one
that is serviced first is the one with the highest priority (the
module in the lowest numbered slot of the lowest numbered
chassis) •

5-20

UNIBUS
CNTL C1
UNIBUS
ADDR

r-J
-

ADDRESS

MSYN
UNIBUS
DATA

- -~

L
\

DATA

SSYN

~
DEVICE
SELECT
DATO

- "-q

'--~

-y

'-~
~

1500 DLAY

2000 DLAY

3500 DLAY

D-BUS

I
ADDR,ESS

\.7(

I"'"

DATA

V
,~

7
~r---

"-.

D SYNC

"-..j

D DOUT
FIELD
OUTPUTS

OLD DATA

NEW DATA

'-..

'--l
I

DR PLY

(

\-.

R PLY
~~~~

SETUP

__________

SYNC

~y~

____________J

DATA TIME

I+-_T_IM_E_ _
T_IM_E_ _ D_BUS CYCLE _ _ _ _ _ _ _......
MA-2993

Figure 5-16

DATA 0 Cycle Timing

5-21

....

UNIBUS
'II

~
=c:

{}

•

BUS TRANSCEIVERS

~~H~~"'~"" ,~
~

:J-:JO

VECT
D IN
MPX

SEL

CSR

=---...J

CSR

MPX

~
,
DEC

~<
-

DOUT
MPX

,~'==

BUS
RX

.",--

o !:::

M8719

~ .. o::
Cl

- - - - TO OTHER 1/0 MODULES

-1

en
:J
co

«
en

0::

Cl
Cl

Cl
U

Cl
Z

>en

z i5

CONTROL

0::

D GATE

BUS
TX

z ~
>- u

en
co en
en
:J
co
t:l

'~
~~

VEeT

en
:!:
en
:J
co

...J
U
0::
~

~
Cl

...J

0::

Cl
0::
~

~
Cl

~ ~r

....

)

~ D-BUS

....... !oj;en
~

0::

Cl
Cl

~>-

>0 ...J

Cl
Cl
Cl

«
~

===

CONTROL

"j<:

Lj"0UTPUT
REG

I GATES

0::
~

I INPUT

Z
Cl
Cl

t:l

...J

r-: a.0::
ci

0::

~
0::
~

CONTROL

FLAG
INTR

'NPUT
GATES

ENABL"4

r CNTL J

OUTPUT
CKTS

OUTPUT MODULE

~,A.lI.

z
>-

0::
.~

...

r-: a.0::
«

~=.

INPUT
CKTS

I
I I
+T1 Tt

INPUT MODULE

FIELD OUTPUTS

f I I I f

I I I I ,

FIELD INPUTS

MA·29Sf,

Figure 5-17
DATA Output
(Upper Byte Transfer Shown)

S-22

UNIBUS
CNTL C1
UNIBUS
ADDR

d-~
./

M SYN

IAR ADDRESS

I
)

Y I -;)
L

INTR MOD ADDRESS

DATI

~DAIA
J

SSYN
DEVICE
SELECT

IAR

UNIBUS
DATA

'-r-r-

1500 DLAY

I'--

2000 DLAY

D ADDR

...,

'-l

D DIN

(

'-l

~
,-J

D-BUS

'-L

INTR. MOD
ADDRESS

\.
I

"---f

D RPLY

'-.j

RPLY

MA·2994

Figure 5-18

D~TI

with Modified D-bus Cycle

5-23

When the D INTR signal is received by the IOCM, the flag bit is
set in the CSR (control and status register) ~ This constitutes an
I/O Subsystem interrupt request, and will be serviced if the
enable bit in the CSR has been set by the program and the
processor status allows interrupts. The signals involved in the
PDP-II interrupt sequence
(BUS INTR, BR, BG, BUS SACK, and
INTERRUPT VECTOR) are shown in Fig ure 5-19 along wi th the I/O
Subsystem interrupt signals (FLAG, D INTR, D RPLY, and RIF). The
inter r upt sig nal sequences fo r the PDP-II a re cover(~d in the
PDP-II Peripherals Handbook.

(

-'"

UNIBUS

._~________~f=~:~~______~<t~

______~

BUS TRANSCEIVERS

,,~

Ul -

Ul-

:::>::2: :::>::2:

OJXOJX

:::>:c:::>g

VEeT

~~U ~

D IN r t E L
MPX

D IN
MPX

so
Ilv'V'v'
D OUT
~Sl
MPX
~

READ
CSR

L)'~
_~
"~,,
~

1'--__. . .

VECT

~ .,

'---------4

BUS

- - - - - - - - - - 1 RX

CONTROL

D GATE

'",1--'-"'---'

M8719

!:::

. -------------~ ,,~-

~v"

- - - TO OTHER I/O MODULES

~ D-BUS

r-~~-~~~~--~

~--~

~ ~ 0 ~

<t:
f-

a:: a::
f-

INPUT
GATES

a::
0

CONTROL

J¢l

I
I I

a..

r INPUT

FL~ GATES

OUTPUT
CKTS

OUTPUT MODULE

0
0

:::> a::

CONTROL~ ~ I
Lf~~~PUTI

I I

INTR
CNTL

ENABLE

L.-J-L

INPUT
CKTS

I
I

INPUT MODULE

+I I I +

t I

I
I
f

I I I I I

FIELD OUTPUTS

FIELD INPUTS

MA-2990

Figure 5-19

5-24

In terrupt

When the program addresses the interrupting module after the RIF
bit in the CSR has been set, the module's internal interrupt
f 1 i p- flo P will be res e t. Th e tim i ng d i ag ram in Fig u r e 5 - 2 0 wi 11
aid the reader in following the interrupt timing.

FIELD~

cos

l...--..-,

FLAG ----,

CSR - - - - ,
I
FLAG
L-I

~-----+----'
PDP 11 INTERRUPT SEQUENCEE]
MODIFIED D-BUS CYCLE
OCCURS HERE

r_---

MSYN-------4'~1
'

UNIBUS~~~

DATA~~~~
IAR DATA = MODULE ADDRESS ~

~~~RUS ------~f S---<' ~DRDRESS

H --(

~~g~~is

'------_----11

RIF

MA-2992

Figure 5-20

I/O Subsystem PDP-II Based Interrupt Timing

5.5.3
M87l9 Maintenance Mode
The IOCM has a maintenance mode that is activated when the program
sets the M bit in the CSR. In this mode, the usual D-bus Cycle is
not initiated when an attempt is made to read an I/O address. The
address is put on the D-bus but D SYNC does not occur and there i,s
no D RPLY. When the IOCM puts. the D-bus data on the UNIBUS data
1 ines, the program reads back the address. Thi s mode allows ,a
diagnostic program to check the D-bus data lines for errors.
If the IoeM is in maintenance mode, it causes the CSR's F bit to
be set. If the E bit is also set, subsystem interrupts are
enabled, and one occurs if the processor status allows. The M bit
may be cleared by writing M=0 in the CSR or by reading the CSR
with R=l. Figures 5-21 and 5-22 show the signals, data paths, and
timing of the maintenance cycle.

5.6
SYSTEM POWER SUPPLIES
There are two power suppl ies used wi th I/O subsystems. They are
the H7870 and H7872, intended respectively for the H333 and the
H334 I/O module chassis. The difference between the two supplies
is that the H7870 provides power for both I/O modules and LSI-II
components, and the H7872 provides only I/O module power.

5-25

BUS TRANSCEIVERS

""~~Ult::Ult::
...

::) :E ::) ~

co X co X

::)-::)0

D IN
MPX

~5H~~

VECT
SEL

MPX

.OIl

CSR

~ ,

Il:

BUS
TX

a Ia ::)
<l: 0
a a

D GATE

~
o ~
~.~

M8719

- "'~
u

I-

::)

U
Il:

Il:

a
ll:

I,
u

/).

r---+-+-~~+-~~--~ ~----·I

Il:
>...J
a aa 0
a..
~ Il:
~ <l: ci
a
a a

...J

a..

I>- is a~ ~
Ul
Z

- - - TO OTHER I/O MODULES
)11111111111 D-BUS

l£
...J

CONTROL

L.L.

~ L-J I~PUT

L, -, GATES

y~~~PUTI

Il:

I-

a a

I NT R
CNTL

I I

a..
Il:

CONTROL

J¢l

F1n16N:~:s I

11+--+-_E_NA-<B-rL~

J_-_

OUTPUT
CKTS

OUTPUT MODULE

<.:J
~

Il:

o Z
Z

a
~ z
a a
<l: a
a

INPUT
CKTS

.. I I I ..
FIELD OUTPUTS

iNPUT MODULE

I I I I I

FIELD INPUTS

MA-29~ 6

Figure 5-21

Maintenance Mode (M=1 in CSR)

5-26

UNIBUS
CNTL C1
UNIBUS
ADDR
UNIBUS
MSYN
UNIBUS
DATA
UNIBUS
SSYN
DEVICE
SELECT
DATI
1000 DLAY

D-BUS
MA-3132

Figure 5-22

Maintenance Cycle Timing

If an LSI-II bus is included in an I/O Subsystem, it appears only
in the H333 chassis; therefore, the H333 chassis is the only on~
in which the H7870 is mandatory. However, since an H7870 can power
I/O modules as well as LSI-II options, some early systems use the
H7870 in both the H333 and H334 chassis. In thi s case, one H7870
i sus e d to po we r two H33 4 c ha s sis, 0 r i f the r e a r e no LSI -11
modules present, the H333 chassis and one H334 chassis. Thi$
requires some interchassis wiring which is not the same for all
system configurations. Details of this wiring are covered in the
installation instructions of Chapter 3, Paragraph 3.3.2.4.
5.6.1
H7870 Power Supply
The H7870 power supply provides both +12 Vdc and +5 Vdc outputs as
well as some LSI-II control functions. The supply is a separate
unit that slides into the bottom of the H333 or H334 chassis. AC
power is input thro ug h the fron t
panel v i a aline co rd; d¢
voltages are output via a cable with a connector that plugs into
the chassis. When used with the H333 chassis, there is an
add i t ion a 1 cab 1 e t ha t car r i e s t he LS I-II f un c t ion s (i. e ., B DC 0 K,
B POK, B EVNT, B HALT, and S RUN) from the H7870 printed circuit
board to the backplane of the H333 chassis. There is only one
version of the H7870 power supply. Conversion from 115 V to 230 V
operation is accomplished by manipulating internal jumpers ana
changing the fuse and line cord. The H7870 front panel controls
and indicators (Figure 5-23) are described below.

5-27

LINE
FUSE

AC ON/OFF

---,.,o:r---I~ @511i~
10
®
0 &~TC ® 0 ® ® ~
rn rIll c]
L"'--______~+1_2_V_...;;;D_C..;;..O_N__..,;O,FF
RTN

RUN

HALT +5V

POWER
CONTROL

AC IN
MA·3141

Figure 5-23

H7870 Power Supply

AC ON/OF'F swi tch

Applies ac
power
to
the
H7870
activates the power control outlet

Li ne fuse

Protects against ac 1 ine ove·rload. Fuse
rat i ng i s 6 • 2 5 A for 11 5 V 0 per a t ion, 0 r
3 A for 230 V operation

Power control outlet

When connected to the power control bus,
ties ac power ON/OFF control of all power
controllers to the AC ON/OFP swi tch 0 f
the H333 chassis

Ground 1 ug

Provides a safety ground
the power supply chassis

LTC swi tch*

When on, enables B EVNT L, ~~h ich is an
LSI-bus compatible line frequency signal
generated by the H7870

EN/HALT swi tch*

When on, enables program execution by the
LSI-II; when off, it places the processor
in hal t mode

DC ON ind icator

When lit, indicates that dc power is on
Should light when the ac ON/OFF switch is
turned on.

RUN 1 ight*

Wh e n 1 it, i n d i cat e s t hat
processor is running

+5 V test point*

For measuring +5 Vdc

+12 V test po int

For measuring +12 Vdc output

RTN test po in t

Meter return for dc voltage measurement

connection

the

LSI -1 1

o~tput

* Applies only if an LSI-II is present in the H333 chassis.

5-28

and

5.6.2
H7872 Power Supply
The H7872 is a +12 Vdc regulated power supply used for powering
the H334 chassis. The supply is a separate unit that slides into
the bottom of the H334 chassi s. AC power is input through the
front panel via a line cord and +12 Vdc is output via a cable with
a connector that plugs into the H334 chassis. There are two
versions of the supply: H7872-A powered by 115 Vac, and H7872~B
powered by 230 Vac.
5.6.2.1
H7872 Detailed Description - A functional block diagram
and basic construction of the supply are shown in Figures 5-24 and
5-25 respectively.
Pr imary power (115 Vac or 230 Vac) is appl ied to the ac input
connector via the proper line cord (Figure 5-25). The line fus:e
and barrier terminal strip jumper configuration are also functions
of the type of service (115 Vac or 230 Vac) intended.
AC power from the terminal strip is applied to the stepd.own
transformer, the output of which is applied to the rectifier and
filter circuit. The resultant dc power is applied to fuse Fl and
thro ug h the ser ies pass transi stor s to 0 utput connec to r Pl. Fuse
Fl protects the circuit board etch in the event of a circuit
failure. Output current and voltage are monitored by the regulator
circuit which controls the voltage drop across the pass
transistors. This circuit provides output voltage regulation and
foldback current limiting which ensures that the maximum current
output never exceeds 7 A (3 A maximum if the output is shorted).
The crowbar circuit shown shorts the power supply output t:o
protect the subsystem from an overvoltage condition. Fuse F2
protec ts the c irc ui t board etch in the even t 0 f crowbar SCR
fail ure. The LED at the output 1 ights when the output vol tage is
present. Output connector PI is on the end of a cable that plugs
into a mating connector on the H334 chassis. Test po ints TP 1 and
TP2 are located on the front panel, and provide a convenient means
of measuring output voltage.

AC LINE FUSE
2AFOR l15V
OUTPUT
CONNECTOR
Pl

TPl
+12V

PRIMARY
POWER
(115V/230V)

7::::,

t---o"J>--<>1 O - - - - - - 1 b { J - r - - - - t 4

lOA
POWER
XFMR

8
RECTIFIER
AND
FILTE R

~~~P2~~V/
SERVICE

AND
FOLDBACK
CURRENT
LIMITER

OVER
VOLTAGE
CROW BAR
CIRCUIT
F2
TP2
RTN

-0\..0-

62 rna
RTN

BARRIER
TERMINAL
STRIP

Figure 5-24

H7872 Power Supply Block Diagram
5-29

Fl = lOA

Rfi VOLTAGE ADJUST -----"'-.:::--I)~4.4?:l
SLIDE CHASSIS FORWARD _ _ _ _~
TO ADJUST R6 THROUGH
ACCESS HOLE ON BOTTOM
+12 V TEST { POINTS
+

POWER
PLUG

MA-3120

Figure 5-25

H7872 Power Supply

5-30

CHAPTER 6
FUNCTIONAL I/O MODULES
6.1
INTRODUCTION
This chapter contains data sheets for each functional I/O module
used in the I/O Subsystem. Each sheet includes a functional
description, specifications, and other pertinent data to aid the
user in implementing the modules in his particular system. The
sheets are arranged in the following order.
M50l0
M50l1
M5012
M5012-YA
M5013
M5014
M5016
M5031

M6010
M6010-YA
M6011
M6012
M6013
M6014
M6015
Analog Input Subsystem - General

A014
A156
A157
A020
ATR16
A630
A631
BC40L

The user should carefully read the data sheets for each module in
his
system,
paying particular
attention to any of
the
switch-selectable options that may pertain to his system.
6.2
MODULE INTERFACES
All I/O modules in this chapter provide an interface between field
equipment and the D-bus. Standard D-bus signals are shown in. Table
6-1-1; those that are relevant to a particular module are
discussed in the individual module sections. The field interface
connector configuration is shown for each type module for a.
customer providing his own field wiring terminations. Customers
using optional DIGITAL-supplied screw terminal field wiring
terminations are referred to Chapter 3 (Installation)
for a
description of field wiring configurations for each type module.
6.3
NUMBERING CONVENTIONS
To avoid confusion, the reader should remember that, in all module
descriptions, octal numbers are used for channel numbers, generic
codes, and addresses. Everything else is numbered decimally.
L

6-1-1

Table 6-1-1

O-Bus Interface Connector Pin Assignments
Connector 0

Connector C
Pin
A
B
C
D
E
F
H
J

K
L
M
N
P
R
S
T
U
V

_. Side 1

Side 2

Side 1

Side 2

+12 V
D MUX HEL L
+12 V
+12 VB.
D D00L.
D D01 L
D D02 L
D D03 L
D D04 L
D D05 L
D D06 L
D D07 L
D DSYNC L
D DIN L
D DOUT L
GND
D RPLY L
D INIT L

Not Used

+12 V
D AUTO ZERO L
+12 V
+12 VB
D GBIT L
D TBIT L
D DBIT
D RIF L
D INTR OUT L
D INTR INH IN L
D INTR CLOCK L
D ADDR L
D MUX READY L
D ANA GUARD
DANA SIG
GND
D MUX STROBE L
D SYS CLOCK L

Not Used

GND

•
II

D ANA ERROR IN L

"
"

GND

•
II

"
"
"

D INTR IN L
D INTR INH OUT

"
"

•
•
•
D ANA ERROR OUT
•
"

Notes
1.
" = bussed connection
2.
• = daisy-chain connection
3. Module connectors C and D are shown here with all D-bus
signals, but a given I/O module uses only those signals
relevant to its function. The only I/O module connect.ions on
connectors A and B (not shown) are jumpers AM2 to AN2 and AR2
to AS2.

6-1-2

M5010
32-BIT NONISOLATED DC SENSE
FUNCTIONAL DESCRIPTION
The M5010 is a nonisolated dc sense module used for monitoring
voltages or contact closures. The module accepts up to 32 inputs,
structured as four 8-bit bytes, and sends them under program
control to the processor. Provision is made for program-controlled
testing, input disabling, and reading the module's generic code.
The mod ule al so fea tures an address se lect ion swi tch and fuse
protection.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-2-1 shows that field data
entering through JI is addressed and controlled by signals from
the D-bus interface connector and is ul timately output to the
D-bus. The sequence of control and data flow is as follows.
Data Paths
Each of the 32 field signals entering at Jl passes through a
signal conditioning network that serves to protect the module's
c i rcui try and enhances the integ r i ty 0 f the input s ig nal. Th is
network is made up of a diode, two resistors, and a capacitor. The
diode protects the input circuit from high positive input voltages
by becoming back-biased and the resistor combination protects from
high negative inputs by dividing the current to favor protection
of the series path. The series resistor and parallel capacitor
constitute a low pass filter that provides moderate high frequency
noise immunity.
After the above conditioning, each signal is applied to the input
of a Schmitt trigger which converts the field input levels to CMOS
levels required by the I/O subsystem.
All field signal common connector pins are bussed together and go
to the module ground through a series fuse, F-I. This fuse
protects the module from any common mode voltage difference
between the field equipment and the I/O Subsystem.
From the ou tputs 0 f the Schm i tt tr iggers the signal s go to the
con t r 0 I gat i ng sec t ion. Th i s s e c t ion a 1 so r e c e i v e s t wo con t r 0 I
inputs from the D-bus interface connector: TBIT and DBIT, which
under program control, may modify the data for testing. The output
of this section is normal data,
if these controls are not
asserted. If the program causes TBIT to be asserted, the output is
disabled and is read as all zeros. If both TBIT and OBIT are
asserted, the output is read as all ones.
The 32 bits out of the input gating section are grouped into four
8-bi t bytes fo r the input mul ti pI exer • One 0 f these bytes is
selected under control of the A0 and Al signals from the
mul ti pI exer control and is sent to the G mul ti pI exer.
The G
multiplexer outputs normal data to the D-bus input gating, unless
the GB IT is asserted. If the program asserts the GB IT, the G

6-2-1

O-BUS INTERFACE
CONNECTOR

r -________________________________________________________________________________O_T_B_IT__

TOBIT.

FIELD INTERFACE
CONNECTOR J-1

o GBIT

SIGNAL
CONDITIONING

+12

G MUX

I
I

- - -'- - -, - -

- - - --

I
I

GEN
CODE

GATING

D-BUS
INPUT
GATING

INPUT
MUX

0(0-7)

MODULE
AODR

--..l.---r-------

+12
ADDR
DEC

MUX
CONTROL

D SYNC
D ADOR

I
I

o I GATE

o RPLY

F-1
ODIN

II
I

MA-0213

Figure 6-2-1
Module M5010, 32-Bit Nonisolated
DC Sense, Simplified Block Diagram

multiplexer transmits the module's generic code to the D-bus input
gating instead of normal data. Data is then strobed onto the D-bus
by the DI GATE signal.
Control Signals
Control signals for the above sequence are initiated by the
program, resulting in the following control sequence. When the
program calls for a DATAl from one of the module's four addresses,
the IOCM starts a D-bus Cycle and causes the address to be put on
the D-bus. The module's address decoder decodes the address and,
after a short delay for deskewing, D SYNC is asserted. This causes
the multiplexer control to produce the A0 and Al signals for the
selection of the correct data byte by the input mul ti plexer.
At
this time MY ADDRESS is also produced. After a short delay, D DIN
is asserted and ANDed wi th MY ADDRESS to give DI GATE, whi ch
strobes data onto the D-bus. After a short delay, DI GATE alpo
produces D RPLY to notify the processor that data is on the D-buS.
When data is received by the processor, D DIN is negated, causing
DI GATE to negate and remove data from the D-bus.
If a modified D-bus Cycle follows to read the IAR, the D ADOR
signal clears the MY ADDRESS signal. This is necessary because in
a Mod if i ed D-bus Cyc Ie, D SYNC does not occur. Th is means tha t
when D DIN occ urred it wo uld put the mod ul e' s data on the bus
again, where it would overlap the IAR data.
Address Selection
The four addresses fo r the modul e must be ass ig ned accord ing to
the rules stated in Chapter 4. They are selected on the module by
the e i g h t - po 1 e s wit c h, E- 41 ( Fig u r e 6 - 2 - 2). To i 11 us t rat e the use
of thi s swi tch an example 0 f one poss i ble add ress select ion is
shown in Figure 6-2-3.
Generic Code
The generic code for the M50l0 module is octal 141.
Pin Connections
The M50l0 module pin connections for Jl,
are shown in Table 6-2-1.

the I/O cable connector,

Application Notes
1.

If unused inputs 0 f an M50l0 are 1 eft open c i rcui ted,
they can be infl uenced by ex ternal no i se • The random
switching of these inputs could be a cause of confusion
to the application programo It is, therefore, always good
practice to tie these unused inputs high (a logic zero).

When used for contact closure detection, a pull-up at the
user end of the field wire prevents the field wire from
acting like an antenna.

6-2-3

A1
81
C1

50,49

2,1

~f1

ADDRESS
SELECT
ON

12346678

OFF

I" 111111

o
E41

MA-OI89

Figure 6-2-2

E41

M5010 32-Bit DC Sense Module

_SWITCH NO.
_

1 = SWITCH ON
o SWITCH OFF

(///h (///h

'I,

OFF '///h '///h

_BITNO,

ADDRESS SELECTED
IS OCTAL 254
MA-0168

Figure 6-2-3

Address Selection Swi tch

6-2-4

Table 6-2-1

Module M5010 I/O Pin Connections

Module I/O
Connector
Pin

Field
I/O

Module I/O
Connector
Pin

Field
I/O

1
3
5
7
9

00
02
04
06
10

2
4
6
8
10

01
03
05
07
11

11
13
15
17
19

12
14
16
Common

12
14
16
18
20

13
15
17
Common

22
24
26
28
30

21
23
25
27
29
31
33
35
37
39

Common
20
22
24

32
34
36
38
40

Common
21
23
25

41
43
45
47
49

26
30
32
34
36

42
44
46
48
50

27
31
33
35
37

' I

SPECIFICATIONS
Power Requirements
Vol tage

Operating current

Main supply: VS
Backup supply:
(VS-0. 7) Vdc

= 12 Vdc + 2 Vdc
14

87 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 73 mA maximum
Backup supply: 14 rnA maximum
Standby current
(backup suppl y)

14 rnA max imum

6-2-5

Vdc

Input Characteristics
positive input voltage

+55 V max imum

Negative input voltage

-30 V max imum

Common mode input voltage

o V maximum

Logic zero threshold

8.2 V typical
12 V max imum

Logic one threshold

3.8 V typical
1.4 V minimum

Hysteresis

4.3 V typical

Input currents

At input = 0 V
0.47 rnA typical
0.73 rnA maximum
At input = -30 V
2.0 rnA typical
2 • 7 rnA ma x i mum
At input = +55 V
0.05 microamp typical
50 microamp maximum

Propagation delay

5.5 microseconds maximum

Fuse

picofuse 62.5 rnA

Mechanical
Dimensions

Quad module, single width, 8-1/2
inch length

Field connector

Cable type BC40A or customersupplied, 50-pin Berg~

Environmental

Complies with DEC STD 102, Class
C. Operates in convection cooled
env ironment up to 60 degrees C
ambient.

o . 1 7 7 Bt u/ h r ma x i murn due to
module circuits
11.0 Bt u/hr max imum due to field
inputs

Heat dissipation

6-2-6

M5~11

16-BIT CHANGE OF STATE INPUT
FUNCTIONAL DESCRIPTION
Th e M50 11 i s a n 0 n i sol ate d d c in put mod u 1 e use d for m0 nit 0 ring
voltages or contact closures. COS (change-of-state)
initiated
interrupt capability is also provided. The module accepts up to 16
inputs, structured as two 8-bit bytes, and sends them under
program control to the O-bus. Two additional bytes contain COS
information. Provision is made for program-controlled testing,
input disabling, and reading the module's generic code. The module
a 1 so f eat u res a n add res s s e 1 e c t ion s wit c h, i nt err up ten a b 1 e
switches for all 16 bits, and fuse protection.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-3-1 shows that field data
enter i ng thro ugh J 1 is add ressed and controlled by signal s from
the D-bus interface connector and is ultimately output to the
O-bus. Also shown is the interrupt selection and control
circuitry, which provides the option of having the module initiate
a processor interrupt when any input changes state. Data paths and
their control are discussed below.
Data Paths
Each of the 16 field signals entering at Jl passes through a
signal conditioning network that protects the module' s circuit~y
and en han c e s t h e i n t eg r i t Y 0 f the in pu t s i g n a I. Th i s net wo r k i s
made up of a diode, two resistors, and a capacitor. The diode
protects the input c i rcui t from high posi t iv e input vol tag es by
becoming back-biased; the resistor combination protects from high
negative inputs by dividing the current to favor protection of the
series path. The series resistor and parallel capacitor constitute
a low pass filter that provides moderate high frequency noise
immunity.
After the above conditioning, each signal is applied to the input
of a Schmitt trigger which converts the field input levels to CMOS
levels required by the I/O Subsystem.
All field signal common connector pins are bussed together and go
to the module ground through a series fuse, F-l. This fuse
protects the module from any common mode voltage difference
between the field equipment and the I/O Subsystem.
From the outputs 0 f the Schm itt tr iggers, the signal s go to the
control gating section. This section also receives two contr.ol
inputs: TBIT and DBIT, from the D-bus inter face connector, which
under program control may modify the data for testing. The output
of this section is normal data if these controls are not asserted.
If the program causes TBIT to be asserted, the data output will be
inverted. If OBIT is asserted, the output is disabled and is read
as all zeros. If both TBIT and DBIT are asserted, the output is
read as all ones.

6-3-1

O-BUS INTERFACE
CONNECTOR
FIELD INPUT
CONNECTOR
J-1

1----_-----11 ~----I

+12

INPUT

MUX

.....-_ _ _ _...J

O-BUS
INPUT
GATE

RiO-7)

I
I

I ________ .!!.7
___ 1
INPUT
CONTROL
GATING

1
I
I

---L---r-----

I
I

+12

Ai0-7)

F _1

o SYNC

MUX
CONTROL

o ADDR

01 GATE

ODIN
FLAG

o INTR OUT

o TBIT
MA-0197

Figure 6-3-1
16-Bit COS Input Module M5011,
Simplified Block Diagram

The 16 outputs of the input gating section are separated into two
8-bi t bytes and go to both the input mul ti plexer and the COS
detectors. If any of the field data bits changes state, this event
i s s tor e d a s a o n e i n t h e COS reg i s t e r • Th e 0 u t pu t 0 f the s e
registers also goes to the input multiplexer.
When the module is addressed,one of the four byte inputs to the
input multiplexer is selected by the A0 and Al signals from the
multiplexer control and sent to the IAR multiplexer. If the module
has an interrupt pending, and there is no higher priority
interrupt, the IAR multiplexer outputs the module's address when D
ADDR is asserted. Similarly, the next section, the G multiplexer,
outputs the module's generic code if the GBIT is asserted. The
output of the G multiplexer then goes to the D-bus input ga1ie
where it is strobed onto the D~bus by the DI GATE signal.
Data Control Signals
Control signals for the above mentioned data paths are initiated
by the program, resulting in the following typical contra I
sequence. When the program cqlls for a DATAl from one of the
module's four addresses, the IOCM starts a D-bus Cycle and causes
the address to be put on the D-bus. The module's address decoder
decodes the address, and after a short delay for deskewing, D SYNC
is asserted. This causes the multiplexer control to produce the A0
and Al signals for selection of the correct data byte by the input
multiplexer. At this time MY ADDRESS is also produced. After a
short delay, D DIN is asserted by the IOCM and ANDed wi th MY
ADDRESS to give DI GATE which strobes the data onto the D-bus. DI
GATE also' produces D RPLY after a short delay to notify the
processor that data is on the D-bus. When data is received by the
processor, D DIN is negated, causing DI GATE to negate and remove
data from the D-bus.
If the pro c e s so r rea d s the I AR i n res po n s e t 0 ani n t err up t fro m
this module, a Modified D-bus Cycle is initiated by the IOCM. In
this case, there is no D SYNC signal, but D ADDR occurs and causes
the IAR multiplexer to output one of the module's addresses
instead of data.
Interrupt Control Signals
If one of the field inputs changes state, a one is produced in the
COS reg i s t e r cor res po nd i ng t o t hat bit. I f t ha t bit ha s bee n
selected as an interrupting bit by one of the interrupt enable
swi tches, it prov ides an input to the interrupt control section.
This section produces a flag signal that results in a processor
interrupt if all priority requirements are met. (The flag signal
is an input to the INTR IN, INTR OUT daisy chain.) When the
interrupt occurs, a Modified D~bus Cycle is initiated by the IOCM.
As previously stated, this results in the D ADDR signal which
selects the address input to the IAR multiplexer and causes the
interrupt control section to produce A SET which results in MY
ADDRESS. When D DIN is asserted, the module's address is put on
the D-bus.

6-3-3

At this point the processor has identified the
interrupting
address. The appropriate interrupt service routine is then
executed. If now the processor RIFs the module (reads the
interrupting data address or the corresponding COS reqister with
R=l in the CSR) , the interrupt control section resets the COS
register to all zeros.
Address Clnd Flag Selection
The four module addresses must be assigned according to the rules
stated in Chapter 4. They are selected on the module by the 8-pole
s wi t c h , E: 48 ( Fig u r e 6 - 3 - 2). To i 11 us t rat e the us e 0 f t his s wit c h
one possible address selection is shown in Figure 6-3-3. Interrupt
enable selection for any or all of the 16 module inputs is
provided by switch modules E24 and E28 for the low and high bytes
res pe c t i vel y • Th e r e I at ion s hip 0 f fie 1 d s i g n a I n urn be r ~: to S wit c h
number s i. s shown in Fig ur e 6-3- 2.
Address Ii'ormat
The module's four data addresses, as determined by the
significant bits of the address word, are as follows.
Yl

Data (octal)

0
0

0
I

1
1

0
1

Field 00-07
Field 10-17
COS reg i s t e r 00-07
COS reg ister 10-17

two

least

Generic Code
The generic code for the M50ll module is octal 121.
Pin Connections
The M50ll pin connections
shown in Table 6-3-1.

for

Jl,

the

I/O

cable

connector,

are

Applicati.on Notes
l~

If unused inputs of an M50ll are left open circuited,
they can be influenced by external noise. The random
switching of these inputs could be a cause of confusion
to the application program. It is, therefore, always good
practice to tie these unused inputs high (a loq ic zero).

When used for contact closure detection, a pull-up at the
user end of the field wire prevents the field wire from
acting like an antenna.

6-3-4

50,49

2, 1
E24

Fflllllill 1
~,

L BYTE

INTERRUPT
ENABLE
E28

1['11111110
~t

H BYTE

E48

o
MA-0184

Figure 6-3-2

M5011 16-Bit COS Input

6-3-5

-------------------2

567

ON--~~~1~O~-1~O~1~

-SWITCH NO.
_
1 = SWITCH ON

o = SWITCH OFF
E48

_BIT NO.

01234567

L--"""L---.-.-J"""!":'"""Y""""'"---T-~
NOT
USED

ADDRESS SELECTED
IS OCTAL 254
MA·0173

Figure 6-3-3

Address Selection Switch

Table 6-3-1

Module M5011 I/O Pin Connections

Module I/O
Connector
Pin

Field
I/O

Module I/O
Connector
!Pin

Fielc
I/O

1
3
5
7
9

00
02
04
06
10

2
4
6
8
10

01
03
05
07
11

12
14
16
Common

12
14
16
18
20

13
15
17
Commc

11
13
15
17
19

21
23
25
27
29
31
33
35
37
39

22
24
26
28
30
,[I

Common

41
43
45
47
49

32
34
36
38
40

,v
Comm on

42
44
46
48
50
--I----.

6-3-6

SPECIFICATIONS
Power Requirements
Vol tag e

Operating current

Main supply: VS = 12 Vdc + 2 Vdc
Backup supply: 14 Vdc > vB >
(VS-0.7) Vdc
61 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 37 mA maximum
Backup supply: 24 rnA maximum
Standby cur r en t
(bac kup s uppl y)

24 rnA maximum

Input Characteristics
positive input voltage

+55 V maximum

Negative input voltage

-30 V max imum

Common mode input voltage

o V max imum

Logic zero threshold

8.2 V typical
12 V max imum

Logic one threshold

3.8 V typical
1 • 4 V min im urn

Hysteresis

4.3 V typical

Input currents

When input = 0 V
0.47 rnA typical
0. 73 rnA max imum
When input = -30 V
2 rnA typical
2 • 7 rnA max i mum
When input = +55 V
0.05 microamp typical
50 microamp maximum

Propagation delay

5.5 microseconds maximum

Fuse

62.5 rnA

6-3-7

Physical Characteristics
Dimensions
Field connector
Environmental Characteristics

Heat dissipation

Quad module,
inch length

single

width,

Cable type BC40A or
supplied, 50-pin Berg

8-1/2

customer-

Complies with DEC STD 102 Class C.
Operates in convection cooled
en vir 0 nm en t up to 6 0 d eg r e esC
ambient
0.759 Btu/hr maximum due to module
c ire u i try; 5 • 9 1 Bt u/ h r max i mum due
to field inputs

6-3-8

M5012
16-BIT ISOLATED DC INPUT
FUNCTIONAL DESCRIPTION
Th e M50 1 2 i s a n i so 1 ate d de in pu t mod u 1 e use d for m0 nit 0 ring
voltages where noise immunity or common mode rejection is
important. Interrupt capability on a per-byte basis is also.
provided. The module accepts :up to 16 inputs, all optically
isolated, structured as two 8-bit bytes, and sends them under
program control to the D-bus. Provision is also made for
program-controlled testing, input disabling, and reading the
module's generic code.
The module also features address and
interrupt enable switches and individual input indicators.
DETAILED DESCRIPTION
The simplified block diagram in 'Figure 6-4-1 shows that field data:
enter i ng thro ugh J 1 is addressed and contro lIed by signal s from
the D-bus interface connector a~d ultimately output to the D-bus •.
Also shown is the interrupt control circuitry, which provides the
option of the module initiating a processor interrupt when two of
the inputs change. Data paths and their control are discussed,
below.
~

SIGNAL CONDITIONING CIRCUITS
_______
________

D-BUS INTERFACE CONNECTOR --~
D TBIT

. -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ D DBIT

(

D(0-7)

INPUT

CONTROL

n- ---1_
l0-----

GATING

D(10-17)
~~------------~

D D
A(0-7)

MUX

01---- 1_

1'....

T -4 .... >-I"

I
DI

GATE

l;t}----

~-=49

D SYNC
D ADDR
D GBIT

~L; I;-ERFACE
CONNECTOR
DI GATE

D RPLY
D DIN
o INTR OUT
D INTRIN
D RIF
MA-0225

Figure 6-4-1
Module M5012, 16-Bit Isolated
DC Input Module, Simplified Block Diagram

6-4-1

Data Paths
Each of the 16 field inputs entering at Jl has a LED circuit that
indicates input circuit activity. Each input also goes through an
optical isolator that isolates the I/O Subsystem from noise or
common mode voltages while allowing transmission of the desired dc
signal. Following each isolator is a low pass fil ter for high
frequency noise immunity and a Schmitt trigger which further
improves noise immunity.
The 16 field signals from the output side of the Schmitt triggers
go to the input gating section where they are separated into two
8 -bi t bytes. Th i s sec tion al so rece i ves two control inputs from
the D-bus interface connector: TBIT and DBIT, which under program
con t r 0 1 ,r may mod i f y the d a t a for t est i ng • Th e 0 u t pu t 0 f t his
section is normal data if these controls are not asserted. If the
program causes TBIT to be asserted, the data output is inverted.
I f DB I Tis ass e r ted, the 0 u t pu t i s dis a bled and i s rea d a s a I l
zeros. If both TBIT and DBIT are asserted the output is all ones.
The input multiplexer receives the two data bytes from the input
gating section, plus the module's generic code and the address
selection byte. This section is controlled by signals from the
multiplE~xer control section and provides normal data out if: one
of the module's two data bytes is selected~ the modules's identity
cod e i f the GBIT s i g n a l i s ass e r ted ~ 0 ron e 0 f the mod u 1 e' s
addresses if the D ADDR signal is asserted. The selected byte goes
to the DI gating section where it is strobed onto the D-bus by the
DI GATE signal.
Data Control Signals
Control signals for the above mentioned data paths are initiated
by the program, resulting in the following typical control
sequence. When the prog ram call s fo r a DATAl f rom one 0 f the
module's two addresses, the IOCM starts a D-bus Cycle and causes
the address to be put on the D-bus. The module's address decoder
decodes the address, and after a short delay for deskewing, D SYNC
is asserted. This causes the multiplexer control to produce the A0
signal for the selection of the correct data byte by the input
multiplexer. At this time MY ADDRESS is also produced. After a
short delay, D DIN is asserted by the IOCM and ANDed with MY
ADDRESS to give DI GATE which strobes the data onto the D-bus. DI
GATE also produces D RPLY after a short delay to notify the
processor that data is on the D-bus. When data is recE~ived by the
processor, D DIN is negated causing DI GATE to negate and remove
data from the D-bus.
If the pro c e s so r read s the I AR i n res po n s e to ani n t. err up t from
this module, a Modified D-bus Cycle is initiated by the IOCM. In
this case, there is no D SYNC signal but D ADDR occurs and causes
the input multiplexer to output one of the module's addresses
instead of data.

6-4-2

Interrupt Control Signals
If one of the interrupt.ing field in.puts (bit 07 or 17) change~
state, a pulse is produced by the COS circuit corresponding tq
that bit. If that bit has been selected as an interrupting bit by
one of the interrupt enable switches, it provides an input to the
in ter r upt control sec tion. Th i s section prod uces a fl ag sig nal
that results in a processor interrupt if all priority requirements
are met. (The flag signal is an input to the INTR IN, INTR OUT
daisy chain.)
When the interrupt occurs, a Modified D-bus Cycle is initiated by
the IOCM. Thi s resul ts in the D ADDR signal which sets up the
input multiplexer for address out and causes the interrupt control
section to produce A SET which results in MY ADDRESS. When D DIN
is asserted, the module's address is put on the D-bus.
At this point the processor has identified the interrupting
address. The appropriate interrupt service routine is then
executed. If now the processor RIFs the module (reads ,the
interrupting address with R=l in the CSR) , the interrupt contro~
section resets the flag.
Address Selection and Interrupt Enable
The two module addresses must be assigned according to the rules
s tat e d i n Ch a pt e r 4. Th e y are s e 1 e c ted 0 n the mod ul e v i a the
l0-pole switch in location E50 (Figure 6-4-2). Part of this switch
is al so used fo r enabl ing in ter r upts. To ill ustr a te the use 0 f
t his s wi tc h 0 n e po s sib 1 e com bin at ion 0 fad d res s a n d i n t err up t
enable selection is shown in Figure 6-4-3.
Generic Code
The generic code for the M50l2 module is octal 122.
Pin Connections
The M5012 module pin connections for Jl,
are shown in Table 6-4-1.

the I/O cable connector,

SPECIFICATIONS
Power Requirements
Voltage

Operating current

Main supply: VS = 12 Vdc +2 Vdc
Backup supply: 14 Vdc > VB >
(VS-0. 7) Vdc
14 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: l~ mA maximum
Backup supply: 4 mA maximum
Standby current
(backup supply)

4 rnA max imum

6-4-3

A1
B1
C1

DO c:::J c::::J
c::::::::J

50.49

[=:1 0

c::::::J
c:::J c::::J
A

J 1

V1
Al

2,1
ClOO
Cl

CJ
CJ
CJ

LED
ACTIVITY
INDICATORS

Cl
Cl
ClO7
C
Cll0
Cl

c=JD

CJ
CJ
CJ

c::::J

c::J c::::l

Cl
Cl17

ADDR SEUINTR EN
ON 12345678910
OFF

11111111111 E50

V1
M-~-----------------------------------------MA·0188

M5012 16-Bit Isolated DC Input

Figure 6-4-2

ADDRESS
SELECT

..
2

- - - - LOW BYTE INTERRUPT ENABLED
_ _ _ _ HIGH BYTE INTERRUPT
NOT ENABLED

-SWITCH NO.

1 = SWITCH ON

o = SWITCH OFF
E50

23456

'---~---------------------

t '---y----J''----v.--''--y---.J

NOT
USED

F'igure 6-4-3

- B I T NO.

ADDRESS SELECTED
IS OCTAL 254
MA·0169

Address Selection and Interrupt Enable

6-4-4

Module M50l2 I/O Pin Connections

Table 6-4-1
Module I/O
Connector
Pin

41
43
45
47
49

8
10

050607-

12
14
16
18 ...
20
22
24
26

Not
Used

Field
I/O
0001020304-

4
6

05+
06+
07+

11
13
15
17'"
19

31
33
35
37
39

00+
01+
02+
03+
04+

3
5
7
9

21
23
25
27
29

Module I/O
Connector
Pi,n

Field
I/O

Not
Used

10+
11+
12+

32
34 . . .
36
38
40

101112-

13+
14+
15+
16+
17+

42
44
46
48
50

1314151617-

Input Characteristics
Differential input voltage

55 V maximum

Logic zero threshold

5.1 V typical
3.86 V minimum

Logic one threshold

5.65 V typical
8.35 V maximum

Isolation voltage
(between inputs
or from
inputs to ground)

1000 V

Common mode source

200 VA

Hysteresis

0.55 V typical

6-4-5

Input Gurrents

When input = +12 V differential
2.55 rnA typical
When input = +55 V differential
20.1 rnA max imum
When input = -12 V differential
0.05 microamp typical
50 microamp maximum

Propagation delay
Physical Characteristics
Dimensions
Field connector

2.5 ms typical
6.2 ms max imum
Quad module,
inch length

single

width,

Cable type BC40A 0 r
supplied, 50-pin Berg

8-1/2

customer-

NOTE
'rwo a-posi tion jumper str ips are
provided with the BC4gA screw
terminal assembly. Thesl~ allow the
user to connect the plus or minus
inputs
together,
in
a-input
groups, to facilitate field wiring
when a common field power source
is used.
Environmemtal Characteristics

Heat dissipation

Complies with DEC STD 102 Class C.
Operates
in convection cooled
en vir 0 nm en t up to 6 0 d eg r e esC
ambient
0.643 Bt u/hr max imum dUE! to mod ul e
circuitry
6 0 • 72 Bt u/ h r
inputs

6-4-6

max im urn due

fie 1 d

M5a12-YA
16-BIT TTL COMPATIBLE INPUT
FUNCTIONAL DESCRIPTION
The M50l2-YA is an isolated dc input module used for monitoring
open collector TTL signals. Interrupt capability on a per byte
basis is provided. The modul:e accepts up to 16 inputs, all
optically isolated, structured as two 8-bit bytes, and sends them
under program control to the D-bus. Provision is made for
program-controlled testing, input disabling, and reading the
module's generic code. The module also features address and
interrupt enable switches.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-5-1 shows' that field data
entering through JI is addressed and controlled by signals from
the O-bus interface connector and ultimately output to the D-bus.
Also shown is the interrupt control circuitry, which provides the
option of the module initiating a processor interrupt when two of
the inputs change. Data paths and their control are discussed
below.

SIGNAL CONDITIONING CIRCUITS

D·BUS INTERFACE CONNECTOR

r-----~A~_ ____..

D= ~ Ci=Q
5 ---------I~-

~
16

--------

D TBIT

S (0-7)

;r
S (10-17)

L---T-r':>-~~
I
I

C (0-7)

I
I

INPUT

01---------f.uv--------- L----,--r··.>--~-J
I

•.••

C (10-17)

MUX

r4-------i- L---~-~>-,,-CJ:
l:J:=F~E~~~~TERFACE

CONNECTOR

Figure 6-5-1

M50l2-YA l6-Bit TTL Compatible Input Module,
Block Di agr am

6-5-1

Data Paths
Field signals are input to the module through Jl. There is a
po sit i v e a nd a neg at i v e t e rm ina 1 for e a c h i n put • T:~ e po sit i v e
terminal of each input must be connected to a customer supplied
power source. The negative terminal is connected to a TTL
switching device.
Each of the 16 TTL field inputs entering at Jl goes through an
optical isolator. The isolator is followed by a low-pass filter
for high frequency noise immunity, and a Schmitt trigqer. The 16
fie 1 d s i g n a 1 s from the 0 u t put sid e 0 f the Sc hm itt t rig g e r s got 0
the input gating section where they are separated into two 8-bit
bytes. ~rhis section also receives two control inputs from the
D-bus interface connector: TBIT and DBIT, which under program
con trol can mod i fy the data fo r test i ng. The 0 utput 0 f thi s
section is normal data if these controls are not asserted. If the
program causes TBIT to be asserted, the data output is inverted.
If DBIT is asserted, the output is disabled and is read as all
zeros. If both TBIT and DBIT are asserted, the output is all ones.
The input mul tiplexer receives the two data bytes from the input
gating section, plus the module's generic code and the address
selection byte. This section is controlled by signals from the
multiplexer control section and provides normal data out if one of
the module's two data bytes is selected, the module's identity
code if the GBIT signal is asserted, or one of the module's
addresses if the D ADDR signal is asserted. The selected byte goes
to the DI gating section where it is strobed onto the D-bus by the
DI GATE s ig nal •
Data Control Signa1s
Control signals for the previously
initiated by the program, resulting
control sequence.

mentioned data paths are
in the following typical

When the program calls for a DATAl from one of the module's two
addresses, the IOCM starts a D-bus Cycle and causes the address to
be put on the D-bus. The module's address decoder decodes the
address, and after a short delay for deskewing,
D SYNC is
asser ted. Th i s cause s the mul ti pI ex er control to prod uc e the AO
signal for the selection of the correct data byte by the input
multiplexer. At this time MY ADDRESS is also producE!d. After a
short dE!lay, D DIN is asserted by the IOCM and ANDed wi th MY
ADDRESS to give DI GATE, which strobes the data onto the D-bus. DI
GATE also produces D RPLY after a short delay to notify the
processor that data is on the D-bus. When data is received by the
processor, D DIN is negated causing DI GATE to negate and remove
data from the D-bus.
If the pr 0 c e s so r read s the I AR i n res po n s e to ani n t j~ r r up t from
this module, a Modified D-bus Cycle is initiated by the IOCM. In
this case, there is no D SYNC signal, but D ADDR occurs and causes
the input multiplexer to output one of the module's addresses
instead of data.

6-5-2

Interrupt Control Signals
If one of the interrupting field inputs (bit 07 or 17) changes
s tat e, a p u 1 s e i s prod uc e d by the COS c i r cui t cor res po nd i ng to
that bit. If that bit has been selected as an interrupting bit by
one of the interrupt enable switches, it provides an input to the
interrupt control section. This section produces a flag signal
that results in a processor interrupt if all priority requirements
are met. (The fl ag sig nal is an input to the INTR IN, INTR OUT
daisy chain.)
When the interrupt occurs, a Modified D-bus Cycle is initiated by
the IOCM. This results in the D ADDR signal that sets up the inp~t
multiplexer for address out and causes the interrupt control
section to produce A SET, which results in MY ADDRESS. When D DIN
is asserted, the module's address is put on the D-bus.
At this point the processor has identified the interrupting
address. The appropriate interrupt service routine is then
executed. If now the processor RIFs the module (reads the
interrupting address with R=l in the CSR) , the interrupt control
section resets the flag.
Address Selection and Interrupt Enable
The two module addresses must be assigned according to the rules
stated in Chapter 4. They ar'e selected on the module via the
10-pole switch in location E50 (Figure 6-5-2). Part of this switch
is also used for enabling interrupts. To illustrate the use of
thi s swi tch one poss ibl e comb ina t ion 0 f add ress and in terr upt
enable selection is shown in Figure 6-5-3.
Generic Code
The generic code for the M5012-YA module is octal 123.
Pin Connections
The M50l2-YA module pin connections
connector, are shown in Table 6-5-1.

for

Jl,

the

I/O

cable

Application Information
The positive terminal of each input must be connected to a +5 vac
source (not to exceed +7 Vdc) •• The negative terminal is connected
to a TTL switching device. This should be an open collector
dr iver, but it can al so be a totem pole TTL output. An input is
defined as a logical one if the input voltage is less than +0.8 V,
and as a logical zero if the input current is less than 250
m ic roamps.
Fi eld connec tions fo r the M50l2-YA may be impl emen ted wi th the
BC40A screw terminal assembly. A typical interface is shown in
Figure 6-5-4. Field wiring connected to the screw terminals is
interfaced to the module via a cable provided with the screw
terminal assembly. Field power connections may be commoned on a
per-byte basis via the eight-position jumper strips provided with
the BC40A. Note that the +5 V power supply shown must be furnished
by the customer.
6-5-3

----

A1
81
C1

c:::::::J
DO c::::J
t:=J

50.49

c:::::::J
CJD c:::J
c::::J
A

J 1

V1
A1

2,1

c:::J00
c:::J

CJ
CJ
CJ

LED
ACTIVITY
INDICATORS

c:::J
c:::J
c:::J 07
C

c:::J 10
c:::J

CJD

CJ
CJ

c::::J
c:J t:=J
V1

CJ
c:::J
c:::J
CJ17

E50

V1
h-~-----------------------------------------.--~
MA·01BB

Figure 6-5-2

M50l2-YA l6-Bit T']'L Compatible Input Module

----r

ADDRESS

r -__

LOW BYTE INTERRUPT ENABLED

..---_____ HIGH BYTE INTERRUPT

~=======S=E=LE~C=T========~__il__~

2
3
4
5
6
7
8
9 10
ONrrm~-.--~-r~r-~-.--~-~__ ,

NOT ENABLED

-SWITCH NO.

1 = SWITCH ON

o = SWITCH OFF
E50

23456

t "--y----J''---v,-~''--y---J
NOT
USED

Figure 6-5-3

- B I T NO.

ADDRESS SELECTED
IS OCTAL 254
MA-0169

M50l2-YA Address Selection and Interrupt
Enabl e Swi tch
6-5-4

Table 6-5-1

Module M50l2-YA I/O Pin Connections

Module I/O
Connector
Pin

Field
I/O

Module I/O
Connector
Pin

00+ "'I
01+
02+
03+
04+ >To +5 V
05+ Supply
06+ *
07+

1
3
5
7
9
11
13
15,"'1
17
19
21
23
25 >27
29
31
33 ....
35
37
39
41
43
45
47
49

Not
Used

10+"'1
11+
12+ To +5 V
13+ >;u pp 1 y
14+
15+
16+
17+oJ

2
4
6
8
10
12
14
16
18"'1
20
22
24
26 >28
30
32
34....36
38
40
42
44
46
48
50

Field
I/O
00-"'1
010203- TTL
04- >Drive r
Input s
050607- oJ

Not
Used

10-"'1
111213- >TT~
14- Dr lve r
15- Input:s
1617-~

*Customer provided
SPECIFICATIONS
Power Requirements
Voltage

Main supply: VS = 12 Vdc + 2 Vdc
Backup supply: 14 Vdc > vB > (VS 0.7) Vdc

Operating current

8 rnA maximum
NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 4.3 mA maximum
Backup supply: 3.7 mA maximum

Standby cur r en t
(bac kup s upp1 y)

3 • 7 rnA max i mum

6-5-5

CUSTOMER SUPPLIED (+1-+-----,

M5012-YA

+5 V POWER SUPPLY

J-1

CUSTOMER'S

• JUMPER STRIPS

TTL DRIVERS

BC40A SCREW TERMINALS
'INTERFACE CABLE

'PROVIDED WITH BC40A

1~ i g u r e

6- 5- 4

Input Characteristics
Connections

MA-2177

M50l2-YA Typical TTL Field Interface

positive terminal
Operating: +5 Vdc, +5 percent
Absolute maximum: +7 Vdc
Negative terminal
Open collector or totem pole
T'l~ L

dr iver

Input current
(with +5 V supply)

3.2 rnA maximum per input (2 TTL
uni t load s)

Logic levels

Logic one: Vin ~ 0.8 V
Log i c z e r 0: 1 i n < 2 50 miG roam p

Isolation voltage

1000 V

Common mode source

200 VA

Propagation delay

Logic zero to logic one: 125
microseconds maximum
Logic one to logic zero: 400
microseconds maximum

6-5-6

Physical Characteristics
Dimensions

Fi eld connec to r

Environmental
Characteristics

Heat dissipation

Quad module, single width, 8-1/2
inch length
Cable type BC40A or
customer-supplied 50-pin Berg
connecto r
Complies with DEC STD 102 Class C.
Operates in convection cooled
environment up to 60 degrees C
ambient
0.6 Bt u/hr max imum due to mod ul e
c i r cui t s ; 1 • 1 Bt u/ h r max i mum due to
field inputs

6-5-7

M5013
a-BIT AC INPUT
FUNCTIONAL DESCRIPTION
The M5013 is an ac input module used for monitoring ac voltage
levels. An optional interrupt capability is also provided. The
module accepts up to eight transformer isolated inputs and
monitors their status. Provision is made for program-controlled
testing, input disabling, and reading the module's generic code.
The module also features an optional interrupt select switch,
address selection switches, individual input indicators, and MOV
input protection.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-6-1 shows that field data
entering through Jl is addressed and controlled by signals from
the D-bus interface connector and ultimately output as an 8-bit
byte to the D-bus. Also shown is the interrupt selection and
control circuitry which provides the option of the module
initiating a processor interrupt when field input 07 changes
state. The sequence of control and data flow is as follows.

Data Paths
The module provides status information for input circuits in the
90-140 Vac range. Up to eight inputs can be monitored to determine
their on or off conditions. Inputs less than 30 Vac are defined as
off and those above 90 Vac as on.
The module block diagram and a typical field connection are shown
in simplified form in Figure 6-6-1. As the figure shows, all
inputs entering at Jl go through transformers which provide
i sol a t ion from undes ired fi eld signal sand al so step down the
field voltage. Each transformer primary has a series LED to
indicate field circuit activity and a parallel metal oxide
varistor (MOV) for overvoltage transient protection. A rectifier
circuit and filter converts the secondary voltage to dc for inp~t
to the 555 threshold detector. The output of the A comparator is
high whenever its input is above 5.6 Vdc, corresponding to a field
i n pu t 0 f 9 0 Va cor m0 r e. Th i s res e t s f 1 i p- flo pCp r 0 v i ding a 1 ow
output. The B comparator goes high when its input is below 2.8
Vdc, correspond ing to a fi eld input 1 ess than 30 Vac. When the B
comparator goes high, it sets the C flip-flop providing a high
output. The 555 output provides the CMOS log ic levels necessary
for the subsystem.
The threshold detector outputs go to the input control gating
section which also receives two control inputs from the D-bus
interface connector: DBIT and TBIT, which under program control
may modify the data for testing. The output of this section is
normal data if these controls are not asserted. If the program
ca uses TB IT to be asserted, the output is inver ted. If DB I Tis
asserted, the output is disabled and is read as all zeros. If both
TBIT and DBIT are asserted, the output is all ones.

6-6-1

(TYpiCAL 1

FIELD INTERFACE
CONNECTOR

{,ELDCKT
I

XFMR

RECT

LPF

r;-HR7s'H~ ;;;E~R-

J·l

OOBIT
o TBIT

555

D G!!!T

NEUT

~~----~~-1~~--~----------"'~--~~

L_J

I
I

r-l
I

I
0'\

I
N

I
I

TI-II I
1

1__ 1_

I I I
I I

L_J
r-l
I
I

GATE

FIELD

INPUT
CONTR

L _ _ _ _ _ --1

I
I
I

o INTR OUT

FIELD

~LI!!.E > 40

NEUT

11--1I

~I_I_

60 . - - ' - - - - - - - ' "

L_J
Figure 6-6-1
Module M50l3 8-Bit AC Input
Simplified Block Diagram

o INTR IN
o RIF

The 0 utput 0 f the control g atihg sec tion then goes throug h the
input multiplexer and the G multiplexer to the D-bus interface
gating where it is strobed onto the D-bus by the DI GATE signal.
If either the D ADDR or D GBIT signals are asserted, the output is
either the module's address or its identity code, respectively.
Data Control Signals
Control signals for the above mentioned data paths are initiated
by the program, resulting in the following typical control
sequence. When the program calls for a DATAl from the module's
address, the IOCM starts a D-bus Cycle and causes the address to
be put on the D-bus. The mod ul e' s add ress decoder decodes the,
address, and after a short delay for deskewing, D SYNC is
asserted. This causes the MY ADDRESS signal to be produced. After
a short delay, D DIN is asserted by the IOCM and ANDed with MY
ADDRESS to produce DI GATE which strobes the data onto the D-bus.
DI GATE also produces D RPLY after a short delay to notify the
processor that data is on the D-bus. When data is received by the
processor, D DIN is negated, causing DI GATE to negate and remove
data from the D-bus.
If the processor reads the IAR in response to an interrupt from
this module, a modified D-bus Cycle is initiated by the IOCM. In
this case there is no D SYNC signal but D ADDR occurs and causes
the input mul ti pI exer to output the mod ul e' s address instead 0 f
data.
Interrupt Control Signals
If the field input 07 changes state, and the interrupt option
selection switch is in the on position, the interrupt control
section produces a flag signal. If all priority requirements are
met, the flag signal results in a processor interrupt. (The flag
signal is an input to the INTR IN, INTR OUT daisy chain.) When the
interrupt occurs, a Modified D-bus Cycle is initiated by the IOCM.
This results in the D ADDR signal which selects the address input
of the input multiplexer and causes the interrupt control section
to produce A SET which results in MY ADDRESS. When D DIN is
asserted, the module's address is put on the D-bus.
At this point the processor has identified the
interrupting
address. The appropriate interrupt service routine is then
executed. If now the processor RIFs the module (reads the module's
address with R=l in the CSR) , the interrupt control section resets
the module's flag fl ip-flop.
Address and Interrupt Selection
The module data address must be assigned according to the rules
stated in Chapter 4. It is selected on the module by the first
e ig ht swi tc hes 0 f the 10-po I e swi tch in location E9
(Fig ur e
6-6-2). An example of one possible address selection is shown in
Figure 6-6-3 to illustrate the use of this switch. The ninth
switch on this module is used to select the interrupt option.

6-6-3

A1
81
C1

50.49

J 1

ION

OFJ

10 I

111111 " II

ADDRESS/INTERRUPT SEL

2.1

c:::J 00
CJ

CJ
CJ
CJ

INPUT
ACTIVITY
INDICATORS

c:::J
CJ

CJ 07

)..--...-------------------------,---MA-Ol!IO

Figure 6-6-2

M50l3 AC Input Module

2
ON

6
0

INTERRUPT ENABLED

ADDRESS
SELECT

NOT USED

-SWITCH NO.
_

=SWITCH ON

o =SWITCH OFF

_BITNO

'---v---"'---v---,J~

~igure

6-6-3

ADDRESS SELECTED
IS OCTAL 254
MA-0171

Address Selection and Interrupt Enable

6-6-4

Generic Code
The generic code for the M50l3 module is octal 101.
Pin Connections
The M50l3 module pin connections for Jl, the I/O cable connector,
are shown in Table 6-6-1.

Table 6-6-1
Module I/O
Connector
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

Module M5013 I/O Pin Connections
Module I/O
Connector
Pin

Field
I/O
00

2
4
6
8
10

01
02

12
14
16
18
20

03
04
05

22
24
26
28
30

06
07

33}

35
37
39

43}

00
01
02
03
04
05
06
07

34}

Field
ac 1 ine

36
38
40

45
47
49

Field
I/O

Field
ac line

Field
ac neutral

6-6-5

44}

46
48
50

Field
ac neutral

SPECIFICATIONS
Power Requirements
Voltage

Operating current

Main supply: VS = 12 Vdc + 2 Vdc
Backup supply: 14 Vdc > VB <
(VS-0.7) Vdc
146 rnA max imum

NOTE
If the backup supply is implemented
total operating current is shared.
Main supply: 133 mA maximum
Backup supply: 13 mA maximum
Standby current
(bac kup s uppl y)
Input Characteristics
Input line voltage

13 mAmaximum

90-140 Vac @ 47-63 Hz = logic 1
0-30 Vac @ 47-63 Hz = logic 0

Input current

9.3 mA minimum @ 90 Vac minimum
25 rnA maximum @ 140 Vac maximum

Tur n-on tim e

8-20 ms @ 60 Hz
8-22 ms @ 50 Hz

Turn-off time

~-14

Contact resistance

Input remains in the logic 0 state
with 22K in series with 120 Vac
input

Isolation voltage

1500 Vrms from inputs to ground
(Inputs are not isolated from each
o the r)

Protection

MOV
over-voltage
protection of all inputs

Physical Characteristics
Dimensions
Fi eld connec to r

ms @ 50-60 Hz

Quad module,
inch length

triple

\llidth,

Cable
type
BC40B or
supplied, 50-pin Berg

6-6-6

transient

8-1/2

customer-

Environmental
Characteristics

Heat dissipation

Complies with DEC STD 102 Class C.
Operates
in
convection
cooled
en vir 0 nm en t
up to 6 0 d eg r e e C
ambient
6.71 Btu/hr maximum due to module
circuits;
92.4 Bt u/hr max imum due to field
inputs

6-6-7

M5014
DUAL INPUT COUNTER

FUNCTIONAL DESCRIPTION
The M50l4 input module contains two independent l6-bit counters.
Each counter is a presettable up counter with internally generated
frequency and time bases. Inputs may be isolated or nonisolated,
low level, high level, or TTL. Typical appl ications include
frequency measurement (e.g., RPM and flow meter), event counting,
and pulse width measurement. Each counter has several switches
that allow the selection of alternate time bases,
input
configurations, counting modes, and interrupt modes. Provision is
made for prog ram controlled testing, input and output d isabl ing,
and reading the module's generic code. Other features include LED
input status indicators, fuse protection, and an address selection
swi. tch •
GENERAL DESCRIPTION
The M50l4 consists of two independent counters with a common D-bus
interface. Figure 6-7-1 is a simplified block diagram of the
module. Each counter receives X and Y inputs from field connector
(J3l) that are used singly or in combination depending on the
application. Each counter has nine programming switches for
selection of its input circuit configuration. A common generator
produces the necessary frequency and time bases for both counters.
Besides the field inputs, the figure also shows data inputs to the
counters from the D-bus. This allows presetting the counters to
any desired starting point. Presetting to zero allows 65,535
events to be counted. Output data from the counters is interfaced
to the D-bus via a multiplexer.
DETAILED DESCRIPTION
The module consists of two printed circuit boards assembled in a
mother-daughter configuration (Figure 6-7-2). The heavy dashed
line in Figure 6-7-1 shows how the module's circuits are divided
between the two circuit boards. The mother board (G670) contains
the counters, data paths, and interrupt logic. The daughter board
(54-13585) contains input signal conditioning, counter control,
and frequency and time bases.
Mother Board
Th e mot he r boa r d i s a mu 1 t i pu r po sec i r cui t boa r d wit h c i r cui t s
that are not used in the M50l4. One of these circuits is the
self-test circuit used for factory testing the mother board when
no daughter board is present. This circuit includes two gates in
the interrupt logic which permit the counters to generate
interrupts when they decrement to zero. The test circuit is
disabled when the daughter board is present; the daughter board
then controls all count and interrupt functions.

6-7-1

....--------.1
FUNCTION
SWITCHES

FIELD
INPUTS

DAUGHTER BD

AOVF

MOTHER BD

I
A

J 31

A
COUNTER

r--

A COUNTER
INPUT
CONDITIONING

INTR~.'----I-----,~~
-----In
I
I

INTERRUPT
LOGIC

B INTR----.!I

I LI

_____ A
INTR

o LiL------------, I

ANTI-COINCIDENCE_

CIRCUIT

FREQUENCY
AND TIME
BASES

0"'1

I
~

B COUNTER
INPUT
CONDITIONING

J
B
-----INTR

OVF~

I r--_rv'--"\
I
I
I

HIGH
BYTE
INPUT
BUFFER

'------~~

I---r-.,.-----------,v
B
COUNTER

01
MUX

I
f--

I------,v

LOW
BYTE
OUTPUT
BUFFER

_______ ANTI-COINCI DENCEI--_ _ _ _----'
CIRCUIT

I f,---------,---L-...j
FUNCTION
SWITCHES

I
I

CONTROL

RI
I IUI

~----------------------~I

MA-3157

Figure 6-7-1

M50l4 Counter Module, Block Diagram

In addition to the test circuit, each of the 16-bit counters has
an extra flip-flop associated with its most significant bit. In
the M5014, this fl ip-flop is held reset and the counter operates
as a 16-bit up counter. In the M6014, which also uses the G670,
the MSB is always zero and the counter operates as a 15-bit down
counter.
The MSB from the bus is routed through the extra
f 1 i p- flo P wh i c hope rat e s a s the s i g nor d ire c t ion bit 0 f the
M6014.

MOTHER BD
(G670)

DAUGHTER BD
(54-13585)

FIELD

1 . - - - - - - - " l ; : : i - CON N ECTO R

B COUNTER

FUNCTION

SWITCHES

11,1 1 '

~
E3~ 11
"rk
E23

IIII

MANUFACTURING
TEST CONNECTOR
(NOT FOR FIELD
CONNECTIONS)
A COUNTER
FUNCTION
SWITCHES

MODULE
ADDRESS
SELECT
MA-3171

Figure 6-7-2

M5014 Co un ter Mod ul e

Finally, the generic code circuit is capable of generating generic
codes 044-047 and 144-147. The least significant digit is chosen
independently for the two counters by the daughter board. The
M6014 always provides generic code 044 for either counter. The
M5014 generates codes 144-147 independently for each counter.

6-7-3

Data Paths
The data paths of the mother board resemble those of
four-address D-bus modules with the following exc~ptions.

other

set of gates in the input data path momentarily
inhibits the bus data and forces the internal data lines
to zero when the modul e is ini tial i zed. These gates are
necessary because the counters can be cleared only by
loading them with zeros. Upon assertion of D INIT, or at
the beginning of D TBIT assertion, wide and narrow
:L nit i ali ze s i g n a 1 s are' 9 en era ted t ha t res pe c t :L vel y z e r 0
the data lines, and load the counters.

1m input buffer is necessary for the high byte because
16 parallel bits must be loaded into the counters from an
B-bit bus. When the program wants to load one of the
counters, it must write the high byte first. This data is
stored in the common input buffer until the low byte is
ltlritten, at which time both the buffered high byte and
the low byte data are loaded into the counter.

An output buffer is necessary for the low byte to prevent
data seen by the program from being changed b(~tween the
readings of the high and low bytes, even though the
counter itself may have changed. When the high byte of
€~ither
counter is selected and read directly onto the
D-bus, the corresponding low byte is loaded into the
common
output
buffer
for
retrieval
by
a
later
l.nstruction. Therefore, both bytes represent data at the
same point in ·time.

1'he module has only one input and one output bu:Efer which
are shared by the two counters.

In the M6014, the MSB of each counter is rout.ed
t.he co un ter to the s ig n/d i r ec t ion fl i p- flop.

around

Anticoincidence Circuit
Each counter has an anticoincidence circuit that prevents counting
during the reading of the high byte and storage of the low byte by
a DATAl. It also delays these reading and storage operations,
allowing the necessary data settl ing time that would bE! required
if a count had occurred immediately prior to the DATAl. A
s imp 1 i f i ed ant i co i nc ide nc e c i r cui t and its t im i ng are s ho wn i n
Figures 6-7-3 and 6-7-4.
Th e c i r cui t
decoder, and

( Fig ur e 6 -7 - 3 ) con sis t s 0 f a n a n a 1 og s wi tc h , a
two delays. The purpose of the analog swi tch is to

6-7-4

DIN

READ LOW BYTE

AOO

WAIT

)-------~RPLY

1.2/lsec
D I GATE

BUFFER STROBE

COUNTER IN

MA·3163

Figure 6-7-3

Anticoincidence Circuit

I BUS CYCLE 2 I

BUS CYCLE 1

SYNC

ANTI-COIN
INPUT
ANTI-COIN
OUTPUT

c:r

DELAYED
COUNT

DIGATE

RPLY

f-J

cf
~

.- ~

1.2/lsec
DELAY

1'-'

SETTLING TIME'
1.2/lS()c_· DELAY

,.....--

~~~

DELAYED REPLY

O.2"~' DEL:3J:.

BUFFER
DATA
MPX DATA

r..f

COUNTER
DATA
BUFFER
STROBE
OUTPUT

r;:

r-I

DIN
WAIT

c:f

'-I

AOO

BUS CYCLE 3

-- H'--

NO
DELAY

If:"''" ~

G-L-

C. -tJ
'---~

READ HIGH BYTE
(COUNT DELAYED UNTIL
END OF CYCLE)

READ LOW BYTE
(BUFFER DATA STABLECOUNT NOT DELAYED)

(

READ HIGH BYTE
DI GATE, STROBE, AND RPLY
)
DELAYED UNTIL DATA IS STABLE
MA-3144

Figure 6-7-4

Anticoincidence Timing
6-7-5

disconnect the input to the counter (WAIT) while it is being read.
When the input is disconnected, the voltage at the input of the
Schmitt trigger (second inverter) is retained on the capacitor.
Diode Dl removes the effect of an open switch upon the negative
transition of COUNTER IN, which is not of interest to the counter.
Diode D2 improves the noise immunity of the circuit by pulling the
Schmitt trigger voltage away from the threshold when the switch is
opened.
The first function of the anticoincidence circuit is to delay the
leading edge of the counter input signal for the entire input
portion of the bus cycle. In the first bus cycle of Figure 6-7-4,
the decodE~r detects a high byte DATAl (i .e., the address A00H and
DINH). Th i s prod uc es the WAIT s ig nal tha t 0 pens the analog swi tch,
delaying the counter input (anticoincidence output) until after
the D-bus has received RPLY, accepted the data, and neg ated DIN.
Stable dat.a is guaranteed at the input of the buffer, at the
leading edge of BUFFER STROBE, and on the bus during the assertion
of RPLY.
The second function of the anticoincidence circuit is to delay
RPLY from the module to ensure stable data if the counter has
changed immediately prior to the DATAl. The third bus cycle of
Figure 6-7-4 is similar to the first except that the counter has
already received the leading edge of the anti-coincidence output.
The 1.2 microseconds delay of Figure 6-7-3 delays BUFFER STROBE
and RPLY until the buffer input data and multiplexer data are
again stable.
The anticoincidence function is unnecessary when the low byte is
being read (A0lL AND DINH) because it is the buffer, not the
counter, that is being read. Since this data is always stable
(except when the high byte is read), the decoder does not issue a
WAIT signal to the analog switch and the 1.2 microseconds delay is
bypassed. This is shown in the second bus cycle of Figure 6-7-4. A
0.2 microseconds delay of RPLY always exists for normal bus
deskewing requirements.
Daughter Board
When the G670 mother board is equipped with a daughter board, all
counter control and interrupt stimuli originate on the daughter
board. The- M50l4 input counter uses the 54-13585 daughter board
and the counters on the mother board operate as 16-bit up
counters. The daughter board monitors only the overflow line from
each counter which is asserted when the counter reaches the all
ones state. (MSB information from each counter is also available
to the daughter board, but is not used in the M5014.)
The 54-13585 daughter board contains two
identic,::.l
input
conditioning and control sections, and one frequency/time base
sou r c e • 'llh e d aug h t e r
boa r d pro v ide s e 1 e c t ric a l i n t e r fa c e ,
frequency and time bases, mode selection, and counter enabling for
the module's field inputs.

6-7-6

Figure 6-7-5 is a block diagram of the 54-13585 daughter board
showing X and Y inputs entering at the field connector (J3l). Each
of these inputs interfaces to the module via an electrical and
1 og i cal in t e r fa c e c i r cui t • Th e 0 u t put s 0 f the s e c i r cui t s are
equipped with LEOs for indicating the logical sense of the X and Y
signals. The X and Y signals are combined with the outputs of the
frequency and time base selection c ircui t in the mode log ic
section. Output of the mode logic section goes to the mode select
circuit where the appropriate combination of signal and frequency
or time base is selected.
The outputs 0 f the mode sel ec t c i rc ui t are A 8I G and A WINDOW;
they are respectively the counter input and time base signals. A
WINDOW is input to the counter enabling circuit. This circuit
causes the next true portion of A WINDOW occurring after a write
command to be output as A EN. Finally, A EN enables A SIG,
producing A CNTR IN, the signal that is ultimately counted.
Several inputs from the mother board shown in Figure 6-7-5 provide
the following control functions.
1.

TBIT and OBIT provide the
discussed below.

WR0 and WRI are inputs to the A counter enabling circuit
that respectively indicate that the counter is to be
armed and readied to count, or that the count is to be
aborted. WR2 and WR3 serve the same purposes for the B
counter enabling circuit.

A OVF and B OVF are interrupt control signals for the A
and B counters respectively; they occur when the counters
reach the all ones state.

4•

S YS C LOC K i s us e d
and time bases.

test and disable functions as

der ive

all

the mod ul e' s

f r e que n c y

Counter enable outputs are provided at J31 for both counters.
These signals enable the user to synchronize the counting interval
with other process activities.
Nine function selector switches for each input conditioning and
control section allow the user to select logical sense, frequency
and time base, mode, and interrupt options.

6-7-7

.---------------------,
J31
r--

ISOLATED
X INPUTS
NON-ISOLATED
X INPUT

FUNCTiON SELECTOR
SWITCHES

X ELECTRICAL
AND LOGICAL
INTERFACE

INPUT
CONTROL
GATING

I
ISOLATED
YINPUTS
NON-ISOLATED
YINPUT

I
I
I
I

X-Y
X+Y

A COUNTER
FREOUENCY
TIME BASE
SE LECT

5 KHz

A COUNTER
INPUT CONDITIONING
AND CONTROL

rL.

MODE
SELECT

r--I-+

'----

-------r"

FROM
G670 «

T BIT
0 BIT

B COUNTER
INPUT CONDITIONING
AND CONTROL

I
L

------.

,>--_A_O_V_F______+--+-____--'

-.J

J31

)>-~~------+-+---~

--~~

X iNPUTS

WRI

~ ::~F 11

i
~

r-------+

I
I
I

~ WRO

FREQUENCYfTlME BASE
WURCE
~------------~

YINPUTS

A
INTR

(X)

SYS CLOCK
(FROM G670)

COUNTER
ENABLING
CIRCUIT

AWINDOW

A EN
I----

...J

A
CNTR
IN

ASIG

MODE
LOGIC

~ ----

0"1

I
i

~
Y ELECTRICAL
AND LOGICAL
INTERFACE

CNTR A
ENOUT
CNTR B
EN OUT

BEN
B CNTR IN
B INTR

-}TO
_
G670

.J
MA-3161

Figure 6-7-5

54-13585 Daughter Board Block Diagram

}

TO
G670

Electrical and Logical Interface Circuit
The module is equipped with four field input interface circuits:;
one for each input of each counter. These interfaces provide th~
user with several input options to accommodate varying field
situations. Figure 6-7-6 shows some details of this circuit. Each
X and Y input is capable of accepting isolated inputs of high or
low levels, or non i sol ate d inputs of high or TTL levels.
Specific applications are configured via function selector
switches and a choice of input terminal options. The function
selector switches shown in the figure as Sl, S2, and S3 correspond
to switches E3l-l, E3l-2, E3l-3, E23-l, E23-2, and E23-3 for the A
and B counters respectively. The proper use of these options
enables the module to accept various combinations of X and Y.
inputs, even though they may differ in signal level, logical
sense, or common mode vol tage. Log ical senses are independently
sel ec tabl e via swi tches Sl and 82. The TTL/HIGH LEVE L c ho ice is
made for both X and Y inputs of a given counter with S3. It should
be noted that S3 affects only the nonisolated inputs. As the
figure shows, isolated inputs use separate input terminals to
accommodate different levels.

+
J31
H IG H
LEV

1 t--'VV\r-.,.-.t\I\r---~~----r--

21---+-~--------.

GATED
INPUTS

3
LOW
LEV

1-------'

+12 V = HIGH LEV
+5 V = TTL

TTL/H I G H LEV 11 t--~~--'----JVV'v---.-----.----J\.N'v----f'.,.
NON-ISOLATED 12
INPUT
REFERENCE
AND
HYSTERESIS
CI RCU ITS
t---------jf-----,
TOY

,------;-+ SE NSE

LPiN NUMBERS FOR

X INPUTS OF THE
A COUNTER SHOWN

FUNCTION
SELECTOR - - - - - SWITCHES

CIRCUIT

~
TTL/HL

SENSE
MA-3155

Figure 6-7-6

Electrical and Logical Interface
Simplified Circuit

6-7-9

At the module input points, current flowing in the isolated input
circuit constitutes a logical one, as does a low level to the
noni sol ated input c i rc ui t. The outputs 0 f these two c irc ui ts are
ORed to represent a single X or Y input. It is at the output of
the OR gate that the logical sense may be inverted by switch 81 or
82. Each of the four interface circuits is equipped ,,,,ith a LED
indicator. The LED is on for a true input.
Frequency and Time Base Select Circuit
The two input conditioning and control sections SharE! a common
frequency and time base source. From this source, the two
frequency and time base selection circuits choose the desired
inputs as a function of the position of switches E31-4 and 5, and
E23-4 and 5, for the A and B counters respectively. These switches
are shown as 84 and 85 in the block diagram of Figure 6-7-7. The
time base part of this section actually multiplies its inputs by
ten to a r r i v e a t its s e 1 e c ted tim e bas e 0 u t put ., T his i s
accomplished by a divide by ten counter that is started when the
counter is armed by writing the low byte (by WR0 for the A counter
or by WR2 for the B counter), and outputs one period for ten of
its input periods. This ensures that the time base starts within
10 percent of its period after the counter has been armed.
When the TBIT is asserted, this section puts out a 5 kHz frequency
and a ten second time base fo r test pur po se s. In thi s mod e,
loading the counter with zeros results in a count of 50,000
decimal. (This equals 141,520 octal which is representee, as 303 in
the high byte and 120 in the low byte.) When the OBIT iE: asserted,
all field inputs and outputs are disabled. Asserting the OBIT and
TBIT together prevents any field signals from being ORed with the
test signals.

TO OTHER FREQUENCY AND
TIME BASE SELECT CIRCUIT

A
COMMON
FREQUENCY I - SYS
......... TIMEBASE
CLOCK
SOURCE

"
,)

--1---+
FREQ
TIME
MUX

A
TIME BASE
(T/10)

I T X 10 1
I COUNTER I

FRE=E
SELECT

T BIT
WRO
~.

FREQUENCY/TIME SELECT
MA-3119

Fi<~ure

6-7-7

Frequency and Time-Base 8elect Circuit

6-7-10

Modes and Time/Frequency Bases
The counter has four operating modes: modes 1, 2, and 3 for
frequency or event counting and mode 4 for measuring time periods.
Typical applications of the four modes are illustrated in Figure
6-7-8. When modes 1, 2, and 3 are chosen, an appropriate time base
( internal or exte rnal) is chosen. When an external time base is
being used, the internal time base selection must be infinite. For
periodic inputs, the frequency of the input is determined by:

f = niT

where:
f = the frequency of the input (events per second)
n = the number of counts
T = the chosen time base in seconds.
In mode 4 an internal
d eterm ined by:

frequency

selected

and

the

period

= nlf

where:
T = the length of the period in seconds
n = the number of counts
f = the internal frequency selection.
The resolution of T is therefore I/f.
The propagation delays associated with the counter's X and Y
inputs are listed below in the module's table of specifications
and must be taken into consideration by the user for modes 2 or 3.
Note that the specification lists significantly different delays
for isolated and nonisolated inputs. If these delays and their
tolerances are not considered, the logical AND or OR of these
signals may result in counting invalid pulses or the negation of
valid pulses. The specifications list maximum propagation delays;
for purposes of calculation, the minimum delay can be assumed to
be one half the maximum delay.

6-7-11

T=COJ

Y'T~
I

MODE 1

r ------,

IL..._ _ _ _ _ _ _

L--_ _ _ _ _---'.

--'-t_-'-_-'--________

COUNT _ _
INTR

THIS MODE COJNTS EVENTS
OF X DURING v AND T.
(Y IS USED AS THE EXTER·
NAL TIME BAS!:')

---------~--------

1..IlJl.JL..JLJ

_~IL__

MODE2
THIS MODE COUNTS EVENTS
OF X AND Y DLRING ASSER·
TION OF T. (Y S USED
~------.--------- TO INHIBIT THE COUNT OF
CERTAIN EVENTS OF X.)
(T = .1,1, OR 10 SECONDS,
OR INFINITY.)
L...--_ _ _

X·y

T~:I
I

GOUNT

____I

INTR
OUTPUT
ENABLE

-.J

Y~~_ _~rl~

_________

X+Y

MODE:!
THIS MODE COLNTS EVENTS
OF X OR Y IN A PERIOD T
(T = .1, 1, OR 10 :lECONDS,
OR INFINITY).

~----------------L
----------------------L
I

COUNT _ _--'-_ _ _...L..-_ _---I._ _ _..L..!

INTR

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIllilllllllllllllllliliIII I

-----------~

L_J
I..J.II.wIIu.I...w.1LL
---------------_.L

X·y _ _ _ _ _ _ _ _ _ _~

L..-_ _ _ _ _

MODEL.
THIS MODE MEASURES THE
TRUE PORTION OF X WHEN
ENABLED BY Y.

COUNT _ _ _ _ _ _ _ _ _
INTR

OUTPUT
ENABLE _ _ _ _ _ _ _ _ _ _ _ _.......

L
MA-316D

Figure 6-7-8

Co un te rOper ating Modes

6-7-12

Counter Enabling and Interrupt Modes
The outputs of the mode select circuit consist of SIG, the signal
that is to be counted, and the WINDOW signal, which determines the
duration of the counting per iod • The WINDOW signal is asynchronous
to the occurrence of any write commands. Synchronization is
achieved by the counter enabling circuit (Figure 6-7-3). When the
application writes a counter's low byte, WR is produced (WR0 for
the A counter or WR2 for the B counter) , and the counter is armed.
The enabling circuit outputs a signal that starts on the first
positive transition of WINDOW after the counter has been armed,
and ends on the next negative transition. The output of the
counter enabling circuit enables the counter input as illustrated
in Figure 6-7-9.
Completion of the count always results in an interrupt, provided
subsystem and processor priority conditions allow. Selection of
the add i tional control func tions via swi tches E31-4 and 5, 0 r
E23-4 and 5, configures this circuit so that the counter also does
one of the following upon reaching the all ones count.
1.

Count for
over flows.

the

In terr upt when an all ones coun t i s reached, but continue
counting.

Interrupt
reached.

and

entire

time

stop counting

period

when

and

all

ignore

ones

count

ASIG

WRO----~n~-----------------------------------------I
AWINDOw-I

,I
1

ACNTREN----~I--------~'
1

\r-------------------------I

n.JlJ1J1:

I
COUNTER ARMED ~

A CNTR IN ---~I-------+I
AINTR ____

""""I- - - - - - - - - - - - - - - - - - - -

~I----------rl---~t~-------------------,

START COUNTING - - - - - - -......1
STOP COUNTING - - - - - - - - - - - - - '
AND INTERRUPT

Figure 6-7-9

MA-3162

Counter Enable (Counter A Shown)

6-7-13

any

PROGRAMl-IING INFORMATION

The contents of the counter may be read at any time. The high byte
must al'ways be read first. When this is done, low byte data is
stored in a common output buffer reg ister. When the low byte is
read, it is the data in the buffer that is read. Therefore, even
though the counter may increment dur ing the time between the high
and low byte readings, both bytes contain data of a Bingle point
in time ..
Wh~n

a counter is loaded, the high byte must be loaded first. This
data is not loaded directly into the counter but is stor~d in a
common input buffer register until the low byte is loaded. At this
time, both data bytes are loaded into the counter.

The counter is armed when the low byte is loaded and can beg in
counting within 10 percent of the time period selected by daughter
board s,~itches E31-8 and 9, or E23-8 and 9. For example, if the
swi tches are set for a ten second counting interval, the counter
can begin counting within one second.
A count€~r may be hal ted at any time by load ing its high byte only.
The coun ter contents are not al tered by thi s ac tion bec ause the
high byte is actually loaded into a buffer register as discussed
previously. The counter can be read at this time" However, when
the counter is restarted, the high byte should be reloaded before
loading the low byte.
Address Selection
The four mod ul e add resses must be assig ned accord ing to the r ul es
stated in Chapter 4. They are selected on the module by the 7-pole
s wi tc h, E61 0 f the mot her bo a r d (F i g u r e 6 -7 - 2). An e x am pI e 0 f 0 n e
po s s i bl e add res sse 1 e c t ion i s s ho wn in Fig u r e 6 -7 -1 0 to i 11 us t rat e
the use of this switch.

5~ L 4
IC:=]I
01
1 1
6
5 4
0
15
14
11 10
2
12
[:=J 1 1 11 11 1 I 0 I 0 11 I~EI 1 0 11 1 CI 1 1
13

.-J

DETERMINED BY 10CM ADDRESS
SELECTION AND COMMON TO ALL
MODULES IN THE 1/0 SUBSYSTEM

E61 OFF

SELECTED ADDRESS

IT SE LECTION

171254, 171255
COUNTER B = 171256, 171257

COUNTER A =

MA-3147

Figure 6-7-10

Add ress Se 1 ection Ex ampl e

6-7-14

Address Format
The mod u1 e' s fo ur data add resse s as d ete rm ined by the
significant bits of the address word are as follows.
Y1

Bits

0
0

0
1

00-07
10-17

1
1

0
1

00-07
10-17

two

1 east

counter A

1
counter B

Generic Code
The generic codes of the
mode and are as follows.
Mode
1
2

3
4

M5014 are

function

the

operatin9

Generic
Code
144
145
146
147

Note that because the modes for the two counters are chosep
independently, the module may have two different generic codes .•
Refer to the section: Modes and Time/Frequency Bases, for an
explanation of the four modes.
Pin Connections
The M5014 mod u1 e pin connec tions fo r J 31, the I/O c abl e connec to r.,
are shown in Table 6-7-1.

APPLICATION INFORMATION
A clear understanding of the M50l4 input options, operating modes,
and interrupt options is necessary to properl y use the mod ule.
Before proceeding with field wiring and function selector switc.h
configurations, it is recommended that the user review the
following sections.
Modes and Time/Frequency Bases
Counter Enabling and Interrupt Options
Field Connections
Field connections for the M5014 may be implemented with the BC40A
screw terminal assembly. Field wiring connected to the scr~w
terminals is connected to the module's field interface connectQr
(J31) via a cable provided with the screw terminal assembly. (The
module's other cable connection, J32, is for manufacturing test
purposes only and is not suitable for field interface.) There are
several possible field wiring configurations. The particular
configuration required depends on some user exercised options as
described below.
6-7-15

Table 6-7-1
Module I/O
Connector
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

Module M50l4 I/O Pin Connections (J3l)
Module I/O
Connector
Pin

Field
I/O
ISO HIGH LEV +
ISO LOW LEV +
ISO HIGH LEV +
ISO LOW LEV + Counter
No t used
A·
X NON-ISO IN
Y NON-ISO IN
ENABLE OUT
Common

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Common
34
X ISO HIGH LEV +
36
X ISO LOW LEV +
38
y ISO HIGH LEV +
40
Y ISO LOW LEV + Co un ter 42
Not used
B
44
X NON-ISO IN
46
Y NON-ISO IN
48
ENABLE OUT
50
X
X
y
y

Field
I/O
ISO HIGH LEV ISO LOW LEV ISO HIGH LEV Coun1
ISO LOW LEV No t used
A
Common
Common
Common
Common
X
X
y
y

Common
X ISO HIGH LEV X ISO LOW LEV y ISO HIGH LEV Y ISO LOW LEV Count
Not used
B
Common
Common
Common

The user has a choice of isolated or nonisolated inputs. Isolated
inputs may be high level
(25-55 V) or low level (12-28 V).
Moreover, isolated X and Y inputs need not be alike (i.e., one may
be a high level and the other a low level). Nonisolated inputs may
be high levels or TTL levels; however, nonisolated X and Y inputs
must be alike because the TTL/HIGH LEVEL option is selected for
both X and Y by a single switch.
The user may also use inverted logic levels. For example, suppose
that the user's signal for true X input is one that turns current
off (isolated input), or is a high level (nonisolatE~d input).
These are inverted inputs for the M5014 but may be used if the X
sense switch for that counter (Sl of E31 or E23) is placed in the
on position. The same option for Y inputs is selected 'rlith the Y
sense switch (S2 of E31 or E23)
0

Th e LED i n d i c a to r fa r a g i v en in pu t will be on for a true fie 1 d
input regardless of whether it is an inverted input, alS long as
the sense swi tc h fa r tha t input is proper 1 y set. The sense swi tch
also enables the user to define an unused X or Y input as either
true or false as required by the mode logic.
6-7-16

Examples of some possible field connections utili zing the BC40A
screw terminal assembly are shown in Figures 6-7-11, -12, and -13.
Tab 1 e 6 -7 - 2 con t a ins a co nv en i en t s umm a r y 0 f a l l sc r e w term ina 1
connections for the module.

USER
FURNISHED
48 V PWR. SUP.
- +
J31

BC40 A
SCREW
TERMINAL

USER
DRIVERS

M5014 COUNTER
MODULE

INTERFACE
CABLE
(PROVIDED
WITH BC40A)
MA-3122

Figure 6-7-11

M50l4 Isolated High Level Input Application

USER
FURNISHED

J31.--.-----------..

BC40A

M5014 COUNTER MODULE

+12 V

PWR. SUP.

USER'S DRIVERS

INTERFACE CABLE
(PROVIDED WITH BC40 A)

BC40 A SCREW TERMINAL

Figure 6-7-12

MA·3152

M50l4 Isolated Low Level Input Application
6-7-17

COUNTER MODULE

XCOM
~--

[y--"Y COM
~---

L
L

TTL
~
HL

INTERFACE CABLE
(PROVIDED WITH BC40 A)

BC40 A SCREW TERMINAL

USER'S TTL DRIVERS
e.g. 7400 OR 7404

Fiqure 6-7-13

MA·3151

M5014 Nonisolated TTL Input Application

6-7-18

Table 6-7-2

Module 5014 Field I/O Screw Terminal Connections
Screw
Terminal
Number

Field I/O

Isolated

{High level +
Low level

{High level +
y
Low leve 1 +
Co unter
A

Nonisolated

Not used
Not used
{ input
TTL/HL ~ common
{input
TTL/HL~ common
Enable
0 utput
common
common
common
High level +

---z..{

Low level

Isolated
Hig h level +
y

Counter

Low level

Nonisolated

Not used
Not used
{input
TTL/HL~ common
{input
TTL/HL ~ common
{output
Enable~ common

6-7 -19

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Function Selector Switches
Input senses, operating modes, interrupt modes, and frequencies or
time bases are selected by switch packs E31 and E23 for the A and
B counters respectively. The two counters are independent and may
be configured differently from one another.
When the desired operating conditions have been established,
switch selection may be facilitated by referring to Figure 6-7-14
which summarizes the possible configurations.

WHEN OFF:

WHEN ON:

{

TRUE = CURRENT IN ISOLATED INPUT
LOW LEVEL IN NON-ISOLATED INPUT

{

TRUE = NO CURRENT IN ISOLATED INPUT
HIGH LEVEL IN NON-ISOLATED INPUT

ON =
INVERT
SENSE

~
1

r--TTLlHL = OFF/ON
I
(BOTH X AND Y)

O~~ DDDDDDDDDI
I

L-y-J ~J ~ L- NOT USED

~
SWITCH
4 5

INTERRUPT MODE

SWITCH
6 7

FREQUENCY
BASE

SWITCH
8 9
MODE

kHz

RESOLUTION

TIME
BASE
sec

IGNORE FULL COUNT

100

0.01

INTERRUPT ON FULL
COUNT

0.1

1.0

0.1

10.0

0::)

NOTE:

}

HALT AND INTERRUPT
ON FULL COUNT

1 =ON

0= OFF
MA 3115

FiqurE~

6-7-14

Function Selector Swi tches - Usage Summary

6-7-20

SPECIFICATIONS
Power Requirements
Vol tage

Main supply: VS = 12 Vdc + 2 Vdc
Backup supply: 14 Vdc- > VB
(VS-0. 7) Vdc

Operating current

1 4 0 rnA ma x i murn

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 100 mA maximum
Backup supply: 40 rnA maximum
Standby current
(backup suppl y)

30 rnA max imum

Isolated Input Characteristics
Maximum ratings
positive input voltage
Negative input voltage
Short-term overload

+55 V
-55 V
Withstands accidental connection to
117 Vac (2 hrs maximum)

Thresholds

12-28 V

25-55 V

Logic zero

5.2 V typical
3.3 V minimum

8.7 V typical
5.5 V min im urn

Logic one

5.5 V typical
7.8 V maximum

9.3 V typical
13.2 V max imum

Hysteresis

0.3 V typical

0.6 V typical

12-28 V

25-55 V

Input current
At input = +12 V, diff.
At input = +25 V, diff.

4.7 rnA typical
10.6 rnA typical
1 2 0 rnA ma x i mum
0

At input = +55 V, diff.
At input = -12 V, diff.

Isolation voltage

50 microamp
max imum
0.05 microamp
typical

13.5 rnA max im urn
50 microamp
max im urn
0.05 microamp
typical

1000 V
200 VA for UL approval

6-7-21

Propagation delay

200 microseconds typical
350 microseconds maximum

Maximum input frequency

1000 Hz (50 percent duty cycle)

Nonisolated Comparator Input Characteristics
Max imum rating s
Positive input voltage
Negative input voltage
Short-term overload
Thresholds

+55 V
-55 V
Withstands accidental connection to
117 Vac (2 hrs max imum)
(TTL mode)

(Hig h-l evel mode)

Log ic zero

1.7 V typical
2.3 V max imum

6.5 V typical
7.9 V max imum

Log ic one

0.9 V typical
0.5 V minimum

4.2 V typical
3.2 V minimum

Hysteresis

0.8 V typical

2.3 V typical

Open circuit voltage

4.4 V typical
S.0 V max imum

11.2 V typical
13.5 V maximum

Input currents
At input = 0 V
-0~40 rnA typical
-0.57 rnA max imum

At input = +55 V
0.05 microamps typical
50 microamps maximum
At input = -55 V
-2.24 rnA typical
-2.50 rnA maximum
Propagation delay
Maximum input frequency

4 microseconds maximum
50 kHz (50 percent duty cycle)

Nonisolated Output Characteristics
Max imum rating s
Positive input voltage
Negative input voltage
Low voltage output
Off leakage current
Sink current

55 V
-0.6 V
0.4 V
20 microamps
250 rnA
6-7-22

Output timing

Maximum times (microseconds)
Vout

= 12 V, RL = 10K

Vout

= 55 V, RL = 3.5K

Transition

Propagation
Time

Transition
Time

Propagation
Time

Transition
Time

Zero to one
One to zero

0.3
30

0.1
10

0.6
20

0.2
6

NOTE
Propagation time is referenced
source of the activating signal.

the

Protection

The output c i rcui ts are protected
from field overvoltage conditions
by a 62 V zener diode across each
output. Common mode protection is
provided by a 1 A picofuse in
series with the dc return

Internal frequency base
range

100 kHz, 10 kHz, 1 kHz, 100 Hz,
+0.1 percent, switch-selectable for
each counter

Internal time-base range

100 msec, 1 sec, 10 sec, +0.1
percent
and
infinite,
switchselectable
for
each
counter.
Maximum
delay
from
arming
of
counter to beginning of time base
period = 10 percent of period

Physical Characteristics
Dimensions

Field connector
Environmental
Characteristics
Heat dissipation

Quad module,
set, triple
long

mother/daughter board
width, 8-1/2 inches

Cable
type
BC40A
provided 50-pin Berg

customer

Complies with DEC STD 102, Class C.
Operates
in
convection
cooled
environment up to 60 degrees C
6. 7 Bt u/hr. max imum from internal
sup pI Y; 1 0 • 2 Bt u/ hr. ma x i rn urn fro rn
field supply

6-7-23

M5~16

QUAD INPUT COUNTER/PRESCALER
FUNCTIONAL DESCRIPTION
The M5016 input module contains four independent 8-bit up counters
intended for prescaling and event counting applications. Each
counter has variable radix overflow detection and overflow driven
interrupt circuitry.
High and low level isolated inputs and
nonisolated inputs are provided. Several switches allow the
counters to be individually programmed for interrupt, reset, and
overflow level options. Provision is made for program controlled
testing, input disabling, and reading the module's generic code.
Other features incl ude fuse protection and an address selection
swi tch.
DETAILED DESCRIPTION
The simplified block diagram in Figu.re 6-8-1 shows the module's
four field inputs entering at Jl. Signal conditioning circuits fo~
each input convert the isolated ornonisolated raw field inputs to
module logic levels. The outputs of the signal conditioning
c i r cui t s go to the con t r 0 I gat i ng sec t ion. Th i s s e c t ion r e c e i v es
two control inputs: DBIT
and TBIT, which provide a program
controlled testing capability. When neither of the control signals
is asserted, this section outputs normal data. If DBIT is
asserted, all field inputs are disabled. Assertion of TBIT forces
all counter inputs to a logical one; therefore, if the inputs are
disabled, assertion of the TBIT causes all four counters to
increment. Repeated assertions of TBIT make it possible to
determine the radices of the counters.
Each output of the control gating section is input to an
anticoincidence circuit. These circuits are controlled by the WAIT
signal. No rmall y these c i rcui ts have no effect on the co unter
inputs. However, when a counter read operation takes place, the
WAIT signal is asserted, causing the counter input to be delayed
until the read operation is complete. This prevents the counter
from incrementing while it is being read so that erroneous data is
not put on the bus. Note that the anticoincidence circuit, as
implemented on this module, only functions when the module's data
reg ister is being read (high byte). It has no effect on read ing or
writing the status register (low byte). A detailed discussion of
the anticoincidence circuit under that heading is contained in the
M5014 input counter section.
Overflow information from the counters goes to the status register
and the counter data to the data mul ti plexer. The selected data
(i.e., counter data, status information, generic code, or the
module's address) goes to the D-bus input gating section where it
is strobed onto the D-bus by the DI GATE signal.

6-8-1

.---

FIELD
INPUTS

D, T, G BIT

ADDR

DIN, DOUT
DIGATE

INPUT
CONDITIONING
CIRCUITS

C~TL

INPUT
CONTROL
GATING
CNTR
DATA
SEL

OBIT

TBIT----

WAIT

MODULE
DATA
SEL

01
GATE

::>
co
Cl

STATUS
REG
01 GATE

ADDR-----J
GBIT----l

MA-3116

Figure 6-8-1

M5016 Quad Input Counter/Prescaler
Block Diagram

Counters
All four M5016 module counters are alike. They arE~ 8-bit up
counters equipped with overflow detection and interrupt circuitry.
Figure 6-8-2 shows the circui t for a typical counter. The swi tch
packs corresponding to 81 through 810 are E17, E18, EJ.9, and E20
for counters 0, 1, 2, and 3 respectively.
One of the counter's data output bits is sampled via one of the
swi tches, 81 throug h 88. The swi tch is presel ected by the user
according to the desired overflow detection point. For example, if
the us e r wi she s to de t e c t a co un t 0 f 1 000 ( bin a r y), he s e 1 e c t s
swi tch 3 (i. e ., bi t 2). The over flow detec t ion (DET) fl i p- flo p
shown goes low momentar il y when that bi t resets (i.e., when the
count changes from 0111 to 1000). This causes the OVF flip-flop to
set.
The OVF flip-flop is one of the overflow bits in the module's
status register. If switch 89 is ON, the OVF flip-flop causes an
i n t err u pt • Th e i n t err up t and the 0 v e r flo w bit s i n the s tat us
register are cleared when the status register is read with the RIF
bit set.

6-8-2

IN-----,

COUNTER

DATA

RST - - . . - - - + - - - - 1

~_OVF

INIT H

T
S10
INT
RIFL------------------------4--------+------~

SELECT OVERFLOW BIT

RESET ON
OVERFLOW

INTERRUPT
ENABLE
MA-3143

Figure 6-8-2

Counter Circuit

If switch 810 is ON, the counter resets on overflow. Therefore,
when 810 is ON, the counter essentially becomes variable radix,
appearing to be only the length selected by the overflow selection
switch (i .e., switch 3 in the above example). With switch 810 off,
the counter is always radix 256, eight bits, regardless of which
bit is selected for overflow detection.
The software can reset the counter via the R8T signal. A software
initiated reset does not cause the DET and OVF fl ip-flops to
respond as would an overflow.
Input Circuits
The module's isolated and nonisolated input circuits resemble
those of the M50l2 and M50l0 modules respectively. The isolated
inputs are dissimilar to those of the M50l2 only in that they
accept higher frequency inputs, and they have separate terminals
for high and low level inputs.
PROGRAMMING INFORMATION
The M50l6 module occupies two byte addresses on the bus. The low
byte contains a status register which provides data selection and
overflow information, as well as a clear enable bit. The high byte
contains the data register. The single read-only data register
serves all four coun ter sand conta ins, a t any given time, the
contents of the counter currently selected by the two low order
bits 0 f the sta tus reg i ster. Th i s means tha t befo re read ing the
module's data register it is first necessary to select the desired
counter by writing the appropriate bits in the status register.
Wh e non e 0 f the mod u 1 e 's co un t e r s 0 v e r flo ws and causes an
interrupt, the corresponding status register overflow bit
identifies the interrupting counter.
6-8-3

To have a counter cleared after its data is read, a one must first
be written in the status register's clear enable bit (bit 2).
Then, when that counter's data is read, both it and the enable bit
are clE~ared. A summary of data and status reg ister information iE
shown in Figure 6-8-3.
Address Selection
The two module addresses must be assigned according to the ruleE
stated in Chapter 4. They are selected on the module by the 7-pole
s wi tc h " E 4 2 ( Fig u r e 6 - 8 - 4). To i 11 us t rat e the us e 0 f t his s wi tc t
an example of one 'possible address selection is shown in Figure
6-8-5.
Generic: Code
The generic code for the M5016 module is octal 142.

CNTR
NO

{~~
~
~~;A~S:~ABLE
~
~

OVERFLOW
BITS
)
READ ONLY

(

=Jl

3 ---,

-----.

(READ/WRITE- SELF
CLEARING AFTER READING THE DATA
REGISTER)
DATA SELECT
(READ/WRITE)

1r..:.7.....I..:....,sl.....:5...-1":""'4~".;r'E.,...-...:..,2IiliJr1....,.......;0
BYTE
ADDRESS
00

'STATUS REG

o/L------,
=oJ
~

0
DATA REG

@TR. 0 DATA

170

~TR, 1 DATA

I CNTR. 2 DATA

1 0

~TR.3DATA

1 1

MA-3135

Figure 6-8-3

6-8-4

50.49

2.1

FUNCTION SELECTOR SWITCHES

COUNTER 3

COUNTER 2

COUNTER 1

COUNTER 0

ON 12345678910

11111111111

OFFill

II III III

OFF

11111111111:

.L.:0:.:...,;FF_ _ _---I L.,;,0_FF_ _ _---l

E18

E19

E20

E17

~Fl
Al

ADDRESS
SELECT

E42

MA-3117

Figure 6-8-4

M5016 Quad Counter/Prescaler

6-8-5

D I____ -----I'L....--l-----,I C~ "'---, ---,I [_4----'
CJ 1111 11 II ° 1° 11 II °111°1111°111 CIOIOI
_7

~----------------~

)

~---------'---Y--------------~
DETERMINED BY 10CM ADDRESS
SELECTION AND COMMON TO ALL
MODULES IN THE I/O SUBSYSTEM

O~~ 1° 11 11 10 11 10 [J.-

SELECTED ADDRESSES SHOWN:

11
STATUS REGISTER = 171254
DATA REGISTER = 171255

23456

'----------II

0= OFF
1 = ON
-BIT SELECTION

7.+- -BITNO.

MA-3146

Figure 6-8-5

Ad d res s Se 1 ec t ion Ex am pI e

Pin Connections
The M5016 module pin connections for Jl, the I/O cable connector,
are shown in Table 6-8-1.
Table 6-8-1

Module M5016 I/O Pin Connections

Module I/O
Connector Field
Pin
I/O
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

ISO HIGH LEV +~CNTR
ISO LOW LEV +
0
NON-ISO IN
Not used
ISO HIGH LEV +} CNTR

ISO LOW LEV +
NON-ISO IN
Not used
Common

,I
Common
ISO HIGH LEV +} CNTR

ISO HIGH LEV +}

ISO LOW LEV +
NON-ISO IN
Not used

4
6

8
10
12
14
16
18

IS a HIGH LEV -~CNTR
IS a LOW LEV 0
Co mmon
No t used
IS a HIGH LEV -}CNTR
IS o LOW LEV 1
Co mmon
No t used
Common

ISO LOW LEV +
NON-ISO IN
No t used

Module I/O
Connector Fi eld
Pin
1/ o

CNTR
3

22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

6--8-6

Common
}
IS a HIGH LEV IS a LOW LEV CNTR
Cornmon
2
No t used
IS a HIGH LEV - }
IS a LOW LEV CNTR
Co mmon
3
No t used

APPLICATION INFORMATION
Proper I/O module installation procedures are presented in Chapter
3, Paragraph 3.3.3.3. The M50l6 has the following additional
r e qu i r em en t s •
Field Connections
The field interface for this module is similar to that of other
dig i tal I/O mod ules. An ex ample 0 f the fi eld wi ring connect ions
for each type of interface is shown in Figure 6-8-6 and 6-8-7.
Screw terminal connections for all the module's counter inputs are
listed in Table 6-8-2.
Function Selector Switches
Overflow, reset, and interrupt options for each of the four
counters are individually selected on the module by the four
1 f2J - po 1 e s wit c he s, E 1 7 t h r 0 ug h E 2 0 ( Fig u r e 6 - 8 - 4). Th e four
counters are independent and may be configured differently from
one another. The option selection procedure is identical for each
counter and is illustrated in Figure 6-8-8. Only one overflow
level detection switch (1 through 8) should be ON at anyone time
or the counter may malfunction.
M5016
USER
FURNISHED
+12 V
SUPPLY

INTERFACE CABLE
I . . . . - - - - - - - - ( S U P P L I E D WITH BC40A)
L....-_ _ _ _ _ _ ._ _ _ _ BC40 A SCREW TERMINAL

MA·3154

Figure 6-8-6

Co un t e r 0 Isola ted Lo w Le vel In put Ap pI i cat ion

6-8-7

M5016
J1

BC40A

+12 V

/~~
_ _ _ _ INTERFACE CABLE
(SUPPLIED WITH BC40A)

1._ USER'S DRIVER

- - - - BC40A SCREW TERMINAL
MA-3153

Figure 6-8-7

Counter 2 Nonisolated Input Application

E17, 18, 19, OR 20
ON

RST CNTR ON
OVERFLOW = ON

2
4

INTR EN = ON

8
OVERFLOW
LEVEL
SELECT = ON

16
32
64
128
256
MA-3136

Fig ur e 6 -8 -8

Function Selector Switches

6-8-8

Table 6-8-2

Module M5016 Field I/O Screw
Terminal Connections
Screw
Terminal
Number

Field I/O

Counter
{

{

HIGH LEVEL

ISO LOW LEVEL

NON-ISO

Input
Common

ISO

HIGH LEVEL

ISO LOW LEVEL

NON-ISO

Input
Common

ISO

Common
Common
{

HIGH LEVEL

ISO LOW LEVEL

NON-ISO

Input
Common

ISO

HIGH LEVEL

ISO LOW LEVEL

NON-ISO

Input
Common

{ISO

6-8-9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

SPECIFICATIONS
Power Requirements
Vol ta9 e

Main supply: VS = 12 Vdc + 2 Vdc
Ba c k u p s up ply : 1 4 Vci C > VB
(VS-0.7) Vdc

10 rnA max imum

Operating current

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 3.2 mA maximum
Backup supply: 6.8 mA maximum
6.8 mA max im um

Standby curren t
(bac kup s uppl y)
Isolated Input Characteristics

Po sit i v e in pu t vol ta g e: + 5 5 V
Negative input voltage: -55 V
Short-term
overload:
Withstands
accidental connection to 117 Vac for
two hour s

Max imum rating s

Thresholds

Range

12-28 V

Log ic zero:

5.2 V typical
3.3 V minimum

typical
V min imum

Logic one:

5. 5 V typical
7.8 V maximum

• 3 " t yp i cal
3.2 V max im um

Hysteresis:

0.3 V typical

.6 V typical

Input current
At input = +12 V differential
At input = +25 V differential
At input = +55 V differential
At input = -12 V differential

4.7 rnA typical
1 0.6 rnA typical
12.0 rnA max imum
1 3 • 5 rnA ma x i mum
50 microamps
50 microamps
maximum
maximum
0.05 microamps 0.05 microamps
typical
typical

Isolation voltage

1000 V
200 VA for UL approval

Propagation delay

200 microseconds typical
350 microseconds maximum

Maximum input frequency

25-5S V

1000 Hz (50% duty cycle)
6-8-10

Nonisolated Input Characteristics
Maximum ratings
positive input voltage: +55 V
Negative input voltage: -30 V
Common mode input voltage: 0 V
Thresholds

Log ic zero:

6.7 V typical
9.7 V max imum

Log ic one:

4.1 V typical
1.7 V minimum

Hysteresis:

2.6 V typical

Input currents
At input = -30 V:
At input = +55 V:

2.0 rnA typical
2. 7 rnA max i mum
0.05 microamp typical
50 microamp maximum

propagation delay

7.0 microseconds maximum

Maximum input frequency

40 kHz (50 percent duty cycle)

Protection

Common mode protection is prov ided
by a 62.5 rnA Picofuse in series with
the de return

Physical Characteristics
Dimensions

Quad module,
inch length

Field connector

Cable
type
BC40A
supplied 50-pin Berg

Environmental
Characteristics
Heat dissipation

single width,
or

8-1/2

customer

Complies with DEC STD 102 Class C.
Operates
in
convection
cooled
environment up to 60 degrees C
0.5 Bt u/hr max imum due to mod ule
circuits; 5 Btu/hr maximum due to
field inputs

6-8-11

M5031
16-BIT ISOLATED CHANGE OF STATE INPUT
FUNCTIONAL DESCRIPTION
The M5031 is an isolated dc input module used for monitoring
voltages or contact closures. COS
(change-of-state)
initiated
interrupt capability is also provided. The module accepts up to 16
inputs, structured as two 8-bit bytes, and sends them under
prog ram control to the D-bus. Two add i tional bytes conta in COS
information. Provision is made for program-controlled testing,
input disabling, and reading the module's generic code. The module
also features an address selection switch, and interrupt enable
switches for all 16 bits.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-9-1 shows that field data
entering through JI is addressed and controlled by signals from
the D-bus interface connector and is ultimately output to the
D-bus.
Also shown is the interrupt selection and control
circuitry, which provides the option of having the module initiate
a processor interrupt when any input changes state. Data paths and
their control are discussed below.
Data Paths
Each of the 16 field inputs entering at J1 goes through an optical
isolator that isolates the I/O Subsystem from noise or common mode
voltages while allowing transmission of the desired dc signal.
Following each isolat'or is a low pass filter for high frequency
noise immunity, and a Schmitt trigger which further improves noise
immuni ty.
The 16 field signals from the output side of the Schmitt triggers,
go to the input gating section, where they are separated into two
8-bit bytes. This section also receives two control inputs from
the D-bus interface connector, TBIT and DBIT, which, under program
control, may modify the data for testing. The output of this
section is normal data if these controls are not asserted. If the
program causes TBIT to be asserted, the data output is all ones.
If OBIT is asserted, the outp'ut is disabled and is read as all
zeros. If both TBIT and DBIT are asserted the output is all ones.
The 16 outputs of the input gating section are separated into two
8-bit bytes and go to both the input multiplexer and the COS
detectors. If any of the field data bits changes state (in either
d i rec tion), thi s event is sto red as a one in the correspond ing bi t
in the COS register. The output of these registers also goes to
the input multiplexer.
The input mul ti pI exer rece iv es the two data bytes from the input
gating section, two more from the COS registers, plus the module's
generic code and its address byte. This section is controlled by
signals from the multiplexer control section and provides normal
data if one of the module's four data bytes is selected, the
module's identity code if the GBIT signal is asserted, or one of

6-9-1

,--_SI_G_NA_L_CO_N_D_IT--,I~,--N_IN_G_C_IR_C_UI_T_S_-...
D-BUS INTERFACE CONNECTOR--_-B-IT..!.n
D 1
l~_Jlr----------------------------------------------------------------~D~D~BIUUT
J-1 (

INPUT
CONTROL
GATING

~~~~====} L----,--f>-!:'- : !
I

--------L-

--------

~
~------50

I"""'"

l
L:

---~E~~:TERFACE

---.,---1 '>----1
I~'"
I

~" 10:

I!",

---r--!
:

C (0-7)

COS
DET

INPUT
MUX

17 t J :'

~--

DI
GATE

CONNECTOR

AO, A1
ADDR

INTERRUPT
CONTROL

MUX

D SYNC
D ADDR
D GBIT

D RPLY
D DIN
D INTR OUT
D INTR IN
D RIF

MA-0225A

Figure 6-9-1

M503l l6-Bit Isolated COS Input Module
Simplified Block Diagram

the module's addresses if the D ADDR signal is ass e r ted. Th e
selected byte goes to the DI gating section where it is strobed
onto the D-bus by the DI GATE signal.
Data Control Signals
Control signals for the above mentioned data paths are initiated
by the program, resulting in the following typical control
sequence. When the program calls for a DATAl from one of the
module's four addresses, the IOCM starts a D-bus Cycle and causes
the address to be put on the D-bus. The module's address decoder
decodes the address, and after a short delay for deskewing, D SYNC
is asserted. This causes the multiplexer control to produce the A0
and Al signals for selection of the correct data byte by the input
multiplexer. At this time MY ADDRESS is also produced. After a
short delay, D DIN is asserted by the IOCM and ANDed wi th MY
ADDRESS to give DI GATE which strobes the data onto the D-bus. DI
GATE also produces D RPLY after a short delay to notify the
processor that data is on the D-bus. When data is received by the
processor, D DIN is negated, causing DI GATE to negate and remove
data from the D-bus.
1 f t he pro c e s so r read s the I AR i n res po n s e to ani n t err up t from
this module, a Modified D-bus Cycle is initiated by the IOCM. In
this case, there is no D SYNC signal, but D ADDR occurs and causes
the input multiplexer to output one of the module's addresses
instead of data.
Interrupt Control Signals
If one of the field inputs changes state, the COS register bit
corresponding to that field input is asserted. If that bit has
been selected as an interrupting bit by one of the interrupt
enable swi tches, it prov ides an input to the interrupt control
section. This section produces a flag signal that results in a
pro c e s so r in t err up t i f a l l p rio r i t y r e qui r em en t s are met. ( Th e
flag signal is an input to the INTR IN, INTR OUT daisy chain.)
When the interrupt occurs, a Modified D-bus Cycle is initiated by
the IOCM. As previously stated, this results in the D ADDR signal
which selects the address input to the input multiplexer and
causes the interrupt control section to produce A SET which
resul ts in MY ADDRESS. When D DIN is asserted, the mod ul e' s
interrupting address is put on the D-bus.
At this point the processor has identified the interrupting
add res s. Th e a p pro p ria t e in t err up t s e r vic e r 0 uti n e i s the n
executed. If now the processor RIFs the module (reads the
interrupting data address or the corresponding COS register with
R=l in the CSR), the interrupt control section resets the COS
reg ister.
Address and Flag Selection
The four module addresses must be assigned according to the rules
stated in Chapter 4. They are selected on the module by the 8-pole
s wi tc h , E 41 ( Fig u r e 6 - 9 - 2). To i 11 us t rat e the use 0 f t his s wi tc h

6-9-3

an example of one possible address selection is shown in Figure
6-9-3. Interrupt enable selection for any or all of the 16 module
inputs is provided by switches located at Ell and E12, for the low
and hig h bytes, r espec ti vel y. The reI ationshi p 0 f field sig nal
numbers to switch numbers is shown in Figure 6-9-2.

A1
B1
C1

50.49

A
INTERRUPT
ENABLE

(--"
Jl

E12

!ON 11111 wfl liON 11 II" [fl IEll V1
~F t ~ .OFF t
~ Al
10

2,1

H BYTE

Ell

L BYTE

E 41
)

o
MA-4738

Figure 6-9-2

M5031 16-Bit Isolated COS Input

6-9-4

2345678

-SWITCH NO.
_ 1 = SWITCH ON
a = SWITCH OFF

E41

-BIT NO.
AD DRESS SE LECTE D
5 2 - IS OCTAL 254
4

'---:-~---'--y-I--:-'~'--_-~.~'::':::I:-L----~--:----I
NOT
USED

MA-4789

Figure 6-9-3

Address Selection Swi tch

Address Format
The module's four data addresses, as determined by the
significant bits of the address word, are as follows.

Data (Octal)

0
0
1
1

0
1
0
1

Field 00-07
Field 10-17
COS r eg i s t e r 00-07
COS reg ister 10-1 7

two

least

Generic Code
The generic code for the M5031 module is octal 124.
Pin Connections
The M5031 pin connections
shown in Table 6-9-1.

for

Jl,

6-9-5

the

I/O

cable

connector,

are

Table 6-9-1
Module I/O
Connector
Pin
1
3
5

7
9

13
15
17"
19

21
23
25
27
29

Module M5031 I/O Pin Connections
Module I/O
Connector
Pin

Field
I/O

00+
01+
02+
03+
04+

4
6
8

05+
06+
07+

12
14
16
18
20

Not
Used

32
34
36
38
40

33 ...

41
43
45

47
49

0001020304050607-

24
26
28
30

31
35
37

Field
I/O

10+
11+
12+
13+
14+
15+
16+
17+

42
44
46
48

6-9-6

Not
Used

1011121314151617-

SPECIFICATIONS
Power Requirements
Vol tage

Operating current

Main supply: VS = 12 Vdc + 2 Vdc
Backup supply: 14 Vdc > vB >
(VS-0.7) Vdc
57 mA max imum

NOTE
If the backup supply is implemented,
total operating current is shared
Main supply: 23 mA maximum
Backup supply: 34 mA maximum
Standby current
(bac kup supp1 y)
Input Characteristics
Differential input voltage

34 mA max imum

55 V maximum

Logic zero threshold

4.1 V typical
1.6 V minimum

Logic one threshold

4.65 V typical
7. 5 V max imum

Hysteresis

0.55 V typical

Isolation voltage
(between inputs or from
inputs to ground)

1000 V max imum

Common mode source

200 VA maximum, for UL approval

Input currents

When input = +12 V differential
3 rnA typical
When input = +55 V differential
2 0 • 5 mA ma x i mum
When input = -12 V differential
0.05 microamp typical
50 microamp maximum

Propagation delay
Physical Characteristics
Dimensions
Field connector

2 .. 5 ms typical
6.2 IDS max imum
Quad module,
inch length

double

width,

Cable type BC40A or
supplied, 50-pin Berg

6-9-7

8-1/2

customer-

NOTE
Two a-posi tion jumper strips are
provided with the BC40A screw
terminal assembly. These allow the
user to connect the plus or minus
inputs
together,
in
a-input
groups, to facilitate field wiring
when a common field power source
is used.
Envi ronulental
CharactE~r istics

Heat dissipation

Complies with DEC STD 102 Class C.
Operates in convection cooled
environment up to 60 degrees C
ambient
I • 0 6 Bt u/ h r max i murn d u. e tom od u I e
circuitry
63 Btu/hr
inputs

6-9-8

maximum

due

field

M6fl1lfll
32-BIT DC OUTPUT MODULE
FUNCTIONAL DESCRIPTION
The M6010 module provides 32 program-controlled dc outputs. These
outputs are single-wire, nonisolated, open-collector, Darlingto'n
switches used for controlling relays, solenoid valves, indicators,
heaters, etc. Provision is made for reading the module's output
status or generic code and for disabling all outputs. The module
also features a common output fuse and address selection switches.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-10-1 shows that processor
output data entering through the D-bus interface connector i,s
addressed and controlled by signals from the D-bus and output to
the field through JI. The sequence of control and data flow is as
follows.
Data Paths
Data lines D(0-7)
from the D-bus interface connector provide
identica I inputs to all four data output reg i sters. One 0 f the
registers, as determined by the A0 and Al signals, accepts a new
data byte when DO CLOCK is asserted. The other three registers
remain unchanged. From the output registers the data lines go
through the output inhibi t gates to the output swi tches. These
gates inhibit all outputs when the DBIT is asserted. The on or off
status of the individual output switches is determined by whiqh
data bits are asserted~
The output circuits are Darlington switches which can turn on or
off a variety of dc circuits. Each of these switches is protected
from field overvoltages by a zener diode across its output. The
common side of all output switches is returned to ground through a
common fuse which protects the module from common mode vol tag e
differences between the field power supplies and the module.
The output data lines also go to the input multiplexer where one
of the output bytes, as determined by the A0 and Al signals, can
be selected for process monitoring by performing a DATAl on its
address. If the GBIT in the CSR of the IOCM is asserted, tl)e
module's ident i ty code is read instead 0 f an output byte. The
selected input is then gated onto the D-bus by the DI GATE signal.
The TBIT signal is not implemented on this module.
Data Control Signals
Control signals for the above mentioned data paths are initiated
by the program, resulting in the following sequence of operation.
When the program calls for an operation requiring a DATAO to one
of the module's four addresses, the IOCM starts a D-bus Cycle and
causes the address to be put on the D-bus. The module's address
decoder decodes the address, and after a short delay for
deskewing, D SYNC is asserted. This causes the module to produce
its internal MY ADDRESS signal as well as the A0 and Al signals
for the selection of the correct data byte. After a short delay, D

6-10-1

FI ELD OUTPUT
CONNECTOR

OUTPUT
SWITCHES

D OBIT

~~O
00(0·7)

DATA
R EGI STE RS

I-----..L-..I--'-...L-.II'\
/.:;~-.

--+..

\".
-->1 I

o GBIT

DO
CLOCK

AO A1

-T - i - ---I

.,-:.~ ,
"'I"

t
I

I
I

~-h
J
.'> ,.', I
~..

Z
Z

a:
w

I
I ___
I _ -I' _ .I
L

c-'

I
37

I----~--~~--~COM

::::>

III

AO A1

01
GATE

D AOOR

DO
CLOCK

ADDRESS

-r CONTROL

t--D~SY_N_C_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

1----.--1

.0 DIN

o OOUT
I----~------------------------------------------~.
MA-0222

Figure 6-10-1
M6010 32-Bit DC Output Module,
Simplified Block Diagram
DOUT is asserted and ANDed with MY ADDRESS to produce DO CLOCK,
which strobes the new data byte into the output register. From
there it goes to the output gating, output swi tches, and to JI,
the field output connector. DO CLOCK also produces the D RPLY
signal, ,,.,hich informs the processor that the data byte has been
accepted for output. The processor then negates D DOUT, which
negates DO CLOCK.
The status of the output data remains unchanged unless the program
outputs 1:0 that address. If the program wants to read back the
contents of an output register, it causes the processor to execute
a DATAl on t hat add res s. Wh e nth i s i s done, the pro c e s s 0 r fir s t
asserts the address as before and causes the IOCM to start aD-bus
Cycle. This causes the add ress to be put on the D-bus a.nd decoded

6-10-2

by the module's address comparator. Then, D SYNC is asserted after
a short delay for deskewing. This results in the A0 and Al signals
for selecting the proper byte and also the MY ADDRESS signal.
However, in this case, the next signal asserted by the IOCM is D
DIN, which is ANDed with MY ADDRESS to produce DI GATE. This
signal strobes the contents of the G multiplexer onto the D-bus.
I f the prog r am has set the GB IT in the CSR 0 f the I OCM, the G
multiplexer contains the module's identity code instead of the
selected data byte. DI GATE also produces D RPLY after a short
delay to notify the processor that data is on the D-bus. When data
is received by the processor, D DIN is negated causing DI GATE to
negate and remove data from the D-bus.
Address Selection
The four module addresses must be assigned according to the rules
stated in Chapter 4. They are selected on the module by the 8-pole
s wit c h , E 3 4 ( Fig u r e 6 -1 0 - 2). An e x am pI e 0 f 0 n e po s sib 1 e add res s
selection is shown in Figure 6-10-3 to illustrate the use of this
switch.
Generic Code
The generic code for the M60l0 module is octal 041.
Pin Connections
The M60l0 module pin connections are shown in Table 6-10-1 for Jl,
the I/O cable connector.
SPECIFICATIONS
Power Requirements
Vol tage

Operating current

Main supply: VS = 12 Vdc + 2 Vdc
Backup supply: 14 Vdc > VB > (VS-0.7)
Vdc
89.6 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 9.2 mA maximum
Backup supply: 89.4 rnA maximum
Standby current
(backup suppl y)
Output Characteristics
Maximum ratings

3.9 rnA maximum

positive output voltage
Negative output voltage
Low voltage output
Off leakage current
Sink current

6-10-3

+55 V
-0.6 V
+1.4 V
20 microamp
250 rnA per
bit
8 A per
module

50. 49

2. 1

I F1

[
A1

ADDR
SEL

o
IvlA·0187

Figure 6-10-2

M6010 32-Bit DC Output

6-10-4

-SWITCH NO.
_ 1 =SWITCH ON
Q=SWITCH OFF

E34

Q
1 2 3
4
5 6
7
-BIT NO.
Ioooo-_~---'-v-'-\:':::~T;::==J-'-y---J-----'

NOT
USED

5 2 _ A D D R E S S SELECTED
IS OCTAL 254
MA-0175

Figure 6-10-3
Table 6-10-1
Module
I/O
Connector
Pin

Address Selection Switch

Module M6019 I/O Pin Connections

Field
I/O

Module
I/O
Connector
Pin

Field
I/O

1
3
5
7
9

00
02
04
06
10

2
4
6
8
10

01
03
05
07
11

11
13
16
17
19

12
14
16
Common

12
14
16
18
20

13
15
17
Common

21
23
25
27
29

22
24
26
28
30

31
33
35
37
39

"
Common
20
22
24

32
34
36
38
40

v
Common
21
23
25

41
43
45
47
49

26
30
32
34
36

42
44
46
48
50

27
31
33
35
37

6-10-5

Output Timing
Maximum Times (microseconds)

- 10K

Vout = 12 V, RL

Vout

= 55 V, RL = 3.5K

Propagation
Time

Transition
Time

Propagation
Time

Transition
Time

Turn-on

0.8

0.05

0.8

0.05

Turn-off

3.6

3.9

1.8

2.4

NOTE
propagation time is referenced to the
point where the activating signal enters
the module.
Protection

Physical Characteristics
Dimensions
Field connector
Environmntal
Characteristics

Heat dissipation

Output circuits are protected from
field overvoltage conditions by a
zener diode across each output.
Common mode protect ion is prov ided
by a 1 A picofuse in series with the
dc return.

Quad module,
inch length

triple

width,

Cable
type
BC40A
or
supplied, 50-pin Berg

8-1/2

customer-

Complies with DEC STD 102 Class C.
Op era t e s i n
con v e c t ion
coole d
env ironment up to 60 deg rees C
ambient
4.52 Btu/hr maximum due to module
circuitry;
3 7 • 0 Bt u/ h r ma x im urn d u E~ to fie 1 d
power so urce

6-10-6

M6010-YA
32-BIT TTL COMPATIBLE OUTPUT MODULE
FUNCTIONAL DESCRIPTION
The M60l0-YA module provides 32 TTL-compatible, program-controlled
dc
outputs.
These
outputs
are
single-wire,
nonisolated,
open-collector switches used primarily to provide TTL logic levels
or to drive low power relays. Provision is made for reading the
module's output status or generic code and for disabling all
outputs. The module also features a common output fuse and address
selection switches.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-11-1 shows the data flow
from the D-bus through the module and to the field output
connector.
Data Paths
Data line? D(0-7)
from the D-bus interface connector provide
identical inputs to all four data output reg i sters • One 0 f the
registers, as determined by the A0 and Al signals, accepts a new
data byte when DO CLOCK is asserted. The other three registers
remain unchanged. From the output reg isters the data I ines go
through the output inhibit gates to the output switches. These
gates inhibit all outputs when the DBIT is asserted. The on or off
status 0 f the ind iv id ual 0 utput swi tches is determ ined by which
data bits are asserted.
The output circuits are open-collector switches that can be used
to drive TTL logic or a variety of other low power dc circuits.
Ea ch 0 f these swi tches is protected from field overvol tag es by a
zener diode
ac ross its output. The common side 0 f all output
switches is returned to ground through a common fuse that protects
the module from common mode voltage differences between the field
power supplies and the module.
The output data lines also go to the input multiplexer where one
of the output bytes, as determined by the A0 and Al signals, cah
be selected for process monitoring by performing a DATAl on its
address. If the GBIT in the CSR of the IOCM is asserted, the
mod u 1 e' s i d en tit Y cod e i s read ins tea d 0 fan 0 u t put b yt e • Th e
selected input is then gated onto the D-bus by the DI GATE signal.
The TBIT signal is not implemented on this module.

6-11'-1

FIE LD OUTPUT
CONNECTOR

OUTPUT
SWITCHES

1 o-OBIT
---------------------------

o D(0-7)

/.:;~--=~--~
\
I

__ +...

\.I"a.

.... ->1

'7.
~t'

a::

o
t;

CLOCK

IL ____ ..... _-,I

.....

AO A1

I
I

~? "SO

w
Z
Z

ou
w

«
u..
a::
w

z
(/)

::>
ID

AO A1
D1
D ADDR

GATE

D SYNC

D DIN

o DOUT

I---~:....;....---------------------------------_L~

D RPLY
MA-0222A

Figure 6-11-1
M6010-YA 32-Bit TTL-Compatible
Output Module, Block Diagram

6-11-2

Data Control Signals
Control signals for the previously mentioned data paths are
initiated by the program, resulting in the following sequence of
operation. When the program calls for an operation requiring a
DATAO to one of the module's four addresses, the IOCM starts a
D-bus Cycle and causes the address to be put on the D-bus. The
module's address decoder decodes the address, and after a short
delay for deskewing, D SYNC is asserted. This causes the module to
produce its internal MY ADDRESS signal, as well as the A0 and Al
signals for the selection of the correct data byte. After a short
delay, D DOUT is asserted and ANDed with MY ADDRESS to produce DO
CLOCK, which strobes the new data byte into the output register.
From there it goes to the output gating, output switches, and to
Jl, the field output connector. DO CLOCK also produces the D RPLY
signal, which informs the processor that the data byte has been
accepted fo r output. The processo r then neg ates D DOUT, wh ich
negates DO CLOCK.
The status of the output data remains unchanged unless the program
outputs to that address. If the progr am wants to read back the
contents of an output register, it causes the processor to execut~
a DATA Ion t ha tad d res s. Wh e nth i s i s don e, the pro c e s so r fir s t
asserts the address as before and cause the IOCM to start aD-bus
Cycle. This causes the address to be put on the D-bus and be
decoded by the module's address comparator. Then D SYNC is
asserted after a short delay for deskewing. This results in the A0
and Al signals for selecting the proper byte and also the MY
ADDRESS signal. However, in this case, the next signal asserted by
the IOCM is D DIN, which is ANDed with MY ADDRESS to produce DI
GATE. This signal strobes the contents of the G multiplexer onto
the D-bus. If the program has set the GBIT in the CSR of the IOCM,
the G multiplexer contains the module's identity code instead of
the selected data byte. DI GATE also produces D RPLY after a short
delay to notify the processor that data is on the D-bus. When data
is received by the processor, D DIN is negated causing DI GATE to
negate and remove data from the D-bus.
Address Selection
The four module addresses must be assigned according to the rules
stated in Chapter 4. They are selected on the module by the 8-pole
s wi tc h , E 3 4 ( Fig u r e 6 -11- 2). An e x am pI e 0 f 0 n e po s sib 1 e ad d res s
selection is shown in Figure 6-11-3 to illustrate the use of the
switch.
Generic Code
The generic code for the M6010-YA module is octal 043.

6-11-3

131

50. 49

V 1

[
A1

2. 1

IF1

'11

ADDR
SEL

o
MA-0187

Figure 6-11-2

M6010-YA 32-Bit TTL-Compatible Output Module

6-11-4

-SWITCH NO.
_ 1 =SWITCH ON
O=SWITCH OFF
E34

NOT
USED

'---~---'-v-'-\---T--,-\...--.....-,----.1----1

..-

BIT NO.
ADD RESS SELECTE D

5 2 - IS OCTAL 254
MA-0175

Figure 6-11-3

M60l0-YA Address Selection Example

Pin Connections
The M60l0-YA module pin connections are shown in Table 6-11-1 for
Jl, the I/O cable connector.
APPLICATION INFORMATION
Field connections for the M60l0-YA module may be implemented with
the BC40A screw terminal assembly. Connections are identical tq
those for the M60l0 module 1 isted in Chapter 3, Table 3-2. The
user's load must provide pull-up resistors to the supply voltage
(+5 V for TTL applications) • A typical field interface using screw
terminals is shown in Figure 6-11-4.
SPECIFICATIONS
Power requirements
Vol tag e

Operating current

Main supply: VS = 12 Vdc + 2 Vdc
Backup supply: 14 Vdc > vB>
(VS - 0. 7) Vdc
177 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 1 mA maximum
Backup supply: 176 rnA maximum
Standby current
(backup supply)

4 rnA max imum

6-11-5

Table 6-11-1
Module
I/O
Connector
Pin

Module M6010-YA I/O Pin Connections

Field
I/O

Module
I/O
Connector
Pin

Field
I/O

1
3
5
7
9

00
02
04
06
10

2
4
6
8
10

01
03
05
07
11

11
13
15
17
19

12
14
16
Common

12
14
16
18
20

13
15
17
Common

21
23
25
27
29

22
24
26
28
30
,I

31
33
35
37
39

Common
20
22
24

32
34
36
38
40

"
Common
21
23
25

41
43
45
47
49

26
30
32
34
36

42
44
46
48
50

27
31
33
35
37

6-11-6

---

M6010-YA
+5V

J-l

~
+5 V

• CUSTOMER PROVIDED

Figure 6-11-4

MA-217B

M60l0-YA Typical TTL Field Interface

Output Characteristics
Max imum rating s

High level output voltage: +5 V +5
percent for TTL loads; +55 V for
non-TTL loads
Low level output voltage: +0.4 V
High level
microamp

leakage

current:

Sink current: 64 rnA per bit (40 TTL
unit loads)
Output timing
Maximum Times (ns)
Vout = 5 V, RL = 78 ohms

Vout

Transition

Propagation
Time

Transition
Time

Propagation Transition
Time
Time

Zero to one
One to zero

250
1400

30
240

300
1600

6-11-7

= 55 V, RL 860 ohms

50
330

NOTE
Propagation time is referenced to the
point where the activating signal enters
the module.
Protection

Physical Characteristics
Dimensions
Field connector
Environmental
Characb~r i st ics

Heat dissipation

Output circuits are protected from
field overvoltage conditions by a 62
V zen e r d i 0 de a c r 0 S S E~ a c h 0 u t put.
Note that this diode will not
protect a TTL load, which normally
has a max imum input vol tage rating
of +5.5 V. Common mode protection is
provided by a 1 A Picofuse in series
with the dc return.
Quad module,
inch length

double

width,

Cable
type
BC40A or
supplied, 50-pin Berg

8-1/2

customer-

Complies with DEC STD 102 Class C.
Operates
in
convection
cooled
environment up to 60 degrees C
ambient
8 • 4 Bt u/ h r max i mum due to modul e
c i r cui t s ; 2. 7 Bt u/ h r ma>~ i mum due to
field power source

6-11-8

M6~11

16-BIT ONE SHOT OUTPUT
FUNCTIONAL DESCRIPTION
The M60ll module provides 16 program-controlled dc outputs. These
outputs are nonisolated, single wire, one shot, open collector,
Darlington switches used for operating devices that must be
activated for only a short duration, such as relays, solenoid
valves, etc. Output timing is selectable from 100 microseconds to
5 seconds on a per-byte basis via switches located on the module.
Provision is made for reading the module's output status or
generic code and for disabling all outputs. The module also
features a common output fuse and switches for address selection.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-12-1 shows that processor
output data enter i ng thro ugh the D-bus inter face connecto r is
addressed and controlled by signals from the D-bus and output to
the field through Jl. The sequence of control and data flow is as
follows.
Data Paths
The eight data lines D(0-7) entering at the D-bus interface
connector go to both the address comparator and to the data out
latches. Data is strobed into one of the holding registers by the
A SET or B SET signal and held for output to the appropriate
output register. The output register is clocked by the A SHIFT or
B SHIFT signal for the high or low byte, respectively. The holding
reg ister is reset at thi s time so the outputs remain acti v e fo r
only one clock period.
The output circuits are Darlington switches which can be used to
turn a variety of dc circuits on or off. Each of these switches is
protected from field overvoltages by a zener diode across its
output. Add i tionall y, the common s ide of all output swi tches is
returned to ground through a cdmmon fuse which protects the module
from common mode voltage differences between the field power
supplies and the module.
Data from the holding registers and the output registers is ORed
and sent to the Data In mul ti plexer so that when the processo r
monitors the status of the output, it receives data corresponding
to the logical OR of these two signals. This is desirable becau$e
once data is loaded into the holding register, it remains there
until it is shifted into the output register where it remains for
a full clock period. Once started, this sequence cannot be
aborted; therefore, the output status includes the status of both
registers.
From the output reg isters, the data 1 ines go through the output
inhibi t gates to the output swi tches. These gates inhibi t a l l
outputs when the DBIT is asserted. The on or off status of the
individual output switches is determined by which data bits are
asserted. The TBIT is not implemented on this module.

6-12-1

OUTPUT
SWITCHES

II:

DO (0-71

/v~--r-I-L.I

Z
Z

-t1

,r-&. I

1'-;..

,r-.. I

.,.

I FIELD OUTPUT
I CONNECTOR
I

-~-+.t'" \ 'i' I I

...~

;.L__-r__ J_J
: II

II>

B SHIFT H

o ADDR

'-~-----r--~--~16

DO IN

100

OUT
DO BIT

o RPLY
DO BIT

o SYNC
1.2 OR 5 MULT

, . . - - - - - - - - . A SHIFT H
A SHIFT L

o SYS CLOCK

I - ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

I
I
L...J

r-,
I

L...J

ANTI
COINCIDENCE
CKTS

- - -OJ>--,-------'-'---fr - - -,1-------------- B SHIFT H
I
I
L _ _ ....Jt-----------. B SHIFT L
--0-.-BTiMER

--~

Figure 6-12-1
M6011 16-Bit One-Shot Output
Simplified Block Diagram

Data Control Signals
Control signals for the above mentioned data paths are initiated
by the program, resulting in the following sequence of operation.
When the program calls for an operation requiring a DATAO to one
of the module's two addresses, the IOCM starts a D-bus Cycle and
causes the address to be put on the D-bus. The modul e' s address
comparator decodes the address, and after a short delay for
deskewing, D SYNC is asserted. This causes the MY ADDRESS and A0
signals. After a short delay, D DOUT is asserted causing either
the A SET or B SET signal, depending on the status of A0. This
selects the proper byte for output. D DOUT also produces D RPLY,
informing the processor that data for output has been accepted
from the D-bus.
The A SHIFT and B SHIFT signals that determine the duration of the
output signal are independently adjustable via switches on the
module. Figure 6-12-1 shows how these signals are derived (f~om
the 100 kHz D SYS CLOCK with countdown circuits) and selected for
the desi red interval us ing swi tch mod ul es E40 and E34. The two
circuits, though independent, are identical and operate as
follows.
The first part of the divider circuit consists of five successive
divide-by-10 circuits that multiply the system clock period of l~
microseconds to periods of 0.1, 1, 10, 100, and 1000 ms (Figure
6-12-2). Anyone of five periods may be selected to drive the A
TIMER multiplier using one of the five switches (4 through 8) in
location E40. Similarly, the B TIMER is selected with the switches
in location E34.
The A TIMER multiplier utilizes a 3-stage counter to further
multiply the selected time period by either 1, 2, or 5, as
selected by switches 1, 2, and 3 of location E40. This provides
the 15 different clock periods listed in Table 6-12-1.
Table 6-12-1
Multiplier

1.1

xl
x2
x5

0.1
0.2
0.5

1
2
5

One Shot Timing Range

Basic Time (ms)
19
10
20
50

199
100
200
500

1000
2000
5000

Switch usage is illustrated in Figure 6-12-2. One switch (4, 5, 6,
7, or 8)
selects the basic time period. A second switch
combination (1, 2, or 3) multiplies by 1, 2, or 5.
Since the D-bus Cycle and the one-shot timing are asynchronous, it
is possible for the output to be activated just when the holding
register is being loaded, resulting in erroneous outputs. This
condition is avoided by the anticoincidence circuit (Figure

6-12-3

SWITCH
SETTINGS

0= OFF

, = ON

0.2

0.5

0
1

0
0
1

0.1

0
0

OUTPUT
TIME (msec)

SWITCH NO
4
5

100

200
500

1000

2000

5000

4
ON

8
0

SELECTED TIME =
500M SEC

OFF

~----------------------~
TIMER SELECTION SWITCH
E40(A TIMER) AND E34 (B TlMEn)
MA-0198

Figure 6-12-2

Timer Selection Switches

6-12-1). The module has two of these circuits; one for the A SHIFT
signals and one for the B SHIFT signals, for the high and low
bytes, respectively.
The A 'rIMER clock going low sets the fi rst fl ip- flop which
provides a data input for the second. The second flip-flop is
c I 0 c ke d hi g h by the A TIM ER c I 0 c k i f D SYN Cis not pre sen t. Th e
output of this second flip-flop is delayed slightly and resets
itself so that the output is a pulse (refer to timing diagram,
Figure 6-12-3). This pulse is the A SHIFT H signal that loads the
output r~~gister. The A SHIFT H signal is inverted to ·provide the A
SHIFT L signal that clears the holding register. ThE~ inversion
al so prov id es del ay so tha t the hold ing reg ister is not c I eared
until after the output register is loaded. When the output
register is clocked by the next A SHIFT H pulse, its data inputs
are all low, so the outputs are reset. Thus, the asserted outputs
for that byte have been activated for one A TIMER clock period.

6-12-4

A TIMER

SIR FF

o SYNC

A SET

A SHIFT H

m
I

......
tv
I
l.TI

A SHIFT L

HOLDING REG.
(DATA)

HOLD REG

OUTPUT REG.

OUTPUT REG

• USUAL TIMING
(A TIMER NOT COINCIDENT WITH D-BUS CYCLE)

COINCIDENT TIMING
(A TIMER GOES HIGH DURING D-BUS CYCLE)
(EXPANDED SCALE)
MA-0194

Fig ur e 6 -12-3

Anticoincidence Timing Diagram

The shift signals are disabled by the SYNC L signal which occurs
during a D-bus Cycle. Thus, the holding register can be loaded,
but the output register is not loaded until the end of the D-bus
Cycle. ~~his means the assertion of the outputs may be delayed as
long as one D-bus Cycle.
The data registers can be monitored by causing the processor to
perform a DATAl during the output interval. If this is done, the
processor will first assert the address, as before, and cause the
IOCM to start a D-bus Cycle. This causes the address to be put on
the D-bus and decoded by the module's address comparator. Then, D
SYNC is produced after a short delay for deskewing, resulting in
the A0 and MY ADDRESS signals. The A0 signal selects the proper
byte from the DATA IN MUX. This time, the next signal asserted by
the IOCM will be D DIN, which is ANDed with MY ADDRESS to produce
DI GATE. DI GATE strobes the contents of the G Mux onto the D-bus.
If the processor has set the GBIT in the CSR of thE~ IOCM, the
contents of the G multiplexer will be the module's identity code
instead of the selected data byte. DI GATE also produces D RPLY
after a short delay, to notify the processor that data is on the
D-bus. Wrhen data is received by the processor, D DIN is negated
causing DI GATE to negate and remove data from the D-bus.
Address Selection
The two addresses for the module must be assigned according to the
rules stated in Chapter 4 and are selected on the module by the
8 - po 1 e s wi tc h , E- 2 2 ( Fig u r e 6 -1 2 -4). An e x am pI e 0 f 0 n e po s sib 1 e
address selection is shown in Figure 6-12-5 to illustrate the use
of this switch.
Generic Code
The generic code for the M6011 module is octal

021~

Pin Connc~ctions
The M6011 module pin connections are shown in Table 6-12-2 for J1,
the I/O cable connector.
SPECIFIC}\TIONS
Power Requirements
Voltage

Operating current

Main supply: VS = 12 Vdc + 2 Vdc
Ba c k u p s up ply :
1 4 Vd
> VB
(VS-0.7) Vdc

7 8 • 2 rnA max i murn

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 2.3 mA maximum
Backup supply: 75.9 mA maximum
Standby current
(bac kup s uppl y)

33.7 rnA maximum

6-12-6

50.49

2. 1

I F1
ADDR SEL

I~PF_F11_11_111_11---1

E22

B TIMER

1
•
. OFF 111111111

IE~

A TIMER

ION 1
OFF

111111111

IE~
MA-0185

Figure 6-12-4

M6011 16-Bit One Shot Output

6-12-7

2345678

-SWITCH NO.
_
1 = SWITCH ON

o = SWITCH OFF
E6

01234567

____

- B I T NO.

~-----------------~'

NOT

-J~

ADDRESS SELECTED
IS OCTAL 254

USED

MA-0174

Figure 6-12-5

Table 6-12-2

Address Selection Switch

Module M6011 I/O Pin Connections
1-"

Module
I/O
Connector
Pin

Field
I/O

Module
I/O
Connector
Pin

1
3
5
7
9

00
02
04
06
10

2
4
6
8
10

01
03
05
07
11

12
14
16
Common

12
14
16
18
20

13
15
17
Common

11
13
15
17
19

21
23
25
27
29

22
24
26
28
30

31
33
35
37
39

32
34
36
38
40

Common

41
43
45
47
49

42
44
46
48
50

6--12-8

Field
I/O

,It

Common

Output Characteristics
Max imum rating s

positive output voltage:
Negative output voltage:
Low vol tag e output:
Off leakage current:
Sink current:

+55 V
-0.6 V
+1.4 V
20 micro amp
250 rnA per
bi t, 4 A
per mod ul e

Output timing
Maximum Times (microseconds)

Vout = 12 V, RL = 10K

Vout = 55 V, RL = 3.5K

Transition

Propagation
Time

Transition
Time

Propagation
Time

Transition
Time

Turn-on
Turn-off

0.8
3.6

0.05
3.9

0.8
1.8

0.05
2.4

NOTE
Propagation time is referenced to the
point where the activating signal enters
the module.
One-shot timing range

100 microseconds to 5 sec + (0.1
percen t + 5 microsecond s)
swi tchselectable on module

Protection
Output c ircui ts are protected from
field overvoltage conditions by a.
zener diode across each output.
Common mode protect ion is prov ided
by a 1 A Picofuse in series with th~
dc return
Physical Characteristics
Dimensions
Field connector
Environmental
Characteristics

Heat dissipation

Quad module,
inch length

triple

width,

Cable
type
BC40A
or
supplied, 50-pin Berg

8-1/2

customer-

Complies with DEC STD 102 Class C.
Operates in convection cooled
environment up to 60 degrees C
ambient
3.83 Bt u/hr max imum due to mod ul e
c i r cui try; 1 8 • 5 8 Bt u/ h r max i mum due
to field power source
6-12-9

M60l2
8-BIT ISOLATED DC OUTPUT MODULE
FUNCTIONAL DESCRIPTION
The M60l2 module provides eight program-controlled dc outputs.
These outputs are isolated, three-wire, open-collector, Darlington
switches used for controlling solenoid valves, relays, indicators,
heaters, etc., where isolation from the controlled process must be
ma.intained. Provision is made for reading the module's output
status, generic code, and for disabl ing all outputs. The module
also features individual output indicators and fuses, and address
selection switches.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-13-1 shows that processor
output data entering through the D-bus interface connector is
addressed and controlled by signals from the D-bus and is output
to the field through Jl. The sequence of control and data flow is
as follows.
Data Paths
The eight data lines D(0-7) entering at the D-bus interface
connector go to both the address comparator and the data output
reg ister. The data output reg ister, controlled by the MY ADDRESS
and D DOUT signals, provides the output data to the output inhibit
gating section. The output of this section, if not disabled by the
DBIT signal, goes to the isolators and then to the eight LED
indicators and output switches. Power for everything after the
i sol a to r s i s in put from the fie 1 d t h r 0 ug h J Ion the fie 1 d c omm 0 n
lines. The TBIT is not implemented on this module.
Th e 0 u t put c i r cui t s are Da r 1 in g to n s wit c he s t ha t can be us e d t 0
turn a variety of dc circuits on or off. Each of these switches is
protected from field overvoltages by a zener diode across its
output and from inductive spikes by a diode clamp to the plus
field supply. Additionally, each output is protected from field
current overload conditions by a series fuse.
The state of the data output register can be read by means of the
G multiplexer, which under control of the GBIT signal, selects
either the output data or the module's identity code. This data is
then strobed onto the D-bus by the DI GATE signal.
Data Control Signals
Control signals for the above mentioned data paths are initiated
by the program, resulting in the following sequence of operation.
When the program calls for an operation requiring a DATAO to the
module, the IOCM starts a D-bus Cycle and causes the module's
address to be put on the D-bus. The module's address comparator
decodes the address, and after a short delay for deskewing, D SYNC
is asserted. This causes the module's address control section to
produce the MY ADDRESS signal which enables the data output
register. After a short delay, D DOUT is asserted to load the data
into the output register. The register outputs drive the output
6-13-1

J-l

()()

DETAILED OUTPUT CIRCUIT
Jl

,---,.------,--<1"\...<1....-,.-----+--......+-.- FIELD

II:

JI
...:>
......
:>
o

0'\

.....

w
I

u::

'~PUT

I ~I

~~--~--~------~--~~--~----~--~~-;I!

0 SYNC

o AOOR

07~

ODIN-

o
o OOUT

o RPLY
o OBIT

Figure 6-13-1

M6012 8-Bi t Is01 ated DC Output Mod u1 e

inhibi t gating, 0 utput swi tches, ind icato rs, and J 1, the output
connector. D DOUT is also ANDed with MY ADDRESS to produce D RPLY,
which informs the processor that the data has been accepted for
output. The processor then negates D DOUT.
Output data remains unchanged unless the processor outputs a new
da ta byte to tha t address. If the progr am wants to moni tor that
data, it causes the processor to perform a DATAl on that address.
When this is done, the processor first asserts the address a'S
before and causes the IOCM to start a D-bus Cycle. This causes tne
address to be put on the D-bus and to be decoded by the mod ul e's
address comparator. Then D SYNC is asserted after a short delay
for deskewing, resulting in the MY ADDRESS signal. However, i'n
this case, the next signal asserted by the IOCM is D DIN, which Ls
ANDed with MY ADDRESS to produce DI GATE. This signal strobes the
contents of the G multiplexer onto the D-bus. If the program has
set the GBIT in the CSR of the 10CM, the G multiplexer contain.s
the module~ s identity code instead of output data. DI GATE also
produces D RPLY after a short delay to notify the processor that
data is on the D-bus. When data is received by the processor, D
DIN is negated, causing DI GATE to negate and remove data from the
D-bus.
Address Selection
The single module address must be assigned according to the rules
stated in Chapter 4. It is selected on the module by the 8-pole
switch, E20 (Figure 6-13-2). An example of one possible addres'S
selection is shown in Figure 6-13-3 to illustrate the use of this
switch.
Generic Code
The generic code for the M60l2 module is octal 001.
Pin Connections
The M60l2 module pin connections for Jl,
are shown in Table 6-13-1.

the

I/O cable connector

SPECIFICATIONS
Power Requirements
Vol tage

Operating current

Main supply: VS = 12 Vdc + 2 Vdc
Ba c k u p s up ply:
1 4 Vde>
VB
(VS-0. 7) Vdc
202 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 1.4 mA maximum
Backup supply: 2~~ mA maximum
Standby current
(bac kup suppl y)

2.3 rnA max imum

6-13-3

50,49

J 1

2,1

c::J
c::J
C:l
C:l
c::J
CJ
c::J
07 c::J

AD DR
SEL
ON 1

,--OFF_I_II_I
I 1_11---01 E20

V1
MA-0186

Figure 6-13-2

M6012 8-Bit Isolated DC Output

6-13-4

2346678
ON

-SWITCH NO.
_

1 = SWITCH ON

o = SWITCH OFF

E20

OFF

-BITNO.

---Vy---"~--~y--_'~

ADDRESS SELECTED
IS OCTAL 254
MA·Ol72

Figure 6-13-3
Table 6-13-1
Module
I/O
Connector
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

Address Selection Switch

Module M6012 I/O Pin Connections
Module
I/O
Connector
Pin

Field
I/O
0

2
4
6
8
10

1
2

12
14
16
18
20

3
4
5

22
24
26
28
30

6
7

33}

34}

Field +

36
38
40

43}

45
47
49

0
1
2
3
4
5
6
7

35
37
39

Field
I/O

Field +

44}

Field -

46
48
50

6-13-5

Field -

Output Characteristics
Max imum rating s

Positive output voltage: +55 V
Negative output voltage: -0.6 V
Low vol tag e output: +1.8 V
Off leakage current:

20 microamp

Sink current: 1 A/bit, 4

~/module

Isolation voltage: 1000 V output to
g ro und - outputs not i sol a ted from
each other
Common mode source: 200

Field power supply current:
~;6 mA/mod ul e
Output timing
Maximum Times (microseconds)

Transition
Turn-on
Turn-off

= 12 V,

= 55 V,

Propagation
Time

Transition
Time

Propagation
Time

Transition
Time

8.6
45

0.1
56

12.6
24

0.2
20

out

= 3.5K

RL = 10K

NOTE
propagation time is referenced to the
point where the activating signal enters
the module.
Protectic)n

Th e 0 u t put c i r cui t s are pro te c te d
from field overvoltage conditions by
a zener diode across each output,
and from inductive spikes by the
clam ping d i 0 d e to the fie 1 d po we r
supply.
Output
overload
protHc.tion
is
provided by a 2 A fuse ln series
with each output. This fuse protects
the module circuitry in case of a
moderate overload, but can only
protect the circuit board in the
event of a shorted load.

6-13-6

Physical Characteristics
Dimensions
Fi eld connec to r
Environmental
Characteristics

Heat dissipation

Quad module,
inch length

triple

width,

Cable
type
BC40B
or
supplied, 50-pin Berg

8-1/2

customer-

Complies with DEC STD 102 Class C.
Operates
in
convection
cooled
environment up to 60 degrees C
ambient
9.24 Btu/hr maximum due to modu1.e
c i r cui try; 2 • 0 2 Bt u/ h r max i mum due
to field power source

6-13-7

M60l3
a-BIT AC OUTPUT MODULE
FUNCTIONAL DESCRIPTION
The M60l3 module provides eight program-controlled ac outputs.
These outputs are transformer-isolated, three-wire, switches used
for controlling alarms, machinery, pumps, blowers, etc. Provision
is made for read ing the mod ul e' s output status, gener ic code, and
for disabling all outputs. The module also features individual
output indicators and fuses, and address selection switches.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-14-1 shows that processor
output da ta en ter ing thro ugh the D-bus in ter fac e connec to r i $
addressed and controlled by signals from the D-bus and is output
to the field through Jl. The sequence of control and data flow is
as follows.
Data Paths
The eight data lines D(0-7) entering at the D-bus interfac~
connector go to both the address comparator and the data output
reg ister. The data output reg ister, controlled by the MY ADDRESS
and D DOUT signals, provides data to the output inhibit gating
section. The output of this section, if not disabled by the DBIT
signal, provides output data to the output switch control
oscillators that control the eight output switches. All power and
output
lines
after
the
switch control
transformers
ar~
electrically isolated from the rest of the module. The output
switches go to JI, the output field connector.
The state of the data output register can be read by the G
multiplexer, which under control of the GBIT signal, selects
either output data or the module's identity code. This data is
then strobed onto the D-bus by the DI GATE signal. The TBIT signal
is not implemented for this module.
Data Control Signals
Control signals for the above mentioned data paths are initiateqi
by the program, resulting in the following sequence of operation.
When the program calls for an operat.ion requiring a DATAO to the
module, the IOCM starts a D-bus Cycle and causes the modul e' S
address to be put on the D-bus. The module's address comparator
decodes the address, and after a short delay for deskewing, D SYNC
is asserted. This causes the MY ADDRESS signal that enables the
data 0 utput reg i ster. After a shor t delay, D DOUT is asser ted
which strobes data out to the output inhibit gate, oscillators,
tr ans fo rmers, 0 utput swi tches, and J 1, the 0 utput connec tor. 0
DOUT is also ANDed with MY ADDRESS to produce D RPLY, which
informs the processor that the data byte has been accepted for
output. The processor then negates D DOUT.

6-14-1

01
GATE

MUX

IDENTITY
CODE

J-1

OUTPUT SWITCHES
(SIMPLIFIED REPRESENT)l,TION)
01
GATE

DATA
OUT
REG

o 0(0-7)

---l

SWITCH
CONTROL
OSCILLATORS

OUTPUT
INHIBIT
GATING

MOD
ADDR

D------.

-UU-I 1

I
I

tU
w
Z
Z

ADDR
COMP

«u..
cc

w
t-

61-----....

ADDR
CONTR

MY
ADDR

o SYNC

o ADDR

u ,

L _.J

CJ)

I r--,
I
1
1-1---= I

::::>

~I
w

r---,1---_
--I
01

L_...J

GATE

- 1

o
C

..J

u..

1--+--........,........ 29

ODIN

LINE
NEUT

o DOUT

o RPLY
o OBIT

MA-0221

Figure 6-14-1

M6013 a-Bit AC Output Module

6-14-2

Output data remains unchanged unless the processor outputs a new
da ta byte to tha t add ress. If the progr am wants to mon i tor tha t
data, it causes the processor to perform a DATAl on that address.
Whe n t h i s i s done, the pro c e s so r fir s t ass e r t s the ad d res s a s
before and causes the IOCM to start a D-bus Cycle. This causes the.
address to be put on the D-bus and decoded by the module's address:
comparator. Then D SYNC is asserted after a short delay for
deskewing, resulting in the MY ADDRESS signal. However, in thi s
case the next signal asserted by the IOCM is D DIN, which is ANDed,
with MY ADDRESS to produce DI GATE. This signal strobes the
contents of the G multiplexer onto the D-bus. If the program has
set the GBIT in the CSR of the IOCM, the G multiplexer contains,
the module's identity code instead of the output data. DI GATE;
also produces D RPLY after a short delay to notify the processor'
that data is on the D-bus. When data is received by the processor,
D DIN is negated, causing DI GATE to negate and remove data from
the D-bus.
Output Switch Operation
The processor activates any or all output switches by writing q
data word to the module's address. Any bit that is asserted has
its corresponding output ac switch activated to turn on it~
assigned field device.
A simplified schematic of one of these switches and its control
circuit is shown in Figure 6-14-2. The switch is implemented with
two SCRs (silicon contrqlled rectifiers) which become activated by
the 555 oscillator signal whenever its control bit is asserted~
When the appl ied ac field signal forward biases one 0 f the SCRs,
and its gate input is positive with respect to its cathode, tha
SCR turns on
and
remains
turned
on as long
as
it
i$
forward-biased, which is one-hal f cycle 0 f the ac field vol tage.
On alternate half cycles, the other SCR conducts to provide a
cond ucting path for an ac current.
Activity of the output switch is indicated by a LED circuit which
is also turned on by the switch. The switch is protected from
excessive current loads by a series fuse and from overvoltag~
transients by a MOV (metal oxide varistor). The fuse only protects
the circuit board (not the module components)
in event of ell
shor ted 10 ad.
WARNING
The series fuse that protects the output
circuit
is
a
special
part.
If
replacement of the fuse is necessary, it
must be replaced wi th DEC part number
12-12442. DO NOT SUBSTITUTE. Replacement
with 0 the r than the spec if i ed fuse may
result in personal injury, equipment
damage, or improper operation. A spare
fuse holder and fuse is provided on the
module to ensure that a replacement is
always conveniently available.

6-14-3

V+

FROM OI,J'r",llT _ _ _ _ _-4_ _ _ _--.:.;R~ES::.;E:...:.T_.....
RA

INHIBIT G,UE
RB

~---4-----~~-----4.-------

I
R

Ie
-=

SWITCH
CONTROL
SIGNAL

SLf

TIMER I
L-=. . . _ - . _ _ _555
_
~

- A C I.INE

MOV

~------~--~--_r--~--._---L--------~-r_-----------SWI1CH

LED

-------~-......".",....---;r-- NEUTRAL
MA·0153

Figure 6-14-2

Output Swi tch and Control Osc ill ator

6-14-4

Address Selection
The single module address must be assigned according to the rules
stated in Chapter 4. It is selected on the module by the a-pole
switch, El (Figure 6-14-3). An. example of one possible address
selection is shown in Figure 6-14-4 to illustrate the use of this
switch.

A1
B1
C1

ADDR
SEL

50.49

c:::::::J

ION 1
OFF

IIIII (III
•

J 1

c:::::J

c:::::J
B

2.1

00 c::J
F4

c:::::J

c::J

CJ
CJ
CJ

OUTPUT ACTIVITY
INDICATORS

c::J

c:=J

07c::J
C
Fe

c:::::::J

F7·

c:::::J

SPARE
FUSE

c:::::J

c:::::J
DO NOT SUBSTITUTE

MA-01a1

Figure 6-14-3

M6013 8-Bit AC Output

6-14-5

2
ON

8
0

-SWITCH NO.
_

1 = SWITCH ON

o = SWITCH OFF

OFF

2
T

Figure 6-14-4

. ----6

'L-.r---'

-BITNO.

ADDRESS SELECTED
IS OCTAL 254·
MA·0170

Address Selection Switch

Generic Code
The generic code for the M60l3 module is octal 002.
Pin Connections
The M60l3 module pin connections for Jl,
are s ho wn i n Tab 1 e 6 -14 - 1 •

6-14-6

the

I/O cable connector

Table 6-14-1
Module
I/O
Connector
Pin

Field
I/O

Module M6913 I/O Pin Connections
Module
I/O
Connector
Pin

7
9

8
2

11
13

15
17
19

10
12
14
16
18
20

2
3
4

25
27
29

26
28

32~

31""

33
35 ~

Field
ac line

34
36

37
39.

38
40 .

43
45 }

47
49

Field
I/O

Field
ac neutral

44
46 }
48
50

6-14-7

Field
ac line

Field
ac neutral

SPEC IFICJI~TIONS
Power Requi rements
Vol tag E~

Operat lng cur rent

Main supply: VS = 12 Vdc + 2 Vdc
Ba c k u p s up ply:
1 4 Vd
> VB
(VS-0. 7) Vdc

1 73 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 170 rnA maximum
Backup supply - 3 mA maximum
Standby cur ren t
(bac kup suppl y)
Output Characteristics
Li ne vol tag e

3 mA max imum

12-140 Vac @ 47-63 Hz

Operating current

38 mA min imurn
2 A max imurn per bit
8 A max im urn pe r mod ul e

Surge current

30 A rms maximum for 32 ms
Min im um tim e bet we ens u r g ,e s = 1 0
seconds

NOTE
Output will not be damaged if turned on
by overvo1tage or
dv/dt,
provided
maximum current ratings have not been
exceeded.
On-state voltage

1.3 V maximum @ 2 A

Isolation voltage

1500 Vrms from output to ground
The outputs are not isolated from
each other

No tc h vol tag e

5.4 V max imum

Turn-on time

54 microseconds maximum

Turn-off time

One-hal f 1 ine vol tag e cycl e max im um

Protection
Ov ervol tag e
Overcurrent

Metal oxide varistor (MOV)
Fuse: DEC part no. 12-12442
Do not substitute

6-14-8

Over-dissipation

Physical Characteristics
Dimensions

Flameproof resistors in circuit
where other component failure could
cause over-dissipation
Quad module,
inch length

triple

width,

8-1/2

Field connector

Cable
type
BC40B
or
supplied, 50-pin Berg

Indicators

LED i nd icators 1 ight when fi eld
circuit is on and ac voltage is
greater than 90 Vac

Env ironmental
Characteristics

Complies with DEC STD 102 Class C.
Op era t e s i n
con vee t ion
coole d
e nv i r 0 nm e n t
up to 60 d eg r e esC
ambient

Heat dissipation

customer~

7 • 5 5 Bt u/ h r max i murn due to mod ul e
c i r cui try; 34 • 3 Bt u/ h r max im urn due
to field power so urce

6-14-9

M60l4
DUAL OUTPUT coUNTER
FUNCTIONAL DESCRIPTION
The M6014 output counter provides two independent program
controlled pulse train outputs for operating synchros, stepping
switches, or other incremental devices. Pulse train frequency and
duty cycle are switch-selectable; ranges are from 10 kHz to 0.2 Hz
and from 10 to 80 percent respectively. Sign/direction and enable
outputs are also provided.
All outputs are single wire,
nonisolated, TTL compatible, open collector, high voltage
switches. Provision is made for reading the module's generic code
and for disabling all outputs. The module also features a common
output fuse and switches for address selection.
GENERAL DESCRIPTION
The M60l4 consists of two counters for controlling output pulse
train lengths, two frequency and duty cycle select circuits, and a
common generator that produces the necessary frequencies for both
outputs (Figure 6-15-1). A common isolated input allows the user
to connect his own frequency source.
DETAILED DESCRIPTION
The module consists of two printed circuit boards assembled in a
mother-daughter configuration (Figure 6-15-2). The heavy dashed
line in Figure 6-15-1 shows the module's circuits divided between
the two circuit boards. The mother board (G670) contains the
counters, data paths, and interrupt logic. The daughter board
(54-13587) contains a common frequency source, frequency and duty
cycle select circuits, output control circuits, and the output
swi tches •
The M60l4 counter s control the number 0 f pul ses prod uced by the
module's PULSE outputs. To have one of these outputs produce n
p u 1 s e s , the pro gram s imp 1 y wr i t e s t h e n urn be r n i n t o t h e
appropriate counter. This action enables the PULSE output and a
series of pulses is started. Each pulse causes the counter to
decrement; when the counter reaches zero, the pulses stop and an
in te r r upt i s g en era ted. Th e M60l4 co un te r s 0 pe rat e as 1 5 - bit down
counters and can therefore produce up to 32,767 pulses per output
word.
Mother Board
For a discussion of the mother board circuits, refer to the
section on the M5014 input co un ter, wh ich uses the same G670
mother board.

6-15-1

J31

A OUTPUT CONTROL

D SYS
CLOCK

t-II:LU

OUTPUTS

B SIGN

J31

B ENABLE
OPTICAL
ISOLATOR

B PULSE

35
39
43

'----y---J

OUTPUT
SWITCHES

+-DAUGHTER BD-MOTHER BD-

~H INTERRUPTrI BINTR
AINTR

LOGIC

AIN

ANTI-COINCIDENCE
CIRCUIT

r ~
....

~
a:

HIGH
BYTE
INPUT
BUFFER

AOVF

....

)

COUNTER

....

)

0
I-

I-

u
w

...

LOW
BYTE
OUTPUT
BUFFER

)
01
MUX

h>I

~hi
II

:::>

I---

f--- CONTROL ~

BIN

ANTI-COINCIDENCE
CIRCUIT

BOVF

I
~/

B
COUNTER

I+--

I--

I
MA·3159

Figure 6-15-1 M6014 Dual Output
Counter, Block Diagram

MOTHER BD
(G670)

DAUGHTER BD
(54-13587)

FIELD
1-------~r-CONNECTOR

~_-.!!.._ B COUNTER

FUNCTION
SWITCHES

MANUFACTURING
TEST CONNECTOR
(NOT FOR FIELD
CONNECTIONS)
A COUNTER
FUNCTION
SWITCHES

MODULE
ADDRESS
SELECT
MA-3134

Figure 6-15-2

M60l4 Co un ter Mod ul e

Daughter Board
The M60l4 counter module uses the 54-13587 daughter board which
provides two independent, program-controlled, pulse train outputs:.
Frequency and duty cycle of the outputs are preselected by the
user via switches on the module. Outputs are initiated by the
program and controlled by the counters on the mother board.
The daughter board contains a single internal frequency source
that derives 15 frequencies from the system clock for selection by
the user. An additional selection is available from an external
source so that the user has the option of providing his own
frequency (Figure 6-15-3). These selected frequencies are input to
two switch-controlled circuits that enable the user to select
different duty cycles for the A and B outputs.
The selector circuits produce the A CLOCK and B CLOCK signals.
These are input to the output control circuits which, under
control of the counters, produce the INPUT, EN, and INTR signals.
These signals, along wi th the SIGN·b':. t from the co un ter, go
through the output inhibit gates to the output switches. These
gates inhibit all outputs when the DBIT is asserted.

6-15-3

A SIGN
A CLOCK
AOVF

o SYS
CLOCK

WRO

INTERNAL
FREO
SOURCE

WRl

A SIGN

A EN
A
OUTPUT
CONTROL

r-A_A

BEN

B OVF

WR2

OUTPUT
CONTROL

WR3

B SIGN
B CLOCK

E_;_~A_LB_S~_E-+I

AIN
AINTR
OUTPUT
INHIBIT

BIN

B SIGN
B ENABLE
B PULSE

BINTR

o ABLE

J31

_ _ _

I I ~ O~~~~~S
:1::11
431J

OUTPUT
SWITCHES
MA·3158

Figure 6-15-3

Daughter Board Block Diagram

Frequency and Duty Cycle Select
The circuit that determines the frequency and duty cycle of the
PULSE output is shown in Figure 6-15-4. All frequencies (internal
and external) are input to a mul tiplexer that selects one of the
frequencies as a function of the E33-4 to E33-7 switch settings
for the A counter or E14-4 to E14-7 for the B counter. (Switches
E33-1 to E33-8 for the A counter, and E14-l to E14-8 for the B
co un te rare represen ted by swi tches 1 thro ug h 8 in Fig ure 6 -15-4.)
The selected frequency, which is ten times the final output
frequency, is input to a divide-by-ten counter. This is a fully
decoded decade counter. One of the counter's outputs is used to
set the fl ip-flop shown and a subsequent one, selected by the duty
cycle multiplexer, resets this flip-flop.
The output of the
flip-flop therefore has a duty cycle determined by the selected
mul t i pI ex e r 0 u t put. On e 0 f e ig h t po s sib 1 e d u t Y c yc 1 e s fro m 1 0
percent to 80 percent can be selected by use of switches E33-l,
E33-2, and E33-3 for the A counter, and E14-l, E14-2, and E14-3
for the B co un te r •
Note that when an external frequency is selected with switches
E33-4 to E33-7, or E14-4 to E14-7, the external frequency must be
ten times the desired output frequency, and the output duty cycle
is determined by switches E33-l, E33-2, and E33-3, or E14-l, E14-2
and E14-3. Al so note that if swi tch E33-8 or E14-8 is on, the
internal frequency and duty cycle select circuits are bypassed,
and the PULSE output is the frequency and duty cycle of the
external signal.
Assertion of the TBIT causes this circuit to
percent duty cycle test frequency.

FROM
EXTERNAL
FREQUENCY
SOURCE
FROM
INTERNAL
FREQUENCY """-_-'
SOURCE

FREQUENCY
SELECT
MUX

-+ 10

CIRCUIT

select a

2 kHz,

EXTERNAL
INTERNAL
.SELECT

DUTY
CYCLE
SELECT

CLOCK

T BIT - - - - . . 1 - - 1 - - - - - - - - - - - - - - 1

jl!1

III
1

Is
MA·3125

Figure 6-15-4

Frequency and Duty Cycle Select

6-15-5

Output Control Circuit
The output control circuit uses the counter's loading and overflow
signals to start and stop the output pulse train .. The control
circuit and output timing for the A outputs are shown in Figures
6-15-5 and 6-15-6. Operation is as follows.
The l6-bi1: data word to the counter is written in two a-bit bytes.
The high byte is written first and stored in a buffer register on
the module. When the low byte data is written, both it and the
buffered high byte data are loaded into the l6-bit counter by WR0.
A SIGN ou'r directly follows the sign bit of the high byte without
wa i t i ng for the A C L0 Ck s i g n a 1 • If the 15 - bit mag nit ud e 0 f the
co un te r is now nonzero, A OVF L goes hig h, and the fi r st 1 ead ing
edge of A CLOCK after this sets the EN flip-flop, turnin9 on the A
ENABLE output. The second leading edge of A CLOCK sets the PULSE
fl i p- flop and A OUTPUT beg ins to prod uce pul ses at the frequency
and pulse width of A CLOCK. The counter is decremented as each
pulse is produced. When the required number of pulses has been
produced, the counter will have decremented to zero and A OVF· L
again goes low. On the next leading edge of A CLOCK, the EN
fl ip- flop resets, turning off the A ENABLE 0 utput and causing an
interrupt •. As shown in Figure 6-15-6, the required number of
pulses is produced within the true
portion of A ENABLE •

.... A ENABLE

AOVF L
WRO
D
D
PULSE

W
WR1

-+ A OUTPUT

-+ A li'llTR

)--1------AC~OCK--------~----------------------------~
MA-3130

Figure 6-15-5

Output Con tro 1 (for A Co un te r)

A CLOCK

t LOAD COUNTER WITH + 3 (100003)

WR 0

ASIGN~-

---'I

A ENABLE _ _

L__

A OUTPUT
(PULSE OUT) _ _ _ _ _---'

AOVFL~
AINTR _ _ _ __
MA-3131

Fig ure 6 -15-6

Output Control Timing

6-15-6

Should the user wish to abort the output pulse train, he can do so
by writing the high byte of the counter. This resets the W
flip-flop causing the pulse train to stop at the end of the
current pulse period. In this case an interrupt is not generated
and the counter still contains data corresponding to the number of
additional pulses that would have been output had operation not
been aborted.
Software Features
The contents of the counter may be read at any time. The high byte
must always be read first. When this is done, the low byte data is
stored in a common output buffer reg ister. When the low byte is
read, it is the data in the buffer that is read. Therefore, even
tho ug h the coun ter may decrement d ur ing the time between the hig h
and low byte readings, both bytes will contain data of a single
po int in time.
When a counter is loaded, the high byte must be loaded first. This
data is no t loaded d i rectI y into the co unte r but is stored in a
common input buffer register until the low byte is loaded. At this
time, both data bytes are loaded into the counter.
Address Selection
The four module addresses must be assigned according to the rules
stated in Chapter 4. They are selected on the module by the 7-pole
switch, E61 of the mother board (Figure 6-15-2). An example of one
possible address selection is shown in Figure 6-15-7 to illustrate
the use of this switch.

[!]

I 1 I1 I 1 I I0 I 0

9
1

~8......-~...;;.6....,

[

5
5

I I 0 I I 0 I I 'I I 0 I 1 I I 1 I D 1 I DO I

E61

O'l

NOT USED ---+--IS::.':::~

DETERMINED BY 10CM ADDRESS
SELECTION AND COMMON TO ALL
MODULES IN THE I/O SUBSYSTEM

B IT NO _ _

--It ' - - - t - - - - '

BIT SELECTION - - - - - - '
0= OFF
1 =ON

SELECTED ADDRESSES
COUNTER A = 171254, 171255
COUNTER B = 171256, 171257

MA,3129

Fig ure 6 -15-7

Address Selection Example

6-15-7

Address Format
The mod Ull e' s four data add resses as determined by the
significant bits of the add ress word are as follows.
Yl

Bits

00-07

10-1 7

00-07

10-17

I
I

Table 6-15-1

least

co un ter A

coun ter B

Module M6014 I/O Pin Connections

-------

'--------~-------------

Module
I/O
Connector
Pin

two

Module
I/O
Connector
Pin

Field
I/O

---------r------------------,~----------~------------------

A SIGN OUT

2
4

Common

A ENABLE OUT
A PULSE OUT

6
8
10

Common

7
9

13
15
17
19

12
14
16
18
20

Co mon

21
23
25

26
28
30

35
37
39

32
Common
B SIGN OUT

47
49

Common
Common

B ENABLE OUT

41
43
45

Common

29
31
33

Common

B PULSE OUT

44
46
ISO HIGH LEV IN + 48
ISO LOW LEV IN + [50

- - - - - " -_ _ _ _ _ _ _ _ _ _ ------ioo., _ _ _ _ _ _ _ _ .L

Note:
Unlabeled pins are not used.

6-15-8

Common

ISO HIGH LEV IN ISO LOW LEV IN -

Gener ic Code
The generic code of the M6014 is 044.
Pin Connections
The M6014 module pin connections for J31, the I/O cable connector,
are listed in Table 6-15-1.
APPLICATION INFORMATION
Proper I/O module installation procedures are presented in Chapter
3, Paragraph 3.3.3.3. The M6014 has the following additional
requirements.
Field Connections
The module's output drivers are able to drive the same type load
as the M6010 module outputs. They are TTL compatible; the outputs
are not Darlingtons. The user's load must provide pull-up
resistors to the supply voltage (+5 V for TTL applications) •
The optional isolated input is common to both counters and may Qe
high level, 25 volts to 55 volts, or low level, 12 volts to 28
vol ts. The max imum allowable frequency at this input is 1 kHz.
Typical field interfaces for the A outputs and the isolated inpqt
are shown in Figure 6-15-8. The screw terminal configuration for
all module field connections is shown in Table 6-15-2.
Function Selector Switches
Output frequency and duty cycle are selected by use of switGh
packs E33 and E14 of the daughter board for the A and B outputs
respectively. The A and B outputs are independent from one
another; frequency and duty cycle of one may be selected without
regard to the other. The selection process can be facilitated by
referring
to
Figure 6-15-9 which summarizes the possible
sel ec tions.

6-15-9

M 601"~ MODULE
J31
OUTPUT SWITCHES ARE
NOT DAR LlNGTONS

ASIGN

ISOLATED INPUT
HIGH LEVEL +
HIGH LEVELLOW

LEVEL +

LOW LEVEL-

* POWER ~;UPPLIES AND PULL-UP

INTERFACE CABLE
(PROVIDED WITH
BC40A)

TERMINALS

USER'S DRIVER AND
TTL RECEIVERS

F'tESISTORS SUPPLIED BY USER
'* FOR MAXIMUM NOISE IMMUNITY
USE SCHMITT TRIGGER INPUTS
SUCH AS 7414
MA-3139

Fig ure 6 -15-8

M6014 Typical TTL Interface

6-15-10

Table 6-15-2
Module M6914 Field I/O Screw
Terminal Connections
Screw
Terminal
Number

Field I/O
A SIGN

OUT
Common

1
2

3
4

A ENABLE

OUT
Common

5
6
7

A PULSE

B SIGN OUT

B ENABLE

B PULSE

OUT
Common

Common
Common
OUT
Common

OUT
Common
OUT
Common

ISOLATED
{ +
HIGH LEVEL IN ISOLATED
{ +
LOW LEVEL IN
-

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

24
25
26
27
28

29
30
31
32

33
34

6-15-11

E33 OR E14 OF DAUGHTER BOARD

~ LJ
r!l\_SELECTION SHOWN
LJ
~

, - '--~

SWITCH NO.

% DUTY

SWITCH NO.

1 2 3

CYCLE

4 5 6 7 8

000
100
010
1 1 0
001
1 0 1
o1 1
111

10
20
30
40
50
60
70
80

o0 0 0 0
1 000 0
o 1 000
1 1 0 0 0
00100
1 0 1 0 0
o1 100
1 1 1 0 0
00010
1 0 0 1 0
o10 10
1 1 0 1 0
o0 1 10
1 0 1 1 0
o1 1 10
1 1 1 1 0
XXXXl

•_ _ _~J

IS 1 kHz @ 50%
DUTY CYCLE
1 = ON
0= OFF

FREQUENCY Hz
10,000
5,000
2,000
1,000
500
200
100
50
20
10

5
2
1
0.5
0.2
1/10 EXT *
EXTERNAL '*

'"'""--

• OUTPUT FREQUENCY IS 1/10 EXTERNAL INPUT FREQUENCY.
DUTY CYCLE DETERMINED BY SWITCHES 1-3 .
.. OUTPUT FREQUENCY AND DUTY CYCLE ARE THAT OF EXTERNAL INPUT.
MA-3128

Figure 6-15-9

Frequency and Duty Cycle Selectors

SPEC I FICA ~r I ON S
Power Requirements
Vol tag e

Main supply: VS
B a c k u p s up ply:

= 12 Vdc + 2 Vdc
1 4 V d c - > VB

(VS-0.7) Vdc
Operat ing cur rent

135 rnA

NOTE
If the backup supply is impl emented,
total operating current is shared.
Main supply: 115 rnA
Backup supply: 20 rnA
Standby current
(bac kup suppl y)
Isolated Input
Character l.st ics
Ma x im urn rat i ng s

20 rnA

Po sit i v e
input voltage:
+55 V
max imum
Neg at iv e
input voltage:
-55 V
max. imum
Short-term overload: Withstands
accidential connection to 117 Vac
for two (2 ) hours

6-15-12

Thresholds

Input current
At Input
+12 V differential
At Input
+25 V differential

Range 12-28 V

25-55 V

Log ic Zero:
5.2 V typical
3.3 V minimum

8 • 7 V t yp i cal
5.5 V min imum

Logic One:
5.5 V typic al
7.8 V max imum

9 • 3 V t yp i cal
1 3 • 2 V max im urn

Hysteresis:
o• 3 V t yp i cal

o • 6 V t yp i cal

5 • 0 rnA t yp i cal
1 0 • 6 rnA t yp i cal
1 2 • 0 rnA max i mum

At Input
+55 V differential
At Input
-12 V differential

1 3 • 5 rnA max im urn
50 microamp
max imum

50 microamp
max imum

0.05 microamp
typical

Isolation voltage

1000 V
200 VA for UL approval

Propag at ion delay

200 microseconds typical
350 microsecond s max imum

Nonisolated Output
Characteristics
Max imum rating s

High level output voltage:
+5 V +5 percent for TTL loads
+55 V-for non-TTL loads
Low level output voltage: +0.4 V
High level leakage current: 20
m icroamp
Sink current: 250 rnA per output

6-15-13

Output tim i ng
Maximum Times (microseconds)

v.ln = 12 V,

RL = 10K

v.ln = 55 V,

RL = 3.5 K

Transition

Propag at ion
Time

Transition
Time

Propag at ion
Time

Transition

Zero to one
one to zero

0.3
30

0.1
10

0.6
20

0.2
6

NOTE
Propagat ion time is re ferenced
source of the activating signal.
Output circuit protection

the

Th e 0 u t put c ire u its are pro t e c t' ed
from field overvoltage conditions
by a 62 V zener diode across each
output. Note that this diode does
not protect a TTL load, which
nor mall y
has
a
m ax i m urn
i n put
vol tag era t i ng 0 f + 5 • 5 V.
Common mode protection is provided
by a 1 A picofuse in ser ies wi th
the dc return.

Internal frequencies

10000, 5000, 2000, 1000, 500, 200,
100, 50, 20, 10, 5, 2, 1, 0.5, 0.2
Hz ±. 0.1 percent
Switch-selectable for each counter

Internal duty cycles

10, 20, 30, 40, 50, 60, 70, 80
percent
switch-selectable for each counter

Physical Characteristics
Two quad modules assemblE~d as a
mother-daughter combination m a k e
up the M6014 module.
Dimen s ion::;:

Quad module,
inch leng th

Field connector

Cable
type BC40A or
supplied 50 pin Berg

6-15-14

tri pIe

width,

8-1/2

customer-

Environmental
Characteristics

Complies with DEC STD 102 Class C.
Operates in convection cooled
environment up to 60 degrees C
ambient

Heat dissipation

6.5 Btu/hr
supply
4.6 Btu/hr
supp1 y

6-15-15

maximum

from

internal

maximum

from

external

M6015
16.rBIT RETENTIVE DC OUTPUT MODULE
FUNCTIONAL DESCRIPTION
The M6015 module provides sixteen program-controlled retentive de
outputs. These outputs are isolated, three wire, power FET
switches. They can be used
for controlling solenoid valves,
relays, indicators, heaters, etc., where retention of existing
output status must be maintained during a computer power failure.
Provision is made for reading the module's output registers and
g ener ic code.
DETAILED DESCRIPTION
The simplified block diagram in Figure 6-16-1 shows that processor
output data enter ing thro ugh the D-bus in ter fac e connec tor is
addressed and controlled by signals from the D-bus and is output
to the field through Jl. The sequence of control and data flow is
as follows.
Data Paths
The eight data lines D(0-7) entering at the D-bus interface
connector go to both data output registers and to an address
comparator in the I/O control section. One of the output registers
accepts new data upon assert ion 0 f either A0H or A0L. The othe r
reg ister remains unchanged. Data from the output reg isters is
applied to the. output circuits. The eight low-byte output circuits
(groups 1 and 2) accept new data upon assertion of LB STROBE. The
eight high-byte circuits (groups 3 and 4) get new data if HB
STROBE is asserted. The output circuits are connected to Jl for
output to the field. If the D BIT is asserted, LB STROBE and HB
STROBE are disabled. This allows testing of the output registers
without affecting the output circuit switches. The T BIT is not
implemented on this module.
Data Control Signals
Control signals for the above mentioned data paths are initiated
by the program, resulting in the following sequence of operation.
When the prog ram call s for an ope r at ion requi ring a DATAO to the
module, the IOCM starts a D-bus Cycle and causes the module's
address to be put on the D-bus. The module's address comparator
decodes the address, and after a short delay for deskewing, D SYNC
is asserted. This causes the module's address control section to
produce the MY ADDRESS signal which enables the data output
register. After a short delay, D DOUT is asserted to load the data
into the output register. The register outputs drive the output
circuits. After a delay, to allow for the propagation time of the
optical isolators, these circuits are strobed, and the output
switches assume their new states. D DOUT is also ANDed with MY
ADDRESS to prod uce D RPL Y, wh ich in fo rms the proce ssor tha t the
data has been accepted for output. The processor then negates D
DOUT.
Output data remains unchanged unless the processor outputs a new
data byte ·to that address. If the program wants to monitor that

6-16-1

GENERIC
CODE

DGBIT

D (0-7)

VLi'r

DI
GATE

INPUT
MUX

~
~

+\1

r-=)

D (0-7)

LB
STROBE

D (10-17)

DADDR
DDIN

TEST
POWER

I/O +12 V __

{~
2A
F6

I/O + 12V RTN

16
19

36
+7~VRj!L
3
+~L 37

I-

FlO
38
GROUP 3
Fl1 39
4 OUTPUT _----E1~
40
CIRCUITS _----E1L 41

COM 3 __

+'1

LB STROBE
HB STROBE
AOH
AOL

DDOUT

GROUP 4

---rV
HB
STROBE

+7vl V REG
4

-~ 4 OUTPUT
CIRCUITS

I) DBIT

D RPLY

Figure 6-16-1

F04
F05

J
I/O
CONTROL

9
10

COM 2

-<f"V)

ADDRESS
SELECT

AbH

DSYNC

V REG

II 2

Lo.\2~

CJ)

DATA
OUTPUT
REG

12
vi 4CIRCUITS
OUTPUT ~-m6
13
F07

::)

+7 V

_~ GROUP 2

AbL

COM 1

3
4
5
6

10
DATA
OUTPUT
REG

JV REG ~~ 1
I 1
+\1 2

FOO
GROUP 1
F01
4 OUTPUT
F02
CIRCUITS _--EQL

GATE

+7 V

J1
~

~4~
2A

~~ 44
+V

F14
F15
F16
F17

46
47
48
49

COM 4

MA-4790

M6015 Retentive DC Output Block Diagram

6-16-2

data, it causes the processor to perform a DATAl on that address.
When this is done, the processor first asserts the address as
before and causes the IOCM to start a D-bus Cycle. This causes the
address to be put on the D-bus and to be decoded by the module's
address comparator. Then D SYNC is asserted after a short delay
for deskewing, resulting in the MY ADDRESS signal. However, in
this case, the next signal asserted by the IOCM is D DIN, which is
ANDed with MY ADDRESS to produce DI GATE. This signal strobes the
contents of the input multiplexer onto the D-bus. If the program
has set the GBIT in the CSR of the IOCM, the input multiplexer
contains the module's identity code instead of the output data. DI
GATE also produces D RPLY after a short delay to notify the
processor that data is on the D-bus. When data is received by the
processor, D DIN is negated, causing DI GATE to negate and remove
data from the D-bus.
Output Circuits
The output circuits are electrically isolated from the I/O
subsystem by optical isolators. They are isolated from each other
i n g r 0 ups 0 f four. Gr 0 ups r e c e i v e th e i r po we r from up to fo ur
user-furnished power supplies in the field. Each group has eli
voltage regulator and overload protection fuse.
Each group of four output circuits contains an output reset
circuit (Figure 6-16-2). This circuit resets the group's output
latches, and turns off its output switches, whenever field power
is turned on or off, or falls below an acceptable value. This
ensures that the output latches and switches will always be in the
off
state
during
a
power-up
or
power-down
transition.
Consequen tl y, when field power is first turned on, or when it
fails and comes back up, the outputs will be all zeros until new
d a t a i s wr itt en.
Jl
3

000

OPTICAL
ISOLATOR

-0

LB STROBE

+7V-

OPTICAL
ISOLATOR

---+ C R 0

I
Fl
COM

OUTPUT
RESET
CIRCUIT
MA-4791

Figure 6-16-2

Single Output Circuit (Simplified)

6-16-3

Each of the sixteen output circuits drives a power FET switch that
can be used to turn a variety of dc circuits ON or OFIi'. Each of
these circuits is protected from field overvoltages by a zener
diode across its output.
The state of the data output registers can be read by means of the
input multiplexer. The addressed data byte is selected by the A0
signal. If the GBIT is asserted, this multiplexer will output the
module's identity code. The selected data is then strobed onto the
D-bus by the DI GATE signal.
The fused +12 V 0 utput prov ides power for
device. It is not available to the user.

field

serv ice

test

Add ress SE!1 ection
The two addresses for the module must be assigned according to the
rules sta~ted in Chapter 4 and are selected on the module by the
8 - po 1 e s wit c h , E- 6 ( Fig u r e 6 -1 6 - 3). An e x am pI e 0 f 0 n €~ po s sib I e
address sE~lection is shown in Figure 6-16-4 to illustrate the ~se
of this sviTi tch.
Generic Code
The generic code of the M6015 module is octal 022.
Pin Connections
The M6015 module pin connections are shown in Table 6-16-1 for J1,
the I/O cable connector.
I/O Connections
Field connections for the M6015 module may be implemented with the
BC40A screw terminal assembly. Switch outputs and field power
supply inputs using the BC40A are identified in Table 6-16-2.
Note that the four groups of four outputs are isolated from each
other. Separate power suppl ies must be used if this isolation is
to be maintained.

6-16-4

50, 49

~F5

SEL
E6

ION 1
OFF

A1
B1
C1

ADDR
8

1111111 II

I
V1 -

2,1

<r=r=JFl

cr=r=J
C

<r=r=J

cc=e==JF4

Vl
MA-4792

Fig ure 6 -16-3

M 601 5

1 6 -B i t

6-16-5

Re te n t i v e DC

Ou t pu t

2345678

-SWITCH NO.
_
1 = SWITCH ON
o SWITCH OFF

01234567

- B I T NO.

t '---.r---J '---y-----'''--y--J
NOT

ADDRESS SELECTED
- I S OCTAL 254

USED
MA-0174

Address Selection Switch

Figure 6-16-4

Table 6-16-1
Module
I/O
Connector
Pin

Field
I/O

+ (12-30)

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

47
49

-Common
+ (12-3~)V }

M6~15

I/O Pin Connections

Module
I/O
Connector
Pin

Gr~up
Gr~up

-Common
Not Used
+12 V Return

2
4

6
8

10
12
14
16
18
20
22

Field
I/O
+ (30-55)

No t Used
+ (30-55)

+12 V OUT

26
28
30
32

No t Used

+(30-55)

No t Used
+(30-55)

34
36
38

Gr~up

40
42

44
46

Gro~p

6-16-6

No t Used

+(12-30)
1~

12
-Common
+(12-30)
14
16
-Common

V}
V}

Gr~up
Gr-~up

Table 6-16-2

M60l5 Field I/O Screw Terminal Connections
Screw
Terminal
Number

Field I/O

Group
1

Group
2

Group
3

Group
4

+ (12-30) V
+ (30-55) V
00
01
02
03
-Common
Not Used
+ (12-30) V
+(30-55) V
04
05
06
07
-Common
+12 V Out
+12 V Return
+12 V Ret urn
+ (12-30)
+ (30-55)
10
11
12
13
-Common
Not Used
+ (12-30)
+ (30-55)
14
15
16
17
-Common

V
V

6-16-7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

APPLICATION INFORMATION
Having a retentive output capability enables the user to prevent
disruption of crucial parts of his application in the event of a
computer power failure. The M60l5 provides this capability.
NOTE
In order to use the M60l5 as a retentive
output module, the user must first
impl ement whatever c ircui t changes may
be necessary to update the system IOeM
to the revision level listed below.

IoeM
M7958
M7959
M87l9

Ci rcui t
Schematic
Rev. Level
H

A*
C

*All versions of the
without modification.

M7959

are

usable

Normal Operation
To summarize briefly, the M60l5 provides 16 retentive outputs. The
states of the output switches will remain intact during a computer
power failure, assertion of the OBIT, or initializ,3tion. The
module's output registers can be read by the computer, and these
registers contain the data that was last written to t.hem unless
there has been a computer power failure. The significance of that
data depends on what failure modes have occurred.
Power Failure Mode
When planning his system power d istr ibution, the user must take
into consideration its various failure modes and their possible
effects on his appl ication. In particular, he must. consider how
different failure modes affect the retentive feature of the M60l5.
Refer to Figure 6-16-5 and the accompanying table.
The figure shows independent power sources for each p,3rt of the
system (:L.e., PI, P2, and P3). This independence, of course,
relies on the design of the site's power distribution system. If
the design is such that one or more parts of the systc~m are not
independent (such as, PI and P2), they can fail simultaneously.
The table summarizes the possible failure combinations and their
consequences.

6-16-8

[M6015- I
COMPUTER

-- ---,
ISOLATED

OUTPUT
REG

BUS
INTERFACE

......

OUTPUT
CIRCUIT

~
I

FIELD
DEVICE

I
L _______ _ - - _ .-JI
P2

FAILURE MODES
FAIL=

CONTAINS DATA
LAST WRITTEN

P1 P2 P3

OUT REG

1 1 1
1 1
1
1
100
1 1
1
1

T
T
T
T
F
F
F
F

a
a a
aa
aaa

OUT REG
=
OUT SW OUT SW
T
T
F
F
T
T
F
F

T
T
F
F
F
F
F
F

T = TRUE
F = FALSE

Fig ure 6 -16-5

MA-4793

Power Failure Modes

Examination of the table shows the following.
1.

A computer power failure
the output switches.

will

not affect

the

status of

Any failure of the computer or output circuit power
(i .e., PI or P2) invalidates the contents of the output
registers as an indicator of the output switch state..
This is true because those failure modes result in either
the output registers being cleared or the output latches
be i ng r e se t •

As long as the module's output power (P2) does not fail,
its output switches will retain the data last written to
them.

A consequence of 3, above, is that if the module's output circuits
are i ndependen tl y powered, the i r sta te s could be retained even
when everything el se (P 1 and P3)
has failed. The user must
consider whether or not this is desirable for his system under all
conditions.

6-16-9

Field Power Wiring
To ensure reliable operation of the M60l5's retentive outputs, the
user must pay close attention to the module's output cirGuit field
power supply wiring. In particular, he must make certain that the
output impedance of the power supply is not inductive. Not taking
this precClution can result in voltage transients on these wires.
If these transients are large enough, they can cause the retentive
outputs to be reset.
To guard against this, the M60l5 has a nominal amount of bypass
capacitance on these inputs. Still, the module can be susceptible
to this type of noise if the user's power supply:!. ines are
excessively inductive. If this be the case, he can compensate by
adding additional bypass capacitance near the module.
Reading Output Switch States
If necessary, the user can monitor the states of the output
switches by connecting them to an isolated input module (i .e., an
M50l2). He will then be able to determine the status of the output
switches even if there has been a power failure.
Isolated Output Application
The M60l5 can also be used advantageously in appl ications not
requiring its retentive output feature. For example, if isolated
outputs are needed, and the current required is less than 1/4
ampere, the M60l5 can be used to provide twice as many outputs per
mod ul e as wo ul d an M6 012.
SPECIFICATIONS
Power Requirements
Vol tag e

Operating current

Main supply: VS = 12 Vdc +2 V -1 V
Ba c k u p s u p ply: 1 4 Vd c > VB >
(VS-0.7) Vdc
130 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 125 mA maximum
Backup supply: 5 mA maximum
Standby current
(bac kup suppl y)

5 mA max imum

output Characteristics
Maximum ratings
positive output voltage

+55 V max imum

Negative output voltage

-0.6 V maximum

Saturation voltage

2 V maximum at 0.25 A

6-16-10

Off leakage current

100 microamp maximum

Sin k c ur r en t

0. 25 A/bit

Isolation voltage

1000 V max imum between any output.
and ground or between groups
Group 1
Group 2
Group 3
Group 4

Common mode source

=
=
=
=

Outputs 0-3
Outputs 4-7
Outputs 10-13
Outputs 14-17

200 VA for UL approval

Field supply current
(Vin = 12-55 V)

15 rnA maximum per group of four
outputs

Field supply voltage

12-35 V or 30-55 V

Output timing
Maximum Times (Microseconds)
V.ln = 55 V,

V.ln = 12 V

RL = 220 ohms

RL = 10K

Transition

propagation
Time

Transition
Time

Propagat ion
Time

Turn-on
Turn-off

210
210

40
40

210
210

NOTE
propagat,ion time is referenced
source of the activating signal.
Output circuit protection

Transitio n
Time
20
40

the

The output c ircui ts are protected
from fi eld ove rvol tag e cond it ion s
by a 62 V zener diode across each
output
Overload protection is provided by
a 2 A picofuse in series with the
dc return (one per group 0 f four,
outputs - four per module)

Dimensions

Quad mod ul e,
inch length

Field connector

Cable type BC40A or
supplied 50 pin Berg

6-16-11

doubl e

wid th,

8-1/2

customer-

Env i ronmt~ntal
Characteristics

Heat dissipation

Complies with DEC STD 102 Class C
Operates in convection cooled
environment up to 60 degrees C
ambient
6.2 Btu/hr maximum dUE! to module
c ircui try, 273 Bt u/hr max imum due
to fi eld power so urce

6-16-12

ANALOG INPUT SUBSYSTEM - GENERAL
INTRODUCTION
The information in this section is specifically directed at analog
input subsystems using the A0l4 converter and its expansion
modules. It is not applicable to the A020 or any other converter.
High speed analog input requirements of the I/O Subsystem are
implemented with the A0l4 A/D converter. The A156 and A151
multiplexers supplement the A/D converter by providing additional
input capability. The A156 provides the same high level inputs as
those built into the AID converter. The A157 has programmable gain
and is intended for use with low level signals.
Before referring to the material on a particular module type, the
reader should understand the following discussion.
1.

Input requirements of many applications cannot be met by
the AID converter module alone because its internal
multiplexer is limited to 16 single-ended or eight
differential inputs, and is not intended for use with low
1 evel inputs.

Expansion of the subsystem to accommodate more of the
same type inputs as accepted by the AID converter modul$
is accomplished by adding A156 multiplexer modules. Up to
seven may be used per A0l4, each add ing 32 singl e-ended
or 1 6 d iff ere n t i a l i n pu t s. Th is g i v e san ex pa n s ion
capability of up to 240 single-ended or 120 differential
inputs. A mix of single-ended and differential mod¢
mod ules is al so permi ssible, but all inputs on a given
mod ul e wi 11 be the same. A swi tch on the mod ul e perm its
the user to select the desired mode.

If the subsystem is required to service low level inputs,
the A157 multiplexer may be used. This module has 16
differential mode inputs with programmable gain to accept
inputs of varying levels with the same module.

The subsystem can consist of the A0l4 A/D convertet
module by itself or supplemented by up to seven A156 or
A157 mul ti pI ex er mod ul es in any combina t ion. A full y
ex pan d e dan a log i n put s ub s Y stem i s s h 0 wn i n Fig u r e
6-17-1.

input subsystem consisting of the AID converter and
its expansion multiplexer modules is, as far as the
programmer is concerned, just one module with a number of
selectable inputs. Although the expansion multiplexer
modules interface with the D-bus, they are addressed and
controlled by the AID module, which occupies four
contiguous addresses on the D-bus.
An

6-17-1

ANALOG
INPUTS

A014 AID CONVERTER MODULE

:::>
co

_ _ _-...A/D
CONVERTER

DIGITAL
OUTPUT

MUX
SEL

L _______________ _
'7
MA-2163

Fig ure 6 -1 7-1

Analog Input Subsystem

SOFTWARE INTERFACE
General
All subsystem registers are contained in the four-byte address
space occupied by the A/D module on the D-bus. These addresses may
be anywhere in the I/O Subsystem address space (subjE!ct to the
addressinq rules in Chapter 4), but will be referred to here
simply as A(0-3). Table 6-17-1 summarizes the register byte
address assignments.

6-17-2

Table 6-17-1
Analog
Subsystem
Byte Address
Assignment
A0
Al

Read
7 1 6,5,4,3.2,1,0
,
, , , ,
Converted data
D,(0,7 ~
I
i I

0,0 0 0
,

MUX
N? .,

, ,

G~ir ,

Write

7 1 6 15 1 4,3.2,1.0

71 ~_+> ,4 13,2 ,1 ,0

.
A/D converte r
grneric codE[ ,
:+-4, ,
,

C. Data
9(~-Tl)

A/D converter
generic code

Chan
No.

Selected MUX
.
d *
grn7r~c IC ? T I
, , ,
r
Selected MUX
.
d *
gr n 7r t c I C ? T I

-1-+, 11-1 I

MUX
A3

I/O Data
Read Generic

, i ,
I

Status
TO,E,D1B

proce++r tra
-+.~+-- I I

~_.~+ess? r I tl.~. __
<

MUX
No.

.~--~-+

Chan
No.

---" . . . . ~~. . . " --~

MUX

Gja i J.n _

;;(~ GO
~~.t/I )(4 _

LLBUSY

~
L

*MUX number zero is the A/D's
same generic code as the A/D.

DONE
ERROR
TIME OUT
internal

multiplexer

and

has

the,

A/D Converter Data Register
This is a 12-bit read-only register on the AID module that
contains the results of the most recent A/D conversion. The
register is contained in the first two bytes of the module's
address space (A0 and AI) as shown below.
A/D
Byte
Address

Data Register

A0
Al
The eight LSBs, D(0-7), are in byte A0 and the four MSBs, D(8-11),
are in the first four bit positions of byte AI.
Channel Number Register
This is a 5-bit read/write register that selects a channel on one
of the input subsystem multiplexers. On a 32-channel module all
five bits are needed to select the channel. But 32-channel
operation is not always the case. For example, if the internal
multiplexer is being used in differential mode, only eight
channels can be addressed. In this case, only three of the five
bits (0-2) are used to select a channel. The other two bits (4, 5)
must be zero; if they are not, the event is detected as an error
condition and the error bit in the status register is set.
6-17-3

The channE~l number register is in the AID module's A2 address and
stores the' channel numbers as 1 isted in Table 6-1 7-2.

AID Channel Number Register

Table 6-17-2

AID
Byte
Address

Channel Number Register
7

r- - -1 ____
4
L ____
.~-

o
o

o
,

3
____

0
0
0
0

2
____

1
____

0
0
0
0

0
__0

Chan. No.

0
0
1
1

0
1
0
1

0
1
2
3

[sets error bit in AID status register if corresponding
number does not exist on the selected multiplexer.

channel

Multiplexer Number Register
This is a 3-bit read/write register that selects one of the eight
possible multiplexers of an input subsystem. The AID (internal
mul tiplexer) is always mul tip1exer number zero. Expansion modules
are e nco d e d wit h m u 1 tip 1 ex e r n urn be r son e t h r 0 ug h s eve n b y
manipulating selector switches on the multiplexer modules. The
multiplexer number register is in the AID module's A2 acldress and
stores the multiplexer number as listed in Table 6-17-3.
Table 6-17-3

Multiplexer Number Registers

AID

Byte
Address

rMultiplexer Number Register
A

7
[71 6 151

=-= =__-_j
0

Multiplexer Number

o (AID internal multiplexer)

000
001
o 1 0
011
100
1

1
2

3
4

110
111

6
7

6-17-4

Status Register
Th i s i s a 4 - bit reg is t e r th at con t a ins AI D con v e r s ion s tat us
information and is located in the AID module's A3 address byte.
Status bit functions are described in Table 6-17-4.
Table 6-17-4
AID
Byte
Address

Status Reg ister

)__-------A---------_~

[= -_ -_ -_-_ ~t. T_I_O----'_E~_D___'_I_B_I_Go__'1
..

A3
Bit
00

AID Status Register

Description
(Busy/GO)

read/wr i te

Reading this bit = 1 means an AID conversion
cycle is in progress.
Setting this bit = 1 initiates the AID
conversion cycle.

01 (DONE)
read onl y

Done bit = 1 means that an A/D conversion
cycle has been completed and data is
available.

02 (ERROR)
read onl y

Error bit = 1 indicates one of the
errors has occurred.

03 (TIME OUT)
read onl y

channel

following

A nonexistent
selected

has

been:

2•

An i 11 eg aIm ul t i pI ex erg a in ha s bee n ,
selected

A time out error exists

Time out bit = 1 indicates that the addressed,
multiplexer has failed to respond to an AID
conversion cycle within the allotted time
(approximately 10 ms after the GO bit was
se t) •

Gain Reg ister
This is a 4-bit register that contains the gain code
selected multiplexer. It is a read-write register and
accessed in the AID converter's A3 byte.

of the,
can be

The internal and A156 multiplexers always have unity gain (code
zero), but the A157 mul tiplexer can be prog rammed for other gains
by writing this register with the proper code. Writing an illegal
gain code (a code other than zero for the A156 multiplexer, for
example), will set the error bit in the status register. Gain
codes are listed in Table 6-17-5.
6-17-5

Gain Codes

Table 6-17-5
AID

Gain Register

Byte
Address
r

7
(7

0
0
0
0
1
1
1
1

0
- - -1I
41 ______

0
0
1
1
0
0
1
1

0
0
0
0
0
0
0
0

0
1
0
1
0
1
0
1

Gain
1
2
10
20
50
100
200
1000

(A156, A014, A157)

A157

The other codes have not yet been implemented.
Generic Code Registers
The generic codes are derived from a-bit read-only registers. The
AID converter and A156 multiplexer modules each have two generic
codes; one for the single-ended mode of operation, and one for the
differential mode. Only one code is enabled at a time and is a
function of the position of its mode switch.
If the GBIT is asserted when reading the A0 or Al byte address of
the analog subsystem, the AID converter module responds with its
own generic code. If the GBIT is asserted when readin<:1 the A2 or
A3 byte addresses, the subsystem responds with the generic code of
the selected multiplexer. If the selected multiplexer is number
zero (internal multiplexer) , the appropriate response is again the
generic code at the AID and all four addresses contain the same
generic Gode. The subsystem generic codes are as follows.

Module

Generic Code
Differential
Single-Ended
Mode
Mode

A014
Al56
Al57

301
322
303

321
342

Sample Program
Analog conversions are accomplished by programs similar to the
followin9. The program includes instructions for setting up the
stack, s4:!lecting a multiplexer number, channel number, and gain
code, and wr it i ng the GO bit., wh ich starts a conver s ion. The
program then waits for an interrupt. When the interrupt occurs,
and is identified as an AID interrupt, the AID handler services
the analog subsystem, reads the data, returns from the interrupt,

6-17-6

and repeats the cycle. The program's major
illustrated by the flow diagram of Figure 6-17-2.

functions

START CONV
WRITE: MUX NO,
CHAN NO,
GAIN CODE, GO BIT

--------,
". ".

~" " .....

</ OTHER ~~
"
'......MODULE / ' "

L . . - -_ _ _ _ _

YvES

I
I
--------L----MA-21S2

Figure 6-17-2

Sample Program Flow Diagram

SAMPLE AID CONVERSION PROGRAM RT-11 MACRO VM02-12 PAGE 1
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17

.TITLE SAMPLE AID CONVERSION PROGRAM
.ASECT
000000
.ENABL AMA
000000
000001
000002
000003
000004
000005
000006
000007
000234
171377
171376
171000

R0 = %0
Rl = %1
R2 = %2
R3 = %3
R4 = %4
R5 = %5
SP = %6
PC = %7
VECTOR = 234
CSR = 171377
IAR = 171376
ADADR = 171000

6-17-7

are

18
19 01000
20 01004

001000. = 1000
MOV
012706 START:
000700
MOV
012737

i700,SP

iSET UP STACK

iINTR, VECTOR
i'SET UP VECTOR

21 01012
22 01020

23 01026
24
25
26
27 01032

001070
000234
012737
000340
000236
112737
000100
171377
106427
000000

MOV

#340, VECTOR+2

MOVB

#100, CSR

; ENAB LE SUBSYSTEM
;INTR.

MTPS

'~0

; ENABLE CPU INTR.
iOTHER CODE

MUXNO, R0

iGET MUX NUMBER

28 01036

113700 STCONV: MOVB
001216
153700
BISB

CHANNO,R0

i ADD IN CHANNEL
iNUMBER

29 01042

001220
110037

MOVB

R0, ADADR+2

iMOV TO A2

MOVB

GAIN, R0

iGET GAIN

INCB
MOVB

R0
R0,ADADR+3

;SET GO BIT

30 01046
31 01052
32 01054

171002
113700
001222
105200
110037

iMOV TO A3
171003
33
34
35 01060
36 01062
37 01064
38
39 01070
40 01074
41 01100
42 01104
43 01112
44 01114
45 01120

000001

WAIT

000240
000137
001000

NOP
JMP

START

113700 INTR:
171376
042700
177400
062700
171000
152737
000004
171377
111001
142701
000030
122701
000301

MOVB

IAR,R0

iGET IAR

BIC

i177400,R0

i C LEAR HIGH BYTE

ADD

#171000,R0

;ADD OFFSET

BISB

#4,CSR

iSET G BIT

MOVB
BICB

@R0, R1
#30,R1

;GET GENERIC CODE
iMASK S/E BIT

CMPB

#301,R1

;A/D CODE?

; INTERRUPT OR OTHER
;CODE

6-17-8

46 01124
47 01126
48 01132
49
50 01132
51 01140
52 01144
53 01150
54 01152
55 01156
56
57
58
59
60 01160
61 01164

62 01172
63 01200
64 01204

001002
000137
001132

BNE
JMP

1$
ADHDLR

iNO

iYES
iOTHER I/O HANDLERS

1$
#4,CSR
142737 ADHDLR: B ICB
000004
171377
ADADR+3, Rl
113701
MOVB
171003
BITB
#4, Rl
132701
000004
BNE
ERROR
001025
BITB # 2, Rl
132701
000002
BNE
DONE
001000

iC LEAR

G BIT

iGET A3
i ERROR?

iYES
i DONE?

iYES
iOTHER CODE

105237 DONE:
171377
113737
171001
001214
042737
177760
001214
000337
001214
153737

INCB

CSR

iSET RIF BIT

MOVB

ADADR+l, BUFF

iGET HIGH BYTE,RIF

BIC

#177760,BUFF

iMASK IRRELEVANT BITS

SWAB

BUFF

iSWAP BYTES

BISB

ADADR, BUFF

iGET LOW BYTE

171000
001214
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

i PROCESS

01212

000002

RTI

01214
01216
01220
01222

000000 BUFF:
000000 MUXNO:
000000 CHANNO:
000000 GAIN:

0
0
0
0

01224

000000 ERROR:
001000.END

HALT
1000

DATA

iRETURN FROM INTERRUPT

6-17-9

Software Restrictions
1.

If a nonexistent multiplexer is addressed, internal
control circuitry prevents further subsystem response and
the processor traps. The condition is cleared by reading
the A0l4 with the RIF bit set in the IOeM, or by
initializing the D-bus.

At the completion of a conversion, the A0l4 must be read
with the RIF bit set in the IOCM before any new data is
written into the subsystem.

The channel number, multiplexer number, and gain must be
reselected before each conversion.

Analog Fi ,eld Wi ring Pr act ices
The DIGITAL 8i te Preparation Guide contains detailed information
on field wiring practices. Particular attention should be paid to
Section 1, Chapter 3 (System Ground ing); Section 2, Chapter 1
(process Connections Guide); and to the following useful
guidelines.
Avoid ing Spur ious Signals
Confirm that the computer
power lin1e (earth) ground.

power

supply ground

connected

Twisted Pair Input Lines
The effects of magnetic coupl ing on the input signals can be
reduced for di fferential inputs by twisting the signal and return
lines in the input cable.
Shielded Input Lines
The effects of electrostatic coupling on the input signals can be
red u c e d by s hie 1 din g the s i g n a 1 wi res • Th i s i s €! s p e cia 11 y
important if the instrument or transducer has high source
impedance. To prevent the shield from carrying current: and thus
developin9 ground loop voltages within the subsystem, connect it
to ground at the instrument end only.
Allowing for Input Settl ing wi th High Source Impedance
All solid-state multiplexers inject a small amount of charge into
their input lines when changing channels, causing a transient
error voltage that is discharged by the input signal's source
imped ance. The analog subsystem shares thi schar ac ter i st ic and
also injects a small charge into the selected input line at the
end 0 f each conver sion when the a uto-ze ro swi tch is turned 0 ff •
The A0l4 and A156 both allow 10 microseconds between receiving the
GO bit and accepting the input data as valid. Normally, this is
sufficient time for the input transient to settle out,. However,
more time may be need ed when the mul ti pI exer is swi tching into an
input channel with high source impedance, particularly when large
amounts of shunt capacitance exist in the interconnecting cables.
Source impedance/cable shunt capacitance products greater than 1
microsecond should be avoided whenever conversions are t:o be made

6-17-10

at maximum rate with less than one-half LSB error. This means that
cable shunt capac}g.ance igr a 1000 ohm sourc~ should not exceed
1000 pF (10 3 X 10
= 10
), that shunt cap~cltanc~ for a 100 ohm
source should not exceed 0.01 microfarad (10 X 10- = 10- 6 ), etc.
Assuming twisted pair cable capacitance of 165 pF/m (50 pF/ft),
these constraints translate into a maximum run of 6 m (20 ft) from
a 1000 ohm source, 60 m (200 ft) from a 100 ohm source, etc. These
values are consistent with good practice for avoiding noise pickup
in long cable runs. Settling errors can be eliminated by
inc rea sin g the tim e bet we e nco n v e r s ion s 0 r inc 0 r po rat in g a
software delay between channel changes and program start commands.
Physical Restr ictions
Analog subsystem signals are not carried from chassis to
1.
chassis by the D-bus cable; therefore, the A/D converter
and all of its multiplexers must reside in the same (H333
or H334) chassis.

Although a small analog subsystem may use only part of
its assigned chassis, it is recommended that the user not
utilize any of the remaining module slots for digital I/O
modules.
To do
otherwise may result
in
serious
degradation of the analog subsystem's accuracy due to
crosstalk.

A user may sometimes be willing to tolerate some degradation if it
is not detrimental to his application. Predicting the degree of
d e g r a d at ion
is
com pI i cat e d
bY
the
n um be r
0 f
po s sib I e
configurations (hardware and software). Some insight into what to
ex pect can be gained by exam in ing the following measured effec ts
of module placement on subsystem performance.
An M5013 ac input module was placed in the slot adjacent to the
A0l4. Its inputs were exercised with a switched 120 V, 60 Hz
signal while the effect of this activity on the performance of the
A014 was monitored (Figure 6-17-3). The A0l4 channel input was
configured with a 1000 ohm unbalanced source. Worst case effects.
over several minutes were recorded for this configuration. The
measurement was repeated after moving the M50l3 and its screw
terminals left to increase the spacing between the M5013 and A0l4.
Measurements were made with and without a grounded shield between.
the modules. Maximum deviations of the converted data are recorded
in Table 6-17-6. Voltage spike amplitudes in the M50l3 inputs are
several hundred volts and represent an extreme condition. Lower
level digital modules should produce less dramatic effects.

6-17-11

SCREW

CHANO
'/1 K UNBALANCE

I
I
I

120 VAC

{----~~r-------~~

M5013

A014

MA-2164

Figure 6-17-3
Table 6-17-6

Crosstalk Measurement Configuration
Crosstalk Error Measurements

Maximum Deviation of

A~14

Output (LSBs)

No. of Empty Module Slots
Spacing

No shield

+34

+13

Shiel d

+24

+13

Analog Input Subsystem Handshaking Signals
When an external multiplexer 1S selected, there are control
s ig nal s passed between the AID conv er te r and the mul ti pI exer via
the D-bus. These signals are described below.
D MUX STROBE

Ass e r ted by the AI D con v e r t ,e r to an
external
multiplexer.
Enables
the
addressed multiplexer to put da.ta on the
D-bus in response to D DIN or accept data
in response to D DOUT.

D MUX READY

Asserted by the selected multiplexer when
its analog data signal is valiCl. Negated
by the multiplexer in response to D AUTO
ZERO, when the analog auto-ze ro sig nal
ha s se ttl ed •

6-17-12

D AUTO ZERO

Asserted by the AID converter at the
beg inn i ng 0 f the auto-zero pha se 0 f the
conversion cycle. This occurs after the
internal sample and hold has acquired and
held
the
signal
data
from
the
m u 1 tip 1 ex e r • Th i s s i g n a l p 1 ace s the
preamplifier of the selected multiplexet
in the auto-zero mode.

D MUX REL

Asserted by the AID converter at the end
of the conversion cycle. Places all
subsystem multiplexers in the idle state.

D ANA ERROR

Asserted by the addressed multiplexer

if~

A nonex istent
written

channel

has

been

A nonexistent
written.

gain

has

been

This signal sets the error bit in the
converter's status register.

AID

The timing diagram of Figure 6-17-4 shows a typical sequence of
handshaking signals. The exchange begins with the D MUX STROBE
signal that is output by the AID when a multiplexer other than
zero is addressed. This occurs when the multiplexer's number is
written in the analog subsystem's A2 byte. This causes the
m u 1 tip 1 ex e r
to set its i n t ern a 1 S ELf 1 i p- flo P , s tor e the
multiplexer and channel number data, and put the selected analog
signal on the DANA SIG line of the D-bus.

r
r ~~~I....----SEL MUX (A2)

WRITE GO BIT (A3)

D MUX STROBE

D MUX READY
START CONV

D AUTO ZERO
CONV DONE

D MUX REL
RIF

MA-2165

Figure 6-17-4

Analog Subsystem Handshaking

6-17-13

The A/D outputs the D MUX STROBE signal again when the program
writes the GO bit in the subsystem's A3 byte. This time the
sel ected mul ti pI exer sets its internal GO fl i p- flop and after an
appropriate time delay (for data settling), sets its READY
flip-flop. This puts the D MUX READY signal on the D-bus. When the
A/D conv ,er ter receives th i s sig nal ,
its i nte rnal START CONV
flip-flop is set. This puts the D AUTO ZERO signal on the D-bus.
The multiplexer now puts its preamplifier in AUTO ZERO mode and
after a suitable time delay negates D MUX READY. This enables the
A/D to start conversion.
When the .~/D finishes converting, it outputs the CONV DONE signal.
This signal sets the A/D's DONE flip-flop producing the D MUX REL
signal and resetting the START CONV fl ip-flop, which terminates
the D AUTO ZERO and CONV DONE signals. D MUX RE L c:l ear s the
multiplex1er's SEL and GO flip-flops, and is itself cl,eared when
the AID data is read with the RIF bit = 1 in the CSR ..

6-17-14

A0l4
A/D CONVERTER MODULE
FUNCTIONAL DESCRIPTION
The A0l4 is a l2-bit A/D converter module used to acquire analog
field signals and convert them to digital data for transactions on
the I/O Subsystem D-bus. The module has a built-in multiplexer
that allows 16 single-ended or eight differential inputs.
Additional inputs (up to 240 single-ended or 120 differential) can
be accommodated by utili zing expansion multiplexer modules.
Provision is made for program-controlled testing and for reading
the module's generic code. The module features series fusible
resistors and clamping diodes for input overvoltage protection,
and switches for selecting the address and input mode.
GENERAL DESCRIPTION
The following discussion is based on the assumption that the
reader has read and is familiar with the material in the preceding
section, .. Analog Input Subsystem - General."
A block diagram of the A014 module is shown in Figure 6-18-1.
Analog field signals entering at J36 are converted and the results
of the conversion are stored in the A/D data register. This data
is put on the module's internal TS-Bus and then to the D-bus. The
right side of the figure shows that the A/D data register shares
the TS-Bus with several other registers. These registers contain
additional information, such as A/D status, generic codes, channel
number, and multiplexer number. This data is also output to the
D-bus under appropriate addressing and control conditions. The
relevant enabling signals are shown with each register and are
derived from the I/O control section, discussed in a later
parag raph.
Other parts of Figure 6-18-1 show the I/O data paths and the
various control sections that regulate the module's channel
selection, A/D conversion, and D-bus data transactions.
Physically
the module
consists of
a
motherboard
and
a
daughterboard as shown in Figure 6-18-2. The functionality of the
module is partitioned as shown by the heavy dashed line in Figure
6-18-1.
The remainder of this section covers the module's major
in more detail.

functions

Channel Selection
The top left of Figure 6-18-1 shows that all channels (analog
field signal s) are input to J36, the field interface connector,
and through the fus i ble resi sto rs to the internal mul ti pI exers.
The fusible resistors, along with clamping diodes, provide
protection from field overvoltage conditions.

6-18-1

FUSIBLE
RESISTORS

D ANALOG SIGNAL
PROTECTION

D Ai\ALOG GUARD

J-36
A/D
CONVERTER
FIG 6-16-6

CONVERTED DATA [0-121
....C-O-NV---DO-N-E---------,/l

~~~A

D[0-31

E CONV D L
EL4B L - - - - - l

VANALOG
FIELD
INPIJT~

FIELD INTERFACE
CONNECTOR

DAUGHTER B " MOTHER BD - CHAN NO 10-31
E DIN

CHAN N010-31
AUTD ZERO
START CONV
T81T

INTERNAL MUX EN

0'\

I
I--'

INT MUX
H4BH
D DB IT

WR CHAN NO H
AIOOI

WR GO BIT H

D TBJT

E CONV D L

D GBIT
D SYNC

EL4B CONV DL
EAD STATUS

D DIN

TIMEOUT 131

D DOUT

E CHAN/MUX NO L

AIOl[

D MUX STS L
I/O
CONTROL
FIG 6168

ERROR 121

DR PLY

AID

D ADDR
D10-31

.D R!F

STATUS

D ERROR

STATES 11-31 L
DONE 111

EDIN

D MUX STB

GO/BUSY 101

INT MUX EN

D MUX READY
D RPLY

D INTR IN

D INTR OUT

+20 V

-----lrFM------I

CONY
DONE

---.J
SYS CLK

I I' - - -

Figure 6-18-1

Module A014 AID Converter,
Block Di agram

';~~';L:::::: .+15V

D INTR OUT
D SYS CLK

R31

R41

E50

MA-2167

Figure 6-18-2

A0l4 AID Converter Module

Channel selection controls cause the multiplexers to select a
channel accord ing to the contents 0 f the channel number reg ister
and the position of the S END switch. Figure 6-18-3 shows the
detailed logic of this part of the circuit in single-ended mode.
In addition to the field signal inputs, a test multiplexer selects
one of four AID test signals. These signals are created by a
built-in test function generator and consist of a full-scale ramp
fun c t ion, a po sit i v e t est vol tag e, a neg at i v e t est vol tag e , and
ground.
Multiplexer Select
The multiplexer select circuit selects either the internal or
external multiplexer and also provides either a single-ended or
differential input to the AID converter. A simplified version of
the multiplexer select circuit in Figure 6-18-4 shows a
configuration where an external multiplexer is selected.

6-18-3

INTERNAL
AUTOZERO
MAN TST

~~EMAT

-------D-J -

T BIT

START~

CONV ~

r;;~D
ENAl

ENA2

CHANO~------~--------~
CHAN1--------r----------~

CHAN2--------~--·------~

" ' - 0 - 4 - - -.... M UX CH 0

~:>---+---- MUX CH 1

1 - 0 - 4 - - -.... MUX CH 2

CHAN 3

SEND.
MA2168

Figure 6-18-3

Channel Select Control

FROM
{
EXTERNAL
MUX
----~~~

FROM
INTERNAL
MUX

{~
:

--0--.:I

INT MUX--[>---'

:r-

+ }TO

----r-I

~ i LO I ~

AID
CONVERTER

I
I
I

I
I

I
I
I

SEND-t>-------1--L---'
MA·2'69

Figure 6-18-4

Multiplexer Select

6-18-4

AID Conversion section
The A014 AID converter accepts bipolar inputs of +10.24 V (20.48 V
peak-to-peak). It utilizes a successive approximation conversion
process and delivers a 12-bit, offset, binary-encoded output td
the AID data register (Figure 6-18-1) •
Successive Approximation Conversion Process
Successive approximation refers to the type of conversion process
ut il i zed. Th is is a process whereby the input s ig nal is exam ined
first to de term in e i f it i s greater than or less than 1 / 2 full;
scale. If greater, a one is assigned to the MSB and the value of
this bit (1/2 scale) is subtracted from the input; if less, a zero
is assigned to the MSB and the input is left as is. This
constitutes the first approximation. Whatever remains of the input
sig nal is now 1 ess than 1/2 scal e. A second compar i son is then
made to determine if the residual analog input is greater than 1/4
scale; if it is, a one is assigned to the second MSB.
These successive approximations continue for 1/8, 1/16
scale, for as many iterations as there are output bits. A floW
diagram for a typical successive approximation converter is shown
in Fig ure 6 -18-5.
Offset Binary Encoding and Resolution
This A/D converter is a 12-bit device that accepts bipolar inputs
of +10.24 V full scale. Twelve bi ts allow 4096 disc rete output
states, corresponding to 4096 input voltage levels. One of these
levels is used for 0 V. There are 4095 states remaining;;
therefore, there can be no even division between the positive and
nega t ive inputs. Zero is cons idered to be a posi t ive n umber and
the extra level is assigned to the negative inputs. Therefore,
full scale is one LSB less than minus full scale.
Since there are 4096 levels and the peak-to-peak input voltag:e
range is 20.48 V (+,10.24 V), the LSB has a weight of 20.48/4096 =
5 mV.

Without describing all 4096 I/O conditions, the situation can be
visualized by examining the abbreviated representation in Tabl;e
6-18-1.

AID Converter Circuit Operation
The AID converter accepts the analog input that has been selected
by the multiplexers and converts it to a l2-bit digital word for
input to the program.
A simplified schematic of the module's A/D section is shown in
Figure 6-18-6. The converter is basically a differential input
device that is reconfigured for single-ended operation when the
multiplexer select circuit grounds its negative input.

6-18-5

ASSERT
DONE

]

SIGNAL

'-----

MA-217ol

Figure 6-18-5

Successive Approximation,
Flow Di agr am

6-18-6

Table 6-18-1
Input
Magni tude

Input Vol tage
Nomlnal

Binary Output Code

1 LSB
2 LSB

+FS +FS -

Offset Binary Encoding

1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0

+10.2350 V >10.2325 V
+10.2300 V (10.2275, 10.2325) V

·
+FS/2 ·
·
·
+2 LSB

·
··
· V
1 1 0 0 0 0 0 0 0 0 0 0
+5.1200
·
·
·
·
1 0 0 0 0 0 0 0 0 0 1 0 +10 mV

+1 LSB
Zero
-1 LSB
-2 LSB

1
1
0
0

0
0
1
1

1
0
1
0

(Ideal)
Range

·
· 5.1225) V
(5.1175,
·
·
(7 . 5, 12.5) mV

(2.5, 7.5) mV
(-2.5, +2.5) mV
- (2.5, 7.5) mV
- (7 • 5, 12.5) mV

+5 mV

-5 mV
-10 mV

· 5.1225) V
· V -(5.1175,
-FS/2 ·
o 1 0 0 0 0 0· 0 0 0 0 0 -5.1200
·
·
·
·
·
·
·
·
-FS + 1 LSB
-10.2350 V -(10.2325, 10,2375) V
0 0 0 0 0 0 0 0 0 0 0 1
-FS

0 0 0 0 0 0 0 0 0 0 0 0

-10.2400 V <-10.2375 V

Note:
Plus full scale can not be realized (see text) .

DAC

INPUT

.±.-.-----I

~J
AID (0-71

1s3
I

SAMPLE AND
HOLD CIRCUIT

AID

SAR
AID (0-111

DATA
REG

AlD(S-lll

S T A R T - { > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JS2
:ONV

::~" - { > ____________________________________

I
I

' - - - - - - - - - - - DONE

Figure 6-18-6
A/D Converter Section,
S im pI i f i ed Ci r cui t Di ag r am
6-18-7

Op era t ion 0 f the con v e r t e r
i s the sam e for e i the r
in put
configuration and is briefly illustrated by the subsystem timing
diagram of Figure 6-18-7, which shows the AID cycle.
The timing diagram shows that as soon as the selected multiplexer
is enabled, the analog signal is sampled and continues to be
sampled until a short time after the GO bit is written. At this
po int the mul tipl exer goes int.o auto-zero mode. After another
short delay, the conversion starts. Conversion is then in progress
until the DONE bit is set, at which time the output data can be
read. Note that the AID converter output is 12 bits, so two bytes
must be read to get all the data.
The progrslm initiates the conversion cycle by writing the GO bit
in the status register. This action is asynchronous with the 100
kHz system clock, while the conversion cycle is synchronized to
the system clock. The GO bit also starts the TIME OUT delay, which
will result in a TIME OUT signal if the delay is not reset by D
MUX RDY or an internal multiplexer ready signal. If it occurs, the
TIME OUT signal sets the TIME OUT bit in the status register.

WRITE NEW MUX NO/CHAN NO (ASYNCHRONOUS)

IDLE
TIME

SIGNAL

ACQUISITION

AUTO ZERO TIME

CONVERSION
IN PROGRESS

CONVERTED
DATA READY

IDLE
TIME

TIME

MUX
ENABLED

GO/BUSY

START
CONV

DONE

RIF

[ASYNCHRONOUS[

cJ,

______________
~~I------~I--------__

_ _--.-.~,...--..---,(I'-----

--------\\c----Il-MA-2172

Figure 6-18-7

Analog Subsystem Timing

6-18-8

I/O Control Section
When the AID converter (analog subsystem) is addressed, this event
is decoded and, at D SYNC time, the SUBSYS ADDR flip-flop is set.
At the same time, the two low-order address bits (D00 f D01) are.
stored. These signals, plus the usual D-bus control signals (DIN,
DOUT, GBIT), are the major inputs to the I/O control section of
Figure 6-18-8. The figure shows that the D00 and D01 flip-flops
are decoded to produce one of the A(0-3) signals, which identifies
the particular subsystem address that is being read or written
(refer the section .. Analog Input Subsystems
General," Table.
6-17-1) .
~

007
006
005

A3otT~

004

---..

H4BH
WR CHAN
NOH

000(1)

SEL

001(1)

-. WR GO BIT H
-. E CONV 0 L

MUX

MUX REL
G BIT

-. INT MUX

INT

-u-

INT MUX

-. EL4B

~
DECODER ~
~
rO E
AO
A1

DECODER

CONV 0 L

-. EAD STATUS
-. ECHAN
MUX NO L
COMB
-.
o MUX STB L
LOGIC

A2
A3

-. o RPLY
-. STATES

,....

(1-3) L
EDIN

r+ INTMUXEL

SUBSYST
ADDR (1) L
DOUT
DIN
MA-2173

Figure 6-18-8

I/O Control

The GBIT and INTERNAL MUX signals are decoded to produce one of
the Q(1-3) signals that selects the proper generic code.
The INTERNAL MUX SEL flip-flop is written when the A2 address is;
written, provided bits (5-7) are all zero (zero is the code for
selecting the internal multiplexer).
The remainder of the I/O control section consists of combinatorial.
logic that creates the appropriate I/O control signals for each
type of data transaction. Details of this logic are shown in the
module's print set.

6-18-9

Error DetHctor
The error detection circuit sets the error bit in thE! module's
status register. Details of this circuit are shown on the module's
print set .. The following conditions cause an output from the error
detection circuit.
1.
2.
3.
4.

an EXT MUX ERROR signal
a MUX TIME OUT signal
writing an incorrect gain code
lJl7riting an incorrect channel number code.

Status Re9 ister
Th i s reg 1. s t e r pro v ide s con v e r s ion s tat us in for mat i () n t o t he
program and
initiates interrupts (Figure 6-18-1).
For an
e~cplanation of the individual status bits, refer Table 6-17-4 of
the" Analog Input Subsystem - General" section.
Interrupt Control Signals
Th ree 0 f the status reg iste r bits (DONE, ERROR, and TIO) are input
to the module's interrupt control section. When one of these bits
is set, the interrupt control section produces a FLAG signal and
if all priority conditions are met, a processor interrupt occurs
(the FLAG signal is an input to the D INTR IN, D INTR OUT
daisy-chain). When an interrupt occurs, a modified D-bus Cycle is
initiated by the IOCM. This results in the D ADDR signal, which
puts the module's address on the TS-Bus and causes the interrupt
control section to produce the A SET and SUB SYS ADDH signals.
When D DIN is asserted., the module's address is put on the D-bus.
At this point the processor has identified the interrupting
address. 'rhe appropriate interrupt routine is then executed. If
now the processor RIFs the module (reads the module's address with
R=l in thE! CSR of the IOCM), the interrupt control section resets
the status bit that produced the flag.
Address, s: END, and Manual Test Selection
The four analog subsystem addresses are selected on the AID
converter module according to the rules stated in ChaptE!r 4. They
are select.ed on the module by the 8-pole switch, E50,' shown in
Figure 6-18-2. An example of one possible address selection is
shown in Figure 6-18-9 to illustrate the use of this switch.
positions 7 and 8 are used for S END and MANUAL TEST as, shown in
the fig ure' •

6-18-10

r - - - - - - ADDRESS SELECT
1 = ON
0= OFF
S END (ON = SINGLE ENDED)
MANUAL TEST (OFF = TEST)

DETERMINED BY 10CM ADDRESS

SELECTION AND COMMON TO ALL
MODULES IN THE I/O SUBSYSTEM

~ 1 I 11 1 0 1 1 I I 0 1 1 1 0 I FoTol I 1 11 11 I
00

07
4

D
15

.II

A/D CONVERTER ADDRESS = 171254
MA·2174

Figure 6-18-9

A0l4 Module - Address, S END, and Manual Test
Selection

Generic Code
The A0l4 module may have one of two generic codes depending on the
position of the S END switch:
301 DIFFERENTIAL and 321
SINGLE-ENDED.
Pin Connections
The A0l4 module pin connections for
are shown in Table 6-18-2.

J36

the

I/O cable connector

Screw Terminal Connections
The reader should refer to Chapter 3, Paragraph 3.8.5, for general
field interface information and then to Table 6-18-3 for this
module's screw terminal configuration.
Calibration
Calibration of the A/D converter module is accomplished by means
of diagnostics included with the I/O Subsystem. Instructions for
using these diagnostics are included with the software package.
Normally the module is calibrated and ready for service when
received by the customer; however, if field adj ustment is
contemplated, the adjustments mentioned in the diagnostic (gain
and offset) are identified in Figure 6-18-2.
To ensure compliance with specifications, all test equipment used
for calibration of the A0l4 must have been accurately and recently
calibrated. In addition, personnel doing the calibration should be
familiar with aligning precision analog equip:nent. If you are not
sure of the foregoing, DO NOT ATTEMPT TO CALIBRATE THE A0l4.
Factory calibration is probably better than that which you will be
able to accomplish.
6-18-11

Table 6-18-2
Module
I/O
Connector
Pin

Module

Field
I/O

A~14

I/O Pin Connections

Module
I/O
Connector
Pin

Field
I/O

7
9

4
6
8

11
13
15
17'"
19
21
23
25 >27
29

12
14
16
18
20

22
24

Gro und

26
28

Ground

33 ....

37
39

36
38
40

43
45

42
44

47
49

46
48
50

----'----------

6-18-12

Table 6-18-3
Type A Screw Terminal 16/32 Bit (BC40A)
A014 AID Converter Module Field Termination Configuration

Field
Channel
Number
DIFF

SEND

00
01

02
03

04
05

06
07

03
Gro und
Ground
04

Screw
Terminal
Number

Gro und
Ground
10
11

12
13

14
15

16
17

6-18-13

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

SPEC IF ICA.TIONS
Powe r Requi rements
Vol tage'

Operating current

Main supply: VS = 12 Vdc (+2 or -1)
Vdc
Backup supply:
14 Vdc
> VB >
(VS - 0 • 7) Vd c
350 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 300 mA maximum
Backup supply: 50 mA maximum
Standby current
(bac kup suppl y)
Input Characteristics
Vo 1 tag e rang e

350 rnA max im urn

-10.24 V to +10.24 V,
1 LSB == 0.005 V

Input impedance

Power on: >50 M ohm
Power off: 1000 ohm

Signal and common mode
vol tag e c a pa b i 1 i t Y

+12 V minimum

Channel to channel
offset

+100 microvolt maximum

Gain

Unity

Overall accuracy

+2 LSBs @ 25 degrees C ambient
max imum
+4 LSBs from 0 degrees C to 60
~egrees C ambient, maximum

NOTE
This includes gain and offset errors
which can be adjusted to zero, leaving
nonlinearity as the only nonreducible
error.
Nonlinearity
(integral and differential)
±.1/2 LSB
range
Common mode rejection

max imum

over

temperature

100 dB minimum (de to 60 Hz with lK
source unbalance)

6-18-14

Noise

No D-bus activity
+0.15 LSB typical
Il/2 LSB maximum
D-bus activity
+0.3 LSB typical
±)/2 LSB max imum
NOTE
The above specifications refer to the
3-sigma limit of Gaussian noise. Spike
noise generated by adjacent digital I/O
mod ules may exceed these 1 imi ts by a
considerable margin. For guaranteed
operation within the noise specification
limits, digital and analog I/O should
not be implemented in the same chassis.
(See discussion in note 2 under Physical
Restr ict ions in the sect ion "Analog
Input Subsystem - General.")

Conversion speed

59 microseconds average
54 microseconds minimum
64 microseconds maximum

NOTE
There is a 10 microsecond uncertainty
due to the asynchronous relationship
between start of a conversion and the
system clock.
Bandwid th

No limitation beyond conversion
samp1 e-ho1d
is
speed. Internal
prov ided.

Protection

Input circuits are protected from
field overvo1tages by diodes to +13
V and by fusible resistors in serres
with each input. A 1 A fuse protects
the circuit board etch in the event
of circuit failure.

Physical Characteristics

Dimensions

Two quad modules assembled as a
mother-daug hter combinat ion make up
the A014 module.
Quad module,
inch length

6-18-15

triple

width,

8-1/2

Fi e1d connec to r
Env ironmE~nta1
Characteristics

Heat dissipation

Cable
type
BC40A
or
customersupplied 50-pin Berg connector
Complies with DEC STD 102 Class C.
Operates
in
convection
cooled
environment up to 60 degrees C
ambient.
15 Bt u/hr max imum

6-18-16

Al56
ANALOG MULTIPLEXER
FUNCTIONAL DESCRIPTION
The Al56 multiplexer module is used in the H333 I/O subsystem to
provide additional input channels to the AflIl4 A/D converter. The
module provides for either 32 single-ended or 16 differential
input channels. Of these modules, 7 may be used to provide up to
224 additional channels for the A0l4. The module has fusible
resistors and clamping diodes for input protection and switches
for
selecting the multiplexer number and
single-ended or
differential operating mode. Provision is made for reading th~
module's two generic codes that identify the module and it$;
operating mode.
DETAILED DESCRIPTION
The following discussion of the A156 module is based on th~
ass umpt ion that the reader is fam il i ar wi th the rna ter i al in the
preceding section, "Analog Input Subsystem - General."
A simplified block diagram of the module is shown in Figure
6-19-1. The upper portion of the figure shows the multiplexer and
preamplifier section that selects an analog field signal from Jll
and delivers it to the A014 via the D-bus. The lower part of the
figure shows the data registers, D-bus interface circuits, and the
module's major control functions. The following paragraphs contain
detailed discussions of the major sections.
Multiplexer preamplifier
The top left portion of Figure 6-19-1 shows that all channels
(analog field signals) are input to the multiplexer via Jl, the
field interface connector, and the fusible resistors. The fusibl~
resistors, along
with clamping diodes, provide protection from
field overvoltage conditions. The channel selection controls cause
the multiplexer to select a channel according to the contents of
the channel number register.
The selected channel is input to the preamplifier circuit which is
configured by the three switches preceding it to operate in either
single-ended or differential mode. For example, when sampling in
single-ended mode, switch T is open and the other two (M and S)
are closed; the opposite is true for differential mode.
When the multiplexer is selected, the SEL L switch is closed and
the preamplifier output is connected to the AID converter modul,e
via the DANA SIG and D ANA GUARD lines on the D-bus. The other
control signals for this section are provided by the channel
select and preamplifier control section. Table 6-19-1 summarizes
the operating state configurations.
Data Paths
Figure 6-19-1 shows that D-bus data input to the module is stored
i n t h e c han n e 1 and m u 1 tip 1 ex e r n urn be r r eg i s t e r s • Th e s e a r e
read-write registers that store the multiplexer and channel
6-19-1

selection data if the multiplexer data matches the setting of the
module's multiplexer number select switches. The contents of these
registers are transmitted to the output select circuit which also
r e c e i v e s t hem od ul e' s rea d - 0 n 1 y d a t a from th e g en e ric cod e and
multiple}~er
gain
registers.
This
circuit
outputs
the
mul ti pI ex er / channel number data unl ess the GB IT Lor GA IN L s ig nal
is asserted, in which case it will output information from one of
those reqisters. The selected data is input to the DI gating
section where it is strobed onto the D-bus by the LO GATE L and HI
GA TE Lsi I;J nal s .
FUSIBLE

PROTECTION

-15 V

~D~BI~T____r-----~ENA

EN B

FIELO
INTERFACE
CONNECTOR

CHANNEL
SELECT
AND
PREAMPLIFIER
CONTROL
SECTION

MI
M2
M3
SL
TL

r -_ _ _~DIO-41

015-71

r--------------------------~------~,'I

SELH-0
CLOCK H _
MUXCLR H -

D 010-7)

MUX I~O

~~~--------------------------------015-71
D SYS CLK
D SYNC
S MUX STROBE
D INIT

110

D MUX REL

CONTROL
SECTION

D AUTO ZERO

DINIT-=D
_MUX CLR H
D MUX RELD SYNC
A3~
MUXCLRH

DIOOIJ~L~WD
GO

D DOUT
D DIN
D ANA ERROR IN
D ANA ERROR OUT

MUX READY

READY

/ D ERROR OUT

D MUX S T 8 - - - - - -

D MUX READY
D RPLY

MUXCLRH-

D --------------------------------

ERRORAUTO ZEROSYS C L K - - - - - -

Figure 6-19-1

D DBIT
D T81T
D G81T

~----------------------

-----------------------------

A156 Analog Multiplexer,
Block Diagram

6-19-2

Table 6-19-1

A156 Operating States
Ci rcui t
Config uration

Mode

State
Switch
S
T

Mux
A

Sampl e time

DIFF

Auto-zero time

S END
EVEN
CHAN

Sampl e time

Auto-zero time

Sample time

Auto-zero time

SEND
ODD
CHAN

1 = on or enabled
o = off or disabled
Data Control Signals
When the program writes an external multiplexer number and channel
number to the analog subsystem's A2 address, the A/D converte(
outputs the D MUX STROBE signal causing the multiplexer to decode
its number and set its SEL flip-flop. (The SEL flip-flop is the
module's data transaction enabling flip-flop; once set, it remainS
set until D MUX REL occurs.) Thi s action causes the module to
store the mul ti pl exer number and channel number data (Fig ure
6-19-1) •
When the program writes the GO bit in the subsystem's A3 byte, the
selected module's GO bit is set. The GO flip-flop arms the READY
fl ip- flop, which sets when the nex t system clock pul se occur s ~
This causes D MUX READY to be asserted, which indicates to the A/D
converter module that the analog signal from the multiplexer will
be valid on the next system clock pulse. On this clock pulse, the
A/D accepts the analog data from the mul tiplexer and asserts D
AUTO ZERO. Assertion of D AUTO ZERO disarms the READY flip-flop,
which resets on the next system clock pulse, negating D MUX READY.
Assertion of D AUTO ZERO also places the preamplifier in the
auto-zero mode (Table 6-19-1) •
When the program reads the A2 address of the analog subsystem, the
multiplexer's I/O control section decodes the address byte, and
when D DIN occurs, produces the HI GATE Land LO GATE L signals
causing the module's multiplexer number and channel number to be
put on the D-bus. If the A3 address is read, only the GAIN Land
HI GATE L signals are produced. This puts the multiplexer gain
code on the D-bus in bit positions 4-7. (The gain code for the

6-19-3

A156 module is zero.) At the same time, the AID modull~ supplies
its status register contents in bit positions 0-3.
Reading either the A2 or A3 byte with the GBIT asserted causes the
module to place one of its generic codes on the D-bus .. The A156
has diffe!rent generic codes for single-ended and differential
modes. ThE~ MODE swi tch sel ec ts the prope r cod e. If e i the r the DB IT
or TBIT is asserted, the module is placed in the auto-zero mode.
When the ,VD module asserts the D MUX REL signal, the A156 resets
its SEL and GO fli p-flops.
Multiplexer Number and Mode Selection
Th emu 1 tip 1 ex e r n urn be r a n d 0 per a tin g mod e ( d iff e r I~ n t i a l o r
single-ended) are selected on the module by the 4-pole switch, EI
( Fig u r e 6 --1 9 - 2). An ex am pI e 0 f 0 ne po s sib 1 e mul t i pI ex e r s e 1 e c t ion
is shown in Figure 6-19-3 to illustrate the use of this switch.

--50.49

t
tillID]
ON[]]]

MUXNO.~
MODE
OFF == SEND

A1
81
C1

2.1

~O~

____________________________________
Vl~
MA·2176

Fig ur e 6 -1 9- 2

A156 Analog Multiplexer Module

6-19-4

~I- - - - - M U X NUMBER 4

SELECTED

r-"---1
1

ON~

tLLLu

BIT NO.---fII>7
MUX NO.

*0
2
3
4

!! ~
0
0
0
0
1
1

0
0

0
1

0
0

I
L..-_ _

~~~E DIFF
OFF = SEND

---SWITCH SETIINGS
1 = ON

o = OFF

* NOTE:

CODE ZERO IS USED ONL Y FOR THE AID CON·
VERTER MODULE'S INTERNAL MULTIPLEXER,
THEREFORE, THIS IS AN ILLEGAL CONFIGURATION.

MA-2156

Figure 6-19-3

Multiplexer and Mode Selection

Software Restrictions
1.

Once an A156 multiplexer has been selected, another
external mul ti plexer cannot be selected without first
doing one of the following.
a.

Starting an AID conversion

b•

Re ad i ng th e A0l 4 wit h th e RI Fbi t
the IOCM

Causing a gain or channel error condition on the A156.
mod ul e

set in th e CSR 0 f

The A156 must not be written during
causes erroneous results.

a conversion;

this

The multiplexers are released at the end of a conversion;
therefore, the multiplexer number, channel number, and
gain registers contain invalid data and must be
reprogrammed before another conversion is started.

Generic Codes
The generic code of the Al56 module is octal 322 for differential
mode and 342 for single-ended mode.

6-19-5

Pin Conne'ct ions
The A156 module pin connections for J1 the I/O cable connector are
shown in Table 6-19-2.
Module A156 I/O Pin Connections

Table 6-19-2

Module
Field I/O
I/O
Connector Channel
SEND DIFF
Pin

Module
I/O
Connector
Pin

Field I/O
Channel
SEND DIFF

1
3
5
7
9

00
02
04
06
10

+00
+01
+02
+03
+04

2
4
6
8
10

01
03
05
07
11

-00
-01
-02
-03
-04

11
13
15
17"'1
19

12
14
16

+05
+06
+07

12
14
16
18 ""I
20

13
15
17

-05
-06
-07

21
23
25 >'Common
27
29

22
24
26 >-Common
28
30

31
33 -'
35
37
39

20
22
24

+10
+11
+12

32
34..,1
36
38
40

21
23
25

-10
-11
-12

41
43
45
47
49

26
30
32
34
36

+13
+14
+15
+16
+17

42
44
46
48
50

27
31
33
35
37

-13
-14
-15
-16
-17

Screw Terminal Connections
The reader should refer to Chapter 3, Paragraph 3.8.5, for general
field interface information. The A156 uses the BC40A screw
terminal assembly. Refer to Table 6-19-3 for this module's screw
terminal configuration.

6-19-6

Table 6-19-3

Module A156 Screw Terminal Connections

BC4flJA Screw Terminal
Screw
Terminal
Number

Field Channel Number
SEND

DIFF
+

0
+

1
+

2
+

3
+

4
+

5
+

6
+

7
Common
Common
+

10
+

11
+

12
+

13
+

14
+

15
+

16
+

0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
Common
Common
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

6-19-7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

SPECIFICATIONS
All specifications refer to the A156 when used in combination with
the A0l4 AID converter.
Power Requirements
Vol tag e

Operating current
(AI 56 onl y)

Ma i n s u pp 1 Y : VS = 1 2 Vd c ( + 2 0 r - 1 )
Vdc
Backup supply:
14 Vdc
> VB >
(VS - 0 • 7) Vd c
79 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 75 mA maximum
Backup supply : 4 mA max imum
Standby current
(bac kup suppl y)
(A156 onl y)
Input Characteristics
Voltage range

25 rnA max imum

-10.24 V to +10.24 V,
1 LSB = +0.005 V

Input impedance

Power on: > 50 M ohm
Power off: 1000 ohm

Signal and common mode
voltage capability

+12 V min imum

Channel to channel
offset

+100 microvolts maximum

Gain

Unity

Overall accuracy

+3 LSBs at 25 degrees C
~5 LSBs from 0 degrees C to 60
degrees C ambient, max imum

Common mode rejection

100 dB min
(dc to 60 Hz with 1K source
unbal anc e)

Conversion speed

69 microseconds average
64 microseconds minimum
74 microseconds maximum

NOTE
There is a 10 microseconds uncertainty
due to the asynchronous relationship
between start of a conversion and the
system clock.
6-19-8

Bandwid th

No
limitation
speed

Protection

Input circuits are protected from
field overvoltages by diodes to + 13
V and by fusible resistors in serieS
with each input. A 1 A fuse protects
the circuit board etch in the event
of circuit failure.

Physical Characteristics
Dimensions
Field connector
Environmental
Characteristics

Heat dissipation

Quad module,
inch length

beyond

triple

conversion

width,

8-1/2

Cable
type
BC40A
or
customersupplied 50-pin Berg connector
Complies with DEC STD 102 Class C.
operates
in
convection
cooled
environment up to 60 degrees C
ambient.
5 Bt u/hr max im urn

6-19-9

A157
WIDE-RANGE ANALOG MULTIPLEXER
FUNCTIONAL DESCRIPTION
The A157 multiplexer module is used in the H333 I/O subsystem to
provide programmable gain of field inputs to the AeJ14 A/D
conver te r. The mod ul e accepts up to 16 d i ffe rent i al inputs tha t
can be independently programmed for anyone of eight different
gains. As many as seven of these modules may be used to provide a
total of 112 programmable gain inputs. Provision is made for
identification' of the module by reading its generic code. The
module has fusible resistors and clamping diodes for input
protection and switches for assigning the multiplexer number.
DETAILED DESCRIPTION
The following discussion of the A157 module is based on the
assumption that the reader is familiar with the material in a
preceding section, Analog Input Subsystem - General.
A simplified block diagram of the module is shown in Figure
6-20-1. The upper portion of the figure shows the multiplexer and
preampli fier sect ion that sel ects an analog fi eld signal from J 1,
applies the appropriate gain, and delivers it to the A014 via the
D-bus. The lower part of the figure shows the data registers,
D-bus interface circuits, and the module's major control
functions. The following paragraphs contain detailed discussions
of the major sections.
Multiplexer/preamplifier
The top left portion of Figure 6-20-1 shows that all channels
(analog field signals) are input to the multiplexer via Jl, the
field interface connector, and the fusible resistors. The fusible
resistors, along with clamping diodes, provide protection from
field overvoltage conditions. The channel selection controls cause
the multiplexer to select a channel according to the contents of
the channel number register.
The selected channel is input to the preamplifier section which is
configured to provide a gain according to the contents of the gain
register. The input section of the preamplifier provides a gain of
1 or 50, depending on the state of the G7 bit; the output section
provides a gain of 1, 2, 4, 10, or 20 according to the state of
bit s G (4, 6 , 7). S i nc e the t wo am pI i fie r s are c a sc ad ed , the
overall module gain is the product of the input amplifier and
output amplifier gains. Table 6-20-1 shows the manner in which the
gains are derived.

6-20-1

~
NON, ISOLATED

GAIN=
GAIN=
1
_ 1 f r ? E j 1 0 R 5 0 '2'4'10

~r---=w--:r-t-l1t--r-----------<:-L,.i.~Mi~UX~rAr+I'

OR 20

ANALOG
FIELD
INPUTS

-13 V

FUSIBLE
RESISTORS

DANA SIG
D ANA GUARD

+13 V
.. ,

~
I

GAIN CONTROL

I
I
I

~--1

~
PROTECTION
DIODES

SEL

D AUTO·ZERO
T BIT
D (4·7)

D BIT

L (0·3)

DOUT

CHANNEL
SELECT
AND
AUTO·ZERO
CONTROL
FIG 6·18·2

L1
L2
EN1
EN2
AUTO·ZERO CONTROL

SEL
MUX CLR H
D (0·4)

D D (0·7)

a::

MUX SELECT

~Z
Z
0

D (5·71

0'\

I
tv
~

I
tv

'"~

CLK H

SEL H
INIT
D SYS CLK

LO GATE L

DSYNC
D MUX STROBE
GAIN

D INIT

1/0

D MUX REL

CONTROL

D AUTO ZERo'

D OUT

SECTION
D INIT

D DOUT
D DIN

D MUX REL

D ANA ERROR IN

D RPLY

D ANA ERROR OUT

J-r----- D MUX READY
MUX CLR
ERROR

~
ONE
SHOT

D MUX READY

..:;,.D.c;.D""B'-IT'---_--.t
DMUXSTROBEI"

CHARGE PUMP RST

Fig ure 6 -20-1

D RPLY

~5
L4
MUX CLR

ERROR
DET

.. ,

D D BIT
D T BIT
D ANA ERROR OUT

D ANA ERROR IN,

A157 Wide-Range Analog Multiplexer

D G BIT

Table 6-20-1
7

J71615141=~~J
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Input
Ampl ifier
Gain

0 0
0 1
0 0
0 1
0 0
0 1
0 0
0 1

Gain Codes
Output
Ampl ifier
Gain

Overall
Module
Gain

1
1
1
50
50
50
50

2
10
20
1
2

2
10
20
50
100
200
1000

The other gains ( those with G=5)
mod ule , and if selected will res ul t

are not impl emented
in an error.

this:

When the multiplexer is selected, the SEL L switch is closed and
the preampl i fier output is connected to the A/D converter mod ul e
v ia the DANA SIG and D ANA GUARD 1 ines on the D-bus. The other
control signals for this section are prov ided by the channel
select and auto-zero control section. Figure 6-20-2 shows the,
detailed logic of this section.

L O - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LO
L1

L3--------------~~

~~~

ENl

EN2

EN L
AUTO ZERO
T BIT
OBIT
SEL

~---.-----

ZE RO L
ZERO 0 L
MA3137

Fig ure 6-20-2

Channel Select and Auto-Zero Control

Data·Paths
Figure 6-20-1 shows three read-write registers that store the
channel number, multiplexer number, and gain. The contents of
these registers are transmitted to the output select circuit,
which also receives the module's read-only data from the generic
code register. This circuit outputs the multiplexer/channel number
data unless the GBIT H or GAIN H signal is asserted, in which case
it outputs information from one of those registers. The selected
data is input to the DI gating section where it is strobed onto
the D-bus by the LO GATE L and HI GATE L signals.

6-20-3

Data Control Signals
When the program writes the multiplexer number assigned to an A157
and a channel number to the analog subsystem's A2 address, the A/D
converter outputs the D MUX STROBE signal causing that multiplexer
to decode its number and set its SEL flip-flop. (The SEL flip-flop
is the mod ul e' s data tr ansac tion enabl ing fl ip·- flop; once set, it
remains set until D MUX REL or D INIT occurs.) This action causes
the module to store the multiplexer number and channel number data
(Figure 6-20-1) •
When the program writes the gain and the GO bit in the subsystem's
A3 byte, the selected module stores the gain data and sets its GO
bit. The GO signal is input to a shift register, which after a
delay of 10 to 20 microseconds, syncs the module to the system
clock. On the second clock pulse after the assertion of GO, the
shift re'9ister outputs the D MUX READY signal to the D-bus and
drives the RESET one-shot. (The RESET signal synchronizes the
module's charge pump to the conversion cycle to ensure that large
cur r e n t sur g e son the po we r s u pp 1 Y bus e s dono t o e cur d uri ng
conversion time.)
The D MUX READY signal indicates to the A/D converter module that
the analog signal from the multiplexer is valid on the next system
clock pulse. On this clock pulse, the A/D accepts the analog data
from the mul ti pI exer and asserts D AUTO ZERO (refer to tim ing
diagram, Figure 6-20-3). Assertion of D AUTO ZEHO to the
multiplexer resets its GO flip-flop and places the preamplifier in
the auto-zero mode as follows.
l~

The multiplexers are disabled by EN H.

2,.

The holding capacitor
EN L (Figure 6-20-4) •

is disconnected

The preamplifier
ZERO L.

and

4..

The common mode vol tage is connected to
input by ZERO D L.

plus

minus

from

inputs

the

are

input by

shorted

the p:reampl ifier

Two clock pulses after the GO flip-flop is reset, the D MUX READY
signal is negated.
When the program reads the A2 address of the analog subsystem, the
multiplexer's I/O control section decodes the address byte, and
when D DIN occurs, produces the HI GATE Hand LO GATE H signals
causing t:he module's multiplexer number and channel number to be
put on the D-bus. If the A3 address is read, only the GAIN Hand
HI GATE L signals are produced. This puts the multiplexer gain
code on the D-bus in bit po si t ions 4-7. At the same t imE~, the A0l4
module supplies its status register contents in bit positions 0-3.

6-20-4

D-SYS
CLOCK

RESET _ _ _ _ _-+--I
D MUX READY _ _ _ _ _ _-1

AUTO::R: ________~(~:~___________
ENL _ _ _ _ _ _ _ _ _ _

ZERO L

~(r------------

-----------t-IL________

ZERODL------------~(MI~______________

MA 3138

Figure 6-20-3

Auto-Zero Timing

INPUT
AMPLIFIER
FROM
MUL TIPLEXERS

-.------------------.-------~

I
I

EN L - - " " ' - - __ J

~HOLDING
CAPACITOR

ZERO D L

I
I
I

I
I

---<t>----------.J
---<t>--------------J

I
I

ZERO L

Figure 6-20-4

MA 3124

Auto-Zero Circuit

Read ing ei ther the A2 or A3 byte wi th the GB IT asserted, causes
the selected A157 module to place it.s generic code on the D-bus.
If either DBIT or TBIT is asserted, the module is placed in the
auto-zero mode.
When the A0l4 module asserts the D MUX REL signal, the A157 resets
its SEL and GO flip-flops, and clears its gain register.

6-20-5

Multiplexer Number and ATRl6 Power Selection
The multiplexer number is selected on the module by the 4-pole
switch, E30
(Figure 6-20-5). An example of one possible
m u 1 tip 1 e:< e r n urn be r s e 1 e c t ion i s s h 0 wn i n Fig u r e 6 - 2 0 - 6 to
illustrate the use of this switch. Only three of the switches
select the multiplexer number; the fourth switch selects the ATRl6
power option. (The ATR16 is an isothermal screw terminal
assembly.) When the ATRl6 is being used, switch 4 of E30 must be
on; when the BC40A screw terminal assembly or a uSE!r-provided
termination is being used, this switch must be off.

A1
B1

50.49

2.1

ItN~j IE30
L-ATR16PWR
- - - M U X NO

L-I

c;::::e=] F2
I)

MA-3269

Figure 6-20-5

Wide-Range Analog Multiplexer

6-20-6

ON~
E30

t L...LLu

BITNO.~

MUX NO
* 0

! ! 1L
7

o 0

1 0

SCREW TERMINAL

{POWER OPTION
ON = ATRI6
OFF -= BC40A OR USER
PROVIDED
TERMINATION

o 1

1 0

1 1

SWITCH SETTINGS
1 =ON
0= OFF

* CODE ZERO IS USED ONLY FOR THE A014 MODULE'S INTERNAL
MULTIPLEXER, THEREFORE, THIS IS AN ILLEGAL CONFIGURATION.

** IF SWITCH 4 OF E30 IS INADVERTENTLY LEFT ON WHEN AN A 157
IS USED WITH A BC40A, FUSE F2 WILL OPEN TO PROTECT THE
SYSTEM +12 VOLT POWER SUPPLY. REPLACEMENT OF THE FUSE
IS NOT NECESSARY UNLESS THE MODULE IS TO BE USED WITH
AN ATR16 OR BC40L, AT A LATER DATE.
WHEN SWITCH 4 OF E30 IS ON, +12 VOLTS IS PROVIDED ON
PIN 25 OF J1. THIS IS FOR POWERING THE ATR16 OR BC40L ONLY.
IT IS NOT AVAILABLE TO THE USER. WHEN USED WITH THE
BC40L, THE ADDITIONAL LOAD MUST NOT EXCEED 95 mA.
MA-3127

Figure 6-20-6

Multiplexer and ATRl6 Power Select

Software Restrictions
1•
Th e A1 57 reg i s t e r s mus t
not b e wr itt end uri n g
conversion; this causes erroneous results.
2.

The multiplexers are released at the end of a conversion;
therefore, the multiplexer number, channel number, an<il
gain registers contain invalid data after this time and
must be reprogrammed before another conversion is
started.

Generic Code
The generic code of the Al57 module is octal 323.
Pin Connections
The Al57 module pin connections
are shown in Table 6-20-2.

for

6-20-7

Jl,

the

I/O cable connector

APPLICATION INFORMATION
The reader should refer to Chapter 3, paragraph 3.8.5 for general
field interface information. The reader should also review the
mater ial under the head ing Analog Fi eld Wi ring Pr ac tices can ta ined
in the sc:!ction Analog Input Subsystems - General.
NOTE
A finite nonzero current flows into both
inputs of the A157. It is the user's
respons ib il i ty to prov ide a common mode
return path for this current. For best
performance and lowest noise, this
return
should
be
provided
at
the
transducer end of the input cable.
Table 6-2£?J-2

Module A157 I/O Pin Connections

Module
I/O
Connector
Pin

Field
I/O

Co nnector
pi n

Field
I/O

1
3
5
7
9

00
01
02
03
£?J4

+
+
+
+
+

2
4
6
8
10

00
01
02
03
04

11
13
15

05 +
06 +
07 +

05 06 07 -

Common

12
14
16
18"
20

17}

Mo dule

1/o

21
23
25

+12 V*

Common

22
24
26
28
30

31
33
35
37
39

10 +
11 +
12 +

32
34
36
38
40

10 11 12 -

4:1
43
45
47
49

13 +
14 +
15 +
16 +
17 +

42
44
46
48
50

13
14
15
16
17

27}

* Fa r ATR 16 anI y
6-20-8

Common

The A157 uses the BC40-A screw terminal assembly as configured in
Table 6-20-3.
Table 6-20-3
BC40A Screw Terminal Configuration
for the Al57 Analog Multiplexer
A157
Field
Bit
Number

Screw
Terminal
Number

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Common
Common
10 +
11

6-20-9

SPEC IFICA~rIONS

All specifications refer to the A157 when used in combination with
the A014 AID converter.
Power Requi rements
Vol tag e

Operat i ng cur rent
(A157 onl y)

Main supply: VS = 12 Vdc (+2 or -1)
Vdc;
backup supply:
14 Vdc
> VB >
(VS - 0. 7) Vd c
255 rnA max imum
NOTE

If the backup supply is implemented,
total operating current is shared.
Main supply: 250 rnA maximum
Backup supply: 5 mA maximum
Standby current
(bac kup s uppl y)
(A157 onl y)
Input Character ist ics
In pu t im ped anc e

Signal plus common mode
voltage capability

3 rnA max imum

Po we ron: >5 0 meg 0 hm s
Po we r 0 f f: 100 0 0 hm s

Gain

Voltage
Range
(Vol ts)

Max imum
Signal+CMV
(Vol ts)

LSB
(mV)

1
2
10
20
50
100
200
1000

+10. 24
+ 5.12
-+ 1.024
+ 0.512
+ 0.2048
+ 0.1024
-+ 0.0512
+ 0.01024

+12
+12
+12
+12
+" 7
+ 9.5
+10.75
+11.75

5
2.5
0.5
0.25
0.1
0.05
0.025
0.005

Gain

1, 2, 10, 20,
prog r ammabl e

50,

Acc uracy

+[2 +(0.008 X gain)]
LS13s at 25
degrees C
+[4 +(0.008 X gain)] LSBs' from 0
degrees C to 60 degrees C ambient,
max imum
NOTE
This includes gain and offset
which can be adjusted to zero.

Channel to channel offset

20 microvolts

6-20-10

100,

errors

200,

or 1000

Common mode rejection

Conver s ion speed

85 dB minimum
(DC
to
60
Hz
unbal anc e)

with

source

79 microsecond average
74 microsecond minimum
84 microsecond maximum
NOTES
There
is
a
ten
microsecond
uncertainty due to the asynchronous
relationship between start of a
conversion and the system clock.
Conversion
speed
and
accuracy
spec ifications are independent of
the order of channel selection.

Bandwid th

No limitation
speed

beyond

conversion

Pro tect ion
The input circuits are protected
from field overvoltages by diodes to
+13 V and by fusible resistors in
ser ies wi th each input. There are
two 0 n e Am p f use s. On e pr 0 te c t s the
circuit board etch in the event of
c h a r g e p u mp c i r cui t fa i 1 u r e. Th e
other
protects the ATR16 power
suppl y (see tex t) •
Physical Characteristics
Dimensions

Quad module,
inch leng th

Field connector

Cabl e type BC40A, c ustomer- suppl ied
50 pin Berg, or ATR16

Environmental
Characteristics

Heat dissipation

triple

width,

8-1/2

Complies with DEC STD 102 Class C
Operates
in
convection
cooled
environment up to 60 degrees C
ambient
14 Bt u/hr max im um

6-20-11

A~20

HIGH COMMON MODE
AID CONVERTER
NCTIONAL DESCRIPTION
e A020 is an isolated, 14-bit plus sign, selectable gain, analog to
gital converter.
It is used to acquire analog field signals for I/O
bsystems where a high degree of isolation from common mode voltages
st be maintained.
A built-in, program-controlled, mercury-relay
Itiplexer selects one of a possible If) two-wire or 8 three-wire
alog field inputs.
Provision is made for reading the generic code
d for disabling all field inputs.
Additional features include
ries fusible resistors to protect the module's input circuitry and
'itches for address and range selection.
WARNING
The A~20 module uses mercury-wetted
relays. Al though these components have
metal cases, they contain glass capsules
containing mercury and a gas under high
pressure. Consequently, these modules
are not as resistant to mechanical abuse
as might otherwise be expected. The
modules should NOT be subjected to
unnecessary shock.
MERCURY IS A TOXIC SUBSTANCE. If a
module
is advertently dropped,
or
otherwise mistreated, it should be
exami ned ca ref ully to dete rmi ne if any
of the relay capsules have broken. If
ANY ev idence of mercury is detected on
the outside of a relay case (this
usually appears as a dull film on the
relay, usually at the seam between the
base and the metal case), the module
should be set aside. Repairs should only
be effected by technicians familiar with
the precautions necessary for handling
mercury.
GENERAL DESCRIPTION
Th e A02 0 con t a ins ani n put mu1 tip 1 ex e r, an A/D con v e r t e r, and a
D-bus data interface (Figure 6-21-1). The input multiplexer and
A/D converter are isolated from the rest of the module and operate
at field potential. This allows direct connections to high common
mode field inputs. Isolation from any input to ground is +500
volts peak, as is the isolation between any two inputs.
The module has switches that allow the user to select among
fourteen available ranges to accommodate different signal levels.
Two of these ranges can be selected on a given module (i.e., some
channels can utilize one of the fourteen ranges and the remaining
channels another).
6-21-1

FIELD
INPUT
CHAN J15

o r-l

~~
---I

~---

I
I

I
I
I
I
I

Nvv-

- ---

---

RELAY
MUX

INT INPUT l
TAKE CHAN
CHAN SHIFT
WR CHAN

SEl

D iNTR ii~ j
D RIF

IN 2

RTN

I
I

GUARD

L....--

r--

50/60 Hz

f---

D.T.GBIT

f---

COUNTER~

NEXT CHAN

1
E60

V
~

LATCH GD DATA
I/O
CNT'l

r---Y

INT INPUT l
TAKE CHAN

ADDR DEC

CHAN SHIFT

SUB SYS
ADDR
DDIN

WR CHAN

DDOUT
DSYNC
3WIRE

3 WIRE

GEN
CODE
REG

DOD

DOUT

D01

DIN

GBIT

DRPlY

ADDR

Figure 6-21-1

J\.,

STATUS
REG

DATA OVERRUN

INT TIME.
ADDR SEl

ERROR

BUSY

a::
f-

DONE

ACTIVE

V
-.....

DATA
MUX

)

r--

DI
GATE

LATCH GOOD DATA

LAST PROG
CHAN

r--

BYTE
REG

r---

D SYS ClK

BYTE
REG

HOLD
ACTIVE

D RIF

MOTHER BOARD
FREQ
SYN.

D DIN

CNT R
CNT'l

CNT'R ClK

_ _ _ D~~~~A!.D_ _ _

DADDR

o RPlY

o SYS ClK
f---

I
I

ADV ClK

LJ SYNC

DONE

I EOC/POl

J
l

-n

D INTR OUT
D INTR IN

INTR
CNT'l

D DOUT

3 WIRE

CHAN SEl
QUEUE

RST A/D

f'>.
- - - - - - - - - - -- - CONVERTED

r-:
I

GAIN

DONE

IN 1

FIELD POTENTIAL
~-~-- ~---------.
I/O SUBSYSTEM POTENTIAL

CHAN SEl
CONTROL

LATCH
GOOD DATA

ERROR

r:;I
I~~~V I

A020 Block Diagram

Z
Z

I
DIN

I I

Two of the module's data reg isters contain the A/D converter's
output which is 14 magnitude bits plus a sign bit and an overrange
bit. Ot her data reg i ster s conta in sta tus, add ress, and g ener it
code da ta.

DETAILED DESCRIPTION
The module consists of two printed circuit boards assembled in ,a
mother-daughter configuration (Figure 6-21-2). The heavy dashed
line in Figure 6-21-1 shows how the module's circuits are divided
between the two boards. The daughter board (54-13442) contains the
input multiplexer and the analog part of the AID converter. The
mother board (54-13729) contains the data registers, interrup:t
control circui ts, mul tipl exer control circui ts, the remainder oif
the AID converter circuits, and the D-bus interface.
Since the A/D converter circuits are divided between the tw:o
c i rcui t boards, it is necessary to have a few in terconnecting
control lines (Figure 6-21-1). Detailed descriptions of the tWo
boards is simplified if the reader is first familiarized with the
following discussion of the conversion process utilized.

AID Conversion Process
The AID converter on this module is a dual-slope integrating type.
A typical converter of
comparato r, a clock, and
and operates as follows.

this kind contains an integrator, a
some control circuitry (Figure 6-21-3)

At the beg inning of a conversion cycle, the swi tch is in the Vin
position. It remains in this position until the counter counts a
predetermined number of clock pulses (a fixed interval of time"
Tref - Figure 6-21-4). At the end of this time, the integrator
output voltage has a value that is proportional to the averag:e
value of the input over the interval. That is
Vo

Vin
=RC
Tref

where:
Vo
= the
Vin = the
Tref = the
RC
= the

integrator output voltage
input voltage
sampling period
circuit time constant

The
switch
is now connected
to
the
Vref
position. and
simultaneously the counter is reset to zero. The integrator output
now starts to decrease because Vref has a polarity opposite to
that of Vine At the same time, the counter starts counting again
from zero. Since Vref is a constant, the integrator output always
decreases with the same slope no matter what value it has at the
time Tref. When the output of the integrator again reaches zero,
the comparator output changes state and the counter is stopped.
Since the charge gained by the integrator in time Tref is equal to
the charge lost in time t, it follows that -

6-21-3

RElAYFIELD~ ~!

~?<{--.

J15

MOTHER BD
(54-13729)

DAUGHTER BD
(54-13442)

SELECT:
• RANGE BOUNDARY
• 3 WIRE MODE
• ATR16 POWER

G(GAIN)B
G(GAIN)A
EOS _~---i'-1.
(OFFSET)

SELECT:
•
•
•
•

RANGE A
RANGE B
SHIELD
INTERNAL
FILTER

MA-4795

Figure 6-21-2

Vin

A020 AID Converter Module

I
IL _ _ _ _ _ _ _ _ _

COUNTER

START---"'~

Figure 6-21-3

Simplified Dual Slope Converter

6-21-4

REJECTS LINE FREQUENCY
EQUAL TO

Tr~f
SLOPE DEPENDS
ON Vin

-Vref

,6t

.Vin

Tref

Vref

1 4 - - - - , 6Tref --+I"IJ.----i:l. t 3 - - + i

Figure 6-21-4

Tref

Dual Slope Converter Time Voltage Relationships

~~n Tref = ~~ef6t
The circuit time constant is the same in each case, so Vi n Tre f = Vre f 6 t
Vin
6 t = 6count
full coun t
Vref = =T-r-e-:f~
Therefore, the number in the counter is a binary representation of
the input voltage.
The dual-slope integrating type of converter was chosen for the
A020 because it exhibits excellent accuracy, linearity, and
res 0 1 uti 0 n c h a r act e r i s tic s, and i s i d e a 1 for ins t r urn en tat i 0 h
applications. Further, integration inherently provides high
frequency noise immunity and virtually total rejection of signals
with periods equal to or multiples of the integration time. This
is due to the fact that signals with that period will average out
to zero over the sampling period (Figure 6-21-4).
Most converters of this type have an input integration time equal
to the period of the power 1 ine frequency, since that is usually
the most troublesome inter fer ing signal. The A020 has swi tche,s
that allow selection of a 16-2/3 ms or a 20 ms integration time
for rejection of power line frequencies of either 60 or 50 Hz
respectively.
6-21-5

Daughter Board
The A02'~ daughter board (54-13442) contains an input :nu1tip1exer,
the A/D converter analog circuits, and the ranqe selector
switches. These are isolated from the rest of the module and
ope rat e a t fie I d po ten t i a 1 • Par t 0 f the con t r 0 1 c i r cui try for
channel and range selection is also present on the dauqhter board,
and is at I/O subsystem potential. The division of potential is
indicated by the heavy dashed line in Figure 6-21-5 and is for the
purpose of isolating high common mode field voltages from the rest
of the subsystem.
Channel Multiplexer - This is a relay multiplexer and is therefore
electrically isolated from the channel select controls, which are
at I/O subsystem potential. The mul tiplexer is configured to
select one of the sixteen 2-wire or eight 3-wire field inputs via
selector switch E6-5. All multiplexer input lines are protected by
fusible resistors.
Ell

- - - - - - - - -.... BuFFER
IN

GAl N B I---JR\II1.!\.8..---...---.
ADJ.

r-o---------·---I
FIELD
INPUT J15
CHAN

TPl

I
I

GA IN A L---'V\I\r--r----l
ADJ.

FUSIBLE
RESISTORS

r-------wt-----,-'--_ _ _ _ _ _ _ _

-L-________

-+lIN1

I
I

~v~~

: I

PflEAMP
OUT

o-t--r--+-----O

-r--o-------------IOIIN2

I
I

CHAN
RELAY
MUX

--~------,-----..t IN4

t------J.---I--+------J------1=====~GUARD

A/Z RTN

I +

I
17

RANGE
CONTROL t-----+--~GAIN CNT·_

50 I---'V',f\./---..t

-----+--1--,
I
I
I

E13

AID COI\IV.

1,7

-----

(RTN)

I
I
I/O'S'U'B'SYSTEMP'OTENT~II-- - - 1 - - RST AID
I

FIELD POTENTIAL

r---~~----~

ADV eLK

=t__J

EDe/PDL

•

3 WIRE

+12 V

Figure 6-21-5

MA-479

A020 Daughter Board

6-21-6

AID Converter

Analog Ci rcui ts - Th i s i s a seal ed un it wh ich i $
isolated from the I/O subsystem ground potential and operates att.
whatever field common mode potentials are present (up to 500 V
peak). A block diagram of the unit is shown in Figure 6-2l-6~
Selected channel inputs from the multiplexer are adjusted by the
Vee

909K
(25).1 N 1 -"VV~-r--"""'"
(24).IN 2-vv"~
100K
(23).IN 3

+12 V IN-e(1)

V+
ISOLATED
SUPPLY

PRE-AMPLIFIER

V-

POWER
RETURN-4 (2)

(22) .SIG RETURN
ClK ADV -e (3)

(21) .AZ --"v'V\r---~
(20) .CASE 100K
(19) __
GAIN ADJUST
(18) __

------4----------'
--__11----+-1'

INTERFACE
lOGIC AND
COUPLER

(17).H

(16). F
(15). E
(14).D

GAIN
SELECT

RESET

-4(4)

EOC/
POL

-e(5)

INTEGRATING
CONVERTER

(13).c
(12). B

VOLTAGE
REFERENCE

(11). A

---IIIJ-ISOLATED V+ OUT ..... (6)
------ISOLATED V- OUT ..... (7)

(10).INT REF-~t--------I

~r----ISOLATED RTN

(9) .REF IN----........

-e(8)
MA4799

Figure 6-21-6

Isolated, Selectable Range Integrating Converter

input attenuator and/or preamplifier shown so that the input to
the integrator is within a +2.5 V full-scale range. Attenuation
and preamplifier gain are selected by external switch settings.
When input and reference integrations are completed, internal
control circuits output POL/EOC (polarity/end of conversion;)
p u 1 s e s t h r 0 ug h i s 0 1 a t ion t ran s for mer s t o e x t ern a 1 con t r 0;1
circuits. Timing is controlled by isolated CLK ADV (clock advance)
and RESET inputs as discussed in a later paragraph.
The analog section also contains its own power supplies which are
powered by but isolated from the module's +12 V power.
Mother Board
The data registers and their control circuits on the mother board
resemble those of other four address D-bus modules (Figure
6-21-1). Also shown are the channel select queue, a frequency
synthesizer, and the counter circuit. These are discussed below.
Channel Select Queue - Throughput of the A020 is optimized by
having the module keep track of not only the channel actively
being converted, but also the channel that is to be converte.d
next, and the one most recently converted. This is accomplished by
a set of five registers that store this information (Figure
6-21-1) •

6-21-7

Al though there are five reg isters in the channel select queue,
there are never more than four channel numbers stored at any given
time. Tr.lis is because the HOLD and CONVERTED reg ist.ers contain the
same number during input integration, and the LAST and NEXT
registers contain the same number during reference integration.
The following is a description of the contents of the five
registers.
1.

Last Program Channel Register - A read/write register
that contains the last channel number written to the
mod ul e.

Next Channel Register
An internal register tha t
con ta ins the channel number 0 f the input signal to be
in teg rated nex t.

Active Register - An internal register that contains the
channel number of the input signal being integrated.

Hold Reg ister
An internal reg ister that holds the
channel number of the signal just integrated until it is
evaluated and the results transferred to the data
reg i ster •

Converted Channel Register - A read-only reqister that
contains the number of the channel for which conversion
is complete and data is available.

Integration Timing Ci rcui t
To ensure max imum rE!j ection 0 f
i n t e r fer en c e a t po we r 1 in e f r e que n c i e s 0 f e i the r 6 0 0 r 5 0 Hz,
input integration times of 16-2/3 and 20 ms are implemented on the
A020. Integration time is determined by decoding the output of the
counter and is changed by selecting a different decoder output and
co un t e r c 1 0 c k f r e que n c y • To 0 b t a ina c cur ac y and s tab i 1 i t y, c 1 0 c k
frequencies
are
phase
locked
to
the
I/O
Subsystem's
crystal-controlled 100 kHz system clock.
The A020 is shipped with the 16-2/3 ms integration time selected
(for 60 Hz rejection).
If site conditions require' a
20 ms
integration time (for 50 Hz rejection), the user may select that
option; however, he must also recalibrate the A/D converter.
Counter and Timing Circuit
The counter on the A020 module
provides the timing for the A/D converter cycle as well as the
data output of the A/D converter. A conversion cycle (Figure
6-21-7) begins with the RST A/D (reset A/D) pulse. Aft.er a delay
of 2 ms the counter is reset, and an A/D eLK ADV (A/D clock
advance) pulse occurs. This begins the input integration period of
the A/D, and starts the counter again.

6-21-8

INTEGRATE
INTEGRATE

INTEGRATOR
----~
OUTPUT

1 + - - - 1 6-2/3 ms ----1*4----+

AID ClK A D V - - -.....

'----------+-4 us
INTEGRATE REF TIME
DEPENDS ON VALUE)
( OF INPUT SIGNAL

EOC/POl ----~~~~::.:.:=:.......:~~::=::'------I

.........-

POLARITY PULSE
OCCURS ONLY IF
)
( INPUT IS NEGATIVE

MAGNITUDE
OF COUNTER
CONTENTS
(DECODED COUNT = END OF)
INPUT
TRANSFER _ _ _ _ _
_ _INTEGRATION
_ _ _ _ TIME
_ _ _ _ _ _ _......._ __

DATA

OUTPUT
DATA REG _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 6-21-7

8k9A •• ~A't.
--MA-4800

-li~~

Conversion Cycle Timing (60 Hz Timing Shown)

The counter counts a number of clock pulses corresponding to the
desired integration time (16-2/3 or 20 ms, for 60 or 50 Ha
respectively). When this count is reached, a second A/D CLK ADV
pulse is produced. At this time, a POL (polarity) pulse will occur
if the input is negative. Four microseconds after the second A/D
CLK ADV pulse, the counter is again reset. This produces a third
AID CLK ADV pul se. At thi s time, in teg rate input time end s, the
counter restarts, and integrate reference time begins.
Integrate reference time continues until the AID comparator input
reaches zero. The comparator output will then change state causing
the AID to output the EOC (end of conversion) pulse. At this time,
the counter is halted;
its contents, which is a binary
representation of the analog input signal, is transferred to the
data register, and the counter resumes counting. When the countet
reaches full scale, corresponding to an elapsed time of 8-1/3 or
10 ms (60 or 50 Hz), another RST A/D pulse occurs, denoting the
start of a new conversion cycle.
Of the sixteen data register bits, fourteen bits (0-13) represent
normal range data; a fifteenth (bit 15) is set if the input signal
is in excess of the AID converter's range as determined by the
selected gain. A sixteenth (bit 14) is set if the POL (polarity)
pulse occurs, indicating a negative input signal.

6-21-9

SOFTWARE INTERFACE
The A020 occupies four byte addresses on the D-bus. The data sent
from the A020 to the computer can be one of six bytes determined
by the two LSBs 0 f the add ress, t.he GB IT signal, and the ADDR
signal as listed in Table 6-21-1.
Table 6-21-1

Data Registers
~

Bit 1

Bit 0

G Bit

ADDR

~~_~_~_~_~_~S_i_~.J_n__l_l_3___M_A_g_~_~_r_U_D_E_____________8 ~

CONVERTED DATA
]
LAST PROGRAM
CHANNEL
CHANNEL
J . - . - - - J . -_ _ _

G
__
CO_D_E_________~I

MAGNITUDE
DATA

Data
Over- Error Done Ac
Run

I______.______

ADDRESS

x = don't care
Data Definitions
Output Data Coding - Sign + Magnitude negative data. Magnitude is true binary.

Sign bit

is asserted

for

Overrange' Bit - Asserted when input is greater than Full Scale
Range selected for that channel. Output data is therefore invalid.
Busy - When asserted, indicates channel
cannot accept any new channels.

queue

full

Done - Asserted when a conversion has been completed
available.*

and module
and data

Error - J'l.sserted when there has been an attempt to prog ram a new
channel into a busy device, or an invalid channel (>17 octal for
2-wire mode, >7 for 3-wire mode) has been programmed .. The A020
will not accept the new channel under these conditions.*

6-21-10

Data Overrun - Ind icates prev ious data was not retr ieved by the
processor before new data was available. The new data is lost, as
are all channel convert commands subsequent to the converted data
channel.*
Active
Asserted whenever a channel is written.
conversion cycle after channel queue is empty.

Negated

one

PROGRAMMING INFORMATION
To read one of the A020 analog inputs, write its channel number in
the last four bits of the third byte. Since inputting a channel
implies a desire to convert on that channel, no separate GO bit is
provided. When the A020 interrupts, read its data registers.
If the A020 is operated in the mode of converting one channel at ~
time, each conversion may take up to 74 ms. Operation at maximu~
speed requires a continuous conversion and channel switching
cycle. To accompl ish this, the A020 can store up to fo ur channel s::
two channels waiting to be converted, one that is actively being
converted, and one representing the converted channel for whicih
data is available in the data registers. To use the A020 mos,t
efficiently, first program two channels and wait for an interrupt.
When the module interrupts, read the data registers and program
two more channels. Subsequen tly, one new channel sho uld be
programmed after each interrupt and data read cycle. This sequenc:e
may be implemented by simply loading in channels at all times
until the busy bit comes up. This mode allows up to 36 conversion~
per second with 60 Hz operation. Up to 31 conversion per second
are possible with 50 Hz operation.
Assertion of the D-bi t opens all input relays, allowing a tes't
voltage to be applied via TPI and TP2 without disconnecting field
inputs. The T-bit is not used on the A020.
The processor will trap if an attempt is made to write any othe.r
byte than the third.
Gener ic Code
The A020 may have one of two generic codes depending on the
position of the MODE switch (E6-5).. The location of the MOD:E
switch is shown in Figure 6-21-9.
The codes are as follows.
324 for the 2-wire mode (switch OFF)
304 for the 3-wire mode (switch ON)

* Re set by RIFi ng the mod ul e. The 1 ast step in retr iev ing data
should be to read the status word (fourth byte) with the RIF bit
se t in the CSR 0 f the IOCM. The contents 0 f the status wo rd
tells the program if any condition exists that invalidates the
data just read.
6-21-11

FUNCTION SELECTOR SWITCHES
The mod ul e' s swi tches are
application as follows.

configured

the

user

sui t

the

Add ress Sc~l ect
The four A020 addresses are selected on the module according to
the rules stated in Chapter 4. They are selected on the module by
swi tc hes lE:60-l throug h E60-6 shown in Fig ure 6 -21-8 ~ An exampl e 0 f
one possible selection is shown in the figure.
50/60 Hz Bel ec t
In teg ration time is determ ined by swi tches E60-·7 and E60-8 or by
E60-9 and E60-l0 (Figure 6-21-8). Only two of these switches may
be on at any given time. If 60 Hz 1 ine frequency re~1 ection is
desired, turn on switches E60-7 and E60-8. If 50 Hz rejection is
desired, turn on E60-9 and E60-l0.

ATRl6 Power Select
Switch E6-l0 (Figure 6-21-8), when on, selects the A~~R16 power
option. (The ATR16 is an isothermal screw terminal assembly.)
Mode Selec:t
Wh ens wi t c h E6 - 5 ( Fig u r e 6 - 2 1-8 ) i S 0 f f , the A0 2 0 Ls se t for
sixteen channel 2-wire operation. When E6-5 is on, the A~20 is set
for eight channel 3-wire operation. In this mode, the upper eight
channel s ,are swi tched in par all el wi th the lower e igh t channel s;
that is, addressing channel 0 simultaneously switches channel 10,
channel 1 and channel 11 switch together, etc. The negative
terminal of channels 10 through 17 are used as third wire (shield)
inputs; the positive terminal of these channels should be left
open. The shield input switches somewhat earlier than the two
signal
inputs and therefore switches all the common mode
potential .. This feature is useful when the three-wire mode is used
with input filters so that commmon-mode switching transients
through the filter capacitors are reduced.
Shield Switch
When E12-9 (Figure 6-21-8) is on, the high voltage shield is
connected to the low side input of the AID converter. This swi tch
should always be ON when the A020 is in two-wire mode.
In
three-wire mode, the switch should generally be off when using
shielded inputs, but on when using input fil ters.
(Re fer to
application notes.)
Internal Filter Switch
When E12-10 (Figure 6-21-8) is on, a capacitor is connec'ted across
the inputs of the AID converter. This capacitor provides high
frequency filtering
and
is also
used
to
implement open
thermocouple detection. (Refer to applications information below.)
This switch should be on at all times except if external filters
are used, when it should generally be off to avoid errors due to
charge dumping (appearing as interchannel crosstalk).

6-21-12

SHIELD
SWITCH
INTERNAL
FILTER
= ON
12345678910
E12

I I I I I I I I III

7
1 2 3 4 5 6 7 8 9 10

DETERMINED BY 10CM
ADDRESS SELECTION
AND COMMON TO ALL
MODULES IN THE I/O
SUBSYSTEM

III I II II I I I

1 = ON
0 = OFF
SELECTION SHOWN = 171254

ADDRESS SELECT
NOTE:
I F SWITCH 10 OF E6 IS INADVERTENTLY LEFT ON WHEN AN A020
IS USED WITH A BC40A, FUSE F1 WI LL OPEN TO PROTECT THE
SYSTEM +12 VOLT POWER SUPPLY REPLACEMENT OF THE FUSE
IS NOT NECESSARY UN LESS THE MODU LE IS TO BE USED WITH
AN ATR16 OR BC40L AT A LATER DATE.
WHEN SWITCH 10 OF E6 IS ON, +12 VOLTS IS PROVIDED ON
PIN 25 OF J1. THIS IS FOR POWERING THE ATR16 OR BC40L ONLY.
IT IS NOT AVAILABLE TO THE USER. WHEN USED WITH THE BC40L,
THE ADDITIONAL LOAD MUST NOT EXCEED 145 mA.

SWITCH #
FIRST
SETTINGS
GAIN B
CHAN NO. 1 121314
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17

0 0 0
1 0 0
o 1 0
1 1 0
0 0 1
1 o 1
0 1 1
1 1 1
0 0 0
1 0 0
0 1 0
1 1 0
0 0 1
1 0 1
0 1 1
1 1 1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MA-5248

Figure 6-21-8

A020 Module Switch Functions

6-21-13

Range Select Switches
The AQl2~i ha s fo ur teen full sc al e input rang es. The use r can sel ec t
a single range for all channels or he may select two ranges and
have one set of consecutive channels operate on one (range A) and
the remainder on the second (range B).
There are switches to select the two ranges (Figures 6-21-9 and
6-2l-1Q1), and to select the point at which the range changes from
A to B (Figure 6-21-8).
Because of the way attenuation and gain
combinations are used to implement the different ranges, some
rang es c an be sel ected in more than one wa y. The recommend ed
swi tch s:et t ing s are shown in Fig ure s 6 -21-9 and 6 -21-1 QI. Channel s
zero through seven are calibrated at the factory on the +5 V range
(range A.). Channels ten through seventeen (octal) are calibrated
on the +5Q1 mV range (range B). If the user selects other ranges,
he must-- recal ibrate the AQl2Q1.. However, the user may change the
range transition point without recalibrating.
To use a singl e range for all channels, do the following.
1.

Select the desired range with
using switches E12-1 through
E13-1Q1 (Figure 6-21-1Q1).

the switches for
E12-6 and E13-8

range B
thro ugh

Set the range AlB boundary at channel zero by
switches E6-1 through E6-4 off (Figure 6-21-8).

turn ing

To use two ranges, do the following,.
1.

Select range A using switches E12-7 and E12-8, and E13-1
t h r 0 ug h E 13 -7 ( Fig u r e 6 - 21- 9) •

Select range B with switches E12-1 through
E13-8 through EI3-lQl (Figure 6-21-lQl).

Set the range AlB bo undary to the lowest n umbered range B
channel number (Figure 6-21-8). All channel numbers less
than the boundary number will be range A; all channel
numbers equal to or greater than the boundary number will
be range B.

EI2-6,

and

Calibration
Th e AQI 2 QI i s cal i bra ted at the fa c to r y for the + 5 V ran g eon the
lower channel s (gain range A), and the ±.5Q1 mV range on the upper
channels (gain range B). These were chosen both as representative
high and low level ranges for intensive testing at the factory and
as reasonable full scale range selections for a wide range of
applications. If other ranges are desired they must be reselected
and recalibrated. Calibration is done with software assistance.
The calibration procedure is included with the diagnostic software
package. The adjustments mentioned in the diagnostic (gain and
offset)
are identified in Figure 6-21-2. A Precision Voltage
Source, EDC model VS-lIN or equivalent, will be required.

6-21-14

12345678910

I II I I II 1111

E12

12345678910

I I I I I I I I I II

E13

FULL
SCALE
RANGE
VOLTS
50
25
20
10
5
2.5
2
0.5
0.2
0.1
0.05
0.02
0.01

0
0
0

1
1
1
0
1
1
1
1
1

0
0
0
0
1
0
0
0
0
0

1
1

1
0
1
0
1
0
1
0
0
1
0
0
1
0

0
1
0
1
0
1
0
1
1
0
1
1
0
1

0
0
1
1
0
0
1
1
1
1
1
1
1
1

1
1
0
0
1
1
0
0
1
1
1
1

1
1
1
1
1
1
1
0
0
1

1
1
1

1
1
1
0
1
1
0
1
1

1
0
0

t. O~

OFF

= GAIN SELECTED

J1 0
ON/OFF
2:1 ATTEN
1 = OFF/ON = NO ATTEN

o 1 = OFF/ON = 10:1 ATTEN

~------ { 1 0

= ON/OFF = NO ATTEN

MA-4801

Figure 6-21-9

Full Scale Range A Selections

6-21-15

,,/'1

",,,'"

"","

III"I Fl

IIlJ

J15 I

l-;;~--;--~~l

I I I I I I I ITQj

E12

"--v---'

.----~

~
L1

~S9~

R1 r1S
R19
R17

E13~JJJJ~

I
I

I
1

I
I

......"'1

O~I/~'
","" ",/,/
Ell

11111
1111111

FULL
SCALE
RANGE
VOLTS
50
25
20
10
5
2,5
2
1
0,5
0.2
0.1
0.05
0.02
0.01

1
0
0

1
1
1
1
1
1
1
1
0
1
1
0
1
1

1
1
1
1
1
1

1
0
0
1

1
1
0
0
1
1
0
0
1
1
1
1

0
0
0
0
1
1
1
1
0
1
1
1
1
1

1
1
1
1
0
0
0
0
1
0
0
0

0
0
1
1
0
0

1
1

1
0
1

'---y--J

0
1
0
1

a
1
0
1
1

1
0
1
0
1
0
1
0
0
1
0
0
1
0

V'-r-'

L-.._{

L-.-_--I_ _ _ _ ..

{

0 1 =: OFF/ON = 2:1 ATTEN
1 0 =: ON/OFF = NO ATTEN

0 1 = OFF/ON
10:1 ATTEN
1 0 = ON/OFF = NO ATTEN

o = OFF = GAIN SELECTED

Figure 6-21-10

MA-4B02

Full Scale Range B Selections

6-21-16

To ensure compl iance wi th speci fications, all test equi pment used
for calibration of the A020 must have been accurately and recently
calibrated. In addition, personnel doing the calibration should be
fam il iar wi th al ig ning analog equi pmen t. If yo u a re not sur e of
the foregoing, DO NOT ATTEMPT TO CALIBRATE THE A020. Factory
calibration is probably better than that which you will be able to
accomplish.
The input amplifier is arranged as shown in Figure 6-21-11.
Vol tage 1 imi t constraints are +5 V max imum at the input to the
major gain block; the output of the entire section is scaled to
+2.5 V full scale.
Whenever the input divider is used the input
Tmpedance drops to 1M ohm.
possible full scale ranges selectable at the switches therefore
include the following: +50 V, +25 V, +20 V, +10 V, +5 V, +2.5 V,
+2 V, +1 V, +500 mV, +200 mV, +100 mV, -+50 mV,- +20 mV--; and +10 mV.
In addftion,-sufficient range is provided in the gain pots so that
all these ranges can be multiplied by 1.024. This has the
advantage that it makes the bit weights decimal multiples of the
familiar and easily remembered powers of two.
Some examples of input voltages versus output codes are listed in
Table 6-21-2 for the 1 volt full-scale range. Table 6-21-3 lists
the LSB values for all the ranges.

MA-4803

Figure 6-21-11

An a 1 og In pu t

Co n fig u rat ion

FIELD WIRING
Field wiring for the A020 can be implemented with either the ATR16
or the BC40A screw terminal assembly, or with a user designed
interface.

Turn to the section on the ATR16 isothermal screw terminal
assembly (in this manual) to find field wiring configurations for
an A020 using that interface.

6-21-17

Table 6-21-2
Input
Magnitude

Binary Output Code
Magnltude
Sign

+FS-1 ~SB
+FS-2 LSB

0
0

Input Voltage ( Ideal)
Range
Nominal

11 III III III III
11 III III III 110

+0.999939 V
+0.999878 V

·
·
·

·
·
·
+FS/2

Absolute Magnitude Code

10 000 000 000 000

·
·
00 000 000 000 010

V
+(0.999847, 0-.999908) V

·
·
·

+0.500000 V

+(0.499969, 0.50(031) V

·
·
·
+2 LSB

> (0.999908)

·
·
+122 uV

·
·
·
+(92, 153 ) uV

0'\

I
N
I-'

I-'
(X)

+1 LSB
Zero
-1 LSB
-2 LSB

X*
1
,

I
1

-FS+l LSB

000
000
000
000

001
000
001
010

·
·

-FS/2·
·
·
-FS+2· LSB

00 000
~Hl 000
00 000
0£1 0£10

1
1

* X = Do n' tea r e

0
-61 uV
-122 uV

·
-(0.499969,· 0.500(31) V
·
·

999878 V
-0.999939 V

-(0.999847, 0.999908) V
< (0.999908) V

1-""

11 III III III 110
11 III III III III

92) uV
+31 ) uV
92) uV
153 ) uV

+ (31,
(-31,
-(31,
- (92,

·
· V
-0.500000
·
·

· 000 000
10 000 000

I +61 uV

Table 6-21-3
Whole Number Ranges
Full Scale
Volts
LSB uV

Least Significant Bit Values
Ranges X 1.024
Full Scale
Volts
LSB uV

50
25
20
10
5

3051.76
1525.88
1220.70
610.35
305.176

51.20
25.60
20.48
10.24
5.12

3125
1562.5
1250
625
312.5

2.5
2
1
0.5
0.2

152.588
122.070
61.035
30.5176
12.2070

2.56
2.048
1.024
0.512
0.2048

156.25
125
62.5
31.25
12.5

0.1
0.05
0.02
0.01

6.1035
3.05176
1.22070
0.61035

0.1024
0.0512
0.02048
0.01024

6.25
3.125
1.25
0.625

Table 6-21-4 shows the A020 field wiring
with the BC40A screw terminal assembly.

configurations

use

Table 6-21-5 shows the pin connections for J15, the module's I/O
cable connector, for' the user who requires a custom A020
interface.
APPLICATION NOTES
The following discussions are provided to help the user cope with
some of the typical problems in applying A/D converters in
general, and the A020 in particular.
Gain, Resolution, and Accuracy
A common error in applying analog input equipment is to confuse
resolution with accuracy.
The number of bits and ranges is often
given inordinate attention as a figure of merit of a data
acquisition system, when in fact it is relatively meaningless.
Accuracy errors can be divided into three categories: those that
are absolute, those that appear as a percentage of the input, and
those that appear as a percentage of the selected full 'scale
range.

6-21-19

Table 6-21-4
Module A020 Screw
Terminal Connections
BC40A Screw Terminal
Field Channel Number
2-Wire

3-Wire

Screw
Terminal
Number
1
2
3
4

Common
Common
10
+

11
12
13

+
+
+

Common
Common

0 Shield
1 Shield
2 Shield
3 Shield
4 Shield

5 Shield
6 Shield
7 Shield

6-21-20

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Table 6-21-5

Module A020 I/O Pin Connections

Module I/O
Connector
Pin

Field I/O
Channel
2-Wire 3-Wire

Module I/O
Connector
Pin

Field I/O
Channel
2-Wire 3-Wire

1
3
5
7
9

+00
+01
+02
+03
+04

2
4
6
8
10

-00
-01
-02
-03
-04

11
13
15
1 7} Not
19 Used
21 }
23 Common

+05
+06
+07

-12
14
16
18} No t
20 Used
22",
24
26 )- Common

-05
-06
-07

-10
-11
-12

00 Shield
01 Shield
02 Shield

-13
-14
-15
-16
-17

03 Shield
04 Shield
05 Shield
06 Shield
07 Shield

25~ATR16

Power
27}rcommon
29

28
30 J

31} No t
33 Used
35
37
39

+10
+11
+12

32} Not
34 Used
36
38
40

41
43
45
47
49

+13
+14
+15
+16
+17

42
44
46
48
50

The category of absolute errors includes offset errors of all
kinds, including initial, channel-to-channel, offset temperature
drift, and noise.
These are independent of gain or resolution.
If the A020, for example, has a 6 microvolt offset error and is
being used on the +100 mV range where an LSB = 6 microvolts, there
will be a one LSB-error, while if it is used on the +10 mV range
where an LSB = 0.6 microvolt, the error will simply become 10
LSBs.
No advantage is gained in regard to these errors by
increasing gain (i.e., changing to a lower range).
The second category of errors, those that appear as a percentage
of the input, include gain errors, gain temperature coefficients,
common mode errors, and crosstalk. If a 10 mV input is applied to
an A020 with a 0.06% gain error set for the +100 mV scale, a gain
error of one LSB will appear at the output; if the full scale
range is reduced to +10 mV, the di9ital output error will simply

6-21-21

become 10 LSBs.
Similarly, if a 1000 volt p-p common mode signal
is applied to the A020 in an input configuration that produces 160
dB 0 f co mm 0 n mod e r e j e c t ion, the 0 u t put err 0 r will b e l 0
microvolts no matter how many bits this is made to J:'epresent by
changing the full scale rangee
The final category of errors, those which appear as a percentage
of full scale, include differential and integral nonlinearity.
For example, differential nonlinearity, which is specified as +1/2
LSB for the A020, would be 0.3 microvolt on the 10 mV range but 3
m i c r 0 vol t son the 1 0 0 mV rang e • Th e us e r mus t d ec ide i f t his i s
significant in his application. Similarly, integral nonlinearity,
at + .01% of FSR, is 2 microvolts on the 10 mV range and 20
m i c r-; v 0 1. t son the 100mV rang e • In d ec i ding ho w s i g n t f i c an t t his
error is, the user should take into account the fact that integral
nonlinearity matters only if a large portion of the dynamic range
is used; if the application involves controlling or monitoring an
in put at ro un d a n a r row set po in t ,
in t eg r a 1 no n 1 in ear i t Y err 0 r s
simply translate into absolute accuracy errors, which can be
adjusted out with the gain pots, software corrected, oJ:' ignored.
From the above discussion, it should be obvious that referring to
total accuracy as a percentage of full scale input is virtually
meaningless. A total accuracy figure should not, therefore, be the
sole criterion for selecting an operating range. That is, one
should not select a lower range in the belief that because the
per c en tag e 0 f full sc ale i s a sm all ern umb e r t his will res ul t i n a
smaller total measurement error. Using a less sensitive higher
range, often has no 'signi ficantly greater error, and often has
advanta'ges in increasing dynamic range and reducing noise
sensitivity.
Th i s i s not to say t ha t the use r i s not in t ere s t E! d i n to tal
accuracy, but only that estimation of this error requires a
thorough understanding of all error components.
In addition to the above considerations of A/D converter
measurement errors, the user must also consider the error of the
transducer itself when calculating a total error.
Noise and Software Filtering
Noise, one of those errors that exists in absolute terms
regardless of the range selected, is specified for the A020 at 3
microvolts RMS or 1/3 LSB RMS maximum, whichever is greater. This
noise is internally generated in the A/D and is in addition to any
externally imposed noise. Three-sigma peak noise is three times
the RMS value for purely Gaussian noise. This all translates into
15 LSBs (3 uV RMS, X 3 = 9 uV pk ~ 0.6 = 15) of peak noise on the
+ 10mV ]~ a ng e , 1 • 5 LS Bs (9 ~ 6 ) 0 nth e + 100mV rang e
and 1 LS B
(1/3 LSB x 3) on all less sensitive ranges. For low level signals,
therefor,e, the lower order bits become meaningless if software
filterinlg is not implemented. For high level signals, internal
noise errors are comparable to quantization and differential
nonlinearity errors.
They can probably be ignored for most
applications.
I'

6-21-22

Software
filtering
can
range
from
simple
averaging
to
sophisticated autocorrelation algorithms. A common technique takes
ten sampl es, d i se ard s the hig he st and lowe st, and aver ag es the
remaining eight. Statistically, of course, the uncertainty of the
results diminishes as the square root of the number of samples
averaged. Averaging eight samples with a 15 LSB uncertainty,
therefo re, red uces the uncer ta in ty to about 5 LSBs (15/ 0 ) ; '
reducing a 15 LSB uncertainty to one LSB requires averaging 225
sampl es.
It is worthwhile noting that in the presence of noise, averaging,
can reduce quantization error to less than 1/2 LSB by simply
k e e ping f r act ion s 0 f a bit in the a r i t hm e tic res u 1 t. Th ism e a n s ,
for example, if eight samples from the A020 on the +100 mV range:
are averaged, the usual 9 microvolts of peak noise is reduced by'
1/8 to 1/2 LSB or 3 microvolts, but quantization error is reduced;
by 1/8 to 1 /1 6 LS B 0 r 0 • 375 mi c r 0 vol t s • Th e sam e 3 mi c r 0 vol t,
uncertainty results after averaging eight samples from the device
set to the +10 mV range, with quantization error reduced to 0.0375
mic rovol ts. -Aga in, increas ing ga in does not necessar i 1 Y res ul tin,
a significant improvement in performance.

High Common Mode Voltage Applications
The internal common mode rejection of the A020 is typically in
excess of 1 70 dB. Thi s i s achieved when the common mode signal s,
are applied through low source impedances (on the order of 10
ohms). Whenever higher source impedances are involved, however,
common mode errors are increased, and special measures must be
taken if best performance is to be achieved. A thorough
understanding of the error mechanisms involved will enable the,
sophisticated user to make use of the considerable flexibility;
available in the A020.
Common to Normal Mode Conversion
This phenomenon may be
under stood in the con tex t 0 f Fig ur e 6-21-12. The common mod ~
voltage appears directly at IN LO, but it appears at IN HI only
after going through the capacitive voltage divider formed by the
source unbalance Rs with the stray capacitance to ground Cs. (Cs
is the sum 0 f
the A/D conver ter
inpu t
capac i tance, the
line-to-line capacitance of the cable plugged into the module
input connec tor, and the capac i tance from the ex ternal wi ring to
ground.) The attenuation at IN HI with respect to IN LO causes a
d if feren ti a 1 (no rmal mod e) signal to appear ac ross the input to
the A02 0.
The mag ni tud e 0 f thi s e r ro r sig nal may be simpl y
calculated as follows:
A020

r----r...,.,..,.I\r-----r-----I1 N HI
~----~--r_~INLO

MA-4804

Figure 6-21-12

So u r c e Unb a 1 a nc e

6-21-23

VE = R + IZcl Vcm
s

= 1K ohm and C s = 100 pF, then at 60 Hz,

If, for example, RS

10 3
V

_ _ _ _. ; ;1____ = 3.8 X 10-

Vcm

10- 10 X 2 17 X 60

Thus, for a 1000-vo1t p-p common mode signal, the error voltage is
38 mV p-p.
Effects of Common to Normal Mode Conversion - Norman mode signals
a pp 1 i e d t 0 the in put 0 f the A020 h a v e t wo e f f e c t s : ex c e s s i v e
normal mode voltages cause dc errors by overloading the input, and
in-range normal mode signals produce ac output errors that are
attenuated by the normal mode rejection of the A/D converter.
The first effect is simple to understand. The normal mode error
appears at the input as a modulation of the desired input signal.
That is, if the input signal is 5 mV dc and the normal mode error
is 10 mV p-p, the total differential input signal will vary
between 0 and 10 mV. This total differential signal cannot be
allowed to exceed 150 percent of the
input range selected;
otherwisc~,
the A/D will run into internal voltage limits and
rectify the error signal, causing de errors.
The magnitude of the second effect, ac output errors, depends on
the normal mode rejection of the A/D. The A020 has a notch filter
characteristic at either 50 or 60 Hz (selected by switches). If
the :E r e que n c y 0 f the err 0 r s i g n a l i s wit hi n + 0 • 01 ~~ 0 f the se
nominals (as the power line frequencies normally are in any
locality served by a large power grid) the output errors will be
reduced by at least 72 dB (4,000 to 1) from the input error
(Figure 6-21-13). For small deviations from nominal, the output
error deqrades roughly linearly. If, for example, the power line
frequency deviates by 0.1% from nominal (a near catastrophic
condition in a large system), the A020 will provide approximately
6 0 dB ( 1 , 0 0 0 to 1)
r e j e c t ion to s uc h f r e que n c i E~ s a p p 1 i e d
d iff ere n t i all y to its in put s • A 3 per c en t d ev i at ion - po s sib 1 e
with some small diesel generators - would lead to approKimately 32
dB of rejection, and might make input filters advantageous (refer
to Di fferentia1 Input Fi 1 ters parag raph). It should be emphasi zed
that these output errors appear as ac noise, and therefore may be
simply eliminated by standard software averaging techniques.

6-21-24

" ~r'\

\ "
['\["

NORMALIZED
FREQUENCY
RESPONSE
(dB)

I\~'

-~~~
I

),"

~,,:-

',.
r),

1/T

\IJ

1/T

nn~

10/T

T = 1 6-2/3 or 20 ms
MA-4B05

Figure 6-21-13

A020 Frequency Response

Handling High Impedance Sources
The following are three methods used to interface the A020 to high
impedance sources.
Lower Gain - This is the easiest method, but involves the worst
accuracy tradeoffs. If, for example, the +100 mV range is selected
for an application where the transducer produces an 8 mV full
scale output, but the high source impedance produces up to 140 mV
of peak normal mode error signal, the system will provide an LSB
resolution of 6 microvolts, which is approximately equivalent to
the resolution of a 12-bit AID operating with a +10 mV full scale
range. Assuming 72 dB of NMR, 70 microvolts p-p of output noise
will be produced.
This method is the most economical, allowing the 2-wire mode and
therefore 16 channels per board to be used. It also requires no
special external measures to be taken. The primary accuracy
tradeoff is in integral nonlinearity; since the spec of +0.01% is
a percentage of full scale range, the linearity as a percentage of
the transducer full scale output will be degraded. This may not be
a ser ious problem, however, in appl ications where the dynamic
range around the nominal input is small.

6-21-25

Shielded Inputs - The A020 may be used in a true 3-wire, shielded
input mode by selecting the 3-wire option and opening the SHIELD
switch. In order for this to be useful, the input leads must be
shielded for their entire length from the transducer to the module
input connector, and the shield must be grounded at the common
mode source, (Figure 6-21-14). With RLI = RL2 = 50" ohms, the
common mode rejection in this configuration has been measured at
over 160 dB.
Differential Input Filters - Input filters provide another method
to reduce the normal mode error signal at the AID so that low full
scale ranges may be used with high source impedances.
In most
cases, however, input fil ters substantially degrade performance.
Consider the simple circuit (Figure 6-21-15).
The A020 in 2-wire mode provides about 100 pF of stray capacitance
to ground. When the channel relays switch, this stray capacitance
must be charged to the common mode potential.
One side of the
channel switching will occur before the other, but since the
charging time for the stray capacitance is nanoseconds, the 90 uF
external capacitor will appear as a short, and half the charging
current will flow through it creating an error voltage whose
magnitude is the following.
1 X 10- 10

X 1/2 Vcm

9 X 10- 5

In other words, this configuration would exhibit a common mode
rejection of only 126 dB. In addition, the dielect.ric absorption
(hysteresis) of a capacitor of this size leads to gross errors if
the input varies over time scales of anything less than hours •

, ~~~

.",.,.

..... ---------- ~~~,
RL1

...... __ _

A020

\-~,--------f IN HI
\

I
~------~AA~-----------------~ INLO

.,,-----

MA-4806

Figure 6-21-14

Shielded Input

6-.21-26

A020

330n
IN HI

90llF

IN LO

VCM

MA-4B07

Fig ur e 6-21-15

Input Fi 1 te r

If input filtering appears to be the only solution to a high
source impedance probl em (or if it is necessary to rej ec t a
frequency other than 50 or 60 Hz or harmonics thereof), and poor
common mode rejection cannot be tolerated, the 3-wire mode can be
used to improve the CMR by approximately 20 dB (factor of 10). In
this case, the SHIELD switch must be on and the INTERNAL FILTER
switch must be off. The shield input must be brought back directly
to the common mode so urce; the stra y capac i tance wi 11 be cha rg ed
through the shield lead and not through the input filter.
Capacitive Source Errors
Capacitive sources can create serious errors when used with any
multiplexed input device, including the A020. The problems become
particularly serious when high common mode voltages are involved.
The problems occur because of spikes due to input and internal
s wi tc hi ng be i ng g en era ted 0 n the in put 1 in e sand i mpo sin g err 0 r
voltages across the source capacitance. This capacitance is
sometimes not deliberately present but arises from stray
capacitance in long wiring runs.
No problem arises if the time constant of the source impedance and
source capacitance is less than 300 microseconds. Such a sourc~
will have adequate time to settle between the time of input
switching and the actual start of a conversion. Therefore, if the
source resistance is lK ohm, the capacitance may be as much as 0.3
mfd before problems are encountered; with Rs = 100 ohms, Cs may be
up to 3 uF. Note that this precludes the use of input filters
effective at 60 Hz unless special measures are taken (refer to
section on using the A020 wi th high common mode vol tages) •
Open Thermocouple Detection
The internal filter provided in the input to the A020 may be used
to implement open thermocouple detection without the enormou~
errors generated by schemes which apply constant voltage or
current sources directly to inputs.
In these older schemes,
moderately high (approximately 10M ohms)
resistors were often
connected between the inputs and ground-referenced power supplies;
since the full common mode voltage was applied through the
resistor to the input, a simple voltage divider was formed which

6-21-27

would effectively reduce the common mode rejection to 80 dB for a
lK source impedance. This translates into a 20 mV error for a 200
volt common mode voltage, making the scheme unusable.
The technique that can be implemented with the A020 involves
alternate high and low level conversions. Whenever it is desired
to check a particular thermocouple, a conversion should be
performed on a high level signal (such as the ATR16 reference
temperature output or the ATR16 12-volt power available on the
A020 input connec to r). The r esul ts 0 f this conver sion are not 0 f
interest and need not be in range. The purpose of this operation
is to charge the internal filter capacitor to a level higher than
the thermocouple full scale. A conversion should then immediately
be done on the thermocouple of interest. If the thermocouple is
good, the capacitor will discharge to the proper input level in
the sever al mill i second s allowed fo r input se ttl ing; 0 the rwi se ,
the results of the conversion will be an overrange, indicating an
open thermocouple.
Thermal Offsets
The joining of any two unlike metals forms a thermocouple. On a
printed circuit board, copper conductors are soldered to
component.s which mayor may not have copper leads but are almost
certainly
not
constructed
of
copper
throughout.
stray
thermocou.ples therefore exist allover the board, and wherever
heat-producing components generate thermal gradients, thermocouple
voltages will be produced.
Th e pr ac 1: i cal res u 1 t 0 f the see f f e c t s i n the A02 0 i san 0 f f set
error voltage produced in the input multiplexer relays. This error
is specified as a channel-to-channel offset, and is measured by
scann ing all six teen channel s a t max imum ra te fo r a t 1 eClst sever al
minutes. The specification of scan mode and rate is important
because the relay coils require significant power, all of which is
dissipated as heat; the faster a channel is scanned the greater
the thermal offset voltage. If one channel is continuously scanned
for a long period of time, the thermal error can be on the order
of 100 microvolts. Furthermore, an error will be generated not
only in the channel being swi tched, but also in channels whose
input relays are nearby and are therefore heated by the operating
relay. Time constants for these thermal effects are on the order
of minutes, so fast scanning of one or a few channels for several
seconds will cause only small errors.
Since thl~ number of variables is too large to allow useful
specification characterization, it is recommended that the user
experiment by shorting the inputs and observing the offsets
produced for his scanning pattern if channels are to be scanned
more t.han twice per second and low level signals are involved.

6-21-28

SPECIFICATIONS
General
Re sol ut ion

14-bi t pI us sign

Number of channels
Power Requirements
Vol tage

Operating current

Sixteen 2-wire or
switch selectable

eight

3-wire"

Main supply: VS = 12 Vdc + 5% Vdc
Backup supply:
14 Vdc") VB >
(VS-I2I~7) Vdc
21215 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 175 mA maximum
Backup supply: 3g mA maximum
Standby current
(backup supply)

3121 rnA max imum

Warmup time

1121 minutes (for module only;
does
not
include
temperature
stabilization time for enclosure)

Input Characteristics
Vol tag e ranges

1121 mV and +
-++ 2121
- 1121.24 mV
mV and + 2121.48 mV
+ 5121 mV and + 51.2121 mV
mV and-+ 1121 2.4121 mV
+
-+ 1121121
2121121 mV and + 21214.8121 mV
+ 5121121 mV and +512 mV
+"
- 1 V and + 1-:-12124 V
+ 2 V and + 2.12148 V
V and + 2.56 V
+"
-+ 2.5
5
V
and + 5.12121 V
+ 1121 V and-+ 1121.24121 V
+ 2121 V and + 2121.48 V
-+ 25 V and + 25.6121 V
+ 5121 V and + 51.2121 V

Input Impedance
1121 and 2121 mV range
All other ranges

1121 Mohms minimum
Input divider off: 5121 Mohms minimum
Input divider on:
1 Mohm + 1%

Power off

5121 Mohms minimum

Maximum input overload

264 Vac RMS minimum with no damage

Bandwidth

2121 Hz min imum
6-21-29

Throug hput

conversions

per

second

for

Hz operation; 37 conversions per
second fo r 60Hz oper ation; to tal

or same channel
Common M.:>de Performance

+500 V peak from ground or between

Common·-mod e
vol tag.~

~hannels, minimum

Common--mod e and
crosstal k
rej ec t:ion

150 dB minimum at 60 or 50 Hz
+ 0.1%, with a 10 ohm source
Tmpedance

RF common mode
r ej ec tion

150 dB typical, 100 dB min imum, 5
kHz to 50 MHz

Normal mode rejection

60 dB
+0.1%

Overload recovery time

By next conversion for overloads
up to 50% over the sel ec ted full
scale
range;
within
four
Gonv er sions fo r overload s between
50% and the maximum ratings

minimum

60 ·Hz,

Accuracy
Differential
Nonl inE~ar i ty

±1/2 LSB maximum

Nonl inE~ar i ty

+0.01% of full
ISBS) maximum

Offset
Initial

scale

range

(±.3

Adjustable to zero

Drift with
temperature

2 microvolts/ o C, maximum

Channel- tochannel

2 microvolts typical
10 microvolts maximum (varies with
air flow over module)

Input bias current

1 nA max imum

Full Scale Temperature
Co e f fie i en t
With input divider
Without input divider

+60 ppm/ o C maximum
o
+30 ppm/ C max imum

6-21-30

Equivalent input noise

3 microvolts or 1/3
whichever is greater

LSB

RMS,

Protec tion

Input c ircui ts are protected from
field
overvoltages by fusible
resistors in series with each
input. There is a one hal f Amp
fuse to protect the ATR16 power
suppl y (see tex t) •

Physical Characteristics

Two quad modules assembled
mother-daughter combination
up the A020 module

as a
make

Dimensions

Quad module,
inch leng th

8-1/2

Field connector

Cable type BC40A, or customer
supplied 50-pin Berg connector

Environmental
Characteristics

Heat dissipation

triple

width,

Complies with DEC STD 102 Class C
Operates in convection cooled
environment up to 60 degrees C
ambient
9 Bt u/hr max imum

6-21-31

ATR16
ISOTHERMAL SCREW TERMINAL ASSEMBL¥
FUNCTIONAL DESCRIPTION
The ATR16 (Analog Temperature Reference
16 Po int)
is an
isothermal
screw
terminal
assembly
used
for
connecting
thermocouple field wiring to an analog
input subsystem. The
assembly accepts up to 16 thermocouple inputs and provides a
single ambient temperature reference output.
The ATR16 consists of a printed circuit board assembly enclosed in
a thermal-insulated chassis. The circuit board assembly includes
screw terminals for field inputs, a temperature transducer, and an
output connector (Figure 6-22-1). A 3 m (10 ft) cable is included
for connecting the ATR16 directly to the analog input module.
(Refer the paragraph Output Cable Installation below foJ:'
additional
information on connecting the ATR16 to the input
module.)
Signal wire pairs from the field
thermocouples are
connected to the plus and minus terminal pairs labeled channel 0
through 7, and 10 through 17 (Figure 6-22-2). ATR16 construction
is such that when field wiring
is connected and the cover
attached, the terminals are all at the same temperature and
provide nearly identical reference junctions for all field inputs~
The temperature inside the enclosure (i.e., the reference
temperature) is monitored by the transducer; its output is
con n e c ted t o t he p air 0 f t e r min a 1 sma r ked H I and L 0 • Th e
temperature transducer is powered by the analog subsystem through
Jl.
The ATR16 has provision for 16 field inputs; one of these may be
used to read the output of the reference temperature transducer,
Alternatively, if all channels are needed for thermocouples, the
transducer output can be connected to one of the analog subsystem
high level inputs (i.e., A0l4 or A156).
DETAILED DESCRIPTION
The ATR16 provides screw terminal pairs at a uniform temperature
(i .e.,
isothermal
reference junctions)
and a transducer that
measures this temperature. These items are discussed below.
Isothermal Reference Junction
In order that the output of the temperature transducer be a valid
datum for all ATR16 screw terminals, they must all be at the same
temperature. Two things are done to achieve this uniform
temperature. First, the terminals are well insulated from any
external thermal shocks in the operating environment, so that they
will experience only gradual temperature changes. This is achieveQ
in the ATR16 by providing a tight enclosure and extensive thermal
insulation around the terminals.

6-22-1

INTERCONNECTING
C/IBLE
(STRIPE AT TOP)

SCREW
TERMINALS

i~~PERATURE
NSDUCER
CIRCUIT

Figure 6 -22-1

MA-3140

ATR16 Ch aSS1S
.
Assembly

6-22-2

TS1ITS2

J-t-------+t 2
3
THERMOCOUPLE
INPUTS

}-t-------.!

CHAN
17

! - + - - - - - - - - . I 50

REF. {HI
TEMP.
OUT
LO------.-----,-,,,

,OUTPUT
TO A157
'OR A020

24
COMMON

TEMPERATURE
TRANSDUCER

+12 V

34
25

MA·3123

Figure 6-22-2

ATR16 Block Diagram

Second, a thermal bond. is provided between all screw terminals to
ensure that they are all at the same temperature. This is
accompl ished as follows. The pr in ted c i rcui t board assembly on
which the terminal strips are mounted includes a copper plate that
is sandwiched between the terminal strips and the printed circuit
board (Figure 6-22-3). Each terminal passes through a hole in the
copper plate so that no electrical contact is made. However, the
hole is filled with thermal compound so that a good thermal bond
is ensured. This thermal bond, combined with the high heat
conductivity of the copper plate, minimi zes thermal gradients
between screw terminal pairs.
Temperature Transducer
The temperature transducer circuit produces an output voltage that
is directly proportional to the reference temperature (i .e., the
temperature of the screw terminals). The relationship is:
Vo = 0.1 Tr
where:
Tr = internal ambient temperature in degrees C
Vo = transducer output voltage.
The operating range is from 5 degrees C to 60 degrees
corresponds to an output voltage range of 0.5 V to 6.0 V.

6-22'-3

C which

COPPER
PLATE

TRANSDUCER
CIRCUIT

COPPER PLATE

Y/
~

PRINTED CIRCUIT BOARD

SOLDER CONNECTION

ISOTHERMAL COMPOUND
Mk3121

Figure 6-22-3

Isothermal Assembly

The circuit consists of a voltage reference, an operational
amplifier, and a temperature sensing element (Figure 6-22-4). The
sensor is a precision thermistor array located in the center of
the copper plate that thermally bonds all the screw terminals. The
rest of the circuit is located at one end of the printed circuit
board assembly (Figure 6-22-1). The resistance of the thermistor
array varies as a function of temperature. The voltaqe reference
and operational amplifier circuit provide the necessar~ offset and
gain to translate this into Vo, the desired output voltage.

Mk3126

Fig ure 6-22-4

Temperature Transducer Circuit

MECHANICAL INSTALLATION
General
The ATR16 may be installed anywhere in the system that allows the
3 m (10 ft) interconnecting cable to reach its intended module
interface. The chassis requi res 13.33 cm (5.25 in) of vertical
mounting space in a standard 48.26 cm (19 in) equi pment rack and
is 11. 43 cm ( 4 • 5 in) dee p •

6-22-4

DEC Cabinet
Using the hardware provided,
location as follows.

install

the

chassis

the

chosen

Fasten the four speed nuts to the equipment rack mounting
holes in the chosen location.

Fasten
nuts.

Place the ATR16 on the standoffs and
10-32 X 5/8 inch truss head screws
internal tooth lockwashers.

Fasten the ATR16 ground lug to the equipment rack side
rail with the 10-32 X 1/2 inch screw, 10-32 kep nut, an~
No. 10 external tooth 10ckwasher provided. The lockwasher
must be placed under the ground lug and the nut fastened
securely to ensure good contact with the equipment ground
through the paint (Figure 6-22-5).

the

four

male/female

hex

standoffs

the

speedi

fasten with four
and fo ur No. 10

I
I

EXTERNAL TOOTH
~
LOCK WASHER---- .~

I
I

~I
GROUNDLUG~
@

KEPNUT~ I
Figure 6-22-5

MA-3142

Ground Wire Fastening

Industrial Enclosure
The ATR16 may also be installed in a user supplied industrial
enc 10 sure. Mo unt ing holes on the rear 0 f the chass i s fac iIi tate
this type installation. Figure 6-22-6 shows the mounting hole
dimensions. When considering this type installation, provision
must be made to ensure that the temperature inside the enclosure
does not exceed 60 degrees C when the system reaches thermal
equilibrium. It is recommended that the ATRl6 be mounted on the

6-22-5

standoffs supplied with the unit rather than directly to the
cabinet backplate; this improves the thermal isolation properties
of the )~ TR 1 6 •

2.5 em (1")
MINIMUM CLEARANCE
TO UNIT ABOVE OR BELOW

10-32 HARDWARE
/ 4 PLACES

+---++
I
+
~
+
1

11.4 em TYP.
(4.50")

41.3 em TYP.____
(16.25")

Figure 6-22-6

10.2em(4")
-MINIMUM CLEARANCE
TO UNIT ON EITHER SIDE
MA-3149

Rear Mounting Dimensions

ELECTRICAL INSTALLATION
Interconnecting Cable
To connect the ATR16 to
with the following steps.

its

intended

module

interface,

proceed

Remove the ATRl6 cover.

Loosen the right cable clamp.

With the stripe up, bring one end of the interconnecting
output cable through the right side of the ATR16 chassis.
Guide the cable through the cable clamp and connect it to
Jl on the printed circuit board assembly with the
cable-free side of the connector against the printed
circuit board.

Tighten the cable clamp.

Guide the other end of the cable through
its intended module interface.

Plug the cable into the module with the cabJ.e-free side
of the connector against the module and with the stripe
down.

the cabinet to

Field Wiring
To ensure that proper practices are followed when installing field
wiring,
the user should
review the field wiring information
contained
in Chapter 3,
paragraphs 3.8 through 3.8.4 before
proceeding with the following installation. This procE~dure is for
bottom entry to a DEC-supplied H960 cabinet and can be modified to
accommodate top entry or a user-supplied cabinet.

6-22-6

NOTE
To realize optimum thermal performance
of the ATR16, it is recommended that the
field wiring be of the smallest size
consistent with the application.
1.

Bring the
cabinet.

field

wiring

Guide the wiring along the channel formed by the cabinet
vertical supports and clamp it securely in place.

Loosen the left cable clamp of the ATR16.

Bring the field wiring into the left side of the chassis
and through the cable clamp.

Fasten the field wiring to the
shown in Figure 6-22-7 or 6-22-8.

Tighten the cable clamp.

Repl ace the ATR16 cover.
CHAN. NOS.- 0
1

2
3

through

the

screw

bottom of

the

terminals

11 12 13 14 15 16 17

TS1
HI

~ TEMPERATURE

~TRANSDUCER

LO
TS2
1

CHAN NOS. -

12 13 14 15 16 17
15

MA-4BOB

Figure 6-22-7

2-Wire I/O Connections (A157 or A020)

CHAN NOS.- 0
1

2
3

10 11

12 13 14 15 16 17

10 11

12 13 14 15 16 17

TS1
HI

L- TEMPERATURE
I
TRANSDUCER

LO
TS2

~C-HAN-----tlllllll-------'
SHIELD---O

7
MA-4B09

Fig ure 6-22-8

3-Wire I/O Connections (A020 only)
6-22-7

H960

DC Power
Separate power supply connections are not required for the ATR16.
Power (+12 Vdc) for the temperaturE~ transducer is input from the
interfacing module via the interconnecting cable (Figure 6-22-2);
however, a switch on the interfacing module must be in the on
position to connect power to the cable. This switch is identified
in Table 6-22-1 for each type interfacing module.
Table 6-22-1
Interfacing
Module

ATR16 Power Switches

Power Switch
Location

A157

E30-4

A020

E6-l0

(on daughter board)

Transducer Output Connection
Temperature output may be connected to one of the ATR16 internal
screw tel~minal pairs or it may be connected to an extE!rnal screw
t e r min a l p air (i. e ., A1 5 6 0 r A0 1 4). Th e s e t wo 0 p t ion s are
illustrated in Figure 6-22-9.

EXTERNAL
TRANSDUCER
CONNECTION

~---------------

MA·3148

Figure 6-22-9

Transducer Output Connection Options

6-22-8

APPLICATION INFORMATION
Voltage output from a thermocouple circuit is a function of the
materials employed and the temperatures of the two thermocouple
junctions. If one of the junctions is at a known temperature, and
the voltage is known, the temperature of the other junction can be
determined.
The ATR16 enables the user to make
example, if Tm is the temperature
thermocouple (Figure 6-22-10), then:

this type measurement. For
of interest at the field

Tm = f[f(Vm - 10 Vo)]
where:
Vm = thermocouple circuit voltage
Vo = temperature transducer output voltage.
The indicated functions are nonlinear and are evaluated by various
analytical and/or lookup techniques that are beyond the scope of
this document.

THERMOCOUPLE JUNCTION AT
KNOWN TEMPERATURE
ATR 16

TEMPERATURE _ _-+-...
TRANSDUCER

MA-3150

Figure 6-22-10

ATR16 Application

Note that the range of Vo is from 0.5 V to 6.0 V, corresponding to
a temperature rang e 0 f 5 deg rees C to 60 deg rees C. The rang e
accommodated by the analog subsystem depends on which A/D
converter and what gain is used. These factors also affect
resolution. Table 6-22-2 lists the characteristics of the two
converters that are pertinen~ to this discussion.

6-22-9

Table 6-22-2

AID Converter Characteristics

AID
Conver'ter

A0l4

A020

Multiplexer

A014, A156,
or A157

A157

A020

Gain

+10 V

+5 V

+10 V

-+5 V

No. bits

LSB

5 mV

2.5 mV

600
microvolt

300
microvolt

Temperature
Span

5 degrees to
60 degrees C

5 degrees to
50 deg rees C

5 deg rees to
60 degrees C

5 degrees
50 degrees

Resol ution*

0.05
d eg rees C

0.025
d eg rees C

0.006
d eg rees C

0.003
d eg rees C

Input Range

*Note that this resolution does not imply equivalent accuracy,
which is a function of the ATR16 temperature transducer.
In order for the reference temperature (i .e., the temperature
transducer output) to be valid, it must be read just bE~fore or
after the field thermocouple voltage is read. This constraint
becomes more critical if the ATR16 environment is subject to
significant thermal shocks. The effect of ambient temperature step
changes on the reference temperature for a given elapsed time can
be described by the following transfer function:

t
To + Ts [1 - e"'-r-]

where:
Tr
reference temperature
To = reference temperature before step change
Ts
magnitude of step change
t = time in hours
T = ATR16 thermal time constant.

The ma~{imum slope given by this equation can be approximated as:

(maximum) = 2 X 10- 4 Ts

In addition to their effect on reference temperature, thermal
shocks to the ATR16 also produce thermal gradients on the screw
terminals which show up as an error (i.e., the temperature of the
terminals is different from the transducer output). The maximum
value of this error for a given step change in the ambient
temperature is shown in Figure 6-22-lla.
6-22-10

The maximum thermal gradient error will not be reached
i mm e d i ate 1 y , but will b u i 1 d up g r ad u a 11 y and t he n dec a y •
Therefo re, the amoun t 0 ferro r depends on how much time has
elapsed since the thermal shock. The relationship between time and
error is shown in Figure 6-22-11b.

0.9
0.8

0.7
u

0.6

~ 0.5

~ 0.4

«
~

0.3

0.2

0.1

STEP CHANGE 0 C
A

01000:
0:

;100~
x

u..

0 1
0.5

1.0

1.5

2.0

2.5.

...J

«
~

~
u..
~

0 --I._ _ _ _ _-=~_-_.----'

3.0

LEFT

CENTER

TIME AFTER STEP CHANGE (HOURS)

TERMINAL LOCATION

RIGHT

MA·3145

Figure 6-22-11 ATR16 Typical Characteristics

6-22-11

In generall, the thermal gradient error is virtually nonexistent
for terminals at the center of the screw terminal assembly where
the sensor for the reference temperature transducer is located.
Th e err 0 r inc rea s e s for term ina 1 s t.o war d e i the rend, rea chi ng a
maximu.m at the outermost terminals
(Figure 6-22-11c:).
It
is
the ref 0 r e po s sib 1 e t o n ear 1 y eli min ate the e f f e c t s () f the rm a 1
gradient errors for a critical thermocouple by assigning it a
center channel.
SPECIFICA'rIONS
Power Requirements
Voltage
Current
Input Characteristics
Cross talk
(channel to channel)
including interconnecting
cabl e)

12 Vdc (+2 or -1) Vdc
10 rnA max imum
with A157:
80 dB minimum at 60 Hz with lK
source unbalance
with A020:
140 dB minimum at
so urce unbalance

Common mode voltage
Physical Characteristics
Dimensions

Weight
Environmental
Characteristics

Heat dissipation
Thermal Characteristics
Transducer output
(nominal)

Limi ted
A157

by analog

60Hz
input

0 f

wi th

A020

13.33 cm (5.25 in) height
48.26 cm (19 in) width
11.43 cm (4.5 in) depth
3.2 Kg

(7.1 Ibs)

Complies with DEC STD 102,
Class C.
Operates
in
convection
cooled
env i ronmen t
up to 60 d eg rees C
ambient.
0.053 Btu/hr maximum
Vo = 0.1 Tr
( T r i n d eg r e esC, V0

i n v o:L t s )

Transducer accuracy

under
C maximum,
+0.25 degrees
normal
ambient
temperature
variations

Thermal time constant

1.5 hours

6-22-12

A630
FOUR-CHANNEL D/A CONVERTER
FUNCTIONAL DESCRIPTION
The A630 module comprises four independently addressable, l0-bit,
digital to analog converters (DACs)
for use in the H333 I/O
Subsystem. Current and voltage output options, with protection
circuits, are provided for each converter. Provision is made for
reading the output status, zeroing all outputs, and reading the
module's generic code. The module features switches for addresS,
selection, calibration, and output mode selection.
DETAILED DESCRIPTION
A s i mpI i f i ed b 1 0 c k d i ag ram 0 f the DA C mod u 1 e i s s ho wn i n Fig u r e
6-23-1. At the left of the figure, the unit receives data and
control signal s from the D-bus, conv'erts the dig i tal data to an
analog signal via one of the four DACs, and outputs this signal to
the field
through the interface connector.
The
following
paragraphs elaborate on individual sections of the block diagram
and discuss the module's control sequences and data flow.

J-1
VOUT
lOUT

VOUT

lOUT

II:

VOUT
lOUT

~
0

...J

VOUT
lOUT

DDOUT
DRPLY
DADDR
DSYNC
DD. T. GBIT

MA-2161

Figure 6-23-1

A630 DAC Module, Block Diagram

6-23-1

Register Formats
Each DAC channel occupies two addresses; a total of eight for the
module. The converters are l0-bit devices; therefore, the input
data word is transmitted in two bytes. The two most significant
bit s ( MS B s) are i nth e D0 and D1 po sit ion s 0 f the h i g h b yt e and
the eight least significant bits (LSBs) in the low byte (Figure
6-23-2). The high byte also contains four read-only status bits in
positions D2-D5 when the TBIT is asserted. Bits D6 and D7 are not
used.

TYPICAL
ADDRESSES

171260

-+~}
43210

DACO
171261

L
07
171262

OUTPUT DATA (READIWRITE)

_ _ _J

STATUS BITS (READ ONLY)
(WHEN TBIT IS ASSERTED)

DAC 1
171263 '"'"--'----'-_S4-..L-S~~
07
171264

-+-+--+---+---1

DAC 2
171265

'"'"--'----'-~~-L~~__'_~

07
171266
DAC3
171267

67 I 66 I 65

64 I 63 I 62 I 61

~
I
I : :
~ S4 1 S~~I 71 1 70

m~l
~.

NOTE:
IF THE GBIT IS ASSERTED, ALL ADDRESSES WILL
CONTAIN THE MODULE'S GENERIC CODE.
MA-2157

Figure 6-23-2

DAC Data Registers

Data Paths
When a data word is to be output to one of the four DACs, the high
byte is output first and then the low byte. The hi9h byte is
strobed into one of the four holding registers by WRl, WR3, WR5,
or WR7, depending on which of the four DACs has been addressed
(Figure 6-23-3). When the low byte data is received, it and the
two bi ts in the holding reg ister are strobed into the l0-bi t
output register by WR0, WR2, WR4, or WR6.
The output register drives the output disable gates. When the DBIT
is asserted, these gates force the data input to the DACs to zero.
The output disable gates drive CMOS switches that drive the D/A
1 adder nE~two r ks. These dev ices prod uce analog sig nal outputs that
are a function of the weights (binary values) of the asserted bits
i nth e 1 QI - bit d a t a wo rd.

6-23-2

STATUS

\-01
J
1
~

REF

DAC
OUTPUTS

REF/2
FIELD INTERFACE
CONNECTOR

DTBIT

J-l

DAC
CHANa
t::::::::J\~--L_~--L

___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....,
13

DAC
CHAN 1
--~--------,.---.---

VOUT

} DACl
OUTPUT

- - - - - - - - -- -- - - ------'

lOUT

t:::::::J\:-;:::::J....l--L_- - - _ _ - _ ____ - _ _ _ _ _ _-,
37

en
I

DAC
CHAN 2

01 GATE

I-==~::::;--'T---

N
W

t::=:::::::::;;:~Ll..--=:J._-

----- - - - -- - _______

39
....J

DAC
CHAN 3

~-------.-..,..------------------------'

DGBIT
o SYNC
DADDR

ODIN

o DOUT
o RPLY
o OBIT

Figu~_e_ 6-23-3

DAC,

} DAC2
OUTPUT
lOUT

_________________.....,
47

VOUT

A630 Four-Channel

Module sfock--OIag ram

VOUT

48
49
50

DAC3

lOUT

OUTPUT

Each D/A ladder network drives a voltage output buffer amplifier;
this amplifier drives a current converter circuit~
Both the
current and voltage output circuits go to the field interface
connector at the right of the figure.
The voltage outputs also go to a comparator network that compares
the outputs of the four DACs and provides output status
information to the diagnostic program for maintenance use when the
TBIT is asserted. These status bits are shown on the block diagram
as bits S{0-4).
Finally, all output data registers and status information goes to
the input multiplexer (at the left of Figure 6-23-3) where it can
be read by the program under control of the A0, AI, and A2
signals. The output of this multiplexer goes to the G multiplexer,
which provides normal output data unless the GBIT is asserted. If
the GBIT is asserted, this circuit puts out the generic code of
the mod u 1 e • Th e G mul tip 1 ex e r 0 u t put i s the n s t rob ed 0 n to the
D-bus by the DI GATE signal.
Control Signals
Data transactions (DATAOs and DATAIs) to and from the DACs, as
called for by the program, are controlled by D-bus Cycles
originating in the IOCM. A data transaction begins with an
addressing phase in which the module's address is put on the
D-bus, followed by D SYNC. The module's address comparator decodes
the address, and when D SYNC occurs, produces its internal MY
ADDRESS signal. The lower three bits of the address are stored as
the A0, AI, and A2 signals. This completes the addressing part of
the D-bus Cycle.
If the data transaction is a DATAO, by this time data will be put
on the D-bus, and the next control signal asserted by the IOCM is
D DOUT. This causes the WR0-WR7 decoder to produce one of its
outputs and strobe the data byte into the proper register. Figure
6-23-3 shows that D DOUT also produces the D RPLY signal telling
the procE~ssor that output data has been received. The processor
then negates D DOUT.
The DACs on this module have a 10-bit input word, so a complete
data transfer actually requires two D-bus Cycles or DATAOs. The
high byte data is always output in the first cycle and the low
byte in the second. For example" if the channel two D~C at base
address 171260 is being addressed, the high byte data (address
1 7 126 5 )
i s o u t put fir s t
and s t rob ed
i n t o t h e 2 - b :L t
ho Id i n g
reg i s t e r by the WR 5 s i g n a 1. Th e low b yt e (ad d res s 1 71 2 6 4 ) i s the n
output and all ten bits are strobed into the output register by
the WR4 signal. The output data remains unchanged until the
processor outputs a new data word to the low byte address.
If the prog ram wants to moni tor the dig i tal word of a [lAC 0 utput,
it causes the processor to perform DATAls on its two addresses. In
the case of a DATAl, the addressing part of the cycle is the same
as for a DATAO. The lower three bits of the address that are

6-23-4

s tor e d as A0 , AI, a nd A2 set up the i n put mu 1 tip I ex e r for the,
correct byte, and when the processor asserts 0 DIN, this data is;
strobed onto the D-bus by the 01 GATE signal. After a short delay,
01 GATE produces 0 RPLY, notifying the processor that data is on
the bus. The processor then causes the IOCM to negate 0 DIN.
Again, two addresses must be read to get all ten bits of data, so
another D-bus Cycle (DATAl) will follow.
Between the input multiplexer and the DI gates is the G
multiplexer. This multiplexer outputs data from the input
multiplexer unless the program has set the GBIT in the CSR of th~
IOCM. In that case, the module's generic code is put on the bus
instead of normal data.
When the program sets the OBIT, it disables the output registers
to all four DACs, which sets all their outputs to zero. Th~
contents of the registers can still be read by the processor.
If the program sets the TBIT, the status bits are
placed in the high byte of the data word being read.

enabled

and

CAUTION
When
using
the
diagnostic
test
associated with the TBIT, the OBIT
cannot be used to disable the OAC
outputs; instead, the m.odule's output
cable must be disconnected to inhibit
output
signals
to
the
customer's
equi pment. Th is is bec ause the TB IT
function
for
this
module
enables
monitoring the output comparator network
status bi ts while the OAC outputs are
being exercised. While it is true that
the OBIT disables
(zeros)
the OAC
outputs to the customer, it is also true
that
it
inval idates
the
output
comparator signals.
OAC
Each channel consi sts 0 f a set 0 f analog swi tches, an R/2R 1 adder
network, a voltage amplifier, and a current converter (Figure
6-23-4). The switches, driven by the output data word, switch the
1 eg s 0 f th e I ad de r bet we e n REF /2 and g r 0 un d ; the MS B i s a t the
amplifier end and the LSB at the other end of the ladder. Eacn
ladder leg that is switched to ground produces an incremental
output
according to its binary weight. The output of the ladder
network is a current that is the sum of the contributions of the
asserted bits of the data word.
The voltage amplifier converts the output current of the ladder
network to a proportional voltage. The LSB (00) produces an output
of 10 mV and succeeding bits are weighted to produce 2 n times this
amount, where n is the bit number. Therefore, the MSB (09)
produces 10 mV times 512 or 5.120 V .. If all bits are asserted,

6-23-5

CURRENT
CONVERTER

+15
IGAINI
2R

REF

2o--...----"VVIr-.

+
R

@££iliJ

I OFFSET I
2R

2R
DATA
WORD
IN

O~ >-_..1~
I
I
I
I
I

I I
I I
I I

VZ
SWITCHED
2R

~>-- --!
2R
REF

_--I '--.,---J

'-----v.
j\NALOG
SWITCHES

RI2R
LADDER

VOLTAGE

AMP

-5
MA·2154

Figure 6-23-4
their combined weights add up to
weight of each bit.

DAC Circuit
l0~230

v. Table 6-23-1 lists the

Voltage amplifier output is current-limited and should not be
loaded in excess of 15 rnA. Clamp diodes provide output protection
in the event of externally applied overvoltages.
In add i ti.on to the vol tage output, each DAC has a uni polar current
converter that outputs a current from 0 to 20 rnA or from 4 to 20
rnA. Switches on the module allow the user to select the desired
current range independently for each DAC. Changing the current
range requires recal ibration of the current converter, but does
not affect the voltage outputs.
The current converter is a self-balancing bridge arrangement that
uses the voltage amplifier's output as its input (Figure 6-23-4) •
When the output of the voltage amplifier is changed, the current
converter rebalances its bridge by changing the current delivered
to its loa d • Th ere for e , i t i s a b 1 e t o p rod u c e a cur r e n t
proportional to the output of the vol tage ampl i fier. When both
switches at the current converter's inputs are opened, an offset
and gain change are introduced, placing it in the 4 to 20 rnA mode.
The current converter circuit includes offset and gain controls
for calibration purposes. The output circuit is a Darlington
amplifier circuit protected by a series fuse and clamping diodes.
The output voltage of the current converter is limited by the
power suppl y. It should not be expected to del iver an output
voltage in excess of 10 v.

6-'23-6

In the 0 to 20 rnA mode, the LSB (D0) produces an output of 19.55
rnicroarnp, and succeeding bits have binary-related weights such
that the MSB (D9) produces a current of 19.55 rnicroarnp X 512 =
10.00978 rnA. Table 6-23-2 lists the current produced bv each bit.
Table 6-23-1

Voltage Output Bit Weights

Bit No.

Weight (mV)

10
20
40
80
160

1
2

3
4
5
6
7
8
9

Total
(All bits asserted)

320
640
1280
2560
5120
10230

Table 6-23-2
Current Output Bit Weights
(9 to 29 rnA option)
Bit No.

Weight (microamp)

19.55
39.10
78.20
156.40
312.81

1
2
3
4
5
6

7
8
9

Total
(All bits asserted)

625.61
1251.22
2502.44
5004.89
10009.78
20000.00

In the 4 to 20 rnA mode, normal current output with no bits
asserted is 4 mAe The LSB causes a current increase of 15.640
microamp for a total output of 4015.640 rnicroamp. Succeeding bits
have binary related weights such that the MSB (D9) causes an
increase of 15.640 microamp X 512 = 8.00782 mA, for a total output
of 12.00782 mAe Table 6-23-3 lists the contribution of each bit
and the resulting current output when only that bit is asserted.
Both voltage and current outputs of a DAC can be used as long as
the total module load does not exceed 80 mAe
6-23-7

Table 6-23-3
Current Output Bit Weights
(4 to 2~ rnA option)
I

Bit No ..
0
I

2
3
4
5
6
7
8
9
Total
(All bits asserted)

Offset
Weight
(microamp) (microamp)

Output
(microamp)

15.640
31.280
62.561
125.122
250.244

+4000
+4000
+4000
+4000
+4000

40150640
4031.,280
4062.,561
4125.122
4250.244

500.489
1000.977
2001.955
4003.910
8007.820
16000.000

+4000
+4000
+4000
+4000
+4000
+4000

4500.489
5000.977
6001.955
8003.910
12007.820
20000.000

Internal Comparator
The module's four DAC outputs are input to a comparison network
that generates the four status bits (Figure 6-23-3). These bits
have the following significance:
81
81

= 1 for VI > (V0 +30 mV)
= 0 for VI < (V0 -30 mV)

82
82

= 1 for V2 > (VI +30 mV)
= 0 for V2 < (VI -30 mV)

83
83

= 1 for V3 > (V0 +30 mV)
= 0 for V3 < (V0 -30 mV)

84
84

= 1 for V3 > (V2 +30 mV)
= 0 for V3 < (V2 -30 mV)

The program monitors this status information by asserting the TBIT
and reading the high byte of the DAC output. If the DACs are all
in calibration, the status bits assume predictable Htates as a
function of the four DAC inputs, thus providing diagnostic
in fo rmat ion to the program. Note that between the 1imit.s specified
above for each status bit, the bits are undefined. Th is is shown
graphically in Figure 6-23-5 for status bit 81 ..

-60

-40

r - - - UNDEFINED
I

Wi__
-20

- : ( V 1 _ V O ) mV

60
MA-2166

Figure 6-23-5
6-23-8

8tatus Bit 81

Reference Supply
There is a separate voltage supply on the module for producing the
REF (10.240 V) and REF /2 (5.120 V) vol tages used by the DAC
c i r cui t s. A s i mpI i f i ed sc h em at i c i s s ho wn i n Fig u r e 6 - 23 - 6 • Th e
circuit consists of a 6.2 V zener reference diode and operational
amplifier buffers.

REF
ADJ

REF

~ (10.24 V)

EREF

REF/z
ADJ

REF
2
(5.12 V)

MA·2158

Figure 6-23-6

Reference Supply

The first amplifier circuit produces the REF voltage. For
calibration purposes, switches 1-4 provide a co a r sea d jus tm en t •
(Switch 1 has the most significant effect.) The potentiometer
provides fine adjustment.
REF/2 is produced by a voltage divider on the REF circuit output,
with a potentiometer for adjustment and a voltage follower.
Charge-Pump Circuit
A separate power supply on the module provides +15 V and -5 V for
all analog circuitry. The supply consists of a 50 kHz switching
stag e t hat d r i v e s t wo reg ul at i ng c h a r g e pum p s . Th e + 1 5 V c h a rg e
pump utilizes the 10.240 V reference supply as its reference.
Address Selection
The addresses for this module must be assigned according to the
rules stated in Chapter 4. They are selected on the module by the
5 - po 1 e s wi t c h E21 s ho wn in Fig u r e 6 - 2 3 -7 • An e x am pI e 0 f 0 n e
possible address selection is shown in Figure 6-23-8 to illustrate
the use of this switch.

6-23-9

CALI BRATION
SWITCHES

CURRENT MODE
SELECT

~J'TCH
'hJ IhJm

RE:F ADJ ---"CB:IT[]
REF/2

ADJ~C[!lli
5049

E79

II" III"

E80
R102

--- [[ill]
[[J]]
Rao

R110

R101

R88

R79

•

R36

R44

R66

R57

CHAN
2

CHAN

E78
R58

®@®®®® ® ®
® •I
~+~)t~t
I
I
Q

J-1

J1---t
•

~
CHAN

R35

•

~
CHAN
o

fG\ VOLTAGE

\.:::.J OFFSET

ADDRESS
SELECT

I" ""I

E21

U-______________________________________________~
MA-2163

Figure 6-23-7

A630 DAC Module

6-23-10

[2J I
14

[2J

I I

7
13
11

12
11

I
11

I I

0 1 0 11

2
7

1 1 0

1 0

I I

0-7
2

02 1 D1

I I
DO

\.~ ",

V
DETERMINED BY 10CM ADDRESS
SELECTION AND COMMON TO ALL
MODULES IN THE 1/0 SUBSYSTEM

Q
."

DAC MODULE.
ADDRESSES SELECTED

a
z

= 171260-171267

BIT SELECTION}
0= OFF
1 = ON
MA-2159

Figure 6-23-8

A630 Address Selection Example

Generic Code
The generic code of the A630 DAC module is 261.
Pin Connections
The A630 module pin connections for Jl,
are listed in Table 6-23-4.

the

I/O cable connector,

CALIBRATION
General
DAC module calibration is accomplished by means of diagnostics
included with the I/O Subsystem. Instructions for using these
diagnostics are included with the software package. Normally the
DAC module is calibrated and ready for service when received by
the customer; however, the customer may wish to change the current
output option from the 4 to 20 rnA range to the 0 to 20 rnA range.
(The module is shipped with the 4 to 20 rnA range selected.) This
necessitates recalibration of those outputs. If calibration is
attempted without the diagnostic, be advised that the low end
calibration point for the 0 to 20 rnA current range is not zero but
+1 LSB or 19.55 microamps.
Identification of adjustments and switches is provided in Figure
6-23-7. A careful study of this figure is recommended to avoid the
frustration of selecting the wrong adjustment during
the
calibration procedure.
6-23-11

Table 6-23-4
Module
I/O
Connector
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
..-.--

Module A630 I/O Connections
Module
I/O
Connector
Pin

Field
I/O

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

Vout Chan 0
lout
Vout Chan 1
lout

Vout Chan 2
lout

Vout Chan 3
Iout
'--'--

6-23-12

Field
I/O

Ground
Ground
Ground
Ground

Ground
Ground

Details of the calibration switches are shown in Figure 6-23-9.
These switches should be operated only during recalibration of the
module.

,,91

:~,tIIlfl 1

REF SWITCH (ALWAYS ON(
REF ADJUST
INCREASE = ON
DECREASE = OFF

EOOFjl E7.Fjl
~

________~~_~I_====CH~N)FOR

~II,

L - ._ _ _

1
2

SPECIFIED
CHANNEL
BOTH
ON = (0-20)
rnA
BOTH OFF = (4-20) rnA

L.---------------------3
MA·2160

Figure 6-23-9

Voltage Reference and Current Mode Switches

Proper placement of the meter leads and precision resistor used,
during calibration is essential to achieve a valid calibration,
(Figure 6-23-10).
The A630 is accurately calibrated and sealed at the factory; it
does not require recalibration at the time of installation. Field.
recalibration should only be attempted when a DAC malfunction iSi
suspected. The malfunction should be verified by running the
diagnostic before proceeding.
To ensure compliance with specifications, all test equipment used
for calibration of the A630 must have been accurately and recently
calibrated. In addition, personnel doing the calibration should be
familiar with procedures for aligning precision analog equipment.
If you are not sure of the foregoing, DO NOT ATTEMPT TO CALIBRATE
THE A630. Factory calibration is probably better than that which
you will be able to accomplish.

6-23-13

SCREW
TERMINALS

~
500 OHM
RESISTOR
(.01%)

~~M

..-{

=~=====::/
CLIP
LEADS

Figure 6-23-10

MA-2161

Calibration Resistor and Meter Lead Placement

Access to the adjustments and switches is permitted by putting the
DAC on an extender module.
CAUTION
The system must be powered down before
inserting or removing any module.
Equipment Needed
mod I~ 1

DVM

We s ton S h 1 urn be r 9 e r
equivalent

Extender module

W904B

Re si stor

5 0 0 0 hm , 0 • 01 per c en t ,
part no. 13-09985-00

I~ • 3

443

0 r

DEC

Screw Terminal Connections
The reader should refer to Chapter 3, Paragraph 3.8.5, for general
field interface information. The A630 uses the BC40A screw
terminal. Refer to Table 6-23-5 for this module's terminal
conf ig ura t ion.

6-23-14

Table 6-23-5

Module
BC4~A

Field
Channel
Number

A63~

Screw Terminal Connections

Screw Terminal
Screw
Terminal
Number
1

2
3
vout
Ground
00 { lout
Ground

Vout
Ground
01
lout
{ Ground

vout
Ground
02 { lout
Ground

vout
Ground
03 . 10 ut
{
Ground

4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

6-23-15

SPEC IF ICA~rIONS
Power Requirements
Voltage

Operating Current

Main supply: VS = 12 Vdc + 2 Vdc
Ba c k u p s u p ply:
1 4 V de> VB
(VS-0.7) Vdc

360 rnA max imum

NOTE
If the backup supply is implemented,
total operating current is shared.
Main supply: 350 rnA maximum
Backup supply: 10 rnA maximum
Standby current
(Bac kup Suppl y)

10 rnA max imum

Number of channels

Four

Digital input

Natural binary, unipolar

Output Characteristics
General
Re sol ut i.on

One part in 1024 of full scale
LSB maximum between end points

Linearit.y

Temperat.ure
drift

Gain: 200 microvolt/degree C
Offset: 200 microvolt/degree C

Long term
drift

Gain: 2 mY/initial 1000 hr
Offset: 2 mY/initial 1000 hr

To tal mod ul e
output

80 rnA max imum

Vol tage
Output

o to 10.230 V @ 15 rnA maximum

Offset

Adjustable to zero on all outputs

Ga in
accuracy

40 mV maximum interchannel
differential

Current
Output

o to 20
max imum

6-23-16

rnA

0 r

rnA

1 elV

Offset

Ad jus tab 1. e
outputs

Gain
accuracy

Adjustable to 20 rnA on all outputs

Protection

All
outputs are
protected
from
negative overvoltages by reference
diodes to ground and from positive
overvoltages by a 13 V zener clamp.
The current outputs are additionally
protected by a 1/16 A fuse.

Physical Characteristics
Dimensions
Field connector
Environmental
Characteristics

Heat dissipation

ze roo r

rnA

0 n

all

Quad module, triple width, 8-1/2
inch length
Cable
type
BC40A
supplied 50 pin Berg

customer-

Complies with DEC STD 102 Class C.
Operates
in
convection
cooled
environment up to 60 degrees C
ambient.
13 Btu/hr maximum

6-23-17

A631
FOUR CHANNEL 12-BIT ISOLATED D/A CONVERTER
FUNCTIONAL DESCRIPTION
The A631 module contains four group-isolated 12-bit digital to
analog converters (DACs). It offers a choice of voltage or current
outputs, and has the additional capability of retaining its output
levels during a computer power failure. Provision is made for
reading the outputs, resetting all outputs, and reading the
generic code.
DETAILED DESCRIPTION
A simplified block diagram of the A631 is shown in Figure 6-24-1.
At the left of the figure, the unit receives data and control
signals from the D-bus. These signals are transmitted to the
module's four DACs through optical couplers that isolate the
analog circuits from the computer. Digital data bytes are
converted to analog voltages or currents by the four DAC channels
and are output through the field interface connector.
The figure also shows a RAM that stores the output data on the
computer side of the isolation, a dc-to-dc converter that produceS
isolated dc power for the DAC circuits, a precision voltage
reference, and a control section. The following paragraphs
elaborate on individual sections of the block diagram and discusS
the module's control sequences and data flow.
Register Formats
The four DACs of the A63l each occupy two byte addresses, a total
of eight for the module. D~ta bytes written to the DAC registers
are also written in a corresponding RAM location so that the data
written to any DAC can be read by the processor.
A map of the RAM is shown in Figure 6-24-2. The figure shows that
the eight LSBs, D (0-7), of DAC data occupy the low bytes in the
DAC addresses. The four MSBs occupy the four low-order bits of the
corresponding high bytes. The other four bits of the high bytes
can be written to and read, but have no effect on the outputs .•
When the GBIT is asserted, all eight bytes contain the module'S
generic code.
Data Paths
The eight data lines, D(0-7), entering at the D-bus interface
connector, go to the control section for address decoding, to the
RAM for data storage, and to the data isolators for output to the
DAC registers.
The data isolators are optical couplers that allow transmission of
data from the computer to the DACs without any common mode
connection between the two. The addressed DAC accepts the data and
converts it to an analog voltage or current for transmission to
the field through JI.

6-24-1

Aifl
lOUT

I RET

V OUT
V RET
lOUT
I RET

V OUT
V RET
DOUT

lOUT

DEV SEL

I RET

13
14
15
16

37
38
39
40

DIN

LlJ

en
i
tv
~

I
tv

'c::t

LlJ

....
~

VI
;:)

D DIN
D DOUT
D ADDR
D SYNC
D RPLY
D OBIT
o TBIT
o GBIT

DOUT
V OUT
CONTROL

lOUT

ADDR 1
AODR 2
RPLY

V RET

ADDR 0

I RET

CONTROL
ISOLATORS

DBIT
+15V ·15V

+3.3V OR
-10V
REF

+12 V

LlJ

':t
~

E66

I
I

.ISOLATED
POWER
SUPPLY

I
I
I

NOTE:
FOR RETENTIVE MODE
OPERATION: ADD
JUMPERS W1 AND W2;
REMOVE W3, W4, C32, C34. AND
R44;AND PROVIDE +24V DC AND
-24V DC EXTERNAL POWER SUPPLIES.

I
I

Figure 6-24-1

REF SEL SN

I
I
D SYS CLOCK

-15V

INIT

R44

47
48

A63l DAC Block Diagram

g
LlJ

u..

RETENTIVE
MODE
FIELD PWR
+24 V
-24 V

Control Signals
Data transfers to and from the A63l module are initiated by the
processor and are accomplished by DATAOs and DATAIs respectively.
Bus protocol is the same as for other D-bus modules.

TYPICAL
ADDRESSES

LSB

::::~ 1'1 1 1 1,: I,: I: I: I} ~~i~~RITEI
5

DAC 0

07
~~~~~~
__~~__~o~o

MSB~
07

6
DAC'

::: :::

1'1

1 1 1,3,

I,: I~ I: I

6
DAC 2

::::::

1'1
07

DAC

3 ::: ::: 1'16

1 1 1,: I,: I :

ill
00

Is141,~ I,: I: I: I

NOTE
IF THE G BIT IS ASSERTED ALL ADDRESSES
WI LL CONTAIN THE MODULE'S GENERIC
CODE. (262)

Figure 6-24-2

A63l DAC Data Registers

When the processor addresses anyone of the A63l module's eight
addresses, its MY ADDRESS signal is asserted, preparing the module
for a data transfer. The module stores the lower 3 address bits as
ADDR0, ADDRl, and ADDR2. These signals are used to select the
proper RAM location. They are also decoded on the field side of
the isolators to produce one of the LDU (0-3), or LDL (0-3)
sig nal s. These sig nal s strobe new data into the add ressed DAC
register at the proper time in the DATAO cycle. When addressing is
completed, the module is ready for D DIN or D DOUT, according to
whether the program is reading or writing data.
Data is written to the module's RAM at the same time data i,s
written to a DAC register. When the program reads a DAC's output
status, it receives data from the RAM, which normally contains the
latest data written to any DAC register.

6-24-3

When the program sets the TBIT in the CSR of the IDeM, it can then
exercise the module by writing and reading into and out of its RAM
registers without affecting the current or voltag'e outputs.
Setting the CBIT or DBIT resets all the module's DAC outputs to
zero unless the retentive mode is implemented, but does not affect
the contents of its RAM registers. Current and voltage outputs
remain at zero when the CBIT and DBIT are cleared, until new data
is written to them. Note that neither the CBIT, nor the DBIT, nor
INIT will clear the module's memory. In fact, the only way to
clear the RAM is to write zeros in it.
DAC Circuit
All four A631 DAC circuits are identical. A block diagram of one
of them is shown in Figure 6-24-3. Note that all data and control
signals are transmitted through optical isolators, as this part of
the module is isolated from the computer.
The 12-bi t data input to the DAC is in two bytes. The high byte,
which contains the four .MSBs, is wr i tten first and stored in the
holding register. The low byte, which contains the eight LSBs, is
written next. When the low byte is written, it and the four MSBs
in the holding register are simultaneously loaded into the output
register, which drives the DAC. All twelve bits are, therefore,
input to the DAC at once. Note that there is a separclte holding
register for each DAC channel, therefore, operation of the four
DAC channels is totally independent.
Dig ita 1 to a n a log con v e r s ion 0 f
the 12 - bit DA C in put i s
accomplished by a single integrated circuit that contains a
current switching R-2R ladder. Its output is a current that is
proportional to the sum of the weights of the asserted bits of its
12-bit input.
The output of the DAC integrated circuit drives a separate
ope rat ion a 1 am pI i fie r t hat con v e r t s the 0 u t put cur r e n t . 0 f the
1 add er nE!two rk to a propo r tional vol tag e. Th is ampl if i er uses a
precision feedback resistor that is included in the DAC integrated
circuit for this purpose. The output of this amplifier is the DAC
channel's voltage output. The voltage amplifier output is also
input to a second circuit that provides the DAC channel's current
output. Both outputs are connected to the module's field interface
connector.
Although separate voltage and current outputs are provided, they
cannot be used simultaneously. When the module is calibrated, the
DAC reference (see below) is configured according to whether the
DAC is to be calibrated for voltage or current,output. Since, the
reference selection is made for all four DACs, they must all be
used in the same (current or voltage) mode.

6-24-4

VREF
GAIN

DATA
ISOLATORS

HB
HOLD
REG

~________ ~VOUT
OUTPUT
REGISTER

LOU

DAC

RST

CURRENT
CONVERTER

lOUT

-15

+ 0J\I'v"v0 -

0'\

I
tv

LDL---I.~I

CURRENT
OFFSET

I
U1

RST

CONTROL
ISOLATORS

LOU
LDL
RST
MA-5151

Figure 6-24-3

DAC Circuit

Conversion Bit Weights
A vol tag e 0 r c ur r en t 0 u t pu t i s the sum 0 f the bin a r y we i g h t s 0 f
the aSBerted bits in the 12-bit output data regi:3ter. For a
voltage output, the value of the LSB is 2.5 mV (0.0025V), and the
output can be any multiple of that value from zero (no bits
asserted) to a full scale value of 10.2375 V (all bits asserted =
2 • 5 mV x 40 95) •
For example, if an analog output of 2.605 volts is r·equired,
necessary 12-bit binary output word is computed as follows:
E out

the

2.605
=

LSB
=

2.5 X 10- 3

1042 decimal

010 000 010 010 binary

The DAC current output LSB value is 5 microamps, and it has a full
scale range of zero (no bits asserted) to 20.475 m.~ (all bits
asserted). Table 6-24-1 lists the weights of all the bits for both
voltage and current outputs.

Table 6-24-1

Bit Values

Bit No.

Weight
Vol tage
Current
Outputs
Outputs
(mV)
(mic roamps)

0
1
2
3
4
5
6
7
8
9
10
11

2.5
5
10
20
40
80
160
320
640
1280
2560
5120

5
10
20
40
80
160
320
640
1280
2560
5120
10240

Total
(All Bits Asserted)

10237.5

20475

DC Power and Operating Modes
The analog circuits of the A631 module require +15 Vdc. These
voltages are not available on the O-bus, and are supplied by a
regulator circuit, the input of which is either the on-board dc-dc
converter, or external +24 Vdc power suppl ies furnis:hed by the
user.

6-24-6

If, as is normally the case, the on-board dc-dc converter provideS
the dc power, then when computer power is turned off, the analog
circuits (i.e., the DAC output channels) no longer function.
If it is desired to have the DACs retain their existing outputs
d ur ing a compute r po we r shut-down, the use r can impl emen t the
A631's retentive output option.
To implement the retentive mode, dc power for the DAC circuits
must be provided by user-furnished +24 Vdc external powe~ supplieS
(Figure 6-24-4). Jumpers WI and w"2, (shown in the figure) are
added to connect the external power; jumpers W3 and W4, and
capacitors C32 and C42, are removed to disconnect and disable th$
module's dc-dc converter. Not shown in the figure is a resistor
(R44) in the control section that must be removed to disable the
DBIT and INIT functions. These functions must be disabled because
when the computer senses that power is being removed, it asserts
INIT, which would clear the DAC outputs, thus defeating the
purpose of the retentive option.
If the user wants the computer to reset the DAC outputs when its
power goes down, but has an application that requires minimum
noise, he can disable the A631' son-board dc-dc converter, and
provide his own low-noise power supplies. This is accomplished by
making the changes as described above for the retentive option.,
except that resistor R44 is left in the circuit.
TO DACS

____--~A.~---"'"
C32

+15
-15
VDC VDC

C42

-10V OR
+3.3 V
REF

±15 V
REGULATOR

CL
~

f(/)

~
::>

(/)

...J

fZ
LU

W1
'---0-

-0---...,--1

+25 VDC

CL
0

-25 VDC

...J

USER
FURNISHED
POWER
SUPPLIES

~
MA·5250

Figure 6-24-4

Isolated Power Options

6-24-7

Reference Circuit
The A631 includes a stable reference for the DAC circuits (Figure
6-24-5). This circuit provides -10 Vdc when the DAC' s voltage
outputs are used, or +3.3 Vdc when the current outputs are used.
The input to the circuit is +10 V which is provided by a precision
ref ere nee. Th i s i s folIo we d by an 0 pe rat ion a 1 am pI i fie r c i r cui t ,
the output of which is the appropriate reference levE~l. Changing
the reference from voltage to current mode is done before
cal ibration wi th swi tches. The swi tches reconfig ure the ampl i fier
c i r cui t from an in v e r tin g am pI i fie r for the -1 0 V ( v 0> 1 tag e) mod e
to a voltage divider and voltage follower for the +3.3 V (current)
mode. Switch settings are discussed under "Calibration".
Address Selection
The addresses for this module must be assigned according to the
rules stated in Chapter 4. They are selected on the module by the
5-Pole swi tch E15 shown in Figure 6-24-6. An example of one
possible address selection is shown in Figure 6-24-7 to illustrate
the use of this switch.

E66-5

E66-1
AD2700L
10V REF

10K

10K
>-0"---. V REF

300

10.3K

MA-5153

Figure 6-24-5

Reference Circuit

Generic Code
The generic code of the A63l DAC module is 262.

6-24-8

50 49
A
E15
ADDRESS
SELECT

111111"
1

B
2

CHAN {GAIN
3

I OFFSET

CHAN {GAIN
2

I OFFSET

{]I]

~
(]I]

Al
B1

D
D
DDJ
Dill]
D 0\0 0ITIIll

OD
CALIBRATION
ADJUSTMENTS

CHAN{GAIN
1
I OFFSET

CHAN~GAIN
o

I OFFSET

Cill
OD
~

QIO

R44

E66

Ia:rr:nm ISELECT
REFERENCE
1

W2)]~~B
W3

ITllvv4

MA-5127

Figure 6-24-6

A631 DAC Mod ul e

6-24-9

0
8

l.-

[

7
14

1 0 11

V
DETERMINED BY 10CM ADDRESS
SELECTION AND COMMON TO ALL
MODULES IN THE 1/0 SUBSYSTEM

]

210

~El

E15

,.,,.,

DAC MODULE
ADDRESSES SELECTED
= 171260-171267

(J'1

0
->

(J'1

BITNoJ
BIT SELECTION}
0= OFF
1 = ON
MA-5124

Figure 6-24-7

A631 Address Selection Example

Screw Terminal Connections
The reader should refer to Chapter 3, Paragraph 3.8~5, for general
field interface information .. The A63l uses the BC40A screw
terminal assembly. Refer to Table 6-24-2 for this module's screw
terminal configuration.
pi n ConnE~ctions
The A631 module pin connections for Jl,
are listed in Table 6-24-3.

6-24-10

the

I/O cable connector,

Table 6-24-2

Module A63l Screw Terminal Connections
BC49A Screw Terminal Assembly
Screw
Terminal
Number

Field
Channel
Number

1
2
3
4
5
6
7
8

~~~~urn

lout
lreturn

Field +24 Vdc*

{

~~~~urn

11
12
13
14
15
16

Field Power return*

I7
{ 18

lout
lreturn

19
20
02

Vout
Vreturn
lout
lreturn

Field -24 Vdc*

21
22

. 24
{ 25

26
27

28
29
30
03

Vout
Vreturn
lout
lreturn

31
32
33
34

* For retentive mode only -

user furnished

6-24-11

Table 6-24-3
Module
I/O
Connector
Pin

Module A631 I/O Connections

Field
I/O

Module
I/O
Connector
Pin

3
5
7
9

4
6
8

Vout Chan 0
lout
Field +24 Vdc*

Vout Chan 1
lout
Fi eld Power Ret urn

13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

Field Power Return
Vout Chan 2
lout
Field -24 Vdc*

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

40
42

Field
I/O

Vreturn Chan 0
Ireturn
Field +24 Vdc*
Vret urn Chan 1
Ireturn
Field Power Return

,
Field Power Return
Vreturn Chan 2
Ireturn
Field -24 Vdc*

Vo ut Chan 3
lout

46
48
50

Vreturn Chan 3
Ireturn

* For retentive mode only - user furnished.
APPLICATION NOTES
1•

'rh e c ur r en t 0 u t pu t s 0 f the A63 1 co v e r the r an9 e 0 f 0 - 2 0
mAe If it is desired to use this module as the source of
an industry-standard 4-20 rnA signal, the 4 rnA offset must
be provided by the application software. While this
approach decreases the DAC's resolution by 20 percent, it
has the advantage of protecting the process from certain
types of computer failures. For example, if the computer
fails in a way in which the I/O subsystem is reset, the
DAC outputs will go to zero (except in retentive mode) •
']~he
process then interprets this condition (DAC output
less than 4 rnA)
as an error, and takes appropr iate
fail-safe action.

6-24-12

If the user requi res retentive outputs (i.e., outputs
that are unaffected by a computer power failure), he must
provide +24 Vdc power to the module. He must also add
jumpers WI and W2, remove jumpers W3. and W4, remove
capacitors C32 and C42, and remove R44. The location of
these components is shown in Figure 6-24-6. Note that
high frequency noise on the outputs of the user-furnished
+24 Vdc power suppl ies wi 11 be re fl ec ted to some ex ten t
Tn the DAC outputs. For best results these power supplies
should be the linear regulated type.

Wh e n t h e r e ten t i v e f eat u r e o f the A6 31m 0 d u 1 e i a
implemented, the user must also implement whatever;
circuit changes may be necessary to update the system
IOCM. That is, the IOCM circuit must be the revision
level listed below or later.
IOCM
M7958
M7959
M8719

Circuit Schematic
Rev. Level
H

A*
C

* All versions of the M7959 are usable without modification.
Configuration Constraints
If the retentive feature of the A631 module is implemented, the
module's current requirements are partially served by the external
field power supplies, and there are no system constraints imposed
by the A631. In addition, use of A63ls in the voltage mode does
not constrain the system. However, if the retentive feature is not
implemented, each A631 module, when used in the current mode, can
d raw up to 4 50 rnA from its + 1 2 V po we r s u pp 1 Y • If mul tip 1 e
current-mode A631 modules are used in a single chassis (or in two
chassis powered by the same power supply), there exists the
possibility of overloading that power supply, causing improper
operation of the subsystem. This situation is avoided by observing
the following configuration guidelines for each type of chassis.
H334-E and H334-J Chassis - Each of these chassis contains its own
H7872 power supply. Maximum current for this supply is 4 Amperes.
Overloads are avoided by observing one of the
following
guidel ines.
1.

Leave one slot unused. All nine remaining slots can then
be filled with current-mode A631 modules. The unused slot
must have an M90l9 continuity module, unless it is the
last slot in the I/O subsystem.

Use five or fewer current-mode A631 modules; the
remalnlng slots can be used for any other module types
(including voltage-mode A631 modules) •

6-24-13

Use 6,
7, 0 r 8 curren t-mode A631 mod ules , and rna ke
certain that the remaining current capacity of the H7872
power supply is not exceeded by computing the total
current requirements of the modules used in the remaining
slots.

H334-A, H334-8, and H334-X Chassis- These chassis are powered in
pa irs by the H7870 power suppl y (Chapter 1, Paragraph 3. 3.1; and
Chapter 3, Table 3-1). The maximum current for the +1:2 V portion
of this supply is 6 A. Since it usually powers two chassis, the
current requirements of all modules in both chassis must be
computed to make certain that multiple current-mode A631 modules
do not overload it.
H333-A and H333-8 Chassis - Each of these chassis is powered by a
separate H7870 power supply. Although this chassis accommodates
only eight I/O modules, its +12 V power supply also powers the
IOCM and any other LSI-II modules that are present. The user must
compute current requirements for all these modules, and make
certain that the use of multiple current-mode A63l modules does
not overload the +12 V power supply. In addition, the total power
del ivered by the power supply must be calculated (both +5 V and
+12 V supplies) and determined not to exceed 122 watts.
Calibration
The DAC module is accurately calibrated at the factory and is
ready for service in the voltage mode when received by the user.
The customer may wish to change from the voltage to the current
output option. This necessitates recalibration of the module.
When calibration is necessary, it is accomplished by means of
diagnostics included with the I/O subsystem. Instru.ctions for
using these diagnostics are included with the software package.
Iden ti f icat ion 0 f adj us tments and swi tches is prov ided in Fig ure
6-24-6 • .7\ careful study of this figure is recommended to avoid
selecting the wrong adjustment during the calibration procedure.
Details of the reference voltage selection switches are shown in
Figure 6-24-8. These switches should be operated only when
changing the DAC outputs from voltage to current or vice versa.
Proper placement of the meter leads and precision res.istor used
d ur ing current mode cal ibration is essential to achieve a val id
result, and is illustrated in Figure 6-24-9.
To ensure compliance with specifications, all test equipment used
for calibration of the A631 must have been accurately and recently
cal ibrated. In add i tion, personnel doing the cal ibration should be
familiar with procedures for aligning precision analog equipment.
If you are not sure of the foregoing, DO NOT ATTEMPT TO CALIBRATE
THE A631. Factory calibration is probably better than that which
you will be able to accomplish.

6-24-14

E66 OtN 11\1\ 0\1\ 0\1\ am
"-------t
NOT

-10 V REF SELECTED
(FOR VOLTAGE OUTPUTS)
1 = ON

a = OFF

USED

- 3 . 3 V REF SELECTED
(FOR CURRENT OUTPUTS)

E66 0tNI1\0\1\0\1\0\1EJ
~---t

NOT
USED
MA-5125

Figure 6-24-8

Reference Voltage Selector Switches

SCREW
TERMINALS

~
CUSTOMER
FURNISHED
500 OHM
RESISTOR
(.01%)

TO CALIBRATION...---{
INSTRUMENT

=:;':::======1/
LEADS
MA-5126

Figure 6-24-9 Resistor and Meter Lead Placement
For Current Mode Calibration

6-24-15

CAUTION
The system must be powered down before
inserting or removing any module.
Equipment Needed
Re si sto r

500 ohm, 0.01 percent,
part no. 13-09985-00

Voltage reference

EDC model MV105G or equivalent

0. 3 W,

DEC

SPECIFICATIONS
Power Requirements From I/O Subsystem
Main supply: VS = 12 Vdc + 2 Vdc - 1
Vdc
Backup supply: VB = 14 Vdc > VB >
(VS - 0. 7) Vd c

Voltage

Current:
Current mode:

Main supply: 450 rnA maximum
Backup supply: 10 rnA maximum
Total: 460 rnA maximum

Vol tag,e mode:

Main supply: 350 rnA maximum
Backup supply: 10 rnA maximum
Total: 360 rnA maximum

Retentive mode:

Main supply: 90 rnA maximum
Backup supply: 10 rnA maximum
Total: 100 rnA maximum

NOTE
If the backup supply is not implemented,
the main supply provides the total
currents listed above.
Power Requilrements From Optional Field Power (Retentive Mode)
Vol tage:
Current:
Current: mode:
Vol tage mode:

+ 24 Vdc + 3 percent
- 24 Vdc + 3 percent
+ 24 V s uppl y: 100 rnA maximum

- 24 V supply: 150 rnA maximum
+ 24 V s uppl y: 120 rnA max imum

- 24 V supply: 40 rnA max imum

6-24-16

Output Characteristics
Voltage Output
Range:
LSB:
Max current output:
Gain ~ccuracy:
Gain temp. coefficient:
Offset:
Of f se t tem p •
coefficient:
Integral nonlinearity:
Differential nonlinearity:

10.24 V
2.5 mV
+5 mA
Adjustable
30 ppm of full scale/oC maximum
~1/2 LSB maximum
+50 microvolts/oC maximum
~1/2 LSB maximum, over temp.

range

1 LSB maximum, over temp. range,
monotonic over temp. range

Slew rate:

0.1V/microsecond (with a load of
2 kohms in parallel with 150pf)

Output noise:
(peak to peak
with 2 kohm load)

2mV from 10 Hz to 10 kHz
20mV from 10 Hz to 100 kHz
150mV from10 Hz to 1 MHz

Capacitive loading:

0.1 microfarad will not cause
instability but will degrade
settl ing time

Set tl ing time:
(to 0.01% of final
val ue)

150 microseconds (with a load of
2 kohms in parallel with 150 pf)

Channel interaction:

1/2 LSB maximum change in output
over the temperature range, with
a full-scale change in all other
outputs

Current Output
Range:
LSB:
Maximum load
resistance:
Gain accuracy:
Gain temp. coefficient:
Offset:
Offset temp.
coefficient:
Integral nonlinearity:
Differential
nonlinearity:

0-20.48 rnA
5 microamps
500 ohms
Adjustable
30 ppm of full scale/oC maximum
Adjustable
0.4 microamps/oC maximum
LSB maximum, over temp. range

~1/2

1 LSB maximum, over temp. range,
monotonic over temp. range

6-24-17

Slew rate:

0.2 rnA/microsecond (with a load of
500 ohms in series with 1000 microhenrys

Output noise:
(peak to peak with
a 500 ohm load)

4 microamps from 10 Hz to 1 kHz
40 microamps from 10 Hz to 100 kHz
300 microamps from 10 Hz to 1 MHz

Settl:lng time:
(to 0h0l% of final
val ue)

100 microseconds (with a load of
500 ohms in series with 1000 microhenrys)

Channel interaction:

1/2 LSB maximum change in output
over the temperature range, with a
full scale change in all other
outputs.

Isolation
Isolation voltage:

1000 Vdc
1000 Vac peak

Common mode source:

200 VA for UL approval

Common mode rejection
ratio ::

120 dB
70 dB
70 dB
60 dB
30 dB

from dc to 60 Hz
at 10 kHz
at 100 kHz
at 1 MHz
at 10 MHz

Physical Characteristics
Dimensions:

Quad module, triple width,
8-1/2 inches long

Field connector:

Cable type BC40A or customersupplied 50 pin Berg

Environmental
Characteristics
Heat dissipation:

Complies with DEC STD 102 Class C.
Ope rates in convection cool,ed
environment up to 60 0 C ambient.
22 BTU/hr maximum

6-24-18

BC4r2JL
SIGNAL CONDITIONING SCREW TERMINAL ASSEMBL~
FUNCTIONAL DESCRIPTION
The BC4r2JL is a more versatile alternative to the BC4r2JA screw
terminal assembly. In addition to the standard screw terminals, it
offers a convenient means of inserting signal conditioning circui~
components in to the I/O field in ter face. It ma kes po ss ibl e the
addition of series and/or parallel components to each interfacie
circuit.
Typical
uses
include
the addition of pull-ups,
attenuators,filter~, etc.
DETAILED DESCRIPTION
The BC4r2JL (Figure 6-25-1) is a specially designed screw terminal
assembly. It is similar to the BC4r2JA in that it has a screw
terminal field interface, and a Berg connector module interface:.
With the ex c e p t ion 0 f term ina 1 1 7, i t ma k e s t h e sam eel e c t ric a 1
connections between these two. It is dissimilar to the BC4r2JA ih
that it is larger (23.4 X 32.5 cm = 9.2 X 12.8 in), has a Berg
connector I/O interface (can be connected directly to the ATR16),
and ha s t u r ret term ina 1 s for qui c k and e as yin s tall at ion 0 f use rr
designed signal conditioning circuits.
Each printed circuit conductor path from the field interface to
the module interface is broken in two places. These breaks are
bridged with wire jumpers (zero ohm resistors) that can be removed
easily to allow the substitution of other series components
(Figure 6-25-2 shows the schematic of two of those circuit paths.)
Turret terminals are provided at these breaks so that the new
series components can be mounted easily. In addition to these
terminals are others that connect to two
independent common
potential buses (V x . and V.xRET~ as well as some. that are no!t
connected to anytlilng. Tne -Vx and V XR T termInals providie
convenient power connections for aevices sucEH as pull-ups or zene:r
diodes. The uncommitted terminals are provided so that they can be
used as convenient tie points in more complex circuits.
INSTALLATION
The BC4r2JL is the same height as, but wider than, a BC4r2JA; and i:s
installed in an H332 chassis in the same manner as a BC4r2JA. rt
merely extends deeper into the chassis. Mounting hardware and
plastic covers are provided. The plastic covers are for the safety
of operating personnel and must be installed after field wi ring is
completed. The proper way to install the I/O module cable and the
ATR16 cable (if used) is shown in Figure 6-25-3.
APPLICATION NOTES
General
BC4r2JL screw terminal and Berg connector (J 1) inputs are parallel.
The Berg connector input is provided to accommodate an ATR16 cable
which normally plugs directly into an A157 or Ar2J2r2J. This does not
cause any change in the field wiring to the ATR16 for these
devices. It remains the same as listed in the ATR16 section of
thi s manual.
6-25-1

2
W69

-c::r-

\-c:::J-.../ ''---C:r-'
0
0

0
0

-flW36
I

,,-C:J-\ /-[=~-\
~
,~, ,r-C=J--\
0 _____0____~ ___ ~ ____ ~ ~3:"' _ _ CL ___~____0_ _
q
Q
P
I
Q
Q
P

\--c:J-" '~'

o
o

,~, ",......CJ----

'~' ''-Cr-l
0
0

0 10

.......r--t...-

00
,~\ ,~,
O-----C!.----tL- __ ~ _____ ~-- _. __d_ ___~___ _
o
~
P
I
000
o
\-c::J--' \--c:J--I
0 10
''--C:J-'' ''---C:J--'
o 2
0
0
0
12
0
0
o
,r-C:::J--\ ,~,
0 10
,~,/-~,

q,__ _

o
o

'--c::J--" \\..-o-j
o
0

0 10
0

,r-C::::J--\ ,~\

''-C:J--' ''---C:J--'
0

5
6
7

0
0

10
11

0------ - - - - - - - - - - - - - - - 0 - -- - - - - - - - - - - - - - - -

0
0

14
15

,r-C:::r-\ ,~,

o- - - - -'6- - - - -b- - - - - - -'0 - - - - - 0 ----tt - - - - -b - - 0---1\
Q
P
I
Q
Q
9
o
""'\-c:::J-,' '--c:J--;'
0, 0
\-c:J-./ ''--C:::J-.../
o 4
0
0
0
14
0
0
o
,~, ,,--c::J--,
0 10
,~, ,re:]-\

0
0
0

16
17
18

o
~
b
I
0
6
'0
0--,-------------------0------------------o
~
p
,
Q
~
P
0
o
\-c:::J--/ \-cr·..,,'
\-c:::J-/ ''-C::J--'"

0
15
0
0
I
o
,~\ ,----0-..
00
...t,.-c::J--.'.tr-C:J--.,
o
\0
I
'"
'"
«:>
0-- - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - o
0
P
,
0
C)
P
o
\-CJ--/ ''---CJ-''
0 10
\-c::J-,.,' ''---C:J--'

°,

,,~, ,r-C:::J--\

,r-C:J--., ,~,

0:0

O __ .__ ~_____ ~_____b______ ()_------~----~--- 0 __
Q
~\
P
I
0
Q
«>

o
o
o

\--c:J--' \--C}-'/

,r-C:J-,.

,~,

0,0
0
I
00

''---C:J-t'

0
0

--c=:r
W17

23
24

\-c:J-j

--co=r-- W34

29
30
31
32
33
34

MA·4865

Figure 6-25-1

BC40L Screw Terminal Assembly

6-25-2

TURRET
TERMINALS

I
BERG OR
SCREW
TERMINAL
INPUT

SERIES
JUMPERS

SCREW
TERMINALS

0
2

) OUTPUT
TO I/O
MODULE

MA-5277

Figure 6-25-2

BC40L Circuits with Jumpers

6-25-3

FROM
ATR16

STRIPEON

RIGHT

1 ~~~-B-C-4-0-L------~------+I--------~I----------~

~ I,{-\ .---", ,..~,

-i

{:l. . .." J1 .... ,/

.... 'I N

r~_~_:===-~~__~~__~__L_L_______. ____~_~-L_'_'U ~~-~
__

____

-I

-I
-I
-I

-I

INSERT
CABLE-FREE SIDE
OF CABLE CONN. FLUSH

FRONT

J1 AND J2 ON
SIDE 1 Of TERM
BOARD

SIDE 2

CABLE COLOR
IS GREY
/
TERMINAL CHASSIS
- - - - - - - - - - - - --STRIPE ON-- - - - - - RIGHT
H334 CHASSIS

INSERT
CABLE
FREE SIDE
OF CABLE
CONN.
FLUSH
TO I/O
MODULE

I/O MODULE
COMPONENT SIDE

50.49
50

STI~IPE ON

2,1

BOTTOM FRONT

MA-5128

Figure 6-25-3

BC40L Cable Installation

6-25-4

If the interfacing module is not an A157 or A020, then power is
not available from the module, and any power requirements of the
signal conditioning circuits must be met with a user furnished
ex te rna! power suppl y connec ted to screw te rm inal s 1 7 and 18. In
most cases, this will require at least the removal of jumper W17
to isolate screw terminal 17. This is because, in most cases the
corresponding module terminal is common. It may also require the
removal 0 f jumpers W34 and W3 5, depend ing on whethe r or no t the
user needs to isolate his field circuit ground from the computer
ground. The user must consider each type of module interface
i nd i v id ua 11 y •
I/O Connections
Except as noted above for terminals 17 and 18, field wiring
con f ig urat ions for the BC40L screw te rm inal s are the same as fo r
the BC40A, and are listed for the individual modules elsewhere in
this chapter. Some of the more common ones are grouped together in
Table 3-2 of Chapter 3.
When. using the BC40L screw terminals, all field wire connections
are the same as when using a BC40A with the possible exception of
terminals 17 and 18. The status of these terminals depends on
several factors and is best visualized by referring to Figure
6-25-4. This figure is a much abreviated schematic of the BC40L,
but it illustrates the key points
(a complete schematic is
included in the BC40L print set).
The important electrical difference between the BC40L and the
BC40A is that screw terminal 17 and its connection to the module
interface, J2, are isolated from screw terminal 18. As the figure
shows, the circuits connected to screw terminals 17 and 18 have
several wire jumpers. These jumpers allow some flexibility in the
use of terminals 17 and 18.
For example, if the interfacing module is an A157 or A020, and the
signal conditioning circuits being added require power, there are
two power options. First, the user can provide an external power
supply for these circuits and connect it to the common potential
buses via screw terminals 17 and 18. In this case, jumpers 17, 34,
and 35 must be removed to isolate the voltage on these buses from
the module and the ATR16.
Second, if +12V is sui table for the signal cond i tioning c ircui ts,
and current requirements are modest, then the +12V ATR16 power
from the module can be used for the BC40L common potential buses.
This is done by leaving the jumpers intact and turning on the
appropriate module switch (i.e., E30-4 on the A157, or E6-l0 on
the A020). Note that this can be done whether an ATR16 is being
used or not.
CAUTION
Maximum additional loads on the +l2V
module power from the A157 and A029
modules must not exceed 95 and 145 mA
respectively.
Using the +12V module
power option for loads greater than this
will cause improper operation of the
subsystem.
6-25-5

(21-24)
(26-30)
r-~

----@
l-+_ _ _....L--+_~-~-_+----o-~5~ -0- '!!.12.8-o--

~-------'---l----l----.-

- - 0 - ~~ -0- '!l.6J.-o---

l-+------L--~--

---o-~~0_o_'!!.~_o__

Vx TERMINALS

I W69

6
~--~----~~w~~~l---~--0-0

W36...... /
r-+---r--------~

I W35

W34' I
VXRET

~----------------~H
(21-25)
(27-30)

1
I
I

I
BC40L

cb
Ml\-4810

Figure 6-25-4

BC40L Simplified Schematic

Channel Number and Component Identification
Dotted lines have been included in Figure 6-25-1 to emphasize the
iterative patterns of terminals, components and field channel
numbers. Part of Figure 6-25-1 is repeated in Figure 6-25-5 which
identifies these items and explains the significance of markings
on the printed circuit board. Table 6-25-1 corrE!lates cell
numbers, screw terminal numbers, and Berg connector pin numbers.
Application Examples
Schematics and component layouts of ten
implemented using the BC40L are shown
6-25-7.

6-25-6

circuits that might be
in Figures 6-25-6 and

TOP 3 AND
UNCOMMITTED

SERIES

CELL

BOTTOM 3
TERMINALS ARE...-------,

FROM SCREW

o_N~rM:;*-JUM~ER~~71~A~~~i- TERMINA~S____ ~~~~~~~~ __ _
•

•

0--

••

• •

tr::::h ~
,
~ r-C:J---,
cS
\/
\
.1
---'--~----1----- O______d____~ ___ Q~ _____ _
I

•

FROM SCREW
TERMINAL 12
~------------------~-.---------------.------~

THESE 3 TERMINALS ARE
ALL COMMON TO Vx
NOTES
1.

EACH TERMINAL GROUP CELL HAS SIX
TERMINALS (SHOWN BLACK) THAT ARE
NOT CONNECTED TO ANYTHING, THEIR
PURPOSE IS TO SERVE AS CONVENIENT
CIRCUIT NODE TIE POINTS,

EACH CELL IS IDENTIFIED BY A NUMBER
ON THE PRINTED CIRCUIT BOARD, AND
IS ASSOCIATED WITH TWO SCREW TERMINALS (TABLE 1). FOR EXAMPLE, CELL
NUMBER 5 SHOWN, IS CONNECTED TO
SCREW TERMINAL S 11 AND 12, THE
SCREW TERMINAL SIDE OF THE CIRCUIT
AS VIEWED IN THE FIGURE IS ON THE
RIGHT, AND THE MODULE SIDE ON THE
LEFT IN ALL CASES,
MA·4811

Figure 6-25-5

Channel Number and Component Identifications

6-25-7

Table 6-25-1
8 C40L Turret
T;erminal
C ell

Number

Terminal Identification

Screw
Terminal
Number

Pin Numbers
J2
Jl

(21-24)
(26-30)

(21-25)
(27-30 )

12
t

6-25-8

Table 6-25-1
BC40L Turret
Terminal
Cell Number

Terminal Identification (Cont)

Screw
Terminal
Number

Pin Numbers
Jl
J2

6-25-9

~~,----~o------1
o

',-c:::::J-/

000
a/re:::::J-",'Q'/-c:::::J-, "'0

0 I0

0 :0

0-- - - --- - -------.-------6
LOW PASS FILTER (SINGLE EI\JD)

0- - - - - - - - - - - - - - - -- - - - -

O~)
o

TOT

-"""9
010

?
010

o-------------------~

BALANCED LOW PASS FILTER

---r

~--o~,:;:,f;~'p-----+
o

rCONTACT PROTECTION

,.-c:::::I--,~,'-c:=::J-"

0 I0
I

'0"

~----------"::------o

0-----------------------<;:>
o

0
0
0----- - - - - - - - - - -

INPUT

010

01 0

--.------6

AC MEASUREMENT CIRCUIT

:J [

o----p·~----E----------T
"-c::~/
0 ~0

~
o

0 :0

/-c:::::J-'"

0------ - - - - - - -

----------.0

PROTECTION CI RCU IT
MA-5282

Figure 6-25-6

Application Examples

6-25-1"

~~-----D-----1

"'-c:::::J-,/

0 I0

000

/,-c:::::J-",

0 :0

,/-c:::::J-'"

0- .- - - - - - - - - - - - - - - - - -

--<:>

SINGLE END ATTENUATOR

PULL-UP

0-.-- - - - - - - - - - - - - - - - - - - - 0

oo Q"-c::=Y/A,'-C:::}-'//>o
o

/--c::::J-..,

/~,

0-------- --- ------- - - ~
3-WIRE RTD BRIDGE CIRCUIT
(RTD APPLICATION NOTE AVAILABLE ON REQUEST)

~---~-----o}
o

0:0

o---------------------~

BALANCED ATTENUATOR

~----------------~
,
p . . o_r\.r-O-Q
I0

o
o

0 I

',-c::::J-/

0
/-c::::J-'"

~------~------6

(NOT COMPUTER GROUND)

GAS DISCHARGE SURGE ARRESTER

Figure 6-25-7

MA-6283

Application Examples

6-25-11

A158
RMS INPUT MULTIPLEXER
FUNCTIONAL DESCRIPTION
The A158 RMS input mu1 tip1 ex er 0 ffe r s a means 0 f mon i to ring ac
voltages, currents, and power consumption. It is particularly
useful in power control and energy management applications. It is
an analog multiplexer, and is intended to be used with the A014
analog input subsystem on the D-bus.
The module accepts up to eight pairs of voltages, and eight
current input signals (Figure 6-26-1). A multiplexer selects a
voltage input signal, and its corresponding current input. These
are amplified and input to separate RMS-to-dc converters, and to a
multiplier and averaging circuit. Three dc voltages are produced,
represen ting the RMS vol tag e, the RMS cur ren t, and the av erag e
power of the selected inputs. These voltages, along with a fourth
(a calibration reference), are input to the module's output
multiplexer. One of the four, selected by the processor, is routed
to the A0l4 via the D-bus, where it is converted to digital data.
The A158 is a product of DIGITAL's Computer Special Systems group.
Additional information is available in CSS document number
YM-C152C

A 158

VRMS

11
INPUT
MUX

AC
IN

PAVE

I RMS

V TEST

Fig u r e 6·"- 2 6-1

OUTPUT
MUX

DANA SIG

.... TO
A014

A158 Block Diagram

6-26-1

CHAPTER 7
SERVICE PROCEDURES
7.1
SCOPE
This chapter provides enough information to enable a person with
mlnlmum exposure to the I/O Subsystem to effect a repalr ln
minimum time. Throughout this chapter, the reader is referred to
sections in other chapters where more detailed information may be
found about items such as switch settings, configurations, etc.
This chapter concludes with a trouble analysis flowchart (Figure
7-2) that illustrates a logical approach to fault isolation. The
chart is intended only as a useful guide to trouble analysis and
does not exhaust all possibilities for system malfunction.
WARNING
Remember that the I/O Subsystem is a
process controller, and its I/O modules
may well control very sophisticated and
perhaps
even
dangerous
industrial
processes. Therefore, before initiating
any diagnostics that may affect field
signals produced by the I/O modules,
always check with the customer for any
safety precautions and any restrictions
on the operations that can be performed.
7.2
REQUIRED EQUIPMENT AND MATERIALS
In addition to standard hand tools, probes, etc., the following
e qui pm en t a n d mat e ria 1 s are r e qui red t o p e r for m m a i n ten a nee
procedures. The two dual extenders serve as a single quad.
Digital voltmeter
Osc i 110 scope
Vo 1 tag e stand ard
Module extenders
Di ag no st ic
Print set

Weston Schlumberger model 443 or equivalent
Tektronix model 465 or equivalent
E.D.C. model MV105G or equivalent*
Two W900 (multilayer extenders must be used)
MD-ll-CVPCAD-0
B-TC-H333

7.3
SPARES
It is recommended that the customer stock one spare for every ten
modules (or fraction thereof) of a given type. The following fuses
should be stocked in quantities of five each.
Fuse Type

DEC Part No.

Where Used

picofuse 62.5 rnA

90-09122

M50l0, M50ll, M50l6, A630

Picofuse 1 A

12-10929-02

M6010, M6011, M5014, M6010-YA,
A014, A156, A157, M6014

*The voltage standard must have been accurately calibrated within
the last six months to achieve acceptable calibration of analog
I/O mod ul es.
7-1

Picofuse 0.5 A

12 -0 91 5 9 - 0 0

A020

Picofuse 2 A

12-11751

M6012, M6015

Special

12-12442

M6013

6.25, A 250 V, SB

90-07223-00

H7870 power supply ( 115 V)

3 A, 250 V, S8

90-07218-00

H7870 power supply (230 V)

2 A, 250 V, SB

9007216-00

H7872-A power supply (115 V)

1.5 A, 250 V, S8

9007213-00

H7872-B power supply (230 V)

WARNING
Use of any fuse other than the one
specified for the M6013 module may
res u I t i n per son a l i n j u r y, e qui pm e n t
damage, and/or improper operation. The
module is equipped with a spare holder
for this fuse to ensure that one is
always conveniently available.
7.4
ADJUSTMENTS
Adjustments may be required for the power supplies and the analog
I/O modules. Adjustment procedures for analog I/O modules are part
o f t he ][ / a sub s Ys t em d i a g nos tic pro g ram. Lo cat ion s 0 f the
adjustments on these modules is shown in Chapter 6 of this manual.
Power supply adjustment procedures are given below.
7.4.1
H7870 Power Supply Adjustment
Power supply voltage measurements can be made without removing the
power supply; however, if adjustment is required, the supply must
be removed. The adj ustment potentiometers (marked on the modul e)
are located on the printed circuit board inside the supply (Figure
7-1). Adj ust the power supply as follows.
1.

lRemove power supply cover and sl ide power
until access to the adjustments is possible.

supply

out

NOTE
In order to slide the supply out far
enough to access the adjustments, it may
be
necessary
to
unplug
the
console/backplane interface cable. If
this is done, proper orientation of the
connector
must
be
observed
when
reinstalling it (Chapter 3, Paragraph
3.3.4 and Figure 3-14).
2.

}\t tac h DVM probes
HETURN (R).

fron t

7-2

panel

test

po in ts + 5 V and

H7870 POWER SUPPLY
VOLTAGE ADJUSTMENT POTS -~--=~
ON P.C. BOARD UNDER COVER

H7872 POWER SUPPLY
R6 VOLTAGE ADJUST
SLIDE CHASSIS FORWARD
TO ADJUST R6 THROUGH
ACCESS HOLE ON BOTTOM

Figure 7-1

+
12V TEST
POINTS

Power Supply Adjustments

Vol tage read ing should be +5.1 V +0.15 V.

If reading is out of tolerance, correct by adjusting the
+5 V potentiometer.

Move the (+) DVM probe to the +12 V test point.

Reading should be +12 V +0.36 V.

If reading is out of tolerance, correct by adjusting the
+12 V potentiometer.

Sl ide the
cover.

supply back

into

7-3

the

frame

and

replace

the

7.4.2
H7872 Power Supply Adjustment
Calibration of the H7872 +12 V output is accomplished by adjusting
R6, which is accessible when the power supply is pulled forward in
its chassis. Access for the adjustment tool is throu~Jh a hole in
the bottom of the power supply drawer (Figure 7-1). If adjustment
is necessary, proceed as follows.
1.

Remove the two screws that fasten the power supply to the
chassis and slide it out until access to R6 is possible.

Attach DVM probes to
-12 V.

Voltage reading should be +12 V ±0.36 V.

If reading is out of
(Fi 9 ur e 7 -1) •

Sl ide the power supply back into the chassis and
the fastening hardware.

the

front

tolerance,

panel

test

points +

and

correct by .adjusting R6
replace

7.5
CORRECTIVE MAINTENANCE
Correct:ive maintenance has been simplified in the I/O Subsystem.
Mo s t
fa i 1 u res can b e l 0 cat e d i n min i mum tim e by us i ng the
main tenance tool s avail abl e. Th i s sec tion incl ud es main tenanc e
feature descriptions and maintenance tips, which should be
understood when solving a problem, and a corrective maintenance
approach listing the basic failure analysis techniques. The flow
diagram (Figure 7-2) is a useful guide to fault isolation.
7.5.1
Maintenance Features
The following is a list of maintenance features built into the I/O
Subsystem.
1.

Maintenance bit -

a CSR bit that provides two functions:

It generates a maintenance interrupt when the
interrupt enable bit is set. After the j'.nterrupt is
accomplished, reading the IAR (interrupting address
register) returns the low byte of the C:SR (control
s tat us r eg i s t e r) ad d res s ( 3 7 7) •

With the maintenance bit set, reading any address
returns the low byte of that address, whether or not
there is a module with that address installed in the
subsystem.

Some input modules are able to read the compl(~ment of the
input data when the TBIT is set in the CSR. Many of the
other modules have an additional built-in test capability
that is activated by the TBIT.

Output modules are able to
written out to them.

7-4

read

back the data

that was

M = MAP OF D-BUS
S '" SYSTEM TEST
D = DIGITAL MODULE TEST
A = ANALOG MODULE TEST
1= 10CM TEST
X '" EXERCISER
T '" SET SWITCH REGISTER
YES

RUN I

ADJUSTMENT
PROCEDURE
REF.SEC.7.3

CHECK FOR
SAME ADDR.
OVERLAPPING
ADDR

YES

MULT

YES

CHECK PWR
ON BACKPLANE;
ADDR. SWS.

NO
BACKPLANE.
CABLES.
HARNESSES
SET SWITCHES
PROPERLY

,---------~~,------~
{IF SYSTEM GOES ON LINE

AND SUSPECT BIT IS STILL
FAULTY. CHECK SCREW
TERMINAL CONNECTIONS
FOR PROPER I/O OPERATION
AND CONTINUITY OF
SCREW TERMINAL CABLE.

MA-0177
MA-0118

Figure 7-2

I/O Subsystem
Trouble Analysis Flowchart

7-5

The A/D converter module (A0l4) has an on-board ramp
feature that allows a basic check of the analog circuits.

The D/A converter module (A630) contains circuits that
allow the outputs of the four channels to be compared and
the result of the comparison sent back when the module i~
read.

All modules can have their
setting the DBIT in the CSR.

7.5.2
Maintenance Tips
The following tips are important when
the I/O Subsystem.

inputs/outputs

performing

disabled

maintenance on

Isolate the I/O control module. In an IPll or IP300
system, this is accomplished by removing the first I/O
module; in an IPl10 or IPV10 system, unplug the D-bus
cable from the M87l9 I/O control module.

Ensure that an I/O failure is not common to all I/O
modules. For example, if you attempt to read a modul e' S
data and receive the low byte of the module's address,
and 0 the r mod ule s reac t the same, the probl em is mo s1:;.
likely to be in the control module.

I/O module addresses do not have to be contiguous.

I/O modules use from 8 to 64 bits depending on the type.
Data is in 8-bit bytes; therefore, a 32-bit module has
four bytes and requires four addresses. Module addressep
must not overlap, i.e., if a 4-byte module has it$;
address set to 1 71000, the next module must have it~
address set to 171004 or higher. If its address were set
to 171002, an overlap condition would exist. Moreover,
I/O module addresses must not overlap the CSR or the IAR,
e.g., a 4-byte module cannot have its address set to
171374.

Multibyte modules must use appropriate address boundaries
as discussed in Chapter 4, Paragraph 4.2.1.

The d iag nost ic pr in ts an I/O modul e map (when the 1M
option is selected), giving module types and addresses.
The list begins with the lowest address. The listing will
not match the physical module layout unless the addresses
have been assigned in ascend ing order on the D-bus. Fo r
instance, the following situation might occur.

7-6

Physical Module Layout

Printed Map

Slot

Module

Address

Module

Address

M5012
M5010
M6010
M5013
M6013
M5011

771000
771020
771004
771015
771014
771010

M5012
M6010
M5011
M6013
M5013
M5010

171000
171004
171010
171014
171015
171020

2
3
4
5
6

NOTE
In addition to the module number
address, the module map includes
full name of the module.

and
the

All modules have switches for selecting addresses. These
switches should be checked before replacing a suspecit
module.

A no tebook conta in ing . the I/O mod ul e config ur at ions and
o the r pe r tin en t i n form a t ion will no rm all y be ma in t a i ned
in the vicinity of the system. When running the map
option of the diagnostic, this list should be compared to
the notebook to ensure that all I/O modules hav'e
responded.

If there is an empty slot(s) between I/O modules o:r
between the IOCM and the first I/O module, a continuit!y
module (M9019) must be installed in the C and 'D
connectors of the empty slot(s).

10.

'Jlhe M7958 (IOCM) must be the last LSI-II option on
LSI-II BUs, not counting the bus terminator.

11.

An I/O module or the IOCM must never be plugged into o'r
removed from the subsystem with system power applied.
This invariably damages the modules.

12.

The IOCM and the I/O modules use CMOS logic; if failureis
require
that
ICs
be
replaced
on
these
modules,
precautions for handling static-sensitive components must
be used.

13.

On subsystems wi th mul tipl e po we r suppl ies, syste'm power
should be controlled by the master power switch either on
the H333 or PDP-II CPU. If power supply problems require
that individual power switches be cycled, the entire
subsystem must be powered down and the I/O modules
removed from the suspect chassis. After the modules are
removed, the individual power switch for that chassis can
be cycl ed.

7-7

the

14.

If problems appear to be in the field wiring, the LEOs on
the I/O modules should be checked for proper installation
and seating. If a LED has become unseated, reinstall it
with the cathode toward the dot etched on the printed
circuit board.

15•

Th ere are tim i n g
res t ric t ion s
t hat a f f E~ C t
programming (Chapter 4, Paragraph 4.5.4).

16.

Memory refresh should be performed only by the MSVll-C or
MSVll-O memory modules. Refresh by the CPU or by the
REVll-A must be disabled or improper operation will
result.

S Y s tern

7.5.3
Basic Failure Analysis Procedure
Throughout this discussion it is assumed that only the I/O
Subsystem has a problem and that the rest of the system is
operational.
NOTE
Although the diagnostic disables the I/O
modules from the field wiring, it is a
good practice to remove all power from
the fie I d wi r i n 9 t o e n sur e t hat no
output point will be inadvertently
enabled.
7.5.3.1 Quick Checklist - The following is a list of the
common causes of failure and should be checked initially.

Check bus cables for
Pa rag r a ph 3. 3. 2.3) •

Ensure that switches on the control
properly (Chapter 3, Paragraph 3.5.1).

Ensure that there are no empty slots between I/O modules.

Check indicator lamps on power supplies (Figure 7-1)
control module (Figure 3-16 or 3-18):

proper

Power supplies - DC ON -

Control module indicators others off.

installation

module

are

3,
set

and

is on
+5 V and +12 V ON -

Check screw terminal cables for
(Cha pte r 3, Pa r ag ra ph 3. 3. 3.3) •

Check power supply voltages (Paragraph 7.3).

7.5.3.2 Diagnostic Check -

(Chapter

proper

all

installation

Load and run diagnostic MD-ll CVPCAO-0.

7-8

Run the map (M) option and
respond properly.

Run the system test (8) option.

Most faults will be located by running the above options'.
One notable exception is the final stage of an I/O
module, which cannot be tested by the diagnostic.
Therefore, if a problem is encountered with "BIT XX" on
one of the I/O modules, and running the diagnostic
indicates the module is functioning properly, the problem
may still be on the module. If the application allows the
use of field wiring during the test, the diagnostic
subtests should be used to verify the operation of the
I/O stages of the suspect module. If this fails tio
isolate the fault, the field wiring should be checked to
see if the proper signals are present.

Dete rm ine whether the probl em is a ssoc i a ted wi th onle
module or more than one. A fault on the control modul:e
can make alII/Os appear faulty. One I/O module could
cause a bus problem that would make alII/Os appear bad.

Bus fa ul t i sol at io n - Isol at ion 0 f
subsystem is readily accomplished.
a.

ensure

that all

mod ule s

I/O modules

the

I/lO

Control modules are isolated from the I/O modules as
follows:
M7958

remove first I/O mod ul e

M7959

unpl ug D-bus cable from Jl of M7959

M8719

unpl ug D-bus cable from Jl of M87l9

Remov ing any I/O mod ule
(H333) chassis.

will

open

the

NOTE
Some bus signal s in the H334 expansion
chassis are bussed straight across the
backplane and removing a module will not
isolate them. In this case, all modules
must be removed and then reinstalled one
at a time to isolate a fault.

7-9

bus

the

APPENDIX A
MNEMONIC DEFINI1IONS
A.I
GENERAL
Some signal names in this list differ by a prefix only such as B
DIN, D DIN, and R DIN. DIN stands for Data In in each case, but
the spaced prefix further identifies the signal:
BUS XXX - UNIBUS signal
B XXX - LSI-II bus signal
D XXX - D-bus signal.
The references identify a location where the signals may be
observed, for example, IOC E6-S stands for M795S I/O Control,
component E6 and pin S (refer to print set B-TC-H333).
Mnemonic

Definition

ADRO

Ref. IOC E6-S. Address Out
beginning of the D-bus Cycle
Selects the address mode of
mul ti pI exer

Asserted

the

output

D-bus

the

A00

Ref. IOC E2-6. Address Bit - Assertion means an
odd address has been selected
Causes transceivers to transmit high byte

B IRQ

Ref. laC E21-S. Bus Interrupt Request - Asserted
by subsystem if its interrupt enable and flag
signals are asserted
Means some device on the LSI-ll bus require:s
service

B RPLY

Ref. IOC E35-1'0. Bus Reply - Asserted in response
to B DIN, B DOUT, and IAK transactions
Indicates some device on the LSI-ll bus has
accepted output data or placed input data on the
bus

B SYNC

Re f. IOC AJ2. Bus Synchroni ze - Asserted by bus
master to indicate it has placed address on bus

BUS BR

Bus Request
Assertion means
requesting control of the UNIBUS

BUS BG

Bus Grant - Assertion means a device is granted
control of the UNIBUS

BUS SACK

Selection Acknowledge - Assertion means device
acknowledges its selection as UNIBUS master

BUS INTR

Interrupt - Assertion means a device has put its
interrupt vector on the UNIBUS

A-I

device

Mnemonic

Defini tion

BUS Cl

Assertion means a data transaction from slave to
master (DATI)
Negation means a data transaction from master to
slave (DATO)

BUS MSYN

Master Sync _. Assertion means the UNIBUS master
is starting a data transaction
Negation means the UNIBUS master considers the
transaction complete

BUS SSYN

Slave Sync
Assertion means that the UNIBUS
slave has valid data on the UNIBUS or that it has
accepted data from the UNIBUS

CIA

Ref. IOC E2-l5. Control or Interrupt Address Asserted when either the CSR or IAR is addressed

CLR

Ref. IOC E36-l4. Clear BIt, bit 01 of the CSRAssertion causes the subsystem to reset without
requiring a reset instruction
Self-clearing and write-only

C MAINT

Ref. IOC E37-3. Clear Maintenance
maintenance bit in the CSR

C RIF

Ref. E37-6.
CSR

CSR

Control and status register

D ADDR

Ref.
IOC E52-5. D-bus address
Assertion
indicates start of modified D-bus Cycle that
reads the address of the interrupting module

D-BUS

H333 I/O bus

DCE

Ref. IOCC El-3. Data Cycle Enable
enables D-bus data transactions

D DIN

Ref.
IOC CR1/CR2.
D-bus Data Input Strobe
Assertion causes addressd I/O module to place
appropr iate data on the D-bus and to .:lcknowl edge
the operation by asserting D RPLY

D DOUT

Re f • IOC CS1/CS2. D-bus Da ta Ou tput St robe
Assertion causes addressed I/O module to accept
data from the D-bus and to acknowledge the
operation by asserting D RPLY

. ,

Clears

the

Clear RIF - Clears the RIF bit in the

i\-2

Assertion

Mnemonic

Defini tion

D GBIT

Ref. IOC DEl/DE2. D-bus Generic Bit, CSR bit 02 Assertion causes an I/O module to respond with
its identity code instead of normal data

DIN

Ref. IOC El-14. Da ta In - Asser t ion prod uce s the
VECTOR s ig nal d ur ing an in te r rupt tr ansac tion,
and NO INTR DIN otherwise

D INTR

Ref. IOC DK2. D-bus Interrupt - Assertion at the
IOCM means that some I/O module on the D-bus
requires service. This signal is daisy-chained to
all I/O modules.

DOUT

Ref. IOC El-13. Data Out - Assertion enables the
R DOUT signal, or writing into the CSR

D SYNC

Ref. IOC CP2. D-bus Synchronize - Strobes I/O
modules at D-bus Cycle SYNC TIME and causes
addressed module to store the output of its
address decoder as the MY ADDRESS signal

DT LATCH

Ref. IOC ES-3. Data Time Latch - Indicates that
the data phase of the D-bus Cycle is in progress

DBIT

Ref. IOC E36-3. Disable Bit, bit 04 of the CSR Assertion implements I/O disable mode on all I/O
modules

DEV SEL

Re f. IOC E2-10. Dev ice Sel ect - Assertion means
that an I/O Subsystem address has been decoded

D INIT

Ref. IOC E32-2. D-bus Initialize - Restores all
I/O mod ul e log ic to the startup state, and is
asserted by B INIT, low backup suppl y vol tag e
(when impl emen ted), neg at ion 0 f the DBIT, or
setting the CBIT

D INTR CLOCK

Ref. IOC DM2. D-bus Interrupt Clock - Stabilizes
interrupt priority

DRIVE DBUS

Re f. IOC ESS-3. D-bus Dr iver
enables D-bus output drivers

D RPLY

Ref. IOC CU2. Reply - Asserted in acknowledgment
of D DIN or D DOUT by the addressed I/O module

D SYS CLOCK

Ref. IOC DV2. D-bus System Clock
crystal-controlled oscillator signal
mod ul e tim ing

A-3

Strobe -

Assertion

100
for

kHz
I/O

Mnemonic

Defini tion

D TBIT

Ref. IOC E52-9. D-bus Test Bit, CSH bit 03
Assertion implements I/O test mode on all I/O
modules

EAB

Ref. IOC E9-l0. Enable Address on Bus - Assertion
starts D-bus Cycle timing sequence

FLAG

Ref. IOC E33-8. FLAG Bit, CSR bit 07 indicates
that the
I/O Subsystem
service

GBIT

Re f • IOC E 3 6 -11 • Ge n e ric Bit, CS Rbi t
02
Assertion produces the D GBIT signal which causes
an I/O module to respond with its identity code
instead of normal data

INTR ENAiBLE

Re f. I DC E 21-1 6 • En a b 1 e In t err up t, CEl Rbi t 06 Enables subsystem interrupts
If F = 1, E = 1, and the processor status allows
interrupts, the processor will be interrupted

IaCM

Input/Output Control Module

IAR

Ref. IOC E4-6. Interrupting Address Register Assertion produces the D ADDR signal
and
initiates the Modified D-bus Cycle that reads the
address of the interrupting module

IN IT

Ref. IOC E37-11. Initialize - Initializes IOCM
Assertion clears the address register, interrupt
control, timeout circuit, and the CSR

lOR

Input/Output Register

LOAD ADDH

Re f • IOC E 1 - 2 • Lo a d Ad d res s - In i t i ate d by B
SYNC
Assertion strobes the I/O module address into the
address register of the M7958
Negation resets the SYNC TIME and DATA TIME
flip-flops and clears the address register

MAINT

Ref. IOC E31-5. Maintenance Bit, CSH bit 05 Assertion forces a maintenance interrupt if E=l.
If M=l, then F=1~ Reading an lOR with M=l results
in data equal to the address of that lOR, whether
or not there is a module installed in that
address

MAINT

DA~rA

REF. IOC E3-6. Maintenance Data
enables a maintenance data input

A-4

Assertion
requires

Assertion

Mnemonic

Defini tion

MY ADDRESS

Ref. I/O module MY ADDRESS flip-flop. Assertion
indicates the module has been addressed
The MY ADDRESS fl ip-flop is set when D SYNC
occurs if the module's address decoder output is
high
1 f t he d ec 0 d e r 0 u t pu t i s low, the f 1 i p- flo p i s
reset

NO INTR DIN

Ref.
laC
E17-6.
No
Interrupt
Data
In
Synchronizes
all
subsystem
data
reading
operations except the interrupt vector

READ CSR

Ref. laC E15-6. Read CSR - Enables the CSR output
to the transceivers
Al so clears MAINT and RIF at the end of the
current cycle

R DIN

Ref. laC E10-6. Data In D DIN signal to the D-bus

R DOUT

Ref. IOC E10-S. Data Out - Assertion produces the
D DOUT signal to the D-bus, after a short delay

REC LB

Ref. laC E17-3. Assertion places the low byte of
the LSI-II bus onto the internal data bus of the
M7958

REC HB

Ref. IOC E25-S. Assertion places the high byte of
the LSI-II bus onto the internal data bus of the
M795S

RIF

Ref. laC E31-9. Reset Interrupt Flag, bit 00 of
the CSR - Causes the I/O mod ul e being read to
reset its internal interrupt flag
RIF is cleared at the end of the cycle in which
an I/O module or the CSR is addressed

R INIT

Ref. laC E3S-11.
INIT signal

R INTR CLOCK

Ref. IOC E3S-6. R Interrupt Clock D INTR CLOCK signal

SYNC

SETUP TIME

Ref. IOC EI0-11.
SYNC signal

Assertion produces the

Initialize -

R Synchronize -

produces

the D

Produces the

Produces the D

Ref. laC E12-6 and E9-4. SETUP TIME - The time
from D-bus Cycle initialization until SYNC TIME
that allows for stabilization of the address on
the D-bus

A-5

Mnemonic

Definition

SYNC TIME

Ref. IOC E9-4 and E9-8. SYNC TIME - The time
between SETUP TIME and DATA TIME that allows for
address determination on the I/O modules prior to
a data transaction

TBIT

Re f. IOC E 36 -7, CS RBi t
the D TBIT signal

UB US HI XlM IT

Assertion causes the M87l9 to
data to the UNIBUS high byte

route

UB US La

Assertion causes the M8719 to
data to the UNIBUS low byte

route its internal

Xl~ IT

03•

Te s t

Bi t -

Pro d uc e s

its internal

VECTOR

Ref. IOC E2l-l. Transmit Interrupt Vector Causes the subsystem interrupt vector to be put
on the LSI-Il bus

WRITE CSR

Ref. IOC E18-l1. Write CSR - Assertion causes the
CSR to store new data

XMIT HB

Ref. IOC E25-12. Transmit High Byte - Assertion
causes the M7958 internal data bus to be routed
to the high byte of the transceiver input to be
put on the high byte of the LSI-Il bus

XMIT LB

Ref. IOC E25-6. Transmit Low Byte - Assertion
causes the M7958 internal data bus to be routed
to the low byte of the transceiver input to be
put on the low byte of the LSI-II bus

A-6

APPENDIX B
FLOATING VECTOR ASSIGNMENTS
B.l
GENERAL
A floating vector convention is used for communication (and other)
devices that interface with the PDP-II. These vector addresses are
assigned in order, starting at 300 and proceeding upward to 777.
Table B-1 shows the assigned sequence. The first vector address,
300, is assigned to the first DCll in the system. If another DCll
i sus ed, i t wo u 1 d the n be ass i g ned v ec to r ad d res s 31 0 , etc. Wh en
the vector addresses have been assigned for all DClls (up to a
maximum of 32), addresses are then assigned consecutively to each
unit of the next highest-ranked device (KLll, DPll, or DMll,
etc.), then to the other devices in accordance with the priority
ranking.
Table B-1
Priority Ranking for Floating Vectors
(Starting at 300 and Proceeding Upward)

.
Device

Vector Si ze
(Octal)

Maximum
Number

DCll
KLll, DL11-A, DL1l-C
DPll
DM11-A
DNl1

10
10
10
10
4

32
16
32
16
16

6
7
8
9
10

DMI1-BB
DR1l-A
DR11-C
PA611 Reader
PA611 Punch

4
10*
10*
4*
4*

16
32
32
16
16

11
12
13
14
15

DTl1
DX11
DL11-C, DLI1-D, DL11-E
DJ11
DH11

10*
10*
10
10
10

8
4
31
16
16

16
17
18
19
20

GT40
LPSl1
DQ11
KW11W
DUll

10
30*
10
10
10

1
1
16
1
16

21
22

ICS11/ICRl1
IPl1/IPl10

4
4

12
16

Rank

"".-

1
2
3
4
5

_._--"----"-"'---

*The first vector for the first device of this type must always be
on a 10 8 boundary.

B-1

When the vector addresses have been assigned to all higher ranking
devices, addresses are then assigned to each IPl10, (or IPll)
beginnin.g with the second one in the system. The first IPl10 (or
IPll) is always assigned vector address 234.
NOTE
vectors range from address
3~~-777,
but addresses 5~~-534 are
reserved for special bus testers. In
addition, address 1~00 is used for the
DSll
Synchronous
Serial
Line
Multiplexer. Refer to Appendix A of the
PDP-II Peripherals Handbook, 1976, for a
complete discussion of UNIBUS addresses.
Floating

B-2

APPENDIX C
USER FORMS

Refer to Chapter 3, Paragraph 3.6 for
use of the forms in this section.

C-l

instructions on the proper

I/O MODULE USER PAGE

PAGE NO. ____________________

MODULE TYPE _____________ BYTE _ _ _ __

OF _ _ _ __

GENERIC CODE _ _ _ _ _ _ _ _ __
BYTE ADDRESS _ _ _ _ _ _ _ _ _ _ SINGLE SHOT TIMING _ _ _ _ __
MUXNO. _______________

MODULE LOCATION:

CHASSIS NO. _ _ _ _ _ _ FIELD POWER:
SLOT NO. _ _ _ _ __

POINT

INTR.
ENAB.

COMMON

ISOLATED

BIT FUNCTION REMARKS

00
01
02
03
04
05
06
07

ADDITIONAL COMMENTS:

MA-0233

Reader's Comments
I/O SUBSYSTEM USER GUIDE
E K-OPIOS-UG-005
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Telephone 1-800-258-1710

Order No.

EK-OPIOS-UG-005

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