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EK-KW11L-TM-002

February 1974

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Document:	EK-KW11L TM-002 KW11-L Line Time Clock Manual Jul74
Order Number:	EK-KW11L-TM
Revision:	002
Pages:	19
Original Filename:	EK-KW11L_TM-002_KW11-L_Line_Time_Clock_Manual_Jul74.pdf

OCR Text

EK-KW11L-TM-002

KW11-L

line time clock
manual

digital equipment corporation - maynard, massachusetts

Ist Edition February 1971
2nd Printing (Rev) December 1971

3rd Printing July 1972
4th Printing October 1972
5th Printing April 1973
6th Printing September 1973
7th Printing July 1974

The material in this manual is for informational
purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS
Page

Chapter

1-1

CHAPTER 1

INTRODUCTION

CHAPTER 2

GENERAL DESCRIPTION

CHAPTER 3

DETAILED DESCRIPTION

3.1

Address Selector

3-1

3.2

Threshold Detector

3-1

3.3

Interrupt Control

3-1

Status Register

CHAPTER 4

PROGRAMMING INFORMATION

4.1

Interrupt Mode

4-1

4.2

Noninterrupt Mode

4-1

CHAPTER 5

KWI11-L ENGINEERING DRAWINGS

5-1

ILLUSTRATIONS
Title

Figure No.

Art No.

Page

2-1

KW11-L Block Diagram

11-0197

2-1

3-1

KW11-L Address Word

11-0199

3-1

3-2

Interrupt Request Section, Simplified Logic Diagram

11-0196

3-1

3-3

Status Register, Simplified Logic Diagram

11-0198

TABLES
Table No.
3-1

Title
Interrupt Control Flip-Flops

iii

CHAPTER 1
INTRODUCTION

The KW11-L Line Time Clock is an option that provides the PDP-11 System with a method of accurately dividing time into intervals. The KW11-L consists of a single-height M787 Line Time Clock Module that generates a
repetitive interrupt request to the processor. The rate of interrupt is the same as the line frequency, either 50 or

60 Hz.

This manual describes the manner in which the KW11-L functions and presents general and detailed descriptions
of the KW11-L. It is assumed that the reader is familiar with basic digital theory.

Line time clock signals pass through the Unibus @ ; it is beyond the scope of this manual to describe the operation of the Unibus. A detailed description of the Unibus is available in the PDP-11 Peripherals Handbook.

Installation of the KW11-L is accomplished by plugging the M787 Module into the appropriate slot for the type

of system used and removing a jumper wire as follows:

System

Processor

M787

Jumper Wire

Slot

Terminals

PDP-11/15

KC11

B12

B12V2

B12R2

PDP11/20

KA1l

B12

B12V2

B12R2

PDP-11/35/40

KDI11-A

F3V2

F3R2

PDP-11/45

KB11-A

Civ2

C1R2

PDP-11/70

KB11-B

D1V2

D1R2

@ Unibus is a trademark of Digital Equipment Corporation.
1-1

CHAPTER

GENERAL DESCRIPTION

The KW11-L accurately divides time into intervals for more efficient use of PDP-11 computer
time. The intervals are determined by the line frequency, either 50 or 60 Hz. The accuracy of the clock period is
that of the

frequency source.

The KW11-L includes an address selector, threshold detector, interrupt control, and a two-bit status register (see
Figure 2-1). The address selector is permanently wired to respond to a single incoming address, 777546.
Before
the KW11-L begins to operate, the processor must send out that address, a master synchronization (MSYN)‘signal, and a gating control signal. MSYN indicates to the device that address and control information are
present.
The gating control signal determines the direction of the data transfer operation desired: DATI for transfer
of
data from slave to master, DATO for transfer from master to slave.

A valid combination of these three sets of signals controls data transfers between the two-bit status register of
the KW11-L and the processor. These transfers determine whether the device is in the interrupt or the noninterrupt mode. In the interrupt mode, the KW11-L signals the processor for an interrupt each time
it receives a

pulse

from the line frequency source. In the noninterrupt mbde, the KW11-L acts as a program switch that the procesSOr can examine or ignore.

When the KW11-L is in the interrupt mode, the interrupt control section of the device provides the circuits and
logic required to make bus requests, gain bus control, and generate interrupts. When the threshold detector provides a pulse from the line frequency source, the interrupt control section initiates a bus request on priority level
6, which is the priority level of the KW11-L.
The priority arbitration logic in the processor recognizes the request and issues a bus grant signal, if this device is

the highest priority device requesting an interrupt. The KW11-L responds with a selection acknowledge (SACK)
signal. When the requirements for becoming bus master have been fulfilled, the KW11-L asserts bus busy
(BBSY), an interrupt (INTR) signal, and an interrupt vector address of 100. The processor generates a slave syn-

chronization (SSYN) signal, then responds to the interrupt with an interrupt service routine. The interrupt control section of the KW11-L then goes to a rest state until the next initialization.

{\
ADDRESS

SELECTOR

A{17:01)
c1
MSYN
SSYN

N
B D (06:07)
S

STATUS
REGISTER

INIT

—
LINE
FREQUENCY

THRESHOLD
DETECTOR

> INTERRUPT
CONTROL

BR6
BG6 IN
BG6 OUT
SACK
INTR
BBSY
D06
SSYN

Figure 2-1

44J
1-0t97

KW11-L Block Diagram

The two-bit status register of the KW11-L consists of bits 6 and 7 on the data bus line. When bit 6 is set, the device is in the interrupt mode; when it is clear, the device is in the noninterrupt mode. Bit 6 is set or cleared by a
processor DATO to the KW11-L; it is also cleared by a processor INIT. Bit 7 is set by a line clock pulse from the
threshold detector or by a processor INIT; it is cleared by any processor DATO to the KW11-L.

Bit 7 can be used by the processor to determine which device caused an interrupt. The interrupt service routine
should include a DATI which reads the interrupt monitor bit (bit 7) to serve as a partial check on the origin of
the interrupt vector. Thus, if bit 7 is clear, there is an indication to the processor that this device did not request
the interrupt.

In the noninterrupt mode, the KW11-L performs a more passive function. The KW11-L acts as a program switch
that the processor can examine or ignore. The interrupt control section is disabled so that the KW11-L cannot
assert a bus request (BR6) and, therefore, cannot go into an interrupt sequence. A programmed DATO must be
used to return the KW11-L to the interrupt mode; programmed DATIs must be used to examine the status of the
device. In the noninterrupt mode, the KW11-L is controlled by programmed instruction from the processor.

A more detailed description of KW11-L operation is presented in Chapter 3. Chapter 4 contains programming information for both the interrupt and the noninterrupt modes.
KW11-L specifications are as follows:

Two-bit status register; bits 6 and 7 on the data bus line

Permanently wired to 777546
Permanently wired to 100,
Generates repetitive time interval indications to processor
Interrupt enable bit
Interrupt monitor bit

Rate

Same as line frequency; 50 or 60 Hz

Bus Cycles
Priority Level
Modes

DATO, DATI
Permanently wired to BR6
Interrupt and noninterrupt

CHAPTER 3

DETAILED DESCRIPTION

The KW11-L includes an address selector, threshold detector, interrupt control, and a two-bit status register.
Each section is discussed with regard to its operation and interrelationship to the other sections of the device.

3.1

ADDRESS SELECTOR

The address selector section of the KW11-L is permanently wired to respond to incoming address 777546. Input
signals enter on 17 address lines, A(17:01), one bus control line, C1, and a master synchronization (MSYN) line

(see drawing D-BS-KW11-L-01). Address line AOO is not brought into the device because its only function is to select between bytes; the KW11-L deals only with complete words. The address format used to select the KW11-L
is shown in Figure 3-1 and is decoded by the address selector. This decoded address, together with a 1 on MSYN,
causes the output of gate E3 to go high (drawing D-BS-KW11-L-01), signalling that the device has been addressed.
3.2 THRESHOLD DETECTOR

The threshold detector section (Q2 and E11 on drawing D-BS-KW11-L-01) of the KW11-L detects a point on a
waveform (LTC L) produced by the H720 Power Supply. A regulator circuit board in that power supply includes a circuit that provides a clipped waveform based on the input-line voltage.
Signal LTC L is inverted to cause a high pulse at the clock input of the flip-flop for bit 7 of the status register,
setting that bit and, if bit 6 is set, the internal interrupt request flip-flop (E6).

Ty
7

rjofrjrjojogt
7

i
6
1H-0199

Figure 3-1

KWI11-L Address Word

3-1

3.3

INTERRUPT CONTROL

The interrupt control section of the KW11-L provides the logic circuits to make bus requests, gain bus control,
and generate interrupts. This section of the device uses three flip-flops:

the interrupt request, FF1 and FF2 (see

Figure 3-2). Table 3-1 lists the settings of these flip-flops in relation to the bus states and the signals asserted.
v

INTERRUPT
REQUEST

_L_OD

‘

ADDRESS H

—

BUS C1 H—

E14

INTERRUPT

ENABLE (0)

LINE CLOCK

BR6

fi
BUS
D07 L

BUS S SYN H —

)

___L_0

FF1

.
]

D
E7

_}"Do 6
BUS

BUS
INTR L

12 DF : 1 91

¢—BUS

BUS S SYN H—O

BG6 IN H—4—O

0..__/

BUSY L

‘

BUS

SACK L

+5V

11-0196

Figure 3-2

Interrupt Request Section, Simplified Logic Diagram

When the KW11-L is not requesting, all three flip-flops are in the O state, and no signals are asserted on the bus.
The requesting state is entered when the interrupt request flip-flop is set by a line clock pulse. This setting of
the flip-flop can occur only when the status bit 6 flip-flop (interrupt enable) is in the 1 state. Setting the inter-

rupt request flip-flop generates a bus request priority level 6 (BR6).
The priority arbitration logic of the processor determines whether priority level 6 is the highest level requesting.
If priority level 6 is the highest level requesting, the processor asserts a bus grant signal (BG6 IN high) that sets

the FF1 flip-flop. Signal BG6 is blocked from being passed on to the next device and the assertion of the bus request (BR6) is droppéd. With flip-flopFF1 a 1 and flip-flop FF2 a 0, the selection acknowledge signal (SACK) is
asserted on the bus.

Table 3-1

Interrupt Control Flip-Flops
Interrupt Request

FF1

FF2

State

Signals

Not Requesting

None

Requesting

BR6

Granted

SACK, inhibit
BG6 OUT

Master

BBSYN, INTR,
D06 (Vector
address)

On receiving the SACK signal the processor drops BG6 IN, and flip-flop FF2 is set if SSYN and BBSY are unasserted. Signals BBSY and IN7'R are then asserted on the bus, as well as interrupt vector address 100 (D06).

The processor responds to these signals by asserting a slave synchronization signal (SSYN) that clears the interrupt request flip-flop. Flip-flops FF1 and FF2 are subsequently cleared; the interrupt control section of the

KW11-L is returned to the not requesting state. At the same time the SSYN is asserted, the processor goes into
the interrupt service routine at vector address 100.
3.4

STATUS REGISTER

The status register of the KW | 1-L contains the interrupt enable (D06) and the interrupt monitor (D0O7) flip-flops
(see Figure 3-3). Operation of the status register circuits is controlled by INIT, the line clock pulse, DATO, and
DATI.

Signal INIT is generated either by depressing the START switch on the console or by issuing a programmed RESET instruction. This signal clears D06 and sets D07 to initialize the status register for a new operation.
The line clock pulse is supplied by the threshold detector section of the KW11-L and is used to set DO7. DATO
and ADDRESS clear D07 when BUS D07 is 0, by applying a signal to the direct clear input.

For DATO and DATI to affect the circuits of the status register section, the address of the KW11-L and MSYN
must be asserted on the bus to provide the ADDRESS H signal shown as an input on Figure 3-3. This ADDRESS

signal is also used, after a delay, to assert a SSYN signal on the bus.
The combination of DATO and ADDRESS provide a signal to the clock input of D06. Depending on BUS D06,
the flip-flop is either set or cleared. Thus, the processor can read a bit into this flip-flop by issuing a DATO and
D06 =1 fora 1, and DATO and D06 = 0 for a 0. The 0 side output of D06 controls the interrupt function of

the KW11-L by holding the interrupt request flip-flop (in the interrupt control section of the KW11-L) in the
cleared state when D06 is in the O state.

DATI and ADDRESS provide gating that reads the content of D06 onto bus line D06 and the content of DO7
onto bus line DO7.

INTERRUPT
ENABLE

2[00
ADDRESS H

Et3

&L “*3-_—__~*\

LI_>;‘[:;
|

o|8_|

BUS DO6

TOINTERRUPT CONTROL SECTION

BUS INIT L

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3
CLOCK—--¢

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RIDES

— BUS DO7

E13
__BUSS
SYN L

L
—
11-0198

Figure 3-3

Status Register, Simplified Logic Diagram

CHAPTER 4
PROGRAMMING

INFORMATION

This chapter presents general programming information for software control of fhe KWI11-L Line Time Clock.
Although typical program examples for both the interrupt and noninterrupt modes of operation are included, it
is beyond the scope of this manual to provide detailed programs. If more detailed programming information is

desired, refer to the PDP-11 Paper Tape Software Programming Handbook, DEC-11-XPTSA-A-D.
All software control of the KW11-L is performed by means of a two-bit status register, which has been assigned
memory address 777546 and the mnemonic LKS. This register can be read or loaded by using any PDP-11 in-

struction that refers to its address.

4.1

INTERRUPT MODE

The following program is an example of one way the KW11-L can be used in the interrupt mode. The purpose

of this program is to enter the routine TIME after every N interrupts. The mnemonic LKS represents the permanent memory address of the KW11-L, 777546; LKV represents the vector address, 100. When the main program
is interrupted, it is directed to LKV, and then to LKV + 2, which is 102. The word in location 100 is the ad-

dress of the first instruction in the interrupt service routine; this address is transferred into the program counter

of the processor. The word in location 102 is the new status word, which is transferred into the status register
of the processor. The new status word contains the number 300, which indicates a priority level of 6, with all

five condition codes, T, Z, N, V, and C equal to 0.
LKS =777546

LKV =100

MAIN:

MOV #N, CNTR

MOV #100, LKS

;ENB INTR

LKV:

LKSERV

LKSERV:

MOV #100, LKS

300
;Clear bit 7. This instruction is optional

DEC CNTR

BEQ TIME

;If counter is zero, go to time.

;If counter is not
;Zero, continue.

RTI

TIME:

MOV #N, CNTR

;Reset counter

RTI

4-1

4.2

NONINTERRUPT MODE

The following program is an example of one way the KW11-L can be used in the noninterrupt mode. In
this example, it is assumed that an INIT or a previous DATO with D06 = 0 has placed the KW11-L in the noninterrupt
mode. This program alternates between two program routines; each routine lasts for approximately
the time period between line clock changes, which is either 16.67 ms or 20 ms. Each routine contains a program loop that

lasts for a considerably shorter time than the period between line clock changes. The mnemonic LKS
represents
the permanent memory address of the KW11-L, 777546.

LKS =777546

START:

CLRB

LKS

;Reset bit 7

SYNC:

TSTB

LKS

;Wait until bit 7 is set,

BPL

SYNC

;Then reset it

CLRB

LKS

;Clear bit

;Do first routine

ON:

TSTB

LKS

;Each time through loop test bit 7

BPL

;When bit is set

CLRB

LKS

;Clear bit

;Do second routine

OFF:

TSTB

LKS

;Test bit 7

BPL

OFF

;If not set, do loop again

CLRB

LKS

;If set, clear bit

JIMP

;Do first program again

CHAPTER 5
KW11-L ENGINEERING DRAWINGS

The engineering drawings for the KW11-L are contained in the print set that is shipped with the equipment. The

drawings that relate to this manual are:
D-TD-KW11-L-02

Timing Diagram (KW11-L)

D-BS-KW11-L-01

Line Frequency Interval Clock

5-1

Reader’s Comments

PDP-11 KW11-L LINE TIME CLOCK
EK-KW11L-TM-002

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of
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What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well

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CUTOUTONI

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MAYNARD, MASS.

BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES

Postage will be paid by:

dlilgliltall

Digital Equipment Corporation

Technical Documentation Department
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3003|3215

THIS SCHEMATIC 1S FURNISHED ONLY FOR TEST AND MAINTEMANCE PURPOSES. THE

CIRCUITS ARE PROPRIETARY N NATURE AND SHOULD € TREATED
COPYRIGHT 1970

BY DIGITAL EQUIPMENT CORPORATION

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