KW11-L line time clock manual

This manual describes the Digital Equipment Corporation KW11-L Line Time Clock, an optional module for PDP-11 systems that provides a method for accurately dividing time into intervals. The KW11-L generates repetitive interrupt requests to the processor at either 50 or 60 Hz, synchronized with the line frequency.

The device consists of a single-height M787 module and comprises an address selector (permanently wired to address 777546), a threshold detector, interrupt control logic, and a two-bit status register. It operates in two modes:

1. Interrupt Mode: When enabled (status register bit 6 is set), each line clock pulse triggers an interrupt request to the processor on priority level 6. Upon receiving a bus grant, the KW11-L asserts a bus busy signal, an interrupt signal, and an interrupt vector address of 100, prompting the processor to execute an interrupt service routine. Status register bit 7 (interrupt monitor) is set by the line clock pulse and can be read by the processor to identify the interrupt source.
2. Non-interrupt Mode: The interrupt control is disabled, and the device acts as a program switch that the processor can examine or ignore, without generating bus requests.

Software control of the KW11-L is achieved through its two-bit status register, memory-mapped to address 777546. Bit 6 enables or disables the interrupt function, while bit 7 indicates a clock pulse. The manual assumes familiarity with basic digital theory and outlines installation procedures, detailed descriptions of the device's logic circuits, and programming information with examples for both interrupt and non-interrupt modes of operation. Engineering drawings are referenced for further technical detail.