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EK-KD1EA-MM-001

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Document:	KD11EA CPU Maint
Order Number:	EK-KD1EA-MM
Revision:	001
Pages:	129
Original Filename:	KD11EA_CPU_Maint.pdf

OCR Text

EK-KD1EA-MM-001

KD11-EA

central processor
maintenance manual

digital equipment corporation « maynard, massachusetts

First Edition April 1977

The material in this mahual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporafion assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11

UNIBUS

CONTENTS

Page

CHAPTER 1

OVERALL DESCRIPTION

CHAPTER 2

INSTRUCTION SET

2.1

INTRODUCTION

2.2

ADDRESSING MODES

2.3

PDP-11/34A INSTRUCTIONS
. . . . . . . . .
o e
2-4
INSTRUCTION EXECUTIONTIME
. . . . . . ... .. .. ... ..... 2-25

2.4

2.4.1

2.4.2

. . . . . . . . e,
. . . . . . . . . . e

Basic Instruction Set Timing

Bus Latency Times

. . . . . . . . . . . . ...

. . . . . . . . . .

2.5

EXTENDED INSTRUCTION SET

2.6

INSTRUCTION SET DIFFERENCES

CHAPTER 3

CPU OPERATING SPECIFICATIONS

CHAPTER 4

DETAILED HARDWARE DESCRIPTION

4.1

INTRODUCTION

4.2

DATAPATH

. .

. . . .

2-1

... .. ... 2-25

. e 2-30

. . . . . . . . . ... ... ... .... 2-30
. . . . . . . . . . ... .. ...... 2-31

. .

4-1

. e

4-1

4.2.1

General Description

422

Arithmetic Logic Unit (ALU)

. . . . . . . ...

d e e

s d

L e

4-1

. . . . . . .. . .. ... .. .. ....

4-5

4.2.3

Scratchpad

. . . . . . . . . ..

424

Bleg

. . .

2-1

4-7

. e
e
e
e 4-12

4.2.5

ALU Multiplexer (AMUX)

. . . . . . . . . . .

4.2.6

Processor StatusWord

. . . .

. . .

. .. 4-21

. o

e e

4.3

4.3.1

CONDITION CODES

. .

. . . .

Instruction Categorizing ROM

4.3.2

Byte Multiplexer (BYTEMUX)

Cand

434

Condition Code Signal CCZH

4.4

e 4-21

e e e e e

e 4-25

. . . . . . . ... .. .. ... ..... 4-25

433

VDecode ROM

. . . . . .. .. ...

... .. .... 4-25

. . . . . . . . . . ...

4-26

. . . . . . . . .. ... .. .. .... 4-26

UNIBUS ADDRESS AND DATA INTERFACE

4.4.1

Unibus Drivers and Receivers

442

Unibus Address Generation Circuitry

4423

Internal Address Decoder

. . . ... ... ... .... 4-26

. . . . . . . . .. . ...
. .

. .

.. .. .... 4-26

. . . . . . . . . . . ... .. .. 4-26
. . .

... ..

... 4-30

4.5

INSTRUCTION DECODING

4.5.1

General Description

. .

Lo 4-30

452

Instruction Register

... 4-31

4.5.3

Instruction Decoder

. .

. 4-30

e 4-31

4.5.3.1

Instruction Decoder Circuitry

4.5.3.2

Double-Operand Instructions

. . . . . . . . . .. .. ... .... 4-32

4533

Single-Operand Instructions

. . . . . ... ... ... .. .... 4-34

4.53.4

Branch Instructions

4.5.3.5

. . . . . . . ..

Operate Instructions

... ...

... ... 4-31

... 4-35

. . . . . . . . . . . . ... ... 4-35

4.6

AUXILIARY ALUCONTROL

4.7

DATA TRANSFER CIRCUITRY

. . . . . . .. . .. .

iii

.. .. ... 4-36

. . . . . . . . . .. ... . . . ... ... 4-40

CONTENTS (CONT)
Page
4.7.1

General Description

4.7.2

Control Circuitry

. .

. . . . . . .

..o 440

. . . o .

e 4-40

4.7.2.1

Processor Clock Inhibit

. . . . . . . . . . . .. ... ... .... 4-40

4.7.2.2

Unibus Synchronization

. . . . . . . . . . . ... ... .. ... 4-40

4.7.2.3

Bus Control

4.7.2.4

NO-SACK Timeout Circuitry

4.7.2.5

MSYN/SSYN Time-Out Circuitry

4.7.2.6

Bus Errors

4.7.2.7

Parity Errors

4.7.2.8

End of Transfer Circuitry

. . . . . .

. . . . .

4.7.2.9

Data-in-Pause Transfer

Odd Address Detection

4.8

POWER FAIL/AUTO RESTART

4.9

PROCESSOR CLOCK

4.10

PRIORITY ARBITRATION

e e

e e 4-46
... 4-46

. . . . . . . . .. . . ... ... 4-46

. . . . . . . . .. ..o oL 4-46
. . . . . . . . . . . .

. . . . . . .

. . . . . . . .

4.10.2

Nonprocessor Requests (NPRs)

e e
.

... .. ..... 4-49

e e e 4-50

o e 4-52

. . . . . . . . . . Lo 4-52
. . . . . . ... .. ... ... .. .. 4-55

Halt Grant Requests
. . . . . . . . . . . . ... L. 4-55
. . . . . .
e
e
e
s 4-57

SERVICE TRAPS

4.11.1

General Description

411.2

Circuit Operation

4.12.1

. . . . . . . . . . .« . . ...

Bus Requests

4.12

. . . . . . . . . . . . . .. ... 4-43

4.10.1

4.11

.o 4-41

. . . . . . . . . . . . .. . ... .. 4-4?

. . . . . . . . Lo 4-46

4.7.2.10

4.10.3

. . . . . . . . . . Lo
oo 4-57
. . . . . . . . . . . .

oo e 4-57

MEMORY MANAGEMENT . . . . . . . . . .
.
General . . . . . . ..
e
e e e
e

oo 4-58
e 4-58

e e e 4-58

4.12.1.1

Introduction

. . . . . . . . L.

4.12.1.2

Programming

. . . . . . . . . ..o
e 4-59

412.1.3

Basic Addressing

Active Page Registers . . . . . . . . . ... 4-59

4.12.2
412.2.1

412.2.2
412.2.3

412.3

4.12.3.1
4.12.3.2
4.12.33
4.12.4

4.12.4.1
4.12.4.2

Lo . o

Capabilities Provided by Memory Management

e e

4.12.1.4
412.1.5

. . . . . . .

e e

e 4-59

. . . . . . . . . .. 4-60

Relocation
. . . . . . . . . . .
e
e e e 4-60
Virtual Addressing
. . . . . . . ..o 000 4-60
Program Relocation . . . . . . . . . .. ... 0.
Memory Units
. . . . . . . .
oL
o e
Protection
. . . . . . . . L .
e e
Inaccessible Memory
. . . . . . ..o
o 000 e d e e
Read-Only Memory

. . . . .
. . .
Active Page Registers . . . . . . .
Page Address Registers (PAR)
Page Descriptor Registers . .
Multiple Address Space

. . . . . . . oo
. . . .. ..o o000
. . . ... oo
. . . . . . . . .. .. ...
..
. . . . . . . . . .. ...
0.

4-61
4-63
4-63
4-63
4-63
4-63
4-64
4-65
4-65

41252

Virtual and Physical Addresses . . . . . . . . . . . ..o 4-70
Construction of a Physical Address . . . . . . . . . . .. ..... 4-70
Determining the Program Physical Address . . . . . . .. . . ... 4-71

4.12.6

Status Registers

4.12.5

4.12.5.1

4.12.6.1

. . . . . . . . .. ... oo 4-72

Status Register

O(SRO)

. . . . . . . . .. ... .o 4-72

CONTENTS (CONT)
Page
4.12.6.2
4.12.7
4.12.8

4.13

Status Register 2 (SR2)
Mode Description

. . .

Interrupt Conditions

CONTROL STORE

4.13.1

General Description

4.13.2
4.13.3

. . . . . . . . . . ... 4-74

. .

... oo 4-74

. . .

. .

...

Lo 4-74

. 4-75

. .

... 4-75

Branching Within Microroutines

. .

Control Store Fields

. .

. . . .

...

. . ..

. . .

..o

. .

. . . .

CHAPTER §

MICROCODE

5.1

MICROPROGRAM FLOWS

5.2

FLOW NOTATION GLOSSARY

. . .

...

... 4-75

L. 4-77

5-1

FIGURES
Title

Figure No.

Page

2-1

Addressing Mode Instruction Formats

PDP-11 Instruction Formats

. . .

. ..

. . . ...

...

... ........
...

2-2

........ 2-24

2-3

Extended Instruction Set Number Formats

4-1

KD11-EA Block Diagram

4-2

Simplified KD11-EA DataPath

4-3

ALU Block Diagram

. . . . . . . . . .. ... ...

4-6

4-4

Scratchpad Timing

. . . . . . . . . . .. ...

4-8

Scratchpad Address Multiplexer (SPAM)

4-6

B Leg Block Diagram

4-7

BREG Block Diagram
BX REG Block Diagram

4-9

BMUX Block Diagram

4-10
4-11

... .. ......
... ... .. .......

. . . ... ...

4-5

4-8

. . . . . . ... ... ... ... 2-30

. . . . . . . . . . ... ...

. . . . . . ... . ...

......

4-2
4-3

4-9

. . . . . . . .. ... ... ..., 4-12
. . . . . . . ... . ... .. 4-13
.

. .

. ..

... ... 4-15

. . . . . . . . .. ... ..., 4-16
. . . . . . . . . e, 4-18
AMUX Block Diagram . . . . . . . ... .. .. .., 4-22

B Leg Shift Logic

4-12

Processor StatusWord

4-13

Byte Multiplexer

4-14

Rotate Instructions

4-15

Cand VDecode ROM

. . . . . .

. ... Lo 4-24

. . . . . . . . .. 4-25
. . . . . . . . . ... 4-27

4-17

. . . . . . .. .. ...
. L, 4-28
. . . . . . . . .. . .. 4-28
Processor Clock Cycle Timing
. . . . . . . . . . ... . ... . ... .... 4-29

4-18

Unibus Address Logic Block Diagram

4-16

4-19
4-20

4-21

Unibus Transceiver

. . . . .. ... ... ... .. .... 4-29
. . . . . . . . . ... 4-40
NO-SACK Timeout Circuitry
. . . . . . . . . . . .
o
s
4-42
Unibus Synchronizer

SSYN/MSYN Control

. . . . .. . . .. ..

4-22

Data Transfer Multiplexer

4-23

Error Logic

. .

4-44
.

...

..... 4-45
. . . . ... 4-47

FIGURES (CONT)
Figure No.

Page

4-24

End-of-Transfer Logic

4-25

Odd Address Detection

. . . . . .

0oL 4-48

... ... ...

. . . . . . . . .. 4-48
. . . . . . . ... . ... .. 4-50

4-26

BUS AC LO and BUS DC LO Timing Diagram

4-27

Processor Clock Circuit

4-28

Priority Arbitration Synchronizer

4-29

Priority Bus Control

4-30

Active Page Registers

4-31

Simplified Memory Relocation Example

4-32

Relocation of a 32K Word Program into 124K-Word Physical Memory

4-33

Page Address Register

. . . . . . . . . . . . .

e 4-51

. .

..o 4-56

. .

. .. .o 4-54

oo 4-60

. . . . . .. .. ... ... .... 4-61
. . .. 4-62

Lo 4-65

oo 4-65

4-34

Page Descriptor Register

4-35

Example of an Upward-Expandable Page

4-36

Example of a Downward-Expandable Page

4-37

Interpretation of a Virtual Address

. . . . .. ... o000 4-70

. . . . . . . .. .. ... .. ... 4-67

. . . .

...

... 4-68

.... 4-70

4-38

Displacement Field of Virtual Address

4-39

Construction of a Physical Address

. . . . . . . . . . .. ... .. ... 4-71

4-40

Format of Status Register

. . . . . . . .. .. ... .. ... .. 4-72

O(SRO)

4-41

Format of Status Register 2 (SR2)

4-42

Control Store Fields

5-1

KDI11-EA Simplified Flow Diagram

. .

. . .

...

.. ..

. ..o 4-74

. . . . . . . . .« . . . oo 4-76
. .

. . . .

. .

. ...

...

... ....

TABLES

Table No.
2-1

Addressing Modes

. .

2-2

Single Operand Instructions

2-3

Double Operand Instructions

. . . . . . . . . . . ... 0oL
. . . . .

2-4

Program Control Instructions

. . . . . . . . . . .. oo

2-5

Miscellaneous Instructions

2-6

Condition Code Operators

. . . . . . . . . . .« v v v i v i i vt v

2-7

PDP-11/34A Instruction Set

2-8

Programming Differences

3-1

Standard and Modified Unibus Pin Assignments

. .

. . . . . .
.

. . . . . . . . . .

. . . . . . . . . ...

oo
oo

L oo
oo

o000

. . . . . . . .. . ... ...

4-1

Function Units of the KD11-EA DataPath

4-2

ALU Functions and Control Signals

4-3

Scratchpad Enabling Configurationsand Modes

4-4

SPAM Input Data Sources

. . . . . . . . . ..

4-5

SPM Register Utilization

4-6

B and BX Register Enabling Configurations and Modes

4-7

BMUX Enabling Configurations and Modes

. .

. . . . . ... .. ... ... ..

. . . . . . . . . . ..

. . . .

. . . . .

...
. . . .

...

... ...

. . . .. L0

. . . . . . . . . . ..

. . . . . . . . .. .. ... ...

5-2

TABLES (CONT)
Title

Table No.

Page

4-8

Processor Status Word Register Bit Assignments

4-9

Auxiliary Control for Binary and Unary Instructions

4-10

Priority Service Order

4-11

Vector Addresses

4.12

PAR/PDR Address Assignments

4-13

Access Control Field Keys

4-14

Relating Virtual Address to PAR/PDR Set

. . . . . . . . . . .

. . . . . . . .

. . . . . . . ... .. ... 4-23
. . ... . .. .. 4-38
4-53

L e 4-58

. . . . . . . . . . ..

. . . . . . . . . . . . .

vii

. . .

. .

e e 4-64

...

0. 4-66

. . . . . . .. .. ... ..... 4-72

PREFACE

This manual describes the KD11-EA Central Processing Unit (M8265 and M8266). The user must

have a general knowledge of digital circuitry and a basic understanding of PDP-11 computers to
completely understand the contents of this manual.
The following related documents may be valuable as references:
PDP-11 Peripherals Handbook

PDP-11/34 Processor Handbook
PDP-11/34 System User’s Guide (EK-11034-OP)
KD 11-EA Print Set (MP00043)

CHAPTER 1

OVERALL DESCRIPTION

The KDI1-EA is a 2-board central processing unit (CPU) that is combined with a memory system,

Unibus terminators, and optional peripherals in a DD 11-P backpanel to build a basic PDP-11/34A
computer. The unit connects directly to the Unibus as a subsystem, and is capable of controlling the
time allocation of the Unibus for peripherals, performing arithmetic and logic operations, and decoding instructions. It can perform data transfers directly between 1/0 devices and memory, do both
single- and double-operand addressing, handle both 16-bit word and 8-bit byte data, and address up to
128K of Unibus address space via a memory management system.

The KD11-EA is program-compatible with both the KD11-A (PDP-11/35 and PDP-11/40 computer
systems) and the LSI-11 (with the inclusion of the two special LSI-11 instructions). It contains the
KT11-D Memory Management System (optional with the KD11-A, not offered with the LSI-11) and

executes the Extended Instruction Set (EIS) instructions, which were optional with the KD11-A and
standard with the LSI-11. The KD11-EA, when used in conjunction with the FP11-A floating point
option, will execute the Full Floating Point Instruction Set (FP11-C compatible).

1-1

CHAPTER 2
INSTRUCTION SET

2.1
INTRODUCTION
The KD11-EA is defined by its instruction set. The sequences of processor operations are selected
according to the instruction decoding. The following describes the PDP-11/34A instructions and
instruction set addressing modes along with instruction set differences from those of the KD11-A,
KD11-B, and KD11-D.

2.2 ADDRESSING MODES
_
Data stored in memory must be accessed and manipulated. Data handling is specified by a PDP11/34A instruction (MOV, ADD, etc.), which usually indicates:
1.

The function (operation code)

A general-purpose register to be used when locating the source operand and/or locating the
destination operand

An addressing mode (to specify how the selected register(s) is to be used)

Because a large portion of the data handled by a computer is usually structured (in character strings, in
arrays, in lists, etc.), the PDP-11/34A has been designed to handle structured data efficiently and
flexibly. The general registers may be used with an instruction in any of the following ways:
1.

As accumulators. The data to be manipulated resides within the register.

As pointers. The contents of the register are the address of the operand, rather than the
operand itself.

As pointers, which automatically step through core locations. Automatically stepping forward through consecutive core locations is known as autoincrement addressing; automatically stepping backward is known as autodecrement addressing. These modes are
particularly useful for processing tabular data.

As index registers. In this instance the contents of the register and the word following the
instruction are summed to produce the address of the operand. This allows easy access to
variable entries in a list.

PDP-11/34As also have instruction addressing mode combinations that facilitate temporary data storage structures for convenient handling of data which must be frequently accessed. This is known as the
“stack.”

2-1

In the PDP-11/34A, any register can be used as a ‘“‘stack pointer” under program control; however,
certain instructions associated with subroutine linkage and interrupt service automatically use Register
6 as a “hardware stack pointer.” For this reason, R6 is frequently referred to as the “SP.”
R7 is used by the processor as its program counter (PC).

Two types of instructions utilize the addressing modes: single-operand and double-operand. Figure 2-1
shows the formats of these two types of instructions. The addressing modes are listed in Table 2-1.

L .3

T
1

OP
» =SPECIFIES DIRECT
*% =SPECIFIES

HOW

MODE

CODE

%
X

]

(@
1

DESTINATION

ADDRESS FIELD

INDIRECT ADDRESS

WILL BE

*%% = SPECIFIES ONE OF 8 GENERAL

USED

PURPOSE REGISTERS

(a)

* %

OP CODE
|

MODE

{

k5.5,

MODE

***,'

(©

SOURCE ADDRESS FIELD

DESTINATION

Rn
v

ADDRESS FIELD

» = DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS
+%x= SPECIFIES HOW SELECTED REGISTERS ARE TO
%% = SPECIFIES

GENERAL

USED

(b)
1-1227

Figure 2-1 Addressing Mode Instruction Formats

Table 2-1
Binary

Mode

Code

Addressing Modes
Assembler

Name

Syntax*

Function

Direct Modes

000

010

Autoincrement

(Rn)+

100

Autodecrement

-(Rn)

110

Index

X(Rn)

and. Register contents incremented
after reference.

before reference register contains
address of operand.

Value X (stored in a word following

the instruction) is added to (Rn) to
produce address of operand. Neither X nor (Rn) is modified.

Deferred Modes

001

@Rnor (Rn)

o011

Autoincrement
Deferred

@(Rn)+

Register is first used as a pointer to
a word containing the address of
the operand, then incremented
(always by two, even for byte
instructions).

101

Autodecrement

@-(Rn)

111

Index Deferred

@X(Rn)

Deferred

two, even for byte instructions) and
then used as a pointer to a word
containing the address of the
operand.
Value X (stored in the memory
word following the instruction) and
(Rn) are added and the sum is used
as a pointer to a word containing
the address of the operand. Neither
X nor (Rn) is modified.

2-3

Table 2-1
Binary

Mode

Code

Addressing Modes (cont)
Assembler

Name

Syntax*

Function

PC Addressing
2

010

Immediate

Operand follows instruction.

011

Absolute

@#A

Absolute

110

Relative

Address of A, relative to the

111

Relative Deferred | @A

instruction.

address

follows

instruction, follows the instruction.

Address of location containing
address of A, relative to the instruction, follows the instruction.

* Rn = Register
X, n, A = next program counter (PC) word (constant)

2.3

PDP-11/34A INSTRUCTIONS

The PDP-11/34A instructions can be divided into five groups:

Single-Operand Instructions (shifts, multiple precision instructions, rotations)
Double-Operand Instructions (arithmetic and logical instructions)
Program Control Instructions (branches, subroutines, traps)
Operate Group Instructions (processor control operations)
Condition Code Operators (processor status word bit instructions)

Tables 2-2 through 2-6 list each instruction, including byte instructions for the respective instruction

groups. Figure 2-2 shows the six different instruction formats of the instruction set, and the individual
instructions in each format.

2-4

Table 2-2

Mnemonic

OP Code

CLR

0050DD*

CLRB

1050DD

Operation

(dst)* <0

Single Operand Instructions

Condition Codes

N: cleared

Description

Contents of specified destination are replaced with zeroes.

Z: sct

Clear

V: cleared
C: cleared

COM

0051DD

COMB

1051DD

(dst) < n (dst)

N: set if most significant
bit of result is O

Complement

Z: setif result is O

INC

0052DD

INCB

1052DD

(dst) < (dst) + 1

cleared

set

N: set if result is less than O

Replaces the contents of the destination address by their
logical complement (each bit equal to O set and each bit equal
to 1 cleared).

Add 1 to the contents of the destination.

Z: setit resultis O

Increment

V: set if (dst) was Q77777

C: not affected
DEC

0053DD

DECB

1053DD

(dst) < (dst) -1

N: set if result is less than O

Subtract 1 from the contents of the destination.

Z: setif resultis O

Decrement

V: set if (dst) was 100000
C: not affected

NEG

0054DD

NEGB

1054DD

(dst) < -(dst)

set if result is less than O

Z: setif result is O

Negate

Replaces the contents of the destination address by its 2’s com-

plement. Note that 100000 is replaced by itself.

V: set if result is 100000
C: cleared if result is O

ADC

0055DD

ADCB

1055DD

Add Carry

(dst) « (dst) + C

set if result is less than O

Adds the contents of the C-bit into the destination. This permits

Z: setif result is O

the carry from the addition of the low-order words/bytes to be

V: setif (dst) is 077777 and |

carried into the high-order results.

Cisl

C: setif (dst)is 177777 and
Cisl

2-5

Table 2-2

OP Code

Operation

SBC

0056DD

(dst) < (dst) -C

SBCB

1056DD

Mnemonic

Single Operand Instructions (Cont)

Description

Condition Codes
set if result is less than O

Subtract Carry

Subtracts the contents of the C-bit from the destination. This

set if result is O

permits the carry from the subtraction of the low order words/

set if (dst) was 100000

bytes to be subtracted from the high-order part of the result.

cleared if (dst) is O and C
is 1

TST

0057DD

TSTB

1057DD

(dst) < (dst)

set if result is less than O

Sets the condition codes N and Z according to the contents of

set if result is O

the destination address.

cleared

Test

ROR

0060DD

(dst) < (dst)

RORB

rotate right

Rotate Right

one place.

cleared

set if high-order bit of

Rotates all bits of the destination right one place. The low-

the result is set

order bit is loaded into the C-bit and the previous contents of

. set if all bits of result

the C-bit are loaded into the high-order bit of the destination.

are 0

loaded with the exclusive-

OR of the N-bit and the
C-bit as set by ROR
ROL

ROLB

Rotate Left

. set if the high order bit of

Rotate all bits of the destination left one place. The high-

0061DD

(dst) < (dst)

1061DD

rotate left

the result word is set

one place.

(result < 0); cleared

previous contents of the C-bit are loaded into the low-order

otherwise

bit of the destination.

order bit is loaded into the C-bit of the status word and the

. set if all bits of the

result word = 0Q; cleared
otherwise

loaded with the exclusive-

OR of the N-bit and C-bit
(as set by the completion
of the rotate operation)

loaded with the high order
bit of the destination

2-6

Table 2-2

Mnemonic

OP Code

Single Operand Instructions (Cont)

Operation

Condition Codes

Description

ASR

0062DD

(dst) < (dst)

set if the high order bit

Shifts all bits of the destination right one place. The high-

ASRB

1062DD

shifted one

of the result is set

order bit is replicated. The C-bit is loaded from the low-order

Arithmetic

place to the

(result < 0), cleared

bit of the destination. ASR performs signed division of the

Shift Right

right.

otherwise

destination by two.

set if the result = 0;

cleared otherwise
. loaded from the exclusive-

OR of the N-bit and C-bit
(as set by the completion
of the shift operation).
. loaded from low order bit
of the destination

ASL

0063DD

(dst) « (dst)

N: set if high-order bit of the

Shifts all bits of the destination left one place. The low-order

ASLB

1063DD

shifted one

(result < 0); cleared

bit is loaded with a 0. The C-bit of the status word is loaded

Arithmetic

Shift Left

place to the left.

otherwise

from the high-order bit of the destination. ASL performs a

set if the result = 0; cleared

signed multiplication of the destination by 2 with overflow

otherwise

indication.

. loaded with the exclusiveOR of the N-bit and C-bit

and C-bit (as set by the
completion of the shift
operation)

. loaded with the high-order

bit of the destination

2-7

Table 2-2

Mnemonic
ASH

OP Code
072RSS

Single Operand Instructions (Cont)

Operation

Condition Codes

Description

R < R Shifted

N: set if result <O;cleared

The contents of the register are shifted right or left

Arithmetic

Arithmetically NN

otherwise.

the number of times specified by the source

Shift

places to right or

Z: set if result = O; cleared

operand. The shift count is taken as the low-order

left

otherwise.

6 bits of the source operand. This number ranges

Where NN = (src¢)

V: set if sign of register

from -32 to +31. Negative is a right shift and posi-

changed during shift; cleared |

tive is a left shift. See Paragraph 2.5 for example.

otherwise.
C: loaded from last bit shift
out of register.
ASHC

073RSS

Arithmetic
Shift Combined

R, Rvl«< R, Rvl

N: set if result <0; cleared

The contents of the register and the register ORed

The double word

otherwise.

with one are treated as one 32-bit word. Rvl (bits
0—15) and R (bits 16—31) are shifted right or left

is shifted NN

Z: set if result = 0; cleared

places to the right

otherwise.

the number of times specified by the shift count.

or left, where NN = |

V: set if sign bit changes

The shift count is taken as the low-order 6 bits of

(src)

during the shift; cleared

the source operand. This number ranges from -32

otherwise.

to +31. Negative is a right shift and positive is a

C: loaded with high-order bit |

left shift.

when right shift (loaded with | When the register chosen is an odd number, the
the last bit shifted out of the |

32-bit operand).

same. In this case, the right shift becomes a rotate.
The 16-bit word is rotated right the number of bits
specified by the shift count. See Paragraph 2.5 for
example.

SXT
Sign Extend

0067DD

(dst) < 0if N bit

N: unaffected

If the condition code bit N is set then a -1 is placed

is clear

Z: set if N bit clear

in the destination operand: if N bit is clear, then a

(dst) « -1 N bit

V: cleared

0 is placed in the destination operand. This instruc-

is set

C: unaffected

tion is particularly useful in multiple precision

arithmetic because it permits the sign to be extended

through multiple words.

2-8

Table 2-2

Mnemonic

SWAB
Swap Byte

OP Code

0003DD

Single Operand Instructions (Cont)

Operation

Condition Codes

Byte 1/Byte O
Byte O/Byte 1

Description

N: set if high-order bit of
low-order byte (bit 7) of
result is set; cleared

Exchanges high-order byte and low-order byte of the
destination word (destination must be a word
address).

otherwise.

Z: set if low-order byte of
result = 0; cleared otherwise.
V: cleared

C: cleared

Table 2-3

Mnemonic

MOV

MOVB

OP Code

Operation

01SSDD*

(dst) « (src) T

11SSDD

Move

Double Operand Instructions

Condition Codes

Description

N: set if (src) <O0; cleared

Word: Moves the source operand to the destination location.

Z: setif (src) = 0: cleared

operand is not affected.

otherwise

The previous contents of the destination are lost. The source

Byte: Same as MOV The MOVB to a resistor (unique among

V: cleared

byte instructions) extends the most significant bit of the low

C: not affected

order byte (sign extension). Otherwise. MOVB operates on
bytes exactly as MOV operates on words.

CMP

02SSDD

(src) - (dst)

DMPB

12SSDD

[in detail,

Compare

(src) +~

(dst) + 1]

N: set if result <0, cleared

otherwise
Z: set if result = 0; cleared

otherwise

Compares the source and destination operands and sets the

condition codes which may then be used for arithmetic and
logical conditional branches. Both operands are unaffected.

The only action is to set the condition codes. The compare is

V: set if there was arithmetic | customarily followed by a conditional branch instruction. Note

overflow (i.e., operands

that unlike the subtract instruction the order of operation is

were of opposite signs

(src) - (dst), not (dst) - (src).

and the sign of the destination was the same

as the sign of the result);
cleared otherwise.
C: cleared if there was a

carry from the most significant bit of the result;

set otherwise

2-9

Table 2-3

Mnemonic

BIT
BITB
Bit Test

OP Code

Operation

03SSDD
13SSDD

(src) A\ (dst) -

Double Operand Instructions (Cont)

Condition Codes

Description

N: set if high order bit of
result set: cleared otherwise

Performs logical AND comparison of the source and destination
operands and modifies condition codes accordingly. Neither
the source nor destination operands are affected. The BIT in-

Z: set if result = 0; cleared
otherwise

struction may be used to test whether any of the corresponding

bits that are set in the destination are clear in the source.

V: cleared

C: not affected

BIC
BICB
Bit Clear

04SSDD
14SSDD

(dst) < ~ (src)
/\ (dst)

N: set if high order bit of
result set; cleared otherwise

Z: set if result = 0;cleared

Clears each bit in the destination that corresponds to a set bit
in the source. The original contents of the destination are lost.
The contents of the source are unaffected.

otherwise
V:

cleared

C: not affected

BIS
BISB
Bit Set

05SSDD
15SSDD

(dst) < (src)
/\ (dst)

N: set if high order bit of
result set; cleared otherwise

Performs inclusive-OR operation between the source and destination operands and leaves the result at the destination
address; i.e., corresponding bits set in the destination. The

Z: set if result = 0; cleared

contents of the destination are lost.

otherwise

V: cleared

C: not affected

ADD
Add

06SSDD

(dst) < (src)
+ (dst)

N: set if result O; cleared
otherwise

Adds the source operand to the destination operand and stores
the result at the destination address. The original contents of

Z: set if result = 0: cleared
otherwise

the destination are lost. The contents of the source are not
affected. Two’s complement addition is performed.

2-10

Table 2-3

Mnemonic

OP Code

Operation

Double Operand Instructions (Cont)

Description

Condition Codes

set if there was arithmetic

ADD (Cont)

overflow as a result of the

operation (that is, both
operands were of the same
sign and the result was of

the opposite sign); cleared
otherwise.

. set if there was a carry from
the most significant bit of

the result; cleared otherwise.

SUB

16SSDD

Subtract

(dst) < (dst) (src) in detail,

(dst) + ~ (src)

+ 1 (dst)

set if result < O; cleared

Subtracts the source operand from the destination operand and

otherwise

leaves the result at the destination address. The original contents

. set if result = Q; cleared

of the destination are lost. The contents of the source are not

otherwise

affected. In double precision arithmetic, the C-bit, when set,

set if there was arithmetic

indicates a borrow.

overflow as a result of

the operation (i.e., if
operands were of op-

posite signs and the sign
of the source was the

same as the sign of the

result); cleared otherwise
. cleared if there was a
carry from the most

significant bit of the
result; set otherwise

* SS = source (address mode and register)
1 (src) = source contents

2-11

Table 2-3

Mnemonic
MUL

OP Code

Operation

070RSS

R, Rvl< Rx(src)

Multiply

Double Operand Instructions (Cont)

Condition Codes
N: set if product is <0;

Description
The contents of the destination register and source

cleared otherwise.

taken as two’s complement integers are multiplied

Z: set if product is O;

and stored in the destination register and the suc-

cleared otherwise.

ceeding register (if R is even). If R is odd, only the

V: cleared

low-order product is stored. Assembler syntax is:

C: set if the result is less

MUL S,R.

than -2'° or greater than
or equal to 2'° -1.

(Note that the actual destination is R, Rvl which
reduces to just R when R is odd.)
(See Paragraph 2.5.1 for example).

DIV

071RSS

Divide

R, Rvl < R, Rvl

N: set if quotient <0;

The 32-bit two’s complement integer in R and Rvl

(src)

cleared otherwise.

is divided by the source operand. The quotient is

Z: set if quotient = 0;

left in R; the remainder is of the same sign as the

cleared otherwise.

dividend. R must be even.

V: set if source = 0 or if the

(See Paragraph 2.5.2 for example.)

absolute value of the register
is larger than the absolute

value of the source. (In this
case the instruction is

aborted because the quotient
would exceed 15 bits.)
C: set if divide O attempted;

cleared otherwise.

XOR

074RDD

(dst) < Rv (dst)

N: set if the result <0;

The exclusive OR of the register and destination

cleared otherwise.

operand is stored in the destination address. Contents

Z: set if result = 0;

of register are unaffected. Assembler format is

cleared otherwise.

XOR R,D.

V: cleared

C: unaffected

2-12

Table 2-4

Mnemonic

OP Code

Operation

000400

PC « PC +

Branch

XXX

(2 X offset)

Program Control Instructions

Condition Codes
Unaffected

Description
Provides a way of transferring program control within a range

of -128 to +127 words with a one word instruction. It is an
unconditional branch.

BNE

001000

PC <« PC +

Branch if not

XXX

(2 X offset)

is clear. BNE is the complementary operation to BEQ. It is

ifZ=0

used to test inequality following a CMP, to test that some bits

equal

Unaffected

Tests the state of the Z-bit and causes a branch if the Z-bit is

set in the destination were also in the source, following a BIT,

and generally, to test that the result of the previous operation
was not 0.

BEQ

001400

PC «<PC +

Branch if equal

XXX

(2 X offset) if

Unaffected

Tests the state of the Z-bit and causes a branch if Z is set. As
an example, it is used to test equality following a CMP opera-

Z=1

tion, to test that no bits set in the destination were also set in

the source following a BIT operation, and generally, to test

that the result of the previous operation was O.

BGE

002000

PC < PC +

Branch if greater

XXX

(2 X offset) if

BGE is the complementary operation to BLT. Thus. BGE

NvV=0

always causes a branch when it follows an operation that

than or equal

Unaffected

Causes a branch if N and V are either both clear or both set.

caused addition to two positive numbers. BGE also causes a

branch on a 0 result.

2-13

Table 2-4

Mnemonic

OP Code

Operation

BLT
Branch if less

002400
XXX

PC <« PC +
(2 X offset) if

than

Program Control Instructions (Cont)

Condition Codes

Unaffected

NVv=]

Description

Causes a branch if the exclusive-OR of the N- and V-bits are 1.
Thus, BLT always branches following an operation that added
two negative numbers, even if overflow occurred. In particular,
BLT always causes a branch if it follows a CMP instruction
operating on a negative source and a positive destination (even

if overflow occurred). Further, BLT never causes a branch when
it follows a CMP instruction operating on a positive source and
negative destination. BLT does not cause a branch if the result

of the previous operation was 0 (without overflow).

BGT

003000

PC < PC +

Branch if greater
than

XXX

(2 X offset)
if Zv (N

Unaffected

Operation of BGT is similar to BGE, except BGT does not

cause a branch on a 0 result.

V)=0

BLE

003400

PC «PC +

Branch if less than

XXX

(2 X offset) if

or equal to

Unaffected

Operation is similar to BLT, but in addition will cause a branch
if the result of the previous operation was 0.

Zv(NTMV)
=1

BPL

100000

PC <« PC +

Branch if plus

XXX

(2 X offset) if

Unaffected

Tests the state of the N-bit and causes a branch if N is clear.

BPL is the complementary operation of BMI.

N=0

BMI

100400

PC < PC +

Branch if minus

XXX

(2 X offset) if

Unaffected

Tests the state of the N-bit and causes a branch if N is set. It is

used to test the sign (most significant bit) of the result of the

N=1

previous operation.

2-14

Table 2-4

Mnemonic

OP Code

Operation

Program Control Instructions (Cont)

Condition Codes
Unaffected

Description

BHI

101000

PC < PC +

Branch if higher

XXX

(2 X offset) if

Causes a branch if the previous operation causes neither a carry

nor a 0 result. This will happen in comparison (CMP) operations

C=0

as long as the source has a higher unsigned value than the
destination.

BLOS

101400

PC < PC +

Branch if lower

XXX

(2 X offset) if

or a 0 result. BLOS is the complementary operation to BHI.

CvZi=1

The brar.ch occurs in comparison operations as long as the

Or same

Unaffected

Causes a branch if the previous operation caused either a carry

source is equal to or has a lower unsigned value than the

destination. Comparison of unsigned values with the CMP
instruction to be tested for “‘higher or same” and “higher” by
a simple test of the C-bit.

BVC

102000

PC < PC +

Branch if V-bit

XXX

(2 X offset) if

clear

BVS
Branch if V-bit set

Unaffected

Tests the state of the V-bit and causes a branch if the V-bit is

clear. BVC is complementary operation to BVS.

V=0

102400
XXX

PC < PC +
(2 X offset) if

Unaffected

V=1

BCC

103000

PC < PC +

BHIS

XXX

(2 X offset) if

Branch if carry

Tests the state of V-bit (overflow) and causes a branch if the
V-bit is set. BVS is used to detect arithmetic overflow in the
previous operation.

Unaffected

Tests the state of the C-bit and causes a branch if C is clear.
BCC is the complementary operation to BCS.

C=0

clear
Branch if higher
than the same
BCS

103400

PC < PC +

BLO

XXX

(2 X offset) if

Branch if carry set

Unaffected

Tests the state of the C-bit and causes a branch if C is set. It is

used to test for a carry in the result of a previous operation.

C=1

Branch if lower

2-15

Table 2-4

Mnemonic
JMP
Jump

OP Code
0001DD

Operation
PC < (dst)

Program Control Instructions (Cont)

Condition Codes
Unaffected

Description
JMP provides more flexible program branching than provided
with the branch instruction. Control may be transferred to any
location in memory (no range limitation) and can be accomplished with the full flexibility of the addressing modes. with

the exception of register mode 0. Execution of a jump with
mode O will cause an illegal instruction condition. (Program
control cannot be transferred to a register.) Register deferred
mode is legal and will cause program control to be transferred

to the address held in the specified register. Note that instructions are word data and must therefore be fetched from
an even numbered address. A boundary error trap condition

will result when the processor attempts to fetch an instruction

from an odd address.

2-16

Table 2-4

Mnemeonic

JRS
Jump to
subroutine

OP Code

Operation

004RDD

(tmp) <« (dst)
(tmp is an internal processor

Program Control Instructions (Cont)

Condition Codes

Unaffected

Description

In execution of the JSR, the old contents of the specified
register (the linkage pointer) are automatically pushed onto
the processor stack and new linkage information placed in

the register. Thus, subroutines nested within subroutines to any

{ (SP) < reg
(push reg con-

depth may all be called with the same linkage register. There
is no need either to plan the maximum depth at which any

tents onto proces-

particular subroutine will be called or to include instructions

sor stack)

in each routine to save and restore the linkage pointer. Further,

reg < PC PC

since all linkages are saved in a re-entrant manner on the pro-

holds location fol-

cessor stack, execution of a subroutine may be interrupted,

lowing JSR; this

and the same subroutine re-entered and executed by an in-

address PC <

terrupt service routine. Execution of the initial subroutine can

(tmp), now put in

then be resumed when other requests are satisfied. This pro-

(reg)

cess (called nesting) can proceed to any level.
JSR PC, dst is a special case of the PDP-11 subroutine call
suitable for subroutine calls that transmit parameters.

RTS

Return from
subroutine

00020R

PC < (reg)

(reg) < SP 1

Unaffected

Loads contents of register into PC and pops the top element

of the processor stack into the specified register.
Return from a non-re-entrant subroutine is typically made
through the same register that was used in its call. Thus, a
subroutine called with a JSR PC, dst exits with an RTS PC,

and a subroutine called with a JSR RS, dst may pick up

parameters with addressing modes (RS) +, X (R5), or @X (R5)
and finally exit, with an RTS RS.

2-17

Table 2-4

Mnemonic
MARK

OP Code
0064NN

Operation
SP < SP + 2xnn
PC <« RS

Program Control Instructions (Cont)

Condition Codes
Unaffected

Description
Used as part of the standard PDP-11 subroutine return
convention. MARK facilitates the stack cleanup pro-

RS < (SP) t

cedures involved in subroutine exit. Assembler format

nn = number of

is: MARK N

parameters

Example:MOV R5,-(SP)

;place old RS on stack

MOV P1,«(SP)

;place N parameters on

MOV P2,-(SP)

;the stack to be used
;there by the subroutine

MOV PN,<(SP)

;places the instruction

MOV #MARKN,~SP) :MARK N on the stack
;set up address at Mark

MOV SP,R5

:N instruction

JSR

;jump to subroutine

PC,SUB

At this point the stack is as follows:

OLD RS
Pl

PN
MARK N

OLD PC
And the program is at the address SUB which is the

beginning of the subroutine.

SUB:

sexecution of the subroutine itself

RTS R5:

;the return begins

This causes the contents of R5 to be placed in the PC

which then results in the execution of the instruction
MARK N. The contents of old PC are placed in R5

MARK N causes: (1) the stack pointer to be adjusted to
point to the old RS value; (2) the value now in R5 (the

old PC) to be placed in the PC; and (3) contents of the
old R5 to be popped into RS, thus completing the return

from subroutine.

2-18

Table 2-4

Mnemonic

SOB
Subtract one and

OP Code

077R00
plus offset |

Operation

R«<R-1
if this result #

branch if not

0 then PC « PC

equal to O

- (2 x offset)

Program Control Instructions (Cont)

Condition Codes

Unaffected

Description

The register is decremented. If it is not equal to 0, twice
the offset is subtracted from the PC (now pointing to the
following word). The offset is interpreted as a six-bit

positive number. This instruction provides a fast, efficient
method of loop control. Assembler syntax is:
SOB R,A
where A is the address to which transfer is to be made if

the decremented R is not equal to 0. Note that the SOB
instruction cannot be used to transfer control in the
forward direction.

BPT

000003

Break-point Trap

I0T
IOT Trap

000004

1 (SP) < PS

N: loaded from trap vector

Performs a trap sequence with a trap vector address of 14.

V (SP) < PC

Z: loaded from trap vector

Used to call debugging aids. The user is cautioned against

PC < (14)

V: loaded from trap vector

employing code 000003 in programs run under these

PS < (16)

C: loaded from trap vector

debugging aids.

} (SP) < PS

N: loaded from trap vector

Performs a trap sequence with a trap vector address of

1 (SP) « PC

Z: loaded from trap vector

20. Used to call the I/O executive routine IOX in the

PC < (20)

C: loaded from trap vector

paper-tape software system and for error reporting in the

PS < (22)

disk operating system.

2-19

Table 2-4

Mnemonic

EMT

OP Code

104000

Emulator Trap

Operation

Program Control Instructions (Cont)

Condition Codes

Description

J (SP) « PS

N: loaded from trap vector

All operation codes from 104000 to 104377 are EMT

V (SP) <« PC

Z: loaded from trap vector

instructions and may be used to transmit information to

PC < (30)

V: loaded from trap vector

the emulating routine (e.g., function to be performed).

PS < (32)

C: loaded from trap vector

The trap vector for EMT is at address 30; the new central

processor status (PS) is taken from the word at address 32.
CAUTION
EMT is used frequently by DEC system software
and is therefore not recommended for general use.

TRAP

104400 to
104777

{ (SP) < PS

N: loaded from trap vector

Operation codes from 104400 to 104777 are TRAP instruc-

{ (SP) « PC

Z: loaded from trap vector

tions. TRAPs and EMTs are identical in operation, except

PC < (34)

V: loaded from trap vector

that the trap vector for TRAP is at address 34.

PS < (36)

C: loaded from trap vector

NOTE

Since DEC software makes frequent use of EMT, the
TRAP instruction is recommended for general use.

NOTE: Condition Codes are unaffected by these instructions
*DD = destination (address mode and register)

(dst) = destination contents

2-20

Table 2-5

Mnemonic
RTI

OP Code
000002

Operation

Miscellaneous Instructions

Condition Codes

Description

PC < (SP) t

N: loaded from processor

Used to exit from an interrupt or trap service routine.

PSW « (SP) 1

stack

The PC and PSW are restored (popped) from the pro-

Z: loaded from processor

cessor stack. If the RTI sets the T-bit in the PSW, a

stack

trace trap will occur prior to executing the next

V: loaded from processor

instruction.

stack
C: loaded from processor

stack
RTT

000006

PC < (SP) 1

PS < (SP) t

N: loaded from processor

This is the same as the RTI instruction, except that it

stack

inhibits a trace trap, while RTI permits a trace trap.

Z: loaded from processor

If a trace trap is pending, the first instruction after the

stack

RTT will be executed prior to the next “T” trap. In

V: loaded from processor

the case of the RTI instruction, the “T” trap will

stack

occur immediately after the RTIL.

C: loaded from processor

stack
MFPI

0065SS

(temp) < (src)

N: set if the source <0;

This instruction pushes a word onto the current stack

MFPD

1065SS

V (SP) « (temp)

otherwise cleared

from an address in previous space. Processor Status

Z: set if the source =0;

(bits 13, 12). The source address is computed using

otherwise cleared

the current registers and memory map.

V: cleared

C: unaffected
MTPI

0066SS

(temp) < (SP) 1

N: set if the source <0;

This instruction pops a word off the current stack

MTPD

1066SS

(dst) < (temp)

otherwise cleared

determined by PS (bits 15, 14) and stores that word

Z: set if the source =0;

into an address in previous space PS (bits 13, 12).

otherwise cleared

The destination address is computed using the cur-

V: cleared

rent registers and memory map.

C: unaffected

2-21

Table 2-5

Mnemonic
MFPS

Miscellaneous Instructions (Cont)

OP Code

Operation

Condition Codes

Description

1067DD

(DST) < PSW

N: set if PSW bit 7=1;

*The 8-bit contents of the PS are moved to the

DST Lower

otherwise cleared.

effective destination. If destination is mode O, PS

8 bits

Z: set if PS[0:7]=0;

bit 7 is sign-extended through upper byte of the

otherwise cleared.

V: cleared

address.

C: not affected

MTPS

1064SS

PSW <« (SRC)

Set according to

*The 8 bits of the effective operand replace the

effective SRC operand

current contents of the PSW. The source operand

0-3.

address is treated as a byte address. Note that PSW
bit 4 cannot be set with this instruction. The SRC
operand remains unchanged.

*Because there is no hardware to prevent execution
of these instructions in User mode, it is necessary
for the system software to prevent any reference to

the PSW address by a user.

HALT

000000

Unaffected

Causes the processor operation to cease. The console
is given control of the processor. The console data

lights display the address of the HALT instruction
plus two. Transfers on the Unibus are terminated

immediately. The PC points to the next instruction
to be executed. Pressing the CON key on the console
causes processor operation to resume. No INIT

signal is given.

2-22

Table 2-5
Mnemonic

WAIT

OP Code

Operation

000001

Miscellaneous Instructions (Cont)
Condition Codes

Unaffected

Description

Provides a way for the processor to relinquish use of

the bus while it waits for an external interrupt. Having
been given a WAIT command, the processor will not
compete for bus by fetching instructions or operands
from memory. This permits higher transfer rates
between device and memory, as no processor-induced

latencies will be encountered by bus requests from
the device. In WAIT, as in all instructions, the PC
points to the next instruction following the WAIT
operation. Thus, when an interrupt causes the PC and
PS to be pushed onto the stack, the address of the
next instruction following the WAIT is saved. The exit

from the interrupt routine (i.e., execution of an RTI

instruction) will cause resumption of the interrupted
process at the instruction following the WAIT.
RESET

000005

PC (SP)
PSW (SP)

Unaffected

Sends INIT on the Unibus for 100 ms. All devices on

the Unibus are reset to their state at power-up.

2-23

Table 2-6

Condition Code Operators

Mnemonic

Op Code

CLC

000241

CLV

Clear condition code C.

000242

CLZ
CLN

Clear condition code V.

000244
000250

Clear condition code Z.
Clear condition code N.

Instruction

CCC
SEC

000257

Clear all condition code bits.

000261

SEV
SEZ
SEN

000262
000264
000270

Set condition code C.
Set condition code V.
Set condition code Z.

SCC

000277

Set condition code N.
Set all condition code bits.

NOTE
Selectable combinations of condition code bits may
be cleared or set together. The status of bit 4 controls
the way in which bits 0, 1, 2, and 3 are to be modi-

fied. If bit 4 = 1, the specified bits are set; if bit 4 =
0, the specified bits are cleared.

1. Single Operand Group {CLR,CLRB,COM,COMB,INC,INCB, DEC,DECB,NEG,NEGB, ADC,ADCB,SBC,SBCB,TST,TSTB,ROR,RORB,ROL.,ROLB,ASR, ASRB,
ASL,ASLB, JMP, SWAB)

)

OP Code

]

)
[

Dst

{

2.0oubte Operand Group(BIT,BIT8,BIC,BICB,BIS,BISB,ADD,SUB)

Code

Src

i
12

dst

]

]
6

{

3.Program Control Group
a.Branch(ail branch instructions)

]

OP Code

]

|
8

offset

)

b.Jump To Subroutine {(JSR)

reg

)

]

Src/dst

]

c.Subroutine Return (RTS)
0

]

{

]

reg

d.Traps (break point, IOT,EMT,TRAP)
OP CODE

]

4.0Operate Groupe {HALT,WAIT,RTI,RESET)

0P CODE

)

5.Condition Code Operatfors
(all condition code instructions)

11-1226

Figure 2-2

PDP-11 Instruction Formats

2-24

2.4

INSTRUCTION EXECUTION TIME

The execution time for an instruction depends on the instruction itself, the modes of addressing used,
and the type of memory being referenced. In the most general case, the instruction execution time is the
sum of a source address (SRC) time, a destination address (DST) time, and an execute, fetch (EF) time.

Instr Time = SRC Time + DST Time + EF Time
Some of the instructions require only some of these times, and are so noted in Paragraph 2.4.1. All
timing information is in microseconds, unless otherwise noted. Times are typical; processor timing can
vary +10%.

2.4.1
Basic Instruction Set Timing
Table 2-7 lists the PDP-11/34A instruction set, together with the timing characteristics and memory
cycles required. The timing requirements for determining instruction execution time are listed below.
Double-Operand {(all instructions)

Instr Time = SRC Time + DST Time + EF Time
Single-Operand (all instructions)

Instr Time = DST Time + EF Time

Branch, Jump, Control, Trap, and Miscellaneous (all instructions)
Instr Time = EF Time

NOTES
The times specified apply to both word and byte
instructions, whether odd or even byte.
Timing is given without regard for NPR or BR
servicing.
If the memory management is enabled, instruc-

tion execution times increase by 0.12 us for
each memory cycle used.
4.

All timing is based on memory with the following performance characteristics:
Access Time

Cycle Time

Memory

(us)

Core
(MM11-DP)

0.510

1.1

MOS

0.635

0.920

(MS11-JP)

2-25

Table 2-7

PDP-11/34A Instruction Set

SOURCE ADDRESS TIME

Instruction

Double Operand

Source

Memory

Core

MOS

Mode

Cycles

(MM11-DP)

(MS11-JP)

0.00

1.33

1.46

2.37

2.62

1.13

1.26

1.28

1.41

2.57

2.82

2.57

2.82

3.80

4.18

DESTINATION TIME

Instruction
Modifying Single-Operand

Destination

Memory

Mode

Cycles

Core

MOS

0.00

1.74

and Modifying Double-

1.62

Operand (Except MOV,

1.77

1.89

SWAB, ROR, ROL, ASR,

2.90

3.15

ASL)

1.77

1.89

3.00

3.25

5.10

3.35

4.29

4.66

0.00

MOV

MTPS

0.93

2.17

2.29

1.13

2.22

2.34

2.37

2.49

3.50

3.75

0.00

0.95

1.13

1.26

2.26

2.51

1.13

1.26

2.26

2.51

2.44

2.69

3.57

4.20

2-26

Table 2-7

PDP-11/34A Instruction Set (Cont)

DESTINATION TIME
Instruction
MFPS

Destination

Memory

Mode

Cycles

0.00

0.64

Core

MOS

1.95

2.08

0.82

1.95

2.08

2.13

2.26

3.26

3.51

Cycles

Core

MOS

2.03

2.16

1.83

1.96

1.83

1.96

SWAB, NEG

2.03

2.16

ROR, ROL, ASR, ASL

2.18

2.31

MTPS

2.99

3.12

MFPS

1.99

2.12

MUL

8.82*

8.95*

DIV (overflow)

2.78

2.91

12.48

12.61

EXECUTE,

FETCH TIME

Destination
Instruction

Mode

' Memory

Double Operand
ADD, SUB, CMP, BIT, BIC,
BIS, XOR
MOV

Single Operand
CLR, COM, INC, DEC, ADC,
SBC, TST

EIS Instructions (use with DST

times)

ASH

4.18**

4.31%*

ASHC

4.18**

4.31**

MFPI(D)

3.07

3.14

MTPI(D)

3.37

3.34

Memory Management Instructions

2-27

Table 2-7 PDP-11/34A Instruction Set (Cont)
EXECUTE, FETCH TIME
Instruction
SWAB, ROR, ROL, ASR,
ASL

Non-modifying
Single Operand and
Double Operand

MFPI(D)
MTPI(D)

Destination

Memory

Mode

Cycles

Core

MOS

0
1

0
2

0.00
1.42

0.00
1.54

1.57

1.69

2.70

2.95

1.62

1.74

2.80

3.05

2.90

3.15

4.09

4.46

0
1
2

0
1
1

0.00
1.13
1.28

0.00
1.26
1.41

2.42

2.67

1.33

1.46

2.52

2.77

2.62

2.87

3.80

4.18

0
1

0.00
0.98

0.00
1.24

2
3
4
5
6
7

1
2
1
2
2
3

1.32
2.20
1.18
2.20
2.40
3.59

2.45
1.44
2.45
2.65
3.96

2.18

2.31

1
1
1

1.63
2.38

1.76
2.51

1.98

2.11

1.44

Branch Instructions

BR, BNE, BEQ, (Branch)
BPL, BMI, BVC, BVS, BCC,

BCS, BGE, BLT, BGT, BLE,
BHI, BLOS, BHIS, BLO

(No Branch)
SOB (Branch)
(No Branch)

2-28

Table 2-7

PDP-11/34A Instruction Set (Cont)
EXECUTE, FETCH TIME

Instruction

Destination

Memory

Mode

Cycles

Core

MOS

Jump Instructions
IMP

JSR

1.83

1.96

2.18

2.31
3.37

3.12

2.03

2.16

3.07

3.32

3.07

3.32

4.25

4.78

3.32

3.44

3.47

3.59

4.40

4.65

3.32

3.44

4.40

4.65

4.60

4.85

5.69

6.06

RTS

3.32

3.57

MARK

4.27

4.52

RTI, RTT

4.60

4.98

Set or Clear C,V,N, Z

2.03

HALT

1.68

2.16
1.81

WAIT

1.68

1.81

RESET

100 ms

10T, EMT, TRAP, BPT

7.32

7.7

*Add 200 ns for each bit transition in serial data from LSB to MSB.

**Add 200 ns per shift.

2-29

2.4.2 Bus Latency Times
|
Interrupts (BR requests) are acknowledged at the end of the current instruction. For a typical instruction, with an instruction execution time of
4 us, the average time to request acknowledgement would

be 2 us.

Interrupt service time, which is the time from BR acknowledgement to the first subroutine instruction,

is 7.32 us max for core, and 7.7 us for MOS.
NPR (DMA) latency, which is the time from request to bus mastership for the first NPR device, is 2.5
us max.

2.5
EXTENDED INSTRUCTION SET
The Extended Instruction Set (EIS) provides the user with the capability of extended manipulation of
fixed-point numbers. Use of the EIS instructions does not degrade processor timing or affect NPR

latency. Interrupts are serviced at the end of an EIS instruction.
The EIS instructions are:

Mnemonic

Instruction

Op Code

MUL

Multiply

070RSS

DIV

Divide

ASH
ASHC

Shift arithmetically
Arithmetic shift combined

071RSS
072RSS
073RSS

The number formats are shown in Figure 2-3. Examples of the operation of each instruction are

presented in the paragraphs that follow.

NUMBER

16-BIT SINGLE WORD:

(‘

)

]

0
HIGH NUMBER PART

S
|

]

32-BIT DOUBLE WORD: <

LOW NUMBER PART

S is the sign bit.

S = 0 for positive quantities
S = 1 for negative quantities; number is in 2's
complement notation
11-4453

Figure 2-3

Extended Instruction Set Number Formats

2-30

Multiply Instruction - MUL 070RSS

Example: 16-bit product (R is odd)
000241
012701,400
070127,10
1034xx

, CLC
, MOV #400,R|
, MUL #10, R1
, BCS ERROR

;Clear carry condition code

:Carry will be set if

;product is less than

;=213 or greater than or ;equal to 2!*
;no significance lost
Before
(R1) = 000400

After
(R1) = 004000

Divide Instruction - DIV 071RSS
Example: ’

005000
012701,20001

, MOV #20001,R
1

, CLR RO

071027.2

, DIV #2,R0

Before

After

(R0) = 000000

(R0O) = 010000 Quotient

(R1) = 020001

(R1) = 000001 Remainder

Arithmetic Shift Instruction - ASH 072RSS
Example: ASH RO, R3

Before

(R3) = 000003

After
(R3) = 000003

(R0O)=001234

(R0O) = 012340

Arithmetic Shift Combined Instruction - ASHC 073RSS

Example: Similar to the example for the ASH instruction except that two registers are used.
2.6 INSTRUCTION SET DIFFERENCES
Table 2-8 lists the instruction set differences between the PDP-11/34A and other PDP-11 machines.

2-31

Table 2-8
11/05 and 11/10

Programming Differences

11/35 and 11/40

11/04

Same as 11/05

Same as 11/40

Same as 11/05

11/34A

GENERAL REGISTERS (including PC and SP)

OPR%ZR (R)+

Initial contents of R

Contents of R are

or OPR%R ,«R)

are used as the source

incremented by 2 (or

OPR%R ,@(R)+

operand.

OPR%R ,@<(R)

decremented by 2),
before being used as

(Using the same register

the source operand.

as both source and

destination)
JMP(R)+ or JSR

Contents of R are

Initial contents of P

incremented by 2,

are used as new PC.

using autoincrement)

then used as the new
PC address.

MOV PC, @#A or

Location A will con-

MOV PC, A (Moving

tain PC + 2.

tain the PC of the

the incremented PC

move instruction +4.

to a memory address

referenced by the PC)
Stack Pointer (SP),

Using the SP for

Odd address or non-

R6 used for referenc-

pointing to odd

existent memory

ing.

addresses or non-

references with SP

existent memory

cause a fatal trap with

causes a halt (double

a new stack created at

bus error).

locations 0 and 2.

2-32

Table 2-8
11/05 and 11/10

Programming Differences (Cont)
11/35 and 11/40

11/04

11/34A

Same as 11/05

GENERAL REGISTERS (including PC and SP) (Co nt)

Stack Overflow

Stack limit fixed at

Variable limit with stack

‘4004 overflow (going

limit option. Overflow

lower) checked after

checked after JSR, traps,

modes 4 and S using

and address modes 1, 2,

R6, and JSR and traps.

4, and 6. Non-altering

Overflow serviced by

references to stack data

an overflow trap. No

are always allowed.

red zone.

There is a 16-word

yellow (warning) zone.

Red zone trap occurs if
stack is 16 words below

boundary; PS and PC
are saved at locations

Oand 2.
TRAPS AND INTERRUPTS
RTI Instruction

First instruction after

If RTI sets the T-bit,

RTI instruction is

the T-bit trap is acknowl-

always executed.

edged immediately after

Same as 11/40

the RTI instruction.

RTT Instruction

Not implemented

First instruction after

Same as 11/40

Same as 11/05

RTT is guaranteed to

be executed.
Processor status odd

Odd byte of PS can be

byte at location

addressed without a

777777

trap.

Same as 11/05

2-33

Table 2-8
11/05 and 11/10

Programming Differences (Cont)
11/35and 11/40

11/04

11/34A

Same as 11/05

Same as 11/40

GENERAL REGISTERS (including PC and SP) (Cont)
T-bit of PS

T-bit can be loaded
by direct address of

Only RTI, RTT traps

PS or from console.

the T-bit

PC unincremented

Same as 11/05

PC incremented

PC unincremented

Same as 11/05

Same as 11/40

Same as 11/05

Same as 11/05 except

and interrupts can load

Bus Errors

PC contains odd
address
PC contains an

address in nonexistent memory

for MOV mode 2 and

odd address and

MTPI where the

instruction mode 2

Same as 11/04 except for

address in nonexist-

MOV mode 2 destination

ent memory and

and MTPI where the

instruction mode 2.

Interrupt service

The first instruction

routine.

will not be executed

Same as 11/05

if another interrupt

occurs at a higher
priority.

2-34

Table 2-8

11/05 and 11/10

Programming Differences (Cont)

11/35and 11/40

11/34A

11/04

GENERAL REGISTERS (including PC and SP) (Cont)
Priority order of

Odd address

Halt instruction

Same as 11/40

of traps and

Time-out

Odd address

Bus error

except no red

interrupts

Halt instruction

Stack overflow (red)

Trap instruction

zone stack over-

Trap instructions

Mem mgt error

Trace trap

flow

Trace trap

Time-out

Stack overflow

Parity

Power fail

Trap instruction

Halt from console

Trace trap

Interrupts

Stack overflow (yellow)

Next instruction fetch

Power fail

Halt from console

MISCELLANEOUS
Swab and V-bit

V-bit is cleared.

Same as 11/05

Instruction set

Basic set

Basic set and Mark,

Basic set and RTT

Memory management

Does not apply

Same as 11/05
Basic set and Mark,

RTT, SOB, SxT, XOR.

RTT, SOB, SxT, XOR,

EIS adds: MUL, DIV

MUL, DIV, ASH,

ASH, ASHC.

ASHC, MTPI, MFPI,

FIS adds: FADD,

MTPS, MFPS. (MTPS

FSUB, FMUL, FDIV.

and MFPS are new

KT11-D adds: MTPI,

instructions used for

MFPI.

LSI-11.)

If a mem mgt viola-

Does not apply

If a mem mgt viola-

violation during a

tion occurs between

trap sequence

the first and second

push down of the stack

during a trap sequence,

the status of the CPU

the status of the vector

before the violation is

+2 of the original trap

placed as the PS on the

is placed as the PS on

the Kernel stack.

2-35

CHAPTER 3

CPU OPERATING SPECIFICATIONS

Operating Temperature

5° to 50° C (41° to 122° F)

Relative Humidity |

20 to 95% (without condensation)

Input Power

+5 Vdc £5% at 4.5 A (typical) per module (M 8265 and M 8266)

Physical Size

Two hex modules (8-1/2 X 15 in.)

Interface Requirements

All 1/0 signals are available on connectors A and B. These signals are pin-compatible with modified Unibus pinout as shown
in Table 3-1. The bus loading on each of these Unibus lines is
equivalent to one bus load.

Power and Ground Pinouts

+5 V: pins AA2, BA2, CA2, DA2, EA2, EA2

GND: pins AC2, AT1, BC2, BT1, CC2, CT1, DC2, DT1, EC2,
ET1, FC2, FT1

Number of Integrated
Circuits

231 (M 8265 = 123, M8266 = 112)

3-1

3-2

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CHAPTER 4

DETAILED HARDWARE DESCRIPTION

4.1

INTRODUCTION

The following paragraphs contain a detailed circuit description of the KD11-EA Central Processing
Unit (CPU), which is used in the PDP-11/34A Computer. Segments of the CPU, shown in Figure 4-1,
are analyzed separately, using the block diagrams contained in this manual and the KD 11-EA circuit
schematics.

4.2
4.2.1

DATA PATH
General Description

The simplified KD11-EA data path consists of six function units, as shown in Figure 4-2. Circuit
schematics K1-1 through K1-4 (D-CS-M8265-0-1) each contain one 4-bit slice of the data path. Table
4-1 briefly describes the function of each of the six function units.

Data flow through the data path is controlled, directly or indirectly, by the Control Store circuitry on
the control module (M8266). Each Control Store ROM location (microinstruction) generates a unique

set of outputs capable of controlling the data path elements and determining the ALU function to be
performed. Sequences of these ROM microinstructions are combined into microroutines, which perform the various PDP-11 instruction operations.

4-1

WT0¥1I1NOD[aQv3o0l0—30¥l%019MsdX88a:4
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1‘H8O-N2)VTH[86--2N)O|STYN9iInySg I TOHLNi“1O-1I3)n(-gu1dm=1s-1ee2)MS(d(_bJp$=z-SIXXelO-WL-)1¥t)v=-]en()-=I1-L)4(b= (L-1M)ao 1))(6=

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a(2-2)‘1-2X)

4-2

NN 1
[4:

vad

31v02073Y

4/Q

2\
ENABLE DATA

BUS DATA

SSMUX [15:00]

KT MODES

VBA

CC DATA

15:00

AUX

CONTROL —_—

SWAP

SWAP + SEX

PSW MUX

MUX

SEX

BX MODE 1—

BMODE 1

BXREG

8X MODE 0 R

BMOD

+1
EXTERNAL DATA PATH

BREG

BLEG 0

SCRATCH PAD

‘r

MEMORY
(TR1
STATE)

SRO

SR2

ENAB —

]

PAR’S

| MoCE

epbrs

VBA

]

AMUX S1

[

A MUX

KT MUX

TRI STATE AMUX

AMUX SO

15:00

CONSTANTS
(VECTORS)

‘
ALU CIN

6-12

SRO

PAR + PDR

(TRI STATE)

ENABLE

aEamm—— BUS CONTROL

ALU

ADDRESS
(VBA)

G, G

von

e ACCESS

VBA

ALU S1

ALU SO

PROCESSOR

Y ; MODES

BUS DATA 15:00

€

SS CONTROL

BITS ACFO, ACF
1

Z?‘Z‘

ALU MODE
BUS DATA

COMPARATCH

VIRTUAL BUS

U s2

KT MUX

ALU S3
AL

VBA 13

BMUX

PSW

VBA 15

VBA 14

BLEG 1

LOAD PSW

[

PSWY 15,14, 13, 12

ADDERS

KT ERROR
LOGIC
ERKORS

PHYSICAL BUS

ADDRESS 17:00 (PBA)

USED IN INTERNAL

o
5

comg:;relow
_

_—

foc;lc

LOAD BA

ADDRESS DECODE
LOGIC

|———— ENABLE ADDRS

READ ONLY

PACE LENGTH

CC DATA
A

VBA
05

6:17

NON RESIDENT

L.JUF

RELOCATE

BUS ADDRS

DEFINITIONS: SRO — MEMORY MANAGEMENT CONTROL REGISTER 0"

SR2 — MEMORY MANAGEMENT CONTROL REGISTER ’2”
PAR — PAG ADDRESS REGISTER
PDR — PAGE DESCRIPTION REGISTER

KT ERROR
DISABLE MSYNM
IgEzr;JGTRAP

11-8183

Figure 4-2

Simplified KD1i-EA Data Path

Table 4-1

Function Units of the KD11-EA Data Path

Unit

Function

Arithmetic Logic Unit (ALU)

The heart of the data path is the ALU, which is the logic ele-

ment that manipulates the data. It is capable of performing 16
arithmetic or 16 logic (Boolean) operations on two 16-bit operands to produce a 16-bit result. The A input comes from either
the scratchpad memory or the memory management system; the
B input comes from the B leg. The ALU output is sent to the
AMUX.
ALU Multiplexer (AMUX)

The AMUX is a 4-to-1 tristate multiplexer that controls the
introduction of new data and the circulation of available data

through the data path. Input to the AMUX is both external
(from the Unibus data lines) and internal (from the ALU, PSW,
or constants). The AMUX output is sent to the SSMUX.
When the signal TRI STATE AMUX L 1s asserted, these multiplexers assume a high impedance state and external data can be

input to the SSMUX from the connector J1 on the M8265
module.
Processor Status Word Register
(PSW)

The PSW register is a 12-bit register that contains information
on the current processor priority, condition codes (C, V, Z, and
N) which indicate the results of the last instruction, a *““trap” bit
(TBIT) which causes automatic traps after each fetch instruction used during program debugging, and both the current and
previous memory management modes (Kernel or User). PSW
input comes from the SSMUX or from condition code logic;
PSW output is sent to the AMUX.

Swap Sign Extend Multiplexer
(SSMUX)

This multiplexer controls the form in which data is output from,
or recirculated into, the data path. The SSMUX can pass the
data unchanged, swap the high and low bytes, sign-extend the
low byte into the entire word, or simultaneously swap high and
low bytes while sign-extending the high byte (which becomes the
new low byte) into the entire word. SSMUX input comes from
the AMUX or from the external data path (connector J1) if the
AMUX assumes a high impedance state. SSM UX output goes
to either the rest of the computer system (via the Unibus), the
other sections of the processor (the control section, via the
Instruction register, and the memory management system), or
to other portions of the data path (the PSW, the B leg, and the
scratchpad memory).

4-4

Table 4-1

Function Units of the KD11-E Data Path (Cont)

Unit

Function

B Leg

The B leg of the ALU consists of two 16-bit registers (B and BX)
and a 4-to-1 multiplexer (BMUX). Both registers can shift left
or right independently, or together they can perform full 32-bit
shifts. The BMUX selects one of the four functions (BREG,
BXREG, +1, +16) and connects to the B input of the ALU.
The B leg is used to store operands for the ALU, to implement
rotate and shift instructions, and to implement Extended
Instruction Set (EIS) instructions. B leg input comes from the
SSMUX. B leg output goes to the B input of the ALU.

Scratchpad Memory (SPM)
:

This random access memory can store sixteen 16-bit words in
eight processor-dedicated registers and eight general-purpose
(user available) registers. One of the general-purpose registers is
used as a stack pointer, another as the program counter. Input
to the scratchpad memory is from the SSMUX. Output, which
can be buffered and latched to enable reading from one address
and modifying another during the same cycle, goes to the A
input of the ALU and to the Virtual and Physical Bus Address
registers.

4.2.2 Arithmetic Logic Unit (ALU)
The ALU (Figure 4-3) is divided into four 4-bit slices (K1-1, K1-2, K1-3, and K1-4 each contain a

slice), with each slice consisting of one 4-bit ALU chip (74S181) and part of a Look-Ahead Carry
Generator chip (745182).
ALU Inputs
|
7
The A input to each ALU chip comes from one of the scratchpad memory (SPM) registers or from the

KTMUX, as specified by the Control Store microinstruction being performed. (Refer to Paragraph
4.2.3 for details.) The B input comes from the B leg multiplexer (BMUX) logic, and can take the form
of the B register contents, the BX register contents, a constant 0, a constant 1, or a constant 16. (Refer
to Paragraph 4.2.4 for details.)

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ALU Functions

The function performed by the ALU is controlled by the four Selection bits (S3, S2, §1, §0), the Mode
bit (M), and the Carry-In bit (CIN). Table 4-2 lists the ALU functions of the KD11-EA and the
corresponding bit patterns for the six control signals,

Table 4-2

4.2.3

ALU Functions and Control Signals
ALU Control Signals

ALU Function

CIN

ZERO
A
A plus |
A minus 1
A minus B
A
B
A plus B
AB
AB
A plus B plus |
AplusA
B
A plus A plus 1
A+ B

0
0
0
1
0
1
1
|
1
0
1
1
0
1
0

0
0
0
1
1
1
0
0
0
0
0
1
1
1
1

1
0
0
1
1
1
1
0
1
1
0
0
0
0
1

1
0
0
1
0
1
0
1
1
0
0
0
1
0
0

0
0
0
1
0
0
0
1
0
0
0
1
0
0
0

1
1
0
0
0
1
1
0
1
1
0
0
1
0
1

Scratchpad

The scratchpad consists of a random access memory that can store sixteen 16-bit words, and can be
used for various functions. Scratchpad operation is divided into four 4-bit slices, with K1-1, K1-2, K13, and K 1-4 (D-CS-M8265-0-1) each containing one slice. The scratchpad address multiplexer circuitry
is shown on K2-4.

Data Input

Data to be written into the scratchpad is channeled from the SSMUX and clocked into the scratchpad

registers.
Addressing the Scratchpad

The address of the scratchpad memory register to be accessed is generated by the scratchpad address
multiplexer (SPAM), located on the control module (K2-4). Depending on the state of the select lines
to the SPAM, the source of the address can be any of the following:
The Control Store ROM (ROMSPA03:ROMSPAQO).
Instruction Register Source Field (IR08:1R06)
Instruction Register Destination Field (IR02:IR00)
Bus Address (PBA03:00)

Reading from the Scratchpad
[f the Control Store circuitry forces a low on the K1-10 ENAB GR L line at the beginning of a

machine cycle, the tristate outputs of the scratchpad will be enabled. Ninety or 120 nanoseconds after
the cycle begins (allows the scratchpad address to set up), K1-5 TAP 30 H goes low, allowing data
stored in the selected scratchpad register to be latched in the output buffer SP15:SP0O lines. This data
will continue to be read during the rest of the machine cycle. (See Figure 4-4.) Table 4-3 shows the
various scratchpad enabling configurations and the modes they select.

|l=

EWW

MACHINE CYCLE

TAP 30H
|

]

ENAB GR L |
SP WRITE L |
PROC CLK

L_J
READ SOURCE

WRITE

SCRATCH PAD

DESIGNATICN

INTO

SCRATCH PAD REGISTER

LATCH SCRATCH PAD

OUTPUT BUFFERS

TAP 30 H

meoow

[

PROC CLK L

[
|_]
je—— 180

1
L]

—

NOTE:
Source and Designation Register

do not

have to be the same. Register selected

may be changed (See SPA Mux description )
for second haif of machine cycle.
11-3878

Figure 4-4

Table 4-3

OD
L

| WE | CLK | OS
L

Scratchpad Timing

Scratchpad Enabling Configurations and Modes

|Mode

Outputs

[OUTPUT STORE

Data from last addressed location

X | WRITE DATA

Data being written (if OD = L and OS = H)

H | READ DATA

Data stored in addressed location

[OUTPUT STORE

High-impedance state

|OUTPUT DISABLE

High-impedance state

4-8

Latching of Outputs
When the OD (pin 12) and OS (pin 13) inputs are both low, the data being read from the scratchpad

that is addressed is latched into the buffers on the output of scratchpad memory (SP15-00). Once those
outputs are stabilized, they are not affected by any modifications to the scratchpad memory address
lines for the remainder of the cycle.
Clocking the Scratchpad
The REG CLK H clock signal clocks data from the SSMUX lines into the scratchpad register and
writes that data into scratchpad memory. TAP 30 H unasserted, placing a high at the OS input (pin 13)

of the scratchpad, is all that is required for a read operation. Both a read and a write can take place
during the same machine cycle. Figure 4-4 shows the scratchpad timing for one machine cycle.
Scratchpad Address Multiplexer (SPAM)
The SPAM (Figure 4-5) generates the four address signals that select the desired scratchpad register, or
word. The SPAM (shown in print K2-4 of D-CS-M8266-0-1) consists of two 74S153 dual 4-line-to-1line data multiplexers, or a total of four 4-to-1 multiplexers, all with a common strobe input signal

(GND) and common address input signals (S1 and 30). Four data input sources are connected so that,

when the SPAM is addressed and strobed, it generates one 4-bit output, selected from one of the four

sources. Table 4-4 lists the sources of SPAM input data and the address input signal configurations
that select them,

PBA |

> D

IR-SRC |

IR-0ST [

N ¢ 74813

STORE ROM L

>A $(1:0)

CONTROL

(K2-4)

SPAM F :> SPM
0

K2-9 SPA DST

SEL (1:0) (1)
H

K2-9 SPA SRC

SEL (1:0) (1) H

(K2-4)

745157

STB

NOTE:
SPA= 6, forced to 16 for
user mode ROM,IR-SRC,
IR-DST.

K1-5 TAP 30 H

Figure 4-5

11-3880

Scratchpad Address Multiplexer (SPAM)

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4-10

Scratchpad Memory Organization

The scratchpad memory (SPM) is a 16-word-by-16-bit random access read/write memory composed
of four 16-word-by-4-bit bipolar (85S68) memory units (K1-1 through K1-4). The 16-word-by-16-bit
organization of this memory provides 16 storage registers that are utilized as shown in Table 4-5.

Table 4-5

SPM Register Utilization

R2
R3
R4
RS

General-Purpose Registers

(Processor Stack Pointer)

(Program Counter)

R10

Temporary Storage

R11

Unused

R12

Temporary Storage

R13

Temporary Storage

R14

Unused

R15

Temporary Storage

R16

Processor Stack Pointer

(Memory Management User Mode)
R17

Temporary Storage

4-11

Scratchpad Outputs
Data outputs from the scratchpad are fed to the ALU as the A leg input and to the memory management system.

42.4

B Leg
The B leg (Figure 4-6) of the ALU consists of three components: the B register, the BX register, and the
B leg multiplexer (BMUX). Each of these components is divided into four 4-bit slices, with circuit
schematic prints K1-1, K1-2, K1-3, and K 1-4 each containing a slice. Data from the SSMUX can be
clocked into either register. Register contents can be shifted either individually as 16-bit words or
together as a double (32-bit) word.

MODE 292
MOD

B MODE

S1]s@]

L | L

|HOLD

S1 SO SR
B

REG.
BITSD-15) («1-1eK1-4)

74194

CLK

SHIFT

H RiGHT

L [CerT

SHIFT

H |H

”fl

]

SHIFT IN B

+16

—2

PROC. CLK

[LOAD

FROM

B
ALC

(K1-1+K1-4)

8 MODE 91

:> T1 5‘0

—

St SO SR

srsey

BLEG@!

REC

(Kt-1=Ki-4)

CLK

s1lsp|

L!'L |

L | H | BX

I
SHIFT IN BX

BLEG 0@

H
St | s@
L | L

16
H

4+1

|HOLD

SHIFT

L | H |RiGHT]
SHFT

HL [LeFT
H

|LOAD
11-3881

Figure 4-6

B Leg Block Diagram

4-12

B Register

The B register (B REG) is a general-purpose storage register (Figure 4-7) on the B leg of the ALU,
consisting of four 4-bit bidirectional universal shift registers (74194). The mode control lines of the
four 4-bit registers are connected in parallel, so that the signals K2-8 B MODE 00 L and K2-8 B
MODE 01 L select the function that will be performed by the B register when clocked by K1-5 PROC
CLK L. Table 4-6 shows the various functions and the shift configurations that select them.

K2-8 BMODE

K2-8

BMODE 90 L

}

{fi'

——
y

S1 S@ SR

B REG

|[BITS 12415

(K1-4)

BITS 12-15

74194

BIT 12

{—& ' L
BITS 8-

|giT 11

SOSR|

B REG

> (K1-3) [BITS8-11)
74194

K-10 SHIFT IN O7 H —

> TO BMUX

BIT 7

31 50 SR

FROM SS MUX I

B REG

> (K1-2) [BITS 4->

BITS 4-7

74194

CLK
K1-5 PROC CLK L—]

4
BIT

}—

S1 SO SR
B REG

BITS @-3 J|> (ki-1)

74194

CLK

;

BIT 3

[B1TS o-3>

S1]5@ [FUNCTION

L|L | HOLD

L | H|

SHIFT
RiGHT

SHIFT

HiL | CeFT
H|H|

LoaD

K1-10 SHIFT IN B H
11-5184

Figure 4-7 BREG Block Diagram

4-13

Table 4-6

B and BX Register Enabling Configurations and Modes

Mode

Hold

Contents of register do not change.

Shift Right

Contents are shifted right one bit.

Shift Left

Contents are shifted left one bit.

Parallel Load

Data from SSMUX is loaded into B register
and appears at output.

Function (when PROC CLK L goes high)

The B register can be shifted as an 8-bit byte or a 16-bit word. The signal K1-10 SHIFT IN B deter-

mines what is shifted into the B register. When the contents of this register and the BX register are
combined into a 32-bit word, the B register contains the upper 16 bits.
BX Register

The BX register (BX REG) is a general-purpose storage register (Figure 4-8) on the B leg of the ALU,
consisting of four 4-bit bidirectional universal shift registers (74194), similar to the B register. The
mode control lines of the four 4-bit registers are connected in parallel, so that the signals K2-8 BX
MODE 00 L and K2-8 BX MODE 01 L select the function to be performed when the BX REG is
clocked by K1-5 PROC CLK L. The BX register can be shifted as a 16-bit word or, in conjunction with
the B register, as a 32-bit word. In the latter case, the BX register contains the lower 16 bits of the 32bit word, and the shift right (SR) input of the most significant register in the BX register is connected
to the zero bit of the B register. Table 4-6 shows the various functions and the shift configurations of
K2-8 BX MODE 00 L and K2-8 BX MODE 01 L that select them.
B Leg Multiplexer (BMUX)

The BMUX (Figure 4-9) consists of three 2-to-1 multiplexers and a 4-to-1 multiplexer, and is used to
select the proper input to be used as an operand on the B leg of the ALU. The BMUX can select the
contents of either the B REG or BX REG, or can act as a constant generator (constants 16, 1, or 0),
depending on the configuration of signals K2-8 B LEG 00 H and B LEG 01 H (Table 4-7) and the state
of K2-4 DISAB MSYN +1 L.

4-14

K1-1

BREG @90 (1) H

___{::::i*S@ SR

BITS 12-15
K1-5 PROC CLK L —

BX REG

)

74194

{

CLK

t—

BITS 8-11

> (K1-4) [BITS12-15

S@ SR

BIT 12

BIT

BX REG

> (K1-3) [BITS 8~‘1>
74194

CLK

BIT
8

|
K FROM SS MUX (:

—i5 1
S1

BITS 4-7

SO SR

BIT 7

REG

> (K1-2) |BITS 4->
74194

CLK
K2-8 BX MODE Of L —

) TO BMUX

BIT 4

{

K2-8 BX MODE 00 L —

BITS O-3

SO SR

BIT 3

1 | so [FUNCTION

BX REG

fi'> (K1-1) [BITS0-3>
74194

L L | HOLD

SHIFT

RIGHT

CLK

SHIFT

HIL ] LEFT
H

{ H{

LOAD

Ki1-10 SHIFT INBX H
11-3883

Figure 4-8

BX REG Block Diagram

4-15

(K1-4)

FROM BX REG

BITS ‘2_115>B
B MUX
FlBITs 12-15

74157

12—15>A

BITS

STB

—

(K1-3)
BITS 8-11

2B
B MUX
FBITS 8-11

BITS

K2-8 BLEG OOH
K2-8

74157

8—11>A

BLEG O1H

STB

CIP

FROM B REG

(K1-2)

ALU

.|
T

BITS 4-7 ¥B

V'l

B Mux

74157

BLEG|BLEG

B-REG

4—2/A

BIT 2

K2-4 DISABLE
BIT @

MSYN +

K2-8 AUX

STB

BIT 3 )
_1BIT 2 N

CONTROL (1) H |giT1

x|r|xo

BITS

ITix|r

FIBITS 4-7

BIT 3

FUNCTION

BX-REG

16
1

S0
{K1-1)

>c B MUX

/7[72&@

FIBITS 0-3
BITS 0-3 }B

BITS 0-3

JA
S

74153

|
11-3884

Figure 4-9

BMUX Block Diagram

4-16

Table 4-7

BMUX Enabling Configurations and Modes

B Leg

Function

B REG

BX REG

Passes data from the BX register to the BMUX
outputs. This is used principally for EIS
instructions.

+16

Forces the constant +16 into the BMUX outputs
to preset a counter that is used for EIS instructions.

Forces the constant +1 into the BMUX outputs
during operations in which the contents of a register are being incremented or decremented by two.

By asserting DISABLE MSYN +1 L, this configuration forces the constant 0 into the BMUX
outputs during operations in which the contents of
a register are being incremented or decremented by
one. (The signal K2-8 ALU CIN L to the ALU
from the control module provides the one.)

Description

Passes data from the B register to the BMUX out-

puts. This is the most common configuration.

B Leg Shift Capabilities
Each of the four shift registers (74194) that make up each register (B REG and BX REG) has the
capability of being shifted left or right, as indicated in Table 4-6 and Figure 4-10. The B register can be
shifted as an 8-bit byte or a 16-bit word; the BX register can be shifted as a 16-bit word or, in conjunction with the B register, as a 32-bit word.
Byte Shifts
If the mode control lines (K2-8 B MODE 00 L and K2-8 B MODE 01 L) specify a shift left, B REG
15:00 are shifted one position toward the most significant bit at the clock pulse K1-5 PROC CLK L
going high. The signal K1-10 SHIFT IN B H is shifted into bit 00 via the SL input. This signal is
generated by the SHIFT MUX (E119 on print K1-10) as a function of the select signals K2-8 SHIFT
MUX 01 L and K2-8 SHIFT MUX 00 L. The shift right input to B REG bits 07:04 comes from the
BYTE MUX (E108 on print K1-10). Assertion of K2-5 BYTE L (indicating a byte instruction) causes
bit 07 of the B REG to be loaded directly by K2-5 SERIAL SHIFT H; if K2-5 BYTE L is high,
however, B REG bit 07 is loaded from B REG 08. B REG bit 15 is loaded from K1-10 SHIFT IN
BH
during a shift right (just as B REG bit 00 is loaded during a shift left), and can be loaded with itself,
K2-5 SERIAL SHIFT H, ground, or BX REG bit 15, depending on the SHIFT MUX. For a shift
‘right, BX REG bits 15:01 are shifted one position toward the least significant bit, and BX REG bit 15
is loaded with B REG bit 00. Thus, for all right shifts, the BX REG acts as the low-order 16 bits of a
32-bit word made up of B REG and BX REG. For a shift left, BX REG bits 15:00 are shifted one bit
position toward the most significant bit. BX REG bit 00 is loaded with the signal K1-10 SHIFT IN BX
H, which is generated by the SHIFT MUX. Depending on the configuration of the SHIFT MUX
control lines K2-8 SHIFT MUX 00 L and K2-8 SHIFT MUX 01 L, the BX REG may be loaded with
any of four possible inputs: K1-4 ALU COUT H, the output of the EIS overflow detection logic (E100
on print K1-10), ONE, and ZERO.

4-17

r— S et

GETS S

Sr]_|

12-15

(K1-4)

(K1-10)
:

STB

I (K1-83.)11SL

lx-2) st

| [ areF

K2-5 BYTE L

K1-10 SHIFT INB H

(Kgl‘s'm
OVERFLOW

+3D

A;‘

DETECTION

LOGIC

ENAB

CLR

Ke-2 PROC"N'TD

B REG_I

c1
B

8-1

|
|

74194

(K1-4) sL[)

| |

.., 5F

(K1-2)

O_BSR

(K1-1) sL

$
. I
|

SL[]

KI-1OSHIFT INBX H e _BEG'

K2-8 SHIFT MUX D0OL

)

SHIFT

Ki-4 ALU CONT H

MUX 01 L

| (K1-4) SL

K2-8 ENABOVXL | \ 5 o oiFT

K2-5 LOAD
IR H

{_ 12 158R

AD MUX

—|—

0-3

SR|_

L (K1-10)
K2-5 SERIAL SHIFT H

_J
11 - 3885

Figure 4-10

B Leg Shift Logic

4-18

Specific Shift and Rotate Operations

The shifting requirements for the ASL, ASR, ROL, ROR, ASH, and ASHC instructions are described
briefly below.

Arithmetic Shift Left (ASL) - Shifts all bits of the destination left one place. The low-order

bit is loaded with a 0. The C-bit of the status word is loaded from the high-order bit of the

destination. ASL performs a signed multiplication of the destination by 2, with overflow
indication.

Arithmetic Shift Right (ASR) - Shifts all bits of the destination right one place. The high-

order bit is duplicated. The C-bit is loaded from the low-order bit of the destination. ASR
performs signed division of the destination by two.

Rotate Left (ROL or ROLB, depending on whether a word or byte operation) — Rotates all
bits of the destination left one place. The high-order bit is loaded into the C-bit of the status
word, and the previous contents of the C-bit are loaded into the low-order bit of the
destination.

Rotate Right (ROR or RORB) - Rotates all bits of the destination right one place. The low-

order bit is loaded into the C-bit, and the previous contents of the C-bit are loaded into the
high-order bit of the destination.

Arithmetic Shift (ASH) - Shifts the contents of the register right or left the number of times
specified by the source operand. The shift count is taken as the low-order six bits of the
source operand. This number ranges from -32 to +31. Negative is a right shift and positive
is a left shift.

Arithmetic Shift Combined (ASHC) - Treats the contents of the register and the register
ORed with one as one 32-bit word. Rv1 (bits 15:00) and R (bits 31:16) are shifted right or left
the number of times specified by the shift count. The shift count is taken as the low-order six
bits of the source operand. This number ranges from -32 to +31. Negative is a right shift
and positive is a left shift. (When the register chosen is an odd number, the register and the
register ORed with one are the same. In this case, the right shift becomes a rotate. The 16-bit
word is rotated right the number of bits specified by the shift count.)
NOTE
When R is an even-numbered register, Rv1l will be
the next highest register. If R is an odd-numbered
register, Rvl will be the same register (e.g., if R =
R4, then Rvl = RS; if R = RS, then Rvl = RS).

4-19

BMUX Operation
Three 2-to-1 multiplexers (74157s) are used to switch B leg bits 15:04. Their select lines are tied in
parallel with each other and with the SO line of the 4-to-1 multiplexer (two 74153s) used to switch B leg
bits 03:00. The SO line is signal K2-8 B LEG 00 H. Signal K2-8 B LEG 01 H is connected to the enable
lines of the 2-to-1 multiplexers and to the S1 line of the 4-to-1 multiplexer. Table 4-7 describes the
enabling configurations and modes for these two select signals, which are logically determined as

follows:
1.

If both K2-8 B LEG 00 H and K2-8 B LEG 01 H are low, the 4-to-1 multiplexer (E9 and E6
on print K1-1) selects the A input and the 2-to-1 multiplexers (E30 on print K1-2, E20 on
K1-3, and E40 on K1-4) select the A inputs; the data from the B REG is switched to the
BMUX output.

If K2-8 B LEG 01 H is low and K2-8 B LEG 00 H is high, the 4-to-1 multiplexer selects
input B, the 2-to-1 multiplexers remain enabled, and the data from the BX REG is switched
to the BMUX output.

If K2-8 B LEG 01 H is high and K2-8 B LEG 00 H is low, the 2-to-1 multiplexers are not
enabled. The 4-to-1 multiplexer selects input C, where bit 0 is low and bits 03:01 are connected to K2-8 AUX CONTROL (1) L unasserted, generating a +16 constant to the B leg.

If both K2-8 B LEG 01 H and K2-8 B LEG 00 H are high, the 2-to-1 multiplexers are still
disabled and the 4-to-1 multiplexer selects input D, where bits 03:01 are grounded and bit 00
is connected to K2-4 DISABLE MSYN +1 L unasserted, generating a constant of +1 to the
B leg.
'

If,in 4 above, K2-4 DISABLE MSYN +1 L is asserted, a constant of 0 is generated to the B
leg.

Constants +16, +1, and 0

The purpose of generating the constants +1 and 0 on the B leg input of the ALU is to aid the processor
to perform autoincrement and autodecrement operations. During either operation, if a word instruction is being performed, the specified register is incremented or decremented by two; if a byte instruction is being performed, the register is incremented or decremented only by one. The actual ALU
operation is:
-

RESULT = A LEG DATA + B LEG DATA + ALU CIN.
The ALU always uses the K2-8 ALU CIN L signal to increment or decrement the A leg input by one;
thus, the B leg input must provide the constant +1 or 0 to obtain the correct autoincrement or autodecrement result for both byte and word instructions. A B leg constant of +1 is generated by enabling
the least significant bit of the BMUX output (bit 00) and forcing all other bits (15:01) to 0. To generate
a constant 0, even bit 00 is cleared. The actual constant generated is defined by the state of the K2-4
DISABLE MSYN +1 L signal, which is determined by the Control Store.

4-20

4.2.5 ALU Multiplexer (AMUX)
The AMUX (Figure 4-11) consists of four 4-to-1 tristate multiplexers (74S253s), each one dedicated to
a 4-bit slice of the AMUX. If the signal K1-1 TRI STATE AMUX H is asserted, the STB input will be

high and each multiplexer will assume a high impedance state. This condition will allow external data
to be brought into the KD11-EA data path via connector J1. If the STB input is low, the output of

each multiplexer will follow one of the inputs, corresponding to the binary value of select lines St and
SO (K1-10 AMUX S1 H and K1-10 AMUX SO H, respectively), as follows:

1.
2.

Unibus Data Function - If both S1 and SO are low (binary 0), the 4-to-1 multiplexers select

input A, Thus, each 4-bit slice of the AMUX switches Unibus data into the data path.

Constant’s Function - Certain operations require the introduction of specific numbers into
the data path. (For example, the data path must generate a vector of 24 for a power-fail trap,

or 114 for a parity trap.) Access to these and other numbers is facilitated by storing certain
constants in a read-only memory and presenting them to the constant’s input of the AMUX.
If S1 is low and S0 is high (binary 1), the multiplexers select input B (the constant’s input).
Bits 11:08 are not used.

ALU Input - If S1 is high\and SO is iow (binary 2), the multiplexers select the ALU inputs

PSW Input - If both S1 and SO are high (binary 3), the multiplexers select the PSW input
(input D).

(input C).

4.2.6 Processor Status Word
The Processor Status Word (PSW) register contains information on the current and previous memory
management mode, the current processor priority, a processor trap for debugging, and the condition
code results of the previous operation. The PSW bit assignments and uses are shown in Table 4-8.

The PSW (Figure 4-12) is a 12-bit register composed of three quad D-type flip-flops (74175s) and one
separate D-type latch. The first of these (E97 on print K1-1) stores the condition code bits (N, Z, V,
and C), and derives its input from the PSW MUX, a quad 2-line-to-1-line multiplexer (E98 on K1-1)
according to the state of the SO select line. When high, SO selects the B inputs (SSMUX bits 03:00);
when low, SO selects the A inputs, which come from the condition code logic (print K1-10). The
selected inputs are passed to the f-outputs of the multiplexer and into the PSW.
A second quad D-type flip-flop (E99 on K1-2) is used to store the three KD 11-EA processor priority
bits, which it obtains from SSMUX bits 07:05. A separate 74S74 (E109 on K1-2) is needed to store the
Trace Trap flag (T-bit), which can be loaded from the K1-2 SSMUX 04 H line.
The third quad D-type flip-flop (E82 on K1-4) stores the bits containing the current and previous

status of the memory management mode. SSMUX bits 15 and 14 provide the in»ut for PSW bits 15
and 14, which are then rerouted through a quad 2-line-to-1-line multiplexer (E92 on K1-4) and multiplexed with SSMUX bits 13 and 12 according to the state of the SO select signal [K2-9 FORCE
KERNEL (1) H] to provide the input for PSW bits 13 and 12. Thus, PSW bits 15 and 14 reflect the
current status of the memory management mode, while PSW bits 13 and 12 indicate the previous
status,

All flip-flops in the PSW are clocked, directly or indirectly, by clocking signal K1-5 REG CLK L. All

of the enabling signals come from the Control Store.

4-21

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4-22

Table 4-8 Processor Staths Word Register Bit Assignments
PSW Bit

Name

Use

15:14

Memory Management
Current Mode

Contain the current memory management modes.

Memory Management

Contain the previous memory management modes.

13:12

Previous Mode

11:08

Unused

07:05

Priority

Set the processor priority.

Trace

When this bit is set, the processor traps to the trace
vector. Used for program debugging.

Set when the result of the last data manipulation is
negative,

Set when the result of the last data manipulation is
Zero.

Set when the result of the last data manipulation
produces an overflow.

Set when the result of the last data manipulation
produces a carry from the most significant bit.

4-23

SS MUX (15:14) |
PSW (15:14)

fi'>B|Ts(:<1;=.:l))
B

(K1-4)

PSW(15:12) | MEM.MGMNT, MODE
BITS (13:12)

PSW MUX

A <0
SS MUX { 13:12 ) E>STB
FORCE KERNAL (1) H

LOAD H PSW

CLR

CLK

——(f

777

(K1-2)

SS MUX (07:05)

PSW(07:05)

({ REG. CLK)

CLR CLK

SS MUX 04

0 (k1-2)

[ (LOAD PSW LOW)+{LOAD PSW 12-15)] 5

ToO

AMUX

]

PSW@4a

(REG CLK)- ( LOAD PSW)

PRIORITY

[T-BIT

CLK
CLR

$S MUX (03:00) :>B (K1-1)

(K1:1)

PSW MUX F>
A
CC LOGIC [:>STB

PSW (03:00)

C.V,N,Z

CLR LK

(AUX CONTROL )-(LOAD PSW LOW)

PROC INIT L
(REG CLK)- [(LOAD PSW) +
(LOAD PSW LOW )+ (LOAD CC)]
11-3887

Figure 4-12

Processor Status Word

4-24

4.3

CONDITION CODES

The logic necessary for determining the condition codes is shown on sheets Ki-idhanth®2+52ahdcan!
be subdivided into three parts, each of which is discussed in some detail in this section. Gonstraints fol
each condition code bit are shown in the instruction set specifications (Chapter 2).
B

4.3.1 Instruction Categoriiing ROM

The Categorizing ROM (E68 on sheet K2-5) decodes the instructions in the IR and categorizes them
into eight groups, based on their effect on the carry and overflow condition codes. These groups are as
follows:

VNN
E WK -~

Group

Instructions
MOV, BIT, BIS, BIC, and non-PDP-11 instructions
INC, DEC
CLR, TST,SWAB
ADD, ADC
NEG,CMP,COM
SUB, SBC
Rotate instructions
Unused

Three of the four outputs of the Categorizing ROM are used to provide a binary representation of one
of the above instruction categories for the C and V Decode ROM (E107 on K1-10). The fourth output
(K2-5 BYTE L) decodes the fact that the instruction in the IR is a byte instruction and is fed to the
select input of the BYTE MUX (E108 on K1-10).
4.3.2

Byte Multiplexer (BYTE MUX)

The BYTE MUX (E108 on K1-10) is a quad 2-line-to-1-line multiplexer (74S157) that determines the
N condition code bit and the K1-10 SHIFT IN 07 H signal for the B REG (Figure 4-13). A single select
input (K2-5 BYTE L) selects the A inputs when a byte operation is performed, and the B inputs when
the operation is not a byte.

“(K1-10)

f@ —— K1-10 SHIFT INOT H

K1-3 BREG #8 ()H ———{ B@
K2-5 SERIAL SHIFT H ——] AQ®
Ki-4 ALU 15

H — B1

K1-2 ALU @7 H — A

BYTE

K1-10CC N H

MUX

K1-4 SP 15 (1) H —— B2 (E108)

K1-2 SP@7 (1)H —{ A2

745157 2

—

ROM

K1-4BLEG 15 H ——{ B3
K1-2 BLEG @7H —— A3
STB

70 C + V DECODER

£f3 —
)

K2-5 BYTE L
11-3888

Figure 4-13

Byte Multiplexer

4-25

Output signal K1-10 CC N H assumes the level of K1-4 ALU 15 H when the instruction being per-

fesmibd
& Qbirherkralibn,
sis and the level of K1-2 ALU 07 H when the instruction is a byte operation.

Byteloperetimay
ofs.
be performed on either the high or low bytes of the input word, depending on
whether the processor microcode has already swapped bytes before the condition codes are detected.
For shift right operations, the K1-10 SHIFT IN 07 H output assumes the level of the K1-3 BREG 08
(1) H input when a word instruction is performed, and the level of the K2-5 SERIAL SHIFT H output
of the ROT/SHFT ROM (E62 on print K2-5) for a byte operation. The diagrams in Figure 4-14
indicate the operations performed by various instructions.
4.3.3

C and V Decode ROM
:
The C and V Decode ROM (E107 on K 1-10) determines the values of the carry and overflow condition
code bits as a function of the instruction being performed (Figure 4-15). Inputs to this ROM come

from the ROT SHIFT ROM (E62 on K2-5), the PSW [K1-1 CBIT (1) H], the BYTE MUX, and the
Categorizing ROM (E68 on K2-5). Outputs K1-10 CC V H and K1-10 CC C H are fed via the PSW
MUX (E98 on K1-1) to the PSW register.

4.3.4

Condition Code Signal CC Z H
Each 4-bit slice of the data path contains an ALU output via a gate (type 8815) reflecting whether all
four of the bits in that slice are ZERO. If the instruction being performed is a byte operation, condition
code signal K1-10 CC Z H assumes the combined state of signals K1-1 0-3=0 H and K1-2 4-7=0 H:
for a word operation, K1-10 CC Z H assumes the combined state of those signals together with K1-3

8-11=0 H and K1-4 12-15=0 H. Thus, K1-10 CC Z H is asserted if bits 00 through 07 = 0 for a byte
operation and if bits 00 through 15 = 0 for a word operation. Assertion of K2-5 BYTE L selects byte

operation.
4.4

UNIBUS ADDRESS AND DATA INTERFACE

4.4.1
Unibus Drivers and Receivers
Standard bus transceiver circuits (type 8641) are used to interface the processor data path to the
Unibus address (BUS A00:A17) and data (BUS DQ0:D15) lines. These circuits are shown on prints
K1-1 through K1-4, and on K1-6. Figure 4-16 shows the logic diagram for an 8641.
4.4.2

Unibus Address Generation Circuitry
A unique feature of the KD11-EA is that KT11-D equivalent memory management capability is built
into the 2-board processor. During Unibus transfers, virtual bus addresses are obtained from the

scratchpad memory (SPM) and the Physical Bus Address (PBA) register, if relocation is not enabled,

and latched in the Virtual Bus Address (VBA) register shown on print K1-6. Figure 4-17 shows the
actual VBA clock timing, while Figure 4-18 shows Unibus address logic in block diagram form.

If the memory management circuit is not enabled (K1-8 RELOCATE H is not asserted), the address

that was clocked into the Physical Bus Address register is used as address data for the 8641 transceivers
and driven onto the Unibus address lines.
When the memory management circuit is enabled (K1-8 RELOCATE H asserted), a selected reloca-

tion constant (detailed description in Paragraph 4.12) is added to the contents of the VBA before it is
latched into the BA and driven onto the Unibus.

4-26

ROR
RORB

WORD:

v b

o by 10|

BYTE:

ROLB

WORD:

IEI'_1 I

BYTE:

I
15

00D

‘]

EVEN

]

‘TB

ASR

ASRB

WORD:

[ti:rl PR

N R T A

N N N A S

R ] IHI
)

BYTE

l 15|

ASL

ODD ADDRESS

]44}"’IHI

| i

[

}_‘III

EVEN ADDRESS

ASLB

WORD:

e L
e
15

BYTE:

IHI'_{ T
15

ODD ADDRESS

I OIII‘—{, T
7

B R T

EVEN ADDRESS

11-3952

Figure 4-14

Rotate Instructions

4-27

+5V

K2-6 1R DECODE (1) L
K2-5 BYTE H

K2-5 IR 15 (1)
H —
K2-5 IR 14 (1)

H —

13 (1)
K2-5IR

H —

K2-51R12 (1)

H —

K2-5 IR 10 (1)

(K2-5)

K2-5 BYTE L

K2-5 CC CODE O2 H
K2-5
CATEGORIZING
ROM

{K1-10)

CC CODE O1 H

K2-5 CC CODE OOH

C+V
DECODE

— K1-10 CCV H

ROM

K2-5 IR09 (1) H —
K2-5 IR 08 (1)

FROM
BYTE MUX

H ——

—K1-10 CCCH

K2-5 IR 07 (1) H

K2-5 ROT CBIT (1) H—

K2-5 IR 06 (1) H —

E68

K1-1 CBIT (1) H—
E107

11-5187

Figure 4-15

C and V Decode ROM

UNIBUS

LINES

>
Figure 4-16

of >

Unibus Transceiver

4-28

11-3891

LOAD VBA

weutT 0 [
DELAY

TAP 120 H

proccLkL

| §

[

[
[
1

LOAD VBA

LOAD BA

[

—»{ f«30ns

LOAD

|<—180ns—>'<———240ns—b|
<«——

SHORT CYCLE

LONG CYCLE —»
1-3900

Figure 4-17

FROM PAR [ PAGE ADDRESS FIELD

Brsnio

Processor Clock Cycle Timing

K1-6
(KI°®

ADDER

K1-6

)BITSIZ-G>

BITs 17-6 M

VBA

K1-6

<18

(K1-8)
[BITS17-6_

DRIVER

BITS1S-2Xoik

rom

DATA PATH

cLR

K1-5 LOAD VBA M _ 1

K2-2 PROC INIT L ——

BIT1S—
8IT 14

—

CLK

L— aursw—@

BITS 17-6

K1-8 RELOCATE H

BITS 5-0

> ORIVER [

K1-5 LOAD BAR L

BIT 17

—

BIT ,3_[‘

UNIBUS

BIT 16
K2-1 ENAB ADDRS L
11-3892

Figure 4-18

Unibus Address Logic Block Diagram

4-29

4.4.3 Internal Address Decoder
The receiver haif of the bus transceivers continually monitors the Unibus address lines. If the processor
1s running (HALT RQST L or BUS SACK L are not asserted), these transceivers allow the Internal
Address Decoder circuit (print K1-10) to detect transfers to or from the PSW and memory management registers. Note, however, that the CPU does not allow access to its general registers through their
Unibus addresses while it is running.
While the processor is halted (BUS SACK L is asserted), this decoder circuit enables data transfers

between CPU registers and Unibus peripheral devices. A list of these CPU registers and their Unibus
addresses is shown below; the registers are discussed in Paragraph 4.12.

4.5

PSW

777776

R10

777710

777700

R11

777711

R1
R2
R3
R4
R5
R6
R7

777701
777702
777703
777704
777705
777706
777707

R12
R13
R14
R15
R16
R17

777712
777713
777714
177715
777716
177717

INSTRUCTION DECODING

4.5.1

General Description

Two methods are used to control instruction decoding, one using microroutine selection and the other
using auxiliary ALU control. Dual control is required because of the large number of instructions that
require source/destination calculations. Auxiliary ALU control is evoked whenever the microcode
executes the action X = Y OP B as a result of a specific instruction.
There are two prerequisites to a thorough understanding of the instruction decoding procedure. One is
a knowledge of the microbranching process, and the other is a knowledge of the PDP-11 instruction
format.
|
The following facts pertain to the KD11-EA /PDP-11 instruction set:

In general, the PDP-11 operation code is variable from 4 to 16 bits.

A number of instructions require two address calculations; an even larger number require
only one address calculation. There are also a number of instructions that require address
calculations, but do not operate on data.

All op codes that are not implemented in the KD11-EA processor must be trapped.

There are illegal combinations of instructions and address modes that must be trapped.

There exists a list of exceptions in the execution of instructions having to do with both the
treatment of data and the setting of condition codes in the processor status word.

4-30

4.5.2

Instruction Register

Each PDP-11 instruction obtained from memory is stored in the 16-bit instruction register (IR). This

type flip-flop (E34). The purpose of the IR is to store the instruction for the complete instruction cycle
so that the IR Decode and Auxiliary ALU Control circuits can decode the correct control signals

throughout the instruction cycle.

The IR latches data from the SSMUX 00-15 lines on K2-7 LOAD IR L and the leading edge of K1-5
PROC CLK L.

On the trailing edge of K2-9 BUT SERVICE (1) H, all the IR bits except K2-5IR15 (1) H are cleared.
[K2-5 IR 15 (1) H is set by the same signal transition.] This means that the IR Decode circuit will see a
conditional branch instruction in the IR after every service microstep. This action prevents the processor from decoding a HLT instruction after an Initialize condition.
If a bus error (BE) occurs while the Control Store output signal Enable Double Bus Error (K2-8
ENAB DBE L) is asserted, the whole IR is cleared (PDP-11 Halt), causing the processor to halt
automatically. Bus errors occurring without the K2-8 ENAB DBE L signal have no effect on the IR.
K2-8 ENAB DBE L is only asserted during certain microwords in the trap sequence to prevent the
possibility of a second bus error occuring (Double Bus Error), which would cause the trap sequence to
be re-entered before it is completed. For example, if R6 (Stack Pointer) were an odd address, the first
bus reference using the stack in the trap routine would cause another trap (Odd Address), a sequence
that could tie up the CPU indefinitely if not for the Halt and Double Bus Error facilities. In short, any
error during the four memory references of the trap sequence is fatal.
4.5.3

Instruction Decoder

4.5.3.1 Instruction Decoder Circuitry - The Instruction Decode (prints K2-5 and K2-6) and Control
Store (prints K2-7 through K2-10) circuitry could be thought of as an internal microprocessor that
interprets PDP-11 instructions and translates them into a set of microinstructions, each consisting of
40 control signals. These control signals then determine the operation of the data path and Unibus
control circuitry.
A block diagram of this internal microprocessor is shown in Figure 4-1. Note that all outputs of the
Control Store ROMs (K2-7 through K2-10) are latched in hex D-type registers (74S174s).
Nine of these latched signals (K2-7 MPC 08 H through K2-7 MPC 00 H) are fed back to the inputs of
the Control Store ROM as the next microinstruction address (and can then be called the micro-PC).
The wired-OR capability of these lines allows the IR Decode circuitry to force microbranching
addresses on certain enabling conditions. The actual microbranch address will depend on the instruction being decoded, the instruction mode used (modes 0-7), and the operand required (source or
destination).
The IR Decode circuitry is shown on prints K2-5 and K2-6. It consists of two 512 X 4 ROMs; nine 256
X 4 ROMs; two 32 X 8 ROMs; and 74S03, 74502, 74800, and 74S10 logic gates. The following
descriptions are based on instruction types. Complete block diagrams of the microcode flow are available in the KD 11-EA print set.
NOTE
The signal FP11-A ATTACHED L is input to the
IR DECODE PROM (E70 on K2-6) to prevent a
Reserved Instruction Trap from occurring for

17xxxx codes while the floating point option (FP11A) is installed.

4-31

4.5.3.2

Double-Operand Instructions - Double-operand instructions require two address calculations,
one for the source and one for the destination operand. The microbranch to the sequence of microinstructions that determine the source operand is initiated by the Control Store output signal K2-6 IR
DECODE (1) H. When this signal is enabled, the IR Decode ROMs DOP Decode (E69 and E70 on
print K2-6) check the instruction in the IR (op code bits IR15-12). If the instruction is a doubleoperand type, the ROM outputs are asserted as follows:
ROM Outputs

Type

Instruction

MOV (SM0*DMO)

K2-6

K2-7

KK2-7

K2-7

IR Code 00OL

MPCO7L

MPCO6L

MPCOSL

MPCO4L

MPCO3L

DOP (MOV+SUB)

MOD (SM0*DMO)
(ADD, BIC, BIS)

SUB (SM0*DMO0)

DOP (SM0*DMO0)

Illegal Instructions

DOP NONMOD (SM0*DMO0) |

(CMP, BIT)

NOTE
Ground on the MPC lines represents a logic ““1.”

Coupled with the microprocessor outputs of the DOP DEC ROM are the outputs of a set of type
74503 gates on K2-6. These gates, when enabled, place the contents of the source mode field (IR 11:09)
of the PDP-11 instruction being decoded onto the MPC 00:02 lines. These gates are enabled by the K26 SRCH ROM output only when the instruction being decoded is of the double-operand type, the K26 IR DECODE (1) L signal is asserted, and the instruction is not reserved (K2-6 IR CODE 00 L
unasserted).
A summary of the various source microaddresses is shown below:

Instruction

Source
Mode

Microbranch Address

Octal

DOP (SM0*DMO0)

110

1
2
3
4
5
6
7

111
112

113
114
115
116

Reserved DOP

NOTE
A ground on the MPC lines represents a logic 1.

4-32

The DOP DEC ROMs described above are also used to decode the microprocessor address for the
various Control Store destination operand routines. When the K2-7 BUT DEST L input is asserted by
the miscellaneous control field circuitry of the Control Store, the DOP DEC ROMs decode the
instructions, determine whether it is a modifying or nonmodifying instruction, and generate the following micro-PC addresses.

ROM Outputs

Type

K2-7

K2.7

K2-7

MPCO7L

MPCO6L

MPCOSL

MPCO4L

MPCO3IL

Moyve

| 0

Modify

Nonmodify

Instruction

(SM0*DMO0)

(ADD BIS BIC but
not MOV or SUB)

(CMP BIT)

SUB

The circuitry used to decode the destination mode field of the instruction being decoded is similar to
that described above for microaddressing the source operand routine. A set of 74S03 gates on K2-6 is
used to place the contents of K2-5 IR 05 (1) H through K2-5 IR 03 (1) H on the lines when enabled.
For double-operand instructions, enabling occurs when the MPC miscellaneous control field asserts
K2-7 BUT DEST L.

ROM E74 on print K2-6 is also considered to be part of the DOP Decoder circuitry. This ROM
decodes all Extended Instruction Set (EIS) instructions, generating the following micro-PC addresses
when K2-6 IR DECODE (1) H is asserted:

Type
Instruction

Multiply or Divide

ROM Outputs
K2-7
K2-7

K2-6

K2-7

K27

K2-7

IR Code OOL

MPCO7TL.

MPCO6L

MPCOSL

MPCO4L

MPCO3L

(MUL, DIV)
Arithmetic Shift or

'
|

SOP

XOR

Reserved

Arithmetic Shift Combined
(ASH,ASHC)

4-33

The K2-6 DEST L output of the EIS Decoder ROM (E74) allows the 74S03 (E65) on print K2-6 to
place the contents of the destination mode field of the instruction being decoded onto the micro-PC
(MPC0O0-MPCO02) lines. This microbranching technique is similar to that described above for micro-

addressing the source operand routine. Use of the EIS instructions does not degrade processor timing
or affect NPR latency.

4.5.3.3 Single-Operand Instructions - Unlike double-operand instructions, single-operand instructions only require one address calculation to obtain the necessary operand. Complete SOP instruction
decoding is done with the two 256- X 4-bit ROMs (E59 and E60).

The SOP Microbranch ROM (E60) monitors the necessary IR input lines and asserts the correct
micro-PC address on lines K2-7 MPCO03-L through K2-7 MPC 06 L when the K2-6 IR DECODE (1) L
signal is asserted and the SOP enable signal K2-5 IR 12-14=0 H is true. The K2-6 DEST L output is
also activated when an SOP instruction is decoded. This signal enables the destination mode mon-

itoring circuitry described in the double-operand instruction decoding section. Microaddresses for
SOP instructions are shown below.
Base
Microbranch

Instruction

Address

SOP Modify
(CLR,COM,INC,DEC)

040

SOP Non-Modify
(TST)

160

NEG

150

Rotate and Shift
JSR
‘
-~ JMP
-

170
150
020

MARK

SWAB

030

MFPI (D)
MTPI (D)

100
250

"MFPS
MTPS

130
120

The SOP Microbranch ROM (E60) is also used to decode JSR instructions. This decoding is performed in the same manner as that for SOP instructions. The K2-6 DMO H input to the ROM is used
to detect the illegal instruction JMP or JSR destination mode 0. When this occurs, no micro-PC
address is allowed on the ROM outputs.

4-34

The SOP Decode ROM (ES9) monitors the same input signals as the SOP Microbranch ROM. Its
purpose, however, is to decode illegal, reserved, and trap instructions. The three output signals K2-6
IR CODE 00 L through K2-6 IR CODE 02 L are enabled as follows:

Instructions

Reserved

IR Code
01

Illegal

(JMP or JSR Mode 0)
EMT
Trap

0
0

1
0

0
1

The fourth output signal of the SOP Decdoe ROM enables the destination mode monitoring circuitry
described in the double-operand instruction decoding section.
4.5.3.4 Branch Instructions - Conditional branch instructions are completely decoded by the Branch
DEC ROM (E72 on print K2-6). This ROM is enabled when bits IR11:IR
14 are all low and the K2-6
IR DECODE (1) L signal is active. The input lines monitored are the four condition code bits (N, Z, V,
and C) and four IR bits (IR15, 10, 9, and 8). When a branch is decoded, the K2-7 MPC 07 L output

signal is enabled. The branch instruction microcode routine in the Control Store will sign-extend the
branch offset and shift it left one place.
4.5.3.5 Operate Instructions - There are three 256- X 4-bit ROMs in the instruction-decoding circuitry for decoding PDP-11 operate instructions. These ROMs are the Reset/Trap Decode, Trap Decode,

and Op Branch ROMs (E63), all found on K2-6.
The Op Branch ROM (E63) monitors IR output lines IR00:IR07. It is enabled when IR08 and IR 15
are low and K2-6 IR DECODE (1) L is active. The PDP-11 operate instructions are decoded into the
following micro-PC addresses on the ROM outputs K2-7 MPC 00 L through K2-7 MPC 03 L.

Instruction

Microbranch
Address

Reset
RTI/RTT
Set Condition Codes
Clear Condition Codes
RTS

003
011
007
006
004

Wait

014

The Reset/Trap Decode ROM (E54) decodes Reset, RTT, and RTI instructions and activates the

outputs K2-6 START RESET H and K2-6 ENAB TBIT H accordingly. This ROM also allows the
lower PSW bits (K2-6 DISABLE LOAD PSW H) to be loaded only from the stack when the processor

is operating in User mode (memory management restriction). It also treats a Reset instruction as a
NOP in User mode.

4-35

The TRAP DEC ROM (ES3) has the same inputs as the Op Branch ROM. Its purpose is to decode
Halt, reserved, trap, and illegal instructions, and to enable the outputs accordingly. The K2-3 USER
MODE H input also allows this ROM to treat Halt instructions as reserved instructions when operating in the memory management User mode.
IR Code

Instruction

Reserved

Illegal
BPT

10T
HALT

‘

1
1

0
0

1
0

0
|
1
Enable HLT RQSTL

4.6 AUXILIARY ALU CONTROL
The AUX Control circuitry on the KD11-EA consists of three bipolar ROMs, shown on K2-5.
ROM

Name

32- X B-bit

DOP (E83)

256- X 4-bit
256- X 4-bit

SOP (E62)
ROT/SHIFT (E62)

These ROMs determine the ALU operation to be performed whenever the microcode executes the
action X « Y OP B, where Y designates a scratchpad register and X designates either the B REG or a
scratchpad register.
The AUX DOP ROM (E83) decodes double-operand instructions, and is enabled by K2-8 AUX
SETUP H. The following table expresses the outputs of this ROM as a function of the instruction
being performed. (B represents the B register, A represents any scratchpad register, and F represents

the ALU output.)
ROM Outputs
Func Code
Func Code

ALU

Func Code

Instruction

Operation

03H

02H

01H

Func Code

00H

MOV (B)

FeA

]

COMP (B)

F < A minus B

]

ADD

F « A plus B

SUB
BIT (B)
BIC (B)

F « A minus B
F—AB
F—AB

0
1
1

|
0
0

0
0
1

0
]
0

BIS (B)

F—~A+B

XOR

F-A(® B

4-36

The AUX SOPP ROM (E61) decodes single-operand instructions, and is enablec'i by K2:8 AUX SETUP
H. The following table expresses the ROM outputs as a function of the SOP instruction decoded.

Instruction
SWAB
CLR (B)
COM (B)
INC (B)
DEC (B)
NEG (B)

ADC (B)

ALU

Function
F<A
F «ZERO
F<A
F <A plusl
F « A minus 1
F « A minus B
F<A

plus CBIT (0)

F < A plus

SBC (B)

CBIT (1)
F<A
minus CBIT (0)

ROM Outputs

Func Code

0
0
0
0
0
0

1
0
0
0
0
1

0
0
0
1
1
0

1
0
1
0
|
0

02H

03H

01H

00H

F « A minus
CBIT (1)

TST (B)
ROR (B)

F<A
F~B

0
0

1
1

0
1

ROL (B)
ASR (B)
ASL (B)
MARK
MFPI

F<B
F<B
F
B
N/A
F«A
F<A
F « NBIT (0)
F «NBIT (1)
F~A
F<A
F~A
FeA

0
0
0
0
0

1
1
1
0
1
1
0
1
1
1
1
1

|
1
1
0
0
0
0
1
0
0
0
0

1
0
0
0
0
0
1

MTPI
SXT

MTPS
MFPD
MTPD
MFPS

0
0
0
0
0
0
0

1
0
0
1
1
1
1

Auxiliary control signals are also necessary for performing rotate and shift operations. The
ROT/SHFT ROM (E62) on K2-5 decodes these instructions and outputs those control signals
required to shift the contents of the B REG. Inputs K1-1 BREG 00 (1) H, K1-10 CC N H, and K1-1
CBIT (1) H also determine the K2-5 SERIAL SHIFT H and K2-5 ROT CBIT (1) H signals. The
SERIAL SHIFT H signal is sent to the BYTE MUX (E108 on K1-10), where it is used in determining
the K1-10 SHIiFT IN 07 H signal used in the B REG shifting operation. K2-5 ROT CBIT (1) H is used
in the calculation of the new carry condition (C and V Bit ROM - E107 on K1-10). Note that for all
rotate and shift operations, the AUX SETUP is performed on the B « B step before each X « Y OP B
step previously mentioned. This is done to allow the condition codes to be set up without slowing the
processor.

Table 4-9 summarizes the auxiliary control instructions.

4-37

Table 4-9

Auxiliary Control for Binary and Unary Instructions
Condition Codes

ALU

Instruction

Nand Z

Function

CIN

MOV(B)

Load

Cleared

Not affected

A Logical

CMP(B)

Load

Load like Subtract.

A minus B

BIT(B)

Load

Cleared

Not affected

A e B Logical

BIC(B)

Load

Cleared

Not affected

AeB Logical

BIS(B)

Load

Cleared

Not affected

A < B Logical

ADD

Load

Set if operands are same

Set if carry out.

A plus B

Set if carry.

A minus B

sign and result different.

SUB

Load

Set if there was arithmetic
overflow as a result of the

operation (i.e., if operands
were of opposite signs and
the sign of the source was
the same as the sign of the

result; cleared otherwise.

XOR

Load

Cleared

Not affected

A*B

CLR(B)

Load

Cleared (like Add)

Clear

COM(B)

Load

Cleared

Set

INC(B)

Load

Set if destination held

Not affected

A plus 1

100000 before operand.
DEC

Load

Set if result is 100000.

Not affected

A minus 1

NEG(B)

Load

Set if result is 100000.

Cleared if result is O;

A minus B

A plus CBIT

A minus CBIT

set otherwise.

ADC(B)

SBC(B)

Load

Set if destination was

077777 and C =1,

177777 and C = 1.

Set if destination was

100000.

Oand C = 1; cleared
otherwise.

4-38

Table 4-9

Auxiliary Control for Binary and Unary Instructions (Cont)
Condition Codes

Nand Z

TST(B)

Load

Cleared

A Logical

Z«1

Unaffected

(0)

B Logical

Unaffected

(15)

B Logical

0« (15

B Logical

C < (15

B Logical

ROR(B)

ALU

Instruction

Function

CIN

[f(15:01)*C=0
N<C

ROL(B)

Z«1
If(14:00)*C=0
N«(14)

ASR(B)

Z<1

B(7)

Unaffected

If(15:01)=0
N<N

ASL(B)

Z<1
1f(14:01)=0
N<(14)

SWAB
SXT

Load

Cleared

A Logical

Z—Load

Cleared

N—Unaffected

MFPI

Load

Cleared

Unaffected

A Logical

MTPI

Load

Cleared

Unaffected

A Logical

Z—Set

Cleared

Unaffected

A Logical

MTPS

If SRC(7)=0
N—Set

If SRC(7)=1
MFPD

Load

Cleared

Unaffected

A Logical

MTPD

Load

Cleared

Unaffected

A Logical

Z—Set

Cleared

Unaffected

A Logical

MFPS

If PS(7)=0
N—Set

If PS(7)=1

4-39

4.7

DATA TRANSFER CIRCUITRY

4.7.1

General Description

All Unibus data transfers are controlled by the DAT TRAN circuitry on K2-1. This logic monitors the
busy status of the Unibus, controls the processor bus control lines BBSY, MSYN, C1, and C0, and

detects parity errors (PEs), and bus errors (BEs).
4.7.2

Control Circuitry

4.7.2.1
Processor Clock Inhibit - All processor data transfers are initiated by K2-8 BUF DAT TRAN
(1) H. When K 1-5 TAP 30 H goes high, the signal combines with K2-1 ABORT RESTART L (normally a logic 1) to enable K2-1 TRAN INH I, shutting off the processor clock until the transfer is

completed. The following conditions must also exist to allow the processor clock to be shut off:
a.

K2-1 MSYN (1) H high AND K2-1 SSYN H low.
K2-1 CACHE HIT H low OR K2-1 CLK MSYN H

low.

The signal CACHE HIT L is generated if the cache memory option is being implemented and the
cache has determined that it has the data being requested. Ten bus address lines are brought to the J1

connector on the M8265 module. When K2-1 START TRAN L is asserted during a DATI cycle, the
cache uses the BA lines to determine if it has the data. If the data is in cache, then CACHE HIT L and
TRI STATE AMUX L are asserted. These signals cause the processor to abort the Unibus transfer
and to receive data via the external data path. The external signal CACHE HIT L will cause K2-1
CACHE HIT H to be asserted. This signal will restart the processor clock when K2-1 CLK MSYN H
goes true (approximately 150 ns after K2-1 START TRAN L).

4.7.2.2

Unibus Synchronization - The synchronizer logic shown in Figure 4-19 (from K2-1) arbitrates

whether the processor or some other Unibus peripheral will control the Unibus. A logic 1 level (+3 V)

at the set input of the E31 flip-flop on K2-1 specifies that the bus is presently in use. Each of the inputs
that combine to create this level monitors a specific set of bus conditions.

(2-1 DATIP (1) L
<2-1 DATIP
(O) L
K2-1

BBSY H

7402 \10

K2-2 NPR H

Eon

)

K2-1

BUS IN

USE H

K2-2 NPG (1) H
K2-2 NO SACK L
q

18
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K2—1 GET BUS H

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TRANSFER

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11-6189

Figure 4-19

Unibus Synchronizer

4-40

(K2-2 NPR H)

A Unibus peripheral has asserted a nonprocessor request
(NPR) and wishes to gain control of the bus immediately.

BBSY
(K2-1 BBSY H)

is asserting a bus busy (BBSY) signal.

NPR

Another Unibus peripheral already has control 'of the bus, and

NPG

[K2-2 NPG (1) H]

An NPR device has requested control of the Unibus and the
KDI11-E processor has issued a nonprocessor request grant
(NPG). The condition may exist where the NPR device has
already recognized the NPG and has dropped its NPR signal,
while not yet having asserted a SACK or BBSY.

NO SACK L
(K2-2 NO SACK)

A device has requested control of the Unibus. The KD 11-E processor has issued a grant, and the device has returned SACK L,
causing NO SACK L to go high. The condition may exist where
only SACK L remains on the Unibus for a period of time before
the peripheral asserts BBSY.

DATIP (0) L
[K2-1 DATIP (0) 1]

When this input is true, all of the above signals are overridden.
It indicates that the processor is performing a DATIP
(Read /Modify/Write) operation, and has control of the Unibus
(BBSY asserted). NPR devices may, however, be granted bus
control, but must wait until the processor releases BBSY before
asserting theirs. (DATIP operations dictate worst-case bus
latencies for NPR devices.)

BUS SSYN L

A data transfer is still being completed; therefore, the processor
must wait before initiating another.

If none of the above Bus-in-Use conditions exist, the E31 flip-flop on K2-1 can be set when K2-1 GET
BUS H is asserted. K2-1 GET BUS H is asserted by K2-8 BUF DAT TRAN (1) H and remains
asserted until K2-1 GET BUS H goes low followed by the assertion of TAP 30 H. Setting E31 starts

the transfer.
4.7.2.3 Bus Control - Once the E31 flip-flop is set, the DAT TRAN circuitry begins a Unibus data
transfer operation by asserting K2-1 ENAB ADDRS L, triggering the following actions:

Enables the bus address drivers (BUS A15:A00 on K1-6).

Enables the BBSY driver (K2-1).

Enables the bus control signals BUS C0 and BUS C1, which determine the kind of transfer

being performed.

Cl1

0
0
1

0
1
0

Operation

DATOB

The actual condition of these control lines is determined by K2-8 BUF CO (1) H and K2-8
BUF C1 (1) H.

Enables the bus data drivers (BUS D00-BUS D15) if the operation being performed is a
DATO.

4-41

4.7.2.4 NO-SACK Timeout Circuitry - The circuit shown in Figure 4-20 (from K2-10) asserts BUS
SACK L on the Unibus if a device requesting Unibus control does not assert SACK within 22 us after
a grant line has been enabled
The grant signals (K2-2 BG L and K2-2 NPG L) are ORed at E35. The output of E35 provides one

enabling signal to a NAND gate (E8) and triggers a monostable multivibrator (E14). The outputs of
E35and E14 are ANDed at E8 to produce BUS SACK L. The monostable effectively delays (by 22 us)

the assertion of BUS SACK L since it produces a 22 us pulse that prevents E8 from being enabled.
BUS SACK L, when asserted, will cause the processor to drop the grant line, which will, in turn, cause
this circuit to drop BUS SACK L.
This circuit prevents the processor from being hung if a grant line is asserted and BUS SACK is not
returned by the device requesting bus control. If the requesting device returns BUS SACK, this circuit
will not assert BUS SACK since the grant line will be dropped before the monostable times out. K2-2
HALT PEND L and K2-2 BG (1) H are ANDed on E35 to prevent
timed out.

a HALT GRANT from being

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T
Figure 4-20

470PF

NO-SACK Timeout Circuitry

4-42

11-5186

4.7.2.5 MSYN/SSYN Time-Out Circuitry - Unibus specifications require that the BUS MSYN L
control signal be enabled no sooner than 150 ns after the bus address, data, and control lines have been
asserted. To meet this requirement, the circuitry in Figure 4-21 has been incorporated into the DAT
TRAN logic (K2-1).

The multiplexer (E10) shown in Figure 4-22 helps adapt the DAT TRAN circuitry to the type of bus
operation being performed (DATI or DATO). Specific functions performed are as follows:
1.

Generates the correct Unibus control signals [K2-1 UBUS CO (1) H and K2-1 UBUS C1 (1)

Inhibits the detection of parity errors during DATO operations.

H].

Generates an End of Transfer (EOT L) signal as soon as BUS SSYN is returned by an

addressed peripheral.

Delays the assertion of BUS MSYN, using the clock signal K1-5 ALLOW MSYN H, which
does not become asserted until the Physical Bus Address register has been loaded.
,
NOTE
,
This applies only to DATI or DATIP. During
DATO or DATOB, the bus address is never loaded
in the same microcycle that does the DATO or
DATOB.

The RC circuit shown in Figure 4-21 prevents the MSYN flip-flop (E31) from being clocked until
approximately 150 ns after the bus address and control lines are placed on the bus. Once this latch is
set, BUS MSYN L is activated and the SSYN TIMEOUT one-shot E16 is triggered. When SSYN is
returned by the addressed peripheral, both the MSYN flip-flop (E31) and the SSYN TIMEOUT oneshot are cleared. The processor clock is then freed by the release of K2-1 TRAN INHL. If a DATI or
DATIP operation is being performed, that will be clocked into either the scratchpad, B REG, PSW, or
IR on the next low-to-high transition of K1-5 PROC CLK L.

If a DATO or DATOB operation is being performed, the data bus drivers are disabled after SSYN is
returned from the addressed peripheral but before the MSYN line is unasserted.

4-43

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11.56191

Figure 4-22

Data Transfer Multiplexer

4-45

4.7.2.6 Bus Errors — Once the SSYN TIMEOUT one-shot is triggered, SSYN must be returned
within 22 us. If SSYN is not returned in this time, E16 times out, setting the TIMEOUT flip-flop
(E32). The output of this latch then generates the signal K2-1 ABORT RESTART L and pulse K2-1
ABORT H. K2-1 ABORT RESTART L reenables the PROC CLK and K2-1 ABORT H sets the Bus
Error flip-flop (E33). This same pulse that sets the Bus Error flip-flop also clears the micro-PC address
latches (MPCO00 through MPCO008) on K2-7, forcing the processor to enter the service microroutine on
the next PROC CLK L low-to-high transition.
4.7.2.7 Parity Errors - If a data transfer is being performed with a parity memory (e.g., MS11-JP or
MMI11-DP), all parity errors detected by the memory will be reflected back to the KD11-E on the
Unibus lines BUS PA L and BUS PB L on K2-1 (Figure 4-23).
ControlError
PA
PB

0
0
|
1

0
1
0
1

Description
No Parity Error
Parity Error on DATI
Reserved for future use
Reserved for future use

Errors detected while performing a DATIP or DATI [K2-8 BUF C1 (1) H unasserted] will result in the
Parity Error flip-flop (E34) being set when SSYN is returned to the processor. Processor operations
resulting from Parity Error will be discussed further in Paragraph 4.11, Service Traps.
4.7.2.8

End of Transfer Circuitry - To synchronize the DAT TRAN logic with the main KD11-E

processor clock, the End of Transfer (EOT) circuitry (Figure 4-24) has been incorporated into the CPU
(K2-1). During a DATI or DATIP, an EOT L signal is generated approximately 100 ns after SSYN is
returned to the processor. That EOT L removes the processor clock disabling signal (Paragraph
4.7.2.1), K2-1 TRANINH L. During a DATO or DATOB, K2-1 TRAN INH L is unasserted immediately when SSYN is returned.
4.7.2.9 Data-in-Pause Transfer - Another circuit included in the DAT TRAN logic detects Data-inPause (DATIP) transfers and controls the bus control signal BBSY. When a DATIP
(Read/M odify/Write) bus operation is initiated, the flip-flop (E32) is latched, forcing the processor to
hold BBSY L until the DATO portion of the routine has been completed. While BBSY is asserted, no

other Unibus peripheral can seize control of the bus. This feature often determines the maximum bus
latency for NPR devices (K2-1).

4.7.2.10 Odd Address Detection — The circuitry shown in Figure 4-25 is incorporated in the KD11-E
to detect odd address errors. ROM ES80 (print K2-8) monitors the signals K2-8 BUF DAT TRAN (1)
H, K2-5BYTE H, and K1-6 VBAOO (1) H, and asserts K2-8 DISABLE MSYN L when an odd address
is detected. The multiplexer circuit (E39 on K2-4) forces the processor to always autoincrement or
autodecrement the PC (R7) or the SP (R6) scratchpad registers by two, regardless of the type of
instruction being performed. This is done by preventing the K2-4 DISABLE MSYN +1 L signal from
being asserted.

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11-5194

Figure 4-25

0Odd Address Detection

4-48

4.8 POWER FAIL/AUTO RESTART
The KD11-EA power fail/auto restart circuitry (K2-3) serves the following purposes:

Initializes the microprogram, the Unibus control, and the Unibus to a known state immediately after power is applied to the computer.

Notifies the »microprogram of an impending power failure.

Prevents the processor from responding to an impending power failure for 2 ms after initial
startup.

The actual power fail/auto restart sequences are microprogram routines. The operation of the power
fail/auto restart circuitry depends on the proper sequencing of two bus signals: AC LO and DC LO.
Because of the electrical properties of the Unibus drivers and receivers, the entire computer system
must be powered up for the machine to operate. Therefore, the processor is notified of a power fail in
peripherals, as well as in its own ac source.
The notification of power status of any PDP-11 system component is transmitted from each device by
the signals BUS ACLO L and BUS DCLO L (K2-3). The power-up sequence (Figure 4-26) shows that
BUS DC LO L is unasserted before BUS AC LO L is unasserted. When BUS DC LO L is not asserted,
it is assumed that the power in every component of the system is sufficient to operate. When BUS AC
LO L is not asserted, there is sufficient stored energy in the regulator capacitors of the power supply to
operate the computer for 5 ms, should power be shut down immediately.
As ac power is removed, BUS AC LO L is asserted first by the power supply warning the processor of
an impending power failure. When BUS DC LO L is asserted, it must be assumed that the computer
system can no longer operate predictably. Memories manufactured by DIGITAL use BUS DCLOL
as a switched signal, turning them off even if power is still available. Time at2 (Figure 4-26) is the time
delay between the assertion of BUS ACLOL and the assertion of BUS DC LO L; this time delay must
be greater than 5 ms. This allows for power to be rapidly cycled on and off. According to PDP-11
specifications, upon system startup a minimum of 2 ms run time is guaranteed before a power fail trap
occurs, even if the line power is removed simultaneously with the beginning of the power-up sequence.
After the power fail trap occurs, a minimum of 2 ms run time is guaranteed before the system shuts

down. Given the tolerances permitted in the timing circuitry used in most equipment, at2 must be
greater than 5 ms.
When a pending power fail is sensed, a program trap occurs, causing the present contents of PC (R7)

and the PSW to be pushed onto the memory stack, as determined by the contents of R6 (Stack Pointer
register). The PSW is then loaded with the contents of location 263 and R7 with the contents of 24;.
Processing is continued with the new R7 and PSW. The user’s program must prepare for the impending power failure by storing away volatile registers and reloading location 245 and 265 with a power-up
vector. This vector points to the beginning of a restart routine.
When power is restored, the processor loads the PC (R7) with the contents of location 245 and the
PSW with the contents of location 26;. After loading these registers, the user program presumably will
prepare locations 24g and 26g for another power failure. If the HLT RQST L input is asserted by an
external switch closure, the processor powers up through locations 24s and 26z, and halts.

Schematics for the power fail, auto restart, and bus reset logic are on K2-3. One-shot E 14 generates a
150-ms processor INIT pulse as soon as BUS DC LO L is nonasserted after power is applied to the

processor. At the end of 150 ms, the PUP one-shot (E7) is fired if BUS DC LO L is not asserted and the
processor begins the PC and PSW load routine. The PUP one-shot generates a 2-ms pulse, during

which the assertion of BUS AC LO L is ignored.

4-49

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BUS AC LO and BUS DC LO Timing Diagram

The triggering of the 150-ms INIT one-shot also resets the POWER INIT flip-flop (E24). Setting this
flip-flop forces the Control Store to run the power-up routine beginning at micro-PC address 001. It is
this routine that reads locations 24; and 26g for the new PC and PSW.

After PUP has timed out, the assertion of BUS AC LO L would fire the one-shot PDWN (E7). Upon
entering the next service microcode state, K2-3 PFAIL H is latched into E19 (K2-2), causing a power
fail trap to be recognized by the microprogram on entering the next service state. Various traps are

arbitrated by the BUT service ROMs (E52 and E51 on K2-3).

If a momentary power failure occurs that causes the assertion of BUS AC LO L but does not cause the

assertion of BUS DC LO L, the processor will restart when the PDWN one-shot times out, retriggering the INIT one-shot.
When a Reset instruction is decoded by ROM E54 (on K2-6), the ROM output signal START RESET

H is clocked into the Start Reset flip-flop (ES4 on K2-2). This flip-flop output triggers a 100-ms INIT,
after which the processor continues operation.
4.9

PROCESSOR CLOCK
The processor clock circuitry for the KD11-EA is shown in Figure 4-27 and on print K1-5. A delay line
is used to generate a pulse train, to which the entire processor is synchronized. Because the KD 11-EA
is a fully clocked processor, events that result in the alteration of storage registers occur only on
defined edges of the processor clock.

If all clock disable inputs are unasserted, the clock will begin running as soon as +5 V is applied. The
length of an operating cycle can be either 180 ns or 240 ns, depending on the nature of the instruction
being performed. Most microinstructions employ the shorter cycle, with the longer one only necessary
when the machine is performing a DATO or DATOB, or in situations where the condition code must
be determined before an operation can be performed. Long cycles are also used in loading the Bus
Address register when memory management is turned on.

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Processor Clock Circuit

4-51

The clock is turned on and off by the gating of the feedback through the delay line. Taps of 120 ns, 90
ns, and 30 ns make it possible to vary the length of the cycle, according to a signal input [K2-8 LONG
CYCLE (1) L] from the Control Store, as the processor clock timing diagrams in Figure 4-17 show.
The indicated jumpers are inserted at W1 and W2 in the standard configuration; the overall cycle can

be slowed down slightly (approximately 30 ns) by inserting jumpers at the alternate locations (shown
on K1-5 by dotted lines) instead. It is also possible to disable the clock manually and use the manual
clock input; any TTL-compatible waveform may be employed. Multiplexer E96 issues the feedback
signal that, in effect, determines the length of the cycle.
The clock is turned off by the appropriate signal under the following conditions:

During a BUS INIT that is not caused by a RESET

During the INIT portion of the power-up routine

During the INIT portion of the power-down routine

During a Reset

During the BUT Service arbitration delay

During a priority interrupt

While BUS SACK is asserted by an interrupting device (not for NPR transfers)

During bus data transfers

After a Halt instruction is executed

10.

When the manual clock is enabled

4.10

PRIORITY ARBITRATION

4.10.1

Bus Requests
The KD11-EA responds to bus requests (BRs) in a manner similar to that of the other PDP-11 processors. Peripherals may request the use of the Unibus in order to make data transfers or to interrupt the

current processor program by asserting a signal on one of the four BR lines, numbered BR4, BRS,
BR6, and BR7 in order of increasing priority. For example, if two devices, one at priority 5 and the
other at priority 7, assert BRs simultaneously, the device at priority 7 is serviced first. Furthermore, if
the processor priority, determined by PSW bits 07:05, is at level 4, only devices requesting BRs at levels
higher than 4, such as BR7, BR6, or BRS, are serviced. Table 4-10 contains the order of priority for all
BRs and other traps.

4-52

Table 4-10

Priority Service Order

Priority

Service Order

Highest

Halt Instructions
Odd Address
Memory Management

Lowest

Error
Time-Out
Parity Error
Trap Instruction
Trace Trap
Stack Overflow
Power Fail
Halt from Console
BR7
BR6
BRS
BR4
Next Instruction Fetch

Because a BR can cause a program interrupt, it may be serviced only after completion of the current
instruction in the IR. A device that requests a program interrupt must, at the appropriate time, place a
vector address on the Unibus data lines. The processor first stacks away the current contents of PSW
and R7; then a new PSW is loaded from the contents of the vector address plus two and a new PC is
loaded with the contents of the vector address. Further discussion of how the processor handles this
BR routine is contained in the section on Service (Paragraph 4.11).
NOTE

The signal K2-2 PFAIL BR PEND H is generated
on the M8266 board and routed to connector J2 (pin
7). This signal is asserted high if the BG lines are
high or the signal K2-2 PFAIL (1) H is asserted (i.e.,

K2-2 PFAIL BR PEND H is asserted if an interrupt
must be serviced). The FP11-A (floating point
option) will use this signal to abort long instructions,
thereby maintaining the system interrupt latency
under 20 us.

4-53

Arbitration logic for BRs is contained on print K2-2 and in Figure 4-28. All BRs are received
directly
from the Unibus (Unibus receivers E17), and latched into register E19 (quad D-type
latch, 74S174)
when the microprogram enters the next service state [K2-9 BUT SERVICE (1) H is true].
The BR
Priority Arbitration ROM (E29) then determines whether the present processor priority [PSW
(7:4)] is
higher than the highest BR received and, if not, which BR received has the highest priority. Arbitration
performed by E29 in the order of priority are shown below.
HLT RQST
PSW7

BR7
PSW6
BR6
PSWS5
BRS
PSW4
BR4

K2-2

RESET

(1) H

K2-2 ALLOW

8 k2-2 86 INH L

K2-2 SACK RET (1) H

K2-2 BUT SERVICE L

K2-2 NOSACK H

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K2-2 PROS INIT H

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11-5195

Figure 4-28

Priority Arbitration Synchronizer

4-54

If the highest BR received is of a higher priority level than the processor, the corresponding grant
enable ROM output is asserted low (Figure 4-29). With no HLT RQST or trap instruction pending,
the processor clock will be disabled by the K2-2 BG INH L signal. The actual bus grant is not transferred to the Unibus until the Enable BG flip-flop (E12) is set. Grants (both BG and NPQG) are
controlled by the synchronizer logic shown in Figure 4-28 and on print K2-2.
This circuitry arbitrates whether a bus grant (BG) or a nonprocessor grant (NPG) will result, depending on which flip-flop input line (set or reset) was deactivated first. The set input K2-2 BUT SERVICE
L will cause the flip-flop to issue the BG ENAB H signal after a delay of 175 ns. Once the flip-flop is
set, the bus grant arbitrated by the BR Priority Arbitration ROM (E29) is channeled onto the Unibus
(bus driver E77). When the requesting peripheral receives BG, it returns BUS SACK L.

Upon receiving BUS SACK L, the processor clears its Enable BG flip-flop, removing the bus grant
from the Unibus, and sets the SACK RET flip-flop to keep the processor clock disabled. Removal of
bus grant causes the peripheral to drop its BUS SACK L (provided that BBSY is unasserted), assert
BUS INTR L and BBSYL, and enable a vector address onto the Unibus data lines. The processor then
deskews the removal of SACK, clears the SACK RET flip-flop (E5), and enables the processor clock
again. Once in operation, the processor clocks the peripheral vector address into the B REG, returns
BUS SSYN L, and begins running the microcode trap routine that branches the processor to the
interrupt handling program determined by the vector obtained.
4.10.2 Nonprocessor Requests (NPRs)
NPRs are a facility of the Unibus that permit devices on the Unibus to communicate with each other
with minimal participation of the processor. The function of the processor in servicing an NPR is to
yield control of the bus in a manner that does not disturb the execution of an instruction by the
processor. For example, the processor will not relinquish the bus following the DATI portion of a
DATIP transfer.
When the reset input of E5 (K2-2 NPR H) becomes unasserted before the set input, and BUS SACK L
is not true, the flip-flop issues K2-2 NPG ENAB H, enabling the BUS NPG H Unibus line and
granting the bus to the DMA device. The requesting device then returns BUS SACK L, clearing the
NPG, and waits until the bus is free (no BBSY).
4.10.3
Halt Grant Requests
The KDI11-EA implements what is, in effect, another priority level by monitoring the
HALT/CONTINUE switch on the front panel. When a Halt is detected (HLT RQST L asserted), the
processor recognizes it as an interrupt request (refer to priority levels in Paragraph 4.10.1) upon entering the next service microstate. The processor then inhibits the processor clock and returns a recogni-

tion signal (K2-2 HLT GRANT H), causing the console to drop HLT RQST L and assert BUS SACK
L, gaining complete control of the Unibus and the KD11-EA.
The user can maintain the processor in this inactive state (Halted) indefinitely. When the HALT switch
is released, the user’s console releases BUS SACK L, and the processor continues operation as if
nothing had happened.

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SERVICE TRAPS

4.11
4.11.1

General Description

All interrupts, error traps, and instruction traps are recognized and serviced by the KD11-EA when
the processor enters what is called the service microinstruction state. The functions performed during
this state are most critical to the operation of the processor.

When the service state is entered, all bus interrupts, error traps, and instruction traps realized during
the performance of the last instruction are arbitrated by the service ROMs (E51 and E52 on print K23). Each trap condition is then serviced according to its priority, as listed in Table 4-10.

4.11.2

Circuit Operation

The service ROMs (ES1 and E52 on print K2-3) service a specific trap by generating a vector address
unique to that trap condition (Table 4-11). Upon leaving the service state, the processor is forced to
push its present program counter (PC) and processor status word (PSW) onto its memory stack and
fetch a new PC from the location specified by the vector address. A new PSW is then obtained from the
next memory location after the vector. The end result of these operations is that the processor is now
performing a software subroutine written by the user that could correct or indicate the occurrence of a

specific error.

The various trap conditions that cause the processor to vector are as follows:
Bus Errors

A bus error indicates that the processor has attempted to access

nonexistent memory or odd address (non-byte), or a memory
location that did not return BUS SSYN within 22 us. The detec-

tion circuitry for bus errors is described in Paragraph 4.7.2.6 of

this manual.

Stack Overflow Error

Any attempt by the processor to decrement the contents of the
Stack Pointer register (R6) below the 400-location stack limit
(K1-10 8-15 = 0 H will result in the Stack Overflow flip-flop
(E24 on K 2-3) being set on the next transition of K1-5 PROC
CLK L. [Note that this does not apply to user stack (R16).]

Parity Error

| iParity error detection circuitry is described in Paragraph

Power Failure

The pdwer failure circnitry is described in Paragraph 4.8.

Trace Trap

' This trap is program-controlled by'the user, allowing him to

- 4.7.2.7.

insert a processor/user interactive subroutine into his main program. The circuitry is described in Paragraph 4.2.6.

Reserved Instructions

Signals IR CODE 00 L-IR CODE 02 L are generated by the IR

Illegal Instructions
EMT Instructions
Trap Instructions

Decode ROMs on K2-6 for these conditions. Their decoding is
discussed in Paragraph 4.5.3.

Upon entering the service microinstruction state, the service ROMzs (E51 and ES2 K2-3) monitor any
combination of the above trap conditions which, if true, cause the assertion of microprocessor address
line K2-7 MPC 00 L. While still in the service state, the ROM also generates a specific vector address
(Table 4-11), using outputs K2-3 C2 H, K2-3 C3 H, and K2-3 C4 H, and channels it onto the processor

AMUX lines to the SSMUX by activating K1-10 AMUX SO H.

4-57

Table 4-11

Vector Addresses

Octal Unibus
Vector Address

004

Trap Conditions

Time-Out, Odd Address, and Stack Overflow Errors

010
014
020
024
030
034
114
250

Illegal and Reserved Instructions
T-Bit Trap (BPT)
Input/Output Trap (I0T)
Power Fail
Emulator Trap (EMT)
Trap Instruction
Memory Parity Errors

Memory Management Errors

Before leaving the service state, the service ROMs also clear the condition that caused the original
trap. This is done either by asserting K2-3 STOV SERV H or K2-3 PFAIL SERV H, or by performing

the steps in the trap service routine. For those traps specified by the IR Code lines, however, it is
necessary to remove the instruction in the IR. This is done through microcode output K2-9 BUT

SERVICE (1) H, which ORs with K2-2 PROC INIT H to generate K2-3 SERV IR H and, hence, K2-3
SERV IR (1) L, removing the trap instruction from the IR. This prevents the processor from looping
on the same trap condition.
For bus requests (BRs), the BUS INTR L control signal is allowed to force K2-7 MPC 00 L during
service, provided that there are no other traps of higher priority. By enabling this line, the processor
will branch to the trap routine. Higher priority BR interrupts are prevented from receiving BG by K2-

9 BUT SERVICE (1) H.
NOTE

The signal SERVICE BR PFAIL (enabled by the
FP11-A floating point option) is input to the service
ROM (ES2) from the J2 connector on the M8266
board. When this signal is asserted, the processor
will only service Bus Request or Power Fail inter-

rupts during the service state. SERVICE BR PFAIL
is asserted when servicing an interrupt after aborting

a floating point MUL, MOD, DIV, ADD, or SUB
operation.
4.12

MEMORY MANAGEMENT

4.12.1 Genefal
4.12.1.1
Introduction - This section describes the memory management unit of the KD11-EA Central
Processor. The KD11-EA provides the hardware facilities necessary for complete memory management and protection. It is designed to be a memory management facility for systems where the memory
size is greater than 28K words and for multiuser, multiprogramming systems where protection and
relocation facilities are necessary.

4-58

4.12.1.2 Programming - The memory management hardware has been optimized toward a multiprogramming environment and the processor can operate in two modes, Kernel and User. When in
Kernel mode, the program has complete control and can execute all instructions. Monitors and supervisory programs would be executed in this mode.

When in User mode, the program is prevented from executing certain instructions that could:

Cause the modification of the Kernel program.
Halt the computer.
Use memory space assigned to the Kernel or other users.
Issue a Reset.

In a multiprogramming environment, several user programs could be resident in memory at any given
time. The task of the supervisory program would be to: control the execution of the various user
programs, manage the allocation of memory and peripheral device resources, and safeguard the integrity of the system as a whole by careful control of each user program.
In a multiprogramming system, the management unit provides the means for assigning pages (relocatable memory segments) to a user program and preventing that user from making any unauthorized
access to those pages outside his assigned area. Thus, a user can effectively be prevented from accidental or willful destruction of any other user program or the system executive program.
Hardware-implemented features enable the operating system to dynamically allocate memory upon

demand while a program is being run. These features are particularly useful when running higher level
language programs, where, for example, arrays are constructed at execution time. No fixed space is
reserved for them by the compiler. Lacking dynamic memory allocation capability, the program would
have to calculate and allow sufficient memory space to accommodate the worst case. Memory management eliminates this time-consuming and wasteful procedure.
4.12.1.3 Basic Addressing - The addresses generated by all PDP-11 family central processor units
(CPUs) are 18-bit addresses. Although the PDP-11 family word length is 16 bits, the Unibus and CPU
addressing logic actually is 18 bits. Thus, while the PDP-11 word can only contain address references

up to 32K words (64K bytes) the CPU and Unibus can reference addresses up to 128K words (256K
bytes). These extra two bits of addressing logic provide the basic framework for expanding memory
references.
In addition to the word length constraint on basic memory addressing space, the uppermost 4K words
of address space are always reserved for Unibus I/O device registers. In a basic PDP-11 memory
configuration (without management), all address references to the uppermost 4K words of 16-bit

address space (160000-177777) are converted to full 18-bit references with bits 17 and 16 always set to
1. Thus, a 16-bit reference to the I/O device register at address 173224 is automatically internally
converted to a full 18-bit reference to the register at address 773224. Accordingly, the basic PDP-11
configuration can directly address up to 28K words of true memory, and 4K words of Unibus I/O
device registers.
4.12.1.4

Active Page Registers - The memory management unit uses two sets of eight 32-bit Active
Page registers (shown on print K1-7). An APR is actually a pair of 16-bit registers: a Page Address

register (PAR) and a Page Descriptor register (PDR). These registers are always used as a pair and
contain all the information needed to describe and relocate the currently active memory pages (Figure

4-30).

One s.et of APRs is used in Kernel mode, and the other in User mode. The choice of which set to be
used is determined by the current CPU mode contained in the processor status word.

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4.12.1.5

Capabilities Provided by Memory Management

Memory Size (words)

124K, max (plus 4K for 1/0O and registers)

Address Space

Virtual (16 bits)
Physical (18 bits)

Modes of Operation

Kernel and User

Stack Pointers

2 (one for each mode)

Memory Relocation
Number of Pages
Page Length

32 to 4096 words

Memory Protection

4.12.2

16 (8 for each mode)

No access
Read-only
Read/write

Relocation

4.12.2.1
Virtual Addressing - When the memory management unit is operating, the normal 16-bit
direct address is no longer interpreted as a direct physical address (BA) but as a virtual address (VBA)
containing information to be used in constructing a new 18-bit physical address. The information
contained in the VBA is combined with relocation and description information contained in the Active
Page register (APR) to yield an 18-bit BA.

4-60

Because addresses are automatically relocated, the computer may be considered to be operating in
virtual address space. This means that no matter where a program is loaded into physical memory, it
will not have to be “relinked”; it always appears to be at the same virtual location in memory.

The virtual address space is divided into eight 4K-word pages. Each page is relocated separately. This

is a useful feature in multiprogrammed timesharing systems. It permits a new large program to be
loaded into discontinuous blocks of physical memory.

A page may be as small as 32 words, so that short procedures or data areas need occupy only as much
memory as required. This is a useful feature in real-time control systems that contain many separate
small tasks. It is also a useful feature for stack and buffer control.
A basic function is to perform memory relocation and provide extended memory addressing capability
for systems with more than 28K of physical memory. Two sets of Page Address registers are used to

relocate virtual addresses to physical addresses in memory, These sets are used as hardware relocation
registers that permit several users’ programs, each starting at virtual address 0, to reside simultaneously in physical memory.

4.12.2.2 Program Relocation - The Page Address registers are used to determine the starting address

of each relocated program memory. Figure 4-31 shows a simplified example of the relocation concept
as implemented by the circuitry on print K1-6.

CPU

MEM

MGMT

RELOCATION

R aEes

CONSTANT
A = 6400

(VBA)

B = 100000

PHYSICAL MEMORY

L
PROGRAM

100000

PHYSICAL ADDRESS(BA)

PROGRAM A
006400

000000
n-3906

Figure 4-31

Simplified Memory Relocation Exémple

4-61

Program A, starting address 0, is relocated by a constant to provide physical address 6400;. If the next
processor virtual address is 2, the relocation constant will then cause physical address 64025, which is

the second item of Program A, to be accessed. When Program B is running, the relocation constant is
changed to 100000s. Then, Program B virtual addresses, starting at 0, are relocated to access physical

addresses starting at 100000s. Using the Active Page Address registers to provide relocation eliminates
the need to “relink” a program each time it is loaded into a different physical memory location. The
program always appears to start at the same address.
A program is relocated in pages consisting of from 1 to 128 blocks. Each block is 32 words in length.
Thus, the maximum length of a page is 4096 (128 X 32) words. Using all of the eight available Active
Page registers in a set, a maximum program length of 32,768 words can be accommodated. Each of the
eight pages can be relocated anywhere in the physical memory, as long as each relocated page begins
on a boundary that is a multiple of 32 words. However, for pages that are smaller than 4K words, only
the memory actually allocated to the page may be accessed.

The relocation example shown in Figure 4-32 illustrates several points about memory relocation.
1.

Although the program appears to be in contiguous address space to the processor, the 32Kword physical address space is actually scattered through several separate areas of physical
memory. As long as the total available physical memory space is adequate, a program can be
ioaded. The physical memory space need not be contiguous.

Pages may be relocated to higher or lower physical addresses with respect to their virtual
address ranges. In the example shown in Figure 4-32, page 1 is relocated to a higher range of
physical addresses, page 4 is relocated to a lower range, and page 3 is not relocated (even
though its relocation constant is non-zero).

All of the pages shown in the example start on 32-word boundaries.

Each page is relocated independently. There is no reason why two or more pages could not
be relocated to the same physical memory space. Using more than one Page Address register
in the set to access the same space would be one way of providing different memory access
rights to the same data, depending on which part of a program was referencing that data.

PROCESSOR

KT11-D

VIRTUAL ADDRESS

PAGE | RELOCATION

RANGES

NO. | CONSTANT

PHYSICAL MEMORY
SPACE

160000-177776

| 1500xx

400000

417776

140000 - 157776

| 0200xx

320000

337776

120000~ 137776

| 1000xx

250000

267776

100000 - 117776

4 | 0200%x

150000

167776

060000 - 077776

3 | 0600XX

100000

- 117776

040000 - 057776

2 | 2500xx

060000

- 077776

020000- 037776

| 3200xx

020000

000000- 017776

| 4000xx

037776

11-1398

Figure 4-32

Relocation of a 32K Word Program into
124K-Word Physical Memory

4-62

4.12.2.3

Memory Units

Block

Page
No. of Pages
Size of Relocatable Memory
4.12.3

32 words

1 to 128 blocks (32 to 4096 words)
8 per mode
27,768 words max (8 X 4096)

Protection

A timesharing system performs multiprogramming; it allows several programs to reside in memory
simultaneously, and to operate sequentially. Access to these programs, and the memory space they
occupy, must be strictly defined and controlled. Several types of memory protection must be afforded
a timesharing system. For example:

2.
3.

User programs must not be allowed to expand beyond allocated space, unless authorized by

the system.

Users must be prevented from modifying common subroutines and algorithms that are resi-

dent for all users.

Users must be prevented from gaining control of or modifying the operating system

software,

The memory management option provides the hardware facilities to implement all of the above types
of memory protection.

4.12.3.1 Inaccessible Memory - Each page has a 2-bit access control key associated with it. The key is
assigned under program control. When the key is set to 0, the page is defined as non-resident. Any
attempt by a user program to access a non-resident page is prevented by an immediate abort. Using

this feature to provide memory protection, only those pages associated with the current program are

set to legal access keys. The access control keys of all other program pages are set to 0, which prevents
illegal memory references.

4.12.3.2

Read-Only Memory - The access control key for a page can be set to 2, which allows read

(fetch) memory references to the pages, but immediately aborts any attempt to write into that page.
This read-only type of memory protection can be afforded to pages that contain common data, subroutines, or shared algorithms. This type of memory protection allows the access rights to a given
information module to be user-independent. That is, the access right to a given information module
may be varied for different users by altering the access control key.
A Page Address register in each of the sets (Kernel and User modes) may be set up to reference the
same physical page in memory and each may be keyed for different access rights. For example, the
User access control key might be 2 (read-only access), and the Kernel access control key might be 6
(allowing complete read/write access).

4.12.3.3 Multiple Address Space - There are two complete, separate PAR/PDR sets provided: one set
for Kernel mode and one set for User mode. This affords the timesharing system with another type of
memory protection capability. The mode of operation is specified by the processor status word current
mode field, or previous mode field, as determined by the current instruction.

4-63

Assuming the current mode PSW bits are valid, the Active Page register sets are enabled as follows:
PSW (Bits 15,14)

PAR/PDR Set Enabled

Kernel mode

(l)(l)

Illegal (all references aborted on access)

User mode

Thus, a User mode program is relocated by its own PAR/PDR set, as are Kernel programs. This

makes it impossible for a program running in one mode to accidently reference space allocated to

another mode when the Active Page registers are set correctly. For example, a user cannot transfer to
Kernel space. The Kernel mode address space may be reserved for resident system monitor functions,
such as the basic input/output control routines, memory management trap handlers, and timesharing
scheduling modules. By dividing the types of timesharing system programs functionally between the
Kernel and User modes, a minimum amount of space control housekeeping is required as the timeshared operating system sequences from one user program to the next. For example, only the user
PAR/PDR sets needs to be updated as each new user program is serviced. The two PAR /PDR sets
implemented in the memory management unit are shown in Figure 4-30.
4.12.4 Active Page Registers
The memory management unit provides two sets of eight Active Page registers (APRs). Each APR

consists of a Page Address register (PAR) and a Page Descriptor register (PDR). These registers are
always used as a pair and contain all the information required to locate and describe the current active
pages for each mode of operation. One PAR /PDR set is used in Kernel mode and the other is used in
User mode. The current mode bits (or in some cases, the previous mode bits) of the processor status
word determine which set will be referenced for each memory access. A program operating in one
mode cannot use the PAR/PDR sets of the other mode to access memory. Thus, the two sets are a key

feature in providing a fully protected environment for a timesharing multiprogramming system.

A specific processor I/O address is assigned to each PAR and PDR of each set. Table 4-12 is a
complete list of address assignments.

NOTE
,
Unibus devices (except DMA and programmer’s
console) cannot access PARs or PDRs. The internal

address decode logic (print K1-10) allows only the
processor to access these registers.

Table 4-12

PAR/PDR Address Assignments

Kernel Active Page Registers

User Active Page Registers

No.

PAR

PDR

No.

PAR

PDR

0
1
2
3

772340
772342

772300
772302
772304
772306

0
|
2
3

777640
777642

777600
777602

777644

777604

772310

777646
777650
777652
777654
777656

777606
777610
777612
777614
777616

4
S

6
7

772344

772346
772350
772352
772354
772356

772312

772314
772316

6
7

4-64

In a fully protected, multiprogramming environment, the implication is that only a program operating
in the Kernel mode would be allowed to write the PAR and PDR locations for the purpose of mapping
user’s programs. However, there are no restraints imposed by the logic that will prevent User mode
programs from writing into these registers. The option of implementing such a feature in the operating
system, and thus explicitly protecting these locations from user’s programs, is available to the system
software designer.

4.12.4.1 Page Address Registers (PAR) - The Page Address register (PAR), shown on print K1-7 and
I in Figure 4-33 contains the 12-bit Page Address Field (PAF) that specifies the base address of the
page.

PAGE

ADDRESS

FIELD

(PAF)
11-1036

Figure 4-33

Page Address Register

Bits 15-12 are unused and reserved for possible future use.

The Page Address register may be alternatively thought of as a relocation constant, or as a base
register containing a base address. Either interpretation indicates the basic function of the Page
Address register (PAR) in the relocation scheme.
The Page Address register (PAR) may be regarded as either a base register containing a base address or
a relocation constant. Bits are fed directly from the SSMUX to an address selected by the PAR/PDR
ADRS MUX (E91 on print K1-7) when enabled by K1-10 PAR & PDR LOW L. The three scratchpad

memories that comprise the PAR (E78, E79, and E80 on print K1-7) are clocked by K1-5 REG CLK
H. The two associated with PAR 03:00 and PAR 07:04 are enabled by K1-10 LOAD PAR LOW L,
while the other (PAR 11:08) is enabled by K1-10 LOAD PAR HIGH L. Outputs of the PARs are fed
directly to the KTMUX on print K1-9, and can be channeled onto the scratchpad output lines
(SP15:00) when K1-10 PAR & PDR L is asserted and K1-10 KTM UX SO L is unasserted. This allows
the contents of the registers to be accessed by a DATI or DATIP.
4.12.4.2

Page Descriptor Registers - The Page Descriptor register (PDR) comprises four scratchpad
memories (E81, E88, E90, and E89 on print K 1-7) and contains information regarding page expansion,
page length, and access control (Figure 4-34). Bits are fed directly from the SSMUX to an address
selected by the PAR/PDR ADRS MUX (E89 on print K1-7) and clocked by K1-5 REG CLK H.

WRITTEN INTO
EXPANSION

Cen v

PAGE LENGTH FIELD

(PLF)

TIA

DIRECTION

ACCESS CONTROL FIELD

Figure 4-34

Page Descriptor Register

4-65

ACF

11-1395

Access Control Field (ACF)
This 2-bit field (PDR 02:01) of the PDR describes the access rights to the specified page. The access
codes or “keys” [K1-7 ACF 2 (1) H and K1-7 ACF 1 (1) H from E88] specify the manner in which a
page may be accessed and whether or not a given access should result in an abort of the current
operation. A memory reference that causes an abort is not completed and is terminated immediately.

Aborts are caused by attempts to access non-resident pages, page length errors, or access violations,
such as attempting to write into a read-only page. All memory management traps vector through
location 250 and can be used as an aid in gathering memory management information.
In the context of access control, the term “write” is used to indicate the action of any instruction which

modifies the contents of any addressable word. A “write” is synonymous with what is usually called a
“store” or “‘modify” in many computer systems. Table 4-13 lists the four ACF keys and their functions. The ACF is written into the PDR under program control.

Table 4-13
ACF

Key | Description

Access Control Field Keys
Function

Non-resident

Abort any attempt to access this non-resident page.

Resident read-only

Abort any attempt to write into this page.

Unused

Abort all accesses.

Resident read /write

Read or write allowed. No trap or abort occurs.

Expansion Direction (ED)
The ED bit located in PDR bit 3 indicates the authorized direction in which the page can expand. A
logic 0 in this bit (ED = 0) indicates the page can expand upward from relative zero. A logic 1 in this
bit (ED = 1) indicates the page can expand downward toward relative zero. The ED bit is written into
the PDR under program control. When the expansion direction is upward (ED = 0), the page length is
increased by adding blocks with higher relative addresses. Upward expansion is usually specified for
program or data pages to add more program or table space. An example of page expansion upward is
shown in Figure 4-35.
When the expansion direction is downward (ED = 1), the page length is increased by adding blocks
with lower relative addresses. Downward expansion is specified for stack pages so that more stack

space can be added. An example of page expansion downward is shown in Figure 4-36.
NOTE
To specify a block length of 42 for an upward-expan-

dable page, write the highest authorized block number directly into the highest byte of PDR. Bit 15 is

not used because the highest allowable block number
is 177,.

4-66

PDR

PAR

000

001

111

000

0101001

CO0OO Q 110

PAF = 0170 :l
PLF =515 = 41,, BLOCK

ED=0=UPWARD

NO.

EXPANSION

ACF=6=READ/WRITE
NOTE:
TO

SPECIFY

PAGE,
BYTE

WRITE

NUMBER

VIRTUAL

BLOCK

PDR. BIT 15

LENGTH

HIGHEST
IS

OF 42

AUTHORIZED

FOR AN UPWARD EXPANDABLE
BLOCK

NO.

DIRECTLY

NOT USED BECAUSE THE HIGHEST

INTO

HIGH

ALLOWABLE

BLOCK

177g

ADDRESS

BLOCK

NO
> PDR

BLOCK

NO-PAGE

LENGTH

ERROR (PLE)

7
7

/BLOCK 1774

ANY BLOCK
ADDRESS

RANGE

OF POTENTIAL PAGE
EXPANSION

//{BLOCK

1764

GREATER

(VA<12:06>) 514)

CHANGING THE

NUMBER

THAN 40 (51g)

PLF

WiLL CAUSE A PAGE
iy

" BLOCK 52

LENGTH

ABORT.

024176
BLOCK 514

024100
b
————
]

01 70XX
51

START
BLOCKS

0241XX

END

e
—

017276
AUTHORIZED

PAGE

BLOCK 2

LENGTH = 42,, BLOCKS

OR O THRU 51g=
52g BLOCKS

017200
017176

BLOCK

017100
017076

BLOCK

O
017000

+—BASE ADDRESS OF PAGE
11-1030

Figure 4-35

Example of an Upward-Expandable Page

4-67

——ACTIVE

PAGE REGISTER

CONTENTS—W

PAR

PDR

000 001 111 000
.

01010110

;

0000

110

PAF=O1?O———~———J
PLF=126g = 860

ED =1= DOWNWARD EXPANSION

TO SPECIFY
WRITE
IN

PAGE

LENGTH

COMPLEMENT

THIS

EXAMPLE,A

FOR A DOWNWARD

BLOCKS

42-BLOCK

REQUIRED
PAGE

EXPANDABLE

INTO

PAGE,

HIGH BYTE

OF PDR.

IS REQUIRED.

PLF IS DERIVED
AS FOLLOWS
:

4240
= 52g ; TWO'S COMPLEMENT
= 1264
VIRTUAL

ADDRESS

BLOCK

NO.<PDR

BLOCK

036776
BLOCK

NO.-» PAGE

LENGTH

ERROR (PLE)

FIRST BLOCK OF DOWNWARD
EXPANDABLE PAGE

177g

036700

036676
BLOCK

176g

036600
036576

AUTHORIZED PAGE

LENGTH=42 40 BLOCKS

BLOCK

175g
036500

]

031676
BLOCK

0170XX
_
_126

PAGE BASE
BLOCKS

0316XX
52

START
BLOCKS

0367XX

END

126g
031600

L0000
'BLOCK

2,7

1254¢

/BLOCK1243;2
ADDRESS

RANGE

OF POTENTIAL PAGE
EXPANSION BY
CHANGING THE PLF

A BLOCK NUMBER
REFERENCE LESS
THAN 126 g

[ (VA <12:06> LESS THAN 126g)
-, 017176

;7ELOCK 77
ol 017100
/

7/,

WILL CAUSE A PAGE
LENGTH ABORT.

011076

’;BLOCK 0%
7

017000

~«—BASE ADDRESS OF PAGE
11-1031

Figure 4-36

Example of a Downward-Expandable Page

4-68

Written Into (W)

The W bit located in PDR bit position 6 indicates whether the page has been written into since it was
loaded into memory. W = 1 is affirmative. The W bit is automatically cleared when the PAR or PDR
of that page is written into. It can only be set by the control logic (print K1-7). In disk-swapping and
memory overlay applications, the W bit can be used to determine which pages in memory have been
modified by a user. Those pages that have been written into must be saved in their current form; those
that have not been written into (W = 1) need not be saved, and can be overlaid with new pages, if

Page Length Field
The 7-bit page length field (PLF) located in PDR bits 14:08 specifies the authorized length of the page
in 32-word blocks. The PLF holds block numbers from 0 to 1775, thus allowing any page length from 1
block to 128 blocks. The PLF is enabled by K1-10 LOAD PDR HIGH L, and written into the PDR
under program control.
PLF for an Upward-Expandable Page
When the page expands upward (ED = 0), the PLF must be set to one less than the intended number of
blocks authorized for that page. Thus, if the number of blocks authorized is 523 or 42, the PLF is set
to Slg or 41,0, with block O being the page boundary and the first block of the page. A comparator
network (E61 and E72 on print K1-8) compares the virtual address block number (VBA 12:06) with
the PLF to determine whether the VBA is within the authorized page length. If the VBA block number
is less than (A < B) or equal to (A = B) the PLF, the VBA is within the authorized page length. If the
VBA block number is greater than (A > B) the PLF, a page length fault is detected by the hardware
and K1-8 KT FAULT L is issued to the DAT TRAN circuitry on print K2-1, where it generates K2-1
ENAB ABORT H, causing a trap. When the expansion direction is upward, the page length is
increased by adding blocks with higher relative addresses. Upward expansion is usually specified for
program or data pages to add more program or table space (Figure 4-35).
PLF for a Downward-Expandable Page

The capability of providing downward expansion for a page is intended specifically for those pages

that are to be used as stacks. In the PDP-11/34A, a stack starts at the highest location reserved for it,
and expands downward toward the lowest address as items are added to the stack. If the page is to be
downward-expandable, the PLF must be set to authorize a page length (in blocks) that starts at the
highest address of the page, which is always block 177;s. The rationale for complementing the number
of blocks required to obtain the PLF is as follows:
Maximum Block No. Minus PLF

Required Length Equals

1775 = 525 = 125s
12710 = 4210 = 8510

Figure 4-36 contains an example of a downwafd-expandable page. A page length of 42 blocks is

arbitrarily chosen to match the upward-expandable example shown in Figure 4-35.
NOTE
The same PAF is used in both examples. This is done
to emphasize that the PAF, as the base address,

always determines the lowest address
of the page,
whether it is upward- or downward-expandable.

4-69

4.12.5

Virtual and Physical Addresses

The memory management Unibus addressing circuitry is shown on print K1-6. When memory management is enabled (K1-8 RELOCATE H asserted), the processor ceases to load Unibus addresses
directly from the scratchpad via the Bus Address register multiplexer latches (E44, E55, and E65).
Instead, addresses are relocated by various constants obtained from the memory management circuitry. (Selected PAR contents are added to the VBA using adders E45, E56, and E66.)

4.12.5.1 Construction of a Physical Address - The basic information needed for the construction of a
physical address (PA) comes from the virtual address (VBA), which is illustrated in Figure 4-37, and
the appropriate PAR set.

APF
!

ACTIVE

PAGE FIELD

DISPLACEMENT

FIELD

1-3908

Figure 4-37

Interpretation of a Virtual Address

The virtual address (VBA) consists of:

The Active Page Field (APF). This 3-bit field determines which of eight Active Page registers
(APRO-APR?7) will be used to form the physical address (BA). The PAR/PDR ADRS
MUX (E91 on print K1-7) actually selects the specific PAR.

The Displacement Field (DF). This 13-bit field contains én’addr'ess relative to the beginning

of a page. This permits page lengths up to 4K words (2!3 = 8K bytes). The DF is further
subdivided into two fields as shown in Figure 4-38.

BN
1

DIB
Il

BLOCK NUMBER

’

DISPLACEMENT IN BLOCKS
11-3909

Figure 4-38

Displacement Field of Virtual Address

of:
The displacement field (DF) consists

The Block Number (BN). This 7-bit field is interpreted as the block number within the
current page.

The Displacement in Block (DIB). This 6-bit field contains the displacement within the
block referred to by the block number.

4-70

The remainder of the information needed to construct the physical address comes from the 12-bit page
address field (PAF) (part of the Active Page register) and specifies the starting address of the memory
which that APR describes. The PAF is actually a block number in the physical memory, ¢.g., PAF = 3
indicates a starting address of 96 (3 X 32 = 96) words in physical memory.

The formation of the physical address is illustrated in Figure 4-39.

APF

DIB

ADDRESS

L
g
////
//

PAGE ADDRESS FIELD
1

‘

ACTIVE PAGE

VIRTUAL

NO.

BLOCK

6
PHYSICAL BLOCK
1

]--__-__-[

oIB

0
PHYSICAL
ADDRESS

(DISPLACEMENT IN BLOCKS)
11-3907

" Figure 4-39

Construction of a Physical Address

The logical seq'uence involved in constructing a physical address is as follows:
1.

Select a set of Active Page registers depending on current mode.

The active page field of the virtual address is used to select an Active Page register (APROAPR?Y).

The page address field of the selected Active Page register contains the starting address of
the currently active page as a block number in physical memory.

The block number from the virtual address is added to the block number from the page
address field to yield the number of the block in physical memory which will contain the
physical address being constructed.

The displacement in block from the displacement field ofthe virtual address is joined to the
physical block number to yield a true 18-bit physical address.

4.12.5.2

Determining the Program Physical Address - A 16-bit virtual address can specify up to 32K
words, in the range from 0 to 177776 (work boundaries are even octal numbers). The three most
significant virtual address bits designate the PAR /PDR set to be referenced during page address relocation. Table 4-14 lists the virtual address ranges that specify each of the PAR/PDR sets.

4-71

Table 4-14

Relating Virtual Address to PAR/PDR Set

Virtual Address Range

PAR/PDR Set

AN DA W

—O

000000-17776
020000-37776
040000-57776
060000-77776
100000-117776

120000-137776
140000-157776

160000-177776

NOTE
Any use of page lengths less than 4K words causes

holes to be left in the virtual address space.

4.12.6

Status Registers
Aborts generated by the protection hardware are vectored through Kernel virtual location 250. Status

registers SRO and SR2 are used to determine why the abort occurred. Note that an abort to a location
which is itself an invalid address will cause another abort. Thus the Kernel program must ensure that
Kernel virtual address 250 is mapped into a valid address; otherwise a loop will occur which will
require console intervention.

4.12.6.1
Status Register 0 (SR0) - SRO contains abort error flags, memory management enable, plus
other essential information required by an operating system to recover from an abort or service a
memory management trap. The SRO format is shown in Figure 4-40. Its address is 777572. Circuitry

used to implement the SRO register is shown on print K1-8.

ABORT- NON-RESIDENT _4

ABORT-PAGE LENGTH ERROR

’

ADDRESS

—

ABORT-READ ONLY
ACCESS VIOLATION
MAINTENANCE MODE
MODE
PAGE NUMBER

ENABLE MANAGEMENT
f1- 391

Figure 4-40

Format of Status Register 0 (SRO)

4-72

Bits 15-13 are the abort flags. They may be considered to be in a *“priority queue’ in that flags to the
right are less significant and should be ignored. For example, a “non-resident’ abort service routine
would ignore page length and access control flags. A “page length” abort service routine would ignore
an access control fault.
|
NOTE
Bit 15, 14, or 13, when set (abort conditions), causes
the logic (E121 generates K1-8 ERROR H) to freeze
the contents of SR0 bits 1 to 6 and status register
SR2. This is done to facilitate recovery from the

abort.

Protection is enabled when an address is being relocated (K1-8 RELOCATE H is active). This implies
that either SRO, bit 0, is equal to 1 (memory management enabled) or that SRO, bit 8, is equal to 1 and
the memory reference is the final one of a destination calculation (maintenance/destination mode).
Note that SRO bits 0 and 8 can be set under program control to provide meaningful memory management control information. However, information written into all other bits is not meaningful. Only
that information which is automatically written into these remaining bits as a result of hardware
actions is useful as a monitor of the status of the memory management unit. Setting bits 15-13 under
program control will not cause traps to occur. These bits, however, must be reset to 0 after an abort or
trap has occurred in order to resume monitoring memory management.

Abort-Non-Resident

Bit 15 is the Abort-Non-Resident bit [K1-8 NR (1) H]. It is set by attempting to access a page with an
access control field (ACF) key equal to 0 or 4 or by enabling relocation with an illegal mode in the
PSW.

Abort-Page Length

Bit 14 is the Abort-Page Length bit [K1-8 PL (1) H]. It is set by attempting to access a location in a
page with a block number (virtual address bits 12-6) that is outside the area authorized by the page
length field (PFL) of the PDR for that page.

Abort-Read-Only
Bit 13 is the Abort-Read-Only bit [K1-8 RO (1) H]. It is set by attempting to write in a read-only page
having an access key of 2.
NOTE
There are no restrictions that any abort bits could
not be set simultaneously by the same access
attempt.

Maintenance/Destination Mode

Bit 8 specifies maintenance use of the memory management unit. It is used for diagnostic purposes.
For the instructions used in the initial diagnostic program, bit 8 is set so that only the final destination
reflerence is relocated. It is useful to prove the capability of relocating addresses, in destination mode
only.

Mode of Operation
Bits 5 and 6 indicate the CPU mode (User or Kernel) associated with the page causing the abort
(Kernel = 00, User = 11).

4-73

Page Number
Bits 3-1 contain the page number of reference. Pages, like blocks, are numbered from O upward The

page number bitis used by the error recovery routine to identify the page being accessed if an abort

occurs.

Enable Relocation and Protection
Bit 0 1s the Enable bit. When it is set to 1, all addresses are relocated and protected by the memory
management unit. When bit 0O is set to 0, the memory management unit is disabled and addresses are
neither relocated nor protected.

4.12.6.2 Status Register 2 (SR2) - SR2 (shown on print K1-9) is loaded with the 16-bit virtual address
(VBA) at the beginning of each instruction fetch but is not updated if the instruction fetch fails. SR2 is
read-only; a write attempt will not modify its contents. SR2 is the virtual address program counter.
Upon an abort, the result of SRO bits 15, 14, or 13 being set will freeze SR2 until the SRO abort flags
are cleared. The address of SR2 is 777576 (Figure 4-41).

]

16-BIT VIRTUAL

ADDRESS

777576

11-3910

Figure 4-41

4.12.7

Format of Status Regi—ser 2 (SR2)

Mode Description

In Kernel mode, the operatmg program has unrestricted use of the machine. The program can map
users’ programs anywherein core and thus explicitly protect key areas (including the device registers
and the processor status word) from the user operatmg environment.

In User mode, a program is inhibited from executing a Halt mstructlon and the processor will trap

through location 10 if an attempt is made to execute this instruction. A Reset instruction resultsin
execution of a NOP (no-operation) instruction.

There are two stacks, called the Kernel stack and the User stack, used by the central processor when
operating in either the Kernel or User mode, respectively.

Stack limit violations are dlsabled in User mode. Stack protectlon is provrded by memory protect
features.
4.12.8

Interrupt Conditions

The memory management unit relocates all addresses. Thus, when management is enabled, all trap,
abort, and interrupt vectors are considered to bein Kernel mode virtual address space. When a vectored transfer occurs, controlis transferred according to a new program counter (PC) and processor
status word (PSW) contained in a 2-word vector relocated through the Kernel Active Page register set.
When a trap, abort, or interrupt occurs, the “push” of the old PC (old PSW) s to the User/Kernel R6
stack specified by CPU mode bits 15 (14) of the new PSW in the vector (00 = Kernel, 11 = User). The
CPU mode bits also determine the new APR set. In this manner it is possible for a Kernel mode
program to have complete control over service assignments for all interrupt conditions, since the
interrupt vector is located in Kernel space. The Kernel program may assign the service of some of these
conditions to a User mode program by simply setting the CPU mode bits of the new PSW in the vector
to return control to the appropriate mode.

474

User Processor Status (PS) operates as follows:
User Traps,

PSW Bits

User RTL,RTT

Interrupts

Cond. Codes (3—0) |

Loaded .from stack

‘Loaded from vector

Trap (4)

Loaded from stack

Loaded from vector

Priority (7-5) .
Previous (13-12) |
Current (15-14)

Cannot be changed
Cafinot be changed
Cannot be éfianged

Loaded from vector
Cépied from PS (15, 14)
Loaded ffom vector

Explicit

PSW Access

*
Cannot be changed

*
*
*

*Explicit operations can be made if the processor status is mapped in user space.

4.13

CONTROL STORE

4.13.1

General Description

The Control Store circuit (prints K2-7 through K2-10) consists of twelve 1024-word by 4-bit bipolar
ROMs, eight hex D-type flip-flops, and an assortment of multiplexers and gates. This logic operates in
a fashion similar to a microprocessor having 10 address lines and 48 data output lines with a fixed set
of ROM program routines.

Each Control Store ROM location can generate a specific set of outputs capable of configuring the
data path, determining the function performed by the arithmetic/logic unit (ALU), influencing the
DAT TRAN circuitry, or exercising general control over the total KD11-EA operation. The contents
of each location are configured in such a way that sequences of locations can be combined into microroutines that perform the various PDP-11 instruction operations. Each ROM location is, therefore,
considered as a microinstruction or microstep.
4.13.2 Branching Within Microroutines
Each microinstruction in the Control Store specifies the location of the next microstep in a sequence.

After the execution of a microstep, the outputs of ROMs E110, E109, and E10 are latched into E90
and E92 (microprogram counter latch) to specify the location of the next microstep. Conditional
branching within a microroutine is accomplished by wire-ORing signals generated by external hardware onto the MPC lines when directed by some other Control Store output. Typical wire-ORed

signals include the following:

Instruction Decode

The microroutines contained in the Control Store are designed
to perform efficiently the operations specified by the various
PDP-11 instructions. Specific microroutines are implemented
for specific instructions. The main purpose of the IR Decode
circuitry is to translate the PDP-11 instruction in the IR to a set

of bits that can be wire-ORed onto the MPC lines upon request

(IR DECODE L), developing the next control word. A description of the specific addresses for each instruction is included in
Paragraph 4.5.3 of this manual.

4-75

Trap Decode

A routine has also been included in the Micro Store to implement an error routine that pushes and pops the PC and PSW
onto or off the processor stack. Upon request of the Control
Store [K2-9 BUT SERVICE (1) H], the MPC 00 line can be
enabled by the Service ROM (ES1), causing a microbranch to
this microroutine.

Upon performing a power restart, the MPC is cleared by an

PWR Restart

Initialize signal (INIT). The power-up circuitry on print K2-3
then enables the MPC 00 line, forcing the Control Store to perform the power-up routine beginning at MPC address 001.

In general, microsteps are not executed from numerically sequential locations in the Control Store;
therefore, care should be taken in following the flows described in Chapter 5 of this manual.
Figure 4-42 shows the format of all 1024 words in the KD 11-EA Control Store. The fields, the possible

values they contain, and the significance of each value are described below.

BUF

ENAB

DATA

TRAN
N

|CYCLE|

CONTROL

ovx | DBE

CONT

BUS

CONTROL

ALU
32

—

MISC

LOAD | LONG | AUX
BAR

MPC

MAINT

e
BUT

/\__w

CONTROL
38

SPA | SRC

FORCE|

SEL | SEL

RSV | MODE | SERV

—~

AMUX

CONTROL

PREV | BUT

SPA DEST

FORCE

SEL

SSMUX

KERNEL

—~
ROM

)

SPA
11-4252

~ Figure 4-42 Control Store Fields

4-76

4.13.3

Control Store Fields

Use the KD 11-EA flow diagrams as reference for actual control field bit patterns.

Field

F-ielvd Length -

Description

MPC

‘Nine-bit micro-PC address, which specifies the ROM loca-

Miscellaneous

Control

Three multipléxed control lines that generate the following

tion of the next microstep to be performed.

enable signals:

LOAD IR L - Allows loading of the Instruction register
(print K2-5).

LOAD PSW L - Allows the PSW register to be loaded upon
completion of this microstep (prints K1-1 through K1-4).
LOAD CC L - Allows the condition codes N, Z, V, and C to
be loaded upon completion of this microstep (print K1-1).
BUT DEST L - Enables microbranch to destination operand
microcode sequence (print K2-6).

ENAB STOV L - Enables the stack overflow detection circuit (print K2-3).
LOAD COUNT L - Allows the counter circuit (print K2-10)
to be loaded upon completion of this microstep.

CLK COUNT L - Enables the counter clock circuit (print
K2-10).

BUF DATTRAN

Bus Control

Enables the data transfer circuitry (print K2-1). Indicates that

the processor is performing a Unibus transfer during this
microstep.

Enables the Unibus control lines BUS CO L and BUS C1 L,
as follows:

ENAB MAINT

Cl(HH

CO(1)H

Transfer

0
0
1
1

0
1
0
1

DATI
DATIP
DATO
DATOB

Enables the memory management maintenance relocation
feature.

LOAD BAR

~ Allows the Physical Bus Address register (BA on print K1-6)
to be loaded during this microstep.

4-77

Field

Field Length

LONG CYCLE

Description

Forces the processor to perform a longer (2‘40 ns) machine

cycle during this microstep. Typically this is done during bus
DATO:s.
AUX CONTROL

Enables the Auxiliary Control ROMs during operate instruction microsteps.

ALU S3-ALU SO
ALU MODE,

Determine the operation performed by the 16-bit ALU
according to Table 4-2. These lines are also wire-ORed,
allowing the Auxiliary Control circuitry to determine the
ALU operations according to Table 4-2.

ALU CIN
BLEG 01:00

These multiplexed outputs control the operation of the B register and BX register during each microstep and detect overflow or double bus errors.

B, BX, OVX,

DBE, CONTROL

Controls the select lines of the SSMUX according to the

SSMUX
CONTROL

following:

Select

SS 01 H

SS00 H

Straight

Sign Extend
Swap Bytes

0
1

External Data

1
0
1

Controls the select lines of the AMUX according to the

AMUX
CONTROL

following:

Data

PSW

ALU
Vector
Unibus

AMUX S0

0
1

1
0

Encoded control lines that select the specific microbranch
condition that can occur during this microstep.

BUT BITS

SPA SRCSEL

AMUX S1

Controls the select lines of the scratchpad address multiplexer
during the first half of this microstep.

Field Select
ROM
RS
RD
RBA

4-78

SEL 1

SEL 0

0
0
1
1

0
|
0
|

Field

Field Length

Description

SPA DST SEL

Controls the select lines of the scratchpad address multiplexer
during the second half of this microstep.
Field Select
ROM
RS
RD
RBA

SEL 1

SELO

0
0
1
1

0
1
0
1

FORCE RSV

Controls which source register will be selected by the scratchpad address multiplexer. If RS = is an even-numbered register, then RSVl = Register 1. If, however, RS = an oddnumbered register, then RSV1 = the same register.

PREVIOUS
MODE

Allows the processor to perform this microstep using the previous memory management mode [PSW (13:12)].

BUT SERVICE

Indicates that the processor has entered the Service microstep. Enables the Service ROM (ES50), causing the processor
to recognize any pending errors or interrupts.

Force Kernel

Forces the processor to perform this microstep in the memory management Kernel mode.

ROM SPA

Allows the microinstructions from the Control Store to determine which scratchpad register will be addressed during the
next microstep, unless otherwise specified by the scratchpad
address multiplexer control lines previously mentioned.

4-79

CHAPTER 5
MICROCODE

5.1 MICROPROGRAM FLOWS
‘
A complete set of microinstruction flows is shown in block diagram form in the KD11-EA print set.
Figure 5-1 is a simplified version that provides an overview and aids in using the detailed flows. No
attempt will be made in this manual to trace each path of this microcode, but the following examples

should provide an adequate background for the reader.
5.2 FLOW NOTATION GLOSSARY
The block flows should be self-explanatory. To aid in understanding them, the following glossary of
flow notation should be reviewed.

Designation

Definition

Unibus Bus Address lines

;
DATI
+
PC
B

IR
BX
RS
RD
RN
ENAB STOV
ENAB DBE
DATO

DATIP
Rn OP B

Minus the operator
Separator
~Initiate DATI operation on Unibus
Plus the arithmetic operator
Program Counter = scratchpad register 7 (R7)
B register

Instruction register
BX register
Scratchpad register specified by the source portion of the current instruction
[IR (08:06)]
Scratchpad register specified by the destination portion of the current
instuction [IR (02:00)]
Scratchpad register n specified by the Control Store ROM SPA lines
Enable the stack overflow detection logic
Enable the double bus error detection logic.
Initiate DATO operation on Unibus.
Initiate DATIP operation on Unibus.
ALU function determined by the auxiliary ALU control logic as a function

~of the instruction currently in the Instruction register.
BUT
LOAD CC

Branch on microtest.
Set condition codes (N, Z, V and C) according to the result of operation

being performed by the ALU.
UDATA

Data being received from the Unibus data lines BUS D00 L through BUS

RSVI

DIS L.
Source register specified by source portion of current instuction [IR (08:06)]

ORed with a logical 1. Example: If RS is even, RSV1 would be the next

highest register (RS = 4, RSV1 = 5); if, however, RS is odd, RSV1 would be
the same register (RS = 5, RSVI1 = 5).
-

Assignment operator.

MAINT

Indicates that the memory management Maintenance feature is enabled.

Indicates that this microstep is using the previous memory management
mode.

5-1

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5-2

KD11-EA

CENTRAL PROCESSOR

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