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VAX Architecture Handbook

VAX Architecture Handbook
1986

Digital believes the information in this publication is accurate as of its publica¬
tion date; such information is subject to change without notice. Digital is not
responsible for any inadvertent errors.
The following are trademarks of Digital Equipment Corporation:
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UNIBUS

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Professional

VAX

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And the Digital Logo: SQSDDSD
Copyright ® 1986 Digital Equipment Corporation. All Rights Reserved.

CONTENTS

Preface
Chapter 1 ■ VAX Architecture Design
Introducing VAX Architecture.1-1
Virtual Address Extension.1-2
PDP-11 Computer Compatibility Option.1-3
Memory Management.1-3
Additional Literature.1-4

Chapter 2 ■ VAX Architecture Overview
Processing Concepts.2-1
Context Switching.2-2
Priority Dispatching.2-3
Virtual Addressing.2-4
Memory Management.2-4
Instruction Set.2-5
Routine Call Capability.2-7
Instruction Operand Processing.2-7
Process Control Instructions.2-8
General Register Addressing.2-9
Data Types.2-10
Stacks.2-13
Condition Codes.2-13
Exceptions and Interrupts.2-14
Input/output Control.2-15

Chapter 3 ■ VAX Architecture Characteristics
Programming Environment.3-1
Processor Status Longword.3-1
Processor Access Modes.3-1
Special Instructions.3-2
Data Sharing.3-3
Data Access Synchronization.3-3

Registers.3-4
General Registers.3-4
Processor Registers.3-7
Input/output Registers.3-13
Stacks.3-14
Cache Memory.3-16
Restartability.

3-17

Interrupts and Errors..3-18

Chapter 4 ■ Data Representation
Character String Data.4-1
Floating-point Data.4-2
D_floating Data.4-2
F_floating Data.4-3
G_floating Data.4-4
H_floating Data.4-5
Integer Data.4-6
Byte Data.4-7
Word Data.4-7
Longword Data.4-8
Quadword Data.4-8
Octaword Data.4-9
Numeric String Data.4-10
Leading Separate Numeric String Data.4-10
Trailing Numeric String Data.4-12
Packed Decimal String Data.4-16
Queue Data.4-17
Variable Length Bit Field Data.4-21
Data in Registers.4-24

Chapter 5 ■ The Instruction Characteristics
Notation Convention.5-1
Assembler Notation.5-1
Operand Notation.5-1
Operation Notation.5-2
Range and Extent Notation.5-5
MACRO Source Statement Format.5-5
Instruction Format.5-6
Operator Field.5-8
Operand Field.5-9

Addressing Modes.5-10
General Mode Addressing.5-12
Branch Mode Addressing.5-41

Chapter 6 ■ Functions of the Instruction Set
Address Instructions.6-1
Arithmetic Instructions.6-2
Character String Instructions.6-2
Control Instructions.6-3
Case Instructions.6-4
Loop Control Instructions.6-4
Subroutine Call Instructions.6-4
Transfer Instructions.6-5
Cyclic Redundancy Check Instruction.6-5
Decimal String Instructions.6-6
Edit Instruction.6-9
Floating-point Instructions.6-10
Index Instruction.6-12
Integer Instructions.6-13
Logic Instructions.6-13
Multiple Register Instructions.6-14
Privileged Instructions.6-15
Procedure Call Instructions.6-16
Processor Status Longword Instructions.6-18
Queue Instructions.6-19
Absolute Queue Instructions.6-19
Self-relative Queue Instructions.6-22
Variable Length Bit Field Instructions.6-25

Chapter 7 ■ Memory Management
Virtual Memory.7-2
Virtual Address Space.7-6
Address Translation.7-8
Page Table Entry.7-8
Page Table Entry for I/O Devices.7-10
Changing Page Table Entries.7-11
System Space Address Translation.7-11
Process Space Address Translation.7-13
Access Control.7-16

Controlling Memory Management.7-19
Faults and Parameters.7-20
Accessing Privileged System Services.7-22

Chapter 8 ■ Exceptions and Interrupts
Event Handling.8-1
Interrupt Priority Levels.8-3
Exceptions and Interrupts.8-3
Processor Status.8-4
Asynchronous System Traps.8-7
Exceptions.8-9
Arithmetic Exceptions.8-9
Instruction Fault.8-11
Memory Management Exceptions.8-12
Operand Reference Exceptions.8-12
Serious System Failures.8-14
Trace Exceptions.8-15
Interrupts.8-18
Device Interrupts.8-19
Software-generated Interrupts.8-19
Urgent Interrupts.8-21
Interrupt Priority Level Register.8-21
Interrupt Example.8-22
System Control Block.8-23
Stacks.8-27
Stack Location.8-28
Stack Alignment.8-28
Status Bits.8-29
Accessing Stack Registers.8-30
Recognition Priority.8-30
Suspended Instructions.8-31
Initiating an Exception or Interrupt.8-31

Chapter 9 ■ The Instruction Set
Add.9-1
Add Aligned Word Interlocked.9-2
Add Compare and Branch.9-2
Add One and Branch.9-3
Add Packed.9-3
Add with Carry.9-4
Arithmetic Shift.9-4

Arithmetic Shift and Round Packed.9-4
Bit Clear.9-5
Bit Clear Processor Status Word.9-5
Bit Set.9-6
Bit Set Processor Status Word.9-6
Bit Test.9-6
Branch.

9-7

Branch on Bit.9-7
Branch on Bit Interlocked.9-7
Branch on Bit and Modify without Interlock.9-8
Branch on Condition.9-8
Branch on Low Bit.9-10
Branch to Subroutine.9-11
Breakpoint Fault.9-11
Bugcheck.9-11
Call Procedure with General Argument List.9-12
Call Procedure with Stack Argument List.9-13
Case.9-14
Change Mode.9-14
Clear.9-15
Compare.

9-15

Compare Characters.9-16
Compare Field.9-17
Compare Packed.9-17
Convert.9-18
Convert Leading Separate Numeric to Packed.9-20
Convert Longword to Packed...9-20
Convert Packed to Leading Separate Numeric.9-21
Convert Packed to Longword.9-21
Convert Packed to Trailing Numeric.9-22
Convert Trailing Numeric to Packed.9-23
Cyclic Redundancy Check Instruction.9-23
Decrement.9-26
Divide.

9-26

Divide Packed.9-27
Edit Instruction.9-27
EO$ ADJUST_INPUT.9-29
EO$BLANK_ZERO.9-29
EO$CLEAR_SIGNIF.9-29
EO$END.9-30
EO$END_FLOAT.9-30
EO$FILL.9-30
EO$FLOAT.9-31

EO$INSERT.9-31
EO$LOAD.9-32
EO$MOVE.9-32
EO$REPLACE_SIGN.9-33
EO$SET_SIGNIF.9-33
EO$STORE_SIGN.9-34
Exclusive OR.9-34
Extended Divide.9-33
Extended Function Call.9-35
Extended Modulus.9-35
Extended Multiply.9-36
Extract Field.9-36
Find First Bit.9-37
Halt.9-37
Increment.9-38
Index.9-38
Insert Entry in Queue.9-38
Insert Entry into Queue at Head, Interlocked.9-39
Insert Entry into Queue at Tail, Interlocked.9-40
Insert Field.9-41
Jump.9-41
Jump to Subroutine.9-41
Load Process Context.9-42
Locate Character.9-42
Match Characters.9-43
Move.9-43
Move Address.9-44
Move Characters.9-44
Move Complement.9-45
Move from Processor Register.9-45
Move from Processor Status Longword.9-47
Move Negated.9-47
Move Packed.9-48
Move to Processor Register.9-48
Move Translated Characters.9-49
Move Translated until Character.9-49
Move Zero-extended.9-50
Multiply.9-50
Multiply Packed.9-51
Polynomial Evaluation.9-31
Pop Registers.9-32
Probe Accessibility.9-32
Push Address.9-33

Push Longword.9-54
Push Registers.9-54
Remove Entry from Queue.9-54
Remove Entry from Queue at Head, Interlocked.9-55
Remove Entry from Queue at Tail, Interlocked.9-56
Return from Exception or Interrupt.9-56
Return from Procedure.9-57
Return from Subroutine.9-58
Rotate Longword.9-58
Save Process Context.9-58
Scan Characters.9-59
Skip Character.9-59
Span Characters.9-60
Subtract.9-60
Subtract One and Branch.9-61
Subtract Packed.9-62
Subtract with Carry.9-62
Test.9-63

Chapter 10 ■ Architectural Subsetting
Subsetting Rules.10-1
Floating-point Instructions.10-1
String Instructions.10-2
Compatibility Mode Instruction Set.10-2
Processor Registers.10-2
The Kernel Instruction Set.10-3
Instruction Emulation.10-4
Micro VAX I Systems.10-4
Micro VAX II Systems.10-4

Chapter 11 ■ PDP-11 Compatibility Mode
PDP-11 User Environment Emulation.11-2
General Registers.11-2
Stack Pointer Register.11-3
Processor Status Word.11-3
Compatibility Mode Instructions.11-4
Entering and Leaving PDP-11 Compatibility Mode.11-6
Memory Management.11-7
Exceptions and Interrupts.11-10
Tracing in Compatibility Mode.11-10

Unimplemented PDP-11 Traps.11-11
Input/output References.11-11
Processor Registers.11-11
Program Synchronization.11-11

Appendix A ■ Powers of Binary and Hexadecimal Numbers.A-l

Appendix B ■ List of Instructions by Mnemonic.B-l

Appendix C ■ List of Instructions by Opcode.C-l

Glossary.Glossary-1

Index.Index-1

Preface

The primary purpose of this handbook is to provide the detail needed to make
a sound technical evaluation of the capabilities and characteristics of the VAX
Architecture. A secondary purpose is its use as a text for students of computer
architecture. The handbook is not an assembly language reference. However,
readers interested in assembly language programming will find this handbook
an excellent introduction to that subject.

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Chapter 1 ■ VAX Architecture Design

During the next decade, computers and the computer industry will witness
ever-increasing, perhaps unpredictable, demands. In finance, government,
industry, and in the home, computers will serve expanding roles, solving prob¬
lems, managing processes, or facilitating communication. Digital developed an
innovative computer technology to confront these challenges—a technology
that offers vast power and enormous flexibility for every application. At the
same time, we have held fast to the philosophy of affordability and ease of use
that made Digital the leader of the minicomputer industry.
Scientific, industrial, commercial, and educational market users have already
put the original VAX model through its paces in numerous situations—real¬
time, computational, program development. In the coming decade we will see
a wide range of new tasks handled by VAX processors.

■ Introducing VAX Architecture
The VAX architecture is the heart of the VAX processor family. We define
architecture as the collection of attributes common to all VAX processors—
attributes that guarantee that all software developed on a VAX processor runs
without change on all VAX processors.
Particularly pertinent attributes are the instruction set, memory management,
and certain other aspects of the design that help define contexts and pro¬
cesses. Let us make a distinction between the architecture and the implemen¬
tation of that architecture. For example, the architecture of the typewriter is
essentially fixed: it is the keyboard layout. With knowledge of the alphabet
and punctuation systems, any typist can make a typewriter work—can pro¬
cess jobs. However, each manufacturer may implement that architecture in
differing ways. Some may have striking print keys while others may have
spherical typing elements. Some may have a blue keyboard, some black. In
addition, the manufacturer could trade one feature for another; for example, a
lighter touch versus the capability to make a number of carbons. Neverthe¬
less, all typewriters still perform an essential function, typing.
Computer architectures also perform an essential function. Each processor in
the family may bear slightly differing implementations and tradeoffs. Yet all
will fulfill the requirements of the machine. And all will deliver the same ser¬
vice to the users. For example, having learned the instruction set, a program¬
mer is ensured that an instruction performs precisely the same operation on
each processor in the VAX computer family. This includes the Micro VAX pro¬
cessors that use a subset of the VAX instruction set.

1-2 ■ VAX Architecture Design

VAX architecture is appropriate over a variety of system costs, performance
and application needs. Therefore, a broad range of user requirements can be
met at a lower cost because the price of supporting many different architec¬
tures is eliminated.
The most visible attribute of VAX architecture is the instruction set. Over
three hundred instructions give an assembly-level programmer extensive con¬
trol of computer operation. Each instruction has a mnemonic, a shorthand
name that suggests its function. (Obvious mnemonics are ADD, DIV, MOV,
and PUSH.) Independence is incorporated into the instruction set. That is, the
operation being performed, the type of data used, and the method of address¬
ing can all be considered independently by the compiler. This makes for
faster, more efficient, and easier to implement compilers.
Some recurrent operations from high-level languages are engineered into the
hardware so that a single instruction can handle them. The FORTRAN DO
loop and three-operand addition (A = B + C) are examples of operations
that are handled by a single VAX instruction.
The instructions include provisions to make various applications and operat¬
ing system codes more efficient. There are, in this group, hardware support of
queues, easy access to bit fields of variable lengths, and simple instructions to
save or restore a program context.
Because Digital foresaw the possibility of adding more and more applications,
the instruction set is extendible. The instruction set can be expanded to
include new data types and operators in a way that consistently matches all the
ones that already exist. Enormous flexibility is assured this way, because
what exists now does not significantly constrain what may be added in the
future.

■ Virtual Address Extension
The word VAX suggests the premier feature of VAX processors—virtual
address extension. In a VAX computer, information is located with a 32-bit
address. This means effectively that the computer can recognize more than
four billion addresses. In minicomputer and programming terms, this is an
enormous address range. The remarkable thing about this address space is that
it is virtual.
The physical memory of the computer need not be nearly as large as the four
billion bytes for the machine to process data whose addresses are scattered
through the address space. In fact, what happens is that a sophisticated
scheme called memory management allows programmers to operate as if a
major part of the virtual address space is available to them. Memory manage¬
ment handles all the details of storing programs and subsequently bringing
them into main memory where they are processed.

1-3

From the programmers’ points of view, two billion bytes of virtual address
space can be used for programs. Programmers need never worry about the
complicated techniques of overlaying or segmenting to squeeze the program
into a smaller address range. Logic is built into the VAX processors to quickly
■ translate all the virtual addresses to physical addresses
■ store the programs and data in convenient locations
■ bring into main memory whatever parts of the program or data are needed
at any instant.

Another characteristic of the VAX architecture is the rapid switching of pro¬
cess context. VAX machines are high-powered processors. Many programs
and many programmers can use a VAX processor simultaneously, with each
appearing to have control. Actually, the processor is executing pieces of one
program and switching back and forth to execute other programs. A switchedin context allows a program to run. A switched-out context makes the program
wait for the processor. Consequently, many different activities can occur on a
VAX processor at any one time. Context switching takes place so quickly that
no one is aware of the change.

■ PDP-11 Computer Compatibility Option
We use the word compatibility to designate VAX systems’ connection to the
PDP-11 computers. Customers have a large investment in the PDP-11 com¬
puters and software. To protect that investment, and to simplify the migra¬
tion procedures, Digital offers optional software to ensure that VAX systems
accept with minimal conversion many types of PDP-11 programs.
Conversely, VAX systems offer an excellent host development environment
for applications that will eventually run on PDP-11 computers. Naturally,
there are some restrictions. But most of the time, a simple recompilation of
programs is all that is required to carry a PDP-11 program to a VAX processor.
Compatibility mode programs may execute with native mode programs in a
VAX system environment.

■ Memory Management
The memory management hardware is responsible for maintaining virtual
memory environment and for enforcing memory protection between access
modes. But that is only a part of the memory management function. In particu¬
lar, the memory management hardware enables the operating system to pro¬
vide an extremely flexible and efficient virtual memory programming
environment.

1-4 ■ VAX Architecture Design

Virtual address space consists of all possible 32-bit addresses that can be
exchanged between a program and the processor to identify a byte location in
physical memory. The memory management hardware translates a virtual
address into a physical address.
NOTE
A physical address is the address exchanged between the pro¬
cessor, memory, and the peripheral adapters. Typically, the
physical address is transparent to the programmer, who deals
with virtual addresses.

■ Additional Literature
Additional literature on the VAX architecture is available. The literature is
directed toward two types of readers—those who need only enough detail to
evaluate the VAX processors and those who need the myriad of detail needed
to develop assembly language programs. Should you need for that literature, it
can be ordered through your local Digital Sales Office or through the Digital
Accessories and Supplies Group.
For the evaluators, there is the VAX Handbook Series of which this handbook
is one. They cover a variety of subjects related to VAX processors—hardware,
software, languages, tools, and others.
For assembly language programmers (and in-depth evaluators), there is a man¬
ual available that describes the architecture in great detail (VAX-11 Architec¬
ture Reference Manual, Order Code EK-VAXAR-RM-002). The manual
provides a functional description of the behavior of the VAX processors. In
addition, there is a programming card containing the instructions in tabular
form. The card lists by opcode each instruction, its arguments, and the affect
the instruction has on the condition codes (VAX-11 Programming Card, order
number AV-D827C-TE).
We hope that the handbooks answer most of your questions about the VAX
family of computers, their architecture, and the abundance of available soft¬
ware. If you have more questions, your Digital sales representative will be
happy to help you.

Chapter 2 ■ VAX Architecture Overview

The term VAX architecture, when used in the context of this discussion, refers
to the functional behavior of a VAX processor as opposed to the logical design
and the physical implementation. The primary advantage of a common family
architecture is that it provides the ability to create software on one processor
and execute that software on any other processor in the family.
NOTE
For your convenience, this handbook contains a glossary of
words and terms that have either a unique meaning in VAX
systems or are used with special meaning.

■ Processing Concepts
VAX processors are designed specifically to support a high-performance multi¬
programming environment. The major advantage of a multiprogramming sys¬
tem is its ability to share its resources. For example, multiprogramming
enables the apparently simultaneous execution of many applications and the
interactive development of applications programs. Hardware characteristics
that support multiprogramming are
■ Rapid context switching.
■ Priority dispatching.
■ Virtual addressing.
■ Memory management.

Multiprogramming VAX systems not only share the processor among several
processes but also protect processes from one another while allowing them to
communicate and share both code and data.
A process is the basic entity that can be executed by a VAX system. Processes
consist of an address space, a hardware context, and a software context. The
hardware context is defined by a process control block (PCB). The block is a
data structure containing images of the general purpose registers, processor
status longword, program counter, process stack pointers, process mapping
registers, and several minor control fields.

2-2 ■ VAX Architecture Overview

When a process is not executing, its hardware context is stored in the process
control block. Most of the process control block must be moved to internal
registers for the process to execute. When a process is executing, some of its
hardware context is updated in the internal registers.
Saving the contents of the privileged registers in the process control block of
the currently executing process and then loading a new set of context in the
privileged registers from another process control block is termed context
switching. Context switching occurs as one process after another is scheduled
for execution.
Context Switching
In a multiprogramming environment, several individual streams of code can
be ready to execute at any time. Instead of allowing each stream to execute to
completion serially (as in a batch-only stream), the operating system inter¬
venes and switches among them. In VAX computers, the hardware establishes
an environment for rapid switching. Switching occurs to increase the effi¬
ciency of the computer by using its resources in a balanced fashion, and to
allow the intervention of processes or events that require priority treatment.
The stream of code executing at any one time is determined by its hardware
context; that is, the information that is in processor registers. That informa¬
tion identifies
■ The location of the stream’s instructions and data.
■ Which instruction to execute next.
■ The processor status during execution.

Therefore, a process is a stream of instructions and data defined by a hardware
context. Each process has a unique identification. The operating system
switches between processes by requesting the processor to save one process’s
context and load another. Context switching occurs rapidly because the
instruction set includes instructions that save and load hardware context.
For each process eligible to execute, the operating system creates a data struc¬
ture called the software process control block. Within that block is a pointer
to another data structure, the hardware process control block. That control
block contains the hardware process context, that is, all the data needed to
load the processor’s programmable registers when a context switch occurs. To
give control of the processor to a process, the operating system loads the pro¬
cessor’s process control block base register with the physical address of a hard¬
ware process control block and issues the load process context instruction. The
processor loads the process context in one operation and is ready to execute
code within that context.

2-3

The process control block also contains the definition of the process virtual
address space. Thus, the mapping of the process is automatically contextswitched.
Furthermore, the process control block provides the mechanism for triggering
asynchronous system traps (AST) to processes. The AST field is used to sched¬
ule a software interrupt. The interrupt initiates an AST routine and ensures
that they (interrupt and AST routine) are delivered to the proper process.
Priority Dispatching
While running in the context of one process, the processor executes instruc¬
tions and controls data flow to and from peripherals and main memory. To
share processor, memory, and peripheral resources among many processes, the
processor has two arbitration mechanisms that support high-performance
multiprogramming—exceptions and interrupts. Exceptions are events that
occur synchronously (predictably) with respect to the execution of a particular
stream of instructions. Interrupts are external events that occur asynchro¬
nously.
The flow of execution can change at any time, and the processor distinguishes
between changes in flow that are local to a process and those that are systemwide. Process-local changes occur as the result of a user software error or
when user software calls operating system services. They are handled through
the processor’s exception detection mechanism and the operating system’s
exception dispatcher.
Systemwide changes in flow generally occur as the result of interrupts from
devices or interrupts generated by the operating system software. Interrupts
are handled by the processor’s interrupt detection mechanism and the operat¬
ing system’s interrupt service routines. Systemwide changes in flow may also
occur as the result of severe hardware errors, in which case they are handled
either as special exceptions or high-priority interrupts.
Systemwide changes in flow take priority over process-local ones. Further¬
more, the processor uses a priority system for servicing interrupts. Each kind
of interrupt is assigned a priority, and the processor responds to the highestpriority interrupt pending. For example, interrupts from the high-speed disk
devices take precedence over interrupts from low-speed devices.
The processor services interrupts between instructions, or at well-defined
points during the execution of long, iterative instructions. When the proces¬
sor acknowledges an interrupt, it switches rapidly to a special systemwide con¬
text to enable the operating system to service the interrupt. Systemwide
changes in the flow of execution are handled so they do not disrupt individual
processes.

2-4 ■ VAX Architecture Overview

Virtual Addressing
Most data is located in memory using the address of an 8-bit byte. Virtual
addresses identify the byte locations. Such addresses are called virtual because
they are not the real addresses for physical memory locations. Rather, they are
translated into real addresses by the processor under operating system control.
A virtual address, unlike a physical memory address, is not a unique address of
a location in memory. For example, two programs using the same virtual
address might refer to two different physical memory locations. Conversely,
two programs could refer to the same physical memory location using differ¬
ent virtual addresses.
The set of all possible 32-bit virtual addresses is called virtual address space.
It can be viewed as an array of byte locations labeled from 0 to 4,294,967,295
(232 - 1). This space is divided into sets of virtual addresses designated for
certain uses: those used by processes constitute half of the total virtual
address space, and are collectively designated as process space. Addresses in
the remaining half of virtual address space refer to locations maintained and
protected by the operating system, and are collectively designated as system
space.
Memory Management
Memory management hardware enables the operating system to provide an
extremely flexible and efficient virtual memory programming environment.
The memory management hardware oversees the handling of virtual address
space including memory protection.
Virtual address space is divided into pages. Each page represents 512 bytes of
contiguously addressed memory. The first page begins at byte 0 and continues
to byte 511. The next page begins at byte 512 and continues to byte 1023,
and so forth.
To make memory mapping efficient, the processor must be able to translate
virtual addresses rapidly to physical addresses. Two features providing rapid
address translation are the processor’s internal address translation buffer and
the translation algorithm itself.
The processor has three pair of page mapping registers. Two pair are for the
process space (P0 and PI) and one pair for system space. The operating sys¬
tem’s memory management software loads the pairs of registers with base
addresses and lengths of data structures called page tables. The tables provide
the mapping information for each virtual page in the system. Thus, there is
one page table for each of the three regions.

2-5

A page table is a virtually contiguous array of page table entries. Each entry is
a longword representing the physical mapping and protection for one virtual
page. To translate a virtual address to a physical address, the processor uses
the virtual page number as an index into the page table from the given page
table base address. Each translation contains 512 virtual addresses.
All process page tables have virtual addresses in the system region of virtual
address space. But the system region page table itself is located by its address
in physical memory. That is, the system region page table base register con¬
tains the physical address of the page table base, while the process page table
base registers contain the virtual addresses of their page table bases.
There are two advantages to using a virtual address as the base address of a
process page table. The first is that all page tables need not reside in physical
memory. The system region page table is the only page table that needs to be
resident in physical memory. The process page tables can reside in auxiliary
memory. That is, they can themselves be paged and swapped as necessary.
The second advantage is that the operating system’s memory management soft¬
ware can allocate process page tables dynamically because they do not need to
be mapped into contiguous physical pages. And although the system region
page table must be mapped into contiguous physical pages, this requirement
does not restrict physical memory allocation. The region is shared among pro¬
cesses and therefore does not require redefinition from context to context.
Memory protection is implemented by having four access modes. Each pro¬
cess is assigned an access mode. The hardware checks the memory access
request against the assigned access mode. There are four access modes: ker¬
nel, executive, supervisor, and user. The kernel mode has the highest degree
of access while the user has the lowest degree of access. Memory management
is described in greater detail later in this book.

■ Instruction Set
A major goal of the VAX architecture is to provide an instruction set that is
symmetrical with respect to data types. Symmetrical operations include data
movement, data conversion, data testing, and computation. Thus, the best
instruction for the data type can be selected for optimum processing.
Instruction mnemonics are formed by combining an operator abbreviation
with a data-type suffix. Conversion instructions are formed by adding suf¬
fixes for both the source and destination data types. Computation instruc¬
tions have an additional suffix to indicate the choice between two-operand
and three-operand instructions. Instruction mnemonics were carefully chosen
to ensure they perform the task for which they were designed.

2-6 ■ VAX Architecture Overview

A native-mode instruction may start on any byte boundary. The variablelength instruction format makes code more compact and also guarantees that
the instruction set can be easily extended. Operation codes or opcodes for the
operations are single or double bytes followed by up to six operand specifiers.
An operand specifier can be from 1 to 17 bytes long depending on the address¬
ing mode and data type.
Figure 2-1 illustrates the autodecrement mode move longword instruction as a
string of bytes starting with the opcode followed by two operand specifiers.
In this example, the assumed starting location is 00003000. When the proces¬
sor completes the execution of an instruction, the program counter contains
the address of the first byte of the next instruction. Program counter opera¬
tion is totally transparent to the programmer.

MACHINE CODE: (ASSUMED STARTING LOCATION 00003000)
00003000

OPCODE FOR MOVE LONG INSTRUCTION

00003001

AUTODECREMENT MODE, REGISTER R3

00003002

Figure 2-1 ■ Autodecrement Move Longword Instruction

The program counter can be used to identify operands. The assembler trans¬
lates many types of operand references into addressing modes using the pro¬
gram counter. The addressing modes have names different from those when
other registers are used. When using the program counter in autoincrement
mode, the mode is called immediate mode. Immediate mode is used to specify
inline constants. Autoincrement deferred mode using the program counter is
called absolute mode. Absolute mode is used to reference an absolute address.
Displacement and displacement-deferred modes using the program counter
are used to specify an operand using an offset from the current location.
Addressing using the program counter enables the coding of position-inde¬
pendent code. Position-independent code can be executed anywhere in virtual
address space after it has been linked. Program linkages are identified as abso¬
lute locations in virtual address space. All other addresses are identified rela¬
tive to the current instruction.

2-7

Routine Call Capability
The processor provides two kinds of routine call instructions—those for sub¬
routines and those for procedures. In general, a subroutine is a routine entered
using a jump to subroutine or branch to subroutine instruction, while a proce¬
dure is a routine entered using a call instruction.
The processor automatically saves and restores the contents of registers to be
preserved across procedure calls, and it provides two methods for passing argu¬
ment lists to called procedures—by passing the arguments on the stack and by
passing addresses of arguments elsewhere in memory. The processor also con¬
structs a journal of procedure call nesting by using a general register as a
pointer to the place on the stack where a procedure has its linkage data. This
record of each procedure’s stack data, called its stack frame, enables proper
returns from procedures even when the procedures leave data on the stack. In
addition, user and operating system software can unwind the stack frame to
trace back through nested calls to handle errors or debug programs.
Instruction Operand Processing
The following three steps are performed by each instruction during execution.
First, each operand specifier is evaluated by type of access in the order in
which they appear in the instruction stream.
1. Read access—evaluate the operand address, read the operand, and save
the operand.
2. Write access—evaluate the operand address and save the address.
3. Modify access—evaluate the operand address, read the operand, save both
the address and the operand.
4. Address and branch access—evaluate the address and save the address.
5. Field access—evaluate the operand base address and save the address.
Second, the operation indicated by the instruction is performed. Third, the
result or results are stored using the saved address in the order indicated by
the occurrence of operand specifiers in the instruction stream.
NOTE
Character and numeric string instructions write any output
strings and store the registers during step 3.
The implications of this processing are
1. Autoincrement and autodecrement operations occur as the operand and
specifiers are processed and subsequent operand specifiers use the
updated contents of register modified by those operations.

2-8 • VAX Architecture Overview

2. Except for those operations mentioned in step 1, all input operations are
read and all addresses of output operands are computed before any results
of the instruction are stored.
3. An operand of modify access type is not read, modified, and written as an
indivisible operation. Therefore, modify access type operands cannot be
used for synchronization. For synchronization, refer to the ADAWI,
BBCCI, BBSSI, INSQHI, INSQTI, REMQHI, and REMQTI instructions.
4. If an instruction references two operands of write or modify access type at
the same or overlapping address, the first will be overwritten by the sec¬
ond. If an instruction modifies a register implicitly and also has an output
operand, the output store is performed after the register update.
Process Control Instructions
Process scheduling software executes on the interrupt stack. This protocol
makes available a noncontext-switched stack. If the scheduler were running
on a process’s kernel stack, any state information in that stack would disap¬
pear whenever a new process is selected. Running on the interrupt stack can
occur as the result of the interrupt origin of scheduling events. Some synchro¬
nous scheduling requests (such as a WAIT service) may cause rescheduling
without any interrupt occurrence. For this reason, the save process context
(SVPCTX) instruction can be executed while on either the kernel or interrupt
stack. It forces a transition to execution on the interrupt stack.
All of the process control instructions are privileged and can be executed in
kernel mode only. Example 2-1 illustrates how the process structure instruc¬
tions can be used to implement process dispatching software. It is assumed
that this simple dispatch routine is always entered by way of an interrupt.
Example 2-1 ■ Simple Dispatch Routine
i ENTERED VIA INTERRUPT , IPL = 3

RESCHED:SVPCTX

iSaue context in PCB.

<set state to runnable and place current PCB on proper RUN queue)

<Remoue head of highest priority, nonempty, RUN queue)
MTPR GHPHYSPCB, PCBB

;Set physical PCB address in PCBB.

LDPCTX

; Load context from PCB for new process.

REI

iPlace process in execution.

2-9

■ General Register Addressing
Within the processor there are locations called general registers that can be
used for temporary data storage and addressing. Sixteen 32-bit general regis¬
ters are available for use with the native instruction set, though some have
special significance. For example, one register is designated as the program
counter, and it contains the address of the next instruction to be executed.
An instruction operand can be located in main memory, in a general register,
or in the instruction stream itself. The method by which an operand location
is specified is called the operand addressing mode. VAX processors offer a
variety of addressing modes and addressing mode optimizations: one address¬
ing mode locates an operand in a register; several other addressing modes
locate an operand in memory by using a register to point to the operand, point
to a table of operands, or point to a table of operand addresses.
Other addressing modes exist that are indexed modifications of the address¬
ing modes that locate an operand in memory. Finally, still other addressing
modes identify the location of the operand in the instruction stream, includ¬
ing one for constant data and one for branch instruction addresses. The gen¬
eral register addressing modes are briefly summarized in Table 2-1.
Table 2-1 ■ General Register Addressing Modes
Mode

Symbol

Indexed

Absolute

@#addr

[Rx]

Autodecrement

-(R n)

[Rx]

Autoincrement

(R «) +

[Rx]

Autoincrement Deferred

@(R«) +

[Rx]

Displacement—
Byte
Word
Longword

Btdispl(Rn)
mdispKRn)
Lfdispl{Rn)

[Rx]
[Rx]
[Rx]

Displacement DeferredByte
Word
Longword

@R^displ(Rn)
@yVMispl(Rn)
@Lfdispl(Rn)

[Rx]
[Rx]
[Rx]

Immediate

It# constant

Literal

St# constant

[Rx]

(R n)

[Rx]

Legend:

n = 0:15,

x = 0:14,

displ = displacement address

2-10 ■ VAX Architecture Overview

■ Data Types
The processor’s native instruction set recognizes several primary data types—
character-string, floating-point, integer, numeric-string, packed-decimal, and
variable-length bit field. For each of these data types, the selection of opera¬
tion immediately informs the processor of the size and interpretation of the
data. This is done so that the processor can then manipulate the bit field as a
function of user-defined field size and relative position from a given byte
address.
Several variations of the primary data types exist. Table 2-2 provides a sum¬
mary of all the data types available. Figure 2-2 illustrates some of them graphi¬
cally.

Table 2-2 ■ Data Types
Data Type

Size

Integer—

Range (decimal)
Signed

Unsigned

Byte

8 bits

- 128 to + 127

0 to 255

Word

16 bits

- 32768 to + 32767

0 to 65535

Longword

32 bits

-231 to +231 - 1

0 to232 - 1

Quadword

64 bits

- 263 to + 263 - 1

0 to 264 - 1

Octaword

128 bits

- 2127 to + 2127 - 1

0 to + 2128 - 1

D_floating

64 bits

approximately 16 decimal digits
precision

F_floating

32 bits

approximately 7 decimal digits
precision

G_floating

64 bits

approximately 15 decimal digits
precision

H_floating

128 bits

approximately 33 decimal digits
precision

0 to 16 bytes
(31 digits)

numeric, two digits per byte sign in
low half of last byte

Floating Point—

Packed Decimal
String

Character String 0 to 65533 bytes one character per byte
Variable-length
Bit Field

0 to 32 bits

dependent on interpretation

Numeric String

0 to 31 bytes
(digits)

- 1031 - 1 to + 1031 - 1

Queue

> 2 longwords/
queue entry

0 through 2 billion entries

2-11

WORD

BYTE

]:A

LONGWORD
31

QUADWORD
31
: A

63
OCTAWORD
31

12
96

127
F_FLOATING

D_FLOATING

FRACTION

EXPONENT

6
|

FRACTION

FRACTION
31

FRACTION
FRACTION
48

H_FLOATING

G_FLOATING

15 14

4 3

15 14
EXPONENT

FRACTION

|:A

EXPONENT
FRACTION

A + 2

FRACTION

A + 4

FRACTION

A + 6

A + 2

FRACTION

A + 8

FRACTION

A + 10

FRACTION

A + 12
A + 14

FRACTION
113

127

PACKED DECIMAL STRING ( 7
4 3
0

CHARACTER STRING (XYZ)
7
0

: A
: A + 1

A + 1
A + 2
VARIABLE-LENGTH BIT FIELD
P + S

P + S - 1

P - 1

]:A
A = ADDRESS

123)

S - 1

Figure 2-2 ■ Data-type Representations

2-12 ■ VAX Architecture Overview

The data type of an instruction operand identifies how many bits of storage
should be considered as a unit and what is to be the interpretation of that unit.
This is important because, as you will see in later sections, identical bit pat¬
terns can be interpreted as very different data items; similarly, different bit
patterns may be used to represent the same numerical value.
Character string data is a string of bytes containing any binary data, for exam¬
ple, ASCII codes. The first character in the string is stored in the first byte,
the second character is stored in the second byte, and so on. In particular, a
character string that contains ASCII codes for decimal digits is called a
numeric string.
Floating-point values are stored using a signed exponent and a binary frac¬
tion. Four types of floating-point data formats are provided. Subset implemen¬
tations of the VAX architecture may not include all four data types. Operating
system software may emulate omitted instructions and may utilize user-mode
stack space during emulation. F_floating and D_floating are 4 and 8 bytes
long, respectively. F_floating data yields approximately 7 decimal digits of
precision, while D_floating yields approximately 16 decimal digits of preci¬
sion. G_floating is also 8 bytes long. Because of the different arrangement
of the fraction and exponent parts, its precision is approximately 15 decimal
digits. However, G_ floating has a wider range of exponents. H_floating
is 16 bytes long with a 15-bit exponent and 113-bit fraction. As a result, its
precision is approximately 33 decimal digits.
Integer data is stored as binary values. An integer can be stored in a byte,
word, longword, quadword, or in an octaword. A byte is 8 bits, a word is 2
bytes, a longword is 4 bytes, a quadword is 8 bytes, and an octaword is 16
bytes. The processor can interpret an integer as either a signed value (sign is
determined by the high-order bit) or an unsigned value.
Numeric-string data is a representation of fixed quantities using 1 byte of the
string for each decimal digit. The variety of external data arrangements
demands a variety of matching numeric string forms; particularly, it is neces¬
sary to know whether the sign of the number appears in the first byte or as
part of the last byte.
Packed decimal data is stored in a string of bytes. Each byte is divided in half
forming two nibbles (4 bits = 1 nibble). One decimal digit is stored in each
nibble. The first, or most significant digit is stored in the high-order nibble of
the first byte, the second digit is stored in the low-order nibble of the first
byte, the third digit is stored in the high-order nibble of the second byte, and
so on. The sign of the number is stored in the low-order nibble of the last byte
of the string.
Variable-length bit field data is small integers packed together in a larger data
structure. Basically, they are used to increase memory efficiency.

2-13

Queue data is held in circular, doubly linked lists (that is, each entry is accom¬
panied by two longwords—one longword tells the location of the succeeding
entry, the other specifies the location of the preceding entry). Two kinds of
queue data exist—absolute queues that use absolute addresses, and relative
queues that use relative addresses.
The address of any data item is the address of the first byte in which the item
resides. All integer, floating-point, packed-decimal, and character data can be
stored starting on an arbitrary byte boundary. A bit field, however, does not
necessarily start on a byte boundary. It is simply a set of contiguous bits (0-32)
whose starting bit location is identified relative to a given byte address. The
native instruction set can interpret a bit field as a signed or unsigned integer.

■ Stacks
A stack is an array of consecutively addressed data items referenced on a lastin/first-out (LIFO) basis using a general register. Data is added to and
removed from the low address end of the stack. A stack grows toward lower
addresses as items are added and shrinks toward higher addresses as items are
removed.
A stack can be created anywhere in the program’s address space and can use
any register to point to the current item on the stack. The operating system,
however, automatically reserves portions of each process address space for
stack data structures. User software refers to its stack data structure, called
the user stack, through a general register designated as the stack pointer (SP).
When you run a program image, the operating system automatically provides
the address of the area designated for the user stack.
A stack is an extremely powerful data structure because it can be used to pass
arguments to routines. In particular, the stack structure enables the coding of
reentrant routines because the processor can handle routine linkages automati¬
cally using the stack pointer. Routines can also be recursive: arguments can be
saved on the stack for each successive call of the same routine.

■ Condition Codes
Condition codes are used to indicate the type of result produced by an instruc¬
tion. The codes are stored as bits in the processor status longword. Four condi¬
tions are coded—carry, negative, overflow, and zero.
■ Carry condition code—indicates that the last instruction had a carry out of
or a borrow from the most significant bit of the result.

2-14 ■ VAX Architecture Overview

■ Negative condition code—indicates that an instruction produced a nega¬
tive result.
■ Overflow condition code—indicates that an instruction produced a result
that could not be represented in an operand or that there was a conversion
error.
■ Zero condition code—indicates that the last instruction produced a zero
result.

■ Exceptions and Interrupts
The processor can automatically initiate changes in the normal flow of pro¬
gram execution. The processor recognizes two kinds of events that cause it to
invoke conditional software—exceptions and interrupts. Some exceptions,
for example, arithmetic traps affect an individual process only. Other excep¬
tions, for example, machine checks affect the system as a whole. Interrupts
include both device interrupts, such as those signaling I/O completion, and
software-requested interrupts, such as those signaling the need for a context
switch operation.
The processor knows which software to invoke when an exception or inter¬
rupt occurs because it references specific locations called vectors to obtain the
starting address of the exception or interrupt dispatcher. The processor has
one internal register, the system control block base register, which the operat¬
ing system loads with the physical address of the base of the system control
block, where the exception and interrupt vectors are contained. The processor
locates each vector by using a specific offset into the system control block.
Each vector tells the processor how to service the event, and contains the sys¬
tem region virtual address of the routine to execute.
To handle interrupt requests, the processor enters a special systemwide con¬
text. In the systemwide context, the processor executes in kernel mode using
a special data structure called the interrupt stack. The interrupt stack cannot
be referenced by any user-mode software because the processor selects the
interrupt stack only after an interrupt, and all interrupts are trapped through
system vectors.
The interrupt service routine executes at the interrupt priority level of the
interrupt request. When the processor receives an interrupt request at a level
higher than that of the currently executing software, the processor honors the
request and services the new interrupt at its priority level. When the inter¬
rupt service routine issues the return from exception or interrupt instruction,
the processor returns control to the previous level.

2-15

■ Input/output Control
An I/O device controller has a set of control/status and data registers. The reg¬
isters are assigned addresses in physical address space, and their physical
addresses are mapped, and thus protected, by the operating system’s memory
management software. That portion of physical address space in which device
controller registers are located is called I/O space.
No special processor instructions are needed to reference I/O space. The regis¬
ters are simply treated as locations containing integer data. An I/O device
driver issues commands to the peripheral controller by writing to the control¬
ler’s registers as if they were physical memory locations. Software reads the
registers to obtain the controller status. The driver controls interrupt
enabling and disabling on the set of controllers for which it is responsible. If
interrupts are enabled, an interrupt occurs when the controller requests it.
The processor accepts the interrupt request and executes the driver’s inter¬
rupt service routine if it is not currently executing on a higher-priority inter¬
rupt level.

Chapter 3 ■ VAX Architecture Characteristics

The VAX architecture defines a functional behavior that is consistent through¬
out the family of VAX processors. From a programming point of view, the user
environment is consistent. Characteristics of this consistency include sharing
address space, sharing data, register usage, memory usage, restartability, inter¬
rupts and errors, and I/O structure.

■ Programming Environment
Within the context of any one process, user-level software controls its execu¬
tion using the instruction sets, the general registers, and the processor status
word. Within the multiprogramming environment, the operating system con¬
trols the system’s execution using a set of' special instructions, the processor
status longword, and the processor registers.
Processor Status Longword
A processor register called the processor status longword (PSL) determines the
execution state of the processor at any time. The low-order 16 bits of the PSL
are the processor status word (PSW) that is available to the user process. The
high-order 16 bits provide privileged control of the system.
The PSL fields can be grouped by functions that control
■ The access mode of the current instruction.
■ The instruction set in execution.
■ Interrupt processing.

Processor Access Modes
In a multiprogramming system, the processor must provide protection and
sharing for the processes competing for system resources. The mechanism for
protection in this system is the processor’s access mode. The access mode is
responsible for determining the
■ Instruction execution privileges (which instructions the processor will exe¬
cute).
■ Memory access privileges (which locations in memory the current instruc¬
tion can access).

3-2 ■ VAX Architecture Characteristics

The processor executes code either in an interrupt context or in process con¬
text. In the interrupt context, all normal processing is halted until the inter¬
rupt is serviced. In the process context, the processor operates in one of four
modes—kernel, executive, supervisor, and user. Kernel is the most privileged
mode and user is the least privileged.
The processor executes in user mode in one process context or another. When
a user process needs privileged services, it calls for those services. Then the
processor executes the services either in the process’s access mode or, tempo¬
rarily under operating system control, in a more privileged mode. Only in ker¬
nel mode can the processor
■ Execute an instruction that halts the processor.
■ Load and save process context or access the internal processor registers con¬
trolling memory management.
■ Access privileged processor registers.

The ability to execute code in a higher-privileged mode is controlled by the
operating system. In general, code executing in one mode can protect itself
and any portion of its data structures from read and/or write access by code
executing in a less privileged mode.
Special Instructions
The VAX instruction set contains instructions that enable user-mode software
to obtain privileged services without jeopardizing the integrity of the operat¬
ing system. They are
■ Change mode instructions (CHMK, CHME, CHMS, CHMU).
■ PROBE instructions.
■ Return from exception or interrupt (REI) instruction.

User-mode software can obtain privileged services with a standard call
instruction. The operating system’s service dispatcher issues an appropriate
change mode instruction before actually entering the procedure. A change
mode instruction is a special trap instruction similar to a service call instruc¬
tion.
The PROBE instructions enable a procedure to check the read (PROBER) and
write (PROBEW) access protection against the privileges of the caller who
requested access to a particular location. This makes the operating system pro¬
vide services that execute in privileged modes to less privileged callers while
preventing the caller from accessing protected areas of memory.

3-3

The operating system’s privileged service procedures and interrupt and excep¬
tion service routines exit using the REI instruction. The instruction is the only
way to decrease the privilege of the processor’s access mode. An REI instruc¬
tion restores both the program counter and the processor state. This ensures
the interrupted process’s execution resumes at the point where it was inter¬
rupted.
When the operating system schedules a context switch, the context switching
procedure uses the save process context (SVPCTX) and load process context
(LDPCTX) instructions. The operating system’s context switching procedure
locates the hardware context to be loaded by updating a processor register.
Data Sharing
Data or instructions may be shared among various entities including pro¬
grams, processors, and I/O devices. Entities sharing data may do so explicitly
by referencing the same data or implicitly by referencing different items
within the same physical memory location.
In VAX architecture, implicit sharing is transparent to the programmer. The
memory system is implemented so the mechanism of access for independent
modification is the byte. Not that this does not imply a maximum reference
size of one byte but only that independent modifying accesses to adjacent
bytes produce the same results regardless of the order of execution. For exam¬
ple, locations 0 and 1 contain the values 3 and 6, respectively. One process
executes an INCB 0 instruction (increment by 1 the byte at location 0) and
another executes an INCB 1 instruction. Regardless of the order of execution
(including effectively simultaneous execution) the final contents must be 6
and 7.
Data Access Synchronization
Access to explicitly shared data that may be written must be synchronized.
Before accessing shared writable data, the programmer must acquire control
of the data structure. Seven instructions are provided to permit interlocked
access to a control variable.
■ The branch on bit set and set, interlocked (BBSSI) and branch on bit clear
and clear, interlocked (BBCCI) instructions make a read and a subsequent
write reference to a single bit within a single byte in an interlocked
sequence.
■ The add aligned word, interlocked (ADAWI) instruction makes a read and a
subsequent write operation to a single aligned word in an interlocked
sequence to allow counters to be maintained without other interlocks.

3-4 ■ VAX Architecture Characteristics

■ The insert at queue head, interlocked (INSQHI), insert at queue tail, inter¬
locked (INSQTI), remove from queue head, interlocked (REMQHI), and
remove from queue tail, interlocked (REMQTI) instructions make a series
of aligned longword reads and writes in an interlocked method to allow
queues to be maintained without other interlocks.

Use of these instructions guarantees that no read operation within the synchro¬
nizing part of these instructions can occur between the synchronized reads
and the writes of the instructions. Such instructions are implemented so that
faults cannot cause the data structure to be locked for an extended period. On
the processor, only interlocking instructions are locked out by the interlock.

■ Registers
VAX processors contain three types of registers used during execution—gen¬
eral registers, processor registers, and input/output registers. The general reg¬
isters are used as counters and pointers, and some are available for use by
programmers. Processor registers perform system functions and normally are
not used for other purposes. The input/output registers function in the con¬
trol and status reporting of peripheral devices.
General Registers
VAX provides sixteen general registers for temporary storage of addresses and
data. General registers are identified as R« where n is an integer in the range
0 through 15. These registers do not have memory addresses. They are
accessed either explicitly by specifying the register number in an instruction
operand specifier, or implicitly by machine operations that automatically refer¬
ence specific registers. Certain registers have specific uses and special names.
■ Register R15—is the program counter (PC). The processor updates the reg¬
ister to address the next byte of the program. The PC is not used as a tem¬
porary, accumulator, or index register.
■ Register R14—is the stack pointer (SP). Several instructions make implicit
references to the SP. Most software assumes that the SP points to memory
set aside for use as a stack. There is no restriction on the explicit use of
other registers (except PC) as stack pointers. Those instructions that make
implicit references to the stack always use the SP.

3-5

■ Register R13—is the frame pointer (FP). The VAX procedure call conven¬
tion builds a data structure called a stack frame on the stack. The call
instructions load the FP with the base address of the stack frame, and the
return instruction depends on the FP containing the address of a stack
frame. Further, VAX software depends on maintenance of the FP for cor¬
rect reporting of certain exceptional conditions.
■ Register R12—is the argument pointer (AP). The VAX procedure call con¬
vention uses a data structure called an argument list. The conventions need
the AP as the base address of the argument list. Call instructions load the
AP in accordance with that convention. There is no hardware or software
restriction on the use of the AP for other purposes.
■ Registers R6 through Rll—these registers have no special significance to
either the hardware or the operating system. Specific software assigns uses
for each register.
■ Registers R5 through RO—these registers are available for any use by soft¬
ware. But, they are also loaded with specific values by those instructions
whose execution must be interruptible — the character string, decimal
arithmetic, cyclic redundancy check, and polynomial instructions. The spe¬
cific instruction descriptions identify which registers are used and what
values are loaded into them.

The general philosophy of register allocation is high-numbered registers have
the most global significance, low-numbered registers are used for the most
temporary, local purposes. While there is no technical basis for this rule, it is
a matter of convention followed by both hardware and system software. Thus,
high-numbered registers are used for pointers needed by all software and hard¬
ware, and low-numbered registers are used for the working storage of stringtype instructions. Similarly, the VAX procedure call software convention
regards registers RO and R1 as so temporary that they are not saved on calls.
This is because RO and R1 are used to return function values. Table 3-1 lists
the use of general registers.

3-6 • VAX Architecture Characteristics

Table 3-1 ■ General Register Usage
Registers

Hardware Use

Conventional Software Use

PC (R15)

Program counter

SP (R14)

Stack pointer

FP (R13)

Frame pointer saved
and loaded by CALL,
used and restored by
RET instruction

Frame pointer; condition signaling

AP (R12)

Argument pointer
saved and loaded by
CALL, restored by
RET instruction

Argument pointer (base address of
argument list)

R6:R11

None

Any

R3,R5

Any
Address counter in
character and decimal
instructions

R2,R4

Length counter in char- Any
acter and decimal
instructions

Result of POLYD
instruction; address
counter in character
and decimal instruc¬
tions

Results of POLY, CRC Results of functions, status of services
instructions; length
(not saved or restored on procedure
counter in character
call)
and decimal instruc¬
tions

Result of functions (not saved or
restored on procedure call)

A reference to the stack pointer (SP) can access one of five general stack
pointers—executive, interrupt, kernel, supervisor, or user stack pointers
depending on certain conditions. The conditions are the values of the current
mode and interrupt stack bits in the processor status longword. Also, the move
to processor register (MTPR) and move from processor register (MFPR) instruc¬
tions can access those stack pointers including the currently selected stack
pointer. This is also true for those processors whose executive, kernel, supervi¬
sor, and user stack pointers reside in the process control block PCB only.

3-7

Processor Registers
Processor registers reside in the processor register space. They are sometimes
called internal registers or privileged registers. These registers perform control
and status functions. They are accessible through the MTPR and MFPR
instructions. These instructions can be invoked from the kernel mode only.
Context switching is the act of suspending an executing process and starting
the execution of another. With the exception of the memory mapping and
asynchronous system trap registers, processor registers are loaded from the
processor control block (PCB) during a context load operation. During a con¬
text save operation, the registers are written to the PCB. In some VAX proces¬
sors, scratchpad registers are used as an intermediate step in the read/write
operation.
Depending on the model of processor, accessing processor registers using the
MTPR and MTFR instructions may render invalid data. In some VAX proces¬
sors, all or some of the processor registers reside in the PCB only. In those
processors, the MTPR and MTFR instructions must be directed to the corre¬
sponding PCB location. VAX processors with processor registers in hardware
scratchpads need not access the corresponding PCB locations.
■ Clock Registers
There are two clocks in VAX processors: a time-of-year clock and an interval
clock. The time-of-year clock register is used to measure the duration of
power failures and is needed for unattended restart after a power failure. The
interval clock is used for accounting, time-dependent events, and to maintain
the date and time.
Time-of-year Clock The time-of-year clock is a longword register. It forms an
unsigned 32-bit binary counter that is driven by a precision clock source. The
clock operates at a minimum accuracy of 0.0025 percent. After approximately
497 days, the clock cycles to zero. As an option, the register can have an emer¬
gency power supply. The power supply may contain a battery that can operate
for several hours. The register does not gain or lose time during the transition
to or from the emergency power supply. The battery is usually automatically
recharged.
Should the battery fail and the clocking is not accurate, the register is cleared
after power is applied. Then the clock is started.
Interval Clock The interval clock provides an interrupt at programmed inter¬
vals. The counter is incremented at microsecond intervals with a minimum
accuracy of 0.01 percent. The clock interface consists of three registers — the
interval count register (ICR), the next interval count register (NICR), and the
interval clock control/status register (ICSS).

3-8 • VAX Architecture Characteristics

The interval count register is a read-only register that is incremented every
microsecond. It is automatically loaded from the next interval count register.
If the interrupt is enabled, an interrupt is initiated when the interval count
register is loaded.
The next interval count register is a write-only device that holds the value to
be loaded into the interval count register when it overflows. The value is
retained when the interval count register is loaded. The next interval count
register is capable of being loaded regardless of the current values of the other
two registers.
The interval clock control/status register contains control and status informa¬
tion for the interval clock. The register contains the following bits:
■ Run bit—when the run bit is set, the interval count register increments
each microsecond. When the bit is reset (0), the interval count register
does not increment. During bootstrap procedures, the run bit is cleared.
■ Transfer bit (XFR)—is a write-only bit. The next interval count register is
transferred to the interval count register when this bit is set.
■ Signal bit (SGL)—is a write-only bit. If the run bit is reset (0), the interval
count register is incremented by one each time this bit is set.
■ Software interrupt request (IE) bit—when this bit is set and the interval
count register overflows, an interrupt request is generated. When this bit
is reset, no interrupt is requested. If the hardware interrupt request bit is
set and then this bit is set, an interrupt is requested.
■ Hardware interrupt request (INT) bit—this bit is set by hardware when¬
ever the interrupt count register overflows. If the IE bit is set and this bit is
set, an interrupt is requested. If this bit is reset with a MTPR instruction,
the clock tick interrupt is enabled.
■ Error (ERR) bit—Whenever the interval count register overflows and the
INT bit is set, this bit is set. This bit indicates that a clock tick was missed.
This bit is cleared by a MTPR instruction.

NOTE
Subset processors may omit the interval count and next inter¬
val count registers. These processors are required to imple¬
ment the software interrupt (IE) bit of the interval clock
control/status register. If this bit is set, an interrupt request
is generated every 10 milliseconds.

3-9

The interval clock is set by loading the negative of the desired interval into
the NIC register. Then invoking an MTPR instruction enables interrupts,
loads the interval count register with the interval stored in the next interval
count register, and the run bit is set. Every interval count microsecond sets the
INT bit and invokes an interrupt request. The interrupt routine should exe¬
cute an MTPR instruction to clear the interrupt. If the INT bit is not reset by
the next interval count register overflow, the err bit is set.
■ Console Terminal Registers
The console terminal is accessed through four processor registers. Two regis¬
ters are used for reception and two are used for transmission. There are con¬
trol/status registers and data buffer registers for both reception and
transmission. A status byte is used to determine the success or failure of a
read or write operation. The status byte is transmitted to the operating system
on completion of every read, write, or read status operation.
Receive Registers During bootstrap procedures, the console receive control/
status register is initialized to zero. Whenever data is received, the done bit is
set by the console. If the register’s interrupt enable bit is set, an interrupt is
requested. If the done bit is set and the software sets the interrupt enable bit,
an interrupt is requested. If the data received contained an error, the error bit
of the console receive data buffer register is set. The data received is stored in
the data field of the register. When a MFPR instruction is executed, the done
bit is reset. If the value in the ID field of the console receive data buffer regis¬
ter is zero, the data is from the console terminal. If the value of the ID field is
other than zero, the entire register is implementation-dependent.
Transmit Registers During bootstrap procedures, the console transmit controlj
status register is initialized with all the bits reset except for the ready (RDY)
bit which is set. Whenever the console transmitter is not busy, it sets the
ready bit. And if the register’s interrupt enable bit is set, an interrupt is
requested. Also, if the ready bit is set, then the interrupt enable bit is set, an
interrupt is requested. The software can send data by writing it to DATA.
When an MTPR instruction is executed with the transmit data buffer as the
destination operand, the ready bit is cleared. If the ID bit is zero, the data is
sent to the console terminal. If the ID bit is set, the entire register is implemen¬
tation-dependent .
■ Process Control Block Base Register
The process control block base (PCBB) register is an internal privileged regis¬
ter containing the physical longword address of the process control block
(PCB). The process control block contains the switchable process context. The
context is collected into a compact form for ease of movement to and from the
privileged registers.

3-10 ■ VAX Architecture Characteristics

In most operating systems, there is additional software context for each pro¬
cess. However, the following description is limited to the hardware process
control block. See Figure 3-1 for an illustration of the process control block.
Table 3-2 contains a description of the process control block longwords.

BIT

KERNEL MODE STACK POINTER

EXECUTIVE MODE STACK POINTER

SUPERVISOR MODE STACK POINTER

USER MODE STACK POINTER

ARGUMENT POINTER

FRAME POINTER

PROGRAM COUNTER

PROCESSOR STATUS LONGWORD
PROGRAM REGION BASE REGISTER

20
1

PROGRAM REGION LENGTH REGISTER
CONTROL REGION BASE REGISTER

22
2

CONTROL REGION BASE REGISTER

3222222
1
7 6
4 3 2 1

NOTES:
1. Asynchronous Trap Pending Field
2. Enable Performance Monitor Field

Figure 3-1 ■ Hardware Process Control Block

0
0

3-11

Table 3-2 ■ Process Control Block Definition
Longword

Bits

Mnemonic

Description

31:0

KSP

Kernel Stack Pointer. Contains the stack
pointer to be used when the value of the current access mode field in the processor
status longword (PSL) is 0 and interrupt
stack (IS) is 0.

31:0

ESP

Executive Stack Pointer. Contains the stack
pointer to be used when the value of the cur¬
rent access mode field in the PSL is 1.

31:0

SSP

Supervisor Stack Pointer. Contains the
stack pointer to be used when the value of
the current access mode field in the PSL
is 2.

31:0

USP

User Stack Pointer. Contains the stack
pointer to be used when the value of the cur¬
rent access mode field in the PSL is 3.

4:17

31:0

R0:R11,
AP, FP

General registers 0 through 11, argument
pointer, and frame pointer.

31:0

Program counter

31:0

PSL

Processor status longword

31:0

P0BR

Base register for the page table describing
the process virtual addresses from 0

21:0

P0LR

Length register for the page table located by
base register P0. Describes the effective len¬
gth of the page table.

23:22

MBZ

Must be zero (0)

26:24

ASTLVL

Contains the access mode number estab¬
lished by software of the most privileged
access mode for which an asynchronous sys¬
tem trap is pending. Controls the triggering
of the asynchronous system trap delivery
interrupt during return from exception or
interrupt instructions.

through 1,073,741,823 (decimal) (230 - 1).

3-12 ■ VAX Architecture Characteristics

Table 3-2 ■ Process Control Block Definition (Cont.)
Long¬
word

Bits

Mnemonic

Description

ASTLVL
Field

Asynchronous system trap
pending for access mode:

0 (kernel)

1 (executive)

2 (supervisor)

3 (user)

No traps pending

5:7

Reserved

31:27

MBZ

Must be zero (0)

31:0

P1BR

Base register for the page table. Describes
the process virtual addresses from
1,073,741,824 through 2,147,483,647
(230 through 231 - 1).

21:0

P1LR

Length register for the page table.
Located by base register PI. Describes
the effective length of the page table.

30:22

MBZ

Must be zero (0)

PME

Performance Monitor Enable. Controls a
signal visible to an external hardware per¬
formance monitor. This bit is set to iden¬
tify those processes for which monitoring
is desired, and to permit their behavior to
be observed without interference from
other system activity
NOTE

Software symbols are defined for these locations by using the
prefix PTX$L and the mnemonics shown above. The prefix
and mnemonic must be separated by an underscore character.
For example, should you wish to specify the supervisor stack
pointer register, the software symbol is: PTX$L_SSP.
There are two exceptions to this symbology: longwords 21
and 23. The symbols for those words are:
PXT$L_POLRASTL (longword 21)
PTX$L_P1LRME (longword 23)

3-13

A process must be executing in one particular mode to alter its context switch¬
ing fields. First the process stores the new value in the memory image of the
process control block. Then it moves the value to the appropriate privileged
register. This protocol is used because the process control block context
switching fields are read-only fields. The context switching fields are POBR,
P1BR, POLR, P1LR, ASTLVL, and PME.
NOTE
The ASTLVL and PME fields of the process control block are
in registers when the process is executing. In order to access
the fields, two privileged registers are provided. These are
the AST Level register and the Performance Monitor Enable
(PME) register.
■ System Identification Register
The system identification (SID) register is a read-only device that specifies the
processor type. The entire register is included in the error log and the type
field may be used by software to distinguish processor types. The register is
divided into two fields—type and type specific. The type field identifies the
model of the processor. The type specific field varies among the models but
contains specific identification for that model.
Input/Output Registers
Input/output registers are also known as peripheral device control/status and
data registers. These registers are in the physical address space. They can be
manipulated by memory reference instructions. Use of general instructions
permits virtual address mapping and protection mechanisms to be used when
referencing I/O registers. An area of the I/O physical address space maps
through to the UNIBUS addresses. This area is called the UNIBUS space. I/O
registers satisfy the following conditions:
■ All registers must be aligned on natural boundaries.
■ The physical address of an I/O register must always be an integral multiple
of the register size in bytes (which must be a power of 2).
■ References using a length attribute other than the length of the register
and/or an unaligned reference may produce unpredictable results. For exam¬
ple, a byte reference to a wordlength register will not necessarily respond
by supplying or modifying the byte addressed.

3-14 • VAX Architecture Characteristics

■ In peripheral devices, error and status bits that may be asynchronously set
by the device are usually cleared by software writing a one to these bits,
and are not affected by writing a zero. This is to prevent resetting bits that
may be asynchronously set between reading and writing a register.
■ Only byte and word references of a read-modify-write type in UNIBUS I/O
spaces are guaranteed to interlock correctly. References in the I/O space
other than in UNIBUS spaces are undefined with respect to interlocking.
This includes the BBSSI and BBCCI instructions.
■ String, quad word, octaword, F_floating, D_floating, G_floating,
H_floating, and field references in the I/O space result in undefined
behavior.

■ Stacks
Stacks are also called pushdown lists or last-in I first-out (LIFO) queues. They
are an important feature of the architecture. They are used to perform various
functions; for example, to
■ Save the general registers including the program counter at entry to a sub¬
routine for restoration at exit.
■ Save the program counter, processor status longword, and general registers
at the time of interrupts and exceptions, and during context switches.
■ Create storage space for temporary use or for nesting of recursive routines.

A stack is implemented in a VAX processor by a block of memory and a general
register that addresses the top of the stack. The top of the stack is that loca¬
tion in the block containing the next candidate for removal. An item is added
to the stack (pushed on) by decrementing the stack pointer register and stor¬
ing the item at the address in the updated register. The pointer is decre¬
mented by the length of the item added to the stack to allow enough room for
it. Conversely, the top item is removed (popped off) by adding the length of
the item to the stack pointer after the last use of the item. These operations
are built into the basic addressing mechanisms of VAX instructions. Thus any
instruction can operate on the stack; it is seldom necessary to devote separate
instructions to maintain the stack pointer.
There are two common programming errors associated with stacks: (1) adding
more data than there is space to store, and (2) removing more data than was
added. In order to catch those common programming errors, a stack is usually
bound by inaccessible pages. By placing the stack in a block of memory
between inaccessible pages, the programmer can be confident of finding such
errors. The operating system initializes the stacks this way.

3-15

Many VAX processor operations make use of the stack implicitly; that is, with¬
out specifying the stack pointer in an operand. This occurs in instructions
used in calling and returning from subroutines and in the processor sequences
that initiate and terminate interrupt or exception service routines. In all such
cases, the processor uses the stack addressed by R14.
This does not mean that exceptions, interrupts, and system services are per¬
formed on the same stacks employed by user-mode programs. The processor
maintains five internal registers as pointers to separate blocks of memory to
be used as stacks and uses one or another as a stack pointer depending on cer¬
tain bits in the processor status longword. Whenever those bits change, the
processor saves the stack pointer in a register selected by the old value of
those bits. Then the processor loads the stack pointer from the register
selected by the new value of these bits. There is one interrupt stack for the
entire system. But the kernel, executive, supervisor, and user stacks are differ¬
ent for each process in the system. Figure 3-2 illustrates the relationships of
the five stacks and multiple processes.

GREATER
MODE
(LESSER
PRIVILEGE)

PROCESS 1

PROCESS 2

PROCESS 3

USER 1
STACK

USER 2
STACK

USER 3
STACK

SUPERVISOR 1

SUPERVISOR 2
STACK

SUPERVISOR 3
STACK

EXECUTIVE 1
STACK

EXECUTIVE 2
STACK

EXECUTIVE 3
STACK

KERNEL 1
STACK

KERNEL 2
STACK

KERNEL 3
STACK

STACK
_

INTERRUPT STACK
(ALL PROCESSES)

Figure 3-2 ■ Stacks by Mode versus Processes

3-16 * VAX Architecture Characteristics

This multiple-stack mechanism offers a number of advantages over a single¬
stack mechanism:
■ User programs are not subject to sudden and nonreproducible changes in
the data beyond the end of their stack. While it is bad practice to depend
on such data, it would also be poor design to make it difficult to debug pro¬
grams that did.
■ The integrity of a privileged mode program cannot be compromised by a
less privileged caller. Even if the caller has completely filled its own stack,
the privileged code is in no danger of running out of space. Separate blocks
of memory are allocated to the stack associated with each mode to prevent
that situation.
■ Privileged mode programs are not vulnerable to accidental or malicious
destruction of the stack pointer by less privileged programs. Even if the
user program uses the stack pointer as a floating-point accumulator, privi¬
leged code can use it as a stack pointer. To accomplish this, the processor
saves the floating-point value and loads the pointer value when a mode
change occurs.
■ By allocating separate stacks for each mode, VAX processors can page most
stack space dynamically while ensuring the availability of space for inter¬
rupt and page fault service. Interrupt service routines and the page fault
handler may be invoked at any time and must have a small amount of stack
available immediately without waiting for it to be paged in. Conversely,
user programs may need very large stack spaces making it desirable to swap
out those regions not in use. Only the kernel and interrupt stacks need be
resident.

■ Cache Memory
Cache memory or cache is a mechanism that reduces access time by making
copies of recently used memory. In VAX family processors, the cache is imple¬
mented in such a way that it is transparent to software except for timing and
error reporting/control. In cache, the following protocol is observed:
■ Program writes to memory—followed by a peripheral output transfer—
result in the output of the updated value.
■ A peripheral input transfer—followed by a program reading of memory—
results in a read of the input value.

3-17

■ A write or modify operation—followed by a halt on one processor—fol¬
lowed by a read or modify operation on another processor—results in a
read of the updated value. (Note that this applies only to customerdesigned multiprocessor systems.)
■ A write or modify operation—followed by a power failure — followed by
restoration of power—followed by a read or modify operation—results in a
read of the updated value. This occurs only if the duration of the power
failure does not exceed the maximum nonvolatile period of the main mem¬
ory or if the contents of memory were protected by an optional batteryoperated emergency power supply.
■ In multiprocessor systems, access to variables shared among processors can
be interlocked by software executing interlocking instructions (ADAWI,
BBCCI, BBSSI, INSQHI, INSQTI, REMQHI, or REMQTI). In particular,
the write device must execute an interlocking instruction after the write to
release the interlock and the read device must execute a successful match¬
ing interlock instruction before the read.

■ Accesses to I/O registers are not loaded into the cache.

■ Restartability
VAX architecture requires that all instructions be restartable after a fault or

interrupt that terminated execution before the instruction was completed.
Generally, this means that modified registers are restored to the value they
had at the start of execution. For some complex or iterative instructions, inter¬
mediate results are stored in the general registers. In this case, memory may
have been altered, but the former case requires that no operand be written
unless the instruction can be completed. For most instructions with only a sin¬
gle modified or written operand, this implies special processing only when a
multibyte operand spans a protection boundary. Spanning the boundary
makes necessary the testing of the accessibility of both parts of the operand.
Instructions that store intermediate results in general registers do not compro¬
mise system integrity. They ensure that any addresses stored or used are vir¬
tual addresses subject to protection checking. Furthermore, they ensure that
any state information stored or used does not result in a sequence that cannot
be interrupted or terminated.

3-18 ■ VAX Architecture Characteristics

Instruction operands that are peripheral device registers having access side
effects may produce unpredictable results due to the instruction restarting
after faults (including page faults) or interrupts. To ensure no interrupts, pro¬
grammers must avoid operand specifier addressing modes 9, 11, 13, and 15,
and the indexed forms of these modes. (Refer to Chapter 5 for details of
addressing modes.) However, the hardware may allow interrupts for these
modes in order to minimize interrupt latency.
Memory modifications are produced as a by-product of instruction execution;
for example, memory access statistics. These modifications are specifically
excluded from the constraint that memory may not be altered until the instruc¬
tion can be completed. Instructions that abort are constrained only to ensure
memory protection; for example, the registers can be changed.

■ Interrupts and Errors
Underlying the VAX architectural concept of an interrupt is the notion that an
interrupt request is a static condition—not a transient event—and can be sam¬
pled by a processor at appropriate times. Further, if an interrupt is no longer
needed before a processor has honored that interrupt request, the interrupt
request can be removed without consequence. Any instruction that changes
the processor’s interrupt priority level to enable a pending interrupt allows
the interrupt to occur before executing the next instruction. Similarly, if pro¬
cessor priority permits, instructions that generate requests at the software
interrupt levels allow the interrupt to occur before executing the next instruc¬
tion.
Processor errors that are consistent with instruction completion create highpriority interrupt requests. Otherwise, they terminate instruction execution
with an exception. Error notification interrupts may be delayed from the
apparent completion of the executing instruction at the time of the error. But,
if enabled, the interrupt is requested before processor context is switched.

Chapter 4 ■ Data Representation

VAX instructions use a variety of types of data. The data must be presented in
a form that is acceptable to the instructions. The acceptable forms are
described in the ensuing paragraphs. They are
■ Character string data
■ Floating-point data
■ Integer data
■ Numeric string data
—

■ Packed decimal data
■ Queue data
■ Variable length bit field data
—
'

NOTE
In the following discussions of floating-point and integer
data, the address of the data in memory is the address of the
byte of the data with the lowest address. In illustrations, this
lowest byte is shown on the right (bits 0 through 7). In text,
when the word right is used to describe the position of a byte,
the lowest byte is the byte being discussed.

■ Character String Data
Character strings are used to represent names, data records, or text. The
instructions allow you to copy, search, concatenate, and translate strings. A
character string is a contiguous sequence of bytes in memory and is specified
by two attributes—the address (A) of the first byte of the string, and the len¬
gth (L) of the string in bytes. The length of a string is in the range 0 through
65,535. A string with a length of 0 is called a null string. Null strings have no
bytes. No memory is referenced; hence, the address need not be valid. The
format of a character string is illustrated in Figure 4-1. The address of a string
specifies the first character of a string as shown in Figure 4-2.

4-2 ■ Data Representation

I
: A

: A + L - 1

Figure 4-1 ■ Character String Format

0
A
A + 1
A + 2

Figwre 4-2 ■ Character String Address

■ Floating-point Data
The VAX instruction set supports floating-point data in longwords, quadwords, and octawords. Four types of floating-point data are available. Two
types are eight bytes long (D_floating and G_floating), one type is four
bytes long (F_floating), and the last is sixteen bytes long (H_floating).
NOTE
An exponent value of zero with a sign bit that is zero is taken
as reserved.

D_floating Data
D

floating data is sometimes called double floating or double-precision float¬

ing. It is eight contiguous bytes starting on an arbitrary byte boundary. The
bits are labeled from the right starting with 0 and terminating with 63 as
shown in Figure 4-3.

4-3

D_floating data is specified by the address of the byte containing the first
bit. The form of D_floating data is identical to F_floating data except for
an additional 32 low-significance fraction bits. Within the fraction, bits
increase in significance from 48 through 63, 32 through 47, 16 through 31,
and 0 through 6. This is illustrated by the widening arrow in Figure 4-3. The
8-bit exponent field encodes the values 0 through 255. An exponent value of
0 with a sign bit of 0 indicates the data has a value of zero. Exponent values of
1 through 255 indicates true binary exponents of -127 through +127. Float¬
ing-point instructions processing a reserved operand take a reserved operand
fault. The values of D_floating data are in the approximate range 0.29 x
10'38 through 1.7 x 1038. The precision is approximately one part in 255 or
16 decimal digits.

0
: A
: A + 2
: A + 4
: A + 6

Figure 4-3 ■ D_floating Data Format

F_floating Data
F_floating data is sometimes called floating or single-precision floating and is
four contiguous bytes starting on an arbitrary byte boundary. The bits are
labeled from the right starting at 0 and terminating with 31 as shown in Fig¬
ure 4-4.

i
5
S

i
4

7
EXPONENT

0
FRACTION

FRACTION
31

Figure 4-4 ■ F_floating Data Format

4-4 ■ Data Representation

F_floating data is specified by the address of the byte containing the first
bit. The form of F_floating data is sign magnitude with bit 15 as the sign
bit, bits 7 through 14 express an excess 128 binary exponent, and bits 0
through 6 and 16 through 31 are a normalized 24-bit fraction with the redun¬
dant most significant fraction bit not represented. Within the fraction, bits
increase in significance from 16 through 31 and 0 through 6. The 8-bit expo¬
nent field encodes the values 0 through 255. An exponent value of 0 with a
sign bit of 0 indicates the data has a value of zero. Exponent values of 1
through 255 indicates true binary exponents of -127 through + 127. Floating
point instructions processing a reserved operand take a reserved operand
fault. The values of F_floating data are in the approximate range 0.29 x
10'38 through 1.7 x 1038. The precision is approximately one part in 223, or
approximately seven decimal digits.
G_floating Data
G_floating data is eight contiguous bytes starting on an arbitrary byte
boundary. The bits are labeled from the right starting with 0 and ending with
63 as shown in Figure 4-5.
The form of G_floating data is sign magnitude with bit 15 as the sign bit,
bits 4 through 14 expressing an excess 1024 binary exponent, and bits 0
through 3 and 16 through 63 expressing a normalized 5 3-bit fraction with the
redundant most significant fraction bit not represented. Within the fraction,
bits increase in significance from 48 through 63, 32 through 47, 16 through
31, and 0 through 3. The 11-bit exponent field encodes the values 0 through
2047. An exponent value of 0 with a sign bit of 0 indicates the data has a value
of zero. Exponent values of 1 through 2047 indicate true binary exponents of
-1023 through + 1023. Floating-point instructions processing a reserved
operand take a reserved operand fault.
The value of G_floating data is in the appropriate range of 0.56 x 10'308
through 0.9 x 10308. The precision is approximately one part in 252 or fifteen
decimal digits.

4-5

4_3
EXPONENT

FRACTION

: A

FRACTION

: A + 2

FRACTION

: A + 4

FRACTION

: A + 6
48

Figure 4-5 ■ G_floating Data Format
H_floating Data
H_floating data is sixteen contiguous bytes starting on an arbitrary byte
boundary. The bits are labeled from the right starting with 0 and ending with
127 as shown in Figure 4-6. H_floating data is specified by the address of
the byte containing the first bit.
The form of H_floating data is sign magnitude with bit 15 as the sign bit,
bits 0 through 14 express an excess 16384 binary exponent, and bits 16
through 127 express a normalized 113-bit fraction with the redundant most
significant fraction bit not represented. Within the fraction, bits increase in
significance from 112 through 127, 96 through 111, 80 through 95, 64
through 79, 48 through 63, 32 through 47, and 16 through 31. The 15-bit
exponent field encodes the values 0 through 32,767. An exponent value of 0
with a sign bit of 0 indicates that the data has a value of zero. Exponent
values of 1 through 32,767 indicate true binary exponents of -16,383
through + 16,383. Floating-point instructions processing a reserved operand
take a reserved operand fault.
The value of H_floating data is in the approximate range 0.84 x 10 4932
through 0.59 x 104932. The precision is approximately one part in 2112 or
thirty-three decimal digits.

4-6 ■ Data Representation

1
A
A + 2
A + 4
A + 6
A + 8
A + 10
A + 12
A + 14

Figure 4-6 ■ H_floating Data Format

■ Integer Data
VAX systems support integer data in 8-bit bytes, 16-bit words, 32-bit longwords, 64-bit quadwords, and 128-bit octawords. Integer data is stored in a
binary format that can be signed or unsigned. As unsigned quantities, inte¬
gers increment from 0. As signed quantities, the integers are represented in
two’s complement form. This means that positive numbers have a zero for the
most significant bit (MSB); and the representation of a negative number is one
greater than the bit-by-bit complement of its positive counterpart. Thus the
MSB is always zero for positive values and one for negative values.

4-7

Byte Data
A byte is eight contiguous bits starting on an addressable byte boundary. The
bits are numbered from the right starting with 0 as shown in Figure 4-7. The
byte is specified by its address. When interpreted arithmetically, a byte is a
two’s complement integer with bits increasing in significance from 0 through
6 and with bit 7 designating the sign. The value of the integer is in the range
of -128 through 127. For addition, subtraction, or comparison, VAX instruc¬
tions provide direct support for interpreting a byte as an unsigned integer
with bits of increasing significance starting at bit 0 and increasing to bit 7.
The value of the unsigned integer is in the range of 0 through 255.

7_0
: A

Figure 4-7 ■ Byte Data Format
Word Data
A word is two contiguous bytes and starts on an arbitrary byte boundary. The
bits are numbered from the right starting with 0 as shown in Figure 4-8.
Words are specified by their address which is the address of the byte contain¬
ing the first bit. When interpreted arithmetically, a word is a two’s comple¬
ment integer with bits increasing in significance from 0 through 14, and bit
15 designating the sign. The value of the integer is in the range -32,768
through 32,767. For addition, subtraction, and comparison, VAX instructions
provide direct support for interpreting a word as an unsigned integer with
bits increasing in significance from bit 0 to bit 15. The value of an unsigned
integer is in the range of 0 through 65,535.

Figure 4-8 ■ Word Data Format

4-8 • Data Representation

Longword Data
A longword is four contiguous bytes starting on an arbitrary byte boundary.
The bits are numbered from the right starting with 0 as shown in Figure 4-9.
A longword is specified by its address that is the address of the byte contain¬
ing the first bit. When interpreted arithmetically, a longword is a two’s com¬
plement integer with bits increasing in significance from 0 through 30 and
with bit 31 designating the sign.
The value of the integer is in the range -2,147,483,648

through

2,147,483,647. For addition, subtraction, and comparison, VAX instructions
provide direct support for interpreting longwords as unsigned integers with
bits increasing in significance from bit 0 to bit 31. The value of the unsigned
integer is in the range of 0 through 4,294,967,295.

Figure 4-9 ■ Longword Data Format

Quadword Data
A quadword is eight contiguous bytes starting on an arbitrary byte boundary.
The bits are numbered from the right starting with 0 and terminating with 63
as shown in Figure 4-10. A quadword is specified by its address that is the
address of the byte containing the first bit. When interpreted arithmetically,
a quadword is a two’s complement integer with bits increasing in significance
from 0 through 62, and bit 63 is the sign bit. The value of the integer is in the
range -263 to (263)-l. The quadword data type is not fully supported by VAX
instructions.

4-9

Figure 4-10 ■ Quadword Data Format
Octaword Data
An octaword is sixteen contiguous bytes starting on an arbitrary byte bound¬
ary. The bits are numbered from the right starting with 0 and terminating
with 127 as shown in Figure 4-11. Octawords are specified by the address of
the byte containing the first bit. When interpreted arithmetically, an
octaword is a two’s complement integer with bits of increasing significance
starting at bit 0 and terminating at bit 126, and bit 127 is the sign bit. The
value of the integer is in the range -2127 to (2127)-1. The octaword data type is
not yet fully supported by VAX instructions.

: A + 8
: A + 12

Figure 4-11 ■ Octaword Data Format

4-10 ■ Data Representation

■ Numeric String Data
Numeric string data is used to represent fixed scaled quantities in forms close
to their external representations. For programs that are input/output inten¬
sive, rather than computation intensive, this presentation can be efficient.
The decimal string form also provides greater precision than floating point
and greater range than integer data types.
There are two forms of decimal data on VAX systems— numeric and packed.
In numeric string data, each digit occupies one byte. In packed decimal
strings, two digits are packed into one byte. Because the numeric string
exactly represents many external data arrangements, it appears in several
forms.
There are two forms of signed numeric strings. The first is called the leading
separate numeric string; the second is called the trailing numeric string. In the
leading separate numeric string, the sign appears before the first digit. In the
trailing numeric string, the sign is superimposed on the last digit.
Leading Separate Numeric String Data
A leading separate numeric string is a contiguous sequence of bytes in mem¬
ory. It is specified by two attributes—an address and a length. The address is
the address of the first byte or the sign character. The length is the length of
the string in digits—not the length of the string in bytes. The number of bytes in
a leading separate numeric string is the length plus one. The address of the
string specifies the byte of the string containing the sign. Digits of decreasing
significance are assigned to bytes of increasing addresses.
The sign of a leading separate numeric string is stored in a separate byte. Valid
sign bytes are listed in Table 4-1. The preferred representation for positive
strings is the ASCII code 2B for the plus sign character. All subsequent bytes
contain an ASCII digit character. Table 4-2 lists the ASCII digit characters.
Table 4-1 ■ Leading Separate Numeric String Sign Bytes
Sign

Decimal

Hexadecimal

ASCII character

< blank >

4-11

Table 4-2 ■ ASCII Digit Characters
Digit

Decimal

Hexadecimal

ASCII character

The length of a leading separate numeric string must be within the range of 0
to 31 (0 to 31 digits). The value of a zero length string is zero. It contains the
sign byte only. Figures 4-12 and 4-13 show how to represent + 123 and -123
in leading separate numeric string format.

0
B

: A

: A + 1

: A + 2

: A + 3

Figure 4-12 ■ Positive Leading Separate Numeric String Format

4-12 • Data Representation

3
D

: A
: A + 1

3
3

: A + 2

: A + 3

Figure 4-13 ■ Negative Leading Separate Numeric String Format
Trailing Numeric String Data
A trailing numeric string is a contiguous sequence of bytes in memory. The
string is specified by two attributes—an address and the length of the string.
The address of the first byte of the string is the most significant digit. The
length is the length of the string in bytes. Note that the address of the string
specifies the byte of the string containing the most significant digit. Digits of
decreasing significance are assigned to increasing addresses. All bytes of a
trailing numeric string except the least significant digit byte must contain
ASCII decimal (0 through 9) characters. See Table 4-2 for a list of the ASCII
characters.
The highest addressed byte of a trailing numeric string represents an encoding
of both the least significant digit and the sign of the numeric string. The
numeric string instructions support any encoding. There are three preferred
encodings used by VAX software
■ overpunched numeric
■ unsigned numeric in which there is no sign and the least significant digit
contains an ASCII decimal digit character
■ zoned numeric

Several variations in overpunched format have evolved because that format
has been used for many years, and because various card encodings are used.
These alternate forms are accepted on input. The normal form is generated on
output of all operations. The valid representations of the digit and sign in each
of the latter two formats is shown in Table 4-3.

4-13

Table 4-3 ■ Representation of Least Significant Digit and Sign
ASCII Character
Digit

Decimal

Hexadecimal

Normal

Alternate

Overpunch Format
*

123

{

-0

125

}

-1

None

-2

None

-3

None

-4

None

-3

None

-6

None

-7

None

-8

None

-9

None

* There are three alternate characters for this code: the zero (0), the left square bracket
([), and the question mark (?).
t There are three alternate characters for this code: the right square bracketQ), the
colon (:), and the exclamation point (!).

4-14 m Data Representation

Table 4-3 ■ Representation of Least Significant Digit and Sign (Cont.)
ASCII Character
Digit

Decimal

Hexadecimal

Normal

Alternate

None

Zoned Numeric Format
0

None

-0

112

None

-1

113

None

-2

114

None

-3

115

None

-4

116

None

-5

117

None

-6

118

None

-7

119

None

-8

120

None

-9

121

None

The length of a trailing numeric string must be within the range of 0 to 31 (0
to 31 digits). The value of a zero length string is zero. It contains no bytes and
no memory is referenced; hence the address need not be valid. Figures 4-14
and 4-15 show how to represent the value 123 in both positive and negative
trailing numeric string format.

4-15

ZONED FORMAT OR UNSIGNED
7

: A
: A + 1
: A + 2

OVERPUNCH FORMAT

7_4

3_0

: A + 1

: A + 2

: A

Figure 4-14 ■ Positive Trailing Numeric String Format

ZONED FORMAT
4

3
: A
: A + 1
: A + 2

OVERPUNCH FORMAT

: A
: A + 1
: A + 2

Figure 4-15 ■ Negative Trailing Numeric String Format

4-16 ■ Data Representation

■ Packed Decimal String Data
A packed decimal string is a contiguous sequence of bytes in memory. The
address and length specify a packed decimal string. The length is the number
of digits in the string—not the number of bytes. Every byte of a packed decimal
string is divided into two 4-bit fields called nibbles. Each nibble must contain
decimal digits except the low nibble of the last byte that must contain a sign.
The representation for the digits and sign is listed in Table 4-4.
Table 4-4 ■ Packed Decimal String Digits and Signs
Character

Decimal

Hexadecimal

+
-

* This value can be 10, 12, 14, or 15 (hexadecimal),
t This value can be A, C, E, or F (hexadecimal).

X This value can be 11 or 13 (hexadecimal).
§ This value can be B or D (hexadecimal).

The preferred sign representation is 12 for a plus sign and 13 for a minus sign.
The length is the number of digits in the packed decimal string (not counting
the sign) and must be within the range of 0 through 31. If the number of
digits is odd, the digits and the sign fit into length/2 + 1 bytes. When the
number of digits is even, an extra 0 digit must appear in the high nibble (bits
4 through 7) of the first byte. The length in bytes of a string with an even
number of bytes is length/2 + 1 bytes. The length is the integer portion only.
The value of a zero-length packed decimal string is zero. It contains only the
sign byte that also includes the extra 0 digit.

4-17

The address of the string specifies the byte of the string containing the most
-significant digit in its high nibble. Digits of decreasing significance are
assigned to increasing byte addresses and from high nibble to low nibble
within a byte. In Figure 4-16, + 123 (length 3) is represented in packed deci¬
mal format. In Figure 4-17, - 12 (length 2) is represented in packed decimal
format.

: A

: A + 1

figure 4-16 ■ Positive Packed Decimal String Format

: A

: A + 1

Figure 4-17 ■ Negative Packed Decimal String Format

■ Queue Data
A queue is a list whose entries are specified by their addresses. Each queue
entry is linked to the next by way of a pair of longwords. The first longword is
the forward link. It specifies the location of the succeeding entry. The second
longword is the backward link. It specifies the location of the preceding entry.
VAX systems support two types of links—absolute and self-relative. Queues
are named after the type of link used in the queue.
An absolute queue uses a link that contains the absolute address of the entry
to which it points. A self-relative queue uses a link that contains a displace¬
ment from the present queue entry.

4-18 ■ Data Representation

Queues require a header that is identical to a pair of queue linkage longwords.
The forward link of the header is the address of the entry called the head of
the queue. The backward link of the header is the address of the entry called
the tail of the queue. Logically, the forward link of the tail points to the
header.
Self-relative queues are intended for use in situations where they are
addressed by two separate processes. Each process may view the queues as
residing in two separate locations in their respective virtual address spaces.
The instructions that operate on self-relative queues are interlocked. When
interlocked instructions only are used on the queue, the processes may be in
separate machines with each process directly addressing the queue.
Absolute queues are somewhat simpler in structure than self-relative queues
in that their pointers are virtual addresses. Also, the instructions that operate
on these queues are not interlocked. In general, operations on absolute queues
are somewhat faster than those on self-relative queues. However, absolute
queues cannot be used when more than one processor is to access them. Also,
the queues can be shared by two processes in the same processor only when
both processes address the queue in the same section of their virtual address
space. Figure 4-18 illustrates the format of the self-relative queue, and Figure
4-19 illustrates the format of the absolute queue.

4-19

EMPTY SELF-RELATIVE QUEUE (HEADER ONLY)

SELF-RELATIVE QUEUE WITH ONE ENTRY
31

SELF-RELATIVE QUEUE WITH TWO ENTRIES
31

1 0

Figure 4-18 ■ Self-relative Queues

1 0

4-20 • Data Representation

EMPTY ABSOLUTE QUEUE (HEADER ONLY-SIMPLE ENTRY ONLY)

ABSOLUTE QUEUE WITH HEADER AND OTHER ENTRY

ABSOLUTE QUEUE WITH HEADER AND TWO OTHER ENTRIES

Figure 4-19 ■ Absolute Queues

4-21

■ Variable Length Bit Field Data
The variable length bit field is a type of data used to store small integers
packed together in a larger data structure. This conserves memory when many
small integers are part of a larger structure. A specific case of the variable bit
field is that of one bit. This form is used to store and access individual flags
efficiently.
A variable bit field is from 0 to 32 contiguous bits located arbitrarily with
respect to byte boundaries and specified by three attributes—a base address,
a bit position, and size.
The base address (A) is the address of a particular byte in memory chosen as a
reference point for locating the bit field F. The bit position (P) is the signed
longword specifying the bit displacement of the least significant bit of the
field with respect to bit zero of the byte at address A. The size (S) is the byte
integer length of field F expressed as a number of bits. Size must be between 0
and 32 bits inclusive. Figure 4-20 illustrates the variable length bit field
where the field is the shaded area.

SIZE OF FIELD IN BITS -1
BIT DISPLACEMENT OF FIELD
FROM BIT 0 OF ADDRESS A -

Figure 4-20 ■ Variable Length Bit Field
For bit strings in memory, the position in bits can be either a positive or nega¬
tive displacement within the range of -231 through (231)-1. It can be viewed
as a signed 29-bit byte offset and a 3-bit bit-within-byte field as shown in Fig¬
ure 4-21.

4-22 • Data Representation

3
j_3

BYTE OFFSET

BIT-WITHIN-BYTE

Figure 4-21 ■ Variable Length Bit Field in Memory
The sign-extended 29-bit byte offset is added to the address and the resulting
address specifies the byte in which the field begins. The 3-bit bit-within-byte
field encodes the starting position (0 through 7) of the field within that byte.
VAX instructions provide direct support for the interpretation of a field as a
signed or unsigned integer. When interpreted as a signed integer, it is the
two’s complement with bits increasing in significance from 0 through S-2
where bit S-l is the sign bit. When interpreted as an unsigned integer, bits
increase in significance from 0 through S-l. A field size of zero has a value of
zero.
A variable bit field may be contained in zero to five bytes. From a memory
management point of view only the minimum number of bytes necessary to
contain the field is actually referenced.
If the field is contained in a register and the size is not zero, the position oper¬
and must have a value in the range 0 through 31 or a reserved operand fault
occurs. If size plus position are greater than 32, then the operand is located in
the

concatenation

\n + 1]

and

[n]

(that

R\n + 1]’RR[«]). See Figure 4-22. The most significant bit of the specified
field lies in R[« + 1] and the least significant bit of the specified field is
located in R[«].

3
1

p - 1

y//////.//
P + s

P + S - 1

Figure 4-22 ■ Variable Length Bit Field in Register

4-23

To illustrate the variable length bit field with a positive displacement, assume
the following variable length bit field attributes—base address (A)

B2204C01, position (P) = 29, and size (S) = 2. See Figure 4-23. The start¬
ing position of the field is bit 29; that is, the first bit of F is the twenty-ninth
bit after bit zero of A as shown in Figure 4-23. Now that the starting bit posi¬
tion of field has been located, determine its length. To determine its length,
apply the size attribute as shown in Figure 4-24.

FIRST
BIT OF F

'29' 28
V77

'/S'.

: A

B2204C01

Figure 4-23 ■ Positive Displacement Variable Bit Field

FIELD F

Figure 4-24 ■ Determining Length of Positive Displacement Field
To determine the length of negative displacement variable length bit field,
assume the following attributes—base address (A) = 801134E3, position (P)
= -7, and size (S) = 6. See Figure 4-25. The starting position of F is the
seventh bit preceding the zero bit of address 801134E3 as shown in Figure
4-25. To determine the field length, apply the size attribute as in the previous
example counting from lower to higher addresses as shown in Figure 4-26.

4-24 ■ Data Representation

STARTING BIT POSITION
OF FIELD F
801134E2
801134E3
801134E4

Figure 4-25 ■ Negative Displacement Variable Bit Field

801134E2
'

FIELD F

Figure 4-26 ■ Determining Length of Negative Displacement Field

■ Data in Registers
When byte, word, longword, or floating type data is stored in a register, the
bit numbering in the register corresponds to the numbering in memory. A
byte is stored in a register in bits 0 through 7. A word is stored in bits 0
through 15. Longword and F_floating data is stored in register bits 0
through 31. A byte or word written to a register writes only bits 7 through 0
and 15 through 0 respectively. The higher bits are unaffected. A byte or word
read from a register reads only bits 0 through 7 and 0 through 15, respec¬
tively. The other bits are ignored.
When quadword or D_floating data is stored in a register, the data is stored
in two adjacent registers. Because of program counter restrictions, wrap¬
around from register PC to register RO is unpredictable. Bits 0 through 31 of
the quadword or D_floating data are stored in the first register. Bits 32
through 63 of the quadword or D_floating data are stored in the second reg¬
ister.

4-25

An octaword or H_floating data stored in a register is stored in four adja¬
cent registers. Bits 0 through 31 of the data are stored in the first register, bits
32 through 63 are stored in the second register, bits 64 through 93 are stored
in the third register, and bits 96 through 127 are stored in the fourth register.
With one restriction, a variable length bit field may be specified in the regis¬
ters. The starting bit position (P) must be in the range 0 through 31. For quadword and D— floating data, a pair of registers is treated as a 64-bit register
with bits 0 through 31 in the base register and bits 32 through 63 in the adja¬
cent register.
The VAX string instructions are unable to process string data types stored in
registers. Thus there is no representation of strings in registers.

Chapter 5 ■ The Instruction Characteristics

The notation conventions, source statement format, and register addressing
modes are described in this chapter. One must understand the notation con¬
ventions before being able to read and comprehend the instructions. Then the
addressing modes can be studied. Addressing modes are related to the instruc¬
tion format because the form of the instruction implicitly specifies the regis¬
ter addressing mode.

■ Notation Conventions
The notation conventions described here are for the assembler and instruction
set only and do not apply to other syntax. The conventions cover the assem¬
bler, instruction operand, instruction operation, and range and extent nota¬
tion.

Assembler Notation
The radix of the assembler is decimal. To express a hexadecimal number in
assembler notation, the number must be preceded by a caret ( -) and an upper¬
case X. For those keyboards without a caret character, the up arrow (t) charac¬
ter is used. For example, in the instruction MOVW #3456,-(SP), the
assembler interprets the number 3456 as a decimal number. If 3456 is to be
interpreted as a hexadecimal number, it must be preceded by a caret or up
arrow and an uppercase X (#tX3456).

Operand Notation
Operands are specified in the following way:
< name >. < access_type > < data_type >
where < name > is typically a mnemonic for the operand of the instruction.
The <access_ type> is a letter denoting the operand access type.
a

means to calculate the effective address of the specified operand.
Address is returned in a longword that is the instruction operand. Con¬
text of address calculation is given by < data_type >.

means there is no operand reference. Operand specifier is a branch dis¬
placement. Size of branch displacement is given by < data_type >.

5-2 ■ The Instruction Characteristics

means the operand is read, sometimes modified, and written. Note
that this is not an indivisible memory operation. Also note that if the
operand is not actually modified, it may not be written back. However,
modify type operands are always checked for both read and write acces¬
sibility.

r
v

means the operand is read only.
means to calculate the effective address of the specified operand. If the
effective address is in memory, the address is returned in a longword
that is the instruction operand. Context of address calculation is given
by <data_type> . If the effective address is R«, then the operand
actually appears in R[«], or in R[n + 1]’R[»].

means the operand is written only.

The < data_type > is a letter denoting the data type of the operand.
b

denotes byte data

denotes D_floating data

denotes F_floating data

denotes G_floating data

denotes H_floating data

denotes longword data

denotes octaword data

denotes quadword data

denotes word data

denotes the first data type specified by instruction

denotes the second data type specified by instruction

Operation Notation
The operation of each instruction is given as a sequence of control and assign¬
ment statements in an ALGOL-like syntax. No attempt is made to define the
syntax formally. The syntax is assumed to be familiar to the reader and is sum¬
marized in Table 5-1.

5-3

Table 5-1 ■ Operation Notation Conventions
Notation

Meaning

addition

subtraction

multiplication

/
**

division (quotient only)
exponentiation
concatenation
is replaced by

is defined as

Rn or R [n]

contents of register Rn

the contents of register R15

the contents of register R14

the contents of register R13

the contents of register R12

PSW

the contents of the Processor Status Word

PSL

the contents of the Processor Status Longword

(x)

contents of memory whose address is x

(x) +

contents of memory whose address is x; x is
incremented by size of operand referenced at x

-(*)

x decremented by size of operand to be referenced
at x; contents of memory whose address is x

x:y

a modifier which delimits an extent from bit
position x to bit position y inclusive

xl,x2,...,xn

a modifier that enumerates bits xl,x2, ... ,xn

x...y

x through y inclusive

{

}

braces used to indicate precedence

AND

logical AND

logical OR

XOR

logical XOR

5-4 ■ The Instruction Characteristics

Table 5-1 ■ Operation Notation Conventions (Cont.)
Notation

Meaning

NOT

logical (l’s) complement

LSS

less than signed

LSSU

less than unsigned

LEQ

less than or equal signed

LEQU

less than or equal unsigned

EQL

equal signed

EQLU

equal unsigned

NEQ

not equal signed

NEQU

not equal unsigned

GEQ

greater than or equal signed

GEQU

greater than or equal unsigned

GTR

greater than signed

GTRU

greater than unsigned

SEXT (x)

x is signed-extended to size of operand needed

ZEXT (x)

x is zero-extended to size of operand needed

REM (x, y)

remainder of x divided by y, such that x/y and REM
(x,y) have the same sign

MINU (x, y)

minimum unsigned of x and y

MAXU (x, y)

maximum unsigned of x and y

The following conventions are used:
■ Other than that caused by (x) + , or - (x), and the advancement of the pro¬
gram counter, only operands or portions of operands appearing on the left
side of assignment statements are affected.
■ No operator precedence is assumed other than that replacement has the
lowest precedence. Precedence is indicated explicitly by braces.
■ All arithmetic, logical, and relational operators are defined in the context
of their operand. For example, a plus sign ( + ) applied to floating operands
means a floating add while the same sign applied to byte operands means
an integer byte add. Similarly, LSS is a floating comparison when applied
to floating operands; and LSS is an integer byte comparison when applied
to byte operands.

5-5

■ Instruction operands are evaluated according to the operand specifier con¬
ventions. The order in which operands appear in the instruction descrip¬
tion has no effect on the order of evaluation.
■ In general, condition codes are affected on the value of actual stored
results, not on true results that might be generated internally to greater pre¬
cision. Thus, for example, two positive integers can be added together and
the sum stored, because of overflow, as a negative value. The condition
codes will indicate a negative value even though the true result is clearly
positive.

Range and Extent Notation
An integer range is specified in English by the word through, or in notational
form by a double period (..), and is inclusive. For example, the range 0 through
4, or 0..4, means the integers 0, 1, 2, 3, and 4.
An extent is given by a pair of numbers separated by a colon and is also inclu¬
sive. For example, bits 7:3 specifies an extent of bits including bits 7, 6, 5, 4,
and 3.

■ MACRO Source Statement Format
MACRO source statements have four fields—label, operator, operand, and
comment fields. The label field defines a location in the program. The opera¬
tor field specifies the action to be performed. The operator can be a VAX archi¬
tecture instruction, an assembler directive, or a MACRO call. The operand
field contains the instruction operand or operands, the assembler directive
argument or arguments, or the MACRO statement or statements. The com¬
ment field contains a comment that explains the meaning of the statement.
Comments do not affect program execution.
The label and comment fields are optional. The label field must end with a
colon (:). The comment field must begin with a semicolon (;). The operand
field must conform to the format of the instruction, directive, or MACRO spec¬
ified in that field. See Figure 5-1 for the MACRO source statement format.
The statement format and fields are fully described in the VAX-11 MACRO
Reference Manual.

5-6m The Instruction Characteristics

COLUMN
1

1
1

LABEL:

COLUMN
9

COLUMN
17

CLRL

1
1

COLUMN
41

1
Y
; CLEAR REGISTER

Figure 5-1 ■ MACRO Source Statement Format
Because of printing restrictions, the instruction examples in this book do not
conform to the field requirements of the assembler. In practice, the instruc¬
tions must be formatted as shown in Figure 5-1. A single statement can be
continued on several lines by using a hyphen as the last nonblank character
before the comment field. When there are no comments, the line can be con¬
tinued by using a hyphen at the end of the line.

■ Instruction Format
The VAX instruction set has a variable length instruction format whose length
depends on the type of instruction. The general instruction format is shown in
Figure 5-2. Each instruction consists of an operator followed by up to six oper¬
ands. The number and type of operands depend on the operator. All operands
have the same format; that is, an address mode plus additional information.
This additional information contains up to two register designators and
addresses, data, or displacements. Operand use is determined implicitly from
the opcode and is called the operand type. It includes both the access type and
the data type. The example in Figure 5-3 shows several VAX instruction for¬
mats.

OPCODE (1 OR 2 BYTES)
OPERATION CODE

OPERAND SPECIFIER 1

OPERAND SPECIFIER 2

OPERAND SPECIFIER 3

OPERAND SPECIFIER N

Figure 5-2 ■ General VAX Instruction Format

5-8 ■ The Instruction Characteristics

MOVL 6(R1), R5

SIX IS ADDED TO R1. THE RESULT USED AS AN
ADDRESS AND THE CONTENTS OF THAT ADDRESS
IS MODED TO R5

BYTE_
1

MOVL

(R1)

OPCODE
OPERAND SPECIFIER 1
OPERAND SPECIFIER 2

A. MOVE LONG INSTRUCTION

MOVW#t X3456, -(SP)

; THE NUMBER 3456 IS PUSHED ON THE
; STACK

BYTE
1

MOVW

(PC) +

~(SP)

OPCODE
OPERAND SPECIFIER 1
\ IMMEDIATE DATA (56 STORED IN BYTE 3)
| (34 STORED IN BYTE 4)
OPERAND SPECIFIER 2

B. MOVE WORD INSTRUCTION

ADDL 3 (SP) + , R4, R5

NUMBER ON THE STACK IS
ADDED TO THE CONTENTS OF
R4 AND RESULT IS STORED
IN R5

BYTE
1

OPCODE

OPERAND SPECIFIER 1

OPERAND SPECIFIER 2

OPERAND SPECIFIER 3

C. ADD LONG INSTRUCTION (3 OPERAND)

Figure 5-3 ■ Instruction Formats
Operator Field
Each VAX instruction contains an operating code (opcode) that specifies the
operation to perform. An instruction is specified by the byte address of its
opcode. The opcode may be one or two bytes long depending on the contents
of the byte at address A. Two bytes are used under the condition that the
value of the first byte is FD (hexadecimal) through FF (hexadecimal). Figure
5-4 illustrates the opcode formats.

0
OPCODE

1 BYTE OPCODE

15_87_0
_

FC-FD
(1111 1100-1111 1111)

2 BYTE OPCODE

Figure 5-4 ■ Opcode Format

Operand Field
The operand field contains an operand specifier that gives the information
needed to locate the operand. Each general mode addressing description
includes the definition of the operand address and the specified operand. For
operand specifiers of address access type, the operand address is the actual
instruction operand. For other access types, the specified operand is the
instruction operand. The branch mode addressing description includes the def¬
inition of the branch address.
The operand types specify how the operand is to be used. The opcode informa¬
tion includes the data type of each operand and how the operand is accessed.
The data types include byte, word, longword, quadword, octaword, and all
the floating types. The following groups of data types are considered equiva¬
lent within groups for addressing mode considerations:
■ Longword and F_floating
■ Quadword, D_floating, and G_floating
■ Octaword and H

floating

An operand may be accessed in one of six ways.
1. Read—the specified operand is read-only.
2. Write—the specified operand is write-only.
3. Modify—the specified operand is read, potentially modified, and is writ¬
ten. This is not a memory interlock.

5-10 ■ The Instruction Characteristics

4. Address—the address of the operand in the form of a longword is the
actual instruction operand. The operand is not accessed directly although
the instruction may subsequently use the address to access that operand.
5. Variable bit field base address—same as address access type except for reg¬
ister mode. In register mode, the field is stored in the register designated
by the destination operand or in the destination register concatenated with
the next higher addressed register. This access type is a special variant of
the address access type.
6. Branch—no operand is accessed. The operand specifier itself is a branch
displacement. In this specifier, the data type indicates the size of the
branch displacement.
For the address and branch address type that do not directly reference oper¬
ands, the data type indicates the address and branch. The address indicates
the operand size to be used in the address calculation in the autoincrement,
autodecrement, and index modes. The branch indicates the branch displace¬
ment.

■ Addressing Modes
VAX register addressing can be divided into two broad categories—general
mode addressing and branch addressing. The sections that follow describe the
various modes under both categories.
Table 5-2 contains a summary of the general register and program counter
addressing modes. It shows the mode specifier for each addressing mode in
hexadecimal and decimal notation; the assembler notation; the access types
that may be used with the various modes; the effect on the program and stack
pointer; and which modes may be indexed. For example, in literal mode, only
a read access may occur. Any other type of access results in a fault. The pro¬
gram counter and stack pointer are not referenced in this mode and are logi¬
cally impossible. If indexing is attempted in this mode, a reserved addressing
mode fault occurs.

Table 5-2 ■ Addressing Modes
GENERAL REGISTER ADDRESSING
Hex Dec Name

Assembler

r m w a v

Indexable?

0-3

literal

St#literal

y f f f f

indexed

i[Rx]

y y y y y

y y y f y

(Rn)

y y y y y

autodecrement

-(Rn)

y yyyy

autoincrement

(Rn) +

y y y y y

autoincrement
deferred

@(Rn) +

y y y y y

byte displacement

BtD (Rn)

y y y y y

byte displacement
deferred

@BtD (Rn)

y y y y y

word displacement WtD (Rn)

y y y y y

word displacement @WtD (Rn) y y y y y
deferred

longword displace¬ LtD (Rn)
ment

y y y y y

longword displace¬
ment deferred

y y y y y

@LtD (Rn)

PROGRAM COUNTER ADDRESSING
8

immediate

It# constant

y u u y y

absolute

@# address

y y y y y

byte relative

Bt address

y y y y y

byte relative
deferred

@Btaddress y y y y y

word relative

Wt address

y y y y y

word relative
deferred

@Wt address y y y y y

longword relative

Lt address

y y y y y

longword relative
deferred

@Lt address y y y y y

5-12 • The Instruction Characteristics

Legend
a

address access

displacement

reserved addressing mode fault

any indexable addressing mode

logically impossible

modify access

program counter addressing

read access

unpredictable

unpredictable for octaword and H_floating format only

unpredictable for quadword, octaword, D_floating, G_floating, and

unpredictable for index register same as base register

H_floating (and field, if position + size is greater than 32)

field access

write access

yes, always valid addressing mode

General Mode Addressing
In general mode addressing, there are two types of addressing—general regis¬
ter addressing and program counter addressing. General register addressing
has nine modes while program counter addressing has four.
■ General Register Addressing
The nine modes in which to access general registers are autodecrement, autoin¬
crement, autoincrement deferred, displacement, displacement deferred,
index, literal, register, and register deferred. Each is described in the ensuing
paragraphs.
Autodecrement Mode. With autodecrement mode, .the size of the operand in
bytes is subtracted from the content of specified source register. Then the con¬
tent of the destination register is replaced by the remainder of the subtraction.
The remainder is the address of the operand.
To specify the autodecrement mode, the source register operand is enclosed in
parentheses and is preceded by a minus (-) sign. See Example 3-1 for the for¬
mat of this address mode.

5-13

Example 5-1 ■ Autodecrement Mode Instruction
MOVL

-(R3)# R4

Figure 5-5 shows a wow /o«g instruction using autodecrement mode. The con¬
tents of register R3 are decremented according to the data type specified in
the opcode. In this example, the register contents are decremented by 4
because a longword is used. The updated contents of R3 are then used as the
address of the operand. The instruction causes the operand to be fetched and
loaded into register R4.

7_4

3_0

v___y v___y
MODE

SPECIFIER

OPERAND SPECIFIER FORMAT

ADDRESS
SPACE
00001014
00001015
00001016
00001017

10
32
54
CE

| 00001018 |

1 00000000 1

> CE543210 .

-NL

BEFORE INSTRUCTION EXECUTION
R3

| 00001014 |

| CE543210 |

AFTER INSTRUCTION EXECUTION

00003000
00003001
00003002

DO
73
54

OPCODE FOR MOVE LONG INSTRUCTION
AUTODECREMENT MODE, REGISTER R3
REGISTER MODE, REGISTER R4

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-5 ■ Autodecrement Mode Instruction
The program counter may not be used in autodecrement mode. If it is, the
address of the operand is unpredictable and the next instruction executed or
the next operand specifier is unpredictable.

3-14 ■ The Instruction Characteristics

Autoincrement Mode. In autoincrement mode addressing, the register speci¬
fied in the source register operand contains the address of the operand. After
the operand address is determined, the size of the operand is added to the
contents of the source register. Then the contents of the destination register
are replaced by the sum of the addition. This mode provides for automatic
stepping of a pointer through sequential elements of a table of operands. Con¬
tents of registers are incremented to address the next sequential location.
The autoincrement mode is especially useful for array processing and stacks.
It accesses an element of a table and then steps the pointer to address the next
operand in the table. Although most useful for table handling, this mode isgeneral and may be used for variety of purposes.
If the program counter is used as the general register, this addressing mode is
considered immediate mode and has special syntax. Immediate mode is
described in the section on Program Counter Addressing.
The autoincrement mode is specified by enclosing the register identifier in
parentheses followed by a plus (+) sign. See Example 5-2 for the format of
the instruction.

Example 5-2 ■ Autoincrement Mode Instruction

H0VL

<R1)+/R2

Figure 5-6 shows a move long instruction using autoincrement mode. The con¬
tent of register R1 is the effective address of the source operand. Because the
operand is a 32-bit longword, 4 bytes are transferred to register R2. Register
R1 is then incremented by 4 because the instruction specifies a longword data
type.
Autoincrement Deferred Mode. In autoincrement deferred addressing, the
source register contains a longword address that is a pointer to the operand
address. After the operand address has been determined, 4 is added to the
contents of the source register. The contents of the source register are
replaced with the sum of the addition. The quantity 4 is used because there
are 4 bytes in an address.
Autoincrement deferred mode is specified by an at (@) sign, the source regis¬
ter enclosed in parentheses, followed by a plus ( + ) sign. Example 5-3 contains
a register in the autoincrement deferred mode.

Example 5-3 ■ Autoincrement Deferred Mode Instruction

«(RD*,R2

SPECIFIER

OPERAND SPECIFIER FORMAT

00000000

SOURCE OPERAND ADDRESS: 00001010

BEFORE INSTRUCTION EXECUTION

ADDRESS
SPACE

00001010
00001011
00001012

| 00001014 |

| 33221100 |

00001013
00001014
00001015

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002

OPCODE FOR MOVE LONG WORD INSTRUCTION
AUTOINCREMENT MODE, REGISTER R1
REGISTER MODE, REGISTER R2

MACHINE CODE: ASSUME STARTING LOCATION 3000

Figure 5-6 ■ Autoincrement Mode Instruction

5-16 ■ The Instruction Characteristics

Figure 5-7 shows a move word instruction using autoincrement deferred
mode. Register R1 is a pointer to the operand address. Because a word length
instruction is specified, the byte at the effective address and the byte at the
effective address plus 1 are loaded into the low-order half of register R2. The
upper half of register R2 is unaltered. Register R1 is then incremented by 4
since it points to a 32-bit address.
If the program counter is used as the general register, this addressing mode is
considered absolute mode. Absolute mode is described in the section on Program Counter Addressing.
4

y
REGISTER
SPECIFIER

MODE-1
SPECIFIER

OPERAND SPECIFIER FORMAT

ADDRESS
SPACE
00001010
00001011
00001012
00001013
00001014
00001015

00
11
22
33
44
55

L 33221100
J

| 00001010 ]

| 00000000 |

DDRESS

/^ADDRESS
SPACE
33221100
33221101
33221102
33221103

34
5F
00
00

BEFORE INSTRUCTION EXECUTION

| 00001014 ”|

| 00005F34 1

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002

B0
91
52

OPCODE FOR MOVE WORD INSTRUCTION
AUTOINCREMENT DEFERRED MODE, REGISTER R1
REGISTER MODE, REGISTER R2

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-7 ■ Autoincrement Deferred Mode Instruction

5-17

Displacement Mode. The VAX architecture provides for an 8-bit, 16-bit, or
32-bit offset. Because most program references occur within small discrete
portions of the address space, a 32-bit offset is not always necessary. The 8and 16-bit offsets use fewer bits. If the displacement is a byte or a word, it is
sign-extended to 32 bits. Then the displacement is added to the content of the
specified register. The result is the operand address. See Example 5-4 for the
syntax of the displacement mode.

Example 5-4 ■ Byte Displacement Mode Instruction
MOVE

Bt5(R4),Bt3(R3)

Figure 5-8 shows a move byte instruction using displacement mode. A dis¬
placement of 5 is added to the content of R4 to form the address of the byte
operand. The operand is moved to the address formed by adding the displace¬
ment of 3 to the contents of R3.
Three data types can be specified. For example,
■ Btd(R«) forces byte displacement.
■ Wtd(Rn) forces word displacement.
■ Ltd(Rtf) forces longword displacement.

If the program counter is used as the general register, this mode is called rela¬
tive mode. The Program Counter Register Addressing section describes the
relative mode.
Displacement Deferred Mode. If the displacement is a byte or word, it is signextended to 32 bits. Then the displacement is added to the contents of the
selected general register. The result is a longword address of the operand
address. See Example 5-5 for an example of an instruction in displacement
deferred mode.
Three data types can be specified. For example,
■ @Btd(R«) forces byte displacement deferred mode.
■ @ Wtd(Rn) forces word displacement deferred mode.
■ @Ltd(Rn) forces longword displacement deferred mode.

5-18 ■ The Instruction Characteristics

4 3
BYTE DISPLACEMENT MODE

WORD DISPLACEMENT MODE

LONGWORD DISPLACEMENT MODE

1- MODE SPECIFIER
A = BYTE DISPLACEMENT
C = WORD DISPLACEMENT
E = LONGWORD DISPLACEMENT

OPERAND SPECIFIER FORMAT
ADDRESS
SPACE
00001015
00001016
00001017
00001018
00001019

06
00

•

00002021
00002022
00002023

00
00

00001012 |

| 00002020 |

—OPERAND
00002020

00001012
+5

00001017

00002023

00
00
00

BEFORE INSTRUCTION EXECUTION
ADDRESS
SPACE
00001015
00001016
00001017
00001018

00
00

| 00001012 1

| 00002020 ]

00002021
00002022
-—OPERAND

00002023

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002
00003003
00003004

90
A4
05
A3
03

OPCODE FOR MOVE BYTE INSTRUCTION
SIGNED BYTE DISPLACEMENT, REGISTER R4
SPECIFIER EXTENSION (DISPLACEMENT OF 5)
SIGNED BYTE DISPLACEMENT, REGISTER R3
SPECIFIER EXTENSION (DISPLACEMENT OF 3)

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-8 ■ Displacement Mode Instruction

5-19

Example 5-5 ■ Byte Displacement Deferred Mode Instruction

INCW

«Bt5CR4)

Figure 5-9 shows an increment word instruction using displacement deferred
mode. The quantity 5 is added to the contents of register R4 to produce the
longword address of the address of the operand. The operand of 5713 is incre¬
mented to 5714.
If the program counter is used as the general register, this is considered rela¬
tive deferred mode.

Index Mode. Index mode addressing provides very general and efficient access¬
ing of arrays. The VAX architecture provides for context indexing where the
number in the index register is shifted left by the context of the data type
specified. It is not shifted for byte data, shifted once for word data, twice for
longword data, three times for quadword data, and four times for octaword
data. This allows loop control variables to be used in the address calculation
without first shifting them the appropriate number of times. This minimizes
the number of instructions required. This feature is used to advantage in the
FORTRAN VAX compiler.
The operand specifier consists of at least two bytes—a primary operand speci¬
fier and a base operand specifier. The primary operand specifier contained in
bits 0 through 7 includes the index register (Rx) and a mode specifier of 4.
The address of the primary operand is determined by first multiplying the con¬
tents of index register Rx by the size of the primary operand in bytes. This
value is then added to the address specified by the base operand specifier (bits
15:8), and the result is taken as the operand address.
Specifying register, literal, or index mode for the base operand specifier
results in an illegal addressing mode fault. If the use of some particular speci¬
fier is illegal (that is, causes a fault or unpredictable behavior), then that speci¬
fier is also illegal as a base operand specifier in index mode under the same
conditions.
The following restrictions are placed on index register Rx:
1. The program counter cannot be used as an index register. If it is, a
reserved addressing mode fault occurs.
2. If the base operand specifier is for an addressing mode that modifies a reg¬
ister, that register cannot be the index register. If it is, the primary oper¬
and address is unpredictable. Addressing modes that modify a register are
the autoincrement, autoincrement deferred, and autodecrement modes.

5-20 ■ The Instruction Characteristics

Table 5-3 lists the various forms of index mode addressing available. The
names of the addressing modes resulting from index mode addressing are
formed by adding index to the addressing mode of the base operand specifier.
The general register is designated Rn and the indexed register is Rx.

DISP
8

SPECIFIER EXTENSION IS
WORD DISPLACEMENT DEFERRED

SPECIFIER EXTENSION IS
LONGWORD DISPLACEMENT DEFERRED

SPECIFIER EXTENSION IS
BYTE DISPLACEMENT DEFERRED

DISP

yl_j \_y

1- MODE SPf
B = BYTE DISPLACEMENT
D = WORD DISPLACEMENT
F = LONGWORD DISPLACEMENT

DISPLACEMENT

OPERAND SPECIFIER FORMAT

ADDRESS
SPACE
00001017
00001018
00001019
00001020

88
42
24
68

R4
^

| 00001012

l OPERAND
f ADDRESS

00001012
+5

■ OPERAND

5713
+1

OPERAND
INCREMENT

5714

NEW OPERAND

BEFORE INSTRUCTION EXECUTION

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002

B6
B4
05

OPCODE FOR INCREMENT WORD INSTRUCTION
SIGNED BYTE DISPLACEMENT, REGISTER R4
SPECIFIER EXTENSION (DISPLACEMENT OF 5)

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-9 ■ Displacement Deferred Mode Instruction

5-21

Table 5-3 ■ Index Mode Addressing
Index Mode

Assembler Notation

Absolute

@#address [Rx]

Autodecrement

-(Rn) [Rx]

Autoincrement

(Rn) + [Rx]

Autoincrement Deferred

@(Rn) + [Rx]

Deferred Displacement:
Byte

@BtD(Rn) [Rx]

Word

@WtD(Rn) [Rx]

Longword

@LtD(Rn) [Rx]

Immediate1

It# constant [Rx]

Immediate Displacement:
Byte

BtD(Rn) [Rx]

Word

WtD(Rn) [Rx]

Longword

LtD(Rn) [Rx]

(Rn) [Rx]

Relative Indexed

address [Rx]

1 The instruction is recognized by assembler but is not generally useful. The operand
address is independent of the value of the constant.

It is important to note that the operand address (the address containing the
operand) is first evaluated. Then the index specified by the index register is
added to the operand address to find the indexed address. To illustrate this,
an example of each type of indexed addressing is shown in Examples 5-6
through 5-12.
Register Deferred Index Mode. See Example 5-6.

Example 5-6 ■ Register Deferred Index Mode Instruction

INCW

CR2) CR5]

Figure 5-10 shows an increment word instruction using register deferred
index addressing. The base operand address is evaluated. This location is
indexed by 6 because the value (3) in the index register is multiplied by the
word data size of 2.

5-22 ■ The Instruction Characteristics

PRIMARY OPERAND

BASE OPERAND SPECIFIER

DISP

- MODE SPECIFIER

OPERAND SPECIFIER FORMAT

ADDRESS
SPACE
00001012
00001013
00001014
00001015

04
56

| 00001012 |

1 00000003 ]

316 x 2 BYTES PER WORD = 6

78
87

00001012
+6
00001018
00001019

45
67

00001018

OPERAND

BEFORE INSTRUCTION EXECUTION

ADDRESS

00001018
00001019

SPACE

46
67

| 0000101*2 1

| 00000003 ]

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002

B6
45
62

OPCODE FOR INCREMENT WORD INSTRUCTION
INDEX MODE, REGISTER R5
REGISTER DEFERRED MODE, REGISTER R2

ASSEMBLY CODE: ASSUME STARTING LOCATION 00003000

Figure 5-10 ■ Register Deferred Index Mode Instruction
Autoincrement Index Mode. See Example 5-7.
Example 5-7 ■ Autoincrement Index Mode Instruction

CLRL

(R4) + CR5]

5-23

Figure 5-11 shows a clear longword instruction using the autoincrement
indexed addressing mode. The base operand address is in register R4. This
value is indexed by the quantity in R5 multiplied by the data size. This loca¬
tion, plus the next three, are cleared because a clear longword instruction is
specified.

000010A6
000010A7
000010A8
000010A9

ADDRESS
SPACE

00001012 |

00000025 |

22
33
44

► OPERAND

INDEX = 2516 x 4 BYTES PER
LONGWORD,

= 94ie
k 00001012
00000094 ADDRESS OF OPERAND 000010A6

BEFORE INSTRUCTION EXECUTION
ADDRESS
SPACE
000010A6
000010A7
000010A8
000010A9

00
00
00
00

| 00001016 |

| 00000025 |

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002

OPCODE FOR CLEAR LONGWORD INSTRUCTION
INDEX MODE, REGISTER R5
AUTOINCREMENT MODE, REGISTER R4

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-11 ■ Autoincrement Index Mode Instruction
Autoincrement Deferred Index Mode. See Example 5-8.

Example 5-8 ■ Autoincrement Deferred Index Mode Instruction

CLRW

9CR4)+[R5]

5-24 ■ The Instruction Characteristics

Figure 5-12 shows a clear word instruction using the autoincrement deferred
indexing mode. Register R4 contains the address of the operand address. The
index value A is obtained by multiplying the contents (5) of the index register
by the context of the data type, which is 2. The calculated word address is
cleared.

ADDRESS
SPACE

00001012
00001013
00001014

| 00001012 |

| 00000005 |

x 2 BYTES PER WORD = 0000000A

00001015

0608214D
ADDRESS
SPACE
0608214D
0608214E
0608214F

OPERAND

BEFORE INSTRUCTION EXECUTION

ADDRESS
SPACE
0608214D
0608214E
0608214F

| 00001014 |

| 00000005 1

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002

B4
45
94

OPCODE FOR CLEAR WORD INSTRUCTION
INDEX MODE, REGISTER R5
AUTOINCREMENT DEFERRED MODE, REGISTER R4

MACHINE CODE: ASSUME STARTING LOCATION 3000

Figure 5-12 ■ Autoincrement Deferred Index Mode Instruction
Autodecrement Index Mode. See Example 5-9.

Example 5-9 ■ Autodecrement Index Mode Instruction

CLRW

-<R2) [ R4 ]

5-25

Figure 5-13 shows a clear word instruction using autodecrement indexed
mode. Register R2 is predecremented and the indexed value is calculated as 6.
Because a clear word instruction is specified, two bytes are cleared.

ADDRESS
SPACE

0000101A
0000101B
0000101C
0000101D

33
33
33
33

| 00001016 ~|

| 00000003 ~[

316 x 2 BYTES PER WORD = 6(INDEX)
00001016
00000002

DECREMENT BY 2

00001014
00000006

OPERAND ADDRESS
INDEX VALUE

0000101A

INDEXED OPERAND ADDRESS

BEFORE INSTRUCTION EXECUTION

ADDRESS
SPACE

0000101A
0000101B
0000101C
0000101D

00
00
00
00

1 00001014 |

| 00000003 |

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002

B4
44

OPCODE FOR CLEAR WORD INSTRUCTION
INDEX MODE, REGISTER R4

AUTODECREMENT MODE, REGISTER R2

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-13 ■ Autodecrement Index Mode Instruction

Absolute Index Mode. See Example 5-10.

Example 5-10 ■ Absolute Index Mode Instruction
CLRL

«#tX1012 CR23

3-26 ■ The Instruction Characteristics

Figure 5-14 shows a clear longword instruction using absolute indexed mode.
The base of 00001012 (hexadecimal) is indexed by R2 that contains 5.
Because a longword data type is specified, 5 x 4 = 14 (hexadecimal), which
becomes the index value. This value is added to 00001012 (hexadecimal) yield¬
ing 0001026 (hexadecimal). This is the operand address, and four bytes are
cleared because a longword data type has been specified.

ADDRESS
SPACE

f 00000005 |
5i6 x 4 = 1416

00001012
00000014
00001026

BEFORE INSTRUCTION EXECUTION

ADDRESS
SPACE
00001026
00001027
00001028
00001029

R2
| 00000005 ]

AFTER INSTRUCTION EXECUTION

Figure 5-14 ■ Absolute Index Mode Instruction

Displacement Index Mode. See Example 5-11.
Example 5-11 ■ Displacement Index Mode Instruction

CLRQ

2CRDCR31

Figure 5-15 shows a clear quadioord instruction using displacement index
mode. The byte displacement of 2 is added to the contents of register R1. The
index, calculated as 28, is added to this address. Because a quadword was spec¬
ified, this location and the next seven locations are cleared.

5-27

ADDRESS
SPACE
0000402A
0000402B

24
68

0000402C
0000402D
0000402E
0000402F

13
57

00004030
00004031

R1
00004000

00000005

516 x 8 BYTES PER QUADWORD
= 2816 (INDEX)

62
43
34
47

00004000

00000002

CONTENTS OF R1
BYTE DISPLACEMENT

00004002
00004002
00000028

OPERAND ADDRESS
INDEX

0000402A

INDEXED OPERAND ADDRESS

BEFORE INSTRUCTION EXECUTION

ADDRESS
SPACE

0000402A

| 00004000 I

| 00000005 |

0000402B
0000402C
0000402D
0000402E
0000402F
00004030
00004031

00
00
00
00
00
00
00

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001
00003002

7C
43
61

OPCODE FOR CLEAR QUADWORD
INDEX MODE, REGISTER R3
REGISTER DEFERRED MODE, REGISTER R1

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-15 ■ Displacement Index Mode Instruction

Displacement Deferred Index Mode. See Example 5-12.

Example 5-12 ■ Displacement Deferred Index Mode Instruction

MOVL

3tX14CRl)CR31#R5

5-28 • The Instruction Characteristics

Figure 5-16 shows a move longivord instruction using displacement deferred
indexed addressing. The displacement of 14 is added to the contents of regis¬
ter Rl. The sum is the address 00001026 (hexadecimal). The contents of this
location yield the operand address (44332211 (hexadecimal)). This quantity is
added to the index yielding the indexed operand address of 44332221 (hexa¬
decimal). The contents of this address are then moved into register R5.

ADDRESS
SPACE
00001012
00001013
00001014

12
34

00001015

| 00001012 |
R3
| 00000004 |

416 x 4 BYTES PER LONGWORD
= 1016 (INDEX)

R5
| 00000000 |

•

00001026
00001027

11
22

00001012
00000014

CONTENTS OF Rl
DISPLACEMENT

00001028
00001029

33
44

00001026

ADDRESS OF OPERAND ADDRESS

44332221
44332222

01
23
45
67
89

O
P
> E
l R

44332211
00000010

OPERAND ADDRESS
INDEX

f A

44332221

INDEXED OPERAND ADDRESS

44332223
44332224
44332225

J N
D

BEFORE INSTRUCTION EXECUTION

|~~00001012 |
R3
[~~00000004 |
R5
| 67452301 1

AFTER INSTRUCTION EXECUTION

Figure 5-16 ■ Displacement Deferred Index Mode Instruction

Literal Mode. Literal mode addressing provides an efficient means of specify¬
ing integer constants in the range from 0 to 63. This is called short literal. Lit¬
eral values greater than 63 are obtained by using the program counter in
autoincrement mode (immediate mode). For predefined values, the assembler
chooses between short literal and immediate modes. The format for short lit¬
eral operands is shown in Figure 3-17. Bits 7 and 6 are always set to zero.
Figure 3-18 shows some short literals (14, 30, 46, and 62). To specify literal
mode, prefix the literal with St#.

MODE SPECIFIER
__A__
"\

4_0

-1--1-1_I_I_I_

Figure 5-17 ■ Short Literal Operand

MODE
SPECIFIER = 0
_A_
*\

0 ( 0

RANGE OF MODE SPECIFIER = 0
ISO - 1510

1110
1
1
1
J
V

141 o = 0E16
MC)DE
SPECIF IER = 1
v._
r
a

0 ( 0

RANGE OF MODE SPECIFIER = 1
IS 16 - 3110

11110
i
i
i
i

3010 = 1Ei6
MC)DE
SPECIF IER = 2
j _
\

RANGE OF MODE SPECIFIER = 2
IS 32 - 4710

10
1110
1
1
1
1
1
V

46-iq = 2E16
MO DE
SPECIFI ER = 3
j c.
r
^

RANGE OF MODE SPECIFIER = 3

111110
-1-1_1_1_1_ IS 48 - 6310
6210 — 3E16

Figure 5-18 ■ Typical Short Literal Operands

5-30 ■ The Instruction Characteristics

Floating-point literals as well as short literals can be expressed. The floating¬
point literals are listed in Table 5-4. For operands of the short floating type,
the 6-bit literal field in the operand specifier is composed of two 3-bit fields.
The field marked EXP designates the exponent column and FRAC designates
the fraction columns. See Figure 5-19.

o
FRAC

EXP

Figure 5-19 ■ Literal Field

The 3-bit EXP field and 3-bit FRAC field are used to form an F_floating or
D_floating operand as shown in Figure 5-20. Bits 63:32 are not present in
an F_floating operand. G_floating and H_floating operands can be
formed in analogous ways using the EXP and FRAC fields.

EXP
15

10^9

FRAC
7^

3_0

Figure 5-20 ■ D_floating and F_floating Operands in Literal Mode

Bits 3 through 5 of the EXP field are stored in bits 7 through 9, respectively,
of the floating operand. (See Figure 5-21.) Bits 0 through 2 of the FRAC field
are stored in bits 4 through 6 in the floating operand. The decimal values that
can be stored are given in Table 5-4.

5-31

LITERAL MODE
7

Figure 5-21 ■ Floating Operand Bit Storage

The EXP field is expressed in excess 128 notation. In this notation, an offset
of 128 is added to the exponent. For example, an exponent of 0 is represented
as 128 or 10000000 (binary), while an exponent of 3 is represented as 131 or
10000011 (binary).
Assume you want to express the floating-point literal of 64. Find the integer
64 in the table. It is in the 7 row of EXP and the 0 column of the fraction
columns. Therefore, 7 is the value of the exponent field and 0 is the value of
the fraction field.

Table 5-4 ■ Floating Literals
Exponent

Fraction

1/2

9/16

5/8

11/16

3/4

13/16

7/8

15/16

1-1/8

1-1/4

1-3/8

1-1/2

1-5/8

1-3/4

1-7/8

2-1/4

2-1/2

2-3/4

3-1/4

3-1/2

3-3/4

4-1/2

5-1/2

6-1/2

7-1/2

104

112

120

5-32 ■ The Instruction Characteristics

Example 5-13 ■ Literal Mode Instruction

MOVL

St#9;R4

Figure 5-22 shows a move long instruction using literal mode. The literal 9 is
transferred to register R4.

5_0_

0
0
LITERAL
-1--I_I—.I_I_I_

OPERAND SPECIFIER FORMAT

f 00000000 |
BEFORE INSTRUCTION EXECUTION
R4
f00000009 1

AFTER INSTRUCTION EXECUTION
ADDRESS
SPACE
00003000
00003001
00003002

OPCODE FOR MOVE LONG INSTRUCTION
LITERAL 9
REGISTER MODE, REGISTER R4

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-22 ■ Literal Mode Instruction

Register Mode. With register mode, any of the general registers may be used
as simple accumulators and the operand is contained in the selected register.
Because they are hardware registers within the processor, they provide speed
advantages when used for operating on frequently accessed variables.
This mode can be used with operand specifiers using read, write, or modify
access but cannot be used with the address access type. Otherwise, an illegal
addressing mode fault occurs. The program counter cannot be used in this
mode. If the program counter is read, the value is unpredictable. If the pro¬
gram counter is written, the next instruction executed or the next operand
specified is unpredictable. Similarly, if the program counter is used in register
mode for a write-access operand that takes two adjacent registers, the con¬
tents of register 0 are unpredictable.

5-33

If register 12, 13, the stack pointer, or program counter is used in register
mode addressing for an operand that takes four adjacent registers, the results
are unpredictable. If the program counter is used in register mode for a write
access that requires four adjacent registers, the contents of registers 0, 1, and
2 are unpredictable. Likewise, if register 13 is used in register mode for a write
access that takes four adjacent registers, the contents of register 0 are unpre¬
dictable. If the stack pointer is used in register mode for a write access that
takes four adjacent registers, the contents of registers 0 and 1 are unpredict¬
able.
The stack pointer cannot be used in this mode for an operand that takes two
adjacent registers because that implies a direct reference to the program coun¬
ter and the results are unpredictable.
The operand is the content of register n, or R[n + 1] concatenated with Rn for
quadword, D_floating, and certain field operations. The following list iden¬
tifies the single- and multiple-register operand format.
One register operand = Rn
Two register operand = R[# + 1]’R[«]
Four register operand = R[« + 3]’R[» + 2]’R[» + 1]’R[«]

Example 5-14 ■ Register Mode Instruction

V\0W

R1, R2

Figure 5-23 shows a move word instruction using register mode. The content
of register 1 is the operand. The move word instruction transfers the least sig¬
nificant half of register 1 to the least significant half of register 2. The upper
half of register 2 is unaffected.
Register Deferred Mode. The register deferred mode provides one level of indi¬
rect addressing over register mode. That is, the general register contains the
address of the operand rather than the operand itself. The deferred modes are
useful when dealing with an operand whose address is calculated. The pro¬
gram counter cannot be used in register deferred mode addressing as the
results are unpredictable. To indicate the register deferred mode, enclose the
register operand in parentheses. See Example 5-15 for the format of the
instruction.

3-34 ■ The Instruction Characteristics

Rn
V_

MODE-'

*- REGISTER

SPECIFIER

OPERAND SPECIFIER FORMAT

BEFORE INSTRUCTION EXECUTION

AFTER INSTRUCTION EXECUTION

00003000

OPCODE FOR MOVE WORD INSTRUCTION

00003001
00003002

51
52

OPERAND SPECIFIER. SOURCE; REGISTER MODE 1
OPERAND SPECIFIER, DESTINATION; REGISTER MODE 2

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 3-23 ■ Register Mode Instruction

Example 5-15 ■ Register Deferred Mode Instruction

CLRQ

CR4)

5-35

Figure 5-24 shows a clear quadword instruction using register deferred mode.
Register 4 contains the address of the operand. The instruction specifies that
the byte at this address plus the following seven bytes are to be cleared.

MODE
SPECIFIER

OPERAND SPECIFIER FORMAT

00001010
00001011
00001012
00001013
00001014

00001015
00001016
00001017

56
76
65

CD
EF
12
34

BEFORE INSTRUCTION EXECUTION

X ADDRESS
SPACE
00001010
00001011
00001012
00001013
00001014
00001015
00001016
00001017

00
00
00
00

\
X

R4
] 00001010 I

00
00
00
00

AFTER INSTRUCTION EXECUTION

ADDRESS
SPACE
00003000
00003001

7C
64

OPCODE FOR CLEAR QUAD INSTRUCTION
OPERAND SPECIFIER FOR REGISTER DEFERRED

MACHINE CODE: ASSUME STARTING LOCATION 00003000

Figure 5-24 ■ Register Deferred Mode Instruction

5-36 ■ The Instruction Characteristics

■ Program Counter Register Addressing
Register 15 is used as the program counter. It can also be used as a register in
addressing modes. The processor increments the program counter as the
opcode, operand specifier, and immediate data or address of the instruction
are evaluated. The amount that the program counter is incremented is deter¬
mined by the opcode, number of operand specifiers, and so on.
The program counter can be used with all the VAX addressing modes except
register or index mode. In those two modes, the results are unpredictable. The
addressing mode register functions are shown in Table 5-5. The following
modes use the program counter as a general register.
■ Absolute Mode—same as> autoincrement deferred mode
■ Immediate Mode—same as autoincrement mode
■ Relative Mode—same as displacement mode
■ Relative Deferred Mode-—same as displacement deferred mode.

Table 5-5 ■ Addressing Mode Functions
Mode

Assembler Notation

Note

Absolute

$#Location

Byte Relative

BtG (R)

Byte Relative Deferred

SBtG (R)

Immediate

IttlOperand

Longword Relative

LtG CR)

Longword Relative Deferred

#LtG (R)

Word Relative

WtG <R>

Word Relative Deferred

<3WtG (R)

* Absolute mode is the same as autoincrement mode with the program counter used as a
general register. Absolute address follows address mode.
t Relative mode is the same as displacement mode with the program counter used as a
general register. Displacement is added to current value of PC to obtain operand
address.

X Relative deferred mode is the same as displacement deferred mode with the program
counter used as a general register. Displacement is added to current value of PC to yield
address of operand address.
§ Immediate mode is the same as autoincrement mode with the program counter used
as a general register. The constant operand follows the address mode.

3-37

When a standard program is available for different users, it is often helpful to
be able to run it at different areas of virtual memory. VAX computers can
accomplish the relocation of a program very efficiently through the use of posi¬
tion-independent code. If an instruction and its objects are moved in such a
way that the relative distance between them is not altered, the same offset
relative to the program counter can be used in all positions in memory.
Absolute Mode. This mode is autoincrement deferred when using the program
counter as a general register. The contents of the location following the
addressing mode are taken as the operand address. This is interpreted as an
absolute address. See Example 5-16 for the format of the operand.

Example 5-16 ■ Absolute Mode Instruction

CLRL

e#tX674533

Figure 5-25 shows a clear longujord instruction using the absolute addressing
mode. This instruction causes the location or locations following the address¬
ing mode to be taken as the address of the operand. In this example, the
address is 00674533 (hexadecimal). The longword operand for this address is
cleared.
Immediate Mode. The immediate addressing mode is autoincrement mode
when the program counter is used as a general register. The contents of the
location following the addressing mode are immediate data. Immediate mode
may not be used for operands of the modify or write access types. If immedi¬
ate mode is used for one of those operands, the value of the data read is unpre¬
dictable. So is the address at which the operand is written. See Example 5-17
for the format of the operand.

5-38 ■ The Instruction Characteristics

ADDRESS

MODE-1
SPECIFIER

1- REGISTER
SPECIFIER

OPERAND SPECIFIER FORMAT

ADDRESS
SPACE

00001012
00001013
00001014

D4
9F
33
45
67
00
55

00001015
00001016
00001017
00001018

OPCODE FOR CLEAR LONG INSTRUCTION
OPERAND SPECIFIER, AUTOINCREMENT DEFERRED PC (ABSOLUTE)

► OPERAND ADDRESS

BEFORE INSTRUCTION EXECUTION

00674533
00674534
00674535
00674536

oo
oo
oo
oo

AFTER INSTRUCTION EXECUTION

Figure 5-25 ■ Absolute Mode Instruction

Example 5-17 ■ Immediate Mode Instruction

MOVL

#6,R4

Figure 5-26 shows a move longword instruction using immediate mode. The
immediate data (00000006(hexadecimal)) following the mnemonic and oper¬
and specifier are moved to register R4.

5-39

CONSTANT
SIZE DEPENDS
ON CONTEXT
MODE
SPECIFIER

OPERAND SPECIFIER FORMAT

00001012
00001013
00001014
00001015
00001016
00001017
00001018

DO
8F
06
00
00
00
54

OPCODE FOR MOVE LONG INSTRUCTION
OPERAND SPECIFIER, AUTOINCREMENT PC (IMMEDIATE)

-► IMMEDIATE DATA

R4
I 00000000 I
1-1

BEFORE INSTRUCTION EXECUTION

00001014
00001015
00001016
00001017
R4
| 00000006 1

AFTER INSTRUCTION EXECUTION

Figure 5-26 ■ Immediate Mode Instruction

Relative Mode. This mode is the displacement mode with the program coun¬
ter used as a general register. The displacement follows the operand specifier
and is added to the program counter. The sum of which becomes the address
of the operand. This mode is useful for writing position-independent code
because the location referenced is always fixed. See Example 5-18 for the for¬
mat of the operand.

Example 5-18 ■ Relative Mode Instruction

MOVL

tX2016,R4

5-40 • The Instruction Characteristics

Figure 5-27 shows a move longword instruction using relative mode. The word
following the address mode is added to the program counter to obtain the
address of the operand. In this example, the program counter is pointing to
location 00001016 (hexadecimal) after the first operand specifier is evalu¬
ated. The word following the mnemonic and first operand specifier is
00001000 (hexadecimal), and is added to the program counter yielding
00002016 (hexadecimal). This value represents the address of the longword
operand (00860077 (hexadecimal)). Then this operand is moved to register
R4. The program counter contains 00001017 (hexadecimal) after instruction
execution.

3
SPECIFIER EXTENSION IS
BYTE DISPLACEMENT
SPECIFIER EXTENSION IS
WORD DISPLACEMENT
SPECIFIER EXTENSION IS
LONGWORD DISPLACEMENT

DISPLACEMENT

MODE
SPECIFIER

1-REGISTER
SPECIFIER

A = BYTE DISPLACEMENT
C = WORD DISPLACEMENT
E = LONGWORD DISPLACEMENT

OPERAND SPECIFIER FORMAT

pr
00001012
00001013
00001014
00001015
00001016

ADDRESS
SPACE
DO
CF
00
10
54

OPCODE FOR MOVE LONG
1 00000000 1
DISPLACEMENT MODE WITH PC
- DISPLACEMENT = 1000
REGISTER MODE. REGISTER R4
00001016

1000
00002016

R4
[ 00860077

AFTER INSTRUCTION EXECUTION

Figure 5-27 ■ Relative Mode Instruction

5-41

Relative Deferred Mode. This mode is similar to relative mode except that the
displacement following the addressing mode is added to the prograjn counter.
The updated contents of the program counter are the address of the first byte
beyond the specifier extension. This addressing mode is useful when process¬
ing tables of addresses. See Example 5-19 for the format of the operand.

Example 5-19 ■ Relative Deferred Mode Instruction

MOML

«tX2058,R2

Figure 5-28 shows a move long instruction where 00002050 (hexadecimal) rep¬
resents the address of the operand. A byte displacement is selected by the
assembler because the displacement is within 128 addressable bytes. When
the displacement is evaluated, the program counter is pointing to 00002003
(hexadecimal). The displacement of 4D is added to the current value of the
program counter yielding the address of 00002050 (hexadecimal). Then the
contents of this address are used as the effective operand address (00006000
(hexadecimal), and the operand of 1234567 (hexadecimal) is moved to regis¬
ter R2.
Branch Mode Addressing
In branch mode displacement addressing, the byte or word displacement is
sign-extended to 32 bits and added to the updated content of the program
counter. The updated content of the program counter is the address of the
first byte beyond the operand specifier. The assembler notation for byte and
word branch displacement addressing is A where A is the branch address.
Note that the branch address and not the displacement is used. See Figure
5-29 for the branch mode instruction operand specifier format.

5-42 ■ The Instruction Characteristics

SPECIFIER EXTENSION IS

DISP

DISPLACEMENT

^'mODE^^
SPECIFIER

WORD DISPLACEMENT DEFERRED
o

F
CO

SPECIFIER EXTENSION IS
BYTE DISPLACEMENT DEFERRED

DISP
39

DISP

SPECIFIER EXTENSION IS
LONGWORD DISPLACEMENT DEFERRED
— REGISTER
SPECIFIER

B = BYTE DISPLACEMENT DEFERRED
D = WORD DISPLACEMENT DEFERREED
F = LONGWORD DISPLACEMENT DEFERRED

OPERAND SPECIFIER FORMAT

PC^
00002000
00002001
00002002
00002003

MOVE LONG OPCODE
BYTE DISPLACEMENT FROM PC
AMOUNT OF DISPLACEMENT

DO
BF
4D
52

00000000 |

DISPLACEMENT
00002050
00002051
00002052

CALCULATION
l

OPERAND

[

ADDRESS

00002053

00006000
00006001
00006002
00006003

00002003
4D
00002050

OPERAND

BEFORE INSTRUCTION EXECUTION

R2
| 01234567 |

AFTER INSTRUCTION EXECUTION

Figure 5-28 ■ Relative Deferred Mode Instruction

5-43

DISPLACEMENT

Figure 5-29 ■ Branch Mode Instruction Operand Specifier Format

Branch instructions are most frequently used after instructions like compare
(CMP). They are used to cause different actions depending on the results of
the compare instruction. Example 5-20 causes a branch to location NOT if C is
not a digit; that is, C is treated as an unsigned number outside the range 0
through 9. See Example 5-21 for a typical branch on bit instruction applica¬
tion.

Example 5-20 ■ Unsigned Branch Mode
CURB

C,#tA/0/

i Compare C and ASCII representation of digit.

BLSSU

NOT

* Branch to location NOT if less than unsigned 8.

CURB

C,#tA/9/

i Compare C and ASCII representation of digit 9.

BGTRU

NOT

i Branch to location NOT if greater than an unsigned 9.

Example 5-21 ■ Branch on Bit Instruction
BBS

#2,B,X

; Branches toXifbit#2inBis set.

BBSC

#2;B> X

> Branches to X if bit #2 in B is set and bit is then cleared.

BLBS

B,X

; Branches to X if bit 0 of B is set.

Chapter 6 ■ Functions of the Instruction Set

A major goal of the VAX architecture is to provide an instruction set that is
symmetrical with respect to data types. For example, there are separate add
instructions for seven integer and floating-point data types. Each is available
in both two-operand and three-operand format. Other symmetrical opera¬
tions include data movement, data conversion, data testing, and computation.
Thus both assembly language programmers and compilers can choose the best
instruction to use independent of the data type.
Instruction mnemonics are formed by combining an base operation abbrevia¬
tion with a data-type suffix. Conversion instructions are formed by adding
suffixes for both the source and destination data types. For example, the basic
convert instruction is CVT. To convert G

floating to F

floating, one must

affix a G for the source and an H for the destination data type. This forms the
mnemonic CVTGH.
Computation instructions have an additional suffix to indicate the choice
between two- and three-operand instructions. For example, the multiply word
instruction uses the mnemonic MULW. A two-operand instruction uses
MULW2 and a three-operand instruction uses MULW3.
Special instruction mnemonics have been chosen for similarity. For example,
a move word instruction has the mnemonic MOVW, while a move F_floating
instruction has the mnemonic MOVF. Some instructions span several catego¬
ries. For example, the compare instruction is found in character string, deci¬
mal string, floating point, integer, and variable length bit field instructions.
Chapter 9 contains detailed descriptions of each instruction. This chapter
describes the general functioning of the types of instructions.
Instructions are described in this chapter according to categories. They are
Address, Arithmetic, Character String, Control, Cyclic Redundancy Check,
Decimal String, Edit, Floating Point, Index, Integer, Logic, Multiple Regis¬
ter, Privileged, Procedure Call, Processor Status Longword, Queue, and Vari¬
able Length Bit Field.

■ Address Instructions
Address instructions are used to manipulate addresses. There are two basic
address instructions: move address (MOVA) and push address (PUSHA). The
move address instruction replaces one address with another. Push address
instructions write an address onto a stack.

6-2 ■ Functions of the Instruction Set

There are suffixes for each type of data. The suffix B is used to specify byte
data, D for D_floating data, F for F_floating data, G for G— floating
data, L for longword data, O for octawords, Q for quadwords, and W for
words. In order to move an address in F_floating data, the mnemonic MOVA
would have an F affixed to it forming the instruction MOVAF. Other mne¬
monics are similarly constructed.

Arithmetic Instructions
Arithmetic instructions are add, subtract, multiply, and divide. The instruc¬
tions are available in both two- and three-operand forms for each applicable
data type. As input, the three-operand form takes the values of the first two
operands, performs the operation, and stores the result in the third operand.

Character String Instructions
The character string instructions are
■ Compare character (CMPC).
■ Locate character (LOCC).
■ Match character (MATCHC).
■ Move character (MOVC).
■ Move translated characters (MOVTC).
■ Move translated until character (MOVTUC).
■ Scan characters (SCANC).
■ Skip characters (SKPC).
■ Span characters (SPANC).

A character string is specified by two operands—an unsigned word operand
giving the length of the character string in bytes and the address of the lowest
addressed byte of the character string. This is specified by a byte operand of
address access type.

6-3

Each of the character string instructions uses general registers to store a con¬
trol block that maintains updated addresses and state information during the
execution of the instruction. At completion, these registers are available to
software to use as string specification operands for a subsequent instruction.
During the execution of the instructions, pending interrupt conditions are
tested. If any are found, the control block is updated, the first part done bit of
the processor status longword is set, and the instruction is interrupted. After
the interruption, the instruction resumes transparently. The format of the con¬
trol block is shown in Figure 6-1.

0
LENGTH 1
ADDRESS 1

: RO
: R1

LENGTH 2
ADDRESS 2

: R2
: R3

LENGTH 3
ADDRESS 3

. R4
: R5

Figure 6-1 ■ Control Block Format

The fields LENGTH 1, LENGTH 2, and LENGTH 3 (if required) contain the
number of bytes remaining to be processed in the first, second, and third
string operands, respectively. The fields ADDRESS 1, ADDRESS 2, and
ADDRESS 3 (if required) contain the address of the next byte to be processed

in the first, second, and third string operands, respectively.

■ Control Instructions
Control instructions include case, loop, subroutine, and transfer instructions.
In most situations, execution speed is improved if the target of a control
instruction is on an aligned longword boundary. But this is not a requirement.

6-4 ■ Functions of the Instruction Set

Case Instructions
Dispatching to a routine based on the value of a variable occurs frequently
enough that some high-level languages include special constructs to handle it;
for example, the computed GOTO in FORTRAN and the case statement in
PASCAL. Because of this, the VAX instruction set includes a case instruction
so that such control structures can be represented efficiently. Not only does
case handle the transfer of control but it also handles the initialization and
bounds checking for the index variable.
The objective of the case instruction is to transfer control to one of several
locations based on the value of the integer selector operand. The base operand
specifies the lower bound for selector. Following the case instruction is a table
of word displacements for the branch locations. Just as the displacements in
branch instructions are added to the program counter to give the branch desti¬
nation, these word displacements are added to the address of the first displace¬
ment to form the case branch destinations.
Loop Control Instructions
There are three loop control instructions—add compare and branch (ACB), add
one and branch (AOB), and subtract one and branch (SOB). The instructions
efficiently implement the general FOR or DO loops in high-level languages.
Specified operands are manipulated and if certain results are obtained, the
program counter is loaded with the result of the manipulation.
The add compare and branch instruction can accommodate seven types of data
—byte, word, longword, D_floating, F_ floating, G_floating, and
H_floating. The add one and branch instruction adds a one to the specified
index operand. The sum of the operation replaces the operand. The subtract
one and branch instruction removes a one from the specified index operand.
The remainder of the operation replaces that operand.
Subroutine Call Instructions
Two special types of branch and jump instruction are provided for calling
subroutines—branch to subroutine and jump to subroutine. Both instructions
save the contents of the program counter on the stack before loading the coun¬
ter with the new address. With branch to subroutine instructions, you can sup¬
ply either a byte or word displacement.
This shortcut to subroutine calling is complemented by the return from subrou¬
tine instruction. The instruction removes the first longword of the stack and
loads it into the program counter. Because the branch to subroutine instruc¬
tion is either two or three bytes long and the return from subroutine instruction
is one byte long, extremely efficient programs can be written using subrou¬
tines.

6-5

The breakpoint fault instruction is used in conjunction with the trace bit to
implement debugging facilities.
Transfer Instructions
The two basic types of control transfer instructions are branch and jump
instructions. Both branch and jump load new addresses in the program coun¬
ter. With branch instructions, you supply a displacement (offset) that is added
to the program counter to obtain the new address. With jump instructions,
you supply the address you want loaded, using one of the normal addressing
modes.
Because most transfers are to locations relatively close to the current instruc¬
tions, and because branch instructions take less space than jump instructions,
the processor offers a variety of branch instructions to choose from. There are
two unconditional branch instructions and many conditional branch instruc¬
tions, such as branch on less than and branch on less than unsigned.
The unconditional branch instructions allow you to specify a byte or word dis¬
placement. This allows you to branch to locations as far from the current loca¬
tion as 32,767 bytes in either direction. For control transfers to locations
farther away, use the jump instruction.

■ Cyclic Redundancy Check Instruction
The cyclic redundancy check (CRC) is an error detection method involving a
division of the data stream by a CRC polynomial. In memory, the data stream
is represented as a standard VAX string. Error detection is accomplished by
computing the CRC polynomial at the source and again at the destination. The
CRC is compared at each end. The CRC that is selected should minimize the
number of undetected block errors of specific lengths.
The operands of the instruction are a string descriptor, a 16-longword table,
and an initial CRC. The string descriptor is a standard VAX operand pair of
the length of the string in bytes (up to 65,535) and the starting address of the
string. The contents of the table are a function of the CRC polynomial to be
used. It can be calculated from the polynomial by a variety of algorithms. The
initial CRC figure is used to start the polynomial correctly. Typically, it has
the value 0 or -1 but would be different if the data stream were represented
by a sequence of noncontiguous strings.

6-6 ■ Functions of the Instruction Set

The CRC instruction operates by scanning the string and for each byte of the
data stream including it in the CRC being calculated. The byte is included by
XORing it to the right eight bits of the CRC. Then the CRC is shifted right
one bit, inserting zero on the left. The rightmost bit of the CRC (lost by the
shift) is used to control the XORing of the CRC polynomial with the resultant
CRC. If the bit is set, the polynomial is XORed with the CRC. Then the CRC
is again shifted right and the polynomial is conditionally XORed with the
result a total of eight times. Actual algorithms used can shift by one, two, or
four bits at a time using the appropriate entries in a specially constructed
table. The instruction produces a 32-bit CRC. For shorter polynomials, the
result must be extracted from the 32-bit field. Data streams must be multiples
of eight bits in length. If they are not, they must be right-adjusted in the
string with leading 0 bits.

■ Decimal String Instructions
Decimal string instructions operate on packed decimal strings. They treat dec¬
imal strings as integers with the decimal point assumed immediately beyond
the least significant digit of the string. If a string in which a result is to be
stored is longer than the result, its most significant digits are filled with zeros.
Instructions are provided to convert between packed decimal and trailing
numeric string (overpunched or zoned) and leading separate numeric string for¬
mats. Where necessary, a specific data type is identified. Where the phrase
decimal string is used, it means any of the three previously mentioned data
types. The instructions are
■ Add packed (ADDP).
■ Arithmetic shift and rounded packed (ASHP).
■ Compare packed (CMPP).
■ Convert leading separate numeric string to packed decimal string (CVTSP).
■ Convert longword integer to packed decimal string (CVTLP).
■ Convert packed decimal to leading separate string (C VTPS).
■ Convert packed decimal string to a longword (C VTPL).
■ Convert packed decimal string to a trailing numeric string (C VTPT).
■ Convert trailing numeric to packed decimal string (C VTTP).
■ Divide packed (DIVP).
■ Move packed (MOVP).

6-7

■ Multiply packed (MULP).
■ Subtract packed (SUBP).

A decimal string is specified by two operands.
■ For decimal strings, the length is the number of digits in the string. The
number of bytes in the string is a function of the length and the type of
decimal string referenced.
■ The address of the lowest addressed byte of the string. This byte contains
the most significant digit for trailing numeric and packed decimal strings.
This byte contains a sign for leading separate numeric strings. The address
is specified by a byte operand of address access type.

Each of the decimal string instructions uses general registers 0 through 3 or 0
through 5 to contain a control block that maintains updated addresses and
state during the execution of the instruction. At completion, the registers con¬
taining addresses are available to the software to use as string specification
operands for a subsequent instruction on the same decimal strings.
During the execution of the instructions, pending interrupt conditions are
tested and, if any are found, the control block is updated. The first part done
bit is set in the processor status longword, and the instruction is interrupted.
After the interruption, the instruction resumes transparently. The format of
the control block at completion is shown in Figure 6-2.

: RO
: R1
: R2

: R4
: R5

Figure 6-2 ■ Control Block after Instruction Execution

6-8 ■ Functions of the Instruction Set

The fields ADDRESS 1, ADDRESS 2, and ADDRESS 3 (if required) contain
the address of the byte containing the lowest addressed byte in the first, sec¬
ond, and third (if required) string operands, respectively.
Decimal overflow occurs if the destination string is too short to contain all the
nonzero digits of the result. On overflow, the destination string is replaced by
the correctly signed least significant digits of the result even if the result is -0.
Note that neither the high nibble of an even length packed decimal string nor
the sign byte of a leading separate numeric string is used to store result digits.
A zero result has a positive sign for all operations that complete without deci¬
mal overflow. However, when digits are lost because of overflow, a zero result
receives the sign of the correct result.
A decimal string with a negative zero value is treated as identical to a decimal
string with a positive zero value. For example, positive zero is equal to nega¬
tive zero in a compare instruction. Similarly, when condition codes are
affected on a negative zero result, they are affected as if the result were posi¬
tive.
A reserved operand fault occurs if the length of a decimal string operand is
outside the range of 0 through 31, or if an invalid sign or digit is encountered
in a CVTSP or CVTTP instruction.
The result of any operation is unpredictable if any source decimal string oper¬
and contains invalid data. Except for CVTSP and CVTTP instructions, the dec¬
imal string instructions do not verify the validity of source operand data. If
the destination operands overlap any source operands, the result of the opera¬
tion is unpredictable. Destination strings, registers used by the instruction,
and condition codes are unpredictable when a reserved operand fault occurs.
Packed decimal strings generated by the decimal string instructions always
have the preferred sign representation—12 for positive and 13 for negative.
An even length packed decimal string is always generated with a 0 digit in the
high nibble of the first byte of the string. A packed decimal string contains an
invalid nibble if
■ A digit occurs in the sign position.
■ A sign occurs in a digit position.
■ A nonzero nibble occurs in the high-order nibble of the lowest addressed
byte for an even length string.

The length of a packed decimal string can be zero. In this case, the value is
zero (plus or minus) and one byte of storage is occupied. This byte must con¬
tain a 0 digit in the high nibble and the sign in the low nibble.

6-9

The length of a trailing numeric string can be zero. In this case, no storage is
occupied by the string. If a destination operand is a zero-length trailing
numeric string, the sign of the operation is lost. Memory access faults do not
occur when a zero-length trailing numeric operand is specified because no
memory reference occurs.
The length of a leading separate numeric string can be zero. In this case, one
byte of storage is occupied by the sign. Memory is accessed when a zero-length
operand is specified, and a reserved operand fault occurs if an invalid sign is
detected. The value of a zero-length decimal string is zero.

■ Edit Instruction
The edit instruction implements the common editing functions that occur in
handling fixed format output. The instruction operates by converting a
packed decimal string to a character string generating characters for the out¬
put. But the instruction can be used for other applications. When converting
digits, options include leading zero fill; leading zero protection; insertion of
floating sign, floating currency symbol, or special sign representations; and
blanking an entire field when it is zero.
The operands to the EDITPC instruction are an input-packed, decimal-string
descriptor, a pattern specification, and the starting address of the output str¬
ing. The packed decimal descriptor comprises a standard VAX operand pair of
the length of the decimal string of up to 31 digits and the starting address of
the string. The pattern specification is the starting address of a pattern opera¬
tion editing sequence that is interpreted in much the same way normal instruc¬
tions are interpreted. Only the starting address of the output string is
required because the pattern unambiguously defines the length.
While the EDITPC instruction is operating, it manipulates two character reg¬
isters and the four condition codes. One character register contains the fill
character. Normally, the character is an ASCII blank character. But the char¬
acter may be changed to an asterisk (*) for check protection. The other charac¬
ter register contains the sign character. Initially, the character is either an
ASCII blank or a minus sign depending upon the sign of the input. The sign
register can be changed to allow other sign representations such as a plus or
minus sign or plus/blank, and can be manipulated to output special notations
such as CR for a credit ( + ) or DB for a debit ( - ). The sign register can also be
changed to the currency sign in order to implement a floating currency sign.

6-10 ■ functions of the Instruction Set

After execution, the condition codes note the sign of the input, the presence
of a nonzero source, an overflow condition, and the presence of significant
digits. Condition code N is determined at the start of the instruction and is
not changed except for correcting a negative zero input. The other condition
codes are computed and updated as the instruction execution proceeds. When
the EDITPC instruction terminates, registers 0 through 5 contain the conven¬
tional values after a decimal instruction.

■ Floating-point Instructions
Mathematically, a floating-point number may be defined as having the form:
± (2K)/where K is an integer and/is a positive fraction. For a nonvanishing
number, K and / are uniquely determined by imposing the condition:

1/2 </< 1.
The fraction factor (/) of the number is then said to be binary normalized.
For the number 0,/must be assigned the value 0, and the value of K is indeter¬
minate.
The VAX floating-point data formats are derived from this mathematical rep¬
resentation for floating-point numbers. Four types of floating-point data are
provided; F_floating numbers are 32 bits long, D_floating and G_float¬
ing numbers are 64 bits long, and H_floating numbers are 128 bits long.
Because of the hidden bit, the fractional factor is not available to distinguish
between zero and nonzero numbers whose fractional factor is exactly one half.
Therefore VAX software reserves a sign-exponent field of zero for this pur¬
pose. Any positive floating-point number with biased exponent of zero is
treated as if it were an exact zero by the floating-point instruction set. In par¬
ticular, a floating-point operand, whose bits are all zero, is treated as zero.
This is the format generated by all floating point instructions for which the
result is zero.
A reserved operand is defined to be any bit pattern with a sign bit of 1 and a
biased exponent of zero. On VAX machines, all floating-point instructions
generate a fault if a reserved operand is encountered. Because a reserved oper¬
and has a biased exponent of 0, it can be internally generated only if overflow
occurs.
An instruction is defined to be exact if its result extended on the right by an
infinite sequence of zeros is identical to that of an infinite-precision calcula¬
tion involving the same operands. The prior accuracy of the operands is thus
ignored. For all arithmetic operations, except division, a 0 operand implies
that the instruction is exact. The same statement holds for division if the 0
operand is the dividend. If it is the divisor, division is undefined and the
instruction traps.

6-11

The add, subtract, multiply, and divide instructions, an overflow bit on the
left, and two guard bits on the right are necessary and sufficient to guarantee
return of a rounded result identical to the corresponding infinite-precision
operation rounded to the specified word length. Thus with two guard bits, a
rounded result has an error bound of one-half the least significant bit.
Note that an arithmetic result is exact if only no bits are lost in truncating the
infinite-precision result to the data length to be stored. The first bit lost in
truncating is called the rounding bit. The value of a rounded result is related
to the truncated result as follows.
■ If the rounding bit is 1, the rounded result is the truncated result incre¬
mented by a least significant bit.
■ If the rounding bit is 0, the rounded and truncated results are identical.

Rounding may be implemented by adding a one to the rounding bit and propa¬
gating the carry if it occurs. Note that a renormalization may be required after
rounding takes place. If this happens, the new rounding bit is zero so renor¬
malization can happen once only. To summarize the relations among trun¬
cated, rounded, and true (infinite-precision) results.
■ If a stored result is exact, then its rounded value = truncated value = true
value.
■ If a stored result is not exact, its magnitude is
— always less than that of the true result for truncating.
— always less than that of the true result for rounding if the rounding
bit is 0.
— greater than that of the true result for rounding if the rounding bit is 1.

To be consistent with the floating-point instruction set that faults on reserved
operands, software-implemented, floating-point functions should verify that
the input operands are not reserved. An easy way to do this is a move or test of
the input operands.
In order to facilitate high-speed implementations of the floating-point instruc¬
tion set, certain restrictions are placed on the addressing mode combinations
usable within a single floating-point instruction. These combinations involve
the logically inconsistent use of a value as both a floating-point operand and
an address.

6-12 ■ Functions of the Instruction Set

Specifically, if within the same instruction the contents of a specified register
are used as an F_floating point operand or part of a larger floating input
operand and as an address in an addressing mode that modifies that register,
the value of the floating-point operand is unpredictable. The operand speci¬
fier notation section describes the notation used for these instructions.
The VAX instruction set includes special floating-point instructions for mod¬
ulus (range reduction) and polynomial calculation to aid in the implementation
of mathematical functions, along with shift and rotate instructions.
The floating point instructions are
■ Add (ADD).
■ Clear (CLR).
■ Compare (CMP).
■ Convert (CVT).
■ Convert rounded (CVTR).
■ Divide (DIV).
■ Extended modulus (EMOD).
■ Move (MOV).
■ Move negated (MNEG).
■ Multiply (MUL).
■ Polynomial evaluation (POLY).
■

Subtract (SUB).

■ Test (TST).

■ Index Instruction
The index instruction calculates an index for an array of fixed-length data
types (integer and floating) and for arrays of bit fields, character strings, and
decimal strings. It accepts as arguments a subscript, lower and upper subscript
bounds, an array element size, a given index, and a destination for the calcu¬
lated index. It incorporates range checking within the calculation for highlevel languages using subscript bounds, and it aids index calculation optimiza¬
tion by removing invariant expressions.

6-13

■ Integer Instructions
The integer optimizations include an instruction to write a longword onto the
stack. Each integer data type includes operations that increment and decre¬
ment. The VAX instruction set includes special instructions to implement mul¬
tiple precision integer arithmetic. A special variant of integer add instruction
is an operation that adds a word under a memory interlock (for operating sys¬
tem counters in a multiprocessor system). The integer instructions are
■ Add aligned word under memory interlock (ADAWI).
■ Add with carry (ADWC).
■ Decrement (DEC).
■ Extended divide (EDIV).
■ Extended multiply (EMUL).
■ Increment (INC).
■ Push longword (PUSHL).
■ Subtract with carry (SBWC).

■ Logic Instructions
The logic computation instructions are for the three integer data types and are
bit set (inclusive OR), bit clear (complement AND), and exclusive OR. The
instructions are available in both two- and three-operand forms for each appli¬
cable data type. As input, the three-operand form takes the values of the first
two operands and stores the result in the third operand.
The logical operations are simple move, clear, arithmetic negate, and logical
complement. The logical complement operations are available only for the
three-integer data types because these are the logical types. Both negate and
complement include a move, rather than being restricted to altering an oper¬
and in place. VAX software has a large set of conversions covering almost all
data type pairs. In addition, special conversions exist to round floating data to
integer, and to extend unsigned integers to larger integers. The data compari¬
son and testing instructions are compare, test against zero, and multiple bit
testing. The logic instructions are
■ Arithmetic shift (ASH).
■ Bit clear (BIC).
■ Bit set (BIS).

6-14 ■ Functions of the Instruction Set

■ Fittest (BIT).
■ C/ttzr (CLR).
■ Compare (CMP).
■ Convert (CVT).
■ Exclusive OR (XOR).
■ Move (MOV).
■ Afcwe complemented (MCOM).
■ Move negated (MNEG).
■ Move zero-extended (MOVZ).
■ Rotate longword (ROTL).
■ Test (TST).

■ Multiple Register Instructions
Multiple register instructions save and restore several registers in one opera¬
tion. The save area is on the stack. The PUSHR instruction saves multiple regis¬
ters by pushing them onto the stack. The POPR instruction restores multiple
registers by popping them from the stack. A 16-bit mask operand specifies the
list of registers. This mask is a normal read operand. The mask can be calcu¬
lated or it can be an inline literal. When registers in the range RO through R5
only are being saved or restored, the mask can be expressed as a short literal.
The software standard for calling and signaling requires that registers be
saved in the call frame. With the exception of registers RO and Rl, any regis¬
ter manipulated by a PUSHR or POPR instruction must appear in the proce¬
dure entry mask. The architecture also requires that any registers between R2
and Rll that are modified by the procedure to be saved in the call frame by
setting up the appropriate entry mask. Registers RO and Rl are used to return
procedure status.
PUSHR or POPR instructions should be used to save and restore only those
registers specified in the procedure entry mask. If a procedure saves registers
that are not noted in the entry mask and that procedure receives an exception,
the procedure’s caller’s registers cannot be properly restored.

6-15

■ Privileged Instructions
The privileged instructions give upward and downward mobility through the
access modes, and provide a way to compare memory protection levels to the
access mode privilege of callers. The instructions are
■ Change mode (CHM).
■ Extended function call (XFC).
■ Haiti HALT).
■ Load process context (LDPCTX).
■ Move from processor register (MFPR).
■ Move to processor register (MTPR).
■ Probe (PROBE).
■ Return from Exception or Interrupt (REI).
■ Save process context (S VPCTX).

A change mode instruction is a special trap instruction that can be likened to
an operating system service call instruction. User access-mode software can
explicitly issue change mode instructions.
The extended function (XFC) instruction is used to request the services of non¬
standard microcode in the writeable control store or simulator software run¬
ning in kernel mode. The request is controlled by the system control block.
The halt instruction is a privileged instruction that halts the processor only if
it is running in kernel mode. If the instruction is issued when the processor is
in any mode other than the kernel mode, a privileged instruction fault is
issued.
When the operating system schedules a context switching operation, the con¬
text switching procedure uses the save process context (S VPCTX) and load pro¬
cess context (LDPCTX) instructions to save the current process context and
load another. The operating system’s context switching procedure identifies
the location of the hardware context to be loaded by updating an internal pro¬
cessor register.
The move to processor register (MTPR) and move from processor register
(MFPR) instructions are the only instructions that can explicitly access the
internal processor registers. MTPR and MFPR instructions are privileged and
can be issued only in kernel mode.

6-16 ■ Functions of the Instruction Set

Probe instructions enable a procedure to compare the read (PROBER) and
write (PROBEW) access protection of pages in memory to the privileges of the
caller. The validation enables the operating system to provide services that
execute in access modes to callers with less privileged access and yet prevent
the caller from accessing protected memory.
The operating system’s privileged service procedures and interrupt and excep¬
tion service routines exit using the return from exception or interrupt (REI)
instruction. The REI instruction is the only way the caller’s access mode privi¬
lege can be decreased.

■ Procedure Call Instructions
Procedures are general purpose routines thar use argument lists passed auto¬
matically by the processor and use only local variables for data storage. A pro¬
cedure call instruction provides several services. It
■ Saves all the registers that the procedure uses, and only those registers,
before entering the procedure.
■ Passes an argument list to a procedure.
■ Maintains the stack, frame, and argument pointers.
■ Sets the arithmetic trap enables to a specific state.

Three instructions are used to implement a standard procedure calling inter¬
face. Two instructions implement a procedure. The third instruction imple¬
ments the matching return instruction. A callg instruction calls a procedure
with the argument list actuals in an arbitrary location. The calfc instruction
calls a procedure with the argument list actuals on the stack. Upon return
after a calls instruction, this list is automatically removed from the stack.
Both call instructions specify the address of the entry point of the procedure
being called. It is assumed to consist of a word called the entry mask followed
by the procedure’s instructions. The procedure terminates by executing a
return instruction.
The entry mask specifies the subprocedure’s register use and overflow
enables. Figure 6-3 shows the entry mask.

6-17

MBZ
_1_

0
,

REGISTERS
_l_1_i
i
i

Figure 6-3 ■ Procedure Call Entry Mask

On call, the stack is aligned to a longword boundary and the trap enable bits
in the processor status word are set to a known state to ensure consistent
behavior of the called procedure. Integer overflow enable and decimal over¬
flow enable are affected according to bits 14 and 15 of the entry mask, respec¬
tively. The floating underflow enable bit is cleared.
Registers Rll through RO are saved on the stack and are restored by the
return instruction. The procedure calling standard requires that all registers in
the range R2 through Rll used in the procedure must appear in the mask. In
addition, call instructions always preserve the program counter, stack
pointer, frame pointer, and argument pointer. However, the stack pointer is
not explicitly saved and differs after a calls instruction with arguments. Thus
a procedure can be considered equivalent to a complex instruction that stores
a value into RO and Rl, affects memory, and clears the condition codes. If the
procedure has no function value, the contents of RO and Rl are unpredictable.
In order to preserve the state, the procedure call instructions form a structure
on the stack called a call frame or stack frame. This contains the saved regis¬
ters and processor status word, the register save mask, and several control
bits. The frame also includes a longword that the procedure call instructions
clear. This is used to implement the condition handling facility. At the end of
execution of the procedure call instruction, the frame pointer contains the
address of the stack frame. The return instruction uses the contents of the
frame pointer to find the stack frame and restore state. The condition han¬
dling facility assumes that frame pointer always points to the stack frame. See
Figure 6-4 for the stack frame format.

6-18 ■ Functions of the Instruction Set

31
CONDITION HANDLER
SPA

MASK <11: 0>

PSW <15: 5>

SAVED ARGUMENT POINTER
SAVED FRAME POINTER
SAVED PROGRAM COUNTER
SAVED REGISTER RO (. . . .)

SAVED REGISTER R11 (. . .)
(0 TO 3 BYTES SPECIFIED BY SPA. STACK POINTER ALIGNMENT)
5 BIT-SET IF CALLS; CLEAR IF CALLG

Figure 6-4 ■ Stack Frame Format

Note that the saved condition codes and the saved trace enable bits are
cleared. The contents of bits 0 through 3 of the frame processor status word at
the time return is executed becomes the condition codes resulting from the
execution of the procedure.

■ Processor Status Longword Instructions
There are three instructions available to manipulate the processor status longword.
■ Bit clear processor status longword (BICPS W) that clears a trap enable condi¬
tion.
■ Bit set processor status longword (BISPSW) that sets a trap enable condition.
■ Move from processor status longword (MOVPSL) that obtains the processor
status.

These are rather straightforward instructions and are not explained here. But
the details on the instructions can be found in Chapter 9.

6-19

■ Queue Instructions
A queue is a circular, doubly linked list whose entries are specified by their
addresses. Each queue entry links to two others by way of a pair of longwords.
The first or lower addressed longword is the forward link. It specifies the loca¬
tion of the succeeding entry. The second longword is the backward link. It
specifies the location of the preceding entry. Two distinct types of queues are
possible in VAX systems—absolute and self-relative. They are classified
according to the type of links they use. An absolute link contains the absolute
address of the entry to which it points. A self-relative link contains a displace¬
ment from the present queue entry.
Absolute Queue Instructions
An absolute queue is specified by a queue header that is identical to a pair of
queue linkage longwords. The forward link of the header is the address of the
entry called the head of the queue. The backward link of the header is the
address of the entry termed the tail of the queue. The forward link of the tail
points to the header.
Two general operations can be performed on queues—insertion and removal
of entries. Generally, entries can be inserted or removed only at the head or
tail of a queue.
The following figures illustrate some queue operations. An empty queue is
specified by its header at address H as shown in Figure 6-5. If an entry at
address B is inserted into an empty queue at either the head or tail, the queue
is as shown in Figure 6-6. If an entry at address A is inserted at the head of the
queue, the queue is as shown in Figure 6-7. Finally, if an entry at address C is
inserted at the tail, the queue appears as shown in Figure 6-8. Following the
steps above in reverse order gives the effect of removal at the tail and removal
at the head.
If more than one process can perform operations on a queue simultaneously,
insertions and removals should be done only at the head or tail of the queue.
When just one process (or one process at a time) can perform operations on a
queue, insertions and removals can be made at other locations. In the example
above with the queue containing entries A, B, and C, the entry at address B
can be removed as shown in Figure 6-9.

6-20 ■ Functions of the Instruction Set

0
: H
: H + 4

Figure 6-5 ■ Empty Absolute Queue

Figure 6-7 ■ Putting an Entry into the Head of an Absolute Queue

6-21

Figure 6-9 ■ Removing an Entry from an Absolute Queue

6-22 ■ Functions of the Instruction Set

The reason for the restriction above is that operations at the head or tail are
always valid because the queue header is always present. Operations else¬
where in the queue depend on specific entries being present and may become
invalid if another process is concurrently performing operations on the queue.
Two instructions are provided for manipulating absolute queues—INSQUE
and REMQUE. The INSQUE instruction inserts an entry specified by an entry
operand into the queue, following the entry specified by the predecessor oper¬
and. The REMQUE instruction removes the entry specified by the entry oper¬
and. Queue entries can be on arbitrary byte boundaries. Both INSQUE and
REMQUE instructions are implemented as noninterruptible instructions.
Self-relative Queue Instructions
Self-relative queues use displacements from queue entries as links. As with
absolute queues, queue entries are linked by a pair of longwords. The first longword is the forward link displacement of the succeeding queue entry from the
present entry. The second longword is the backward link—the displacement
of the preceding queue from the present entry. A queue is specified by a queue
header that also consists of two longword links.
The following shows some examples of queue operations. An empty queue is
specified by its header at address H. Because the queue is empty, the selfrelative links must be 0, as shown in Figure 6-10. If an entry at address B is
inserted into an empty queue at either the head or tail, the queue is as shown
in Figure 6-11. If an entry at address A is inserted at the head of the queue,
the queue is as shown in Figure 6-12. Finally, if an entry at address C is
inserted at the tail, the queue appears as shown in Figure 6-13. Following the
steps above in reverse order yields the effect of removal at the tail and removal
at the head.

: H

: H + 4

Figure 6-10 ■ Empty Self-relative Queue

6-23

: H
: H + 4

: B
: B + 4

Figure 6-11 ■ Putting an Entry into an Empty Self-relative Queue

Figure 6-12 ■ Putting an Entry into the Head of a Self-relative Queue

6-24 • Functions of the Instruction Set

Figure 6-13 ■ Putting an Entry into the Tail of a Self-relative Queue

There are four self-relative queue instructions.
■ Insert entry into queue at head, interlocked (INSQHI).
■ Insert entry into queue at tail, interlocked (INSQTI).
■ Remove entry from queue at head, interlocked (REMQHI).
■ Remove entry from queue at tail, interlocked (REMQTI).

These operations are interlocked to allow cooperating processes in a multipro¬
cessor system to access a shared list without additional synchronization.
Queue entries must be quad word aligned. A hardware- supported interlocked
memory access mechanism is used to read the queue header. Bit 0 of the
queue header is used as a secondary interlock and is set when the queue is
being accessed.
If an interlocked queue instruction encounters the secondary interlock set,
the instruction terminates after setting the condition codes to indicate failure
to gain access to the queue. If the secondary interlock bit is not set, then the
interlocked queue instruction sets the bit during its operation and clears the
bit upon completion. This prevents other interlocked queue instructions from
operating on the same queue.

6-25

■ Variable Length Bit Field Instructions
Variable length bit field instructions are useful when dealing with data not in
8-bit increments; for example, 13 bits of data that do not start on a byte
boundary. Such data could also be handled without these instructions but less
efficiently because it requires additional shift and mask operations to get the
bits into the proper form and to eliminate the nonrequired bits.
There are four variable length bit field instructions.
■ Compare field (CMP).
■ Extract field (EXT).
■ Find first (FF).
■ Insert field (INSV).

The CMP instruction compares the field specified with a source operand. The
EXT instruction causes the destination operand to be replaced by the speci¬
fied sign-extended field. The FF instruction extracts a field specified by the
start position, size, and base operand. The INSV instruction replaces a speci¬
fied field with a base operand.
A variable bit field is 0 to 32 contiguous bits (contained in 1 to 5 bytes) that is
arbitrarily located with respect to byte boundaries. The variable length bit
field instructions have four operand specifiers. Three of these specifiers deter¬
mine how to find the variable length field. The fourth designates where it is to
be stored. The first three specifiers are the position operand, the size oper¬
and, and the base address.
The position operand is a signed longword operand that designates the num¬
ber of bits away from the base address operand. If the variable length field is
contained in a register, the position operand must have a value in the range 0
through 31 (if the size is nonzero) or a reserved operand fault occurs.
The size operand is a byte operand that specifies the length of the field. This
operand must be in the range 0 through 32 or a reserved operand fault occurs.
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Chapter 7 ■ Memory Management

Memory management is the control, allocation, and use of main memory for
the VAX family of processors. VAX architecture is intended to support multi¬
programming—the concurrent execution of a number of processes in a single
computer system. A process can be defined for now as a single stream of
machine instructions executed in sequence. Memory management includes
both hardware and software. The hardware provides page mapping and pro¬
tection, while the software provides the operating system image activator and
pager.
Virtual address space is mapped into the physical address space by the proces¬
sor’s memory management logic. In addition, the memory management hard¬
ware supports paging. Paging is a technique that keeps in physical memory
only those parts of a process’s virtual memory that are in use. A VAX process
exists in and operates on a memory space of 4,294,967,296 (232) bytes. Cer¬
tain addresses and data are kept in the sixteen 32-bit general registers. A few
processor state variables are kept in a special register called the processor
status longword, or PSL. The combined set of information in memory, general
registers, and PSL defines a process.
In a typical multiprogramming system, several processes may simultaneously
reside in main memory. Memory protection is provided to ensure that one pro¬
cess does not affect other processes or the operating system. To improve soft¬
ware reliability further, memory access is controlled by the use of four
privilege modes. They are kernel, executive, supervisor, and user. Kernel
mode is the most privileged. User mode is the least privileged. Protection is
specified at the individual page level. A page may be inaccessible, read only, or
read/write for each of the four access modes. Any location accessible to a less
privileged mode is also accessible to all more privileged modes. For each access
mode, any location that may be written can also be read. While an image is
being executed by the CPU, virtual addresses are generated. Before these
addresses can be used to access instructions and data, they must be translated
into physical addresses. Memory management software maintains tables of
mapping information (page tables) that keep track of where each 512-byte vir¬
tual page is located in main memory. The processor uses this mapping informa¬
tion in translating virtual

addresses

to physical

addresses.

Memory

management provides both memory protection and memory mapping func¬
tions for VAX systems. This feature is designed to
■ Provide a large address space for instructions and data.
■ Allow data structures up to one billion bytes.

7-2 ■ Memory Management

■ Provide convenient and efficient sharing of instructions and data.
■ Contribute to software reliability.

A virtual memory system is used to provide a large address space, while allow¬
ing programs to run on systems that have smaller memories. The operating
system provides each process with a potential 4-billion-byte virtual address
space.

11 Virtual Memory
Half of the virtual address space is called system space. System space contains
the operating system software and systemwide data. To facilitate interrupt
handling and system service routines, system space is shared by all processes.
The other half of the virtual address space is separately defined for each pro¬
cess. It is called process space or per-process space. For consistency, we shall
use the term process space. Process space is subdivided into PO and PI space.
Program images and most of their data reside in PO space. In PI space, the
system allocates space for stacks and process-specific data. Because PI space is
used for stacks, it is unique in that it is allocated from high addresses down¬
ward. Together, PO and PI space constitute a process’s working memory.
Except for special cases of sharing, each process has its own PO and PI spaces
independent of others in the system. Figure 7-1 illustrates the address spaces
of several processes in a multiprogramming system. Each process space is inde¬
pendent of the others. System space is shared by all.

7-3

PROCESS 1

PROCESS 2

PROCESS 3

Though the basic addressable unit in VAX machines is the 8-bit byte, larger
units can be constructed by doubling byte sizes: a word is two bytes; a longword is four bytes; a quad word is eight bytes; and an octaword is sixteen
bytes. These five are the units in which VAX memory stores data. But the
processor sometimes interprets operands in other units; for example, half
bytes (nibbles) for decimal digits, or variable-sized bit fields.
Generally, the memory system processes requests only for naturally aligned
data. In other words, a byte can be obtained from any address. But a word can
come only from an even address, and a longword can come only from an
address that is a multiple of four, and so on. VAX processors convert an
unaligned request into a sequence of requests that can be accepted by the mem¬
ory. However, this conversion has a serious impact on performance. Data
structures should be designed in such a way that the natural alignment of oper¬
ands is preserved wherever possible.
The VAX memory management logic serves six principal purposes.
1. A number of processes may simultaneously occupy main memory. All pro¬
cesses can use process space addresses while referring independently to
tfieir own programs and data.

7-4 • Memory Management

2. The operating system keeps selected parts of a process and its data in mem¬
ory, bringing in other parts as needed without explicit intervention by the
program. Large programs can be run in reduced memory space without re¬
coding or overlays visible to the programmer.
3. The operating system may scatter pieces of programs and data wherever
space is available in memory without regard to the apparent contiguity of
the program. It is never necessary for the system to shuffle memory in
order to collect contiguous space for another process to be brought into
memory.
4. Cooperating processes share memory in a controlled way. Two or more pro¬
cesses may communicate through shared memory, in which both have
read/write access. One process may be granted read access to memory
being modified by others; or, a number of processes may share a single
copy of a read-only area.
5. The operating system limits access to memory according to a privilege hier¬
archy. Within any address space, privileged software can maintain
databases that it can access but that code running in less privileged modes
cannot.
6. The operating system may grant or inhibit access to control, status, and
data registers in peripheral devices and their controllers. Since those regis¬
ters are part of the physical address space, access to them is achieved by
creation of a page table entry. The page frame number field of the page
table entry selects the desired device or controller address in the I/O por¬
tion of the physical address space. References to the registers are then
under control of the access control field of the page table entry. The same
privilege mechanisms that control access to sensitive data in memory are
used to control access to I/O devices.
For the purposes of memory management—specifically protection and transla¬
tion of virtual to physical addresses—the unit of memory is the 512-byte
page. Pages are always naturally aligned; that is, the address of the first byte of
a page is a multiple of 512. Virtual addresses are 32 bits long, and are parti¬
tioned by the memory management logic as shown in Figure 7-2.

3
1

9
VIRTUAL PAGE NUMBER

0
BYTE WITHIN PAGE

Figure 1-2 ■ Virtual Address Format

7-5

Field Extent: Bits 31:9
Field Name: Virtual Page Number
Function: The virtual page number field specifies the virtual page to be refer¬
enced. There are 8,388,608 pages in each virtual address space. Each page
contains 512 bytes. When bit 31 is set (1), the address is in the system space.
When bit 31 is clear (0), the address is in process space. Within the process
space, bit 30 distinguishes between the program and control regions. When
bit 30 is set (1), the control region is referenced. When bit 30 is clear (0), the
program region is referenced.

Field Extent: Bits 8:0
Field Name: Byte Number
Function: The byte number field specifies the byte address within the page. A
page contains 512 bytes.
The nine low-order bits select a byte within a page and are unchanged by the
address translation process. The two high-order bits select the P0, PI, or sys¬
tem portion of the address space. The remaining 21 bits are used to obtain a
longword called the page table entry (PTE) from the P0, PI, or system page
table as appropriate. The page table entry format is described in detail later in
this chapter. The PTE contains four pieces of information.
■ Protection code—specifying which, if any, access modes are to be permit¬
ted read or write access to the page.
■ Page frame number—identifying the 512-byte page of physical memory to
be used on references to the virtual address.
■ Valid bit—indicating that the page frame number is valid; that is, it iden¬
tifies a page in memory rather than one in the swapping space on a disk.
■ Modification flag—set by the processor whenever a write to the page
occurs.

In concept, the process of obtaining a page table entry occurs on every mem¬
ory reference. In practice, the processor maintains a translation buffer that is
a special purpose cache of recently used page table entries. Most of the time,
the translation buffer already contains the page table entries for the virtual
addresses used by the program, and the processor need not go to memory to
obtain them.

7-6 ■ Memory Management

There is one page table entry for each existing page of the virtual address
space. A length register associated with each region specifies how many pages
exist in that region of the address space. The system page table (SPT) is allo¬
cated to contiguous pages in physical memory. The table contains page table
entries for addresses greater than 80000000 (hexadecimal). Since the size of
system space is relatively constant and can be determined at system startup
time, allocating a fixed amount of physical memory to the system page table
poses no problems.
Process space page tables change quite dynamically and can become very large.
Because it would be awkward to require the operating system to keep the pro¬
cess page tables in contiguous areas of physical memory, VAX architecture
defines structures called the process space page tables. The tables are identified
as P0PT and P1PT and are to be allocated in contiguous areas of system space.
Thus, the mapping for process space addresses involves two memory refer¬
ences: one to translate the process space address into a physical memory
address, and the second to translate the system virtual address of the table
containing the first translation. It is important to note that even if the transla¬
tion buffer does not have the mapping for the process space address, it is likely
to have that for the page table and can save one of the references.

■ Virtual Address Space
The virtual address space is divided into two address spaces of equal size; one
for the processes, the other for the system. The system address space is the
same for all processes. The operating system resides in the lower half of the
system address space. The operating system is implemented as a series of call¬
able procedures. This arrangement makes the system code available to all
other system and user codes using a call instruction. The upper half of the
system space is reserved for future use. Process address space is separate for
each process. However, several processes may have access to the same page
thus providing controlled sharing. A virtual address is a 32-bit unsigned inte¬
ger specifying a byte location in the address space. The address space seen by
the programmer is a linear array of over 4 billion bytes. The space is divided
into a collection of 512-byte units called pages. The page is the basic unit of
both relocation and protection.

7-7

Virtual address space cannot be contained in currently manufactured main
memory. Memory management maps the active part of the virtual address
space to the available physical address space. Memory management also pro¬
vides page protection between processes. The operating system controls the
memory management tables that map virtual addresses into main memory
addresses. Parts of the virtual address space that are not in use are copied or
swapped to auxiliary memory. When those parts are needed, they are brought
back into the virtual address space. See Figure 7-3 for a diagram of virtual
address space.

VIRTUAL ADDRESS
(32 BITS)
0000 0000

VIRTUAL ADDRESS
SPACE
>
P0 REGION
(PROGRAM)
GROWTH DIRECTION

3FFF FFFF
4000 0000

PROCESS
SPACE

(
GROWTH DIRECTION

7FFF FFFF

PI REGION
(CONTROL)

8000 0000
SYSTEM REGION
GROWTH DIRECTION
BFFF FFFF

SYSTEM
SPACE

C000 0000
RESERVED
FFFF FFFF

Figure 7-3 ■ Virtual Address Space

The figure shows that virtual address space is divided into two major areas—
process space and system space. Each process has a separate address transla¬
tion map for process space, so the process spaces of all processes are nonconti¬
guous.
The address map for process space is context-switched when the process run¬
ning on the system is changed. Process space is further divided into two
regions named PO and PI. These regions are described in detail later in this
chapter.

7-8 ■ Memory Management

The other half of virtual address space is called system space. All processes use
the same address translation map for system space. System space is shared by
all processes. The address map for system space is not context-switched. In a
shared-memory multiprocessor configuration, changing any of the address
mapping information for system space requires that all processors execute an
MTPR xxx,#TBIS instruction.
Access to each of the three regions is controlled by a length register. The
length registers are POLR, P1LR, and SLR. Register POLR controls access to
region PO. Register P1LR controls access to region PI. Register SLR controls
access to the system space of the virtual address space. Within the limits set
by the length registers, the access is controlled by a page table that specifies
the validity, access requirements, and location of each page in the region.

■ Address Translation
The action of translating a virtual address to a physical address is governed by
the setting of the Memory Mapping Enable (MME) bit. When MME is reset
(0), page protection is disabled. This feature is reserved for Field Service. This
section describes address translation when the MME bit is set (1) and page pro¬
tection is enabled.
The address translation mechanism is presented with a virtual address, an
intended access (read or write), and a mode against which to check that
access. If the access is allowed and the address is not faulted, the output of
this routine is a physical address corresponding to the specified virtual
address. The mode that is used is normally the current mode field of the pro¬
cessor status longword. But process page table entry references use the kernel
mode.
If the operation to be performed is a read operation, the intended access is
read access. If the operation to be performed is a write operation, the
intended access is write access. If the operation to be performed is a modify
(that is, a read followed by a write operation), the intended access for the read
portion is specified as a write access. If an operand is not an address operand,
no reference is made.
Page Table Entry
All virtual addresses are translated to physical addresses by means of a page
table entry (PTE). See Figure 7-4 for a graphic description of the page table
entry.

7-9

33
10
V

22222222
76543210_
PROT

M Z OWN S

0
PFN

Figure 7-4 ■ Page Table Entry

Field Extent: Bit 31
Field Name: Valid bit (V)
Function: Governs the validity of the modify (M) bit and the page frame num¬
ber (PFN) field. The bit is set (1) for valid; reset (0) for invalid. When this bit
is reset, the modify and page frame number fields are reserved for system soft¬
ware.

Field Extent: Bits 30:27
Field Name: Protection (PROT)
Function: This field is always valid and is used by the hardware even when the
valid bit is reset (0). The protection field is defined as always being valid and
is checked first. The page table entry is defined as having a valid bit that con¬
trols the validity of the modify bit and page frame number field only. Protec¬
tion is checked first so that programs executing in user mode do not perform
access protection checks in the system region and fault all the swappable
pages.

Field Extent: Bit 26
Field Name: Modify bit (M)
Function: When the valid bit is reset (0), the modify bit is reserved for system
software and I/O devices. When the valid bit is set(l) and this bit is reset (0),
the page has not been modified. When the valid bit and this bit are set, the
page has been modified. The modify bit is reset by software. It is set by the
CPU on a successful write or modify to the page. In addition, it may be set by a
probe-write instruction or an implied probe-write. This bit is not set if the
page is inaccessible.

7-10 ■ Memory Management

Field Extent: Bit 25
Field Name: Must Be Zero
Function: This bit is reserved and must be zero.

Field Extent: Bits 24:23
Field Name: Owner (OWN) bits
Function: These bits are reserved for system software use. The VAX/VMS
operating system uses these system bits as the access mode of the owner of the
page; that is, the mode allowed to alter the page. The field is not examined or
altered by hardware.

Field Extent: Bits 22:21
Field Name: Operating System Software
Function: These bits are reserved for Operating System Software.

Field Extent: Bits 20:0
Field Name: Page Frame Number (PFN)
Function: The upper 21 bits of the physical address of the base of the page.
The field is used by hardware only if the valid bit is set.
The operating system software uses combinations of software bits to imple¬
ment its page management data structures and functions. Some of the func¬
tions implemented are initialize pages with zeros, copy on reference, page
sharing, and transitions between active and swapped-out states. VAX/VMS
software encodes these functions in page table entries whose valid bit is reset
(0) and processes them whenever a page fault occurs.
Page Table Entry for I/O Devices
Some I/O devices use memory management to translate addresses. These
devices use a page table entry format that is an extension of the page table
entry used by the CPU. For hardware, the extended page table entry imple¬
ments some functions that the CPU implements with software. Three page
table entry bits are used in four combinations to identify a valid page frame
number, a global page table index, and an I/O abort. The page table bits are
22, 26, and 31. The page frame number is valid if bit 31 is set (1) or if bits 22,
26, and 31 are reset (0). When bit 22 is set (1) and bits 26 and 31 are reset (0),
the page frame number field is a global page table index (GPTX). The I/O
device has a global page table base register that is loaded with a system virtual
address.

7-11

The I/O device calculates the system virtual address of a second page table
entry. The second page table entry must yield a valid page frame number and
the three bits must indicate a valid page frame number. If either of these
requirements is not met, the result is undefined. The protection field always
comes from the first PTE. Some I/O devices may examine and check the pro¬
tection field or modify the M bit—this is device dependent. Devices that use
the protection field and M bit do so in the same manner as does the CPU.
I/O devices that perform memory mapping use the same SPT as the CPU. But
the devices have their own copies of the system base register and system space
length register. Buffer addresses are described in terms of a system virtual
address of the PTE for the first buffer page and a byte offset within that page.
In addition, the I/O devices use a global page table in memory and an I/O hard¬
ware global page table base register (GBR) which must be loaded by software.
Changing Page Table Entries
Page table entries are changed by the operating system as part of its memory
management functions. For example, the operating system sets and resets the
valid bit and changes page frame numbers as pages are swapped.
The software must guarantee that each PTE is consistent within itself. Chang¬
ing a PTE one field at a time may cause incorrect system operation. For exam¬
ple, the valid bit could be set for one instruction while the page frame number
is for another instruction. Then, an interrupt routine could occur between the
two instructions that would use an address mapped to this inconsistent PTE.
This problem can be avoided by simultaneously changing all the fields in PTE.
Simply build the new PTE in a register and move that PTE into the page table
with one instruction (MOVL).
Multiprocessors complicate the matter. One processor can reference a page
table that is being modified by another processor. The PTEs must be consis¬
tent. In order to guarantee this, first note that PTEs are longword-aligned longwords. Because of this, two requirements must be met. First, whenever the
software modifies a PTE in more than one byte, the software must use a longword, longword-aligned, write-destination instruction (such as MOVL). Sec¬
ond, the hardware must guarantee that an incomplete longword-aligned
longword write operation cannot be read or overwritten.
System Space Address Translation
Figure 7-5 graphically describes the system space address format. The figure
shows a virtual page number field with bits 31 and 30 set to a value of 2.

7-12 • Memory Management

31 30 29

VIRTUAL PAGE NO. (VPN)

BYTE #

Figure 7-5 ■ System Space Address Format

The system virtual address space is defined by the system page table, which is
a vector of page table entries. The physical base address of the system page
table is in the system base register. The size of the system page table in longwords (number of page table entries) is in the system length register. The page
table entry addressed by the system base register maps the first page of system
space; that is, virtual byte address 80000000 (hexadecimal).
The virtual page number field is bits 9 through 29 of the virtual address.
Thus, there could be as many as 2,097,152 (221) pages in the system region.
Typically, the value is in the range of a few hundred to a few thousand system
pages. A 22-bit field is required to express the values 0 through 2,097,152
inclusive. During a bootstrap procedure, the contents of both registers are
unpredictable. The translation from system space virtual address to physical
address is shown in Figure 7-6.

7-13

33 2
10 9

980

Figure 7-6 ■ System Space Address Translation

Process Space Address Translation
The process virtual address .space is divided into two separately mapped
regions according to the setting of bit 30 in the process virtual address. If bit
30 is reset (0), the P0 region of the address space is selected. If bit 30 is set (1),
the PI region is selected.
The P0 region of the address space defines a contiguous area starting at the
smallest address in the process virtual space and moving toward the larger
addresses. The P0 region is used typically for program images, and the region
grows dynamically.
In contrast, the PI region of the address space defines a contiguous area that
starts at the largest address in the process virtual space and moves toward the
smaller addresses. The PI region is typically used for system-maintained pro¬
cess context. It may grow dynamically for the user stack.

7-14 ■ Memory Management

Both regions of the process virtual space are described by page tables. The two
page tables are addressed with virtual addresses in the system region of the
virtual address space. For process space, the address of the page table entry is
a virtual address in system space, and the fetch of the page table entry is sim¬
ply a fetch of a longword using a system virtual address.
Process page tables are addressed in virtual space. If the tables were addressed
in physical space, a process page table that required more than a page of page
table entries would also require physically contiguous pages. Such a require¬
ment would make the dynamic allocation of process page table space more com¬
plex.
A process space translation causing a translation buffer miss usually causes
one memory reference for a page table entry. If the virtual address of the page
containing the process page table entry is also missing from the translation
buffer, a second memory reference is required.
When a process page table entry is fetched, a reference is made to system
space. This reference is made as a kernel read. The system page containing a
process page table is either accessible or inaccessible. Similarly, a check is
made against the system length register (SLR). The fetch of an entry from a
process page table can cause access or length violation faults.
The PO region of the address space is mapped by the PO page table (POPT) that
is defined by the PO Base Register (POBR) and the PO Length Register (POLR).
The base register contains a virtual address in the system half of virtual
address space that is the base address of the PO page table. The length register
contains the size of the PO page table in longwords; that is, the number of page
table entries. The page table entry addressed by the PO base register maps the
first page of the PO region of the virtual address space (virtual byte address
zero). The page table entries in the PO page table contain the mapping informa¬
tion themselves; or point to the mapping information in the global page table
if the page table entry is in the global page table index format.
The virtual page number is bits 9 through 29 of the virtual address. This
means there could be as many as 2,097,152 (221) pages in the PO region. A 22bit field is needed to express the values 0 through 2,097,152 inclusive. Bits
24 through 26 of register POLR are ignored on the move to processor register
(MTPR) instruction and are read back as zero on the move from processor regis¬
ter (MFPR) instruction. During bootstrap procedures, the contents of both
registers are unpredictable. An attempt to load register POBR with a value less
than 2,147,483,648 (231) or greater than 3,221,225,468 (((231) + (230))-4)
causes a reserved operand fault. The translation from PO virtual address to
physical address is shown in Figure 7-7.

7-13

33 2

Figure 7-7 m PO Region Address Translation

The PI region of the address space is mapped by the PI page table (P1PT) that
is defined by the PI Base Register (P1BR) and the PI Length Register (P1LR).
Because PI space moves from higher to lower addresses and because a consis¬
tent hardware interpretation of the base and length registers is important, reg¬
isters P1BR and P1LR describe that portion of PI space that is inaccessible.
The base register contains a virtual address of what would be the page table
entry for the first page PI-virtual byte address 40000000 (hexadecimal). The
length register contains the number of nonexistent page table entries. An
address in the base register is not necessarily an address in system space; but
an address of a page table entry must be in system space. The page table
entries in the PI page table contain the mapping information or point to the
mapping information in the global page table entry if the page table entry is in
global page table index format.

7-16 • Memory Management

Bit 31 of the length register is ignored by a move to processor register instruc¬
tion and is read as zero by a move from processor register instruction. During
bootstrap procedures, the contents of both registers are unpredictable.
Attempting to load register P1BR with a value less than 2,139,095,040
(7F800000 (hexadecimal)) causes a reserved operand fault. The translation
from PI virtual address to physical address is shown in Figure 7-8.

PVA:
(FHUCbSS VIH 1 UAL
ADDRESS)

CM CT>

33
10

EXTRACT AND
CHECK LENGTH

o I1 0
^ 11 ^
3 2

0
BYTE

2 10

ADD

SYS VIRT BASE ADR OF P1PT

P1BR:

YIELDS

SYS VIRT ADR OF PTE

FETCH BY SYSTEM SPACE TRANSLATION ALGORITHM,
INCLUDING LENGTH AND KERNEL MODE ACCESS
CHECKS

PTE:

2 2

1 0

_0
PFN

1
CHECK ACCESS
3 31
g
1 0

PHYS ADR OF DATA:

THIS ACCESS CHECK
IN CURRENT MODE

1
8

Figure 7-8 ■ PI Region Address Translation

■ Access Control
Access control is the process of screening page access requests and verifying
that the requester is authorized access to that page. Every page is assigned a
protection code. That code specifies for each mode whether or not read or
write references are allowed. Also, each address is checked to ensure that it
resides in the virtual address space.

7-17

There are four access modes. The modes are listed in Table 7-1 in the order of
most to least privileged. The mode at which the processor is currently running
is stored in the current mode field of the processor status longword.

Table 7-1 ■ Processor Access Modes
Access Mode Code

Access Mode Name

Kernel

Executive

Supervisor

User

Page protection is assigned according to its use, not its location in the virtual
address space. Although the system space is shared, a program may be pre¬
vented from modifying or accessing portions of the system space. A program
may also be prevented from accessing or modifying portions of process space.
For example, in system space, scheduling queues are highly protected, but
library routines may be executed by any privilege code. Also, in process space,
process accounting information may be highly protected, while normal user
code may be executed by any privilege code.
Each page is assigned a protection code describing the accessibility of the page
for each mode. The protection codes allow a choice of protection for each
access level within the following limits.
■ Each level’s access can be read or write, read only, or no access.
■ Whichever level has read access, all more privileged levels also have read
access.
■ Whichever level has write access, all more privileged levels also have write
access.

This scheme results in 15 possible protection codes. The protection code is
encoded in a 4-bit field in the page table entry. See Table 7-2 for a list of the
codes.

7-18 ■ Memory Management

Table 7-2 ■ Page Table Entry Protection Codes
Protection Code

Access Modef

Decimal

Binary

Mnemonic* K

0000

0001

0010

0011

Comments

No access

Reserved

Kernel write

Kernel read

0100

All access

0101

0110

ERKW

0111

1000

1001

SREW

1010

SRKW

1011

1100

URSW

1101

UREW

1110

URKW

* Software symbols are defined using PTE$K as a prefix to the mnemonics listed
above. For example, the software protection symbol PTE$KUR means that that soft¬
ware can be read by anyone with user access privileges and those with higher privileges.
A software protection symbol of PTE$KER means that that software can be read by
anyone with kernel or supervisor access privileges. No one is allowed write access to
that software.
t There are four access modes—K for Kernel Access Mode, E for Executive Access
Mode, S for Supervisor Access Mode, and U for User Access Mode. Within these
access modes, there are certain functions that may be performed - R indicates read
access only, RW indicates read and/or write access, NO indicates no access, and UN
indicates unpredictable results if access is attempted.

Every valid virtual address must reside in one of the addressing regions and
the associated length registers. The algorithm for making these checks is a
limit check. The notation for this check is shown in Example 7-1.

7-19

Example 7-1 ■ Valid Virtual Address Checking Algorithm
case Vftddr <31=30>
set
!P0 region

[0]:

if ZEXT (VAddr<29:9>) GEQU P0LR
then (length violation)
!PI region

[i3 =
if ZEXT (iVAddr<29:9>) LSSU P1LR
then {length violation);

!S region

[23:

if ZEXT (VAddr<29:9>) GEQU SLR
then {length violation);
! reserved region

[33:

{length violation);
tes;
An access control fault occurs if the current mode of the processor status longword and the page protection fields indicate the access is illegal, or if the
address causes a length violation. If an access is made across a page boundary,
the order in which the pages are accessed is unpredictable. However, for a
given page, access control violation always takes precedence over translation
not valid.

■ Controlling Memory Management
There are three additional privileged registers used to control the memory
management hardware. One register is used to enable and disable memory
management. The other two are used to clear the hardware address transla¬
tion buffer when a page table entry is changed.
The action of translating a virtual address to a physical address is governed by
the setting of the memory mapping enable bit of the map enable register. The
map enable register (MAPEN) contains a value of 0 or 1 depending upon mem¬
ory management. If memory management is disabled, the value is 0. If mem¬
ory management is enabled, the value is 1. During bootstrap procedures, this
register is initialized to zero.
When memory management is disabled, virtual addresses are mapped to physi¬
cal addresses by ignoring their high-order bits. Access is allowed in all modes,
and the modify bit is not maintained.
To read the register, use the move from processor register (MFPR) with the
source operand specified as ff56. To write to the register, use the move to pro¬
cessor register (MTPR) instruction using If56 as the destination operand.

7-20 ■ Memory Management

In order to reduce repeated address translations, the hardware includes a trans¬
lation buffer that records virtual address translations and page status. When¬
ever the process context is loaded by the load process context (LDPCTX)
instruction, the translation buffer is automatically updated. That is, the pro¬
cess virtual address translations are invalidated. Whenever a page table entry
for the system or current process region is changed other than to set the page
table entry valid bit, the software must notify the translation buffer of this
change. This is done by moving an address within the corresponding page into
the translation buffer invalidate single (TBIS) register.
Additionally, when the software changes a system page table entry that maps
any part of the current process page table, all process pages so mapped must be
invalidated in the translation buffer. They may be invalidated by moving an
address within each such page into the TBIS register. They may also be invali¬
dated by clearing the entire translation buffer. This is done by moving zero to
the translation buffer invalidate all register with a move to processor register
instruction.
The translation buffer must not store invalid page table entries. Software is
not required to invalidate translation buffer entries when making changes for
page table entries that are already invalid. Whenever the location or size of
the system map is changed (SBR, SLR) the entire translation buffer must be
cleared by moving 0 into the translation buffer invalidate all (TBIA) register.
Before enabling memory management, the translation buffer must be cleared
by moving 0 into the TBIA register with the move to processor register instruc¬
tion.
Whenever the memory management enable bit is zero, the contents of the
translation buffer are unpredictable. Therefore, the entire translation buffer
must be cleared before enabling memory management.

■ Faults and Parameters
Two types of faults are associated with memory mapping and protection. A
translation not valid fault is taken when a read or write reference is attempted
through an invalid page table entry. An access control violation fault is taken
when the protection field of the page table entry indicates that the intended
access is illegal.
Note that these two faults have distinct vectors in the system control block. If
both access control violation and translation not valid faults occur, the access
control violation fault takes precedence.
An access control violation fault is also taken if the virtual address referenced
is beyond the end of the associated page table. Such a length violation is essen¬
tially the same as referencing a page table entry that specifies no access. To
avoid repeating the length check, a length violation is stored in the fault param¬
eter word. The fault parameter word format is shown in Figure 7-9.

7-21

2 10

Figure 7-9 ■ Fault Parameter Word Format

The same parameters are stored for both types of faults. The first parameter
pushed on the kernel stack after the processor status longword and program
counter is the initial virtual address that caused the fault. A process space ref¬
erence can result in a system space virtual reference for the page table entry.
If the page table entry reference faults, the process virtual address is saved. In
addition, a bit is stored in the fault parameter word indicating that the fault
occurred in the process page table entry reference. The second parameter
pushed on the kernel stack contains the information listed below.

Field Extent: Bit 2
Field Name: Write or Modify Intent
Function: This bit is set (1) to indicate that the program’s intended access is a
write or modify. This bit is reset (0) if the program’s intended access is a read.

Field Extent: Bit 1
Field Name: Page Table Entry Reference
Function: This bit is set (1) to indicate that the fault occurred during the refer¬
ence to the process page table associated with the virtual address. This bit is
set on either length or protection faults.

Field Extent: Bit 0
Field Name: Length Violation
Function: This bit is set (1) to indicate that an access control violation was the
result of a length violation rather than a protection violation. This bit is reset
(0) for a translation not valid fault.

7-22 ■ Memory Management

■ Accessing Privileged System Services
Most processes execute in the user access mode. At times, the user access
mode processes need to use system services that execute at a higher-level
access mode. These user mode processes are not allowed access to other modes
except for these necessary services. VAX systems provide instructions that
change an access mode to one of greater privilege under strictly controlled con¬
ditions. These instructions are called the privilege instructions.
The privilege instructions change a process’s mode to a more privileged mode
and transfer control to a service dispatcher for the new mode. The instruc¬
tions provide the only mechanism for less privileged code to call more privi¬
leged code. When the mode transition takes place, the previous mode is saved
in the previous mode field of the processor status longword. This allows the
more privileged code to determine the privilege of its caller.
The instructions give upward and downward mobility through the access
modes, and provide a way to compare memory protection levels to the access
mode privilege of callers. The instructions are change mode (CHM), probe,
return from exception or interrupt (REI), save process context (SVPCTX), load
process context (LDPCTX), move to processor register (MTPR), and move from
processor register (MFPR).
User mode software can access privileged services by calling operating system
service procedures with a call instruction. The operating system’s service dis¬
patcher issues an appropriate change mode instruction before entering the pro¬
cedure. A change mode instruction allows access mode transitions to take place
from one mode to the same or more privileged access mode (upward) only.
When such a mode transition takes place, the previous mode is saved in the
previous mode field of the processor status longword. This action allows the
more privileged code to determine the access privilege of its caller.
A change mode instruction is a special trap instruction that can be likened to
an operating system service call instruction. User access-mode software can
explicitly issue change mode instructions. Because the operating system
receives the trap, nonprivileged users cannot write software to execute in any
of the privileged access modes. User mode software can include a condition
handler for change mode to user traps. This instruction provides general pur¬
pose services for user access-mode software. Before software with a change
mode instruction can be executed, the user’s privilege must be changed in the
system authorize database (SYSUAF.DAT). The privilege is changed for one
program and is not a global change for the user.

7-23

For service procedures written to execute in privileged access modes, the pro¬
cessor provides address access privilege validation instructions called probe
instructions. Probe instructions enable a procedure to compare the read
(PROBER) and write (PROBEW) access protection of pages in memory to the
privileges of the caller. The validation enables the operating system to provide
services that execute in access modes to callers with less privileged access and
yet prevent the caller from accessing protected memory.
When the operating system schedules a context switching operation, the con¬
text switching procedure uses the save process context (SVPCTX) and load pro¬
cess context (LDPCTX) instructions to save the current process context and
load another. The operating system’s context switching procedure identifies
the location of the hardware context to be loaded by updating an internal pro¬
cessor register.
Internal processor registers include not only those that identify the executing
process but also the memory management and other registers such as the con¬
sole and clock control registers. The move to processor register (MTPR) and
move from processor register (MFPR) instructions are the only instructions that
can explicitly access the internal processor registers. MTPR and MFPR instruc¬
tions are privileged and can be issued only in kernel mode.
The operating system’s privileged service procedures and interrupt and excep¬
tion service routines exit using the return from exception or interrupt (REI)
instruction. The REI instruction is the only way the caller’s access mode privi¬
lege can be decreased. Like the procedure and subroutine return instructions,
the REI instruction restores the program counter and the processor state to
the values that were stored there before the change mode trap interruption.
This procedure ensures that the process resumes execution at the point where
it was interrupted.
REI instructions perform special services that normal return instructions do
not. For example, REI instructions inspect the asynchronous system trap
queue for the executing process. If an asynchronous system trap was queued
for the process while the interrupt or exception service routine was executing,
the REI instruction ensures that the process receives them. Also, REI instruc¬
tions check the mode to which control is being returned. That mode must be
the same as or a less privileged mode than the one in which the exception or
interrupt occurred. The REI instruction is available to all software including
user-written trap handling routines. There is a restriction; a program cannot
increase its privilege by altering the processor state to be restored.

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Chapter 8 ■ Exceptions and Interrupts

Events within the system sometimes need software outside the flow of con¬
trol. In these cases, the processor changes the flow of control from that indi¬
cated in the executing process. Some such events are relevant to the current
process and normally invoke software within the context of that process. The
notification of these events is called an exception.
Other events are relevant to other processes or to the system as a whole and
are serviced in a systemwide context. The notification process for these events
is called an interrupt. The systemwide context is described as executing on the
interrupt stack. Some interrupts require high-priority service, while others
must be synchronized with independent events. To meet these needs, the pro¬
cessor has priority logic that grants interrupt service to the highest priority
event at any moment. The priority assigned to an interrupt is called its inter¬
rupt priority level (IPL).

■ Event Handling
Exceptions are handled by the operating system. Usually they are reflected to
the originating mode as a signal. In general, the exception is described by a
vector that is a list of longwords. The first longword contains a count of other
longwords in the vector. The second longword identifies which exception
occurred. The remaining longwords are the stack parameters, the program
counter, and the processor status longword. There are three kinds of excep¬
tions — aborts, faults, and traps.
An abort is a condition that occurs when an instruction leaves the value of the
registers and memory in an unpredictable condition and the instruction cannot
be correctly restarted, completed, simulated, or undone. After an instruction
aborts, the program counter addresses the opcode of the aborted instruction.
The following events produce unpredictable results.
■ Destination operands including implied operands such as the top of the
stack in a JSB instruction.
■ Registers modified by an operand specifier evaluation including specifiers
for implied operands.
■ The modify bit of the page table entry in those entries that map destination
operands if the operands could have been but were not written, and the
modify bit was clear before the instruction.

8-2 • Exceptions and Interrupts

■ The first part done bit of the processor status longword.
■ The trace pending bit of the processor status longword.

If not noted in the description of the abort exception, the rest of the processor
status longword, other registers, and memory are not affected.
A fault exception is a condition that occurs during an instruction. Faults leave
the registers and memory in a consistent state. When the fault condition is
corrected and the instruction is restarted, the execution yields correct results.
Note that faults do not always leave everything as it was prior to the fault
instruction. Faults restore only enough to allow restarting. Thus the state of a
faulted process may not be the same as that of an interrupted process if both
occurred at the same point.
A trap exception is a condition that occurs at the end of the instruction that
caused the exception. Therefore, the program counter saved on the stack is
the address of the next instruction that would normally have been executed.
Any software can enable and disable some of the trap conditions with a single
instruction. For example, refer to the descriptions of the bit set processor
status word (BISPSW) and bit clear processor status word (BICPSW) instruc¬
tions.
The processor arbitrates interrupt requests according to priority. Only when
the priority of an interrupt request is higher than the current interrupt prior¬
ity level does the processor raise the level and service of the interrupt request.
The interrupt service routine is entered at the level of the interrupt request
and usually does not change the set by the processor.
Interrupt requests come from devices, controllers, other processors (in cus¬
tomer-designed systems), or the processor itself. Software executing in kernel
mode can raise and lower the priority of the processor. But note that the prior¬
ity level of one processor does not affect the priority level of the other proces¬
sors. This is done to prevent the interrupt priority levels from being used to
synchronize access to shared resources in multiprocessor systems. Special soft¬
ware action is required to stop other processors in your multiprocessor system.
Most service routines for software-generated exceptions execute at interrupt
priority level 0. However, if a serious system failure occurs, the processor
raises the interrupt priority level to the highest level to prevent interruption
until the problem is corrected. Exception service routines are usually coded to
avoid exceptions. However, nested exceptions may occur in the the following
faults—an access control violation, reserved operand, or reserved addressing
mode.

8-3

Interrupt Priority Levels
The processor has 31 interrupt priority levels (IPLs) divided into 15 software
levels (numbered 1 through F (hexadecimal)) and 16 hardware levels (10
through IF (hexadecimal)). User applications, system calls, and system ser¬
vices run at process level (IPLO). Higher numbered IPLs have higher priority.
Any request with an IPL higher than the processor’s IPL causes an immediate
interrupt. But requests with a lower or equal IPL are deferred.
Interrupt levels 1 through F (hexadecimal) exist entirely for use by software.
No hardware device can request interrupts on those levels but software can
force an interrupt. The interrupt is forced by executing a move to processor
register instruction using the software interrupt request register as the destina¬
tion. After a software interrupt request is made, the request is cleared by hard¬
ware when the interrupt is taken.

Interrupt levels

through

(hexadecimal) are for use by devices and controllers, including UNIBUS
devices. Interrupt levels 18 through IF (hexadecimal) are used by urgent con¬
ditions including—the interval clock, serious errors, and powerfail.
Two of the software interrupt priorities are reserved for process structure soft¬
ware. They are IPL2 and IPL3. IPL2 is the AST delivery interrupt. It is trig¬
gered by a return from exception or interrupt instruction that detects
PSLcCUR MOD> GEQU ASTLVL. IPL2 indicates that a pending AST for
the executing process can now be delivered.
IPL3 is the process scheduling interrupt. It is triggered by software to allow
the process running at IPL3 to cause the executing process to be blocked and
the highest priority executable process to be scheduled.
Exceptions and Interrupts
Exceptions and interrupts are similar. When either is initiated, both the pro¬
cessor status longword (PSL) and the program counter are put on a stack. How¬
ever,

there are seven important differences between exceptions and

interrupts.
■ An exception is caused by an executing instruction. An interrupt is caused
by the computing system and is usually independent of an instruction.
■ Usually, an exception is serviced in the context of the process that pro¬
duced that exception. An interrupt is serviced independently of the cur¬
rent process.
■ Generally, the interrupt priority level of the processor is not changed when
the processor initiates an exception. The interrupt priority level is always
raised when an interrupt is initiated.

8-4 • Exceptions and Interrupts

■ Normally, exception service routines execute on a process stack. Interrupt
service routines normally execute on a processor stack. However, a
machine check always executes on the interrupt stack pointer.
■ Enabled exceptions are initiated immediately, independent of the proces¬
sor interrupt priority level. Interrupts are delayed until the processor inter¬
rupt priority level drops below the level of the requesting interrupt.
■ Most exceptions cannot be disabled. If an exception-causing event should
occur while that exception is disabled, no exception is initiated even when
that event is subsequently enabled. This includes overflow exceptions. If
an interrupt is disabled and an initiating event occurs, the event initiates
an interrupt when subsequently enabled if the interrupt condition exists.
Also, if the process is at an equal or higher interrupt priority level, the
interrupt is initiated when enabled.
■ The previous mode field in the processor status longword is always set to
kernel on an interrupt. On an exception, the field indicates the mode in
which the exception occurred.

Processor Status
When an exception or interrupt is serviced, the processor status must be pre¬
served. This is done so the interrupted process continues normally. Processor
status preservation is the task of the program counter and the processor status
longword. The counter and longword are restored with a return from exception
or interrupt instruction. Any other status information needed to resume an
interruptible instruction is stored in the general registers. Process context is
not saved or restored on each exception or interrupt. Instead, context is saved
and restored only when process context is switched. Other processors’ status
is changed less frequently.
There are several processor state variables associated with each process, and
VAX software groups them into the 32-bit processor status longword (PSL).
Bits 15 through 0 of the PSL are referred to separately as the processor status
word (PSW). The PSW contains unprivileged information and those bits of
the PSW that have defined meaning are controllable by any program. Bits 31
through 16 of the PSL have privileged status. While any program can perform
the REI instruction (which loads PSL), the instruction refuses to load any PSL
that would increase the privilege of a process, or create an undefined state in
the processor. Figure 8-1 illustrates the processor status longword and the fol¬
lowing paragraphs explain the various fields.

8-5

31 30 2928 27 26

CM TP MBZj|fpd IS

CURRENT PREVIOUS
MBZ
MODE
MODE

16 15
IPL

MBZ

8 7 6 5 4 3 2 1

DV FU IV T N Z V

v
PSW

Figure 8-1 ■ Processor Status Longword

Bits 3:0 of the PSL are called the condition codes. In general, they reflect the
result status of the most recent instruction that affects them. The condition
codes are tested by the conditional branch instructions.
Bit 3 is the negative condition code (N bit). In general, it is set by negative
result instructions. The bit is cleared by positive result or zero instructions.
For those instructions that affect the bit according to a stored result, the N bit
reflects the actual result even if the sign of the result is algebraically incorrect
as a result of overflow.
Bit 2 is the zero condition code (Z bit). Typically it is set by instructions that
store an exactly zero result and cleared if the result is not zero. Again, this
reflects the actual result even if overflow occurs.
Bit 1 is the overflow condition code (V bit). In general, it is set after arithme¬
tic operations in which the magnitude of the algebraically correct result is too
large to be represented in the available space, and cleared after operations
whose result fits. Instructions in which overflow is impossible or meaningless
either clear the bit or leave it unaffected. Note that all overflow conditions
that set the V bit can also cause traps if the appropriate trap enable bits are
set.
Bit 0 is the carry condition code (C Bit). Usually, it is set after arithmetic oper¬
ations in which a carry out of, or borrow into, the most significant bit
occurred. The bit is cleared after arithmetic operations that had no carry or
borrow, and is either cleared or unaffected by other instructions. The C bit is
unique in that it not only determines the operation of conditional branch
instructions, it also serves as an input variable to the ADWC (Add with Carry)
and SBWC (Subtract with Carry) instructions used to implement multiple-pre¬
cision arithmetic.
Bits 7 through 4 of the PSL are trap-enable flags that cause traps to occur
under special circumstances.

8-6 ■ Exceptions and Interrupts

Bit 7 is the decimal overflow trap enable bit (DV bit). When set, it causes a
decimal overflow trap after the execution of any instruction that produces a
decimal result whose absolute value is too large to be represented in the desti¬
nation space provided. When the DV bit is clear, no decimal overflow trap
occurs. The result stored consists of the low-order digits and sign of the alge¬
braically correct result. Note that there are other trap conditions for which
there are no enable flags-division by zero and floating overflow.
Bit 6 is the floating underflow exception enable bit (FU bit). When the FU bit
is set (1), it forces a floating underflow exception after execution of the instruc¬
tion that produced an underflowed result. When the FU bit is clear (0), no
exception occurs. The result stored is zero.
NOTE
On VAX-11/780 processors with a hardware revision level of
less than 7, a trap occurs. On all other VAX processors, a
fault occurs.
Bit 5 is the integer overflow trap enable bit (IV bit). When set, it causes an
integer overflow trap after an instruction that produced an integer result that
could not be correctly represented in the space provided. When bit 5 is clear,
no integer overflow trap occurs. The V condition code is set independently of
the state of the IV condition code.
Bit 4 is the trace bit (T bit). When set, it causes a trace trap to occur after
execution of the next instruction. This facility is used by debugging and per¬
formance analysis software to step through a program one instruction at a
time. If any instruction is traced and causes an arithmetic trap, the trace trap
occurs after the arithmetic trap.
Bits 15 through 8 of the PSL are not used and are reserved.
Bits 20 through 16 represent the processor’s interrupt priority level (IPL). In
order to be acknowledged by the processor, an interrupt must be at a priority
higher than the current IPL. Virtually all software runs at IPL 0, so the proces¬
sor acknowledges and services interrupt requests of any priority. The inter¬
rupt service routine for any request runs at the IPL of the request. This
temporarily blocking interrupt requests lower or equal priority. Briefly, there
are 31 interrupt priority levels above zero, numbered 01 through IF (hexadec¬
imal). Interrupt levels 01 through OF exist entirely for use by software. IPLs
10 through 17 are for use by peripheral devices and their controllers.
Although present systems support only 14 through 17. Levels 18 to IF are for
use for urgent conditions including the interval clock, serious errors, and
powerfail.

8-7

Bits 23 and 22 are the previous mode bits that contain the value from the cur¬
rent mode field at the most recent exception that transferred from a less privi¬
leged mode to this one. Previous mode is of interest in the PROBE
instructions that enable privileged routines to determine whether a caller at
the previous mode is sufficiently privileged to reference a given area of mem¬
ory.
Bits 25 and 24 are the current mode bits that determine the privilege level of
the currently executing program. Privilege is granted in two ways by the mode
field-certain instructions (halt, move to processor register, and move from pro¬
cessor register) are not performed unless the current mode is kernel. The mem¬
ory management logic controls access to virtual addresses on the basis of the
program’s current mode, the type of reference (read or write), and a protec¬
tion code assigned to each page of the address space.
Bit 26 is the interrupt stack flag (IS bit) that indicates that the processor is
using the special interrupt stack rather than one of the four stacks associated
with the current process. When the IS bit is set, the current mode is always
kernel. Thus, for example software operating on the interrupt stack has full
kernel mode privileges.
Bit 27 is the first part done flag (FPD bit) that the processor uses in certain
instructions. These instructions may be interrupted or page faulted in the mid¬
dle of their execution. If the FPD bit is set when the processor returns from an
exception or interrupt, the processor resumes the interrupted operation
where it left off rather than restart the instruction.
Bit 30 is the trace pending bit (TP bit) that is used by the processor to ensure
that one trace trap occurs for each instruction performed with the trace bit
set.
Bit 31 is the compatibility mode bit (CM bit). When the CM bit is set, the
processor is in PDP-11 compatibility mode and executes PDP-11 instructions.
When the bit is clear, the processor is in native mode and executes VAX
instructions. Compatibility mode may be omitted from subset implementa¬
tions of the VAX architecture. In a processor that does not have compatibility
mode, this bit is always clear.
Asynchronous System Traps
An asynchronous system trap (AST) is used to notify a process that some
events are not synchronized with process execution. Traps are also used to ini¬
tiate processing for those events with the least possible delay.
Delay in delivery may be due to one of two causes. Either the process is not on
the system or there is an access mode mismatch. The efficient handling of
traps in VAX processors requires some hardware assistance to detect changes
in access mode.

8-8 • Exceptions and Interrupts

Each of the execution access modes may receive ASTs. However, an AST for a
less privileged access mode must not be permitted to interrupt execution in a
more privileged access mode. Because transitions to a less privileged access
mode occur only in the return from exception or interrupt instruction, compari¬
son of the current access mode field is made with a privileged register
(ASTLVL). The register contains the most privileged access mode number for
which an AST is pending. If the new access mode is greater than or equal to
the pending ASTLVL, an Interrupt Processor Level (IPL) 2 interrupt is initi¬
ated to deliver the pending AST.
NOTE
Loading an ASTLVL or LDPCTX instruction with a move to
processor register instruction does not request a software
interrupt at IPL2. During a return from exception or interrupt
instruction only can an ASTLVL instruction cause an inter¬
rupt request.
The general software flow for AST processing is described in the following
paragraphs.
1. An event associated with an AST causes software to put an AST control
block in the queue to the software process control block. Then the soft¬
ware sets the hardware process control block ASTLVL field to the most
privileged access mode for which an AST is pending. If the target process
is executing, the ASTLVL privileged register also has to be set.
2. When a return from exception or interrupt instruction detects a transition
to an access mode that can be interrupted by a pending AST, a priority
level 2 interrupt is requested to deliver the AST. Note that the instruction
does not check pending ASTs when returning to a routine executing on the
interrupt stack.
3. The priority level 2 interrupt service routine computes the new value for
ASTLVL to prevent additional AST delivery interrupts while in kernel
mode. And the service routine moves that value to the process control
block and the ASTLVL register before lowering the interrupt priority level
and actually dispatching the AST. This interrupt service routine normally
executes on the kernel stack in the context of the process receiving the
AST.
4. At the conclusion of processing for an AST, the ASTLVL is recomputed
and moved to the process control block and ASTLVL register by software.

8-9

NOTE
Two of the software interrupt priority levels are reserved for
process structure software. Interrupt priority level 2 is for
AST delivery interrupts. Interrupt priority level 3 is for pro¬
cess scheduling interrupts.

■ Exceptions
There are six types of exceptions—arithmetic, instruction fault, memory man¬
agement, operand reference, serious system failures, and tracing. All are
described in the subsequent paragraphs.
Arithmetic Exceptions
Exceptions caused by arithmetic or conversion operations are mutually exclu¬
sive and can be assigned the same vector in the system control block. Each
indicates that an exception occurred during the last instruction and that the
instruction has been either completed (in the case of a trap) or backed up (in
the case of a fault). A code identifying the exception is written on the stack as
a longword. Figure 8-2 illustrates the stack after an arithmetic exception. In
the case of a fault, the program counter of the next instruction is the same as
the instruction that caused the exception. Arithmetic exception codes are
listed in Table 8-1.

TYPE CODE
PROGRAM COUNTER OF
NEXT INSTRUCTION TO EXECUTE
PROCESSOR STATUS LONGWORD

Figure 8-2 ■ Stack after Arithmetic Exception

8-10 ■ Exceptions and Interrupts

Table 8-1 ■ Arithmetic Exception Type Codes
Code

Exception Type

Integer overflow

SRM$K_INT OVF T

Integer divide by zero

SRM$K

INT

DIV

Software Mnemonic
Traps

Floating overflow*

SRM$K

FLT

OVF

Floating/decimal divide by zero

SRM$K

FLT

DIV

Floating underflow*

SRM$K

FLT

UND

Decimal overflow

SRM$K

DEC

OVF

Subscript range

SRMJK

SUB

RNG

Floating overflow

SRM$K

FLT

OVF

Floating divide by zero

SRM$K

FLT

DIV

Floating underflow

SRM$K

FLT

UND

Faults

Not on VAX-11/750

An integer overflow trap exception indicates that the preceding instruction set
the overflow condition code bit. This trap occurs only if the integer overflow
enable bit in the processor status word is set. The result stored is the loworder part of the correct result, and type code 1 is put on the stack. The nega¬
tive and zero condition-code bits are set according to the stored result. Note
that the BISPSW, MOVTUC, REI, REMQHI, REMQTI, REMQUE, and RET
instructions do not cause an integer overflow even if they set the overflow con¬
dition code bit. EMOD instructions can cause integer overflow.
An integer divide by zero trap exception indicates that the preceding instruc¬
tion had an integer zero divisor. The result stored is equal to the dividend,
and the overflow condition code bit is set and type code 2 is put on the stack.
A decimal string divide by zero trap exception indicates that the preceding
instruction had a decimal string zero divisor. The destination, registers R0
through R5, and condition codes are unpredictable. The zero divisor can be
either positive or negative. Type code 4 is put on the stack.
A decimal string overflow trap exception indicates that the preceding instruc¬
tion had a decimal string result too large for the destination string provided,
and that decimal overflow trap enable bit is set. The overflow condition code
bit is always set. Type code 6 is put on the stack.

8-11

A subscript range trap exception indicates that the preceding instruction was
an index instruction with a subscript operand that failed the range check. The
value of the subscript operand is lower than the low operand or greater than
the high operand. The result is stored in the indexout operand and the condi¬
tion codes are set as if the operand is within range. Type code 7 is put on the
stack.
A floating-overflow fault exception indicates that the preceding instruction
resulted in an exponent greater than the largest representable exponent for
the data type. The result is normalized and rounded before comparison. The
destination is unaffected and the saved condition codes are unpredictable. The
saved program counter points to the instruction causing the fault. If the
instruction is an extended polynomial instruction, it is suspended and the pro¬
cessor status word first part done bit is set. Type code 8 is put on the stack.
A divide by zero floating fault exception indicates the preceding instruction
had a floating zero divisor. The quotient operand is unaffected, and the saved
condition codes are unpredictable. The saved program counter points to the
instruction causing the fault. Type code 9 is put on the stack.
A floating-underflow fault exception indicates that the preceding instruction
resulted in an exponent less than the smallest representable exponent for the
data type. The result is normalized and rounded before comparison. The desti¬
nation operand is unaffected, and the saved condition codes are unpredict¬
able. The saved program counter points to the instruction causing the fault. If
the instruction is an extended polynomial instruction, it is suspended and the
processor status word’s first part done bit is set. Type code A is put on the
stack.
Instruction Fault
There are four instruction faults. They are breakpoint fault, compatibility
mode fault, opcode reserved to Digital fault, and opcode reserved to users fault.
A breakpoint fault occurs when the breakpoint (BPT) instruction is executed.
No parameters are saved. To proceed from a breakpoint, a debugger or tracing
program typically restores the original contents of the location containing the
breakpoint, sets the trace enable bit in the processor status longword that was
saved by the breakpoint fault, and resumes. When the breakpointed instruc¬
tion completes, a trace exception occurs. Then the tracing program can rein¬
sert the breakpoint, restore the trace enable bit of the processor status
longword to its original state, and resume. Note that if both tracing and break¬
pointing are in progress, then on the trace exception both the breakpoint resto¬
ration and a normal trace exception should be processed by the trace handler.

8-12 ■ Exceptions and Interrupts

A compatibility mode fault occurs when the processor is in compatibility
mode. A longword of information is written to the stack. All other exceptions
in compatibility mode occur to the regular VAX vector. The compatibility
mode is an option and is not present on all VAX systems.
An opcode reserved to Digital fault occurs when the processor finds an opcode
that is not specifically defined, or one that requires higher privileges than the
current mode. No parameters are written. Opcode FFFF (hexadecimal) is
always faulted.
An opcode reserved to users fault occurs for exactly the same reasons as above
except that the event is caused by a different set of opcodes and faults through
a different vector. All user-reserved opcodes start with FC (hexadecimal). If
the special instruction needs to generate a unique exception, one of the userreserved vectors should be used. An example of a unique exception is an unrec¬
ognized second byte of an instruction.
Memory Management Exceptions
There are two memory management exceptions—the access control violation
fault, and the translation not valid fault.
An access control violation fault is an exception indicating that the process
attempted a reference not allowed at the access mode at which the process was
operating. Software may restart the process after changing the address transla¬
tion information.
A translation not valid fault indicates the process attempted a reference to a
page for which the valid bit of the page table was not set. If a process attempts
to reference a page for which the page table entry specifies both not valid and
access violation, an access control violation fault occurs.
Operand Reference Exceptions
Two types of operand reference cause exceptions—a reserved addressing mode
fault, and a reserved operand exception.
A reserved addressing mode fault is an exception that indicates an operand
specifier attempted to use an addressing mode that is not allowed. No parame¬
ters are written. A short literal specifier is not allowed in the modify, destina¬
tion, address source operand reference. A register specifier is not allowed in an
address source operand reference. An index mode specifier is not allowed
with the program counter as the index. Short literal, register and index mode
specifiers are not allowed in the index mode.

8-13

A reserved operand exception indicates that an accessed operand has a format
reserved for future use by Digital. No parameters are written. This exception
always backs up the program counter to point to the opcode. The exception
service routing may determine the type of operand by examining the opcode
using the stored program counter. Note that only the changes made by instruc¬
tion fetch and, because of operand specifier evaluation, may be restored.
Therefore, some instructions are not restartable. These exceptions are labeled
as aborts rather than faults. The program counter is always restored properly
unless the instruction attempted to modify the counter so that it has unpre¬
dictable results. With the exception of the first part done and the trace pending
bits, the processor status longword is not changed except for the condition
codes, which are unpredictable. Reserved operand exceptions are caused by
the following conditions.
■ Bit field is too wide.
■ Decimal string is too long.
■ Floating-point numbers with the sign bit set and the exponent is zero
except in the POLY table.
■ Floating-point numbers with the sign bit set and the exponent is zero in
the POLY table.

ft Incorrect source string length at completion of EDITPC instruction.
ft Invalid bit combination in a BISPSW or BICPSW instruction.
■ Invalid bit combination in PSW or MASK longword during RET instruc¬
tion.

ft Invalid CALL entry mask.
ft Invalid combinations in the process control block loaded by an LDPCTX
instruction.
■ Invalid digit in a CVTTP or CVTSP instruction.

ft Invalid operand addresses in an INSQHI, INSQTI, REMQHI, or REMQTI
instruction.

ft Invalid processor status longword bit combination stored by a return from
exception or interrupt instruction.
■ Invalid register content in MTPR instructions to some register for some
implementations.
■ Invalid register number in MFPR or MTPR instruction.

8-14 • Exceptions and Interrupts

■ Misaligned operand in ADAWI instruction.
■ POLY degree is too large.
■ Reserved pattern operator in EDITPC instruction.

Serious System Failures
Serious system failures are processed by privileged software. There are three
types of serious system failures.
■ Interrupt stack not valid—halt.
■ Kernel stack not valid—abort.
■ Machine check.

An interrupt stack not valid—halt indicates that
■ The interrupt stack was invalid.
■ A memory error occurred while the processor was writing information onto
the stack during the initiation of an exception or interrupt.

No further interrupt requests are acknowledged on this processor. The proces¬
sor leaves the program counter, the processor status longword, and the reason
for the halt in registers. That is made available to a debugger, the normal boot¬
strap routine, or an optional watchdog bootstrap routine. A watchdog boot¬
strap routine can cause the processor to leave the halted state.
Kernel stack not valid—abort exceptions indicate that the kernel stack was
not valid while the processor was writing information onto the stack during
the initiation of an exception or interrupt. Usually, this is an indication of
stack overflow or another executive software error. The attempted exception
is transformed into an abort that uses the interrupt stack. No information
other than the processor status longword and program counter is written onto
the interrupt stack. The interrupt priority level is raised to IF (hexadecimal).
Software may abort the process without aborting the system. Because of the
lost information, the process cannot be continued. If the kernel stack is not
valid during the normal execution of an instruction including change mode ker¬
nel and return from exception or interrupt instructions, the processor initiates
the normal memory management fault. If the exception vector for kernel stack
not valid is 0 or 3, the behavior of the processor is undefined.

8-15

A machine check exception indicates that the processor detected an internal
error. Machine check exceptions can be caused by such bus errors as nonexist¬
ent memory, cache parity, translation buffer parity, or by a control store par¬
ity error. Like other exceptions, this exception is taken independently of the
interrupt priority level. The level is raised to IF (hexadecimal). Implementa¬
tion-specific data is written as longwords to the stack. The processor specifies
the length parameter by placing the number of bytes written as the last longword written. This count excludes the program counter, processor status longword, and the length parameter. On the basis of presented information,
software decides whether or not to abort the current process if the machine
check came from the process. Machine check includes uncorrected bus and
memory errors, and any other processor-detected errors. Some processor
errors cannot ensure the state of the machine at all. For such errors, the state
is preserved on a best effort basis. If the exception vector for the machine
check is 0 or 3, the behavior of the processor is undefined. Under these condi¬
tions, the VAX processor halts.

Trace Exceptions
Trace exceptions occur between instructions when trace is enabled. Trace is
used for tracing programs, for performance evaluation, or for debugging pur¬
poses. The machine is designed so that one trace exception occurs before the
execution of each traced instruction. The program counter saved on a trace is
the address of the next instruction that would normally be executed. If a trace
fault and a memory management fault occur simultaneously, the order in
which the exceptions are taken is unpredictable. The trace fault for an instruc¬
tion takes precedence over all other exceptions.

8-16 • Exceptions and Interrupts

In order to ensure that exactly one trace occurs per instruction despite other
traps and faults, the processor status longword contains two bits—the trace
enable (T) bit, and the trace pending (TP) bit. If only one bit is used, the occur¬
rence of an interrupt at the end of an instruction would produce either no
trace or two traces depending on the design. The trap is implemented by copy¬
ing the trace enable bit to a second bit. The second bit is the trace pending
(TP) bit. The TP bit is used to generate the exception. The trace pending bit
generates a fault before any other processing at the start of the next instruc¬
tion.
The rules of operation for trace are as follows:
1. At the beginning of an instruction, if the trace pending bit is set, a trace
fault is taken after clearing the trace pending bit.
2. The trace pending bit is loaded with the value of the trace bit.
3. If the instruction faults or an interrupt is serviced, the trace pending bit is
cleared before writing the processor status longword. The written program
counter is set to the start of the faulting or interrupted instruction. Instruc¬
tion execution is resumed at step 1 above.
4. If the instruction aborts or takes an arithmetic trap, the trace pending bit
of the processor status longword is not changed before the processor status
longword is written.
5. If an interrupt is serviced after instruction completion and arithmetic
traps but before tracing is checked for at the start of the next instruction,
then the trace pending bit is not changed before the processor status lon¬
gword is written.
The routine entered by a change mode instruction is not traced because the
instruction clears the trace and trace pending bits in the new processor status
longword. However, if the trace bit was set at the beginning of the change
mode instruction, the trace and trace pending bits of the saved processor
status longword are set. Trace faults resume with the instructions following
the return from exception or interrupt (REI) instruction in the routine that was
entered by the change mode instruction.
An instruction following a REI faults either if the trace bit is set when the REI
instruction was executed, or if the trace pending bit is set in the saved proces¬
sor status longword. In both cases, the trace pending is set after the REI
instruction. Note that a trace fault is taken with the new processor status long¬
word if that fault occurs for an instruction following a return from exception
or interrupt that sets the trace pending bit. Thus, special care must be
observed if exception or interrupt routines are traced. If the trace bit is set by
a BISPSW instruction, trace faults begin with the second instruction after the
BISPSW instruction.

8-17

In addition, the call instructions save a clear trace bit, although the trace bit in
the processor status long word is unchanged. This is done so that a debugger or
trace program proceeding from a breakpoint fault does not get a spurious trace
from the RET instruction that matches the call instruction.
The detection of reserved instruction faults occurs after the trace fault. The
detection of interrupts and other exceptions can occur during instruction exe¬
cution. In this case, the trace pending bit is cleared before the exception or
interrupt is initiated. The entire processor status longword is saved automati¬
cally on interrupt or exception initiation and is restored at the end with an
REI instruction. This makes interrupts and benign exceptions totally transpar¬
ent to the executing program.
Routines using the trace facility are called trace handlers. When developing
handling routines, the following conventions and restrictions should be
observed.
1. When the trace handler routine returns control to the traced program, the
handler should always set the trace bit of the processor status longword
that is to be restored. This prevents other programs from clearing the bit.
2. The trace handler should never examine or alter the trace pending bit
when tracing. The hardware ensures that this bit is correctly maintained.
3. When tracing is complete, both the trace and trace pending bits must be
cleared. This ensures that tracing ceases.
4. Tracing a service routine that completes with an REI instruction initiates a
trace in the restored mode when the instruction completes. If the program
to which control is being restored was being traced, only one trace excep¬
tion is initiated.
5. If a routine entered by a call instruction is executed at full speed by clear¬
ing the trace bit, trace control can be regained by setting the trace bit in
the call frame of the processor status word. Tracing resumes after the
instruction following the RET instruction.
6. Tracing is disabled for routines entered by a change mode instruction or
any exception. If a change mode instruction or exception service routine is
to be traced, a breakpoint instruction must be placed at the entry point in
the routine. If the routine is recursive, breakpointing catches each recur¬
sion only if the breakpoint is not on the change mode instruction or the
instruction with the exception.
7. If multiple trace handlers are used, all handlers must preserve the trace bit
when turning the handler on and off. They also have to simulate traced
code that alters or reads the trace bit.

8-18 • Exceptions and Interrupts

■ Interrupts
The processor arbitrates interrupt requests according to priority. When the
interrupt request priority level is higher than the current interrupt priority
level, the processor raises the interrupt priority level and services the inter¬
rupt request. The interrupt service routine is entered at the interrupt priority
level of the interrupt request and usually does not change the interrupt prior¬
ity level set by the processor.
Interrupt requests can come from devices, controllers, other processors, or the
processor itself. Software executing in kernel mode can raise and lower the
priority of the processor by executing an MTPR instruction with the source
operand specifying the priority desired. However, a processor cannot disable
interrupts on other processors. Furthermore, the priority level of one proces¬
sor does not affect the priority level of the other processors. Thus, in multipro¬
cessor systems, interrupt priority levels cannot be used to synchronize access
to shared resources. Even the various urgent interrupts including those excep¬
tions that run at IPL IF (hexadecimal) do so on one processor only. Because of
this, special software action is required to stop other processors in a multipro¬
cessor system.
The processor services an interrupt request when the currently executing
instruction is completed. The processor also services interrupt requests at
well-defined points during the execution of long, iterative instructions. To
avoid saving additional instruction state in memory, interrupts are initiated
when the instruction state can be completely contained in the registers, proces¬
sor status longword, and program counter. The following events cause inter¬
rupts:
■ Asynchronous system trap delivery when a return from exception or inter¬
rupt instruction restores a processor status longword with the interrupt
stack bit clear, and mode greater than or equal to ASTLVL (IPL 2 (hexadeci¬
mal)).
■ Console storage device (IPL 17 (hexadecimal) or IPL 14 (hexadecimal).
■ Console terminal transmit and receive (IPL 14 (hexadecimal)).
■ Device alert (IPL 10:17 (hexadecimal)).
■ Device completion (IPL 10:17 (hexadecimal)).
■ Device error (IPL 10:17 (hexadecimal)).
■ Device memory error (IPL 10:17 (hexadecimal)).
■ Interval timer (IPL 18 (hexadecimal)).

8-19

■ Power failure (IPL IE (hexadecimal)).
■ Recovered memory, bus or processor errors (the VAX-11/750 interrupts at
IPL 1A (hexadecimal) for corrected memory reads; the VAX-11/780 at IPL
IB (hexadecimal), implementation specific).
■ Software interrupt invoked by a move to processor register instruction with
the software interrupt request register as the destination (IPL IF (hexadeci¬
mal)).
■ Unrecovered memory, bus, or processor errors (the VAX-11/750 and VAX11/780 interrupt at IPL ID (hexadecimal) for write memory errors, imple¬
mentation specific).

Each device controller has a separate set of interrupt vector locations in the
system control block. This eliminates the need to determine which controller
originated the interrupt. The vector address for each controller is fixed by
hardware.
In order to reduce interrupt overhead, memory mapping information is not
changed when an interrupt occurs. The instructions, data, and contents of the
interrupt vector for an interrupt service routine must be in the system address
space or present in every process at the same address.
Device Interrupts
Interrupt priority levels 10 through 17 (hexadecimal) are assigned to device
interrupts. Any given implementation may or may not have all levels of inter¬
rupts. For example, on the VAX-11/750, levels 14 (hexadecimal) through 17
(hexadecimal) only are available for device interrupts. These levels correspond
to the UNIBUS levels BR4 through BR7.
Software-generated Interrupts
The system software has 15 interrupt priority levels (1 through F (hexadeci¬
mal)). Refer to the VAX Software Handbook for details of these interrupts.
Two registers are used in software- generated interrupt processing—the soft¬
ware interrupt summary register, and the software interrupt request register.
The software interrupt summary register (SISR) is a privileged register that
records pending software interrupts. The register contains a value of 1 in the
bit positions corresponding to levels on which software interrupts are pend¬
ing. See Figure 8-3. All such levels must be lower than the current processor
interrupt priority level. Otherwise, the processor would have taken the
requested interrupt.

8-20 • Exceptions and Interrupts

3
1

1 1
6 5

Figure 8-3 ■ Software Interrupt Summary Register

The software interrupt summary register is a read/write register accessible
only to privileged software. During bootstrap procedures, the contents of the
register are cleared. To read the contents of the register, use the move from
processor register instruction. To write to the register, use the move to proces¬
sor register instruction. The move to processor register instruction writes to the
register; but this is not the normal way to make software interrupt requests.
The instruction is useful for clearing the software interrupt system and for
reloading its state after a power failure.
The software interrupt request register is a write-only 4-bit privileged register
used for making software interrupt requests. See Figure 8-4. Executing an
MTPR source, #SIRR instruction requests an interrupt at the level specified
by bits 0 through 3 of the source operand. After a software interrupt request
is made, the corresponding bit in the register is set. The hardware clears the
bit when the interrupt is taken. If the specified level is greater than the cur¬
rent interrupt priority level, the interrupt occurs before execution of the fol¬
lowing instruction. If the specified level is less than or equal to the current
interrupt priority level, the interrupt is deferred until the interrupt priority
level is lowered to less than the specified level with no higher interrupt level
pending. Either a return to exception or interrupt or a move to processor register
instruction lowers the level. If the value of bits 0 through 3 of the specified
source is 0, an interrupt does not occur.

4 3
IGNORED

Figure 8-4 ■ Software Interrupt Request Register

REQUEST

8-21

No indication is given if there is a request at the selected level. Therefore, the
service routine must not assume there is a one-to-one correspondence of inter¬
rupts generated to interrupts initiated. A valid protocol for generating such a
correspondence is as follows:
■ The requester uses an INSQUE instruction to replace a control block
describing the request onto a queue for the service routine.
■ The requester uses an MTPR instruction to request an interrupt at the
appropriate level.
■ The service routine uses a REMQUE instruction to remove a control block
from the queue of the service requests. If the instruction returns failure
(nothing in the queue), the service routine exits with a return from excep¬
tion or interrupt instruction.
■ If the REMQUE instruction returns with an item from the queue, the ser¬
vice routine performs the service and returns to the third step to look for
other requests.

Urgent Interrupts
The processor has eight priority levels for urgent conditions including serious
errors and powerfail. Interrupts on these levels are initiated by the processor
upon detection. Some of these conditions are not interrupts. For example, a
machine check is usually an exception. But it runs at a high priority level on
the interrupt stack. Interrupt level IE (hexadecimal) is reserved for powerfail. Interrupt level IF (hexadecimal) is reserved for those exceptions that
must lock out all processing until handled. This includes the hardware and
software disasters {kernelstack not valid and machine check). It might also be
used to allow a kernel mode debugger to gain control on any exception.
Interrupt Priority Level Register
Writing to the interrupt priority level register with the move to processor regis¬
ter instruction loads the processor priority field in the processor status longword. That is, bits 20 through 16 of the processor status longword are loaded
from bits 4 through 0 of the interrupt priority level register. Reading from the
interrupt priority level register with the move from processor register instruc¬
tion reads the processor priority field from the processor status longword.
When writing to the register, bits 5 through 31 are ignored. When reading
from the register, bits 5 through 31 are returned zero. During a bootstrap
routine, the interrupt priority level is initialized to IF (hexadecimal).

8-22 • Exceptions and Interrupts

Interrupt service routines must follow the discipline of not lowering the inter¬
rupt priority level below the initial level. If they do, an interrupt at an interme¬
diate level could cause improper stack nesting. This would fault the return
from exception or interrupt instruction. Actually, a service routine could lower
the interrupt priority level if it ensured that no intermediate levels could inter¬
rupt. However, this would result in unreliable code.
Interrupt Example
Using Example 8-1, assume the processor is running in response to an inter¬
rupt at interrupt priority level 5 (Step 1). (All numbers in this example are
hexadecimal.) Then the processor sets the interrupt priority level to 8 (Step 2)
and posts software requests at interrupt priority levels 3 (Step 3), 7 (Step 4),
and 9 (Step 5). Subsequently, a device interrupt arrives at interrupt priority
level 11 (Step 6). Finally the interrupt priority level is set back to interrupt
priority level 5 (Step 10).

Example 8-1 ■ Interrupt Sequence
State after Event Interrupt
Priority Level in Contents of
SISR PSL
Step

Event

IPL (hex) (hex)

stack

Initiate sequence

MTPR #8, #IPL instruction

MTPR #3, #SIRR instruction

MTPR #7, #SIRR instruction

MTPR #9, #SIRR instruction

8,0

Interrupts to device

9,8,0

Interrupts to device service
routine REI

.8,0

IPL 9 service routine REI

MTPR #5, #IPL instruction
changes IPL to 5 and the request
for 7 is granted immediately

5,0

IPL 7 service routine REI

Initial IPL 5 service routine REI
back to IPL 0 and the request
for 3 is granted immediately

IPL 3 service routine REI

8-23

■ System Control Block
The system control block (SCB) is a page containing the vectors by which
exceptions and interrupts are dispatched to the appropriate service routines.
The system control block base is a privileged register containing the physical
address of the system control block, which must be page-aligned. During boot¬
strap routines, the contents of the system control block base register are unpre¬
dictable. The actual length is dependent upon the system implementation
because the length represents a physical address.
NOTE
On some processors, the SCB may have additional pages that
contain the addresses of interrupt service routines for I/O
devices.
A vector is a longword in the SCB that is examined by the processor when an
exception or interrupt occurs. The vector is used to determine how to service
the event. See Table 8-2 for a list of the vectors. Separate vectors are defined
for each interrupting device controller and each class of exception. Each vec¬
tor is interpreted according to the value stored in bits 0 and 1.
If the value is 0, the event is serviced on the kernel stack unless it is running
on the interrupt stack. If it is running on the interrupt stack, it is serviced
there. Behavior of the processor is undefined for a kernel stack not valid excep¬
tion with this code.
If the value is 1, the event is serviced on the interrupt stack. If this event is an
exception, the interrupt priority level is raised to IF (hexadecimal).
If the value is 2, the event is serviced in writable control store passing bits 2
through 15 to the installation-specific microcode there. If writable control
store does not exist or is not loaded, the operation is undefined.
If the value is 3, the operation is undefined.
For values 0 and 1, bits 2 through 31 contain the virtual address of the service
routine. The address must begin on a longword boundary and is normally in
the system space. A change mode instruction is serviced on the stack selected
by the new mode. Bits 0 and 1 in the change mode vectors must be zero or the
operation is undefined.

8-24 ■ Exceptions and Interrupts

Table 8-2 ■ Event Vectors
Vector

Vector Name

(hex)*
Passive Release

Type of

Number of

Event

Parameters

Notes

May occur when an inter¬

Interrupt

rupt request is removed
before the interrupt is ini¬
tiated. IPL is that of the
request.
Machine Check

Abort or

Processor- and error-

Fault or

dependent information is

Trap

pushed onto the stack if
possible. Restartability is
processor-dependent.
IPL is raised to lF(hex)
and the interrupt stack is
used (PSL < IS >

Kernel Stack Not

Abort

1).

IPL is raised to lF(hex)
and the interrupt stack is

Valid

used (PSL < IS > <— 1).
OC
10

Powerfail

Interrupt

IPL is raised to lE(hex)

Reserved or Privi¬

Fault

Opcodes reserved to Digi¬
tal and privileged instruc¬

leged Instruction

tions
Customer-reserved

Fault

XFC instruction

Fault or

Type depends on the cir¬

Instruction
Reserved Operand

Abort
1C

Reserved Addressing Fault

Access Control Viola- Fault

cumstances
0

Mode

tion

Virtual address causing
fault is pushed onto stack

Notes:
*

(Hex) indicates the preceding number is in hexadecimal notation.

The number of bytes of parameters is pushed onto the stack and is imple¬

mentation-dependent .

8-25

Table 8-2 ■ Event Vectors (Cont.)
Vector
(hex)*

Vector Name

Type of
Event

Number of Notes
Parameters

Translation Not

Fault

Valid

Virtual address causing
the fault is pushed onto
the stack

28
2C

Trace Pending

Fault

Breakpoint Instruc¬

Fault

Fault or

tion
30

Compatibility

Arithmetic

Trap or

Reserved to Digital

CHMK

Trap

A type code is pushed onto
the stack

Fault
38:3C

A type code is pushed onto
the stack

Abort

The operand word is sign
extended and pushed onto
the stack. Vector < 1:0>
must be zeros.

CHME

Trap

The operand word is sign
extended and pushed onto
the stack. Vector < 1:0 >
must be zeros.

CHMS

Trap

The operand word is sign
extended and pushed onto
the stack. Vector < 1:0 >
must be zeros.

CHMU

Trap

The operand word is sign
extended and pushed onto
the stack. Vector < 1:0>
must be zeros.

8-26 ■ Exceptions and Interrupts

Table 8-2 ■ Event Vectors (Cont.)
Vector

Vector Name

(hex)*
50:60

Type of

Number of

Event

Parameters

Notes

Reserved for System Interrupt

IPL is implementation

Bus and Memory

dependent.

Errors
64:80

Reserved to Digital

Software Level 1

Interrupt

IPL is 1.

Software Level 2

Interrupt

IPL is 2. Ordinarily used
for AST delivery.

Software Level 3

Interrupt

IPL is 3. Ordinarily used
for process scheduling.

90:BC

Software Levels 4:F

Interrupt

Vector corresponds to IPL.

Interval Timer

Interrupt

IPL is 16 or 18(hex).

Reserved to Digital

Subset Emulation

Trap

FPD bit clear. Subset VAX
systems only.

Suspended Emula¬

Fault

D0:DC

Reserved to Digital

E0:EC

Reserved to Cus¬

FPD bit set. Subset VAX
systems only.

tion

tomer or Computer
Special Systems
(Digital)
F0

Console Storage
Receive

Interrupt

On VAX-11/730 andVAX11/750. IPL is implementa¬
tion-dependent.

8-27

Table 8-2 ■ Event Vectors (Cont.)
Vector

Vector Name

(hex)*
F4

Console Storage

Type of

Number of

Event

Parameters

Interrupt

Transmit

Notes

On VAX-11/730 and VAX11/750 only. IPL is imple¬
mentation-dependent .

Console Terminal

Interrupt

IPL is 14(hex).

Interrupt

IPL is 14(hex).

Adapter Vectors

Interrupt

IPL is 14(hex).

Adapter Vectors

Interrupt

IPL is 15(hex).

Adapter Vectors

Interrupt

IPL is 16(hex).

Adapter Vectors

Interrupt

IPL is 17(hex).

Device Vectors

Interrupt

May be any IPL

Receive
FC

Console Terminal
Transmit

100:
13C
140:
17C
180:
1BC
ICO:
1FC
200:
3FC
400:

14:17(hex).
Device Vectors

5FC

Interrupt

May be any IPL
14:17(hex).

■ Stacks
The processor is either in a process context or a systemwide interrupt service
context at all times. When in the process context, the processor is in one of
four modes (kernel, executive, supervisor, or user), and the interrupt stack
(IS) is zero. When the processor is in the systemwide interrupt service con¬
text, it operates with kernel privileges, and the interrupt stack is one. A stack
pointer (SP) is assigned to each of these five states. Whenever the processor
changes states, stack pointer R14 is stored in the process context stack
pointer for the old state and loaded from that for the new state. The process
context stack pointers are allocated in the hardware process control block.
There are four stack pointers—KSP (kernel), ESP (executive), SSP (supervi¬
sor), and USP (user).

8-28 ■ Exceptions and Interrupts

Operating system design must choose a priority level that is the boundary
between kernel and interrupt stack use. The system control block interrupt
vectors must be set so the interrupts to levels above the boundary run on the
interrupt stack and interrupts below this boundary run on the kernel stack.
Typically, asynchronous system trap delivery is on the kernel stack and higher
levels are on the interrupt stack.
In addition, VAX systems keep copies of the four process stack pointers in
privileged registers. These registers are accessed during stack switch opera¬
tions. The stack pointers in the hardware process control block are referenced
only during context switch by the save process context (SVPCTX) and load pro¬
cess context (LDPCTX) instructions.
Stack Location
The executive, supervisor, and user stacks need not be resident in main mem¬
ory. The kernel can bring in or allocate process stack pages as address transla¬
tion not valid faults occur. However, the kernel stack for the current process
and the interrupt stack must be resident and accessible. Translation not valid
and access control violation faults occurring on references to either of these
stacks are serious system failures from which recovery is impossible.
If either of these faults occurs on a kernel stack reference, the processor
aborts the current sequence and initiates a kernel stack not valid abort on hard¬
ware level IF (hexadecimal). If either fault occurs on a reference to the inter¬
rupt stack, the processor halts. Note that this does not mean every possible
reference is checked. It means the processor does not loop under these condi¬
tions. The kernel stack for processes other than the current one need not be
resident; but it must be resident before the software’s process dispatcher
selects a process to run. Further, any mechanism using access control violation
or translation not valid faults to gather process statistics must exercise care not
to invalidate kernel stack pages.
Stack Alignment
Except on call instructions, the hardware does not attempt to align the stacks.
For best performance, the software should align the stack on a longword
boundary and allocate the stack in longword increments. In order to keep the
stacks longword-aligned, the following six instructions are recommended.
■ Convert byte to longword (CVTBL).
■ Convert longword to byte (CVTLB).
■ Convert longword to word (CVTLW).
■ Convert word to longword (CVTWL).

8-29

■ Move zero-extended byte to longword (MOVZBL).
■ Move zero-extended word to longword (MOVZWL).

Status Bits
The interrupt stack bit and current mode bits in the processor status long¬
word (PSL) specify which of the five stack pointers is in use. Table 8-3 lists the
interrupt stack (IS) and current mode bits that identify the stack pointers.

Table 8-3 ■ PSL Stack Status Bits
IS Bit
Current
Register
_Mode Bit_
_1_0_Interrupt stack pointer (ISP)
0

Kernel stack pointer (KSP)

0_1_Executive stack pointer (ESP)_
0_2_Supervisor stack pointer (SSP)
0

User stack pointer (USP)

The processor does not allow the current mode bits to be set (1) when the inter¬
rupt stack bit is set. This is done by clearing the mode bits
■ When taking an exception or interrupt.
■ By causing a reserved operand fault if the return from exception or inter¬
rupt instruction attempts to load a processor status longword in which both
the interrupt status bit and current mode bits are set.

The stack to be used for an exception is selected by the current processor
status longword interrupt stack bit and the event vector bits. Figure 8-5 illus¬
trates the stack selection logic. Values 10 (binary) and 11 (binary) of the vec¬
tor are used for other purposes as described in the system control block
vectors section.

8-30 ■ Exceptions and Interrupts

VECTOR <1: 0>

KSP

ISP

PSL< IS>

Figure 8-3 ■ Stack Selection

Accessing Stack Registers
Reference to the stack pointer in the general registers will access one of five
stack pointers depending on the values of the current mode and interrupt stack
bits in the processor status longword. Some processors implement stack
pointers as processor registers. On these processors, software can access any
of the stack pointers that are not selected by the current mode and interrupt
stack bits. Results are correct even if the currently selected stack pointer is
referenced in the processor register space by an MTPR or MFPR instruction. If
the process stack pointers are implemented as registers, move processor regis¬
ter instructions are the only method for accessing the stack pointers of the
current process. If the process stack pointers are kept only in the process con¬
trol block, an MTPR or MFPR instruction might not access the process control
block.
The internal processor register numbers were chosen to be the same as bits 24
through 26 of the processor status longword. The previous stack pointer is the
same as bits 22 and 23 of the processor status longword unless the interrupt
stack bit is set. If the interrupt stack bit is set, the previous mode cannot be
determined from the processor status longword because interrupts always
clear bits 22 and 23 of that longword. At bootstrap time, the contents of all
stack pointers are unpredictable.

■ Recognition Priority
The order in which recognition of simultaneous exceptions and interrupts
takes place is as follows:
1. Arithmetic exceptions.
2. Console halt or higher priority interrupt.
3. Machine check exception.

8-31

4. Start instruction execution or restart suspended instruction.
5. Trace fault (only one per instruction).
NOTE
The order in which console halt and interrupt recognition
occurs is not dictated by the VAX architecture. Future VAX
processors may not take these in the same order as the VAX11/750 or VAX-11/780 that take console halts before inter¬
rupts.

■ Suspended Instructions
The VAX architecture allows the suspension of certain instructions at welldefined intermediate points in the execution. This is done to take memory
management faults, console halts, or interrupts. In this case, the hardware
uses processor status longword trace and trace pending bits to ensure that no
additional trace faults occur when execution is resumed.

■ Initiating an Exception or Interrupt
The handling of the event is determined by the contents of the longword vec¬
tor in the system control block. If bits 0 and 1 of the vector contain an invalid
code, the CPU behavior is unpredictable.
During the following sequence, interrupts are disabled.
1. The condition codes are replaced with zeros if bits 0 and 1 of the vector
have a value of 0 or 1.
2. The current pointer is saved and the new stack pointer is fetched if the
CPU is not executing on the interrupt stack.
3. The old processor status longword is written onto the new stack.
4. If the event being processed is either an interrupt between instructions or
a trap, this step is not performed. A copy of the program counter is stored.
Then the program counter is written onto a new stack. The value that is
saved on the stack points to an event or the next instruction to execute.
5. The new processor status longword is initialized.
6. The interrupt priority level is changed only if
— the event is an interrupt.
— the event is an exception and the processor status longword vector bits
0 and 1 is a value of 1.
7. Any and all related parameters are stored.

8-32 • Exceptions and Interrupts

8. For exceptions only, the previous mode field of the processor status longword is set to the old value of the current mode.
9. Last, the program counter is changed to point to the longword bits 2
through 31 of the vector.
If the processor received an access control violation or a translation not valid
condition while attempting to write information on the kernel stack, a kernel
stack not valid—abort is initiated. And the interrupt priority level is changed
to IF (hexadecimal). Any additional information associated with the original
exception is lost. However, the processor status longword and the program
counter are written to the interrupt stack with the same values as would have
been written on the kernel stack. If the processor receives an access control
violation or a translation not valid condition while attempting to write to the
interrupt stack, the processor is halted and only the state of interrupt stack
pointer, program counter, and processor status longword is ensured to be cor¬
rect for subsequent analysis. The processor status longword and the program
counter have the values that would have been written on the interrupt stack.
The value of the processor status longword trace pending bit that is saved on
the stack is shown in Table 8-4. The value of the program counter that is saved
on the stack is shown in Table 8-3.

Table 8-4 ■ Trace Pending Bit Saved Values
Cause of Event

Source of Value Saved

Abort

PSL TP bit

BPT instruction

(Bit is cleared.)

CHM instruction

PSL TP bit

Fault

(Bit is cleared.)

Interrupt

If EPD bit is set, this bit is cleared.
If after traps, before trace—from PSL TP bit.

Trace

(Bit is cleared.)

Trap

PSL TP bit

Reserved instructions

(Bit is cleared.)

XEC instruction

(Bit is cleared.)

8-33

Table 8-5 ■ Program Counter Saved Values
Cause of Event

Interrupt Stack Points to

Abort

The instruction aborting or detecting
the kernel-stack-not-valid condition
(not ensured on a machine check
event).

BPT instruction

The BPT instruction.

CHM instruction

The next instruction to execute.

Fault

The instruction faulting.

Interrupt

The instruction interrupted or the
next instruction to execute.

Trace

The next instruction to execute; that
is, the instruction at the beginning of
which the trace fault was taken.

Trap

The next instruction to execute.

Reserved instruction

The reserved instruction.

XFC instruction

The XFC instruction.

The noninterrupt stack pointers may be fetched and stored by hardware in
either privileged registers or in the processor control block. Only LDPCTX
and SVPCTX instructions always fetch the processor control block. Move from
processor register and move to processor register instructions always fetch and
store the pointers whether in privileged registers or the processor control
block.

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Chapter 9 ■ The Instruction Set

The instructions are arranged in alphabetic order. Notation conventions,
instruction format, and addressing modes and conventions are described in
detail in Chapter 5. No attempt is made to reiterate those details in this chap¬
ter. A general description of the instructions by category is in Chapter 6.

-Ada
Purpose: Used to perform arithmetic addition
Format: There are two formats—two operand and three operand.
operator

add.rx, sum.mx

operator

addl.rx, add2.rx, sum.vjx

Opcode

Operator

Function

ADDB2

Add Byte 2 Operand

ADDB3

Add Byte 3 Operand

ADDW2

Add Word 2 Operand

ADDW3

Add Word 3 Operand

ADDL2

Add Longword 2 Operand

ADDL3

Add Longword 3 Operand

ADDF2

Add F_floating 2 Operand

ADDF3

Add F_floating 3 Operand

ADDD2

Add D_floating 2 Operand

ADDD3

Add D_floating 3 Operand

40FD

ADDG2

Add G_floating 2 Operand

41FD

ADDG3

Add G_floating 3 Operand

60FD

ADDH2

Add H_floating 2 Operand

61FD

ADDH3

Add H_floating 3 Operand

Description: In 2-operand format, the addend operand is added to the sum
operand and the sum operand is replaced by the result. In 3-operand format,
the addend 1 operand is added to the addend2 operand and the sum operand is
replaced by the result. In floating-point format, the result is rounded.

9-2 ■ The Instruction Set

Add Aligned Word Interlocked
Purpose: Used to maintain operating system resource usage counts
Format: ADAWI

add.rw, sum.mw

Opcode

Operator

Function

ADAWI

Add Aligned Word Interlocked

Description: The addend operand is added to the sum operand and the sum
operand is replaced by the result. The operation is interlocked against similar
operations by other processors or in a multiple multiprocecessor system. The
destination must be aligned on a word boundary. Otherwise a reserved oper¬
and fault is taken.
NOTE
If the addend and the sum operand overlap, the result and
the condition codes are unpredictable.

Add Compare and Branch
Purpose: Used to maintain a loop count and loop
Format: operator

limitsx, add.rx, index.mx, displ.bw

Opcode

Operator

Function

ACBB

Add Compare and Branch Byte

ACBW

Add Compare and Branch Word

ACBL

Add Compare and Branch Longword

ACBF

Add Compare and Branch F_floating

ACBD

Add Compare and Branch D_floating

4FFD

ACBG

Add Compare and Branch G_floating

6FFD

ACBH

Add Compare and Branch H_floating

Description: The addend operand is added to the index operand and the index
operand is replaced by the result. The index operand is compared with the
limit operand. If the addend operand is positive (or 0) and the comparison is
less than or equal, or if the addend is negative and the comparison is greater
than or equal, then the sign-extended branch displacement is added to the pro¬
gram counter (PC) and the PC is replaced by the result.

9-3

NOTE
ACB efficiently implements the general FOR or DO loops in
high-level languages because the sense of the comparison
between index and limit is dependent on the sign of the
addend.

■ Add One and Branch
Purpose: Used to increment an integer loop count and loop
Format: operator

limit A, index, ml, displ.bb

Opcode

Operator

Function

AOBLSS

Add One and Branch Less Than

AOBLEQ

Add One and Branch Less Than or Equal

Description: One is added to the index operand and the index operand is
replaced by the result. The index operand is compared with the limit operand.
On AOBLSS, if the index operand is less than the limit operand, the branch is
taken. On AOBLEQ, if the index operand is less than or equal to the limit
operand, the branch is taken. If the branch is taken, the sign-extended branch
displacement is added to the program counter (PC) and the PC is replaced by
the result.

■ Add Packed
Purpose: Used to add one packed decimal string to another
Format: There are two formats—4 operand and 6 operand.
ADDP4

addlen.rw, addadr.ab, sumlen.xvj, sumadr.ab

ADDP6

addllen.rw, addladr.ab, add2len.rw, add2adr.ab, sumlen.rw,

sumadr.ab
Opcode

Operator

Function

ADDP4

Add Packed 4 Operand

ADDP6

Add Packed 6 Operand

Description: In 4-operand format, the addend string specified by the addend
length and addend address operands is added to the sum string specified by
the sum length and sum address operands and the sum string is replaced by
the result.

9-4 ■ The Instruction Set

In 6-operand format, the addend 1 string specified by the addend 1 length and
addend 1 address operands is added to the addend2 string specified by the
addend2 length and addend2 address operands. The sum string specified by
the sum length and sum address operands is replaced by the result.

■ Add with Carry
Purpose: Used to perform extended-precision addition
Format: ADWC

add.rl, sum.vcA

Opcode

Mnemonic

Function

ADWC

Add with Carry

Description: The contents of the condition code C bit and the addend oper¬
and are added to the sum operand. The sum operand is replaced by the result.

■ Arithmetic Shift
Purpose: Used to shift integers
Format: operator

count.rb, source.rx, destination.wx

Opcode

Operator

Function

ASHL

Arithmetic Shift Longword

ASHQ

Arithmetic Shift Quadword

Description: The source operand is arithmetically shifted by the number of
bits specified by the count operand, and the destination operand is replaced
by the result. The source operand is unaffected. A positive count operand
shifts to the left bringing zeros into the least significant bit. A negative count
operand shifts to the right bringing in copies of the most significant (sign) bit
into the most significant bit position. A zero count operand replaces the desti¬
nation operand with the unshifted source operand.

■ Arithmetic Shift and Round Packed
Purpose: Used to scale numeric content of a packed decimal string by a power
of 10
Format:
ASHP

cnt.rb, srclen.rw, srcadr.ab, round.rb, dstlen.rw, dstadr.ab

Opcode

Operator

Function

ASHP

Arithmetic Shift and Round Packed

9-3

Description: The source string specified by the source length and source
address operands is scaled by a power of 10 specified by the count operand.
The destination string specified by the destination length and destination
address operands is replaced by the result.
A positive count operand effectively multiplies. A negative count effectively
divides. A zero count just moves and affects condition codes. When a nega¬
tive count is specified, the result is rounded using the round operand.

■ Bit Clear
Purpose: Used to perform complemented AND of two integers
Format: There are two formats—2 operand and 3 operand
operator

mask.rx, destination.mx

operator

mask.rx, source.rx, destination.wx

Opcode

Operator

Function

BICB2

Bit Clear Byte 2 Operand

BICB3

Bit Clear Byte 3 Operand

BICW2

Bit Clear Word 2 Operand

BICW3

Bit Clear Word 3 Operand

BICL2

Bit Clear Longword 2 Operand

BICL3

Bit Clear Longword 3 Operand

Description: In 2-operand format, the destination operand is ANDed with the
one’s complement of the mask operand and the destination operand is
replaced by the result. In 3-operand format, the source operand is ANDed
with the one’s complement of the mask operand and the destination operand
is replaced by the result.

■ Bit Clear Processor Status Longword
Purpose: Used to clear trap enables
Format: BICPSW

mask.rw

Opcode

Operator

Function

BICPSW

Bit Clear PSW

Description: On BICPSW, the Processor Status Longword is ANDed with the
one’s complement of the 16-bit mask operand and the PSW is replaced by the
result.

9-6 ■ The Instruction Set

Bit Set
Purpose: Used to perform logical inclusive OR of two integers
Format: There are two formats—2 operand and 3 operand
operator

mask.rx, destination.mx

operator

mask.rx, source.rx, destination.wx

Opcode

Operator

Function

BISB2

Bit Set Byte 2 Operand

BISB3

Bit Set Byte 3 Operand

BISW2

Bit Set Word 2 Operand

BISW3

Bit Set Word 3 Operand

BISL2

Bit Set Longword 2 Operand

BISL3

Bit Set Longword 3 Operand

Description: In 2-operand format, the mask operand is ORed with the destina¬
tion operand and the destination operand is replaced by the result. In 3-oper¬
and format, the mask operand is ORed with the source operand and the
destination operand is replaced by the result.

Bit Set Processor Status Longword
Purpose: Used to set trap enables
Format: BISPSW

mask.rw

Opcode

Operator

Function

BISPSW

Bit set PSW

Description:On BISPSW, the Processor Status Longword is ORed with the
16-bit mask operand and the PSW is replaced by the result.

Bit Test
Purpose: Used to test a set of bits for all zero
Format: operand

mask.rx, source.rx

Opcode

Operator

Function

BITB

Bit Test Byte

BITW

Bit Test Word

BITL

Bit Test Longword

9-7

Description: The mask operand is ANDed with the source operand. Both oper¬
ands are unaffected. The only action is to affect condition codes.

■ Branch
Purpose: Used to transfer control
Format: operator
Opcode

displ.bx

Operator

Function

BRB

Branch with Byte Displacement

BRW

Branch with Word Displacement

Description: The sign-extended branch displacement is added to the program
counter (PC) and the PC is replaced by the result.

■ Branch on Bit
Purpose: Used to test a selected bit
Format: operator
Opcode

pos.rl, base.vh, displ.bb

Operator

Function

BBS

Branch on Bit Set

BBC

Branch on Bit Clear

Description: The single bit field specified by the position and base operands is
tested. If it is in the test state indicated by the instruction, the sign-extended
branch displacement is added to the program counter (PC) and PC is replaced
by the result.

■ Branch on Bit Interlocked
Purpose: Used to test and modify a specified bit under memory interlock
Format: operator
Opcode

pos.rl, base.vh, displ.bb

Operator

Function

BBSSI

Branch on Bit Set and Set Interlocked

BBCCI

Branch on Bit Clear and Clear Interlocked

9-8 • The Instruction Set

Description: The single bit field specified by the pos and base operands is
tested. If it is in the test state indicated by the instruction, the sign-extended
branch displacement is added to the program counter (PC) and PC is replaced
by the result. Regardless of whether or not the branch is affected, the tested
bit is put in the new state as indicated by the instruction. If the bit is stored in
memory, the reading of the state of the bit and the setting of it to the new
state constitute an interlocked operation, interlocked against similar opera¬
tions by other processors or devices in the system.

■ Branch on Bit and Modify without Interlock
Purpose: Used to test and modify a specified bit
Format: operator

pos.rl, base.vb, displ.bb

Opcode

Operator

Function

BBSS

Branch on Bit Set and Set

BBCS

Branch on Bit Clear and Set

BBSC

Branch on Bit Set and Clear

BBCC

Branch on Bit Clear and Clear

Description: The single bit field specified by the position (pos) and base oper¬
ands is tested. If it is in the test state indicated by the instruction, the signextended branch displacement is added to the program counter (PC) and PC is
replaced by the result. Regardless of whether or not the branch is taken, the
tested bit is put in the new state as indicated by the instruction.

■ Branch on Condition
Purpose: Used to test condition codes
Format: operator

displ.bb

9-9

Condition

Operator

Function

ZEQLO

BNEQ

Branch on Not Equal (Signed)

ZEQLO

BNEQU

Branch on Not Equal Unsigned

ZEQL 1

BEQL

Branch on Equal (Signed)

ZEQL1

BEQLU

Branch on Equal Unsigned

{N OR Z} EQLO

BGTR

Branch on Greater Than (Signed)

{N OR Z} EQL 1

BLEQ

Branch on Less Than or Equal
(Signed)

N EQLO

BGEQ

Branch on Greater Than or Equal
(Signed)

N EQL 1

BLSS

Branch on Less Than (Signed)

{C OR Z} EQL 0

BGTRU

Branch on Greater Than Unsigned

{C OR Z} EQL 1

BLEQU

Branch Less Than or Equal
Unsigned

V EQL 0

BVC

Branch on Overflow Clear

V EQL 1

BVS

Branch on Overflow Set

C EQLO

BGEQU

Branch on Greater Than or Equal
Unsigned

C EQL 0

BCC

Branch on Carry Clear

C EQL 1

BLSSU

Branch on Less Than Unsigned

C EQL 1

BCS

Branch on Carry Set

t Opcode
Description: The condition codes are tested, and if the condition indicated by
the instruction is met, the sign-extended branch displacement is added to the
program counter (PC) and PC is replaced by the result.
The VAX conditional branch instructions permit considerable flexibility in
branching but you need to exercise some care to choose the correct one. The
conditional branch instructions are divided into three overlapping groups:
1. The Overflow and Carry Group
BVSV

EQL 1

BVCV

EQLO

BCSC

EQL 1

BCCC

EQLO

9-10 ■ The Instruction Set

These instructions are typically used to check for overflow (when overflow
traps are not enabled), for multiprecision arithmetic, and for other special
purposes.

2. The Unsigned Group
BLSSU

CEQLl

BLEQU

{C or Z} EQL 1

BEQLU

ZEQL 1

BNEQU

Z EQL 0

BGEQU

CEQLO

BGTRU

{C OR Z} EQLO

These instructions typically follow integer and field instructions where the
operands are treated as unsigned integers, addressed instructions, and
character string instructions.

3. The Signed Group
BLSS

N EQL 1

BLEQ

{N OR Z} EQL 1

BEQL

Z EQL 1

BNEQ

ZEQLO

BGEQ

N EQLO

BGTR

{N OR Z} EQLO

These instructions typically follow integer and field instructions where the
operands are being treated as signed integers, floating- point instructions,
and decimal-string instructions.

■ Branch on Low Bit
Purpose: Used to test a specified bit
Format: operator

source.rl, displacement.bb

Opcode

Operator

Function

BLBS

Branch on Low Bit Set

BLBC

Branch on Low Bit Clear

9-11

Description: The low bit (bit 0) of the source operand is tested and if it is
equal to the test state indicated by the instruction, the sign-extended branch
displacement is added to program counter (PC) and PC is replaced by the
result.

■ Branch to Subroutine
Purpose: Used to transfer control to subroutine
Format: operator
Opcode

displ.bx

Operator

Function

BSBB

Branch to Subroutine with Byte Displacement

BSBW

Branch to Subroutine with Word Displacement

Description: The program counter (PC) is pushed on the stack as a longword.
The sign-extended branch displacement is added to PC and PC is replaced by
the result.
NOTE
Since the operand specifier conventions cause the evaluation
of the destination operand before saving PC, JSB can be used
for coroutine calls, with the stack used for linkage. The form
of such a call is JSB @(SP) + .

■ Breakpoint Fault
Purpose: Used to help to implement debugging
Format: BPT
Opcode

Operator

Function

BPT

Breakpoint Fault

Description: This instruction is used with the trace bit of the processor status
word to implement debugging facilities.

■ Bugcheck
Purpose: Used to report software-detected errors
Format: operator

message.bx

Opcode

Operator

Function

FEFF

BUGW

Bugcheck with Word Message Identifier

FDFF

BUGL

Bugcheck with Longword Message Identifier

9-12 ■ The Instruction Set

Description: The hardware treats these opcodes as Reserved to Digital and
faults. The VAX/VMS operating system treats these as requests to report soft¬
ware-detected errors. The inline message identifier is zero-extended to a longword (BUGW) and interpreted as a condition value. If the process is privileged
to report bugs, a log entry is made. If the process is not privileged, a reserved
instruction is signaled.

■ Call Procedure with General Argument List
Purpose: Used to invoke a procedure with actual arguments from anywhere in
memory
Format: CALLG

arglist.ab, dst.ab

Opcode

Operator

Function

CALLG

Call Procedure with General Argument List

Description: The stack pointer (SP) is saved in a temporary register and then
bits 1:0 are replaced by zero so that the stack is longword aligned. The proce¬
dure entry mask is scanned from bit 11 to bit 0. The contents of registers
whose number corresponds to set bits in the mask are pushed on the stack as
longwords, along with the program counter, frame pointer, and argument
pointer. The condition codes are cleared. A longword containing the saved
two low bits of SP in bits 31:30, a zero in bit 29 and bit 28, the low 12 bits of
the procedure entry mask in bits 27:16, and in bits 15 through 0 of the proces¬
sor status word, with the T bit cleared is pushed on the stack. A longword zero
is pushed on the stack. The frame pointer is replaced by the stack pointer. The
argument pointer is replaced by the arglist operand that specifies the address
of the actual argument list. The trap enables in the processor status word are
set to a known state. Integer overflow and decimal overflow are affected
according to bits 14 and 15 of the entry mask, respectively; floating under¬
flow is cleared. The T bit is unaffected. PC is replaced by the sum of destina¬
tion operand and 2 that transfers control to the called procedure at the byte
beyond the entry mask.
NOTE
The VMS Procedure Calling Software Standard and the con¬
dition handling facility require the following register saving
conventions. R0 and R1 are always available for function
return values and are never saved in the entry mask. Regis¬
ters 2 through 11 which are modified in the called procedure
must be preserved in the mask.

9-13

■ Call Procedure with Stack Argument List
Purpose: Used to invoke a procedure with actual arguments or addresses on
the stack
Format: CALLS

numarg.rl, dst.ab

Opcode

Operator

Function

CALLS

Call Procedure with Stack Argument List

Description: The numarg operand is pushed on the stack as a longword (byte 0
contains the number of arguments; the high-order 24 bits are used by Digital
software). SP is saved in a temporary location and then bits 1:0 of SP are
replaced by zero so that the stack is longword aligned. The procedure entry
mask is scanned from bit 11 to bit 0 and the contents of the register whose
number corresponds to set bits in the mask are pushed on the stack. PC, FP,
and AP are pushed on the stack as longwords. The condition codes are cleared.
A longword containing the saved two low bits of SP in bits 31:30, a 1 in bit 29,
0 in bit 28, the low 12 bits of the procedure entry mask in bits 27:16, and the
PSW in bits 15:0 with the T bit cleared is pushed on the stack. A longword
zero is pushed on the stack. FP is replaced by SP. AP is set to the saved SP (the
value of the Stack Pointer after the number of arguments operand was pushed
on the stack). The trap enables in the PSW are set to a known state. Integer
overflow and decimal overflow are affected according to bits 14 and 15 of the
entry mask, respectively; floating underflow is cleared; the T bit is unaf¬
fected. PC is replaced by the sum of destination operand and 2, which trans¬
fers control to the called procedure at the byte beyond the entry mask.
NOTES
1. Normally, the arglist is pushed onto the stack in reverse
order prior to the CALLS. On return, the arglist is removed
from the stack automatically.
2. The VMS Procedure Calling Software Standard and the
condition handling facility require the following register sav¬
ing conventions. R0 and Rl are always available for function
return values and are never saved in the entry mask. All regis¬
ters 2 through 11 that are modified in the called procedure
must be preserved in the entry mask.

9-14 • The Instruction Set

Case
Purpose: Used to perform multiple branching depending upon arithmetic
input
Format:
operator

selector.rx, base.rx, limit.rx, displ [0].bw,...ydispl [limit].bw

Opcode

Operator

Function

CASEB

Case Byte

CASEW

Case Word

CASEL

Case Longword

Description: The base operand is subtracted from the selector operand and a
temporary operand is replaced by the result. The temporary operand is com¬
pared with the limit operand and if it is less than or equal unsigned, a branch
displacement selected by the temporary value is added to the program counter
(PC) and the PC is replaced by the result. Otherwise, 2 times the sum of the
limit operand and 1 is added to the PC and the PC is replaced by the result.
This causes the PC to be moved past the array of branch displacements.
Regardless of the branch taken, the condition codes are affected by the com¬
parison of the temporary operand with the limit operand.
This instruction implements high-level language computed GOTO statements.
You supply a list of displacements that generate different branch addresses
depending on the value you obtain as a selector. The branch falls through if
the selector does not generate any of the displacements on the list.
NOTE
After operand evaluation, PC is pointing at displ[0]—not the
next instruction. The branch displacements are relative to
the address of displ[0].

Change Mode
Purpose: Used to request higher privilege software
Format: operator

code.rw

Opcode

Operator

Function

CHMK

Change Mode to Kernel

CHME

Change Mode to Executive

CHMS

Change Mode to Supervisor

CHMU

Change Mode to User

9-15

Description: Change mode instructions allow processors to change their
access mode in a controlled manner. The instruction increases privilege only.
A change in mode also results in a change of stack pointers. The old pointer is
saved, and the new pointer is loaded. The PSL, PC, and any code passed by the
instruction are pushed onto the stack of the new mode. The saved PC
addresses the instruction following the CHMx instruction. The code is sign
extended. After execution, the new stack’s appearance is
sign extended code

:(SP)

PC of next instruction
Old PSL
The destination mode selected by the opcode is used to select a location from
the System Control Block. This location addresses the CHMx dispatcher for
the specified mode.

■ Clear
Purpose: Used to clear a scalar quantity
Format: operator
Opcode

destination.wx

Operator

Function

CLRB

Clear Byte

CLRW

Clear Word

CLRL

Clear Longword

CLRQ

Clear Quadword

7CFD

CLRO

Clear Octaword

CLRD

Clear D_floating

CLRF

Clear F_floating

CLRG

Clear G_floating

7CFD

CLRH

Clear H_floating

Description: The destination operand is replaced by 0.

■ Compare
Purpose: Used to perform an arithmetic comparison between two specified
scalar quantities
Format: operator

srcl.rx, src2.rx

9-16 • The Instruction Set

Opcode

Operator

Function

CMPB

Compare Byte

CMPW

Compare Word

CMPL

Compare Longword

CMPF

Compare F_floating

CMPD

Compare D_floating

31FD

CMPG

Compare G_floating

71FD

CMPH

Compare H_floating

Description: The srcl operand is compared with the src2 operand. The only
action is to affect the condition codes.

■ Compare Characters
Purpose: Used to compare two character strings
Format: There are two formats—3 operand and 3 operand.
CMPC3

/e«.rw, srcladr. ab, src2adr. ab

CMPC3

srcllen.xvj, srcladr. 3b, fill, rb, src2len. rw, src2adr.ab

Opcode

Operator

Function

CMPC3

Compare Characters 3 Operand

CMPC3

Compare Characters 5 Operand

Description: In 3-operand format, the first string is specified by the srcladr
operand. The second string is specified by the src2adr operand. The strings
are compared until inequality is detected or until all the bytes of the strings
have been examined. Condition codes are affected by the result of the last
byte comparison.
In 3-operand format, the bytes of one string are compared to the bytes of the
second string. If one string is longer than the other, the shorter string is con¬
ceptually extended to the length of the longer by appending (at higher
addresses) bytes equal to the fill operand. Comparison proceeds until inequal¬
ity is detected or all the bytes of the strings have been examined. Condition
codes are affected by the result of the last byte comparison.
NOTE
1. After execution of a 3-operand instruction RO = number
of bytes remaining in string 1 including byte that terminated
comparison, R1 = address of the byte in string 1 that termi¬
nated comparison, R2 = RO, R3 = address of the byte in
string 2 that terminated the comparison.

9-17

2. After execution of a 5-character instruction RO = the num¬
ber of bytes remaining in string 1 including the byte that ter¬
minated comparison, R1 = address of the byte in string 1
that terminated comparison, R2 = the number of bytes
remaining in string 2 including the byte that terminated com¬
parison, and R3 = the address of the byte in string 2 that
terminated comparison.

■ Compare Field
Purpose: Used to compare bit field to integer
Format: operator
Opcode

pos.rl, size.rb, base.vb, src.rl

Operator

Function

CMPV

Compare Field

CMPZV

Compare Zero-extended Field

Description: The field specified by the position, size, and base operands is
compared with the source operand. For CMPV, the source operand is com¬
pared with the sign-extended field. For CMPZV, the source operand is com¬
pared with the zero-extended field. The only action is to affect the condition
codes.

■ Compare Packed
Purpose: Used to compare two packed decimal strings and set condition codes
Format: There are two formats—3 operand and 4 operand.
CMPP

len. rw, scrladr.ab, src2adr. ah

CMPP

src lien, rw, srcladr. ab, src2len. rw, src2adr. ab

Opcode

Operator

Function

CMPP3

Compare Packed—3 Operand

CMPP4

Compare Packed—4 Operand

Description: In 3-operand format, the srcl string is compared to the src2
string. The only action is to affect the condition codes.
In 4-operand format, the srcl string is compared to the src2 string. The only
action is to affect the condition codes.

9-18 • The Instruction Set

■ Convert
Purpose: Used to convert a signed quantity to a different signed data type
Format: operator

src.rx, dst.vry

Opcode

Operator

Function

CVTBW

Convert Byte to Word

CVTBL

Convert Byte to Longword

CVTWB

Convert Word to Byte

CVTWL

Convert Word to Longword

CVTLB

Convert Longword to Byte

CVTLW

Convert Longword to Word

CVTBF

Convert Byte to F_floating

CVTBD

Convert Byte to D_floating

4CFD

CVTBG

Convert Byte to G_floating

6CFD

CVTBH

Convert Byte to H_floating

CVTWF

Convert Word to F_floating

CVTWD

Convert Word to D_floating

4DFD

CVTWG

Convert Word to G_floating

6DFD

CVTWH

Convert Word to H_floating

CVTLF

Convert Longword to F_floating

CVTLD

Convert Longword to D_floating

4EFD

CVTLG

Convert Longword to G_floating

6EFD

CVTLH

Convert Longword to H_floating

CVTFB

Convert F_floating to Byte

CVTDB

Convert D_floating to Byte

48FD

CVTGB

Convert G_floating to Byte

68FD

CVTHB

Convert H_floating to Byte

CVTFW

Convert F_floating to Word

CVTDW

Convert D_floating to Word

49FD

CVTGW

Convert G_floating to Word

69FD

CVTHW

Convert H_floating to Word

9-19

CVTFL

Convert F_floating to Longword
Convert Rounded F_floating to Longword

CVTRFL

CVTDL

Convert D_floating to Longword

CVTRDL

Convert Rounded D_floating to Longword

4AFD

CVTGL

Convert G_floating to Longword

48FD

CVTRGL

Convert Rounded G_floating to Longword

6AFD

CVTHL

Convert H_floating to Longword

6BFD

CVTRHL

Convert Rounded H_floating to Longword

CVTFD

Convert F_floating to D_floating

99FD

CVTFG

Convert F_floating to G_floating

98FD

CVTFH

Convert F_floating to H_floating

CVTDF

Convert D_floating to F_floating

32FD

CVTDH

Convert D_floating to H_floating

33FD

CVTGF

Convert G_floating to F_floating

56FD

CVTGH

Convert G_floating to H_floating

F6FD

CVTHF

Convert H_floating to F_floating

F7FD

CVTHD

Convert H_floating to D_floating

76FD

CVTHG

Convert H_floating to G_floating

Description: The source operand is converted to the data type of the destina¬
tion operand and the destination operand is replaced by the result. For integer
format, conversion of a shorter data type to a longer is done by sign extension.
Conversion of longer to a shorter is done by truncation of the higher num¬
bered (most significant) bits. For floating format, the form of the conversion
is as follows:

9-20 • The Instruction Set

Exact Conversion

Truncated Conversion

Rounded Conversion

CVTBF

CVTHW

CVTLF

CVTBD

CVTFL

CVTDF

CVTBG

CVTFB

CVTRHL

CVTBH

CVTDL

CVTRFL

CVTWF

CVTDB

CVTRDL

CVTWD

CVTGL

CVTHG

CVTWG

CVTHL

CVTRGL

CVTWH

CVTGB

CVTGF

CVTLD

CVTFW

CVTHF

CVTFD

CVTDW

CVTHD

CVTLG

CVTGW

CVTLH

CVTHB

CVTFH
CVTFG
CVTDH
CVTGH

Convert Leading Separate Numeric to Packed
Purpose: Used to convert leading separate numeric string to packed decimal
string
Format: CVTSP

srclen.tvj, srcadr.ab, dstlen.rw, dstadr.ab

Opcode

Operator

Function

CVTSP

Convert Leading Separate Numeric to Packed

Description: The source numeric string specified by the source length and
source address operands is converted to a packed decimal string, and the desti¬
nation string specified by the destination address and destination length oper¬
ands is replaced by the result.

Convert Longword to Packed
Purpose: Used to convert longword integer to packed decimal string
Format: CVTLP

src.rl, dstlen.rw, dstadr.ab

Opcode

Operator

Function

CVTLP

Convert Long to Packed

9-21

Description: The destination string is specified by the destination length and
address operands. The source operand is converted to a packed decimal string
and the destination string is replaced by the result.

■ Convert Packed to Leading Separate Numeric
Purpose: Used to convert packed decimal string to leading separate numeric
string
Format: CVTPS

srclen.rvj, srcadr.ab, dstlen.rw, dstadr.ab

Opcode

Operator

Function

CVTPS

Convert Packed to Leading Separate Numeric

Description: The source packed decimal string specified by the source length
and source address operands is converted to a leading separate numeric string.
The destination string specified by the destination length and destination
address operands is replaced by the result.
Conversion is effected by replacing the lowest addressed byte of the destina¬
tion string by the ASCII plus or minus characters which is determined by the
sign of the source string. The remaining bytes of the destination string are
replaced by the ASCII representations of the values of the corresponding
packed decimal digits of the source string.

■ Convert Packed to Longword
Purpose: Used to convert a packed decimal string to a longword
Format: CVTPL

srclen.rw, srcadr.ab, dst.wl

Opcode

Operator

Function

CVTPL

Convert Packed to Long

Description: The source string specified by the source length and source
address operands is converted to a longword and the destination operand is
replaced by the result.

9-22 ■ The Instruction Set

■ Convert Packed to Trailing Numeric
Purpose: Used to convert packed decimal string to trailing numeric string
Format: CVTPT

srclen.rw, srcadr.ab, tbladr.ab, dstlensw, dstadr.ab

Opcode

Operator

Function

CVTPT

Convert Packed to Trailing Numeric

Description: The source packed decimal string specified by the source length
and source address operands is converted to a trailing numeric string. The des¬
tination string specified by the destination length and destination address
operands is replaced by the result. The condition code N and Z bits are
affected by the value of the source packed decimal string.
Conversion is effected by using the highest addressed byte of the source
string as an unsigned index into a 256-byte table whose zeroth entry address
is specified by the table address operand. The byte read out of the table
replaces the least significant byte of the destination string. The remaining
bytes of the destination string are replaced by the ASCII representations of
the values of the corresponding packed decimal digits of the source string.
NOTE
By appropriate specification of the table, conversion to any
form of trailing numeric string may be realized. See Chapter
4 for the preferred form of trailing overpunch, zoned, and
unsigned data. In addition, the table may be set up for abso¬
lute value, negative absolute value, or negative conversions.

9-23

■ Convert Trailing Numeric to Packed
Purpose: Used to convert trailing numeric string to packed decimal string
Format: CVTTP

srclen.rw, srcadr.ab, tbladr.ab, dstlen.rw, dstadr.ab

Opcode

Operator

Function

CVTTP

Convert Trailing Numeric to Packed

Description: The source trailing numeric string specified by the source length
and source address operands is converted to a packed decimal string. The des¬
tination packed decimal string specified by the destination address and desti¬
nation length operands is replaced by the result.
Conversion is effected by using the highest addressed (trailing) byte of the
source string as an unsigned index into a 256-byte table whose zeroth entry is
specified by the table address operand. The byte read out of the table replaces
the highest addressed byte of the destination string; that is, the byte contain¬
ing the sign and the least significant digit. The remaining packed digits of the
destination string are replaced by the low-order four bits of the corresponding
bytes in the source string.
NOTES
1. By appropriate specification of the table, conversion from
any form of trailing numeric string may be realized. In addi¬
tion, the table may be set up for absolute value, negative abso¬
lute value or negated conversions. Refer to Chapter 4 for the
preferred form of trailing overpunch, zoned, and unsigned
data.
2. If the table translation produces a sign nibble containing
any valid sign, the preferred sign representation is stored in
the destination packed decimal string.

■ Cyclic Redundancy Check Instruction
Purpose: Used to initiate communications or software redundancy checks
Format: CRC

tbl.ab, inicrc.rl, strlen.rw, stream.ab

Opcode

Operator

Function

CRC

Calculate Cyclic Redundancy Check

9-24 ■ The Instruction Set

Description: The CRC of the data stream described by the string descriptor is
calculated. The initial CRC is given by inicrc and is normally 0 or -1 unless the
CRC is calculated in several steps. RO is replaced by the result. If the polyno¬
mial is less than order-32, the result must be extracted from RO. The CRC
polynomial is expressed by the contents of the 16-longword table. See the
Notes for calculation of the table.
NOTES
1. If the data stream is not a multiple of eight bits long, it
must be right-adjusted with leading zero fill.
2. If the CRC polynomial is less than order-32, the result
must be extracted from the low-order bits of RO.
3. The following algorithm can be used to calculate the CRC
table given a polynomial expressed as follows:
poly<n> — {coefficient of x**{ order-l-n}}
This routine is available as system library routine LIB$CRC_TABLE (POLY, TABLE). The table is the location of a
64-byte (16-longword) table into which the result is written.
4. The following are descriptions of some commonly used
CRC polynomials.

■ CRC-16 (used in DDCMP and Bisync):
Polynomial: X16 + X15 + X2 + 1
Poly: 120001 (octal)
Initialize: 0
Result: RO < 15:0 >

■ CCITT (used in ADCCP, HDLC, SDLC):
Polynomial: X16 + X12 + X5 + 1
Poly: 102010 (octal)
Initialize: -1 < 15:0 >
Result: one’s complement of R0 < 15:0 >

9-25

■ AUTODIN-II
Polynomial: X32 + X26 + X23 + X22 + X16 + X12 + X11
+ X10 + Xs + X7 + X3 + X4 + X2 + X + 1
Poly: EDB88320 (hexadecimal)
Initialize: —1 < 31:0 >
Result: one’s complement of R0 < 31:0 >
5. This instruction produces an unpredictable result unless
the table is well formed, such as produced in Note 3. Note
that for any well-formed table, entry [0] is always 0 and entry
[8] is always the polynomial expressed as in Note 3. The oper¬
ation can be implemented using shifts of one, two, or four
bits at a time as follows:

Shift: 1
Steps per byte (limit): 8
Index table index: tmp3 < 0 >
Table multiplier: 8
Use table entries: [0] = 0, < 8>

Shift: 2
Steps per byte (limit): 4
Index table index: tmp3 < 1:0 >
Table multiplier: 4
Use table entries: [0] = 0,[4],[8],[12]

Shift: 4
Steps per byte (limit): 2
Index table index: tmp3 < 3:0 >
Table multiplier: 1
Use table entries: all

- *' •

Vs£TVv

9-26 ■ The Instruction Set

Decrement
Purpose: Used to subtract 1 from an integer
Format: operator

difference.mx

Opcode

Operator

Function

DECB

Decrement Byte

DECW

Decrement Word

DECL

Decrement Longword

Description: One is subtracted from the difference operand and the differ¬
ence operand is replaced by the result.

Divide
Purpose: Used to perform arithmetic division
Format: There are two formats—2 operand and 3 operand.
operator

divr.tx, quo.mx

operator

divr.rx, divd. rx, quo.wx

Opcode

Operator

Function

DIVB2

Divide Byte 2 Operand

DIVB3

Divide Byte 3 Operand

DIVW2

Divide Word 2 Operand

DIVW3

Divide Word 3 Operand

DIVL2

Divide Longword 2 Operand

DIVL3

Divide Longword 3 Operand

DIVF2

Divide F_floating 2 Operand

DIVF3

Divide F_floating 3 Operand

DIVD2

Divide D_floating 2 Operand

DIVD 3

Divide D_floating 3 Operand

46FD

DIVG2

Divide G_floating 2 Operand

47FD

DIVG3

Divide G_floating 3 Operand

66FD

DIVH2

Divide H_floating 2 Operand

67FD

DIVH3

Divide H_floating 3 Operand

9-27

Description: In 2-operand format, the quotient operand is divided by the divi¬
sor operand, and the quotient operand is replaced by the result.
In 3-operand format, the dividend operand is divided by the divisor operand
and the quotient operand is replaced by the result. In floating format, the quo¬
tient operand result is rounded for both 2- and 3-operand formats.
Integer division is performed so that the remainder (unless it is zero) has the
same sign as the dividend. That is, the result is truncated toward zero.

■ Divide Packed
Purpose: Used to divide one packed decimal string by a second, with the result
placed in a third
Format:
DIVP
divrlen. rw,
quoadr.ab

divradr. ab,

divdlen.vu,

Opcode

Operator

Function

DIVP

Divide Packed

divdadr.ab,

quolen.rw,

Description: The dividend string is specified by the dividend length and divi¬
dend address operands. The divisor string is specified by the divisor length
and divisor address operands. The quotient string is specified by the quotient
length and quotient address operands. The dividend string is divided by the
divisor string. The quotient string is replaced by the result. The division is
performed in the following manner:
1. The absolute value of the remainder (which is lost) is less than the absolute
value of the divisor.
2. The product of the absolute value of the quotient and the absolute value of
the divisor is less than or equal to the absolute value of the dividend.
3. The sign of the quotient is determined by the rules of algebra from the
signs of the dividend and the divisor. If the value of the quotient is zero,
the sign is always positive.

■ Edit Instruction
Purpose: Used to edit a source string
Format: EDITPC

srclen.rw, srcadr.ab, pattern.ab, dstadr.ab

Opcode

Operator

Function

EDITPC

Edit Packed to Character String

9-28 ■ The Instruction Set

Description: The destination string is specified by the pattern and destination
address (dstadr) operands. The source string is specified by the source length
(srclen) and source address (srcadr) operands. The destination string is
replaced by the edited version of the source string.
Editing is performed according to the pattern string. The pattern string con¬
sists of one-byte pattern operators. Editing starts at the address pattern and
extends until an end (EO$END) pattern operator is encountered. Some pat¬
tern operators take no operands. Some take a repeat count that is in the
rightmost nibble of the pattern operator itself. The rest take a one-byte oper¬
and that immediately follows the pattern operator. This operand is either an
unsigned integer length or a byte character. Pattern operators are described
on subsequent pages and are summarized in Table 9-1.
Table 9-1 ■ Edit Instruction Pattern Operators
Operand*

Function Name
Control:

EO$ ADJUST_INPUT len

Adjust source length.

EO$CLEAR_ SIGNIF

—

Clear significance flag.

EO$END

—

End edit.

—

Set significance flag.

len

Fill backward when zero.

EO$SET
Fixup:

SIGNIF

EO$BLANK_ZERO
EO$REPLACE

Insert:

Move:

SIGN len

Replace with fill if -0.

EO$FILL

rep

Insert fill.

EO$INSERT

char

Insert character, fill if insignifi¬
cant.

—

Insert sign.

EO$STORE
Load:

Summary

SIGN

EO$LOAD_FILL

char

Load fill character.

EO$LOAD_MINUS

char

Load sign character if negative.

EOfLOAD_PLUS

char

Load sign character if positive.

EO$LOAD

char

Load sign character.

EO$END_FLOAT

—

End floating sign.

EOfFLOAT

rep

Move digits, floating sign.

EO$MOVE

rep

Move digits, filling insignificant.

SIGN

* char = one character
len = length in the range 1 through 255
rep = repeat counter in the range 1 through 15

9-29

The following definitions are used:
fiH = R2 < 7:0>
sign = R2< 15:8 >

EO$ ADJUST

INPUT

Purpose: Used to handle source strings of a length different from the output
string
Format: EO$ADJUST_ INPUT

len

Opcode

Pattern Operator

Function

EO$ADJUST

Adjust Input Length

INPUT

Description: The pattern operator is foUowed by an unsigned byte integer
length in the range 1 through 31. If the source string has more digits than the
length, the excess digits are read and discarded. If any discarded digits are not
zero, the overflow and significance bits are set, and the zero bit is cleared. If
the source string has fewer digits than the length, a counter is set to the num¬
ber of leading zeros to supply. This counter is stored as a negative number in
register RO in bits 31 through 16.

EOJBLANK_ZERO
Purpose: Used to fix the destination to be blank when the source value is zero
Format: EO$BLANK_ZERO

len

Opcode

Pattern Operator

Function

EO$BLANK

Blank Backwards When Zero

ZERO

Description: The pattern operator is followed by an unsigned byte integer
length. If the value of the source string is zero, the contents of the fill register
are stored into the last length bytes of the destination string.
NOTE
This pattern operator is used to blank any characters stored
in the destination under a forced significance such as a sign or
the digits following the radix point.

EOJCLEAR_SIGNIF
Purpose: Used to control the significance (leading zero) indicator
Format: EO$CLEAR__ SIGNIF
Opcode

Pattern Operator

Function

EO$CLEAR

Clear Significance

SIGNF

9-JO ■ The Instruction Set

Description: The significance indicator is cleared. This controls the treatment
of leading zeros. (Leading zeros are zero digits for which the significance indi¬
cator is clear.) EO$CLEAR_SIGNIF is used to initialize leading zero suppres¬
sion (EO$MOVE) or floating sign (EOJFLOAT) following a fixed insert
(EO$INSERT with significance set).

EO$END
Purpose: Used to end edit operation
Format: EO$END
Opcode

Pattern Operator

Function

EO$END

End Edit

Description: The edit operation is terminated.

EO$END_FLOAT
Purpose: Used to end a floating-sign operation
Format: EO$END_FLOAT
Opcode

Pattern Operator

Function

EO$END_FLOAT

End Floating Sign

Description: If the floating sign has not yet been placed in the destination
(that is, if significance is not set), the contents of the sign register are stored in
the destination and significance is set.
NOTE
This pattern operator is used after a sequence of one or more
EO$FLOAT pattern operators that start with significance
clear. The EOfFLOAT sequence can include intermixed
EO$INSERTs and EO$FILLs.

EOJFILL
Purpose: Used to insert the fill character
Format: EO$FILL

rep

Opcode

Pattern Operator

Function

81:8F

EOJFILL

Store Fill

Description: The right nibble of the pattern operator is the repeat count. The
contents of the fill register are placed into the destination the number of times
specified in the rep operand. This pattern operator is used for fill (blank) inser¬
tion.

9-31

EOfFLOAT
Purpose: Used to move digits, floating the sign across insignificant digits
Format: EO$FLOAT

rep

Opcode

Pattern Operator

Function

A1:AF

EOfFLOAT

Float Sign

Description: The right nibble of the pattern operator is the repeat count. For
repeat iterations, the following algorithm is executed the number of times
specified in the repeat count (rep) operand.
Repeat Count Algorithm—The next digit from the source is examined for one
of two conditions:
■ If the next digit is nonzero and significance is not yet set, the contents of
the sign register are stored in the destination, the significance bit is set,
and the zero bit is cleared.
■ If the digit is significant, it is stored in the destination. Otherwise, the
content of the fill register is stored in the destination.

This pattern operator is used to move digits with a floating arithmetic sign.
The sign must already be set up as for EO$STORE_SIGN. A sequence of one
or more EOjFLOATs can include intermixed EOjINSERTs and EO$FILLs.
Significance must be clear before the first pattern operator of the sequence.
The sequence must be terminated by one EO$END_FLOAT.
This pattern operator is used to move digits with a floating currency sign. The
sign must already be set up with an EOJLOAD_SIGN. A sequence of one or
more EO$FLOATs can include intermixed EOJINSERTs and EOjFILLs. Sig¬
nificance must be clear before the first pattern operator of the sequence. The
sequence must be terminated by one EO$END_FLOAT.

EOJINSERT
Purpose: Used to insert a fixed character, substituting the fill character if not
significant
Format: EOJINSERT

char

Opcode

Pattern Operator

Function

EOJINSERT

Insert Character

Description: The pattern operator is followed by a character. If the signifi¬
cance bit is set, the character is placed into the destination. If the significance
bit is not set, the contents of the fill register are placed into the destination.

9-32 ■ The Instruction Set

NOTE
This pattern operator is used for blankable inserts (for exam¬
ple, comma) and fixed inserts (for example, slash). Fixed
inserts require that significance be set by EO$SET_SIGNIF
or EO$END_FLOAT.

EOJLOAD
Purpose: Used to change the contents of the fill or sign register
Format: pattern_operator

char

Opcode

Pattern Operator

Function

EO$LOAD_ FILL

Load Fill Register

EO$LOAD_SIGN

Load Sign Register

EO$LOAD_PLUS

Load Sign Register If Plus

EO$LOAD_ MINUS

Load Sign Register If Minus

Description: The pattern operator is followed by a character. For EO$LOAD
_FILL, this character is placed into the fill register. For EO$LOAD_SIGN,
this character is placed into the sign register . For EO$LOAD_PLUS, this
character is placed into the sign register if the source string has a positive sign.
For EOfLOAD_MINUS, this character is placed into the sign register if the
source string has a negative sign.
NOTES
1. EO$LOAD_FILL is used to set up check protection
instead of space.
2. EO$LOAD_SIGN is used to set up a floating currency
sign.
3. EOfLOAD_PLUS is used to set up a nonblank plus sign.
4. EOJLOAD_MINUS is used to set up a alternate minus
sign such as CR, DB, or the PL/1 + .

EO$MOVE
Purpose: Used to move digits, filling for insignificant digits (leading zeros)
Format: EO$MOVE

rep

Opcode

Pattern Operator

Function

91:9F

EO$MOVE

Move Digits

Description: The right nibble of the pattern operator is the repeat count. For
repeat iterations, the following algorithm is executed the number of times
specified in the repeat count (rep) operand.

9-33

The next digit is moved from the source to the destination under the following
conditions:
■ If the digit is nonzero, the significance bit is set and the zero bit is cleared.
■ If the digit is not significant (that is, it is a leading zero), it is replaced by
the contents of the fill register in the destination.

NOTES
1. This pattern operator is used to move digits without a float¬
ing sign. If leading zero suppression is desired, the signifi¬
cance bit must be clear. If leading zero should be explicit, the
significance bit must be set. A string of EO$MOVE operators
intermixed with EOflNSERT and EO$FILL operators cor¬
rectly handles suppression.
2. If check protection (*) is desired, EOJLOAD_FILL must
precede the EO$MOVE.

EO$REPLACE_SIGN
Purpose: Used to change the destination sign when the value is minus zero
Format: EO$REPLACE_SIGN

len

Opcode

Pattern Operator

Function

EO$REPLACE

Replace Sign When Minus Zero

SIGN

Description: The pattern operator is followed by an unsigned byte integer
length. If the value of the source string is zero (that is, if the Z bit is set), the
contents of the fill register are stored into the byte of the destination string
that is len bytes before the current position.
NOTES
1. The length must be nonzero and within the destination
string already produced.
2. This pattern operator is used to correct a stored sign
(EOfEND_FLOAT or EO$STORE_ SIGN) if a minus was
stored and the source value is zero.

EOfSET_SIGNIF
Purpose: Used to control the significance (leading zero) indicator
Format: EO$SET_ SIGNIF
Opcode

Pattern Operator

Function

EO$SET

Set Significance

SIGNIF

9-34 • The Instruction Set

Description: The significance indicator is set. This controls the treatment of
leading zeros. (Leading zeros are zero digits for which the significance indica¬
tor is clear.) EOJSET_SIGNIF is used to avoid leading suppression (before
EO$MOVE) or to force a fixed insert (before EOJINSERT).

EO$ STORE_SIGN
Purpose: Used to insert the sign character
Format: EO$STORE_ SIGN
Opcode

Pattern Operator

Function

EO$STORE

Store Sign

SIGN

Description: The contents of the sign register are placed into the destination.

NOTE
This pattern operator is used for any nonfloating arithmetic
sign. It should be preceded by a EO$LOAD_PLUS and/or
EO$LOAD_MINUS if the default sign convention is not
desired.

■ Exclusive OR
Purpose: Used to perform logical exclusive OR of two integers
Format: There are two formats—2 operand and 3 operand
operator

mask.rx, destination.mx

operator

mask.rx, source.rx, destination.wx

Opcode

Operator

Function

XORB2

Exclusive OR Byte 2 Operand

XORB3

Exclusive OR Byte 3 Operand

XORW2

Exclusive OR Word 2 Operand

XORW3

Exclusive OR Word 3 Operand

XORL2

Exclusive OR Longword 2 Operand

XORL3

Exclusive OR Longword 3 Operand

Description: In 2-operand format, the mask operand is XORed with the desti¬
nation operand and the destination operand is replaced by the result. In 3operand format, the mask operand is XORed with the source operand and the
destination operand is replaced by the result.

9-35

■ Extended Divide
Purpose: Used to perform extended-precision division
Format: EDIV

divisor.rl, dividend.rq, quotient.wl, remainder.wl

Opcode

Operator

Function

EDIV

Extended Divide

Description: The dividend operand is divided by the divisor operand. The
quotient operand is replaced by the quotient and the remainder operand is
replaced by the remainder.
Unless the remainder operand is zero, the division is performed so that the
remainder operand has the same sign as the dividend operand. If the quotient
and remainder operands both reference the same location, the remainder oper¬
and overlays the quotient operand.

■ Extended Function Call
Purpose: Used to provide customer-defined extensions to the instruction set.
Format: XFC
Opcode

Operator

Function

XFC

Extended Function Call

Description: This instruction requests services of nonstandard microcode or
software. If no special microcode is loaded, then an exception is generated to a
kernel mode software simulator. Typically, the next byte would specify which
of several extended functions are requested. Parameters would be passed
either as normal operands or, more likely, in fixed registers.

■ Extended Modulus
Purpose: Used to perform accurate range reduction of math function argu¬
ments
Format: There are four formats—one for each type of floating point data
EMODD

mulr.rx, mulrx.rb, muld.rx, int.vAJ'racism

EMODF

mulr.rx, mulrx.rb, muld.rx, int.vA,fract.wx

EMODG

mulr.rx, mulrx.rw, muld.rx, int.vAJract.vix

EMODH

mulr.rx, mulrx.rw, muld.rx, int.vA,fract.vix

9-36 • The Instruction Set

Opcode

Operator

Function

EMODF

Extended Multiply and Integerize F_floating

EMODD

Extended Multiply and Integerize D_floating

MFD

EMODG

Extended Multiply and Integerize G_floating

74FD

EMODH

Extended Multiply and Integerize H_floating

Description: The multiplier extension operand is concatenated with the multi¬
plier operand to gain 8 (EMODD and EMODF), 11 (EMODG), or 15
(EMODH) additional low-order fraction bits. The low-order 5 or 1 bits of the
16-bit multiplier extension operand are ignored by the EMODG and EMODH
instructions, respectively. The multiplicand operand is multiplied by the
extended multiplier operand. This multiplication is such that the result is
equivalent to the exact product truncated (before normalization) to a fraction
field of 32 bits in F_floating, 64 bits in D_floating and G_floating, and
128 in H_floating. Regarding the result as the sum of an integer and frac¬
tion of the same sign, the integer operand is replaced by the integer part of the
result and the fraction operand is replaced by the rounded fractional part of
the result.

Extended Multiply
Purpose: Used to perform extended-precision multiplication
Format: EMUL

multiplier.rl, multiplicand.rl, addend.rl, product.wq

Opcode

Operator

Function

EMUL

Extended

Description: The multiplicand operand is multiplied by the multiplier oper¬
and giving a double-length result. The addend operand is sign-extended to
double length and added to the result. Then, the product operand is replaced
by the result.

Extract Field
Purpose: Used to move bit field to integer
Format: operator

pos.rl, size.rb, hase.wb, dst.wl

Opcode

Operator

Function

EXTV

Extract Field

EXTZV

Extract Zero-extended Field

Description: For EXTV, the destination operand is replaced by the signextended field specified by the position, size, and base operands. For EXTZV,
the destination operand is replaced by the zero-extended field specified by the
position, size, and base operands. If the size operand is zero, the only action is
to replace the destination operand with zero and affect the condition codes.
An example of this instruction is to extract the four protection bits (bits 27
through 30) from the memory management unit Page Table Entry. The base
address is the address of a longword operand containing these bits; the posi¬
tion operand could be the number of bits from the base address to the protec¬
tion code; and the size operand would be 4 because the protection code is 4
bits long. The destination operand would specify where the protection bits are
to be stored.
Because the protection code is not an arithmetic operand and does not need to
be sign-extended, the extract zero-extended field instruction should be speci¬
fied.

Find First Bit
Purpose: Used to locate the first bit in a bit field
Format: operator

startpos.rl, size.rb, base.vb, findpos.wl

Opcode

Operator

Function

FFC

Find First Clear

FFS

Find First Set

Description: A field specified by the start position, size, and base operands is
extracted. The field is tested for a bit in the state indicated by the instruction
starting at bit 0 and extending to the highest bit in the field. If a bit in the
indicated state is found, the find position operand is replaced by the position
of the bit and the Z condition code bit is cleared. If no bit in the indicated
state is found, the find position operand is replaced by the position (relative to
the base) of a bit one position to the left of the specified field and the Z condi¬
tion code bit is set. If the size operand is zero, the find position operand is
replaced by the start position operand and the Z condition code bit is set.

Halt
Purpose: Used to stop processor operation
Format: HALT
Opcode

Operator

Function

HALT

Halt

9-38 • The Instruction Set

Description: If the process is running in kernel mode, the processor is halted.
Otherwise, a privileged instruction fault occurs.
NOTE
This opcode is zero to trap many branches to data.

Increment
Purpose: Used to add 1 to an integer
Format: operator
Opcode

sum.mx

Operator

Function

INCB

Increment Byte

INCW

Increment Word

INCL

Increment Longword

Description: One is added to the sum operand and the sum operand is
replaced by the result.

Index
Purpose:Used for index calculation of arrays of fixed length data, bit fields,
and strings
Format:
INDEX

subscript.rl, low.rl, high.rl, size.rl, indexin.A, indexout.wl

Opcode

Operator

Function

INDEX

Compute Index

Description: The index in operand is added to the subscript operand and the
sum is multiplied by the size operand. The indexout operand is replaced by
the result. If the subscript operand is less than the low operand or greater than
the high operand, a subscript range trap is taken.

Insert Entry in Queue
Purpose: Used to add an entry to the head or tail of a queue
Format: INSQUE

entry.ab, predecessor.ab

Opcode

Operator

Function

INSQUE

Insert Entry in Queue

9-39

Description: The entry specified by the entry operand is inserted into the
queue following the entry specified by the predecessor operand. If the entry
inserted was the first one in the queue, the condition code Z-bit is set; other¬
wise, it is cleared. The insertion is a noninterruptible operation. Before per¬
forming any part of the operation, the processor validates that the entire
operation can be completed. This ensures that if a memory management excep¬
tion occurs, the queue is left in a consistent state.
NOTES
1. Because the insertion is noninterruptible, processes run¬
ning in kernel mode can share queues with interrupt service
routines.
2. The INSQUE instruction is implemented so the cooperat¬
ing software processes in a single processor may access a
shared list without additional synchronization if the inser¬
tions and removals are only at the head or tail of the queue.
3. During access validation, any access that cannot be com¬
pleted results in a memory management exception, even
though the queue insertion is not started.

■ Insert Entry into Queue at Head, Interlocked
Purpose: Used to perform an interlocked entry insert at head of queue
Format: INSQHI

entry.ab, header.aq

Opcode

Operator

Function

INSQHI

Insert Entry into Queue at Head, Interlocked

Description: The entry specified by the entry operand is inserted into the
queue following the header. If the entry inserted was the first one in the
queue, the condition code Z-bit is set; otherwise, it is cleared. The insertion is
a noninterruptible operation. The insertion is interlocked to prevent concur¬
rent interlocked insertions or removals at the head or tail of the same queue by
another process even in a processor environment. Before performing any part
of the operation, the processor validates that the entire operation can be com¬
pleted. This ensures that if a memory management exception occurs, the
queue is left in a consistent state. If the instruction fails to acquire the second¬
ary interlock, the instruction sets condition codes and terminates.

9-40 ■ The Instruction Set

NOTES
1. Because the insertion is noninterruptible, processes run¬
ning in kernel mode can share queues with interrupt service
routines.
2. The INSQHI instruction is implemented so the cooperat¬
ing software processes in a processor may access a shared list
without additional synchronization.
3. During access validation, any access that cannot be com¬
pleted results in a memory management exception even
though the queue insertion is not started.

■ Insert Entry into Queue at Tail, Interlocked
Purpose: Used to perform an interlocked entry insert at tail of queue
Format: INSQTI

entry.2b, header.aq

Opcode

Operator

Function

INSQTI

Insert Entry into Queue at Tail, Interlocked

Description: The entry specified by the entry operand is inserted into the
queue preceding the header. If the entry inserted was the first one in the
queue, the conditon code Z-bit is set; otherwise it is cleared. The insertion is a
noninterruptible operation. The insertion is interlocked to prevent concur¬
rent interlocked insertions or removals at the head or tail of the same queue by
another process even in a processor environment. Before performing any part
of the operation, the processor validates that the entire operation can be com¬
pleted. This ensures that if a memory management exception occurs, the
queue is left in a consistent state. If the instruction fails to acquire the second¬
ary interlock, the instruction sets condition codes and terminates.
NOTES
1. Because the insertion is noninterruptible, processes run¬
ning in kernel mode can share queues with interrupt service
routines.
2. The INSQTI instruction is implemented so the cooperat¬
ing software processes in a processor may access a shared list
without additional synchronization.
3. During access validation, any access that cannot be com¬
pleted results in a memory management exception even
though the queue insertion was not started.

9-41

■ Insert Field
Purpose: Used to move an integer to a bit field
Format: INSV

source.rl, position.rl, size.rb, ^se.vb

Opcode

Operator

Function

INSV

Insert Field

Description: The field specified by the position, size, and base operands is
replaced by bits < size - 1:0 > of the source operand. If the size operand is
zero, the only action is to affect the condition codes.

■ Jump
Purpose: Used to transfer control
Format: JMP

dst. ab

Opcode

Operator

Function

JMP

Jump

Description: The PC is replaced by the destination operand.

■ Jump to Subroutine
Purpose: Used to transfer control to subroutine
Format: JSB

dst. ab

Opcode

Operator

Function

JSB

Jump to Subroutine

9-42 ■ The Instruction Set

Description: The program counter (PC) is pushed on the stack as a longword.
The PC is replaced by the destination operand.
NOTE
Since the operand specifier conventions cause the evaluation
of the destination operand before saving PC, JSB can be used
for coroutine calls, with the stack used for linkage. The form
of such a call is: JSB @(SP) + .

Load Process Context
Purpose: Used to restore register and memory management context
Format: LDPCTX
Opcode

Operator

Function

LDPCTX

Load Process Context

Description: The process control block is specified by the process control
block base. The general registers are loaded from the PCB. The memory man¬
agement registers describing the process address space are also loaded and the
process entries in the translation buffer are cleared. Execution is switched to
the kernel stack. The PC and PSL are moved between the PCB and the stack
suitable for use by a subsequent REI instruction. This instruction can be exe¬
cuted only in kernel mode.
Some processors keep a copy of each of the process stack pointers in internal
registers. In those processors, LDPCTX loads the internal registers from the
PCB. Processors that do not keep a copy of all four process stack pointers in
internal registers keep only the current access mode register in an internal reg¬
ister. The contents of the internal register are switched with the PCB contents
whenever the current access mode field changes.

Locate Character
Purpose: Used to find a character in a character string
Format: LOCC

char.rb, /e«.rw, adr.ab

Opcode

Operator

Function

LOCC

Locate Character

9-43

Description: The character (char) operand is compared with the bytes of the
string specified by the length (len) and address (adr) operands. Comparison
continues until equality is detected, or until all bytes of the string have been
compared. If equality is detected, the condition code Z bit is cleared. Other¬
wise the Z bit is set.

■ Match Characters
Purpose: Used to find substring (object) in character string
Format: MATCHC

objlen.rvr, objadr.ab, srclen.rvj, srcadr.ab

Opcode

Operator

Function

MATCHC

Match Characters

Description: The source string is specified by the source length and source
address operands. The object string is specified by the object length and
object address operands. The source string is examined for a substring that
matches the object string. If the substring is found, the condition code Z bit is
set. Otherwise, it is cleared.

■ Move
Purpose: Used to move a specified scalar quantity
Format: operator
Opcode

source.rx, destination.wx

Operator

Function

MOVB

Move Byte

MOVW

Move Word

MOVL

Move Longword

MOVQ

Move Quadword

7DFD

MOVO

Move Octaword

MOVF

Move F_floating

MOVD

Move D_floating

50FD

MOVG

Move G_floating

70FD

MOVH

Move H_floating

Description: The destination operand is replaced by the source operand. The
source operand is unaffected.

9-44 • The Instruction Set

NOTE
The MOVB and MOVW instructions do not modify the highorder bytes of a register destination. Refer to the MOVZxL
and CVTxL instructions to update the full register contents.

Move Address
Purpose: Calculates address of quantity
Format: operator

source.ax, destination.wl

Opcode

Operator

Function

MOVAB

Move Address Byte

MOVAW

Move Address Word

MOVAL

Move Address Longword

MOVAF

Move Address F_floating

MOVAQ

Move Address Quadword

MOVAD

Move Address D_floating

MOVAG

Move Address G_floating

7EFD

MOVAH

Move Address H_floating

7EFD

MOVAO

Move Address Octaword

Description: The destination operand is replaced by the source operand,
which is an address. The context in which the source operand is evaluated is
given by the data type of the instruction. The operand whose address replaces
the destination operand is not referenced.

Move Characters
Purpose: Used to move a character string or block of memory
Formats: There are two formats—3 operand and 5 operand
MOVC

srclen. rw, sreadr. ab, dstadr. ab

MOVC

srclen.rvj, sreadr.ab, fill.rb, dstlen.rw, dstadr.ab

Opcode

Operator

Function

MOVC 3

Move Character—3 Operand

MOVC5

Move Character—5 Operand

9-45

Description: The destination string is replaced by the source string. If the des¬
tination string is longer than the source string, the highest address bytes of the
destination are replaced by the fill operand. However, if the destination string
is shorter than the source string, the highest addressed bytes of the source
string are not moved. The operation of the instruction is such that overlap of
the source and destination strings does not affect the result.

■ Move Complement
Purpose: Used to move the logical complement of an integer
Format: operator

source.rx destination.wx

Opcode

Operator

Function

MCOMB

Move Complemented Byte

MCOMW

Move Complemented Word

MCOML

Move Complemented Longword

Description: The destination operand is replaced by the one’s complement of
the source operand.

■ Move from Processor Register
Purpose: Used to provide access to the internal privileged (processor) registers
Format: MFPR

procreg.rl, dst.wl

Opcode

Operator

Function

MFPR

Move from Processor Register

Description: The specified register is stored. The procreg operand is a longword that contains the privileged register number. Execution may have regis¬
ter-specific side effects. A reserved operand fault may occur if the processor
internal register does not exist. A reserved instruction fault occurs if instruc¬
tion execution is attempted in other than kernel mode. (See also “Move to
Processor Register”.) See Table 9-2 for a list of the processor registers.

9-46 ■ The Instruction Set

Table 9-2 ■ Processor (Privileged) Registers
Number

Mnemonic*

Typet

Scopef

Kernel Stack Pointer

KSP

R/W

PROC

Executive Stack Pointer

ESP

R/W

PROC

Supervisor Stack Pointer

SSP

R/W

PROC

User Stack Pointer

USP

R/W

PROC

Interrupt Stack Pointer

ISP

R/W

CPU

P0 Base Register

POBR

R/W

PROC

P0 Length Register

POLR

R/W

PROC

PI Base Register

PlBR

R/W

PROC

Pi Length Register

P1LR

R/W

PROC

System Base Register

SBR

R/W

CPU

System Length Register

SLR

R/W

CPU

Process Control Block Base

PCBB

R/W

PROC

System Control Block Base

SCBB

R/W

CPU

Interrupt Priority Level

IPL

R/W

CPU

Asynchronous System Trap Level

ASTLVL

R/W

PROC

Software Interrupt Request

SIRR

CPU

Software Interrupt Summary

SISR

R/W

CPU

* Each register address is formed as PR$ followed by the register’s mnemonic. For
example, the register address for the user stack pointer is PR$USP. Once assigned, the
register number is not changed. Implementation-dependent registers are assigned dis¬
tinct addresses for each implementation. Thus, any privileged register present on more
than one implementation performs the same function whenever implemented. All
unsigned positive numbers are reserved to Digital. All negative numbers are reserved
to Digital’s Customer Software Services and customers.
t The Type column indicates the read/write characteristics of that register. The letter
R means the register is read-only. The characters R/W means the register is both read
and write. The character W means the register is write-only.

t The Scope column indicates if a register is a CPU register or a process register. Regis¬
ters labeled CPU are manipulated through software only using the MTPR and MFPR
instructions. Registers labeled PROC are manipulated by context switch instructions.

9-47

Table 9-2 ■ Processor (Privileged) Registers (Cont.)
Number

Mnemonic*

Interval Clock Control

ICCS

R/W

CPU

Next Interval Count

NICR

CPU

Interval Count

ICR

CPU

Time of Year (optional)

TODR

R/W

CPU

Console Receive Control/status

RXCS

R/W

CPU

Console Receiver Data Buffer

RXDB

CPU

Typet

ScopeJ

Console Transmit Control/status

TXCS

R/W

CPU

Console Transmit Date Buffer

TXDB

CPU

Memory Management Enable

MAPEN

R/W

CPU

Translation Buffer Invalidate All

TBIA

CPU

Translation Buffer Invalidate Single

TBIS

CPU

Performance Monitor Enable

PMR

R/W

PROC

System Identification

SID

CPU

■ Move from Processor Status Longword
Purpose: Used to obtain processor status
Format: MOVPSL

dst.wl

Opcode

Operator

Function

MOVPSL

Move from PSL

Description: The destination operand is replaced by the processor status longword.

■ Move Negated
Purpose: Used to move the arithmetic negation of a scalar quantity
Format: operator

source.rx, destination.wx

9-48 • The Instruction Set

Opcode

Operator

Function

MNEGB

Move Negated Byte

MNEGW

Move Negated Word

MNEGL

Move Negated Longword

MNEGF

Move Negated F_floating

MNEGD

Move Negated D_floating

52FD

MNEGG

Move Negated G_floating

72FD

MNEGH

Move Negated H_floating

Description: The destination operand is replaced by the negative of the source
operand.

Move Packed
Purpose: Used to move a packed decimal string from one memory location to
another memory location
Format: MOVP

len.rw, srcadr.ab, dstadr.ab

Opcode

Operator

Function

MOVP

Move Packed

Description: The destination string specified by the length and destination
address operands is replaced by the source string specified by the length and
source address operands.

Move to Processor Register
Purpose: Used to provide access to the internal privileged registers
Format: MTPR

src.rl, procreg.rl

Opcode

Operator

Function

MTPR

Move to Processor Register

Description: The specified register is loaded. The procreg operand is a longword that contains the privileged register number. Execution may have regis¬
ter-specific side effects. A reserved instruction fault occurs if instruction
execution is attempted in other than kernel mode. A reserved operand fault
may occur if the processor internal register does not exist. See “Move from
Processor Register”
(Table 9-2).

for a summary of accessible privileged registers

9-49

■ Move Translated Characters
Purpose: Used to move and translate character strings
Format:
MOVTC

srclen.Yvj, srcadr.2bJill.Yb, tbladr.ab, dstlen.rw, dstadr.ab

Opcode

Operator

MOVTC

Move Translated Characters

Function

Description: The source string is translated and replaces the destination
string. Translation is accomplished by using each byte of the source string as
an index into a 256-byte table whose first entry address is specified by the
table address operand. The byte selected replaces the byte of the destination
string. If the destination string is longer than the source string, the highest
addressed bytes of the destination string are replaced by the fill operand. If
the destination string is shorter than the source string, the highest addressed
bytes of the source string are not translated and moved. The operation of the
instruction is such that overlap of the source and destination strings does not
affect the result. If the destination string overlaps the translation table, the
destination string is unpredictable.

■ Move Translated until Character
Purpose: Used to move and translate a character string and to handle escape
codes
Format:
MOVTUC

srclen.Yvj, srcadr.ab, esc.rb, tbladr.ab, dstlen.rw, dstadr.ab

Opcode

Operator

Function

MOVTUC

Move Translated until Character

Description: The specified source string is translated and replaces the destina¬
tion string. Translation is accomplished by using each byte of the source string
as an index into a 256-byte table whose first entry address is specified by the
table address operand. The byte selected replaces the byte of the destination
string. Translation continues until a translated byte is equal to the escape byte
or until the source string or destination string is exhausted. If translation is
terminated because of escape, the condition code V bit is set. Otherwise, it is
cleared. If the destination string overlaps the table, the results are unpredict¬
able. If the source and destination strings overlap and their addresses are not
identical, then the results are unpredictable. If the source and destination
string addresses are identical, the translation is performed correctly.

9-50 • The Instruction Set

■ Move Zero-extended
Purpose: Used to convert an unsigned integer to a wider unsigned integer
Format: operator

source.rx, destination.wy

Opcode

Operator

Function

MOVZBW

Move Zero-Extended Byte to Word

MOVZBL

Move Zero-Extended Byte to Longword

MOVZWL

Move Zero-Extended Word to Longword

Description: For MOVZBW, bits 7:0 of the destination operand are replaced
by the source operand; bits 15:8 are replaced by zero. For MOVZBL, bits 7:0
of the destination operand are replaced by the source operand; bits 31:8 are
replaced by zero. For MOVZWL, bits 15:0 of the destination operand are
replaced by the source operand; bits 31:16 are replaced by zero.

■ Multiply
Purpose: Used to perform arithmetic multiplication
Format: There are two formats—2 operand and 3 operand.
operator

multiplier.rx y product, mx

operator

multiplier.rx , multiplicand.rx, product, wx

Opcode

Operator

Function

MULB2

Multiply Byte 2 Operand

MULB3

Multiply Byte 3 Operand

MULW2

Multiply Word 2 Operand

MULW3

Multiply Word 3 Operand

MULL2

Multiply Longword 2 Operand

MULL3

Multiply Longword 3 Operand

MULF2

Multiply F_floating 2 Operand

MULF3

Multiply F_floating 3 Operand

MULD2

Multiply D_floating 2 Operand

MULD3

Multiply D_floating 3 Operand

44FD

MULG2

Multiply G_floating 2 Operand

45FD

MULG3

Multiply G_floating 3 Operand

64FD

MULH2

Multiply H_floating 2 Operand

65FD

MULH3

Multiply H_floating 3 Operand

9-51

Description: In 2-operand format, the product operand is multiplied by the
multiplier operand and the product operand is replaced by the result.
In 3-operand format, the multiplicand operand is multiplied by the multiplier
operand and the product operand is replaced by the result. In floating format,
the product operand result is rounded for both 2- and 3-operand formats.

■ Multiply Packed
Purpose: Used to multiply one packed decimal string by a second, result placed
in a third
Format:

MULP

mulrlen.rw, mulradr.ab, muldlen.rw, muldadr.do, prodlen.rw,

prodadr.ab
Opcode

Operator

Function

MULP

Multiply Packed

Description: The multiplicand string is specified by the multiplicand length
and multiplicand address operands. The multiplier string is specified by the
multiplier length and multiplier address operands. The product string speci¬
fied by the product length and product address operands. The multiplicand
string is multiplied by the multiplier string. The product string is replaced by
the result.

■ Polynomial Evaluation
Purpose: Used for fast calculation of math functions
Format: operator

argument.rx, degree.rw, table address.ah

Opcode

Operator

Function

POLYF

Polynomial Evaluation F_floating

POLYD

Polynomial Evaluation D_ floating

55FD

POLYG

Polynomial Evaluation G_floating

75FD

POLYH

Polynomial Evaluation H_floating

Description: The table address operand points to a table of polynomial coeffi¬
cients. The coefficient of the highest order term of the polynomial is pointed
to by the table address operand. The table is specified with lower order coeffi¬
cients stored at increasing addresses. The data type of the coefficients is the
same as the data type of the argument operand.

9-52 ■ The Instruction Set

Evaluation is carried out by Horner’s method, and the contents of RO (Rl’RO
for POLYD and POLYG, R3’R2’Rl’RO for POLYH) are replaced by the result.
The result computed is
result = C [0] + X*(C[1] + X*(C[2] + ... X*C [d]))
where d = degree and X = arg. The unsigned word degree operand specifies
the highest numbered coefficient to participate in the evaluation. POLYH
requires four longwords on the stack to store arg in case the instruction is inter¬
rupted.

Pop Registers
Purpose: Used to restore multiple registers from stack
Format: POPR

mask.rw

Opcode

Operator

Function

POPR

Pop Registers

Description: The contents of registers whose number corresponds to set bits
in the mask operand are replaced by longwords popped from the stack. R[n] is
replaced if mask < n > is set. The mask is scanned from bit 0 to bit 14 and bit
15 is ignored.

Probe Accessibility
Purpose: Used to verify that arguments can be accessed
Format: operator

mode.rb, len.rv/, base.2b

Opcode

Operator

Function

PROBER

Probe Read Accessibility

PROBEW

Probe Write Accessibility

Description: The PROBE instruction checks the read or write accessibility of
the first and last byte specified by the base address and the zero-extended
length. The bytes in between are not checked. System software must check all
pages between the two end bytes if they are to be accessed.
The protection is checked against the larger of the modes specified in bits
< 1:0> of the mode operand and the previous mode field of the PSL. Note
that probing with a mode operand of zero is equivalent to probing the mode
specified in PSL < previous-mode >.

9-53

NOTES
1. On the probe of a process virtual address, if the valid bit of
the system page table entry is zero, then a translation not
valid fault occurs. This allows for the demand paging of the
process page tables.
2. On the probe of a process virtual address, if the protection
field of the system page table entry indicates no access, then a
status of not-accessible is given. One no access page table
entry in the system map is equivalent to 128 no access page
table entries in the process map.

■ Push Address
Purpose: Calculates address of quantity
Format: operator

source.ax

Opcode

Operator

Function

PUSHAB

Push Address Byte

PUSHAW

Push Address Word

PUSHAL

Push Address Longword

PUSHAF

Push Address F_floating

PUSHAQ

Push Address Quadword

PUSHAD

Push Address D_floating

PUSHAG

Push Address G_floating

7FFD

PUSHAH

Push Address H_floating

7FFD

PUSHAO

Push Address Octaword

Description: The source operand is pushed on the stack. The context in which
the source operand is evaluated is given by the data type of the instruction.
The operand whose address replaces the destination operand is not refer¬
enced.

9-54 ■ The Instruction Set

Push Longword
Purpose: Used to push a longword source operand onto the stack pointer
Format: PUSHL

src.rl

Opcode

Operator

Function

PUSHL

Push Longword

Description: The longword source (src) operand is pushed onto the stack.

Push Registers
Purpose: Used to save multiple registers on stack
Format: PUSHR

mask.rw

Opcode

Operator

Function

PUSHR

Push registers

Description:The contents of registers whose number corresponds to set bits in
the mask operand are pushed on the stack as longwords. R[n] is pushed if mask
< n > is set. The mask is scanned from bit 14 to bit 0, and bit 15 is ignored.

Remove Entry from Queue
Purpose: Used to remove an entry from the head or tail of a queue
Format: REMQUE

entry.ab, address.wl

Opcode

Operator

Function

REMQUE

Remove Entry from Queue

Description: The queue entry specified by the entry operand is removed from
the queue. The address operand is replaced by the address of the entry
removed. If there was no entry in the queue to be removed, the condition code
V bit is set; otherwise, it is cleared. If the queue is empty at the end of this
instruction, the condition code Z-bit is set; otherwise, it is cleared. The
removal is a noninterruptible operation. Before performing any part of the
operation, the processor validates that the entire operation can be completed.
This ensures that if a memory management exception occurs, the queue is left
in a consistent state.

9-55

NOTES
1. Because the removal is noninterruptible, processes run¬
ning in kernel mode can share queues with interrupt service
routines.
2. The REMQUE instruction is implemented so the cooperat¬
ing software processes in a single processor may access a
shared list without additional synchronization if insertions
and removals are only at the head or tail of the queue.
3. During access validation, any access that cannot be com¬
pleted results in a memory management exception, even
though the queue removal is not started.

■ Remove Entry from Queue at Head, Interlocked
Purpose: Used to perform an interlocked remove of an entry from the head of
queue
Format: REMQHI

header.aq, address.vA

Opcode

Operator

Function

REMQHI

Remove Entry from Queue at Head, Interlocked

Description: The queue entry following the header is removed from the
queue. The address operand is replaced by the address of the entry removed.
If no entry was removed from the queue (because either there is nothing to
remove or secondary interlock failed), the condition code V bit is set; other¬
wise, it is cleared. If the interlock succeeded and the queue is empty at the end
of this instruction, the condition code Z-bit is set; otherwise, it is cleared. The
removal is interlocked to prevent concurrent interlocked insertions or
removals at the head or tail of the same queue by another process even in a
processor environment. The removal is a noninterruptible operation. Before
performing any part of the operation, the processor validates that the entire
operation can be completed. This ensures that if a memory management excep¬
tion occurs, the queue is left in a consistent state. If the instruction fails to
acquire the secondary interlock, the instruction sets condition codes and termi¬
nates without altering the queue.
NOTES
1. Because the removal is noninterruptible, processes run¬
ning in kernel mode can share queues with interrupt service
routines.
2. The REMQHI instruction is implemented so the cooperat¬
ing software processes in a processor may access a shared list
without additional synchronization.

9-56 ■ The Instruction Set

3. During access validation, any access that cannot be com¬
pleted results in a memory management exception even
though the queue removal is not started.

■ Remove Entry from Queue at Tail, Interlocked
Purpose: Used to perform an interlocked entry remove from the tail of a
queue
Format: REMQTI

header.aq, address.wl

Opcode

Operator

Function

REMQTI

Remove Entry from Queue Tail, Interlocked

Description: The queue entry preceding the header is removed from the
queue. The address operand is replaced by the address of the entry removed.
If no entry was removed from the queue (because either there is nothing to
remove or secondary interlock failed), the condition code V bit is set; other¬
wise, it is cleared. If the interlock succeeded and the queue is empty at the end
of this instruction, the condition code Z-bit is set; otherwise, it is cleared. The
removal is interlocked to prevent concurrent interlocked insertions or
removals at the head or tail of the same queue by another process even in a
processor environment. The removal is a noninterruptible operation. Before
performing any part of the operation, the processor validates that the entire
operation can be completed. This ensures that if a memory management excep¬
tion occurs, the queue is left in a consistent state. If the instruction fails to
acquire the secondary interlock, the instruction sets condition codes and termi¬
nates without altering the queue.
NOTES
1. Because the removal is noninterruptible, processes run¬
ning in kernel mode can share queues with interrupt service
routines.
2. The REMQTI instruction is implemented so the cooperat¬
ing software processes in a processor may access a shared list
without additional synchronization.
3. During access validation, any access that cannot be com¬
pleted results in a memory management exception even
though the queue removal is not started.

■ Return from Exception or Interrupt
Purpose: Used to exit from an exception or interrupt service routine and initi¬
ate a controlled return.

9-57

Format: REI
Opcode

Operator

Function

REI

Return from Exception or Interrupt

Description: A longword is popped from the current stack and held in a tempo¬
rary PC. A second longword is popped from the current stack and held in a
temporary PSL. Validity of the popped PSL is checked. The current stack
pointer is saved and a new stack pointer is selected according to the new PSL
CURRENT— MODE and IS fields. The level of the highest-privilege AST is
checked against the current access mode to see whether a pending AST can be
delivered. Execution resumes with the instruction being executed at the time
of the exception or interrupt. Any instruction lookahead in the processor is
reinitialized.
The exception or interrupt service routine is responsible for restoring any reg¬
isters saved and removing any parameters from the stack.

■ Return from Procedure
Purpose: Used to transfer control from a procedure to the calling process
Format: RET
Opcode

Operator

Function

RET

Return from Procedure

Description: The stack pointer (SP) is replaced by the frame pointer (FP) plus
4. A longword containing stack alignment bits in bits 31:30, a CALLS/CALLG
flag in bit 29, the low 12 bits of the procedure entry mask in bits 27:16, and a
saved PSW in bits 15:0 is popped from the stack and saved in a temporary
register. The program counter (PC), frame pointer (FP), and argument pointer
(AP) are replaced by longwords popped from the stack. A register restore mask
is formed from bits 27:16 of the temporary register. Scanning from bit 0 to
bit 11 of the restore mask, the contents of registers whose number is indicated
by set bits in the mask are replaced by longwords popped from the stack. SP is
incremented by bits 31:30 of the temporary register. PSW is replaced by bits
15:0 of the temporary register. If bit 29 in the temporary register is 1 (indicat¬
ing that the procedure was called by CALLS), a longword containing the num¬
ber of arguments is popped from the stack. Four times the unsigned value of
the low byte of this longword is added to SP and SP is replaced by the result.
The VMS Procedure Calling Software Standard and condition handling facil¬
ity assume that procedures that return a function value or a status code do so
in R0 or R0 and Rl.

9-58 • The Instruction Set

■ Return from Subroutine
Purpose: Used to return control from subroutine
Format: RSB
Opcode

Operator

Function

RSB

Return from Subroutine

Description: The program counter (PC) is replaced by a longword removed
from the stack.
NOTE
RSB is used to return from subroutines called by the BSBB,
BSBW, and JSB instructions.

■ Rotate Longword
Purpose: Used to rotate integer
Format: ROTL

count.rb, source, rl, destination. wl

Opcode

Operator

Function

ROTL

Rotate Longword

Description: The source operand is rotated logically by the number of bits
specified by the count operand and the destination operand is replaced by the
result. The source operand is unaffected. A positive count operand rotates to
the left. A negative count operand rotates to the right. A 0 count operand
replaces the destination operand with the source operand.

■ Save Process Context
Purpose: Used to save register context
Format: SVPCTX
Opcode

Operator

Function

SVPCTX

Save Process Context

Description: The process control block (PCB) is specified by the privileged reg¬
ister process control block base (PCBB). The general registers are saved into
the PCB. The PC and PSL currently on the top of the current stack are popped
and stored in the PCB. If a SVPCTX instruction is executed when the IS is
clear, then the IS is set, the interrupt stack pointer is activated, and the IPL is
maximized with 1 because of the switch to the interrupt stack. This instruc¬
tion can be executed only in kernel mode.

9-59

NOTES
1. The map, ASTLVL, and PME contents of the PCB are not
saved because they are rarely changed. Thus, not writing
them saves overhead.
2. Some processors keep a copy of each of the process stack
pointers in internal registers. In those processors, SVPCTX
stores the internal registers in the PCB. Processors that do
not keep a copy of all four process stack pointers in internal
registers keep only current access mode register in an internal
register and switch this with the PCB contents whenever the
current access mode field changes.
3. Between the SVPCTX instruction that saves state for one
process and the LDPCTX that loads the state of another, the
internal stack pointers may not be referenced by MFPR or
MTPR instructions. This implies that interrupt service rou¬
tines invoked at a priority higher than the lowest one used for
context switching must not reference the process stack
pointers.

■ Scan Characters
Purpose: Used to find (scan) a set of characters in character string
Format: SCANC

/e/z.rw, adr.ab, tableadr.ab, mask.rb

Opcode

Operator

Function

SCANC

Scan Characters

Description: The bytes of the string specified by the length and address oper¬
ands are successively used to index into a 256-byte table whose entry address
is specified by the table address operand. The byte selected from the table is
ANDed with the mask operand. The operation continues until the result of
the AND is nonzero or until all the bytes of the string have been exhausted. If
a nonzero AND result is detected, the condition code Z bit is cleared. Other¬
wise, the Z bit is set.

■ Skip Character
Purpose: Used to skip a character in a character string
Format: SKPC

char.rb, len.rw, adr.ab

Opcode

Operator

Function

SKPC

Skip Character

9-60 • The Instruction Set

Description: The character (char) operand is compared with the bytes of the
string specified by the length (len) and address (adr) operands. Comparison
continues until inequality is detected, or until all bytes of the string have been
compared. If inequality is detected, the condition code Z bit is cleared. Other¬
wise the Z bit is set.

■ Span Characters
Purpose: Used to skip (span) a set of characters in character string
Format: SPANC

len.rw, adr.ab, tableadr.ab, mask.rb

Opcode

Operator

Function

SPANC

Span Characters

Description: The bytes of the string specified by the length and address oper¬
ands are successively used to index into a 256-byte table whose entry address
is specified by the table address operand. The byte selected from the table is
ANDed with the mask operand. The operation continues until the result of
the AND is zero or until all the bytes of the string have been exhausted. If a
zero result is detected, the condition code Z bit is cleared. Otherwise, the Z
bit is set.

■ Subtract
Purpose: Used to perform arithmetic subtraction
Format: There are two formats—2 operand and 3 operand
operator

subtrahend.rx, difference.mx

operator

subtrahend.rx, minuend.rx,dif Jerence.wx

9-61

Opcode

Operator

Function

SUBB2

Subtract Byte 2 Operand

SUBB3

Subtract Byte 3 Operand

SUBW2

Subtract Word 2 Operand

SUBW3

Subtract Word 3 Operand

SUBL2

Subtract Longword 2 Operand

SUBL3

Subtract Longword 3 Operand

SUBF2

Subtract F_floating 2 Operand

SUBF3

Subtract F_floating 3 Operand

SUBD2,

Subtract D_floating 2 Operand

SUBD3

Subtract D_floating 3 Operand

42FD

SUBG2

Subtract G_floating 2 Operand

43FD

SUBG3

Subtract G_floating 3 Operand

62 FD

SUBH2

Subtract H_floating 2 Operand

63FD

SUBH3

Subtract H_floating 3 Operand

Description: In 2-operand format, the subtrahend operand is subtracted from
the difference operand and the difference operand is replaced by the result.
In 3-operand format, the subtrahend operand is subtracted from the minuend
operand and the difference operand is replaced by the result. In floating for¬
mat, the result is rounded.

■ Subtract One and Branch
Purpose: Used to decrement an integer loop count and loop
Format: operator

index.ml, displ.bb

Opcode

Operator

Function

SOBGEQ

Subtract One and Branch Greater Than or
Equal to Zero

SOBGTR

Subtract One and Branch Greater Than Zero

Description: One is subtracted from the index operand and the index operand
is replaced by the result. On SOBGEQ, if the index operand is greater than or
equal to 0, the branch is taken. On SOBGTR, if the index operand is greater
than 0, the branch is taken. If the branch is taken, the sign-extended branch
displacement is added to the program counter (PC) and the PC is replaced by
the result.

9-62 ■ The Instruction Set

■ Subtract Packed
Purpose: Used to subtract one packed decimal string from another
Format: There are two formats—a 4-operand and a 6-operand format.
SUBP4

sublen.rw, subadr.ab, diflen.rvj, difadr.ab

SUBP6

sublen.rv/, subadr.sb, minlen.rw, minadr.ab, diflen.rvj, difadr.ab

Opcode

Operator

Function

SUBP4

Subtract Packed 4 Operand

SUBP6

Subtract Packed 6 Operand

Description: In 4-operand format, the subtrahend string is specified by subtrahend length and subtrahend address operands. The difference string is
specified by the difference length and difference address operands. The sub¬
trahend string is subtracted from the difference string and the difference
string is replaced by the result.
In 6-operand format, the subtrahend string is specified by the subtrahend
length and subtrahend address operands. The minuend string is specified by
the minuend length and minuend address operands. The difference string is
specified by the difference length and difference address operands. The sub¬
trahend string is subtracted from the minuend string. The difference string is
replaced by the result.

■ Subtract with Carry
Purpose: Used to perform extended-precision subtraction
Format: SBWC

subtrahend, rl, difference .ml

Opcode

Operator

Function

SWBC

Subtract with Carry

Description: The subtrahend operand and the contents of the condition code
C bit are subtracted from the difference operand and the difference operand
is replaced by the result.

9-63

■ Test
Purpose: Used to perform an arithmetic compare of a scalar to 0
Format: operator
Opcode

src.rx

Operator

Function

TSTB

Test Byte

TSTW

Test Word

TSTL

Test Longword

TSTF

Test F_floating

TSTD

Test D_floating

53FD

TSTG

Test G_floating

73FD

TSTH

Test FI_floating

Description: The condition codes are affected according to the value of the
source (src) operand.
NOTE
On a floating reserved operand, the condition codes are unpre¬
dictable.

Chapter 10 ■ Architectural Subsetting

Architectural subsetting deals with those parts of the VAX architecture that
may be included as standard features of a processor, provided as options to the
processor, or omitted completely from the processor.
A processor implementing a subset of the VAX instructions, data types, or reg¬
isters, as described in this chapter, is known as a subset VAX processor. Of
the many subsets possible, the following four subsets are the most common.
■ Full VAX—includes all VAX data types, instructions, and registers.
■ Kernel subset—the minimum allowed subset.
■ Micro VAX I subset—as implemented by the Micro VAX I systems.
■ Micro VAX II subset—as implemented by the MicroVAX II chip.

■ Subsetting Rules
The features of the architecture that may be omitted are divided into several
groups, each with different rules for subsetting. Floating and string instruc¬
tions with their associated data types, compatibility mode instruction set, and
processor registers may be omitted in a subset implementation.
Floating-point Instructions
The first group consists of the D_floating, F_floating, G_floating, and
H— floating data types, and the associated instructions. Each of these data
types may be subset only as an entity. This means that if one of these data
types is included, all the instructions that operate on that data type must be
included. If an instruction in this group is omitted by a processor, execution
of the instruction results in a reserved instruction fault.
■ D_floating

instructions

(24)—ACBD,

ADDD2,

ADDD3,

CMPD,

CVTBD, CVTDB, CVTDF, CVTDL, CVTDW, CVTFD, CVTLD, CVTRDL,
CVTWD, DIVD2, DIVD3, EMODD, MNEGD, MOVD, MULD2, MULD3,
POLYD, SUBD2, SUBD3, and TSTD.
■ F_floating instructions (22)—ACBF, ADDF2, ADDF3, CMPF, CVTBF,
CVTFB, CVTFL, CVTFW, CVTLF, CVTRFL, CVTWF, DIVF2, DIVF3,
EMODF, MNEGF, MOVF, MULF2, MULF3, POLYF, SUBF2, SUBF3, and
TSTF.

10-2 ■ Architectural Subsetting

■ G_floating

instructions

(24)—ACBG,

ADDG2,

ADDG3,

CMPG,

CVTBG, CVTFG, CVTGB, CVTGF, CVTGL, CVTGW, CVTLG, CVTRGL,
CVTWG, DIVG2, DIVG3, EMODG, MNEGG, MOVG, MULG2, MULG3,
POLYG, SUBG2, SUBG3, and TSTG.
■ H_floating

instructions

(32)—ACBH,

ADDH2,

ADDH3,

CLRH

(CLRO), CMPH, CVTBH, CVTDH, CVTFH, CVTGH, CVTHB, CVTHD,
CVTHF, CVTHG, CVTHL, CVTHW, CVTLH, CVTRHL, CVTWH,
DIVH2, DIVH3, EMODH, MNEGH, MOVAH (MOVAO), MOVH, MOVO,
MULH2, MULH3, PUSHAH (PUSHAO), POLYH, SUBH2, SUBH3, and
TSTH.

String Instructions
The second group consists of the string instructions and their associated data
types, including the decimal string, EDITPC, CRC, and character string
instructions, but not including MOVC3 or MOVC5 instructions. The MOVC3
and MOVC3 instructions are part of the kernel instruction set and may not be
omitted. Instructions in this group may be subset individually.
■ Character string instructions (10)—CMPC3, CMPC5, CRC, LOCC,
MATCHC, MOVTC, MOVTUC, SCANC, SKPC, and SPANC.
■ Decimal string instructions (17)—ADDP4, ADDP6, ASHP, CMPP3,
CMPP4, CVTLP, CVTPL, CVTPT, CVTTP, CVTPS, CVTSP, DIVP,
EDITPC, MOVP, MULP, SUBP4, and SUBP6.

If an instruction in this group is omitted, an attempt to execute the instruc¬
tion results in a subset-emulation exception.
Compatibility Mode Instruction Set
The third group consists of the compatibility mode instruction set. If compati¬
bility mode is omitted by a processor, the execution of an REI instruction
attempting to enter compatibility mode results in a reserved operand fault.
Processor Registers
The fourth group consists of processor registers. The registers described
below may be omitted from subset processors. If any of the registers named in
one of the following subgroups is included, all the registers in that subgroup
must be included.
■ Interval timer registers NICR, ICR, ICCS except for

<IE>. The

ICCS < IE > register is part of the kernel subset and may not be omitted.

10-3

■ Time-of-Year clock register TODR.
■ Console registers RXCS, RXDB, TXCS, and TXDB.
■ Performance Monitor Enable register PME.

■ The Kernel Instruction Set
The kernel instruction set is defined by exception; it is those instructions that
may not be omitted. For convenience, the kernel set is listed here. There are
304 native mode instructions in the full VAX instruction set. Of these, 129
may be omitted, leaving 175 instructions in the kernel instruction set. Byte,
word, longword, and quadword operand sizes have been included in the kernel
instruction set. The octaword operand size has not been included. The follow¬
ing instructions are the kernel instruction set.
■ Address

instructions

(8)—MOVAB,

MOVAL,

MOVAQ,

MOVAW,

PUSHAB, PUSHAL, PUSHAQ, and PUSHAW.
■ Branch and control instructions (39)—ACBB, ACBL, ACBW, AOBLEQ,
AOBLSS, BBC, BBCC, BBCCI, BBCS, BBS, BBSC, BBSS, BBSSI, BEQL,
BGEQ, BGEQU, BGTR, BGTRU, BLBC, BLBS, BNEQ, BRB, BRW, BSBB,
BSBW, BVC, BVS, CASEB, CASEL, CASEW, JMP, JSB, RSB, SOBGEQ,
and SOBGTR.
■ Character string instructions (2)—MOVC3 and MOVC5.
■ Instructions for use by operating systems (12)—CHME, CHMK, CHMS,
CHMU, HALT, LDPCTX, MFPR, MTPR, PROBER, PROBEW, REI, and
SVPCTX.
■ Integer arithmetic and logical instructions (89)—ADAWI, ADDB2,
ADDB3, ADDL2, ADDL3, ADDW2, ADDW3, ADWC, ASHL, ASHQ,
BICB2, BICB3, BICL2, BICL3, BICW2, BICW3, BISB2, BISB3, BISL2,
BISL3, BISW2, BISW3, BITB, BITL, BITW, CLRB, CLRL, CLRQ, CLRW,
CMPB, CMPL, CMPW, CVTBL, CVTBW, CVTLB, CVTLW, CVTWB,
CVTWL, DECB, DECL, DECW, DIVB2, DIVB3, DIVL2, DIVL3, DIVW2,
DIVW3,

EDIV,

EMUL,

INCB,

INCL,

INCW,

MCOMB,

MCOML,

MCOMW, MNEGB, MNEGL, MNEGW, MOVB, MOVL, MOVQ, MOVW,
MOVZBL, MOVZBW, MOVZWL, MULB2, MULB3, MULL2, MULL3,
MULW2, MULW3, PUSHL, ROTL, SBWC, SUBB2, SUBB3, SUBL2,
SUBL3, SUBW2, SUBW3, TSTB, TSTL, TSTW, XORB2, XORB3, XORL2,
XORL3, XORW2, and XORW3.

10-4 ■ Architectural Subsetting

- Miscellaneous

instructions

(9)—BICPSW,

BISPSW,

BPT,

INDEX,

MOVPSL, NOP, POPR, PUSHR, and XFC.
■ Procedure call instructions (3)—CALLG, CALLS, and RET.
■

Queue

instructions

(6)—INSQHI,

INSQTI,

INSQUE,

REMQHI,

REMQTI, and REMQUE.
■ Variable length bit field instructions (7)—CMPV, CMPZV, EXTV,
EXTZV, FFC, FFS, and INSV.

Instruction Emulation
Subset VAX processors and their operating systems cooperate to support emu¬
lation of those instructions that are omitted from the processor’s instruction
set. Programs running under the operating system can make use of these
instructions as though they were supported directly by the processor. The pro¬
cess of emulating an omitted instruction depends on the instruction type.
Emulation of string instructions is assisted by the processor, through the
instruction emulation exception. Emulation of compatibility mode instruc¬
tions and floating point instructions is done entirely by software.

Micro VAX I Systems
The Micro VAX I is the first subset VAX system. There are two versions of the
subset—one that includes F_floating and G_floating instructions, and
one that includes F_floating and D_floating instructions. Neither version
includes H_floating instructions. The MicroVAX I processor includes some
of the optional string instructions (CMPC3, LOCC, SCANC, SKPC, and
SPANC), but does not include compatibility mode.

MicroVAX II Systems
MicroVAX II is the first subset VAX system with the processor on a single
chip. It includes the F_floating, D_floating, and G_floating instruc¬
tions in an optional floating-point unit (a separate chip), but does not include
the H_floating instructions. MicroVAX II includes none of the optional
string instructions. It does not include optional processor registers or compati¬
bility mode.

Chapter 11 ■ PDP-11 Compatibility Mode

During the design of the VAX computer architecture, Digital’s engineers were
acutely aware of the need to establish a high degree of compatibility with the
large, well-established PDP-11 computer family. VAX systems represent the
natural growth direction for many installations using PDP-11 machines and
programs. It was important that VAX machines display selected compatibility
features for good reasons—to ease the growth, to quicken program transition,
and to protect customer investment. Also, VAX machines had to provide com¬
patibility for people who would take advantage of its excellent program devel¬
opment tools. These tools are used to create and test programs that are to be
run on PDP-11 systems. PDP-11 compatibility mode is now an option. VAX
processors that implement compatibility mode do so as described in this chap¬
ter. Operating system software may emulate compatibility mode on proces¬
sors that omit it. For details of the PDP-11 instruction set, see the PDP-11
Architecture Handbook.
NOTE
In this chapter, references to compatibility mode mean the
PDP-11 compatibility mode of operation. References to
native mode mean the VAX native mode of operation.
The PDP-11 compatibility mode makes a VAX computer look like a PDP-11
computer running PDP-11 instructions. Naturally, there are some restrictions
and requirements. A VAX computer treats compatibility mode programs like
other processes, and can run them in its multiprogramming environment
along with native mode programs. The VAX computer should not be thought
of as existing in one state or another, but rather as capable of handling both
modes as needed.
If you are considering a VAX system for growth and for host program develop¬
ment, you will find that it provides useful compatibility with PDP-11 systems
already in use or others that might be added. As a powerful link joining PDP11 computers and VAX computers, compatibility mode can help you expand
your computing resources efficiently. And programs that cannot take advan¬
tage of compatibility mode, for one reason or another, usually can be fixed
easily and quickly.
What follows in this chapter is a fairly detailed review of the powers and the
restrictions of the compatibility mode. Should you need a greater depth of
information, your Digital Sales Representative or Software Specialist can sup¬
ply it for you.

11-2 • PDP-11 Compatibility Mode

■ PDP-11 User Environment Emulation
Compatibility mode hardware, in conjunction with a compatibility mode soft¬
ware executive (which runs in native mode), can emulate the environment pro¬
vided to user programs on a PDP-11 system. But this environment excludes
from a complete PDP-11 the normal operation of the following features:
1. Privileged instructions such as HALT and RESET.
2. Special instructions such as traps and WAIT.
3. Access to internal processor registers (for example, processor status word
and console switch register).
4. Direct access to trap and interrupt vectors.
5. Direct access to I/O devices. (PDP-11 compatibility mode programs can
directly reference I/O devices if and only if proper mapping has been estab¬
lished by native mode software.)
6. Interrupt servicing.
7. Stack overflow protection.
8. Alternate general register sets.
9. The PDP-11 processor kernel and supervisor modes are not supported.
The user mode is the only mode supported in PDP-11 compatibility mode.
10. Floating-point instructions.
Compatibility mode architecture is divided into two parts. The first part is
the PDP-11 environment provided by the VAX hardware. Details of the opera¬
tion of PDP-11 compatible operations can be found in the PDP-11 Architec¬
ture Handbook. The second part is the hardware provided in the VAX
architecture that enable the implementation of various compatibility mode
executives. This part is considered a subset of the VAX System Architecture.

General Registers
All the PDP-11 general registers and addressing modes are in the compatibil¬
ity mode. Side effects caused by a destination address calculation have no
effect on source values (except in JSR instructions), and autoincrement modes
in JMP and JSR do not affect the new program counter. However, side effects
caused by a source address calculation affect the value of a register used for
destination address calculation. All PDP-11 addresses are 16 bits long. In com¬
patibility mode, a 16-bit PDP-11 address is zero-extended to 32 bits.
The operands of some PDP-11 instructions are implied by the instruction type
while others are specified as part of the instruction. Address mode operand
specifiers include a 3-bit mode field specifying one of eight modes—
autodecrement,

autodecrement

deferred,

autoincrement,

autoincrement

deferred, index, index deferred, register, and register deferred.

11-3

Compatibility mode registers 0 through 6 are bits 13 through 0 of VAX gen¬
eral registers 0 through 6, respectively. Compatibility mode register 7 (pro¬
gram counter) is bit 13 through 0 of VAX general register 13. VAX registers 8
through 14 (stack pointer) are not affected by compatibility mode. When
entering compatibility mode, VAX register 7 and the upper halves of registers
0 through 6 and 13 are ignored. When an exception or interrupt occurs from
compatibility mode, VAX register 7 is unpredictable and the upper halves of
RO through R6 and the stacked R15 (PC) are zero. There are no floating accu¬
mulators (registers). That is why there are no FP11 floating point instructions
in compatibility mode.
Stack Pointer Register
As in the PDP-11 processors, general register R6 is used as the stack pointer
by certain instructions. However, it is not used by the hardware for any excep¬
tions or interrupts, nor is there any stack overflow protection in compatibility
mode.
Processor Status Word
A subset of the PDP-11 processor status word is available in compatibility
mode. The format of the compatibility mode processor status word (PSW) is
shown in Figure 11-1. Compatibility mode processor status word bits 0
through 4 have the same meaning as do the VAX processor status longword
bits 0 through 4. They are the trace bit and the condition code bits.

Figure 11-1 ■ Compatibility Mode Processor Status Word
The processor status word can be affected only by the RTI and RTT condition
code instructions. When an RTI or RTT instruction is executed, bits 13
through 3 in the saved processor status word (PSW) on the stack are ignored.

11-4 • PDP-11 Compatibility Mode

Compatibility Mode Instructions
The compatibility mode instructions are listed in Table 11-1. Table 11-2 lists
the trap instructions that cause the VAX processor to enter native mode. In
native mode, either the complete trap may be serviced or the instruction may
be simulated. Some instructions (such as WAIT and RESET) are considered
reserved instructions in compatibility mode. When these instructions are
encountered, they cause a fault to native mode. Table 11-3 lists the reserved
instructions. In addition, all other opcodes not defined in Tables 11-1 and
11-2 result in a fault to native mode. No floating-point instructions are
included in compatibility mode.

Table 11-1 ■ PDP-11 Compatibility Mode Instructions
Opcode (octal)

Mnemonic

Name

000002

RTI

Return from Interrupt

000006

RTT

Return from Trap

0001DD

JMP

Jump

00020R

RTS

Return from Subroutine

000240-000277

Condition Codes

0003DD

SWAB

Swap Bytes

000400-003777

Branches

Branch

100000-103777

Branches

Branch

004RDD

JSR

Jump to Subroutine

X050DD

CLR(B)

Clear

X051DD

COM(B)

Complement

X052DD

INC(B)

Increment

X053DD

DEC(B)

Decrement

X054DD

NEG(B)

Negate

X055DD

ADC(B)

Add Carry

X056DD

SBC(B)

Subtract Carry

X057DD

TST(B)

Test

X060DD

ROR(B)

Rotate Right

X061DD

ROL(B)

Rotate Left

X062DD

ASR(B)

Arithmetic Shift Right

X063DD

ASL(B)

Arithmetic Shift Left

0065SS

MFPI*

Move from Previous Instruction
Space

11-5

Table 11-1 ■ PDP-11 Compatibility Mode Instructions (Cont.)
Opcode (octal)

Mnemonic

Name

0066DD

MTPI*

Move to Previous Instruction Space

1065SS

MFPD*

Move from Previous Data Space

1066DD

MTPD*

Move to Previous Data Space

0067DD

SXT

Sign Extend Word

070RSS

MUL

Multiply

071RSS

DIV

Divide

072RSS

ASH

Arithmetic Shift

073RSS

ASHC

Arithmetic Shift Combined

074RSS

XOR

Exclusive OR

077RNN

SOB

Subtract One and Branch

X1SSDD

MOV(B)

Move

X2SSSS

CMP(B)

Compare

X3SSSS

BIT(B)

Bit Test

X4SSDD

BIC(B)

Bit Clear

X5SSDD

BIS(B)

Bit Set

06SSDD

ADD

Add

16SSDD

SUB

Subtract

Legend
DD

Destination operand specifier

Source operand specifier

Operation specifier—0 for word, 1 for byte
These instructions execute exactly as they would on a PDP-11 in user
mode with Instruction and Data space overmapped. More specifically,
they ignore the previous access level and act as if they were PUSH and
POP instructions referencing the current stack.

11-6 ■ PDP-11 Compatibility Mode

Table 11-2 ■ PDP-11 Compatibility Mode Trap Instructions
Opcode (octal)

Mnemonic

000003

BPT

000004

IOT

104000-104377

EMT

104400-104777

TRAP

Table 11-3 ■ PDP-11 Compatibility Mode Reserved Instructions
Opcode (octal)

Mnemonic

000000

HALT

000001

WAIT

000003

RESET

000007

MFPT

00023N

SPL

0064NN

MARK

0070DD

CSM

07500R

FADD - FIS

07501R

FSUB - FIS

07502R

FMUL-FIS

07503R

FDIV - FIS

076XXX

Extended Instructions

1064SS

MTPS

1067DD

MFPS

17XXXX

FP11 Floating Point

■ Entering and Leaving PDP-11 Compatibility Mode
Compatibility mode is entered when an REI instruction is executed with the
compatibility mode bit of the processor status longword (PSL) on the stack is
set. Other bits in the PSL either have the same effect as in native mode or are
required to have specific values in compatibility mode. The effects of other
bits in the PSL are listed in Table 11-4.

11-7

Table 11-4 ■ Effects of Processor Status Longword Bits
Bit

Effect

Condition Code

CUR MOD

Reserved operand fault if not 3

Reserved operand fault if not zero

FPD

Reserved operand fault if not zero

IPL

Reserved operand fault if not zero

Condition Code

PRV MOD

Reserved operand fault if not 3

Trace bit

Trace pending bit

Condition Code

Native mode is reentered from compatibility mode on an exception or an inter¬
rupt. The processor status longword (PSL) pushed on the stack has all the bits
that cause reserved operand faults set to the appropriate state.
Note that when an RTI or RTT instruction is executed in compatibility mode,
the 11 high bits of the processor status word (PSW) are ignored. But when the
PSW is restored as part of the PSL when going from native to compatibility
mode, those bits must be zero or a reserved operand fault will occur.

■ Memory Management
The PDP-11 uses 16-bit byte addresses. For this reason, compatibility mode
programs are confined to execute in the first 64 Kbytes of the process part of
virtual address space. There is a one-to-one correspondence between a compati¬
bility mode virtual address and its VAX counterpart. For example, virtual
address 0 references the same location in both modes. A compatibility mode
address is interpreted as shown in Figure 11-2.

11-8 • PDP-11 Compatibility Mode

3
i
0

9 8

5
PAGE

o
0
DISPLACEMENT

Figure 11-2 ■ Compatibility Mode Address Interpretation
The PDP-11 computers can provide different access protection to different
segments of memory. PDP-11 segments are in 8-block increments. VAX seg¬
ments are 512-byte pages. This is done because protection is specified by
pages in the VAX architecture. (One VAX page equals eight PDP-11 blocks.)
The memory management system protects and relocates compatibility mode
addresses in the normal manner. Thus, all of the memory management mecha¬
nisms available in native mode are available to the compatibility mode execu¬
tive for managing both the virtual and physical memory of compatibility
mode programs. All the exception conditions that can be caused by memory
management in native mode can also occur when relocating a compatibility
mode address.
Most of the features of the PDP-11 memory management hardware affecting
the user environment can be simulated with the VAX memory management
system. Table 11-5 provides a general description of how this can be done.
Table 11-6 demonstrates how a PDP-11 environment can be created using the
concepts in Table 11-5. There are 8 segments. Segments 0,1, and 2 are pro¬
gram segments; 3 is unused; 4 and 5 are stack; 6 and 7 are read/write data.

11-9

Table 11-5 ■ PDP-11 Memory Management Simulation
PDP-11 Memory Management
Feature

VAX Simulation Method

Eight segments per user

Eight segments can be simulated by
dividing the 128 pages of the compati¬
bility mode virtual address space into
eight logical groups of 16 pages each
having possibly different protection.

Segment size from 64 bytes to 8
Kbytes (1 to 128 blocks) in 64-byl:e
increments, using contiguous
memory

Segment size from 512 bytes to 8
Kbytes (1 to 16 pages) in 512-byte (1
page) increments, using discontiguous
memory.

Forward growing segments
(Expand Direction 0)

Can be simulated using page table
entries specifying no access for those
pages that are not allocated.

Backward growing segments
(Expand Direction 1)

Can be simulated using page table
entries specifying no access for those
pages that are not allocated.

Segments begin on any 64-byte
boundary

Segments begin on any 512-byte
boundary.

Table 11-6 ■ Creating a PDP-11 Environment
PDP-11 Environment

VAX Page Table

Segment
Number

Size
(bytes)

Expand
Direction

Access
Type

Page

Access
Type

Read only

0-15

Read only

Readonly

16-31

Readonly

256

Read only

None

33-77

No Access

Down

Read/Write

78-79

Read/Write

Down

Read/Write

80-95

Read/Write

96-111

Read/Write

112-115 Read/write
116-127 No access

11-10 ■ PDP-11 Compatibility Mode

Exceptions and Interrupts
All interrupts and exception conditions that occur while the machine is in com¬
patibility mode cause the machine to enter native mode. Note that this
includes backing up instruction side effects if necessary. The following excep¬
tion conditions are specific to compatibility mode. All these exceptions create
a three-longword frame on the kernel stack containing a processor status longword (PSL), program counter (PC), and one longword of trap-specific informa¬
tion. Bits 15 through 0 of this longword contain a code indicating the specific
type of trap and bits 31 through 16 are zero. No compatibility mode excep¬
tion conditions result in traps.

Tracing in Compatibility Mode
A compatibility mode trace fault occurs at the beginning of an instruction
when the trace bit is set in the processor status word at the beginning of the
prior instruction. On trace faults, a 2-longword kernel stack frame is created.
The frame contains the processor status longword and the program counter.
The interrupt priority level (IPL) and interrupt stack (IS) bits are 0, and the
compatibility mode (CM) bit is 1 in the stacked processor status longword.
Compatibility mode trace faults use the same vector as native mode trace
fault. In fact, the rules for trace fault generation in compatibility mode are
identical to those for native mode. However, an odd address abort for an
instruction fetch may precede the trace fault for that instruction. There are
two ways to set the trace bit at the beginning of a compatibility mode instruc¬
tion.
1. An RTT/RTI instruction is executed in compatibility mode and the trace
bit in the processor status word image on the stack is set. In this case, the
next instruction is executed and a trace fault is taken after that instruc¬
tion. (The next instruction is the one pointed to by the program counter on
the stack.)
2. An REI instruction is executed in native mode under the following condi¬
tions. The instruction has both the trace bit and the compatibility mode
bit set and the trace pending bit clear in the saved processor status long¬
word image on the stack. Again, one instruction is executed, and the trace
trap is taken. (The operations that occur as a function of these conditions
are the same whether or not compatibility mode is being entered from the
REI instruction.)

11-11

■ Unimplemented PDP-11 Traps
Some traps that occur in PDP-11 systems are not implemented in VAX sys¬
tems PDP-11 compatibility mode.
1. There is no stack overflow trap. Stack overflow can be provided by the
compatibility mode executive using the memory management mecha¬
nisms.
2. There is no concept of a double error trap in compatibility mode. This is
because the first error always returns the machine to native mode.
3. All other trap conditions such as power failure, memory parity, and mem¬
ory management traps cause the machine to enter native mode.

■ Input/output References
Instruction stream, data read, or data write references to I/O space are not
allowed. The results are unpredictable if I/O space is referenced from compati¬
bility mode.

■ Processor Registers
The only processor register available in compatibility mode is part of the pro¬
cessor status word, and it may be referenced only with the condition code
instructions, RTI and RTT. Access to all other registers must be done in native
mode.

■ Program Synchronization
All PDP-11 systems guarantee that read-modify-write operations to I/O
device registers are interlocked. That is, the device can determine at the time
of the read that the same register will be written as the next bus cycle. This
synchronization also works in memory on most PDP-11 systems. In compatibil¬
ity mode, instructions that have modify destinations perform this synchroniza¬
tion for UNIBUS I/O device registers but never for memory. Compatibility
mode procedures can write data that is to be subsequently executed as an
instruction without requiring additional synchronization.

Appendix A ■ Powers of Binary and Hexadecimal Numbers

Powers of Binary Numbers

Power

Number

128

256

512

1,024

2,048

4,096

8,192

16,384

32,768

65,536

131,072

262,144

524,288

1,048,576

2,097,152

4,194,304

8,388,608

16,777,216

33,554,432

67,108,864

134,217,728

Appendix A-2 ■ Powers of Binary and Hexadecimal Numbers

Powers of Binary Numbers (Cont.)

Power

Number

268,433,456

536,870,912

1,073,741,824

2,147,483,648

4,294,967,296

8,589,934,592

17,179,869,184

34,359,738,368

Powers of Hexadecimal Numbers

Power

Number

256

4,096

65,536

1,048,576

16,777,216

268,435,456

4,294,967,296

68,719,476,736

1,099,511,627,776

17,592,186,044,416

281,474,976,710,656

4,503,599,627,370,496

72,057,594,037,927,936

1,152,921,504,606,846,976

Appendix B ■ List of Instructions by Mnemonic

Mnemonic

Instruction

Opcode

ACBB

Add compare and branch byte

ACBD

Add compare and branch D

floating

ACBF

Add compare and branch F

floating

ACBG

Add compare and branch G

floating

4FFD

ACBH

Add compare and branch H

floating

6FFD

ACBL

Add compare and branch longword

ACBW

Add compare and branch word

ADAWI

Add aligned word, interlocked

ADDB2

Add byte 2 operand

ADDB3

Add byte 3 operand

ADDD2

Add D

floating 2 operand

ADDD3

Add D

floating 3 operand

ADDF2

Add F

floating 2 operand

ADDF3

Add F

floating 3 operand

ADDG2

Add G

floating 2 operand

40FD

ADDG3

Add G

floating 3 operand

41FD

ADDH2

Add H

floating 2 operand

60FD

ADDH3

Add H

floating 3 operand

ADDL2

Add longword 2 operand

61FD
CO

ADDL3

Add longword 3 operand

ADDP4

Add packed 4 operand

ADDP6

Add packed 6 operand

ADDW2

Add word 2 operand

ADDW3

Add word 3 operand

ADWC

Add with carry

AOBLEQ

Add one and branch on less or equal

AOBLSS

Add one and branch on less

ASHL

Arithmetic shift longword

Appendix B-2 ■ List of Instructions by Mnemonic

Mnemonic

Instruction

Opcode

ASHP

Arithmetic shift and round packed

ASHQ

Arithmetic shift quadword

BBC

Branch on bit clear

BBCC

Branch on bit clear and clear

BBCCI

Branch on bit clear and clear, interlocked

BBCS

Branch on bit clear and set

BBS

Branch on bit set

BBSC

Branch on bit set and clear

BBSS

Branch on bit set and set

BBSSI

Branch on bit set and set, interlocked

BCC

Branch on carry clear

BCS

Branch on carry set

BEQL

Branch on equal

BEQLU

Branch on equal, unsigned

BGEQ

Branch on greater or equal

BGEQU

Branch on greater or equal, unsigned

BGTR

Branch on greater

BGTRU

Branch on greater, unsigned

BICB2

Bit clear byte 2 operand

BICB3

Bit clear byte 3 operand

BICL2

Bit clear longword 2 operand

BICL3

Bit clear longword 3 operand

BICPSW

Bit clear processor status word

BICW2

Bit clear word 2 operand

BICW3

Bit clear word 3 operand

BISB2

Bit set byte 2 operand

BISB3

Bit set byte 3 operand

BISL2

Bit set longword 2 operand

BISL3

Bit set longword 3 operand

BISPSW

Bit set processor status word

BISW2

Bit set word 2 operand

BISW3

Bit set word 3 operand

BITB

Bit test byte

Appendix B-3

Mnemonic

Instruction

Opcode

BITL

Bit test longword

BITW

Bit test word

BLBC

Branch on low bit clear

BLBS

Branch on low bit set

BLEQ

Branch on less or equal

BLEQU

Branch on less or equal, unsigned

BLSS

Branch on less

BLSSU

Branch on less, unsigned

BNEQ

Branch on not equal

BNEQU

Branch on not equal, unsigned

BPT

Breakpoint fault

BRB

Branch with byte displacement

BRW

Branch with word displacement

31
10

BSBB

Branch to subroutine with byte displacement

BSBW

Branch to subroutine with word displacement 30

BUGL

Bugcheck longword

FDFF

BUGW

Bugcheck word

FEFF

BVC

Branch on overflow clear

BVS

Branch on overflow set

ID
FA

CALLG

Call with general argument list

CALLS

Call with stack

CASE

BCase byte

CASEL

Case longword

CASEW

Case word

CHME

Change mode to executive

CHMK

Change mode to kernel

CHMS

Change mode to supervisor

CHMU

Change mode to user

CLRB

Clear byte

CLRD

Clear D

floating

CLRF

Clear F

floating

CLRG

Clear G

floating

CLRH

Clear H

floating

7CFD

Appendix B-4 • List of Instructions by Mnemonic

Mnemonic

Instruction

Opcode

CLRL

Clear longword

CLRO

Clear octaword

7CFD

CLRQ

• Clear quadword

CLRW

Clear word

CMPB

Compare byte

CMPC3

Compare character 3 operand

CMPC3

Compare character 5 operand

CMPD

Compare D

floating

CMPF

Compare F

floating

CMPG

Compare G

floating

31FD

CMPH

Compare H

floating

71FD

CMPL

Compare longword

CMPP3

Compare packed 3 operand

CMPP4

Compare packed 4 operand

CMPV

Compare field

CMPW

Compare word

CMPZV

Compare zero-extended field

CRC

Calculate cyclic redundancy check

CVTBD

Convert byte to D

floating

CVTBF

Convert byte to F

floating

CVTBG

Convert byte to G

floating

4CFD

CVTBH

Convert byte to H

floating

6CFD

CVTBL

Convert byte to longword

CVTBW

Convert byte to word

CVTDB

Convert D

floating to byte

CVTDF

Convert D

floating to F

floating

CVTDH

Convert D

floating to H

floating

32FD

CVTDL

Convert D

floating to longword

CVTDW

Convert D

floating to word

CVTFB

Convert F

floating to byte

CVTFD

Convert F

floating to D

floating

CVTFG

Convert F

floating to G

floating

99FD

CVTFH

Convert F

floating to H

floating

98FD

Appendix B-5

Mnemonic

Instruction

CVTFL

Convert F

floating to longword

CVTFW

Convert F

floating to word

CVTGB

Convert G

floating to byte

48FD

CVTGF

Convert G

floating to F

floating

33FD

CVTGH

Convert G

floating to H

floating

56FD

CVTGL

Convert G

floating to longword

4AFD

CVTGW

Convert G

floating to word

49FD

CVTHB

Convert H

floating to byte

CVTHD

Convert H

floating to D

floating

F7FD

CVTHF

Convert H_floating to F_floating

F6FD

CVTHG

Convert H

floating to G

76FD

CVTHL

Convert H

floating to longword

CVTHW

Convert H_floating to word

69FD

CVTLB

Convert longword to byte

CVTLD

Convert longword to D

floating

CVTLF

Convert longword to F

floating

CVTLG

Convert longword to G

floating

4EFD

CVTLH

Convert longword to H

floating

CVTLP

Convert longword to packed

CVTLW

Convert longword to word

CVTPL

Convert packed to longword

CVTPT

Convert packed to trailing numeric

CVTPS

Convert packed to leading separate numeric

Opcode
4A

68FD

floating

6AFD

6EFD

CVTRDL

Convert rounded D

floating to longword

CVTRFL

Convert rounded F

floating to longword

CVTRGL

Convert rounded G

floating to longword

4BFD

CVTRHL

Convert rounded FI

floating to longword

6BFD

CVTSP

Convert leading separate numeric to packed

CVTTP

Convert trailing numeric to packed

CVTWB

Convert word to byte

CVTWD

Convert word to D

floating

CVTWF

Convert word to F

floating

CVTWG

Convert word to G

floating

4DFD

Appendix B-6 ■ List of Instructions by Mnemonic

Opcode

Mnemonic

Instruction

CVTWH

Convert word to H

CVTWL

Convert word to longword

DECB

Decrement byte

DECL

Decrement longword

DECW

Decrement word

DIVB2

Divide byte 2 operand

DIVB3

Divide byte 3 operand

DIVD2

Divide D

floating 2 operand

DIVD3

Divide D

floating 3 operand

DIVF2

Divide F

floating 2 operand

DIVF3

Divide F

floating 3 operand

DIVG2

Divide G

floating 2 operand

46FD

DIVG3

Divide G

floating 3 operand

47FD

DIVH2

Divide H

floating 2 operand

66FD

DIVH3

Divide H

floating 3 operand

67FD

DIVL2

Divide longword 2 operand

DIVL3

Divide longword 3 operand

DIVP

Divide packed

DIVW2

Divide word 2 operand

DIVW3

Divide word 3 operand

EDITPC

Edit packed to character

EDIV

Extended divide

EMODD

Extended modulus D

floating

6DFD

floating

EMODF

Extended modulus F

floating

EMODG

Extended modulus G

floating

54FD

EMODH

Extended modulus H

floating

74FD

EMUL

Extended multiply

EXTV

Extract field

EXTZV

Extract zero-extended field

FFC

Find first clear bit

FFS

Find first set bit

HALT

Halt

INCB

Increment byte

Appendix B- 7

Mnemonic

Instruction

INCL

Increment longword

INCW

Increment word

B6
OA

Opcode

INDEX

Compute index

INSQHI

Insert into queue head, interlocked

INSQTI

Insert into queue tail, interlocked

INSQUE

Insert into queue

INSV

Insert field

JMP

Jump

JSB

Jump to subroutine

LDPCTX

Load process context

LOCC

Locate character

MATCHC

Match characters

MCOMB

Move complemented byte

MCOML

Move complemented longword

MCOMW

Move complemented word

MFPR

Move from processor register

MNEGB

Move negated byte

MNEGD

Move negated D

floating

MNEGF

Move negated F

floating

MNEGG

Move negated G

floating

32FD

MNEGH

Move negated H

floating

72FD

MNEGL

Move negated longword

MNEGW

Move negated word

MOVAB

Move address of byte

MOVAD

Move address of D

floating

MOVAF

Move address of F

floating

MOVAG

Move address of G

floating

MOVAH

Move address of H

floating

7EFD

MOVAL

Move address of longword

MOVAO

Move address of octaword

7EFD

MOVAQ

Move address of quadword

MOVAW

Move address of word

MOVB

Move byte

Appendix B-8 • List of Instructions by Mnemonic

Mnemonic

Instruction

Opcode

MOVC 3

Move character 3 operand

MOVC5

Move character 5 operand

MOVD

Move D

floating

MOVF

Move F

floating

MOVG

Move G

floating

50FD

MOVH

Move H

floating

70FD

MOVL

Move longword

MOVO

Move octaword

7DFD

MOVP

Move packed

MOVPSL

Move processor status longword

MOVQ

Move quadword

MOVTC

Move translated characters

MOVTUC

Move translated until character

MOVW

Move word

MOVZBL

Move zero-extended byte to longword

MOVZBW

Move zero-extended byte to word

MOVZWL

Move zero-extended word to longword

MTPR

Move to processor register

MULB2

Multiply byte 2 operand

MULB3

Multiply byte 3 operand

MULD2

Multiply D

floating 2 operand

MULD3

Multiply D

floating 3 operand

MULF2

Multiply F

floating 2 operand

MULF3

Multiply F

floating 3 operand

MULG2

Multiply G

floating 2 operand

44FD

MULG3

Multiply G

floating 3 operand

45FO

MULH2

Multiply H

floating 2 operand

64FD

MULH3

Multiply H

floating 3 operand

65FD

MULL2

Multiply longword 2 operand

MULL3

Multiply longword 3 operand

MULP

Multiply packed

MULW2

Multiply word 2 operand

MULW3

Multiply word 3 operand

Appendix B-9

Mnemonic

Instruction

NOP

No operation

POLYD

Polynomial evaluate D

floating

POLYF

Polynomial evaluate F

floating

POLYG

Polynomial evaluate G

floating

55FD

POLYH

Polynomial evaluate H

floating

POPR

Pop registers

PROBER

Probe read access

PROBEW

Probe write access

PUSHAB

Push address byte

PUSHAD

Push address of D

floating

PUSHAF

Push address of F

floating

PUSHAG

Push address of G

floating

PUSHAH

Push address of H

floating

PUSHAL

Push address of longword

PUSHAO

Push address of octaword

7FFD

PUSHAQ

Push address of quadword

PUSHAW

Push address of word

PUSHL

Push longword

PUSHR

Push registers

REI

Return from exception or interrupt

Opcode
01
75

75FD
BA

7FFD
DF

REMQHI

Remove from queue head, interlocked

REMQTI

Remove from queue tail, interlocked

REMQUE

Remove from queue

RET

Return from called procedure

ROTL

Rotate longword

RSB

Return from subroutine

SBWC

Subtract with carry

SCANC

Scan for character

SKPC

Skip character

SOBGEQ

Subtract one and branch on greater or equal

SOBGTR

Subtract one and branch on greater

SPANC

Span characters

SUBB2

Subtract byte 2 operand

Appendix B-10m List of Instructions by Mnemonic

Opcode

Mnemonic

Instruction

SUBB3

Subtract byte 3 operand

SUBD2

Subtract D

floating 2 operand

SUBD3

Subtract D

floating 3 operand

SUBF2

Subtract F

floating 2 operand

SUBF3

Subtract F

floating 3 operand

SUBG2

Subtract G

floating 2 operand

42FD

SUBG3

Subtract G

floating 3 operand

43FD

SUBH2

Subtract H

floating 2 operand

62FD

SUBH3

Subtract H

floating 3 operand

63FD

SUBL2

Subtract longword 2 operand

SUBL3

Subtract longword 3 operand

SUBP4

Subtract packed 4 operand

SUBP6

Subtract packed 6 operand

SUBW2

Subtract word 2 operand

SUBW3

Subtract word 3 operand

SVPCTX

Save process context

TSTB

Test byte

TSTD

Test D

floating

TSTF

Test F

floating

TSTG

Test G

floating

53FD

TSTH

Test H

floating

73FD

TSTL

Test longword

TSTW

Test word

XFC

Extended function call

XORB2

Exclusive OR byte 2 operand

XORB3

Exclusive OR byte 3 operand

XORL2

Exclusive OR longword 2 operand

XORL3

Exclusive OR longword 3 operand

XORW2

Exclusive OR word 2 operand

XORW3

Exclusive OR word 3 operand

Appendix C ■ List of Instructions by Opcode

Opcode

Mnemonic

HALT

Halt

NOP

No operation

REI

Return from exception or interrupt

BPT

Breakpoint fault

RET

Return from called procedure

RSB

Return from subroutine

LDPCTX

Load process context

SVPGTX

Save process context

Instruction

CVTPS

Convert packed to leading separate numeric

CVTSP

Convert leading separate numeric to packed

INDEX

Compute index

CRC

Calculate cyclic redundancy check

PROBER

Probe read access

PROBEW

Prove write access

INSQUE

Insert into queue

REMQUE

Remove from queue

BSBB

Branch to subroutine with byte displacement

BRB

Branch with byte displacement

BNEQ

Branch on not equal

BNEQU

Branch on not equal, unsigned

BEQL

Branch on equal

BEQLU

Branch on equal, unsigned

BGTR

Branch on greater

BLEQ

Branch on less or equal

JSB

Jump to subroutine

JMP

Jump

BGEQ

Branch on greater or equal

BLSS

Branch on less

Appendix C-2 • List of Instructions by Opcode

Opcode

Mnemonic

Instruction

BGTRU

Branch on greater, unsigned

BLEQU

Branch on less or equal, unsigned

BVC

Branch on overflow clear

BVS

Branch on overflow set

BGEQU

Branch on greater or equal, unsigned

BCC

Branch on carry clear

BLSSU

Branch on less, unsigned

BCS

Branch on carry set

ADDP4

Add packed 4 operand

ADDP6

Add packed 6 operand

SUBP4

Subtract packed 4 operand

SUBP6

Subtract packed 6 operand

CVTPT

Convert packed to trailing numeric

MULP

Multiply packed

CVTTP

Convert trailing numeric to packed

DIVP

Divide packed

MOVC 3

Move character 3 operand

CMPC3

Compare character 3 operand

SCANC

Scan for character

SPANC

Span characters

MOVC5

Move character 5 operand

CMPC5

Compare character 5 operand

MOVTC

Move translated characters

MOVTUC

Move translated until character

BSBW

Branch to subroutine with word displacement

BRW

Branch with word displacement
Convert word to longword

CVTWL

CVTWB

Convert word to byte

MOVP

Move packed

CMPP3

Compare packed 3 operand

CVTPL

Convert packed to longword

CMPP4

Compare packed 4 operand

EDITPC

Edit packed to character

Opcode

Mnemonic

Instruction

MATCHC

Match characters

LOCC

Locate character

SKPC

Skip character

MOVZWL

Move zero-extended word to longword

ACBW

Add compare and branch word

MOVAW

Move address of word

PUSHAW

Push address of word

ADDF2

Add F_floating 2 operand
Add F

ADDF3

SUBF2

Subtract F

floating 2 operand

SUBF3

Subtract F

floating 3 operand

MULF2

Multiply F_floating 2 operand

MULF3

Multiply F

DIVF2

Divide F

floating 2 operand

DIVF3

Divide F

floating 3 operand

CVTFB

Convert F

floating to byte

CVTFW

Convert F

floating to word
floating to longword

CVTFL

Convert F

CVTRFL

Convert rounded F

floating to longword

CVTBF

Convert byte to F

floating

CVTWF

Convert word to F

floating

CVTLF

Convert longword to F

ACBF

Add compare and branch floating

MOVF

Move F

CMPF

Compare F

MNEGF

Move negated F

TSTF

Test F

floating

floating
floating
floating

floating

EMODF

Extended modulus F

floating

POLYF

Polynomial evaluate F

floating

CVTFD

Convert F

Reserved

ADAWI

Reserved

floating to D

floating

Add aligned word, interlocked

Appendix C-4 • List of Instructions by Opcode

Instruction

Opcode

Mnemonic

Reserved

INSQHI

Insert into queue head, interlocked

INSQTI

Insert into queue tail, interlocked

REMQHI

Remove from queue head, interlocked

REMQTI

Remove from queue tail, interlocked

ADDD2

Add D

floating 2 operand

ADDD3

Add D

floating 3 operand

SUBD2

Subtract D

floating 2 operand

SUBD3

Subtract D

floating 3 operand

MULD2

Multiply D

floating 2 operand

MULD3

Multiply D

floating 3 operand

DIVD2

Divide D

floating 2 operand

DIVD3

Divide D

floating 3 operand

CVTDB

Convert D

floating to byte

CVTDW

Convert D

floating to word

CVTDL

Convert D

floating to longword

CVTRDL

Convert rounded D

floating to longword

CVTBD

Convert byte to D

floating

CVTWD

Convert word to D

floating

CVTLD

Convert longword to D

ACBD

Add compare and branch D

MOVD

Move D

CMPD

Compare D

MNEGD

Move negated D

TSTD

Test D

EMODD

Extended modulus D

floating

POLYD

Polynomial evaluate D

floating

CVTDF

Convert D

Reserved

ASHL

Arithmetic shift longword

ASHQ

Arithmetic shift quadword

EMUL

Extended multiply

floating
floating

floating
floating
floating

floating

floating to F

floating

Opcode

Mnemonic

Instruction

7B_EDIV_Extended divide
7C_CLRQ_Clear quadword_
7C

CLRD

Clear D_floating

CLRG

Clear G_floating

7D_MQVQ_Move quadword

7E_MOVAQ_Move address of quadword
7E_MOVAD

Move address of D

floating

7E_MOVAG

Move address of G

floating

7F_PUSHAQ

Push address of quadword

7F_PUSH AD

Push address of D

floating

7F_PUSHAG

Push address of G

floating

ADDB2

Add byte 2 operand

ADDB3

Add byte 3 operand

82 _SUBB2_Subtract byte 2 operand
83 _SUBB3_Subtract byte 3 operand_
84 _MULB2_Multiply byte 2 operand_
85 _MULB3_Multiply byte 3 operand_
86

DIVB2

Divide byte 2 operand

DIVB3

Divide byte 3 operand

88 _BISB2_Bit set byte 2 operand_
89

BISB3

Bit set byte 3 operand

BICB2

Bit clear byte 2 operand

BICB3

Bit clear byte 3 operand

8C_XORB2_Exclusive OR byte 2 operand
8D_XQRB3_Exclusive OR byte 3 operand
8E

MNEGB

Move negated byte

CASEB

Case byte

MOVB

Move byte

CMPB

Compare byte

92 _ MCOMB

Move complemented byte

93 _ BITB

Bit test byte

CLRB

Clear byte

TSTB

Test byte

Appendix C-6 ■ List of Instructions by Opcode

Opcode

Mnemonic

Instruction

INCB

Increment byte

DECB

Decrement byte

CVTBL

Convert byte to longword

CVTBW

Convert byte to word

MOVZBL

Move zero-extended byte to longword

MOVZBW

Move zero-extended byte to word

ROTL

Rotate longword

ACBB

Add compare and branch byte

MOVAB

Move address of byte

PUSHAB

Push address of byte

ADDW2

Add word 2 operand

ADDW3

Add word 3 operand

SUBW2

Subtract word 2 operand

SUBW3

Subtract word 3 operand

MULW2

Multiply word 2 operand

MULW3

Multiply word 3 operand

DIVW2

Divide word 2 operand

DIVW3

Divide word 3 operand

BISW2

Bit set word 2 operand

BISW3

Bit set word 3 operand

BICW2

Bit clear word 2 operand

BICW3

Bit clear word 3 operand

XORW2

Exclusive OR word 2 operand

XORW3

Exclusive OR word 3 operand

MNEGW

Move negated word

CASEW

Case word

MOVW

Move word

CMPW

Compare word

MCOMW

Move complemented word

BITW

Bit test word

CLRW

Clear word

TSTW

Test word

INCW

Increment word

Opcode

Mnemonic

B7_

DECW_Decrement word

Instruction

B8_

BISPSW

Bit set processor status word

B9_

BICPSW

Bit clear processor status word

BA_

POPR_Pop register

BB_

PUS FIR

Push register

BC_

CFFMK

Change mode to kernel

CFFME

Change mode to executive

BE_

CHMS_Change mode to supervisor

BF_

CHMU_Change mode to user

CO_

ADDL2_Add longword 2 operand

Cl_

ADDL3_Add longword 3 operand

C2_

SUBL2_Subtract longword 2 operand

C3_

SUBL3_Subtract longword 3 operand

C4_

MULL2

C3_

MULL3_Multiply longword 3 operand

Multiply longword 2 operand

C6_ DIVL2_Divide longword 2 operand
C7_ DIVL3

Divide longword 3 operand

C8_ BISL2_Bit set longword 2 operand
09_ BISL3_Bit set longword 3 operand
CA

BICL2_Bit clear longword 2 operand

CB_ BICL3

Bit clear longword 3 operand

CC_ XORL2

Exclusive OR longword 2 operand

XORL3

Exclusive OR longword 3 operand

MNEGL_Move negated longword

CF_ CASEL

Case longword

DO_ MOVL_Move longword_
D1_ CMPL

Compare longword

D2_ MCOML

Move complemented longword

D3_ BITL

Bit test longword

D4_ CLRL_Clear longword
D4_ CLRF

Clear F_floating

D5_ TSTL

Test longword

Increment longword

INCL

Appendix C-8 ■ List of Instructions by Opcode

Opcode

Mnemonic

Instruction

DECL

Decrement longword

ADWC

Add with carry

SBWC

Subtract with carry

MTPR

Move to processor register

MFPR

Move from processor register

MOVPSL

Move processor status longword

PUSHL

Push longword

MOVAL

Move address of longword

MOVAF

Move address of F

PUSHAL

Push address of longword

PUSHAF

Push address of F

BBS

Branch on bit set

BBC

Branch on bit clear

BBSS

Branch on bit set and set

BBCS

Branch on bit clear and set

BBSC

Branch on bit set and clear

BBCC

Branch on bit clear and clear

BBSSI

Branch on bit set and set, interlocked

BBCCI

Branch on bit clear and clear, interlocked

BLBS

Branch on low bit set

BLBC

Branch on low bit clear

FFS

Find first set bit

FFC

Find first clear bit

CMPV

Compare field

CMPZV

Compare zero-extended field

EXTV

Extract field

EXTZV

Extract zero-extended field

floating

INSV

Insert field

ACBL

Add compare and branch longword

AOBLSS

Add one and branch on less

AOBLEQ

Add one and branch on less or equal

SOBGEQ

Subtract one and branch on greater or equal

SOBGTR

Subtract one and branch on greater

Appendix C-9

Opcode

Mnemonic

CVTLB

Convert longword to byte

CVTLW

Convert longword to word

ASHP

Arithmetic shift and round packed

CVTLP

Convert longword to packed

Instruction

CALLG

Call with general argument list

CALLS

Call with stack argument list

XFC

Extended function call

Reserved

Escape to 2-byte opcode

Reserved

Escape to 2-byte opcode

Reserved

Escape to 2-byte opcode

OOFD

Reserved

31FD

Reserved

32FD

CVTDH

Convert D

floating to H

floating

Convert G

floating to F

floating

33FD

CVTGF

34FD

Reserved

3FFD

Reserved

40FD

ADDG2

Add G

floating 2 operand

41FD

ADDG3

Add G

floating 3 operand

42FD

SUBG2

Subtract G

floating 2 operand

43FD

SUBG3

Subtract G

floating 3 operand

44FD

MULG2

Multiply G

floating 2 operand

45FD

MULG3

Multiply G

floating 3 operand

46FD

DIVG2

Divide G

floating 2 operand

47FD

DIVG3

Divide G

floating 3 operand

48FD

CVTGB

Convert G

floating to byte

49FD

CVTGW

Convert G

floating to word

4AFD

CVTGL

Convert G

floating to longword

Appendix C-10 ■ List of Instructions by Opcode

Opcode

Mnemonic

Instruction

4BFD

CVTRGL

Convert rounded G_floating to longword

4CFD

CVTBG

Convert byte to G

floating

4DFD

CVTWG

Convert word to G

floating

4EFD

CVTLG

Convert longword to G

4FFD

ACBG

Add compare and branch G

50FD

MOVG

Move G

51FD

CMPG

Compare G

52FD

MNEGG

Move negated G

53FD

TSTG

Test G

MFD

EMODG

Extended modulus G

floating

MFD

POLYG

Polynomial evaluate G

floating

56FD

CVTGH

Convert G

57FD

Reserved

5FFD

Reserved

60FD

ADDH2

Add H

floating 2 operand

61FD

ADDH3

Add H

floating 3 operand

62FD

SUBH2

Subtract H

floating 2 operand

63FD

SUBH3

Subtract H

floating 3 operand

64FD

MULH2

Multiply H

floating 2 operand

65FD

MULH3

Multiply H

floating 3 operand

66FD

DIVH2

Divide H

floating 2 operand

67FD

DIVH3

Divide H

floating 3 operand

floating
floating

floating.
floating
floating

floating

floating to H

floating

68FD

CVTHB

Convert H

floating to byte

69FD

CVTHW

Convert H

floating to word

6AFD

CVTHL

Convert H

floating to longword

6BFD

CVTRHL

Convert rounded H

floating to longword

6CFD

CVTBH

Convert byte to H

floating

6DFD

CVTWH

Convert word to H

floating

6EFD

CVTLH

Convert longword to H

6FFD

ACBH

Add compare and branch H

floating
floating

Appendix C-ll

Opcode

Mnemonic

Instruction
Move H

70FD

MOVH

71FD

CMPH

Compare H

72FD

MNEGH

Move negated H

73FD

TSTH

Test H

74FD

EMODH

Extended modulus H

floating

75FD

POLYH

Polynomial evaluate H

floating

76FD

CVTHG

Convert H

77FD

Reserved

7BFD

Reserved

floating
floating
floating

floating

floating to G

7CFD

CLRH

7CFD

CLRO

Clear octaword

7DFD

MOVO

Move octaword

7EFD

MOVAH

Move address of H

7EFD

MOVAO

Move address of octaword

7FFD

PUSHAH

Push address of H

7FFD

PUSHAO

Push address of octaword

80FD

Reserved

Clear H

floating

8FFD

Reserved

90FD

Reserved

97FD

Reserved

98FD

CVTFH

Convert F

floating to H

floating

99FD

CVTFG

Convert F

floating to G

floating

Appendix C-12 ■ List of Instructions by Opcode

Opcode

Mnemonic

Instruction

9AFD

Reserved

9FFD

Reserved

AOFD

Reserved

EFFD

Reserved

FOFD

Reserved

F5FD

Reserved

F6FD

CVTHF

Convert H

floating to F

floating

F7FD

CVTHD

Convert FI

floating to D

floating

F8FD

Reserved

FFFD

Reserved

OOFF

Reserved

FCFF

Reserved

FDFF

BUGL

Bugcheck longword

FEFF

BUGW

Bugcheck word

FFFF

Reserved

Glossary

abort:

An exception that occurs in the middle of an instruction that can

leave the registers and memory in an indeterminate state. When in this state,
the instruction may not be able to be restarted.
absolute indexed mode:

An indexed addressing mode in which the base

operand specifier is addressed in absolute mode.
absolute mode:

Autoincrement deferred mode in which the program coun¬

ter (PC) is used as the register. The PC contains the address of the location
containing the actual operand.
access mode:

Any of the four processor access modes in which software exe¬

cutes. Processor access modes are, in order from most to least privileged and
protected, kernel (mode 0), executive (mode 1), supervisor (mode 2), and user
(mode 3).
access type:

(1) How the processor accesses instruction operands. Access

types are read, write, modify, address, and branch. (2) The way in which a
procedure accesses its arguments.
access violation:

(1) An attempt to reference an address that is not mapped

into virtual memory. (2) An attempt to reference an address that is not accessi¬
ble by the current access mode.
address:

A number used by the operating system and user software to iden¬

tify a storage location. See also virtual address, physical address.
address access type:

A type of operation in which the specified operand of

an instruction is not directly accessed when the processor executes the instruc¬
tion. The context of the address calculation is given by the data type of the
operand.
addressing mode:

The way in which an operand is specified; for example,

the way in which the effective address of an instruction operand is calculated
using the general registers.
address space:

The set of all possible addresses available to a process. Vir¬

tual address space refers to the set of all possible virtual addresses. Physical
address space refers to the set of all possible physical addresses.
alphanumeric character:

An uppercase or lowercase letter (A to Z, a to z), a

dollar sign ($), an underscore (_.), or a decimal digit (0 to 9).
American Standard Code for Information Interchange (ASCII):

A set of

8-bit binary numbers representing the alphabet, punctuation, numerals, con¬
trol, and other special symbols used in text representation and communica¬
tions protocol.

G-2 • Glossary

Argument Pointer:

General register 12 (R12). By convention, the argument

pointer (AP) contains the address of the base of the argument list for proce¬
dures initiated using the CALL instructions.
autodecrement index mode:

A mode in which the base operand specifier

uses autodecrement mode addressing.
autodecrement mode:

A mode in which the contents of the selected register

are decremented, and the result is used as the address of the actual operand of
the instruction. The contents of the register are decremented according to the
data type context of the register—1 for byte; 2 for word; 4 for longword and
F_floating; 8 for quadword, G_floating, and D_floating; and 16 for
octaword and H_floating.
auto deferred indexed mode:

An indexed addressing mode in which the

base operand specifier uses autoincrement deferred mode addressing.
autoincrement deferred mode:

An addressing mode in which the specified

register contains the address of a longword that contains the address of the
actual operand. The contents of the register are incremented by 4 (the num¬
ber of bytes in a longword). If the program counter is used as the register, this
mode is called absolute mode.
autoincrement indexed mode:

An indexed addressing mode in which the

base operand specifier uses autoincrement mode addressing.
autoincrement mode: A mode in which the contents of the specified register
are used as the address of the operand; then the contents of the register are
incremented by the size of the operand.
balance set:

The set of all process working sets currently resident in physical

memory. The processes whose working sets are in the balance set have mem¬
ory requirements that balance with available memory.
base operand address:

The address of the base of a table or array referenced

by index mode addressing.
base operand specifier:

The register used to calculate the base operand

address of a table or array referenced by index mode addressing.
base register:

A general register used to contain the address of the first entry

in a list, table, array, or other data structure.
bit complement:

The result of exchanging Os and Is in the binary representa¬

tion of a number. Thus the bit complement of the binary number 11011001
(217 (decimal)) is 00100110. Bit complements are used in place of their corre¬
sponding binary numbers in some arithmetic computations in computers.
Also called one's complement.
bit string:

See variable length bit field.

G-3

block:

(1) The smallest addressable unit of data that a device can transfer in

an I/O operation (512 contiguous bytes for most disk devices). (2) An arbi¬
trary number of contiguous bytes used to store logically related status, con¬
trol, or other processing information.
branch access type:

An instruction attribute that indicates that the proces¬

sor does not reference an operand address, but rather that the operand is a
branch displacement. The size of the branch displacement is given by the data
type of the operand.
branch mode:

In branch address mode, the instruction operand specifier is a

signed byte or word displacement. The displacement is added to the contents
of the updated program counter (which is the address of the first byte beyond
the displacement), and the result is the branch address.
byte:

Eight contiguous bits starting on an addressable byte boundary. Bits

are numbered from the right, 0 through 7, with bit 0 the low-order bit.
cache memory: A small, high-speed memory placed between main memory
and the processor.
call frame:

See stack frame.

Call instructions:

The processor instructions CALLG (Call Procedure with

General Argument List) and CALLS (Call Procedure with Stack Argument
List).
call stack:

The stack and conventional stack structure used during a proce¬

dure call. Each access mode of each process context has one call stack, and the
interrupt service context has one call stack.
character:

A symbol represented by an ASCII code. See also alphanumeric

character.
character string:

A contiguous set of bytes identified by two attributes—an

address and a length. Its address is the address of the byte containing the first
character of the string. Subsequent characters are stored in bytes of increas¬
ing addresses. The length is the number of characters in the string.
character string descriptor:

A quadword data structure used for passing

character data (strings). The first word of the quadword contains the length of
the character string. The second word can contain type information. The
remaining longword contains the address of the string.
compatibility mode:
condition codes:

See PDP-11 compatibility mode.

Four bits in the Processor Status Word (PSW) that indicate

the results of previously executed instructions.
condition handler: A procedure that a process wants the system to execute
when an exception condition occurs.

G-4 • Glossary

console:

A manual-control unit integrated into the central processor that

enables the operator to start and stop the system, monitor system operation,
and run diagnostics.
console terminal:

The part of a computer used by the operator to determine

the status of, and to control, the operation of the computer. The console may
have controls and indicators that are used for manual operation of the com¬
puter.
context indexing:

The process of indexing through a data structure automat¬

ically because the size of the data type is known and is used to determine the
offset factor.
context switching:

Interrupting the activity in progress and switching to

another activity. Context switching occurs as one process after another is
scheduled for execution.
control region:

The highest-addressed half of process space (the PI region).

Control region virtual addresses refer to the process-related information used
by the system to control the process.
control region base register (P1BR):

The processor register, or its equiva¬

lent in a hardware process control block, that contains the base virtual address
of a process control region page table.
control region length register (P1LR):

The processor register, or its equiva¬

lent in a hardware process control block, that contains the number of nonexist¬
ent page table entries for virtual pages in a process control region.
current access mode:

The processor access mode of the currently executing

software. The Current Mode field of the Processor Status Longword (PSL)
indicates the access mode of the currently executing software.
D_floating datum:

Eight contiguous bytes starting on an addressable byte

boundary that are interpreted as containing a floating point number. The bits
are labeled from right to left, 0 to 63.
data structure:

Any table, list, array, queue, or tree whose format and access

conventions are well defined for reference by one or more images.
data type: In reference to the processor instructions, the data type of an oper¬
and identifies the size of the operand and the significance of the bits in the
operand. Operand data types include floating point, integer, character string,
packed decimal string, numeric string, queue, and variable length bit field.
descriptor:

A data structure used in calling sequences for passing argument

types, addresses and other optional information. See character string descrip¬
tor.
device interrupt:

An interrupt received on interrupt priority levels 16

through 23. Device interrupts can be requested only by devices, controllers,
and memories.

device register:

A location in device controller logic used to request device

functions (such as I/O transfers) and/or to report status.
diagnostic:

A program that tests logic and reports any faults it detects,

direct mapping cache:

A cache organization in which any block of main

memory data can be placed in only one possible position in the cache. Compare
with fully associative cache.
displacement deferred indexed mode:

An indexed addressing mode in

which the base operand specifier uses displacement deferred mode address¬
ing.
displacement deferred mode:

A mode in which the specifier extension is a

byte, word, or longword displacement. The displacement is sign-extended to
32 bits and added to a base address obtained from the specified registers. The
result is the address of a longword that contains the address of the actual oper¬
and.
displacement indexed mode: A mode in which the base operand specifier
uses displacement mode addressing.
displacement mode:

A displacement addressing mode in which the specifier

extension is a byte, word, or longword displacement. The displacement is sign
extended to 32 bits and added to a base address obtained from the specified
register. The result is the address of the actual operand.
double floating datum:

See D_floating datum.

effective address: The address obtained after indirect or indexing modifica¬
tions are calculated.
entry mask:

A word whose bits represent the registers to be saved or

restored on a subroutine or procedure call using the call and return instruc¬
tions.
entry point:

A location that can be specified as the object of a call instruc¬

tion. It contains an entry mask and exception enables known as the entry
point mask.
event:

A change in process status or an indication of the occurrence of some

activity that concerns an individual process or cooperating processes. An inci¬
dent reported to the scheduler that affects a process’s ability to execute.
Events can be synchronous with the process’s execution (waic request), or
they can be asynchronous (I/O completion).
exception:

An event that changes the normal flow of instruction or set of

instructions. Interrupts and branch, call, case, and jump instructions are
excluded from this class of events. Exceptions are detected by the hardware.
There are three types of hardware exceptions—traps, faults, and aborts.

G-6 ■ Glossary

exception condition:

A hardware- or software-detected event other than an

interrupt or jump, branch, case, or call instruction that changes the normal
flow of instruction execution.
exception enables:

See trap enables,

exception vector:

See vector.

executive mode:

The second most privileged processor access mode (mode

1). The Record Management Services (RMS) and many of the operating sys¬
tem’s programmed service procedures execute in executive mode.
F_floating datum:

Four contiguous bytes starting on an addressable byte

boundary. The bits are labeled from right to left 0 to 31. A two-word floating¬
point number is identified by the address of the byte containing bit 0.
fault: A hardware exception condition that occurs in the middle of an instruc¬
tion. A fault leaves the registers and memory in a consistent state so the elimi¬
nation of the fault and restarting the instruction gives correct results.
field:

A set of contiguous bytes in a logical record. See also variable length

bit field.
floating (point) datum:
frame pointer:

See F_floating datum.

General register 13 (R13). By convention, the frame pointer

(FP) contains the base address of the most recent call frame on the stack.
fully associative cache:

A cache organization in which any block of data

from main memory can be placed anywhere in the cache. Compare with direct
mapping cache.
G_floating datum:

Eight contiguous bytes starting on an arbitrary byte

boundary. The bits are labeled from the right 0 through 63. The address of a
G_floating datum is specified by the address of the byte containing bit 0.
general register: Any of the sixteen 32-bit registers used as the primary oper¬
ands of the native mode instructions. The general registers include 12 general
purpose registers that can be used as accumulators, as counters, and as
pointers to locations in main memory, and the Frame Pointer (FP), Argument
Pointer (AP), Stack Pointer (SP), and Program Counter (PC) registers.
giga:

A prefix meaning 1,000,000,000 (109). In the computer industry, giga

is often used to mean 1,073,741,824 (230) which is about 7.4 percent larger.
H_floating datum:

Sixteen contiguous bytes starting on an arbitrary byte

boundary. The bits are labeled from the right 0 through 127. The address of
an H_floating datum is specified by the address of the byte containing
bit 0.

G-7

hardware context:

The values contained in the following registers while a

process is executing—the Program Counter (PC), the Processor Status Longword (PSL), the 14 general registers (RO through R13), the four processor reg¬
isters (POBR, POLR, PlBR, and P1LR), the Stack Pointer (SP) for the current
access mode in which the processor is executing, and the contents to be loaded
in the stack pointer for every access mode other than the current access mode.
When a process is executing, its hardware context is continuously updated by
the processor. When a process is not executing, its hardware context is stored
in its hardware process control block.
hardware process control block (PCB):

A data structure known to the pro¬

cessor that contains the hardware context when a process is not executing. A
process’s hardware PCB resides in its process header.
image file:

A file containing the necessary information to establish an incar¬

nation of a user program in a process including the memory image. Image files
can be of the executable, shareable, and system types.
immediate mode:

Autoincrement mode addressing in which the program

counter is used as the register.
incarnation:

A resource that is automatically allocated on a call or recursive

call. A resource is a physical part of the computer such as a device, memory, or
an interlocked data structure.
indexed addressing mode:

In indexed mode addressing, two registers are

used to determine the actual instruction operand — an index register and a
base operand specifier. The contents of the index register are used as an index
(offset) into a table or array.
index register:

A register containing an address offset.

instruction buffer:

An 8-byte buffer in the processor used to contain bytes

of the instruction currently being decoded and to prefetch instructions in the
instruction stream. The control logic continuously fetches data from memory
to keep the 8-byte buffer full.
interleaving:

Assigning consecutive physical memory addresses alternately

between two memory controllers.
internal processor register:

A part of the processor used by the operating

system software to control the execution states of the computer system. Some¬
times called privileged processor register. These registers are accessed with
MTPR and MFPR instructions.
interrupt:

An event other than an exception or branch, call, case, or jump

instruction that changes the normal flow of instruction execution. Interrupts
are generally external to the process executing when the interrupt occurs. See
also device interrupt, software interrupt, and urgent interrupt.

G-8 ■ Glossary

interrupt priority level (IPL):

The interrupt level at which the processor

executes when an interrupt is generated. There are 31 possible interrupt prior¬
ity levels (IPL). IPL 1 is lowest, 31 highest.

interrupt service routine:

The software executed when a device interrupt

occurs.

interrupt stack: The systemwide stack used when executing in interrupt ser¬
vice context. At any time, the processor is either in a process context or in
systemwide interrupt service context. When executing in interrupt service
context, the processor is operating with kernel privileges on the kernel or
interrupt stack. The interrupt stack is not context-switched or swapped.

interrupt stack pointer:

The stack pointer for the interrupt stack. Unlike

the stack pointers for process context stacks, which are stored in the hardware
PCB, the interrupt stack pointer is stored in an internal register.

interrupt vector: See vector.
kernel mode: The most privileged processor access mode (mode 0). The oper¬
ating system’s most privileged services (I/O drivers, the pager) run in kernel
mode.

literal mode: An addressing mode in which the instruction operand is a con¬
stant whose value is expressed in a 6-bit field of the instruction.

longword: Four contiguous bytes starting on an addressable byte boundary.
Bits are numbered from right to left 0 through 31.

main memory: See physical memory.
mass-storage device: A device capable of reading and writing data on mass
storage media such as a diskpack or a magnetic tape reel.

memory management:

The system functions that include the hardware’s

page mapping and protection and the operating system’s image activator and
pager.
Memory Mapping Enable (MME):

A bit in a processor register that governs

address translation.

modify access type: A specific way of accessing characterized by a specified
operand of an instruction or procedure being read, and potentially modified
and written, during that instruction’s or procedure’s execution.

native mode: See VAX native mode,
nibble: Four bits of memory; one half of a byte.
normalized fraction: A numeric representation patterned on scientific nota¬
tion, but in which the fraction part of the representation is greater than or
equal to 0.3 and less than 1. As a binary form, such a fraction always begins
with a 1 in the leftmost (most significant) bit, unless the number is zero.
Because of this, the lead 1 is not stored, and a bit-per-number saving is
effected in storage.

G-9

numeric string:

A contiguous sequence of bytes representing up to 31 deci¬

mal digits (one per byte) and possibly a sign. The numeric string is specified
by its lowest addressed location, its length, and its sign representation.
octaword:

An octaword is 16 contiguous bytes starting on an arbitrary byte

boundary. The bits are numbered from the right 0 through 127. An octaword
is specified by the address of the byte containing bit 0.
offset:

A fixed displacement from the beginning of a data structure. System

offsets for items within a data structure normally have an associated symbolic
name used instead of the numeric displacement. Where symbols are defined,
programmers always reference the symbolic names for items in a data struc¬
ture instead of using the numeric displacement.
one’s complement:
opcode:

See bit complement.

Short form of operation code. That part of a machine language

instruction that identifies the operation the CPU is to perform. The pattern of
bits within an instruction that specifies the operation to be performed.
operand specifier:

The pattern of bits in an instruction that indicates the

addressing mode and a register or displacement that identifies an instruction
operand.
operand specifier type:

The access type and data type of an instruction’s

operand(s). For example, test instructions are of read access type because they
only read the value of the operand. The operand can be of byte, word, or longword data type, depending on whether the opcode is for the TST3 (test byte),
TSTW (test word), or TSTL (test longword) instruction.
packed decimal:

A method of representing a decimal number by storing a

pair of decimal digits in one byte, taking advantage of the fact that only four
bits are required to represent the numbers 0 through 9.
packed decimal string:

A contiguous sequence of up to 16 bytes interpreted

as a string of nibbles. Each nibble represents a digit, except the low-order nib¬
ble of the highest addressed byte, which represents the sign. The packed deci¬
mal string is specified by its lowest addressed location and the number of
digits.
page:

(1) A set of 512 contiguous byte locations used as the unit of memory

mapping and protection. (2) The data between the beginning of file and a
page marker, between two markers, or between a marker and the end of a file.
page fault: An exception generated by a reference to a page that is not map¬
ped into a working set.
page fault cluster size:

The number of pages read in on a page fault.

page frame number (PFN):

The address of the first byte of a page in physi¬

cal memory. The high-order 21 bits of the physical address of the base of a
page.

G-10m Glossary

page table entry (PTE):

The data structure that identifies the location and

status of a page of virtual address space. When a virtual page is in memory, the
PTE contains the page. When it is not in memory, the PTE contains the infor¬
mation needed to locate the page on secondary storage (disk).
paging:

The process of bringing pages of an executing process into physical

memory when referenced. When a process executes, all of its pages are said to
reside in virtual memory. Only the actively used pages need to reside in physi¬
cal memory. The remaining pages can reside on disk until they are needed in
physical memory. In this system, a process is paged only when it references
more pages than it is allowed to have in its working set. A page fault occurs
when the process refers to a page not in its working set. This causes the operat¬
ing system’s pager to read in the referenced page if it is on disk, replacing the
least recently faulted pages as needed. A process pages only against itself; that
is, one process cannot exceed the working set limit assigned to it by bringing
in more than its quota of pages. This protects other processes in the system.
PDP-11 compatibility mode:

(This is now an optional feature of the VAX

architecture.) A mode of execution that enables the central processor to exe¬
cute nonprivileged PDP-11 instructions.
physical address:

The address used by hardware to identify a location in

physical memory or on directly addressable secondary storage devices such as a
disk. A physical memory address consists of a page frame number and the num¬
ber of a byte within the page. A physical disk block address consists of a cylin¬
der or track and sector number.
physical address space:

The set of all possible 30-bit physical addresses that

can be used to refer to locations in memory (memory space) or device registers
(I/O space).
physical memory: The memory modules connected to the Synchronous Back¬
plane Interconnect that are used to store (1) instructions that the processor
can directly fetch and execute, and (2) any other data that a processor is
instructed to manipulate. Also called main memory.
position dependent code:

Code that can execute properly only in the loca¬

tions in virtual address space that are assigned to it by the linker.
position independent code:

Code that can execute properly without modifi¬

cation wherever it is located in virtual address space, even if its location is
changed after it has been linked. Generally, this code uses addressing modes
that form an effective address relative to the Program Counter register.
privileged instruction:

In general, any instruction intended for use by the

operating system or privileged system programs. In particular, an instruction
that the processor does not execute unless the current access mode is kernel
mode (for example, HALT, SVPCTX, LDPCTX, MTPR, and MFPR).
privileged processor register:

See internal processor register.

G-ll

procedure:
process:

A routine entered by way of a call instruction.

The basic entity scheduled by the system software that provides

the context in which an image executes. A process consists of an address space
and both hardware and software contexts.
process address space:
process context:

See process space.

The hardware and software contexts of a process.

process control block (PCB):

A data structure used to contain the process

context. The hardware PCB contains the hardware context. The software
PCB contains the software context, which includes a pointer to the hardware
PCB. See also hardware process control block.
process page tables:

The page tables used to describe process virtual mem¬

ory.
process space: The lowest-addressed half of virtual address space, where pro¬
cess instructions and data reside. Process space is divided inco a program
region and a control region.
Processor Status Longword (PSL):

A system-programmed processor regis¬

ter consisting of a word of privileged processor status and the PSW. The privi¬
leged processor status information includes the current interrupt priority
level, the previous access mode, the current access mode, the interrupt stack
bit, the trace trap pending bit, and the compatibility mode bit.
Processor Status Word (PSW):

The low-order word of the Processor Status

Longword. Processor status information includes the condition codes (carry,
overflow, zero, negative), the arithmetic trap enable bits (integer overflow,
decimal overflow, floating underflow), and the trace enable bit.
Program Counter (PC):

General register 15 (R15). At the beginning of an

instruction’s execution, the program counter (PC) normally contains the
address of a location in memory from which the processor will fetch the next
instruction to execute.
program locality:

An indication of the proximity of a program’s references

to virtual memory locations. A program with a high degree of locality does not
refer to many widely scattered virtual addresses in a short period of time.
program region:

The lowest-addressed half of process address space (PO

space). The program region contains the image being executed by the process
and other user code called by the image.
program region base register (POBR):

The processor register, or its equiva¬

lent in a hardware process control block, that contains the base virtual address
of the page table entry for virtual page number 0 in a process program region.
program region length register (POLR):

The processor register, or its equiv¬

alent in a hardware process control block, that contains the number of entries
in the page table for a process program region.

G-12 • Glossary

quadword:

Eight contiguous bytes (64 bits) starting on an addressable byte

boundary. Bits are numbered from right to left, 0 to 63. A quadword is identi¬
fied by the address of the byte containing the low-order bit (bit 0).
queue:

(1) noun. A circular, doubly linked list. (2) verb. To make an entry in

a list or table, perhaps using the INSQUE instruction.
read access type:

An instruction or procedure operand attribute indicating

that the specified operand is only read during instruction or procedure execu¬
tion.
register:

A storage location in hardware logic other than main memory. See

also general register, processor register, device register.
register deferred indexed mode:

An indexed addressing mode in which the

base operand specifier uses register deferred mode addressing.
register deferred mode:

An addressing mode in which the contents of the

specified register are used as the address of the actual instruction operand.
register mode:

An addressing mode in which the contents of the specified

A method used to transfer in one I/O operation data from

discontiguous pages in memory to contiguous blocks on disk, or data from con¬
tiguous blocks on disk to discontiguous pages in memory.
secondary storage:
signal:

Random access mass storage.

(1) An electrical impulse conveying information. (2) The software

mechanism used to indicate that an exception condition was detected.
software interrupt:

An interrupt generated on interrupt priority levels 1

through 15, that can be requested only by software.
software process control block:
stack:

See process control block.

An area of memory set aside for temporary storage, or for procedure

and interrupt service linkages. A stack uses the last-in/ first-out concept. As
items are added to (pushed on) the stack, the stack pointer decrements. As
items are retrieved from (popped off) the stack, the stack pointer increments.
stack frame:

A standard data structure built on the stack during a procedure

call, starting from the location addressed by the frame pointer and going to
lower addresses, and popped off during a return from procedure. Also called
call frame.
Stack Pointer (SP):

General register 14 (R14). SP contains the address of

the top (lowest address) of the processor-defined stack. Reference to SP will
access one of the five possible stack pointers—kernel, executive, supervisor,
user, or interrupt—depending on the value in the current mode and interrupt
stack bits in the processor status longword.
store through:

See write through.

G-13

Supervisor mode:

The third most privileged processor access mode (mode

2). The operating system’s command interpreter runs in supervisor mode.
Synchronous Backplane Interconnect (SBI):

That part of the hardware

that interconnects the processor, memory controllers, MASSBUS adapters,
and the UNIBUS adapter.
system address space:

See system space, system region.

system base register (SBR): A processor register that contains the physical
address of the base of the system page table.
system control block (SCB):

The data structure in system space that con¬

tains all the interrupt and exception vectors known to the system.
system control block base register (SCBB): A processor register containing
the base address of the system control block.
system identification register (SIR):
the processor type and serial number.
system length register (SLR):

A processor register which contains

A processor register containing the length of

the system page table in longwords, that is, the number of page table entries in
the system region page table.
system page table (SPT):

The data structure that maps the system region

virtual addresses, including the addresses used to refer to the process page
tables. The system page table (SPT) contains one page table entry (PTE) for
each page of system region virtual memory. The physical base address of the
SPT is contained in a register called the system base register (SBR).
system region:

The third quarter of virtual address space; that is, the lower-

addressed half of system space. Virtual addresses in the system region are
shareable between processes. Some of the data structures mapped by system
region virtual addresses are system entry vectors, the system control block
(SCB), the system page table (SPT), and process page tables.
system space: The higher-addressed half of virtual address space. See also
system region.
system virtual address: A virtual address identifying a location mapped by
an address in system space.
system virtual space:
terminal:

See system space.

The general name for those peripheral devices that have key¬

boards and videoscreens or printers. Under program control, a terminal
enables users to type commands and data on the keyboard and receive mes¬
sages on the videoscreen or printer. Examples of terminals are the LA38 DECwriter hardcopy terminal and the VT100 video display terminal.
translation buffer: An internal processor cache containing translations for
recently used virtual addresses.

G-14m Glossary

trap:

An exception condition that occurs at the end of the instruction that

caused the exception. The program counter (PC) saved on the stack is the
address of the next instruction that would normally have been executed. All
software can enable and disable some of the trap conditions with a single
instruction.
trap enables:

Three bits in the Processor Status Word that control the pro¬

cessor’s action on certain arithmetic exceptions.
two’s complement:

A binary representation for integers in which a negative

number is one greater than the bit complement of the positive number.
two-way associative cache:

A type of cache memory organization that has

two groups of directly mapped blocks. Each group contains several blocks for
each index position in the cache. A block of data from main memory can go
into either group at its proper index position. A two-way associative cache is a
compromise between the extremes of fully associative and direct mapping
cache organizations. It takes advantage of the features of both,
undefined: An operation that may vary from moment to moment, implemen¬
tation to implementation, and instruction to instruction. The operation can
vary in effect from doing nothing to halting system operation. Nonprivileged
software should avoid invoking operations identified as undefined.
unpredictable:

Results of an operation that may vary from moment to

moment, implementation to implementation, and instruction to instruction.
Engineering Change Orders (ECOs) may alter unpredictable results. Software
should not depend on results specified as unpredictable.
urgent interrupt:

An interrupt received on interrupt priority levels 24

through 31. These can be generated only by the processor for the interval
clock, serious errors, and powerfail.
user mode:

The least privileged processor access mode (mode 3). User pro¬

cesses and the Runtime Library procedures run in user mode.
user privileges:

The privileges granted a user by the system manager.

variable length bit field:

A set of 0 to 32 contiguous bits located arbitrarily

with respect to byte boundaries. A variable bit field has four attributes—the
address of a byte, the bit position of the starting location of the bit field with
respect to bit 0 of the byte address, the size of the bit field in bits, and
whether the field is signed or unsigned.
VAX native mode:

The processor’s primary execution mode.

G-25

vector:

(1) An interrupt or exception vector is a storage location, known to

the system, that contains the starting address of a procedure to be executed
when a given interrupt or exception occurs. The system defines separate vec¬
tors for each interrupting device controller and for classes of exceptions. Each
system vector is a longword. (2) For the purposes of exception handling, users
can declare up to two software exception vectors (primary and secondary) for
each of the four access modes. Each vector contains the address of a condition
handler. (3) A one-dimensional array.
virtual address:

A 32-bit integer identifying a byte location in virtual

address space. The memory management hardware translates a virtual address
to a physical address. The term virtual address may also refer to the address
used to identify a virtual block on a mass storage device.
virtual.address space:

The set of all possible virtual addresses that an image

executing in the context of a process can use to identify the location of an
instruction or of data. The virtual address space seen by the programmer is a
linear array of 4,294,967,296 (232) byte addresses.
virtual memory:

The set of storage locations in physical memory and on disk

that is referred to by virtual addresses. From the programmer’s viewpoint, the
secondary storage locations appear to be locations in physical memory. The
size of virtual memory in any system depends on the amount of physical mem¬
ory available and the amount of disk storage used for nonresident virtual mem¬
ory.
virtual page number:
word:

The virtual address of a page of virtual memory.

Two contiguous bytes (16 bits) starting on an addressable byte bound¬

ary. Bits are numbered from the right, 0 through 15. A word is identified by
the address of the byte containing bit 0.
working set:

The set of pages in process address space to which an executing

process can refer without incurring a page fault. The working set must be resi¬
dent in memory for the process to execute. The remaining pages of that pro¬
cess, if any, are either in memory and not in the process working set or they
are on secondary storage.
write access type:

The specified operand of an instruction or procedure that

is only written during that instruction’s execution.
write allocate: A cache management in which cache is allocated on a write
miss as well as on the usual read miss.
write back:

A cache management technique in which data from a write oper¬

ation to cache is copied into main memory only when the data in cache must be
overwritten. This results in temporary inconsistencies between cache and
main memory. Compare with write through.

G-16m Glossary

write through:

A cache management technique in which data from a write

operation is copied in both cache and main memory. Cache and main memory
data are always consistent. Compare with write hack.

Index

A
aborts, 8-1—8-2
caused by kernel stack not valid
exceptions, 8-14
caused by reserved operand
exceptions, 8-13
absolute index mode, 3-25—5-26
absolute mode, 2-6, 5-37
absolute queues, 2-13, 4-17, 4-18
instructions for, 6-19—6-22
access
control of, 7-16—7-19
to privileged system services,
7-22—7-23
to shared data, synchronization of,
3-3—3-4
to stack registers, 8-30
access control violation faults, 7-20,
8-12, 8-32
access modes, 2-5, 3-1—3-2, 7-17
asynchronous system traps and, 8-8
change mode instruction for,
9-14—9-15
in PDP-11 compatibility mode, 11-2
privileged instructions for,
6-15—6-16
access types, 2-7
in operand notation, 5-1—5-2
add instructions
add, 6-2, 6-11, 6-12, 9-1
add aligned word interlocked
(ADAWI), 3-3, 6-13, 9-2
add compare and branch (ACB),
6-4, 9-2—9-3
add one and branch (AOB), 6-4, 9-3
add packed (ADDP), 6-6, 9-3—9-4
add with carry (ADWC), 6-13, 9-4

address and branch access, 2-7
addresses
instructions for, 6-1—6-2
move address instruction for, 9-44
in PDP-11 compatibility mode, 11-7
push address instruction for, 9-53
translation of, 7-8—7-16
virtual, 2-4
virtual address extension for,
1-2—1-3
in virtual address space, 1-4
addressing
of general registers, 2-9
virtual, 2-4
addressing modes, 2-6, 2-9, 5-10—5-12
absolute, 5-37
absolute index, 5-25—5-26
autodecrement, 5-12—5-13
autodecrement index, 5-24—5-25
autoincrement, 5-14
autoincrement deferred, 5-14—5-16
autoincrement deferred index,
5-23—5-24
autoincrement index, 5-22—5-23
branch mode addressing,
5.41—5.43

displacement, 5-17
displacement deferred, 5-17—5-19
displacement deferred index,
5-27—5-28
displacement index, 5-36—5-27
faults and, 8-12
general mode addressing, 5-12
general register addressing, 5-12
immediate, 5-37—5-39
index, 5-19—5-21
literal, 5-29—5-32
program counter register
addressing, 5-36—5-37
register, 5-32—5-33

1-2 ■ Index

addressing modes, (cont.)

register deferred, 5-33—5-35
register deferred index, 5-21—5-22
relative, 5-39—5-40
relative deferred, 5-41
restarts and, 3-18

backward link, 4-17
base addresses, 6-25
batteries, for time-of-year clock, 3-7

address space, virtual, 7-6—7-8

binary normalized numbers, 6-10

address translation maps, 7-7

bit clear (BIC) instruction, 6-13, 9-5

architectural subsetting, 10-1—10-4

bit clear processor status word
(BICPSW) instruction, 6-18, 9-5

architecture, 1-1—1-2
of PDP-11 compatibility mode,

11-2
argument lists, 3-5
argument pointer (AP), 3-5
arithmetic exceptions, 8-9—8-11
arithmetic instructions, 6-2
add, 9-1
arithmetic shift and round packed
(ASHP), 6-6, 9-4—9-5
arithmetic shift (ASH), 6-13, 9-4
divide, 9-26—9-27
multiply, 9-50—9-51
subtract, 9-60—9-61

bit set (BIS) instruction, 6-13, 9-6
bit set processor status word (BISPSW)
instruction, 6-18, 9-6
bit test (BIT) instruction, 6-14,
9-6—97
branch instructions, 6-4—6-5
add compare and branch, 9-2—9-3
add one and branch, 9-3
branch (BR), 9-7
branch on bit (BB), 9-7
branch on bit and modify without
interlock (BR), 9-8
branch on bit and clear and clear,
interlocked (BBCCI), 3-3

array processing
autoincrement mode used for, 5-14
index instruction for, 6-12
index mode used for, 5-19
assembler, notation conventions for,
5-1
ASTLVL registers, 8-8

branch on bit interlocked (BB),
9-7—9-8
branch on bit set and set,
interlocked (BBSSI), 3-3
branch on condition, 9-8—9-10
branch on low bit (BLB),
9-10—9-11
branch to subroutine (BSB), 2-7,

asynchronous system traps (ASTs), 2-3,
8-7—8-9
autodecrement index mode, 5-24—5-25

6-4, 9-11
case, 9-14
subtract one and branch, 9-61

autodecrement mode, 5-12—5-13

branch mode addressing, 5-41—5-43

autoincrement deferred index mode,

breakpoint fault (BPT) instruction, 6-5,

5-23—5-24
autoincrement deferred mode, 2-6,

5.14—5-16
autoincrement index mode, 5-22—5-23
autoincrement mode, 5-14

9-11
breakpoint faults, 8-11
budcheck (BUG) instruction,
9-11—9-12
byte data type, 4-7
bytes, 4-7, 7-3

1-3

clock registers, 3-7—3-9

comments, in MACRO source
statements, 5-5

cache memory, 3-16—3-17
compare characters (CMPC)
call frames (stack frames), 2-7, 3-5,

instruction, 6-2, 9-16—9-17

6-14, 6-17
compare field (CMP) instruction, 6-25,
call instructions, 2-7, 3-2, 6-4—6-5,

9-17

6-16—18
to access privileged system services,
7-22
call procedure with general
argument list (CALLG), 6-16,
9-12
call procedure with stack argument

compare (CMP) instruction, 6-12, 6-14,
9- 15—9-16
compare packed (CMPP) instruction,
6-6, 9-17
compatibility, with PDP-11 systems,
1-3, 11-1—11-11

lists (CALLS), 9-13
call procedure with stack pointer

compatibility mode bit, 8-7

argument list (CALLS), 6-16,

compatibility mode faults, 8-12

6-17

compatibility mode instruction set,

extended function call, 9-35
frame pointer and, 3-5
trace exceptions and, 8-17
carry condition code, 2-13, 8-5

10- 2
computation instructions, 6-1
computers, architecture of, 1-1

case instructions, 6-4, 9-14

condition codes, 2-13—2-14, 5-5, 8-5

change mode (CHM) instruction,

console receive control/status register,

3-2, 6-15, 7-22, 9-14—9-15
character string data type, 2-12,
4-1—4-2

3-9
console registers, 10-3
console terminal registers, 3-9

edit instruction to convert packed
decimal to, 6-9

console transmit control/status register,
3-9

character string instructions, 6-2—6-3,

10-2

constants, literal mode for, 5-29—5-30

compare characters, 9-16—9-17

context load operations, 3-7

edit, 9-27—9-34
locate character, 9-42—9-43
match character, 9-43
move character, 9-44—9-45
move translated characters, 9-49
move translated until character,

contexts, 2-1, 3-2
for exceptions and interrupts, 2-14
during exceptions and interrupts,
8-4
process, 8-27
switched, 1-3, 2-2—2-3, 3-7

9-49
scan characters, 9-59
skip characters, 9-59—9-60
span characters, 9-60
clear (CLR) instruction, 6-12, 6-14,
9-15

context save operations, 3-7
control instructions, 6-3—6-5
case, 9-14
jump, 9-41
jump to subroutine, 9-41—9-42

See also branch instructions;
subroutines

1-4 ■ Index

conversion exceptions, 8-9
conversion instructions, 6-1
convert (CVT) instruction, 6-12, 6-14,
9-18—9-20
convert leading separate numeric to
packed (CVTSP) instruction, 6-6,

debugging, trace exceptions during,
8-15
decimal overflow trap enable bit, 8-6
decimal string data types
packed, 2-12
packed decimal string, 4-16—4-17
decimal string divide by zero trap

9-20
convert longword to packed (CVTLP)
instruction, 6-6, 9-20—9-21
convert packed to leading separate
numeric (CVTPS) instruction, 6-6,

exceptions, 8-10
decimal string instructions, 6-6—6-9,

10-2
add packed, 9-3—9-4
arithmetic shift and round packed,

9-21

9-4—9-5
convert packed to longword (CVTPL)
instruction, 6-6, 9-21
convert packed to trailing numeric
(CVTPT) instruction, 6-6, 9-22
convert rounded (CVTR) instruction,

compare packed, 9-17
convert leading separate numeric to
packed, 9-20
convert longword to packed,
9-20—9-21
convert packed to leading separate

6-12

numeric, 9-21
convert trailing numeric to packed
(CVTTP) instruction, 6-6, 9-23
cyclic redundancy check (CRC)
instruction, 6-5—6-6, 9-23—9-25

convert packed to longword, 9-21
convert packed to trailing numeric,
9-22
convert trailing numeric to packed,
9-23
divide packed, 9-27
move packed, 9-48

multiply packed, 9-51
subtract packed, 9-62

data
in registers, 4-24—4-25
sharing of, 3-3—3-4
data types, 2-10—2-13, 4-1
address instructions for, 6-2
character string, 4-1—4-2
convert instructions for, 9-18—9-23
floating-point, 4-2—4-6

decimal string overflow trap
exceptions, 8-10
decrement (DEC) instruction, 6-13,
9-26
device controllers, interrupt vectors in,
8-19
device interrupts, 8-19

floating-point, instructions for,

10-1—10-2
instructions symmetrical with, 2-5,

6-1
integer, 4-6—4-9
numeric string, 4-10—4-15
in operand notation, 5-2
packed decimal string, 4-16—4-17
queue, 4-17—4-21
variable length bit field, 4-21—4-24

D_floating-point data type, 2-12,
4- 2—4-3, 6-10
instructions for, 10-1
stored in registers, 4-24, 4-25
displacement deferred index mode,
5- 27—5-28
displacement deferred mode, 2-6,
5-17—5-19
displacement index mode, 5-26—5-27

1-5

displacement mode, 2-6, 5-17
divide by zero floating fault exceptions,

errors
cyclic redundancy check instruction
for, 6-5—6-6

8-11
divide (DIV) instruction, 6-2,
6-10—6-12, 9-26—9-27
divide packed (DIVP) instruction, 6-6,
9-27

processor, 3-18
in use of stacks, 3-14
event handling, 8-1—8-2
asynchronous system traps for,
8-7—8-9

documentation, 1-14
double-precision floating (D_) data
type, 4-2

for exceptions and interrupts,
8-3—8-4
interrupt priority levels for, 8-3
processor status and, 8-4—8-7
system control block vectors for,
8-23—8-27