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EK-KXTCA-UG-002

May 1984

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Document:	EK-KXYCA-UG-002 KXT11-CA Single-Board Computer Users Guide 198409
Order Number:	EK-KXTCA-UG
Revision:	002
Pages:	302
Original Filename:	EK-KXYCA-UG-002_KXT11-CA_Single-Board_Computer_Users_Guide_198409.pdf

OCR Text

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KXT11-CA
Single-Board Computer
User's Guide

EK-KXTCA-UG-002

KXT11-CA
Single-Board Computer
User's Guide

Prepared by Educational Services
of
Digital Equipment Corporation

1st Edition, May, 1984
2nd Edition, September 1984

~ Digital Equipment Corporation 1984.

The material in this manual is for informational purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors that may appear in this manual.
The manuscript for this book was created on a DIGITAL Word Processing System and, via a translation
program, was automatically typeset on DIGITAL's DECset Integrated Publishing System. Book production was done by Educational Services Development and Publishing in Marlboro, MA.
The following are trademarks of Digital Equipment Corporation:

mamDDID™

DEC
DECmate
DECsystem-I 0
DECSYSTEM-20
DECUS
DECwriter
DIBOL

MASSBUS
PDP
P/OS
Professional

Q-Bus
Rainbow
.RSTS
RSX

TOPS-10
TOPS-20
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS

Page
PREFACE
CHAPTER 1

INTRODUCTION

I.I
1.2
1.3
1.4
1.4.I
1.4.2
1.5
1.6

INTRODUCTION ..................................................................................................... 1-1
KXTll-CA HARDWARE ........................................................................................ 1-1
KXTl 1-CA FEATURES ........................................................................................... 1-4
KXTI I-CA OPERATING MODES ......................................................................... 1-5
Standalone Mode ................................................................................................ 1-5
Peripheral Processor Mode ................................................................................. 1-5
KXTll-CA SPECIFICATIONS ............................................................................... 1-5
RELATED DOCUMENTS ....................................................................................... 1-7

CHAPTER 2

KXT11-CA SBC ARCHITECTURE

2.1
. 2.2
2.3
2.3.l
2.3.2
2.4
2.5
2.5.1
2.5.2
2.5.2.1
2.5.2.2
2.5.2.3
2.5.3
2.5.3.1
2.5.3.2
2.6
2.7
2.8
2.8.l
2.8.2
2.9
2.9.1

INTRODUCTION ..................................................................................................... 2-1
STANDALONE MODE ........................................................................................... 2-1
STANDALONE HARDWARE ............................................................................... 2-1
Backplane Connections ....................................................................................... 2-1
Power Connections ............................................................................................. 2-1
DMA OPERATIONS ................................................................................................ 2-3
NATIVE FIRMWARE ............................................................................................. 2~3
Selftest/Boot Routines ....................................................................................... 2-3
Start-Up Protocols .............................................................................................. 2-4
Initialization ............................................................................................... 2-4
Selftest. ....................................................................................................... 2-4
Booting ....................................................................................................... 2-4
Communication Protocols .................................................................................. 2-4
1/0 Port Booting ....................................................................................... 2-5
1/0 Port Communications ....................................................................... 2-5
PERIPHERAL PROCESSOR MODE ..................................................................... 2-5
PERIPHERAL PROCESSOR ARBITER ............................................................... 2-5
PERIPHERAL PROCESSOR/IOP HARDWARE ................................................. 2-6
Backplane Connections ....................................................................................... 2-6
Power Connections ............................................................................................. 2-6
NATIVE FIRMWARE ............................................................................................. 2-7
Two-Port RAM (TPR) ...................................................................................... 2-7
DMA Operations ................................................................................................ 2-7
Arbiter to SBC Interrupts .................................................................................. 2-7
KXTl 1-CA SBC to Arbiter Interrupts ............................................................. 2-8

2.9.~

2.9.3
2.9.4

iii

CONTENTS (Cont)
Page
2.9.5

2.9.6
2.9.6.1
2.9.6.2
2.9.6.3
2.9.7
2.9.7.1
2.9.7.2
2.9.7.3
2.9.7.4

Selftest/Boot Switch .......................................................................................... 2-8
Command Protocols ........................................................................................... 2-.8
Start-Up ................................... :................................................................. 2-9
Selftest. ........................................................................................................ 2-9
Boot ............................................................................................................ 2-9
Communication Protocols .................................................................................. 2-9
Two-Port RAM (TPR) .............................................................................. 2-9
DTC Transfers ........................................................................................... 2-9
1/0 Port Booting ....................................................................................... 2-9
1/0 Port Communication ........................................................................ 2-10

CHAPTER 3

THEORY OF OPERATIONS

3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.2
3.2.2.1
3.2.2.2
3.2.,2.3
3.2.2.4
3.2.2.5
3.2.2.6
3.2.2.7
3.2.2.8
3.2.2.9
3.2.3
3.2.3.1
3.2.3.2
3.2.3.3
3.2.3.4
3.2.3.5
3.2.3.6
3.3
3.4
3A.1
3A.2
3.4.3
3.4.4

INTRODUCTION ..................................................... ,............................................... 3-1
MICROPROCESSOR ................................................................................................ 3-4
Microprocessor Initialization .............................................................................. 3-4
Power-Up Input (PUP) .............................................................................. 3-4
Reset Instruction .............................................................................. _.......... 3-6
Microprocessor Control Signals.......................................................................... 3-6
ROW Address Strobe (RAS L) ................................................................ 3-6
Column Address Strobe (CAS L) ............................................................. 3-6
Priority In (PI H) ....................................................................................... 3-6
Read/Write (R/WHB L and R/WLB L) ................................................. 3-6
Select Output Flags (SELO H and SELl H) ............................................ 3-6
Bus Clear (BCLR L) .........................................................•........................ 3-6
Clock Out (COUT H) ............................................................................... 3-6
CLOCK (CLK 142 H) .............................................................................. 3-7
Ready (READY H) .....................................•............................................. 3-7
Microprocessor Transactions .............................................................................. 3-7
Fetch/Read ................................................................................................ 3-7
Write ..............................................................•........................................... 3-8
!AK/Internal/External .............................................................................. 3-9
DMA ........................................................................................................ 3-10
ASPI .......................................................................................................... 3-10
NOP ......................................................................................................... 3-12
MODE REGISTER ................................................................................................. 3-12
CONTROL STATUS REGISTERS (KXTCSR) ................................................... 3-13
KXTCSR A ..................................................................................................... 3-13
KXTCSR B ...................................................................................................... 3-13
KXTCSR C ...................................................................................................... 3-13
KXTCSR D ...................................................................................................... 3-13
SYSTEM CLOCKS ................................................................................................. 3-14
Q-BUS INTERRUPT PROTOCOL CHIP (DC003) ............................................. 3·15
Q-BUS DMA PROTOCOL CHIP (DCOlO) ........................................................... 3-16
Q-BUS INTERFACE GATE ARRAY (DC340) ...................... °'........................... 3-17
Two-Port RAM (TPR) .................................................................................... 3-18
Q-Bus Interrupt Register (QIR) ....................................................................... 3-18
Logic. Sequencer ............................................................................................... 3-19
INTERRUPT CONTROL GATE ARRAY (DC339) ........................................... 3-21

3.5
3.6
3.7
3.8
3.8.1
3.8.2
3.8.3
3.9

CONTENTS (Cont)
Page

3.10
3.10.1
3.10.2
3.10.3
3.10.4
3.10.5
3.10.6
3.10.7
3.10.8
3.11
3.12
3.13
3.14
3.15
3.16
3.16.1
3.16.1.1
3.16.1.2
3.16.1.3
3.16.2
3.16.2.1
3.16.2.2
3.16.2.3
3.16.2.4
3.16.2.5
3.17
3.17.1
3.17.2
3.17.2.1
3.17.2.2
3.18
3.19

INTERRUPT CONTROL ...................................................................................... 3-21
Interrupt Hardware .......................................................................................... 3-21
Ready Logic ..................................................................................................... 3-24
Restart Interrupts ............................................................................................. 3-25
Power-Fail (PFAIL) ......................................................................................... 3-26
External Vector Cycle ...................................................................................... 3-26
Internal Vector Cycle ....................................................................................... 3-27
DMA Request/Grant ....................................................................................... 3-27
End of Pass (EOP) ........................................................................................... 3-27
ADDRESS LATCH ................................................................................................. 3-28
MEMORY DECODE .............................................................................................. 3-28
RAM MEMORY ..................................................................................................... 3-28
USER MEMORY SOCKET SITES ..................................................................... 3-28
NATIVE FIRMWARE SOCKET SITES .............................................................. 3-30
DTC OPERATONS ................................................................................................ 3-30
Flowthrough Transactions ................................................................................ 3-31
Local Transfers ........................................................................................ 3-31
Q-Bus Transfers ....................................................................................... 3-32
I/O Transfers ........................................................................................... 3-32
Exceptions ........................................................................................................ 3-32
Timeout .................................................................................................... 3-32
SBC Mode ................................................................................................ 3-33
Power-Fail ................................................................................................ 3-33
Bus Initiation ............................................................................................ 3-33
Bus Halt ................................................................................................... 3-33
SERIAL 1/0 UNIT ................................................................................................. 3-33
Serial Line Unit 1 (SLUl) ............................................................................... 3-33
Serial Line Unit 2 (SLU2) ............................................................................... 3-34
Channel A ................................................................................................ 3-36
Channel B................................................................................................. 3-36
PARALLEL I/O UNIT ......................................................................................... 3-37
POWER-UP ............................................................................................................. 3-38

CHAPTER 4

NATIVE FIRMWARE

4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4

INTRODUCTION ..................................................................................................... 4-1
NATIVE FIRMWARE ............................................................................................. 4-1
BOOTSTRAP/SELFTEST SEQUENCE ................................................................. 4-3
SBC Set-Up Routine .......................................................................................... 4-3
Initialization ........................................................................................................ 4-3
Battery Backup ................................................................................................... 4-3
Selftests ............................................................................................................... 44
Booting................................................................................................................ 4-4
COMMAND REGISTER .......................................................................................... 4-4
Control Commands ............................................................ :............................... 4-5
Trap Command (Bit 0 Set) ....................................................................... 4-5
DMA Load Command (Bit 1 Set) ............................................................ 4-6
Reinitialization Command (Bit 2 Set) ....................................................... 4-6
Q-Bus ODT Command (Bit 3 Set) ............................................................ 4-6

CONTENTS (Cont)
Page
4.4.1.5
4.4.1.6
4.4.2
4.4.2.1
4.4.2.2
4.4.2.3
4.4.2.4
4.4.2.5
4.4.2.6
4.4.2.7
4.4.2.8
4.4.2.9
4.4.2.10
4.4.2.11
4.4.3
4.4.3.1
4.4.3.2
4.4.3.3
4.4.3.4
4.4.3.5
4.4.3.6
4.5
4.5.1
4.6
4.7
4.8
4.9

Show Command (Bit 4 Set) ...................................................................... 4-6
No Operation Command (Bit 5 Set) ......................................................... 4-6
Selftest Commands............................................................................................. 4-6
CSR Test Command (Bit 0 Set) ............................................................... 4-6
RAM Test Command (Bit 1 Set).............................................................. 4-6
ROM Test Command (Bit 2 Set) .............................................................. 4-6
MPU Test Command (Bit 3 Set) .............................................................. 4-7
BEVNT Test Command (Bit 4 Set) ......................................................... 4-7
SLUl Test Command (Bit 5 Set) ............................................................. 4-7
SLU2 Test Command (Bit 6 Set) ............................................................. 4-7
PIO Test Command (Bit 7 Set) ................................................................ 4-7
DMA Controller Test Command (Bit 8 Set) ............................................ 4-7
QIR Test Command (Bit 9 Set) ................................................................ 4-7
Two-Port RAM (TPR) Test Command (Bit 10 Set).. .4-7
Q-Bus ODT Commands ..................................................................................... 4-7
Open and Examine Memory Command Code .......................................... 4-7
Open and Examine Register Command Code .......................................... 4-7
Deposit Command Code ............................................................................ 4-7
Go Command Code ................................................................................... 4-7
Proceed Command Code ........................................................................... 4-8
Exit Mode Command Code ............................... ~ ....................................... 4-8
SERIAL ODT ............................................................................................................ 4-8
Autobaud ............................................................................................................ 4-9
LED DISPLAY .......................................................................................................... 4-9
MEMORY MAP CONFIGURATION .................................................................. 4-10
RESTART HANDLING ......................................................................................... 4-10
BOOT EXIT ............................................................................................................. 4-11

CHAPTERS

PROGRAMMING INFORMATION

5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.2
5.4.3
5.4.4
5.4.5
5.5
5.5.1
5.5.2

INTRODUCTION ..................................................................................................... 5-1
CONTROL STATUS REGISTERS (KXTCSR) ..................................................... 5-1
KXTCSR A Register .......................................................................................... ·5-1
KXTCSR B Register ......................................................................................... 5-3
KXTCSR C Register ......................................................................................... 5-5
KXTCSR D Register ......................................................................................... 5-6
Q-BUS INTERRUPT REGISTER (QIR) ................................................................ 5-9
TWO-PORT RAM (TPR) ....................................................................................... 5-10
Control Command Register {TPR 0) .............................................................. 5-10
Control Commands .................................................................................. 5-11
Test Commands ......................................................................................... 5-11
ODT Commands ....................................................................................... 5-12
Status Register 1 (TPR 1) ............................................................................... 5-12
Control Register 2 (TPR 2) ............................................................................. 5-14
Control Register 3 (TPR 3) ............................................................................. 5-14
ROM Test Status (Test Code = 03) ................................................................ 5-20
OMA TRANSACTIONS ........................................................................................ 5-20
Master Mode Register (MM) ........................................................................... 5-22
COMMAND Register (CM) ........................................................................... 5-22

CONTENTS (Cont)
Page
5.5.3
5.5.4
5.5.5
5.5.6
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5

Chain Control Register (CC) ........................................................................... 5-24
Temporary Register (TMP) ............................................................................. 5-24
Current Address Registers ............................................................................... 5-24
Special-Purpose Registers ................................................................................. 5-31
ASYNCHRONOUS SERIAL LINE UNIT (SLUl) ............................................. 5-34
Operating Parameters Selection ....................................................................... 5-34
Console Functions............................................................................................. 5-35
Interrupt Vectors/Priorities .............................................................................. 5-35
Address Selection ............................................................................................. 5-35
Register Bit Assignments ................................................................................. 5-35
PARALLEL I/O ...................................................................................................... 5-37
Address Selection ............................................................................................. 5-38
Interrupt Vectors/Priorities .............................................................................. 5-38
Buffers and I/0 Connector .............................................................................. 5-38
Register Assignments ....................................................................................... 5-38
SYNCHRONOUS/ASYNCHRONOUS SERIAL COMMUNICATIONS ........ 5-49
Programmable Baud Rate Generation ............................................................. 5-49
Address Selection ............................................................................................. 5-52
Interrupt Vectors/Priorities .............................................................................. 5-53
I/O Drivers and Receivers ............................................................................... 5-53
Register Bit Assignments (CRO through CR 7; SRO through SR2) ................ 5-53

CHAPTER 6

CONFIGURATION/INSTALLATION/MAINTENANCE

6.1
6.2

INTRODUCTION ..................................................................................................... 6-1
CONFIGURATION/INSTALLATION/
VERIFICATION PROCEDURE .............................................................................. 6-1
SELECTING OPERATING FEATURES ............................................................... 6-5
User EPROM, EEPROM and RAM ................................................................ 6-9
Battery Backup ................................................................................................. 6-11
User Socket +5 V Power ................................................................................. 6-12
Memory Maps .................................................................................................. 6-13
Boot/Selftest Switch ........................................................................................ 6-15
Q-Bus Base Address (ID Switch) ..................................................................... 6-16
Real-Time Clock Interrupt ............................................................................... 6-18
Break Enable .................................................................................................... 6-19
SLUl Transmitter ............................................................................................ 6-20
SLU 1 Receiver ................................................................................................. 6-21
SLUl Baud Rate .............................................................................................. 6-22
DMA Requests ................................................................................................. 6-23
SLU2 Channel A Receiver .............................................................................. 6-24
SLU2 Channel B Operation ............................................................................. 6-25
SLU2 Channel B Receiver ............................................................................... 6-26
SLU2 Channel B Transmitter .......................................................................... 6-27
POWER SUPPLY ................................................................................................... 6-28
BACKPLANE INSTALLATION .......................................................................... 6-28
BACKPLANE PIN IDENTIFICATIONS ............................................................. 6-30
EXTERNAL CABLES.............................................................. ;............................. 6-32
Parallel I/0 Interface (J4) ............................................................................... 6-32

6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.4
6.5
6.6
6.7
6.7.1

CONTENTS (Cont)
Page
6.7.2
6.8
6.9
6.10

Serial 1/0 Interfaces (Jl, 12 and 13) ..................................................... ;........ 6-32
LOOPBACK CONNECTORS ................................................................................ 6-35
KXTl 1-CA SBC DIAGNOSTIC TESTING PROCEDURES .............................. 6-36
ERROR INFORMATION ...................................................................................... 6-37

APPENDIX A

ADDRESSING MODES AND INSTRUCTION SET

A.l
A.2
A.2.1
A.2.2
A.2.3
A.2.3.1
A.2.3.2
A.2.3.3
A.2.3.4
A.2.4
A.2.5
A.2.5.1
A.2.5.2
A.2.5.3
A.2.5.4
A.2.6
A.3
A.3.1
A.3.2
A.3.3
A.3.3.l
A.3.3.2
A.3.3.3
A.3.3.4
A.3.4
A.3.4.1
A.3.4.2
A.3.5
A.3.5.1
A.3.5.2
A.3.5.3
A.3.5.4
A.3.5.5
A.3.5.6
A.3.5.7
A.3.5.8
A.3.5.9
A.3.5.10
A.3.5.11
A.3.6
A.3.7

INTRODUCTION .................................................................................................... A-1
ADDRESSING MODES .......................................................................................... A-1
Single-Operand Addressing ............................................................................... A-3
Double-Operand Addressing .............................................................................. A-3
Direct Addressing .............................................................................................. A-4
Register Mode (Mode 0) .......................................................................... A-6
Autoincrement Mode (Mode 2) ................................................................ A-7
Autodecrement Mode (Mode 4) ............................................................... A-9
Index Mode (Mode 6) ............................................................................. A-11
Deferred (Indirect) Addressing ....................................................................... A-13
Use of the PC as a General-Purpose Register ................................................ A-17
Immediate Mode ..................................................................................... A-18
Absolute Addressing ............................................................................... A-19
Relative Addressing ................................................................................ A-21
Relative Deferred Addressing ................................................................. A-22
Use of the Stack Pointer as a General-Purpose Register ............................... A-22
INSTRUCTION SET ............................................................................................. A-23
Instruction Formats ......................................................................................... A-24
List of Instructions .......................................................................................... A-26
Single Operand Instructions ............................................................................ A-29
General .................................................................................................... A-30
Shifts and Rotates ................................................................................... A-33
Multiple Precision .........................•......................................................... A-38
PS Word Operators ............................................... ;................................ A-41
Double-Operand Instructions ........................................................................... A-42
General .................................................................................................... A-42
Logical ..................................................................................................... A-45
Program Control Instructions .......................................................................... A-47
Branches .................................................................................................. A-47
Signed Conditional Branches.: ................................................................ A-52
Unsigned Conditional Branches .............................................................. A-54
Jump and Subroutine Instructions .......................................................... A-56
Traps ....................................................................................................... A-61
Reserved Instruction Traps ..................................................................... A-65
HALT Interrupt ...................................................................................... A-65
Trace Trap .............................................................................................. A-65
Power-Failure Interrupt .......................................................................... A-65
Interrupts ................................................................................................. A-65
Special Cases {T-bit) ............................................................................... A-66
Miscellaneous Instructions ............................................................................... A-66
Condition Code Operators ............................................................................... A-68

viii

CONTENTS (Cont)

APPENDIX B

PROGRAMMING DIFFERENCES

APPENDIX C

PERFORMANCE PARAMETERS

APPENDIX D

KXTll-CA SBC SCHEMATIC DRAWINGS

APPENDIX E

ADDRESS ENVIRONMENT

APPENDIX F

LOOPBACK CONNECTORS

APPENDIX G

GLOSSARY

FIGURES
Figure No.
1-I
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-1
3-I
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-I I
3-12
3-13

3-14
3-15
3-16
3-17
3-I8
3-19
3-20

Title

Page

KXTl 1-CA SBC Layout ............................................................................................ 1-2
KXT I 1-CA SBC Simplified Block Diagram ............................................................. 1-3
Simplified KXTI 1-CA SBC Block Diagram, Standalone Mode ............................... 2-2
KXTl 1-CA SBC Native Firmware ........................................................................... 2-3
Start-Up Protocol Flow Diagram ............................................................................... 2-4
1/0 Port Boot Path .................................................................................................... 2-5
Peripheral Processor/IOP Interface ........................................................................... 2-6
Bus Arbiter to KXTl I-CA SBC Interrupt Cycle ...................................................... 2-7
.KXTl I-CA SBC to Bus Arbiter Interrupt Cycle ...................................................... 2-8
KXTl 1-CA SBC Functional Block Diagram (Sheet 1)............................................. 3-2
KXTl 1-CA SBC Functional Block Diagram (Sheet 2) ............................................. 3-3
KXTl I-CA SBC Functional Block Diagram (Sheet 3)............................................. 3-4
DCTl 1-AA Microprocessor ....................................................................................... 3-5
Read/Fetch Transaction ............................................................................................. 3-8
Write Transaction ....................................................................................................... 3-9
IAK Transaction ....................................................................................................... 3-10
OMA Transaction ..................................................................................................... 3-11
ASPI Transaction ...................................................................................................... 3-11
NOP Transaction ...................................................................................................... 3-I2
Mode Control Register ............................................................................................. 3- I 3
28-MHz System Clocks ............................................................................................ 3-14
19 .066-MHz System Clock ...................................................................................... 3- I 5
Q-Bus Interrupt Chip (DC003) ................................................................................ 3-15
Q-Bus OMA Protocol (DCOIO) ................................................................................ 3-I6
Q-Bus Interface Date Array Simplified Block Diagram (DC340) .......................... 3-17
TPR and Logic Simplified Block Diagram .............................................................. 3-17
Q-Bus Vector Interrupt Register ............................................................. , ................ 3-19
Logic Sequencer Functional Diagram ...................................................................... 3-20
Interrupt Control Signals .......................................................................................... 3-21
Interrupt Control Simplified Block .......................................................................... 3-22
READY Logic .......................................................................................................... 3-24

FIGURES (Cont)
Figure No.
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12

5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32

Title

Page

Restart Interrupts ..................................................................................................... 3-25
Power-Fail Interrupt ................................................................................................. 3-26
End of Pass (EOP) Logic ......................................................................................... 3-27
RAM Logic ................................................................................................................ 3-29
User Socket Sites ...................................................................................................... 3-29
Native Firmware Socket Sites ................................................................................... 3-30
DTC Control Signals ................................................................................................ 3-31
Local OMA Control Signals ..................................................................................... 3-31
Q-Bus DMA Control Signals ..................................................................................... 3-32
SLUl Transmit/Receive Configuration ................................................................... 3-33
SLU2 Channel A Receiver....................................................................................... 3-34
SLU2 Channel B Transmitter/Receiver .................................................................. 3-35
Parallel 1/0 (PIO) Port Configuration..................................................................... 3-37
Power-Up (PUP) Logic ............................................................................................ 3-38.
Memory Configuration Showing Native Firmware ................................................... 4-2
KXTl 1-CA SBC Power-Up Sequence ....................................................................... 4-3
Two-Port RAM (TPR) ................................................................................................ 4-5
KXTCSR A Register ................................................................................................. 5-1
KXTCSR B Register .................................................................................................. 5-3
KXTCSR C R~gister ................................................................................................. 5-5
KXTCSR D Register ................................................................................................. 5-6
Q-Bus Interrupt Register (QIR) ................................................... ,............................. 5-9
16-Bit X 16-Word Two-Port Ram (TPR) ................................................................ 5-10
TPR Control Command Register 0 ......................................................................... 5-11
Test Command Register ........................................................................................... 5-11
TPR Status Register 1 ............................................................................................. 5-12
TPR Control Register 2 ........................................................................................... 5-15
TPR Control Register 3 ........................................................................................... 5-15
DTC Master Mode Register ..................................................................................... 5-22
Address Registers A and B ...................................................................................... 5-25
DTC Internal Register .............................................................................................. 5-14
Chain Address Register ............................................................................................ 5-28
Status Register ........................................................................................................... 5-28
Interrupt Save Register ............................................................................................ 5-29
Interrupt Vector Register ......................................................................................... 5-31
Channel Mode Register ............................................................................................ 5-31
RCSR Register ......................................................................................................... 5-36
RBUF Register ......................................................................................................... 5-36
SCSR Register .......................................................................................................... 5-36
XBUF Register ......................................................................................................... 5-36
Pulse Output Mode Operation ................................................................................. 5-37
One-Shot Mode Operation........................................................................................ 5-37
1/0 Buffer Control Register .................................................................................... 5-38
Master Interrupt Control Register ........................................................................... 5-41
Master Configuration Control Register .................................................................... 5-41
Port Mode Specification Register ............................................................................ 5-42
Port Handshake Specification Register .................................................................... 5-42
Port Command and Status Register ........................................................................ 5-43
Data Path Polarity Register ..................................................................................... 5-44

FIGURES (Cont)
Figure No.
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5~51

5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
5-60
5-61
5-62
5-63
5-64
5-65
5-66
5-67
5-68
5-69
5-70
5-71
5-72
5-73
5-74
6-1
6-2
6-3
6-4
6-5
6-6

Title

Page

Data Direction Register ............................................................................................ 5-44
Special 1/0 Control Register ................................................................................... 5-44
Port A, Port B Data Register .................................................................................. 5-44
Port C Data Register ................................................................................................ 5-45
Pattern Polarity Register .......................................................................................... 5-45
Pattern Transition Register .................................................................•.................... 5-45
Pattern Mask Register .............................................................................................. 5-46
Counter/Timer Mode Specification Register ........................................................... 5-46
Counter/Timer Command and Status Register ....................................................... 5-46
Counter/Timer Time Constant Register .................................................................. 5-4 7
Counter/Timer Current Count Register .................................................................. 5-4 7
Port A and B Interrupt Vector Register .................................................................. 5-48
Counter/Timer Interrupt Vector Register ............................................................... 5-48
Current Vector Register ........................................................................................... 5-48
Timer Control Register ............................................................................................ 5-50
Counter Latch Register ............................................................................................ 5-51
Current Counter Value Register ............................................................................... 5-51
Counter Status Register ........................................................................................... 5-52
Command Control and Pointer Control Register (CRO) ......................................... 5-53
Interrupt Control Register (CRl) ............................................................................ 5-55
Processor/Bus Interface Control Register (CR2) .................................................... 5-55
Receiver Control Register (CR3) ............................................................................. 5-56
Mode Control Register (CR4) .................................................................................. 5-56
Transmitter Control Register (CR5) ........................................................................ 5-57
Sync/Address Character Register (CR6) ................................................................ 5-58
Sync Character Register (CR7) ............................................................................... 5-58
Buffer and (External/Status) Status Register (SRO) ............................................... 5-59
Received Character Error and Special Condition Status Register (SRI) ............... 5-59
Receiver Data Buffer Register ................................................................................. 5-59
Transmit Data Buffer Register ................................................................................ 5-59
Interrupt Vector Status Register (SR2) ................................................................... 5-60
Command Control and Pointer Control Register (CRO) ......................................... 5-60
Interrupt Control Register (CRl) ............................................................................ 5-61
Receiver Control Register ........................................................................................ 5-62
Mode Control Register ............................................................................................. 5-63
Transmitter Control Register ................................................................................... 5-64
Sync/Address Character Register ............................................................................ 5-65
Sync Character Register ........................................................................................... 5-65
Buffer and (External Status) Status Register .......................................................... 5-65
Received Character Error and Special Condition Status Register .......................... 5-65
Receiver Data Buffer Register .........................................................•....................... 5-66
Transmit Data Buffer Register ................................................................................ 5-66
KXTll-CA SBC Configuration/Installation/Verification Procedure Flow Diagram
(Sheet 1 of 3) ............................................................................................................ :. 6-2
KXTl 1-CA SBC Operating Features Flow Diagram ................................................ 6-5
KXTl 1-CA SBC Jumper Layout .............................................................................. 6-6
User EPROM and RAM Jumper Configurations ..................................................... 6-9
User Socket Sites ........................................................................................................ 6-9
Battery Backup Selection ......................................................................................... 6-11

FIGURES (Cont)
Figure No.
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-lS
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-2S
6-26
6-27
A-1
A-2
A-3
A-4
A-S
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
A-lS
A-16
A-17
A-18
A-19
A-20
A-21
A-22
A-23
A-24
A-25
A-26
A-27
A-28

Title

Page

User Socket +S V Power ..................,. ........................................ ;............................. 6-12
Memory Map Configurations ......................... .-......................................................... 6-13
Memory Maps .......................................................................................................... 6-14
Boot/Selftest Switch ................................................................................................. 6-1 S
Q-Bus Base Address Configurations ......................................................................... 6-17
Real-Time Clock Interrupt ........................................ :.............................................. 6-18
Break Enable ............................................................................................................ 6-19
SLUl Transmitter .................................................................................................... 6-20
SLUl Receiver ......................................................................................................... 6-21
SLUl Baud Rate ................................. , .................................................................... 6-22
OMA Requests ........................................................ , ................................................ 6-23
SLU2 Channel A Receiver ...................... ;................................................................ 6-24
SLU2 Channel B Operation ..................................................................................... 6-2S
SLU2 Channel B Receiver ....................................................................................... 6-26
SLU2 Channel B Transmitter ....................................... :.......................................... 6-27
Q/Q22-CD Backplane Assembly ............................................................................. 6-29
Q/Q22-Q/Q22 Backplane Assembly with Grant Card ........................................... 6-29
PIO Connector Pin Assignments .............................................................................. 6~32
SLU2 Connector (Jl) Pin Assignments ................................................................... 6-33
·Loopback Connectors ............................................................................................... 6-3S
LED Error Display ................................................................................................... 6-37
Single-Operand Addressing ..................: ............................................. ,....................... A-3
Double-Operand Addressing .................................... :................................................. A-3
Mode 0 Register ........................................................................................................ A-S
Mode 2 Autoincrement ............................................................................................. A-S
Mode 4 Autodecrement ............... :................................. ;........................................... A-S
Mode 6 Index .............................................................................................................. A-S
INC R3 ...................................................................................................................... A-6
ADD R2, R4 .............................................................................................................. A-7
COMB R4 .............................................................. ;.................................................. A-7
CLR (RS)+ ................................................................................................................ A-8
CLRB (RS)+ ........................................................................................ ;..................... A-8
ADD (R2)+, R4 ....................................... ;................................................................ A-9
INC -(RO) ................................................................................................................ A-10·
INCB -(RO) ............................................................................................................ A-10
ADD -(R3), RO ...................................................................................................... A·l l
CLR 200 (R4) ............................................................................................ ;............ A-12
COMB 200 {Rl) ....................................................... ;.............................................. A-12
ADD 30 (42), 20(R5) ........................ '. ..................................................................... A-13
Mode 1 Register Deferred ....................................................................................... A-14
Mode 3 Autoincrement Deferred ....... ;.................................................................... A-14
Mode S Autodecrement Deferred ................................................ ;.......................... A-14
Mode 7 Index Preferred .......................................................................................... A-lS
CLR @RS ................................................................................................................ A-lS
INC @ (R2)+ .................... :....................................... ;............................................. A-16
COMM@ - (RO) ................................................................................................... A-16
ADD@ 1000 (R2), Rl ... ;....................................................................................... A-17
' ' ;........................................ A-19
ADD # 1O; RO ................. ,;; .............................................
CLR @ # 1100 ....................................·......................................... :.......................... A-20

XII

FIGURES (Cont)
Page

Figure No.
A-29
A-30
A-31
A-32
A-33
A-34
F-1
F-2
F-3

ADD @ # 2000, R3 ................................................................................................ A-20
INC A ...................................................................................................................... A-21
CLR@A ................................................................................................................ A-22
Byte Instructions ...................................................................................................... A-26
Multiple Precision .................................................................................................... A-38
JSR Example ........................................................................................................... A-59
IO-Pin Loopback Connector (J2 and 13) ................................................................... F-l
40-Pin Loopback Connector (Jl) ............................................................................... F-2
40-Pin Loopback Connector (J4) ............................................................................... F-3

TABLES
Table No.
1-1
3-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9

5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
6-1
6-2
6-3
6-4
6-5

Title

Page

Related Documentation .............................................................................................. 1-7
Designated Interrupts ................................................................................................ 3-23
KXTCSR A Bit Description ...................................................................................... 5-2
KXTCSR B Bit Description ....................................................................................... 5-4
KXTCSR C Bit Description ....................................................................................... 5-5
KXTCSR D Bit Description ...................................................................................... 5-6
Power-Up Test Status ............................................................................................... 5-14
CSR Test Status (Test Code= 01) ......................................................................... 5-15
RAM Test Status (Test Code= 02) ........................................................................ 5-16
CPU Test Status (Test Code= 04) ......................................................................... 5-16
BEVNT Test Status (Test Code= 05) .................................................................... 5-16
SLUl Test Status (Test Code= 06) ........................................................................ 5-17
SLU2 Test Status (Test Code = 07) ........................................................................ 5-17
Parallel 1/0 Test Status (Test Code = 10) .............................................................. 5-18
OMA Test Status {Test Code= 11) ........................................................................ 5-18
Q-Bus Interrupt Register Test Status (Test Code= 12) ......................................... 5-19
Two-Port RAM (TPR) Test Status (Test Code= 13) ............................................ 5-19
OTC Internal Registers ............................................................,................................ 5-20
Command Register Operation Code .................................................................. ~····· 5-23
OTC Transfers .......................................................................................................... 5-32
Local I/O RegiSter ,Address ............................................................................... ~ ..... 5-34
Parallel Port Registers .............................................................................................. 5-39
I/O Buffer Control Register Bit Description ........................................................... 5-40
Actual Synchronous 'Bit Rate ................................................................................... 5-49
Actual Synchronous Baud Rate ............................................................................... 5-50
Timer (8254-2) Addressable Registers ..................................................................... 5-52
SLU2 Controller Addressable Registers .................................................................. 5-53
Functional Jumper Pin Definition .............................................................................. 6-7
Factory Shipped Jumper Configuration ..................................................................... 6-8
EPROM Configuration ............................................................................................. 6-10
RAM Configurations ................. :.............................................................................. 6-10
Memory Map Jumper Configurations ...................................................................... 6-13

xiii

TABLES (Cont)
Figure No.

6-6
6-7
6-8

6-9
6-10
A-1
A-2
A-3
A-4
A-5
B-1
C-1

E-1

Title

Page

Boot/Selftest Switch Functions ................................................................................ 6-15
Q-Bus Base Address Configurations ......................................................................... 6-17
SLUl Baud Rate ...................................................................................................... 6-22
KXTl 1-CA Backplane Pin Identification ................................................................ 6-30
Compatible 1/0 Signal Names ................................................................................ 6-34
Sample KXTl 1-CA Instructions ............................................................................... A-4
Direct Addressing Modes .......................................................................................... A-4
Indirect Addressing Modes ...................................................................................... A-14
PC Register Addressing Modes ............................................................................... A-18
KXTl 1-CA Instruction Set ..................................................................................... A-27
KXTl 1-CA, LSI-11/2, and LSI-11/23 Comparisons ............................................... B-1
Instruction Timing .................................................................................................... ,. C-2
KXTl 1-CA Address Assignments ............................................................................. E-2

xiv

PREFACE

This user's guide is intended for hardware, software, and field engineers as an aid in the application/use,
programming, and maintenance of the KXTl 1-CA single board computer (SBC). KXTl I-CA SBC users
should be familiar with Digital's Q-Bus family of products, the PDP-11 instruction set, general
microprocessor operations, and microcomputer system applications.
GUIDE STRUCTURE
Chapter l provides a brief description of the KXT 11-CA SBC, a list of features, and a simplified block
diagram with description.
Chapter 2 supplies an overview of the two operating modes and discusses the hardware and firmware
associated with each. Included is the 22-bit address/16-bit data Q-Bus interface block diagram.
Chapter 3 provides detailed functional descriptions of the KXT I l -CA SBC operations with timing
diagrams and a detailed functional block diagram.
Chapter 4 details the macro-ODT, bootstrap, and selftest routines performed by the native firmware of the
KXTI I-CA SBC and how each routine is implemented.
Chapter 5 describes all the software programmable registers located on the KXTI I-CA SBC and the
register contents after initialization.
Chapter 6 describes how to configure, install, and maintain the KXTI 1-CA SBC. Details include operational features, external cable connections, and maintenance verification procedures.
Appendix A lists the PDP-11 instruction set and general addressing modes.
Appendix Bis a list comparing KXTI 1-CA SBC operations with Digital's other Q-Bus family members.
Appendix C lists the performance parameters of the on-board T-11 microprocessor (CPU) for the entire
instruction set.
Appendix D includes a complete set of KXTI 1-CA SBC schematic drawings.
Appendix E provides a listing of the KXTl 1-CA address environment.
f\ppendix F provides details on constructing the four 1/0 loopback connectors.
Appendix G is a glossary of terms used in this guide.
The Index is an alphabetical listing of the guide's content.

CHAPTER 1
INTRODUCTION

1.1 INTRODUCTION
The KXTll-CA (M8377) single-board computer (SBC) is shown in Figure 1-1. It is a quad-height,
extended-length, single-width board that executes the PDP-11 instruction set (see Appendix A). The
KXTl 1-CA SBC operates as a peripheral processor, or a standalone single-board computer. In addition,
the KXTl 1-CA SBC supports the complete Q-Bus extended bus interface as a bus slave and a DMA
master. This enables the KXTl I-CA SBC to communicate with most of Digital's large family of modules
(see Chapter 3) described in the Microcomputer Interfaces Handbook and the Microcomputers and
Memories Handbook.
1.2 KXTll-CA HARDWARE
The KXTl I-CA simplified functional block diagram (Figure I-2) provides an overview of the board's
functions and how they are related. The KXTll-CA SBC has a 16-bit microprocessor interconnected to
the following.
•

Three serial 1/0 ports

•

One 20-line parallel 1/0 port

•

A two-channel 16-bit DMA transfer controller (DTC).

•

Three programmable timers

•

Local status/control registers

•

A memory consisting of RAM, user socket sites, and native PROM firmware via the local 16bit address/data bus lines

The internal bus operates as either a 16-bit or an 8-bit bus.

1-1

2 ... 101
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..------. .
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MR-12023

Figure 1-1

KXTl 1-CA SBC Layout

PROGRAMMABLE
TIMERS

Tl 1
MICROPROCESSOR
USER
SOCKETS
SITES

RAM

NATIVE
PROM

SELF-TEST/
BOOT
SWITCH

SYNC/ASYNC
DATA AND
TIMING

LOCAL BUS
______,

--~~~---~~~----~~~~~~--.

CONTROLLER)11--~--.--~--.

L_s~2

EIA
BUFFERS
CHAN A

SYNC/ASYNC
MODEM
CONTROL

(16 POSITIONS)

DTC
(DMA
TRANSFER

- ~

Jl
EIA

BUFFERS
CHAN 8
•

_ _J
EIA
BUFFERS

CONTROL
STATUS
REGISTERS

LSl-11 BUS
INTERFACE

SLU 1
J3

1/0
(CONSOLE)
IEEE
BUFFERS

22 ADDRESS I 16 DATA
SBC
ID SWITCH
(16 POSITIONS)

PARALLEL
1/0 AND
I•
2 TIMERS

•I

MR-10760

Figure 1-2

KXTl 1-CA SBC Simplified Block Diagram

1.3 KXTtt-CA FEATURES
The features of the KXTll-CA SBC include the following.

•

T-11 16-bit microprocessor emulating the PDP-11 instruction set
Direct addressing of 64 K bytes

•

Local memory
On-board 32 Kb of static read/write memory {RAM)
Sockets for up to 32 Kb of additional PROM or static RAM.
8 Kb of native firmware

•

Q-Bus extended bus interface
A 16-word, two-port register file (TPR)
A local-to-Q-Bus interrupt mechanism.

•

A direct transfer controller (DTC) for memory or 1/0 data transfers
Local-to-local
Local-to-Q-Bus
Q-Bus-to-local
Q-Bus-to-Q-Bus

•

Four local registers for status and control
Four programmable LED indicators for diagnostic fault isolation
Selftest mode switch

•

One asynchronous serial (console) 1/0 line unit
EIA RS-422/RS-423/RS-232 compatible
Px<:>grammable baud rates of 300 to 38,400 bits/baud

•

One synchronous/asynchronous serial line unit
Full modem support
RS-449 (CCITT V.24) type SR (send-receive)
EIA RS-422/EIA RS-232C compatible
Programmable baud rates of 110 to 56,000 bits/baud

•

One asynchronous secondary channel
RS-449 (CCITT V.24) type DT (data and timing only)
EIA RS-423/RS-422 compatible
Asynchronous 32-node party line electrical interface
Programmable baud rates of 110 to 56,000 bits/baud

•

Three programmable timers/counters for serial communications

•

One parallel 1/0 interface
Two bidirectional 8-bit input/output ports
One 4-bit control port
Three 16-bit programmable interval timers/counters
IEEE 488 Electrical Interface compliance
1-4

1.4 KXTtl-CA OPERATING MODES
The KXTI 1-CA SBC can be operated in either of two modes: standalone or peripheral processor. A
general description of both operating modes is included in the following sections.
1.4.1 Standalone Mode
In the standalone mode, the KXT 11-CA SBC can be used as a dedicated controller or general-purpose
microcomputer. When physically connected to the Q-Bus via its backplane, the KXTl 1-CA SBC's local
address/data bus is isolated from the Q address/data bus. However, the power supply and ground signals
can be supplied by the Q-Bus. If the KXTl 1-CA SBC is not connected to a Q-Bus, power and ground
signals must be externally supplied.
All communications between local and global addresses are done via one of the four communication 1/0
ports.
1.4.2 Peripheral Processor Mode
As in the general-purpose, single-board computer operation, the microprocessor, DTC, and 1/0 port
operations are identical. In addition, the KXTl 1-CA SBC is capable of interfacing with Digital's Q-Bus
(22-bit address) via backplane connections. The Q-Bus interface allows the existing system to off-load
some work onto a maximum of 14 KXTll-CA SBCs.
Q-Bus interfacing is provided by KXTll-CA hardware, firmware, and software. The Q-Bus interface
allows the internal SBC's multiplexed address/data bus access, via the external Q-Bus 22-bit memory
space, to the direct transfer controller (DTC) interface for moving data parameters. The bus master
(arbiter) uses the Q-Bus to transmit commands, receive status, and transfer blocks of control data to the
16-word, two-port register file.(TPR). In addition, the KXTl 1-CA SBC includes Q-Bus interrupt hardware for signaling the Q-Bus arbiter. The interrupt is initiated when service by the existing system is
required.

In the peripheral processing mode, DTC operations are not limited to transferring data between local 16bit addresses. Transferring of data also occurs between the following.
•
•
•

A local 16-bit address and a 22-bit Q-Bus address
A 22-bit Q-Bus LSI address and a 16-bit local address
Two 22-bit Q-Bus addresses

The DTC transfers data using flowthrough operations allowing up to 64 Kb to be transferred during one
DMA operation.
1.5

KXTl 1-CA SPECIFICATIONS

Physical
Height (quad)

26.6 cm (10.5 in)

Length (dual)

22.8 cm (8.9 in)
(includes module handle)

Width (single)

1.27 cm (0.5 in)

Weight

665 g (22 oz) maximum

1-5

Power Requirements
Power Supply
+5 v ± 5%

3.5 A (typical), 4 A (maximum)

+12 v ± 5%

60 mA (typical) used by on-board circuitry; 2 A (maximum)
includes current provided to outside interface through pin 10
of the serial 1/0 connector for operating the DLV 11-KA
EIA-20 mA converter option.
NOTE
The +12 V typical current is measured with no connections at pin 10 of the serial 1/0 connector (fused
line).

Battery Backup
+5 v ± 5%

12 mA (typical), 20 mA (maximum)

Bus Loading
AC loads
DC loads
PIO
EIA

2.7
1.0

Environmental
Temperature
Storage
Operating

-40°C to 66°C (-40°F to 150°F)
5°C to 60°C ( 41°F to 140°F)

NOTE
The module must be brought into the operating temperature environment and allowed to stabilize for
five minutes before operating.
Relative Humidity
Storage
Operating

10% to 95% (no condensation)
10% to 95% (no condensation)

Altitude
Storage
Operating

Up to 15 km (50,000 ft)
Up to 15 km (50,000 ft)
(90 mm mercury minimum)

NOTE
Lower the maximum operating temperature by 1°C
(1.8°F) for each 300 m (1,000 ft) of altitude above
2.4 km (8,000 ft).
1-6

Air quality

Air must be noncaustic.

Airflow (operating)

There must be enough airflow to limit the input to output temperature rise across the module to S°C (9°F) when the input temperature is 60°C (140°F). For operation below SS°C (131°F), there
must be enough airflow to limit the input to output temperature
rise across the module to l 0°C ( l 8°F) maximum.

1.6 RELATED DOCUMENTS
This user's guide is the primary reference document for the KXTl 1-CA SBC. Important information
about other Q-Bus-compatible products may be found in the publications listed in Table 1-1.
Table 1-1

Related Documentation

Title

Document Number

Microcomputers and Memories Handbook
Microcomputer Interfaces Handbook
PDP-11 Architecture Handbook
Chipkit Users Manual
µ/Tl 1 User's Guide
TU58 Technical Manual
KXTl 1-CA ROM Listing

EB-20912-20
EB-23144-18
EB-23657-18
EJ-1747S
EK-DCTl 1-UG
EK-OTUS8-TM
EK-KXTCA-HR

These documents can be ordered from:
Digital Equipment Corporation
Accessories and Supplies Group
Cotton Road
Nashua, NH 03060
Attention: Documentation Products
Telephone: 1-800-2S8-1710
Additional Documents
For backup information involving chip-level detail, the following publications can be ordered.

Z8036 Counter/Timer and Parallel 1/0 Unit, 1982 Edition
Z8016 DMA Controller, 1982 Edition
Zilog
131S Dell Ave.
Campbell, CA 9S008
Attention: Corporate Publications

µPD7201 Technical Manual, 1981 Edition
NEC Electronics, Inc.
One Natick Executive Park
Natick, MA 01760
Attention: Corporate Publications

1-7

CHAPTER 2
KXTll-CA SBC ARCHITECTURE

2.1 INTRODUCTION
The KXTl 1-CA SBC architecture enables the KXTl 1-CA SBC to be configured in either of two basic
modes: standalone or peripheral processor. An ID switch, mounted on the SBC's edge, enables operating
mode selection according to the user's application. This chapter describes how each mode is used and what
portion of the SBC's native firmware is implemented. In addition, the protocols invoked by the native
firmware for each mode are discussed.
2.2 STANDALONE MODE
The KXTl 1-CA SBC contains all the necessary hardware and native firmware needed to operate as a
complete standalone single-board microcomputer. In the standalone mode the KXTl 1-CA SBC can be
used for dedicated computer tasks, operating completely independent of any Q-Bus signals.
2.3 STANDALONE HARDWARE
The KXTll-CA SBC hardware includes the following.
•
•
•
•
•
•
•
•
•

A CPU for instruction manipulations
RAM for temporary data storage
ROM for execution of on-board selftest/boot/ODT (octal debugging technique) routines
User socket sites for executing application code
Direct transfer controller (OTC) for executing OMA transfers
Control and status registers for system operations
ID switch for selecting operating mode
Selftest/boot switch for selecting selftest/boot routines
Four I/O ports for communications with a variety of I/O devices

See Figure 2-1 for the simplified KCTll-CA SBC hardware block diagram.
2.3.1 Backplane Connections
The KXTl 1-CA SBC can be operated in the standalone mode while physically connected, via the
backplane connections, to the Q-Bus. In the standalone mode the KXTl 1-CA SBC bus transceivers are
disabled, inhibiting any local references from the Q-Bus to be detected and local references to the Q-Bus to
be aborted. Since references between local and Q-Bus spaces are electrically isolated, the KXTl 1-CA SBC
can operate completely independent of any Q-Bus signals.
2.3.2 Power Connections
In the standalone mode, when the KXTl 1-CA SBC is physically connected to an Q-Bus, the +5 Vdc, +12
Vdc and system ground can be received either from the Q-Bus or from an external source. If the KXTl 1CA SBC is not physically connected to the Q-Bus, the +5 Vdc, +12 Vdc, and system ground must be
externally supplied. In addition, the on-board RAM (if installed in user sockets) can be backed up by
battery by supplying a minimum of +2 Vdc either externally or via the Q-Bus. See Paragraph 1.5 for the
battery back-up voltage specifications.

2-1

-PROGRAMMABLE
TIMERS

T11
MICROPROCESSOR
RAM

USER
SOCKETS
SITES

NATIVE
PROM

SELF-TEST/
BOOT
SWITCH

SYNC/ASYNC
MODEM
CONTROL

(16 POSITIONS)

DTC
(DMA
TRANSFER
CONTROLLER)

LOCAL TOAL BUS

SYNC/ASYNC
DATA AND
TIMING

L_s~2 _

EIA
BUFFERS

I
I

CHAN A

EIA
BUFFERS

I - I CHAN B

N
I
N

EIA
BUFFERS
CONTROL
STATUS
REGISTERS

SLU 1

1/0
(CONSOLE)

_,
IEEE
BUFFERS

PARALLEL
1/0 AND
I•
2TIMERS

20
•'

•I

MR-11892

Figure 2-1

Simplified KXTI 1-CA SBC Block Diagram, Standalone Mode

2.4 DMA OPERA TIO NS
The direct transfer controller (OTC) is a two-channel controller capable of transferring large blocks of
data (up to 64 Kb), using a OMA operation, with minimal microprocessor involvement. All OMA
transfers are initiated locally by the T-11 microprocessor. OMA transfers can occur between I 6-bit local
addresses and support hardware requests from the two-channel synchronous/asynchronous 1/0 port
controller or the parallel 1/0 port controller. OMA operations can be interleaved between the DTC's two
channels, between one channel and the local processor, or occur in various bursts.
These transfers are performed in a two-step sequence called flowthrough transactions, where a source is
read and a destination is written. Flowthrough transactions can occur between all local memory combinations. The data is temporarily held in OTC registers between the source and destination portions of the
transfers. On the next local bus cycle, the OTC reads the source and temporarily stores the data. During
the following local bus cycle, the destination is written and the data is transferred to the destination.
2.5 NATIVE FIRMWARE
The KXTI I-CA SBC contains all the necessary native firmware for controlling on-board basic operations.
These include selftest/boot/ODT codes for implementing the start-up and communications protocols. All
KXTI I-CA SBC registers are accessed using a 16-bit even boundary octal address. Data information can
be in either 16-bit word or 8-bit byte format. Refer to Figure 2-2 for the KXTI I-CA native firmware
chart.

NATIVE FIRMWARE

COMMAND
PROTOCOLS

INITIALIZATION

SELF-TEST

COMMUNICATION
PROTOCOLS
I

BOOTSTRAP

Figure 2-2

APPLICATION

TPR

DMA

FOUR 1/0 PORTS

KXTI I-CA SBC Native Firmware

2.5.1 Selftest/Boot Routines
Selftest/boot routines are selected via the hardware selftest/boot switch. The native firmware provides
three selectable functions as follows.
1.

The user can select one of three selftest functions. One function disables the selftests; the second
performs a normal selftest; and the third performs selftests repeatedly.

If the user's application program is stored in an off-board 1/0 device, any one of the four 1/0
ports can be selected as the communication path for booting the application program into the
local RAM space.

The user's application program can be booted from two possible memory sources. One memory
source is located in a section of the user's PROM, and the other memory source is located offboard in an 1/0 device.

2-3

2.5.2 Start-Up Protocols
The start-up protocols are a subset of the ODT command protocols. Start-up protocols cover three
separate SBC operations: initialization, selftest and bootstrap. Each step in these operations is followed to
ensure proper operating procedures. The start-up protocols (Figure 2-3) are software implemented through
the native firmware.

BOOT SWITCH

POWER-UP MODULE

MODULE INITIALIZATION

SELF TEST ROUTINE

BOOTSTRAP ROUTINE

ODT RUN

APPLICATION CODE RUN
MR-10762

Figure 2-3

Start-Up Protocol Flow Diagram

2.5.2.1 Initialization - Before power is applied to the KXTl 1-CA SBC, the selftest/boot routines are
selected via the selftest/boot switch. During power-up, the T-11 initializes all on-board chips according to
the native firmware ROM. This includes clearing some registers and writing into others.
2.5.2.2 Selftest - After the KXTl 1-CA SBC is initialized, the native firmware performs the selected
selftest routines. The selftest routine invoked is dependent on the selftest/boot switch position. These
routines verify proper operations of many on-board SBC functions. Selftest routines can be performed as a
portion of the power-up procedure or can be implemented by native firmware directives.
Selftest routines check for two types of errors: nonfatal and fatal. For nonfatal errors the boot routine
continues and the LEDs display the error encountered , after booting SBC operations are halted. When a
fatal error is detected, the boot routine is immediately stopped with the LEDs displaying the error
encountered. Refer to Chapter 6 for detailed LED error information.
2.5.2.3 Boot - If the selftest routine is passed, a boot routine is initiated by the firmware according to the
selftest/boot switch selection. The application software code is then booted into local RAM space. The
boot routine is done via a preselected 1/0 port. Once the boot routine is complete, control of KXTl 1-CA
SBC is transferred to application software. The native firmware supports system level exception handling
while thtl application program is running.
2.5.3 Communication Protocols
In the standalone mode communication protocols exist for all four 1/0 ports. Two protocols are used: one
during boot routines and the other during the running of the application program. Three serial 1/0 ports
are available for boot routines and all four 1/0 ports are available for communications during the running
of application programs.

2-4

2.5.3.1 1/0 Port Booting - The KXT 11-CA SBC firmware supports communications for primary
bootstrap routines to load the application program into local RAM space. Any one of the three serial 1/0
ports can be used for this purpose - the asynchronous SLU 1 (serial line unit) or either of the two SLU2
channels (A and B).
SLU I can be used to load the application program from the off-board TU58 I/O device. The TU58 is a
mass storage cassette tape device that can be used to store and down-line-load user application programs.
To ensure proper operation between the TU58 and the KXTl 1-CA SBC, both baud rates must match. See
the TU58 Technical Manual for baud rate details. Also, refer to Paragraph 6.3.11 in this user guide for
SLU 1 baud rate details.
SLU2 can be used to boot the application program in either asynchronous or synchronous mode. The
controller for SLU2 consists of a two-channel device, channels 1 and 2. Both channels are separate I/O
ports and can be used for either asynchronous or synchronous communications. The necessary firmware
for using SLUl or 2 as communication I/O ports during boot routines is supported by the local ROM and
is implemented through the selftest/boot select switch. Figure 2-4 shows the I/O port boot path.

RAM

SLU 1

TU58

INTERNAL
LOCAL BUS

MR-10763

Figure 2-4

1/0 Port Boot Path

2.5.3.2 I/O Port Communications - After the application program is booted into local RAM space,
communications via one of four 1/0 ports is supported and controlled by the application program. The
user's application program must contain the necessary code to implement communications via the selected
1/0 port. Since the T-11 microprocessor is interrupt driven, the KXT 11-CA SBC can support simultaneous communications via all four I/O ports. This means that each time data is received by an I/0 port, an
interrupt to the T-11 is generated. Servicing of these bus interrupts is on a priority basis.
2.6 PERIPHERAL PROCESSOR MODE
The KXTll-CA SBC uses the same hardware circuits and performs all of the operations as in the
standalone mode. Some additional hardware circuitry is used to interface the KXTl 1-CA SBC to the
Q-Bus extended bus. This hardware enables the KXTl 1-CA SBC to operate as a peripheral processor or
an intelligent processor on Digital's Q-Bus. Digital's Q-Bus extended bus consists of a multiplexed 22-bit
address/16-bit data lines. The main purpose of this mode is to allow the system currently existing on the
Q-Bus to off-load some work onto the KXTl 1-CA SBC.
2.7 PERIPHERAL PROCESSOR ARBITER
When the peripheral processor mode is selected, the KXTl 1-CA SBC operates as a bus slave device
requiring the operation of an arbiter (master) device on the bus. A bus arbiter is a CPU having the ability
to handle bus initialization, arbitrate DMA operations, and service Q-Bus interrupts. A bus master can be

2-5

any device on the bus having control over current bus operations. A bus arbiter is capable of being both
arbiter and bus master. A KXTl 1-CA SBC can be a bus master during DMA operations but can never be
bus arbiter. Any and all transactions between the arbiter and the IOP must be initiated by the bus arbiter.
The SBC must always receive a command before any data is made available to the Q-Bus or any data is
taken from the Q-Bus arbiter.
2.8 PERIPHERAL PROCESSOR/IOP HARDWARE
KXTl 1-CA SBC hardware interface includes 22-bit bus transceivers, a 16-bit by 16-word two-port RAM
(TPR) file, and a Q-Bus interrupt register (QIR). The bus transceivers are the primary interface for
transferring 22/16-bit multiplexed address/data lines across the Q-Bus. A unique two-port RAM file
supports system control, status, and data transactions between the Q-Bus and the on-board T-11
microprocessor. The DTC transfers large blocks of data using the local 22-bit bidirectional transceivers for
DMA operations. The Q-Bus interrupt register (QIR) allows the SBC to send 8-bit level 4 interrupt vectors
to the bus arbiter. Figure 2-5 is a block diagram showing the peripheral processor interface.

16 BIT X 16 WORD
TWO PORT
RAM (TPR)

BIDIRECTIONAL
TRANSCEIVERS
AND LATCHES

INTERRUPT
REGISTER (OIR)

0 BUS
TRANSCEIVERS

0 (LSl-11) EXTENDED BUS
MR-10764

Figure 2-5

Peripheral Processor/IOP Interface

2.8.1 Backplane Connections
Backplane connections provide the signal path between the KXTll-CA hardware and the Q-Bus. This
signal path carries bidirectional, multiplexed, 22-bit address/16-bit data and control signals.
2.8.2 Power Connections
The Q-Bus supplies power (+5 Vdc, +12 Vdc, and system ground) to the KXTl 1-CA SBC. In addition,
the battery backup voltage for the on-board RAM can be supplied through the Q-Bus. This battery
backup voltage ensures RAM data retention when power is removed from the module.
2-6

2.9 NATIVE FIRMWARE
In addition to using standalone mode native firmware, the peripheral processor mode uses some additional
native firmware for two-port RAM operations, Q-Bus arbiter interrupts, and SBC interrupts.
The native firmware ROM contains the necessary selftest/boot/ODT codes for implementing, selftesting,
SBC initializing, application program booting, and application program running.
2.9.1 Two-Port RAM (TPR)
All commands between the arbiter and the KXTl 1-CA SBC are passed through the SBC's two-port RAM
file. The TPR is a 16-bit by 16-word register file supporting simultaneous read references and concurrent
read/write combinations from both local and Q-Bus memory spaces.
The first four registers in the file are used exclusively for local SBC system control. Support for the system
control registers consists of supplying local status information to the bus arbiter. The remaining 12
registers can be used by the SBC's application software and the system applications software.
2.9.2 DMA OPERATIONS
The direct transfer controller (DTC) is the device used to transfer large blocks of data, using DMA
operations, with minimal local processor involvement. A DMA operation can be initiated locally by the
processor or by the Q-Bus arbiter.
When initiated by the bus arbiter, the local processor receives command words and DMA transfer
parameters via the TPR file. After receiving transfer commands and parameters, the local processor
initiates the proper DTC operations. DMA operations occur between a 16-bit local address to a 22-bit
global address, a 22-bit global address to a 16-bit local address, a 22-bit global address to a 22-bit global
address, or a 16-bit local address to a 16-bit local address.
2.9.3 Arbiter To SBC Interrupts
During or after initialization, the Q-Bus arbiter can interrupt SBC operations by writing a command into
the TPR's first register. This is the only register available to the bus arbiter prior to complete initialization.
Every time the bus arbiter writes into this register, an interrupt is generated causing a nonmaskable trap to
the restart address of the T-11 chip. Native firmware then interprets the source of the interrupt and
implements the proper action. This register is intended to be the priority command channel for the arbiter.
Figure 2-6 shows the arbiter to KXTl 1-CA interrupt cycle.

BUS ARBITER

BUS SLAVE (SBC)

ISSUES INTERRUPT COMMAND
• WRITE TO SBC'S TWO PORT RAM (TPR) Fl AST WORD
-

RECEIVES STATUS
• READS CONTENTS OF TPR
STATUS REGISTER

TPR GENERATES INTERRUPT
• Tll RECEIVES NONMASKABLE INTERRUPT
• TRAPS T11 TO THE RESTART ADDRESS
- • NATIVE FIRMWARE INTERPRETS REQUEST

e SENDS COMMAND PARAMETERS - - - - _ -

CHECKS SBC STATUS
..,_. - - - REGISTER FOR DONE BITS
WHEN TASK IS COMPLETED

Figure 2-6

---

READS COMMAND PARAMETERS
-

• PERFORMS TASK WITH PARAMETERS
• DISPLAYS RESULTS IN TPR STATUS REGISTER

MR-12016

Bus Arbiter to KXTl 1-CA SBC Interrupt Cycle

2-7

After complete SBC initialization, interrupts can be sent from the arbiter into either of two register
locations in the two-port RAM file. The firmware associated with these two registers interpret the
interrupt as a level 5 interrupt. After receiving this type of interrupt the processor reads the contents of the
first TPR register for the command word. These two registers are intended to be secondary command
channels for the arbiter.
2.9.4 KXTll-CA SBC To Arbiter Interrupts
The KXTl 1-CA SBC must signal the bus arbiter every time it requires attention or completes a task.
Native firmware supports this signal by providing a word addressable write-only Q-Bus interrupt register
(QIR). The local processor can write vector values between 0 and 1774 (octal) into this register and the
QIR asserts Q-Bus interrupt request line. The bus arbiter responds by requesting the interrupt register
contents. After receipt of the interrupt acknowledge, a control signal from the bus arbiter, the contents of
the QIR is driven onto the bus. Upon receipt of the vector, the arbiter can service the SBC. Refer to
Figure 2-7 for the KXT 11-CA to arbiter interrupt cycle.

BUS ARBITER (MASTER)

SBC (SLAVE)
SENDS INTERRUPT REQUEST
•WRITES INTO QIR
• ASSERTS BUS REQUEST LINE -

---

VECTOR SENT TO ARBITER
• DRIVES QIR CONTENTS ONTO BUS...._

REQUEST SERVICE FLAG
• BUS REQUEST GOES TO
UNASSERTED CONDITION

..... .....

...------

PERFORMS INTERRUPT ACKNOWLEDGE
• ASSERTS BUS INTERRUPT ACKNOWLEDGE SIGNAL
- • RECEIVES INTERRUPT VECTOR

.....
'-RECEIVES INTERRUPT VECTOR
_ - • SERVICES REQUEST

Figure 2-7 KXT 11-CA SBC to Bus Arbiter Interrupt Cycle

2.9.5 Selftest/Boot Switch
Selftest/boot routines are selected via the hardware selftest/boot switch. The native firmware supports
these routines by providing two selectable functions as follows.
1.

The user can select one of three selftest functions. One function does not perform a selftest; the
second performs a selftest; and the third performs extended selftests.

The user's application program can be booted from two possible memory sources. One memory
source is located in the user's PROM; the other is located off-board in an 1/0 device.

2.9.6 Command Protocols
When operating in the peripheral processor mode, portions of SBC native firmware are used for implementing command and communications protocols. These protocols cover all basic SBC operations. Included under command protocols are the initialization, selftest, bootstrap, and application program routines.
Communication protocols are implemented using one of three separate 1/0 ports.
SBC initialization, selftest, and boot routines can be entirely initiated and directed by the Q-Bus arbiter.
This includes both the selftest and bootstrap operations. Boot operations provide the loading of an
application program from a Q-Bus memory space or local memory space to local SBC RAM space.
2-8

2.9.6.1 Start-Up - Prior to applying SBC power, both SBC ID and the selftest/boot switches are set.
The SBC ID switch selects the peripheral mode providing proper I/O page addressing. The selftest/boot
switch selects the routines to be implemented. Applying power to the bus supplies the Q-Bus with +5 Vdc,
+12 Vdc and system ground. During power-up the T-11 microprocessor initializes all on-board chips
according to the native firmware ROM. This includes the clearing of some registers and writing into
others.
2.9.6.2 Selftest - After SBC initialization is complete, the native firmware invokes the selected selftest.
This test verifies the operations of as many specific basic SBC functions as possible. The test performed is
dependent on the selftest/boot switch position. One selftest function initiates booting from the Q-Bus
thereby disabling any selftests. Another selftest function performs the test as a portion of the power-up
procedure or is implemented by directives from the native firmware. The last selectable selftest function
does not perform a selftest but waits for a command from the Q-Bus arbiter.
Sel{test routines check for two types of errors: nonfatal and fatal. For nonfatal errors the boot routine
continues with the LEDs displaying the last error encountered. After booting is complete a nonfatal error
will halt any further SBC operations. When a fatal error is detected, the boot routine is immediately
stopped with the LEDs displaying the last fatal error encountered. Refer to Chapter 6 for detailed LED
error information.
2.9.6.3 Boot - In addition to the standalone mode booting procedure described in Paragraph 2.5.1.2,
booting from a Q-Bus memory space is supported. One boot routine does not perform any booting but
places the SBC in a hold state, waiting for a command from the Q-Bus arbiter. Another boot routine
initiates the selftests and places the SBC in a hold state waiting for a command, via the TPR's first word,
from the Q-Bus arbiter. When the command is received, booting of the application program is done via a
OMA operation. The application program is then transferred into the local RAM space. Once the
application program is booted, application software controls SBC operations.
2.9. 7 Communication Protocols
Three data paths are supported by the peripheral processor mode. One path uses the TPR register file and
the second data path bypasses the TPR using local bidirectional latched transceivers. The third path occurs
between the SBC and off-board I/0 devices using one of the four I/0 ports.
2.9.7.1 Two-Port RAM (TPR) - Six words in the two-port RAM form the main communication path for
transferring data between the SBC and the Q-Bus. This path is used when messages are small in length.
Normally, these file words are used in conjunction with the four system control words. After sending a
command word, six file words are used to pass associated parameters. Considerable microprocessor time is
required for this type of data transfer. When large blocks of data are transferred, a OMA operation is
used, requiring minimal microprocessor time.
2.9.7.2 DTC Transfers - For transferring large blocks of data during OMA operations, a communication path requiring minimum microprocessor time is provided. The transfer of large blocks of data is
initiated locally (T-11) or globally (arbiter), both using the OTC for performing these transfers. Locally, all
DMA transfer commands and parameters are sent directly to the DTC from the T-11. Global transfer
commands and parameters are first sent to the TPR's first register. Then, the transfer commands and
parameters are received by the T-11 and passed to the local OTC (OMA controller). Finally, the OTC
initiates the OMA operation. Data being transferred is latched, via OTC control, onto the local bus via
internal bus transceivers. This path uses the Q-Bus transceivers bypassing the TPR.
2.9.7.3 1/0 Port Booting - The KXTl 1-CA SBC supports all the same booting protocols and procedures as in the standalone mode. (See Paragraph 2.5.3.1.) In addition, the peripheral processor mode
supports boot routines initiated and directed from the Q-Bus arbiter. To do this, the bus arbiter writes into
the first register of the local two-port RAM. Associated parameters are sent via the TPR's secondary
control registers.

2-9

2.9.7.4 1/0 Port Communication - After the application program is booted into the local RAM space,
communications via any 1/0 port is supported and controlled by the native firmware through the
application software. The user's application software must contain the necessary commands to implement
communications via selected 1/0 ports. Since the T-11 microprocessor is interrupt driven, the KXTl 1-CA
SBC can simultaneously support communications over all four 1/0 ports. This means that during each
interval data is received by an 1/0 port, an interrupt to the T-11 is generated.

2-10

CHAPTER 3
THEORY OF OPERATION

3.1 INTRODUCTION
This chapter provides a detailed explanation of KXTl 1-CA hardware operation from the perspective of
the logic designer. It is useful for an understanding of the SBC to the chip level.
NOTE
The negated or inverse signal is designated by letter
after the signal name. For example, Pl H is normally low and asserted high when activated; RAS L is
normally high and asserted low when activated. This
convention is used throughout this chapter.
The KXTl 1-CA SBC functional block diagram (Figure 3-1, Sheets l, 2, and 3) provides an overview of
the SBC functions and how they are related. The main components of the SBC are shown on Sheets 1 and
2. The SBC has a microprocessor interconnected to the serial line units, RAM memory, ROM memory,
direct transfer controller (DTC), and parallel 1/0 interface via internal TOAL and IIDAL buses. The
address bus, memory address decode function, Q-Bus bus interrupt register, two-port RAM with logic
sequencer, and the interrupt control function are also shown on Sheets 1 and 2.
The microprocessor support functions and the Q-Bus interface control functions are detailed on Sheet 3 of
Figure 3-1. Also included are the power-up, clock control, ready, DMA, and bus interrupt function. The
DMA, interrupt control, read/write and other functions are used to interface the Q-Bus to the
microprocessor.
The functional descriptions used in this chapter define the microprocessor and the input/output signals
associated with its operation. The support functions, Q-Bus interface functions, and the remaining devices
are also described in detail.

3-1

DLRRQ H I
DLXRQ

1----'-P'-'1H"--ll....i
DMARO L

ZCIORQ L
R0124 H

INTERRUPT
CONTROL

RQ130H

- AlO L _J PROCESSOR

I ~
I ~
A12L
r;;;;a;:-1

I ~

I ~
I
CLRRS H
~

RHALTH I
BREAK H

-r

R0134 H

BR0140 HT

MICRO~

I Ir----1
Al5 L .J

R0120 H _j_
PFAIL H T

I
I

t-+-~

R0104 H-,-

RESET H

I I ~

UPDRO H

RINITL

--,

_l ZAS L

GAS L

Pl H

_J_

~~~~C

I ZDS L

R/WLB L J

ARRAY

RAS L
SELO H

SEL1 H

R/WHB L I

DREQB L
ZAS L

RAS L

DMG L

YDAL

SELO H
SEL1 H

08,
1--15 H

~
1R/WLB L-

F:.::.+

DMG L

~ llDAL

-v

ADDRESS
DECODER

"\.I TOAL

,/I LATCHES

CSDL L
ZCIEI H

ZWRITE L

CSDTC L
CSPPI L

C~DTCL·I

CSLIP1L
CSLIP4L
CSRAM1 L

fJJ

CSRAM2 L

CSKTA L
CSKTB L

"-. ADDRESS
.

,-V

IREAD L

~
012

LATCHES

'.)

ADB 00 15 H

~ -

""V

ru
f-----i

AK120 L

AK124 L

I
I
I

AK130
AK134 L

DISDE H

L~_-_-_~J

Figure 3-1

SllDAL L
W11 L

DISDE H

TOAL 00-15 H

CSBCIO L
CSCIO L

TDRCVL

CSTMR L

""V
CLK285

!WRITE L

J: I R/WLB L

EDALS 16-21

CSDPR L
CSOIKX L

4
4 X2
MUX

CSUPD L

1---~'-

ZAK L

ZBW L

"-.

TDAL00-15H

_l ZWR1TE L

OTC

]

(OMA
CONTROLLER)

ZDS L
EDP L

CSll DAL L_I_
ZBWL

DMARQ L

MODE
CONTROL

IDS L

ZCIORQ L

DREQA L
Pl H
CAS L

TDRCV H

j AK134 L

AOPB L

KXTl 1-CA SBC Functional Block Diagram (Sheet 1 of 3)

W12 L

Qq)

f~....._

~IU

_ __

--.!DALS 16-21 H

DE646 L

().
BDAL00-16 H

<ij

CSRAM1 L
CSRAM2 L

LSl-11
BUS
DATA
INTER·
FACE

BML

BOAL
TO

1!VECTOR;

XDAL
LATCHES

IMATCH H.

JI TI
I

~ ~H
AD801 H

ADB02 H

IEWLB L
.___...

:c
..,

IREAD L

------

~ii.

.L1· ,...
CSKTA L

SOCKET

tMEMORY)

wI
w

-----,

XDAL 00--04 H

A DB03 H

~--><--~

IASL

PORT A

AK134 L

---<
IR/WLB L

---<

DPRHIT H
~

LOGIC
seauENCEA

CLK71 H

I
I

'----

..----

.I\
.,____.
AK130 L
VETCH
IR/WLB L

0-----..

QIR

L ______ J

I
I

T:o

PORT

DPRHIT H
Ra120 H

I
I
I

Figure 3-1

CSKTB L

LINE

40
PIN

UNIT2

~loRE~L

ADB03 H

SERIAL

LINE
UNIT2

-.I\. CHANNEL B DREOB L

J2
10
PIN

~
CSCIO L
ZCIEI H

PARALLEL
1/0

(MEMORY)

-,.

PORT 8

CONTROL
AND
STATUS
REGISTERS
(A,B,C,DI

I
I
I

SBC ID
SWITCH

KXTl 1-CA SBC Functional Block Diagram (Sheet 2 of 3)

J4
40
PIN

RAM)

AD801 H

____ ...JI

R0130 H

SERIAL

CSUPD L

<
0

USER
SOCKET

10
PIN

.---

CSUPD L

PDRAM L

I I:=:

ADB01 H

. . rf

"'0

SERIAL
LINE
UNIT1

I-·····

IR/WLB L

>MCO " "

lAM

IR/WHB L

XDAL00-15H

~'------'

TDINH

jllo. BIR04 L
BIAKO L

BIAKI L

I----'

BINIT L
DC3ROH
SBCOP L

DIDO L
CLK71 H
CSDTC L
ROTM L

INTERRUPT
CONTROL

OBER H

<lLK571 H

END OF
PROCESS
TIMEOUT
IEOPI

PFAIL H

BOIN L

~SBCOPL
~

BDMGO L
BDMR L
BDMGI L
RODC10 H
SBCOP L
DC10RP H
CLK142 H
TSYNCH

LSl-11
BUS
OMA
CONTROL

SEL1 H

MYBUSH
RRPLY H

IWRITE L

SELOH

LSl-11
BUS
OMA
CONTROL

TSYNC H

IASL
BDCOK H

OBER H

BPOKH

ODCLO L

BHALT L

PFAIL H

BRPLY L
BWTBT L
BDOUTL

LSl-11
BUS
INTERFACE

CLK 571 H
CLK 285 H
SYSTEM
CLOCK

RDIN L
RSYNC L

CLK 142 H
CLK71 H
CLK36 H

RDOUT L

SELOH

BSYNC L
BBS7 L

SELi H

PORAM L

COUTL

ZAKL
CSLIP1 L
CSLIP4 L

P FAIL H

ROTML

WAKE UP
INITIALIZE

READY H

SEE SHEET 1

I
I
1--~~~~~~~~~~~~P~UP~H.....1 __ _JI
OPRDY L
CASL

Figure 3-1

READY

I
I
I ~~~~SSOR I
1
I
I

KXTl 1-CA SBC Functional Block Diagram (Sheet 3 of 3)

3.2 MICROPROCESSOR
The DCTl 1-AA microprocessor is contained within a 40-pin LSI chip and is shown in Figure 3-2. There
are eight internal 16-bit general-purpose registers (RO-R 7). R6 operates as a stack pointer (SP); R 7
operates as the microprocessor program counter (PC). A special-purpose status register contains the
current processor status word (PSW). The operating characteristics of the microprocessor are affected by
the mode register which is discussed in detail in Paragraph 3.3.
3.2.1 Microprocessor Initialization
The microprocessor initializes the KXTl 1-CA SBC during the power-up sequence or when the RESET
instruction is exe.cuted.
3.2.1.1 Power-Up Input (PUP) - The power-up (PUP) input goes from a high to a low transition
approximately 47 ms after the 5 V power is first applied initiating the power-up sequence. The BCLR L
output is then asserted. The SBC functions are reset as for the RESET instruction; however, both serial
line units (SLUl and -2), control status registers (CSR A, B, C and D) are cleared and reset. In the
peripheral processor mode, after a delay, incoming Q-Bus signals BDCOK Land BPOK Lare asserted,
PUP H is negated, and the BCLR L output goes high. In the standalone mode, PUP H is negated by

3-4

BHALT L
PFAIL H

~N ,.~ ~Eu°PT
INPUTS

DMARQ L

READY H

Al7 L ..-

39
Al6 L
38
A15L ~
37
Al4 L
Al3L A12 L _

5 6 ~
7 i-.
9~

PUP

XTL1 _.
XTLO -

TOAL 11 H
TOAL 10H
~

TDAL09 H
TDAL08 H
~

i-.

TDAL06 H
TDAL05 H

...
~

TDAL02 H
~

TDAL01 H

TDALOO H

22
31

TDAL03 H

TOAL
BUS

TDAL04 H

17
CLK 142 H

TOAL 13 H
TOAL 12 H

13
PUP L

TOAL 14H

TDAL07 H

--~

2 i-3 ~

34
Al1 L ::
33
AIOL ~
32

READY

TOAL 15 H

Pl H
~

MICROPROCESSOR
DCT11-AA
18

21
29
30
+5

GND

COUTH
~

RASL

}

TRANSACTION
CONTROL
STROBES

}

TRANSACTION
TYPE
CONTROLS

CASL

RESET

BCLRL RESET..-

RIWLB L

RIWHB L

SELOH

SEL1 H

...

--...--

MR·11871

Figure 3-2 DCTI 1-AA Microprocessor

clearing the PUP flip-flop during the assertion of TPUP L. The microprocessor then performs 10 bus
NOP transactions. The processor loads the starting address into the program counter (R 7) and loads
location 376 into the stack pointer (R6); the processor status word is set to 340. An assert priority in
(ASPI) transaction is performed (Pl His asserted) to service any interrupts or DMA requests before the
first instruction is fetched.
The PUP H input normally stays fow for all operations. If PUP H is asserted high, the present transaction
is terminated and the internal registers go to an undetermined state. The local TOAL bus, the interrupt
inputs, and the microprocessor control signals will all go to an initial reset state.

3-5

3.2.1.2 Reset Instruction - T)le reset instruction asserts the BCLR L output. This clears or resets the
control logic of the SBC to an initial state'. The microprocessor loads the mode register from the TDAL
bus with the mode register control data. The Q-Bus transceivers and local TDAL-IIDAL bus transceivers
are disabled when BCLR Lis asserted. All interrupts from the gate array (vector encode circuitry) to the
T-11 are inhibited and any pending latched requests are cleared. Allbits in KXT control status register
(CSR) D are cleared.
The BCLR L output is then negated and an assert priority in (ASPI) transaction is performed to service
any interrupts or DMA requests. The reset instruction does not change the PSW or any internal register
values.
3.2.2 Microprocessor Control Signals
The microprocessor controls the functions of the KXTll-CA through the use of nine microprocessor
control signals. A description of these signals and their functions follows. The RAS, CAS, Pl, COUT, and
BCLR are transaction control strobes used for logic transitions. The R/WLB L, R/WHB L, SELO, and
SELl are steady state logic signals used as "transaction type" control signals.
3.2.2.1 Row Address Strobe (RAS L) - The leading edge of the RAS L signal is used to acknowledge
that the address is stable on the TDAL bus during read/write and fetch transactions. During interrupt
transactions, the leading edge of the RAS L signal strobes the interrupt acknowledge data onto the TDAL
12-8 bus lines.
3.2.2.2 Column Address Strobe (CAS L) - The trailing edge of the CAS L signal is used to acknowledge
that data on the TDAL bus lines during read and fetch transactions was read by the microprocessor. The
trailing edge is also used to enable the microprocessor to read the interrupt inputs AIO L to AI7 L and to
initiate IAK, restart, power fail, or DMA transactions. For write transactions, the signal is used to
acknowledge that microprocessor data will be removed after a specified time.
The leading edge of the signal is used to request that read data be placed on the TDAL bus and to strobe
interrupt requests into latches that are read during the assertion of PI H.
3.2.2.3 Priority In (PI H) - The leading edge of the PI H signal is used to acknowledge that data on the
TDAL bus lines during write transactions is stable. In addition, asserted PI H enables encoded information
to be driven on the AI lines.
3.2.2.4 Read/Write (R/WHB L and R/WLB L) - The R/WHB L and R/WLB L signals control the
read/write and fetch transactions by enabling T-11 reads and writes into and out of local RAM/ROM and
1/0 ports.
3.2.2.5 Select Output Flags (SELO H and SELi H) - The SELO H and SELl H signals indicate the
transaction being performed. When both signals are low, a read, write, ASPI, or NOP transaction is
selected. When both signals are high, a DMA transaction is selected. When SELl His low and SELO His
high, the fetch transaction is selected. When SELl His high and SELO H is low, an IAK transaction is
being performed.

3.2.2.6 Bus Clear (BCLR L) - The BCLR L signal is used to reset the control logic. The signal is
asserted during the power-up sequence and during the execution of a reset instruction only.
3.2.2.7 Clock Out (COUT H)-The COUT H signal is asserted once for every microcycle and is used to
synchronize external signals with the T-11.

3-6

3.2.2.8 Clock (CLK 142 H) - The CLK 142 H input is a 7-MHz clock that is derived from the 28-MHz
crystal oscillator. This clock input is used for the internal time base of the microprocessor and the source
of the clock output (COUT). COUT is pulsed once for every microcycle. A microcycle can represent
either three or four CLK 142 H input pulses depending on the type of transaction. The microprocessor will
halt or stop when the CLK 142 H input is disabled.
3.2.2.9 Ready (READY H) - The READY input is normally high and will not interfere with
microprocessor transactions. However, when the input pulsed, a single microcycle slip occurs during every
bus transaction. When READY is clocked with COUT H, while RAS L is asserted, the microprocessor
slips a microcycle every time the input is pulsed. This allows the microprocessor to be placed in an idle or
wait state until a peripheral device has either received or asserted data on the bus.
3.2.3 Microprocessor Transactions
The microprocessor performs the following six types of transactions to support the instruction set, direct
memory access, and the interrupt structure.
1.
2.
3.
4.
5.
6.

Fetch/read
Write (word or byte)
OMA
IAK/External/lnternal
ASPI
Bus NOP

A normal fetch/read or IAK transaction requires either one or two microcycles; extended transactions can
take multiple microcycles as required. The COUT H signal is asserted once for every microcycle. The
transactions are used to transfer information and data via the TOAL bus which interconnects all local
devices and connects them to the Q-Bus interface. A description of each transaction operation follows.
3.2.3.1 Fetch/Read - The fetch/read transaction is used either to fetch an instruction or read data for
the microprocessor. The data may originate from the on-board memory I/O device. The microprocessor
control signals for the transaction are shown in Figure 3-3. The R/WLB Land R/WHB L control signals
are unasserted. The SELO H output is high, and the SELi H output is low for the fetch transaction; both
of these outputs are low for the read transaction.
The following sequence of events takes place during a fetch/read transaction.
1.

The microprocessor places the address onto the TOAL bus when the transaction is initiated and
is latched into the memory address circuits by the assertion of IAS L (derived from RAS L).

The data is received on the TOAL bus after RAS L is received. The microprocessor accepts the
data and asserts CAS L.

Interrupt and OMA requests are latched by CAS L, set up while PIH is asserted, and latched
into the microprocessor when PI H is asserted.
NOTE
A write transaction is always preceded by a read
transaction except when the microprocessor pushes
onto the stack. Therefore, each write has at least
four microcycles: assert address, read data, assert
address, and write data.

3-7

>--------FETCH/READ•TiR•ANSACTION-------...

1411-----ASSERT ADDRESS----+i--t-----READ DATA---..i1
NOTE 2

COUTH _ _ __

x__________{.____

~~~H::x___A_o_o_R_Es_s_ _ _

Al-0-Al-7 L-.::J,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

RAS L

____

r:::_

o_A_TA_IN_ _ _

...,(_1_N'""JE"""'i_tt,""~'""s°T.._M_A_.._)_ __

PIH--------------J
CASL _ _ _ _ _ _ _ _ _ _ _J

R/WLB L":J

~HBL~
SELOH =i--------N~~E-,--------,

SEL1 H

~-------------------L
NOTES:
1. SELO IS HIGH FOR FETCH TRANSACTIONS
AND. LOW FOR READ TRANSACTIONS.
2. TOAL BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTIL THE
DEVICE RESPONDS OR TIME-OUT OCCURS.
MR-12462

Figure 3-3

Read/Fetch Transaction

3.2.3.2 Write -The write transaction is used to write data from the microprocessor to memory or a local
1/0 device. The microprocessor control signals for the transaction are shown in Figure 3-4. The R/WLB L
and R/WHB L control signals are asserted low when writing a word; when writing a byte, either the high
or low byte signal is asserted. Both SELO and SEL 1 control signals are asserted.
The following sequence of events take place during a write transaction.
1.

The microprocessor places the address onto the TDAL bus, and the state of the read/write lines
causes !WRITE L to assert. The address is latched into the memory address decoder by the
assertion of RAS L.

When CAS is asserted, !WRITE L is unasserted for word transactions and left asserted for byte
transactions.

3-8

1 4 ' - - - - - - - - W R I T E TRANSACTION--------:1
---ASSERT ADDRESS---•114•--WRITE D A T A - - - - - - ·
NOTE 2
COUTH _ _ _

_.f

'--------'

'------

~~~H~..___ _Ao_o_R_E_ss_ _ _~-----D-AT_A_o_u_T_ _ _ _ _ _ _~

Al-0-Al-7 L

J _______________.(. . . .

_oM_A_R_E_o_u_E_sT_ _) _ _

___

RAS L

__,

PIH _ _ _ _ _ _ _ _ _ _ _ _....1

CAS._ _ _ _ _ _ _ _ _J
R/WLB L J _______N O T E l - - - - - - - - - - - - - - - - - - - - - - - - - -

-c_

NoTE,----------------------------c_

R/WHB L=1_______

SELO H
SELi H

NOTES:
1. R/WHB LOR R/WLB L CAN BE HIGH WHEN
PERFORMING A WRITE BYTE TRANSACTION.
2. TOAL BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF THE TIME TOSLIP UNTIL THE DEVICE
RESPONDS OR TIME-OUT OCCURS.
MA-12461

Figure 3-4

Write Transaction

The data is placed on the TDAL bus before PI H is asserted. The data is written into the
addressed location when PI H is asserted.

The DMA requests are detected while PIH is asserted; they are latched into the microprocessor
when PI H is unnasserted. No other interrupts are read by the microprocessor during write
transactions.

3.2.3.3 IAK/Internal/External - If an interrupt request was detected during a previous read transaction, the microprocessor initiates an IAK transaction as shown in Figure 3-5. The CAS L, R/WHB Land
R/WLB L control signals are asserted; PIH and SELO Hare unasserted for the IAK transaction. TDAL
bits 12-8 output a code representing the acknowledged input and are used to reset the interrupt request
logic. The T-11 chip can service both local and external interrupts.

3-9

..
,• ...___ _ SEE N O T E - - - - . i · I

COUT H

TOAL 12-08 HJ....__ _ _ _ _,_N_TE_R_R_u_PT_R_E_o_uE_s_T_D_AT_A_ _ _ _ _ _

ToAL 01-00 H

==xt_______,,X'"____

v_E_cT_o_R_,_N_ _

RAS L. _ _ _ _ __.

_,JX___

SELOH:-1.__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

SEL1H~

\'-----

''-----

IAKDIN~
TVECTOR - - - - - - - - - -

\.._

TDINH__J

____

NOTE:
LSl-11 BUS TRANSACTIONS CAN CAUSE THIS
PORTION OF TIME TO SLIP UNTIL THE DEVICE
RESPONDS OR TIME-OUT OCCURS.
MR-12457

Figure 3-5

IAK .Transaction

For local interrupts, TOAL bits 7-0 are ignored because the vector address is located in the microprocessor. For external (OTC, PI/0) interrupts, the vector address is read from TOAL bus bits 7-2. TOAL 12
(VECT L) is set low for external IAK transactions and commands the control logic to initiate an external
vector IAK transaction. TOIN H is asserted for the transaction, TVECTOR L acknowledges the interrupt.
The requesting device places the vector address on low byte of the Q-Bus and asserts B RPLY L. The
microprocessor asserts TDIN Hand accepts the vector. Software programmable vectors are read into the
T-11 when VEC L is asserted.

3.2.3.4 OMA - The OMA request is read during a previous transaction. The microprocessor will
acknowledge the request by tristating the TOAL bus as shown in Figure 3-6. The SELO Hand SELl H
outputs are asserted to indicate that the bus mastership has been relinquished to an external device (OTC).
The OTC is the only device that can acquire local bus mastership from the T-11. The transaction will
continue with no interruptions until the OMA transfer is completed. The microprocessor will then unassert
the SELl H control output to indicate that the T-11 is resuming bus mastership. The unassertion of SELO
H will follow if the next transaction is not a fetch.
3.2.3~5 ASPI -' The assert priority in (ASPI) transaction is used by the reset and wait instructions or
during the power-up sequence as shown in Figure J. 7. The CAS L and PI H outputs are asserted, enabling
the microprocessor to recognize and latch any interrupts or OMA requests. The R/WHB L and R/WLB L
outputs are unasserted and the SELO H, SELl H, and RAS L outputs are negated for the transaction.

3-10

COUT H

-(c

--------J,_________

T_R_l-_ST_A_T_E_ _ _ _ _ _ _ _ _ _ _

~~ H - - - - - - - RAS L

\.__
PIH

__
c
c

R/WHBH------)
TRI-STATE
R/WLB H _ - - - - - ~---------------------- - - -

-.1/

SELO H _ _ _ _ _ _

SEL1H _ _ _ _ _ _ __,

DMG H - - - - - - - - '
MR-12460

Figure 3-6

DMA Transaction

COUTH

TOAL
)
TRI-STATE
{
00-15H -----~-----~...;;.;.~;;.....-----<

_________

~~~~~~~ (..._ _ _ _ _ _ __.(_IN""'J~l;;:QN""U~:;,:S;:.:~M__.A}'---'->------

Al-0-Al7 H

r--------______________
________

------,

- ----- ....._
'

RAS L

__________

CAS L
Pl H

1
__.'-

R/WHB L - - - -

R/WLB L------~

\--'-------

SELO H - - - - - - \

/"----------

SEL1 H - - - - - - - - - - - - - - - - - - - - - - - ' · - - - - - - - · - - - MR·12468

Figure 3-7 ASPI Transaction

3-11

3.2.3.6 NOP - The bus NOP transaction performs no operation and is used during the power-up
sequence or if the programmer intentionally introduces a delay into the program. The AIO L-AI7 L inputs
are tristated to prevent interrupts. The R/WHB L and R/WLB L outputs are asserted, and the SELO H
and SELl H outputs are unasserted low. The RAS L, CAS L, and PI H control strobes are inhibited
during the transaction as shown in Figure 3-8.

COUT H

TOAL
00_15

\______r

- - - -I

v--------

H-------v
------ __ _A_ _ _ _
PR_E_v_1o_u_sL_Y_L_A_T_cH_E_D_D_A_TA_ ____,/\.._ - - - - - -

Al·O-Al-7 H=====)>-------T.-.R-1-S-.T-.AT"'"E'--------c(~~---------

RAS L......\
\

CAS L \

R/WHB L - - - - - R/WLB L ______/

I\...

_______ __

r--------_
__________________________
---------------------------

-------,
________ ......._
'

SELO H

MR-12459

Figure 3-8

NOP Transaction

3.3 MODE REGISTER
The mode register is used to define the operating mode of the T-11 microprocessor. The 16-bit mode
register is written into from the TOAL 0-15 data lines during a power-up sequence or when a reset
instruction is executed. During this time, the BCLR L output is asserted and the mode register is loaded.
The mode register logic (Figure 3-9) has five tristate drivers that are enabled. TOAL bits 8 and 11 are
factory set to force the microprocessor to operate in the following mode.
1.

The microprocessor clock mode is selected. The microprocessor pulses the COUT output once
for every four XTLl input pulses during OMA and interrupt transactions. For all other
transactions, it pulses the COUT output once for every three XTLl input pulses.

The standard microcycle mode is selected. This mode uses four XTLl input periods for OMA
and interrupt transactions and three XTLl input periods for all other transactions.

The normal read/write mode is selected. This mode sets the read/write control lines (R/WLB L
and R/WHB L) prior to the assertion of -RAS and remains valid after the negation of CAS L.

3-12

The static memory mode is selected, and therefore, no dynamic memory chips may be installed
on the board. The refresh function is disabled.

The memory addressing is limited to 64 Kb.

The bus has 16 bits.

The user mode is selected. This mode performs transactions with no automatic test of the
processor status word.

The status of TOAL bits 13-15 are factory set and determine the start address for the microprocessor.
The start address is the location of the first fetch after power-up.

TDAL 08 H
TDAL11H
TRI
STATE
DRIVERS

!3v

TDAL 13 H

0
0

TDAL 14 H
TDAL 15 H

RESET H
MA·11667

Figure 3-9

Mode Control Register

3.4 CONTROL STATUS REGISTERS (KXTCSR)
The local processor has four I/O page addressable registers for controlling and monitoring the SBC system
environment. The following represents an overview of each register. More specific register bit detail and
usage can be found in Chapter 5.
3.4.1 KXTCSR A
SBC control status register A is an 8-bit read/write word or low byte addressable register providing
synchronous/asynchronous clock control bits, party line receiver enable bit, modem control bits, diagnostic
PROM control bit, real-time clock (RTC) enable bit, and programmable clock-inteaupt control bits.
3.4.2 KXTCSR B
SBC control status register B is an 8-bit read only low byte or word-addressable register providing status
for synchronous/asynchronous modem line, memory map configuration, and the boot/selftest switch
selection.
3.4.3 KXTCSR C
SBC control status register C is an 8-bit read only (RO) low byte or word-addressable register providing
status for SBC ID switch setting and four programmable red LEDs for error reporting.
3.4.4 KXTCSR D
SBC control status register D is a 16-bit read/write word-addressable register providing status and control
for nonexistent memory (NXM) flag, Q-Bus interrupt register (QIR), full flag, QIR interrupt enables,
Q-Bus reset occurred flag with trap enable, BHALT trap enable control, two-port register (TPR) restart
occurred flag bit, TPR enable bit, TPR interrupt enable bits, and TPR interrupt status flags.

3-13

3.5. SYSTEM CLOCKS
The KXTl 1-CA SBC uses two crystal oscillators: one 28-MHz and one 19.660-MHz. The 28-MHz
oscillator is used as the basic time base reference for the microprocessor. The 19.660-MHz oscillator is
used as the basic time reference for the 1/0 ports.
The 28-MHz oscillator (Yl) output (Figure 3-10) goes to the divide-by-7 clock control logic and to the
binary counters. During the power-up sequence, TPUP L asserts to load the counter with data. The
28-MHz output is divided by seven, providing a 4-MHz output (CLK250 H) that is used in the counter
timer parallel 1/0 chip and SLU2. The 28-MHz output is also divided by two, and the (14-MHz) output
(CLK71 H) goes to the logic sequencer. This 14-MHz output is further divided by 2, 4, and 8. The divideby-2 (7-MHz) output (CLK 142 H) goes to the T-11 microprocessor and the Q-Bus DMA request
(DCOOlO) chip. The divide-by-4 output, a 3.5-MHz output (CLK285 H), goes to the DTC. The divide-by8 output, a 1.75-MHz output (CLK571 H), goes to the DC0003 interrupt control chip. During the
KXTl 1-CA power-up cycle, the asserted TPUP L signal clears the following counters: divide-by-7, divideby-4, and divide-by-8. Asserted TPUP L also presets both divide-by-2 counters.

TPUP H
28.0
MHZ
Y1

CLK 250 H

ri-------,
I
.
I

CLK 71 H

TPUP L J"I

....,

_,.,....,

I
I

CLK 142 H

JOI

I
I

_,.,

L _______
J

.1
I

CLK 285 H

CLK 571 H

MR-11761

Figure 3-10

28-MHz System Clocks

The 19.660-MHz oscillator (Y2) output (Figure 3-11) goes to a dual 4-bit binary counter. These binary
counters are always enabled. The output of Y2 js divided by two, providing a 9.83-MHz output (CLKlOl
H) that is used to drive the output ·or the programmable baud rate generator. The 19.06608-MHz is
divided by 32, providing a 614.4 KHz output (CLK016 H) used to drive SLUl driver and 12 V charge
pump.

3-14

r---,
I
I
I

19.06608
MHZ
Y2

I
I

...,

I
CLK 101 H (9.533 MHZ)

CLK 016 (595 KHZ)
I

TL __ ..JI
72

MR-11762

Figure 3-11

19.066-MHz System Clock

3.6 Q-BUS INTERRUPT PROTOCOL CHIP (DC003)
The DC003 protocol logic chip (Figure 3-12) is used to generate a level 4 interrupt on the Q-Bus with a
programmable vector address generated by the KXTI 1-CA SBC. When an interrupt request is pending,
the Q-Bus interrupt register (QIR) sends a request to the DC003 chip. The DC003 request signal, DC3RQ
H, asserts, enabling the bus interrupt request line (BIRQ4 L) to assert on the next low-to-high transition of
the 1.75-MHz clock (CLK571 H). The bus arbiter acknowledges the assertion of BIRQ4 L by asserting
RDIN L and then asserts the BIAKI L line. This BIAKI L signal is daisy chained through each board. The
BIAKI L line of one board is the BIAKO L line from the electrically closer board, to the arbiter in the
daisy chain. The first board with an interrupt request (BIRQ4 L line asserted) captures the BIAKI Land
inhibits the remaining boards in the daisy chain from receiving the IAK by keeping BIAKO L unasserted.

DC3RQ H

DC 3RQ H

VECT H
DC003

Figure 3-12

Q-Bus Interrupt Chip (DC003)

After capturing the bus interrupt acknowledge, VECT H becomes asserted. This enables the SBC's Q-Bus
transceivers to drive the interrupt vector onto the Q-Bus. When the interrupt request cycle is completed,
the DC3RQ L line becomes unasserted high. This causes the BIRQ L line to become unasserted and the
bus arbiter unasserts lines RDIN L and BIAKO L. The DC003 protocol is used only during Q-Bus
interrupt operations. During standalone mode, SCOP L is asserted, inhibiting all DC003 outputs except for
RINIT L. The KXTI 1-CA SBC can then detect and respond to Q-Bus resets (looks at state of BINIT L).
When the KXTll-CA is operated in the peripheral processor mode and the arbiter asserts BINIT L, all
lines driven by the DC0003 become unasserted except for output RINIT L. This line asserts, causing the
SBC to perform a trap to location 24, if enabled.
3-15

3.7 Q-BUS DMA PROTOCOL CHIP (DCOIO)
The DCOlO DMA protocol (Figure 3-13) is used by the SBC's DTC (OMA controller chip) to gain control
of the Q-Bus for read/write DMA transfers. The DTC sequence is operated by a 7-MHz clock rate
(CLK142 H). Read/write OMA transactions are initiated by asserting the request line RQDClO H. The
asserted RQDClO H combines with the unasserted SBCOP L to assert the bus direct memory request
(BDMR L) line. The Q-Bus arbiter responds to the direct memory request by asserting the bus direct
memory grant line (BDMGI L), which causes the direct memory grant output (BDMGO L) to the
unasserted state. This ensures that only the electrically closest (to the arbiter) requesting SBC gains control
of the bus. BDMGI Lis daisy chained through each board in the daisy chain. The BDMGI L line of one
board is the BDMGO L line from the electrically closer board in the daisy chain. The first board
requesting a direct memory grant inhibits the remaining daisy-chained boards from receiving a grant by
keeping BDMR L unasserted.
When the arbiter's current operation cycle is completed, RSYNC H becomes unasserted. This enables the ·
SBC to assert MYBUS H and send a control signal to the Q-Bus. The OTC has now completed the
acquisition of the Q-Bus and is ready to do a read or write cycle.

REO

RODC10 H

INIT

SBCOP L
BDMGI

BDMR L

BDMG

IAS L
DC10RP H

DIN

:fDATA L

RPLY

TAODR H

RSYNCH
CLK 142

TDIN H
CLK

DOUTH

MR-11769

Figure 3-13

Q-Bus OMA Protocol Chip (DCOlO)

The following occurs when a Q-Bus write cycle is requested. During this transaction the SBC is Q-Bus
master and the arbiter is Q-Bus slave. Both IAS Land !WRITE Lare asserted in sequence, toggling the
flip-flop, thereby supplying a low to DCOlO input RDIN. The DCOlO asserts the transmit address signal
TADDR H used by the SBC to latch the address onto the Q-Bus. After latching the outgoing address, the
DCOlO asserts transmit sync signal TSYNC H used by the slave device to latch in the address. Next, the
DCOlO latches outgoing data onto the Q-Bus by asserting TDATA L.
The DCOlO now asserts TDOUT Hand is used by the slave device to latch in the data from the Q-Bus.
After data is latched into the bus processor, it responds by asserting BRPLY L, which is then received by
the DCOlO as an asserted reply (DClORP H). This ends the write cycle, causing TDOUT H, TSYNC H to
unassert and begin the next cycle.
When a Q-Bus read cycle is requested, the Q-Bus slave (arbiter during this interval) first latches the
address asserted by the SBC when TSYNC H is asserted. For read cycles !WRITE L is unasserted.
DCOlO requests data from the slave device by asserting TDIN H. After receiving TDIN H the slave drives
addressed data onto the Q-Bus and asserts BRPLY L, indicating that data on the Q-Bus is valid. The
asserted BRPLY L combines with asserted MYBUS H in the Q-Bus OMA control portion of the DC340
to provide the DCOlO with an asserted DClORP H input. Data is then latched into the SBC when TDIN H
becomes unasserted during a high-to-low transition.

3-16

3.8 Q-BUS INTERFACE GATE ARRAY (DC340)
The DC340 gate array contafos a 16-bit X 16-word two-port register (TPR) which includes a 16-bit system
control register (TPR Register 0) that is a read only from the local bus and a wwrite only from. the Q-Bus.
In addition, the DC340 contains the QIR, an 8-bit vector interrupt register. Figure 3-14 shows the DC340
logic. The DC340 is intended to operate with a state machine that provides the two-port RAM write access
control arbitration between local bus and Q-Bus access. (See Figure 3-15.) The local bus consists of the
bidirectional TDALOO H-TDALl 5 H lines. The Q-Bus consists of the bidirectional XDALOO H
-XDAL15 H lines.
16
IDAL (LOCAL)

16 BIT X 16 WORD
REGISTERS
(TPR)

16-BIT
CONTROL
REGISTER D

B BIT (QIR)
INTERRUPT
REGISTER

MR-11758

Figure 3-14

Q-Bus Interface Gate Array Simplified Block Diagram (DC340)

CLK71

LOGIC
SEQ.

TPR
CONTROL
LINES

LSl-11 BUS

Figure 3-15

TPR and Logic Simplified Block Diagram

3-17

3.8.1 Two-Port RAM (TPR)
The two-port RAM is a 16-bit X 16-word file. (See Figure 3-15.) Concurrent reads can occur between the
Q-Bus and local TDAL bus; concurrent read/write combinations from both buses can occur. The local
TDAL bus has read/write priority over the Q-Bus, enabling some T-11 read-modify-write operations. This
word file is Q-Bus addressable and has an address that changes with the SBC system ID switch setting.
Q-Bus writes to the fifth, ninth or thirteenth words cause flags to be set in control register D and/or
interrupts to the T-11 through vectors 120, 124, and 134 on level 5. A priority channel is provided by the
first word (O), so that when written from the Q-Bus, a T-11 restart trap is generated and a flag bit in
register Dis set. All words are addressable from both the Q-Bus and the T-11. Not all words are R/W
from both buses. The TPR state machine diagram is on page D-19.
Read/write cycles (IICYC) are performed using TPR port B and local TDAL bus. To do a local read
(IIRD cycle) a logic sequencer must assert two-port ready input enable line DPRDY L. Then the logic
sequencer asserts the B port input enable line ENBPTL. These two asserted outputs enable the TDAL bus
access to the TPR through port B.
To do a local write (IIWT) the logic sequencer must assert two-port ready output DPRDY L. Then the
logic sequencer asserts the write into two-port RAM enable line WTDPR L. These two asserted inputs
enable the TDAL bus data to be driven into the TPR through port B.
The Q-Bus arbiter can perform read/write operations in/out of the TPR using port A. TPR operations are
enabled by setting TDAL bit 6. Prior to TDAL bit 6 being set, the arbiter is limited to writing only into the
first TPR register. In addition, control status register D (KXCSRD) and the second, sixth, and tenth words
are Q-Bus read only.
Attempted writes from the Q-Bus processor into any other word causes a timeout to occur. Attempted
Q-Bus processor reads of any readable TPR word asserts FZO Hand forces all TPR word contents to be
read by the Q-Bus processor as zeroes. Asserted FZO L is used as an input to the logic sequencer that
inhibits Q-Bus read sequencing. Until the TPR is fully initialized, FZO L is asserted, inhibiting any TPR
Q-Bus re_ad operations. Write operations from the Q-Bus are limited to TPR register 0. In addition, the
local TDAL bus can do read/write TPR operations. When the TPR is fully initialized, TDAL 6 acts as the
TPR Q-Bus read/write enable (FZO L becomes unasserted).
During a Q-Bus read cycle, the arbiter selects the TPR by asserting MATCH H with RSYNC H. These
two assertions combine and assert the TPR ready line DPRHIT H. This high is clocked through a flip-flop
and becomes logic sequencer asserted SMATCH H. Next, the Q-Bus processor asserts RDIN H. The logic
sequencer receives RDIN Hand asserts both ENAPT Land then TRPLY L. These two assertions enable
port A to drive selected TPR data onto the BDAL bus via internal XDAL bus. After data is transferred
either RDIN H or SMATCH H becomes unasserted ending the read cycle.
During a Q-Bus write cycle, the MATCH Hand RSYNC H lines are asserted when the Q-Bus processor
addresses the TPR. To sftobe the Q-Bus address into the TPR, the logic sequencer now asserts SQBAD L.
Next, WTPDR L becomes asserted, enabling the Q-Bus arbiter to write into the TPR file. The data is
transferred via port A into the TPR when input strobe TRPL Y L asserts. The selected Q-Bus data now
resides in the TPR file.
3.8.2 Q-Bus Interrupt Register (QIR)
The QIR is an 8-bit, word addressable, write only vector register (Figure 3-16) used to signal the Q-Bus
arbiter (with a level 4 interrupt request) that it requires attention or that some task has been completed.
The local microprocessor can write vector values between 0 and 1774 into this register using the local
TDAL bus. The QIR is not initialized on power-up, and is only cleared by a local reset or by a Q-Bus
interrupt acknowledge. The register is updated with each T-11 write to the register. Bit 13 of register
KXTCSR D must be set to enable the QIR. (See Chapter 5 for register D details.)

3-18

CSOIKX L 1"I
VECT H "'
IR/WLB L 1"I
IAS L ;

PART OF
DC340
QIR

XDAL 02-XDAL 09 )
R0130 H

AK130 L ;
~

MR-11757

Figure 3-16

Q-Bus Vector Interrupt Register

The local T-11 processor initiates QIR operations by asserting chip select line CSQIKX L when address
strobe IAS L is asserted during a T-11 write cycle (IR/WLB L asserted). The interrupt vector data on
TOAL 02-09 is then latched into the QIR. This fills the QIR causing DC3RQ H to assert. The DC003
interrupt control chip receives asserted DC3RQ Hand responds by asserting BIRQ4 Lon the Q-Bus. After
receiving the Q-Bus BIAKI L assertion, the DC003 asserts the TVECT H line. The DC340 drives the
vector onto the XDAL bus 02-09 lines.
The Q-Bus arbiter now latches in the vector and also signals the DC003 chip that the cycle is completed.
This causes the TVECT H line to unassert. The high-to-low transition of the TVECT H line causes the
RQ130 L local interrupt line to assert. The interrupt vector (RQ130 H) line generates a local T-11
interrupt through internal vector 130. This local interrupt is read into the T-11 and then is acknowledged
by the assertion of AK 130 L. This interrupt signals the T-11 that the previous Q-Bus interrupt request was
acknowledged. The SBC interrupt is now ready to be serviced.
A local reset will flush the request, interrupt enable, and the vector 130 interrupt.
3.8.3 Logic Sequencer
The logic sequencer is used to control both local and Q-Bus arbitration for the two-port RAM. The logic
sequencer runs at a 14-MHz clock rate (see Figure 3-15). Operations are initialized during the initial
power-up interval when PUP H is asserted.
After power-up logic sequencer operations are unaffected by local or Q-Bus initializations. The sequencer
controls the two possible TPR cycles: a local bus cycle (IICYC) and a Q-Bus cycle (QBCYC). Each of
these cycles is further divided into read or write cycles. The state diagram for both TPR cycles is shown in
Figure 3-17. A detailed state diagram is on page D-19. Input signals controlling local bus cycles (IICYC)
are CSDPR L, IREAD L, IWRITE L, SMATCH H, and IDS L. The input signals controlling Q-Bus
cycles (QBCYC) are SMATCH H, RDIN H, RDOUT H, FZO L, and ADBOl H-ADB04 H.
A brief description of both read and write TPR operations for local and Q-Bus cycles follows.
The logic sequencer remains in the initial state until either a local or Q-Bus request line becomes asserted;
the CSDPR L line becomes asserted for a local cycle and the SMATCH L line becomes asserted for a
Q-Bus cycle. The logic sequencer then enters the ARBB state to arbitrate between local and Q-Bus cycle
requests.
When a local cycle (IICYC) is requested the IICYC state determines if a read or a write is requested. For a
write cycle the !WRITE L input asserts; enabling the DPR ready output DPRDY L to assert. The next
logic sequencer input needed is the data strobe assertion IDS L. After IDS L asserts, the logic sequencer
enters the ITWT state and asserts two outputs: write WTDPR L and the two-port ready DPRDY L.
During this interval a write into the DPR RAM occurs. The next CLK71 transition unasserts WTDPR L.
The sequencer changes state when data strobe IDS L unasserts. The logic sequencer then returns to the
initial state.

3-19

ITWT

llCYC

1-----.i

QBCYC

llRD

QBRD

QBWT

MR-11755

Figure 3-17

Logic Sequencer Functional Diagram

When a local read is requested the sequencer enters IIRD state when !READ L asserts. Then, on CLK71
transition, the two-port ready signal DPRDY L asserts, enabling port Bline ENBPT L to assert. The d~ta
is read during this interval and ENBPTL is asserted until !READ L becomes unasserted. When this occurs
the sequencer forces both DPRDY L and ENBPT L outputs to become unasserted. The sequencer goes
through three NOP states for syncing purposes when a T-11 read/write cycle is done, and then enters the
ITWT state checking for a write (!WRITE) request. If no write request is detected, the sequencer returns
to the initial state.
A Q-Bus read occurs if SMATCH H and RDIN H input lines become asserted. The sequencer enters the
QBCYC state and output line enable port A (ENAPT L) becomes asserted. On the next clock transition
input, the logic sequencer output - transmit reply, TRPLY L - is asserted. The logic sequencer enters the
QBRD state, a Q-Bus read occurs through port A, and the sequencer output, TRPLY L, remains asserted
until input signal SMATCH H or RDIN H become unasserted. When this occurs the sequencer unasserts
both EN APT L and TRPLY L outputs. The sequencer then ensures all its outputs are unasserted and
returns to the initial state.
A Q-Bus write occurs if SMATCH H and RDOUT H lines become asserted. The logic sequencer enters
the QBCYC state and output select Q-Bus address, SQBAD L, is asserted, enabling the address selected.
Next, a check of the address lines ADBOl-04 ensures that Q-Bus writes are not loaded into read only
registers. Another check ensures that the FZO L line is unasserted. This line is asserted by the DC339 logic
during initial SBC power-up. After the check is complete, the logic sequencer enters the QBWT state,
causing the write two-port RAM line, WTPDR L, to become asserted, enabling the transfer of data into
the two-port RAM. On the next CLK71 transition, the reply signal TRPLY L output asserts and latches
the XDAL data into the TPR registers. The next transition of CLK71 forces WTDPR L to unassert. The
sequencer waits until either SMATCH H or RDIN H is unasserted by the Q-Bus device. Either forces all
sequencer outputs to the unasserted state. The sequencer now returns to the initial state.

3-20

3.9 INTERRUPT CONTROL GATE ARRAY (DC339)
The DC339 chip is an 84-pin gate array used to provide a compatible interface between the T-11
microprocessor and the direct memory controller (DTC). Figure 3-18 shows the DC339 input and output
signals.

r,: - -:E:,T--,
21

CONTROL

/: o--:-~DY-:'

'?llD

~p I
/ - . --/--11

L_o~g

_ _j

MR-11754

Figure 3-18

Interrupt Control Signals

3.10 INTERRUPT CONTROL
The interrupt control logic provides asynchronous wait state (READY H); interrupt and exception
handling; address, read and write strobes; bus DMA arbitration control; and external/internal vector
cycles.
3.10.1 Interrupt Hardware
The KXT 11-CA interrupt control design (Figure 3-19) includes the following elements.
1.

Seven interrupt lines that are latched.
a.
b.

c.
d.
e.
f.
g.
2.

UPDRQ
RTCRQ
RQ 134
RQ 130
RQ 120
RQ 124
RQ 104

SLU2 interrupt request
Real-Time clock 50- or 60-Hz interrupt request
Two-Port RAM request
Q-Bus interrupt register request
Two-Port request
Two-Port RAM request
Timer counter register request

A logic circuit containing five inputs that latches two lines.

b.
c.

d.
e.

RHALT
Q-Bus halt, nonmaskable level 7 interrupt
PFAIL
Q-Bus power-fail, nonmaskable level 7 interrupt
QBRESET Q-Bus reset, nonmaskable level 7 interrupt
BREAK
Console user selectable nonmaskable level 7 interrupt
RI NIT
Q-Bus initiate interrupt request

3-21

Thirteen interrupt synchronizing latches, that latch the following signals.
a.
b.
c.

Outputs of the seven latches described previously
Two outputs, from the logic circuit described previously
Three interrupt signals:
(1)
(2)
(3)

ZCIORQ
DLRRQ
DLXRQ

DMARQ

Counter Pl/O timer interrupt request
Console receiver interrupt request
Console transmitter interrupt request

Direct memory request interrupt

~Al7L

BREAK H

PFAIL H

~Al6L
~Al5L
~Al4L

SBCOP L ~

hA13L

BRO 140 H
RESET H

ORESETOC L ~

"'- A12L

OMARQ L ~

h_ All L

ZCIORQ L ~

:: AIO L

UPORQH

~AK134 L

.....

OLXRQH ~

CLRRS H

~AK130 L
~AK124 L

RQ134 H
RQ130 H

h_AK120 L

RQ124 H

.....

R0120 H
RQ104 L ~
TOAL12H ~
TOAL 11 H
TOAL 10 H
TOAL 09 H
TOAL 08 H
CAS L _...,
~

MR-11753

Figure 3-19 Interrupt Control Simplified Block

The operation of the KXTI 1-CA interrupt control centers around eight microprocessor input lines, AIO to
Al7, driven by interrupt signals, either directly or indirectly, through the DC339 gate array.
•

AIO is the DMA request line connected directly to DMRQ.

•

All to AI4 are driven by the output of the interrupt encoder to request maskable interrupts.

•

AI5 is driven by the VEC gate which detects the presence of an externally generated vector on
the outputs of the interrupt encoder. It calls for a vector read transaction from the bus.

•

AI6 is ORed between the power-fail and Q-Bus input lines to force a power fail interrupt.

•

Al7 is ORed between the halt and break interrupt lines to force a restart trap.

3-22

The microprocessor reads the AIO to AI7 input lines and arbitrates the interrupt priority according to
Table 3-1. In addition, the state of All to AI5 is reproduced on TDAL 12-8 lines during the acknowledge
cycle. TDAL 11-8 lines are used to decode the interrupt acknowledge. TDAL 12 reflects the state of the
VEC L signal: asserted VECT L for external interrupts; unasserted for internal interrupts.
The interrupt logic (Figure 3-1, Sheet 1) receives interrupt requests from interface devices and applies
them to the microprocessor. The microprocessor will acknowledge the highest priority interrupt if its
priority is higher than the current microprocessor status word priority. There are 16 interrupts available,
and either one or all can be active at the same time. Four interrupts become active for low going signals,
and the remaining 11 become active for high going signals. Three of these inputs are ORed to produce one
level 6 request, and two other interrupts are ORed to produce one latched level 7 request. Five of the

Table 3-1

Designated Interrupts

Coded Input Vector
AI-1
AI-2
AI-3
AI-4
AI-5
TDALS TDAL9 TDALlO TDALll TDAL12

Interrupt
Source

Priority
Signal

Level

Halt/
break

HLTRQ/
BREAK

Nonmaskable

Restart
address

DMA
request

DMARQ

Nonmaskable

DMA

Power-Fail/
QB reset

PFAIL/
BINIT

Nonmaskable

Real-Time
clock

RTCRQ

Counter
timer

RQ104

Two-Port
RAM

RQ120

Two-Port
RAM

RQ124

Two-Port
RAM

134

QIR

RQ130

SLUl
receive

DLRRQ

SLUl
transmit

DLXRQ

SLU2

UPDRQ

104
0

120
124
134

130

60
64

0
0

3-23

100

remammg 10 interrupts are latched and stay active until reset. The 12 enabled interrupts are clocked
through internal flip-flops by BCAS L asserting during the present microprocessor transaction. These
outputs are used to produce an encoded vector. The vectors are enabled by the PIH ·input of the present
transaction.
The interrupt codes and their priority levels are listed in Table 3-1. When the PI H output is asserted, the
microprocessor looks at the interrupt inputs and initiates an interrupt acknowledge (IAK) transaction for
any interrupts with correct priority following completion of the current microprocessor instruction. The
microprocessor coded input is placed on TDAL bus bits 8-12. Each TDAL bit is listed with its proper AI
interrupt code input in Table 3-1. These five TDAL bus bits are inputs to the acknowledge decoder that is
enabled when the microprocessor starts an IAK transaction which occurs after an IAK input becomes
active. These inputs are decoded to determine which interrupt was acknowledged and outputs a low to
negate the interrupt request. SLU 1 transmitter and receiver interrupt lines are reset by wire ORing and
asserting the acknowledge decoder output low. TDAL 12 represents the state of the VEC L input when the
microprocessor acknowledges the interrupt: a low for external interrupts and a high for internal interrupts.
The signal is used to determine if an external vector interrupt acknowledge must be initiated.
3.10.2 Ready Logic
The ready logic (Figure 3-20) provides the microprocessor READY input and is used to control the
microprocessor cycle slip function. The microprocessor cycle slips when the READY input is being pulsed
from high to low, while RAS L is asserted; the cycle slip function will be inhibited when READY H input
is set high. The pulsed READY H input causes the T-11 to slip one, four, or more cycles. Both cycle
function control lines, CSLIPl L and CSLIP4 L, are outputs of the memory address decoder. These
signals are initiated by either the T-11 or DTC chips with the DC339 encoding the control signals. For any
cycle slips to occur, the following five lines with proper states must be present.
1.
2.
3.
4.
5.

DPRDY L is unasserted (high), indicating the two-port RAM is not being accessed.
EIAK L is unasserted (high), indicating no external interrupt acknowledge is being serviced.
RQTM Lis unasserted (high), indicating no timeout request is being serviced.
SELO Hand SELl Hare unasserted (low), indicating no direct memory grant was given.
RAS L is asserted (low), indicating a read operation.

CSLIP1 L
CSUP4 L

READY H
READY H

CSDTC L
Pl H
COUTH

INTERRUPT
CONTROL

MICROPROCESSOR

Tl 1

IDS L
DPRDY L
RQTM L
RAS L
SELO H
SEL1 H

ZAK L
CAS L

Figure 3-20 Ready Logic

3-24

During normal operations one T-11 cycle slip occurs for the T-11 interface with SLUl, SLU2, or the
counter/timer chip. When PI Lis asserted and clock COUT goes from low to high, the READY line goes
from high to low. This high-to-low transition of the READY line is ORed. The other OR gate input
ensures gating of the READY line during any OTC interrupt acknowledge or at the beginning of a CAS L
strobe. This is due to the DTC operating at double the T-11 speed. The high-to-low gate output transition
causes the T-11 to slip one cycle.
Before the next low-to-high transition of COUT H, PI H becomes unasserted, causing the READY line to
go back to a high.
For four cycle slips to occur, the OTC chip select (CSDTC L) and cycle slip (CSLIPl L) lines must be
asserted, while CSLIP4 L remains unasserted. During assertion of data strobe (IDS L) and a low-to-high
transition of the clock line (COUT H) into the DC339, the READY line begins to pulse. After the fourth
READY transition the READY line remains high, inhibiting any more T-11 cycle slips to occur.
Multiple cycle slips occur when the two-port RAM (DPRDY L) line remains unasserted with cycle slip
(CSLIPl L) and (CSLIP4 L) lines both asserted. When this happens, each low-to-high transition of the
clock (COUT) line into the DC339 causes the READY line to pulse low. This low causes the T-11 to cycle
slip once. READY line pulsing stops when the two-port ready line becomes asserted (DPRDY L).

3.10.3 Restart Interrupts
The restart interrupts (Figure 3-21) are defined as BREAK Hand RHALT H going to the microprocess01
AI7 input. RHALT H is a bus arbiter command and BREAK H is a console command. The restart
interrupts are developed in gate arrays DC339 and DC340. DC340 outputs RHALT Has BRQ140 Hand
is applied as an input to DC339.

BREAK H
CAS L _,..
i,.,._ Al 7 L

SELO H ""

I"'

SEL 1 H
Pl H
ZWRITE L,..

INTERRUPT
CONTROL
(DC339)

BRQ140 H-...

RHALT H
DC340

CLRRS H

i----

r---

RESET H

1
MR-11751

Figure 3-21

Restart Interrupts

During a reset, the logic associated with both restart interrupts are reset. The restart interrupt output line
AI7 Lis unasserted high.
During normal operations, BREAK Hand RHALT H remain unasserted. If either line becomes asserted
due to a restart interrupt, the interrupt is clocked out on line AI7 L when CAS L is asserted. The interrupt
is read into the T-11 at the leading edge of PI H, causing a nonmaskable level 7 interrupt. During this
interval the CLRRS H line is unasserted. CLRRS H becomes asserted after the interrupt has been read
into the T-11. To ensure that an interrupt was not cleared before it was read into the T-11, four lines -

3-25

SELl H, SELl L, ZWRITE, and PI H - control the CLRRS H line. The CLRRS H line is asserted after
SELO H and SELl H are unasserted, indicating the T-11 is in control of the bus (no direct memory grant);
ZWRITE Lis unasserted, indicating that a T-11 read has been done; and PIH is asserted indicating an
interrupt read has been done by the T-11. When all these conditions are met, CLRRS H asserts. This line
clears the restart interrupt logic and resets the AI7 L line to the unasserted state.

3.10.4 Power-Fail (PFAIL)
The PFAIL H output is connected to microprocessor AI6 input and is recognized as a power-fail
nonmaskable interrupt (Figure 3-22). When acknowledged, the microprocessor traps through octal address
24 to access the PC and the PSW for a user's power-fail routine. It is suggested that user power-fail
routines should set the PSW to 340 to prevent other interrupt requests from disrupting the power-fail
routine. During a reset instruction the power-fail logic is reset.
CAS L_,,
SBCOP L~
PFAlL H ""I
QRESETOC L ~

IAS L _,.,
RINIT H,,,.

n_ Al6 L
I""

""I

IR/WLB L ;
IDAL01 H

INTERRUPT
CONTROL
(DC339)

OBUS
RESET

IDAL 10 H

MR-11750

Figure 3-22

Power-Fail Interrupt

The input lines for the AI6 L interrupt are SBCOP L, PF AIL H, and RINIT H. The inputs are used
differently depending on which mode the board is operated in. In the standalone mode, SBCOP L asserted
when the SBC ID switch is placed in the standalone position. This low inhibits the PFAIL H line from
initiating a Q-Bus power-fail interrupt. In the peripheral processor operating mode, the PFAIL H asserts a
minimum of 9 ms before loss of Q-Bus de power. This signal allows an orderly KXTl 1-CA power-down
sequence thereby minimizing erroneous microprocessor cycles. The RINIT H line enables the SBC to
detect Q-Bus resets. When a Q-Bus reset occurs with the reset detect function enabled, QRESETOC Lis
asserted. For additional details about QRESETOC L, see Paragraph 3.9. In addition, RINIT H can still
detect Q-Bus resets and cause AI6 L interrupts even though the board is terminated to a Q-Bus backplane
but operating in the standalone mode. If the board is not terminated to a Q-Bus backplane, the RINIT H
line can be externally wired and controlled. When externally controlled, the bus initialize bit in control
status register D must be enabled. See Chapter 5 for the bit enable information. If the bit is not enabled,
the RINIT L line is inhibited. When both RINIT H and PFAIL H are inhibited, no AI6 L interrupts are
detectable.
In the Q-Bus mode after a power-up or reset instruction is performed, all power-fail interrupt input lines
become unasserted. A power-fail interrupt is generated upon detection of either PF AIL H or RINIT H
assertion. When either line is asserted, CAS L latches AI6 L interrupt low. The AI6 L low is read into the
T-11 during assertion of PI H.

3.10.5 External Vector Cycle
Two devices can generate an external T-11 interrupt vector. They are the OTC and PI/O counter timer
chips. An external vector cycle starts when one of these devices generates an interrupt that is driven onto
interrupt lines All L-AI5 L. During the next microprocessor read cycle, this interrupt request data is

3-26

strobed, when PI His asserted, into the microprocessor. This assertion indicates to the microprocessor that
an externally generated interrupt vector address is to be read in. The microprocessor now performs an
external IACK transaction. The interrupt request address (All L-AI5 L) is output on TOAL 8-12 when
SEL l H is asserted. The microprocessor asserts RAS L, enabling the interrupting device to drive the
external vector onto TOAL bus lines. The external vector is read into the microprocessor when RAS L
goes unasserted. During an external IACK cycle, one microprocessor cycle slip occurs, and ZAK L is
asserted, due to the relative faster speed of the external interrupting devices.

3.10.6 Internal Vector Cycle
An internal vector cycle occurs when the interrupt control logic receives an internal interrupt request. The
request is encoded and driven onto interrupt request data lines All L-AI5 L. Request data line Al5 L
(VECT L) is unasserted for internal interrupt vectors. The interrupt request data is strobed into the
microprocessor during PI H assertion. The microprocessor reads the encoded interrupt request data lines
(TOAL) and points internally to the requested internal interrupt vector address. The microprocessor
performs an JACK transaction by driving encoded request data onto TOAL lines 8-12 enabling the
interrupting device to be reset.
3.10.7 DMA Request/Grant
The DMA request is connected to the AIO input to the microprocessor. The OMA request is received by
the microprocessor during any read, write, fetch, or ASPI transaction. A request is not acknowledged by
an IAK transaction, but is acknowledged by the microprocessor, asserting both SELO and SELl outputs to
initiate a OMA grant. (See Paragraph 3.15 for a discussion of OTC operations.)
3.10.8 End Of Pass (EOP)
The end of pass (EOP L) signal, when asserted, stops all OMA operations which are in progress. (See
Figure 3-23.) The EOP logic is reset when SELO H and SELl Hare asserted and monitors several SBC
functions centering around OMA operations using the Q-Bus. An EOP L assertion occurs for the
following.

SEL 0 H
SEL 1 H
t--._ EOP L

ROTM l--""

....,

I"'

RQDC 10 H
MYBUS H
DIDO l

CSDTC L ~
ZDS l

=:l

DC339

SBCOP L ~
SQBH ~

PFAILH
BDCOK L 1 '
BINIT l ;

.....

MA-11749

Figure 3-23

End of Pass (EOP) Logic

3-27

The OTC tries to address a local nonexistent memory location (RQTM L asserts).

A OTC request for the Q-Bus is not granted in less than 10 us. Request for the bus RQDClO H
is asserted, ownership of the bus has not been granted, MYBUS L is unasserted, and both data
strobes DIDO L (output) are unasserted.

OTC has local bus control and tries to address its own internal registers. This condition exists
when CSDTC Land ZDS L occur together.

When in SBC mode (SBCOP L asserted) and a Q-Bus address is referenced (SQB H asserts).

When a Q-Bus address is referenced during a Q-Bus power-failure (PF AIL H asserts), Q-Bus
power-down sequence (BDCOK L unasserts), or a Q-Bus initialization (BINIT L asserts).

OTC references to a Q-Bus address and no response from the Q-Bus is received in less than 10
µs. The data in/data out signal DIDO L asserts for a Q-Bus read/write cycle and starts the 10
µs count clock.

3.11 ADDRESS LATCH
The address latching logic (Figure 3-1, Sheet 1) has 16 transparent latches. The output is always enabled.
New incoming TOAL data becomes address bus lines ADBO 1-15 during the leading edge assertion of
ddress strobe IAS L. The address bus goes to the logic sequencer and memory address decode logic. The
address bus is common to on-board memories, remaining stable during assertion of address strobe IAS L.
3.12 MEMORY DECODE
The memory decode logic has two field programmable logic arrays (FPLA) that decode applied address
bits and three memory map bits. The memory map bits can be jumpered providing eight memory maps,
shown in Chapter 6, for the user. The FPLA is enabled when the disable decode line DISDE H is
unasserted. Signal DISDE His asserted, and the FPLA output is inhibited during Q Bus operations. The
address lines ADB01-ADB15 come from the address latch .
. 3.13 RAM MEMORY
The static RAM memory (Figure 3-24) is a 16 K X 16-bit memory that has two 8 K X 8 high byte chips
and two 8 K X 8 low byte chips. The memory is selected by assertion of CSRAMI Land CSRAM2 L
inputs going to pin El. The memory is addressed by bits ADB01-ADB13, and 16-bit data is read from or
written to via TOAL bits 00-15. The IR/WLB L assertion selects read/write operations for a low byte,
and IR/WHB L assertion selects read/write operations for a high byte. The write inputs go to the OE
input pins.
The user can supply the static RAM memory with +5 V battery backup. The user must supply +5 V to
SBC pin AVI and install the battery backup jumper between two jumper posts. See Chapter 6 for detailed
information.
3.14 USER MEMORY SOCKET SITES
The RAM/ROM memory (Figure 3-25) provides the user with two 28-pin sockets to accept either 24-pin
or 28-pin standard +5 V chips. The sockets can hold either EPROMs, PROMs, RAMs or +5 V only
EEPROMs. There is a high byte and low byte socket. Both sockets use the CSKTA L output from the
memory address decode as chip enables. (See Chapter 6 for memory maps.) The IR/WLB L, IR/WHB L,
and the IREAD L signals from the DC339 are used to produce a high byte read/write and a low byte chip
read/write. There are 15 jumper posts available for memory configurations.

3-28

TOAL 00 H-07 H

14
IR/WLB L
IREAO L

SK XS

CSRAM1 L

TOAL 00 H- 07 H

SK XS
TOAL OS H-15 H
AOB 01 H-AOB 13 H
TOAL OS H-15 H

14
IR/WHB L
IREAO L

SKXS

CSRAM2 L

TOAL 00 H-15 H

SKXS

MF'-11748

Figure 3-24 RAM Logic

+5.0V 0 M70

+5.0 V BU O M57

CSKTA L

2S i--.---+----o M69
20

i-----Mn56 M~5 +5.0 V

271--1----+---

26
23i--......,I--'

PORAM LO

M53

2S
PIN
SOCKET

M54

----o
AOB14 H M52

CSKTA L

AOB12 H M5S
-----o

27 - - - - - - M o 6 7 Mgs +5.0V
26

AOB00-13 H

UOAL 00-07 H

IR/WHB L M60 M59
-----<O
u---~

23
2S
PIN
SOCKET

I R/WLB L M65 M64

-----o

AOB12 H M63

MR-12018

Figure 3-25

User Socket Sites

3-29

3.15 NATIVE FIRMWARE SOCKET SITES
The native firmware sockets sites (Figure 3-26) can accommodate 24-pin 4 K X 8, 28-pin 8 K X 8 PROMs
or additional 24- or 28-pin RAMs with battery backup. Native firmware PROMS control the power-up
selftest, device initialization, program booting, program loading, system primitives, and diagnostics. Local
address decode logic allows only 3 Kw of the 4 Kw portion of this PROM above 160000 (octal) to be
directly mapped into the memory space at any one time. So, to use the last 1 Kw portion, the lower 1 Kw
portion can be overlaid with the last 1 Kw portion of PROM. KXTCSR A, the local status control register,
controls the overlay bit. See Chapter 4 for detailed information.
Both sockets use the CSKTB L output from the memory address decode for chip select. In addition,
IREAD L signal from the DC339 is used to perform reads of the PROM.

28
PIN
SOCKET
ADBDO-ADB13 H

28
llDAL00-07 H

PIN
SOCKET

CSKTB L
IREAD L

MR-12022

Figure 3-26

Native Firmware Socket Sites

3.16 DTC OPERATIONS
The direct transfer controller (OTC) is a 16-bit OMA controller addressable by the local microprocessor as
an 1/0 device. See Figure 3-27 for OTC control signal lines. The OTC supports two channels and performs
data transfers, using OMA operations, between any local 16-bit address and any 16-, 18- or 22-bit Q-Bus
address. Word, high byte, and low byte data transfers are supported locally. Only word data transfers are
supported across the Q-Bus.
The OTC has the ability to load its control parameters from memory in a chaining sequence. During a
chaining sequence the only operation the microprocessor must perform is to load a control parameter table
into the OTC channel and issue a start chain command. The OTC can operate independent of the
microprocessor except for an interrupt at the termination of the operation. In addition to transferring data,
~he OTC can compare data from the source device to the content of a pattern and mask register and then
notify the microprocessor when a match or no match occurs.
OMA operations can be interleaved between the T-11 and both OTC channels, or they may occur in
various burst sizes. Channel A or B can be used to service hardware requests from SLU2 channel A
(transmitter and receiver) or from the PI/O timer counter when transferring data via the serial port (Jl)
and the parallel port (J4).

3-30

STO

ZAK L

TOAL 00 H-TOAL 15 H

2X 1
STl
MUX ,__S_T_2__.

OMG L

SQB H

ST3

Q310P H

ZWRITE L
EOAL 16 H-21 H

OTC

OMG L
CSWTOTC L

ZBW L

ZAS L
RQPB L M49
ZOS L
O
M48
OREQB L OM 47 ~--------f
OREQA LO
M51

M50

OMARQ L
ZCTORQ L
ZCIEI H

EOP L
CLK285 H

MR-11747

Figure 3-27

DTC Control Signals

3.16.1 Flowthrough Transactions
Data transfers are performed in a two-step sequence called flowthrough transactions, where a source is
read and a destination is written. The data is held in a temporary register between the source and
destination portions of the transfers. The DTC can perform three types of transfers: local, Q-Bus, and l/O.
3.16.1.1 Local Transfers - Local data transfers occur between two on-board memory locations. (See
Figure 3-28.) Local transfers are initiated by the microprocessor when the DTC chip select line
CSWTDTC L is asserted, and the read/write line, ZWRITE L, is selected, unasserted for a read or
asserted for a write. Since the DTC is neither doing a vectored acknowledge (ZAK Lis unasserted) nor has
it received a direct memory grant yet, DMG Lis unasserted, forcing the output of the 4 X 2 multiplexer to
all lows. This indicates an internal DTC operation is being done. In addition, the DTC is currently a local
bus slave, forcing both ZAS Land ZDS L to be DTC inputs. When the address on the TDAL bus is valid,
the microprocessor asserts the address strobe ZAS L. The byte/word output is active (ZBW L) indicating
that a word, high byte, or low byte operation was selected. Next, the data to be transferred is driven onto
the TDAL bus and when valid, the microprocessor asserts the data strobe ZDS L line. This strobes the
data into the DTC. After the data is stored in the temporary DTC registers, the DTC asserts DMARQ L
to request local bus mastership.
ZAK L
TOAL00-15
OMG L

4X1
MUX

ZWRITE L

OTC

OMG L
CSWTOTC L
ZAS L
ZOS L
EOP L
CLK285 H

MR-11746

Figure 3-28

Local DMA Control Signals

3-31

The microprocessor responds via the DC339 gate array by asserting the memory grant line DMG L. The
DTC now is master of the local bus. Control lines ZAS L, ZDS L and ZWRITE L become outputs to the
local bus. First, ZAS L asserts when the address is valid, then ZDS L asserts, indicating valid data is
present on the bus. Finally, ZWRITE L asserts if a write to the bus is being done. At the end of the
transfer. the DC339 logic asserts the end of pass EOP L line. This input into the DTC terminates, causing
DMARQ L to go unasserted and forcing the microprocessor to remove the grant (DMG L). The DTC is
once again a local bus slave and the microprocessor is local bus master.

3.16.1.2 Q-Bus Transfers - Q-Bus DTC transfers are similiar to local transfers in that the DTC must
acquire mastership of the local bus exactly the same way. See Figure 3-29 for the Q-Bus transfer control
signal lines. After acquiring the local bus, the DTC must request and then acquire mastership of the Q-Bus
via DCO I0 operations. To initiate the DCO I 0 operations, SQB H asserts. Once the DCO I 0 acquires bus
mastership, the DTC performs the requested transfer via the SBC's XDAL bus transceivers (see Figure
3-1, Sheet 2). If the Q-Bus 1/0 device is addressed, the device address is located in the top 4 K of memory.
To address these devices the DTC asserts QIOP H line. When addressing 18- or 22-bit Q-Bus addresses,
the EDAL 16-22 lines are used. At the completion of the transfer, lines SQB H and DMARQ L unassert.
Unasserted SQB H terminates DCO I 0 operations and returns bus control back to the bus arbiter.

ZAKL
TDAL00-15

4X1
MUX
DMG L

ZWRITE L

OTC

OIOPH

DMGL
CSWTDTC L
EDAL 15-21 H

ZAS L
ZDS L
EOP L
CLK285 H

MR-11745

Figure 3-29

Q-Bus DMA Control Signals

3.16.t.3 1/0 Transfers - Both channel A and B of the DTC support hardware DMA requests. See
Figure 3-27 for DTC control signal lines. The hardware requests can be from three sources: PI/O counter
timer and SLU2 channel A for both receiver and transmitter. The DTC hardware requests from SLU2 are
DREQA L for the transmitter and DREQB L for the receiver. In addition, the DTC hardware request
from the counter timer request line is RQPB L. Requests DREQA L and RQPB L can by jumpered to
channel A of the DTC. All three hardware requests are maskable. See Chapter 5 for details on masking.

3.16.2 Exceptions
Flowthrough transactions are operated on by the DTC until a terminal count is read or an end of pass
(EOP L) signal is received. This low-going signal terminates the activity of the active channel. If neither
channel is active, the EOP line is ignored. The signals used to develop EOP are breifly described below.
The EOP signal is developed in the DC339 gate array logic. For more details pertaining to EOP signal, see
Paragraph 3.8.1.7.

3.16.2.1

Timeout - When the local timeout request line RQTM L asserts, the EOP L line asserts. This
returns control of the local bus to the microprocessor.

3-32

3.16.2.2 SBC Mode - When operating in the SBC mode, anytime the DTC tries to read or write to
Q-Bus address an EOP L assertion will occur.
3.16.2.3

Power-Fail - When a Q-Bus power failure occurs, the EOP L line asserts. This enables the
microprocessor to regain control of the local bus so an orderly power-down cycle occurs.

3.16.2.4

Bus Initiation - When the DTC is in control of the local bus and a Q-Bus initiation occurs, the
DTC responds by returning control of the local bus to the microprocessor. The microprocessor controls the
local bus for the duration of the bus initiation.

3.16.2.5 Bus Halt - When a Q-Bus halt occurs and the DTC is in control of the local bus, the DTC
operations do not stop. The RHAL T L line assertion is read into the microprocessor's interrupt line,
causing the microprocessor to trap to the restart address.
3.17 SERIAL I/O UNIT
The KXTl I-CA SBC has three serial line units (SLUs) which operate via three 1/0 ports. SLUI operates
over a I 0-pin 1/0 port, J3. SLU2 consists of two channels: channel A operates over a 40-pin 1/0 port, JI,
and channel B operates over a I 0-pin 1/0 port, J2.

3.17.l

Serial Line Unit l (SLUl)

SLU I is driven, as shown in Figure 3-30, by the DC3 l 9 DLART (DL compatible asynchronous receiver /transmitter) chip. The DC3 J9 chip has a programmable output baud/second rate, either software or
hardware Uumper) selectable. See Chapter 5 for the DC3 J 9 software programmable register control
information; Chapter 6 contains hardware baud/second rate jumper selections. The hardware selectable
baud rates are from 300 to 38.4 K baud/second in eight steps. If neither hardware or software baud rates
are selected, the DC3 J 9 chip powers up to a default baud rate of 300.

BRCLK H
DC319
SLU1

RDLDAT H

J3
(10PIN)

M5
M4

RDLDAT L

::st ::: ::~o

M81

BRS1

M74

M73

M72

M71

BREAK H

MSO

0-M79

BRS2

81---~

'-----f4

RS423
M43
DRIVER XDLAT H
M41

M42

...__....

RDLDAT L
RDLDAT H

Figure 3-30

SLUl Transmit/Receive Configuration

Outgoing serial data transmitted by the DC319 (DLSO) is inverted and is driven by two transmitter
drivers. One driver provides compatibility for differential (EIA RS422) transmission and the second driver
provides compatibility for single-ended (EIA RS423) transmission. In addition, an external real-time clock
output from DC319 (BRCLK) is provided for transmission. The real-time clock output rate is 76.8 KHz.

3-33

Serial data coming in on the DC3 I 9 can be supported for either single-ended or diffcrential input
conditioning. The incoming serial data is received on J3 pins 7 and 8, A sirtglc jumper is installed for
differential receiver operation and no jumper is installed for single-ended operation. Sec Chapter 6 for
jumper details.

3.17.2 Serial Line Unit 2 (SLU2)
SLU2 is driven by a two-channel multiprotocol serial controller (UPD 7201). Local data transfers to/from
the controller and TDAL bus are in parallel form; 1/0 port data transfers between the controller and
drivers are in serial form. These transfer protocols are for both transmit and receive operations. Simultaneous operation of both channel A (see Figure 3-31) and B (see Figure 3-32) is possible, each capable of
supporting asynchronous or synchronous communications .

..-----------------------------------------124

..-----------------------------------------17

..-------------------------------------~35

TT103A L 6

M15

Mt14

...._,

~~_,~
+

..._DREOA L
~

(40 PIN)

,_____.__-lv
RECEIVER

~ l

~v;ECEIVER>--~

.___

r-<' M~
M17

RS422 k. TT103A L
DRIVERS
RSA H

,--~""'-------! ~ECEIVER

TT103A H

31
23
.___,
1---="'-'--t 32
RSA L 13
'-=R.,,..,S4"'°'22,..._.
DRIVERS

~;;.CO--'-R""SA"'"'-H---f

r:~AH
Mt12

....___....1----l

r-+-1

TX~

M13

I*
I

TT103A L

;oo.-.~~

TT104A H ~
TXCA ~
FCL ~
DML ~

RS423 I
DRIVERSl----J
1-----T'R=SA"'-'H--t 18

SLU 2
CHANA

~~_,

1:0~0~
~~--~

'"4X2
MUX

TT114A H
SYNMA H

TXCAHj

1--'

t---

~TT115AH

I--

_ _ . _ _ - I v SYNMA H

'--------------------~14

'-----------------------t37
'-------------------------112

'------------------------138

~+---t,__---t--------------------------------l8

----t---+----+---------------------------------t15
----t----------------------------------417
'----------------------------------422
20
MR·11743

Figure 3-31

SLU2 Channel A Receiver

M36

M35

n ~"

ADB01 H

4X 2 MUX

RS423
DRIVER

TT1148 H
SYNMB H
DREQB L

v
M34

M33

TXCB H

ITXC9

SYNMB H
TT115BH

M29
SLU2
CHAN B

I M~

(PARTY LINE)
PN1360 DRIVER

IREAD L

M27

SEND H

R1360 EN L
M46
_f\

6
5
7
8

M44
BCLK250 H
M45 RXCB

R1360 H

M28

IEWLB L

TT1048 H

J2
(10 PIN)

2
TT1038 L

CSUPD L
M38

wI
w

0
M31

M26

(PARITY
LINE)
PN 1360
DRIVER

I I M40

M39

R1360 H

MR-11742

Figure 3-32

SLU2 Channel B Transmitter/Receiver

Chip select line CSUPD L must be asserted for all controller operations. The controller is driven by a
7-MHz clock signal (BCLK250 H). During SBC power-up the INIT L signal is asserted. This disables both
channel A and B outputs and clears all the internal controller registers. The native firmware writes into
these registers at the end of the power-up cycle. After this is complete, signal ADBO I H selects either data
or control transfers - a high for control and a low for data. Signal ADB03 H is used to select either channel
A or channel B operations. An asserted ADB03 H selects channel B and an unasserted ADB03 H selects
channel A. Assertion of the IREAD L signal transfers data out onto the local TOAL bus, and assertion of
IEWLB L transfers control parameters into the controller. See Chapter 6 for more details on configuring
channels A and B.

3.17.2.1 Channel A -The transmit inputs consists of eight parallel TOAL bus lines (TOAL 00-08 H), a
clear to send CSA L, and a transmit clock rate. The TOAL bus lines are used to transfer data to the
controller in parallel form. CSA L can be used as a transmitter enable sent by the receiver at the opposite
end of the communication link. The transmit clock rate is used to clock outgoing transmitter data. The
transmit clock rate is software programmable for either local or remote clock via a 4 X 2 multiplexer. One
multiplexer input is tlie programmable timer output (TXCA H) and the other is the received clock rate
(TT114A H) output. The multiplexer output is controlled by the software programmable line, SYNMA
H. A high selects TTI 14A H and a low selects the programmable timer output, TXCA, for data
transmissions.
The output serial data {TT! 03A L) is inverted and applied to both RS423 and RS422 driver inputs. Both
driver outputs are wired to 1/0 connector J l. The request to send RSA H is also inverted and is applied to
both RS423 and RS422 driver inputs. The outputs are wired to connector J l. The user must wire the J l
cable for either RS422 or RS423 transmission, depending on the application. The OMA request line,
DREQA L, is used as OMA interrupt input to the local OTC.
The channel A receiver consists of a serial receiver input and a receiver clock signal. The incoming serial
data {TT104A H) can be jumpered for either RS422 or RS423 reception through the receiver driver. The
receiver clock rate is software programmable for either a local or remote receiver clock via a 4 X 2
multiplexer. One input to the multiplexer is a programmable timer output, TXCA, and the other input is a
received clock, TTl l 5A H. The multiplexer output is selected by the SYNMA H signal. A high into the
multiplexer selects TT115A H and a low selects the programmable timer output, TXCA, for data
reception. The receiver output is driven onto the TOAL bus in parallel form.

3.17.2.2 Channel B - The transmitter inputs consists of 8 parallel bus (TOAL 00-08 H) data lines, an
incoming call {IC L), and a receiver clock rate. The TOAL bus lines are used to transfer data to the
controller in parallel form. The incoming call, IC L, is used as a channel B receiver enable signal. The
receiver clock is software programmable for either local or remote receiver clock. Receiver clock rate,
TXCB, is selected via a 4 X 2 multiplexer. One input of the multiplexer is a programmable timer output,
TXCA H, and the other input is the receiver clock rate output, TTI l 5B L. The multiplexer output is
selected by SYNMA H. A high selects TTl l 5B L and a low selects TXCB as the clock.
The transmitter outputs are serial data {TT103B L) and party line enable (SEND H). The transmitter
output is inverted and is applied to all three output drivers: RS422, RS423, and party line. The user must
jumper in the proper transmitter driver for the application. If the party line is jumpered in, enable signal
SEND H must be asserted. The serial data is transmitted via 1/0 connector J2.
The channel B receiver input signals are serial data, data mode carrier detect (OM L), and receiver clock
rate. The user must jumper the receiver input line for either RS422, RS423, or party line receiving.
Carrier detect (OM L) can be used as a receiver enable sent by the receiver at the opposite end of the
communication link. The receiver clock is software programmable for either a local or remote receiver
clock. The local receiver clock is the programmable timer output, TXCB, and the remote clock is the

3-36

transmitter output, TTl 158 H, from the opposite end of the communication link. The local and remote
clocks are fed to a 4 X 2 multiplexer. The multiplexer output is selected by signal SYNMA H. A high
selects TTl 158 H and a low selects TXCB for data transmissions. The receiver output is driven onto the
TOAL bus in parallel form.

3.18 PARALLEL 1/0 UNIT
The parallel 1/0 port is implemented with the 8036 counter/timer (ZCIO) chip and connects to the user's
interface through 1/0 connector J4. (See Figure 3-33.) The 1/0 buffers are capable of providing high
impedance inputs, with 600 m V of hysteresis and either passive internal pull-up driver outputs or TTLcompatible driver outputs. The ZCIO chip configures port A buffers, in nibbles, for either input or output
operation. In addition, each bit within a nibble can be configured for bidirectional operation. Port B is
configurable as an 8-bit port (two 4-bit nibbles) or as a bit port with the direction of each bit controlled by
the ZCIO chip. The four port C bidirectional lines can be individually configured as input or output bits
controlled by the ZCIO chip. See Chapter 5 for configuration details on the software programmable ZCIO
registers.

J4
PORT

TDAL 00-07 H)

-y

ZCIEI H;:

PORT
B
COUNTER/
TIME
PORT
p 1/0
B

-(:>o--

PORT
A

ZWRITE L ;
ZAKL;

-...

CSCIO L

TX/RX

'-+
/

40
PIN

TX/RX

,,~

.......

llDAL 00-07 H )
y

__,

LATCHES
CSBC
10~::3
I ASL
IR/W LBL

ZASL ~

ZDSL~

,_.
'>c~

.___
llDAL08-15H:> LATCHES
-y

TX/RX

MR-12019

Figure 3-33

Parallel 1/0 (PIO) Port Configuration

3-37

3.19 POWER-UP
The power-up logic (Figure 3-34) senses the application of +5 V power to the SBC and initiates a power-up
sequence. When the +5 Vis first applied, Cl charges up.·Before Cl is charged, PDRAM Lis unasserted.
This low is inverted twice through two inverters and becomes TPUP L. Asserted TPUP L inhibits the
NAND gate output, clears the power-fail flip-flop, and resets the RS flip-flop. The output of the AND
gate, PUP H, asserts, causing the microprocessor RESET L output signal to assert. The reset flip-flop Q
output, LDCLO H, remains unas.serted. The +5 V charges C 1 through RS until the threshold level of the
inverter is reached. This occurs at approximately 2.6 Vdc and 50 ms after +5 V was applied. TPUP L
unasserts high, enabling the unasserted GPFAIL H signal to preset the PUP/power-fail flip-flop to a high
on the Q output. This high combines with the unasserted PUP L to gate the NANO gate. The NAND
gate output, PUP H, goes low, enabling microprocessor operations. The SBC has successfully completed
power-up. The GPFAIL H signal prevents PUP H from negating until BPOK H asserts.
During normal peripheral processor operation, Q-Bus power signals, QDCLO Land GPFAIL H remain
unasserted. If a Q-Bus power-down sequence occurs, the first signal to become asserted is GPFAIL H.
After a minimum of 4 ms, the QDCLO L signal becomes asserted low. This low sets the power-fail to a
high. The high is inverted to a low, enabling Cl to discharge through R28. This low (discharge) PD RAM
L is inverted twice, supplying a low TPUP L line. T PUP L clears the PUP flip-flop to a low, resets the
power-fail flip-flop, then goes high. The microprocessor is forced to initiate a power-up sequence.
R5

+5.0V

PDRAM L

PUP

LSI
BUS
TRANSCEIVERS

L-----.J

LDCLO H

GPFAIL H

POWER
FAIL

Q
MR·11741

Figure 3-34

Power-Up (PUP) Logic

3-38

CHAPTER 4
NATIVE FIRMWARE

4.1 INTRODUCTION
The native firmware ROM programs are routines executed by the SBC on power-up (address 173000), on
receiving a console break or on receiving Q-Bus commands. ROM programs execute the selftests, initialize
Q-Bus interfaces, and perform processes that indirectly allow an application program to be loaded and
executed. In addition, ROM programs service various local events, NXM (nonexistent memory), HALT
(local), and B HALT (Q-BUS HALT). The KXTl 1-CA native firmware ROM listing is located in a
separate document. See Chapter 1 for document ordering details.

4.2 NATIVE FIRMWARE
The top 64 bytes of the native RAM are reserved for native firmware usage. See Figure 4-1 for the native
firmware location within any of the eight possible memory configurations. The user should not attempt to
address this portion of RAM, with the exception of the top two words which are the battery backup flags.
Any user data present in this space is altered by the native firmware. The firmware sets the stack pointer
to the RAM location directly below this reserved space before control is passed to the application code
(default user SP). Because this portion of the native RAM is reserved, the user sockets should be mapped
low if they contain RAM.
The native firmware interfaces with the following.
1.
2.
3.
4.
5.

Boot/Selftest switch (power-up)
Two-Port RAM command register
SLUl console serial ODT
LED display
Memory map selection

4-1

1K 1/0 PAGE

173777

1K 1/0 PAGE

2K NATIVE FIRMWARE
163777

1K SELF TEST OVERLAY

157777

2K NATIVE FIRMWARE
1K SELF TEST OVERLAY

---

----

4K
*
NATIVE
FIRMWARE
EXTENSION

NXM
137777

4K
*
NATIVE
FIRMWARE
EXTENSION

NXM
24

SK
SK
PROM/RAM PROM/RAM

RAM
117777

20
4K
PROM/RAM

107777
2K
PROM/RAM

100000

RAM

RAM
16K
PROM/RAM

RAM

F!AM

SK
PROM/RAM

NXM

4
4K
PROM/RAM

2K
PROM/RAM

MAPO

MAP 1

MAP2

MAP3

MAP4

MAPS

MAP6

MAP7

000

001

010

011

100

101

110

111

KXTCSRB

<3-1>

*NOT CURRENTLY SUPPORTED
**THE TOP 64 BYTES OF NATIVE RAM ARE RESERVED BY NATIVE FIRMWARE
MA-11673

Figure 4-1 · Memory Configuration Showing Native Firmware

4-2

4.3 BOOTSTRAP/SELFTEST SEQUENCE
The bootstrap sequence brings the SBC from an initial power.:up or reinitialized state to running user
application programs. Several native firmware routines are used. There are two entry points into the
bootstrap seqttence, power-up and reinitialization. Figure 4-2 shows the power-up sequence.
REINITIALIZATION
COMMAND

POWER UP

BOOT/SELF TEST
SWITCH SELECTION

INITIALIZATION

POWER UP
SELF TESTS

POWER RECOVER
(TRAP 24)

INITIALIZATION

BOOT
MA-11672

Figure 4-2

KXTI I-CA SBC Power-Up Sequence

4.3.1 SBC Set-Up Routine
After receiving a power-up or reinitialization command, the native firmware initializes the SBC hardware
control registers. The set-up routine disables all maskable interrupts and causes the two-port RAM (TPR)
to appear as all zeroes to any Q-Bus reads.
4.3.2 Initialization
The native firmware initializes the local I/O portion of the SBC. The following local devices are initialized.
1.
2.
3.

The direct transfer controller (DTC) chip (is first reset)
The serial driver for SLU2 channels A and B
The parallel interface device (PIO).

See Chapter 5 for more details on specific device register contents during reset and initialization.

4.3.3 Battery Backup
The native firmware must determine if the native RAM is provided with battery backup. The test for
battery backup consists of comparing the contents of two RAM locations for specific values. The values
are 125252 (octal) in the top word and 52525 in the word below native firmware. If provided with battery
backup, the microprocessor will trap to the power-up address (24). For details on native firmware detection
of battery backup, see the status register description in Chapter 5.

4.3.4 Selftests
The native firmware determines which, if any, selftests are to be executed. The boot/selftest switch is used
to select the mode of operation. A portion of the selftests are called the auto selftests. They are a subset of
the total selftest functions available. The auto selftests include the following.
·
I.

CPU test

RAM test, native and user (if RAM in user sockets)

ROM test, native and user (if selected)

Control status registers (CSR), nonexistent memory test of all native CSRs and TPR (read only
test)

DMA test, test of local DMA only transfers

If the RAM or native ROM tests fail, the SBC will not allow the application code to run and places the
SBC in a dead state, displaying a fatal error. The same happens if the TPR portion of the CSR test fails
when the SBC is in the peripheral processor mode. The reporting of any test failures is done via the LEDs
and the TPR. The test results are placed in TPR registers 2 and 3 at the completion of the auto selftests.
Register 3 is overwritten only if an error was encountered and contains the valid discrete error code for the
last test run that found an error.
4.3.5 Booting
Upon successfully passing the selftest routine, the boot/selftest switch is used to determine which booting
routine is to be used. The boot routine selects either booting application code from a ROM or a TU58
drive unit. If booting from a ROM is selected, the native firmware transfers control to that ROM code by
emulating a trap to location 24. When a TU58 drive unit is selected, booting is done via SLUI console 1/0
port Jl. Once the bootstrap begins receiving boot blocks from the TU58, receiving boot blocks from the
TU58, a comparison of the first byte to octal value of 240 to 277 is made. If a match occurs, then the boot
block is considered valid and all remaining blocks are transferred. If no match occurs, the bootstrap
continues to retry alternating between units 0 and 1.
4.4 COMMAND REGISTER
The (first) register 0 (local address 175000) in the two-port RAM (TPR) is called the command register
(Figure 4-3). Any time this register is written to by a Q-Bus processor, a nonmaskable restart interrupt
(173004) to the SBC is generated. This interrupt is serviced by the native firmware which interprets the
command sent.
There are three types of commands that can be sent from the Q-Bus arbiter to the command register:
control, selftest and ODT. For details on the bit definitions of the command register see Chapter 5.
The procedure for issuing any type of command to this register is as follows.
1.

2.
3.
4.
5.
6.

Test the status register for valid state.
Test the command register for zero.
If the command register is.all zeros, the SBC is not available.
Write the command into the command register.
Wait for the command register to be cleared.
Check the status register for a command error.

4-4

0 - BUS ADDRESS

LOCAL ADDRESS

BASE+ ID +36

175036 R/W

175034 R/W

175032 R/W

175030 R/W
SIGNAL LOCAL CPU ON WRITE
(LEVEL 5 VECTOR 134)

175026 R/W

175024 R/W

175022 RO
STATUS, WRITES TIMEOUT

175020 R/W
SIGNAL LOCAL CPU ON WRITE
(LEVEL 5 VECTOR 124)

175016 R/W

175014 R/W

175012 RO
STATUS, WRITES TIMEOUT

1---------------11 175010 R/W
SIGNAL LOCAL CPU ON WRITE
1---------------11 (LEVEL5VECTOR L 120)

175006 R/W

175004 R/W

175002 RO
STATUS, WRITES TIMEOUT

t---------------1 175000 R/W
BASE+ ID+ 00

SIGNAL LOCAL CPU ON WRITE
(NON - MASKABLE RESTART TRAP)
MR·12169

Figure 4-3

Two-Port RAM (TPR)

4.4.1 Control Commands
There are six control commands, described in the following paragraphs, that can be issued to the command
register by a Q-Bus device. The native firmware detects these commands and responds with a specific
function.
4.4.1.1 Trap Command (Bit 0 Set) - The trap command causes the firmware to emulate a trap routine.
The trap address must be placed in TPR register 2 using the PSW from TPR register 3. The native
firmware will trap to the specified address using the PSW. Just before the trap is started, the command
register (0) will be cleared acknowledging that the command is being done. This command is used in the
debug stage for testing trap handling routines.

4-5

4.4.1.2 DMA Load Command (Bit 1 Set) - This command causes the native firmware to perform a
chain load via the OMA controller (OTC). TPR registers 2 and 3 are used to pass data parameters that are
loaded into the chain control registers for channel l of the OTC. Register 2 contains the segment tag
parameter, and register 3 contains the offset tag parameter. After the data parameters are loaded into the
chain control registers, the native firmware starts the chain load. When the OTC has either completed the
transfer or aborted, the command register is cleared. If the transfer is aborted, an error bit in TPR register
l is set, and the contents of the OMA status for channel l is placed in TPR register 3 before the command
register is cleared. In either case of completion, the native firmware enters a wait state.
4.4.1.3 Reinitialize Command (Bit 2 Set) - This command is equivalent to a power-up. The native
firmware performs a power-up without battery backup. With this command, the boot/selftest switch can
be overridden. TPR register 3 is used to pass the selftest/boot test selection codes. See Chapter 6 for the
selftest codes.
4.4.1.4 Q-Bus ODT Command (Bit 3 Set) - This command causes the native firmware to enter the
Q-Bus ODT mode. In this mode the internal microprocessor registers are saved, the contents of TPR
register l are saved, and the command register accepts the Q-Bus ODT commands. On completion, TPR
register l state field is set to the Q-Bus ODT mode and the command register is cleared.
4.4.1.5 Show Command (Bit 4 Set) - This command causes the SBC to present its boot/selftest switch
setting and memory map switch settings in TPR register 3. Register 3 can then be viewed from a Q-Bus
device. See Chapter 5 for register 3 bit information. On completion of the Show command, the SBC enters
a wait state.
4.4.1.6 No Operation Command (Bit 5 Set) - This command is reserved for Digital Equipment Corporation use only. Issuing this command when running application code on the SBC may cause mishandling of
the restart interrupt.
4.4.2 Selftest Commands
There are 11 test commands that can be issued by writing to the TPR command register from the Q-Bus.
A brief description of each test follows. (For more register bit pattern information, see Chapter 5.) If a
parameter is associated with a test command that parameter is issued prior to issuing the command.
Parameters are issued via TPR3. On completion of any test, the results are placed in TPR registers 2 and 3
and the command register is cleared. Register 2 contains cumulative error information and register 3
contains discrete error information. Execution of any test may alter the state of the SBC control status
registers (CSRs) and RAM. All tests involve the use of interrupts, where applicable, only if the native
RAM is mapped to low memory location 0 or the user socket contains RAM. To map the RAM to
location 0, set the memory map to a position that maps the RAM low or set the boot/selftest switch to
position 10. If RAM is not set low, the interrupt portions of tests are not performed. On completion of any
test, the SBC enters the wait state.
4.4.2.1 CSR Test Command (Bit 0 Set) - This is one of the initial power-up or reinitialization tests.
When this command is received, the native firmware attempts to read the local command/status registers
(KXTCSR A, B, C, and D).
4.4.2.2 RAM Test Command (Bit 1 Set) - This test command enables a nondestructive test of the SBC
RAM to be performed. The test is also run on power-up or reinitialization if enabled. If RAM is present in
the user sockets, it, too, is tested. The native firmware determines if RAM is present in these sockets by
attempting to alter the first socket address location. If the contents at this address can be successfully
altered and restored, then the RAM test is performed.
4.4.2.3 ROM Test Command (Bit 2 Set) - This test performs a checksum of the native ROM contents
(and the user ROM, if selected). TPR register 3 is set to one before this command is issued if the user
ROM is to be tested, or set to zero if it is not. The algorithm for the ROM test is listed in Chapter 5.
4-6

4.4.2.4 CPU Test Command (Bit 3 Set) - This test command causes the microprocessor to exercise a
subset of the instruction set. The result is presented in TPR register 3.
4.4.2.5 BEVENT Test Command (Bit 4 Set) - This test verifies that the line clock interrupt can be
enabled, generated, and disabled. The generated interrupt is at priority level 6 through internal vector 100.
For this test to be performed, RAM must be mapped to zero.
4.4.2.6 SLUl Test Command (Bit 5 Set) - This test causes the console serial line unit to be tested. The
loopback connector must be in place for this test to be performed. RAM must be mapped to zero for the
interrupt portion of this test to be performed.
4.4.2.7 SLU2 Test Command (Bit 6 Set) - This test performs the multiprotocol interface chip test. Both
SLU2 channel A and B loopback connectors must be in place for channel A and B to pass the tests. The
channel tested is selectable via the TPR. RAM must be mapped to zero for the interrupt portion of this
test to be performed. The channels should be tested individually to provide meaningful error data.
4.4.2.8 PIO Test Command (Bit 7 Set) - This command causes a test of the Z8036 chip. The test checks
the parallel 1/0 port and the timers. The loopback connector must be used in performing this test. RAM
must be mapped to zero for the interrupt portion of this test to be performed.
4.4.2.9 DMA Controller Test Command (Bit 8 Set) - This test command causes the DMA controller to
be tested. The test is done by performing a DMA transfer from local memory to local RAM, from local
memory to Q-Bus RAM, from Q-Bus RAM to Q-Bus RAM, and from Q-Bus RAM to local RAM. Before
this command can be issued, TPR register 3 must be loaded with the high 16 bits of the base address of the
4 K word of Q-Bus RAM to be used.
4.4.2.10 QIR Test Command (Bit 9 Set) - This command causes the QIR (Q-Bus interrupt register)
interface to be tested. Q-Bus interrupt vector address (0-1776 octal) must be placed in TPR register 3
before the test command can be issued. When the Q arbiter receives the interrupt, it signals the SBC that
an interrupt was received by performing a reset instruction.
4.4.2.11 Two-Port RAM (TPR) Test Command (Bit 10 Set) - This command initiates a read and write
test of both ports of the TPR. The test uses the DMA controller in testing the TPR, so the DMA controller
test (Paragraph 4.3.2.9) should be done prior to testing the TPR.
4.4.3 Q-Bus ODT Commands
Once the SBC is in the Q-Bus ODT mode, by receiving the Enter Q-Bus ODT command (Chapter 5), the
command register format is changed, but procedures for issuing ODT commands remain the same. This
also includes how the SBC responds to a command error. The Q-Bus processor-initiated ODT command
details follow.
4.4.3.1 Open and Examine Memory Command Code - The memory specified by TPR register 3 is
opened and its contents are presented in TPR register 2.
4.4.3.2 Open and Examine Register Command Code - The microprocessor general-purpose register
specified by TPR register 3 is opened and the contents are presented in TPR register 2. See Paragraph 4.5
on opening registers.
4.4.3.3 Deposit Command Code - This command initiates the deposit of the data presented in TPR
register 2 into the open memory location or register.
4.4.3.4 Go Command Code - This command instructs the native firmware to restore all CPU registers to
the user values and to transfer control to the location specified by TPR register 3. The PSW is set to zero
and a reset instruction is performed.
4-7

4.4.3.5 Proceed Command Code - This command is the same as the Go command except it uses the
current saved PC value, restores the PSW, and does not perform a reset.
4.4.3.6 Exit Mode Command Code - This command exits the SBC from the Q-Bus mode and waits for a
control command. When completed, the previously running application code context is lost. The command
register format returns to the control/test format and the SBC waits for the next command.
4.5 SERIAL ODT
In addition to boot programs, the SBC native firmware contains code for performing the serial ODT
functions via the console 1/0 port (Jl). This is necessary because the T-11 microprocessor does not
implement ODT in microcode. The following ODT commands are implemented in macrocode. The ODT
monitor responds to the following ASCII character encoded commands.
1.

"n/" - Open memory location or register (e.g., 1000/ or Rl/)

"/" - Reopen last memory location or register previously closed
NOTE

If the "/" command is used without a target

and a target was never specified in the current
ODT session, a default address of zero is used.
2.

If the"/" command is used after an error, the

command is not accepted and an error is
issued.
3.

CARRIAGE RETURN - Close memory /register

LINE FEED - Close last memory /register and open the next

""" - Close last memory location or register and open preceeding

"R" or "r" - Specify register to be opened (e.g., Rl), (set of: RO through R7, RS)
•
•

"0" ... "7" - CPU register RO through R7 (e.g., Rl)
"S" or "s" - CPU status register (e.g., RS)

"," - Specify range to be examined (e.g., 1000,1100/ or R0,4/)

"G" - Restore all CPU registers to user values. Perform a reset instruction.

"P" - Same as "G" command, except a reset instruction is not performed.
NOTE
1.

The last location is opened on completion of
the command.

Number following "," must be greater than the
preceding number. 11,not true, an error prompt
is displayed.

4-8

The user enters serial ODT mode by sending a BREAK signal to the console serial interface on the SBC.
NOTE
The BREAK signal is received if the BREAK jumper
is installed.
When the SBC is in the serial ODT mode, the TPR is disabled and all commands from the Q-Bus are
ignored. Serial ODT mode can also be entered if the boot/selftest switch is in position 4 on power-up or
reinitialization. BREAK commands entered while the SBC is in the serial ODT mode cause the present
command to be aborted and the original BREAK PC to reappear with a new prompt. This can be used to
abort a range examine, as shown in the following example.
entry

(BREAK)

response

123456
@

entry

0,100/

response

@0,100/011565
000002/177776
000004/005015

entry

(BREAK) [ In the middle of the range examine]

response

123456
@

4.5.1 Autobaud
Serial ODT autobauds if SLUl (console 1/0 port) is configured for software baud rate operation and the
baud rate has not been previously programmed. The autobaud routine determines the proper operating
baud rate by comparing the character received to the value of a RETURN character. The procedure for
causing the ODT to perform this function is to enter several RETURNs after the SBC is in the ODT mode
until the following ODT response is printed (PC value, CR, LF, @). The autobaud routine works for a
terminal set at 300, 600, 1200, 2400, 4800 or 9600 baud.
NOTE
The baud rate can be configured for either hardware
or software baud rate operation. If the IOP is configured for hardware operation (see Paragraph
6.2.9), autobaud is inhibited.
4.6 LED DISPLAY
The native firmware sets the state of all four LED display indicators using four bits in KXTCSR C. The
results of the SBC selftests and the state of the firmware are displayed by the four LEDs. The LEDs
indicate one of two types of errors: first encountered nonfatal error or a fatal error. A table of the error
displays and a descripiton of each error is shown in Chapter 6. It is suggested that the user should not alter
the LED status.

4-9

4.7 MEMORY MAP CONFIGURATION
The native firmware reads the state of three bits in KXTCSR B. The three bits are user selectable for eight
possible memory maps. For details on the eight memory maps available, see Chapter 6.
4.8 RESTART HANDLING
The KXTl 1-CA firmware must interpret the cause when the T-11 microprocessor is vectored to the
restart address 173004. Five events can cause the SBC to interrupt to the restart address. The native
firmware tests for each of these events in the following order and services the first one to occur. For
detailed register bit and flag information, see Chapter 5.
1.

Break - The native firmware determines if the Break function was the cause of the restart by
testing the low three bits of the boot/selftest switch. If BREAK caused the interrupt, all three
bits will be ones. These three bits are located in KXTCSR D.
The native firmware clears any break interrupts by reading the RBUF of SLUl. It also clears
the NXM and TPR interrupt indicators. The flag bits of the KXTCSR D are used to determine
what action to take. Then these bits are normally cleared. If cleared, the native firmware enters
the serial ODT mode.

TPR Interrupt - This event is indicated by bits in local KXTCSR D (control status register).
The native firmware responds to the event by clearing the TPR interrupt indicator and the
NXM indicator, then decoding the command received for the Q-Bus and taking the appropriate
action.

Nonexistent memory (NXM) - This event is determined through another indicator by a bit in
KXTCSR D. If this indicator is set the native firmware clears it. The firmware then attempts to
emulate a trap through the vector at 4. This process requires a valid stack. If the stack is
determined to be invalid (pointing to a nonexistent memory location), the native firmware sets
the SP to the default SP value (top of native RAM - 100), sets the stack error flag of the status
register (TPR word 1), and emulates a trap to 4. If there was no stack problem during the trap
emulation, the stack error flag of the status register is cleared.

Halt instruction - When the T-11 microprocessor executes a halt instruction, the peripheral
processor traps to the restart address (173004). The native firmware determines if this is the
cause of the restart by checking the location pointed to by the return PC on the stack minus 2.
If the location contains a 0, the cause of the restart is assumed to be a halt instruction. If bit 4 of
the status register, TPR word 1, is set to a "l" the native firmware enters serial ODT. If the bit
has not been set to a "l" {cleared on initialization), the native firmware emulates a trap through
the vector at 10.
NOTE
This bit should be set when using MAC DEBUG or
POS DEBUG.

BHALT - Receiving a Q-Bus halt (BHALT) with the BHALT enable bit set in KXTCSR D
causes an interrupt to the restart address. The native firmware tests the BHALT bit in
KXTCSR D register to determine if this is the cause of the interrupt. If this is the case, the
native firmware emulates a trap through the vector at location 24, leaving the BHALT bit in
KXTCSR D register set. This is the last test for the cause of the restart. If the cause is not
found, the native firmware performs a return from interrupt.

4-10

4.9 BOOT EXIT
When the native firmware transfers control of the SBC to the application software, the SBC assumes the
following state.
•
•
•
•
•
•
•
•
•
•

All TPR registers are cleared except for TPR registers l, 2, and 3.
All 1/0 interrupts are disabled.
Parallel port A interrupt vector is set to 200.
Parallel port B interrupt vector is set to 204.
Parallel port timer interrupt vector is set to 210.
DTC channel A interrupt vector is set to 110.
DTC channel B interrupt vector is set to 114.
DTC internal registers are at indeterminate values.
The LEDs are set to non-native code running state or error display.
The stack pointer is set to first RAM address below the reserved RAM space.

4-11

CHAPTER 5
PROGRAMMING INFORMATION

5.1 INTRODUCTION
This chapter details all the user-addressable registers for the KXTl 1-CA single-board computer. This
chapter also describes the usage of each software programmable register bit. Appendix Eis a list of each
addressable register in the KXTl 1-CA local environment.
5.2 CONTROL STATUS REGISTERS (KXTCSR)
The local processor has four 1/0 page addressable registers available for controlling and monitoring the
SBC system environment. KXTCSR A is an 8-bit read/write byte- or word- addressable register at
address 177520. KXTCSR B is an 8-bit byte- or word-addressable read-only status register at address
177522. KXTCSR C is an 8-bit byte- or word- addressable read/write register at address 177524. These
three low-byte registers are available through the 8255A-5 chip. During power-up the native firmware
initializes the three registers by writing a 212 at address 177526. This causes all low-byte register outputs
to be driven to a zero state. Rewriting the mode control word reinitializes the 8255 chip. The high byte of
these registers must be treated as erroneous. The 8255A-5 chip is not altered by the reset instruction.
KXTCSR Dis a 16-bit word-addressable control and status register at address 177530 and is cleared by a
local reset.
5.2.1 KXTCSR A Register
Figure 5-1 shows the bit positions and the bit definitions of the KXTCSR A register at address 177520.
Table 5-1 defines the KXTCSR A register.
ADDRESS: 177520
07
06
05

CNT
IE

DIAG
PROM
EN
R/W

R/W
RTC
IE
R/W

TT108

SLU

R/W

REN
R/W

TERM
IN
SER
R/W

SYN CM
A

SYN CM

R/W

MA-11682

Figure 5-1

KXTCSR A Register

5-1

Table 5-1

KXTCSR A Bit Description

Bit

Name

Status

Function

CNTIE

Read/write

Programmable counter interrupt enable,
cleared on power-up, or by writing a zero.
When cleared the programmable
counter/timer 2 interrupt is inhibited from
being asserted. When set by writing a one,
the counter/timer can interrupt the T-11
on level 6 vector 104 each time the OUT
pin is driven high.

RTCIE

Read/write

This bit is cleared on power-up or by writing a zero. When cleared, the RTC interrupt is inhibited from being asserted to the
local processor. When set by writing a one,
the R TC interrupt is enabled.

DIAG PROM EN

Read/write

This bit is cleared on power-up or by writing a zero. It is set by writing a one, which
causes a 1 K word portion of the extended
selftest PROM to be visible at location
163777-160000. When cleared, the other
1 K word portion of the PROM is visible at
the same addresses. This, in conjunction
with the directly addressable 2 K word portion mapped to 173777-174000, allows a
total of 4 K word of dedicated firmware for
ODT, selftest, diagnostics, device initialization, and boots to reside in the 1/0 page.

TERM IN SER

Read/write

This bit is cleared on power-up or by writing a zero. When cleared, the modem is
signaled that the IOP is not available for
service or that the modem should appear
busy so that incoming calls will not be connected. When written with a one, the IOP
is in service and incoming calls can be
connected.

TT108/2

Read/write

This bit is cleared on power-up or by writing a zero. when cleared, the modem is
signaled to be removed from the communication channel following_ completion of the
transfer of all data presented before this
signal was turned off. When set by writing
a one, the modem prepares to be connected
to the communication channel and maintains the connection.

5-2

Table 5-1

KXTCSR A Bit Description (cont)

Bit

Name

Status

Function

SYNCM A

Read/write

This bit is cleared on power-up or by writing a zero. When cleared, the UPD 7201
channel A transmitter and receiver both
receive a clock derived from the programmable baud rate generator zero. When set,
the transmitter receives a clock from the
line (CCITTl 14) and the receiver receives
a clock from the line (CCITTl 15). This bit
effectively controls the internal baud rate
or external baud rate selection.

SLU2B REN

Read/write

This bit is cleared on power-up or by writing a zero. When cleared, the "party line
receive data" to the UPD7201 channel B
comes from the party line receiver if a
jumper is selecting the party line receiver
rather than the RS449 receiver. When
written to a one, the party line receive qata
to channel B is disabled. This facilitates
utilization of the PART LINE option.

SYNCM B

Read/write

This bit is cleared on power-up or by writing a zero. When cleared, the UPD7201
channel B transmitter and receiver receive
a clock derived from the programmable
baud rate generator zero. When set, the
transmitter receives a clock from the line
(CCITTl 14) and the receiver receives a
clock from the line (CCITTl 15). This bit
effectively controls the internal baud rate
or external baud rate selection.

5.2.2 KXTCSR B Register
Figure 5-2 shows the bit positions and the bit definitions of the KXTCSR B register at address 177522.
Table 5-2 describes the KXTCSR B register.
ADDRESS: 177522

SW3

SW1

(l4

MAP3

MAP1

SW2

SWO

MAP2

TT142
RO
MR-11683

Figure 5-2

KXTCSR B Register
5-3

Table S-2 KXTCSR B Bit Description
Bit

Name

Status

Function

07-04

SW3-SWO

Read only

These four hex-encoded general-purpose
flags are controlled by a manual 16-position switch (boot/selftest switch) and can
be utilized to cause different operational
modes like autoboot, run selftest only, or
enter ODT. Switch settings 7 and 15 are
reserved for Digital use only and must not
be selected. If console SLU 1 Break is configured to cause a T-11 restart trap, the
least significant 3 bits are forced to an all
ones state until the RBUF is read to clear
the condition. If this break trap in not configured, then the switch is not altered by a
break condition. The native firmware will
remain in ODT after a restart with a 7 or
15 seen until directed otherwise. Switch
settings 8-15 will force MAP 3 bit to the
zero state, which causes the RAM to be
mapped in low address space.

MAP3

Read only

This bit reflects the state of a switch input
to the local address decoder, which, when
read as zero, selects RAM to be mapped
starting at 000000, or, when read is asserted, selects RAM above PROM as determined by bits 02 and 01. Memory
configurations are described in Chapter 6.

02-01

MAP2-MAP1

Read only

These bits reflect the state of two switches
which configure the logical decode size of
the four 28-pin user socket sites. Chapter 6
defines the four possible combinations.

TT142

Read only

When this bit is read in the zero state, the
UPD 7201 channel A modem is not in a
test mode and is available for normal service. When read in the one state, it indicates that the modem has been placed in a
test condition. This condition is in response
to an "on" condition of CCITT140 or
CCITT141 and indicates that a test condition has been established.

5-4

5.2.3 KXTCSR C Register
Figure 5-3 shows the bit positions and the bit definitions of the KXTCSR C register at address 177524.
Table 5-3 defines the KXTCSR C register.
NOTE
The high byte of registers KXTCSR A, KXTCSR B
and KXTCSR C must be treated as indeterminate
read and write data. These registers are low byte
and word addressable by the T-11.

ADDRESS: 177524
07
06
05

103

101

LED3

R/W

LEDi
R/W

102

IDO

LED2

R/W

LEDO
R/W
MA-11684

Figure 5-3

Table 5-3

KXTCSR C Register

KXTCSR C Bit Description

Bit

Name

Status

Function

07-04

ID3-IDO

Read only

These four bits reflect the SBC ID number
assigned by the hex-encoded switch position. Codes 0 and 1 cause the Q-Bus interface to be disabled. Codes 2- 7 indicate
normal system operation with a base
address in the lower quarter of the 1/0
page. Codes 8-15 indicate a base address in
the upper quarter of the 1/0 page.

03-00

LED3-LEDO

Read/write

These bits are cleared on power-up or by
writing a zero. When in the zero state,
these bits drive four red LEDs to the off
state. Writing ones will turn the LEDs on.
On power-up, the LEDs are on until the
8255 chip mode is programmed; then, the
LEDs are turned off.

5-5

S.2.4 KXTCSR D Register
Figure 5-4 shows the bit positions and the bit definitions of the KXTCSR D register at address 177530 and
Table 5-4 describes the register.
ADDRESS: 177530
15
14
13

IQIR
IE

NXM
R/W

QB
RESET

R/W

QIR
REQ

BQIR
EN

R/W

01··

BHALT

TPR
ROST

R/W

QB
RESET
TE
R/W

R/W

RQ
124

IE
120

IE
134

R/W

BHALT
TE

TPR
EN

IE
124

RQ
134

R/W

RQ
120
R/W
MR·11686

Figure 5-4

KXTCSR D Register

Table S-4 KXTCSR D Bit Description
Bit

Name

Status

Function

NXM

Read/write

This bit is cleared on power-up, by a local
RESET, or by writing a zero. This bit is set
when the non-OMA local active address
does not map to any local device and causes
the T-11 to trap to the restart address if the
T-11 is in control of the bus. If the OTC is
in control of the bus, an EOP to the OTC is
caused and this NXM bit is not set for
Q-Bus or local accesses.

QIR Request

Read/write

This bit is cleared on power-up, by a local
reset, or by a Q-Bus reset, by the reception
of BIAKI, or by writing a zero. When set,
this bit indicates that the Q-Bus interrupt
register (QIR) has been written by the local
processor, and that a Q-Bus interrupt
request is pending service (i.e., BIRQ4 is
asserted). If KXTCSR D bit 12 is set
except when SBC ID numbers zero or one
are selected, BIRQ4 is blocked. This bit
cannot be set if the backplane is
unterminated; it can be set if the backplane
is terminated. Writing this bit to zero after
it has been set by a write to the QIR flushes
the pending request to the Q-Bus.

5-6

Table S-4

KXTCSR D Bit Description (cont)

Bit

Name

Status

Function

IQIR IE

Read/write

This bit is cleared on power-up, by a local
reset, or by writing a zero. When cleared
the T-11 will not be interrupted when the
QIR is emptied. When set by writing a one,
the T-11 will receive a level 5 interrupt
request for vector 130 when the QIR is
serviced by the reception of BIAKI and the
vector is taken, or when a Q-Bus reset
occurs while the QIR is full, or when the
QIR request bit is written to zero after having been set by a write to the QIR. Clearing
this bit does not flush a pending Q-Bus
interrupt request; it disables further T-11
interrupt requests. This bit does not disable
the assertion of the Q-Bus BIRQ4 line.

BQIR EN

Read/write

This bit is cleared on power-up, by a local
reset, or by writing a zero. When cleared,
the QIR request is blocked from the Q-Bus.
When set by writing a one, the Q-Bus will
receive a level 4 interrupt request for the
vector in the QIR. Clearing this bit does
not flush a pending Q-Bus interrupt
request; it blocks the request from the
Q-Bus.

QB RESET

Read/write

This bit is cleared on power-up, by a local
reset, or by writing a zero. It is set by the
reception of Q-Bus BINIT if KXTCSR D
bit 10 is set and causes a T-11 trap to 24.
Once set, this bit blocks further traps to 24
until it is cleared. This bit should not be set
if ID 0 or 1 is selected since BINIT may
always be asserted in an unterminated
backplane. For this case, no traps will occur
if the bit is set.

QB RESET TE

Read/write

This bit is cleared on power-up, by a local
reset, or by writing a zero. It is set by writing a one to enable the detection of a Q-Bus
reset occurrence, which, when detected,
sets KXTCSR D bit 11 and trap the T-11
to 24. Clearing this enable bit does not alter
KXTCSR D bit 11; it prevents further trap
requests.

5-7

Table 5-4

KXTCSR D Bit Description (cont)

Bit

Name

Status

Function

BHALT

Read/write

This bit is cleared .on power-up, by a local
reset, or by writing a zero. It is set by the
assertion of the Q-Bus BHALT signal when
KXTCSR D bit 08 is set to flag the occurrence of this signal and cause a T-11 restart
trap. Once set, further occurrences of
BHALT are ignored, but other T-11 trap
sources can still operate.

BHALTTE

Read/write

This bit is cleared on power-up, by a local
reset, or by writing a zero. When clear, this
bit prevents the SBC from responding to
the assertion of BHALT. When written
with a one, the assertion of the Q-Bus
BHALT will cause a T-11 restart and set
KXTCSR D bit 9. BHALT does not affect
the DMA operation.

DPR RQST

Read/write

This bit is cleared on power-up, by a local
reset, or by writing a zero. Writing a one
has no effect. This bit reflects the state of
the two-port register file (TPR) nonmaskable request bit which is set by any Q-Bus
write to the first word of the two-port register file. Setting this bit causes a T-11
restart. Once set, further writes to the TPR
first word (register zero) will not cause further T-11 restarts.

DPREN

Read/write

This bit is cleared on power-up, by a local
reset, or by writing a zero to force the QBus processor to read. zeros from the TPR.
Q-Bus writes will timeout. When written
with a one, the Q-Bus can read the actual
contents of the TPR, and writes to the
fifth, ninth, or thirteenth file words that
will latch requests into KXTCSR D bits 00,
01, and 02. If KXTCSR D bits 03, 04, or
05 are set, level 5 interrupt requests are
sent to the T-11. The T-11 or the DTC can
always read the TPR, regardless of the
state of this bit.

5-8

Table 5-4

KXTCSR D Bit Description (cont)

Bit

Name

Status

Function

05,04,03

IE 134, 124, 120>

Read/write

These bits are TPR level 5 interrupt
enables which are cleared on power-up, by
local reset, or by writing zeros to block
interrupt requests from the thirteenth,
ninth, and fifth TPR on level 5 from the
T-11. When these bits are set by writing
ones, any pending or succedent level 5 vector 134, 124, or 120 interrupts can pass
through to the T-11.

02,01,00

RQ134,124,120>

Read/write

These bits are TPR request flags which are
cleared on power-up, by local reset, by
writing zeros, or by interrupt acknowledge
transactions. They are set by writes to the
thirteenth, ninth, or fifth two-port registers
from the Q-Bus to flag the T-11 of the
occurrence of a write. If KXTCSR D bits
05, 04, or 03 are set, a T-11 level 5 interrupt will occur.

5.3 Q-BUS INTERRUPT REGISTER (QIR)
The local processor must signal the Q-Bus arbiter that it requires attention or that it has completed some
task. The mechanism supporting this function is a word-addressable write-only vector register located at
local address 177532 (see Figure 5-5). The local processor can write vector values between 0 and 1774 into
this register, causing KXTCSR D bit 14 to set and the BIRQ4 signal to assert if the BQIR EN bit is set.
The contents of this register are driven onto the Q-Bus when BIAKI is received and bits 14 and 12 in
KXTCSR Dare set. After the vector is transferred, the KXTCSR D status bit 14 is cleared. The QIR is
not initialized on power-up nor is it cleared by a local reset or by an Q-Bus interrupt acknowledge. The
register is updated with each write. If KXTCSR D bit 14 is set when a Q-Bus or a local reset occurs, the
BIRQ4 driver will be disabled and the pending request killed along with KXTCSR D bit 14. If bit 13 of
KXTCSR D was set, an interrupt is generated to the T-11 through vector 130 when the QIR is emptied by
a Q-Bus IACK, a Q-Bus reset, or a T-11 write of the QIRRQ bit to zero. A local reset flushes the request,
the interrupt enable, and the vector 130 interrupt.
When this register is driven onto the Q-Bus during an interrupt acknowledge transaction, the vector is
continued in bits 02-09; all other bits are read by the processor as zeros.
ADDRESS: 177532
15

14
0

10
0

MR-11686

Figure 5-5

Q-Bus Interrupt Register (QIR)

5-9

5.4 TWO-PORT RAM (TPR)
The two-port RAM (TPR) contains 16 (word) registers with 16 bits in each. Both the local TOAL and
global Q-Bus can do read/write operations via the TPR. The registers have a fixed local set of addresses
(175016-175020, 175016-175000) and a Q-Bus address that is a variable base address plus 2. (See Figure
5-6). The first four registers, starting at register 0, are used exclusively to enable the Q-Bus processor to
communicate with the SBC's native firmware. For more details on overall register usage and definitions,
refer to Chapters 3 and 4.
0-BUS ADDRESS

LOCAL ADDRESS

BASE+ ID +36

175036 R/W

175034 R/W

175032 R/W

175030 R/W
SIGNAL LOCAL CPU ON WRITE
(LEVEL 5 VECTOR 134)

175026 R/W

175024 R/W

175022 RO
STATUS, WRITES TIMEOUT

175020 R/W
SIGNAL LOCAL CPU ON WRITE
(LEVEL 5 VECTOR 124)

175016 R/W

175014 R/W

175012 RO
STATUS, WRITES TIMEOUT

175010 R/W
SIGNAL.LOCAL CPU ON WRITE
(LEVEL 5 VECTOR L 120)

175006 R/W

175004 R/W

175002 RO
STATUS, WRITES TIMEOUT
175000 R/W
SIGNAL LOCAL CPU ON WRITE
(NON - MASKABLE RESTART TRAP)

BASE+ ID+ 00

MR-12169

Figure 5-6

16 Bit X 16 Word Two-Port Ram (TPR)

5.4.1 Control Command Register (TPR 0)
The first register in the file is register 0 at local address 175000. There are six control commands that can
be written into this register from the Q-Bus processor using the appropriate bit pattern. The control
command register selects either a control command or test command. Bit 15 of the register selects which
set of commands are used.

5-10

5.4.1.1 Control Commands - Figure 5-7 shows the bits used for all six control commands. All other bit
combinations with bit I 5 set to zero are considered erroneous. The SBC responds by setting the command
error bit I 5 in status register I, clears the control command register, and enters the SBC into the wait
state. Only one control command bit can be set at one time. Paragraph 4.4. I begins the description of the
function for each bit in this register.
15

COMMAND BITS
NO OPERATION COMMAND (RESERVED)
SHOW CONFIGURATION
ENTER QBUS ODT MODE
RE-INTIALIZE
OMA LOAD

TEST/COMMAND INDICATOR BIT
(0 =COMMAND)

----------~

TRAP
MA-11681

Figure 5-7

TPR Control Command Register 0

5.4.1.2 Test Commands - Figure 5-8 shows the bit pattern for all I I test commands. Descriptions of all
11 test commands are included in Paragraph 4.4.2. As in the control command register, only one test
selection bit can be set at one time. On completion of the test, the results are placed in TPR register 2
(local address 175004), register 3 (local address 175006), and the command register is cleared. (See Figure
5-6 and Figure 5-7). Execution of any of these tests may alter the state of the CSRs and RAM. All tests
involve the use of interrupts only when the native RAM is mapped to location 0. This can be done by
either setting the memory map configuration to a position which maps the native RAM low or by setting
the boot/selftest switch to position 10. The SBC then enters the wait state on completion of the test. See
Chapter 6 for memory maps.

~ T1

13
I

I
0

_[_

11
I

0
_l_

_[_

_l_

_[_

_l_

TESTS
_[_

l L

CSR TEST
TEST RAM
TEST ROM
TEST CPU
BEVENT TEST
TEST SLU1 LOOPBACK
TEST SLU2 LOOPBACK
AND TIMER
TEST PARALLEL 1/0
LOOPBACK AND TIMER
TEST QBUS OMA TRANSFER
QIR TEST
TEST TWO PORT RAM
TEST/COMMAND INDICATOR
BIT (1 =TEST)
MR-11680

Figure 5-8

Test Command Register

5-I I

5.4.1.3 ODT Format - After entering the Q-Bus ODT mode via the enter ODT command the format of
the control register changes as shown in Figure 5-8. The rule for issuing Q-Bus commands are the same as
for issuing control commands. This includes how the SBC responds to a command error. For definitions of
each ODT command see Paragraph 4.4.3.
When the SBC is in the ODT mode, the internal readable microprocessor general-purpose registers are
presented in register 2 by the following codes. All other codes are invalid.
Register

Code

RO
Rl
R2
R3
R4
RS
SP
PC
PS

000000
000001
000002
000003
000004
000005
000006
000007
000010

5.4.2 Status Register (TPR 1)
The second TPR register is the SBC status register. Figure 5-9 shows the status register bit format. The
following describes the bits as they pertain to the user.
NOTE
The bits marked for internal use are not to be
altered by the user's application code.

[EJDJTJNJPJBJuJ

lolsl

F]o]x]

00
I

STATE
_l

J
STATUS BITS

[NATI;E FIRMWARE STATE CODE
STACK ERROR FLAG
ODTO N HALT INSTRUCTION*
FATAL ERROR FLAG
SERIA LODT FLAG
(INTER NAL USE)
QBUS ODT FLAG (INTERNAL USE)
POWE R UP WITHOUT BATTERY BACKUP*
POWE R UP WITH BATTERY BACKUP*
SP NXM TEST FLAG (INTERNAL USE)
NXM F LAG (FOR INTERNAL USE)
TRAP TO 4 DISABLE FLAG
(INTE RNAL USE)
DMAL OAD ERROR
COMM AND ERROR
*USER WRITEABLE BITS
MA-11679

Figure 5-9

TPR Status Register 1

5-12

Bits 00-02 are the state field of the status register. These bits are used for SBC status read by
the Q-Bus arbiter. These bits cannot be written to by SBC application code or through ODT
commands. The following describes the codes for each bit.
a.

State 000 - This field is read when the SBC is not available and occurs when the SBC is in
serial ODT mode or during power-up or reinitialization. When in this state, no commands
from the Q-Bus should be sent.

State 001 - Indicates the SBC is performing selftests. This state should be brief unless a
fatal error is encountered during the tests. If a fatal error is found, the SBC will remain in
this state until power-down.

State 010 - Indicates that the SBC boot/selftest switch is in position 10. This state is a
dedicated test mode. The SBC should not receive commands to load or run application
code.

State 011 - Indicates that only Q-Bus commands are responded to by the SBC.

State 100 - Indicates that the SBC is in an idle state and is waiting for a command from
the Q-Bus arbiter. The SBC is in this state if the boot/selftest switch is set for not booting
mode or after the following commands are received:
- DMA load
- Show configuration
- Any test command
- Any erroneous command

State 101 - Indicates that the application code is being loaded or is attempting to load a
boot block from a TU58 boot device connected to the serial console line (SLUl).

State 110 - This is an invalid state indicating possible errors in this register.

State 111 - Indicates that the SBC is passing control to RAM code or user ROM.

Bit 03 is the stack error flag. The flag is set when a trap to 4 emulation found the user stack
pointing to a nonwritable memory location. This is necessary because the trap emulation
involves the use of the stack. If the flag is set, the native firmware sets the stack pointer to the
default user stack value (TOR - 100) before emulating the trap to four ..The stack error bit is
cleared when a trap to 4 emulation (without stack pointer problems) is performed. The application trap 4 handler may use this bit to determine if there was a stack problem and take
appropriate action.

Bit 04 is set by the user if the SBC is to enter ODT in the execution of a haltjnstruction. If this
bit is left cleared (cleared during initialization), the SBC responds to a halt instruction by
performing a trap to 10 emulation.

Bit 05 is the fatal error flag. When this bit is set the SBC has detected a fatal error while
executing a selftest or a Q-Bus controlled selftest. Also, this bit is set if the boot/selftest switch
is set to an invalid setting. When the bit is set, the SBC is inoperative and does not respond to
any Q-Bus commands. A BREAK command from the console serial interface (if the board is
jumpered for BREAK enable) causes the SBC to enter serial ODT if it can.

5-13

Bits 06, 07, 11, 12 and 13 are for internal use by the native firmware. These bits should never
be altered by the application code or through ODT.

Bit 09 is set on power-up if the SBC is not powering up from a battery backup state (see bit 10
description).

Bit l 0 is set when the SBC powers up from a battery backup state. If bits 08 or 09 are to be
used by the application code, they must be cleared after being tested. In this way, when a
power-fail trap to 24 occurs, both bits are cleared, indicating that this is a power-fail interrupt.
It is important to note that the SBC hardware traps to 24 on power-fail. In a MicroPower
application the kernel handles these bits. These bits are user alterable. Table 5-5 summarizes the
meaning of these bits.

Bit 14 is the DMA error bit that is described in the DMA application load description (Chapter
4) and bit 15 is the command error bit also described in Chapter 4.
Table 5-5
Bit*
10 9

Power-Up Test Status

Description
Power-up no battery backup
Power-up with battery backup
Power-fail interrupt

0 1

l 0
Ot 0
*

Bits 9 and 10 are both user writable bits.

Bits are not altered by the native firmware. They will be 0
only if the application has previously cleared them.

5.4.3 Control Register 2 (TPR 2)
TPR register 2 is used by the native firmware to report errors encountered when the SBC performs any
selftests. See Figure 5-10 for register 2 bit format. Only the bit in register 2 associated with the test run is
set or cleared after the test is completed. This represents an accumulated error status format for handling
more than one test error. Register 2 bits set to one indicate an error; bits set to zero indicate successful
completion of the test.
5.4.4 Control Register 3 (TPR 3)
TPR control register 3 (local address 17 5006) is used to invoke, if necessary, a particular selftest. The
selftest codes and discrete error codes passed are from the last test completed. See Figure 5-11 for register
3 bit format. The discrete error bits indicate which portion or portions of a selftest failed and test coded
bits identify the test that was executed. Tables 5-6 through 5-15 describe each error bit for all 11 tests.

5-14

TESTS
_L

]

TESTS FAILED

CSRTEST
.....__ _ TEST RAM
- - - - - - TEST ROM
' - - - - - - - - TEST CPU
- - - - - - - - - BEVENT TEST
' - - - - - - - - - - - TESTSLU1 LOOPBACK
' - - - - - - - - - - - - - TESTSLU2 LOOPBACK
AND TIMER
' - - - - - - - - - - - - - - - TEST PARALLEL 1/0
LOOPBACK AND TIMER
- - - - - - - - - - - - - - - - TEST QBUS OMA TRANSFER
- - - - - - - - - - - - - - - - - - QIRTEST
, _ _ _ - - - - - - - - - - - - - - - - - - - TEST TWO PORT RAM
MR·11178

Figure 5-10 TPR Control Register 2

C~DE

Dl~CRET~ ERRO;S

TEST CODE OF LAST TEST

DISCRETE BIT ENCODED ERROR OF LAST TEST

MR-11817

Figure 5-11

TPR Control Register 3

Table S-6 CSR Test Status (Test Code = 01)
Bit

Location

Local Address

CSR (control status register)

177530

QIR (Q-Bus interrupt register)

177532

TPR

175000-175016
175020-175036

SLUl Driver

177566-177560

SLU2 Driver

175736-175700

Counter/Timer

175736

PI/O Counter/Timer

177136-177000

OTC

174536-174400

5-15

Table 5-7

RAM Test Status (Test Code= 02)

Bit

Error

Native RAM address is nonexistent memory (NXM)

Native RAM write-read

Native RAM read-modify-write (RMW)

Native RAM read-modify-write to low byte

Native RAM read-modify-write to high byte

User RAM address is nonexistent memory

User RAM write-read

User RAM read-modify-write (RMW)

User RAM read-modify-write to low byte

User RAM read-modify-write to high byte

Table 5-8 CPU Test Status (Test Code = 04)
Bit

Error

CPU test failed

Table 5-9

BEVNT Test Status (Test Code = 05)

Bit

Error

No RAM in vector space

Clock interrupt not masked by level 6

Clock does not interrupt

Clock cannot be disabled

5-16

Table 5-10

SLUl Test Status (Test Code = 06)

Bit

Error

No RAM in vector space

Transmit interrupt not masked at level 4

Transmit interrupt not received

Receive interrupt not masked at level 4

Receive interrupt not received

Receive data not correct

Receive done failed

Table 5-11

SLU2 Test Status (Test Code = 07)

Bit

Error

No RAM in vector space

Interval timer does not interrupt

Async mode data transfer incomplete

Sync mode EOF-SDLC not received

Sync mode data transfer not complete

Sync/async modes receive data incomplete

DMA mode data transfer incomplete

DMA mode received data incomplete

Status incorrect or no interrupt request with "request to send" set

Status incorrect or no interrupt request with "RS-422" set

Status incorrect or no interrupt request with "terminal in service" set

Status incorrect with everything off

5-17

Table S-12

Parallel 1/0 Test Status (Test Code= 10)

Bit

Error

No RAM in vector space

Reset state incorrect

Timer does not start

Timer does not stop

Interrupt not masked by level 4

Timer interrupt not received

Loopback timeout

Receive data incorrect

Table S-13 DMA Test Status Test Code= 11
Bit

Error

No RAM in vector space

Q-Bus address undefined (for local test only)

Chain interrupt not received

OMA channel hung up

DMA aborted

OMA data error
~

5-.18

Table 5-14 Q-Bus Interrupt Register Test Status (Test Code= 12)
Bit

Error

Q-Bus vector undefined

Break request was not set

No RAM in vector space

BIACK interrupt not masked at priority level 5

BIACK interrupt not received

BIACK not cleared by break request

Bus request not received

Table 5-15 Two-Port RAM (TPR) Test Status (Test Code= 13)
Bit

Error

Local TPR write-read

Bus error on Q-Bus TPR read

Non-zero data on Q-Bus read

No RAM in vector space

Bus error on Q-Bus TPR write

No interrupt on write to command register

Q-Bus write or interrupt with TPR disabled

Q-Bus write did not time out

Q-Bus write timed out

TPR interrupt level 4 not received

TPR interrupt level 8 not received

TPR interrupt level 12 not received

5-19

5.4.5 ROM Test Status (Test Code = 03) ·
The test performs a checksum of the native ROM contents and the user ROM if selected. If user ROM is
installed, TPR register 3 is set for OOOOOOI when the ROM test is selected. When the user ROM test is not
selected TPR register 3 must be set for 0000000. The algorithm for the ROM test follows.
SET CHECKSUM = 0
DO UNTIL ALL ROM CHIP LOCATIONS TESTED
ADD NEXT BYTE TO CHECKSUM (BYTE)
SHIFT CHECKSUM LEFT I (BYTE)
ADD CARRY INTO CHECKSUM
END UNTIL
This checksum test is passed if the difference of the above calculation and the checksum number of the
ROM being tested is equal to zero. The resultant checksum number is placed in the last physical location
of each ROM.
Prior to entering the OMA controller test, register 3 must be loaded with the high I6 bits from the base
address of the arbiter RAM 4 K words to be used. If, during this interval, a zero is written into TPR 3,
only the local portion of the test is performed. The Q-Bus portion is disabled.
5.5 DMA TRANSACTIONS
The controller registers are categorized into chip-level registers, which control the overall operation and
configuration of the OMA controller, and channel-level registers, which are duplicated for each channel.
The two chip-level registers are the master mode register and the command register. All registers must be
treated as word~wide during programmed transactions on even address boundaries. OMA controller
registers are addressable at local I/O page addresses I 74536- I 74400. Table 5-16 lists the registers by
their address, provides the number of bits used in the registers, and provides the register name.
The following paragraphs (5.5.I through 5.5.6) detail the bit assignments listed in Table 5-I6 and provide
a set of programming rules for the manipulation of these bits, which if followed will ensure correct
controller chip behavior. Certain operational modes of the OMA controller (OTC) are not supported and
the following paragraphs describe these cases as "must be" or "illegal" conditions.

Used
Bits

Table 5-16

DTC Internal Registers

Channel

Address

Access

I74400
I74402
174404
174406
I74410

R/W/C* I6
R/W/C I6
R/W/C 16
R/W/C I6
R/W/C I6

CHI
CHO
CHl
CHO
CHl

Current B address offset field
Current B address offset field
Base B address offset field
Base B address offset field
Current A address offset field

174412
I74414
174416
174420
174422

R/W/C
R/W/C
R/W/C
R/W/C
R/W/C

16
I6
16
I6
16

CHO
CHI
CHO
CHI
CHO

Current A address offset field
Base A address offset field
Base A address offset field
Current B address segment/tag field
Current B address segment/tag field

5-20

Table 5-16

DTC Internal Registers (cont)

Address

Access

Used
Bits

Channel

I74424
I74426
I74430
I74432
I74434

R/W/C
R/W/C
R/W/C
R/W/C
R/W/C

10
10
I6
I6
I6

CHI
CHO
CHI
CHO
CHI

Base B address segment/tag field
Base B address segment/tag field
Current A address segment/tag field
Current A address segment/tag field
Base A address segment/tag field

I74436
I74440
I74442
I74444
I74446

R/W/C
R/W/C
R/W/C
R/W/C
R/W/C

I6
I6
I6
10
10

CHO
CHI
CHO
CHI
CHO

Base A address segment/tag field
Chain address offset field
Chain address offset field
Chain address segment/tag field
Chain address segment/tag field

I74450
I74452
I74454
174456
174460

R
R
R/W
R
R/W/C

I6
I6
I6/8
I6
I6

CHO
CHO
CHI and CHO
CHO
CHI

Interrupt save register
Interrupt save register
CHI status/CHO and CHI command
CHO status
Current operation count

174462
I74464
174466
174470
174472

R/W/C
R/W/C
R/W/C
R/W

I6
I6
I6
8

CHO
CHI
CHO
CHO and CHI

Current operation count
Base operation count
Base operation count
Master mode

x
x
x
x
x
x

174474
I74476
I74500
I74502
I74504
I74506
I74510
1745I2
1745I4
1745I6

R/W/C
R/W/C
R/W/C
R/W/C

16
16
I6
16

CHI
CHO
CHI
CHO

Pattern
Pattern
Mask
Mask

174520
I74522
I74524
174526
I74530

R/W/C
R/W/C
R/W/C
R/W/C
R/W/C

I6
I6
5
5
8

CHI
CHO
CHI
CHO
CHI

Channel mode low
Channel mode low
Channel mode high
Channel mode high
Interrupt vector

I74532
174534
I74536

R/W/C

CHO

Interrupt vector

x
x

* R = local processor can read this register
W = local processor can write this register
C = chain operations can load this register
t X = unused registers; reads produce indeterminate data, writes have no effect
5-2I

5.5.1 Master Mode Register (MM)
This 8-bit read/write register (local address 17 44 70) is cleared to all zeros on power-up, by a T-11 reset
instruction, or by issuing a DTC reset command. (See Figure 5-12.) The bits and their functions follow.

MODE REGISTER

I I I

MR-11909

Figure 5-12

DTC Master Mode Register

Bit 07 - This bit must always be written to zero.
Bit 06 - This bit must always be written to one to enable a vector to be sent during an interrupt
acknowledge transaction.
Bit 05 - This bit must always be written to zero to enable the interrupt save register to be driven onto the
bus during interrupt acknowledge transactions.
Bit 04 - This bit can be written to a one, preventing an interrupt request from being asserted by the
counter timer chip which is on an interrupt daisy chain with the DTC at a lower hardware level. When
cleared, the counter timer chip can interrupt the T-11. This bit is known as the disable lower chain control
bit.
Bit 03 - This bit must always be set to one, enabling asynchronous controller operation when the Q-Bus or
TDAL bus is a source or a destination. It may be set to zero and programmed wait states can be used for
certain slow local devices (writes to the 8255A-5, ZCIO, or UPD 7201).
Bit 02 - When set to a one, the controller interleaves bus control with the local processor. When clear, the
controller retains bus control until a terminal condition is reached by the operation count register if hog
mode is selected.
Bit 01 - This bit must be written to zero.
Bit 00 - When written to a one, the controller can request bus control and perform operations. When
cleared to zero, the controller is inhibited from requesting the bus and, consequently, from performing
operations.

5.5.2 COMMAND Register (CM)
This 8-bit write-only register (local address 174454) is written to by the local processor to start execution
of controller commands immediately after they are written. The· register is divided into four fields: a 3-bit
function field, a 3-bit interrupt control field, a 1-bit set/clear function control field, and a 1-bit channel
select field. Table 5-17 lists the commands and the octal value which represents the command.
The reset command causes the controller to return to an initial state with MM register zeroed (other
registers are not altered) and channel activity inhibited. A T-11 reset instruction execution has the same

5-22

'
'

Table 5-17 Command Register Operation Codes
Command
Reset
Start chain
Start chain
Set software request
Set software request
Clear software request
Clear software request
Set hardware mask
Set hardware mask
Clear hardware mask
Clear hardware mask
Set CIE, IUS, IP
Set CIE, IUS, IP
Clear CIE, IUS, IP
Clear CIE, IUS, IP
Set CIE
Clear CIE
CIE is not altered
Set IUS
Clear IUS
IUS is not altered
Set IP
Clear IP
IP is not altered
Set flip bit
Set flip bit
Clear flip bit
Clear flip bit

Channel
CHO

CHI
CHO

CHI
CHO/CHI
CHO/CHI
CHO/CHI
CHO/CHI
CHO/CHI
CHO/CHI
CHO/CHI
CHO/CHI
CHO/CHI
CHO
CHI
CHO
CHI

Op Codes

000*
240*
24I*
102*
103*
100*
101 *
202*
203*
200*
201*
076t
077t
074t
075t
062/063t
060/06lt
Bit 4 = Ot
052/053t
050/05It
Bit 3 = Ot

042/043t
040/041t
Bit 2 = Ot

142*
143*
140*
I41*

Commands which do not specifically utilize the interrupt control field cannot alter the field when they are
issued but treat bits 4, 3, and 2 as "don't cares."
Bits 4, 3, and 2 are enable operation control bits which, when set, will enable IE, IUS, and IP bits to be
altered. When cleared, the IE, IUS, and IP bits are not altered.

effect as the OTC reset command. On power-up, however, the OTC is initialized, the register contents are
undefined and must be written before a start command is issued. Or, the chain address can be written, a
start chain command can be issued, and the selected channel clears the no auto-reload or chain bit in the
channel's status register, which starts a chain reload operation of the channel's registers. The start chain
channel command is only honored if both the chain abort (CA) and second interrupt pending (SIP) bits in
the channel status register are clear. If either bit is set, the command is disregarded. When the waiting for
bus bit in the status register is set, and a start chain command is issued, the channel honors the command
after one OMA iteration. The software request command sets the software request bit in the selected
channel's mode register. If the second interrupt pending (SIP) bit and no auto-reload or chain (NAC) bit in
the channel's status register are both clear, the channel starts executing the programmed OMA operation.
If either the SIP or NAC bit is set, the channel does not start executing a OMA operation until both bits
are cleared. The SIP bit clears when the channel receives an interrupt acknowledge. One way to clear the
NAC bit is to issue a start chain command to the channel.

5-23

If the fetched reload word is all zeros, the channel's registers remains unchanged and the software request
bit, if set earlier by command, causes the programmed DMA operation to start immediately. If during
chaining new information is loaded into the channel mode register, this new information overwrites the
software request bit.

The set/clear hardware mask command sets or clears the hardware mask bit in the selected channel's
mode register. This command always takes effect. The hardware mask bit inhibits recognition of an active
signal on the channel's DMA request pin; this bit does not affect recognition of a software request.
The flip bit in the selected channel's mode register can be cleared and set by the flip bit command. This
allows the source and destination to be reversed, thereby reversing the data transfer direction without
reprogramming the channel. Chaining new information into the channel mode register overwrites the flip
bit.
The set/clear channel interrupt enable (CIE), interrupt pending (IP), and interrupt under service (IUS)
commands allows the user to either set or clear any combination of these bits in the selected channel's
status register. These bits control the operation of the channel's interrupt structure. Setting the IP bit
causes the interrupt save register to be loaded with the current vector and status. The IP and IUS bits can
be simultaneously cleared to facilitate an efficient conclusion to the processing of an interrupt.
5.5.3 Chain Control Register (CC)
This register cannot be written to or read by the local microprocessor. When a channel starts a chaining
operation, it fetches a reload word from the memory location pointed to by the chain address register and
stores it in the CC register.
5.5.4 Temporary Register (TMP)
The temporary register is used to store data during flowthrough transfers and to hold data being compared
during a search or transfer-and-search. The temporary register cannot be written to or read from by the
local processor.
5.5.5 Current Address Registers
The current address registers A and B (current ARA and ARB) are used to point to the source and
destination addresses for DMA operations. The base address registers A and B (base ARA and ARB)
contents are transferred into the current ARA and ABA registers at the end of a DMA operation if the
user enables base-to-current reloading in the completion field of the channel mode register. This facilitates
DMA operations without reloading the current registers. The ARA and ARB registers can be loaded
during chaining and can be written to or read by the local processor. Each of the base and current ARA
and ARB registers consists of two words organized as a 7-bit tag field and an 8-bit segment in one word
and a 16-bit offset in the other. The segment and offset contain the actual address driven onto the bus. The
tag field selects whether the address is to be incremented, decremented, or left unchanged. It also selects
status codes associated with the address. The tag field also allows the user to insert 0, 1, 2, or 4 wait states
into memory or I/O accesses addressed by the offset and segment fields. These programmed wait states
are added to the asynchronous wait states generated external to the DTC.
The address reference field portion of the tag field can contain ARF (000) or ARF (011) for all local or
Q-Bus transactions. The 000 value enables the addresses to increment/decrement by one for byte operations and by two for word operations. The 011 value enables the address to increment/decrement by two
for byte and word operations. Low byte, high byte, and word-to-byte funneling operations are supported
locally only. Only word operations are supported across the Q-Bus interface. Word operations require that
even address values be placed in the address registers. Low byte operations require that odd address values
be placed in the byte address registers. High byte operations require that even values be placed in the byte
address registers. Byte operations are only supported locally; attempted byte writes to the Q-Bus result in
word operations with the unspecified byte being corrupted. Q-Bus word-to-local byte funneling is fully

5-24

supported, as is local byte-to-Q-Bus word funneling. The 8-bit segment field contains the most significant
address bits (16-21) and an address space select bit. The 1/0 page is decoded from the TDAL lines during
local DMA operations to select a 16-bit 1/0 page locally. The Q-Bus 1/0 page bit selects either a 16-, 18-,
or 22-bit 1/0 page on the Q-Bus. Bit AR3 l determines whether a local or Q-Bus operation is selected.
Figure 5-13 shows the ARA and ARB registers.
ADDRESS: 174436, 174420
AR31

AR30 AR29 AR28 AR27 AR26 AR25 AR24 AR23 AR22 AR21

Q/L

1/0

A21

A20

A19

A18

A17

A16

AR20 AR19 AR18 AR17

ARF2 ARF1 ARFO ACF1

ACFO WSF1 WSFO

AR16
0

SEGMENT /TAG
ADDRESS: 174416, 174400
AR15 AR14 AR13 AR12 AR11

AR10 AR09 AR08 AR07 AR06 AR05 AR04 AR03 AR02 AR01

AROO

A15

A10

AOO

A14

A13

A12

A11

A09

A08

A07

A06

A05

A04

A03

A02

A01

OFFSET

Figure 5-13

Address Registers A and B

The Q/L bit, when set to one, causes the address to reference the Q-Bus space; when cleared, the local
space is accessed. The 1/0 bit controls the assertion of the Q-Bus BBS? line during DMA transactions to
Q-Bus space. The one state asserts BBS?. This bit has no affect during local references since physical
addresses are decoded. Note that A21-A16 are ignored by the local 1/0 page decode logic when Q/L is
detected cleared. The A21-00 bits correspond with address bits BDAL21-00 for Q-Bus space and
TDALl 5-00 for local space.

NOTE
For local references, A21--16 bits should be zeros.
For local low byte operations, the AOO bit must be one; for word operations, it must be zero. The ACF bits
select one of three counting methods as follows.
00 = increment address
01 = decrement address
10 = hold address
11 = hold address
The WSF bits select the number of wait states to install when accessing local devices which are slow. These
bits are encoded as follows.
00 = 0 wait states
01 = 1 wait states
10 = 2 wait states
11 = 4 wait states
Bits AR23, AR22, AR21, and AR16 of the tag field are not used and must be set to zero.

5-25

The 16-bit, current-operation count register is used to specify the number of words or bytes to be
transferred, searched, or transferred-and-searched. For word-to-word operations, the current operation
count register must be programmed with the number of words to be transferred or searched. Each time a
data is transferred or searched, the operation count register is decremented by one.
Once all of the data is transferred or searched, the transfer or search operation stops, the current operation
count register contains all zeros, and the TC bit in the status register is one.
If the transfer or search stops before the current operation count register reaches zero, the register contents

will indicate the number of words remaining to be transferred or searched. This allows a channel - which
has been stopped prematurely by the local processor, or a negation of the channel request line, or a
nonexistent memory reference (NXM), - to be restarted where it left off without having to reload the
current operation count register. It also allows the local processor to determine how many operations
remain.
The maximum number of words to be transferred or searched are specified by setting a word count of
zero. Care must be taken to ensure that operation counts with incrementing/decrementing addresses do
not wrap over into the I/O page or under into the I/O page.
When a channel finishes a DMA operation, the user may choose to perform a base-to-current reload. In
this type of reload, the current address registers A and B are loaded with the data in the base address
registers A and B, respectively, and the current operation count register is loaded with the data in the base
operation count register. The base-to-current reload operation facilitates repetitive DMA operations
without the multiple memory accesses required by chaining. Although the channel must have local bus
control to perform base-to-current reloading, complete reloading operation occurs in four clock cycles.
Note that if the channel had to relinquish the local bus control because two unacknowledged interrupts
were queued, it would have to regain bus control to perform any base-to-current reloading (or chaining, for
that matter). In this case, it acquires the bus once an interrupt acknowledge is received, even if it
relinquishes the bus immediately afterward because no hardware or software request is present.
If the channel is programmed to chain at the end of a DMA operation, it will use the chain address register

to point to a chain control table in memory. The first word in the table is a reload word, specifying the
register(s) to be loaded. Following the reload word are the data values to be transferred into the register(s).
Because chaining occurs after base-to-current reloading, it is possible to reset the current address registers
A and B and the current operation count register to the values used for previous DMA operations and then
chain reload one or two of these registers to some special value to be used, perhaps, for this DMA
operation only. For burst operations of, say, four or eight words, the DTC is set up to interrupt the T-11 on
end of process (BOP), to chain reload the operation count and channel mode register with the software
request bit cleared, and to operate in demand dedicated with bus release mode.
The DTC will notify the T-11 after each operation terminates. The T-11 can then decide to either issue a
software start command or terminate the process and set up a new process. If the base values are not
reloaded during chaining, the channel can revert to the base values at a later cycle. If an all-zero-reload
word is fetched during chaining, the chain operations do not reload any registers; but in all other respects,
it performs like any other chaining operation. Thus, the chain address is incremented by two to point to the
next word in memory, and at the end of the all-zero-reload word chain operation, the channel will be ready
to perform a DMA. operation. All-zero-reload words are useful to start or terminate linked lists of DMA
operations traversed by chaining. On the other hand, care must be taken in their use since the channel may
perform an erroneous operation if it is unintentionally started after the chaining operation.

5-26

The two-port register file supports 16 of the possible 18 reload parameters at one time, so it is possible for
the Q-Bus arbiter to load the two-port register (TPR) with an operation and to have the controller pick
information up and perform the operation. Then the controller returns to the two-port register for the next
operation or waits until told to reload before returning to the two-port register for new parameter
information. The controller can also go to Q-Bus memory or to local memory to pick up the parameter
information as specified by the Q/L bit in the chain address register. The reload word format is shown in
Figure 5-14.

SYSTEM MEMORY
NEW CHAIN ADDRESS
REGISTER DATA
RELOAD WORD
SYSTEM MEMORY
CHAIN ADDRESS (OFFSET)
CHAIN ADDRESS (SEG(fAG)
CHANNEL MODE LOW

CHANNEL MODE HIGH

INTERRUPT VECTOR

32
30

MASK REGISTER
PATTERN REGISTER

BASE OP COUNT

24
22
20
16
14
12
10

BASE ARB (OFFSET)
BASE ARB (SEG(fAG)
BASE ARA (OFFSET)
BASE ARA (SEG/TAG)
CURRENT OP COUNT
CURRENT ARB (OFFSET)

CURRENT ARA (OFFSET)

06
04

CURRENT ARA (SEGffAG)

CURRENT ARB (SEGffAG)

RELOAD WORD:

42
40

o1o1o1o1o1 olcAR~CARBj coPcjBARAlBARBlBoPcj P&M I 1v I CM1CA 00
CA= CHAIN ADDRESS
CM= CHANNEL MODE
IV= INTERRUPT VECTOR
P&M = PATTERN AND MASK
BOPC = BASE OP-COUNT

BARB = BASE ARB
BARA = BASE ARA
COPC =CURRENT OP-COUNT
CARB =CURRENT ARB
CARA= CURRENT ARA
MR-11676

Figure 5-14

DTC Internal Registers

Each channel has a chain address register which points to the chain control table in memory containing
data to be loaded into the channel's registers. The chain address register (Figure 5-15) is two words long.
The first word consists of a segment and tag field. The second word contains the 16-bit offset portion of
the memory address. The tag field contains two bits to designate the number of wait states to be inserted
during accesses to the chain control table. The chain control table should reside in local space, but can
reside in Q-Bus space.

5-27

ADDRESS: 174444, 174446
CH31

CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21

Q/L

1/0

A21

A20

A19

A18

A17

A16

CH20 CH19 CH18 CH17 CH16

WSF1 WSFO

SEGMENT/TAG
ADDRESS: 174440, 174442
CH15 CH14 CH13 CH12 CH11

CH10 CH09 CH08 CH07 CHOO CH05 CH04 CH03 CH02 CH01

A15

A10

A14

A13

A12

A11

A09

A08

A07

A06

A05

A04

A03

A02

CHOO

A01

AOO

OFFSET
MA-11689

Figure 5-15

Chain Address Register

When the Q-Bus space is selected, the wait states are generated external to the chip and programmed wait
states are not required. The chain address register may be loaded during chaining and may be read from
and written to by the local processor. If an NXM occurs during chaining, the chain address register holds
the old address. This is true even if the access failure occurred while new chain address data was being
loaded, since the old data is restored unless both words of the new data are successfully read. Note,
however, that NXM's that occur when chaining and while loading a new chain address cause the new data
to be lost.
The Q/L, I/O, WSFl, WSFO, and A21-00 lines are functionally the same as the corresponding lines in
address register ARA and ARB described previously, except for the ACF and ARF fields, which are
defaulted to zero by the DTC. The chain address register is always incremented by two and assumes
memory data operations. The 0 bits are not assigned and are read as zeros and must be written with zeros.
The AOO bit must be written to zero by all write or chain operations to this register.
The two 16-bit status registers (Figure 5-16) are read-only registers which report on the status of their
associated channels. Each register has five fields: a 3-bit interrupt status field, a 4-bit DMA controller
status field, a 2-bit reserved field, a 2-bit hardware interface status field, and a 5-bit completion status
field. There is one status register for each channel.

ADDRESS: 174454, 174456
ST15

ST14

ST13

ST12

ST11

ST10

ST09

CIE

IUS

NAG

WFB

SIP

INTERRUPT
STATUS

ST08 ST07
0

DTC STATUS

ST06

ST05

ST04 ST03

ST02

ST01

STOO

HRQ

MCH

EOP

HARDWARE
INTERFACE

MCL

COMPLETION
STATUS
MR-11690

Figure 5-16

Status Register

5-28

Each controller channel is a source of interrupts and has three bits that control how the channel generates
interrupts. The interrupt status bits are programmed from the command register. These bits - channel
interrupt enable (CIE), interrupt pending (IP), and interrupt under service (IUS) - for each channel must
be monitored in the interrupt service routine and initialized via the command register. They are also copied
into the interrupt save register when the channel interrupt request is posted. To allow the controller to start
executing a new operation after issuing an interrupt (but before an interrupt acknowledge is received), a
two-deep interrupt queue is implemented on each channel. Each channel has its own interrupt vector
register for identifying the source of the interrupt during the acknowledge transaction. While an interrupt
source has an interrupt under service (IUS = 1), it prevents all lower priority interrupt sources from
requesting interrupts. When interrupt servicing is complete, the local processor must reset the IUS bit by
means of a command to the command register.
Once a channel issues a T-11 interrupt on maskable level 4, it is desirable to allow the channel to proceed
with the next DMA operation before the interrupt is acknowledged. This could lead to problems if the
controller channel attempted to chain reload the vector register contents. In such a situation, it may not be
clear whether the old or new vector would be returned during the acknowledge. This dilemma is resolved
in the controller by providing each channel with an interrupt save register. When the channel sets the IP as
part of the procedure followed to issue an interrupt, the contents of the vector register and some of the
status register bits are saved in an interrupt save register.
When an interrupt acknowledge cycle is performed, the contents of the interrupt save register (Figure
5-17) are driven onto the bus and only IS7-2 are read by the T-11 from TDAL 7-2. Although the use of an
interrupt save register allows the channel to proceed with a new task, problems may occur if a second
interrupt is to be issued by the channel before the first interrupt is acknowledged. To avoid conflicts
between the first and second interrupt, each channel has a second interrupt pending (SIP) bit in its status
register. When a second interrupt is to be issued before the first interrupt is acknowledged, the SIP bit is
set and the channel relinquishes the bus until an acknowledge occurs. For compatibility with polled
interrupt schemes, the interrupt save register can be read by the local processor without wait states.
Whenever the IP bit is set, the interrupt save register is loaded from the vector and status register. Note
that the SIP bit is transferred to the IP bit when IP is cleared by the local processor. Whenever IEI is high,
CIE is set and IUS is cleared, the interrupt request line will assert as IP is set. Note that some care must be
taken in programming the interrupt service routines to reset IUS if the user does not wish to reset IUS
until both interrupts are serviced.

ADDRESS: 174450, 174452
IS15

IS14

IS13

IHRO I MCH I MCL

IS12

IS11

IS10

IS09

CA I MC I EOP I TC

ISOB

IS07

I
I

IS06

IS05

IS04

IS03

IS02

IS01

x I x

I I I
V5

ISOO

CHAN
NUM
0/1

MR-11691

Figure 5-17

Interrupt Save Register

The DTC status field reports on the current channel state. The "channel initialized and waiting for
request" status is not explicitly stated; it is reflected by status bits STl 2-09 being all zero. The waiting for
· bus (WFB) status bit (STlO), when set, indicates that the channel wants bus control to perform a DMA
operation.
The channel may or may not be actually asserting the request line to the local processor, depending on the
programming of the master mode chip enable bit and the state of the request line and the grant line when
5-29

the channel decided it wanted the bus. If a channel completes a OMA operation and neither base-tocurrent reloading nor auto-chaining were enabled, the no auto-reload or chaining (NAC) bit will be set.
The NAC bit is only reset when the channel receives a start chain command. If two interrupts are queued,
the second interrupt pending bit (SIP) will be set and the channel will be inhibited from further activity
until an interrupt acknowledge occurs. Finally, if the channel address is nonexistent during chaining, the
chain abort (CA) and the NAC bit will be set. These bits are also set when the OTC is reset by command
or hardware. The CA bit holds the NAC bit in the set state until the end of process (EOP) bit is cleared.
The CA bit is cleared when a new chain address segment and tag word or offset word is loaded into the
channel address registers.
The hardware interface field provides a hardware request (HRQ) bit which provides a means of monitoring the channel's hardware request line. When the request is asserted, the HRQ bit will be one. The HM
bit, when set, prevents the controller from responding to the request line. Note, however, that the HRQ bit
always reports the true (unmasked) status of the request pin. The HM bit can be cleared by software
command.
When a OMA operation ends, the channel can interrupt the local processor, perform base-to-current
reloading, chain reload the next OMA operation, perform any combination of the above, or take no action.
The action to be performed by the channel is selected in the completion option field of the channel mode
register. The completion field stores data at the end of each OMA operation. This data indicates why the
OMA operation ended. When the next OMA operation ends, new data is loaded into these bits, overwriting and, thereby, erasing the old data.
Three bits indicate whether the OMA operation ended as a result of a terminal count (TC), a match count
(MC), or an end of process (EOP) termination. The TC bit sets to one if the operation count reaching zero
ended the OMA operation. The MC bit will be set to one if an MC termination occurred regardless of
whether stop-on-match or stop-on-no-match was selected or not. The EOP bit is set only when an EOP
ends a OMA transfer; it is not set for EOPs issued during chaining. Note that two or even all three of MC,
TC, and EOP may be set if multiple reasons existed for ending the OMA operation. The MCH and MCL
bits report on the match state of the upper and lower comparator bytes, respectively. These bits are set
when the associated comparator byte has a match; otherwise, they are reset regardless of whether stop-onmatch or stop-on-no-match is programmed or not. Regardless of the OMA operation performed, these bits
reflect the comparator status at the end of the OMA operation. These two bits are provided to help
determine which byte matched or did not match when using 8-bit matches with word searches and
transfer-and-searches. The two reserved bits return zeros during reads.
Each channel has an interrupt save register which can be read by the local processor. When an interrupt
occurs and IP equals one, either because a OMA operation terminated or because an NXM abort occurred
during chaining, the contents of the interrupt vector register and part of the channel status register are
stored in the 16-bit interrupt save register shown in Figure 5-17. Because the vector and status are stored, a
new vector can be loaded during chaining and a new OMA operation can be performed before an interrupt
acknowledge cycle occurs. If another interrupt occurs on the channel before the first is acknowledged,
further channel activity is suspended. As soon as the first clear IP command is issued, the status and vector
for the second interrupt is loaded into the interrupt save register and channel operation resumes. The
controller can retain only two interrupts for each channel; a third operation cannot be initiated until the
first interrupt has been cleared.
NOTE
For bits ISOl and ISOO in Figure 5-17, the X indicates that the T-11 will not use these bits as part of
the vector address. However, they can be read and
written from the vector register and may serve as
identifiers to the vector address.

5-30

S.S.6 Special-Purpose Registers
The pattern and mask registers are used in search and transfer-and-search operations. Both the pattern and
mask registers may be loaded by chaining or may be read or written by the T-11. The pattern register
contains the pattern that the read data is compared with. Setting a mask register bit to a one specifies that
the bit always matches.
The interrupt vector register (Figure 5-18) contains the vector or identifier to be output during an interrupt
acknowledge cycle. The DTC interrupts the local processor on level 4 with an external interrupt. The local
processor will only respond during a vector read transaction of an interrupt acknowledge cycle to bits
V7-2. Bits VO and Vl, however, may be used as a TAG field since the T-11 can read and write these bits
under program or chain control. The vector register is copied into the interrupt save queue when an
interrupt occurs.
ADDRESS: 174530, 114532
IV15

IV14

IV13

IV12

Ix Ix x Ix

IV11

IV10

IV09

IV08

IV07

IV06

IV05

IV04

IV03

IV02

IV01

I x I x I x v., Ivs I I I I

IVOO

I I
VO

'4A-11692

Figure 5-18

Interrupt Vector Register

NOTE
The X bits in Figure S-18 are disregarded by the
controller chip. Bits Vt and VO are not part of a
valid vector address since the processor cannot
accept them during an interrupt acknowledge.
Associated with each chan,nel are two channel mode registers (Figure 5-19). There are 21 bits defined in
each channel mode register. These bits are described in the following paragraphs. The other 11 bits are
unused and are read as zeros. The channel mode register selects what type of DMA operation the channel
is to perform, how the operation is to be executed, and what action, if any, is to be taken when the channel
finishes.
ADDRESS: 174524, 174526
CM31 CM30 CM29 CM28 CM27 CM26 CM25 CM24 CM23 CM22 CM21 CM20 CM19 CM18 CM17 CM16

Ix I x Ix I x Ix Ix I x I x I x I x Ix I I I I I I
SR

HRM

MC1

MCO

CHANNEL MODE HIGH
ADDRESS; 174520, 174522
CM15 CM14 CM13 CM12 CM11 CM10 CM09 CMOS
TC

EOP

CHAIN ENABLE

CM07 CM06 CM05 CM04 CM03 CM02 CM01 CMOO
FLIP

EOP

XFERO

BASE-CURRENT INTERRUPT ENABLE

OP3

OP2

OP1

OPO

OPERATION

XFER1
TRANSFER TYPE

COMPLETION FIELD

MR-11693

Figure 5-19

Channel Mode Register
5-31

Operation Field (OP3-0) - These four bits select the type of operation the channel is to perform. It also
selects the operand size of words. The code definition for these bits are listed in Table 5-18.
Flip - The flip bit is used to select whether the current ARA register points to the source and the ARB
register points to the destination or vice-versa. When cleared to zero, ARA = source and ARB =
destination; when set to one, ARA = destination and ARB = source.

Table 5-18

DTC Transfers
Operand
Size

OP3 OP2 OPl OPO

Operation*

ARA

ARB

Transaction
Type

Transfer

Word

Flowthrough

Transfer

Byte

Flowthrough

Transferand-search

Word

Flowthrough

Transferand-search

Byte

Flowthrough

Byte

Word

Flowthrough

Byte

Word

Flowthrough

Word

Read

Byte

Read

Illegal

Illegal
Illegal

Transfer
Illegal

Illegal
Illegal

Transferand-search
Illegal

Illegal

Byte operations are only supported locally; Q-Bus byte operations will result in word operations being performed.

5-32

XFER1, XFERO - This field selects the type of transfer to be performed by the channel according to the
following bit definitions.
XFER1

XFERO

Type of Transfer

1
1

0
1

Single transfer
Demand dedicated with bus hold (software hog mode)
Demand dedicated with bus release (software hog mode)
Channel-to-channel demand interleave

The combination of these transfer type bits with software control allows the controller to perform transfers
in single operation steps, n operation steps, or bus interleaved operation steps.
Single transfer operation is intended for use with peripherals which transfer single bytes or words at
irregular intervals. Each application of a software request command will cause the channel to perform a
single iteration of the DMA operation. Each application of a hardware request input will also cause a single
iteration of the DMA operation.
Demand dedicated with bus hold operation allows a software request to run to completion. The hardware
request causes the DTC to perform iterations as long as the request is asserted and there is a valid
operation count.
Negating the request line with a valid operation count causes the DTC to stall while holding the bus. Thus,
the user can start or stop execution of DMA operations by modulating the request pin. The demand
dedicated with bus release operation allows the DTC to give the bus back to the T-11 when the hardware
request negates.
Demand interleave operation forces the DTC to share the bus between its channels; if the master-mode bit
MM2 (CPU interleave) is set, the bus is shared with the T-11.
Completion Field - This field is divided into three subfields called chain enable, base-to-current reload
enable, and interrupt enable. These fields are used to program the action taken by the channel at the end
of a DMA operation. Setting a 1 in any of the bits in this field selects the completion operation to be
performed. The reason for ending is stored in the completion status field of the channel's status register.
This information is retained until the next DMA operation ends, at which time the status register is
updated to reflect the reason(s) for the latest termination. If no actions are selected for the type of
termination that occurred, the NAC bit in the status register will be set. More than one action can occur
when a DMA operation ends. This may happen if more than one action was programmed for the
applicable termination. The interrupt enable completion field for a channel directs a response to an event
to be detected by the IP bit in the channel status register. If the CIE channel status bit is set, then a
completion field event may set the IP bit and generate an interrupt to the T-11. For any completion field
event to set the IP bit, the particular event must be enabled in the completion field. Hence, polled
operation can be done by setting channel mode bits 7 and 9 and polling the IP bit in the channel status
register with CIE cleared. When the IP bit is tested asserted, then the channel status register contains the
valid termination control bits.

5-33

MCI, MCO - This field selects the type of match control operation that is in effect during DMA transfers
according to the following bit definitions.
MCI

MCO

Operation

0
0
1
1

0
1
0
1

Stop on no match
Stop on no match
Stop on word match
Stop on byte match

0 - This bit must always be written to zero to enable the channel DMA acknowledge strobe to assert
during transfers.
HRM - This bit, when set, masks the channel hardware request line from initiating DMA activity, and
may be treated as a don't-care bit since no sources of hardware requests exist to the OTC.
SR - This bit, when set by a processor write or by a chain reload, causes the channel to request the bus and
perform transfers according to the X FER 1, XFER 0 operation.
5.6 ASYNCHRONOUS SERIAL UNE UNIT (SLUI)
One asynchronous serial line unit is provided by a custom MOS 40-pin DL UART chip that has data
buffers and control and status registers as part of the chip. Serial line unit 1 (SLUl) can be a system
console with proper software handling. The assigned register addresses are shown Table 5-19 and the
interrupt vector addresses are shown in Table 3-1. The data buffers and the status registers can be accessed
by either the T-11 or the DMA controller. The serial data leads have an electrical interface which is
compatible with RS422/RS232-C/RS423. The user can optionally add a DLVll-KA EIA to 20 mA
converter; however, a reader run strobe is not provided, nor is a 110 baud rate input capability.

Table 5-19 Local 1/0 Register Address
Address Input

Device Register

177561-177560
177563-177562
177565-177564
177567-177566

SLUl receive CSR
SLUl receive buffer
SLU 1 transmit CSR
SLUl transmit buffer

5.6.1 Operating Parameters Selection
Programmable or jumper-selectable baud rates are supported by four XCSR bits which control the baud
rate selection (see Paragraph 6.3.11). These baud rates are level sensitive, not latched. This requires the
software control of the XCSR. use bit set and bit reset type instructions after the baud rate has been
written into the SLUl driver. The SLUf driver powers up with a default programmable baud rate of 300.
XCSR bits 05-03 can be read or written to define a new baud rate if bit 01 (PBRE) of the XCSR is set
and the PBRE shunt is removed. Split speed operation of the transmitter and the receiver is not supported.
Providing an external baud rate clock into the SLUl is not supported. Table 6-8 lists the internal
(programmable) baud rates. When the PBRE jumper is installed, the baud rate is selected by three other
jumpers. See Chapter 6 for jumper configurations. Note that the default power-up baud rate of 300 may
be altered by configuring the BRS02-00 bits and by not configuring. the PBRE bit.

5-34

5.6.2 Console Functions
In this description, console is defined as the interface between the system bus and 1/0 connector J3 on
SLU I. The unique features of serial line unit 1 (SLU 1) are the 177 566-177 560 address assignments,
vector addresses 60 and 64 assigned to the RBUF and XBUF, and an interrupt request pin which is a
hardware interrupt that is asserted when a BREAK is detected. This pin can be jumpered to cause the
T-11 to halt trap to the restart address. SLU2 does not have the capability of causing a T-11 restart
directly, since it does not have a pin dedicated to BREAK detect functions. Detected BREAK is asserted
when the RCVBRK bit is set in the RBUF by the serial-in signal going from a mark to a space and staying
in the space condition for 11 bit times after serial reception starts. This RBUF bit is negated when the
serial-in signal returns to the mark condition.
The BREAK detect interrupt remains asserted until either the RBUF is read or +5 V is removed. The
BREAK restart condition is jumper selectable and if selected KXTCSRB bits 06-04 will read all ones
when a BREAK is detected and before an RBUF read occurs. Hence, the response to this interrupt must
be a read of the RBUF.

5.6.3 Interrupt Vectors/Priorities
T-11 internal level 4 vectors 60 and 64 are assigned to the receive and transmit interrupts, respectively.
The receive has a higher priority than the transmit.
5.6.4 Address Selection
SLUl is a 16-bit bus-compatible device in the KXTl 1-C SBC that responds only to even address word or
low byte writes, or to even address reads. Table 5-19 lists the locally addressable I/O page register address
assignments.
5.6.5 Register Bit Assignments
The register bit assignments for transmit and receive registers are shown in Figures 5-20 through 5-23.
The following are the bit definitions for Figures 5-20 through 5-23.
RO

read only and is always read as zero if not serving one of the following
functions:

FR
RW
BRK
RCV
RDY
ACT

Framing
Read/write
Break
Receive
Ready
Active
Transmit
Done
Maintenance
Interrupt enable
Programmable baud rate
Error select
Over run
Programmable baud rate, select

M
IE
PB<2-0>
ERR
OR
PBE

5-35

RCSR
15
RO

14
RO

13
RO

12
RO

11
RO
RCV
ACT

09
RO

08
RO

07
06
RO
RO
RCV RCV
DN

05
RO

03
RO

02
RO

01
RO

00
RO

IE
MA-12246

Figure 5-20 RCSR Register

RBUF
15
RO
ERR

14
RO
OR
ERR

13
RO
FR
ERR

12
RO

11
RO
RCV
BAK

10
RO

09
RO

07
RO

08
RO

06
RO

04
RO

05
RO

03
RO

02
RO

01
RO

00
RO

RCV DATA BUFFER
MA-12246

Figure 5-21

XCSR
15
RO

14
RO

13
RO

12
RO

11
RO

10
RO

09
RO

RBUF Register

08
RO

07
RO

ROY

05
RW
BP2

RW
PB1

03
RW
PBO

02
RW
M

01
RW
PBE

00
RW

BAK
MA·12247

Figure 5-22 XCSR Register

XBUF
15
RO

I I

14
RO

13
RO

12
RO

11
RO

10
RO

09
RO

08
RO

07
RW

06
: RW:

05
RW

02
RW

: RW:

01
RW

00
: RW

TRANSMIT DATA BUFFER
MR-12248

Figure 5-23

XBUF Register

5-36

5. 7 PARALLEL 1/0
The parallel I/O and functions are provided by the Z8036 ZCIO counter/timer and parallel I/O (PIO)
transceiver chips. The ZCIO chip provides a counter/timer operating at a frequency of 2 MHz or a
resolution of 500 ns.
The PIO chip is protected from the connector by high input impedance, passive pull-up or TTL-compatible
driver transceivers. These transceivers provide no glitch protection to the 40-pin connector interface. They
comply with IEEE 488 electrical standards. The direction and TTL/open collector options are selected by
programming the write only PIO 1/0 buffer control register at (PCR) address 17777140.
The significant features of the PIO chip are: two independent 8-bit, double buffered, bidirectional 1/0
ports, plus a 4-bit special-purpose 1/0 port. The 1/0 ports feature programmable polarity, programmable
direction (bit mode), pulse catchers, and programmable passive pull-up outputs; four handshake modes,
including 3-wire (like IEEE-488); pattern-recognition logic, programmable as a 16-vector interrupt controller; three independent 16-bit counter /timers with three output duty cycles (pulsed, one-shot, and
square wave), and up to four external access lines for each counter (count input, output, gate, and trigger).
The counter/timers are programmable as retriggerable or nonretriggerable.
The ZCIO time constant register contains a value of N which is down counted at a rate of 500 ns per N
value or at the rate of the externally supplied clock. An external counter clock input must have a
minimum clock low time of 230 ns and a minimum clock high time of 230 ns, with a minimum period of
500 ns. The counter/timers can be operated in three modes: pulse output, one-shot, and square-wave. In
pulse output mode the output strobes for one clock pulse (500 ns) N +one clock pulses after the trigger or
reload. An example is shown in Figure 5-24.
500 NS_,

1--

N=7
T7654321T76
MR-11694

Figure 5-24

Pulse Output Mode Operation

In one-shot mode a time constant of N results in a pulse duration of N clock pulses starting one clock pulse
after the trigger. An example is shown in Figure 5-25.
For square wave mode an initial count of N results in a square wave with a period of N clock pulses. For
odd values of N, the output is high for (N+ 1)/2 counts and low for (N-1)/2 counts.

N=7
I

T765432

T7
MR-11695

Figure 5-25

One-Shot Mode Operation

5-37

5. 7.1

Address Selection

The PIO chip is addressable in the local I/O page on even address boundaries from address 17777000 to
17777136. In all PIO transactions, the high byte must be treated as erroneous data. The RJA bit (see
Figure 5-26) in the master interrupt control register must be written to zero on power-up or after a reset
instruction to ensure that the PIO chip responds to even addresses only. The only accessible register in the
PIO chip following power-up or a reset is the master interrupt control register, which must be written with
100 at address 17777000 before any other register can be read or written to.
ADDRESS: 17777140
15

PCTT

PABTT

PCO
DIR
WO

PC2
DIR
WO

PAHN
DIR
WO

PC1
DIR
WO

PC3
DIR
WO

P85
DIR
WO

P87
DIR
WO
PALN
DIR
WO

PB6
DIR
WO

P83
DIR
WO
PB4
DIR
WO

PB1
DIR
WO
PB2
DIR
WO

PBO
DIR
WO
MF'-11696

Figure 5-26

1/0 Buffer Control Register

5. 7.2 Interrupt Vectors/Priorities
The interrupt request is received as a level 5 interrupt and the PIO chip must supply a vector when the
interrupt is acknowledged.
The PIO chip must be programmed with three vector addresses, one for each data port and one for the
counter and timers. It must be programmed not to provide status with the vector addresses. This is done by
writing zeros to the master interrupt control register bits 5, 4, 3, and 2. The vector returned is the contents
of the port interrupt vector register or the counter/timer's interrupt vector register. The PCl request
strobe can be configured to operate with the DTC channel A or channel B request input. The wait mode is
not supported.

5.7.3 Buffers and 1/0 Connector
The PIO lines are buffered by bidirectional, high-current buffers from J4, a 40-pin, right-angle shrouded
header. The buffers are capable of providing high impedance inputs, with 600 mV of hysteresis and either
passive internal pull-up driver outputs or TTL-compatible driver outputs. These buffers comply with IEEE
488 electrical standards. Paragraph 6. 7 .2 describes the pin assignments of the PIO connector as seen from
the SBC edge and provides a signal cross-reference list.
The IEEE 488 buffers restrict to some degree the configurability of the output/input lines. Port A buffers
are configurable as nibbles as either input or output or bidirectionally controlled via the PIO I/O buffer
control register bits PAHN and PALN. Port Bis configurable as an 8-bit pprt, two 4-bit nibbles, or as a
bit port with the direction of each bit controlled via the PIO 1/0 buffer control register. The four lines of
port C can be individually configured to be an input or output as controlled by the PIO buffer control
register at address 17777140.

5.7.4 Register Assignments
Table 5-20 lists the PIO registers by address and by name. Refer to the Zilog Z8036 Counter/Timer and

Parallel 1/0 Unit Manual for additional details.

5-38

Table 5-20 Parallel Port Registers
Address

Name

17777000
17777002
17777004
17777006
17777010
17777012
17777014
17777016
17777020
17777022
17777024
17777026
17777030
17777032
17777034
17777036
17777040
17777042
17777044
17777046
17777050
17777052
17777054
17777056
17777060
17777062
17777064
17777066
17777070
17777072
17777074
17777076
17777100
17777102
17777104
17777106
17777110
17777112
17777114
17777116
17777120
17777122
17777124
17777126
17777130
17777132
17777134
17777136
17777140

Master interrupt control
Master configuration control
Port A interrupt vector
Port B interrupt vector
Counter/timer interrupt vector
Port C data path polarity
Port C data direction
Port C special 1/0 control
Port A command and status
Port B command and status
Counter/timer l's control
Counter/timer 2's control
Counter/timer 3's control
Port A data
Port B data
Port C data
Counter/timer l's current count MSB
Counter/timer l's current count LSB
Counter/timer 2's current count MSB
Counter/timer 2's current count LSB
Counter/timer 3's current count MSB
Counter/timer 3's current count LSB
Counter/timer l's time constant MSB
Counter/timer l's time constant LSB
Counter/timer 2's time constant MSB
Counter/timer 2's time constant LSB
Counter/timer 3's time constant MSB
Counter/timer 3's time constant LSB
Counter/timer l's mode specification
Counter/timer 2's mode specification
Counter/timer 3's mode specification
Current vector
Port A mode specification
Port A handshake specification
Port A data path polarity
Port A data direction
Port A special 1/0 control
Port A pattern polarity
Port A pattern transition
Port A pattern mask
Port B mode specification
Port B handshake specification
Port B data path polarity
Port B data direction
Port B special 1/0 control
Port B pattern polarity
Port B pattern transition
Port B pattern mask
1/0 buffer control register

5-39

Figures 5-26 through 5-46 show the bit map for each type of register; Table 5-21 defines the I/0 buffer
control register bits.
Table 5-21 1/0 Buffer Control Register Bit Description
Bit

Name

Status

Function

07-00

PB<7-0> DIR

Write only

These bits are cleared on power-up or by
writing a zero to configure the PIO port B
buffers for receivers. When written with
ones, the eight buffers are configured for
driving the 1/0 connector. All lines are in
the receive state on power-up or reset.

PALN DIR

Write only

This bit is cleared on power-up or by writing
a zero to configure the PIO port A low nibble buffers for receivers. When written with
a one, the four buffers are configured for
driving the 1/0 connector. All lines are in
the receive state on power-up or reset.

PAHN DIR

Write only

This bit is cleared on power-up or by writing
a zero to configure the PIO port A high
nibble buffers for receivers. When written
with a one, the four buffers are configured
for driving the 1/0 connector. All lines are in
the receive state on power~up or reset.

13-10

PC<3-0> DIR

Write only

These. bits are cleared on power-up or by
writing a zero to configure the PIO port C
buffers for receivers. When written with a
one, the programmed buffer is configured
for driving the 1/0 connector. All lines are in
the receive state on power-up or reset.

PABTT

Write only

This bit is cleared on power-up or by writing
a zero to configure the PIO port A and port
B driver buffers for open collector. When
written with a one, the port A and port B
driver buffers are configured for active pullup. Cleared on reset.

PCTT

Write only

This bit is cleared on power-up or by writing
a zero to configure. the PIO port C driver
buffers for open collector. When written
with a one, the port C driver buffers are
configured for active pull-up. Cleared on
reset.

5-40

ADDRESS: 17777000
07

MIE

NV
DLC

PBVIS
PAVIS

RJA
CTVIS

CHIP
RESET
MA-11697

Figure 5-27
•
•
•
•
•
•
•
•

Master Interrupt Control Register

MIE - Master interrupt enable
DLC - Disable lower chain
NV - No vector
PA VIS - Port A vector includes status
PBVIS - Port B vector includes status
CTVIS - Counter/timers vector includes status
RJA - Right justify address
CHIP RESET

ADDRESS: 17777002

PBE lcT1E

I 1~fjEI
CT2E

PLC I PAE I LC1

I I
Leo

MR-11698

Figure 5-28
•
•
•
•
•
•
•

Master Configuration Control Register

PBE - Port B enable
CTlE - Counter/timer 1 enable
CT2E - Counter/timer 2 enable
PCE/CT3E - Port C and counter/timer 3 enable
PLC - Port link control: 0 = port A/port B independent, 1 = port A/port B linked
PAE - Port A enable
u:;1, LCO - Counter/timer link controls:
00 =counter/timers independent
01 = C/Tl's /output gates C/T2
10 = C/Tl 's /output triggers C/T2
11 = C/Tl 's /output is C/T2's count input

5-41

ADDRESS: 177771000, 17777120
07

PTS1

PTSO

ITS

IMO

PMS1 PMSO

I I I I I I I I~~~ I
Mfl-118"

Figure 5-29

•

Port Mode Specification Register

PTS l, PTSO - Port type select:
00 =bit port
01 =input port
10 = output port
11 = bidirectional port

•

ITB - Interrupt on two bytes

•

SB - Single buffered mode

•

IMO - Interrupt on match only

•

PMSl, PMSO - Pattern mode specification:
00 = disable pattern match
01 =AND mode
10 =OR mode
11 =OR-priority encoded vector mode

•

LPM/DTE - Latch on pattern match (bit mode only)/deskew timer enable (handshake mode)

ADDRESS: 17777102, 17777122
07

HST1

RWS2
HSTO

RWSO
RWS1

DTSB2
DTSB3

DTSB1
MA·11700

Figure 5-30 Port Handshake Specification Register
•

HSTl, HSTO - Handshake type specification:
00 = interlocked handshake
01 = strobed handshake
10 = pulsed handshake
11 = three-wire handshake

5-42

•

RWS2, RWSI, RWSO - Request/wait specification:
000 = disabled
00 I = not supported
011 = not supported
I 00 = special Request
I 0 I = output Request
111 = input Request

•

DTSB3, DTSB2, DTSBI - Deskew time specification (specify the 3 MSBs of the deskew timer,
LSB is forced I and one additional count is added).
1.
2.

Example: 000 = 2 4-MHz clock cycles
Example: I 00 = 10 4-MHz clock cycles

ADDRESS: 17777020. 17777022

j 1us

ERR

ORE

1RF

PMF

10E

I I I I I I I I
MR-11701

Figure 5-31

•
•
•

Port Command and Status Register

IUS - Interrupt under service
IE - Interrupt enable
IP - Interrupt pending

NOTE
Writing IUS, IE, and IP are encoded as follows:
000 null code (do nothing)
001 clear IP and IUS
010 set IUS
011 clear IUS
100 set IP
101 clear IP
110 set IE
111 clear IE
•
•
•
•
•

ERR - Interrupt error read-only
ORE - Output register empty read-only
IRF - Input register full read-only
PMF - Pattern match flag read-only
JOE - Interrupt on error read/write

5-43

ADDRESS: 17777100, 17777120
07

DPP7 DPP6

DPP5 DPP4 DPP3

DPP2

DPP1 DPPO
MFM1702

Figure 5-32

Data Path Polarity Register

DPP7-DPPO - Data path polarity: 0 = noninverting, 1 =inverting

ADDRESS: 17777106, 17777126
07

DD7

DD6

DD5

DD4

0031 002

I I I I I

DD1

ODO

I I I
MR-11703

Figure 5-33

Data Direction Register

DD7-DDO - Data direction: 0 = output bit, 1 = input bit

ADDRESS: 17777130
07

SI07 SI06

Sl05

SI04

SI03

Sl02

SI01 SIOO
MR-11704

Figure 5-34

Special 1/0 Control Register

SI07-SIOO - Special input/output:
•
•

0 = normal input or output
1 = output with open drain (not supported) or input with 1's catcher

ADDRESS: 17777032, 17777034
07

PA7
PB7

PA6
PB6

PA5
PB5

PA4
PB4

PA3
PB3

PA2
PB2

PA1
PB1

PAO
PBO
MR-11706

Figure 5-35

Port A, Port B Data Register

5-44

ADDRESS: 17777036
07

PC3EN

PC1EN
PC2EN

PC3
PCOEN

PC1
PC2

PCO
MR-11706

Figure 5-36

Port C Data Register

PC3EN-PCOEN
•

0 = writing of corresponding PC enabled
1 = writing of corresponding PC inhibited

•

ADDRESS: 17777112, 17777132
07

PP7

PPB

PPS

PP4

PP3

PP2

PP1

PPO

I I I I I I I I I
MR-11707

Figure 5-37

Pattern Polarity Register

ADDRESS: 17777114, 17777134
07

1~1m1~1~1~1~1m1~1
MR-11708

Figure 5-38

PM PT
0
0
0

1
I

0
0

I
I

l
I

Pattern Transition Register

pp
X bit masked off
X any transition
0 zero*
l one*
0 one* to zero* logic transition
l zero* to one* logic transition

•The definition of zero and one is determined by the data path polarity.

5-45

ADDRESS: 17777116, 17777136
07

PM7

PM6

PM5

PM4

PM3

PM2

PM1

PMO

I I I I I I I I I
MR-11709

Figure 5-39

Pattern Mask Register

ADDRESS: 17777070, 17777072, 17777074
07

C/SC

EOE

ECE

ETE

EGE

DSC1 OSCO

I I I I I I I I I
MFM1710

Figure 5-40 Counter/Timer Mode Specification Register

•
•
•
•
•
•
•

C/SC - Continuous/single cycle 1 = continuous
EOE - External output enable
ECE - External count enable
ETE - External trigger enable
EGE - External gate enable
RE - Retrigger enable bit
DSCl, DSCO - Output duty cycle select:
00 = pulse output
01 = one-shot output
10 =square-wave output
11 =illegal

ADDRESS: 17777024, 17777026, 17777030

01.

j 1us j 1E j 1P

Figure 5-41

•
•
•

ERR

Rec

GCB

TCB

c1P

I I I I I I

Counter/Timer Command and Status Register

IUS - Interrupt under service read/write
IE - Interrupt enable read/write
IP - Interrupt pending read/write

5-46

NOTE
Writing IUS, IE, and IP are encoded as follows:
000 null code (do nothing)
001 clear IP and IUS
010 set IUS
011 clear IUS
100 set IP
101 clear IP
110 set IE
111 clear IE
•
•
•
•
•

ERR - Interrupt error read-only
RCC - Read counter control (only cleared by reading CCR LSB)
GCB - Gate command read/write
TCB - Trigger command write-only, read returns
CIP - Count in progress read-only

READ/WRITE
ADDRESS:

17777054, 17777060, 17'777064
MOST SIGNI Fl CANT BYTE

II
ADDRESS:

17777056, 17777062, 17777066
LEAST SIGNIFICANT BYTE

MA·11712

Figure 5-42 Counter/Timer Time Constant Register

READ ONLY
ADDRESS:

17777040, 17777044, 17777050
MOST SIGNIFICANT BYTE

I I
ADDRESS:

17777042, 17777046, 17777052
LEAST SIGNIFICANT BYTE

MFM1713

Figure 5-43 Counter 'Timer Current Count Register
5-47

ADDRESS: 17777004, 17777006
07
06
05
04
03

01 .

I I
Figure 5-44 Port A and B Interrupt Vector Register

Port vector status: bits 03, 02 and 01 are modified if VIS= 1 or MIE = 1 according to:
•

Priority encoded mode = number of highest priority bit with a match

•

All other modes = ORE, IRF, PMF (output empty, input full, pattern match flag)

•

000 =error

ADDRESS: 17777010
07
06
05

I I I I

I I
MR-1171&

Figure 5-45

Counter/Timer Interrupt Vector Register

Counter/timer status: bits 02 and 01 are modified to indicate interrupting counter according to:
00 = C/T3 source
01 = C/T2 source
10 = C/Tl source
11 =error

READ ONLY
ADDRESS: 17777076
07
06
05

I I
MR-11118

Figure 5-46 Current Vector Register
Interrupt vector based on highest priority unmasked IP. If no IP is present, this register reads all ones.

5-48

S.8 SYNCHRONOUS/ASYNCHRONOUS SERIAL COMMUNICATIONS (SLU2)
To facilitate remote synchronous or asynchronous 1/0 communications, a two-channel, serial 1/0 port
controller is provided. This port controller is a NEC UPD7201 multiprotocol, two-channel, serial communications controller. Channel A complies with RS449 mandatory interchange circuits for a type SR (sendreceive) data transmission element. Channel B complies with RS449 mandatory interchange circuits for a
type DT (data and timing only) data transmission element. The programmable baud rate generator
provides fundamental clocking rates to the controller providing variable programmable data rates of times
(X) 1, 16, 32, or 64, thus facilitating data rates from 150 baud to 76.8 K baud. The controller attributes
are: double-buffered transmitter data and triple-buffered received data; programmable CRC algorithm;
asynchronous operation with 5, 6, 7, or 8 data bits; l, 1-1/2, 2 stop bits; odd, even, or no parity; break
generation and detection; interrupt on parity, overrun, or framing errors; monosync, bisync, and external
sync operations; software selectable sync characters; auto-sync insertion; CRC generation and checking;
HDLC and SDLC operations; abort sequence generation and detection; auto-zero insertion and detection;
address field recognition; CRC generation and checking; and I-field residue handling. Refer to the
UPD7201 Technical Manual for additional information. The RS449 modem interface is supported by an
Intel 8255A-5 chip operated in mode 0, with ports A and C lower outputs, and ports B and C upper inputs.
This chip provides A, B and C (KXTCSRA, KXTCSRB, KXTCSRC) low bytes.
S.8.1 Programmable Baud Rate Generation
Programmable baud rates are supplied by an Intel 8254-2 timing controller chip with two counters
operated at fundamental frequency 9.8304 MHz for baud rate generation for both channels A and B.
The third counter is supplied with an 800-Hz clock and is a general-purpose counter used to facilitate
watchdog timers or software waits. KXTCSRA bit 07 controls a level 6 (vector 104) interrupt request
from the counter/timer OUT pin. The 8254-2 has three independent 16-bit counters, all of the GATE
inputs are fixed to the one state. The 9.8304-MHz and the 800-Hz clocks can be scaled in BCD or binary.
Counters zero and one support the UPD 7201 baud rate clock.
The clock rates that feed the 7201 controller are computed as follows. For the 8254-2 chip mode 3 even
counts of n, the clock period is n (9.8304-MHz or 800-Hz) clock periods, and clock high time= clock low
time. Odd count values must not be used for baud rate generation. Tables 5-22 and 5-23 provide the
decimal divider ratio (n) required by the 8254-2 chip for a specified baud rate. Note that asynchronous
baud rate n values have assumed that the UPD 7201 controller divides by 16.

Table 5-22

Actual Synchronous Bit Rate

Synchronous bit rate= 9830.4 K/divider ratio(N)
Ratio (Decimal)

Actual Bit Rate

Error(%)

136
176
204
512
1024
2048
8192

72.282 K
55.855 K
47.720 K
19.2 K
9.6 K
4.8 K
1.2 K

.3917
.2597
.3922

5-49

Table 5-23 Actual Asynchronous Baud Rate
Asynchronous baud rate= [9830.4 K(l/16)]/divider ratio
Ratio (Decimal)

Actual Baud Rate

307.2 K
153.6 K
76.8 K
38.4 K
19.2 K
9.6 K
4.8 K
2.4 K
1.2 K
600
300
150
109.989

4
8
16
32
64
128
256
512
1024
2048
4096
5586

Counter/timer 2 can be used as a general-purpose software counter/timer in mode 0 (interrupt on
terminal count), mode 2 (rate generator), mode 3 (square wave mode), or mode 4 (software triggered
strobe). When programming the 8254-2 chip, control register is sent a command which indicates a counter
and a mode or a counter operation to follow the command. The write-only timer control register at address
175736 has the format shown in Figure 5-47.

1~1~1~1~1~1~1~1~1
MR-11717

Figure 5-47

Timer Control Register

Bit 00 (BCD) - Zero state indicates binary counter 16-bits; one state indicates binary coded decimal
(BCD) counter with 4 decades.
Bits 01, 02, 03 (M2, Ml, MO) - Mode select bits used to configure the timer modes.
000
001
010
011
l 00
l0l
110
111

Mode 0 - interrupt on terminal count
Mode 1 - not supported
Mode 2 - rate generator
Mode 3 - square wave mode
Mode 4 - software triggered strobe
Mode 5 - not supported
Reserved - don't use
Reserved - don't use

5-50

Bits 04, 05 (RWl, RWO) - Read/write sequence selection:

00
01
10

Counter latch command
Read/write least significant byte only
Read/write most significant byte only
Read/write least significant byte first, then most significant byte

Bits 06, 07 (SCl, SCO) - Select counter for command:

00
01
10
11

Select counter 0
Select counter 1
Select counter 2
Read-back command

To avoid reading a changing count, the counter latch command should be used. The counter latch
command format is shown in Figure 5-48.
07

COUNTER 0

COUNTER 1

COUNTER 2

x
MA-11718

Figure 5-48

Counter Latch Register

Issuing this command causes the current counter value to be latched and held in a buffer either until it is
read or the mode is changed. The read-back command may also be used to obtain count and status
information for a particular counter. The read-back command format as shown in Figure 5-49.

00
0

/COUNT

CNT2

/STATUS

CNTO
CNT1
MA-11719

Figure· 5-49 · Current Counter Value Register

The selected counter is determined by bits 03, 02, and 01 being set. The command may be used to latch
multiple counter output latches by setting the count bit and selecting the desired counter(s). Once a
counter is latched, it must be read before another command is valid. The read-back command may also be
used to latch status information of a selected counter(s) by setting the status bit. Status must be latched to
be read from that counter's data register. The status byte format is shown in Figure 5-50.
·

5-51

I I

OUT NULL' RW1

RWO

I I

I I
BCD

MR-11720

Figure 5-50

Counter Status Register

Bits 05-00 are the same as those issued to a counter through the control register. The null bit is asserted to
indicate that a count value may not be loaded into a counter just yet. When the null bit is cleared, the
counter is active. Bit 07 will be a one when the OUT pin is not asserted and a zero when the OUT pin is
asserted low. Three typical 8254 load sequences follow.
MODE 3:
MOVB
MOVB
MOVB

MODE 3:
#67, @#175736
#LSB,@#175730
#MSB,@#175730

MOVB
MOVB

MODE 3:
#226,@#175736
#15, @#175734

MOVB
MOVB

#126,@#176736
#100,@#175732

5.8.2 Address Selection
The control registers and data buffers for the UPD 7201 controller and the 8254-2 chip are addressable by
the local processor at addresses 175736-175700. KXTCSR A register is located at address 177520 and
supports some of the SLU2 modem options. KXTCSR Bis located at address 177522 and supports the
test mode signal for the modem interface. The control registers and data buffers for the SLU2 controller
and the 8254-2 chip are divided into read-only and write-only groups. Reading a write-only register
address returns indeterminate data but does not alter the state of any register bits. Writing read-only
addressable registers does not alter the register contents. These low-byte registers are addressable on even
address boundaries only, and for the UPD 7201, and 8254-2, the high must be treated as erroneous. There
are 16 addressable registers: eight are SLU2 controller registers and eight are timer registers. Table 5-24
defines the addressable 8254-2 registers and Table 5-25 defines the addressable SLU2 controller registers.
Table 5-24

Timer (8254-2) Addressable Registers

Address

Name

Function

175736
175734
175734
175730
175726
175724
175722
175720

Timer control register
Timer 2 data register
Timer 1 data register
Timer 0 data register
X valid address
Timer 2 data register
Timer 1 data register
Timer 0 data register

Write only
Write only
Write only
Write only
Read only indeterminate data
Read only
Read only
Read only

5-52

Table 5-25 SLU2 Controller Addressable Registers
Address

Name

Function

175716
175714
175712
175710
175706
175704
175702
175700

Channel B transmitter
Channel B control register
Channel B receiver
Channel B status
Channel A transmitter
Channel A control register
Channel A receiver
Channel A status

Write only
Write only
Read only
Read only
Write only
Write only
Read only
Read only

5.8.3 Interrupt Vectors/Priorities
The UPD 7201 controller must be operated in nonvectored interrupt mode, or in either of two vectored
interrupt modes: in channel A OMA/channel B non-DMA mode, or channel A and B non-DMA mode.
Vectored interrupt mode is selected by writing a 025 or a 024 into the channel A control register 2 at
address 175704. The receiver then has a higher internal interrupt priority than the transmitter, which has a
higher internal priority than the modem interrupts. The vector includes the status bit that must also be set
since the 7201 controller interrupts the T-11 on level 4 through internal vector 70. The service routine
must be able to determine the cause of the interrupt by reading the interrupt vector from control register 2
channel Band then the IP bit from channel A status register. Timer 2 can interrupt the T-11 on level 6 via
the OUT pin through vector 104. This interrupt is maskable via KXTCSR A bit 7 control. When the
controller is operated in DMA mode, the request signals to the DTC must be configured by installing
jumpers from the controller request pins to the DTC request pins. See Chapter 6 for jumper sections. The
wait mode or block mode of operation is not supported.
5.8.4 I/O Drivers and Receivers
The electrical interface complies with RS449 standards, which implies that RS422 and RS232-C interfacing is available. In addition, channel B may be operated in party line mode by controlling the party line
transmitter through UPD transmitter control register at address 175714 (register pointer 5). The receiver
is enabled via KXTCSR A bit 1 and is enabled when the bit is in the zero state. Note that all modem
control signals asserted from the SLU2 controller or KXTCSR A are asserted by writing a one. All
received control or status signals are read asserted in the one state.
5.8.5 Register Bit Assignments (CRO through CR7; SRO through SR2)
The asynchronous/synchronous UPD controller chip register bit assignments are detailed in the following
paragraphs.
COMMAND REGISTER (CHANNEL A) (See Figure 5-51.)
ADDRE!SS: 175704-CHANNEL A, REGISTER POINTER= 000, WRITE ONLY

REGISTtR
POINTER
I

~
CRCCONTROL
COMMAND

Figure 5-51

MA-11721

Command Control and Pointer Control Register (CRO)

5-53

Register Pointer
The register pointer specifies the next accessed register number. After a hardware/software reset, this
field is set to 0. The first control byte always goes to control register 0. When this field is set to a value
other than zero, the next control or status access is to the specified register.
Commands
000 Null - No effect, used when setting a CRC command.
001 Send Abort - SOLC mode abort code.
010 Reset External/Status Interrupts - Clears a pending interrupt and reenables the latches so that new
external/status changes are detected.
011 Channel Reset - Resets the internal interrupt prioritization logic. Must wait one NOP instruction
before writing a new command.
100 Enable Interrupt on Next Character - When in interrupt on first received character mode, this
command reenables the interrupt logic for the next received character.
101 Reset Pending Transmitter Interrupt /OMA Request - Resets a pending transmitter buffer becoming
empty interrupt or OMA request without sending another character.
110 Error Reset - Resets a special receive condition interrupt. It also reenables the parity and overrun
error latches that allow you to check for these errors at the end of a message.
111 End Of Interrupt - Unblocks lower priority interrupt requests, must be issued at some point in the
interrupt service routine.
CRC Control Commands
00 Null - No effect, used when issuing other commands.
01 Reset Receiver CRC Checker - Resets the CRC checker to zero for synchronous mode and resets to all
ones when in SOLC mode.
10 Reset Transmitter CRC Generator - Resets the CRC generator to zero for synchronous mode and
resets to all ones when in SOLC mode.
11 Reset Idle/CRC Latch L - Resets the idle/CRC latch so that when a transmitter underrun condition
occurs, the transmitter enters the CRC phase of operation and begins to send the 16-bit CRC character
calculated up to that point. The latch is then set so that if the underrun condition persists, idle characters
are sent following the CRC. After a hardware or software reset, the latch is in the set state.

5-54

INTERRUPT CONTROL REGISTER (CHANNEL A) (See Figure 5-52.)
ADDRESS 175704- CHANNEL A, REGISTER POINTER= 001, WRITE ONLY

RECEIVER
INTERRUPT
MODE

WAIT
FUNCTION
ENABLE

EXT/STATUS
INT ENABLE

MUST
BE ZERO
WAITON
RECEIVER
TRANSMITTER

TRANSMITTER
INTERRUPT
ENABLE
MR-12613

Figure 5-52

Interrupt Control Register (CRl)

Receiver Interrupt Mode
00 Receiver Interrupt/OMA Request Disabled - Polled operation mode.
01 Interrupt on first received character only and issue OMA Request OMA Mode - Interrupt is issued
only for the first character received after an enable interrupt on first character command.
10 Interrupt and issue a OMA request if OMA mode on all received characters - An interrupt is issued
whenever there is a character present in the receiver buffer (parity error is a special receive condition).
11 Interrupt and issue a OMA request if OMA mode on all received characters - Same as 10 except that
parity error is not considered a special receive condition. The vector status will reflect the special error
conditions: receiver overrun, asynchronous framing error, parity error, SDLC end of message.
PROCESSOR/BUS INTERFACE REGISTER (CHANNEL A) (See Figure 5-53.)
ADDRESS: 175704-CHANNELA, REGISTER POINTER= 010, WRITE ONLY
07

0/1

INTERRUPT VECTOR
MODE

SELECT
PIN 10AS
SEND BEN

DMAMODE
SELECT

PRIORITY

MR·11723

Figure 5-53

Processor/Bus Interface Control Register (CR2)

5-55

OMA Mode Select

DMA Priority

Interrupt Priority

00 Non-DMA

0 RxA> TxA>RxB>TxB>ExTA>ExTB
I RxA>RxB>TxA>TxB>ExTA>ExTB

0 I DMA channel A,

RxA>TxA
RxA>TxA

Non-DMA channel B

0 RxA>RxB>TxB>ExTA>ExTB
1 RxA>RxB>TxB>ExTA>ExTB

10 Not supported

11 Illegal
RECEIVER CONTROL REGISTER (CHANNEL A) (See Figure 5-54.)
ADDRESS: 175704-CHANNEL A, REGISTER POINTER= 011, WRITE ONLY
07

1/0

'--..,---J
NUMBER OF
RECEIVED
BITS/CHARACTER

ENTER
HUNT
PHASE

AUTO
ENABLES

Figure 5-54

ADDRESS
SEARCH
MODE

RECEIVER
ENABLE

RECEIVER SYNC
CRC
CHARACTER
ENABLE
LOAD INHIBIT

Receiver Control Register (CR3)

Number of Received Bits/Character
00
01

10
11

5
7
6

MODE CONTROL REGISTER (CHANNEL A) (See Figure 5-55.)
ADDRESS: 175704-CHANNEL A, REGISTER POINTER= 100, WRITE ONLY

CLOCK RATE

SYNC
MODE

NUMBER OF STOP
BITS SYNC MODE

PARITY
ENABLE

PARITY
EVEN/ODD
MR-11726

Figure 5-55

Mode Control Register (CR4)

5-56

Number of Stop Bits/Sync Mode
00 Synchronous modes
01 Asynchronous 1 bit time (1 stop bit)
10 Asynchronous 1-1/2 bit times (1 1/2 stop bits)
11 Asynchronous 2 bit times (2 stop bits)
Sync Mode
00 8-bit internal synchronization character (monosync)
01 16-bit internal synchronization character (bisync)
10 SDLC
11 Not supported
Clock Rate
00 Clock rate = 1 X data rate
01 Clock rate= 16 X data rate
10 Clock Rate = 32 X Data Rate
11 Clock Rate = 64 X Data Rate
TRANSMIITER CONTROL REGISTER (CHANNEL B) (See Figure 5-56.)
ADDRESS: 175714-CHANNEL B, REGISTER POINTER= 101, WRITE ONLY
07

0
TRANSMITTER
CRC ENABLE
" " - - - - PARTY LINE
X EN SEND B
-----CRC
POLYNOMIAL
SELECT
' - - - - - - - - - TRANSMITTER
ENABLE
- - - - - - - - SEND
BREAK
----------~NUMBEROF

TRANSMITTED BITS
PER CHARACTER
MA-11738

Figure 5-56

Transmitter Control Register (CR5)

5-57

Number of Transmitted Bits/Character
00
01
10
11

5 or less

7
6
8
NOTE
For five or less data bits/character, The data must
be formatted as follows:
1 bit/character
2 bits/character
3 bits/character
4 bits/character
5 bits/character

llllOOOd
lllOOOdd
llOOOddd
lOOOdddd
OOOddddd

SYNC/ADDRESS CHARACTER REGISTER (CHANNEL A) (See Figure 5-57.)
SYNC CHARACTER REGISTER (See Figure 5-58.)
STATUS REGISTER (CHANNEL A) (See Figure 5-59.)
STATUS REGISTER 1 (CHANNEL A) (See Figures 5-60, 5-61, and 5-62.)
INTERRUPT STATUS VECTOR REGISTER (CHANNEL B ONLY) (See Figure 5-63.)
--1

ADDRESS 175704-CHANNEL A, REGISTER POINTER= 110 WRITE ONLY
07

I I I I

I I

SYNC BYTE 1
SYNC/ADDRESS REGISTER
MR·12614

Figure 5-57 Sync/Address Character Register (CR6)

ADDRESS: 175704-CHANNEL A, REGISTER POINTER= 111, WRITE ONLY
07

SYNC BYTE 2
MA-11728

Figure 5-58 Sync Character Register (CR7)
5-58

ADDRESS: 175700-CHANNEL A; REGISTER POINTER= 000, READ ONLY

cs
A

BREAK/
ABORT

SYNC
STATUS

INTERRUPT
PENDING

IDLE/CRC

TRANSMITTER
BUFFER EMPTY

RECEIVED
CHARACTER
AVAILABLE
MA-11729

Figure 5-59

Buffer and (External/Status) Status Register (SRO)

ADDRESS: 175700.CHANNEL A,"REGISTER POINTER= 001, READ ONLY
07

SDLC
RESIDUE CODE

ALL
SENT

CRC
PARITY
FRAMING
ERROR
ERROR
END OF
OVERRUN
FRAME
ERROR
MfM1730

Figure 5-60 Received Character Error and Special Condition
Status Register (SR 1)

ADDRESS: 175702-CHANNEL A, REGISTER POINTER= XXX, READ ONLY

I I
RECIEVED DATA
MR-11731

Figure 5-61

Receiver Data Buffer Register

ADDRESS: 175706-CHANNEL A, REGISTER POINTER= XXX, WRITE ONLY

I I
TRANSMITTED DATA
MFM1732

Figure 5-62 Transmit Data Buffer Register

5-59

ADDRESS: 175710-CHANNEL B, REGISTER POINTER= 010, READ ONLY
07

I I

so
MA-11733

Figure 5-63

Interrupt Vector Status Register (SR2)

Since the 7201 controller is operated with condition affects vector mode enabled, the value of the vector
written to the register at 175714 register pointer= 010 is modified as follows.
S2

Field Description

1
0
0
0
0
1
1
1
1

1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1

No interrupt pending
Channel B transmitter buffer empty
Channel B external/status change
Channel B received character available
Channel B special receive condition
Channel A transmitter buffer empty
Channel A external/status change
Channel A received character available
Channel A special receive condition

Status 111 can mean either channel A special receive condition or no interrupt pending. To determine
which condition is in effect, examine the interrupt pending bit of status register 0, channel A. Note that in
nonvectored interrupt mode you must read the vector register first for interrupt pending to be valid.
COMMAND CONTROL AND POINTER CONTROL REGISTER (See Figure 5-64.)
ADDRESS: 175714-CHANNEL B, REGISTER POINTER= 000, WRITE ONLY
07

CRCCONTROL
COMMAND

COMMAND

Figure 5-64

Command Control and Pointer Control
Register (CRO)

Commands
000 Null - No effect, used when setting a CRC command.
001 Send Abort - SDLC mode abort code.
010 Reset External/Status Interrupts - Clears a pending interrupt and reenables the latches so that new
external/status changes are detected.

5-60

011 Channel Reset - Resets the internal interrupt prioritization logic. Must wait one NOP instruction
before writing a new command.
100 Enable Interrupt on Next Character - When in interrupt on first received character mode, this
command reenables the interrupt logic for the next received character.
I 0 I Reset Pending Transmitter Interrupt/OMA Request - Resets a pending transmitter buffer becoming
empty interrupt or DMA request without sending another character.
110 Error Reset - Resets a special receive condition interrupt. it also reenables the parity and overrun
error latches that allow you to check for these errors at the end of a message.
111 End Of Interrupt - Unblocks lower priority interrupt requests; must be issued at some point in the
interrupt service routine.
CRC Control Commands
00 Null - No effect, used when issuing o there commands.
0 I Reset Receiver CRC Checker - Resets the CRC checker to zero for synchronous mode and resets to all
ones when in SDLC mode.
I 0 Reset Transmitter CRC Generator - Resets the CRC generator to zero for synchronous mode and
resets to all ones when in SDLC mode.
11 Reset Idle/CRC Latch - Resets the idle/CRC latch so that when a transmitter underrun condition
occurs the transmitter enters the CRC phase of operation and begins to send the 16-bit CRC character
calculated up to that point. The latch is then set so that if the underrun condition persists, idle characters
are sent following the CRC. After a hardware or software reset, the latch is in the set state.
INTERRUPT CONTROL REGISTER (See Figure 5-65.)
ADDRESS: 175714-CHANNEL B, REGISTER POINTER= 001, WRITE ONLY

RECEIVER
INTERRUPT
MODE

WAIT
FUNCTION
ENABLE

WAIT ON
RECEIVER
TRANSMITTER

CONDITION EXT/STATUS
AFFECTS
INT ENABLE
VECTOR

TRANSMITTER
INTERRUPT
ENABLE
MR-1173&

Figure 5-65

Interrupt Control Register (CRl)

5-61

Receiver Interrupt Mode
00 Receiver Interrupt/OMA Request Disabled - Polled operation mode.
01 Interrupt on first received character only and issue OMA request if OMA mode - Interrupt is issued
only for the first character received after an enable interrupt on first character command.
10 Interrupt and issue a OMA request if OMA mode on all received characters - An interrupt is issued
whenever there is a character present in the receiver buffer (parity error is a special receive condition).
11 Interrupt and issue a OMA request if OMA mode on all received characters - Same as 10 except that
parity error is not considered a special receive condition. The vector status will reflect the special error
conditions: receiver overrun, asynchronous framing error, parity error, or SDLC end of message.
Condition Affects Vector
0

Fixed vector interrupt acknowledge sequence is initiated.
Modified vector, which reflects condition causing interrupt; interrupt acknowledge sequence is
initiated.

RECEIVER CONTROL REGISTER (See Figure 5-66.)
ADDRESS: 175714-CHANNEL B, REGISTER POINTER= 011, WRITE ONLY
07

05 '

0
T

NUMBER OF
RECEIVED
BITS/CHARACTER

ENTER
HUNT
PHASE

AUTO
ENABLES

ADD~ESS

SEA CH
MODE

RECEIVER
ENABLE

RECEIVER SYNC
CRC
CHARACTER
ENABLE
LOAD INHIBIT
MR-11738

Figure 5-66

Receiver Control Register

Number of Received Bits/Character
00
01
10
11

5
7
6
8

Auto Enables
Setting this bit allows receiver ready and clear to send modem lines to enable the receiver.

5-62

MODE CONTROL REGISTER (See Figure 5-67 .)
ADDRESS: 175714-CHANNEL B, REGISTER POINTER• 100, WRITE ONLY

....w,___,,,_--.....,.....--"
CLOCK
RATE

SYNC
MODE

..,

NUMBER OF
STOP BITS
SYNC MODE

PARITY
ENABLE

PARITY
EVEN/ODD
MR·1t737

Figure 5-67

Mode Control Register

Number of. Stop Bits/Sync Mode
00 Synchronous modes
01 Asynchronous 1 bit time (I stop bit)
10 Asynchronous 1 1/2 bit times (I 1/2 stop bits)
11 Asynchronous 2 bit times (2 stop bits)
Sync Mode
·
00 8-bit internal synchronization character (monosync)
01 16-bit internal synchronization character (bisync)
10 SDLC
11 Not supported
Clock Rate
00 Clock rate = 1 x data rate
01 Clock rate = 16 x data rate ·
10 Clock rate = 32 x data rate
11 Clock rate = 64 X data rate

5-63

TRANSMITTER CONTROL REGISTER (See Figure 5-68.)
ADDRESS: 175714-CHANNEL B, REGISTER POINTER:. 101, WRITE ONLY
07

TRANSMITTER
CRC ENABLE
- - - PARTY LINE
X EN SEND B
" - - - - - CRC
POLYNOMIAL
SELECT
~-----

TRANSMITTER
ENABLE

' - - - - - - - - - SEND
BREAK
~----------NUMBER OF

TRANSMITTED BITS
PER CHARACTER
MA-11738

Figure 5-68

Transmitter Control Register

Number of Transmitted Bits/Character

00
01

5 or less
7

8
NOTE
For 5 or less data bits/character, the data must be
formatted as follows:
1111000D
1 bit/character
111000DD
2 bits/character
11000DDD
3 bits/character
1000DDDD
4 bits/character
OOODDDDD
5 bits/character

SYNC/ADDRESS CHARACTER REGISTER (See Figure 5-69.)
SYNC CHARACTER REGISTER (See Figure 5-70.)
BUFFER AND EXTERNAL/STATUS REGISTER (See Figure 5-71.)
RECEIVED CHARACTER ERROR AND SPECIAL CONDITION STATUS REGISTER (See Figure
5-72.)
RECEIVER/TRANSMITTER DATA BUFFER REGISTERS (See Figure 5-73 and 5-74.)

5-64

ADDRESS: 175714-CHANNEL B, REGISTER POINTER= 110, WRITE ONLY

SYNC BYTE 1

MA-11739

Figure 5-69 Sync/Address Character Register

ADDRESS: 175714-CHANNEL B, REGISTER POINTER= 111, WRITE ONLY

SYNC BYTE 2
MR-11740

Figure 5-70 Sync Character Register

ADDRESS: 175710-CHANNEL B, REGISTER POINTER= 000, READ ONLY

BREAK/
ABORT

RECEIVED
CHARACTER
AVAILABLE

SYNC
STATUS

IDLE/CRC

TRANSMITTER
BUFFER EMPTY
MR-11766

Figure 5-71

Buffer and (External Status) Status Register

ADDRESS: 175710-CHANNEL B, REGISTER POINTER= 001, READ ONLY

SDLC RESIDUE CODE
END OF
FRAME

OVERRUN
ERROR

CRC
FRAMING
ERROR

PARITY
ERROR

ALL SENT

MR-11763

Figure 5-72

Received Character Error and Special Condition
Status Register
5-65

ADDRESS: 176712-CHANNEL B, REGISTER POINTER'= XXX, READ ONLY

MR·117M

Figure 5-73 Receiver Data Buffer Register

ADDRESS: 175718-CHANNEL B, REGISTER POINTER• XXX. WRITE ONLY

TR~NSMl~ED ~ATA

Figure 5-74 Transmiter Data Buffer Register

5-66

CHAPTER 6
CONFIGURATION/INSTALLATION/VERIFICATION

6.1 INTRODUCTION
The configuration, installation and verification of the KXT 11-CA single-board computer is described in
this chapter. The following four steps, which are an integral part of the procedures, are covered in detail.
NOTE
Leave the factory configuration as is until KXT11CA SBC performance is verified.
1.

Installing jumpers to select operational features

Selecting and connecting an appropriate power supply

Providing appropriate cables to connect external devices to the serial line and parallel 1/0
interfaces

Verifying operation of the SBC

6.2 CONFIGURATION/INSTALLATION/VERIFICATION PROCEDURE
The configuration/installation/verification procedure shown in Figure 6-1 should be completed by the user
to ensure proper SBC operation for the application selected.

6-1

CONFIGURATION

CHECK DESI RED
CONFIGURATION
AGAINST FACTORY
SHIP CONFIGURATION IN TABLE 6-2

USE SECTIONS 6.3.1
THRU 6.3.16 TO
SELECT NON FACTORY CONFIGURED
OPTIONS
INSTALLATION
INSURE BACKPLANE
POWER IS OFF.
INSERT A KXT11-CA
IN THE BACKPLANE
INSURE NO EMPTY
SLOTS BETWEEN
KXT11-CA PREVIOUSLY INSTALLED
BOARD. SEE SECTION
6.5 FOR DETAILS
VERIFICATION -

TURN OFF POWER

YES

2
MA-12173

Figure 6-1

KXTl 1-CA SBC Configuration/Installation/Verification Procedure
Flow Diagram (Sheet 1 of 3)

6-2

STANDALONE

PERIPHERAL PROCESSOR

DISCONNECT 1/0 CABLES
AND INSERT LOOPBACK
CONNECTORS AS SHOWN
ON SECTION 6.6.1

DISCONNECT 1/0 CABLES
ON KXT11-CAAND
INSERT LOOPBACK
CONNECTORS AS SHOWN
IN SECTION 6.6.2

IS SLU2 CHANNEL A
CONFIGURED FOR RS 422
OR RS 423 OPERATION.
SEE SECTION 6.2.11 FOR
FOR DETAIL

RS422

RS423

SET SWITCHES ON
LOOPBACK CONNECTOR
H3270 FOR RS 423
TESTING. SEE SECTION
6.6.2

SET SWITCHES ON
LOOPBACK CONNECTOR
H3270 FOR RS 422
TESTING. SEE SECTION
6.6

INSERT LOOPBACK
CONNECTOR AS
SHOWN IN
SECTION 6.6

SET THE BOOT/SELF
TEST SWITCH TO
POSITION B

SET THE BOOT/SELF
TEST SWITCH TO
POSITION 9. NOTE
' - - - - - - THATTHISTEST
DOES NOT WORK
PROPERLY IF MEMORY
MAP 7 IS SELECTED.

MR-12174

Figure 6-1

KXTI 1-CA SBC Configuration/Installation/Verification Procedure
Flow Diagram (Sheet 2 of 3)

6-3

RESTORE POWER OR
RESTART AND
WATCH THE LEDS.

SET BOOT/SELF TEST
SWITCH TO POSITION10

MOUNT XXDP+
MEDIUM ON MASS
STORAGE DEVICE.

RESTORE POWER OR
RESTART SYSTEM
AND WATCH THE LEDS.
THE LEDS SHOULD
NOW ALTERNATE
BETWEEN "OFF ON
ON" AND "OFF ON ON
OFF". ANY OTHER
DISPLAY INDICATES
THERE ISA FAULT
ON THE BOARD.

THE LEDS SHOULD NOT
DISPLAY "OFF OFF ON
ON" TO INDICATE THE
SELF TESTS HAVE BEEN
COMPLETED AND IS
WAITING FOR FURTHER
TEST COMMANDS FROM
THE XXDP+. ANY OTHER
DISPLAYS INDICATE
THAT THERE IS FAULT
ON THE BOARD.

BOARD IS NOT
GETTING POWER OR
LEDS ARE BURNTOUT.

BOOT XXDP+

RUN KXT11-CA
DIAGNOSTIC (CZKTCA)
USING THE EXAMPLE
ON SECTION 6.9
MR-12175
MR-12176

Figure 6-1

KXTl 1-CA SBC Configuration/Installation/Verification Procedure
Flow Diagram (Sheet 3 of 3)

6-4

6.3 SELECTING OPERATING FEATURES
The KXTl 1-CA SBC has 32 jumperable functions and two-edge mounted switches which you use to
configure the SBC for operating modes necessary to meet your requirements. (See Figure 6-2.) Jumper
configurations are done by either installing, repositioning, or removing jumpers between pins. The location
and identification number of the pins are shown in Figure 6-3. Table 6-1 defines the pins by functional
groups. You can select the operating features you need by connecting the jumper pins with the 29 jumpers
that are supplied with the board. The standard factory shipped jumper arrangement is shown in Figure 6-3
and is listed in Table 6-2.

START

YES

USER
RAM

BATTERY
BACK-UP

MEMORY
MAP

BOOT/SELF
TEST

BASE
ADDRESS

REAL TIME CLOCK
INTERRUPTS

SERIAL
LINE
UNIT NO. 1

SERIAL
LINE
UNIT NO. 2

END
MR-12177

Figure 6-2

KXTll-CA SBC Operating Features Flow Diagram

6-5

Pl/0

CHANNEL B

CONSOLE

CHANNEL A

DI__ ID D DI
J4

___

M3~1-o--:M~3~2~---------:=::=;~
o M16

M42

~OM29
M41 M38 o o M37
M30
M36~M35 M28~0M26
M27
M34~M33

M17 o

M43<>~M40~M39

BOOT/SELFTEST SWITCH

o M14
M12
M10
MB
M6

o M84

D·~'°

SWITCH

0 0
M5M4

fQIMB3

~MB2
I01MB1
WMBO
o M79

[;]~:~D
IOI

M78~M77
M76~M75
M74 o o M73

o M49
M48
~ M47

M72~M71

fOl M70
WM69
o M68

fOl

M46

IOI M45

M67
o M66
M66 ~[OJ M64
~M63

WM44

M62 [01 o M61

M60~folM59
~M58

M57 o
M56~M55
M54~M53
o M52

M25Uo M24
M23 o o M22
M21 o o M20
o M19
o M18

0@:21
M2

MA-11842

Figure 6-3

KXTl 1-CA SBC Jumper Layout

6-6

Table 6-1

Functional Jumper Pin Definition

Function

Jumpers

Base Address

M18 and M19

DMA Requests

M47, M48, M49, M50, M59

Parallel port

M49

Real-Time clock (60-Hz or 50-Hz)

M84, M82, M83

SLU 1 break (nonmaskable)

M81, M80

Memory
User socket sites

M57, M66, M61, M55, M60, M65, M63, M58,
M52, M67, M64, M59, M56, M53, M62

Memory map selection

M24, M25, M22, M23, M20, M21

Battery backup
Ml, M2, M3
M68, M69, M70

On-Board RAM
User RAM (if installed)

SLUl
Programmable baud rate

M72, M74, M76, M78, M75, M73, M71, M77

Serial output (RS422, RS423)

M43, M41, M42

Serial input

M5,M4

SLU2
Channel A

M13, Ml2, Ml7, Ml6, Mll, MlO, M9, M8,
M15, Ml4, M7, M6

Channel B

M39, M40, M38, M37, M46, M45, M44, M34,
M33, M28, M26, M35, M36, M29, M32, M27,
M31, M30, M43

6-7

Table 6-2

Factory Shipped Jumper Configuration

Function

Jumpers Installed*

Base address

Low range Uumper out)

Interrupts
SLU2 channel A
SLU2 channel B
Real-Time clock R TC60
SLU 1 (break)

M51 to M50
M47 to M48
M82 to M83
M81 to M80

Memories
2 K X 8 EPROM
Memory map 0
Battery backup (no)
User RAM (no)

M53 to M55
No jumpers installed
Ml to M2
M69 to M70

SLUl
Serial baud/bits
Rate (300)
Receiver RS422

No jumpers installed
M4 to M5

SLU2
Channel A receiver
RS422

M15 to M14
M13 to M12
Mll to MlO
M7 to M6
MS to M9

Channel B receiver
RS422 option

M17 to M16
M37 to M38
M33 to M34
M35 to M30

Channel B transmitter
RS422 option

M28 to M27
M32 to M30
M39 to M40

Boot/Selftest switch
•

Position 10

There are no connections to the following jumper pins: M3, Ml8, Ml9, M20, M21, M22, M23, M24, M25, M26, M29, M31,
M41, M42, M43, M44, M45, M46, M49, M52, M54, M56, M57 through M68, M71 through M79, and M84.

Paragraphs 6.3.1 through 6.3.16 contain specific jumper configuration information for each functional
grouping of jumpers. You can use this information to select the correct configuration for your application.
Each paragraph contains a brief description about the particular functional grouping. The SBC layout
drawing follows, with an expanded view of the jumper grouping that is being described. Following the
layout drawing are all the possible jumper configurations for that particular grouping and a description of
each. An asterisk to the left of jumpers denotes the factory shipped configuration.

6-8

6.3.1

User EPROM, EEPROM and RAM
The user can install EPROMs, EEPROMs or RAMs into the two user socket sites (Figures 6-4 and 6-5).
Tables 6-3 and 6-4 list jumper configurations for several memory chips. The user may select chips from
other vendors, however, pin configurations must be compatible. Selected EPROMs or RAMs must meet a
maximum enable time of 250 ns and a maximum access time of 450 ns.

D.__I_ __.ID D D ..__I:.----' D
...
o M67 o M66

o M65 o M64
o M63

o M62 o M61
o M60 o M59
o M58

o M57
o M56 o M55

o M54 o M53
o M52

MA·11896

Figure 6-4

User EPROM and RAM Jumper Configurations

USER SOCKET SITES

CHIPS

LEFT EDGE OF
PC BOARD
COMPONENT
SIDE

PIN 12 OF CHIP
PIN 14 OF SOCKET

NOTE: PIN 12 OF THE USER'S CHIP, 24 PIN OR 28 PIN, IS
INSERTED INTO PIN 14 OF THE USER SOCKET SITES.
SHOWN INSERTED IS A 24 PIN CHIP.
MR·12618

Figure 6-5

User Socket Sites

6-9

Table 6-3 EPROM Configuration
Intel
Part No.

2716
2732
2764
27128

Pins

24t
24t
28
28

Size

Pin Number

2KX8
4KX8
8KX8
16 K X 8

56
to
55

61
to
62

55
to
53

52
to
53

61
to
59

58
to
59*

66
to
67

66
to
64

63
to
64*

Out
Out
In
In

In
In
Out
Out

Out
Out
Out
In

In
Out
Out In
Out In
Out In

Out
Out
In
In

In
Out
Out
Out

Out
In
In
In

Table 6-4 RAM Configurations
Toshiba
Part No.

TMM2016P-01
TMM5565P-1

Pins

24t
28:!:

Size

2KX8
8KX8

Pin Number
62*
to
60

53*
to
54

53
to
55

59
to
60

67*
to
65

64
to
65

59*
to
58

64*
to
63

56
to
55

Out
In

In
Out

Out
In

In
Out

Out
In

Factory shipped configuration.
For proper insertion of 24-pin chips into the user sockets, see Figure 6-5.
When 28-pin RAM devices are installed, M57 is jumpered to either M56 (+5 V source) or M55 (+5 V battery backup source).

6-10

6.3.2 Battery Backup
The user can select the battery backup configuration to maintain a +5 Vdc battery supply to the 16 K
static RAM after the de power is removed. (See Figure 6-6.)

D. .__I_

__,ID D 0.1......_:.----' D

...

..
..
...
..
.

Figure 6-6

Description

*M3

No battery backup for RAMs.

M2
lo

Ml
0

0 0 0

Ei=

Battery Backup Selection

Jumper Connection
()

Battery backup for RAMs selected. The user must supply battery
backup voltage to pin AVl.

*Factory shipped configuration.

6-11

6.3.3 User Socket +S V Power
If the 32 Kb static RAM is jumpered for battery backup, then the user socket also can be jumpered for
battery backup. Refer to Figure 6-7.

. _ _ I_

o M70
o M69
o M68

___.ID c:;3 :D.
... .

._
: _.
I
- - - - '

...
..
..
.. .

MR·11897

Figure 6-7 User Socket +5 V Power

Jumper Connection

Description

fOIM70
l.QJM69*
o M68

Jumpers +5 V from the Q-Bus source.

o M70
fOIM69
lEJM68

Jumpers +5 V from the on-board 32 Kb static RAM +5 V source.

*Factory shipped configuration.

6-12

6.3.4 Memory Maps
Figure 6-8 shows and Table 6-5 lists the jumper configuraton for the eight memory maps (Figure 6-9)
available to the user.

D.___I_____.ID ~ :D.._:_I.----'~ D
..

.....

D
D

..
...
.. ..

M25 0 0 M24
M23 o o M22
M21 o o M20

®
MA-11906

Memory
Map

Figure 6-8

Memory Map Jumper Configurations

Table 6-5

Memory Map Jumper Configurations

Jumper Connection
M24 to M2S
M22 to M23

1
2
3
4
5
6
7

Out

In
Out

In
In
Out
Out

*Factory shipped configuration.

6-13

M20 to M21

In
In
In
In
Out
Out
Out
Out

1K 1/0 PAGE

173777

1K 1/0 PAGE

2K NATIVE FIRMWARE

163777
1K SELF TEST OVERLAY

157777

NXM
137777

---

1K SELF TEST OVERLAY

-----1
4K
*
NATIVE
FIRMWARE
EXTENSION

4K
*
NATIVE
FIRMWARE
EXTENSION

NXM
24

SK
SK
PROM/RAM PROM/RAM

RAM
117777

20
4K
PROM/RAM

107777
2K
PROM/RAM

100000

RAM

RAM
16K
PROM/RAM

RAM

SK
PROM/RAM

NXM

4
4K
PROM/RAM

2K
PROM/RAM

MAPO

MAP 1

MAP2

MAP3

MAP4

MAP5

MAPS

MAP7

000

001

010

011

100

101

110

111

KXTCSRB

<3-1>

*NOT CURRENTLY SUPPORTED
**THE TOP 64 BYTES OF NATIVE RAM ARE RESERVED BY NATIVE FIRMWARE
MR-11673

Figure 6-9

Memory Maps

6-14

6.3.S Boot/Selftest Switch
The boot/selftest switch selections are divided into two major functions: first, standalone booting from the
user ROM into the application code memory area; second, selftests. Figure 6-10 shows the boot/selftest
switch; Table 6-6 describes its functions .

...._____.D D. .D . ...
..

BOOT/SELFTEST SWITCH

....

. _ _ _ I_

____,

.. ..
...
.. .
.

MA-11902

Figure 6-10

Table 6-6
Switch
Position

Boot/Selftest Switch

Boot/Selftest Switch Functions

Description

Standalone Boot
0

User ROM application code is executed; no selftest is performed.

Application code in user ROM is executed; a selftest is performed.

Application code in user ROM is executed; selftest and ROM test are
performed.

Boot application code from TU58 drive unit; a selftest is performed.

No auto selftest; enter serial ODT.

6-15

Table 6-6
Switch
Position

Boot/Selftest Switch Functions (Cont)

Description

System Boot
5

Selftest is performed; do not boot; wait for boot command from arbiter.

No selftest performed; do not boot; wait for boot command from arbiter.

Reserved.

Dedicated Test
8

Used for standalone testing. Selftest is performed; loopback test is run; no
application code is run; the RAM is mapped low.

Used for standalone testing. Selftest and user ROM test are performed; loopback test is run; no application is code run; the RAM is mapped low.

10*

For use when running XXDP+ diagnostics. Selftest is performed; wait for
additional test commands; the RAM is mapped low.

11-15

Reserved.

*Factory shipped configuration.

6.3.6 Q-Bus Base Address (ID Switch)
The jumper between M18 and M19 enables the user to select either a high or low base address range. The
system ID switch enables the user to select one of 14 base addresses within a range. The high base address
range should be used if a Falcon SBC or more than 8KXTl1-CA SBCs are on the Q-Bus due to a conflict
of CPU addressing. Figure 6-11 shows and Table 6-7 lists the Q-Bus base address configurations.

6-16

Dl._______.I D D D_...__:. SBCID
SWITCH

...
..

..
.... ..
.

o M19
o M18

MA-11905

Figure 6-11

Q-Bus Base Address Configurations

Table 6-7 Q-Bus Base Address Configurations

ID Switch
Position

0
1

2
3
4
5*
6
7
8
9

10
11
12
13
14

Low Range*
M18 to M19
Out
SBC Base
Address

t
t

17760100
17760140
17760200
17760240
17760300
17760340
17775400
17775440
17775500
17775540
17775600
17775640
17775700
17775740

High Range
M18 to M19
In
SBC Base
Address

17762100
17762140
17762200
17762240
17762300
17762340
17777400t
17777440t
17777500t
17777540+
17777600t
17777640t
17777700t
17777740t

Factory shipped configuration.
For these two switch positions, the Q-Bus interface is disabled.
Caution - Using these base addresses may conflict with existing Q-Bus devices.

6-17

6.3. 7 Real-Time Clock Interrupt
The real-time clock interrupt can be set for either 50-Hz or 60-Hz operation. (See Figure 6-12.)

o M84

D-1__ID ~=D.I.__:.----' D
..

o M83
o M82

..
.. .
.

MR-11903

Figure 6-12 Real-Time Clock Interrupt

Jumper Connection

Description

o M84
f01M83
l_gJM82*

Selects the real-time clock 60-Hz interrupt

JolM84
[2JM83
o M82

Selects the real-time clock 50-Hz interrupt

*Factory shipped configuration.

6-18

6.3.8 Break Enable
This interrupt (Figure 6-13) is controlled by the user via the console BREAK key, causing a nonmaskable
T-11 trap to restart.

.____I_

__.ID

.____I
• _

___.

o M81
o M80
o M79

D
D

MR-11899

Figure 6-13

Break Enable

Jumper Connection

Description

f01M81

Selects console SLU 1 break key interrupt

~M80*

o M79
o M81
iolM80

Disables SLU l console BREAK key interrupt

~M79

*Factory shipped configuration.

6-19

6.3.9 SLUI Transmitter
SLU 1 can be configured to transmit either single-ended (RS423) or differential (RS422) asynchronous
serial data out on connector J3. (See Figure 6-14.)

0 ____.l~j iD·'.:..
.___I

M43 M41
0

0 0

M42

.....
. ..
...
.. ..

D ....
MA-11894

Figure 6-14 SLU 1 Transmitter

Jumper Connection
M43
0

M43
lo

M42
lo
M42
0

M41*
ol

Description
SLUl console serial output is jumpered for RS423 transmission.

M41
0

SLUl console seerial output is jumpered for RS422 transmission.

*Factory shipped configuration.

6-20

6.3.10 SLUt Receh·er
SLU 1 can be configured to receive either single-ended (RS423) or differential (RS422) asynchronous
serial data in on connector J3. (See Figure 6-15.)

IDoDI. . .

D
0

M5M4

....

..
...
.. .
.

c:::::J

MR·11907

Figure 6-15

SLU 1 Receiver

Jumper Connection

Description

M5* M4

SLUI console serial input single-ended input.

SLU 1 console serial input differential input.

*Factory shipped configuration.

6-21

6.3.11 SLUI Baud Rate
SLUl output baud/bit rate (Figure 6-16, Table 6-8) is hardware programmable from 300 baud to 38400
baud when jumper M78 to M77 is inserted. If this jumper is not inserted, the baud rate is under software
control.

0.__I_

__.ID D D_.__I
: .---' D

o M78 o M77
o M76 o M75
o M74 o M73
o M72 o M71

..
..
...
. ..

D ..
MR-11898

Figure 6-16

SLUl Baud Rate

Table 6-8

SLUI Baud Rate

Baud Rate
(Bits/S)

Jumper Connection
M72 to M71

M74 to M73

M76 to M75

38400
19200
9600*
4800
2400
1200
600
300

In
In
In
In
Out
Out
Out
Out

In
In
Out
Out
In
In
Out
Out

In
Out
In
Out
In
Out
In
Out

*Factory shipped configuration.

6-22

6.3.12 DMA Requests
There are three DMA request lines to the direct transfer controller (DTC). Two request lines come from
SLU2 channels A and B. The third request comes from the counter /timer (8036) chip. Only two of the
three requests can be jumpered in at one time. (See Figure 6-17.)

D.__I_

__.ID D D_.__l
. ____. D

o M51
o M50

~o ~::'fif\D
\J:..)
M47

..
.

MR-11901

Figure 6-17

DMA Requests

Jumper Connection

Description

lo]M51 *

Jumpers a DMA request from SLU2 channel A.

~M50t

o M49
o M48
o M47
o M51
o M50t
roJM49
l.2JM48
o M47

Jumpers a DMA request from the counter /timer chip.

o M51*
o M50t
o M49
f01M48
l£1M47

Jumpers a DMA request from SLU2 channel B.

* Factory shipped configuration.

t Do not place a jumper from M49 to M50 because this configuration is not supported.

6-23

6.3.13 SLU2 Channel A Receiver
SLU2 channel A output (Figure 6-18) can be either single-ended for RS423 receiver or differential for
RS422 receiver. Channel A receives a synchronous/asynchronous serial data in on connector J 1.
M17 o
M15 o
M13 o
M11 Ci

o M16
o M14
o M12
o M10

M900M8
M7 o o M6

....
..
.....
..

.
Figure 6-18

D ....

SLU2 Channel A Receiver

Jumper Connectiont

Description

M17 0
MIS 0
M13 o
Mll o
M9 0
M7 0

o M16
0 M14
0 M12
o MIO
o M8
o M6

SLU2 channel A single-ended (RS423) receiver operation

Ml7
MIS
Ml3
Mll
M9
M7

0
0
0
0
0
0

•

0
0
0
0
0
0

Ml6*
Ml4*
Ml2*
MIO*
M8*
M6 *

SLU2 differential input (RS422)

Factory shipped configuration.
Jumpers are inserted horizontally for a differential signal.

6-24

6.3.14 SLU2 Channel B Operation
SLU2 channel B (Figure 6-19) can be configured to receive either driver (differential or single-ended) or
party line signals (CCITT R1360) in on connector J2.

D.__I_

.....
.
...
...
.. .
..

__,ID D D_.___I:. - - D

...

o M46
o
0

·o
:

M45'@•
M44

•

1:1

D ....
MR-11900

Figure 6-19 SLU2 Channel B Operation

Jumper Connection

Description

M46f0l

R 1360 party line input signal

M45~

M44o
M46o
M45iol *
M44ill_I

TT104B input signal (RS423)

*Factory shipped configuration.

6-25

6.3.15 SLU2 Channel B Receiver
SLU2 channel B input (Figure 6-20) can be configured for RS422 (differential) or RS423 (single-ended)
receiver operation. Channel B output can be configured for either RS423 (single-ended), RS422 (differential), or party line (CCITT R1360) operation. When configured for party line operation, a jumper is
inserted between M39 and M40 for party line termination.

0.__I-~10 o o .. . ._1.-~ 0
"k)
=

M38 o o M37
M36 o o M35
M34 o o M33

..
.. ..
.

D
D

MR·11895

Figure 6-20 SLU2 Channel B Receiver

Jumper Connection

Description

o M37
o M35
o M33

RS423 receiver operation

M38 o o M37*
M36~M35

RS422 receiver operation

M38I 0
0 I M37
M36 ~o--o_. M35
M34 o o M33

Party line receiver operation

M38 o
M36 o
M34 o

M34~M33

*Factory shipped configuration.

6-26

6.3.16 SLU2 Channel B Transmitter
SLU2 channel B transmitter (Figure 6-21) can be selected for one of three operation moves: RS423
(single-ended), RS422 (differential), or party line. The channel transmits synchronous/asynchronous serial
data out on connector J2.

0!._______.ID
M40 O o M39

M31o O OM29
M30
M28 O o OM26
M27

.
...
.. .
.

D
MR-11893

Figure 6-21

SLU2 Channel B Transmitter

OM32
M400

0 M39

M31~ OM29
M30
M280

RS423 TRANSMITTER OPERATION.

0 M26

M27

M400

OM39

M31 0

~ M~ 2M29
RS422 TRANSMITTER OPERATION.

M30

M28~ OM26
M27

OM32

M40~M39

M310

~M29
M30

M280

CITT 1360 PARTYLINE OPERATION.

0 M26

M27
NOTE: IF TERMINATION IS NEEDED M39 TO M40 IS JUMPERED.
MR-12619

6-27

6.4 POWER SUPPLY
The choice of power supply is controlled by the size of the system and packaging requirements. An
important consideration is the performance of the supply during power-up and power-down. All Digital
Equipment Corporation power supplies listed in the Microcomputer Interfaces Handbook are compatible
with the Q-Bus protocol which allows dependable operation with no loss of data when using battery
' backed-up memories.
6.5 BACKPLANE INSTALLATION
The KXTI I-CA board can be inserted into either of the two currently available types of standard
backplane assemblies made by Digital Equipment Corporation. One backplane assembly is the Q/Q22-CD
type (H9273), and the other backplane assembly is the Q/Q22-Q/Q22 type (H9275). An important point
to remember when installing a KXTI 1-CA SBC into either of these backplane assemblies is the bus grant
continuity. Both types of backplanes have unique bus grant daisy-chain arrangements and are priority
structured. The highest priority propagates away from the top-most slot downward. The user can ensure
proper grant continuity for all backplane-installed boards by inserting each device in the first slot
physically below a previously installed board referenced from the assembly top.
The Q/Q22-CD backplane assembly is shown in Figure 6-22. It can accept both double-height and quad. height boards. If double-height boards are inserted, the grant continuity is supported only for slots A and
B. Any double-height boards inserted in slots C and Dare not supported. The KXTl 1-CA board grant
continuity is supported with this backplane assembly.
The Q/Q22-Q/Q22 backplane assembly is shown in Figure 6-22 also. It can accept both double-height
and quad-height boards. Double-height board grant continuity is supported for both slots A and B and C
and D. In addition, quad-height KXTl 1-CA board grant signal continuity is supported on the KXTI 1-CA
board with mounted jumpers Wl and W2. If, however, a quad-height KXTl 1-CA board is to be installed
at a lower priority than an existing double-height board, then a grant card (G7272) must be installed. The
grant card and backplane are shown in Figure 6-23.

6-28

figure 6-22 0/022-CD Backplane ;..ssernbly

figure 6-23 0/022-0/022 Backplane ;..sscrnblY With Grant Card

6-29

6.6 BACKPLANE PIN IDENTIFICATION
Table 6-9 lists backplane pin connections for the KXT I I-CA SBC, pin identification and signal names
unique to the KXTI I-CA SBC, and standard Q-Bus backplane names assigned to each pin. Although the
signal names may differ, the SBC is completely Q-Bus-compatible, with the exception of bus refresh
transaction (BREF), which is not performed by the KXTI I-CA SBC.

Table 6-9
Backplane
Pin

KXTll-CA Backplane Pin Identification
KXTll-CA
Signal Function

Q-Bus
Signal Name

Side 1 (Component Side)
AAI
ABI
ACI
ADI
AEl
AFl
AHi
AJI
AKI
ALI
AMI
ANl
API
ARI
ASI
ATl
AUl
AVI

Not connected
Not connected
Bus terminator
Bus terminator
Not connected
Not connected
Not connected
GND
Not connected
Not connected
GND
BDMRL
BHALT L
Not connected
Not connected
GND
Not connected
+5 VB (battery)

BIRQ5 L
BIRQ6 L
BDALl6 L
BDALl7 L
SSPAREl
SSPARE2
SSPARE3
GND
MSPAREA
MSPAREA
GND
BDMR L
BHALT L
BREF L
+I2B
GND
PSPAREl
+5B

BAI
BBI
BCI
BDI
BEl
BFI
BHI
BJI
BKI
BLI
BMI
BNI
BPI
BRl
BSI
BTI
BUI
BVI

BDCOK H
BPOKH
BDAL18 L
BDAL19 L
BDAL20 L
BDAL2I L
START L
GND
Not connected
,Not connected
GND
BSACK L
Not connected
Not connected
Not connected
GND
Not connected
+5 v

BDCOK H
BPOK H
SSPARE4
SSPARE5
SSPARE6
SSPARE7
SSPARE8

6-30

MSPAREB
MSPAREB
BSACK L
BIRQ7 L
BEVNT L
+128
GND
PSPARE2
+5 v

Table 6-9

KXTt 1-CA Backplane Pin Identification (Cont)
KXTtt-CA
Signal Function

Q-Bus
Signal Name

AA2
AB2
AC2
A02
AE2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

+5 v
Not connected
GNO
+12 v
BOOUT L
BRPLY L
BOIN L
BSYNC L
BWTBT L
BIRQ4 L
BIAKI L
BIAKO L
BBS7 L
BOMGI L
BOMGO L
BINIT L
BOALO L
BOALl L

+5 v
-12 v
GNO
+12 v
BOOUT L
BRPLY L
BOIN L
BSYNC L
BWTBT L
BIRQ4 L
BIAKI L
BIAKO L
BBS7 L
BOMGI L
BOMGO L
BINIT L
BOALO L
BOALl L

BA2
BB2
BC2
B02
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

+5 v
Not connected
GNO
+12 v
BOAL2 L
BOAL3 L
BOAL4 L
BOAL5 L
BOAL6 L
BOAL7 L
BOA[8 L
BOAL9 L
BOALlO L
BOALll L
BOAL12 L
BOAL13 L
BOAL14 L
BOAL15 L

+5 v
-12 v
GNO
+12 v
BOAL2 L
BOAL3 L
BOAL4 L
BOAL5 L
BOAL6 L
BOAL7 L
BOALS L
BOAL9 L
BOALlO L
BOALll L
BOAL12 L
BOAL13 L
BOAL14 L
BOAL15 L

Backplane
Pin
Side 2 (Solder Side)

6-31

6.7 EXTERNAL CABLES
The SBC has a 40-pin connector (J4) for an external interface with the programmable 1/0 interface, a 40pin connector for full modem support interface (J 1), and two 10-pin connectors (J2 and 13) for the
external interface of the serial line units (SLUs). The locations of these connectors on the SBC are shown
in Figure 6-22. The requirements to interface with these connectors are defined in the following
paragraphs.
6.7.1 Parallel I/O Interface (J4)
The 1/0 signals are buffered and are capable of driving up to 50 feet (maximum) of flat ribbon or round
cable with a 40-pin AMP contact housing at each end. The following two cables are compatible with the
module connector.
1.
2.

BC05 L mirror image cable
BC06 R shielded ribbon cable

Figure 6-24 shows the PIO connector pin assignments.

SG SG SG

SG SG SG SG C1

A7 A6 AS A4 A3

C2 SG

SG SG SG SG

AA CC EE HH KK MM PP

DD FF

NN RR TT VV

co BO B1 B2 B3 B4 BS B6 B7
SG

SG SG SG SG
SS

NOTE: SG =SIGNAL GROUND
AO-A7= PORT A
BO- B7 = PORT B
CO- C7 =PORT C
MR-12615

Figure 6-24

PIO Connector Pin Assignments

6.7.2 Serial I/O Interfaces (Jt, J2 and J3)
Each serial line unit (SLU) is compatible with EIA RS232-C and EIA RS423 serial type interfaces. SLUl
interfaces through 13, SLU2 channel A interfaces through J1, while SLU2 channel B interfaces through
12. When a 20 mA current loop device is needed, the DLVl 1-KA option must be used.
The user provides the interconnecting cables. The following list describes some standard Digital cables for
use with the KXTl 1-CA SBC and also provides some information to help the user design cables.
BC20N-05

5-foot EIA RS232-C null modem cable to directly interface with the EIA terminal (2 X 5
pin AMP female to RS232-C female)

BC21B-05

5-foot EIA RS232-C modem cable to interface with modems and acoustic couplers (2 X 5
pin AMP female to RS232-C male)

BC20M-50

50-foot EIA RS422 or RS423 cable for high throughput transmission (19.2 K baud)
between two KXTl 1-CA computers (2 X 5 pin AMP female to 2 X 5 pin AMP female)

6-32

When designing a cable for the KXT 11-CA SBC, the user should consider the following points.
I.

The receivers on the KXTl 1-CA SBC have differential inputs. Therefore, when designing an
RS232-C or RS423 cable, RECEIVE DATA- (pin 7 on the 2 X 5 pin AMP connector) must
be tied to signal ground (pins 2, 5, or 9) in order to maintain correct EIA levels. RS422 uses
both RECEIVE DATA+ and RECEIVE DATA-.

To directly connect to a local EIA RS232-C terminal, use a null modem. To design the null
modem into the cable, a user must switch RECEIVE DATA (pin 2) with TRANSMITTED
DATA (pin 3) on the RS232-C male connector as shown in Appendix H.

To mate to the 2 X 5 pin connector block, the following parts are needed.
Cable receptacle

AMP PN 87133-5
DEC PN 12-14268-02

Locking clip contacts

AMP PN 87124-1
DEC PN 12-14267-00

Key pin (pin 6)

AMP PN 87179-1
DEC PN 12-15418-00

The pin assignments for connector J2 and J3 are shown in Appendix F, Figure F-2. The pin assignments
for connector J1 are shown in Figure 6-25. Table 6-10 lists compatible 1/0 signal names for JI.

RC
SC
A

NC
IS

10
L

RD
RRR
H

ST
NC
M

BA
TM

RT
RS

cs
RDR

CA
IC
DMR TRR

RR
SD
AA

DM
NC

TTR

RSR
SDR
KK

NC
TR
MM

NC
CSR

TT
NC
HH

vv
101

STR
RTR
SS

uu
MR-12352

Figure 6-25

SLU2 Connector (Jl) Pin Assignments

Notes to Figure 6-25:
l.

Pins denoted by an asterisk(*) are driven by dummy generators and hold the RL (TT140), LL
(TT141), and SS (TTl 16) signals in the off state.

NC indicates no connection.

R attached to a two-letter code implies the RETURN side of a differential driver or receiver.

Signals marked with a $ are not supported.

Signals marked with a # can be defined by the user at the expense of another signal, i.e., circuit
IS can be redefined to mean SR and circuit TM can be redefined to mean SI, or only circuit IS
could be redefined to mean SF.

6-33

Table 6-10

Compatible 1/0 Signal Names
CCITT
Logical
Equivalent

JI (SLU2,

RS232-C Signal

Channel A)

RS449 Signal

40, VY
1, A

102
102a
102b

AB Signal ground

23, AA
8, J
30, JJ

SB Signal ground
SC Send common
RC Receive common
#IS Terminal in service
IC Incoming call
TR Terminal ready
OM Data mode
SD Send data
RD Receive data
TT Terminal timing

125
108/2
107
103
104
113

12, N

ST Send timing

114

14, R

RT Receive timing

115

13, p
16, T
24, BB

RS Request to send
CS Clear to send
RR Receiver ready

105
106
109

CE Ring indicator
CD Data terminal ready
CC Data set ready
BA Transmitted data
BB Received data
DA DTE signal element
timing (transmitter)
DB DCE signal element
timing (transmitter)
DD DCE receiver signal
element timing
CA Request to send
CB Clear to send
CF Received line signal
detector

5, E
N/A

#TM Test mode

N/A
N/A

$SS Select standby
SB Standby indicator
LL Local loopback
$RL Remote loopback
$SQ Signal quality
$NS New signal
#SF Select frequency

142
101 Signal
ground
116
117
141
140
110

2, B

3, c
20, x
33, M

22, z

N/A
N/A
N/A
See Note
See Note

#SR Signaling rate
selector

See Note

#SI Signaling rate
indicator

126 Select
transmit
frequency
111 DTE
data signal
rate
selector
112 DCE
data signal
rate
selector

CB Signal quality

CH DTE data
signal rate
selector
CI DCE data
signal rate
selector

Note:
A dollar sign ($) preceding a signal name indicates the signal is unsupported. A pound sign (#) preceding a signal name indicates
the signal can be defined by the user at the expense of another signal. For example, signal IS can be redefined to mean SR and
signal TM can be redefined to mean SI, or only signal IS could be redefined to mean signal SF.

6-34

6.8 LOOPBACK CONNECTORS
Three loopback connectors - part numbers H302 l, H3022 and H3270 - are used in testing the KXT 11CA single-board computer. Two 10-pin loopback connectors (H3270) are used: ( 1) SLU2 channel B
sync/async 1/0 connector J2, and (2) SLUl console 1/0 connector J3. The 40-pin loopback connector
(H3022) is used with SLU2 channel A sync/async 1/0 connector J 1. Note that the J 1 connector can be
configured, with I 0 switches, for RS422 or RS423 loopback operation. The 40-pin loopback connector
(H3021) is used with the parallel 1/0 connector J4. Insertion of the loopback connectors is shown in Figure
6-26. Users can design and build their own loopback connectors that are compatible. (See Appendix H for
information.)

t 1

~QQQ~Q~Q~~Q

Sl-1

Sl-2

Sl-3

Sl-4

Sl-5

Sl-6

Sl-7

Sl-8

Sl-9

S1-10

OFF

t 1 2 3 4 5 6 7 8 9 10

RS 423 TEST

~DDDQDQDQQD

Sl-1

Sl-2

S1-3

S1-4

Sl-5

S1-6

S1-7

Sl-8

Sl-9

S1-10

OFF

MR-11674

Figure 6-26

Loopback Connectors

6-35

6.9 KXTl 1-CA SBC DIAGNOSTIC TESTING PROCEDURES
After properly booting the XXDP+ diagnostic software, the user is required to answer all the console
prompts. Answering the console prompts builds entries into a table describing each KXTl 1-CA SBC
under test. The console prompts are as follows:
I.

Enter the date and answer the LSI and 50-Hz questions.

Type "R CZKTCA" to load the KXTl 1-CA test software.

After the test software is loaded into the arbiter, prompt "DS>" appears.

Type "START", then <CR>.

Answer the question, "CHANGE HW(L)?" with "Y", then <CR>.

Answer the question, "# UNITS (D) ?" with the number of units in the system, then <CR>.

The prompt "UNIT O" appears.

Answer the question, "SBC ID SWITCH SETTING (D) ?" with the setting of the SBC under
test, then <CR>.

Answer the question, "IS THE IOP'S LSI-11 ADDRESS IN THE LOW ADDRESS RANGE
(Y /N) ?" with "Y" if the jumper is in or "N" if it is out, then <CR>.

10.

Answer the question, "LOOP-BACK CONNECTOR ON SERIAL PORT #1 (L)" with "Y"
or "N", then <CR>.

11.

Answer the question, "CHANNEL A LOOP-BACK CONNECTOR ON SERIAL PORT #2
(L)" with "Y" or "N", then <CR>.

12.

Answer the question, "CHANNEL B LOOP-BACK CONNECTOR ON SERIAL PORT #2
(L) " with "Y" or "N", then <CR>.

13.

Answer the question, "LOOP-BACK CONNECTOR ON PARALLEL PORT (L)" with "Y"
or "N", then <CR>.

14.

Answer the question, "IS SLU2 SERIAL PORT CONFIGURED FOR DMA OPERATION
(L)" with "Y" or "N", then <CR>.

15.

Answer the question, "TEST USER ROM (L)" with "Y" or "N", then <CR>.

After the last <CR>, in step 15, the test software is immediately invoked.

6-36

6.10 ERROR INFORMATION
The results of the KXTI 1-CA selftest and firmware state will be displayed by the edge mounted LEDs.
The LEDs are used to indicate how far the SBC got intothe selftest process. Refer to Figure 6-27 for the
LED display sequence and error codes.
On power-up or reinitialization the LEDs are lit for approximately one-half second to demonstrate they
work correctly. The LEDs flicker as they cycle through the selftests. If LI is off after the completion of
the selftests, an error was encountered and is being displayed. The boot sequence continues if a nonfatal
error is detected, but the LEDs indicate the state in which the first error was detected. If the LEDs
encounter a fatal error, the boot sequence stops. If the SBC remains in the primary bootstrap or wait state,
this indicates a possible error in booting or master/IOP communications, respectively.

Definition

LED State*
Lt
L2
L3

x
x

x
x
x

x
x
x
x

x
x
x
x
x
x
x
x
x
0
0

x
x

All LEDs on for about 0.5 s only during power-up or reinitialization
Fatal SBC selftest error (SBC not functional)
Nonfatal SBC selftest error
User ROM low byte test failed or user RAM test failed
User ROM high byte test failed
Serial loop back of SLU 1 failed
Serial loopback of SLU2 channel A failed
Serial loopback of SLU2 channel B failed
Parallel loopback failed
Auto selftests running
Loopback tests running
Q-Bus ODT mode
Serial ODT mode
Waiting for command
Performing OMA load
TU58 primary bootstrap executing
Executing non-native code

Quick LED Reference
L2
L3
L4
Lt
0

x
x

No errors, state displayed
Normal, application running state
Error detected
Fatal error detected

x = On, o = Off, + = Either

LI lit indicates error display; LI unlit indicates state display. L2 through L4 lit indicate state of SBC.

Figure 6-27

LED Error Display

6-37

The not-running native code is the normal state of the SBC. This state is displayed when the application
code or a secondary loader is running and no errors were previously displayed. State changes are not
displayed by the LEDs if a previous error is being displayed.
There are three levels of error messages that may be issued by a diagnostic to the system arbiter: general,
basic, and extended.
General error messages are always printed unless the IER flag is set (see the XXDP+ User's Manual). The
general error message format follows:
NAME TYPE NUMBER ON UNIT NUMBER TEST NUMBER PC:XXXXXX
ERROR MESSAGE
WHERE; NAME = DIDAGNOSTIC NAME
TYPE = ERROR TYPE (SYS FATAL, HARDWARE OR SOFTWARE)
NUMBER = ERROR NUMBER
UNIT NUMBER= 0 - N
TEST NUMBER= TEST AND SUBTEST WHERE ERROR OCCURRED
PC:XXXXXX =ADDRESS OF ERROR MESSAGE CALL
Basic error messages are messages that contain some additional information about the error. These are
always printed unless the IER or IBR flags are set (see the XXDP+ User's Manual for details). These
messages are printed after the associated general messages.
Extended error messages contain supplementary error information such as register contents or good/bad
data. These are always printed unless the IER, IBR, or IXR flags are set (see the XXDP+ User's Manual
for details). Messages are printed after the associated general error message and any associated basic error.

6-38

APPENDIX A
ADDRESSING MODES AND INSTRUCTION SET

A.1 INTRODUCTION
This appendix provides a detailed description of addressing modes and of individual instructions. The
description of addressing modes is divided into six major topics.
1.

Single-operand addressing - One part of the instruction word specifies the registers; the remaining part provides information for locating the operand.

Double-operand addressing - Part of the instruction word specifies the registers; the remaining
parts provide information for locating two operands.

Direct addressing - The operand is the content of the selected register.

Deferred (indirect) addressing - The content of the selected register is the address of the
operand.

Use of the program counter (PC) as a general-purpose register - The PC is unique from other
general-purpose registers. Whenever the processor retrieves an instruction, it automatically
advances the PC by two. By combining this automatic advancement of the PC with four of the
basic addressing modes, four special PC modes are produced - immediate, absolute, relative,
and relative deferred.

Use of the stack pointer (SP) as a general-purpose register - The SP can be used for stack
operations.
NOTE
Instruction mnemonics and address mode symbols
are sufficient for writing assembly language programs. The programmer need not be concerned
about conversion to binary digits; this is accomplished automatically by the assembler program.

A.2 ADDRESSING MODES
Data stored in memory must be accessed and manipulated. Data handling is specified by a KXTI 1-CA
instruction (MOY, ADD, etc.) that usually specifies the following.
1.

The function to be performed (operation code).

A general-purpose register to be used when locating the source and/or destination operand.

An addressing mode that specifies how the selected register(s) is/are to be used.

A-I

Most data handled by a computer is structured (in character strings, arrays, lists, etc.). KXTI I-CA
addressing modes allow efficient and flexible handling of structured data.
The general-purpose registers may be used with an instruction in any of the following four ways.
I.

As accumulators - The data to be manipulated resides within the register.

As pointers - The content of the register is the operand address, rather than the operand itself.

As pointers that automatically step through memory locations - Automatically stepping forward through consecutive locations is known as autoincrement addressing; automatically stepping backward is known as autodecrement addressing. These modes are particularly useful for
processing tabular or array data.

As index registers - The register contents and the word following the instruction are summed to
produce the address of the operand. This allows easy access to variable entries in a list.

The register arrangement is an important microprocessor feature that should be considered in conjunction
with the addressing modes. There are six general-purpose registers (RO-RS), a hardware stack pointer (SP)
register (R6), and a program counter (PC) register (R 7).
Registers RO-RS are not dedicated to any specific function; their use is determined by the instruction that
is decoded.
I.

They can be used for operand storage. For example, the contents of two registers can be added
and stored in another register.

They can contain the address of an operand or serve as pointers to the address of an operand.

They can be used for the autoincrement or autodecrement features.

They can be used as index registers for convenient data and program access.

The KXTI I-CA SBC also has instruction-addressing mode combinations that facilitate temporary data
storage structures. These combinations can be used for conveniently handling data that must be accessed
frequently. This is known as stack manipulation. The register that keeps track of stack manipulation is the
stack pointer (SP). Any register can be used as a stack pointer under program control; however, certain
instructions associated with subroutine linkage and interrupt service automatically use register R6 as a
hardware stack pointer, and therefore, R6 is frequently referred to as the SP.
•

The stack pointer keeps track of the latest entry on the stack.

•

The stack pointer moves down as items are added to the stack and moves up as items are
removed. It always points to the top of the stack.

•

The hardware stack is used during trap or interrupt handling to store information and allow the
processor to return to the main program.

Register R 7 is used by the processor as its program counter (PC) and should not be used as a stack pointer
or accumulator. Whenever an instruction is fetched from memory, the program counter is automatically
incremented by two to point to the next instruction word.

A-2

A.2.1 Single-Operand Addressing
The instruction format for all single-operand instructions (such as clear, increment, and test) is illustrated
in Figure A-1.
06

02
Rn

OP CODE

DESTINATION ADDRESS
MR-5458

Figure A- I

Single Operand Addressing

Bits 15-6 specify the operation code that defines the type of instruction to be executed. Bits 5-0 form a
six-bit field called the destination address field that consists of two subfields.

Bits 0-2 specify which of the eight general-purpose registers is to be referenced by the instruction word.

Bits 3-5 specify how the selected register will be used (address mode). Bit 3 is set to indicate
deferred (indirect) addressing.

A.2.2 Double-Operand Addressing
Operations that imply two operands (such as add, subtract, move, and compare) are handled by instructions that specify two addresses. The first operand is called the source operand; the second operand is
called the destination operand. Bit assignments in the source and destination address fields may specify
different modes and different registers. The instruction format for the double-operand instruction is
illustrated in Figure A-2.

15
OP

~ODE

: MODE:

02
Rn

SOURCE ADDRESS

DESTINATION ADDRESS
MR-5459

Figure A-2

Double Operand Addressing

The source address field is used to select the source operand, the first operand. The destination is used
similarly and locates the second operand and the result. For example, the instruction ADD A, B adds the
contents (source operand) of location A to the contents (destination operand) of location B. After
execution, B will contain the result of the addition; the contents of A will be unchanged.
Examples in this chapter use the sample KXT 11-CA instructions listed in Table A-1. See Paragraph A.3
for a complete list of the KXT 11-CA instructions.

A-3

Table A-1

Sample KXTll-CA Instructions

Mnemonic

Description

CLR

Clear (zero the specified destination)

005000

CLRB

Clear byte (zero the byte in the specified
destination)

105000

INC

Increment (add one to the contents of the
destination)

005200

INCB

Increment byte (add one to the contents of
the destination byte)

105200

COM

Complement (replace the contents of the
destination by its logical complement; each
zero bit is set and each one bit is cleared)

005100

COMB

Complement byte (replace the contents of the
destination byte by its logical complement; each
zero bit is set and each one bit is cleared)

105100

ADD

Add (add source operand to destination operand
and store the result at destination address)

06SSOO

Octal Code

DD =destination field (6 bits)
SS

= source field ( 6 bits)

()

= contents of

A.2.3 Direct Addressing
Table A-2 summarizes the four basic modes used with direct addressing. Figures A-3, A-4, A-5, and A-6,
which follow the table, illustrate these four modes.
Table A-2

Direct Addressing Modes

Mode

Name

Assembler
Syntax

Function

A utoincrement

(Rn)+

Autodecrement

-(R~

Index

X(Rn)

Register is decremented and then used as a pointer.
Value X is added to (Rn) to produce address of
operand.
Neither X nor (Rn) is modified.

A-4

INSTRUCTION

OPERAND
MR-5460

INSTRUCTION

Figure A-3

Mode 0 Register

ADDRESS

OPERAND

+2 FOR WORD,
+1 FOR BYTE

Figure A-4

INSTRUCTION

Mode 2 Autoincrement

-2 FOR WORD,
-1 FOR BYTE

ADDRESS

OPERAND

MR-6462

Figure A-5

INSTRUCTION

Mode 4 Autodecrement

ADDRESS
OPERAND

x
MA.0463

Figure A-6

Mode 6 Index

A-5

A.2.3.1 Register Mode (Mode 0)- With register mode, any of the general-purpose registers may be used
as simple accumulators, and the operand is contained in the selected register. Because they are hardware
registers, within the processor, the general-purpose registers operate at high speeds and provide speed
advantages when used for operating on frequently accessed variables. The assembler interprets and
assembles instructions in the following forrri as register mode operations.
OPR Rn
Rn represents a general-purpose register name or number, and OPR represents a general instruction
mnemonic. Assembler syntax requires that a general-purpose register be defined as follows.
RO = %0 (The '%' sign indicates register definition.)
RI= %1
R2 = %2, etc.
Registers are typically referred to by name as RO, Rl, R2, R3, R4, R5, R6, and R7. However, R6 and R7
are also referred to as SP and PC, respectively.
Register Mode Examples (Figures A-7, A-8, and A-9)
(all numbers in octal)

Symbolic

Octal Code

Instruction
Name

INC R3

005203

Increment

One is added to the contents of generalpurpose register R3.

:o Io

15
0

Operation

OP CODE (INC(0052))

l I : : ~,SELECT
1

I REGISTER
I
I

DESTINATION FIELD

RO
R1
R2
R3

i
I
I

I
~J

R4
RS
R6 (SP)
R7 (PC)
MA-5467

Figure A-7

A-6

INC R3

Symbolic

Octal Code

Instruction
Name

ADD R2, R4

060204

Add

I
I

Operation
The contents of R2 are added to the contents of R4.

BEFORE
000002

000004

I
I

AFTER
000002

000006
MR-6468

Figure A-8

Symbolic

Octal Code

COMB R4

105104

ADD R2,R4

Instruction
Name

Operation

Complement
byte

Complement bits 0-7 (byte) of one in R4.
(When general-purpose registers are used,
byte instructions only operate on bits 0-7;
i.e., byte 0 of the register.)

BEFORE

AFTER

022222

022155

Figure A-9

COMB R4

A.2.3.2 Autoincrement Mode (Mode 2) - Autoincrement mode allows automatic stepping of a pointer
through sequential elements of a table of operands. It assumes that the content of the selected generalpurpose register is the address of the operand. Contents of registers are stepped (by one for bytes, by two
for words, and by two for R6 and R 7) to address the next sequential location. The autoincrement mode is
especially useful for array processing and stack processing; it accesses an element of a table and then steps
the pointer to address the next operand in the table. Although most useful for table handling, this mode is
general and may be used for a variety of purposes. The assembler interprets and assembles instructions in
the following form as autoincrement mode operations.
OPR (Rn)+
Autoincrement Mode Examples (Figures A-10, A-11, and A-12)

A-7

Symbolic

Octal Code

Instruction
Name

CLR (RS)+

00502S

Clear

Operation
The contents of RS are used as the
address of the operand. The selected operand is cleared, and the contents of RS are
then incremented by two.

AFTER

BEFORE
ADDRESS SPACE

20000

30000

OOS02S

ADDRESS SPACE

20000

30000

111l11s

00502S

030002

000000
MR-6464

Figure A-10

Symbolic

Octal Code

Instruction
Name

CLRB (RS)+

10S02S

Clear byte

CLR (RS)+

Operation
The contents of RS are used as the
address of the operand. The s~lected byte
operand is cleared, and the contents of RS
are then incremented by one.

BEFORE

AF1"ER

ADDRESS SPACE

20000

30002

10S02S

111

ADDRESS SPACE

030000

20000

!.~. I

10502S

030001

~rn
30002

MR-5466

Figure A-11

CLRB (RS)+

A-8

Symbolic

Octal Code

Instruction
Name

ADD (R2)+,R4

062204

Add

Operation
The contents of R2 are used as the
address of the operand that is added to
the contents of R4. R2 is then incremented by two.

AFTER

BEFORE
ADDRESS SPACE

10000

062204

100002

ADDRESS SPACES

REGISTERS

10000 1 062204

100002

010000

100002

010000

REGISTERS

100004

020000

010000
MR-5470

Figure A-12

ADD (R2)+,R4

A.2.3.3 Autodecrement Mode (Mode 4) - Autodecrement mode is useful for processing data in a list in
reverse direction. The contents of the selected general-purpose register are decremented (by two for word
instructions, by one for byte instructions) and then used as the address of the operand. The choice of
postincrement, predecrement features for the KXT 11-CA are not arbitrary; they are intended to facilitate
hardware/software stack operations. The assembler interprets and assembles instructions in the following
form as autodecrement mode operations.
OPR -(Rn)
Autodecrement Mode Examples (Figures A-13, A-14, and A-15)

Symbolic

Octal Code

Instruction
Name

INC -(RO)

005240

Increment

A-9

Operation
The contents of RO are decremented by
two and used as the address of the operand. The operand is incremented by one.

AFTER

BEFORE
ADDRESS SPACE
1ooo

17774

1 005240

ADDRESS SPACE

REGISTERS

017776

1000

17774

000000

I
I

005240

017774

000001
MR-5466

Figure A-13

INC -(RO)

Symbolic

Octal Code

Instruction
Name

INCB-(RO)

105240

Increment byte

Operation
The contents of RO are decremented by
one and used as the operand address.
The operand byte is increased by one.

BEFORE

AFTER

ADDRESS SPACE

1000

105240

ADDRESS SPACE

1000

017776

17774~

17774

[TI

17776

105240

001

017775

I ooo

MR-6471

Figure A-14

Symbolic

Octal Code

Instruction
Name

ADD -(R3),RO

064300

Add

INCB -(RO)

Operation
The contents of R3 are decremented by
two and then used as a pointer to an operand (source) which is added to the contents of RO (destination operand).

A-10

AFTER

BEFORE

, 0020

064300

000020

077776

ADDRESS SPACE

, 0020

064300

0000070

077774

77774~

77774

77776CJ

77776

Figure A-15

000050

ADD -(R3),RO

A.2.3.4 Index Mode (Mode 6) - With index mode, the contents of the selected general-purpose register
and an index word following the instruction word are summed to form the address of the operand. The
contents of the selected register may be used as a base for calculating a series of addresses, thus allowing
random access to elements of data structures. The selected register can then be modified by the program
to access data in the table. Index addressing instructions are in the following form:
OPR X(Rn)
where X is the indexed word and is located in the memory location following the instruction word, and Rn
is the selected general-purpose register.
Index Mode Examples (Figures A-16, A-17, and A-18)

Symbolic

Octal Code

Instruction
Name

CLR 200(R4)

005064
000200

Clear

Operation
The address of the operand is determined
by adding 200 to the contents of R4. The
operand location is cleared.

A-11

AFTER

BEFORE
ADDRESS SPACE

~
~

1020
1022

001000

1020

1024

1200
1202

1022
1000
+200
1200

1024

Octal Code

COMB 200(RI)

105161

1022

000200

001000

MR-6473

CLR 200(R4)

Instruction
Name

Operation

Complement
byte location

The contents of a 000200 that is determined by adding 200 to the contents of
Rl are one's complemented (i.e., logically complemented).

AFTER
ADDRESS SPACE

BEFORE
ADDRESS SPACE
REGISTER
1020

1m~
Figure A-16

Symbolic

ADDRESS SPACE

017777

1020

105161

1022

000200

017777

017777
+200

20176
20200

I,~,! ~1

020177
20176
20200

Figure A-17

ffi

COMB 200(Rl)

A-12

MR-7230

Symbolic

Octal Code

ADD 30(R2),20(R5)

066265
000030
000020

BEFORE
ADDRESS SPACE
1020

066265

1022

000030

1024

000020

1130

2020

Instruction
Name

Operation

Add
The contents of a location that
is determined by adding 30 to
the contents of R2 are added to
the contents of a location that is
determined by adding 20 to the
contents of R5. The result is
stored at the destination
address, i.e., 20(R5).

AFTER
ADDRESS SPACE

1020

066265

1022

000030

1024

000020

000001

1130

000001

2020

000002

001100

002000

001100

002000

1100 2000
+30 +20
1130 2020

Figure A-18

ADD 30(R2),20(R5)

A.2.4 Deferred (Indirect) Addressing
The four basic modes may also be used with deferred addressing. In the register mode, the operand is the
content of the selected register; in the register deferred mode, the content of the selected register is the
address of the operand. In the three other deferred modes, the contents of the register select the address of
the operand rather than the operand itself. Therefore, these modes are used when a table consists of
addresses rather than operands. Assembler syntax for indicating deferred addressing is '@' (or '()' when
this is not ambiguous). Table A-3 summarizes the deferred versions of the basic modes. Figures A-19,
A-20, A-21, and A-22, which follow the table, illustrate these deferred versions of the basic modes.

A-13

Table A-3 Indirect Addressing Modes
Mode

Name

Assembler
Syntax

Function

@Rn or (Rn)

Autoincrement
deferred

@(Rn)+

Register is first used as a pointer to a word containing the address of the operand and then incremented (always by two, even for byte instructions).

Autodecrement
deferred

@-(Rn)

Register is decremented (always by two, even for
byte instructions) and then used as a pointer to a
word containing the address of the operand.

Index
deferred

@X(Rn)

Value X (stored in a word following the instruction)
and (Rn) are added, and the sum is used as a
pointer to a word containing the address of the
operand. Neither X nor (Rn) is modified.

INSTRUCTION

ADDRESS

OPERAND
MR-6476

Figure A-19

INSTRUCTION

Mode 1 Register Deferred

ADDRESS

OPERAND

MR-5477

Figure A-20

INSTRUCTION

ADDRESS

Mode 3 Autoincrement Deferred

-2

ADDRESS

OPERAND

MR-5478

Figure A-21

Mode 5 Autodecrement Deferred

A-14

INSTRUCTION

ADDRESS
ADDRESS

OPERAND

x
MR-6479

Figure A-22

Mode 7 Index Deferred

Symbolic

Octal Code

Instruction
Name

CLR @RS

OOSOlS

Clear

Operation
The contents of the location specified in
RS are cleared.

BEFORE
ADDRESS SPACE
1677

1700

AFTER
REGISTER

ADDRESS SPACE

001700

1677

1700

Figure A-23

001700

MR-5480

CLR @RS

Autoincrement Deferred Mode Example - Mode 3 (Figure A-24)

Symbolic

Octal Code

Instruction
Name

INC @(R2)+

OOS232

Increment

A-IS

Operation
The contents of R2 are used as the
address of the address of the operand.
The operand is increased by one; and the
contents of R2 are incremented by two.

1010
1012

10000

BEFORE
ADDRESS SPACE
REGISTER

AFTER
ADDRESS SPACE
REGISTER

010300

1010
1012

10000

010302

~
MR-7231

Figure A-24

INC @(R2)+

Autodecrement Deferred Mode Example - Mode 5 (Figure A-25)

Symbolic

Octal Code

Instruction
Name

COM @-(RO)

005150

Complement

Operation
The contents of RO are decremented by
two and then used as the address of the
address of the operand. Operand is one's
complemented
(i.e.,
logically
complemented).

BEFORE
ADDRESS SPACE
REGISTER
10100
10102

10774
10776

010776

AFTER
ADDRESS SPACE
REGISTER

B
.

10100

010774

10102

t=j

10774
10776

Figure A-25

COM @ -(RO)

A-16

MR-7232

Index Deferred Mode Example - Mode 7 (Figure A-26)

Symbolic

Octal Code

ADD ®1000(R2),Rl

067201

Instruction
Name

Operation

Add
contents

I 000 and the 00 I 000 of R2 are
summed to produce the address
of the address of the source
operand. The contents of the
source operand are added to the
contents of RI; the result is
stored in RI .

BEFORE
ADDRESS SPACE
1020

067201

1022

001000

R2
1024

1050

AFTER
REGISTER

I
I

001234

ADDRESS SPACE
1020

067201

1022

001000

000100

1050

1100

001050

R2
1024

1100
1000
+100
1100

I
I

001236

000100

B
MR-5483

Figure A-26

ADD @1000(R2),Rl

A.2.5 Use of the PC as a General-Purpose Register
Although R7 is a general-purpose register, it doubles as the program counter for the microprocessor.
Whenever the processor uses the program counter to acquire a word from memory, the program counter is
automatically incremented by two to contain the address of the next word of the instruction being
executed or the address of the next instruction to be executed. (When the program uses the PC to locate
byte data, the PC is still incremented by two.)
The PC responds to all standard KXT 11-CA addressing modes. The PC, however, provides advantages for
handling position independent code and unstructured data with four of these modes. When utilizing the
PC, these modes are termed immediate, absolute (or immediate deferred), relative, and relative deferred.
Table A-4 provides a summary of these modes.

A-17

Table A-4

PC Register Addressing Modes

Mode

Name

Assembler
Syntax

Function

Immediate

Operand follows the instruction.

Absolute

@#A

Absolute address of operand follows the
instruction.

Relative

Relative address (index value) follows the
instruction.

Relative
deferred

@A
Index value (stored in the word following the
instruction) is the relative address for the address
of the operand.

When a standard program is available to different users, the ability to load it into different areas of
memory and run it is useful. The KXTl 1-CA can relocate a program efficiently using position independent code (PIC) that is written using the PC addressing modes. If an instruction and its operands are
moved so that the relative distance between them is not altered, the same offset relative to the PC can be
used in all positions in memory. Thus, PIC usually references locations relative to the current location.
The PC also facilitates the handling of unstructured data. This is particularly true of the immediate and
relative modes.
A.2.S.t Immediate Mode - Using the immediate mode is equivalent to using the autoincrement mode
with the PC. It provides time improvements for accessing constant operands by including the constant in
the memory location immediately following the instruction word. The assembler interprets and assembles
instructions in the following form as immediate mode operations.
QPR #n,DD
Immediate Mode Example (Figure A-27)

A-18

Symbolic

Octal Code

ADD #10,RO

062700
000010

Instruction
Name

Operation

Add
The value l 0 is located in the second
word of the instruction and is added to
the contents of RO. Just before this
instruction is fetched and executed, the
PC points to the first word of the instruction. The processor fetches the first word
and increments the PC by two. The
source operand mode is 27 (autoincrement the PC). Thus, the PC is used as a
pointer to fetch the operand (the second
word of the instruction) before being
incremented by two to point to the next
instruction.

AFTER
REGISTER
ADDRESS SPACE

BEFORE
ADDRESS SPACE
REGISTER

1020

062700

1022

000010

1024

I
I

000020

1020

062700

001020

1022

000010

1024

I
v I
RO

000030

001024

MR-7233

Figure A-27

ADD #10,RO

A.2.5.2 Absolute Addressing - Using the absolute addressing mode is the equivalent of using the
immediate deferred or autoincrement deferred modes with the PC. The contents of the location following
the instruction are taken as the address of the operand. Immediate data is interpreted as an absolute
address (i.e., an address that remains constant no matter where in memory the assembled instruction is
executed). The assembler interprets and assembles instructions in the following form as absolute addressing mode operations.
OPR @#A
Absolute Mode Examples (Figures A-28 and A-29)

Symbolic

Octal Code

CLR @#1100

005037
001100

Instruction
Name

Operation

Clear
The the contents of location 1100 are
cleared.

A-19

BEFORE
ADDRESS SPACE
20

005037

001100

AFTER
ADDRESS SPACE

005037

001100

1100
1102

t=j

1100
1102

Figure A-28

Symbolic

Octal Code

ADD @#2000,R3

063703
002000

Instruction
Name

The contents of location 2000
are added to R3.

063703

002000

I
I

AFTER
ADDRESS SPACE
REGISTER

000500

063703

000020

002000

Operation

Add

2000

MR~6485

CLR @#1100

BEFORE
ADDRESS SPACE
REGISTER

2000

001000
000024

I
MR-7234

Figure A-29

ADD @#2000,R3

A-20

A.2.5.3 Relative Addressing - The relative addressing mode is assembled as index mode using R 7. The
base of the address calculation, which is stored in the second or third word of the instruction, is not the
address of the operand, but the number that, when added to the PC, becomes the address of the operand.
This mode is useful for writing position independent code because the location referenced is always fixed
relative to the PC. When instructions are to be relocated, the operand is moved by the same amount. The
assembler interprets and assembles instructions in the following forms as relative addressing mode
operations.
OPR A
or
OPR X(PC)
where X is the location of A relative to the instruction.
Relative Addressing Example (Figure A-30)

Symbolic

Octal Code

INC A

005267
000054

Instruction
Name

Operation

Increment
To increment location A, contents of
memory location immediately following
instruction word are added to (PC) to produce address A. Contents of A are
increased by one.

AFTER
ADDRESS SPACE

BEFORE
ADDRESS SPACE

1020

005267

1022

000054

1020

0005267

1022

000054

1024

1026

1100

000000

1024
+54

1100

14-PC

000001

,__~~~~~~~~~1100

MR--6487

Figure A-30

A-21

INC A

A.2.5.4 Relative Deferred Addressing - The relative deferred addressing mode is similar to the relative
mode. The second word of the instruction, however, when added to the PC,. contains the address of the
address of the operand rather than the address of the operand. The assembler interprets and assembles
instructions in the following forms as relative deferred addressing mode operations.
OPR ®A
or
OPR @X(PC)
where X is the location containing the address of A relative to the instruction.
Relative Deferred Mode Example (Figure A-31)

Symbolic

Octal Code

CLR@A

005077

Instruction
Name
Clear
instruction

Operation
The second word of 000020 is added to
updated PC to produce the address of the
address of the operand. The operand is
cleared.

BEFORE
ADDRESS SPACE

1020

005077

1022

000020

AFTER
ADDRESS SPACE

1024
+20
1044

1024

'~
10100

100001

1020

005077

1022

000020

1024

1044

010100

10100

000000
MR-7235

Figure A-31

CLR@A

A.2.6 Use of the Stack Pointer as a General-Purpose Register
The processor stack pointer (SP, register R6) is the general-purpose register most often used for stack
operations related to program nesting. Autodecrement with register R6 pushes data onto the stack, and
autoincrement with register R6 pops data off the stack. Since the SP is used by the processor for interrupt
handling, it has a special attribute: autoincrements and autodecrements are always done in steps of two.
Byte operations using the SP in this way leave odd addresses unmodified.

A-22

A.3 INSTRUCTION SET
Specifications for each instruction in the KXT 11-CA instruction set follow and include each instruction's
mnemonic, octal code, binary code, a diagram showing the format of the instruction, a symbolic notation
describing its execution and effect on the condition codes, a description, special comments, and examples.
MNEMONIC: A mnemonic is indicated before each description. When the word instruction has a byte
equivalent, the byte mnemonic is also shown.
INSTRUCTION FORMAT: A diagram accompanying each instruction shows the octal op code, binary
op code, and bit assignments. In byte instructions, the most significant bit (bit 15) is always a one.
SYMBOLS: The following symbols are used in the instruction specifications.
()

= contents of

SS or src

= source address

DD or dst

= destination address

Joe

= location

+--

=becomes

= "is popped from stack"

= "is pushed onto stack"

= boolean AND

= boolean OR

= exclusive OR
= boolean not

Reg or R

=register

=Byte

•

0 for word
1 for byte
= concatenated

A-23

A.3.1

Instruction Formats

The following formats include all instructions used in the KXTI I-CA SBC. Refer to individual instructions for more detailed information.
I . Single-operand group:

CLR, CLRB, COM, COMB, INC, INCB, DEC,
DECB, NEG, NEGB, ADC, ADCB, SBC, SBCB,
TST, TSTB, ROR, RORB, ROL, ROLB, ASR,
ASRB, ASL, ASLB, JMP, SW AB, MFPS, MTPS,
SXT, XOR
06

Double-operand group:

BIT, BITB, BIC, BICB, BIS, BISB, ADD, SUB, MOY,
MOVB, CMP, CMPB
06

:
MR-5192

3. Program control group:
a.

Branch (all branch instructions)
15

OPC~DE

OF~SET
MR-6193

Jump to subroutine (JSR)

00
DD

MR-5194

Subroutine return (RTS)
15

02
R

:
MR-5195

A-24

Traps (breakpoint, IOT, EMT, TRAP, BPT)
00

MA-5196

Subtract 1 and branch if = 0 (SOB)
09

MR·5197

Operate group:

HALT, WAIT, RTI, RESET, RTT, NOP, MFPT
00

Condition code operators: (all condition code instructions)
06

MA-5199

A-25

Byte Instructions - The KXTt 1-CA includes a full complement of instructions that manipulate byte
operands. Because all microprocessor addressing is byte-oriented, byte manipulation addressing is straightforward. Byte instructions with autoincrement or autodecrement direct addressing cause the specified
register to be modified by one to point to the next byte of data. Byte operations in register mode access the
low-order byte of the specified register. These provisions enable the KXTl 1-CA SBC to perform as either
a word or byte microprocessor. The numbering scheme for word and byte addresses in memory is
illustrated in Figure A-32.
WORD OR BYTE
ADDRESS

HIGH BYTE
ADDRESS

002001

BYTE 1

BYTEO

002000

002003

BYTE 3

BYTE 2

002002

MR-5201

Figure A-32

Byte Instructions

The most significant bit (bit 15) of the instruction word is set to indicate a byte instruction.
Byte Instruction Example
Symbolic

Octal Code

Instruction Name

CLR
CLRB

0050DD
1050DD

Clear word
Clear byte

A.3.2 List of Instructions
The KXTl 1-CA instruction set is shown in Table A-5.

A-26

Table A-5

KXTt 1-CA Instruction Set

Instruction

Op Code

General
CLR(B)
COM(B)
INC(B)
DEC(B)
NEG(B)
TST(B)

Clear dst
Complement dst
Increment dst
Decrement dst
Negate dst
Test dst

•osooo
•051DD
•052DD
•053DD
•0'54DD
•057DD

Shift and Rotate
ASR(B)
ASL(B)
ROR(B)
ROL(B)
SWAB

Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Swap bytes

•062DD
•063DD
•060DD
•061DD
0003DD

Multiple Precision
ADC(B)
SBC(B)
SXT

Add carry
Subtract carry
Sign extend

•ossDD
•os6DD
0067DD

PS Word Operators
MFPS
MTPS

Move byte from PS
Move byte to PS

1067DD
1064SS

General
MOV(B)
CMP(B)
ADD
SUB

Move source to destination
Compare src to dst
Add src to dst
Subtract src from dst

•tSSDD
•2SSDD
06SSDD
16SSDD

Logical
BIT(B)
BIC(B)
BIS(B)
XOR

Bit test
Bit clear
Bit set
Exclusive OR

•3SSDD
•4SSDD
•sSSDD
074RDD

Mnemonic
SINGLE OPERAND

DOUBLE OPERAND

A-27

Table A-S
Mnemonic

KXTl 1-CA Instruction Set (Cont)

Instruction

Op Code

Branch (unconditional)
Branch if not equal (to zero)
Branch if equal (to zero)
Branch if plus
Branch if minus
Branch if overflow is clear
Branch if overflow is set
Branch if carry is clear
Branch if carry is set

000400
001000
001400
100000
100400
102000
102400
103000
103400

PROGRAM CONTROL
Branch
BR
BNE
BEQ
BPL
BMI

BVC
BYS

BCC
BCS

Signed Conditional Branch
BGE
Branch if greater than or equal (to zero)
BLT
Branch if less than (zero)
BGT
Branch if greater than (zero)
BLE
Branch if less than or equal (to zero)

002000
002400
003000
003400

Unsigned Conditional Branch
BHI
Branch if higher
BLOS
Branch if lower or same
BHIS
Branch if higher or same
BLO
Branch if lower

101000
101400
103000
103400

Jump and Subroutine
JMP
JSR
RTS

SOB
Trap and Interrupt
EMT
TRAP
BPT

IOT
RTI

RTT

Jump
Jump to subroutine
Return from subroutine
Subtract one and branch (if ::/=- 0)

OOOIDD
004RDD
00020R
077ROO

Emulator trap
Trap
Breakpoint trap
Input/output trap
Return from interrupt
Return from interrupt

104000-104377
104400-104777
000003
000004
000002
000006

Halt
Wait for interrupt
Reset external bus
Move processor type

000000
000001
000005
000007

MISCELLANEOUS
HALT
WAIT
RESET
MFPT

A-28

Table A-5
Mnemonic

KXTl 1-CA Instruction Set (Cont)
Op Code

Instruction

RESERVED INSTRUCTIONS

00021R
00022R
CONDITION CODE OPERATORS
CLC
CLY
CLZ
CLN
CCC
SEC
SEY
SEZ
SEN

Clear C
Clear Y
Clear Z
Clear N
Clear all CC bits
Set C
Set Y
Set Z
Set N
Set all CC bits
No operation

sec

NOP

000241
000242
000244
000250
000257
000261
000262
000264
000270
000277
000240

A.3.3 Single-Operand Instructions
NOTE
In most KXTl 1-CA instructions, a write operation
to a memory location or register is always preceded
by a read operation from the same location except
when writing PC and processor status (PS) to the
stack in the following two cases.
1.

The execution of the microcode preceding an
interrupt or trap service routine.

Interrupt and trap instructions:
HLT
TRAP
BPT
IOT

A-29

A.3.3.1

General -

CLR
CLRB
m<>50DD

Clear Destination
15

MA-5202

Operation:

(dst) ,_ 0

Condition Codes:

N: cleared
Z: set
V: cleared
C: cleared

Description:

Word:
Byte:

Contents of specified destination are replaced with zeros.
Same

Example:

CLR Rl
Before
(Rl) = 177777

After
(R 1) = 000000

NZVC
1 1 1 1

NZVC
0 1 0 0

COM
COMB
m<>51DD

Compiement Destination

MR-5203

Operation:

(dst) <- - (dst)

Condition Codes:

N:
Z:
V:
C:

set if most significant bit of result is set; cleared otherwise
set if result = 0; cleared otherwise
cleared
set
A-30

Description:

Word:
Byte:

The contents of the destination address are replaced by their logical
complement (each bit equal to zero is set, and each bit equal to one
is cleared).
Same

Example:

COM RO
Before
(RO)= 013333

After
(RO) = 164444

NZVC

0 1 1 0

1 0 0 1

INC
INCB
Increment Destination

ll052DD

01,; o : o : o : , : o : , : o :

05
d

00
:

d
MA-52CM

Operation:

(dst) ,_ (dst) + 1

Condition Codes:

N:
Z:
V:
C:

Description:

Word:
Byte:

set if result < O; cleared otherwise
set if result = 0; cleared otherwise
set if (dst) held 077777; cleared otherwise
not affected
One is added to contents of destination.
Same

Example:

INC R2
Before

After

(R2) = 000333

(R2) = 000334

NZVC

0 0 0 0

A-31

DEC
DECB
Decrement Destination

•053DD
06

Operation:

(dst) +- (dst) -1

Condition Codes:

N:
Z:
V:
C:

Description:

Word:
Byte:

set if result < 0, cleared otherwise
set is result = 0; cleared otherwise
set if (dst) was 100000; cleared otherwise
not affected
One is subtracted from the contents of the destination.
Same

Example:

DECR5
Before
(R5) = 000001

After
(R5) = 000000

NZVC

1 0 0 0

0 1 0 0

NEG
NEGB
Negate Destination

•054DD
06

I O/<

0 :

: :

05
d

MA-5206

Operation:

(dst) +- - (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

set if the result < 0; cleared otherwise
set if the result = O; cleared otherwise
set if the result is 100000; cleared otherwise
cleared if the result is O; set otherwise

Byte:

The contents of the destination address are replaced by its two's
complement. 100000 is replaced by itself (in two's complement
notation, the most negative number has no positive counterpart).
Same

Example:

NEGRO
Before
(RO) = 000010

After
(RO) = 177770

NZVC

0 0 0 0

1 0 0 1

A-32

TST
TSTB
Test Destination

•057DD
06

0/1:

0 :

1 :

0 :
MA-5207

Operation:

(dst) - (dst)

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

set if the result < 0; cleared otherwise
set if result = O; cleared otherwise
cleared
cleared

Byte:

The condition codes N and Z are set according to the contents of
the destination address, and the contents of the destination remain
unmodified.
Same

Example:

TST RI
Before
(RI)= OI2340

After
(RI)= OI2340

NZVC
0 0 I 1

NZVC

0 0 0 0

A.3.3.2 Shifts and Rotates - Scaling data by factors of two is accomplished with two shift instructions:
I.
2.

ASR - Arithmetic shift right
ASL - Arithmetic shift left

The sign bit (bit I 5) of the operand is reproduced in shifts to the right. The low-order bit is filled with zero
in shifts to the left. Bits shifted out of the C-bit, as shown in the following examples, are lost.
The rotate instructions operate on the destination word and the C-bit as though they formed a 17-bit
circular buffer. These instructions facilitate sequential bit testing and detailed bit manipulation.

A-33

ASR
ASRB

•062DD

Arithmetic Shift Right
06

15
O/<

1
MR-6208

Operation:

(dst) - (dst) shifted one place to the right

Condition Codes:

N: set if the high-order bit of the result is set (result< 0); cleared otherwise
Z: set if the result = O; cleared otherwise
V: loaded from the exclusive OR of the N-bit and C-bit (as set by the
completion of the shift operation)
C: loaded from the low-order bit of the destination

Description:

Word:
Byte:

All bits of the destination are shifted right one place. Bit 15 is
reproduced. The C-bit is loaded from bit 0 of the destination. ASR
performs signed division of the destination by two.
Same

Example:
WORD:

1--D-

re:·
r:J,
""
~--.--:----------:r8 L.11_ --=----=---:~-------~........._I-[]
BYTE:

000 ADDRESS

AOORESS

--=._:

MA-7236

A-34

ASL
ASLB
Arithmetic Shift Left

•063DD

15
0/1 :

0
MA-5210

Operation:

(dst) <---- (dst) shifted one place to the left

Condition Codes:

N: set if the high-order bit of the result is set (result< O); cleared otherwise
Z: set if the result = O; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set by the
completion of the shift operation)
C: loaded with the high-order bit of the destination

Description:

Word:

Byte:

All bits of the destination are shifted left one place. Bit 0 is loaded
with a zero. The C-bit of the status word is loaded from the most
significant bit of the destination. ASL performs signed multiplication of the destination by two with overflow indication.
Same

Example:
WORD:

BYrE:
ODD ADDRESS

EVEN ADDRESS

A-35

ROR
RORB

•060DD

Rotate Right

MR-5212

Operation:

(dst) +- (dst) rotate right one place

Condition Codes:

N: set if the high-order bit of the result is set (result < O); cleared otherwise
Z: set if all bits of result = 0; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set by the
completion of the rotate operation)
C: loaded with the low-order bit of the destination

Description:

Word:
Byte:

All bits of the destination are rotated right one place. Bit 0 is loaded
into the C-bit, and the previous contents of the C-bit are loaded into
bit 15 of the destination.
Same

Example:
WORD:

BYTE:

.~---~--

~
00

E~EN
MFM5213

A-36

ROL
ROLD
Rotate Left

ll061DD

0/1 :

0
MR-6214

Operation:

(dst) +- (dst) rotate left one place

Condition Codes:

N: set if the high-order bit of the result word is set (result < 0); cleared
otherwise
Z: set if all bits of the result word = O; cleared otherwise
V: loaded with the exclusive OR of the N-bit and C-bit (as set by the
completion of the rotate operation)
C: loaded with the high-order bit of the destination

Description:

Word:
Byte:

All bits of the destination are rotated left one place. Bit 15 is loaded
into the C-bit of the status word, and the previous contents of the
C-bit are loaded into bit 0 of the destination.
Same

Example:
WORD:

DST

&I
BYTE:

{~]
15

O~D

00
EV:EN

MR-5215

A-37

SWAB

000300

Swap Bytes
06

()()

MA-6216

Operation:

Byte I/Byte 0 +- Byte 0/Byte 1

Condition Codes:

N: set if the high-order bit of the low-order byte (bit 7) of the result is set;
cleared otherwise
Z: set if low-order byte of result = 0; cleared otherwise
V: cleared
C: cleared

Description:

High-order byte and low-order byte of the destination word are exchanged
(destination must be a word address).
SWAB Rl

Example:
Before
(Rl) = 077777

After
(Rl) = 177577

NZVC
1 1 1 1

0 0 0 0

NZVC

A.3.3.3 Multiple Precision - It is sometimes necessary to do arithmetic on operands considered as
multiple words or bytes. The SBC-11/21 PLUS makes special provisions for such operations with the
instructions ADC (add carry) and SBC (subtract carry) and their byte equivalents. For example, two 16bit words may be combined into a 32-bit double precision word and added or subtracted as shown in
Figure A-33.
32-BITWORD
31

.-15....___ _ _ _ _ _ _ _ _ _ _ _ _ _
o

OPERANDl_ _ _ _ _ _ _ _ _
A_1_ _ _ _ _ _ _ _ _,

_l_ _ _ _ _ _ _A_o_ _ _ _ _ _ _ _ _,

1__ _ _ _ _ _ _s_o_ _ _ _ _ _ _ _

OPERANDj_'_ _ _ _ _ _ _ _ _s_1_ _ _ _ _ _ _ _ _

_________.,....._________......,o

I l_________I
~15.__

RESULTl_ _ _ _ _ _ _ _

MA·5217

Figure A-33

Multiple Precision
A-38

Multiple Precision Example
The addition of -1 and -1 could be performed as follows:
-1 = 37777777777
(R 1) = 177777 (R2) = 177777 (R3) = 177777 (R4) = 177777
ADD Rl,R2
ADC R3
ADD R4,R3
1.
2.
3.
4.

After (R 1) and (R2) are added, 1 is loaded into the C-bit
ADC instruction adds C-bit to (R3); (R3) = 0
(R3) and (R4) are added
Result is 37777777776 or -2

ADC
ADCB

Add Carry

•055DD
06

0/1: 0

05
d

d
MR-5218

Operation:

(dst) +- (dst) + (C-bit)

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

set if result < O; cleared otherwise
set if result = O; cleared otherwise
set if (dst) was 077777 and (C) was l; cleared otherwise
set if (dst) was 177777 and (C) was l; cleared otherwise

Byte:
Example:

The contents of the C-bit are added into the destination. This
permits the carry from the addition of the low-order words to be
carried into the high-order result.
Same

Double precision addition is done with the following instruction sequence:
ADD AO,BO
ADC Bl
ADD Al,Bl

add low-order parts
add carry into high order
add high-order parts

A-39

SBC
SBCB

ll056DD

Subtract Carry
15

0/1:

o : o : o :

1 :

o :

1 :

: I

d :

02
:

01
:

00
:

MR-5219

Operation:

(dst) - (dst) - (C)

Condition Codes:

N:
Z:
V:
C:

Description:

Word:

set if result < O; cleared otherwise
set if result = O; cleared otherwise
set if (dst) was 100000; cleared otherwise
set if (dst) was 0 and C was l; cleared otherwise

Byte:

The contents of the C-bit are subtracted from the destination. This
permits the carry from the subtraction of two low-order words to be
subtracted from the high-order part of the result.
Same

Double precision subtraction is done with the following instruction sequence:

Example:

SUB AO,BO
SBC Bl
SUB Al,Bl

SXT
Sign Extend

0067DD
06

o : o : o : o :

1 :

: 1

00
:

MR-5220

Operation:

(dst) - 0 if N-bit is clear
(dst) - l if N-bit is set

Condition Codes:

N:
Z:
V:
C:

Description:

If the condition code bit N is set, a -1 is placed in the destination operand; if
the N-bit is clear, then a zero is placed in the destination operand. This
instruction is particularly useful in multiple precision arithmetic because it
permits the sign to be extended through multiple words.

unaffected
set if !'-J-bit is clear
cleared
unaffected

Example:

SXTA
Before

After

(A)= 012345

(A)= 177777

NZVC
1 0 0 0

A-40

A.3.3.4

PS Word Operators -

MFPS

Move Byte from Processor Status (PS)

106700
08

15
1

: 0

07
11

00
:

: d

d
MR-5221

Operation:

(dst) - PS
dst lower 8 bits

Condition Codes:

N: set if PS bit 7 = 1; cleared otherwise
Z: set if PS <0:7> = 0; cleared otherwise
V: cleared
C: not affected

Description:

The 8-bit contents of the PS are moved to the effective destination. If the
destination is mode 0, PS bit 7 is sign extended through the upper byte of the
register. The destination operand address is treated as a byte address.
MFPS RO

Example:
Before
RO [O]
PS [000014]

After
RO [000014]
PS [000000]

MTPS
1064SS

Move Byte to Processor Status

15
1

: : :

07
0

: 0

: s

: s
MR-5222

Operation:

PS - (src)

Condition Codes:

Set according to effective source operand bits 0'-3

Description:

The 8 bits of the effective operand replace the current contents of the PS.
The source operand address is treated as a byte address. The T-bit (PS bit 4)
cannot be set with this instruction. The source operand remains unchanged.
This instruction can be used to change the priority bits (PS bits 7-5) in the
PS.

A-41

A.3.4 Double-Operand Instructions
Double operand instructions save instructions and time because they eliminate the need for load and save
sequences such as those used in accumulator-oriented machines.
A.3.4.1

General MOV
MOVB

Move Source to Destination
15

O/<

•lSSDD

12
0

00
:

d
MR-5223

Operation:

(dst) +-- (src)

Condition Codes:

N:
Z:
Y:
C:

Description:

Word:

set if (src) < O; cleared otherwise
set if (src) = 0; cleared otherwise
cleared
not affected

Byte:

Example:

The source operand is moved to the destination location. The previous contents of the destination are lost. The contents of the source
address are not affected.
Same as MOY. The MOYB to a register (unique among byte
instructions) extends the most significant bit of the low-order byte
(sign extension). Otherwise, MOYB operates on bytes exactly as
MOY operates on words.

MOY XXX,Rl

loads register 1 with the contents
of memory location; XXX represents a programmer-defined mnemonic used to represent a
memory location

MOY #20,RO

loads the number 20 into register
O; '#' indicates that the value 20
is the operand

MOY @#20,-(R6)

pushes the operand contained in
location 20 onto the stack

MOY (R6)+,@#177566

pops the operand off a stack and
moves it into memory location
177566 (terminal print buffer)

MOY Rl,R3

performs
transfer

MOYB @# 177562,@# 177 566

moves a character from terminal
keyboard buffer to terminal
printer buffer

A-42

inter-register

CMP
CMPB
Compare Source to Destination

•2SSDD
06

MR-5224

Operation:

(src) - (dst)

Condition Codes:

N: set if result < O; cleared otherwise
Z: set if result = O; cleared otherwise
V: set if there was arithmetic overflow; that is, operands were of opposite
signs and the sign of the destination was the same as the sign of the
result; cleared otherwise
C: cleared if there was a carry from the most significant bit of the result;
set otherwise

Description:

Word:

Byte:

The source and destination operands are compared, and the condition codes are set. The condition codes may then be used for
arithmetic and logical conditional branches. Both operands are
unaffected. The 'only action is to set the condition codes. The
compare is customarily followed by a conditional branch instruction. Unlike the subtract instruction, the order of operation is (src)
- (dst), not (dst) - (src).
Same

ADD
06SSDD

Add Source to Destination
06

MR-5225

Operation:

(dst) +- (src) + (dst)

Condition Codes:

N: set if result < O; cleared otherwise
Z: set if result = O; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation; that is,
both operands were of the same sign and the result was of the opposite
sign; cleared otherwise
C: set if there was a carry from the most significant bit of the result;
cleared otherwise

A-43

Description:

Word:

Byte:

The source operand is added to the destination operand and the
result is stored at the destination address. The original contents of
the destination are lost. The contents of the source are not affected.
Two's complement addition is performed.
There is no equivalent byte mode.
add to register
add to memory
add register to register
add memory to memory

ADD 20,RO
ADD Rl,XXX
ADD Rl,R2
ADD @#17750,XXX

Example:

XXX is a programmer-defined mnemonic for a memory location.

SUB
16SSDD

Subtract Source from Destination
15

MR-6226

Operation:

(dst) - (dst) - (src)

Condition Codes:

N: set if result < O; cleared otherwise
Z: set if result = O; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation, that is if
operands were of opposite signs and the sign of the source was the same
as the sign of the result; cleared otherwise
C: cleared if there was a carry from the most significant bit of the result;
set otherwise

Description:

Word:

Byte:

The source operand is subtracted from the destination operand, and
the result is left at the destination address. The original contents of
the destination are lost. The contents of the source are not affected.
In double-precision arithmetic, the C-bit, when set, indicates a
borrow.
There is no equivalent byte mode.

Example:

SUB Rl,R2
Before
(R 1) = 011111
(R2) = 012345

After
(R 1) = 011111
(R2) = 001234

NZVC

1 1 1 I

0 0 0 0

A-44

A.3.4.2 Logical - Logical group instructions have the same format as the double operand arithmetic
group. They permit operations on data at the bit level.

BIT
BITB
Bit Test

•3SSDD
12

15
0/1 : 0

06
:

: s

00
:

MA-5227

Operation:

(src) /\ (dst)

Condition Codes:

N: set if high-order bit of result is set; cleared otherwise
Z: set if result = O; cleared otherwise
V: cleared
C: not affected

Description:

Word:

Logical "and" comparison of the source and destination operands is
performed, and condition codes are modified accordingly. Neither
the source nor destination is affected. The BIT instruction may be
used either to test whether any of the corresponding bits that are set
in the destination are also set in the source or whether all corresponding bits set in the destination are clear in the source.
Same

Byte:
Example:

test bits three and four of R3 to see if both are off

BIT #30,R3

R3 = O 000 000 000 011 000
After
NZVC
0 0 0 1

Before
NZVC
1 1 1 1

BIC
BICB
Bit Clear

•4SSDD
12

15
0/<

: 0

d
MA-5228

Operation:

(dst) +- (dst)

Condition Codes:

N:
Z:
V:
C:

,..,, (src)

set if high-order bit of result is set; cleared otherwise
set if result = O; cleared otherwise
cleared
not affected
A-45

Description:

Word:
Byte:

Each bit in the destination that corresponds to a set bit in the source
is cleared. The original contents of the destination are lost. The
contents of the source are not affected.
Same

Example:

BIC R3,R4
Before
(R3) = 001234
(R4) = 001111

After
(R3) = 001234
(R4) = 000101

NZVC

1 1 1 1

0 0 0 1

Before:

(R3) = 0 000 001 010 011 100
(R4) = 0 000 001 001 001 001

After:

(R4) = 0 000 000 001 000 001

BIS
BISB

•sssoo

Bit Set
15

: s

MR-5229

Operation:

(dst) +- (dst) V (src)

Condition Codes:

N: set if high-order bit of result is set, cleared otherwise
Z: set if result = O; cleared otherwise
V: cleared
C: not affected

Description:

Word:

Byte:

Inclusive OR operation is performed between the source and destination operands, and the result is left at the destination address (i.e.,
corresponding bits set in the source are set in the destination). The
contents of the destination are lost.
Same

Example:

BIS RO,Rl
Before
(RO) = 001234
(Rl) = 001111

After
(RO)= 001234
(Rl) = 001335

NZVC

0 0 0 0

Before:

(RO) = 0 000 001 010 011 100
(Rl) = 0 000 001 001 001 001

After:

(Rl) = 0 000 001 011 011 101
A-46

XOR

Exclusive OR

074RDD

15
: 1

: 1

: 0

: r

00
: d

: d

MR-5230

Operation:

(dst) -

Condition Codes:

N: set if the result < O; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: unaffected

Description:

The exclusive OR of the register and destination operand is stored in the
destination address. Contents of register are unaffected. Assembler format is:
XOR R,D.

(dst) V (Reg)

Example:

A.3.5

XOR RO,R2
Before
(RO)= 001234
(R2) = 001111

After
(RO) = 001234
(R2) = 000325

NZVC
1 1 1 1

NZVC
0 0 0 1

Before:

(RO)= O 000 001 010 011 100
(R2) = 0 000 001 001 001 001

After:

(R2) = 0 000 000 011 010 101

Program Control Instructions

A.3.5.1 Branches -Program control instructions cause a branch to a location defined by the sum of the
offset (multiplied by two) and the current contents of the program counter if:
l.

The branch instruction is unconditional.

The branch instruction is conditional, and the conditions are met after testing the condition
codes (NZVC).

The offset is the number of words from the current contents of the PC forward or backward. The current
contents of the PC point to the word following the branch instruction.

A-47

Although the offset expresses a byte address, the PC is expressed in words. Before it is added to the PC,
the offset is automatically multiplied by two and sign extended to express words. Bit 7 is the sign of the
offset. If it is set, the offset is negative and the branch is done in the backward direction. Similarly, if bit 7
is not set, the offset is positive and the branch is done in the forward direction.
The 8-bit offset allows branching in the backward direction by 200g words (400 bytes) from the current
PC, and in the forward direction by l 77g words (376 bytes) from the current PC.
The microprocessor assembler handles address arithmetic for the user and computes and assembles the
proper offset field for branch instructions in the following form.
Bxx Joe
where Bxx is the branch instruction and loc is the address to which the branch is to be made. The
assembler gives an error indication in the instruction if the permissible branch range is exceeded. Branch
instructions have no effect on condition codes. Conditional branch instructions, where the branch condition
is not met, are treated as NO OPs.

BR
Branch (Unconditional)

000400 Plus Offset
00

MR-5231

Operation:

PC +- PC + (2 x offset)

Condition Codes:

Unaffected

Description:

A way of transferring program control within a range of -12810 to +12710
words with a one-word instruction is provided.
New PC address = updated PC + (2 X offset)
Updated PC = address of branch instruction +2

Example:

With the branch instruction at location 500, the following offsets apply.
New PC 'Address

Offset Code

Offset (decimal)

474
476
500
502
504
506

375
376
377
000
001
002

-3
-2
-1
0
+1
+2

A-48

BNE
Branch If Not Equal (to Zero)

001000 Plus Offset

0 :

OFF~ET

: I
0

MR-5232

Operation:

PC +- PC + (2 x offset) if Z = 0

Condition Codes:

Unaffected

Description:

The state of the Z-bit is tested, and a branch is caused if the Z-bit is clear.
BNE is the complementary operation to BEQ. BNE is used to test inequality
following a CMP, to test that some bits set in the destination were also in the
source following a BIT operation, and generally, to test that the result of the
previous operation was not zero.

Example:

CMPA,B
BNEC

compare A and B
branch if they are not equal

will branch to C if A =/= B
and the sequence
ADD A,B
BNEC

add A to B
branch if the result is not equal to 0

will branch to C if A + B = 0

BEQ
Branch If Equal (to Zero)

001400 Plus Offset
08
0

1
MR-5233

Operation:

PC +- PC + (2 x offset) if Z = l

Condition Codes:

Unaffected

Description:

The state of the Z-bit is tested and a branch is caused if Z is set. BEQ is used
to test equality following a CMP operation, to test that no bits set in the
destination were also set in the source following a BIT operation, and generally, to test that the result of the previous operation was zero.

A-49

CMPA,B
BEQC

Example:

compare A and B
branch if they are equal
(A - B = O)

will branch to C if A = B
and the sequence
ADDA,B
BEQC

add A to B
branch if the result = 0

will branch to C if A + B = 0

BPL
100000 Plus Offset

Branch If Plus

0 :

OFF:SET
MA-5234

Operation:

PC +- PC + (2 x offset) if N = 0

Condition Codes:

Unaffected

Description:

The state of the N-bit is tested, and a branch is caused if N is clear (positive
result). BPL is the complementary operation of BMI.

BMI
Branch If Minus

100400 Plus Offset

15
:

0 :

OFF~ET
MR-5235

Operation:

PC +- PC + (2 x offset) if N = 1

Condition Codes:

Unaffected

Description:

The state of the N-:bit is tested, and a branch is caused if N is set. BMI is
used to test the sign (most significant bit) of the result of the previous
operation, branching if negative. BMI is the complementary function of BPL.

A-50

BVC
Branch If Overflow Is Clear

I 02000 Plus Offset
08

MA-5236

Operation:

PC ,_ PC + (2 x offset) if Y = O

Condition Codes:

Unaffected

Description:

The state of the Y-bit is tested, and a branch is caused if the Y-bit is clear.
BYC is the complementary operation to BYS.

BVS
102400 Plus Offset

Branch If Overflow Is Set
08

Operation:

PC ,_ PC + (2 X offset) if Y = 1

Condition Codes:

Unaffected

Description:

The state of the Y-bit (overflow) is tested, and a branch is caused if the Y-bit
is set. BYS is used to detect arithmetic overflow in the previous operation.

DCC
Branch If Carry Is Clear

103000 Plus Offset
08

MR-5238

Operation:

PC <---- PC + (2 x offset) if C = 0

Condition Codes:

Unaffected

Description:

The state of the C-bit is tested, and a branch is caused if C is clear. BCC is
the complementary operation to BCS.

A-51

RCS
103400 Plus Offset

Branch If Carry Is Set
08

15
1

:0 : 0 : 0 : 0 :

: :

,OFF~ET

MR-5239

Operation:

PC +- PC + (2 X offset) if C = 1

Condition Codes:

Unaffected

Description:

The state of the C-bit is tested, and a branch is caused if C is set. BCS is used
to test for a carry in the result of a previous operation.

A.3.5.2 Signed Conditional Branches - Particular combinations of the condition code bits are tested with
the signed conditional branches. These instructions are used to test the results of instructions in which the
operands were considered as signed (two's complement) values.
The sense of signed comparisons differs from unsigned comparisons. In signed 16-bit (two's complement)
arithmetic, the sequence of values is as follows.
largest

077777
077776

positive

zero

000001
000000
177777
177776

negative
smallest

100001
100000

In unsigned 16-bit arithmetic, the sequence is as follows.
highest

177777

lowest

000002
000001
000000

A-52

BGE
Branch If Greater Than or Equal (to Zero)

002000 Plus Offset
OB

MA-5240

PC + (2 X offset) if N V V = 0

Operation:

PC -

Condition Codes:

Unaffected

Description:

A branch is caused if N and V are either both clear or both set. BGE is the
complementary operation to BLT. Thus, BGE will always cause a branch
when it follows an operation that caused addition of two positive numbers.
BGE will also cause a branch on a zero result.

BLT
Branch If Less Than (Zero)

002400 Plus Offset
OB

1
MA-5241

PC + (2 X offset) if N V V = 1

Operation:

PC -

Condition Codes:

Unaffected

Description:

A branch is caused if the exclusive OR of the N- and V-bits is one. Thus,
BLT will always branch following an operation that added two negative
numbers, even if overflow occurred. In particular, BLT will always cause a
branch if it follows a CMP instruction operating on a negative source and a
positive destination (even if overflow occurred). Further, BLT will never
cause a branch when it follows a CMP instruction operating on a positive
source and negative destination. BLT will not cause a branch if the result of
the previous operation was zero (without overflow).

A-53

BGT

Sranch If Greater Than (Zero)

003000 Plus Offset
00

I~·:.:.:.:.:,:,'.:

MR-6242

Operation:

PC <--- PC + (2 X offset) if Z V (N V V) = 0

Condition Codes:

Unaffected

Description:

Operation of BGT is similar to BGE, however, BGT will not cause a branch
on a zero result.

BLE
Branch If Less Than or Equal (to Zero)

003400 Plus Offset

MA-5243

Operation:

PC ._ PC + (2 x offset) if Z V (N V V) = 1

Condition Codes:

Unaffected

Description:

Operation is similar to BLT, however, BLE also will cause a branch if the
result of the previous operation was zero.

A.3.S.3 Unsigned Conditional Branches -The unsigned conditional branches provide a means to test the
results of comparison operations in which the operands are considered unsigned values.

BHI
Branch If Higher

101000 Plus Offset
08

1 :

0 :

: I

OFF~ET
MA-5244

Operation:

PC <--- PC + (2 x offset) if C = 0 and Z = 0

Condition Codes:

Unaffected

Description:

A branch occurs if the previous operation did not cause a carry or a zero
result. This will happen in comparison (CMP) operations as long as the source
has a higher unsigned value than the destination.

A-54

BLOS
Branch If Lower or Same

101400 Plus Offset
08

I :· : , : , : , : , : , :

MA·5245

Operation:

PC +- PC + (2 X offset) if C V Z = 1

Condition Codes:

Unaffected

Description:

A branch occurs if the previous operation caused either a carry or a zero
result. BLOS is the complementary operation to BHI. The branch will occur
in comparison operations as long as the source is equal to, or has a lower
unsigned value than the destination.

BHIS
Branch If Higher or Same

103000 Plus Offset
08

: :

00
OFF:SET

MR-5246

Operation:

PC +- PC + (2 x offset) if C = 0

Condition Codes:

Unaffected

Description:

BHIS is the same instruction as BCC. This mnemonic is included for convenience only.

BLO
Branch If Lower

103400 Plus Offset
00

MR-5247

operation:

PC +- PC + (2 x offset) if C = 1

Condition Codes:

Unaffected

Description:

BLO is the same instruction as BCS. This mnemonic is included for convenience only.

A-55

A.3.5.4 Jump and Subroutine Instructions - The subroutine call in the microprocessor provides for
automatic nesting of subroutines, re-entrance, and multiple entry points. Subroutines may call other
subroutines (or themselves) to any level of nesting without making special provisions for storage of return
addresses at each level of subroutine call. The subroutine calling mechanism does not modify any fixed
location in memory, and thus, provides for re-entrance. This allows one copy of a subroutine to be shared
among several interrupting processes.

JMP

000100

Jump
06

o : o : o : o : o : o : o : o : o : ,

00
d

d
MR-5248

Operation:

PC+- (dst)

Condition Codes:

Unaffected

Description:

More flexible program branching than that available with the branch instructions is provided. Control may be transferred to any location in memory (no
range limitation) and can be accomplished with the full flexibility of the
addressing modes, with the exception of register mode 0. Execution of a jump
with mode 0 will cause an illegal instruction condition, and will cause the
CPU to trap to vector address 4. (Program control cannot be transferred to a
register.) Register deferred mode is legal and will cause program control to be
transferred to the address held in the specified register. Instructions are word
data and therefore, must be fetched from an even-numbered address.
Deferred index mode JMP instructions permit transfer of control to the
address contained in a selectable element of a table of dispatch vectors.

Example:
JMP FIRST

transfers to FIRST

JMP@LIST

transfers to location pointed
to at LIST
pointer to FIRST

First:
List:

FIRST
JMP@(SP)+

transfers to location pointed to by the top of the
stack and removes the pointer from the stack

A-56

JSR
Jump to Subroutine

004RDD
09

I :
r

06
r

05
d

00
:

MR-5249

Operation:

(tmp) -

(dst) (tmp is an internal processor register)

l (SP) -

reg (push reg contents onto processor stack)

reg -

PC (PC holds location following JSR; this address is now put in reg)

PC -

(dst) (PC now points to subroutine destination)

Condition Codes:

Unaffected

Description:

The old contents of the specified register (the linkage pointer) are automatically pushed onto the processor stack, and new linkage information is placed
in the register. Thus, subroutines nested within subroutines to any depth may
all be called with the same linkage register. There is no need either to plan the
maximum depth at which any particular subroutine will be called or to
include instructions in each routine to save and restore the linkage pointer.
Further, since all linkages are saved in a re-entrant manner on the processor
stack, execution of a subroutine may be interrupted, and the same subroutine
re-entered and executed by an interrupt service routine. Execution of the
initial subroutine can then be resumed when other requests are satisfied. This
process (called nesting) can proceed to any level.
A subroutine called with a JSR reg,(dst) instruction can access the arguments
following the call with either autoincrement addressing, (reg)+, (if arguments
are accessed sequentially) or by indexed addressing, X(reg), (if arguments are
accessed in random order). These addressing modes may also be deferred,
@(reg)+ and @X(reg), if the parameters are operand addresses rather than
the operands themselves.
JSR PC,(dst) is a special case of the microprocessor subroutine call and is
used for subroutine calls that transmit parameters through the general-purpose registers. The SP and the PC are the only registers that may be modified
by this call.
JSR PC,@(SP)+ is another special case of the JSR instruction. It exchanges
the top element of the processor stack and the contents of the program
counter. This instruction is used to allow two routines to swap program
control and resume operation when recalled where.they left off. Such routines
are called co-routines.
Return from a subroutine is done with the RTS instruction. RTS reg loads
the contents of reg into the PC and pops the top element of the processor
stack into the specified register.

A-57

Example:

R6
n

R7
SBCALL

CONT

SBCALL+4

n-2

SBR

SBCALL+2+2M
CONT
CONT

n-2

EXIT

R5
SBCALL
SBCALL+4

JSR R5, SBR
ARGl
ARG2

SBCALL+2+2M
CONT

ARGM
NEXT INSTRUCTION

SBR

MOV(R5)+,dstl
MOV(R5)+,dst2
MOV(R5)+,dst2

EXIT

MOV(R5)+,dstM
OTHER INSTRUCTIONS
RTSR5

This example is illustrated in the following figure.

A-58

JSR R5, SBR

BEFORE:

(PC)

(SP)

AFTER:

I
r

SBR

STACK

DATAO

DATAO
R6

n-2

PC+2

JSR PC, SBR
BEFORE:

AFTER:

(PC)

(SP)

[

STACK

DATAO

SBR

n-2

DATAO
PC+2
MA-5250

Figure A-34

JSR Example

A-59

RTS

Return from Subroutine

00020R
03

MA-5251

Operation:

PC - (reg)
(reg) <- (SP) T

Condition Codes:

Unaffected

Description:

Contents of register are loaded into PC, and the top element of the processor
stack is popped into the specified register. Return from a nonre-entrant
subroutine is typically made through the same register that was used in its
call. Thus, a subroutine called with a JSR PC,(dst) exits with an RTS PC. A
subroutine called with a JSR R5,(dst) may pick up parameters with addressing modes (R5)+, X(R5), or @X(R5) and finally exit with an RTS R5.

Example:

RTS R5
RTS R5
BEFORE:

(PC)

SBR

STACK

I
DATAO

(SP)

AFTER:

[

_,.

n+2

DATAD

MA-5252

A-60

SOB
Subtract One and Branch (If =I= 0)

077RNN
09

15
0 :

1 :

I : : I
r

OFF~ET
MR-5253

Operation:

(R) ~ (R) - 1; if this result =I= 0 then PC ~ PC - (2 x offset); if (R) = 0
then PC~ PC

Condition Codes:

Unaffected

Description:

The register is decremented. If it is not equal to zero, twice the offset is
subtracted from the PC (now pointing to the following word). The offset is
interpreted as a 6-bit positive number. SOB provides a fast, efficient method
of loop control. The assembler syntax is:
SOB R,A
where A is the address to which transfer is to be made if the decremented R
is not equal to zero. The SOB instruction cannot be used to transfer control in
the forward direction.

A.3.5.5 Traps -Trap instructions provide for calls to emulators, 1/0 monitors, debugging packages, and
user-defined interpreters. A trap is effectively an interrupt generated by software. When a trap occurs the
contents of the current program counter (PC) and processor status (PS) are pushed onto the processor
stack and replaced by the contents of a two-word trap vector containing a new PC and PS. The return
sequence from a trap involves executing an RTI or RTT instruction that restores the old PC and PS by
popping them from the stack. Trap instruction vectors are located at permanently assigned fixed
addresses.

EMT
Emulator Trap

104000-1043 77
08

: : :
0

0
MR-6254

A-61

Operation:

l (SP)+-- PS
l (SP)+-- PC
PC+-- (30)
PS+-- (32)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

All operation codes from 104000 to 104377 are EMT instructions and may
be used to transmit information to the emulating routine (e.g., function to be
performed). The trap vector for EMT is at address 30. The new PC is taken
from the word at address 30, and the new processor status (PS) is taken from
the word at address 32.
CAUTION
EMT is used frequently by Digital system software
and is not recommended for general use.

Example:

PC 1

STACK

BEFORE:
SP

AFTER:

I
[

DATA 1

(32)

(30)

n-4

I
L

DATA 1

PS 1
PC 1

MR~5255

A-62

TRAP
Trap

104400-104777
15

: :

MA-5256

Operation:

l (SP) 1 (SP) -

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

Operation codes from 104400 to 104777 are TRAP instructions. TRAP and
EMT instructions are identical in operation, however, the trap vector for
TRAP is at address 34.

PS
PC
PC - (34)
PS - (36)

NOTE
Because Digital software makes frequent use of
EMT, the TRAP instruction is recommended for
general use.

BPT
000003

Breakpoint Trap
00

0 :

MR-5257

Operation:

1 (SP) - PS
1 (SP) - PC
PC - (14)
PS - (16)

Condition Codes:

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Description:

A trap sequence with a trap vector address of 14 is performed. BPT is used to
call debugging aids. The user is cautioned against employing code 000003 in
programs run under these debugging aids.
(No information is transmitted in the low byte.)

A-63

IOT
Input/Output Trap

000004
00

15
0

: 0

MR-5258

l (SP) - PS
l (SP) - PC

Operation:

PC - (20)
PS- (22)
Condition Codes:

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Description:

A trap sequence with a trap vector address of 20 is performed.
(No information is transmitted in the low byte.)

RTI
Return from Interrupt

000002
00

o: o: o: o: o: o: o: o: o: o: o: o: o: 1: 1: ol
MR-5260

Operation:

PC - (SP) T
PS - (SP) T
1vau.\.IU 1 l v111 p1 v...,.....,.,v1

Z:
V:
C:

loaded from processor stack
loaded from processor stack
loaded from processor stack

"1111 •

Description:

1"'nr1.or1 .f.. ,.,,._ ......",.,,"°',('lil"I,.,,.. il"l,..,,.,,L131.a\,tll\..

1'.T·
.&.

Used to exit from an interrupt or TRAP service routine. The PC and PS are
restored (popped) from the processor stack, If a trace trap, is pending, the first
instruction after RTI will not be executed prior to the next T trap.

A-64

RIT
Return from Trap

000006
00

MR-5259

Operation:

PC - (SP) T
PS - (SP) T

Condition Codes:

N:
Z:
V:
C:

Description:

Operation is the same as RTI, however, RTT inhibits a trace trap while RTI
permits a trace trap. If new PS has T-bit set, trap will occur after execution
of first instruction after RTT.

loaded from processor stack
loaded from processor stack
loaded from processor stack
loaded from processor stack

A.3.5.6 Reserved Instruction Traps - Reserved instruction traps are caused by attempts to execute
instruction codes reserved for future processor expansion (reserved instructions) or instructions with illegal
addressing modes (illegal instructions). Order codes not corresponding to any of the instructions described
are reserved instructions. JMP and JSR with register mode destinations are illegal instructions and trap to
vector address 4. Reserved instructions trap to vector address 10.
A.3.5.7 HALT Interrupt -The HALT interrupt is caused by the -HALT line. The -HALT interrupt
saves the PC and PS and goes to the restart address with PS = 340.
A.3.5.8 Trace Trap -The trace trap is enabled by bit 4 of the PS and causes processor traps at the end of
instruction execution. The instruction that is executed after the instruction that set the T-bit will proceed
to completion and then trap through the trap vector at address 14. The trace trap is a system debugging
aid and is transparent to the general programmer.
A.3.5.9 Power Failure Interrupt -The power failure interrupt occurs when -PF line is asserted. Vectors
for power failure are locations 24 and 26. Trap will occur if an RTI instruction is executed in a power fail
service routine.
A.3.5.10 Interrupts - See Table 3-1.
NOTE
Bit 4 of the processor status can only be set indirectly by executing an RTI or RIT instruction with the
desired PS on the stack.

A-65

A.3.5.11 Special Cases (T-bit) - The following are special cases of the T-bit.
NOTE
The traced instruction follows the instruction that
sets the T-bit.
I.

An instruction that cleared the T-bit - Upon fetching the traced instruction, an internal flag,
the trace flag, was set. The trap will still occur at the end of execution of this instruction. The
status word on the stack, however, will have a clear T-bit.

An instruction that set the T-bit - Because the T-bit was already set, setting it again has no
effect. The trap will occur.

An instruction that caused an instruction trap - The instruction trap is performed, and the
entire routine for the service trap is executed. If the service routine exits with an RTI or in any
other way restores the stacked status word, the T-bit is set again, the instruction following the
traced instruction is executed, and, unless it is one of the special cases noted previously, a trace
trap occurs.

Interrupt trap priorities - When multiple trap and interrupt conditions occur simultaneously,
the following order of priorities is observed (from high to low).
l.
2.
3.
4.
5.
6.

A.3.6

Halt line
Power fail trap
Trace trap
Internal interrupt request
External interrupt request
Instruction traps

Miscellaneous Instructions

HALT
Halt

000000
00

15
0

0 :

MR-5261

Operation:

l (SP)_. PS
l (SP)_. PC
PC - restart address
PS- 340

Condition Codes:

Unaffected

Description:

The processor goes to the restart address after placing the current PC and PS
on the stack. PS is initialized to 340.

A-66

WAIT
Wait for Interrupt

000001
00

MR-5262

Condition Codes:

Unaffected

Description:

In WAIT, as in all instructions, the PC points to the next instruction following the WAIT instruction. Thus, when an interrupt causes the PC and PS to
be pushed onto the processor stack, the address of the next instruction
following the WAIT is saved. The exit from the interrupt routine (i.e.,
execution of an RTI instruction) will cause resumption of the interrupted
process at the instruction following the WAIT.

RESET
000005

Reset External Bus
00

MR-5263

Condition Codes:

Unaffected

Description:

The -BCLR line is asserted and the mode register is loaded. -BCLR is
negated, and an ASPI transaction takes place. PC, PS, and RO-R5 are not
affected.

MFPT

000007

Move from Processor Type Word

I ~, : •

MR-7198

Operation:

RO .--- 4

Condition Codes:

Unaffected

Description:

The number four is placed in RO telling the system software that the processor type is Micro /T-11.

A-67

A.3. 7 Condition Code Operators

CLN SEN
CLZ SEZ
CLV SEV
CLC SEC

cccscc

0002XX

Condition Code Operators
05

MR-5266

Description:

Condition code bits are set and cleared. Selectable combinations of these bits
may be cleared or set together. Condition code bits corresponding to bits in
the condition code operator (bits 0-3) are modified according to the sense of
bit 4, the set/clear bit of the operator (i.e., set the bit specified by bit 0, 1, 2,
or 3, if bit 4 is a one). Corresponding bits are cleared if bit 4 = 0.
Mnemonic

Operation

OP Code

CLC
CLY
CLZ
CLN
SEC
SEY
SEZ
SEN

Clear C
Clear Y
Clear Z
Clear N
Set C
Set Y
Set Z
Set N
Set all CCs
Clear all CCs
Clear Y and C*
No operation

000241
000242
000244
000250
000261
000262
000264
000270
000277
000257
000243
000240

sec

CCC
NOP

*Combinations of the above set or clear operations may be ORed together to form combined instructions. Clear V and C represents CLC (241) ORed with CLY (code 242).

A-68

APPENDIX B
PROGRAMMING DIFFERENCES
Table B-1 presents a concise comparison of the KXTI 1-CA SBC, LSI-11/2, and LSI-11/23 modules.

Table B-1

KXTll-CA, LSI-11/2, and LSI-11/23 Comparisons

Activity

KXTll-CA

OPR %R,(R)+ or OPR %R,-(R)
using the same register as both
source and destination: contents
of 'R' are incremented (decremented)
by two before being used as the
source operand.

OPR %R,@(R)+ or OPR %R,@-(R)
using the same register as both
source and destination: contents
of 'R' are incremented (decremented)
by two before being used as the
source operand.

LSI-11/2

LSI-11/23

In the previous two cases, initial
contents of 'R' are used as the
source operand.

OPR PC,X(R); OPR PC,@X(R);
OPR PC,@A; or OPR PC,A: location A
will contain the PC of OPR + 4.

In the previous case, location A
will contain the PC of OPR + 2.
JMP (R)+ or JSR reg,(R)+: initial
contents of 'R' are used as the
new PC.

JMP %R or JSR reg,%R traps to 4
(illegal instruction).

Only one LSI-11 bus interrupt
level (BR4) exists.

B-1

Table B-1

KXTtt-CA, LSI-11/2, and LSI-11/23 Comparisons (Cont)

Activity

KXT11-CA

Four local interrupt levels exist.

LSI-11/2

LSI-11/23

Four LSl-11 interrupt levels exist.

Stack overflow not implemented.

A stack overflow trap exists.

x
x

The first instruction in an
interrupt routine will not be
executed if another interrupt
occurs at a higher priority level
than assumed by the first interrupt.

Eight general-purpose registers.

x
x

Only implicit references (RTI, RTT,
traps, and interrupts) can load
T-bit. Console cannot load T-bit.

If an interrupt occurs during an
instruction that has the T-bit set,
the T-bit trap is acknowledged
before the interrupt.

If RTI sets the T-bit, T-bit trap
is acknowledged immediately following
RTL

T-bit trap will sequence out of
WAIT instruction.

If RTT sets the T-bit, the T-bit
trap occurs after the instruction
following RTT.

RESET instruction consists of 17
µs of INIT followed by a minimum
3.2 µs pause. Power fail is not
recognized until the instruction
is complete.

Odd address references using the
· SP do not trap.

PSW address 177776 not implemented.
Must use MTPS and MFPS instructions.

B-2

x
x

Table B-1

KXT11-CA, LSl-11/2, and LSl-11/23 Comparisons (Cont)

Activity

KXT11-CA

Nonexistent address references
using the SP trap to the restart
address.

LSl-11/2

MOVB instruction does a read
(DATl) and a write (DATO) bus
sequence for last memory cycle.

MOY instruction does a write
(DATO) bus sequence for the last
memory cycle.

MOY instruction does a read
(DA Tl) and a write (DATO) bus
sequence for last memory cycle.

CLR(B) and SXT do a read (DATI)
and a write (DATO) sequence for
the last bus cycle.

LSl-11/23

CLR(B) and SXT do a read (DATI)
and a write (DATO) bus sequence
for the last bus cycle.

CLR(B) and SXT do a write (DATO)
bus sequence for the last bus cycle.
MARK instruction.

x
x

SOB, RTT, SXT, XOR instructions.
SW AB clears V.
ASH, ASHC, DIV, MUL instructions.

x
x
x
x

Register addresses ( 177700177717) are handled as regular
memory addresses. No internal
registers are addressable from
either the bus or the console.
Register addresses ( 177000177717) timeout when used as
program addresses by the CPU.

If PC contains a nonexistent
memory address and a bus error
occurs, PC will have been incremented.

8-3

, Table B-l .KXTll-CA, LSl·ll/2, and LSI-11/23 Comparisons (Cont)
Activity

KXT11-CA

LSI-11/2

LSl-11/23

If register contains a nonexistent
memory address in mode 2 and a bus
error occurs, register will be
incremented.

If register contains an odd value
in mode 2 and a bus error occurs,
register will be incremented.

x
x

HALT in user mode traps to 10.
HALT instruction pushes PC and
PSW on the stack and loads the
PSW with 340 and the PC with
the restart address.

Only power-up mode 2 implemented.

x
x

Resident ODT microcode.
Instruction execution runs to
completion regardless of bus error.

BEVNT line interrupt on level 6.

Bus error traps to restart
address. Instruction runs to
completion before trap.

Bus error during IAK vectors
through 0 and traps to restart
address. The first instruction
of service routine is guaranteed
to execute.

Only 16-bit addressing supported.

The no-BSACK 18 µs timeout
implemented. If timeout occurs
BDMGO aborted.

Bus halt line is a jumper
configured nonmaskable interrupt.
Acknowledgement causes PC and PSW
to be stacked and the proc~ssor
vectors through level 7 internal
vector 140.

B-4

Table B-1

KXT11-CA, LSI-11/2, and LSI-11/23 Comparisons (Cont)

Activity

KXT11-CA

Vector address accepted only on
BDAL<7:2>. This limits vector
address space to 374.

Certain vector addresses are
reserved for local devices other
than BEVNT.

LSl-11/2

LSI-11/23

T-11 Internal Priorities
Priority of DMA, system traps, external interrupts, internal interrupts, HALT trap, and WAIT are as
follows.
DMA
(highest priority)
HALT trap (timeout request)
Power-fail trap
Traps (illegal instruction, T-bit, EMT)
Internal interrupt request
External interrupt request
WAIT instruction
(lowest priority)

KXT11-C Priorities
Priority of system traps, external interrupts, internal interrupts, HALT trap, and WAIT are as follows.

(highest priority)

HALT trap (timeout request)
Power-Fail trap
Traps {illegal instruction, T-bit, EMT)
Internal vector
External vector
WAIT instruction
TEST

(lowest priority)

B-5

APPENDIX C
PERFORMANCE PARAMETERS

The fetch and execute times listed in Table C-1 assume that the KXTl 1-CA is transacting with local
devices that do not require cycle slips when accessed.
The measure of Q-Bus interrupt latency is the time from the assertion of BIRQ until BIAKI is accepted by
the interrupting device electrically closest to the processor on the Q-Bus.
The measure of local interrupt latency is the time from assertion of the request until the time the
microprocessor is ready to fetch the first instruction in the interrupt service routine. This time is primarily
comprised of the time to perform two pushes and a PC and PSW restore.
Interrupt Latency:

LOCAL
Q-BUS

23.2 µs
9.3 µs

NOTE
Assume that the stack and vector memory reside on
the KXTll-CA and that the Q-Bus device can assert
BRPLY and vector within 600 ns after receiving
IAKI. The service latency (time from BIRQ until the
time the microprocessor is ready to fetch the first
instruction in the interrupt service routine) depends
on the response time of the interrupting device (i.e.,
RDIN to TRPLY and negation of TRPLY).
OMA latency is the period of time between a device asserting its BOMR and receiving BOMGI when it
resides on the Q-Bus as the electrically closest OMA device to the processor.
OMA latency:

1.3 µs (minimum)

WAIT instruction latencies:
Internal vector:
External vector:
OMA:

11.8 µs
12.4 µs
5.06 µs

C-1

11.0 µs (maximum)

Table C-1

Instruction Timing

Single Operand
Instructions

Destination
Mode

Fetch and
Execute
Time (µs)

Number of
Bus
Transactions

Number of
Microcycles

CLR(B), COM(B),
INC(B), DEC(B),
NEG(B), ROR(B),
ROL(B), ASR(B),
ASL(B), SW AP,
ADC(B), SBC(B),
SXT, MFPS,
XOR

0
1
2
3
4
5
6
7

2.44
4.27
4.27
5.49
4.88
6.10
6.10
7.32

1
3
3
4
3
4
4
5

4
7
7
9
8
10
10
12

0
1
2
3
4
5
6
7

2.44
3.66
3.66
5.49
4.27
5.49
5.49
6.71

1
2
2
3
2
3
3
4

4
6
6
8
7
9
9
11

0
1
2
3
4
5
6
7

4.88
6.10
6.10
7.32
6.71
7.93
7.93
9.16

1
2
2
3
2
3
3
4

8
10
10
12
11
13
13
15

Source Mode

Source Mode
Time (µs)
Includes
Fetch

Number of
Bus
Transactions

Number of
Microcycles

0
I
2
3
4
5
6
7

1.83
3.05
3.05
4.27
3.66
4.88
4.88
6.10

I
2
2
3
2
3
3
4

3
5
5
7
6
8
8
10

TST(B)

MTPS

Double Operand
Instructions
MOV(B), CMP(B),
ADO, SUB,
BIT(B), BIC(B),
BIS(B)

C-2

Table C-1

Instruction Timing (Cont)

Double Operand
Instructions

Destination
Mode

Destination
Mode
Time (µs)

Number of
Bus
Transactions

Number of
Microcycles

MOV(B), CMP(B),
ADD, SUB,
BIT(B), BIC(B),
BIS(B)

0
1
2
3
4
5
6
7

0.61
2.44
2.44
3.66
3.05
4.27
4.27
5.49

0
2
2
3
2
3
3
4

1
4
4
6
5
7
7
9

0
1
2
3
4
5
6
7

0.61
1.83
1.83
3.05
2.44
3.66
3.66
4.88

Q
1
1
2
I
2
2
3

1
3
3
5
4
6
6
8

Destination
Mode

Fetch and
Execute
Time (µs)

Number of
Bus
Transactions

Number of
Microcycles

1
2
3
4
5
6
7

3.05
3.66
3.66
3.66
4.27
4.27
5.49

2
2
3
2
3
3
4

5
6
6
6
7
7
9

1
2
3
4
5
6
7

5.49
6.10
6.10
6.10
6.71
6.71
7.90

4
4
5
4
5
5
6

9
10
10
10
11
11
13

RTS

4.27

SOB

3.66

CMP(B), BIT(B)

Jump and
Subroutine
Instructions

JMP

JSR

C-3

Table C-1

Instruction Timing (Cont)

Destination
Mode

Fetch and
Execute
Time (µs)

BR, BNE, BEQ,.
BPL, BMI, BYC,
BYS, BCC, BCS,
BGE, BLT, BGT,
BLE, BHI, BLOS,
BHIS, BLO

2.44

EMT, TRAP,
BPT, IOT

9.77

RTI

4.88

RTT

6.71

Miscellaneous
and Condition
Code
Instructions

.Destination
Mode

Fetch and
Execute
Time (µs)

Number of
Bus
Transactions

Number of
Microcycles

HALT

8.54

WAIT

2.44

4
then loop

RESET

22.28

NOP

3.66

CLC, CLY, CLZ,
CLN, CCC, SEC,
SEY, SEZ, SEN,

3.66

MFPT

3.05

Branch, Trap,
and Interrupt
Instructions

Number of
Bus
Transactions

Number of
Microcycles
4

sec

C-4

APPENDIX D
KXTll-CA SBC SCHEMATIC DRAWINGS

The following is the complete KXTl 1-CA SBC schematic drawing set.

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NON-SOURCED SIGNALS
PAGE 01

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CAB'J RHALT H
CA9'3 SHATCH L
CAB'3 SHATCH H
CA8'J ·rADDR L
CAB'J T8S7 H
CAH TDATA- H
CAB'J TMTBT L
CAB'J XA081 H
CA8'J l(A082 H
CA83 ICADl'J H
CA83 ICAOIJ't H
CA83 KDAL16 H
CA8'J ICDAl..17 H

PAGE 0 4- g::: ~~K~'58 H
CA8't
CAl't
CAl't
CAl't
CA8't
CA8't
CA8't
CA8't
CA8't
CA8't
CA8't
CJt8't
CAl't
CAB't
CAll't

CL.Kl 't2 H
CLICH'S H
CLIC'.l'S H
CLK'S71 H
CLK71 H
CDlJT H
DIDO L
DMARQ L
EDAl..16 H
EDAl..17 H
EDALl8 H
EDALl9 H
EDAl..21 H
EDAL21 H
EMllRO L

PAGE 06
=~::: t
CA86 AK118 l
CA86
CAH
CAK
CA86

CA8't RESET H

BRl'fB H
CLK71 L
CLRRS H
CSUTDTC L
CAH DCllRP H

CA8'1" RESET L
CAB't SELlll H

CA86 0C1RQ H
CAB& OE6o't6 L

CA9't Sl!'LI ff

CA86 DlSDE H
CAfi on6 L
CA86 OPRDT L
CA86 DPRHI T H
CA86 EHAPT L
CA96 EHBPT L
CA86 FZB L
CAO& UIS L
CA86 lf>S L
CA86 IEULB L
CA86 UVUHB L
CA8g IR"ULB L
CA8g tREAD L
CA86 tUIUTE L
CA86 llRESETDC L
CA96 1111128 H
CA86 RQl2't H
CA86 RQl'J8 H
CA86 Rill3't H
CA86 RQDC\8 H
CA86 SQBAD L
CA86 TJ>RCV L
CA86 TRPLT L
CA86 UTDPR L
CA86 i!AI( L
CA86 i!AS L
CA8' i!DS L
CA86 i!MRITE L

CAl't OIIOP H

CA8't SQB H
CAB't TDAL.811 M
CA9.. TDAL99 H
CA8't TDALl8 H
CA8't TDALll H
CA9't TDALli! H
CA9't TDALl'3 H
CA9't TDALl't H
CA9't TIHIL1'5 H
CAB't TPUP L
CA9't TPUP H
CA8't i!BU L
CAll't_i!CtEI H

PAGE 0 5 ~::; =~==~ ~
CABIJ ADSfl'J H
CA8'5 AD&fl't H
CA81J AD88'5 H
CA8'5 AD886 H
CA8'S AD&fl7 H
CA8'5 Af>.888 H
CAll'5 ADB89 H
CA8'S ADBll H
CA8'S ADBl I H
CA1'5 AD812 H
CAB'S AD81'J H
CAB'S AD81't H
CAl!l'5 AD81'5 H
CA8'S ADIA6"n H
CA8'5 CSBCtO L
CAl'S CSCIO L
CA.., CSDL L
CA8'S CSOPR L
CA8'S CSDTC L
CA8'S CSI IDAL L
CAB'S CSKTA L
CA8'S CSKTB L
CAl!l'J CSLIPI L
CA8'S CSLIP't L
CA8'5 CSPPI L
CA8'5 CSQIICJC L
CA8" CSRAMI L
CA8'5 CSRAH2 L
CA8'S CSTMR L
CA8'5 CSUPO L
CA8'5 6RQTH L
CA8'S RQTM L
CAl'S SI IOAL L
C.AlllJ Ull L
CA9'J M12.L

CAl2 JKll8't L
CAt2 f«IRTC L
CAl2 RTC'59 H
CAl2 ll'TCH H
Ct:IH! RTC888 H
CAl2 TKCA H
CAl2 TllCB H

CA416 QKl'J't L

PAGE 09
PAGE 10
PAGE 11

PAGE

CA89 CLK2'S8 H
CAUi RQPB L
CAii
CAii
CAii
CAii
CAii
CAii
CAii

DREBA L
OREQB L
RSA L
SEND H
TTlll3A H
TTlll38 H
UPDRQ L

CA12 BRCLIC H
CA12 CLKBl6 H
CA12 CLKl81 H
CA12 DLRRQ H
CA12 DLSO H
CA12 OLKRQ H
CAii! UUT L
CAl2 EMIT H
CAl2 P20UT H

PAGE

1 3 ~:~~ :~~~
CAl1 BkKT't H
CAil BREAK H
CAI 1 DlAGPn ff
CAI"! HAP9 H
CAI"! HAPI H
CAl'3 MAP2 H
CA1 3 RU68EH L
CA1'3 RTCEH H
CAl'l SYHnA H
CA13 SYHrtB H
CAl'J TEll!IHSER L
CA\'J TTl88,.2A L

PAGE

llt

g::: g~ALL

CAl't lC L
CAl't TllU2 H
CAl't TTIB'tA H
CAl't TT189A L
CAl't TTll'tA H
CAl't TT\ 15'1 H

PAGE 1 '5 g::; g~~~ ~
CAl'5
CAl'5
CAl'S
CAl'5
CAl'5
CA\'5
CAl'5
CAl'S
C.Al5

IHSER H
Rl36fl H
TnM& L
TTIB'tll H
TTll'tB H
TTlllJB H
KDL't22 H
ICOLOAT L
XDLOAT H

PAGE 1 b g::: ~==T[ L
CA16 PALL
CAl6 PH L
CAl6 Piil L
CAl6 PB2 L
CAl6 PB'J L
CAl6 PB't "CAl6 PB'S L
CAl6 PK L
CAl6 P87 L
cA-10 Pee 1..
CAl6 PCI L
CAl6 PC2 L
CAl6 PC3 L
CAl6 PCTT L

+12.avF
+lVA
+'JVD
+'.S.8VBB

+'J".BV8U
Al9 L
All L
Al2 L
AUL
A(lt L

Al'J L
Al& L
Al7 L
81 l't H
811'tH L
111'5 H
811'5H L
8857 L
8Cn2 L
BCH2 L
BCR2 L
8C52 L
BOAL89 L
8DAL81 L
BDAL.112 L
BDAL8'J L
BDAL9't L
BDAL8" L
BDAl..96 L
8DAL87 L
BDAL.88 L
BDAL89 L
BDAL18 L
BOAL!! L
8DAL12 L
BOALl'J L
BDALl't L
BDALllJ L
BDAl..16 L
80ALl7 L
8DALl8 L
8DA-Ll9 L
8DAL21J L
BtlAL21 L
8DCOK H
BDlH L
BDM&I L
8Dn80 L
BDHll L
BDOUT L
SHALT L
BIAK[ L
BIAl<O L
BIHlT L
BIRQ't L
BPOK H
Bfll"LT L
BSACK L
8STHC L
BUTBT L

DLRC L
EOf'L
ID9 H
IOI H
UJ2 H
101 H
lt~Lll

UDALBI H
lfDAL82 H
lllmLl'J H
llDALB't H
llOAL.8'5 H
IIDAL.86 H

ll°"L.87 H
ltDAL88 H
11DALB9 H
llDAll8 H
IIDALll H
IIDALH!' H
IIDAt..l'J H
IIDALl't H
llDALl'S H
PDRAH L
RDLOAT L
RDLOAT H
lilEADT H
561 L
SG2 L
TDAL89 H
TDAL81 H
TDAL82 H
TDALll'J If
TDAL8't H
1'0AL8'5 H
TDAL86 H
TDAL87 ti
TTl't2A L.
XDAL88 H
KDAL81 H
ICOAl..82 H
X0AL8'J H
ICDALl't H
ICDAL8'S H
KOAL86 H
KDAl..87 H
K0ALll8 H
KOAL89 H
JCl)ALl8 H
KDALll H
KDAL\2 H
KDALl3 H
ICOALl't H
KOALl'5 H
JCDALl8 H
ICDllLl9 H
ICDAl..28 H
ICOAL21 H
i!CIORO L

IF CONDUION/THEN OPEJUITION

""'

HLLLLH

llSTHCI

RODA TA

HLLLHH

HLLHHH

NOP
LHLHHH

II BYE
LLLHHH

'-ROT , -RPL T , -WtlliP 1 -SHA ,-!NI, -ENA

HOP2'
LHHLHH

..n

llCTC

UTDATA

UTRPLTI

HHHLLH

HHLLLH

LHLLHL

LHHLHL

9
'°

. ,.

081110
HLliLLL

RMU
HLHHHH

HLHHHL

GBUT
LHHLLL

CHECK

uon

LHHHU.

HHHHLL

STlllOBEI

STROBE

RESPOND

LLHHLL

LLHHHL

LHHHML

....

HHHHHt..

DUAL PORT RAM STATE MACHINE

APPENDIX E
ADDRESS ENVIRONMENT

Table E-1 lists all KXTl 1-CA locally addressable registers. The register addresses listed under the twoport register file description are addressable by the Q-Bus. The Q-Bus address is the local address plus the
CPU ID offset.

E-1

Table E-1

KXTl 1-CA Address Assignments

Local Address

Level

Vectors

Description

177566-177560

60,64

SLU 1 console DL registers

177532

5i, Q-Bus

130 level 4

Q-Bus interrupt register (QIR)

177530
177526

177524-177520

KXTCSR D
Mode control word for KXTCSR A, B
and C. Do not alter
104 (P CNTR)

Parallel 1/0 Buffer control register

177140
177136-177000
173736-175700

KXTCSR A, KXTCSR B, KXTCSR C

4e
4i

Read-in
programmable
70

Parallel 1/0 and timers registers
SLU2 synchronous/asynchronous serial

1/0 channel A, channel B, and
counter/timer registers
175036-175032
175030

l 34w

Two-Port register file:

175026-175022
175020

124w

User control secondary

175016-175012
175010

120w

User control primary

175006-175002

(nonmaskable)

l 73004w

System control

174536-174400

Read-in
programmable

OMA controller registers

i73000
173004

T-ii Power-Up start address
T-11 Restart address

173777-164000

Two 28-pin system PROM socket sites
for OCT/boot/self-test/diagnostics

163777-160000

1 K word overlay PROM for diagnostics

15777-0000000

Two 28-pin user sockets for RAM or
PROM and 16 KW static system RAM.

i = T-11 internal
e = T-11 external
w = Q-Bus write induced
On an interrupt level, internal (i) interrupts have priority over external (e) interrupts.

E-2

APPENDIX F
LOOPBACK CONNECTORS

Three different types of loopback connectors are needed if certain built-in selftests are selected to be
performed. Users can build their own loopback connectors that are compatible with the built-in selftest.
Two are 10-pin loopback connectors for testing via 1/0 port J2 (SLU2 channel B) and via 1/0 port J3
(SLU 1). See Figure F-1 for loopback connector details. A 40-pin loopback connector is for testing via 1/0
port J 1 (SLU2 channel A). This loopback set up 10 has switches enabling the testing of either RS423 or
RS422 connector operation. See Figure F-2 for details. One 40-pin loopback connector is used for testing
via 1/0 port J4 (parallel port). See Figure F-3 for details.

LOOPBACK
SLU
TEST CONNECTOR
CONNECTOR JUMPER WIRES
BAUD RATE
CLOCK OUTPUT
(16 X BAUD)
TRANSMIT DATA

INDEXING KEY

RECEIVE DATA

-12 voe FUSED

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE

4
2

PC"
BOARD
"
MR-12172

Figure F-1

10-Pin Loopback Connector (J2 and J3)

F-1

40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4

39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3

A
FRONT EDGE VIEW

TOP VIEW

40
38
36
34
32
30
28
26

~
v~ u0u 39
T~ ~S
R~ ~p

ft_ K°K
6"

HH
0
EE

16
14

29
27

rfo c°c 25
B~ AA
0

Nt M°M 33

f y

x
0

v
0

21
19

~
~

f 1311
N t;
10
12

R
0

J
F

D
B

f 3

t
:

MR-12170

Figure F-2

40-Pin Loopback Connector (Jl)

F-2

40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6

39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9

A
FRONT EDGE VIEW

TOP VIEW

Sl-3

S1-4

NOTE:
Sl-8 IS NOT USED

2
MR-12171

Figure F-3

40-Pin Loopback Connector (J4)

F-3

APPENDIX G

GLOSSARY

AD01-A01S - A 15-bit on-board address bus used to address memory and peripheral devices. Generated
by two 8-bit latches that are loaded from the TDAL bus. See also BBS7.
AIO-Al7 - Input lines used by the microprocessor for interrupts and OMA requests.
ASPI - Microprocessor transaction that allows the microprocessor to recognize and accept pending
interrupts or DMA requests.
Autobaud - Self-adjusting baud rates for SLUl only. Implemented by firmware in the optional MacroODT ROM.
BBS7 - Q-Bus signal indicating that the device addressed is in the 1/0 page.
BOAL 0-15 - Multiplexed data and address lines of the Q-Bus connected through the backplane.
BOCOK - Q-Bus signal that goes high 3 ms after de power is applied and stays high until 4 ms after de
power is removed.
BOIN - Q-Bus data input strobe.
BOMGI - Q-Bus DMA grant signal derived from the BDMGO bus pin. It is daisy chained through each
SBC entering on the BDMGI pin and exiting on the BDMGO pin. It represents the bus grant for the DMA
control line.
BOMGO - See BDMGI.
BOMR - OMA request signal from the Q-Bus.
BDOUT - Q-Bus data output strobe.
BEVNT - Q-Bus signal used to generate REVNT. Can be used to initiate an interrupt.
BHALT - Q-Bus halt signal used for a priority 7 interrupt that vectors through location 140.
BINIT - Q-Bus signal used to initialize all the devices on the bus.
BIRQ4 - Q-Bus level 4 priority interrupt request that is used to initiate the internal IRQ4 signal.
BKRQ - Internal control signal initiated by BHALT or BREAK detect from terminal.
BPOK - Q-Bus signal that goes high 70 ms after BDCOK and goes low when ac power is lost.

G-1

BREAK - Initiated by pressing the BREAK key. Causes the KXTI 1-CA SBC to generate BREAK H that
is used as an interrupt.
BRPLY - Slave's acknowledge of a Q-Bus cycle.
BSACK - Acknowledges receipt of a OMA grant signal.
BSYNC - Q-Bus cycle control signal.
BWTBT - Q-Bus write byte control signal.
CAS - An output from the microprocessor that acts as data strobe. Used for the read/write, OMA, and
ASPI transactions.
Condition codes - The least significant four bits of the processor status word that indicate the results of the
last instruction executed.
Configuration - Allows the user to select optional features of the SBC by inserting jumpers.
Control and status register (CSR) - Internal register that allows the program to control and monitor the
operation of the SBC.
Control word - The data contained in the control register of the parallel 1/0 chip that determines the
configuration of the parallel 1/0 interface.
COUT - An output from the microprocessor clock that is asserted once during each microcycle.
CSKTA - The RAM/ROM socket set A chip select strobe.
CSKTB - The RAM/ROM socket set B chip select strobe.
CTMER - Time-out interrupt that has the same effect as HALT.
Cycle slip - This condition exists when the READY input is pulsed while RAS is asserted. It causes the
microprocessor to be idle, and no transactions occur.
DATI - Q-Bus transaction that transfers 16 bits of data from the slave to the master.
DATO - Q-Bus transaction that transfers 16 bits of data from the master to the slave.
DATO(B) - Q-Bus transaction that transfers 8 bits of data from the master to the slave.
DMA - Direct memory access for transferring blocks of data without program intervention.
DMA transaction - A microprocessor transaction during which the microprocessor gives up bus mastership to another device for direct transfer of memory data.
DTC - Direct transfer controller for OMA transactions.
EIA RS232-C - Electronics Industries Association serial line interface standard.
EIA RS423 - Electronics Industries Association serial line interface standard.
EOP - End of Process or End of Pass.
G-2

Fetch/read - Microprocessor transaction that transfers data from memory or 1/0 into the microprocessor.
The data may be an instruction (fetch) or an operand (read).
Firmware - The programs that reside in the PROM or ROM hardware.
FPLA - Field programmable logic array. Used to decode memory addresses.
HALT - The highest priority interrupt. Causes the microprocessor to go to the restart address and loads
the PSW with 340.
Handshaking protocol - The series of events used to establish data transfers.
IAK - Microprocessor transaction to acknowledge an interrupt and secure a vector from an on-board
location or from the Q-Bus.
llDAL 0-15 - Local multiplexed data and address lines used for DMA transfers.
Interrupts - Interruption of the normal program execution to service an external request.
Interrupt protocol - Signal sequence required to initiate and service interrupts.
Interrupt vector - The memory location in which the address of the interrupt service routine is stored.
LSl-11 bus - An asynchronous bus that provides interconnections for LSI-11 type modules.
Maskable - A priority level that can be inhibited by loading the PSW with a higher priority code.
Memory mapping - The partitioning of memory via jumper configurations to determine the on-board
portions and the Q-Bus portions of memory.
Microcycle - The time necessary to execute one microinstruction. A transaction may use three or four
microcycles.
Mode register - A register used to define the microprocessor's operations structure.
Nibble - The upper or lower half of a byte that consists of four bits.
Nonmaskable - A priority level that is higher than the level selectable by the PSW. An interrupt which
cannot be disabled.
NOP - A transaction that produces no useful output. It is used to introduce a delay or wait period.
Parallel 1/0 - Parallel data interface.
Parallel 1/0 handshaking - Control signals used to establish parallel data transfers.
PI (priority in) - A microprocessor output signal used to strobe interrupt and DMA requests into the
microprocessor.
Power-Fail (PFAIL) - A nonmaskable interrupt caused by a power failure that causes the microprocessor
to vector through location 24 to the power-fail routine.
Priority - Bits 5 and 6 of the PSW. Used to define the priority level of the microprocessor.

G-3

.PSW register ·.,-; A micropi:ocessor ·register that contains the processor status· word (PSW).
PUP - An input to the microprocessor that controls the power-up sequence. When it is switched from high
to low, the microprocessor power-.up sequence is initiated.
Q-Bus - See LSI-11 bus definition.
QIR - Interrupt register to the Q-Bus arbiter.
RAM - Random-access memory defined as read/write memory.
RAS - Microprocessor output used as an address strobe in read/write, IAK, and OMA transactions.
READY - Input to the microprocessor that causes cycle slips when pulsed.
Restart address - The address that the microprocessor jumps to when executing a HALT interrupt.
REVNT - See BEVNT.
ROM - Read-only memory that cannot be modified with a normal write operation.
R/WHB - A microprocessor output that is low for high byte write transactions and high for read
transactions.
R/WLB - A microprocessor output that is low for low byte write transactions and high for read
transactions.
RTI - Return from interrupt instruction.
SBC - Single board computer.
SELO/SELl - Microprocessor outputs used to define the transaction being performed.
Serial 1/0 - Asynchronous serial line units for the transfer of serial data. SLUl and SLU2 are two such
units used in the KXTI 1-CA SBC.
Spurious halts - Halt conditions that are not internally created in normal operation.
Stack pointer - The register that contains the address of the last word stored on the stack.
Start address - The address that the microprocessor goes to during power-up.
TDAL 0-15 - Internal on-board bus used for multiplexed data and address lines. See BOAL 0-15.
Trace bit - Bit 4 of the PSW that causes a trap to location 14 after the next instruction is completed.
Transaction - A sequence of microcycles used to complete a designated microprocessor function such as
read, write, ASPI, or IAK.
Tristate - Designates that a signal is in a high impedance ·condition and not a logic "l" or "O".
Vector address - Memory location the microprocessor accesses for the address of the interrupt service
routine during an interrupt.

G-4

Wait state - A condition during which the microprocessor performs no useful transactions while waiting
for a response or data.
Wakeup circuit - Holds BDCOK negated for 50 ms after de power has been applied.

G-5

INDEX

Address decoder, 3-24
Autobaud, 4-9
Arbiter, 2-7 ,2-8

Interrupts, 3-21
external vector, 3-26
internal vector cycle, 3-27
handling, 3-23-3-28
1/0 interface, 1-1
parallel configuring, 3-37, 5-37-5-48
SLUl, 3-33, 5-34-5-36
SLU2, 3-34, 3-35, 5-49-5-66
channel A, 3-36
channel B, 3-36

Backplane, 6-28
installation into, 6-28
pin identification, 6-30
Battery back-up, 4-3
specifications, 1-6
Bus cycle, 3-17-3-20

Logic sequencer, 3-17, 3-19
Loopback connectors, 6-3, 6-35, F-1

Cables, external, 6-32, 6-33
Connectors, see loopback
compatible signals, 6-34
Control status registers KXTCSR, 5-1
KXTCSR A, 5-1
KXTCSR B, 5-3
KXTCSR C, 5-5
KXTCSR D, 5-6

Memory, local, 1-1, 1-4, 3-28
battery backup, 6-11
configuring, 6-9-6-14
maps, 4-2, 4-10,
user sockets, 3-28, 6-9, 6-12
Microprocessor, 3-1
control signals, 3-4-3-12
interrupt priority, 3-23
cycle slipping, 3-24

D
DMA controller, see DTC
DTC, 2-3
operations, 1-4, 2-3, 3-30, 5-20-5-33
local, 3-31
Q-Bus, 3-32
1/0 port, 3-32
termination of, 3-32, 3-33
Diagnostics, 6-36

Native firmware, 2-5, 4-1
SBC set-up, 4-3
command register, 4-4
control commands, 4-5-4-6
restart handling, 4-10-4-11
selftest commands, 4-6-4-8
serial ODT, 4-8-4-9
NXM (nonexistent memory location), 5-6

F
Firmware, see native firmware

1-1

INDEX (Cont)
0
Operating modes, 1-1
peripheral processor, 2·6-2-10
standalone, 2-1-2-6

p
Programmable timers, 1-1, 1-3, 5-49
Power connections, external backplane, 2-1, 6-31
Power-fail Handling, 3·26
Power supply, 6-28
specifications, 1-6
Q

QIR (Q-Bus Interrupt Register), 3-17, 5-9
R

Restart handling, 3-25

s
Specifications, board, 1-5-1·7

1-2

Digital Equipment Corporation • Bedford, MA 01730