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Document:	PDP-15 Systems Maintenance Manual Volume 1
Order Number:	EK-15001-MM
Revision:	004
Pages:	194
Original Filename:

OCR Text

Digital Equipment Corporation
.

Maynard, Massachusetts

PDP-15 Systems

EK-15001-MM-004

PDP-15 SYSTEMS
MAINTENANCE MANUAL
VOLUME 1

DIGITAL

EQUIPMENT

CORPORATION

MAYNARD, MASSACHUSETTS

First Edition, October 1970

2nd Printing (Rev), December 1970

3rd Printing (Rev), October 1973
4th Printing (Rev), February 1975

Copyright © 1970, 1973, 1975 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this
manual.

Printed in U.S.A.

The following are trademarks of Digital EQquipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS
Page

CHAPTER 1

GENERAL DESCRIPTION

Introduction

System Description

Central Processor

KP15 Central Processor

.3.2

Teletype Control

.3.3

KC15 Console

.3.4

KE15 Extended Arithmetic Element (optional)

.3.5

KF15 Power Fail (optional)

1/O Processor

4.1

KD15 1/O Processor

4.2

KW15 Real-Time Clock (optional)

Memory

5.1

MM15 Memory

.5.2

MK15 4K Memory Expander (optional)

.5.3

ME15 Memory

.5.4

MP15 Memory Parity (optional)

BA15 Peripheral Option Expander

6.1

PC15 High-Speed Paper-Tape Reader/Punch (optional)

.6.2

LT15A Single Teletype Control (optional)

.6.3

VP15 Display Control (optional)

BB15 Internal Option Expander

7.1

KA15 Automatic Priority Interrupt (API - optional)

7.2

KM15 Memory Protect (optional)

7.3

KT15 Memory Protect and Relocate (optional)

System Interconnections

.8.1

CPU and IPU-to-Memory Bus

.8.2

IPU-to-1/O Devices (1/0O Bus)

1-9

.8.3

Console=to=-CPU (I Bus)

1-10

.8.4

BB Option Panel to Ceniral Processor

1-10

System Specifications

1-10

CONTENTS (Cont)
Page

CHAPTER 2

MM15 MEMORY
Introduction

Core Addressing Matrix

2. 1

Stack Dimensions

.2, 2

X-Y Matrix Construction

2. 3

Control Logic Architecture

Control Logic Flow

4. 1

Read/Restore Cycle

Clear/Write Cycle

N
N

Memory Port Switch

2-12

Registers

3-1

Accumulator (AC)

3-1

Link (L)

3-1

Program Counter (PC)

3-1

Memory Input Register (MI)

3-1

Memory Output Register (MO)

3-2

Operand Address Register (OA)

3-2

Instruction Register (IR)

3-2

Index Register (XR)

3-2

Limit Register

3-2

Bus Structure

3-2

C Bus

3-3

A Bus

3-4

B Bus

3-4

Sum Bus

3-4

Shift Bus (D Bus)

3-5

Data Manipulation Hardware

3-5

Control State Generation

3-6

Ul(.h-hOJNN.N)

FR
TR

W
W
W
W
W
W
W
w
w
WwWw
W
W
W
W

~003.\10~01-th-'

CENTRAL PROCESSOR

CHAPTER 3

Read/Pause/Write Cycle

.4. 3

W oW

Inhibit/Sensing Construction

Addressing

Page Mode

3-7

CONTENTS (Cont)
Page
3-9

Memory Read and Write

3-10

Instruction Fetch

3-10

Instruction Operation Details

3-11

3 .8.1

Read Group (LAC, ADD, TAD, AND, XOR)

3-11

3 .8.2

DAC and DZM

3-11

3 .8.3

JMP

3-11

3 .8.4

JMS and CAL

3-11

3 .8.5

1Sz

3-15

3 .8.6

SAD

3-16

3. 8.7

XCT

3-16

3 .8.8

OPR

3=-16

3 .8.9

LAW

3-17

3 .8.10

I0T

3=17

3 .8.11

Index Group (XG)

3-17

3 .8.12

Interrupts (API and PI)

3-18

3 .9

Defer and Auto~Increment

3-18

3 .10

Console Operation

3-20

3 .10.1

Console Cable Multiplexer

3-20

3 .10.2

Key Functions

3=21

3. 11

Read In

3-21

CHAPTER 4

1/O PROCESSOR
4-1

Timing Generator

4-3

Request Synchronization

4-4

10T

4-4

I/O Bus

4-5

Data Channel Facility (DCH)

4-5

1/O Bus Device Priority and Synchronization

4-16

Single Cycle Input Transfers

4-18

Single Cycle Output Transfers

4-23

Multicycle Input Transfers

4-23

Multicycle Output Transfers

4-33

N
o

—l_o

KD15 Input/Qutput Processor

Bank Mode

3 .5.2

CONTENTS (Cont)

4.14

Inhibit Increment the Current Address

4~33

4.15

Data Channel Latency

4-41

4.16

Program Interrupt

4-41

CHAPTER 5

POWER DISTRIBUTION

PDP-15 Power

5-1
5-1

AC Control

5-2

DC Power Source

5=2

715 Power Supply

Power Harness

5-4

Local Regulation

5-4

Power Monitor Network

PDP-15/C Power

5-5

861 Power Controls

5-8

PDP-15/C Power Supply Adjustments

5-11

CHAPTER 6

OPTIONS

.
O
;r

KE15 Extended Arithmetic Element (EAE)

6-1

AW~

General Operation

6-1

Normalize Instructions

6-3

MUL(S) Instruction

6~6

DIV(S) Instruction

6-15

IDIV(S) Instruction (See Table 6-19)

6-20

FRDIV(S) Instruction (See Table 6-20)

6-21

Bulk Regulation

Indicators

6-22

el
cesd
)

AN
—

4-33

Increment Memory

4.13

4-33

Add to Memory

4.12

Page

EAE Execution Times

6-22

KW15 Real-Time Clock

6-22

KF15 Power Fail Option

6-23

KA15 Automatic Priority Interrupt (API)

6=26

General Description

6-26

Operational Description

6-29

1
1
1
1

1
1

4. 2

CONTENTS (Cont)
Page

6-37

KM15 Memory Protect

6-38

KT15 Memory Protect and Relocate

6-42

PC15 High-Speed Paper-Tape Reader/Punch

6-45

High=-Speed Reader

6-45

.8.1.1

Alpha Mode

6-47

.8.1.2

Binary Mode

6-48

.8.1.3

Read-In

6-48

.8.2

High=Speed Punch

6-48

LT15A Teletype Interface

6-48

.10

VP15 Display Control

6-55

.10.1

Display Control

6-56

.10.2

Digital-to-~Analog Converters (D/A)

6-56

.10.3

VP15A Storage Tube Display 10Ts

6-57

.10.3.1

Non=Store Mode

6-57

.10.3.2

Store Mode

6-57

.10.3.3

Store and Non=Store Mode

6-57

.10.4

VP15C Display and VP15B Oscilloscope 10Ts

6-57

.10.5

Principles of Operation

6-58

N
O
O

MP15 Memory‘ Parity

CHAPTER 7

MAINTENANCE

7.1

Introduction

7-1

7.2

System Maintenance

7-1

7.2.1

Maintenance Equipment

7-1

7.2.2

Maintenance Test Programs

7-2

7.3

Preventive Maintenance

7-4

7.3.1

Introduction

7-4

7.3.2

Scheduled Mdaintenance

7-5

7.4

Corrective Maintenance

7-6

7.4.1

Introduction

7-6

7.4.2

Preliminary Investigation

7-7

7.4.3

System Troubleshooting

7-7

7.4.4

Console Checks

7-8

7.4.5

Processor Troubleshooting

7-9

7.4.6

Logic Troubleshooting

7-10

vili

CONTENTS (Cont)
Page

7.4.6.1

Troubleshooting Intermittent System Problems

7-11

7.4.7

Module (Circuit) Troubleshootiing

7-12

7.4.8

Repairs and Replacements

7-14

7.4.9

Validation Tests

7-14

7.4.10

Recording (Log Book)

7-15

7.5

Adjustment Procedure

7-15

DC Voltage Adjustments

7-15

7.5 72

Memory Timing Adjustments

7-17

7.5.2.1

Memory Strobe with Current Probe

7-17

7.5.2.2

Memory Strobe with No Current Probe

7-18

7.5.3

CP Timing Adjustment

7-18

7.5.3.1

CP Clock

7-18

7.5.4

I/O Timing

7-20

7.5.4.1

1/0 Clock

7-20

7.5.4.2

Console Clock

7-20

7.5.4.3

Teletype Clock

7-22

7.5.5

Timing Adjustment Summary

7=22

8.1

ILLUSTRATIONS

Title

Figure No.

Page

1-1

PDP~15 Configuration

1-1

1-2

PDP-15 System Block Diagram

1-2

1-3

PDP-15/10 System Configuration Diagram

1-4

PDP-15/20 System Configuration Diagram

1-5

PDP-15/30 System Configurati on Diagram

1-6

PDP-15/40 System Configuration Diagram

1-7

PDP-15/C System Configuration Diagram

2-1

Current Path Diagram

2-2

Sense Amplifier/Inhibit Driver, Simplified Diagram

2-3

Typical I nhibit Current Waveforms

2-4

Basic Device=-Memory Conirol Signal Flow

2-5

Memory Cycle Detailed Flow Chart

2-13

2-6

Central Processor Read Cycle

2-15

2-7

Central Process or Wri te Cycle

2-16

viii

ILLUSTRATIONS (Cont)
Title

Figure No.
3-1

CPU Bus Structure

3-2

Page (PDP-15) Mode Address Formation

Page
3-3

Bank ( PDP-9) Mode Address Formation

3-9

3-4

Read-In Flow Diagram

3-22

4-1

Basic I/O Timing

4-3

4-2

IOT Instruction Format

4-4

4-3

IOT I nstruction Timing

4-6

4-4

IOT Flow Diagram

4-7

4-5

1/O Bus Cabiles

4-9

4-6

Data Channel Block Diagram

4-17

4-7

Simplified M104 Module Diagram

4-17

4-8

M104 Timing Diagram

4-18

4-9

Single Cycle Data In Transfer, Block Diagram

4-19

4-10

Single Cycle Data In Transfer, Detailed Flow Chart

4-21

4-11

Single Cycle Data Out Transfer, Block Diagram

4-24

4-12

Single Cycle Data Out Transfers, Detailed Flow Chart

4-25

4-13

Multicycle Data In Transfer Block Diagram

4-27

4-14

Multicycle Timing Diagram

4-29

4-15

Multicycle Data In Transfer, Block Diagram

4-31

4-16

Multicycle Data Out Transfers, Block Diagram

4-35

4-17

Multicycle Data Out Transfer, Detailed Flow Chart,

Sheet1 of 2

4-37

Power Distribution Block Diagram

5-1

PDP-15/C Fower Distribution Block Diagram

5-7

861B Power Controller Schematic

5-9

861C Power Controller Schematic

5-9

EAE General Flow Diagram

6-4

EAE Multiply
EAE Divide

6-17

Real=Time Clock, General Flow Diagram

6-24

Power Fail Sequence With Power Fail Option Disabled,
Flow Diagram

6-25

Power Restore Sequence With Power Fail Option Disabled,
Flow Diagram

6-25

ILLUSTRATIONS (Cont)
Title

Figure No.
6~7

Power Fail Sequence With Power Fail Option Enabled,
Flow Diagram

6-8

Page

6-26

Power Restore Sequence With Power Fail Option Enabled,
Flow Diagram

6-27

6-9

API Flow Diagram

6-31

6-10

API Block Diagram

6-33

6-11

AP1/P1/Central Processor Flow Diagram

6-35

6-12

KM15 Memory Protect Flow Diagram

6-41

6-13

KT15 Memory Protect/Relocate Flow Diagram

6-44

6-14

Memory Protect and Relocate Interconnection Diagram

6-46

6-15

Tape Format and Accumulator Bits (Alphanumeric Mode)

647

6-16

HRI Tape Format and Accumulator Bits (Binary Mode)

6-49

6-17

High=Speed U ader Operation, Flow Diagram

6-50

6-18

High-Speed Punch Operation, Flow Diagram

6-51

6-19

Teletype Receiver (Keyboard) Timing

6-53

6-20

Teletype Transmitter (Printer) Timing

6-21

VP15 Controller, Simplified Block Diagram

6-58

7-1

Integrated Circuit Location

7-13

7-2

Integrated Circuit Pin Location

7=13

7-3

G821 Module Adjustment

7-16

7-4

G822 Module Adjustment Locations

7-16

7-5

G823 Module Adjustment Locations

7-17

7-6

MEM Current

7-17

7-7

MEM Sirobe Delay

7-18

7-8

MEM Strobe/Sense Amp Output

7-19

7-9

CP Clock

7-19

7-10

TSO1 Duration

7-20

7-1

Machine Cycle Time

7-21

7-12

I/O Clock

7-21

7-13

Console Clock

7-22

7-14

Teletype Clock

7-23

TABLES

Title

Table No.
1-1

Page

PDP-15 Central Processor Cycle Times, Basic and
1-10

Expanded Configurations*

2-1

Memory Bus Signals and Data Lines

2=2

Control Flops and Register Responsibilities

2-10

Control States for LAC Instruction

3-7

3-2

CPU/Memory Interaction

3-12

3-3

Instruction Operation

3-13

3-4

ISZ Instruction Operation

3-15

3=5

XCT Instruction Operation

3-16

3-6

Deferred Addressing Operation

3-19

Auto-Increment Operation

3-20

Summary of PDP-15 Input/Output Facilities

4-2

1/O Bus Signal Functions

4-10

715 Power Supply Distribution

5-5

PDP-15/C Power Supply Source Distribution

5-8

PDP-15/C Voltage Regulator Adjustments

5-11

EAE Instructions

6-2

EAE Microinstructions

6-3

4-1

EAE NOP 640000

OSC 640001

6-9

OMQ 640002

6~9

CMQ 640004

6-10

LACS 641001

6-10

LACQ 641002

6-10

6-9

ABS 644000

6-11

6-10

CLQ 650000

6-11

LMQ 652000

6-11

6-12

GSM 664000

6-12

6-13

LRS 6405XX and LRSS 6605XX

6~12

6-14

LLS 6406XX and LLSS 6606XX

6-13

6-15

ALS 6407XX and ALSS 6607XX

6-13

6-16

NORM 640444 and NORMS 660444

6-13

6-17

MULS 6531XX and MULS 6571XX

6-14

6-18

DIV 6403XX and DIVS 6443XX

6-19

TABLES (Cont)
Title

Table No.

Page

6-19

IDIV 6533XX and IDIVS 6573XX

6-21

6-20

FRDIV 6503XX and FRDIVS 6543XX

6-21

EAE Indicators

6-22

Standard API Channel/Priority Assignments

6-28

6-23

MP15 1OT Instructions

6-38

6-24

High-Speed Reader IOTs

6-47

6-25

High-Speed Paper Tape Punch

6-48

6-26

Primary Teletype 10Ts

6-52

6-27

The LT15A Instruction Set

6-55

6-28

Settling and Intensification Times

6-59

7-1

Maintenance Equipment

7-2

MAINDEC Diagnostic Programs

7-3

PDP-15 Timing Adjustment Summary

7-23

xii

CHAPTER 1

GENERAL DESCRIPTION
1.1

INTRODUCTION

This chapter identifies and describes the modular parts of the PDP=15 system hardware, and shows how
they are incorporated into the system.

PDP=-15 system configuration.

Figure 1=1 shows the physical location of these parts in the

Figure 1-2 is a block diagram of the inter-connection of the elements

of the system which are covered by this manual. Other options are covered
by separate manuals.

HO963D
BAY 00

H963E
BAY IR

MM15

IND PANEL

MK15

kP15

FANS

KD15

BBI15

KP15
KD15
KE15
KF15

KW15

KE15

KT15

MP15

KM15

KA15

KF15
KW15
PCO5

DISPLAY

KC15

PCOS

FANS

*[H742

FANS

Bals

PC15

BA15

LT15A

VP15
DW15A

’

LTisa
:

BB15
KT15

KM15
KA15

715 PS

INDICATOR

* H742 Power Supply is employed if ME15 Memory

PANEL

PDP-15/C

.
is installed
18- 0272

Figure 1-1

1.2

PDP=-15 Configuration

SYSTEM DESCRIPTION

The PDP-15 System consists of a KP15 Central Processor, KD15 I/O Processor, KC15 Console, ME15
and/or MM15 Memory, associated cabinets, hardware, power supplies, and any of a large number of
options.

1-1

ME 15

ME15

}

mm1s | mmis
4K : 4K

I
|

MM15 | MK15
4K | 4K

i
|

MM15 : MK15
4K | 4K

MM 15 = MK15
4K | 4K

]

BB15
1

BUS

OPTION

CABLE

MEMORY DATA LINES

MEM
PROTECT

KMI1S

MEM
| RELOCATE

KT15

MEM
PARITY

MP15

APl KA1S

MEMORY
PORT
SWITCH

BA15
IPU
KD 15

PC15
READER

cPU
KP15

PUNCH

VP15
DISPLAY

KW15 RTC

KE15

EAE

KF15

PWR FAIL

TTY CONTROL

TTY

LT15A
TTY

POS 1/0 BUS

I BUS

POS 1/0 BUS

KC15

CONSOLE
DWI5A

NEG

CONVERTER

15-0274

Figure 1-2

PDP=15 System Block Diagram

Hardware configurations for which special software systems have been developed are designated as
follows:
G.

PDP-15/10 Compact System — consists of a 4K core memory, Central Processor, 1/O Pro~
cessor, and ASR33 Teletype
®. This is the basic PDP-15 System (see Figure 1-3).

PDP-15/20 Advanced Monitor System — consists of the basic PDP=15 with 8K of core
memory, DECtape control and 2 DECtape transports, high-speed paper-tape reader/
punch, extended arithmetic element, and KSR 35 Teletype (see Figure 1-4).

® Teletype is a registered trademark of Teletype Corporation.
1-2

LOGO

Ffirs

CARAYEL

LOGO

FAN

MEMORY

LOGIC

CP/10

INTER—

CONNECTION

COVERS

CP/IO

ENCLOSED

__”_,,,,_4——’"‘“"‘LOGK

(REMOVABLE)

CONSOLE

cowsou-:—7

REAR

DOOR

FANS

*|H742

TABLE/'

POWER
SUPPLY

H742 POWER SUPPLY

POWER

POOR

POWER

SUPPLY

DEC 19" CABINET
DIMENSIONS:

30" DEEP

21-11716" WIDE

71-7/16" HIGH

* H742 Power Supply is empioyed
if

ME15 Memory is installed.

15-0013

Figure 1-3

PDP-15/10 System Configuration Diagram

H963D

HO63E

FAN

INDICATOR

BLANK

(BAY 00)

(BAY IR)

MMI5A, MKISA
8K MEMORY

PROCESSOR
AND
1/0 PROCESSOR.

AND KE {5
EXTENDED
ARITHMETIC
ELEMENT

PC15

SPEED
HIGH
PAPER TAPE

égglf)SOLE
TABLE

35 KSR

TELETYPE

READER/PUNCH

* gg&%R
SUPPLY

|_FANS

PC15)

SECTARE AL

TRANSPORT

TCIS

| DECTAPE

CONTROL

BLANK
AC UTILITY

OUTLETS

¥ H742 Power Supply is employed if ME15 Mernory is installed.

Figure 1-4

(BAY 2R)

BLANK
BA15 {CONTROL FOR

715
power

H963F

BLANK
15- 0326

PDP-15/20 System Configuration Diagram

PDP=15/30 Background-Foreground System — consists of a PDP-15/20 with a 16K core

memory, four DECtapes, a real-time clock, automatic priority interrupt, a second online Teletype and memory protect (see Figure 1-5).

PDP-15/35 Disk Oriented Real=Time Executive System (RSX) — consists of a PDP~15/20

with a 16K core memory, two DECtape transports, automatic priority interrupt option,

real-time clock, a DECdisk file with 262K words of storage and memory protect.

PDP-15/40 Disk Criented Background-Foreground System — consists of a PDP~15/30 with

a 24K core memory, two DECtapes, DECdisk Control, two random access DECdisk files
with a capacity of 524K words of storage and memory protect (see Figure 1-6).

Unichannel 15 System. Refer to Unichannel 15 System Maintenance Manual
(DEC-15-HUCMA-B-D) for a complete description of the system.

PDP-15/C Compact System - consists of 48K core memory, central processor,
I/O processor, and high-speed paper-tape reader/punch (see Figure 1-7).

D.B CENTRAL PROCESSOR !
—mm——

1.3.1

KP15 Central Processor.
T

The KP15 Central Processor functions as the main component of the computer by carrying on bi-

directional communication with both the memory and 1/O Processor.

Provided with the capability to

perform all required arithmetic and logical operations, the central processor controls and executes
stored programs.

It accomplishes this with an extensive complement of registers, control lines, and

logic.

1.3.2

Teletype Control
_

This provides the control for the console Teletype which may be an ASR or KSR Type 33 or 35 Teletype.

Logic is provided for the hardware readin of tapes from the Teletype reader in systems without

high-speed tape facilities. Characters may be read from the keyboard in either half-duplex mode

(characters echoed onto the printer) or full~duplex mode.

1.3.3

KC15 Console

The KC15 Control Console provides facilities for operator initiation of programs, monitoring of central

processor (CPU) and I/O Processor (IPU) registers, starting program execution and the manual examination and modification of memory contents.

1.3.4

KE15 Extended Arithmetic Element (optional)

e
————

The optional KE15 Extended Arithmetic Element (EAE) facilitates high-speed arithmetic operations and
register manipulations.

The EAE adds an 18-bit multiplier quotient register (MQ) to the system as

well as a 6-bit step counter register (SC).
7.65 ps.

Worst case multiplication time is 7.4 ps; division time is

H963D

H96 3E

H963F

(BAY 00)

(BAY IR)

{BAY 2R)

FAN

INDICATOR

MMIS A , MKIS
A
8K MEMORY

(See Note 1)

FANS

KP15 CENTRAL
CESSOR AND
1/0 PROCESSOR,

KAIS AUTOMATIC
PRIORITY INTERRUPT
AND
KMI5 MEMORY

BLANK

DECTAPE

E6NsoLE

PCI5

TUS6 DUAL
DECTAPE

PROTECTION

KE 15 EXTENDED

ELEMENT,) AND

READER /PUNCH

* 'P*g;‘ng

ELETYPE

TRANSPORT

HiCH SPeeR

TABLE

35 KSR

TU56 DUAL

suPPLY

BLANK

RANSPOR

|_FANS

TC15

BAIS (CONTROL FOR
LTISA AND PCI5)

DECTAPE
CONTROL.

AC _UTILITY

BLANK

33 KSR

TELETYPE

715

OUTLETS
NOTES

1. An identical 8K memory is mounted on the rear door of cabinet H963D.
There is space on this door for mounting two more 8K modules.

¥ H742 Power Supply is employed when ME15 Memory is installed.
15-0327

Figure 1-5

PDP-15/30 System Configuration Diagram

H963E

HO63D

H963B

HO63F

{BAY 2R)

{BAY 2L}

(BAY 00)

(BAY IR)

FAN

FAN
INDICATOR

INDICATOR

MM15A, MKISA

INDICATOR

(See Note 1)

FANS

KP15 CENTRAL

PRIORITY INTERRUPT | BLANK

8K MEMORY

RF18

ggfi%sgl.

KA15 AUTOMATIC

PROCESSOR
70
KE 15 EXTENDED'

RS09

ARITHMETIC

DECDISK

ELEMENT, AND

BLANK

DECTAPE

KC15

HigH SPEED

PC15

TU56 DUAL

READER /PUNCH

TRANSPORT

CONSOLE
TABLE

BLANK

35 KSR

TELETYPE
A(R DISTRIBUTION
SYSTEM AND POWER

SUPPLIES

NOTES

8K memory

dAul

are

TRANSPORT

DECTAPE

FANS

TCI8

BA15 (CONTROL FOR
LT1SA AND PC15)

DECTAPE
CONTROL

DWISA I/0 BUS

718

33 KSR

TELETYPE

CONVERTER

POWER

AC UTILITY

SUPPLY

1. Two more

TU56 DUAL

KW15 REAL

TIME CLOCK

RS9 sk

kM5 MEMORY

PROTECTION

OUTLETS

BLANK

ted on the rear door of cabinet H963D. There is space on

this door for mounting one more 8K module.

2. 96K of ME15 Memory may be installed inrear door.
15-0328

Figure 1-6

PDP-15/40 System Configuration Diagram

FRONT

SIDE

FAN

REAR
}

FANS

KP15

CENTRAL PROCESSOR

ME15 48K

AND I/0 PROCESSOR

MEMORY

FANS
PCOS5

HIGH SPEED

50 Hz

PAPER TAPE

TRANSFORMER

READER/PUNCH

716 POWER SUPPLY

KC158

856A POWER CONTROL

CONSOLE
|

H742 POWER SUPPLY

FAN

BA15

(CONTROL FOR P60S5)

BB15
CHASSIS

BA BB
INDICATOR

PANEL

861

POWER CONTROL

15-0809

Figure 1-7

PDP-15/C System Configuration Diagram

1.3.5

KF15 Power Fail (optional)

The KF15 Power Fail option offers maximum protection to programs during power failure and recovery

of power after failure. It enables the PDP-15 system to store active registers in memory before power
diminishes to a point beyond which data will be lost.

It also enables the PDP=15, upon the restora-

tion of power, to restore these registers and continue with the program that was previously in progress.

1.4

1/0 PROCESSOR

1.4.1

KDI15 /O Processor

The KD15 Processor (IPU) is an autonomous subsystem of PDP=15 which supervises and synchronizes all
IOT and Data Channel (DCH) transfers between the devices and the PDP~15 central processor and

memory. The I/O Processor contains the arithmetic and control logic hardware to supervise all 1/O
device activity.

The IPU is, however, a passive system in that it responds to requests for activity

from devices or the CPU rather than initiating activity.

1.4.2

KW15 Real-Time Clock (optional)

The KW15 Real-Time Clock option gives the user a time reference capability. The real-time clock
produces clock pulses at a rate of 1 every 16.7 ms for 60 Hz systems; these systems increment a core
location which can be preset and monitored under program control .
1.5

MEMORY

1.5.1

MMI5 Memory

The MM15 Memory is the primary storage area for the computer instructions and data.
ganized into pages which are paired into memory banks.

Memory is or=

Each MMI15 has 4K 18-bit binary words of

high-speed random access magnetic core storage. Each bank is a unit of 8K words. The Central Pro-

cessor and 1/O Processor have provisions to address up to 128K words of core memory with the aid of a
MX15 Memory Multiplexer. Any word in memory may be addressed by either the Central Processor or
the 1/O Processor.
1.5.2

MK15 4K Memory Expander (optional)

This option expands the MM15 memory control from 4K to 8K 18-bit words. It consists of the core
memory stack and the necessary read/write circuits and must be used with an MM15.
1.5.3

ME15 Memory

The ME15 Core Memory provides the PDP-15 wi th up to 96K 18-bit words on the rear door. The ME15
is mounted on the rear door of the CPU cabinet and may be added to PDP-15 installations equipped
with MM15 Memory. The MX15 Memory Multiplexer is not required. For additional information
regarding the ME15, refer to the ME15 Core Memory Maintenance Manual, DEC-15-HMEMA-A-D.
1-7

1.5.4

MP15 Memory Parity (optional)

The MP15 Memory Parity option enables the PDP-15 to continuously check information being read
from core memory and determine whether information has been erroneously picked up or dropped.

does this by monitoring all information as it is being sent to the memory for storage, and writing a
parity bit.

When this word is read from memory, the word and the bit are checked to determine

whether any information has been changed, and a parity error flag is raised if a change is detected.
Memory parity is not available with the ME15 memory.

1.6

BAI15 PERIPHERAL OPTION EXPANDER

This option houses power and 1/O bus interface logic for the PC15, LT15A, and VP15 which are described below; only one BA15 is required per system.

1.6.1

PC15 High-Speed Paper-Tape Reader/Punch (optional)
S

This option includes a PC05 Reader/Punch and the control to interface it to the PDP=15. Characters
can be read from paper tape at a maximum rate of 300 characters per second or punched at a rate of
50 characters per second.

When this option is installed, the PC15, instead of the TTY, is used for

hardware READIN.

1.6.2

LT15A Single Teletype Control (optional)
A

This option provides the logic to receive and transmit information through a KSR33 or KSR35 Teletype.
This provides a second Teletype capability to the PDP~15 system.

1.6.3

VP15 Display Control (optional)
————

This option interfaces the PDP-15 to various display devices by providing the digital-to~analog converters and the control logic for the x and y positioning as well as the intensification of the VP15A
Storage Tube Display, VP15B Oscilloscope Display, or VP15C X-Y Oscilloscope Display.

1.7

BBI15 INTERNAL OPTION EXPANDER
g

This expander houses the power, 1/O bus interface, memory bus interface and various control signals
from the processor for the operation of the KA15 Automatic Priority Interrupt, KM15 Memory Protect,

KT15 Memory Protect and Relocate, and MP15 Memory Parity options.
per system,

1-8

Only one BB15 is required

1.7.1

KAI15 Automatic Priority Interrupt (API - 6pfion.a|)

The API option adds 8 additional levels of priority to the PDP=15. The upper 4 levels are assigned tc

1/O devices and are initiated by flags (interrupt requests) from these devices. The lower four levels
are programming levels and are initiated by software requests.

High data rate or critical devices are

assigned to high priority levels and can interrupt slower device service routines.

the slower device interrupt request until it can be serviced.

The API option holds

The cause of the interrupt is also direct-

ly identified eliminating the need for service routines and flag search routines.

1.7.2

KMI

optional)

The KM15 memory protect provides the PDP=15 core memory with protected memory locations that

cannot be accessed by the user. It includes a boundary register and associated control logic to establish the lower limit of the user's program. It has the facility to trap IOT, HALT OAS and chained
execute instructions and the addressing of a non-existent memory bank .

1.7.3

KT15 Memory Protect and Relocate (optional)

The memory protect and relocate option is similar to the memory protect option. The KM15 must be
used with the KT15. However, it contains a relocation register as well as a core allocation regi:.er.

The relocation register provides the lower limit of the user program and relocates the user upward from
the real machine location by the quantity contained in the relocation register. The core allocation

register indicates the last 256 word increment available to the user. Other features of the memory
protect option are also included in this option.

1.8

SYSTEM INTERCONNECTIONS

1.8.1

CPU and IPU-to~Memory Bus

The central processor and 1/O processor each asynchronously access memory over the same memory data lines (MDL). The priority structure concerning which processor's request is sent to memory is deter-

mined by the memory port switch. The 1/O processor is given first priority. The memory data lines
consist of 18 bi-directional lines over which address and then data information is transmitted to and
from memory. Various control signals are on this bus.

1.8.2

1PU=to=1/O Devices (I/O Bus)

The 1/O processor communicates with all devices over a common 1/O bus which contains bidirectional data lines; address lines; enable, request, and grant lines for API and data channel; and
others such as program interrupt and skip request.

1-9

1.8.3

Console=to~CPU (I Bus)

The indicator bus contains bi-directional lines to transmit information to the lights on the console and
switch information from the console to the central processor.

on the cable.
1.8.4

Several control lines are also located

The ME15 memory does not use the IBus,

BB Option Panel to Central Processor

Because the BB15 Option Panel contains several internal options which deal with the operation of the
central processor, a special cable is required so that the option may utilize these internal central processor signals.
1.9

SYSTEM SPECIFICATIONS

Functional Characteristics
Word Length

18 bits

Cycle time

Refer to Table 1-1

Core memory capacity

4096 words, expandable to 131,072 words
in 4K increments with MM15/MK15 Memory; 8K increments with ME15 Memory.

Core memory access
Page mode
Direct

Indirect
Indexed

4096 words
32,768 words
131,072 words

Bank mode
Direct

8,192 words

Indirect

32,768 words

Computation rate

625,000 additions per second

ASR33 Teletype

10 characters per second

Program-controlled [/O capacity

Up to 256 devices including prewired CPU
and IPU IOTs

Data channel capacity

Up to 8 device controllers

Operating Characteristics (H963D Cabinet; CP, 1/O and Memory)
PDP-15 power requirements

115V £15% or 230V £15%, 50 or

60 Hz £2%, single phase, 18-30A

PDP-15/C power requirements

95-130V or 190-260V, 47-63 Hz,

single phase, 12A
PDP-15 power consumption

4 KW max

PDP-15/C power consumption

1.3 KW max

Power supply outputs after local
regulation

+5, -6, -24 Vdc

Logic levels

0- .4V = logic 0

Test temperature range

50°120%

Relative humidity

10-95%

PDP~15 heat dissipation

13,650 BTU/hr.

PDP-15/C heat dissipation

4,000 BTU/hr.

2.4-5V = logic 1

Dimensions

Cabinet height

71-7/16 in.

Cabinet width

21-11/16 in.

Cabinet depth

30 in.

Shelf widths

19 in.

Shelf depth

19-5/16 in.

Door clearance (rear)

18-7/32 in.

Cabinet weight (loaded)

750 Ibs.

Teletype height

8-3/8 in.

Teletype width

22 in.

Teletype depth

18-1/2 in.

Teletype weight

44 lbs.

Table 1-1
PDP-15 Central Processor Cycle Times, Basic and Expanded Configurations*

Not In User Mode

Configuration

Read

In User Mode

Write

Read

Write

Max | Typical | Max | Typical | Max | Typical | Max | Typical

Basic

800

KM15 Memory Protect

830

800

830

800

830

800

975

KM15 Memory Protect and

965

880

965

880

| 1165 |

1080

1165 | 1080

MP15 Memory Parity

1100 | 1050

| 1100 |

1050

| 1100 |

1050

1100 | 1050

MP15 Memory Parity and
KM15 Memory Protect

1130

1255

MP15 Memory Parity,
KM15 Memory Protect and

1155

1355

KT15 Memory Protect/Relocate

920

KT15 Memory Protect/Relocate

Note: Cycle times are affected by installation of ME15 memory and by the Unichannel 15 System.
Refer to the appropriate maintenance manual for additional information.
*All cycle times are listed in nanoseconds.

CHAPTER 2
MM15 MEMORY
2.1

INTRODUCTION

The basic PDP=15 computer has a 4096 word, 18-bit memory. It occupies the top four racks of the
PDP-15 mainframe (racks A through D). The principal elements comprising rack A are control logic,

bus drivers, and INPUT slots for the memory bus cables. The memory address and memory buffer registers, x= and y=-select and driver confrols; and OUTPUT slots for the memory bus cables comprise
rack B. The stack matrix, sense amps and inhibit drivers, and slots for the indicator bus, make up

racks C and D.

This basic memory may be expanded to 8192 words by adding a 4K stack, a set of X~ and Y-select
and driver modules, and a set of inhibit and sense amp modules. The appropriate slots are available
in the MM15 and the addition is the option called MK15.

Each 4K unit of memory is called a page. Two 4K pages form an 8K bank. The physical capacity
of the mainframe is 32K (32,768) words. One 8K bank of memory is located above the mainframe

front panel. The three remaining 8K banks are located on the rear door. This 32K unit is called a
block of memory.

2.2

2.2.1

CORE ADDRESSING MATRIX

Stack Dimensions

The MM15 memory stack is a three dimension~three wire matrix (3D-3 wire). The term three dimen-

sion refers to an X-current, a Y=current, and an inhibit current. The X- and Y-currents are used to
switch the direction of the flux of a core; the inhibit current is used during the writing time to prevent the writing of bits where 0 bits are desired.

One matrix control network is used for each 4096 core words. The memory address selects which word
of the 4096 words is to be read or written into or both. The drive current pulses are generated by G223
Read/Write Drivers.

G222 Memory Selectors steer the direction of these currents.

2-1

When these currents flow through the core region they pass through 18 planes; the X~current pulse
through one set of wires and Y~-current pulse through another set of wires.
Y current pulses intersect at one of the possible 4096 cores (bits).
ducing an 18-bit word selection.

In each plane, the X and

This happens in all 18 planes pro-

A nineteenth plane is added for parity options.

The inhibit current pulse occurs only during a write portion of the memory cycle.
controls the bit data to be written into the address selected.

The inhibit current

This control is accomplished by stringing

a wire through all the cores of each individual plane to nullify the effect of the Y current at the core
intersection point.

In addition to using these wires for the inhibit current during a write portion of a

memory cycle, they are used for sensing the data during a read portion of a memory cycle.

2.2.2

X-=Y Matrix Construction

Each of the 4096 word locations provided by a 64 x 64 X<=Y matrix mdy be referenced by a 12-bit
memory address.

This memory address is separated into two sections:

bits 06-11 for the Y-select and

bits 12-17 for the X-select. It is decoded by the G222 modules. The total combination results in a
4096 word selection.

The current pulse, generated from the G223s, provides the current needed to

change the flux in the core.

There is a G223 for each X and Y matrix.

Figure 2-1 shows the current path produced by the combination of the modules and stack.

Although

this figure represents only one matrix of either X or Y, both matrices run at the same time.

The solid

arrows show a read current path and the dashed arrows show a write current path through the same se~
lected network.

the gates.

In this figure one can visualize four different core line paths by having pre=selected

Block schematics MMO06 through MM09 (Volume 2) show the X and Y matrices contained

in a bank of memory.

The I Loop is a jumpered wire on the back panel wiring for observation of

current waveforms on an oscilloscope.

2.2.3

There is a loop for each matrix.

Inhibit/Sensing Construction

The construction of the sense/inhibit network consists of one wire threaded through all the cores in
each plane.

The circuitry, for the sensing of a bit during a readtime and inhibiting during a write-

time, is contained in the G100 Sense Amplifier and Inhibit Driver modules.

The G100 module contains four sense amplifiers and four inhibit drivers.
used in the PDP-15 for each 4K memory stack.

Five of these modules are

(Refer to block schematics

MM 10 through MM15.)

Each inhibit driver consists of a two=input NAND gate and a high-speed current switch.

One driver

is used for each bit plane of the memory array. An inhibit signal is received by all inhibit drivers
only during a write operation (see Figure 2-2).

2-2

MEMORY STACK

READ

|
|
I
I
|
I
|

CURRENT

WRITE

CURRENT

172

G223

_
v

172 G223

SELECTED MA—[

READ

[ ]

WRITE

}

—

READ

24v

Low

HIGH

- o—

15-0133

Figure 2-1

365mA

Current Path Diagram

CORE
STACK

Ba;

AD2 AC1

CONN

-24v
24V

THRESHOLD

BB1 =3V
DATA

STROBE

-38V

>
\

. AKl —

';'R“

INHIBIT

AJT ——

CORES —»

BCI

BD1

BALUN
NET

DRIVER

)c ouT

JO—— AH1

AV1 (TEST POINT)

15-0119

365mA

Figure 2-2

Sense Amplifier/Inhibit Driver, Simplified Diagram

Each driver also receives a signal indicating the state of the corresponding bit in the MB. Inhibit
drivers that receive a signal indicating a O state in the MB bit are gated on and cause inhibit current
to be applied to the associated bit plane of the memory array. Each inhibit driver employs a discharge network to speed up inhibit current cutoff. The output of the inhibit driver is connected to

the middle of one core sensing string, which represents one bit plane of the memory array. The balun
network at the front end of the sense amplifier ensures equal current at all times through both sides of
the core string.

In addition to the balun network, the sense amplifier consists of a differential amplifier and output
driver. One sense amplifier is used for each bit plane of the memory array.

During a read operation

only the signal induced on the sense winding of a core plane by a core-changing state is received by
the differential amplifier. The differential amplifier has a nominal threshold of 17 mV. Output
pulses of standard amplitude and duration are supplied by the output driver when the sense amplifier
reads a logic 1 from the associated core, and is strobed by a standard positive going pulse at AC1.

Propagation delay from the input to the sense amplifier to the buffered output is 25 ns (maximum) and
from strobe input to buffered output is 15 ns (maximum). These output pulses directly set the MB register.

Typical waveforms of the inhibit current and the test point of the sense amplifier during a readtime are
shown in Figure 2-3. The only way to look at an inhibit current is to place a current probe around
one of the twisted pairs of wires coming out of the stack at the plug end.

X-Y DRIVE

CURRENTS

ReaD!

" ¥ (EQUAL
TO WRITE PULSE)
400MA NOMINAL

{
-

(TEST POINT)

CORE OUTPUT
(READ TIME)

720 MA TYPICAL

INHIBIT CURRENT
2
[

1%-027%

Figure 2-3

Typical Inhibit Current Waveforms

2.3

CONTROL LOGIC ARCHITECTURE

The control logic is designed so that each bank can be coupled to one bus network called the memory

bus.

Each bank responds when address lines 03 and 04 equal the setting of the manual switches on the

bank select card. These two switches can be preset by the operator (refer to Volume 2, drawing MMOT1).
Maintenance hint: Any computer with more than one bank of memory may interchange one addressing
bank number with another bank.

bank of memory.

All that is necessary is to manipulate the toggle switches on each

No two should be set to the same number. Volume 2, drawing MMO1 shows the

logic representation of the switches.
An exchange of signals between the memory and the device requesting access to the memory provides

asynchronous operation. The device has to provide five control signals, a 17-bit address (15 bits for
32K addressing and two more bits for the multiplexer option when addressing up to 128K), 18 bits of data,
and one more bit for parity, when a parity option is included. In return the memory accepts the signals

and notifies the device with a combination of four control signals and 18 bits of data plus one bit for
parity checking.

Table 2-1 identifies the bus signals and data lines on the memory bus.

lines are considered activated when at ground level.

All signal

All data lines are considered a one when at

ground level.

Table 2-1
Memory Bus Signals and Data Lines

Abbreviation

Signal & Direction

Definition

MDLO00-17

Memory Data Lines,

(MA)

00 through 17
(Memory Address to
memory)

Sends a seventeen bit word fo memory, address=
ing up to 128K locations.

(DATA)

(Data bidirectional)

Data consisting of 18 bits per word going in both
directions on the memory data lines (MDL).

MWR

Memory Write

MRD

Memory Read (to

Two levels used by the memory to identify what
mode of operation the device has selected.

(to memory)

There are three:

Read/Restore

(MRD ground)
(MWR high)

Clear/Write

(MRD high)
(MWR ground)

Read/Pause/Write (MRD ground)
(MWR ground)

M REQ

Memory Request (to

The initial signal that begins the memory cycle.

memory)
M BUSY B

Memory Busy on the

This signal inhibits a memory request from being

~ Bus (from Memory
bank to other Memory banks)

accepted by any memory bank on the same bus
while any one of the memory banks is busy.

Table 2-1 (Cont)
Memory Bus Signals and Data Lines

Abbreviation

Signal & Direction

ADR ACK B

Address Acknow-

RD RST B

Notifies the device of acceptance of the Memo-

ledge on the Bus (to
device)

ry Request, the Memory Address, and the mode
of operation (MRD and MWR signals).

Read/Restart on the

Notifies the device that the memory data is on

bus (to device)

DATA ACK

Definition

the bus for the device to strobe into its buffer.

This signal occurs only during a Read/Restore cycle or Read/Pause/Write cycle.

Data Acknowledge

Notifies the memory that it may take the memo-

(to memory)

ry data off the bus.

This signal is only needed

during a Read/Restore cycle or a Read/Pause/
Write cycle.

MRLS

Memory Release (to

memory)

Notifies the memory it has accepted the data

from memory during a Read/Restore cycle. During a Clear/Write cycle or a Read/Pause/Write
cycle, this signal tells the memory the device
has placed data on the bus.

MRLS ACK B

M PAR

Memory Release
Acknowledge on the
Bus (to device)

Notifies the device that the memory accepted
the data from the device and the memory cycle
is terminating .

Memory Parity (bi-

This signal line carries a 19th bit of data to be

directional)

stored into or readout of memory. This bit is
used to check data errors when a memory parity
option is implemented into the system.

‘

Refer to Figure 2-4 for the device=memory control signal flow.

Only one memory is allowed to be activated at a time. In order to guarantee that only one bank will

be accessed, a Memory Busy level (refer to Volume 2, MMO1 and MM19) is placed on the bus, inhibiting any other Memory Request from being accepted.

The internal timing of this signal, as well

as all other signals, is described in Paragraph 2.4,

2.4

CONTROL LOGIC FLOW

Refer to Figure 2-4. The memory is able to operate in any of three modes: Read/Restore, Clear/
Write, or Read/Pause/Write. The mode of operation to be selected depends entirely upon the needs
of the device.

This can be seen as the sequence of a memory cycle is defined.

Before memory can be started, Memory Busy must not be true and a 17-bit memory address (MDL 00-17)
and MRD, MWR, or both must be activated on the bus.

2-6

READ CYCLE

DEVICE

—

M REQ—___|
0—» MREQ

MEMORY

a—

SO AR

—

ADR ACK

0 —»ADR ACK
/‘

MRLS
= |

DATA ACK

RD RST

L
MRLS ACK

o--—mm_s/

0— DATA ACK

" 0 —»RDRST
—
0 —=MRLS ACK

WRITE

CYCLE

DEVICE

MEMORY

M REQ~__

\ADR ACK

—
o—> MREQET
|

= 5 —= ADR ACK
MRLS
—
\

a—

MRLS

ACK

0—> MRLSZ
|

[

6 —=MRLS ACK

READ/PAUSE/WRITE CYCLE
DEVICE

MEMORY

[

= MRLS AcK
O —» RD RST

o—>MRLs/
O—» DATA ACK—_____|

[ 0—»MRLS ACK
19-0278

Figure 2-4

Basic Device=Memory Control Signal Flow

2-7

The memory cycle starts with the Memory Request level from the device.,

50 ns after the above levels to allow for settling time on the bus.,

This level is generated

(Settling time is needed to avoid

potential skewing problems,) The device will wait until it receives an acceptance level from the

memory called Address Acknowledge (ADR ACK (1) B L).
M REQ.

This occurs approximately 110 ns after

The initiation of this level tells the device that the memory has accepted the request for ac~

cess to memory, the mode of operation, and has strobed the memory address lines into the MA latch
register.
level.

The Address Acknowledge causes Memory Busy to go low and also clears the Memory Request

The fall of the Memory Request level clears the Address Acknowledge level,

the sequence of the memory cycle may go into any.
of the three modes of operation.

At this point
Each is described

in the following paragraphs.,

2.4.1

Read/Restore Cycle

For this mode of operation the RD CON (read control) flop would have been set and the memory weuld
proceed to read data from the address requested.

The 18 bits of data read from core are strobed into

the Memory Buffer register and enabled on the bus (MDL 00-17) approximately 150 ns after ADR ACK

is set.

A parity bit is also strobed, if the option is present (MDL PAR (1) B L).

In order to allow for

settling time on the bus, the device only strobes this data when a Read/Restart level (RD RST (1) B L)
is placed on the bus by the memory, approximately 100 ns after the data is on the bus.

The total data

access time is approximately 350 ns.

After a delay, the memory sets the WR EN (write enable) flop which is ANDed with the WR CON

(write control) flop on a zero state to begin the write portion of the cycle.

The sequence is to rewrite

the data from the memory buffer registers into the same location from which it was read.

In parallel

with the memory data rewrite, the device sends a level called Data Acknowledge (DATA ACK L) which
the memory uses to clear the bus enable register, removing data from the bus.

A Memory Release level

(MRLS L) is sent at the same time as the Data Acknowledge level to tell the memory that the device
has accepted the data,

When the MRLS level has been received and the write enable flop has been

set in the memory, the memory sends to the device an acknowledge called MRLS Acknowledge
(MRLS ACK (1) BL).

The device uses the MRLS ACK level to clear its MRLS level which, in turn,

clears MRLS Acknowledge.

(This sequence occurs in every mode of operation.) The memory cycle

then terminates with the Memory Bus level (M Busy B L) going high.

2.4.2 Clear/Write Cycle
For this mode of operation the WR CON (write control) flop is set, and the memory proceeds to read

the data from the address requested as is cone in a Read/Restore cycle.

The exceptions are that the

data is not loaded into the Memory Buffer, and the bus enable and read/restart flops are not set.

2-8

The

function of this read is to clear the core location for the writing process. In parallel with this, the
device accepts the Address Acknowledge level and places the data to be written into memory on the

bus. To ensure seftling time on the bus, a 50 ns delay occurs before the MRLS level is sent to memory.

In the memory, an MB load pulse is generated with the MRLS level and the data is loaded into the
Memory Buffer register. A Data Acknowledge level is not needed at this time with the MRLS level
because it is only used to clear the bus enable register.

The MRLS level sets the MRLS ACK flop telling the device that the memory has accepted the data, The
MRLS ACK flop ANDed with the Write Enable flop (detecting the termination of the read portion of
this cycle) begins the write portion of this cycle, writing the data into the address requested.
During the write portion, a delayed sequence sets the inhibit flop and the write flop. The inhibit flop

ANDed with the memory buffer bits produces inhibit currents that are applied to each individual bit
plane, depending on the status of the memory buffer bit. A zero bit initiates the current pulse. The
memory cycle then terminates with @ Memory Busy level going high.

2.4.3 Read/Pause/Write Cycle

For this mode of operation both the read control and write control flops are set. The memory proceeds

to read the data from the address requested as in a Read/Restore cycle. When the Read/Restart level is
sent out to the device, the device strobes the data into its registers and proceeds to modify the data,

The device at this time sends to memory a Data Acknowledge level which in turn clears the bus enable
flop taking the memory data off the bus. The MRLS level is not sent at this time. The write enable
flop does not initiate a write portion of the cycle. Instead the memory cycle halts. This is called the
Pause portion of the Read/Pause/Write cycle.

While the memory is in the Pause state, the device modifies the data it has previously read from the
memory and places it back on the bus. In order to provide settling time on the bus, the MRLS level is
sent to the memory approximately 50 ns after the data is on the bus. When the memory receives MRLS,
the modified data is strobed into the memory buffer registers. The write portion of this cycle begins
with the MRLS ACK flop and the Write enable flop set.

The data is written into the same address as

requested at the beginning of this cycle, A Memory Address Hold flop ensures the address will be saved
throughout the cycle. The memory cycle then terminates with a Memory Busy level going high.

The advantage of a Read/Pause/Write cycle is that @ memory word may be read, modified, and rewritten

in one memory cycle. An example of this is when a device wishes to update a current address location
by adding one and restoring it. The flow chart in Figure 2-5 shows these same sequences with a little
more attention to the internal logic flow.
Table 2-2 describes control flop and register nomenclature and major responsibilities.

“understanding the detailed flow chart shown in Figure 2-5.
2-9

It is an aid in

Table 2-2
Control Flops and Register Responsibilities

Abbreviation

Control Flops

Responsibility

or Register

RD Con

Read Control

WR Con

Write Control

Strobed when a request is accepted.
Holds data throughout memory cycle.
Tells memory which one of the three modes
fo pursue.

MA HOLD

Memory Address

Cleared and set when a request is ac-

Hold

cepted.

It holds the memory address in-

formation in the latches throughout the
memory cycle.

MAOQO through MA17

ADR ACK

Memory Address 00

A set of 18 latches which contain the ad-

through 17 (bus address to memory direction only)

dress to be accessed during the memory

Address Acknowledge
(bus signal)

This control flop tells the device that it

cycle.

has accepted the request for memory use
and strobed in the address.

It will clear
itself with the loss of the Memory Request

on the bus.
RDY

Read Y-matrix

This control flop turns on the y-matrix cur~
rents during a read portion of a memory

cycle.

It automatically clears after ap-

proximately 200 ns.
RDX

Read X-matrix

This control flop turns on the x=matrix currents during a read portion of a memory
cycle. I sets 50 ns after the RDY register
to minimize stack noise. It clears at the

same fime the RDY register clears.

MBOO through MB17
PAR MB

Memory Buffer 00
through 17

A set of 18 buffers plus a parity register
are cleared when a request has been ac-

Parity Memory Buffer

cepted.

(bus data, bidirectional)

are directly set from the sense amplifiers.

During a Read/Restore cycle they

During a Clear/Write cycle they are
strobed, accepting data from the memory

bus.
BUS EN

Bus Enable

This control flop enables the data in the

memory buffers, that was read out of mem-~

ory, onto the memory bus. A Data Ack~nowledge from a device clears it.
RD RST

Read/Restart (bus
signal)

This control flop is used to tell the device
that data from memory is stable on the
memory bus. It sets only during a readout
cycle and clears with a Memory Release

Acknowledge .

Table 2-2 (Cont)
Control Flops and Register Responsibilities

Abbreviation

WR EN

Control Flops

Responsibility

~or Register

Write Enable

This control flop is used to set up a defi-

nite delay between the readout of memory
and the rewrite back into memory on a

Read/Restore cycle. It also sets up a net-

work to accept a Memory Release from the

device.

MRLS ACK EN

Memory Release

Acknowledge Enable

This control flop ensures a delay time be-

fore a Memory Release is accepted by the
memory.

This delay is important during a

Clear/Write cycle. It sets with the Write
Enable register setting, and clears on the

next Memory Address Hold register clear

in the next cycle.
MRLS ACK

Memory Release
Acknowledge (bus
signal)

This control flop is used to tell the device
that it has accepted the devices Memory
Release. It will clear itself with the loss
of the Memory Release on the bus.

INH

Inhibit

This control flop enables all the inhibit
drivers only during a write portion of a
memory cycle.
mately 200 ns.

Write

The on-time is approxi-

Not being concerned with stack noise at
this time, this register turns on both the
x= and y-matrices only during the write
portion of the memory cycle. The ontime is approximately 175 ns.

It is de-

layed 25 ns after the Inhibit register to
allow for the slower rise time of the in-

hibit current to skew up with the Write.
BUS DONE

Bus Done

This control flop sets with a sefting of the

Memory Release Acknowledge register. It
denotes the extent of time that the memory bus is busy. The next setting of the
Read X register will clear it.

WR DONE

Write Done

This control flop is used to set up a defi~

nite delay between the write portion of

the memory cycle and the read portion of
the next memory cycle. It sets with the
termination of the write and clears on the
next setting of the Read X register.

Table 2-2 (Cont)

Control Flops and Register Responsibilities
Control Flops

Abbreviation

M BUSY

Responsibility

or Register

This signal, not being a control flop direct-

Memory Busy (bus

ly, is a combination of three control flops

signal)

to tell the device that the memory bus is
busy and any memory tied on this bus will
not accept a Memory Request until the
presently active memory completes its cy=cle. The three control flops that control
this bus signal are Address Acknowledge,
Bus Done, and Write Done. Address Acknowledge is the first control flop to bring
the bus signal low, then when Read X
clears the other two control flops they continue the low signal. The bus signal will
then only come up when both Bus Done and
Write Done control flops are set.

2.5

MEMORY PORT SWITCH

The memory port switch (KP26) establishes the priority between the CPU and IPU. The IPU is given

the higher priority to minimize latency ard prevent data loss to devices on the 1/O bus. The port

switch also provides the synchronizers necessary for switching between the IPU and CPU. De-skewing
is provided by the port switch such that the address is put on the memory data lines 50 to 60 ns before
memory request, and data is put on the lines 50 to 60 ns before memory release. The port switch also
contains the drivers that send control signals to memory .

The memory interface control (KP32), which is an integral part of the port switch, generates the CPU
control signals for memory and control signals for the CPU. The first stage of CPU synchronization
CP MEM REQ HOLD is also shown on KP32.

When the CP is running and the IPU is inactive, the MPX flop is set. Aslong as MPX is set, I/O ACT
cannot be set, and CP ACT may be set. Each time the CP needs memory, the CP MEM REQ HOLD
flop is set. This occurs during TSO1 PHASE 2, CP ACT is set during TS02 PHASE 0. Each event in
the sequence is typically separated by one HS CLOCK or 65 ns. The HS CLOCK is used to provide
the necessary de-skewing of address and request. If however, the IPU needs memory, it ra ises a sync
(DCH SYNC or CLK SYNC) which will cause MPX to be reset. MPX (0) inhibits CP ACT from being
set again. When the CP completes its present memory cycle, it is then prevented from asking for
memory again until the IPU completes its use of memory. MPX is reset before the IPU is ready to
2-12

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Figure 2-5
Detailed Flow Chart

Memory Cycle

2-13

HEO-GI

use memory to provide a minimum wait when it is finally ready. When it is ready, /O MREQ is set,
then 1/O ACT, and then MREQ.

The IPU also uses the high-speed clock of the CPU to provide de-

skewing between address and request.

The control signals to memory have their drivers shown on print KP26.

Each control signal may be

produced by either the CPU or the IPU. The control signals are MREQ, MRLS, DATA ACK, MRD,
and MWR. Read cycle and write cycle flow charts are shown in Figures 2-6 and 2-7.
As previously explained, MRD and/or MWR as well as the address must be on the memory bus 50 to 60
ns before MREQ.

START WRITE.

On print KP32, Memory Interface Control, the CPU generates START READ and

START READ is generated any time the CPU needs to read information from memory
.

This will occur no later than the end of TSO1 PHASE 2.

It may occur as early as TSO1 PHASE 0.

START WRITE is generated by the CPU any time a write into memory is to be performed.

The CPU will

never raise MREQ with both START READ and START WRITE since the CPU is not capable of perform-

ing read/pause/write cycles.

EN CP MEM REQ

HS CLOCK
CP MEM REQ HOLD

%
CP ACT

ADDR-MDL

pr—

MREQ

I 0-HOLD MO

MRD

TS01 PHASE 2

START READ

——

[

0- CP MEM REQ HOLD

TS03

AND

PHASE 3 AND

RD RST

YES

LD MI

0- CP ACT,
MRLS, DATA ACK

AND
FUNCTION

MRLS ACK

I 0—CPMRLS, DATA ACKJ
18-0277
SEE KP26 AND 32

Figure 2-6

Central Processor Read Cycle

2-15

TS01PHASE 2

[ START WRITE

]

[

MWR

]

I EN CP MEM REQ HOLD

HS CLOCK

L CP MEM REQ HOLD

ADDR-MDL

_.é AND

FUNCTION

]

CP ACT

]

[ MREQ

]

TS02@
PHASE 3@

ADR ACK

YES

0-+ MREQ

0 -+ HOLD MO
0—+ CP MEM REQ HOLD
MO-MDL
MRLS

MRLS ACK

]

;

0-MRLS
0-CP ACT

‘

SEE KP26 AND 32

Figure 2-7

15-0278

Central Processor Write Cycle

For CP cycles, after MREQ is issued, the memory replies with ADR ACK.
move the address from the MDL and also clear MREQ.

ADR ACK is issued to re-

In the case of write cycles, it is used to pro-

duce MRLS at the TSO2 PHASE 3 time. On read cycles, the next response from memory is RD RST. This
signifies that data is present on the MDL's.

The CP cannot use the data until TS03 PHASE 3, so the

data is not loaded into the MI register until that time.

At the same time that data is loaded into the

MI, END OF CP CYCLE, MRLS, and DATA ACK are issued signifying the
CP has completed its use of
memory .

For 1/O cycles, control signals from memory are gated with I/O ACT to determine that they are meant
for the IPU.

The chain of events is similar to that of the CP with one exception.

DATA ACK and MRLS simultaneously .
lines.

The CP issues

The IPU issues DATA ACK first to remove memory data from the

Then, when the IPU has placed data on the lines to be written into memory, it issues MRLS.

CHAPTER 3
CENTRAL PROCESSOR
3.1

REGISTERS

This section describes the internal CPU registers of the PDP=15.,

Most of these are 18 bits long; they

appear in prints KPO1 through KP18, one bit of ec:ch. register per page. The exceptions are the é=bit
Instruction Register on KP31 and the 1-=bit Link on KP22.,
in Paragraph 3.2,

3.1.1

The buses mentioned below are described

Refer to the block diagram shown on drawing KP70.

Accumulator (AC)

This is the main data register in the CPU; most instructions reference and/or modify the accumulator.
It is loaded from the D (shift) bus by the LD AC strobe (KP24).

3.1.2

Link (L)

Essentially a high-order extension of the AC, the Link is also strobed by LD AC.

Its input circuitry

(KP22) is similar to the AC shift bus, but is more complex because of its arithmetic fuficfions: it
contains the carry from the high order bit after a TAD, and indicates an arithmetic overflow if set
after an ADD.

The Link may also be cleared, complemented, and tested by OPR instructions.

It is

also used by the extended arithmetic element (EAE) option.

3.1.3

Program Counter (PC)

The Program Counter contains the address in core of the next instruction fo be executed by the PDP-15,
It is loaded from the SUM bus by the LD PC strobes (KP24).

To accommodate the various addressing

modes (see Paragraph 3.5), the PC bits are broken info three groups which are strobed separately .

is possible to load bits 6=17, bits 517, or all bits of the PC.

3.1.4 Memory Input Register (MI)
All words read from memory into the CPU first enter the MI.
Memory Data Lines to be read into the MI.
speed of operation.

The LD MI strobe (see KP32) causes the

This register is made up of clocked set-reset flops for

3.1.5 Memory Output Register (MO)
This register holds all information going from the CPU to the Memory Data Lines.

addresses, as well as data for write cycles.

This includes all

The MO is loaded by LD MO from the SUM bus. The

PC may be loaded directly into the MO by the signal JAM PC to MO (see KP23, KP24).

This causes

a direct set of all MO bits, then clears all MO bits whose corresponding PC bits uré 0.
3.1.6

Operand Address Register (OA)

The OA is used for temporary storage of the operand address, computed for all memory reference instructions.

3.1.7

It is loaded from the SUM bus by the LD OA strobe (see KP24).

Instruction Register (IR)

This is a 6=bit register used to hold the 4-bit instruction code, the indirect bit, and the index bit
(see KP31).

It is looded from MI bits 0-5 by the load IR strobe (see KP31).

Some of the more time~

critical instruction decoding is done directly from the MI, but most is done from the IR after it is

loaded (see KP28, KP29, and KP30).

3.1.8

Index Register (XR)

This register holds a quantity which is added in to the operand address of indexed instructions.

It is

locded from the SHIFT bus by LD XR (see KP24, KP29),

3.1.9

Limit Register

This register holds a quantity which can be tested against the XR by an AXS instruction.

It is loaded

from the SHIFT bus by the LD LR strobe (see KP24, KP29),

3.2

BUS STRUCTURE

Most of the internal data routine of the CPU is handled by five internal buses, designated A, B, C,

D (or SHIFT), and Sum.

Like the registers, these appear on prints KPO1~KP18, one bit of each per

page (see Figure 3-1).

3-2

DATA SWITCH REGISTER —
1/0 BUS DATA ——————
MI M AC

C=0

| saTES

SHIFT COUNTER (EAE) —#

TEST

LR
MQ

C BUS
-C BUS
XR

SUM

GATES

SL6,TTY

»TO MO, PC,MA

CARRY

1/0 ADDRESS ————

ADDRESS SWITCHES —

CARRY IN

LINK

SHIFT
CONTROL

CONTROL

GATES

XR
ACAMI

D OR SHIFT

TO LINK

TO AC,XR,LR
15-0279

Figure 3-1

3.2.1

CPU Bus Structure

C Bus

This bus carries one of seven possible signals, according to the enabling level it receives:

The AC (buffered, called BAC), enabled by the BAC-C signal (see KP19).
The DS register (data switches, see Chapter 8), gated by DS-C (see KP19).
The I/O bus data lines, gated by 1/O BUS = C (see KP19).
The exclusive OR of the MI and the AC, gated by XOR-C (see KP19).

The Step Counter (from the EAE, print KEO3) gated by SC-C (see KP19, KEO4).
The MQ (from the EAE, print KEOT, KE02) gated by MQ-C (see KP19, KE04).
The LR, gated by LR=C (see KP19, KP29).

3.2.2

A Bus

The A bus is one of the inputs to the adder, and carries one of eight possible signals:
d.

The C bus, gated onto the A bus by C~A (see KP19)
The complement of the C bus, gated by =C=A (see KP19)
The XR, gated by the XR-A signals (see KP19). These are split into XR-A 0-2, XR-A 3-5,
and XR=A 6~17 to accommodate the various address modes (see Paragraph 3.5).
The PC, gated by the PC=A signals (see KP19). These signals, too, are divided into
groups of bits to accommodate the various address modes. The groups are 1-2, 3-4, 5,
and 6~17. Bit 0 is never enabled.
The signal L BM UM=-A causes the link, the bank mode flop, and the user mode fiop to
be placed on the high-order three bits of the A bus, and the PC on bits 3=17. This is
used by the JMS and CAL instructions to store the processor status.
The AC, left=shifted 6 places, with TT DATA lines (from KP66) filling in the six low
order bits, gated onto the A bus by SL6~A (see KP19). This is used during TTY hardware
readin.

The I/O ADDRESS lines, gated by 10 ADD-A (see KP19).
The console ADDRESS SWITCH signals (see Paragraph 3.10) gated by ADDR SW-A (see
KP19).
The OA gated by OA-A.

3.2.3

BBus

This bus is the second input to the adder and carries one of four signals, depending on the enabling
level received:
a.

The MI, gated by the MI-B signals (see KP47). To allow for the various addressing modes,
the MI=B signal is split to allow gating of groups of bits, as follows: 0-2, 3-4, 5, 6-8,
and 9-17.

The MI complemented, gated by the ~MI-B signals (see KP19).
~-MI-B 0-8 and -MI-B 9-17.
The XR, gated by the XR-B signals (see KP19).
6-17.

These are split into

These are split into XR-B 0-2, 3-5, and

The logical AND of the MI and the AC (buffered), gated by AND-B (see KP19).

3.2.4

Sum Bus

The Sum bus is the output of the 18-bit adder.

It carries the sum of the A bus and the B bus, plus 1

if the low order CARRY INSERT of the adder is high.
able signal, the other bus being 0.

3-4

Often, only one of the buses will have an en-

3.2.5 Shift Bus (D Bus)

Although the Shift bus is used as input to the XR and LR as well as the AC, its primary purpose is to

implement the various AC rotates and shifts. This is done by gating various shifted positions of the
AC onto the bus, then strobing the bus back into the AC.

The Link input circuitry contains gating

corresponding to the Shift bus gating. The eight Shift bus signals and their enabling levels are as
follows:

Sum bus unshifted, gated by NO SHIFT=D (see KP19). This is used for all unshifted
transfers into the XR, LR, and AC.

AC with halves swapped (bits 0-8 swapped with bits 9=17), gated by SW-D (see KP19).

Sum bus, rotated 1 left (including Link), gated by RAL-D (see KP19).

Sum bus, rotated 1 right (including Link), gated by RAR-D (see KP19).

Sum bus, rotated 2 left, (including Link), gated by RTL=D (see KP19).

Sum bus, rotated 2 right (including Link), gated by RTR=D (see KP19).

Sum bus, shifted 1 left, with ACOO entering Link and MQOO entering AC17, gated by
DIVSHIFT-D (see EAE).

3.3

Sum bus, shifted 1 right, with Link entering AC00, gated by MULSHIFT-D (see EAE).

DATA MANIPULATION HARDWARE

The bus structure described in Paragraph 3.2 not only transports data, but performs the logical AND,
XOR, and complement operations and all shifts,
bus.

The adder performs the addition of the A and B

Normally this is a simple binary add, compatible with two's complement representation for

negative numbers, with the high order carry placed in the Link.
crementing, by forcing a low order carry insert (see KP48).

The adder is also used for all in-

One's complement add uses the same

adder circuits, but any high order carry must be re=inserted at the low end, and the adder must be

‘cllowed to settle a second féme. The link is used to indicate an arithmetic overflow, in which both
operands are of the same sign and the result has the opposite sign (see KP22).
Internally, the adder uses a conditional sum technique for speed.

The 18-bit adder is divided into

three groups of six bits each. Within each group, the addition is performed by two separate é-bit

adders.

One adder assumes a carry in, and the other assumes no carry in.

The low order adder re-

quires about 48 ns to settle, but the second and third groups can operate much faster; when they receive the carry they gate the proper sum, already calculated, to the output.

Thus, total adder

settling time is 82 ns,

Comparison and testing of data is handled in several ways. A high-order carry from the adder, while
incrementing, indicates that the ISZ skip should be taken (see KP23).

3-5

The zero tests for SAD and OPR

are performed by a C-bus zero test circuit (see KP33).

The test portion of the AXS instruction is

carried out by subtracting the LR from the XR (add, with LR complemented and carry insert high) and

skipping if the result is positive (see KP29).

3.4 CONTROL STATE GENERATION
At any given time, the CPU may be in one of five major states: Fetch, Defer, Execute, Increment,
or EAE.

These states each last for about 780 ns and correspond to the approximate time required for

one complete memory cycle.

From one to five of these states are used in the execution of an instruc-

tion, the exact number and sequence depending upon the instruction type.

See Paragraphs 3.7, 3.8

and 3,9 for more information on this subject.

Each major state is made up of three 260-ns time states, designated TSO1, TS02, and TS03.

The only

exception to this occurs during the Execute state of the ADD (one's complement) instruction.

In this

single instance, an exira time state (designated TSO2A) is inserted between time states TS02 and TS03,
thus stretching the Execute cycle to 1040 ns.

This allows extra time to perform the end-around carry

as described in Paragraph 3.3.

Each of the 260 ns time states is further divided into four 65 ns phases, numbered 0~3.

Each phase

corresponds to a complete cycle of a 65 ns pulse generator called the high-speed clock.

The circuitry to produce the major states is shown in KP20; the state, phase, and clock logic are
shown in KP21; a general timing diagram appears in KP79.

Each major state, time state, and phase

is represented by a flip-flop; only one flop in each of the three groups is set at once.

The phase is

changed by the falling edge of the HS CLOCK; the time state changes on the phase 3-phase O transition; the major state changes on the time state TS03-time state TSO1 transition, A 30-ns pulse called
CLOCK is generated during the last half of every phase 3.

This is used to generate most of the register

load strobes.

Because the memory has its own internal timing mechanisms, and the I/O processor has priority over
central processor requests, some provision is needed to stop the control state progression while awaiting
completion of memory service.

This is accomplished by means of the STOP CLK signal (see KP21)

which holds the high-speed clock in the high condition.
cycling resumes.

As soon as this line is released, normal

In this way the processor can be held in time state TS03, phase 3, to await RD RST

(see Chapter 2) during memory read cycles, and the time state TS02, phase 3, to await ADR ACK during
memory writes.

flip-flops.

Other signals inhibit processor state changes by freezing the enabling levels on the

These are described in later paragraphs, along with their uses.

timing involved in a typical 2-cycle central processor operation.

3-6

Table 3-1 indicates the

Table 3-1
Control States for LAC Instruction

Major State

Time State

Phase

Fetch

TS01

0
1

T502

Elapsed Time (ns)

¢S

[ 43

2
3

195
260

390

Execute

325

0
1

520
715
780

TSO1

0
1
2
3

845

910
975
1040

TS02

0
1

1105
1170

2
3

0
1
2
3

585
650

2
3

TSO1

260

3
TSO3

130

1235
1300

1365

1430
1495
1560

3.5 ADDRESSING
3.5.1

Page Mode

The address portion of a PDP-15 instruction is 12 bits long, sufficient to directly address only 4K of
the computer's possible 128K of core memory. The address, therefore, refers to a word in the 4K

memory page in which the program is currently running; PC bits 1=5 are appended to MI bits 6-17 to
form the address sent out on the MO. Bit 0 is not needed. (Refer to Figure 3-2.)

If the instruction is indirect, the address is formed as above, and a deferred address word is obtained

from the location referenced. Bits 0, 1, and 2 of this word are reserved for processor status bits
(Link, Bank Mode, User Mode), which are deposited by JMS or CAL and used later to restore the

CPU to its previous status. Thus, only 15 bits of the deferred word may be used as « final address.
PC bits 1-2 are appended to MI bits 3=17 in this case.

3-7

ENTER FETCH
INSTRUCTION
IN M1

DIRECT (BIT 4=0)

INDIRECT (BIT 4=1)

PC1-5,M06—17 TO OA, MO

READ INDIRECT WORD INTO MI

NOT INDEXED

INDEXED

(BIT5=0)

(BIT5=1)

l
PC1-5,MI6-17

TO0
OA,MO

NOT AUTO

AUTO

PC1-5,M16-17

ENTER INCREMENT STATE

+XR0O-17

REWRITE INDIRECT WORD

TO
OA MO

WITH MIO-17+1

NOT
INDEXED

INDEXED

(BIT 5=0)

(BIT 5=1)

ENTER DEFER
PC1-2,MI13-17
+XRO-17
TO 0A,MO

ENTER DEFER
PC1-2,MI3-17
TO
0A,MO

NOT
INDEXED

(BIT 5=0)

INDEXED

(BIT5=1)

ENTER DEFER
MIO-17+1

ENTER DEFER
MIO-17+1+XR0O-17

TO
0A,MO

0A,MO

15-0280

Figure 3-2

Page (PDP-15) Mode Address Formation

3-8

If the instruction is to be indexed, the XR is added to the final operand address.

In this way the

programmer can reference an address outside the 32K bank in which his program is running.

Since the

MI bits use part of the B bus, and the PC bits use part of the A bus, the XR must be split befween the
two to add properly.

For direct addressing the A bus carries PC 1-5 and XR 6=17, while the B bus

carries XR 0=5 and MI 6-17. For indirect addressing the A bus hold PC 1-2 and XR 3-17, and B
carries XR 0-2 and MI 3-17.

3.5.2

Bank Mode

For compatibility with PDP-9 programs the processor may be put into Bank mode. (Refer to Figure 3-3.)
This eliminates all indexing, and thus the possibility of addressing outside the current 32K. Bit 5 is
used as part of the instruction address field, expanding direct addressing capabilities o 8K.
1-4 are now used, along with MI bits 517,

PC bits

Deferred addresses are handled in the same way os in

Paoge mode.

During jumps, the final address, formed as described, is placed in the PC.

During normal program

incrementation and skips, however, only PC bits 6=17 (517 in Bank mode) are altered. This causes
the program to wrap=around within its own 4K or 8K, when an attempt is made to cross the boundary
without a jump.

ENTER FETCH
INSTRUCTION
IN ML

DIRECT(BIT4=0)

INDIRECT (BIT421)

Pc1-4,Tuz)15-17

PC1-4,M15-17 TO OA, MO

OA, MO

READ INDIRECT WORD INTO MI

NOT AUTO

AUTO

PC1-2 ,MI3-~17

ENTER INCREMENT STATE

REWRITE INDIRECT WORD

OA,MO

WITH MIO-17+1

ENTER DEFER
MIO-17+1
TO
OA ,MO

15-0281

Figure 3-3

Bank (PDP=9) Mode Address Formation

3-9

3.6 MEMORY READ AND WRITE

The following pcfcgraphs describe how a memory read or write cycle relates to CPU states. The
operation of the memory and of the memory port switch are described in Chapter 2.
Each memory cycle occupies exactly one major state.

Refer to Table 3=2.

This state can be either

a read or a write cycle 1; read/pause/write is used only by the I/O in referencing memory.
state TSO1 is used for address calculation.

Time

The information is placed on the A and B buses, goes

through the adder, and is strobed into the MO by the CLOCK signal at the end of TS01.

The memory

is then started to read from or write into this address.

On a read cycle, normal CPU operation continues until phase 3 of the time state TSO3 is reached. If
the memory has not yet returned the RD RST signal, the processor stops its clock at this point and

waits. When RD RST arrives, the data from memory is available on the MDL; it is strobed into the MI
and the clock cycles are resumed.
On a write cycle, time state TS02 is used to gate the data to be written through the adder and onto

the Sum bus.

The clock is stopped (if necessary) at TS02, phase 3 to await ADR ACK from memory.

At this point, the data is strobed into the MO replacing the address, and MRLS is sent to the memory,

allowing it to complete the write.

3.7

The normal clock cycles are resumed.

INSTRUCTION FETCH

Although every instruction begins execution in the Fetch state, this is not the state in which the in-

struction is fetched from memory.

The instruction has already been fetched during the final state

(Execute, Fetch, or Defer) of the previous instruction.

The Fetch state is entered with the instruction

word already in the MI, and with the PC already incremented and pointing to the following instruction.

To accomplish this, the following procedure takes place during the final major state of each instruction.

In time state TSO1, the address of the instruction to be fetched is sent to the MO.

this is done by JAM PC TO MO signal (see Paragraph 3.1, Memory Output Register).

Normally,

If, however,

the SKIP flip-flop (see KP23) is set at this time, or the SAD or OPR SKP signals are high (see KP23),
the PC is incremented by sending it through the adder with a CARRY INSERT (see KP48) and strobed
into the MO and PC.

A memory read cycle is started, as above, and the new instruction is loaded

into the MI at the end of the state.
Meanwhile, during the time state TSO3, the PC is incremented by gating it to the adder, causing a

Carry Insert, and strobing the Sum bus back into the PC.

To provide the wrap~around mentioned in

Paragraph 3.5.2, only PC bits 6=17 (5~17 in Bank Mode) are strobed.
of whether a skip was taken in time state TSO1.

This increment occurs regardless

3.8

INSTRUCTION OPERATION DETAILS

Paragraphs 3.1 through 3.7 describe the data handling structures and basic operation necessary to
implement the PDP-15 instructions.

The following paragraphs describe the sequence in which these

operations occur for each instruction.

Detailed information is provided in Tables 3=3 and 3-4.

Supplementary explanations are included in the text.

All descriptions in this paragraph assume direct (non-deferred) addressing and Page (or PDP-15) Mode.
Indirect and auto-incrementing address modes are described in Paragraph 3.9.

For Bank (or PDP=9)

Mode, convert all references to PC 1-5, MI 6=17 to PC 1-4, MI 5-17, and remember that no indexing

is possible.
All statements of the form "PC TO OA, MO" mean that the PC is enabled to the bus structure during

the entire time state, and the output of the adder is strobed into the OA and MO at CLOCK time
(end of phase 3).

3.8.1

All incrementing uses the adder with a carry inserted (see Paragraph 3.3).

Read Group (LAC, ADD, TAD, AND, XOR)

These instructions use a Fetch state, in which the opef'ond is brought info the MI, and an Execute
state, in which the next instruction is fetched.

During time state TS02 of Execute, the data is sent

through the adder, operated on appropriately (see Paragraph 3.3), and strobed into the AC.

As noted

in Paragraph 3.3, ADD requires an extra time state (TS02A) to complete its end-around-carry.

3.8.2

DAC and DZM

These instructions consist of a Fetch state, in which the AC or 0 is written into memory, and an
Execute state, in which the next instruction is fetched.

3.8.3

JMP

JMP uses only the Fetch state.

During time state TSO1, the address is formed and strobed into the PC;

at the same time, it is sent o the MO and is used as the address for an instruction fetch.

3.8.4

JMS and CAL

These instructions begin with a Fetch state, in which the Link, Bank mode, User mode, and PC bits
3-17 are written into memory.

For the JMS, the address is formed in the usual way from PC 1-5 and

MI 6-17, and sent to the OA and MO.

For CAL, however, a constant address of 20 must be generated.

This is done by enabling the =C=A for bit 13 only, and strobing the OA and MO.

3-11

Table 3-2

CPU/Memory Interaction

Time State | Phaose

Read Cycle

Write Cycle

PC 1-5 -A BUS
MEM IN 6-17 - B BUS

Ml
A

|
2

START READ, MRD
1 -CP MEM REQ HOLD

START WRITE , MWR

1 -CPACT

1 +CPACT

LD MO, OA

MO - MDL

1 -CP MEM REQ HOLD

TS02

MO -~MDL

M REQ

AC -C BUS

ADR ACK (Occurs sometime after M REQ determined
0 =M REQ

by memory)

0 +~CP MEM REQ HOLD

STOP CLK

( Wait for ADR ACK)

LD MO

(Change MO from address to dafa)

ADR ACK

0 ~HOLD MO

0 -HOLD MO
0 -MO -MDL

1 -CP MRLS
MRLS

0
1

MRLS ACK

0 -CP MRLS, MRLS
0 -CP ACT
0 ~MO -MDL

703

1 -HOLD MO
3

STOP CLK

(Wait for RD RST)

RD RST
LD MEM IN
END OF CP CYCLE
0 -CP ACT

1 ~HOLD MO
1 -CP MRLS
MRLS, DATA ACK

MRLS ACK
0 -CP MRLS, MRLS, DATA ACK

TS01

2
3

3-12

Table 3-3
Instruction Operation

Instruc~

Fetch

TS02

Execute

tion

TSO1

TS03

TSO1

LAC

PC 1-5,MI 6-17

PC JAM to MO.

(+XR if indexed)

Start Read.

TS02

TS03

MI to AC

PC + 1 to PC

MI + AC to AC
TS02A: AC end

|PC+1 to PC

to OA, MO.

Start Read.

ADD

TAD

PC1-5, MI 6~17,
(+XR if indexed)

PC JAM to MO.
Start Read.

to OA, MO.

around carry to

Start Read.

PC 1-5, MI 6~17

PC JAM to MO.

(+XR if indexed)

Start Read.

MI + AC to AC

PC +1 to PC

MIAAC to AC

|PC+1to PC

MI % AC to AC

|PC + 1to PC

to OA, MO.

Start Read
AND

PC 1-5, MI 6-17

PC JAM to MO.

(+XR if indexed)

Start Read.

to OA, MO.
Start Read.

EOR

PC 1-5, MI 6-17

PC JAM to MO.

(+XR if indexed)

Start Read.

to OA, MO,

Start Read.

DAC

PC 1-5, M1 6-17

AC to MO

PC JAM to MO,

PC +1to PC

0 to MO

PC JAM to MO.

PC +1to PC

PC + 1 to PC

(+XR if indexed)
to OA, MO.
Start Write.
DZM

PC 1-5, MI 6~-17

(+XR if indexed)
to OA, MO

Start Write
JMP

PC 1-5, MI 6~17

PC + 1 to PC

(+XR if indexed)
to OA, MO, PC
Start Read.

JMS

PC 1-5, MI 6~17

L,BM,UM,PC 3=-17

OA + 1 to MO, PC

(+XR if indexed)

to MO.

Start Read

20 to OA, MO

L,BM,UM,PC 3-17

OA + 1 to MO, PC

Start Write

to MO.

Stort Read

to OA, MO,
Start Write.

CAL

SAD

PC 1-5, MI 6-17
(+XR if indexed)
to MO, OA

C=0:

MI XOR AC to C BUS.
JAM PC to MO

C#0:

PC + 1 to MO,

Start Read.

PC.

Start Read.

PC + 1 to PC

PC +1to PC

Table 3=-3 (Cont)
Instruction Operation

Instruc—

TS01

Hon

OPR

Fetch

T503

TS02

OPR SKIP: PC+1 to | (CLR LINK)

TS01

PC + 1 to PC

MO,PC | Operate on AC, L
OPR SKIP: PC JAM
to MO
Start Read

(CLR AQ)

LAW | PC JAM to MO

MI ta AC

PC +1 to PC

Start Read

IOT

Stop Run

| IOT Request

Start Run on IOT

0 to AC if MI14=1
No memory cycle.

SKIP: PC+1 to MO,
PC
SKIP: PC JAM to
MO

Start Read.

No memory cycle. | Transfer, ADD to
AC, LR, XR

Done if AXS, TEST.
XR=LR: 1-SKIP

XR<LR: O0-SKIP

|SKIP: PC+1 to MO,
__ PC
SKIP: PC JAM to
MO
Start Read.

0to IR (CAL)
I/O Address (<0)

OA + 1 to MO, PC
Start Read.

L,BM,UM,PC3-17
to MO

to OA, MO
Start Write

APl

Execute operand as

1 to IROO (XCT)
I/O address to OA,

instruction

Start Read.

3-14

Execute

T502

7503

An Execute state follows in which the OA + 1 is loaded into the MO and PC, and an instruction
fetch is carried out from this location.

3.8.5

ISZ

The ISZ instruction uses three major states; Fetch, Increment, and Execute. (Refer to Table 3-4.) The
Fetch cycle reads an operand in the usual manner. The Increment cycle adds 1 and rewrites the word
in memory. (Read/Pause/Write is not used.) While the operand is being incremented (in time state

TS02), the high-order carry output is checked, and if a carry occurs the SKIP flop (KP23) is set. This
implements the skip-on-zero. The Execute state is an instruction fetch, using the PC or the PC + 1
according to the state of SKIP.

Table 3-4
ISZ Instruction Operation

Major State

Fetch

Time State

TSOT

Operation

PC 1-5, MI 6-17
(+XR if indexed) to
MO, OA
Start Read.

TS02
TSO3

Increment

TSO1

OA to MO
Start Write

TS02

MI + 1 to MO
If carry out, set SKIP

TS03

Execute

TS01

SKIP: PC JAM to MO
SKIP: PC + 1 to MO,
PC
Start Read.

TS02

TSO3

3.8.6

SAD

The Fetch cycle of SAD brings in an operand.

This is followed by an Execute cycle in which the

comparison, skipping, ond instruction fetch are carried out.

During time state TSO1 of execute, the

XOR of the AC and the MI (operand) is gated onto the C bus.

If the C=0 circuitry (see KP33) shows

a perfect match, PC JAM to MO is used and the instruction fetch occurs with no skip.
PC is incremented before the fetch.

If C #0, the

This incrementation is set up using the A bus, so it does not inter-

fere with the comparison on the C bus.

3.8.7 XCT

This instruction goes through a Fetch state, getting an operand in the usual manner, and then enters
the Fetch state a second time.

The operand, now in the MI, is treated exactly as if it had been en-

countered in normal program flow as an instruction that was fetched into the MI by a previous instruc-

tion.

All of the instruction states will occur, and the PC will be incremented or altered as usual .

Refer to Table 3-5.

Table 3=5
XCT Instruction Operation

Major State

Fetch

Time State

Operation

TS01

PC 1-5, MI 6-17
(+XR if indexed) to MO,
OA.
Start Read.

T502
TS03

Fetch

TSO1

Execute operand as
instruction

T502

TS03

3.8.8

OPR

This instruction group uses a single Fetch state for its execution.

In time state TSO1, the OPR SKIP

logic (see KP23) determines whether a skip will take place, and the fetch for the next instruction is
initiated.

The actual operation on the Link and AC takes place in TS02, by setting up the appropriate

3-16

buses and strobing the output into the Link and AC.

The only exceptions to this are the clear

operations which take place during TSO1; CLOCK, for the AC; and TS02, phase 1, for the Link.

3.8.9

LAW

LAW consists of a single Fetch state, used to fetch the following instruction. During TS02, the LAW
instruction (still in the MI) is loaded into the AC.

3.8.10

IOT

The IOT begins with o Fetch state, in which no memory cycle occurs.

1OT REQUEST is raised,

activating the 1/O processor (see Chapter 4). If bit 14 of the MI is set, the AC is cleared at clock
time of TSO1.

The Fetch state continues until, at the end of TS03, phase 2, the RUN flop (KP21) is

dropped, stopping all CPU phase transitions.

By this mechanism, the CPU waits for the IOT DONE

signal (see KP55) which sets RUN. The I/O processor, in the meantime, may have strobed the I/O
Bus data lines into the AC, and may have set the SKIP flop.

An Execute state follows Fetch, and

the next instruction is brought in, controlled by SKIP.

3.8.11

Index Group (XG)

These instructions consist of a Fetch state, with no memory operation, followed by a standard Execute
state instruction fetch.

In time state TS02 of Fetch, the transfer (PAX, PAL, PXA, PXL, PLA, PLX); clear (CLX, CLR); or
add (AXR, AAC, AXYS) takes place.

The add gates the AC or XR onto the A bus, and MI 9-17 onto

the B bus.

If MIbit 2 is a 1, the number is negative and bits 0=8 must be filled with the 1s for proper

addition.

This is done by activating both MI=B 0-8 and =MI~B 0-~8 simultaneously during the addition

(see KP19).

Time state TSO3 of Fetch is used only by the AXS, for comparing the XR to the LR.

The XR is gated

onto the B bus; the two's complement negative of the LR is added to it by gating the LR to the C bus,
-C to the A, and raising carry in.

The high order carry output, along with the XR and LR signs,

indicates whether SKIP should be set (see KP29).

Like signs with a carry or opposite signs with no

carry indicate that XR > LR and a SKIP is called for.
Execute state.

Skip, of course, takes effect in the following

3.8.12

Interrupts (APl and PI)

While API and PI are not properly instructions, they behave in very much the same manner once they

are recognized. The recognition sequence is described in Chapter 6 for API and Chapter 4 for PI.
Whenever the INT ACK + ST signal is asserted and the CPU enters an instruction Fetch cycle, the
interrupt begins. An instruction fetch is allowed to take place, but since the instruction will not be

used at this time, the PC increment is disabled (KP24).

Upon entering the Fetch state, the interrupt

takes full precedence over the instruction in the MI.
~

If the interrupt is a PI, the 00 code (CAL) is forced into the IR.

From this point, execution is identi-

cal to a CAL, except the /O Address Lines are used to provide the operand address, instead of the
constant 20.

These lines will always give a 0 on PI requests.

Thus the L, BM UM and PC 3-17 are

stored in location 0 and the next instruction is fetched from location 1.

The API forces an XCT code (40) into the IR, and proceeds as an XCT would, except that the address

of the operand is read from the I/O Address Lines instead of the MI. The device requesting the API
must, when acknowledged, place the appropriate interrupt address on these lines.

tion (in an address peculiar to the device) is executed.

Thus, some instruc-

This will usually be a JMS to the interrupt

handler.

3.9

DEFER AND AUTO-INCREMENT

If bit 4 of any memory reference instruction is set, that instruction is to use deferred (or indirect)
addressing.

Instead of the usual Fetch state, the instruction begins with Fetch and Defer states, as

shown in Table 3-6.
address word.

The Fetch state is always a memory read, which brings in the pointer or indirect

The Defer state is almost identical to the Fetch state of the same instruction in non=-

deferred mode; it brings in or writes out the operand, just as Fetch would have.
is that MI 3~17 are used instead of MI 5-17.

addressed word is obtained.

The only difference

In the Defer state, indexing occurs after the indirect=-

The remaining states of the instruction proceed as though in non-deferred

mode.

If a deferred instruction has an address of 10-17 (octal), regardless of the PC contents, the instruction
is to use Auto~Increment mode addressing.

Refer to Table 3<7.

The contents of the addressed word,

absolute 000010-000017, are first incremented, then used as a deferred address.

This is accomplished

by replacing the normal Fetch state with the Fetch, Increment, Defer sequence shown in the table.
This sequence is caused by the circuitry on KP33 which sets the AUTO flop during TSO1. The Fetch
state is used to read the indirect word from memory.

is assured by gating only MO 6~17 to the MDL.

Use of locations 10=17 on the lowest core page

In the Increment state, the pointer is incremented

3-18

Table 3-6
Deferred Addressing Operation

Maijor State

Time State

Fetch

TSO1

Operation

PC 1=5, ML 6=17 to OA,
MO

Start Read
T502

TS03

Defer

TSO1

PC 1-2, MI 3-17
(+XR if indexed) to OA,
MO
Start Read or Write

T502

Identical to operation
specified for non=Defer,

Fetch, TSO2.

TS03

Identical to operation
specified for non-Defer,

Fetch, TSO3.

and re=written.

In the Defer state the original pointer plus one is used as the address and the operand

is either read or written into, as it would be in the Fetch state of a normal mode instruction.
CAL can be deferred, but not auto~incremented.
used as the final address.

In deferred mode,

the contents of location 20 are

Operation is identical to that shown in the table, except that an address

of 20 is forced in TSO1 of Fetch.

In a JMP deferred or auto, the Defer State is the final state of the instruction, and thus fetches not an
operand, but the next instruction.

In TSO1 of Defer, the final address is strobed into the PC as well

as the OA and MO.

ISZ auto uses the Increment state twice; the major state sequence is Fetch, Increment, Defer, Increment, Execute.

The first increment is for rewriting the address pointer, while the second is for the

normal increment of the operand.

The skip=on=zero circuit can only set SKIP during the second

Increment state, while AUTO is zero.
All 18 bits of the auto-increment register are used as an address. This provides another method of addressing more than 32K of core memory.

3-19

Table 3-7
Auto-Increment Operation

Major State

Fetch

Time State

Operation

TS01

PC 1-5, MI 6=17 to OA,MO
1 -=AUTO
Start Read

(MO 6-17 to MDL)
7502

TS03

Increment

TSO1

OA to MO
Start Write

(MO 6-17 to MDL)

TS02

MI +1 to MO

TS03

Defer

TS01

MI 0-17 + 1
(+XR if indexed) to OA, MO
Start Read or Write

TS02

Identical to non-Defer,
Fetch, TS02

TS03

Identical to non=Defer
Fetch, TSO3
0 -AUTO

3.10 CONSOLE OPERATION

3.10.1

Console Cable Multiplexer

Only two 18-conductor flexprint cables are used between the CPU and the console.

These are multi-

plexed six ways by a free-running 36 kHz clock and a modulo =6 counter (see KP45, KP46). Three
lines of the cable carry the state identification (console zero=high order), and 24 of the others com-

prise the I bus which carries information to or from the console, depending on the console state. The
I bus assignments and timing are shown in KP72,

During console states 0, 1, and 2, various internal CPU signals are placed on the I bus, and three
different sets of console lights are sequentially enabled to display this information.

Each light, when

on, is only enabled for one sixth of each 333 ps console cycle, but brightness is maintained by using

3-20

30 volts instead of the normal 18 volts to drive the lamps.

Console state 0 and 2 display permanently

assigned CPU signals; state 1 displays one of 24 registers, as selected by the rotary switch on the
console.

Console states 3, 4, and 5 are used to read the status of the various console switches into the CPU.
In general , these are read into active registers so that they can be referenced by the CPU at any time.
The rotary switch status register is shown in KP44.

shown in KP45 and KP46.
through KP18.

The various key functions are stored in the flops

The data switch register appears with the main CPU registers in KPO1

The address switches are not stored in a register; whenever the CPU references these

switches it must wait for console state 4 (CF pulse).

3.10.2

Key Functions

The control flow of the various console key functions (start, continue, execute, examine, and deposit)
is shown in KP73.

This paragraph provides additional explanation.

Most of the associated logic ap-

pears in KP34.

The Stop switch causes the RUN flop (see KP21) to drop as soon as the CPU enters phase 3, time state

TS03, of the final major state of an instruction. (Set Fetch is high.) The CPU is effectively frozen
at the end of an instruction, with the next instruction in the MI, but with the PC not yet incremented.
Once the CPU is stopped, deposits and examines may be performed.

These start RUN, go through a

forced Fetch state in which a memory word is read or written, then drop RUN again, under control

of the STOP TS RUN flop (see KP34).

Executes operate similarly, using a forced fetch to load the

data switches into the MI, then executing this as an instruction.

RUN is stopped after this operation

by the XSW IN PROG flop (see KP34),
START and CONTINUE (when stopped at TS03, Set Fetch) both use a forced Fetch state to read in the

next instruction. START uses the Address Switches as an address, while CONTINUE uses the PC. The
PC is incremented, and the CPU resumes normal operation.

If CONTINUE is used and the CPU is not

in TSO3 of a Set Fetch state, RUN is simply raised and operation resumed.
Single Instruction, Single Step, and Single Time operate by dropping RUN at the appropriate intervals

(see KP21).

3.11

READ IN

To load binary tapes or bootstraps (refer to Figure 3-4), the PDP-15 uses a hardware read=-in function,

which loads core from either the Teletype or the high=speed paper-tape reader, depending on an

3-21

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internal jumper wire shown in KP66. Each frame of the tape carries data in bits 1-6; three consecutive
frames form an 18-bit word for storage. Bit 7, if punched, causes the last word read to be executed
as an instruction, terminating the read. Bit 8 is always punched. The read=in logic is shown in KP66
and KP49; the flow diagram is in KP75.

In Teletype read=in operation, the address switches are first read into the OA and MO. These give

the core location where loading is to begin. The time states are allowed to run, but are stopped by
STOP TS RUN (see KP34) when TS03 is reached. Meanwhile, the Teletype reader has been started by
the READ IN START signal (KP66), and-eventually this returns with a character. This causes an IOP2
pulse which stores the character in the AC via ALS6 (see Paragraph 3.2.2, A bus), restarts the time

states, and increments the character counter (see KP66). When three such characters have been brought
in, they are written into memory, the OA is incremented, and the process continues. When a bit 7
punch is detected, the AC is strobed into the MI instead of being written into memory, all the readin enables are dropped, and the MI is executed like an instruction. Usually this will be a jump to
the start of the program.

Operation using the high-speed reader is quite similar to Teletype read-in. The principal difference

is that the reader interface, instead of the CPU, packs the three 6-bit characters into a word, so each
cycle after the first is a store and read cycle. The character counter and the ALS6 logic is not needed.

3-23

CHAPTER 4
1/0 PROCESSOR
4.1 KD15 INPUT/OUTPUT PROCESSOR
The 1/O processor coordinates data transfer between the central processor and peripheral devices and
also between core memory and peripheral devices.

Data transfer between the CPU and peripheral

devices is called program control transfer and is implemented by the input/output transfer (IOT) instructions. Data transfer between core memory and peripheral devices is accomplished by a request/
grant priority scheme and is referred to as the data channel.

Table 4-1 summarizes the PDP-15

input/output facilities.
Program control transfers occur as a result of the IOT instruction execution.

These instructions, con-

tained in the body of the main program or in appropriate subroutines, are microcoded to effect response

of a specific device interfaced to the 1/O bus system. The microcoding includes the issue of a unique
device selection code and appropriate processor generated pulses to initiate device operations such as
transmitting data from the device to the central processor, or from the processor to the device. All

program control transfers are executed through the accumulator in 18-bit words.

This portion of the

I/O processor also contains facilities for skipping on device flags and interrupts which cause a break
in the normal flow of central processor operations.

The data channel facility provides for high=speed transfer of data in blocks between peripherals and

system core memory.

Since the 1/O processor and central processor of the PDP=15 are asynchronous,

a data channel transfer request raises an I/O memory request, which is granted and transmitted to mem=ory at the conclusion of the current central processor memory reference in progress.

These requests

will continue to take priority over the central processor until the transfer is completed.

The types of

transfers available to the data channel facility are single cycle input and output transfers, multicycle

input and output transfers, add to memory transfers, and increment memory transfers. The 1/O processor
consists of five sections:
Timing Generator

Request Synchronizer
IOT Control Logic

I/0 Bus Control Logic
Data Channel

Table 4-1

Summary of PDP-15 Input/Output Facilities

Remarks

Facility

Data Transfers To/From Memory
Multi~Cycle Data Channel Input

Used to transfer 18-bit data words directly to core
memory at high speed (250 kHz).

Multi=Cycle Data Channel Output

Used to transfer data directly from memory in 18-bit
words. Maximum speed is 188 kHz.

Add to Memory

Used to add the contents of a device register to the
contents of a specified core location in 18-bit words.
Maximum speed is 188 kHz.

This facility allows an external device to increment
the content of a core location by 1. Maximum speed

Increment Memory

is 333 kHz.

Single~Cycle Data Channel Output

With this facility a device can transfer a burst of
data from core memory at 1 mHz in 18-bit words.

Single=Cycle Data Channel Input

Used to transfer a burst of data from a device to core
memory at 1 mHz per 18-bit word.

Data Transfers To/From CPU
Addressable 1/0O Bus

With this facility, devices can transfer data in 18-bit
words to or from the ceniral processor. A typical
rate is one transfer every 200 ps.
Command and Status Transfers

Addressable 1/O Bus

Commana and status information can be transferred to
or from the CPU in the same manner as ordinary data.

Read Status

This is a special facility designed to allow the user to
monitfor all vital flags in the system. Each device is
assigned a bit for its flag(s), which is read onto the

addressable /O bus and into the CPU when the Read

Status command is given. No two devices should use
the same bit.
Skip

The addressable /O bus allows the computer to test
the status of a flag (typically) by issuing a pulse which
will echo if the addressed flag is up. Every flag that
posts a program interrupt must be identifiable by the
skip facility.
Interrupts

Program Interrupt

All devices share a common program interrupt line.
When a device posts an interrupt the computer is
forced to location 0, bank O, and then on to a service
routine designed to identify the requesting device
using the skip facility.

4-2

Table 4=1 (Cont)

Summary of PDP=15 Input/Output Facilities
Remarks

Facility
Interrupts (Cont)

This facility reduces the time to service a requesting

Automatic Priority Interrupt

device and establishes a priority among devices so
that important interrupts can be handled quickly
and without interference.

4.2 TIMING GENERATOR

The timing for the 1/O processor is controlled by an M401 clock located on KP51 which runs freely,
with the exception of waiting for memory, on multicycle and single cycle output transfers. This clock
steps a 2-bit counter which is decoded on KP55 into 4 times called TIME 1, TIME 2, TIME 3 and

TIME 4. This is shown in Figure 4~1. TIME 1 is called I/O SYNC, and is used to synchronize de~
vices on the 1/O bus to the I/O processor. The frequency of the I/O clock is 4 MHz. The overall

frequency of the 1/O processor is 1 MHz and therefore the 1/O clock on KP51, N21-E2 should be

set so that pulses are 250 ns apart.

..|

|-—zso NS

L L L LMLUt
woroesn [L
500 NS

T1(KP51)

mwerzs
) e
[
(KP55)

TIME

[

=—-r-== [

LT
1

LT
4

L
2

15-0282

Figure 41

Basic I/O Timing
4-3

4.3

REQUEST SYNCHRONIZATION

A priority structure is set up in the PDP-15 as follows:

Data channel request

Clock requests

Automatic priority interrupt requests

Program interrupt request

Main program

In order to establish these priorities a two stage synchronizer is provided in the I/O processor as shown

in KP51.

Each priority contains two stages of synchronization.

CLOCK, API, PI, and IOT flops on KP51.

flops are clocked at TIME 4.

The first stage consists of the DCH,

The various requests for activity on the data input to these

Any one or all of these flops may become set at this time.

250 ns later,

at TIME 1, a clock pulse is provided to the sync flops immediately above each of the first stage synchro-

nizer flops, and sets one of these flops.

During the previous 250 ns, if a higher priority request had

been set into one of the first stage flops, a clear would have been transmitted to all lower request flops

and, therefore, only one of the second stage synchronizer flops would become set.
sync flop will allow highest priority request activity to proceed.

The setting of the

Once one of the lower priority sync

flops is set, such os in program control transfers, it will remain set until the transfer is completed.

4.4

10T

The 10T instruction is a command from the central processor to transfer data from the central processor

(accumulator) to the device or to read data back from the device into the accumulator of the central
processor.

The instruction format in Figure 4-2 consists of the instruction code; a é-bit device select

and a 2-bit subdevice select code which are put onto the 1/0 bus to designate the device with which

the processor wishes to communicate; a clear the AC bit which if set, will cause the clearing of the

accumulator; and three I/O pulses; any one or all of which may be given in a single IOT instruction.

GENERATE

OPERATION CODF

70g

A
0

{

DEVICE

CLEAR

SELECTION

avs
3

A
6

TM
9

o011

r
|12

(13

1I0P 2

PULSE

—

(14|15

)]

|17

SUB-DEVICE

GENERATE

SELECTION

IOP
4

PULSE

IOP{

PULSE

15-0203

Figure 4-2

1OT Instruction Format

4-4

The general purpose of these pulses is as follows: IOP 1 transmits data to the device, tests the device
flag, and causes the program to skip the next sequential instruction; IOP 2 transmits data to or from

the device via the accumulator; IOP 4 transmits data to the device from the accumulator.

The 10T instruction requires the operation of both central processor and the 1/O processor. The
central processor, upon detecting the IOT instruction, sets the 10T request flip-flop on KP35.

MI bit 14 is set, the AC will be cleared.

1If

When the processor reaches FETCH, TS03, and

CLOCK, it halts and waits for the 1/O processor to finish its execution and respond with IOT
DONE.

The 1/O processor has to synchronize the IOT on KP51 with the other priority requests. Upon synchro-

nization, the information in the accumulator is enabled to I/O bus lines along with the device select
and subdevice select bits from MI bits 6 to 13.

IOP 1 is enabled on the bus if bit 17 in the MI is set.

IOP 1 in the 1/O processor lasts for 1 ps. IOP 1 on the bus is 750 ns long. At the end of IOP 1, if
neither bit 15 nor 16 in the MI is set, IOT DONE is generated.

Otherwise, IOP 2 in the /O processor

is set. If bit 16 in the MI is set, IOP 2 is enabled on the 1/O bus for 750 ns.r If READ REQUEST is
true at this time the AC is disabled from the I/O bus. 750 ns after IOP 2 is placed on the bus, the AC
is strobed and information that was on the I/O bus is placed in the accumulator. At the end of IOP 2
if bit 15 of the MI is not set, an IOT DONE is generated.

onto the bus for 500 ns.

If it is set, IOP 4 is set.

IOP 4 is enabled

After this time, an IOT DONE is generated; the IOT and IOT SYNC flops on

KP51 are cleared out and the central processor is restarted. Figure 4-3 shows the 10T instruction
timing, giving the synchronization time between central processor and /O processor. An IOT flow
diagram is in Figure 4-4,

4,5 I/O BUS

The 1/O bus cables are shown in Figure 4=5. The 1I/O bus signals are described in Table 4-2.

4.6 DATA CHANNEL FACILITY (DCH)
Refer to Figure 4=6.

The hardware to implement the memory to peripheral device data transfer in=

cludes: a bus buffer for temporary storage (I/O Buffer 0-17, KD04, KDO5); a data storage register,
an input mixer and adder used to transfer information from the devices to memory and from memory to

the devices (DSR KDO1, KD02, KDO03); priority logic for the synchronization of requests (KP51) and
generation of GRANT (KD06); and DCH conirol logic (KD04, KDO5, and KDO06).

|e—

0-60NS MAX—»|

CP RUN
-

|es0ONS

- [|e-160NS MAX.

800 Ns——|\ e

EXECUTE

10T RECQ.

10T

10T SYNC

j«

[T~

——‘\l-—,o TO 1,SEC

—|

-»

10P 1

fe—250 NS

jo- 1 pSEC

)
/

10P 2

|
|

10P 4

<~
-

[«

|«———500NS

]

10T DONE

|
|

]

AC ON BUS

N SR

]
15-0176

Figure 4=3

IOT Instruction Timing

Data channel devices on the I/O bus are initialized by IOT commands, and the data transfer process

is initiated also by IOT. After initialization, the device, when ready for a transfer, raises its flag,
which is then synchronized to the I/O processor. The device then transfers the data through the /'O
processor to or from memory .

10T REQ

JKPS

SET 10T F/F

TIME 4 I

I KPS1

TIME 4

YES
KP23

ANY

PRIORITY

[
l

EN 1/O LINES
AC~1/O BUS

[

1->SKIP

KP23

0-10T WIDTH

KPS5

10P 1 OFF 1/O BUSJ

KPS0

YES

TIME 1

YES

HIGHER

CLR IOT F/F

0+10P 1

KPS1

1-10P 2

J KPS5

2(2)

] KPS52,53

Mi 611-DS 05

KPS0

MI 12-13-SD0-1

KPS5

10P4~1/O BUS

[

o~10P4

SET 10T SYNC

10P4 OFF 1/0 BUS I KPS0

| KP50

[

0~EN 1/0 LINES

READ

REQ

CLEAR AC

I KP28

DEV TRANS

SET 10P 1
10P1-1
JOT WIDTH-1

TIME 4

10T

DON
DONE

| KPS5

l KPS5

0-10T

0-10T SYNC

] KP50

[ AC OFFL1/0 BUS I KP52,53

TIME 3

KPS0

YES

] KP51

10P2 ON BUS

KP50

KPS5

1-10T WIDTH

]

l
TIME 1

KPS1

1+ 10P4

YES

1
TIME

0~ 10P2

KP51

START RUNv J KP34

PROCESSOR THEN PROCEEDS
TO EXECUTE, TIME STATE 1

KPS51
KPS5

[

EN 10P2

J KPS5

AC~C BUS

kP19

1/0 BUS-C BUS
C BUS-A BUS
NO SHIFT-D BUS

TIME &
YES

{OP 1 ON I/O BUS
1

] KPS0

[

LOAD AC

0-10T WIDTH
10P2 OFF 1/O BUS

KP24

I KPS5
KPS0,52,53

AC ON 1/0 BUS

15-0293

Figure 4-4

10T Flow Diagram

4-7

10 BUS 0OL —}—@

IO SYNCH——@

@—f—— 10 BUS 05L

E2
@——— 10 BUS 0L
H2

10 BUS 03, —}—®

@—f—— IO BUS 12L

10 BUS 02L —}—0
HI

D1
10 8US 01 ——8
El

1OP

@—]}——10BUS 11L
K2

10 BUS 0O6L ——®

10 BUS 07L —+—®

10 BUS 08t —f—@
IORUNH—}—e
DATA OFLOH —}—e

®——— 10 BUS 151

RDRQ L ——®

@—1— 10 BUS T6L

RD STATUSH—}®

@&—}— 10 BUS 17L

IOPWRCIRH—1—®

@—f—— DS5H
S2

@—1— SING CYRQL

@—1—spoH

@—1—— SDTH

@—f— API2RQL
@—— API2GRH

@&—]—10 ADDR 11L

+1-CAINHL —1—®

@—}— API2ENH

@—}—— 10 ADDR 12L

APIORQL —f—@

@—1— API3RQL

10 ADDR 13L
@—}——

APIOGRH——®

10 ADDR 14L
@—f——

APLOENH—1—®

@—}—— 10 ADDR 15L

APLIRQL —{—®

@—f—— 10 ADDR 16L

APL1GRH—1—®

@——— 1O ADDR 17L

API1ENH—}—0

D1
El

CABLE

}

H2
K2

noom2

10 ADDR 08 L —}—@

WRRQL —}—

10 ADDR 07 L —}—

@——— DS3H

INCMBL —}—0

10 ADDR 06 L ——@

@&———DS2H
K2

10 ADDR 09L
@———

10 ADDR 05 L —}—®

@—F——DSO0H

E2
@—]—Ds1H
H2

@—1——10 ADDR 10L

10 ADDR 04 L —}—@

PROG INTRQ L —4—®

1O ADDR 03 L —}—®

Jom2
&—1—Ds4H
SKIPRQL —}—e

@—]—— 10 BUS 14L

10 OFLOH —4—®

2H—f—8
HT

0P 4H —-1—@

Jom2
@—}—— 10 BUS 13L
10 BUS 04L ——@

10 BUS 05L —}—®

D1
1H—}-o
El

@—}—— API3GRH

@—1— APIJEN

@—— DCHRQL

@—}—— DCHGRH

@—}— DCHENH

CABLE 2

15-0325

Figure 4=5

1/O Bus Cables

4-9

Table 4-2

1I/O Bus Signal Functions

Signal

Mnemonic

API O

Connector

| Pin Number

2BL1

ENH

Signal Definition

This enable signal, one of four in
the API system, is a dc level orig-

Signal Function

Each device can post a request to
its API level only if the incoming

inating in the I/O Processor and
API EN level is true. By posting
daisy chained from device to device | a request the device immediately
on the same level. The M104 logic
inhibits all controllers below it on
in each controller can interrupt this
the bus. In this way priorities on
level, cutting the level off all de=
each level are established when
vices that follow it on the bus. A
devices request simultaneously.

device receives it as API 0 EN IN H

and transmits it as API 0 EN OUT H.

API 1

2B3S1

Same as AP1 0 EN H

Same as API 0 EN

2BH2

Same as API 0 EN H

2BP2

Same as API 0 EN H

2BJ1

One of four possible signals issued
by the I/O processor indicating

The device uses this signal to
gate the address of its API entry

ENH

API 2
EN H

API 3
EN H

APL O
GRH

that it grants the API request at
the corresponding level .
API 1

Same as API 0 GR H

2BE2

Same as API 0 GR H

Same as API0 GR H

2BM2

Same as API 0 GR H

2BH1

One of four API request signals
on channels 0-3. This signal is
set by the device at I/O Sync

The device uses this signal to inform the 1/O processor of its re-

GRH
API3

GRH
API O

RQ L

time.

API 1

Request API priority level 1.

2BD2

Same as API 0 RQ L

Request API priority level 2.

2BK2

Same as API 0 RQ L

Request API priority level 3.

1BD1

This signal is gated onto the bus by
the I/O processor during the third

This signal is used by the device
to notify it when an incorrect sum

RQL
DATA
OFLOH

highest of the four.

Some as API 0 RQ L

RQL
API 3

quest for API priority level 0, the

2BM1

RQ L
API 2

location onto the I/O ADDR lines.

2BP1

GRH
API 2

cycle of an add=fo=-memory opera-

tion when the sum (1's complement)

of two like~signed numbers has an
opposite sign.

4-10

occurs, because of overflow dur-

ing an add-to-memory operation.

Table 4=2 (Cont)

/O Bus Signal Functions

Milegr:g:fic

P(i::nl:s;f;;r

DCH

2BV2

ENH

Signal Definition
This enable signal is a dc level

Signal Function
Each device can post a DCH re-

originating at the 1/O processor

quest only if the incoming DCH

and daisy chained from device
to device. The M104 logic in
each device can interrupt this
level, cutting the level off all
devices that follow on the bus.

EN level is true. By posting a re=
quest, the device immediately inhibits all controllers below it on
the bus. In this way priorities are
established when devices request
simultaneously
.

A device receives it as DCH EN
IN H and transmits it as DCH EN

OUT H.

DCH

2BT2

GRH

Issued by the 1/O processor when

The device uses DCH GR to gate

it acknowledges a device's

the address of its word count onto

DCHRQ L.

the 1/O ADDR for 3-cycle transfers
and gates memory address during

1=cycle transfers.

DCH
RQ L

2BS2

A signal from a device to the I/O
processor indicating either o re-

This signal is interpreted by the
1I/O processor in two ways:

quest for a multicycle data channel transfer or, when posted with
a single cycle request, showing that
an input transfer must be effected.
The table below shows how the two

If it is present without a single=~
cycle request, it implies that
some device wants to carry out a
multicycle transfer, an increment memory, or add to memory.

functions relate.

.
.
If a single=cycle request is also

DCH

SING

posted, then the two signals are

RQL

CYRQL

FUNCTION

Single Cycle

Otherwise, the 1/O processor

Transfer Out

assumes an outgoing single-

Multi Cycle

cycle transfer is required.

ANDed to inform the 1/O pro-

cessor that a single~cycle trans-

fer into memory is to be effected.

Transfer (In
or Out)
1

Single Cycle
Transfer In

DSO H

2AD2

The first of six device select lines
decoded from bit 6 of the IOT in-

This signal together with DS1-DS5
is decoded by the device select

struction.

logic in the controller, which
responds to ifs unique code only.

DST H

2AE2

The second of the six device select

See DSO H

lines.

DS2 H

2AH2

The third of the six device select
lines.

4-11

See DSO H

Table 4-2 (Cont)

I/O Bus Signal Functions

Mrsl;s:::r:ic

Piom:r::::r

Signal Definition

DS3 H

2AK2

The fourth of the six device select

DS4 H

2AM2

The fifth of the six device select

DS5 H

2AP2

The sixth of the six device select

INC
MB L

2BD1

See DSO H

lines.

See DSO H

lines.

See DSO H

lines.

Forces the I/O processor to incre=
ment the contents of the memory
location specified by the 15-bit

This feature allows a device to
increment memory locations in one
cycle without disturbing the CPU.

One of fifteen lines which constitute an input bus for devices which

This address bus has two uses:
a) To deliver the device's API

address lines on the /O bus.

I/O ADDR|
03 L

Signal Function

1BHI1

must deliver address data to the
processor.

entry location during its API
break.

b) To deliver the device's word
count address during a multicycle
DCH transfer, an increment mem-

.
ory operation, or add to memory
To deliver an absolute address
during single cycle transfers.

I/O ADDR|

1BJ1

Similar to I/O ADDR 03 L

Similar to 1/O ADDR 03 L

I/O ADDR|

Similar to I/O ADDR 03 L

Similar to /O ADDR 03 L

1BM1

Similar to I/O ADDR 03 L

Similar to /O ADDR 03 L

1BP1

Similar to /O ADDR 03 L

Similar to /O ADDR O3 L

1BS1

Similar to /O ADDR 03 L

Similar to /O ADDR O3 L

1BD2

Similar to I/O ADDR O3 L

Similar to I/O ADDR 03 L

1BE2

Similar to /O ADDR 03 L

1BH2

Similar to 1/0O ADDR 03 L

Similar to I/O ADDR 03 L

1BK2

Similar to I/O ADDR 03 L

Similar to 1/O ADDR 03 L

1BM2

Similar to I/O ADDR 03 L

Similar to /O ADDR 03 L

04 L

05L

I/O ADDR|
06 L

I/O ADDR|
07 L

I/O ADDR|
08 L

I/O ADDR|
09 L

I/O ADDR|
10L

I/O ADDR|
1ML

I/O ADDR|
12L

I/O ADDR|
13L

Table 4-2 (Cont)

I/O Bus Signal Functions

M::a?::rilic
I/O ADDR|

P?:?:j:;;r

Signal Definition

Signal Function

1BP2

Similar o I/O ADDR 03 L

Similar to I/O ADDR 03 L

1BS2

Similar to I/O ADDR O3 L

Similar o I/O ADDR 03 L

1BT2

Similar to /O ADDR O3 L

Similar to I/O ADDR O3 L

1BV2

Similar to I/O ADDR 03 L

Similar to /O ADDR O3 L

14 L

I/O ADDR|
15L

I/O ADDR|
16 L

I/O ADDR|
17 L

1/0 BUS
00 L

1AB1

The first of 18 data lines which

constitute the bidirectional fo-

cility for transferring data in
bytes of up fo 18 bits between
the device and either the CPU
or memory.

This is the MSB.

These data lines (I/O BUS 00 L

through 1/O BUS 17 L convey

data befween
a) the AC of the CPU and a selected device information buffer
register or

b) the bus buffer of the 1/O pro-

cessor and a selected device buffer register during data channel

operations.

1AD1

Data line two

See I/O BUS 00 L

I/O

1AE1

Data line three

See I/O BUS 00 L

I/O

TAH1

Data line four

See /O BUS 00 L

1AJ1

Data line five

See I/O BUS 00 L

1AL1

Data line six

See I/O BUS 00 L

1AM1

Data line seven

See /O BUS 00 L

1AP1

Data line eight

See /O BUS 00 L

1AS1

Data line nine

See I/O BUS 00 L

1AD2

Data line ten

See /0O BUS 00 L

1AE2

Data line eleven

See I/O BUS 00 L

1AH2

Data line twelve

See I/O BUS 00 L

/0
BUSO1L

BUSO02 L
BUS 03 L

I/O
BUS 04 L

1/0
BUSO5 L

1/O

BUS 06 L

I/O
BUSO7 L

I/0
BUSO8 L

/O
BUS 09 L

1/0
BUS 10 L

I/O
BUS 11 L

Table 4~2 (Cont)

1/O Bus Signal Functions

Signal

Mnemonic

Connector

| Pin Number

. e

Signal Definition

Signal Function

1AK2

Data line thirteen

See /O BUS 00 L

1AM2

Data line fourteen

See /O BUS 00 L

1AP2

Data line fifteen

See I/O BUS 00 L

1AS2

Data line sixteen

See 1/O BUS 00 L

1AT2

Data line seventeen

See /O BUS 00 L

Data line eighteen

See I/O BUS 00 L

BUS 12 L

I/O
BUS13 L

/0
BUS 14 L

I/O
BUS15L

I/O
BUS 16 L

I/O

1AV2

BUS17 L

This is the LSB

1BE1T

OFLOH

This signal is issued during the first

This signal indicates to the device

cycle of a multicycle data channel

that the specified number or words

transfer or an increment memory cy=~ | have been transferred at the comcle if the content (2's complement)
pletion of the transfer in progress.
of the word count assigned to the
It is normally used to turn off the

currently active data channel device becomes zero when incre-

respective device and to initiate
a program interrupt or API request.

mented .
IOP 1 H

2AD1

Microprogrammable control signal

Used for 1/O skip instructions to

part of an IOT instruction=specified

test a device flag or other control

operation within a device.

De-

coded from bit 17 of the 10T.

functions.

Cannot be used to

read a device buffer register.
In general , a designer should be
wary of using IOP pulses for mul-

tiple purposes. Never clear and
skip on a flag, with the same 10T,
for examplel

IOP 2H

2AE1

Same as IOP 1 H and it is also issued | Usually used to effect a transfer
during a multicycle data channel

of data from a selected device to

transfer into memory.

the processor or memory, to clear
a device register, but may be used

Decoded

from bit 16 of the 10T.

for other control functions. May
not be-used to determine a skip.
IOP 4 H

2AH1

Same as IOP 1 H and it is also is-

Usually used to effect transfer of

sued during a multi- or single—cycle

data from the CPU or memory to

data channel transfer out of memory
.
Decoded from bit 15 of the 10T,

the device or control.

May not
be used to determine a skip con-

dition or to effect a transfer of
data from a selected device to the

CPU.

Table 4~2 (Cont)

I/O Bus Signal Functions

Signal

Connector

1/0O PWR
CLRH

2AS51

Mnemonic | Pin Number

. ere

Signal Definition

System clear signal generated in
response to:
1) Power on or off

Signal Function

This signal is treated as an initializing signal for all devices (controllers) attached to the I/O bus.

2) CAF instruction
3) I/O RESET key

All registers are reset to "initial"
status.

1 mHz, 250-ns pulse width

I/0
RUNH

2BB1

This level becomes high when the
IPU is running.
:

Can be used to disable a device
if the CPU stops.

I/0
SYNCH

2AB1

The I/O processor clock pulse
issued every microsecond; 1 mHz,
250~ns pulse width,

This signal is used to synchronize
device control timing such as
API RQ and DC H RQ to the I/O
.
processor

PROG
INTRQL

2AL1

2AM1

RQL
RD

STATUS H

This signal can cause the program
to CAL to location 000000. The

instruction resident in location
000001 is fetched and executed.

2AP1

Indicates to the processor that the

device is sending it a data word.

A signal issued when the CPU is-

sues an IORS instruction or when
the console switch is placed on
I/O STATUS.

SDO H

2AT2

SD1 H

2AV2

The first of two subdevice select

A device delivers this level to the
/0 processor to request interruption of the program in progress in
order that the device be serviced.

- Used by the device fo specify to

the 1/O processor an input=to=

CPU data transfer is required.

Used by the device to gate its

status onto the I/O bus data lines

(one line per status bit) which is
then read into the AC of the CPU.

This signal and DS1 H can be de-

lines decoded from bit 12 of the
IOT instruction.

coded by the device for mode
selection.

Same as SDO H except it is de-

Same as SDO H

coded from bit 13 of the IOT instruction.

SING CY

2AS2

Indicates when a device wants to
carry out a single =cycle data
transfer to memory.

' This device uses this line to re~
quest from the 1/O processor a

single=cycle transfer. If a DCH
RQ signal is sent with it, then the
I/O processor responds to an in=
put (to computer) transfer. Otherwise it determines an output

transfer.

SKIP
RQL

2AN

The return of the signal to the 1/O
processor during IOP 1 indicates
that an IOT instruction test for a

skip condition has been satisfied.
The PC is subsequently incremented
by one.

Used by a device to inform the
program of the state of its inter-

rupt flag. Also used in Single
Cycle breaks as address line 01.

Table 4~2 (Cont)

I/O Bus Signal Functions

Signal

Connector

WR
RQ L

2BB1

2BE1

Mnemonic | Pin Number

CAINHL

Signal Definition

Signal Function

Indicates to the 1/O processor that

The device uses this signal to in-

channel . Also used during Single
Cycle breaks as address line 02,

ticycle data channel transfer). Also used during Single Cycle breaks
as address line 02.

the device requires a transfer from
memory during a multicycle data

form the 1/O processor that it wants
a word from memory (during a mul-

If the 1/O processor sees this signal | This facility is used by such periph-

erals as DECtape and magnetic

during multicycle transfers, it in=hibits normal incrementing of the

tape when they search for records.

device's assigned current address
memory location.

checkout.

It is also useful during device

4.7 1/0 BUS DEVICE PRIORITY AND SYNCHRONIZATION
In DCH and API, (described in Paragraph 6.4), a priority exists among the eight devices which may

be placed on the DCH or API level 0, 1, 2 or 3 lines.
given priority.

The device closest to the 1/Q processor is

The M104 Multiplexer Module is used in determining the priority by issuing the DCH

or API request and controlling the device during the fransfer.
An enaoble signal is daisy=chained from device to device on the bus.

allows its request to be raised.

An endble signal to a device

When a device raises a request, it disables the enable transmitted to

the next device on the bus, clearing or inhibiting the request of any device further down the bus. The

enable is disabled until the action requested is completed.
The synchronization of a device starts when the device raises its device flag.

If the enable (EN IN)

is true the REQ will be set at the next /O SYNC. Approximately 1 ps later, a GRANT signal will

be sent out on the 1/O bus and will load the contents of the REQ flip-flop into ENA flop.

This micro=

second is used to allow the EN OUT signal that was taken away, to propagate down the bus and clear
any other requests which may have been set.

the I/O ADDRESS lines.

ENA is used to gate the address from the device onto

ENB which is set one microsecond after ENA is used in Multicycle DCH

breaks to specify the data transfer.

Figure 4-7 is a simplified description of the M104 logic.

Timing is shown in Figure 4-8.

TO MEMORY
KP26

MEMORY PORT SWITCH

LTO cPU

;

KDO1
KDO2

REQUEST

KDO3
DSR

(DATA STORAGE |——}-—~

{

KD Ot
KDO2
KDO3

KDO4
KDO5
KDO6

u
n

! OE?DER

CONTROL

| GRANT

PRIORITIES

j-~————

AND

_______

LoGIC

MIXER LOGIC F--]--———-—

REQUEST

|REQUEST

TOCPU

GRANT

[7 BUS BUFFER I
KDO4
KD OS5

P 10 cPU

1/0 BUS
TO
1/0 DEVICES
15~0181

Figure 46

Data Channel Block Diagram

IN
ENABLE
ENABLE OUT

DEVICE FLAG

1/0 SYNC

ENB

ENA

REQ

m o

—Cc

i%LEAR
®

GRANT
P2

EXTERNAL

CONNECTION

FLA
CLEAR
FLAG
LEAR

15-0283

Figure 4~7

Simplified M104 Module Diagram

4-17

M104

1/0 SYNC c‘,i |

REQ EN o

GRANT H o
.

gt
%

/ / /
U
r—‘{fi \ \

)

J1iS ASSUMED TO BE WIRED TO F2
15 -0087

Figure 4-8

4.8

MI104 Timing Diagram

SINGLE CYCLE INPUT TRANSFERS

In utilizing this type of transfer, a device must first be synchronized to the 1/O processor as described
in Paragraph 4~3.
sor.

Both address and data must then be transmitted over the I/O bus to the 1/O proces-

The processor then makes a memory request fo store data.

In performing this operation (refer to Figure 4=9), the address from the device is loaded intc the DSR

register and the data into the 1/O buffer register. A memory write request is generated and, when
the ADR ACK signal is returned from memory, the 1/O buffer is loaded into the DSR, the DSR enabled
on the MDL, the MRLS signal is sent back to memory and the 1/O cycle is terminated.

Figure 4-10 is

a flow diagram of single cycle input transfers.

If the active device maintains the request signal when the address is strobed into the DSR, a BACK fo
BACK transfer will be performed and another GRANT

will be sent out to the device, instead of

terminating the cycle. The device can change its address and data when GRANT is removed from the
bus, but it must have both enabled to the bus when GRANT becomes true again.
prevented from syncing, because 1/O SYNC is disabled from the bus.

Other devices are

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START

DCH RQ H

SING BR
KPE8

KPS0

SING CYCLE
o

rQ
STROBE ADR

KPS0

KDO6
.
=

DATA RQ

‘

SET 1/0 MEM REQ

KDO4

‘
DCH (1}
KP51

()

KDO4

5,14

1/0 MEM HOLD (0}

6,15

WC ENABLE (0}

1/0 MEM REQ {1}

KD04

KP26

cy
3,12

TIME 1
KD04

1/0 WRITE (1)
ONE CYCLE BK (1]

DCH SYNC {1}

KDoA

SING CYC DIR (1}

HS CLOCK

7.16

KDO6

[

hs CLOCK

BACK

1/0 ACTIVE (1)

STOP 1/0 SYNC

1/0 BUF

KP26

-- DSR (1]

KPS5

DATA IN - 1/O
ADDER WAITING

FOR NEXT STROBE

SING CYCLE

DIR {1}

1/0 ADDR -- MDL

1/0 CLOCK

—

KDO&
KP26

STROBE 1/0 BUF

STP TIA

KDO5

HS CLOCK

RANT (1)

DATA GATED

INTO 1/0 BUFFER

KD
oc

TO DEVICE ENA

SET, ADDR PLACED

MEM REQ

ON 1/0 ADDR LINE#

DATA PLACED ON
BUS

y
~ MDL ~ DSR

WAIT FOR ADDR

1/0 MEM

HOLD {1}

g
p

KD04

1o
ADDR ACK

WC ENABLE (1)

1/0 ADDR -~ DSR

KDO4
KDO4

KP26

LEGEND

I
m

KDOo4

2ND TRANSFER

1/0 MEM REQ (0)1

GRANT CLEARED
JF SING CYC REQ STILL HIGH, THEN BACK-TO-BACK iS SET

AND THE 1/0 CLOCK IS STOPPED

9. FIRST DATA WORD PLACED IN DSR.

SET GRANT FOR SECOND WORD TRANSFER.

KP26

10.

BACK-TO-BACK DLYD IS SET.

11. FIRST WORD TRANSFERRED TO MEMORY AND | 'O CLOCK IS

14. SECOND MEM REQUEST INITIATED BY 'O MEM REQ (11,
15.

16.

147 KDOS

KDO6

SECOND IO ADDRESS PLACED IN DSR FOLLOWING TIME 4.

SECOND DATA WORD PLACED IN DSR THROUGH ADDER TO
THE INPUT OF THE DSR.

STP TM CHAIN {0)

KDO6

KDO4

i2.

13.

KDOG

KP26

DATA PLACED IN i:0 BUFFER THROUGH THE ADDER TO

FIRST MEM REQ INITIATED.

8. IF BACK-TO-BACK IS SET, ADDR ACK FROM MEMORY WILL

170 ACTIVE {0}

GRANT (1)

—

WC ENABLE (0)

BK-TO-BK DLYD (1).
GRANT CLEARED.

SING CYC RQ DISABLED WHICH RESETS BACK-TO-BACK TO

INHIBIT FUTURE TRANSFERS.

RESTART I/O CLK

/O MEM REQ {1}

KDO04

6.
7.

BACK-TO-BACK {1}

)¢

KDO04

1/0 MEM HOLD {0}

L 1/0 WRITE (0)

P26

KDO6

{

5, 14

DATA AND I'O ADDR PLACED ON BUS AFTER GRANT ISSET.

RESTARTED.

SET 1/O MEM REQ

‘

KP26

1’0 ADDRESS
PLACED IN DSR.

THE INPUT OF THE DSR.
MRLS ACK

KP26

- 3CYCLE

1/0 ADDR ACK

STROBE ADR

SINGLE CYCLE BREAK INITIATED

2.
P

SING

CYCLE REQ

IN TIME 3

KP50

3.12

STROBE DSR

ONE CYCLE BK
KD04

‘

KDOG

SING €YC DIR (1)

HS CLOCK

ol
7.16

KDO06

BACK 1)

BK TO BK DLYD

BACK-TO-

SING CYC DIR (1)

1/0 ACTIVE (1)

KP26

KD06

1/O BUF -~ DSR {1}

Koboe

Koo

BACK-TO-BACK (Q)

RETURN DATA

a,
KDO4
DATA IN - i/O
ADDER WAITING
FOR NEXT STROBE

’
_
1/0 CLOCK

TIME
4

DSR

SET DSR TO MDL

1/O ADDR -- MDL

DCH DONE

KP26

STROBE 1/0 BUF

KDO6

STP TIM CHAIN
{1)

KDO5
o

TIME 2

KDO04

KDO4

DATA GATED

DCH (0)

BK-TO-BK DLYD (0}

DCH SYNC (0)

S!NG CYC DIR (0}

ONE CYC 8K {0}

INTO 1/0 BUFFER
75 NS DLY

kP51

DCH WAIT

MEM REQ

STROBE MRLS

DIS /0 CLK

KDO6

]

Transrer

COMPLETE

KDOB

KD06

RESTART 1/0

SYNC PULSES

KDOo4
KP35

KP55

———t

ACK FROM

MEMORY

WAIT FOR
1/0 MRLS (1}

——

=
KD0o24

I
-

MRLS TO MEM
ADDR ACK

KP26

15-0798

Figure 4-10

Single Cycle Data In Transfer,
Detailed Flow Chart

4-21

After the device has taken all the breaks required (device word count register overflows), it may

interrupt the [/O processor through the PI or API system.

4.9

SINGLE CYCLE OUTPUT TRANSFERS

For this type of transfer, a device, after synchronizing with the 1/O processor, transmits its address

over the I/O address lines. The I/O processor requests memory , reads the data from memory, and
transmits the data back out to the device.

Figure 4-11 shows a block diagram of this type of transfer, in which the address is loaded into the
D3R, a memory read request is made, the DSR is loaded with the memory data when RD RST is received,

.and then enabled on the 1/O bus, and an IOP 4 is generated to load the data in the peripheral device.
Back-to-back transfers are detected in a similar manner as input fransfers.

Figure 4~12 is a detailed

flow diagram of single cycle output transfers.

4.10 MULTICYCLE INPUT TRANSFERS
Multicycle transfers rely on word count and current address registers located in core memory.

For

input transfers, the device specifies the word count location by an address on the /O address lines

and places the data on the I/O bus.

The I/O processor increments both the word count and the current

address location and writes the data into the memory location specified by the incremented current

address location.

This takes 3 /O processor cycles and 3 memory cycles.

Figure 4-13 shows a block diagram of multicycle input transfers.

The word count address, specified

by the device on the I/O address lines, is loaded into the DSR, and a memory read/pause/write cycle
is requested.

One is added to the data read from memory, the result is loaded into the DSR, and then

is rewritten into memory.

This is called the word count cycle.

The address on the I/O address lines

is then incremented by one, to point to the current address location, loaded into memory, and another

read/pause/write cycle is requested. The data from memory is incremented by one, loaded into the
D3R, and written back into memory.

This is the current address cycle.

points fo the address into which data is to be written.

buffer during the current address cycle by IOP 2.

The number now in the DSR

Data from the device is loaded into the I/O

A memory write request is now made, and then

ADR ACK is received from memory, the 1/O buffer is loaded into the DSR, and the data written into

memory.

The /O cycle is then terminated.

If the word count register has overflowed when it was incremented (there was a carry), an I/O OFLO
signal is sent fo the device to prevent it from requesting another break.
gress is completed.

The current request in pro-

Refer to Figure 4-14 for a timing diagram and Figure 4=15 for a detailed flow diagram.

4-23

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m
KPS0

RD RST FROM

SET 1/0 MEM REQ

MEMORY

KDo4

75 NS

KP26

SING CYC REQ

1/0 RD RST

KP50

1/0 MEM HOLD (0)

KP26

STROI

KDO04
1

DATA REQ
I

MDL — DSR

Vo M

1/0 READ (1)
KD04

KDo4

50 NS DELAY

WAIT
ACK F(

i/0 MEM REQ (1)

DCH (1)

KP26

9.20

KP51

PRE MRLS

KDO6

\
1/0 DATA ACK

DSR — 1

(o)

ONE CYCLE BK
1
)

KDO04

KDOG

STOP 1/0 SYNC

1/0 ACTIVE (1)

DCH SYNC (1)

PULSES

1/0 DATA ACK (1)

KP51

DSR — 1/0 BUS (1}

KDO4

KP55

KDOS
1

5.17

DATA ACK TO

YCDIRO
SING CYC

MEMORY

STP TM CHAIN (0)

{/0 ADDR -- MDL
v

SET

0-- MPX

GRANT 1

«P26

DSR

KP26

KDO5

MDL

HS CLOCK

KD06
18

KP26

RESTART I/0 CLK
CLK IN TIME 3

BK TO BK DLYD

{

KDO06

SETSENA &

PLACES ADDR ON

SING CYCDIR

1/0 ADDR LINES

MEM REQ

10. 21

STROBE DSR

KDO6

WAIT FOR ADDR
1/0 MEM HOLD (1)

KDO04

ACK
DATA FROM MEM

KDO4

STROBED IN DSR

KP26

ADDR ACK FROM
MEMORY

1/0 ADDR - DSR

| WC ENABLE (1) I

KDOo4

KDoa

719

KP26

IO ADDR ACK
12

l
KP26

KDO6

I MEM REQ (0} —l
STROBE ADDR

—t

—r

KP26

BK-TO-BK

KD04

l 1/0 READ (0}

/O MEM REQ (0]

KDC4

y
WAIT FOR RD
RST

GRANT (1}

KDG6
KP26

—

e———

—

—0

RD RST FROM

MEMORY

)

KDoO6

)

1/0 RD RST
o

12,22

ONE CYC BK (1}

2.15

DSR ~ 1/0 BUS (1}

STROBE DSR

WC ENABLE

ROBE M
KDO5

KDO6

KDO4

DCH OUT XER

KDo4

KD04

SONSPELAY )

13,23

WAIT FOR MRLS

GRANT (0)

1/0 ADDR IN DSR

SING CYC 10P4

ACK

9,20

cvst.!';crso

l KDO6
PRE MRLS

KDO06

o))

1I0P4 H

ONE CYC BK (1)
1/O DATA ACK
©

/O DATA ACK (1)

DSR - 1/0 BUS (1}

Kooa

DSR - MDL. (0}

KkDo4

KD04
)

KDo6

KDO§

CLR DSR — 1/0
l

KDO0S

KP50

1/0 MRLS (0)

KDOo6

—

KDOS

190 NS DELAY

DSR — 1/0 BUS

)

1/0 ADDR ACK

BK.TO-BK (11

KDOS

KP26

KPS0

DCH DONE

(s1|)<-1'o-sn< DLYD

KDO6

SET DSR — MDL

prve

‘

KDO5
KDO6

KD06

KDo&

STB MRLS DLY

DCH (0)

RESTART I/O CLK

1/Q CLOCK

ONE CYC BK {0}

KP51

10,21

SING CYC DIR

BACK.-TO-BACK (11

SING CYC 10P4 {0}

KDO6

KD0B

STP TM CHAIN (1}

KPS55

TIME 2

BACK-TO-BACK

DLYD (0}

KP26

KD06

KDO5

TRANSFER

COMPLETE

KP51

SYNC PULSES

KD06

KDO6

RESTART J/C

o
STROBE DSR

KP51

DCH SYNC (0}

TIME 4

BK DLYD

10P4

DSR - 1/0 BUS (0)

DATA ACK TO

kP26

1
BACK-TO-BACK

DIS1/O CLK

KP35
WAIT FOR PRE
MRLS

LEGEND

(D06

1/0 ADR AVAILABLE AT DSR.

ADRPLACED IN DSR, GRANT CLEAREL.

IFSING CYCREQSTILL HIGH BK TO BK F/F SET.

4.
.

1/O CLOCK STOPPED.
ADR

SENT

13.

10P4TO DEVICE, DEVICE ACCEPTS DATA.

14.

STBMRLS DLY GIVESSTROBE ADDR IF BK TOBK SET

15.

2ND ADR PLACED IN DSR,

16.

BACK-TO-BACK CLEARED.

17.

6.
7.

8.
9.
10.
1.

12.

GRANT CLEARED

MEMORY.

MEMORY REQUEST INITIATED.

1/0

ADR

SENT

MEMORY.

18.

2ND MEM REQUEST MADE WITH BK TO BK DLYD AND [ O MEM REQ

BKTOBKDLYDSET.
DATA AVAILABLE AT DSR FROM MEMORY.
DATAPLACED IN DSR.

19.
20.
21.

ADR ACKNOWLEDGED BY MEMORY.
DATA AVAILABLE AT DSR FROM MEMORY.
DATA PLACED IN DSR.

DATAPLACED ON I/0 BUS.

23,

10P4 TO DEVICE, DEVICE ACCEPTS DATA

ADR ACKNOWLEDGED BY MEMORY, GRANT SET IF BK TO BK = 1.

1/0 CLOCK RESTARTED.

(HS CLOCK NOT INVOLVED).

DATA PLACED ON 1O BUS.

15-0799

Figure 4-12

Single Cycle Data Out Transfers,
Detailed Flow Chart

4-25

L MEMORY

—I

’

WC ADDRESS/15
1/0 BUS

—
DATA CHANNEL
|

DATA

INTERFACE

MEMOR'Y
PORT

SWITCH

1/0

ADDR

ACK

1/0 RD RST

KDO1,KDO2,

Ir—

» 170 DATA ACK

REQ

READ REQ

CJ"CCLE

<— 1/0 ADDR-MDL KP26

GRANT

le—— STROBE DSR KDO4

le—— 1/0 ADDR-DSR KDO4

MRLS ACK

INC WORD COUNT

KDO3

1/0 MRLS

WORD COUNT

DCH

r—————]

;

KP26

1/0 SYNC

KDO1 THRU KDO6

STORAGE

{/0 M REQ
I

LOGIC

WC ADDRESS /15

}
|

fe— MDL
- DSR

j ADD1 —;l
]

Ir|

le—— 1/0 ADDR-DSR KDO4
ca

le— STROBE DSR KDO4

| AUD;’[')‘Afi,SES

le—— 1/0 ADDR- MDL KP26

CYCLE

18 CURRENT ADDRESS MINUS ONE

I
I|

MDL-DSR

| I

F—

STROBE DSR

DSR-MDL

KDO1

,'éggg

170

BUFFER

|
I

DATA /18

INCREMENTED WC

ADD1

18 CURRENT ADDRESS

1/0
DEVICE

DATA /18

l«— DSR-MDL ( ADDRESS MEMORY)

DATA

CYCLE

.
10P2

le— MDL-DSR

le— STROBE

DSR KDOS5

l«— DSR-1/0 BUS KDO5

15-0289

Figure 4-13

Multicycle Data In Transfer

Block Diagram

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Multicycle Data In Transfer,
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4.11

MULTICYCLE OUTPUT TRANSFERS

Output transfers use the word count and current address location as the input transfer.

The data is

fetched from memory and loaded into the device in the third cycle.
Both the word count and current address cycles are similar to the input transfers.
block diagram of the multicycle output transfer.

Figure 4-16 is a

During the data cycle a memory read request is made,

and the I/O processor stopped. When the data is read from memory into the DSR, the I/O processor
is restarted, data in the DSR put onto the I/O bus, and an IOP 4 generated to load the data into the
device.

Figure 4-17 is a detailed flow chart of the multicycle output transfers.

4.12 ADD TO MEMORY

This feature is similar to the multicycle fransfers but differs in that, during the data cycle, data from
memory is added to data from the device, and written into memory and transmitted to the device.

A read/pause/write cycle is requested in the data cycle and, when data is available from memory, it
is enabled through one input on the DSR adder while the 1/O buffer is enabled through the other and
the DSR is then loaded with the result.

The data is then rewritten into memory, enabled onto the I/O

bus, and an 1OP 4 is generated to load the device buffer if desired.
This type of cycle is performed by the device enabling both RD RQ and WR RQ on the I/O bus.

4.13

INCREMENT MEMORY

This feature increments a memory location in one 1/O processor cycle.
of a multicycle break is performed.

is incremented by one.

Only the word count cycle

The location specified by the address on the 1/O address line

Enabling the INC MB line on the 1/O bus along with DCH REQ will cause

this type of cycle.

4.14 INHIBIT INCREMENT THE CURRENT ADDRESS

This line on the I/O bus inhibits the current address from being incremented. ADD ONE is not turned
on during the data portion of the current address cycle.

4-33

| wemory |
> MDL

WC ADDRESS

—

DATA CHANNEL LOGIC
TA STOMAGE

1/0 M REQ
1/0 ADDR ACK

KP26

DCH REQ

(DSR)

WRITE REQ

KDO1,KDO2 ,KDO3

o [/0 DATA ACK

1/0 MRLS

MRLS ACK

WORD COUNT

C;NCCLE

l«—— STROBE DSR KDO4

l«—— 1/0 ADDR-MDL KDO4

{

ADDRESS /15

e—— STROBE DSR

INC WC ADDR

GRANT

1/0 RD RST
INTERFACE

170 SYNC

KDO1 THRU KDO6

(ADD!

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MDL-DSR —F
E—
I
|

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CA

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CYCLE

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MDL-DSR—
18 CURRENT ADDRESS MINUS ONE

INC WC ADDR

—

ADD1

aopg

18 CURRENT ADDRESS

1/0

DEVICE

>
KDO1

STROBE DSR

1/0

KDO2

KDo2

BUFFER

'DSR-MDL

|
|I

{_
1

DATA /18

le— DSR-MDL

‘

DATA

CYCLE

10P4

|e— MDL-DSR

le——

STROBE

—>

DSR

DSR-1/0 BUS KDOS

15-0291

Figure 4-16

Multicycle Data Out Transfers,
Block Diagram

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4-39

4.15

DATA CHANNEL LATENCY

Latency is defined as the amount of time which is required to transfer data ofter the request is made
by a device. When a worst case latency time is stated, it is assumed that the requesting device has

priority over all other devices on the 1/0 bus.
Worst case latency in the PDP-15 occurs when a request is granted to a multicycle output device.

The

worst case latency for a single cycle output device is 8.5 ps.

4.16

PROGRAM INTERRUPT

The program interrupt facility has two IOTs associated with it:
ION

700042

Enable the PI

IOF

700002

Disable the PI

When the PI is disabled, the computer does not respond fo any program interrupt requests (PROG INT

RQ). However, when the PI is enabled, an interruption of normal program flow will occur. Upon
receipt of a PROG INT RQ, the computer proceeds to complete its present instruction before interrupt-

ing. At clock time of TS02, Phase 3 and Set Fetch of an instruction, interrupt acknowledge (INTRPT
ACK - KP35) is set.

This causes RUN to be cleared at TS03, Phase 3, preventing the CP from con-

tinuing.

During TS03, the I/O address lines are placed on the A Bus.

zeroes.

At clock time of TS03, a PI REQ is raised.

in Section 4.2.

The lines should contain all

This is used in the Request Synchronizer described

Pl is set at Time 4 and Pl SYNC at Time 1.

On the next Time 4, INTERRUPT STB is

issued which loads the MO with the /O address, sets INTERRUPT STATE, and sets START RUN allowing the CP.timing to continue.

The IR is cleared at TSO1, forcing the CP to do a CAL.

However, the

CAL is to location zero, because the MO was loaded with zero. A flow diagram of PI/CPU interaction
is in Chapter 6.

4-41

CHAPTER 5

POWER DISTRIBUTION
5.1

PDP-15 POWER

The power distribution system for the basic PDP=15 and 32K of memory is contained in the CP/10
mainframe. It comprises a 715 Power Supply with bulk regulation, regulation at the logic end, and

a power monitoring network. It is designed to offer a high percentage of heat dissipation at the
power supply end, and be able to supply each logic rack with maximum load=to-voltage response.

The power monitoring network was designed to protect the logic and assist troubleshooting with the
loss of dc power.

Figure 5-1 is a block diagram that shows the power distribution of the cabinet. The following paragraphs will explain each block.

POWER HARNESS

715 POWER SUPPLY

ACINLET

rer === |

AC CONTROL

DC POWER SOURCE

CONSOLE CONTROL

BULK REGULATION.

RAW VOLTAGE

REGULATOR VOLTAGE

}

POWER OK SIGNAL

[

=—

___________

POWER MONITOR RELAY | =—

PDP-15 LOGIC POWER

L,
—

LOCAL

REGULATION
— T

= — =

| POWER MONITOR NETWORK

15-0292

Figure 51

5.1.1

Power Distribution Block Diagram

715 Power Supply

The 715 Power Supply has a ferro=resonant fransformer and has the capability of accepting 110 Vac or

220 Vac, 50/60 cycle with small modification to the ac power control. (Tables are shown on the

power supplies back door panel to aid in implementing such modifications.)

An autotap with multiple

outlets (P8 and P9) is provided for operating the required system fans.
The 715 Power Supply circuit schematic, D=CS-715-0~1,

5.1.2

is shown in Volume 2.

AC Control

Power protection is controlled at the ac inlet prior to the primary of the transformer.

cuit breaker CB1, provides the main transformer T1 overcurrent protection.
lines are tied to the primary of transformer T2.

A two-line cir-

At the next node the cac

The next component on the ac line is a 35 A capacity,

double line break relay K1 for remote control of power on/off.

At the next node the ac lines are

tied to the main transformer's T1 primary winding, and the autotap plugs.

A dual ac outlet is con-

nected through a noise filter network to this same node to provide power for Teletypes plus remote
power control in other cabinets.

Relay K1 is operated by remote control at the console end.
primary coil of the relay.

Twelve volts are used to energize the

This voltage is supplied by step down transformer T2.

The secondary wind-

ing is fused (F13) and is in series to the relay coil and connections that are wired to the console switch

shown in drawing D-C5-5408392-0-1 in Volume 2.
Switch SW1, connected in parallel with the console switch connections in the power supply provides
a console lock out feature.

To complete this feature a second section of this switch, a ground signal,

is wired to an outlet plug (P2, pin 6).

A wire run to the console, completes the connection, and

locks out the console control switches.

This feature prevents the operator from disturbing the running

program,

Transformer T2, besides supplying the relay 12 volts, supplies 6 volts ac and =6 volts dc.

The 6 Vac

is used in the real time clock option and the =6 Vdc is used to bias the console switch card.

5.1.3

DC Power Source

The secondary network of the main transformer T1 is comprised of four full wave rectified windings
and one resonator winding (part of the ferroresonant network).

The four windings produce +11V with

80 to 85A capacity, =11V, =30V, and +30V each having 55.5A maximum capacity.

All four raw voltage sources are used for the system logic needs.
all the +5V local voltage regulator units (module G821),

The +11V is used primarily to bias

The =11V is used to supply a 6V negative

bias for the sense amplifiers on the memory G100 modules through a negative voltage regulator

(module G822).

The regulator also supplies the threshold voltage for the sense amplifiers.

The =30V

is used to supply a =24V potential for producing x,y and inhibit currents through a voltage regulator

and a passive element (modules G823 and G825 respectively).

The +30V is used to power the con-

sole lights.

All the windings are accurately fused for burn out protection at the power supply.

A table is provided

on the rear door panel of the 715 Power Supply to facilitate a correlation between the potential voltage
system racks, power supply plug, fuse holder, and fuse capacity.

CAUTION

All fuse capacities noted on table must be used for maximum
system protection.

5.1.4

Bulk Regulation

A bulk regulation network is incorporated to distribute a maximum of 80A to the system from the +11V
source and keep the IR drops, line reflections, and ac ripple at a minimum.

The network consists of

three bulk regulator circuits each capable of supplying 30A maximum.

The three regulators provide an 8.1V potential and are accurate from no load to full load. Each 8.1V
is used to supply the current need through the local regulators (G821 +5V regulator module).

One

added advantage of using +8.1V instead of +11V is that it minimizes power dissipation in the series

pass element at the local regulator.
system in 10A chunks.

The harness distribution allows the 8.1V to be distributed to the

Each 10A chunk is fused at the power supply for maximum system protection.

As well as having fused 10A chunks, each bulk regulator has an overcurrent protection in case of power
supply short circuits.

This overcurrent protection is fused through circuit breaker CB2 for each

regulator.

The circuit breaker reset switch houses a 3=pole single throw with the three poles ganged

together.

This switch is located on the front door panel of the power supply.

The bulk regulators are modular in form and are part of the subassembly of the power supply.

Each

regulator has o large heat sink attached to it, with one fan blowing air past the three units.

This

same subassembly contains the two rectifier diodes for the +11V.

at all times to ensure proper heat dissipation.

objects on top of the power supply screen.

The fan must be running properly

Care must be taken not to block the air path by placing

The screen cover must never be removed from the power

supply for any length of time, to protect hands and prevent foreign objects from falling into the
power supply.

5.1.5

Power Harness

The power harness in this system is built for minimum IR drop and maximum reflection immunity. Each
hot line sent to the logic has a ground return line back to the power supply and is paired in o twisted

form. The wire size used is an AWG #12, and throughout the system not more than 10A flow through
any one line.

The wire distribution supplies a total of 16 voltage regulators in a 32K memory system,

console power, real time clock option, and the systems fan assembly .

Volume 2, drawing D-IC-PDP15-0-14 shows a pictoral sketch of the power distribution between the
power supply and the logic racks. Refer to Table 5-1 for the power distribution to each plug.

5.1.6

Local Regulation

Local regulation is incorporated to supply the transient current needs with maximum voltage stability
possible.

An added advantage of local regulation in each rack is isolation from the other racks and

minimization of noise flow on the power bus throughout the system.

In @ 32K memory system there is a total of eight G821 modules (+5V), four G822 modules (-6V), and

four G823 modules with each having a pass element module G825 (-24V). The G821 modules supply a

maximum of 7A each and have overvoltage protection and undervoltage/overcurrent protection. The
G822 modules supply 2A maximum each and have zero voltage and overvoltage protection. The G823
modules supply 4A maximum each and have zero voltage and overvoltage protection.
Descriptions of these four modules are provided in the PDP=15 Systems Module Manual.

Their ad-

justment procedures may be found in Volume 2, drawing D-BS-MM15-0-20.

5.1.7

Power Monitor Network

The power monitor network is incorporated to detect abnormal operation of any voltage regulator and,

upon detection, shut down the =30V source (memory voltage).

This, in turn, sequentially halts the

computer, and turns the console PWR light off.
The network in the mainframe and back door consists of a small amount of circuitry on each regulator
module, and a signal line which reaches each regulator slot with a receiver at the CP end to monitor

the line.

Each 45V regulator has an open collector inverter on the module that ties the line to ground

if any of the following voltage errors occur:

The +5V line is shorted to ground. Result:
and the low voltage detector turns on.

Excess amount of voltage on +5V, >5.5V.

high current drain, so a +8V fuse blows out

Table 5-1
715 Power Supply Distribution
TO
From

P1-1
-2
-3
-4
-5
-6

P2-1

-2
-3
-4
-5

-6

+11V
+ 8V
6 Vac

Loc

M515

M&N
M &N
LO3

Tab 6
Tab 1
Tab 1

Gnd
Gnd
Gnd

G821
G821
M515

M&N
M&N
LO3

Tab 5
Tab 3
Tab 4

+ 8V
- 6V
Gnd
Gnd

G821
K&L
Console Switch Board
G821
K&L
G821
K&L

+11V

G821
G821

G821

K&L

Lock (Gnd)

G827

P3-1
-2
-3

+11V
6 Vac
+30V

G827
K03
Console Switch Board
Console Switch Board

-6
P4-1
-2

Gnd
Not Used

-4
-5

-3

Tab 5
Tab 3
Tab 6
Tab 1

+5V Regulator

+5V Regulator
- V Tab
+5V Regulator
+5V Regulator

Console Locked

Monitored Voltage for Power Low
Power On/Off Tabs
+30V Tab

G827
K03
Console Switch Board

Tab 8

Gnd (Floating)
=11V (Floating)

G822
G822

Co1
Co1

+V Tab | =6V Regulator
-V Tab | -6V Regulator

G825
G825

D16
D16

Gnd Tab | =24V Pass Element
-SOVB
-24V Pass Element
Ta
Tab 6
+5V Regulator
Tab 1
+5V Regulator
Tab 2
Real Time Clock
Tab 5
+5V Regulator
Tab 3
+5V Regulator
Tab 5
Real Time Clock
Tab 6
+5V Regulator
Tab 1
+5V Regulator
Tab 2
Power Sequencer
Tab 5
+5V Regulator
Tab 3
+5V Regulator
Tab 3
Power Sequencer
Tab 6
+5V Regulator
Tab 1
+5V Regulator
+10V Tab
Tab 5
+5V Regulator
Tab 3
+5V Regulator

Not Used
Gnd
=30V

P5~1
-2
-3
-4
=5
-6
P6-1
-2
-3
-4
-5
-6
P7-1
-2
-3
-4
=5
)

+11V
+ 8V
+11V
Gnd
Gnd
Gnd
+11V
+ 8V
+30V
Gnd
Gnd
Gnd
+11V
+ 8V
+11V
Gnd
Gnd
Not Used

-6

KO3

Tab 6

Tab 1

+5V Regulator
+5V Regulator
Real Time Clock Reference
(60 Hz)
+5V Regulator
+5V Regulator
Real Time Clock

Power Up (Gnd)
Gnd

-4
-5
-6

P8-1
-2
-3
-4
-5

Note

115 Vac (Line)
115 Vac (Line)
Not Used
115 Vac (Line)
115 Vac (Line)

Not Used

Console Indicator Panel

G821
H&J
G821
H&J
M515
LO3
G821
H&J
G821
- H&J
M515
LO3
G821
E&F
G821
E&F
G827
K03
G821
E&F
G821
E&F
G827
K03
G821
A&B
G821
A&B
Console Indicator Panel
G821
A&B
G821
A&B

Top Chassis ac Tabs
Bottom Chassis ac Tabs
Top Chassis ac Tabs
Bottom Chassis ac Tabs

Energizes K2 when Power Up
Power On/Off Tabs

Gnd Tab

b. (Cont)

Results:

SCR turns on and crowbars the +5V line which blows out a +8V fuse and turns

on the low voltage detector.
c.

Low voltage on +5V > 4.75V.

Results:

low voltage detector turns on.

In the memory section only, when the =6V or the =24V regulator has a shorted output to
ground or zero voltage. Results: the respective fuse blows out for both regulators with
a short circuit only, but in both situations a ground signal is sent to the respective +5V

regulator (turning on the power-not-OK inverter).
e.

In the memory section only, when the =6V has an excess amount of voltage, >6.5V.
Results: The SCR turns on and crowbars the =6V line, which blows out the =11V fuse
and sends a ground signal to the +5V regulator (turning on the power=not=OK inverter).

In the memory section only, when the =24V has an excess amount of voltage, >26V.
Results: an operational amplifier switches polarity and a ground signal is sent to the +5V
regulator (turning the power not OK inverter on).

Refer to a complete block diagram of the power monitor network in Volume 2, drawing D-BS-KP15-0-81.

As well as placing a ground on the signal line by each +5V regulator, each regulator has an inverter
which controls a light on the back panel of each rack.
are on.

When power in the system is OK all the lights

If one rack should show trouble, the respective light will go out, providing aid to quick

troubleshooting.

If the +11V, which is o bias voltage for all the regulators, goes to zero, all the

lights will go out.

The remaining portion of the network comprises a redrive section on the G827 module, a power line
from the logic rack to the power supply, and a relay control in the power supply for the =30V source.

The G827, located in the central processor, monitors the signal line observing the regulators and redrives the signal noninverted.
at the power supply.

The output is an open collector driver that draws current through a relay

Once a ground is detected by the redrive network the relay (K2) in the power

supply is energized. This in turn opens the =30V source line not allowing rfiemory X, Y, and Inhibit
currents to occur while the system is having power problems.

The G827 also turns off the PWR light

on the console for troubleshooting assistance.

5.2

PDP-15/C POWER

The PDP-15/C uses a different power distribution system than the PDP-15.
diagram of the PDP-15/C power system.

Figure 5-2 is a block

Descriptions of the H742 Power Supply, the H744 5V

Regulator, and the H745 -15V Regulator are provided in the ME15 Core Memory Maintenance Manual,
DEC-15-HMEMA-A-D.

The 716 Indicator Power Supply and the 856A DC Power Control are

described in the print set.

A description of the 861 Power Controller is provided in Paragraph 5.2, 1.

Table 5-2 lists the power distribution connections for the PDP-15/C.

+5V —

-15V —»}
N

ME15

CABINET
FANS
SWITCHED
+15V —»

=15V —

H742

POWER

SUPPLY

> +15V

KP15

+5V —»

[72}

+5V

AC LINE
VOLTAGE —#

FOUR

8618 OR C
POWER

H744

REGULATORS

CONTROL

ONE

H745

REGULATOR

-6V —»

|- +5V

KC15

+15V —

| > —15V +5V—»

BA1S

=15V —»

716

+15V —»

INDICATOR

856A

BB15

|-+ +6V
+5V —o

POWER SUPPLY

SWITCHED

L » +15V

-15V —=| POWER CONTROL |+ -6V

+ev—s|

INDICATORS

15-0808

Figure 5-2

PDP-15/C Power Distribution Block Diagram

Table 5-2

PDP-15/C Power Supply Source Distribution

Note

From

P9-2
P9-3
P9-10
P9-11
P9-12
P11-1
P12-2
P12-5
P13-2
P13-5
P14-2
P14-5

H742 Power Supply
H742 Power Supply
H742 Power Supply
H742 Power Supply
H742 Power Supply
H745 Regulator
H744 Regulator
H744 Regulator
H744 Regulator
H744 Regulator
H744 Regulator
H744 Regulator

T1-11 856 Power Supply
P11-4 H745
K03T2 KP Backplane
LO3R2 KP Backplane
ME-15 Memory
T1-6 856 Power Supply
ME-15 Memory
ME-15 Memory
P6-1 BA15 Power Connector
P10-1 BB15 Power Connector
Rows H & J KP Backplane
Rows E & F KP Backplane

+15V
+15V
AC Low
Clock
DC Low
-15V
+5V
+5V
+5V
+5V
+5V
+5V

P3-1
P3-3

861 Power Control
861 Power Control

Lock Switch
Lock Switch

Logic Console Lock
Logic Console Lock

P7-4
P7-6
P7-8

G827 Module Connector
G827 Module Connector
G827 Module Connector

Lock Switch
Lock Switch
T1-14 856 Power Supply

Logic Console Lock
Logic Console Lock
Energizes 856A

T1-4
T1-5
T1=5
T1-6
T1-8

856 Terminal Board
856 Terminal Board
856 Terminal Board
856 Terminal Board
856 Terminal Board

Console
P7-2 G827 Module (Location K03)
ME=-15 Memory
P6-8 BA15 Power Connector
Console

-6V
-15v
-15V
-15V
+15V

5.2.1

861 Power Controls

P15-2
P15-5

H744 Regulator
H744 Regulator

Rows M & N KP Backplane
Rows K & L KP Backplane

+5V
+5V

Relay

There are two versions of the 861 Power Control used in the PDP=15/C:
861-B

180-270 Vac, 1 phase, 16A (20A circuit breaker)

861-C

90-135 Vac, 1 phase, 24A (30A circuit breaker)

The following paragraphs describe the operation of the 861 Power Controls in general terms; Figures
5-3 and 5-4 are simplified schematics of the two 861 modules used in the PDP-15/C.

5-8

r—-

[
|
|
|

AC mpulr_q
L6-20P

~ 1uF TRARF

|
[
|

L
}

[T
——

MPILOT CONTROL BOARD

0%
2

re
g

50ufF

—h
»
1S

Y03

L
N

3]}

vzl
v 2z 3]

3]
CP-0358

Figure 5-3

861B Power Controller Schematic

—-—————--q

PHASE

20A

R AuF
T AuF

ACINPUT
L5-30P

Lo-d

FRILOT CONTROL BOARD

2 3]

2 3]
se[v
CP-0357

Figure 5-4

861C Power Controller Schematic

5-9

Refer to Figure 5-3 or 5-4. Power is applied to the terminal block mounted on the power line filter,
which is an L-type L-C filter with series RF chokes and shunt capacitors to ground. If the rated
voltage is present at the indicator terminals, 11 and/or 12 light. All ac lines are connected to

elements at the circuit breaker CB1. All loads connected to the power controller (both switched and
unswitched) are controlled by CB1.

If the current through any of the ac lines exceeds the rating of CB1, CB1 frips, removing power from

the loads. Power outlets P1 and P2 connect across the circuit breaker output. These outlets are
energized whenever the circuit breaker is closed. Each outlet line from CB1 is connected to a

normally open contact on relay K1.

The field coil associated with K1 is energized by the output

of CB1 if a relay on the Pilot Control Board is closed.

When K1 is closed, ac power is applied across outlets P3, P4, P5, and P6.

The two 0.1 pF capacitors

(C1) connected across the lines at the relay reduce the amplitude of voltage spikes at the output of
the controller when switching inductive loads, thereby preventing interference to nearby electronic
data processing equipment.

Figures 5-3 and 5-4 illustrate the pilot control board simplified circuit schematic.

The pilot control

board contains the circuitry that allows remote turn-on and emergency turn-off of the switched power
outlets (P3, P4, P5, and P6) in all 861 Power Controller versions.

These functions are accomplished

by controlling the voltage applied to the field coil of relay K1 in the 861 Power Controller.
The circuit consists basically of a full wave rectifier loaded by the center-tapped field coil of o relay.

Three control lines connect to the board.
wave rectifier transformer.

Pin 3 connects to the center-tapped secondary of the full

Pin 2 is the disable (Emergency Shutdown) line from the signal bus, pin 1

is the enable (Power Request) line from the signal bus. Two additional lines (from the thermal switch)
are connected to the lines associated with pins 3 and 2.

When the LOCAL/OFF/REMOTE switch is in the REMOTE position and pins 3 and 1 are connected,

current flows through the lower portion of the center-tapped relay field coil to the full wave
rectifier transformer.

This action closes the relay on the pilot control board and causes an energizing

potential to be applied across the field coil associated with K1 in the power controller energizing

the controlled outlets P3, P4, P5, and P6.

When pins 3 and 2 are connected (Emergency Shutdown

is true), current flows through the lower and upper halves of the center-tapped field coil in opposite
directions before returning to the power supply transformer.

The resultant current through the field

coil is less than that required for holding the relay closed.

Energizing potential therefore is not

present at relay K1 and power is removed from controlled outlets P3, P4, P5, and P6.

5-10

Diode D2 provides a current path in the lower section of the coil to prevent closing the relay in
instances where pins 3 and 2 are connected but pins 1 and 3 are not.

Closing T1 (the thermal switch) performs the same function as Emergency Shutdown (connects pins 2
and 3 together). This switch is exposed to the ambient air surrounding the power controller. Temperatures above 160°F close the switch (disabling P3, P4, P5, and P6). The switch resets automatically

when the temperature drops below 120°F.

Placing the LOCAL/OFF/REMOTE switch in the LOCAL position provides a connection between pin 3
and the lower portion of the coil to energize K1, regardless of the state of the Power Request line on
the signal bus. This switch position is normally used for maintenance purposes; operations on the pilot
control board are exactly the same for situations where a connection is provided between pins 3 and 1
of the signal bus connector due to closing of a circuit in an external device. A connection between

pins 2 and 3 disables the switched outlets regardless of the position of the LOCAL/OFF/REMOTE
switch.

The power supply that provides the potential for closing the relay need not be returned to ground.

can be operated in a floating configuration where a connection between pins 3 and 2 (as by the thermal
switch or Emergency Shutdown) disables the switched outlets and a connection between pins 1 and 3
(Power Request) enables the switched outlets.

5.2.2

PDP-15/C Power Supply Adjustments

Table 5-3 lists the monitoring points for adjusting the voltage regulators of the PDP-15/C Power
Supply.

Table 5-3

PDP-15/C Voltage Regulator Adjustments
Regulator

Plug

Monitoring Point

-15V
+5V
+5V

P11
P12
P13

ME15
ME15
BA15, AOTA2

+5V

P14

KP15, FO1A2

+5V

P15

KP15, LOT1A2

CHAPTER 6

OPTIONS
6.1

KE15 EXTENDED ARITHMETIC ELEMENT (EAE)

The KE15 Extended Arithmetic Element (EAE) option facilitates high-speed multiplication, division,
shifting, normalizing, and register manipulation.

The EAE endables fast, flexible, hardware execution of the following signed or unsigned functions.

Shifting the contents of the primary arithmetic registers (AC MQ) right or left, requires
2.91t05.2 ps.

Normalizes the quantity in the primary arithmetic registers, i.e., shifts the contents left
to remove leading binary zeros (or ones in the case of negative numbers) for the purpose
of preserving as many significant bits as possible. The time required is 2.9 to 5.2 ps.

Multiplication is performed in 2.75 to 6.4 ps.

Division including integer divide and fraction divide, require 2.75 to 6.6 ps. Divide
overflow indication is fumished by the link when signed division produces a quotient
exceeding 377777g in magnitude, or unsigned division produces a quotient exceeding
777777g in magnitude.

Basic setup instructions to manipulate the data in the registers prior to execution of the
above instructions require 1,3 ps.

6.1.1

General Operation

Control logic for the KE15 option consists of a 6-bit event time counter, an instruction decoder, bus
control circuitry, load signals, an instruction register, quotient detection circuitry, and other con-

trol flip-flops. In addition to this control logic there is an 18-bit MQ/shift register.
During event time A, AC modifications occur; MQ transfers happen at time B; AC transfers occur at

time C; nothing takes place af time D.

All shifting occurs at time E; complementing takes place at

event time F for multiply and divide operations if necessary.

For further information refer to EAE

flow drawing KE06.

There are four types of EAE instructions: SETUP, SHIFT, MULTIPLY, and DIVIDE.

SETUP instruc-

tions use only four event times while SHIFT, MULTIPLY and DIVIDE instructions use all six event
fimes.

6-1

Figure 6-1 is a general flow diagram for EAE instructions.

Table 6-1 lists EAE instructions and Table

6-2 lists EAE microinstructions.

Table 6-1
EAE Instructions

Octal Code *

Mnemonic

640000

EAE

Operation
Basic EAE instruction.

Acts as an NOP in-

struction.

640001

OSsC

Inclusive-OR the SC with the AC,

640002

oMQ

Inclusive-OR the MQ with the AC.

640004

CMQ

Complement the MQ.

641001

LACS

Load AC12 through 17 with the contents of
the SC.

641002

LACQ

Load the AC with the contfents of the MQ.

644000

ABS

Get the absolute value of the AC.

650000

CLQ

Clear the MQ.

652000

LMQ

Load the MQ with the contents of the AC.,

664000

GSM

Get the sign and magnitude of the AC,

6405XX

LRS

Long right shift.

6605XX

LRSS

Long right shift, signed.

6406XX

LLS

Long left shift.

6606XX

LLSS

Long left shift, signed.

6407XX

ALS

Accumulator left shift.

6607XX

ALSS

Accumulator left shift, signed.

640444

NORM

Normalize.

660444

NORMS

Normalize, signed.

653 1XX

MUL

Multiply.

657 1XX

MULS

MULTIPLY, signed.

6403XX

DIV

Divide.

6443XX

DIVS

Divide, signed.

6533XX

IDIV

Integer divide.

6573XX

IDIVS

Integer divide, signed.

6503XX

FRDIV

Fraction divide.

6543XX

FRDIVS

Fraction divide, signed.

* "XX" indicates the number to be loaded into step counter and depends upon the number of
shifts required or answer precision required.

6-2

Table 6-2
EAE Microinstructions

Bit

Bci:f;re)'

Function

0,1,2,3

1101

SETUP instruction.

Enters AC0O0 into the Link for signed operations.

Clears the MQ.

Reads ACOO into the EAE SIGN register prior to
a signed multiply or divide operation.

6,7

Takes the absolute value of the AC after the
ACOO bit is read into the EAE SIGN register.

[

Inclusive=ORs the AC with the MQ and places

the result in the MQ.
8

Clears the AC,

9,10, 11

000

SETUP instruction code.
bits 15, 16, 17.

9,10, N

001

MUL instruction code.

9, 10, 11

010

Unused instruction code.

9, 10, 11

011

DIV instruction code.

9, 10, 11

101

LONG RIGHT SHIFT instruction code.

9, 10, 1

110

LONG LEFT SHIFT instructions code.

9,10, 1

100

NORMALIZE instruction code.

9,10, 11

111

ACCUMULATOR LEFT SHIFT instruction code.

12-17

6.1.2

Accompanies code in

Specifies the step count for all EAE codes (9=
11) except SETUP.

For SETUP instruction code only, complements
the MQ contents.

For SETUP instruction code only, inclusive=ORs
the MQ with the AC and places the result in
the AC.

For SETUP instruction code only, inclusive=ORs
the AC with the SC and places the result in the
AC.

Normalize Instructions

The NORM and NORMS instructions are commonly used within a subroutine to convert an integer
into a fraction and exponent for use in floating-point arithmetic.

The algorithm for normalize is to

shift the contents of the AC and MQ left until ACOO differs with ACO1.
itive numbers, this results in ACO0 (0) and ACO1 (1).
6-3

For signed, normalize pos-

For signed, normalized numbers the sign (AC00)

[

EAE*F*TS01 L

EAE*F*TS01 H

I KP30
| KP23

;
A EVENT TIME

KEQ4

AC MODIFICATION

SHEET 1

B EVENT TIME

KEO4

MA TRANSFERS

SHEET 1

C EVENT TIME

KEO04

AC TRANSFERS

SHEET 1

D EVENT TIME

KEO4
SHEET 1

NO TRANSFERS

E EVENT TIME

KEQ1

SHIFTING

SHEET 1

F EVENT TIME

KEO4

COMPLEMENTING

SHEET 1

15-030t

Figure 6-1

is first duplicated in the Link.

EAE General Flow Diagram

For unsigned numbers the LINK is usually initialized to 0.

In both

cases the content of MQOD enters AC17, the content shiffed out of ACO0 is lost, and the content of
the LINK enters MQ17, on each shift.

When shifting halts, the contents of the SC reflects the num-

ber of shifts executed to reach the normalized condition.

The SC contents are available through the

use of the EAE OSC or EAE LACS instruction.

For normalized numbers, the binary point is assumed to be between AC00 and ACO1.
the exponent is in the SC.

The value of

The number in the SC, after normalization, is actually the sum of the

pre-established characteristic and the exponent (n) in 2's complement form.

The characteristic is a

number equivalent to the total number of bit positions in the AC and MQ, 36]0 or 448.

The NORMS

instruction contains this number in bits 12 through 17 and loads it into the SC in 2's complement to

establish the exponent in excess 44 code.

when normalized is 20 to 2

This means that the exponential range of the fraction

, or -448 +n.

For example, if the integer +3 is stored in the MQ (MQ16, MQ17 are 1s) and it is desired to convert
this to a fraction and exponent, the following program sequence is required.

NORM(S)

DAC
LACQ
DAC
LACS
TAD (44
DAC

/NORMALIZE CONTENTS OF AC, MQ

/DEPOSIT AC IN MEMORY
/MOVE MQ TO AC
/DEPOSIT MQ IN MEMORY
/MOVE SC TO AC .
/SUBTRACT CHARACTERISTIC FROM STEP COUNT
/DEPOSIT RESULT (EXPONENT) IN MEMORY

In the process of normalization, a total of 33 shifts is required to shift MQ16(1) into ACO1. This
leaves the SC with a step count of:
011100 initialized step count
100001 plus 33 steps
111101

final step count

Because the step count is in 2's complement, the TAD 448 instruction (2's complement add) in effect
subtracts the characteristic from the final step count to arrive at the exponent:
111101

final step count

100100 TAD Characteristic
100001

exponent

In order to save the contents of the SC after a NORM instruction if an interrupt occurs, an interrupt

is held off for 2 cycles after a NORM instruction.

This allows time to store the SC.

Restoration of

the step counter requires that the 2's complemented quantity, taken from the SC at the time of interrupt, be complemented, then combined with the pseudo~NORM instruction.

The step count follow-

ing the TAD, AND operation below is one less (1's complement) than the actual value produced by

the previous normalization (2's complement).

Execution of the pseudo-NORM instruction, then, 2's

complements the step count into the SC, and in shifting the AC and MQ left one bit position adds

the necessary 1 to the SC to produce the correctly restored step count (the 6404XX present in the AC
from TAD, AND operation shifts to become 501XXX).
Restoration program

LAC SCSAVE

XOR (77
TAD (640401

/COMPLEMENT STEP COUNT
/DEVELOP PSEUDO-NORM

AND (640477

/DELETE POSSIBLE STEP COUNT OVERFLOW

HLT
LAC MQSAVE
LMQ

/STEP COUNT TO SC

DAC .+1

/PLACE NORM IN SEQUENCE

LAC ACSAVE

/LOAD THE MQ
/LOAD THE AC

DBR

/RESTORE PC, LINK, ETC.

JMP I SUBENTR

6-5

6.1.3 MUL(S) Instruction

The MUL(S) instruction multiplies the contents of the AC (multiplier) by the contents of the next
sequential core memory location (multiplicand) to form a product in the AC and MQ.
Bits 12 through 17 in the instruction are usually programmed for a step count of 228 (1810), repre-

senting the multiplication of one 18-bit quantity (the sign bit and 17 magnitude bits for MULS) by
another to produce a 36-bit product.

When full precision is not required, the step count may be

decreased by subtracting the appropriate number n from the instruction code. The product is always
scaled 18-n from MQ17.

If n is programmed in the instruction, the 18-n lower bits in the long reg-

ister are meaningless.

For a MUL instruction the link must previously have been initialized to 0.

During the preparatory

phase, the multiplier is transferred from the AC to the MQ, the AC is cleared, and the step counter
(SC) is set to the 2's complement of bits 12 through 17 of the instruction.
the multiplicand into the MI.

A core memory cycle reads

The arithmetic phase, executed as multiplication of one unsigned

quantity by another (binary point of no consequence), halts when the SC counts up to 0 (see Figure
6-2).

For a MULS instruction, a previous LAC/GSM/DAC CAND sequence stores the absolute value of the
multiplicand in memory and places the original sign of the multiplicand in the link.

During the prep-

aratory phase of MULS, a memory cycle reads the multiplicand into the MI, compares the link (sign
of multiplicand) with AC00 (sign of multiplier) and sets the product quotient flip-flop if they differ
and resets the link.

The multiplier is transferred from the AC to the MQ and is complemented if

negative, the AC is zeroed, and the SC is initialized. The arithmetic phase is complete when the
SC counts to 0.

ACO00 and ACO1 each receive the sign of the product; the remaining AC and MQ

bits represent the magnitude. If initially the multiplier and multiplicand had had unlike signs (P/Q
neg (1)), then the resulting MQ after the arithmetic operation would have been complemented.
The algorithm for multiplication using the EAE is simple: add and shift right.
plier is sampled, starting with the least significant bit.

Each bit of the multi-

If the sampled bit is a 1, the multiplicand

is added to the partial product. The partial product and the multiplier are then shifted right one
position for the next multiplier bit sampling.
partial product.

If the sampled bit is a zero, zeros are added to the

With each shift the contents of the least significant bit are lost.

ends when the SC, up-counted with each shift, reaches 0.

Multiplication

START

YES

ACO-+Sign
L ¥ ACO -+ P/Q NEG

SIGN (1)

YES

COMP DIVIDEND

YES

MQ17 (1)

AC + Mt

SHIFT RIGHT

SUM BUS17
> MQO
MQ17 - LOST
CARRY - ACO

MQp— MQp

YES

[

DONE

COMP MQ, AC

—I

]
15- 0302

Figure 6-2

EAE Multiply

Programming Example
Multiply 2,

START

x 5

200

200100

LAC CAND

/Load multiplicand into AC

201

100500

JMS MPY

/Store main program address in 500 and jump
to MPY subroutine

202

200101

LAC PLIER

/Load multiplier into AC

203

MPY

CAND

L
0

/Main program re-entry

500

000202

/Main program address

501

664000

GSM

/Absolute value in AC

502

040505

DAC.+3

/Deposit CAND in 505

503

420500

XCT I MPY

/Load multiplier into AC

504

657122

MULS

/Fetch [CAND| and multiply

505

000002

506

440500

ISZ PC

/Increment main program address

507

620500

JMP I 500

/JMP to main program

100

000002

MULTIPLICAND

101

000005

MULTIPLICAND

AC
0000

(multiplier)

(multiplicand)

0101

0010

OPERATION

1100

0010

ADD

0010

0001

0010

1101

0000

SHIFT
ADD

0001

0000

1001

0010

1110

0010

SHIFT
ADD

0010

0001

0100

0010

1111

0000

SHIFT
ADD

0001

0000

1010
ANSWER =12

0010

0000

SHIFT

Tables 6-3 through 6=15 illustrate the operations that take place in each instruction.
6-8

Table 6-3
EAE NOP 640000

CP State

Event Time

Functions

Drawings

TS02

e e

TS02

MQ-MQ

MQ1-CL
EAE LD MQ H

TS02

KEO4, Sheet 1

KEO4, Sheet 2

AC-AC

EAE ENAB AC L
EAE LD ACL
TSO3

cceeee

KEO4, Sheet 2
KEO4, Sheet 2

Table 6-4
OSC 640001

CP State

Event Time

TS02

TS03

Functions

Drawings

MQ-MQ

amaaea

MQ1-C L

KEO4, Sheet 1

EAE LD MQH

KEO4, Sheet 2

EAE SC-C L

KEO4, Sheet 1

AC - C BUS
EAE LD AC

KEO4, Sheet 2

Table 6-5
OMQ 640002
CP State

Event Time

T502

1502

Functions

Drawings

mmee——

Same as NOP,

=====-

Event Time B

TS02

TS03

C-MQ2L

KEO4, Sheet 1

EAE ENAB AC L

KEO4, Sheet 2

EAE LD ACL

KEO4, Sheet 2

memee——

6-9

Table 6-6
CMQ 640004

CP State

Event Time

TS02

T502

TS02

TS03

Functions

Drawings
————

N I

MQT1-C L

KEO4, Sheet 1

EAE COMPCAL

KEO4, Sheet 2

EAE LD MQ H

KEO4, Sheet 2

Same as NOP,
Event Time C

=—=-am-

e
|m—eemee

Table 6-7
LACS 641001
CP State

Event Time

1502

TS02

Functions

Drawings

e
e

Same as NOP,

=—====-

Event Time B

TS02

TSO3

EAE SC~-C L
EAE LD ACL

KEO4, Sheet 1
KEO4, Sheet 2

emee——

mmaac
|

Table 6-8
LACQ 641002

CP State

Event Time

TS02

TS03

Functions

Drawings

Same as NOP,
Event Time B

-—=—--—-

MQ2-C L

KEO4, Sheet 1

EAE LD ACL

KEO4, Sheet 2

el
"

6-10

Table 6-9
ABS 644000

CP State

Event Time

Functions

Drawings

TS02

EAE ENAB AC L
EAE COMP

KEO4, Sheet 2
KEO4, Sheet 2

ABS *A L IF AC00

KEO4, Sheet 1

EAE LD AC L

KEO4, Sheet 2

TS02

Same as NOP,

| =

——--m-

TS02

Same as NOP,
Event Time C

~——=——--

TS03

Event Time B

meeee-

Table 6-10
CLQ 650000

CP State

Event Time

1502

TS02

71502

Functions
|

Drawings
|

emeea-

MQ1-C L

KEO4, Sheet 1

EAE LD MQ H

KEO4, Sheet 2

Same as NOP,

—=====

Event Time C

TS03

N e

Table 6-11
LMQ 652000

CP State

Event Time

Functions

TS02

EAE ENAB AC L

TS02

Same as NOP,

Drawings

e
e

KEO4, Sheet 2

EAE LD MQH

KEO4, Sheet 2

[

====e-

Event Time C

TSO03

Table 6-12

GSM 664000
CP State

F*TS02

Event Time

‘

Functions

Drawings

EAE ENAB AC L

KEO4, Sheet 2

EAE COMP C-AL

KEO4, Sheet 2

ABS*A L, if

KEO4, Sheet 1

ACO1(1)
EAE LD ACL,

KEO4, Sheet 2

if ACOO(1), SET
LINK
F*TS02

Same as NOP,
Event Time B

= ——e=—-

F*TS02

Same as NOP,
Event Time C

F*TS03

—ce-e-

mmme——|
emeea-

Table 6-13
LRS 6405XX and LRSS 6605XX
CP State

Event Time

F*TS02

Functions

Drawings

MEM4 (1) A

ACO0(1) 1~L
MI 12-17-SC
LOAD SC

F*TS02

Same as NOP,
Event Time B

F*TS02

Same as NOP
COUNT SC L

KP22

KEO4, Sheet 2
|

= ——=eex

KEQO5

(+1)
F*TS03

EAE*TSO1

EAE*TS02

emeem—e

LRS DECODED

KEO4, Sheet 1

L-ACO, AC, -

KPO1-KF18

ACn+1

EAE*TS03
EXECUTE

F
|

AC 17-MQ 00

KEO!

MQ, ~MQp+1

KEO1, KEO2

SC OVERFLO

KEO3, Sheet 1

|
|

emee—-

e
|
mmee-

=emmem
|
mmmeee

6-12

Table 6-14

LLS 6406XX and LLSS 6606XX

Drawings

Functions

CP State

Event Time

F*TS02

Sameas LRS

= —=-—--

F*TS02

Sameas LRS

-—=——-

F*TS02

Sameas RS

= ——=—--

F*TSO3

m————

EAE*TSO]1
EAE*TS02

LLS decoded
L -MQ 17

KEO4, Sheet 1
KEO2

MQO00 ~AC 17
AC, ~AC,
1

KP18
KP17

SC OVERFLO

KEO3, Sheet 1

MQ,, - MQ,_1

===—=—==

KEO1, KEOQ2

EAE*TS03
EXECUTE

mmee—

===

Table 6-15
ALS 6407XX and ALSS 6607XX

Drawings

Functions

CP State

Event Time

F*TS02

Sameas LRS

—=eee-

F*TS02

Sameas LRS

—eee—-

F*TS02

Sameas LRS

—=----

F*TS03

mmee—-

EAE*TSO1

meme—-

KEO4, Sheet 1

ALS is decoded

EAE*TS02

L~AC 17

KP18

KPO1-KP17

1
AC, - AC,

KEO3, Sheet 1

SC OVERFLO

EXECUTE

EAE*TS03
|

—=====

=emeee-

Table 6-16

NORM 640444 and NORMS 660444

CP State

Event Time

Functions

Drawings

F*TS02

Sameas LLS

| @

—=—e--

F*TS02

Sameas LLS

| @

—m——e-

F*TS02

Sameas LLS

—==——-

Table 6-16 (Cont)
NORM 440444 ~nd NIORMS 660444
CP State

Event Time

F*TS03

EAE*TSO1

Functions

Same as LLS

Drawings

NORMS decoded

Same as LLS

emeeea
KEO4, Sheet 1

EAE*TS02

1-F when normalized

EAE*TSO3

T
[
————"

| KE03, Sheet 2

Table 6-17
MULS 6531XX and MULS 6571XX

wwy
CP State

Event Time

F*TS02

;,-t“)B

F*TS02

“-=

Functions
MI 12-17-5C

LD SC

KEO3, Sheet 1
KEO4, Sheet 2

= 13SIGN

KEO5

15°/Q NEG

KEO5

If SIGN(0):
EAE ENAB AC

KEO4, Sheet 2

EAELD MQ H

KEO4, Sheet 2

_ M1 06 (1)%Aco0 (1)

oTM | MI06 (1)*L£ACO0
==

If SIGN (1):
EAE ENAB AC

KEO4, Sheet 2

EAE COMP C-A L

KEO4, Sheet 2

EAE LD MQ H

KEO4, Sheet 2

If MI 08 (1):

0-AC
F*TS03

EAE*TSO1

EAE ENAB AC L
EAE LD ACL

KEO4, Sheet 2
KEO4, Sheet 2

EAE MUL decoded

KEO4, Sheet 1

Ao Iy COUNT SC L (+1)
EAE*TS02

Drawings

KEO5

If MQ17(1):

EAE MI-B L

KEO3, Sheet 2

EAE ENAB AC L
EAE SHIFT RT H

KEO4, Sheet 2

If MQ17 (0):
EAE ENAB AC L
EAE SHIFT RT L

KEO4, Sheet 2

L-ACO0

KPO1

SUM BUS 17-MQ00

KEO1

MQ, - MQ,
_;

KEO1, KEO2

SUM BUS,, -AC,
_1

KP02-KP18

EAE LD AC L

KEO4, Sheet 2

6-14

Table 6-17 (Cont)
MULS 6531XX and MULS 6571XX

CP State

Event Time

EAE*TSO2
(cont)

EAE*TS03

Functions

Drawings

EAE LD MQ H
SC OVERFLO

KE04, Sheet 2
KEO3, Sheet 2

P/Q NEG (1):

KEO4, Sheet 2

COMP MQ

6.1.4 DIV(S) Instruction

The DIV(S) instruction divides the contents of the AC and MQ by the contents of the next sequential
core memory location to form a quotient in the MQ and remainder in the AC.

For a DIVS instruction the link must previously have been set to 0 and remains 0 unless divide overflow occurs. During the preparatory phase, the step counter is set to the 2's complement of the step

count in bits 12 through 17 of the instruction. Bits 12 through 17 of the instruction are usually programmed for a step count of 238 (19]0) unless full precision is not necessary. A core memory cycle

takes place to read the division into the MI. The arithmetic phase, executed as the division of one

unsigned quantity by another halts when the SC counts up to zero (see Figure 6-3).
For a DIVS instruction, a previous LAC/GSM/DAC/DUR sequence stores the absolute value of the
divisor in memory and places the original sign of the divisor in the link. If AC00(1), the sign flipflop is set; if.L is unequal to AC00, the product quotient flop is set. These flops, if set, act to 1's
complement the MQ and AC during the preparatory phase and to perform other complementary functo arrive at the correctly signed quotient as shown on the EAE flow
tions during the arithmetic phase
drawing KE15-0-06.

The algorithm for divide using the EAE is simple: add or subtract, and shifi left. The divisor is first
subtracted from the AC portion of the dividend, and the result is shifted left. If the result is a neg-

ative number (TEMP (1)), the divisor is added to the quotient; if the result is a positive number
(TEMP (0)), the divisor is subtracted (2's complement add) from the quotient. The result is then
shifted left one position for the next sampling. Divide overflow occurs, if in the first subtraction

(aa

the divisor is not greater than the AC portion of the dividend. Divide overflow sets the link and stops

the divide operation.

Programming Example
Divide 12,

+ 5

500

200100

LAC DIWR

/Load divisor into AC

501

100200

JMS D1V

/Store program address in 200 and jump
/to D1V subroutine
/main program re-entry

502

DIV

200

502

/program address

201

664000

GSM

/Store DIVR sign in link and absolute value
/in AC

202

040207

DAC.+5

/Deposit DIWR in 207

203

200101

LAC DIVD1

/Load half dividend into AC

204

652000

LMQ

/Move to MQ

205

200102

LAC DIVD2

/Load half dividend into AC

206

644323

DIVS

/Fetch DIVR and divide

207

000005

210

620200

JMP T 200

/Return to main program

100

000005

DIVR

101

000012

DIVD1

/(Least significant)

102

000000

DIVD2

/(Most significant)

6-16

START

)

MEM 6 (1)

YES

ACO-SIGN
L¥ACO-P/Q NEG

YES

COMP MQ

COMP AC,

YES

SIGN (1)

TEMP (1)

(Wi+1) + AC (SUB)

YES

COMP AC

AC + MI {ADD)

(

DONE

)

L(1) AND NO CARRY
v

L(C} AND CARRY:

TEMP(1): ADD

(0): sUB
L(0) AND NO CARRY
v

L(1) AND CARRY:
1-0

1-TEMP

SHIFT LEFT
NO SHIFT AC

SC OVERFLO

MQ 0~LOST
0-MmQ17

MQr-Man-1

SHIFT LEFT
o-MQ17

MQ 0-AC17

+1-SC

]

SC OVERFLO

SUM BUS 0L

NO SHIFT

15-0303

Figure 6-3

EAE Divide

6-17

Divide Example:

12 +5=2

LINK

TEMP

00000

01010

00101

1010

11011

SUB

10110

10100

1011

00101

ADD

10111

01000

1100

00101

11000

100000

1101

11011

00000

1110

00001 )

1111

11011

SHIFT
ADD

00000
11011

SHIFT
ADD

00101

SHIFT
ADD

00101

SHIFT

SUB

No shift AC because SC OVERFLO full

/ 00010

0000

SHIFT

ADD

00101
00000

SHIFT

00010

Answer

Do one last add because TEMP (1)

(But no Shift)

Table 6-18
DIV 6403XX and DIVS 6443XX
CP State

Event Time

Function

Drawings

F*TS02

Same as MU L except
if MI 06(1)*ACO00(1)
COMPAC:
EAE ENAB AC L
EAE COMP C-AL
ABS*A L
EAELD AC L

KEO5, Sheet 2

F*TS02

KEO5, Sheet 2
KEO4, Sheet 1
KEO4, Sheet 2

SIGN (1):COMP MQ
C-MQ1L
EAE COMP, C- AL
EAE LD MQ H

6-19

KEO4, Sheet 1
KEO4, Sheet 2
KEO4, Sheet 2

Table 6-18 (Cont)
DIV 6403XX and DIVS 6443XX
CP State

Event Time

F*TS02

COUNT SC L(+1)

F*TS03

_—

EAE*TSO1

Check for divide
overflow:
carry on first or
second
if DIV overflow set
LINK
TEMP(0): EAE-MI
-BL
TEMP(1): EAE

EAE*TS02

EAE*TS03

Function

Drawings

KEO5
_—

KEO3, Sheet 2
KP22

KEO3, Sheet 2

MI-BL

KEO3, Sheet 2

EAE ENAB AC L
EAE SHIFT LEFT H

KEO4, Sheet 2
KEO5

SUM BUS 00- LINK
SUM BUS,, -AC,
4
MQ,-MQ,_1

KP22
KPO1-KP18
KEO1, KEO2

Q-MQ 17
Q-TEMP
EAE LD ACL
EAE LD MQ H
SC OVERFLOW

KEQ2
KEO5
KEO4, Sheet 2
KEO4, Sheet 2
KEOQ3, Sheet 2

IF P/Q NEG(1):

COMP MQ
IF SIGN(1):
COMP AC
EAE ENAB AC L

MUL/DIV COMP H
EAE LD AC

KEO4, Sheet 2

KEO4, Sheet 1

KEO4, Sheet 2

6.1.5 IDIV(S) Instruction (See Table 6-19)

The instruction IDIV(S) divides the contents of the AC (integer dividend) by the contents of the next
sequential core memory location to form a quotient in the MQ and a remainder in the AC.

The arithmetic phase of the instruction(s) is identical to that of DIV(S). The preparatory phase trans-

fers the contents of the AC to the MQ and clears the AC. Thereafter the arithmetic phase in reality
performs the division on the long register dividend first as in DIV, with the exception of the most
significant portion of the dividend (AC) is af 0.

6-20

Table 6-19
IDIV 6533XX and IDIVS 6573XX

CP State

Event Time

Function

F*TS02

Same as MUL

F*TS02

Same as MUL

F*TS02

Same as MUL

F*TSO3

EAE*TSO1

Same as DIV

Drawings

EAE*TS02
EAE*TS03

6.1.6 FRDIV(S) Instruction (See Table 6-20)
The FRDIV(S) instruction divides the contents of the AC (fraction dividend) by the contents of the
next sequential core memory location and forms a quotient in the MQ and a remainder in the AC.
The arithmetic phase of the instruction (S) is identical to that of the DIV(S).

clears the MQ.

The preparatory phase

The arithmetic phase is a division of the long register with the MQ at 0.

FRDIV, the binary point is assumed at the left of ACO0.

For FRDIVS the binary point is assumed be-

tween AC00 and ACOT.

Table 6-20
FRDIV 6503XX and FRDIVS 6543XX

CP State

Event Time

Function

F*TS02

Same as DIV

F*TS02

0-MQ:
MQI-C L

KEO4, Sheet 1

EAE LD MQ H

KEO4, Sheet 2

F*TS02

F*TS03

EAE*TSO1

Same as DIV

EAE*TS02
EAE*TS03

6-21

For

Drawings

6.1.7 Indicators

The 18-bit MQ register, 7-bit step counter (6-bits plus overflow), and an 18-bit EAE register are all
accessible from the rotary indicator switch.
control functions.

The EAE switch position indicates the complement of 13

Table 6-21 lists these signals and their positions.

Table 6-21
EAE Indicators

Position

Signal

0
1
2

A (0)H
B(O)H
C()H

3
4
5
6
7
8
9
10
11

D (0)H
E (0)H
F(0)H
-SUH
-EAE MUL H
-EAE DIV SHIFT H
-EAE NORMS H
-EAE LRS H
-EAE LLS H

-EAE ACLS H

13
14
15
16

EAE SIGN (0) H
EAE P/Q NEG (0) H
DIV OVERFLOW (0) H
-EAE FULL H

EAE NO SHIFT H

6.1.8 EAE Execution Times
Set Up

1.32 ps

Shifts

2.75 ps + 130 ns/step

MUL + D1V 2.75 ps + 260 ns/step

6.2 KW15 REAL-TIME CLOCK
The KW15 Real-Time Clock option, when enabled, increments location 00007 at a rate specified by
a clock in module slot LO3.

The M515 mcdule, usually supplied with this option, increments every

16.7 ms in 60 Hz systems and every 20 ms in 50 Hz systems.

An M401 variable clock may be used

instead of the M515.
The 10T's for the Real-Time Clock are:
CLSF

700001

Skip if Clock flag is set

6=-22

CLOF

700004

Clear Clock Flag and disable clock

CLON

700044

Clear Clock Flag and enable clock

When the CLON IOT is executed, the CLK EN flop is set (see KP57) this enables the CLK REQ flop
to be set at the clock frequency if the console is locked or the CLK switch on the console is enabled

(front of switch depressed).

The CLK REQ is synchronized to the 1/O as described in Chapter 4 and

a DCH word count cycle is used to increment location 00007,

When location 00007 increments from all 1s to all Os, a clock overflow occurs and the CLK FLAG is
set.

This flag is interfaced to the PI and APl whose entry address is 51.

The clock will continue to

count up from zero after overflow until location 00007 is reinitialized or the clock is turned off.
Figure 6-4 is a flow diagram of the Real-Time Clock operation.

6.3

KF15 POWER FAIL OPTION

The KF15 Power Fail option protects the PDP-15 computer system from loss of power by providing a
means of storing important CP registers, upon loss of power, and the subsequent restoration of these

registers and restarting of the program when power returns.

Whether the option is installed or not, the system is always power cleared when turned on or off.

With the option installed, there are three ways in which power failures are handled.
If the console is not locked, the system acts exactly as though the power fail option is not installed.
A power low condition is detected by the G827 on KP57 which clears the CP RUN flop at the end of

the current instruction in progress.
tion.

INT reset pulses are then generated until the logic cannot func-

When power is restored, a series of INT reset pulses are produced as soon as there is enough

power to supply the logic.

This burst continues 750 ps after the POWER OK line goes positive.

The

single power fail 1OT instruction is:
SPFAL

703201

Skip on power fail flag.

The other two modes of operation are with the console locked and the machine with PI or API enabled.
When the power failure is detected as above, a power fail program interrupt request or API request is
made.

In the case of API, a level 0 API request is made, synchronized, and location 52 is executed.

JMS should be in this location and the subroutine should store all CPU registers in memory, place a
jump to a restart routine in location 0 and then halt.

6-23

[

CLON

J KP58

CLOCK ENABLE

]

KP57

CLOCK FREQUENCY ] KP57
LOCKED OR
CLK SWITCH

ENABLED

(

Ci.K RQ

END

KP57

]

KP51

)

TIME 4 ———.é
TIME 1 ——-—-’%
l

CLK SYNC

l KPS1

0~ CLKRQ

| KP57

DCH WORD COUNT
CYCLE TO iN-

KDO4

CREMENT LOC 00007

[

CLK FLAG

]
AND
FUNCTION

18-0134

Figure 6-4

Real-Time Clock, General Flow Diagram

6-24

KP57

DETECTED BY G827

L POWER GOING LOW

MONITORING +11V
__’LINE
FROM THE

KP57

POWER SUPPLY

POWER LOW

PLUS 250 us

KP57

POWER LOW-DLY —I

KP57 |

~POWER UP

KP50 I

INT RESET

O
|

15-0308

Figure 6-5
Power Fail Sequence With
Power Fail Option Disabled, Flow Diagram

[

POWER COMING UP 1

L = POWER OK

KP81

= POWER UP

KP57

INT RESET

KP41

TIME 1

—POWER OK
+750 us

IMachine power fully restorgl
15-0305

Figure 6-6
Power Restore Sequence With
Power Fail Option Disabled, Flow Diagram

In the case of PI, a program interrupt break is performed and the power fail flag detected by the power

fail skip (SPFAL).

A subroutine should then store the CPU registers, place a jump to a restart routine

in location 0 and then halt.

6-25

When power is restored, the machine executes the instruction which was stored in location 0 which
restores the registers and returns the machine to its previous program sequence.

[ POWER GOING DOWN ]
[

;

+250 us

I
[

POWER LOW

J KP57

l
l

POWER LOWDLY J

POWER FAIL

KP527

J KP57
KP57
NO

API

— POWER UP

I KP57

YES

[

Time 1

PWR FAIL

J KP57

POWER FAIL Pl

to program

interrupt

INT RESET

I KP 50

To AP} Logic

KP69

redusst
logic

KP50

16§-0307

Figure 6-7 Power Fail Sequence With
Power Fail Option Enabled, Flow Diagram

6.4 KA15 AUTOMATIC PRIORITY INTERRUPT (API)

The KA15 Automatic Priority Interrupt (API) option is located in the BB15 option panel. The option
consists of standard M Series logic with no special modules. The API logic for the internal options,
i.e., Power Fail and Real-Time Clock, is contained within the API option. All communications to

external devices using the API facility are handled by the standard 1/O bus cables. One additional
control cable is necessary for communication between the PDP-151/0 processor and the API option.
All external devices using the API facility will be required to use the M104 module or its logical
equivalent.

6.4.1

See Chapter 4 for a description of the M104 Multiplexer module.

General Description

The API option increases the 1/O handling capabilities of the PDP-15 by adding eight levels of prior-

ity servicing for up to 28 1/O devices along with four software channels for a total of 32 API channels.

6-26

I POWER COMING UP

-POWER OK

Kpr57

[

-POWER LP

KP57

INT RESET

MEM POWER UP

TIME 1

KPGO

KP57

250 us

POWER ON

AUTO RESTART

—l

KP57

KEY ACTIVE

KP34

START RUN

KP34

KP21

[

RUN

:
INSTRUCTION IS
FETCHED FROM
LOCATION 0 AND
EXECUTED

_.é AND

FUNCTION

LEGEND
1.

Power turned on

-Powerup L * Time 1 = INT RESET

-KP57 POWER OK L goes high

KP57 POWER LOW DLY L goes high

750 usac. later, power is enabled to memory

6.,

250 usec. later, KP POWER ON H clocks Auto-restart

18-0306

Figure 6-8 Power Restore Sequence With Power
Fail Option Enabled, Flow Diagram

6-27

The four highest priority levels (0, 1, 2, and 3) have a higher priority than the program interrupt
facility and main program operation, but a lower priority than the single-cycle DCH and real time
clock operations. The four lower priority levels (4, 5, 6, and 7) have a higher priority than the main
program operation, but a lower priority than program interrupts, the four higher AFI levels, singlecycle, DCH, and real-time clock operation.

Each of the 32 channels (0-378) has its own unique entry point to its specific service routine.

These

entry points are memory addresses 40(8) -77(8) in page 0 of bank 0 in the main memory (see Table
6-22)
Table 6-22

Standard API Channel/Priority Assignments

Octal

Channel
Number

Device.

Device Name

nemonic

| = ====-| = =mee-—| = ——==a| = ===--TC02, TC15
TC59

Priority
Level

Unique
Entry Point
o

4
5
6
7
1
1
]
1

40
41
42
43
44
45
46
47

Assigned

ctal Address

0
1
2
3
4
5
6
7

Software Priority
Software Priority
Software Priority
Software Priority
DECtape
Magtape
Not assigned
Not assigned

10
11

High Speed Tape Reader
Real Time Clock

PC15
KW15

2
3

50
51

12
13
14
15
16
17
20
21
22

Power Fail
Memory Parity
Display Control
Card Reader

KF15
MP15
VP15 or VT15
CRO3B

Line Printer Control

LP15C or F

A/D Conv.
Inter Processor Buffer

AD15
DBO?

0
0
2
2
3
0
3

637 Data Phone

DP0O9

52
53
54
55
56
57
60
61
62

23
24

DEC Disk Control
Disk Pack Control

RF15
RP15

1
1

63
64

Plotter

XY 15

26
27

30
31
32
33
34

Display

340

Teletype Keyboard
Teletype Printer

LT19/LT15A
LT19/LTI5A

DECtape (DCH channel 36)

TC02/TC15*

Dataphone

66
67

DP0O9*

3
3

71
72
73
74

NOTE: The above table channel assignments should remain fixed for software compatibility, but the
suggested priority levels may be changed at the discretion of the user.
*Channel allocated for system with more than one of the above options.
6-28

The highest four levels of priority, i.e., 0, 1, 2, and 3 are assigned to hardware devices.
four levels, i.e., 4, 5, 6, and 7 are assigned to the four software channels.

The lower

Of the 28 hardware

channels, no more than eight can be multiplexed on any one of the four priority levels. This is
strictly a hardware limitation imposed by cable lengths and circuit delays, and attempts to circum-

vent this restriction will create needless problems.
Each device, when granted service via the API facility, sends its specific entry point address to the

computer.

This address, which will contain a JMP or JMS instruction
to the device service routine,

will then be executed by the computer.

This type of interrupt service eliminates the need for time

consuming flag search routines, and extensive core use for interrupt handling routines, by automatically determining which device requested service and providing immediate entry to the proper service
routine.

Higher priority devices will be able to interrupt lower priority routines upon sending and having a
request granted. The priority of devices multiplexed on the same priority level is determined by the

relative position of the devices on the I/O bus.

The first device on the bus having highest priority

at that level, the second having second highest priority, etc.
The entire API facility can be enabled or disabled by a single 10T instruction.

enable or disable specific priority levels or devices.

There is no way to

A device may, however, disconnect itself from

the API facility by merely clearing its flag in much the same way as it disconnects from the program
interrupt facility.

In addition to the above, there are two special features in the API facility.
a.

These are:

The CAL Instruction - Execution of a CAL instruction with the API facility enabled automatically sets priority level 4 thereby shutting out software requests of a lower priority
until this level is released.

Program Interrupt - A program interrupt, from any 1/O device connected to the computer,
sets priority level 3. This occurs whether or not the API facility is enabled. This causes
all devices on priority level 3, all software requests and program interrupts to be shut
out until the level is released.

Special care must be taken in the programming of the API option to take account of these two features.

6.4.2 Operational Description

There are three sources of request for service to the API facility. They are hardware (I/O devices),
software (program requests), and test requests (maintenance aid).

The requests are handled in the

same way by the API facility regardless of the source (see Figure 6-9).

6-29

The only difference in the requests is their level of priority; the hardware having the highest and the
software lowest, The test requests are used by the diagnostic program to simulate hardware requests.

When an API request is received, the appropriate RQ flop will be set at /O processor Time 4, if the
API facility is enabled, and if there is no API operation in progress [API SYNC (0) H]. Refer to KAQ4
and KAQO1.

The RQ flop is compared against its associated priority level (PLOO through PLO7, KAO2 and KAO3) and,
if it is enabled, a RQ SYNC level is generated (see Figure 6=10).

The RQ SYNC of all eight priority

levels are ORed together and used to generate a CP API RQ signal (KA04 and KP35). It should be
noted that the priority level is enabled when the PL flip=flop is reset.
The CP API RQ level is sent to the CPU where it informs the processor that the API facility is request-

ing service.

If it is a hardware request, i.e., level 0-3, the program interrupt facility of the CPU is

disabled. The API interrupt is handled by the CP and 1I/O processors in the same way as a program
interrupt (see Figure 6~11).

Once the CPU and the IPU are ready to handle the API interrupt, the API SYNC flop (KP51) in the
[PU is set at IPU Time 1.

The API SYNC flop is used to set the enabled APl GRANT flop (KAO1) which in turn sets the EN A

flop in the 1/O device to allow the device to send its unique entry address to the IPU via the 1/O bus.
API SYNC is ANDed with IPU Time 3 to clear the APl GRANT flop and is also ANDed with IPU Time

4 to set the PL flop corresponding to the priority level of the request.

The setting of the PL flip~flop

disabled this priority level and all lower levels until a DBK or DBR instruction clears out the PL flop.

With API GRANT on a zero, the next I/O SYNC pulse (IPU Time 1) will clear the EN A flop in the
device,

The following are IOTs used in the API option.

Refer to the PDP=15 Systems User Handbook for 10T

descriptions.

10T

Mnemonic

Name

703304

DBK

Debreak

703344

DBR

Debreak and Restore

705501

SPI

Skip on Priorities Inactive

705504

ISA

Initiate Selected Activity

705512

RPL

Read API Status

707742

RES

Restore

6-30

ISA

10T

[

DEVICE

1SA

FLAG

10T

1/0 SYNC

PUT

APt SYNC

P SYNC

SETPLO3

]

KPS1

SOFTWARE
REQUESTS

KP51

FROM CP

DEVICE

REQUESTS

KAO1

APl

KAO1

TEST
REQUESTS

KAOS
KA02, 03

RQ SYNC

1 KAQ2

API REQUEST

I KAO1

SET

API GRANT

DISABLE THIS

[

PRIORITY LEVEL

IPUTA

KPS1

KP51

PUTS

AND ALL LOWER

T0 DEVICE

LEVELS

KAO1
4

IPUT3

KP51

SETS EN “A”

API 00-03 RQ L

API

RO SYNC 04-07 L

APl

ENABLE (1)

SYNC {0}

CAL INST

KA1

KAD1

APl ENABLE (1)

}

SET APl RO

1 KAD!

KP51

API STROBE

I KA04

PL F/F SET

—|—-> PRIORITY LEVEL

KAQ2

SET

PL 04

DISABLE THIS LEVEL

kam

KAOZ, 03

API GRANT (0) AND

APIRQL
l

]

[

KAD4

RQ F/F

PROGRAM INTERRUPT |

PL ENABLE

KP35

F/F RESET

RQ SYNC

KA02, KAO3

DISABLES THIS

NEXT 1/0 SYNC

AND ALL LOWER

“ATM IN DEVICE

LEVELS

{IPU T1) CLEARS EN

KAD1

DISABLES
KAQ3

GRANT

RQ F/F SET

—PLO3 ENABLE

CLEAR API

KAD2, KAO3

KAO02, KAG3

AND ALL LOWER
PRIORITY LEVELS

AND

FUNCTION

CP API RQ

KAO4

TO CPU, IPU

KP35

15-0310

Figure 6-9

API Flow Diagram

6-31

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N_.€z05S1LalvOoILANYHILN—I_owailrW1_|—1iHdN1<YdOLI1YdSO<0«N1L3AN4SYr|—_1SLzGESaddxAx_1dNHILNa*I<LALVIS_—|_<0tL1ddV1vY<dlIv1N<O0ILN3OA4SV,Nl|_—’LsfSladr)_onyav-vsnaE.c__W18QA
03y a3LigiHNI
N
O
0
d
d
3

WYHOUd o3y

H3d43H OL 1dV MOT4

63WUON9YDId

—_LH4dNYE1BILdDN

Figure 6-11

6-35

60€0-GI

API/P1/Central Processor
Flow Diagram

6.5 MP15 MEMORY PARITY

The MP15 Memory Parity option provides a continuous check of information being read from core
memory, to determine whether bits are being picked up or dropped.
all information as it is being sent to the memory for storage.

It does this first by monitoring

If there are an even number of bits in

the data word, the MP15 control causes memory to write the parity bit, thus making the total number

of bits odd.

If there are an odd number of bits in the data word, 1_'he MP15 control inhibits the mem-

ory from writing the parity bit.

The word is stored with an odd number of bits.

When information is

read from core, the parity control checks to see that an odd number of bits are read.
it finds an even number, then a parity error has occurred.

If, per chance,

The parity error flag, which is set upon

detection of an error, may be used to cause an APl interrupt, a program interrupt, a skip request, or
an immediate stop of the processor.

To perform the task of writing or not writing the parity bit into core, the MP15 needs time to calculate
parity once it knows that data is present on the MDLs.

it has calculated that the bit is needed.

It also needs time fo generate the bit, once

Since the only way the MP15 knows that data is present is

by MRLS, and since memory will not use the data until it receives MRLS, the MP15 interrupts the
MRLS line of the memory bus and inserts a delay.

Refer to MP10.

When the delay times out, MRLS is redriven onto the memory.

The length of the delay time has been

calculated to allow for worst case propogation times in the parity detection and parity bit circuitry.
Time is also required to perform the task of checking parity as information is read from memory.

The

only way the MP15 can know that data is coming from memory to the CP and is present on the MDLs,
is by RD RST; the RD RST line of the memory bus is broken and the signal delayed.
times out, RD RST is redriven to the CP.

When the delay

The delay time has been calculated to allow for worst case

propogation time in the pdrify detection network. Refer to MP10.
The parity error flag, called PAR ERR, may be used in one of four ways.

It is connected to the pro-

gram interrupt facility, the automatic program interrupt facility, the skip facility and the CP stopping

network.

A switch is provided for the purpose of selecting whether or not the computer should stop

upon detection of a parity error.

The parity error channel address for the API is address 53 and the

level is 0.

For maintenance purposes, the ability to force wrong parity to be written has been provided.
ample follows:
.LOC

100

Fwp
DAC 200
CPE

/SET WRNG PAR FLOP
/WRITE WRONG PARITY
/MAKE SURE PAR ERR CLEAR

6-37

An ex-

LAC 200
SPE
HLT
CPE
JMP 100

/SHOULD SET PAR ERR
/SKIP IF PAR ERR (1)
/PARITY ERROR NOT SET
/CLEAR PAR ERR
/DO IT AGAIN

The RD PAR and WR PAR flops are connected only to the indicators on the BB15 indicator panel.
RD PAR is a 1, the parity bit has been read from core.

When

When WR PAR is set, the parity bit has been

written into core.

The M WRITE flop determines in which direction information is going.
memory, M WRITE is set causing MRLS to be delayed.

If data is being written into

If data is coming from memory, M WRITE is

cleared causing MRLS not to be delayed.

The M182 module is a parity detector and contains two high speed parity circuits.

Each circuit indi-

cates whether the binary data presented to it contains an odd or even number of 1s.

The data and its

complement are required for inputs.
V1.

Indication of odd parity is given by a HIGH level at pins K1 and

Pins L1 and V2, when HIGH, indicate even parity or no input.

Table 6-23 contains the instruction set for the MP15.

Table 6-23
MP15 T1OT Instructions

Mnemonic

Octal Code

Operation Executed

SPE

702701

Skip on Parity Error Flag

CPE

702702

Clear Parity Error Flag

FWP

702704

Force wrong parity (maintenance only)

6.6 KM15 MEMORY PROTECT
The KM15 Memory Protect option provides the PDP-15 with memory protection capabilities.

boundary register which establishes the lower limit of the user's program.

It has a

It also has facilities to trap

I0Ts, HLTs, OASs, XCTs of XCTs, boundary violations, and addressing of non-existent memory banks.

The KM15 slows down the computer by 30 ns or 175 ns, depending upon certain restrictions.

allows addressing below the boundary on all Read instructions except JMP and ISZ.
modes of operation in the PDP-15 protect system:

User mode and Monitor mode.

It also

There are two

In Monitor mode,

the protect hardware is disabled and the machine functions as it would without protect hardware.
When in User mode, the protect hardware is enabled.

6-38

The KM15 also makes use of the memory data lines and the 1/O bus.

The following signals are used

as control signals between the KM15 and the processor, and the memory:
M REQ

ADDR ACK

TRAP

RD RST

NEXM

INT + APIST

USER MODE

RESTORE UM

SET FETCH

CP ACT

The KM15 is activated by the IOT, MPEU.

on the next ADR ACK.

DEFER

This first sets PRE which in furn conditions UM to get set

With PRE and UM set, the KM15 monitors instructions as they are read from

memory, and the addresses of core locations being referenced.
core, a register is used to save the instruction.

To monitor the instructions read from

The signal used to sirobe the instruction register is

also put through a delay and used to strobe the decoding networks after the instruction register has
had time to settle.
is checked.

To monitor addresses, M REQ is stopped from going to memory until the address

The circuitry for this is the M214 which contains an adder.

When the addition of the

boundary register and the address is performed, if a carry is generated, the address is less than the
boundary register.

If the memory protect logic detects an illegal instruction, (HLT, OAS, IOT, XCT OF XCT), or an
address below the boundary register which is preset by the programmer, or a reference to a nonexistent memory, then the TRAP process begins.

Since a HLT or an OAS may be micro-coded with

other operate instructions, the HLT or OAS function is inhibited and the other portions of the micro-

code are allowed to be executed before the trap interrupt occurs.
20, if PIE is not set, and to O if PIE is set.

The trap interrupt goes to address

It operates essentially the same as a CAL or a program

interrupt insomuch as it stores the LINK, BANK MODE, USER MODE, and PC+1 in 20 or 0.

are two exceptions to this.
will be saved.

There

If it is a jump below the boundary, the address to which it tried to jump

If it is a jump indirect to a non-existent memory, the address +1 in the non-existent

memory will be stored.

Refer to the flow diagram shown in Figure 6=12.

The operation of the trap is as follows.

When an

illegal instruction is decoded in the KM15 (HLT, OAS, XCT of XCT, or IOT) the PV flop and the

TRAP flop are set.

TRAP is sent to the processor to sync it up for the interrupt.

1 time, INTERRUPT ACK is set.

At TS03 and PHASE

At TSO3 and PHASE 2 time, the major states are reset to EXECUTE.

This forces the computer to produce a SET FETCH signal which is needed to produce an EN INTERRUPT,
EN INTERRUPT and TRAP produce PI REQ which syncs up the computer for a program interrupt in the

normal fashion.

Bit 13 is enabled for the address if PIE is a 0 so that the interrupt goes to 20.

INTERRUPT STATE (1) goes up to the KM15 and clears TRAP and PRE.

6-39

It also inhibits UM from being

cleared until the ADR ACK following the write cycle of the interrupt.

This is to allow UM (1) to be

saved in 20 or O.

If the violation is a boundary violation, it is detected before M REQ is allowed to go to memory; M
REQ is inhibited from going to memory until the CP has synced up for a trap.
TRAP is set as soon as the violation is detected and will start the sync up process at TS03 and PHASE
1.

If the violating instruction is a write instruction, TRAP produces a pulse in the processor called

TRAP P which clears
tinve.

M REQ.

It also produces an ADR ACK so that the processor time states may con-

END OF CP CYCLE is forced by TRAP, START WRITE, and M REQ (0).

WRITE also disables CP MEM REQ HOLD.

TRAP and START

Therefore, another M REQ will not occur until the inter-

rupt.

A non-existent memory violationis detected by timing out adelay started by

is not received within 500 ns, then NEXM is set.
the M REQ from the bus.

M REQ OUT.

This forces PV and TRAP.

If an ADRACK

TRAP and NEXM remove

The functions in the processor are the same as those for a boundary viola-

tion on a write instruction as discussed in the preceding paragraph.
A CAL, PI, or API will cause user mode tc be turned off and no violation will occur.
PI will save the state of user mode.

The CAL and

On an API break, the instruction in the break address must be a

JMS, JMS 1, or CAL if the state of USER MODE is to be saved.

If USER MODE is on and the program tries to address non-existent memory, a TRAP occurs.

The non-

existent memory flag gets set; the computer restarts in a CAL just like any other violation.

If USER

MODE is OFF and the program tries to address non-existent memory, the computer hangs up and the

non-existent memory flag gets set.
Although the KM15 introduces a delay to the computer, it is only 30 ns when not in USER MODE,

when the 1/O is active, or when in USER MODE and during any read function, except JMP or ISZ.
The only time the cycle time is increased by 175 ns is with USER MODE and doing a write function,
a JMP, or an ISZ.

The KM15 has the following instruction set:
MPSK

701701

Skip on memory protect violation flag.

MPCV

701702

Clear memory protection flag.

MPLD

701704

Load boundary register.

MPSNE

701741

Skip on non-existent memory flag.

MPEU

701742

Enter User Mode.

MPCNE

701744

Clear non-existent memory flag.

6-40

[

M REQ IN

—l KM11

M REQOUT

KM11

NORMAL MACHINE
OPERATION

KM11

L ADDRESS CHECK —l KM13, 14

BOUNDARY
VIOLATION

KM13

}

| KM11

M REQ OUT

1-MEM OK

] KM10

500 NS DELAY

—I KM10

ADR ACK

STROBE E NE NEXM

I KM10

| KM10

‘

RD RST

[

'
STROBE IR

j KM10

0~MREQ

I KP26

L END OF CP CYCLE ] KP32
TSO03-PHASE 1- TRAP

KP35

15INT ACK

0->MEM OK

|
[

1-TRAP. PV

YES

‘

1-INT STATE

0~TRAP, PRE

KM10

NO EFFECT ON

I KM10

MACHINE OPERATION

*ADDR ACK

T oss

%% NORMAL INTERRUPT FLOW

NOT RECEIVED

INST. DECODE

] KmM10

ILLEGAL

1>TRAP PV

INSTRUCTION

1 KM10

L m RiQ IN

1 KM11

L MRE;OUT

—l KM11

—I

CONTINUE TO NEXT

MEMORY CYCLE

ADR ACK

!
TS03:PHASE 1-TRAP
1-INT ACK

RD IST j

L1~>INT;TATE j KP35
L 0-TRAP, PRE

* % ADDRESS TO WHICH TRAP INTERRUPT
IS 20 IF PIE(0) AND 0 IF PIE (1)

GOES

Figure 6-12

] KM10

**%NORMAL INTERRUPT FLOW

KM15 Memory Protect Flow Diagram

6-41

_I KM10

15-0313

6.7 KT15 MEMORY PROTECT AND RELOCATE

The KT15 provides the PDP-15 with memory protection and relocation capabilities. It has the facil-ities to trap IOTs, HLTs, OASs, XCTs of XCTs, and address non-existent memory banks. It also has
a core allocation register or upper boundary register which specifies the last 256 word page allocated
to the user, and a relocation register which specifies the first address to which the user's program
will be relocated. The KT15 slows down the computer by 165 ns or 365 ns, depending upon certain
restrictions. In addition, it does not allow the user to go above the boundary for read instructions.

There are two modes of operation in the PDP-15 protect and relocate system: User mode and Monitor
mode. In Monitor mode, the relocation and protect hardware is disabled and the machine functions

as it would without protect hardware. The program running in Monitor mode addresses real locations
within the system. In User mode, the relocation and protect hardware is enabled. The machine is

programmed as though the user had the machine all to himself. His memory begins from location O
and goes up to and includes the last 256 word page specified by the core allocation register (upper
boundary register). In the real machine, the program is located from the content of the relocation
register up, with the exception of 1/O operations and the CAL instruction; the user virtually has
machine to himself and programs it that way.

The KT15 provides the PDP-15 with memory protection, and relocation capabilities. The following
signals are used as control signals between the KT15 and the CP and the memory.
DEFER

M REQ

ADDR ACK

TRAP

RD RST

NEXM

INT + API ST

USER MODE

RESTORE UM

SET FETCH

CP ACT

The KT15 also makes use of the memory data lines and the 1/O bus. The KT15 is activated by the
IOT, MPEU. Prior to issuance of this instruction, the core allocation register should be set to equal
the last 256 word page available to the User. The relocation register should be set to the first address to which the user is to be relocated. The relocation register is a nine bit register containing

bits 01-09. The IOT, MPEU, first sets PRE. On the next ADR ACK, UM gets sef. With PRE and

UM set, the KT15 monitors instructions as they are read from the memory and addresses of core loca-

tions being referenced.

To monitor instructions read from core, a register is used to save the instruction. The signal used to
strobe the instruction register is also put through a delay and used to strobe the decoding networks
after the instruction register has had time to settle. To monitor addresses, M REQ is prevented from

6-42

going to memory until the address is checked.
adder.

The circuitry for this is the M214 which contains an

When the addition of the boundary register and the address is performed, if a carry is gen-

erated, the address is greater than the last address of the 256 word page specified by the boundary
register.

If the KT15 logic detects an illegal instruction, (HLT, OAS, IOT, XCT of XCT), or an address
greater than the last address of the page specified by the boundary register, the trap process begins.
Since a HLT or an OAS may be microcoded with other instructions, the HLT or OAS function is inhibited and the other portions of the micro-code are allowed to be executed before the protect violation occurs.

If UM and PRE are set and the CP is active, the relocation portion goes into action upon receipt of
M REQ at the KT15.

The MDLs 01-09 are added to the contents of the relocation register and the

results placed on the MDLs to the memory along with the other address bits 10-17. Therefore, the
actual address which the memory sees is the sum of the address sent from the processor and the contents
of the relocation register.

The checking of the address for a violation and the modifying of the ad-

dress for relocation takes place in parallel to minimize slow down of the computer.
The trap interrupt goes to address 20 if PIE is not enabled, and to O if PIE is enabled.

ure 6=13.

The trap interrupt operates essentially the same as a CAL or a program interrupt in as much

as it stores the LINK, BANK MODE, USER MODE, and PC+1 in 20 or 0.
to this.

Refer to Fig-

There are two exceptions

If it is a jump above the boundary, the address to which it tried to jump will be stored.

it is a JMP indirect to non-existent memory, the address +1 in the non-existent memory will be stored.

The operation of the trap is as follows.

When an illegal instruction (HLT, OAS, XCT of XCT or IOT)

is decoded in the KT15, the PV flop and the TRAP flop are set.

TRAP is sent to the processor to sync

it up for the interrupt.
At TSO3 and PHASE 1 time, INTERRUPT ACK is set. At TSO3 and CLOCK H time, the major states are

reset to EXECUTE.

This forces the computer to produce a SET FETCH signal which is needed to pro-

duce EN INTERRUPT.

EN INTERRUPT and TRAP produced PI REQ which synchronizes the CP for a

program interrupt in the normal fashion.
terrupt goes to address 20.

Bit 13 is enabled for the address if PIE is a O so that the in-

INTERRUPT STATE (1) goes up to the KT15 and clears TRAP and PRE.

also inhibits UM from being cleared until the ADR ACK following the write cycle of the interrupt.

This is to allow UM (1) to be saved in address 20 or 0.
If the violation is a boundary violation (core allocation violation), it is detected before M REQ is

allowed to go to memory, and M REQ is inhibited from going to memory until the CP is synchronized

for a trap.

As soon as the violation is detected, TRAP and PV are sef and start the synchronization

process at TS03 and PHASE 1.

6-43

M REQ IN

KM11

KM11
M REQOUT
KM11

NORMAL MACHINE
OPERATION

!
GENERATE
NEW ADDRESS

KT15, 18

ADDRESS CHECK

l KM13, 14

'
NEW ADDIRESS

TOMDL'S

BOUNDARY S YES

KT12

VIOLATION

M REQ OUT

KM11

[

1-MEM OK

KM10

DELAY

1-TRAP, PV

KM10

KM10
KP31
YES

ADR ACK

0-MEM OK —I KM10

RD RST

STROBE I R

]

—l

[

]

KM10

YES

[

0+M REQ

END OF CP CYCLE

KM10

NO EFFECT ON

KM10

KP26

—l

KP32

If?;:x‘f T'TRAP

MACHINE OPERATION

KP36

% ADDR ACK

STROBE NEXM

NOT RECEIVED

INST DECODE

KM10

ILLEGAL

TINTSTATE
l

kP35

0 >TRAP, PRE

KM10

CONTINUE TO

INSTRUCTION

NEXT MEMORY CYCLE

T503 - PHASE 3 CLOCK

STOPS, WAITS FOR

INTERRUPT STROBE

1-TRAP, PV

KM10

KM11

M REQ OUT

‘

]

KM11

ADR ACK

]

LANT ACK

;

KP35

TS03-PHASE 1-TRAP

‘

%% ADDRESS TO WHICH TRAP INTERRUPT GOES

% ¥NORMAL INTERRUPT

1-INT STATE

] KP35

0~TRAP, PRE

] KM10

FLOW

**¥NORMAL INTERRUPT FLOW

*NORM

15 20 IF PIE(0) AND 0 IF PIE (1).

15-0312

Figure 6-13

KT15 Memory Protect/Relocate
Flow Diagram

6-44

If the violating instruction is a write instruction, TRAP produces a pulse in the CP called TRAP P
which clears

M REQ.

It also produces an ADR ACK so that the CP time states may continue.

OF CP CYCLE is forced by TRAP, START WRITE, and
M REQ (0).

END

TRAP and START WRITE also dis-

ables CP MEM REQ HOLD to prevent another M REQ until the interrupt.
A non-existent memory violation is detected by timing out a delay started by
ACK is not received within 500 ns then NEXM is set.

removes the M REQ from the bus.

M REQ.

This forces PV and TRAP set.

If an ADR
TRAP and NEXM

The functions in the processor are the same as those for a boundary

violation on a write instruction as discussed in the preceding paragraph.
A CAL, PI, or API will cause User mode to be turned off and no violation will occur.

PI will save the state of User mode prior to clearing the UM flop.

On an API break, if the state of

User mode is to be saved the break address must contain a JMS, JMS I, or a CAL.
on and the program tries to address non-existent memory, a TRAP occurs.

and the computer restarts in a CAL just like any other violation.

The CAL and

If User mode is

The NEXM flag gets set,

If User mode is off and the program

tries to address non-existent memory, the computer hangs up and the NEXM flag gets set.

The KT15 has the following instruction set:
MPSK

701701

Skip on memory protect violation flag.

MPCV

701702

Clear memory protect violation flag.

MPLD

701704

Load core allocation register.

MPSNE

701741

Skip on non-existent memory flag.

MPEU

701742

Enter User Mode

MPCNE

701744

Clear non-existent memory flag.

MPLR

701724

Load Relocation Register.

Figure 6=14 is a block diagram showing the interconnection of the MDL lines with the Relocate and
Boundary Registers.

6.8 PC15 HIGH-SPEED PAPER-TAPE READER/PUNCH
The PC15 High Speed Reader/Punch consists of control logic located in the BA15 peripheral option
expander and the PC0O5 Reader/Punch which contains the Reader Punch mechanics and the tape movement circuifry.

6.8.1

High-Speed Reader

The PCOS5 Reader has the capability of advancing and reading tape one character at a time up to a

maximum of 300 characters per second (refer to PCO5 manual for complete details).

The control logic

in the BA15 interfaces the PCO5 to the PDP-151/0 Bus and also adds two features required by the
PDP-15, i.e., character packing and hardware read-in.

6-45

———
G
G
SEE
CE——

% JCOW d HIAM

F'l A. _[1q.

6-46

-1

<- _|

21nb1y41-9Alowew123104PUDB4PD013YUO1IDBUODISIUwplBola
—
f——————

$1H0LT}

]

The PC15 is able to read tapes in two modes, alpha and binary.

A hardware read-in feature is also

included.

Table 6-24
High-Speed Reader IOTs

Mnemonic

Octal Code

RSF

700101

RCF

700102

Operation Executed
Skip if Reader Flag is set.
Clear Reader flag, then inclusively OR the contents of the reader buffer into the AC.

RRB

700112

Clear Reader flag, and AC, then transfer contents

of reader buffer into AC.
RSA

700104

Select Reader in alphanumeric mode.

RSB

700144

Select Reader in binary mode.

6.8.1.1 Alpha Mode - The reader, in this mode, reads one 8-bit character from tape and then signals
the computer that the operation is completed.
The reader control sets the ALPHA flop, signals the reader to read a character, loads tape channels
7 and 8 into the 12-bit buffer in the control and then raises the reader flag (the remaining six bits

are stored in the PCO5 reader) (see Figure 6-15).

CHANNEL

fof1]2]3]a]s]s] 7]al9||o|11||2[|3|14||5[16|17] ACCUMULATOR

)

UNUSED

T 5

T cHanneL

TAPE CHANNEL

87654

321
o - ——

FEED HOLE

LEADER
L)

(FEED HOLE ONLY)

DIRECTION
OF TAPE
MOVEMENT

0
®

6000

0060
00 0

00O

— 337g <+— READ BY ONE IOT

— 277g

INSTRUCTION

— 303g

TRAILER

(FEED HOLE ONLY)

o=HOLE POSITION
*=HOLE PUNCHED
15-0232

Figure 6~15

Tape Format and Accumulator Bits
(Alphanumeric Mode)

6-47

6.8.1.2 Binary Mode - The reader advances and reads the tape and loads an 18-bit buffer with three
6-bit characters. Characters without an eight hole punch are ignored. When the buffer is full, an
18-bit' word can be transferred to the accumulator of the central processor,
The first two 6=bit characters are loaded into the 12-bit register in the reader control, the remaining
are stored in the PCO5 until read by a RRB 1OT (see Figure 6~16).

6.8.1.3

Read-In - When the console READ IN key is pressed and the PC15 is installed, the PCO

READ IN flop KP66 is set (see Figure 6~17).

Refer to the read-in flow diagram (KP75).

mode, 18-bit characters are assembled, as in binary mode.

In read-in

When the central processor has signaled

by the character interrupt line that a character is ready, the character is transferred by IOP2 and
then another character is read.
3.11.

The storage of the character in memory is described in Paragraph

When a hole seven punch is detected, the SKIP RQ line is enabled to signal the processor

that this is the last word to be transferred and that it should be executed.

A /O PWR CLR pulse then

clears out the READ IN mode.

6.8.2 High-Speed Punch

The punch receives data from the I/O bus and punches it on paper tape. Almost all of the punch
logic is located in the PC05. The punch is capable of punching in two modes, binary or alpha.

binary mode, a 6-bit character is punched onto tape, bit 7 is never punched and bit 8 is always
punched. Inalphamode, 8-bit charactersare punched. Figure 6~18isaflow diagram of the high speed punch,

Table 6-25
High-Speed Paper Tape Punch

6.9

Mnemonic

Octal Code

Operation Executed

PSF

700201

Skip if punch flag is set.

PCF

700202

Clear punch flag.

PSA

700204

Punch a line of tape in alphanumeric mode.

PSB

700244

Punch a line of tape in binary mode.

LT15A TELETYPE INTERFACE

The interface for the first Teletype in @ PDP=15 system is included with the CPU logic (see KP64 and
KP65).

If a second Teletype is used, it requires an LT15A Teletype interface, which mounts in the

BA15 panel. Because the internal and LT15A interfaces are nearly identical, this paragraph describes
both.

6-48

FIRST CHAR READ

CHANNEL ‘6
P

4
R

SECOND CHAR READ
—A

THIRD CHAR READ

e
T

2
o

[o|1]2]3]a]s]e]|7]|8]o]o]in]iz]m]ta[i5]16]17] AccumuLaToR
CHANNEL

hn'and
5

b md
3

N~
!

St
5

S’
3

hoaznd
1

—
5

Aa'md
3

ha'and
|

TAPE CHANNEL
87654

321
Ld

LEADER

««+———F— FEED HOLE

(FEED HOLE ONLY)

Ld
Ld

8 CHANNEL PUNCHED FOR EACHCHA-"
RACTER

g
|®
¢
e

DIRECTION

MOVEMENT

L4
©0 00
0 o [—FIRST CHARACTER READ
©o0 o0+
00 o |—SECOND CHARACTER READ » FIRST INSTRUCTION
L)
00000 0|—THRD CHARACTER READ
READ BY ONE IOT OR
[}

*
ocoo0so00o0

e co0oso00o0 } NEXT INSTRUCTION
s cccsooo

INITIATED

BY READIN

[]

©o0oeo000
*

e cc0o0so0oo0 } LAST INSTRUCTION

o 0

[

CHANNEL 7 PUNCHL% °°
ED CAUSES LAST =|
INSTRUCTION TO

®
®

*° °

N\\CHARACTER MUST BE

PUNCHED USING ALPHANUMERIC MODE

L
L)

TRAILER

(FEED HOLE ONLY)

o= HOLE POSITION

e = HOLE PUNCHED
15-0233

Figure 6=16

HRI Tape Format and Accumulator Bits

(Binary Mode)

6-49

3¢8041s

0=1Qav3y

JONVAQY

6~-50

0G4+

H3739aVvYYN33Y01#3409

SQvO 1 951 8

38041s
avol L91 S0

avOo 84 ‘0L L1

L1938HILOVHVHDNO

_%2p01e0a1d°s1a-v3yybiy—J€0e2dpay‘uoipied()mol4woibo1q
S3A

S3A

LEPY

1UM0d
SIA
(@

0=10vay

1=VHJTV

€02d

SI1€E0-Gi

£0 d

£€02d

[

JAUTVYONIWE

378V0

10T 0204

PCO1

SDOo0=1

1/0 BUS 1217~
PUN BUFFER 1-6

1/0 BUS 10-17

PCO1

PCO5-4

-+ PUNCH BUFFER

PUNCH FLAG

0-» PUN BUFFER 7

1- PUN BUFFER 8

PCO1

LOAD & PUNCH

[

10T 0201

I PCO1

PUNCH SKP

I PCO1

BA SKIP RQ

[

SKip

[

SKIP RQ

I BAOS

J BAO3

BAO3

15-0314

SKIP ON PUNCH FLAG

Figure 6-18

High=Speed Punch Operation,
Flow Diagram

6-51

The Teletypes send and receive 8-bit ASCII codes in the following serial format:

+3
0

_[o.09] [71 J6eLIsl T4 I3 T2 il Jol_
MSEL
|

“

Start

8 DATA BITS

Pulse

[ 1

At least 2

cycles of O Start

The keyboard and the printer are completely separate systems, and use different serial lines for their
data.

The corresponding sections of the interface are also separate, but share the 880-Hz clock

(LTO2).

Figures 6=19 and 6=20 show the keyboard and printer timing, respectively.

The receiver portion of the interface (KP64,LT02) uses a 9-bit shift register to store the start pulse
and serial data bits as they come in.
DETECTOR flop is cleared.

When the input line is raised by the start pulse, the SPIKE

If the signal is still present a half cycle (4.5 ms) later, IN ACTIVE is

cleared and shifting of input data begins.

The CLOCK SCALE network causes a shift every 9,09 ms

until the start pulse reaches the IN LAST UNIT flop.

At this point the keyboard flag is raised,

indicating that data is ready to be read into the PDP-15 with an IOT.

The IN STOP flops prevent

further operation for the full two zero cycles.
The transmitter (KP65,LT03) uses a 9-bit shift register to convert parallel data from the 1/O bus to

serial form. The print IOT loads TTO00-TTOO07 from bus bits 10~17. TTO ENABLE and OUT ACTIVE
are set.

LINE is also set, causing the start pulse at the output.

The bits are shifted, one-by-one

into the LINE flop until no 1s remain to the left of TTO07.

TTO FIN detects this, stops the shifting

by dropping OUT ACTIVE, and sets the TELEPRINT FLAG.

The OUT STOP flops produce the two

cycles of O by preventing further enables until they clear.
In the internal interface, automatic printing of incoming characters is provided by connecting the
input line to the output line, and holding off IOT enables while this is in progress.
When executing the KRS instruction, and during read-in operations, the READER RUN flop
is set. This
inhibits the echo and activates the Teletype poper-tape reader.

Only the internal interface uses

this feature.
Table 6-26
Primary Teletype IOTs

Mnemonic

Octal Code

Operation Executed

KSF

700301

Skip if keyboard flag set.

KRB

700312

Read keyboard buffer into AC10-17, clear flag.

KRS

700332

Read keyboard buffer, clear flag, select key-

board reader for next character.

6-52

ek LT
TT KBDIN

(SP)

(MK)]

START

O
i

SPACE

STOP |

STOP 2

INACTIVE [

2 START ENABLE ]
PRESET
|

CLOCK SCALE 00

CLOCK SCALE 01

CLOCK SCALEOQ2

J]IJ

—-_3t
TTIOS

(BIT 12)

TTISHIFT

APy

KBD FLAG

IN LAST UNIT

IN STOP Ot

IN STOP 02;
15-0318

Figure 6-19

Teletype Receiver (Keyboard) Timing

6-53

cu LLLLUALL

R L O LT
L

o LMLy
L L
TLS

=~-[~=pr—em—y|

-- e —-- =]-—-—_——d—.}_—,—_—_

TTO ENABLE

TTO 00

(BIT 17)
TTO O1

(BIT 16)

TTO 02

(BIT 15)

TTO 03

(BIT 14)
TTO 04

(81T 13)
TTO 05

(BIT 12)

(BIT 1)

TTO O7

(BIT 10)
LINE

START

OUT ACTIVE

QUT STOP 1

QUT STOP 1.5

OUT STOP 2

FREQ DIV
t-D
ECHO

TTO SHIFT

TTO FIN

15-0317

Figure 620

Teletype Transmitter (Printer) Timing

6-54

Table 6-26 (Cont)
Primary Teletype 10Ts

Operation Executed

Mnemonic

Octal Code

TSF

700401

Skip if teleprinter flag set.

TCF

700402

Clear teleprinter flag.

TLS

700406

Load teleprinter buffer from AC10-17, start
print operation.

There is no API connection and the internal Teletype uses the PI only.
Table 6-27
The LT15A Instruction Set

Mnemonic

Octal Code

Operation Executed

TSF1

704001

Skip on transmitter (teleprinter) flag.

TCF1

704002

Clear transmitter flag.

TLS1

704004

Load transmitter buffer and transmit.

KSF1

704101

Skip on receiver flag.

KRB1

704102

Clear receiver flag and read buffer.

The LT15A is connected to the API system, when installed.
API for keyboard: Priority level 3, Address 74.
API for teleprinter: Priority level 3, Address 75.

1/O bus receivers and drivers for the LT15A are provided in the BA15 option panel.

6.10 VP15 DISPLAY CONTROL

The VP15 is a point plotting display control which interfaces any one of three displays to a PDP-15:

The VP15A uses a Tektronix® 611 storage tube (VTOT1), the VP15B uses a Tektronix RM503 oscilloscope,
and the VP15C uses a DECtype VR12 X-~Y Display.

Points are displayed in a 1024 x 1024 bit matrix on an 8-1/4" x 6-3/8" display surface for the 611
tube, an 8 cm x 10 cm display surface for the RM503 scope, and a 6=3/4" x 9" display surface for
the VR12 display.

®Tekfronix is a registered trademark of Tektronix, Inc., Beaverton, Oregon.
6-55

A light pen option is available for both the RM503 and VR12 display systems (VP15 BL and VP15 CL).

The VP15A operates in two modes:

Store Mode, where the point plotted is stored on the screen, and

Non-Store Mode, where points displayed must be "refreshed" or replotted at least 30 times a second

in order to remain visible.

A display Done Flag is raised at the completion of the display command.

The VTO1 storage oscilloscope may be erased by IOT command and requires about 0.5 seconds for completion.

The display Done Flag is raised at the end of this operation.

The Display Flag interrupts the computer and a skip on Display Flag is provided.
is designed for the display of pointers and small groups of characters.

cantly less than in store mode.

The non-store mode

Its intensity may be signifi-

It does not use the write-through feature on the VTO1.

The VP15B and VP15C are refresh displays and must have the information replotted at least 30 times
a second.

If a light pen is on the system, a light pen flag is raised whenever light is detected.

timer is provided to limit the occurrence of the light pen flag to about 1 kHz.

The VP15 Display Conirol includes the display control logic and the digital-to-analog converters.

6.10.1

Display Control

The Display Control provides the timing for point intensification and programmable erasing (VT01) of

the display, and a 2-bit brightness register used on the RM503 and VR12 displays.
IOTs initiate the timing sequence for all displays.
for store mode and another for non-store.

The VP15A has two 10Ts for this purpose, one

The VP15B and C have only one IOT for intensification.

In the VP15A, a display Done Flag is raised when the display has finished plotting the point previously

requested.

This flag may be cleared and skipped
by an IOT control.

The display may be erased manually by depressing a button on the scope or by an IOT Command (VTO1

storage oscilloscope only).

Erase takes 0.5 seconds.

The 2-bit brightness register (BRO0O and BRO1) is loaded from 1/O bus bits 16-17 by 1OT control.

There

are four brightness levels for the RM503 and VR12.

6.10.2

Digital-to-Analog Converters (D/A)

The VP15 display contains two digital-to-analog converters (D/A); one for the x-coordinate buffer,
and one for the y-coordinate buffer.

Coordinate data is loaded into these from the accumulator of

the PDP-15 by IOT control.

6-56

Upon IOT command, the D/A converters for each coordinate are cleared and loaded with ten bits of
information from accumulator bits 08-17.,

The x buffer (XB) and y buffer (YB) are loaded separately.

These 10 bits are converted into a voltage which is used as the input to either the x or y deflection
circuitry in the oscilloscope.

6.10.3 VP15A Storage Tube Display 1OTs
6.10.3.1

Non-=Store Mode

LXDNS

700544

Load the x-coordinate buffer and display
(non-stored); the point specified by XB
and YB.

LYDNS

700644

Load the y-coordinate buffer and display
(non-stored); the point specified by XB
and YB.

6.10.3.2

Store Mode

LXBD

700564

Load the x-coordinate buffer and display
(stored); the point specified by XB and
YB.

LYBD

700664

Load the y=-coordinate buffer and display

(stored); the point specified by XB and
YB.

EST

6.10.3.3

700724

Erase the storage oscilloscope.

Store and Non-Store Mode

CXB

700522

Clear x-coordinate buffer.

CYB

700622

Clear y-coordinate buffer.

LXB

700524

Load x-coordinate buffer from AC08-17.

LYB

700624

Load y-coordinate buffer from AC08-17.

EST

700724

Erase the storage tube.

SDDF

700521

Skip if display Done Flag is set.

CDDF

700722

Clear display Done Flag.

DIE

700721

Display Interrupt Enable/AC bit 16 = 1
Disable/AC bit 16=0

6.10.4 VP15C Display and VP15B Oscilloscope 10Ts
DXL

700504

DXS

700544

Load x=-coordinate buffer from AC08-17.

Load x-coordinate buffer and display

point specified by XB and YB.

DYL

700604

Load y-coordinate buffer from AC08-17..

6-57

DYS

700644

Load y=-coordinate buffer and display point
specified by XB and YB.

DXC

700502

Clear x=coordinate buffer.

DYC

700602

Clear y=coordinate buffer.

DLB

700704

Load brightness register from bits 1617 of AC.,

DSF

700501

Skip if Display (light pen) Flag is set.

DCF

700702

Clear Display (light pen) Flag.

6.10.5 Principles of Operation
A simplified block diagram of the VP15 controller is given in Figure 6-21.

This controller consists of

three sub-systems:

A 10 bit buffer and D/A converted for each x and y deflection circuit.

Z axis timing and control circuits.

Device decoding, 1/0 bus receivers and drivers, and interrupt logic (OR API Logic).

ERASE

*—FINISH
VP15

conTROL[

TM ERASE
—»TO Z AXIS

VPO2

PDP-15

170 {BCO9B)
BUS CABLE

DEVICE
SELECTOR

RECEIVERS
AND

AC BITS 08-17

COMMANDS

X ~AX

D,A|S —»TO X AX IS ?TO SCOPE

DRIVERS

VPO1

BAO2

COMMANDS

VPO1

YOXS L
wtov Axts

VPO1

Figure 6=21

VP15 Controller, Simplified Block Diagram

6-58

15- 0316

The receivers and drivers interface the device to the 1/O bus and to the PDP-15.
lectors decode the various IOT commands.

The device se-

The 10 bit x and y coordinate buffers, which define a

1024 x 1024 matrix, are cleared and |oadéd, by IOT commands. After an intensify command has
been completed in the VP15A, a display done flag will be set, and the computer interrupt will occur.
This condition may be tested by a skip or display done flag.

The VTO01 scope may be erased by IOT command and the display flag will be set as above upon the

completion of the erase.

An input/output read status, (IORS), instruction will read the status of the display flag into AC bit
05, and light pen flag into AC bit 05; for systems with API, the display is a priority level 2, and its

1/O address is 54.

Table 6-28

Settling and Intensification Times

VP15A

Deflection Settling

Intensification

Time (us)

Store Mode

Non-Store Mode

1.5-2.2

VP15B

1.5-2.2

VP15C

1.5-2.2

6-59

CHAPTER 7
MAINTENANCE

7.1

INTRODUCTION

It is not the purpose of this chapter to train the reader in the theory of operation of the PDP-15 com~
puter. It is assumed that the reader is already familiar with the PDP-15's operation, and this chapter
will act as an aid in the maintenance and troubleshooting of the PDP-15.

It is recommended that maintenance and repairs be performed by qualified service personnel only. Potentially dangerous voltages are present in the power supplies. Safety precautions must be observed.

In this chapter the preventative and corrective maintenance procedures for the PDP-15 computer will
be discussed, and a general description of logic troubleshooting is given. The adjustments of PDP-15

Memory, Central Processor, and 1/O Processor are shown, and are accompanied by appropriate pictures of the wave forms which can be expected to be seen when the adjustments are properly made.

7.2

SYSTEM MAINTENANCE

System reliability and maintainability are two of the most important criteria in the design of the
PDP-15 computer. This fact, however, does not preclude the necessity of setting up a systematic
preventative maintenance program. Proper application of such a program will aid both the maintenance personnel and the user through detection and prevention of probable failures that will help
keep maintenance and downtime to a minimum.

7.2.1

Maintenance Equipment

Special tools and test equipment required for maintenance are listed in Table 7-1. Except for DEC

equipment, suggested commercial brands are given for purposes of specification only; their being
mentioned does not constitute exclusive endorsement.

Table 7~1
Maintenance Equipment

Equipment

Specification

Multimeter

10 Kohms/V - 20 Kohms/V

Oscilloscope

Model or Type

Triplett model 310 or 630-NA
Tektronix type 454, 547

Probes

X10 with response charac~

Tektronix type P6010, P6047

teristics matched to oscil~
loscope

Clip=on current

2 mA/mV or 10 mA/mV

Tektronix type P6022 with

probe

passive terminator

Recessed probe tip
(2 each)

Tektronix

Unwrapping tool

30 gauge

Gardner Denver 505-244-475

Wire=-wrap tool

30 gauge

Gardner Denver A-20557-29

30-gauge bit for

Gardner Denver 504221

wire=wrap tool

Sleeve for 30-gauge
bit

Module extender (2)

Gardner Denver 500350

DEC no. W982

Jumper wires

Assorted lengths affixed with
30~gauge Termi=Points

Screw driver

6-in. non-conductive shaft

Field service kit
Diagnostic programs

7.2.2

DEC type 142
(Supplied with system)

Maintenance Test Programs

Table 7-2 lists the diagnostic programs designated MAINDEC.

Altogether these programs provide a

complete check of the system logic.

These programs are written in such a manner as to check certain circuits or functions of the machine,

from a go/no go situation to isolate basic logic faults, through the use of random number generation
to help isolate the more difficult random failures that may occur, and finally to programs designed to
test the operability of the system under the interaction of various tests coupled with peripheral requests and interrupts.

When an error or failure is detected by the diagnostic it will signify such by either halting or through
an error typeout.

The reason for the halt or typeout may then be determined through investigation of

the console indicators and controls or by use of a scope loop in the diagnostic if one is provided.

The diagnostic write ups and listings should be consulted for the type of error failure and for the use
of console controls and/or switch settings that will aid in the isolating of the machine fault.
Table 7-2
MAINDEC Diagnostic Programs

Program Name

Identification Number

PDP-15/20

(basic central processor, memory and Teletype)
Instruction Test = Document

MAINDEC~-15-D0BO-D

1-PH
2-PH

Part 1
Part 1A
Instruction Test, Part 2
Hardware Index Register Test
JMP = Self Test
JMP=Y Interrupt Test
JMS=Y Interrupt Test

MAINDEC-15-DOBB
MAINDEC-15-DOAB
MAINDEC-15-DODA
MAINDEC-15-DOEA
MAINDEC-15-DOFA
MAINDEC~15-DOKA
MAINDEC-15-D1AO-D

ISZ Test

Basic Memory Checkerboard Document

1-PB

Low

2-PB

High

Extended Memory Checkerboard

MAINDEC-15-D1BB
MAINDEC-15-DOCA
MAINDEC-15-D1CD
MAINDEC-15-D1FA
MAINDEC-15-D1GA
MAINDEC-15-D7AA
MAINDEC-15-D7BC
MAINDEC-15-DZAA
MAINDEC-15-DZBA
MAINDEC-15-D2G3
MAINDEC~15-DAMXA

MAINDEC-15-DOGA
MAINDEC-15-DOHA
MAINDEC-15-DZDA
MAINDEC-15-DZCA
MAINDEC-15-DZCO
MAINDEC-15-D3BA
MAINDEC-15-D3CA
MAINDEC-15-D3RA

PDP-15/30
MAINDEC-15-D0IB
MAINDEC-15-D1EA
MAINDEC-15-D8CA

4K Basic Exerciser

8K Basic Exerciser (if 8K of core)

ASR33/35 Teletype Test (Part 1)
ASR33/35 Teletype Test (Part 2)
Binary Count Pattern Test Tape (for above)
ME15 Extended Memory Checkerboard

(sam eda 8K 15/10, plus the following)
wn

PDP-15/20

Memory Address Test
Extended Memory Test
Extended Memory Address Test
Memory Address Timing Test

EAE Test, Part 1
EAE Test, Part 2

High Speed Punch Test
High Speed Reader Test
Reader Test Tape (for above)
DECtape Basic Exerciser, Part 1
DECtape Basic Exerciser, Part 2
DECtape Random Exerciser

(same.as 15/20, plus the following)
1/O Test (API)

Memory Protect Test

LT09/LT19 Teletype Control Test

7-3

Table 7=2 (Cont)
MAINDEC Diagnostic Programs

Identification Number

PDP-15/40

Program Name

(same as 15/30, plus the following)

MAINDEC=-15-D5AA

RF15 Disk Data Test

MAINDEC-15-D5BB

RF15 Multi=Disk Test

MAINDEC-15-D5CA

DISKLESS

Peripherals and Options for PDP-15/20/30/40
1) With CRO3B Card
Reader
MAINDEC-15-DZUA

CRO3B GDI Card Reader Test

MAINDEC-15-DZAZ~C

Binary Cards (for above)

2) With VP15A Display
MAINDEC-15-D6BA

Display Diagnostic

3) With TU20 or TU20A
Magnetic Tape

MAINDEC-15-D4CB

Magnetic Tape
Control Drive
Function Timer

MAINDEC-15-D4DA

7 Track Data Reliability

MAINDEC-15-D4EA
MAINDEC-15-D4GB

9 Track Data Reliability
Random Exerciser

4) KT15 Memory Relocate
KT15 D1JA

Memory Relocate Test

5)KT15 D1KO-D

Memory Parity Test Document

1-PB
2-PB

High

Low

6) KF Power Fail
KF DOJA

7.3

7.3.1

Power Fail Test

PREVENTIVE MAINTENANCE

Introduction

This section provides information for performing preventive maintenance inspections.

This informa-

tion consists of visual, static, and dynamic fests that provide better equipment reliability.

Preven-

tive maintenance consists of procedures that are performed prior to the initial operation of the com=

puter and periodically during its operating life.

These procedures include visual inspéctions,

7-4

cleaning, mechanical checks, and operational testing.

A log should be kept for recording specific

data which indicates the performance history and rate of deterioration.

This information can then be

used to determine the need and time for performing corrective maintenance on the system.

Scheduling of computer usage should always include time for scheduled preventive maintenance

checks. Careful testing during this scheduled time may turn up faults that occur intermittently during
normal operation or catch problems before they occur resulting in an overall saving of computer usage
time for a line operation.

7.3.2

Scheduled Maintenance

The PDP-15 must receive certain routine maintenance aftention to ensure maximum life and reliability
of the computer system.

DEC recommends the following schedule:

1000 hrs:

Electrical Inspection

500 hrs:

Mechanical Inspection or at least once every 3 months

Daily Maintenance

Once a day the Basic Exerciser Program MAINDEC should be run for several minutes to ensure general overall system operation.

Weekly Maintenance

Time should be scheduled each week to run the MAINDEC Programs listed in Table 7-2.
gram should be run for a minimum of five minutes.
and log the results.

Each pro-

Take any corrective action needed at this time

The external cleanliness of the system should also be maintained on a weekly

basis.

Computer downtime can be minimized by a rigid adherence to a preventive maintenance schedule.
A dirty, clogged air filter can lead to machine failure due to overheating.
cleaned periodically.

All filters should be

The procedure for cleaning filters is described under Preventive Maintenance

Tasks.

Preventive Maintenance Tasks
The following tasks should be performed at least once every three months.
a.

Clean both the exterior and interior of the computer cabinet, using a vacuum cleaner

and/or clean cloth moistened in a non=-flammable solvent.

Clean all air filters.

Use a vacuum cleaner to remove the dirt and dust or wash the fil-

ters in clean warm water.

Lubricate all slide mechanisms, door pins and castors with a light machine oil . Wipe off
any excess oil .

Inspect all wiring, cables and harnesses for cuts, breaks, fraying, wear, deterioration,
kinks, strains and mechanical security. Replace or repair any defects found.

Inspect the following for both proper operation and/or mechanical security. Repair, re=
place, or tighten as required all lamps, switches, knobs, connectors, fuses, fans and
covers.

Inspect all module mounting panels to ensure that all modules are firmly seated in their
sockets. Remove and clean any modules that may have collected excess dirt or dust.

Inspect the power supply for leaky capacitors, overheated resistors, relay operation,
etc.; replace or repair any defective items found.

Check the outputs of the 715 Power Supply without disconnecting the load. The outputs
of the 715 Power Supply are non-adjustable; therefore, if any voltage is not within specification then corrective maintenance must be performed to remedy the defect.

Check the voltage outputs of all voltage regulators and make any necessary adjustments
of the regulators to bring the voltages into specification. If the voltage cannot be adjusted to meet the specification the corrective maintenance must be performed.

Run all MAINDEC Programs to verify proper machine operation.

Each program should be

run for a minimum of 5 minutes.

7.4
7.4.1

Perform all preventive maintenance procedures for each peripheral device connected to
the PDP=15 system as directed by the individual instructions supplied with each option.

Check for circuit deterioration by varying the machine timing in accordance with the
PDP=-15 engineering specification.

Enter the results of the preventive maintenance in the log book.

CORRECTIVE MAINTENANCE
Introduction

The PDP-15 is constructed of reliable TTL M-series modules.

Proven reliability of this circuitry en-

sures relatively little equipment downtime due to logic failure.

If a malfunction occurs, mainten-

ance personnel should analyze the condition and correct it as indicated in the following procedures.

The best corrective maintenance tool is a thorough understanding of the physical and electrical characteristics of the equipment.

Personnel responsible for maintenance should be familiar with the sys-

tem concept, the logic drawings, the theory of operation of the specific module circuits, and location of mechanical and electrical components.
The first step in repairing a reported malfunction is to isolate the problem.

In a hardware-software

system environment such as the PDP=15, the first step is to determine whether the problem lies in the
hardware, the software, or both.

The only practical way of doing this is by maintaining good com=

munications between the operator, programmer, and maintenance personnel .
7-6

Until the problem is isolated to either hardware or software, the cooperation of all parties concerned

is essential. A step=by-step procedure should be used to trace the problem until a point is reached
where all the inputs (conditions) to an element (of the hardware) are correct, but the output is not

correct. The faulty element thus located should be repaired. Where necessary, the element itself
may be subjected to step-by-step fault location (from output to input) until the source of the problem
is found.

It is virtually impossible to outline all specific procedures for locating faults within digital systems

such as the PDP=15. However, diagnosis and remedial action for a faulty condition can be undertak=-

en logically and systematically in the following phases:

7.4.2

.
.

Preliminary investigation
System troubleshooting
Logic troubleshooting
Circuit troubleshooting
Repairs and replacement
Validation tests
Recording

Preliminary Investigation

Before beginning troubleshooting procedures, explore every possible source of information. Gather
all available information from those users who have encountered the same problem and check the sys=tem log book for any previous references to the problem or to a similar one.

Do not attempt to troubleshoot by using only complex system programs. Run the MAINDEC programs
and select the shortest, simplest program available which exhibits the error conditions. MAINDEC

programs are carefully written to include program loops for assistance in system and logic troubleshooting .

7.4.3

System Troubleshooting

Once the problem is understood and the proper program is selected, the logical section of the system
at fault should be determined. Obviously, the program which has been selected gives a reasonable
idea of what section of the system is failing. However, faults in equipment which transmits or re~

ceives information, or improper connection of the system, frequently gives indications similar to
those caused by computer malfunctions.

Reduce the program to its simplest scope loop and duplicate this loop in a dissimilar portion of memo-

ry to verify, for instance, that an operation failure is not dependent upon memory location. This
process can aid in distinguishing memory failures from processor failures. Use of this technique often
pinpoints the problem to a few modules.

System troubleshooting is the first step towards isolating and repairing a machine malfunction.
machine cannot be started, refer to the section on console checks (Paragraph 7.4.4).
is running, determine that hardware, not software, is causing the problem.

If the

If the machine

If the problem is occur-

ring with DEC software (Compact, system monitor, etc.), obtain a certified copy of the program that
is in good condition and attempt to repeat the malfunction.

a logic failure.

Generally, a recurring problem indicates

If the problem occurs only with the user's software, an analysis of the failing pro-

gram must be made.

Use of the single time and single step is recommended.

Some other items to

check in the user's software are special bit assignments and functions.

Are bank mede, page mode,

etc., being used properly? Are memory fields being used properly?

Is the program making unwar-

ranted assumptions; i.e., assuming that the accumulator will be clear on start-up, etc?
In general, attempt to isolate the problem to a major system; then exercise that system with the
MAINDEC diagnostics.

7.4.4

Then, if necessary, proceed to logic troubleshooting and repair.

Console Checks

Assuming the problem is not clearly defined, the following checks should be made in an attempt to
isolate basic machine faults.

further.

Any malfunctions observed at this time should be remedied before going

Refer to Paragraph 7.5 for adjustments.
a.

Power On — Does the power indicator on the console come on?

cification?
b.

Is the power up to spe-

(Refer to Paragraph 7.3.2, steps i and j.)

Reset — Does the exec major state lamp light as well as the time state 3 lamp? Are the
IR, MB, AC, PC, LINK and MO Registers cleared
?

Deposit — Do the data switches transfer to the MO and MB?
transfer to the OA?

Do the address switches

Are the fetch and time state 3 lamps on
?

Examine — Do the address switches trarsfer to the OA and MO register?

Do the contents

of the location addressed appear in the MB register?
e.

Deposit Next — Do the data switches transfer to the MO and MB?

Do the contents of the

OA register increment properly
?

Examine Next — Do the OA and MO registers increment?

Do the contents of each se-

quential memory location appear in the MB?
g.

Deposit all 1s through memory using the repeat deposit next feature.
crement through TO the final available memory address +1?

Does the QA in-

When the first non-existent

memory address is accessed, does the computer stop in the fetch state at time state 2?

the run light on and the non-existent address in the OA and MO ? Is the MB cleared
?
Does the repeat speed vary with the on/off speed switch? With the machine hung with
the run light on, the stop and reset keys should have to be depressed together to clear
this condition.

Either one by itself should have no effect.

Examine all of memory for bit loss.

With the address switches equal to 0, and with all Ts in memory, depress reset and start.
Does the run light come on?

Do the PC and MO registers increment up through 7777 (for

4K systems) or 17777 (for 8K or greater)?
1, 2, and 3 lamps light
?

Does the AC equal all 1s?

Do the time states

Depress stop — Does the run light go out? Does the computer stop in fetch, time state 37

Depress continue — Are the indications as in step i ?

Deposit a Lac 100 in location zero, a jump to zero in location 1, and a 525252 in location 100. Depress start key. Does the machine cycle properly between the fetch and
execute states? Does 525252 appear in the AC?

Using the execute switch try performing several instructions set in the data switches.
Does the processor react properly to each instruction? Can the instructions be repeated
by the use of the repeat function?

If the computer performs the above operations successfully, the timing of the CP, Memory, console

and 1/O are approximately correct and troubleshooting at a processor level can be commenced.

7.4.5

Processor Troubleshooting

Memory, 1/O and CP processor troubleshooting is best achieved through the use of the MAINDEC diagnostic programs listed in Table 7-2. They provide the most rapid method of exercising these system
areas.

Since the use of the MAINDECs requires the Readin function of the Teletype or high-speed reader to
be operational this section of the processor must be checked first.

If the Readin section of the computer is not working, the operation of the reader IOTs should be
checked by use of the execute repeat function of the console or by toggling in small read routines
and comparing the processor operation against the appropriate timing and flow charts.

The extensive use of indicators (including two maintenance positions on the console indicator switch)
in the PDP-15 and its peripheral devices was purposely included in the design.

These indicators can,

and should be used as aids in troubleshooting problems. You will probably find that many problems
can be found and repaired through the use of these indicators without the need of any other test
equipment.

Since the three main sections of the PDP=15 computer rely upon a request-grant system of operation
most basic problems should be fairly easy to locate.

As an example, the CP requests memory and

waits for memory to acknowledge with an address acknowledge signal.

If memory fails to answer, the

processor will hang up with memory request still set, thus almost immediately pointing out the source
of the trouble.

More subtle problems should be investigated through the use of the appropriate diagnostic program.

Timing margins and module vibration often will point up intermittent problems more rapidly although
care should be exercised in the use of module vibrating so as not to introduce more problems.

When troubleshooting peripheral devices a check of the signals on the 1/O bus should be performed
first, i.e., IOP pulses, device and subdevice select lines, etc., for proper levels and timing.

Then

the appropriate peripheral diagnostic should be run and the problem investigated by use of the diagnostic write-up.

If the diagnostic will not run, check the operation of the individual IOTs for the peripheral.

Can the

command register be loaded ? Can data be transferred to and from the devices data register? Can the
status registers of the device be transferred to the processor? In the case of a 3-cycle device a small
routine to transfer blocks of data with +1 CA inhibit set will prevent wiping out core memory if there
is a word count or current address problem.

Once the fault has been isolated to a particular section,

the next logical step is logic troubleshooting.

7.4.6

Logic Troubleshooting

Logic troubleshooting in the PDP=15 is best accomplished using the technique of reverse signal tracing.
That is, when a malfunction has been isolated to a section of logic, some type of failure loop using
either the reset=start switch combination, a small program, or a scope loop option in a diagnostic
MAINDEC should be used.

Then, by comparing the logic engineering drawings with the machine

status, that portion of logic which is causing the failure becomes evident.
NOTE

An unconnected input to a gate, if not tied to a

+3V pullup high, floats at approximately +1.9V.

Before attempting to troubleshoot the logic, make sure that proper and calibrated test equipment is
available.

Always calibrate the vertical preamplifier and probes of the oscilloscope before using.

Make certain that the oscilloscope has a good ac ground, and keep the dc ground from the probe as
short as possible.

Use the oscilloscope to trace signal flow through the suspected logic element.

Oscilloscope sweep

can be synchronized by control pulses or by level transitions which are available at individual module
terminals on the wiring side of the logic.
shorting between pins.

Care should be exercised when probing the logic to avoid

Shorting of signal pins to power supply pins can result in damaged components.

Within modules, unused gate inputs are held at +3V.
WARNING

Standard safety practices should be observed when
working with energized equipment. Remember that
peripherals are not always connected to the mainframe power control and may be energized when the

PDP-15 is off.

7-10

7.4.6.1

Troubleshooting Intermittent System Problems

Power

Perform the dc voltage adjustment procedures listed in Paragraph 7.5.1.
Check a ll Mate~N=-Lok connectors on the H715 Power Supply. These connectors
should be lightly vibrated while running s ystems exerciser diagnostic.

Check for mercury contact relays in H715 Power Supply and in 841 Power Control in
each bay. If relay is erratic, replace with dry contact relay (12-10241 for the H715
Power Supply and 12-9406 for the Power Control). A 5309232-0-0 mounting bracket
is required for the H715 Power Supply.

Timing

Check memory strobe by syncing channel A positive on RDY (AT19E1) and observing
that strobe A appearing at pins C14E1, L1, S1, J2, P2, V2, occurs 200 ns after RDY.

Check CP cycle time by doing a "jmp self" and looking at duration of TSO1 H (E30K2).
Adjust pot on M775 in location E30 for 260 ns (350 ns for parity machines).
For machines with MX15A and no options, adjust TSO1 H for a cycle time of 1080 ns,
MX15A and KM15 for 1120 ns, MX15A, KM15 and KT15 for 1160 ns.
For machines with MX15A or FP15, perform the following check. Write an all 1's
pattern into the last memory on the MDL cables using the DAC instruction. Sync
channel "A" negative on CPWR ADR ACK (F12J2), and channel "B" on MRLS ACK
(F2802). Record delay between ADDR ACK and MRLS ACK.
Now observe TSO1-Ph2 (H31N1) using channel B probe. TS01-Ph2 should occur af
least 50 ns after the delay recorded in step d. If necessary, adjust CP clock E30 to
obtain at least a 50 ns window.

Check 1/0 clock (N21D2) for 250 ns min.
Check console clock (N28D2) for 27.5 ps. Erratic console clock operation can cause
system halts with all registers resef, in many cases.
NOTE

Refer to Table 7=3 for complete timing summary and margins.

Check 1OP pulses for correct width on the I/O bus.

IOP1+IOP2 should be 750 ns,

IOP4 should be 500 ns for IOT's and 3 cycle devices, and IOP4 should be 100 ns for
single cycle devices.

Check data pulses on 1/O bus.

Pulse should be +2.5V to GND.

Cables

Check all I/O cables for tightness.
Ensure that the I/O cables are inserted in the correct input and output locations.
RP02 Disk systems = check disk control and data cables.
at the end of the cable connected to the disk.

Look for pushed in pins

MDL cables = do not mix coax and ribbon cables. Use M?211 and M902 terminators
with the coax cables. Use either all M966 or M210 and M202 terminators with
the ribbon cable. Separate API control and all indicator cables from MDL cables.
Refer to PDP-15 print set for latest configuration.

7-11

Miscellaneous

If an RP15 is installed, check RP15 timi ng adjustments using RP15 Instruction Test
(MAINDEC-15-D5HB).

Read Data Separator Module M420 must Rev C efch and Rev E schematic.

If memory has 8K of MM/MC memory, check that pin C2151 is grounded.

If processor has the KM15 memory protect option with more than 8K of memory or an
MX15-A Memory Multiplexer, check for proper installation of the four-wire add/
delete on KD15-0~06.

7.4.7

Ensure that jumpers for A2 and B2 on indicator cables in the BB15 (slots A4, B4) and
in each memory (slots 2, 3) are cut to prevent paralleling the voltage regulators.

Check operation of all muffin fans.

Clean all filters.

Module (Circuit) Troubleshooting

Engineering schematic diagrams of each module are supplied with each PDP~=15 system in the Module:
Manual and should be referred to for detailed circuit information.

Engineering block schematic dia-

grams are contained in Volume 2 of the Maintenance Manual .

Visually inspect the module on both the component side and the printed=wiring side to check for
overheated or broken components, etc.

If this inspection fails to reveal any signs of trouble or fails

to confirm a fault condition observed, use the multimeter to measure resistance.
CAUTION
Do not use the lowest or highest resistance ranges of

the multimeter when checking semiconductor devices. The X10 range is suggested.

Failure to heed

this warning may result in damage to components.

Measure the forward and reverse resistance of diodes.
forward and more than 1000 ohms reverse.
10 to 1.)

Diodes should measure approximately 20 ohms

(Front-to=back ratio should always be greater than

If readings in each direction are the same and no parallel circuit paths exist, replace the

diode.

Measure in both directions the emitter-collector, collector-base, and emitter=base resistances to
transistors.

Short circuits between collector and emitter or an open circuit in the base~emitter path

cause most failures.
and emitter.

A good transistor indicates an open circuit in both directions between collector

Normally 50 to 100 ohms exist between the emitter and the base, or between the col-

lector and the base in the forward direction; an open circuit exists in the reverse direction.

To deter-

mine forward and reverse directions, consider a transistor as two diodes connected back to back.

this analogy, PNP fransistors would have cathodes connected together to form the base, and both the
emitter and collector would assume the function of an anode.

In NPN transistors, the base would be

a common=-anode connection; and both the emitter and collector would be the cathode.
7-12

Multimeter polarity must be checked before measuring resistance because many meters apply a positive
voltage to the common lead when in the resistance mode.

Since integrated circuits contain complex circuits with only the input, output, and power terminals
available, static multimeter testing is limited to continuity checks for shorts between terminals. In-

tegrated circuit checking is best done under dynamic conditions and using a module extender to make
terminals readily accessible. Using PDP=15 engineering drawings and the M-series module schematics,
an integrated circuit may be located on a circuit board in the following ways:

Hold the module with the handle in your left hand (the component side facing you).

Integrated circuits are numbered starting at the contact end of the board in the upper
right corner.

¢c.

The numbers increase toward the handle.

When a row is complete, the next integrated circuit is located in the next row ot the
contact end of the board (see Figure 7-1).

The pins on each integrated circuit are located as shown in Figure 7-2.

e
A

15-0295

Figure 7=1

Integrated Circuit Location

=14

144

-1

2 1

13
4

- 2

121

-3

-4

5 -

10
o

-5

6 -

-6

-7

TOP

BOTTOM
15-0296

Figure 7-2

Integrated Circuit Pin Location

7-13

7.4.8

Repairs and Replacements
NOTE

DEC recommends replacing defective modules with
modules of known quality on a one=for-one basis and

returning the suspect module to a DEC field office

for subsequent repair and/or replacement.

If, how-

ever, for expediency, field repairs must be performed, it is imperative that the following procedure
be strictly adhered to.
When soldering semiconductor devices (transistors, diodes, rectifiers, or integrated circuits, any of
which may be damaged easily by heat, physical shock, or excessive electrical current), take the fol~-

lowing special precautions:
a.

Make sure the equipment is turned off.

Use a heat sink, such as a pair of pliers, to grip the lead between the nearest joint and
device soldered.

Use a 6V iron with an isolation transformer.

Use the smallest iron adequate for the work.

Using an iron without an isolation transformer may result in excessive voltages present at
the iron tip.
d.

Perform the soldering operation in the shortest possible time to prevent damage to the
component and delamination of the module-etched wiring.

Integrated circuits may be removed by using a solder puller to remove all excessive solder

from contacts.

Then, by straightening the leads, lift the integrated circuit from its ter-

minal points.

If it is not desirable to save the defective integrated circuit for test pur-

poses, the terminals may be cut at the integrated body and each terminal removed from
the board individually.
CAUTION
Never attempt to remove solder from terminal points
by heating and rapping modules against another sur=
face. This practice usually results in module or com=
ponent damage. Always remove solder with a soldersucking tool .

When removing any part of the equipment for repair and replacement, make sure that all leads or
wires which are unsoldered, or otherwise disconnected, are legibly tagged or marked for identifica~tion with their respective terminals.

Replace defective components with parts of equal or better qua-

lity and tolerance.

In all soldering and unsoldering operations in the repair and replacement of parts, avoid placing excessive solder or flux on adjacent parts or service lines.

When the repair has been completed, remove

all excess flux by washing junctions with a solvent such as trichlorethylene.

Be very careful not to

expose painted or plastic surfaces to this solvent.

7.4.9

Validation Tests

Always return repaired modules to the location from which they were taken.

If a defective module is

replaced by a new one during a repair period, tag the defective module, noting the location from

which it was taken and the nature of the failure.

When repairs are complete, return the repaired

module to its original location and determine whether or not the repairs have corrected the problem.
7-14

To confirm the fact that repairs have been completed, run all tests which originally showed up the
problem.

If modules were moved during the troubleshooting period, refurn them to their original po-

sitions before running the validation tests.

Any time that a module is replaced by one from spares, return the module to its original location to
confirm its defectiveness before initiating a repair procedure.

7.4.10

Recording (Log Book)

A log book is supplied with each PDP=15 system. Corrective maintenance is not complete until all
activities are recorded in the log book. Record all data, indicating the symptoms displayed by the

fault, the method of fault detection, the component at fault, and any comments which would be helpful in maintaining the equipment in the future. The log should be maintained on a daily basis, recording all operator usage and preventive maintenance results.

7.5

ADJUSTMENT PROCEDURE

The PDP=15 computer system has been purposely designed to eliminate numerous delay and timing ad=~

justments which have proved to be frequent sources of trouble in other machines. The aim of this design is to aid the serviceman in troubleshooting and maintaining the PDP=-15 system by eliminating

time wasted in the adjustment of a large number of delays and timing chains. This feature is probably

best pointed up in the PDP=15 memory where the only adjustment, other than the voltages, is the
memory strobe delay.
NOTE

All timing adjustments are taken at +1.5V point on
the appropriate wave form.

7.5.1

DC Voltage Adjustments

+5V Memory, CP, 1/O

There is one G821 +5V regulator in each MM15 Memory and four in the CP, 1/O proces~
sor section of the PDP-15 Computer System. Each one must be properly set up to supply
the correct voltage to its associated logic (refer to MM15-20).

Each G821 module also has a low voltage detector adjustment R17, (see Figure 7-3), and
this adjustment should be made at this time to ensure that the logic will not have to operate at a marginal voltage setting, which could induce errors. To set the low voltage
detector, adjust the +5V output with R3 for 4.75 volts. With the regulators now providing the lower I.C. voltage limit, adjust R17 on each G821.
While observing the panel light (grain of wheat bulb on wire wrap panel) associated with
the G821 being adjusted, turn R17 counterclockwise until the panel light goes out. Then
turn it clockwise until it just comes back on. Then proceed with the +5V adjustment des=
cribed below.
7-15

+5V Adjustment

Look at pins AOTA2 in each memory bank; EO1A2, HO1A2, KO1A2, and MOTA2 in the

CP/10 and adjust R3 on the appropriate G821 for +5V to ground with your multimeter.
(See Figure 7-3 for potentiometer position on module.)
6821 REV D AND LATER

6821 REV C

—°

h—

[
2N4941

@ R3
B

RI7 @

Ri7

15-0297

Figure 7-3

G821 Module Adjustment

-6V Memory Slice Voltage
Each MM15 memory contains a G822 slice and threshold voltage regulator.
To adjust the -6V slice look at pin CO1B2 in each memory and adjust R3 (see Figure 7-4)
until =6V to ground is measured on the multimeter.

Memory Threshold Voltage
To adjust the memory threshold voltage with the multimeter, measure between pin CO1V2
in memory and ground. Adjust POT R10 on the (53822 module (see Figure 7-4) until a
reading of 4V is obtained.
G822 REVD

)
-

1O
15-0299

Figure 7-4

G822 Module Adjustment Locations

7-16

=24V Memory Voltage

To adjust the =24V memory voltage in each memory, measure between pin C17R1 and

ground. Adjust POT R14 on the G823 module (see Figure 7-5) until a reading of =24V
is obtained on the meter. This is an approximate setting.

This voltage should give you approximately 400 mA of current when a current probe is
used on the current loops in memory (see Figure 7-6). Further adjustment of R14 may be
necessary to obtain exactly 400 mA.

s
P—

15-0300

Figure 7-5

G823 Module Adjustment Locations

TIME:100Ons/CM

CURRENT : 200 mA/CM
Figure 7-6
7.5.2

MEM Current

Memory Timing Adjustments

7.5.2.1

Memory Strobe with Current Probe = As stated before, memory strobe is the only variable

timing adjustment in memory.

To adjust memory strobe use an oscilloscope with a dual trace.

Sync

on chan #1 and with current probe #1 ook at the RDX current loop B0452-B05T2, Trigger the scope
positive.

With probe #2 look at CO4C1 (memory strobe H). Set the sweep speed to 50 ns/cm and use a
chopped trace.

start key.

Toggle in a JMP 0 in location 000000 of the memory being adiusted and depress the

Adjust the POT on A17 until the leading edge of memory strobe occurs 115 ns after the

leading edge of 10% point of RDX current (see Figure 7-7).

7-17

TIM
: 50ns/CM
E

A CURRENT : 100mA/CM
B

VOLTAGE : {V/CM

Figure 7-7

MEM Strobe Delay

Deposit 777777 in Loc 0 and a JMP 0 in Loc 1 of the memory being adjusted. With probe #1, ob-

serve CO4C1. With probe #2 look at CO5A1, a sense amp output test point. The wave forms should
look like Figure 7-8.
7.5.2.2

Use scope settings previously described.

Memory Strobe with No Current Probe = Check the strobe adjustment in each memory by

syncing channel A positive on RDY (A19E1) and observing that "strobe A" (C14E1, L1, S1, J2, P2,

V2) occurs 200 ns after the beginning of RDY.
7.5.3

7.5.3.1

CP Timing Adjustment

CP Clock — With probe #1 sync on, and Look at pin E30F2 in the CP (HS clock H), adjust

the pot on E30 to give approximately a 65 ns cycle time (85 ns for machines with parity) (see Figure
7-9).

Deposit the following program in memory and loop on it.

Loc

100/
101/
102/

15Z

JMP
JMP

103

100
100

440103

600100
600100

With probe #1 sync on, and look at E30K2 (TSO1 H) (see Figure 7-10). Readjust the pot on E30 to
give a 260 ns duration (350 ns for parity machines).
7-18

TIME:50ns/CM

A:{v/CM
B:iv/CM

Figure 7-8

MEM Strobe/Sense Amp Output

TIME:20ns/CM

VOLTAGE :1v/CM

Figure 7-9

CP Clock

7-19

TIME:50ns/CM

VOLTAGE :1v/CM
Figure 7=10

TSO1 Duration

Now change the time base of the scope and measure the time between the leading edge of one TSO1

to the leading edge of the next (see Figure 7-11).

Typically, this time should be 780-810 ns.

(For

machines with Memory Protect Option 800-850 ns; for machines with memory relocate option
800~950 ns; for machines with parity option 1.02-1.08 ps.)

The variations in time are due to syn-

chronization circuitry, cable and circuit delays.

The. CP timing can be varied as per Table 7-3 to test the operation of the synchronization circuitry
and as a margin test to aid in troubleshooting.

Data path speeds that are deteriorating may show up as

the processor speed is increased, and they can be repaired beforea problem at normal speed occurs.

7.5.4
7.5.4.1

1/0O Timing
1/O Clock — The 1/O clock is adjusted by observing with probe #1 pin N21D2 (I/O Clock)

(see Figure 7-12).

7.5.4.2

Adjust the pot on N21 so that the pulses occur every 250 ns.

Console Clock — With probe #1 sync on and look at pin N28D2, Clk in H (see Figure 7-13).

Adjust the pot on N28 so that the pulses occur every 27.5 ps.

7-20

TIME:100ns/CM

VOLTAGE :i{v/CM

Figure 7=11

Machine Cycle Time

TIME:100ns/CM

VOLTAGE :iv/CM

Figure 7-12

1/O Clock

7-21

TIME:S5pus/CM

VOLTAGE : iv/CM

Figure 7-13

7.5.4.3

Console Clock

Teletype Clock — With probe #1 sync on and Look at pin M28K2 - T to Clock L (see Fig-

ure 7-14), adjust the pot on M28 so that the clock pulse occurs every 4.5 ms.

This adjustment is fairly critical and may need to be slightly readjusted if type-out errors are noted
when running the Teletype diagnostics.

7.5.5

Timing Adjustment Summary

Table 7-=3 gives a summary of all the PDP~15 timing adjustments and the margin variations which can
be obtained under normal conditions.

7=22

TIME:2ms/CM

VOLTAGE :iv/CM

Figure 7-14

Teletype Clock

Table 7-3

PDP~15 Timing Adjustment Summary

Machine
.

Adjustment

Monitor | Nominal

Minimum

Maximum | Cycle Time

Point

Setting | High Margin | Low Margin | at Nominal

Console

N28D2

27 .5 ps

N/A

CP Clock

TSO1

260 ns

350 ns

230 ns

790-820 ns | No KM15,

Setting

E30K2

CP Clock

TSO1

Conditions

KT15 or MP15

260 ns

350 ns

250 ns

800-850 ns | With KM15

E30K2

and no MP15

CP Clock

TS01
E30K2

260 ns

350 ns

250 ns

800-900 ns | With KT15
and no MP15

CP Clock

TS01

350 ns

375 ns

320 ns

1.05 s

E30K2

With MP15
and no KT15

or KM15

CP Clock

TSO1
E30K2

350 ns

375 ns

320 ns

1.0-1.2 ps | With MP15
and either
KT15 or KM15

7-23

Table 7-3 (Cont)
PDP-~15 Timing Adjustment Summary

Adjustment
1/O Clock

Monitor | Nominal

Minimum

Machine
Maximum | Cycle Time

Point

Setting | High Margin | Low Margin| at Nominal

N21D2

250 ns

N/A

4.5 ms

N/A

Teletype Clock | M28K2

Setting

(220 Hz)

.re

Conditions

1.0 ps

1/O time

Double check

by running
Teletype

diagnostic

7-24

Reader’s Comments
PDP-15 SYSTEMS MAINTENANCE MANUAL
VOLUME 1
EK-15001-MM-004

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