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EK-1184A-TM-PR2

May 1985

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Document:	PDP-11/84 System Installation and Technical Reference Manual
Order Number:	EK-1184A-TM
Revision:	PR2
Pages:	338
Original Filename:

OCR Text

EK-1184A-TM-PR2

PRELIMINARY
PDP-11/84

- SYSTEM INSTALLATION
AND

Y_—YTY®
an
I 1}

TECHNICAL REFERENCE MANUAL

I
Jaiilaliltlall

EK-1184A-TM-PR2

PRELIMINARY

PDP-11/84
SYSTEM INSTALLATION
AND

TECHNICAL REFERENCE MANUAL

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, May 1985

C>Qigital Equipment Corporation 1985.
All Rights Reserved.
Printed

in U.S.A.

oses and
ment is for informationalnotpurp
The material in this docu
be construed
out notice; it should ion.
is subject to change with
Digital
orat
Digital EquipmentonsiCorp
as a commitment by
bility for any errors
ion assumes no resp

~ Equipment Corporat

that may appear in this document.

assumes no responsibilitythatforis the
Digital Equipment Corporation
not
use or reliability of its software on equipment
supplied by Digital.
NOTICE:

o frequency
uses, and may emit dradi
This equipment generates,
ly with
been tested and foun to comp
energy. The equipment has utin
g device pursuant to Subpart J

s A comp
the limits for a Clas
provigde resonable
s, which are designed tointe
Rule
FFC
of
15
Part
of
ence when
radio frequency Operrfer
protection against such
n of this
atio
ronment.
a commercial envi
operated in resi
in which
ence
rfer
dential area may cause inte
equipment in a
measures
take
ired to
nse may be requ
case the user at his own expe
.
to correct the interference

The

following

Corporation:

d]ifa]i[t]a] I
DEC
DECmate
DECUS
DECwriter
DIBOL
LSI-11
MASSBUS

are

trademarks
Micro/PDP-11
MicroVaxX
PDP
P/0S
Professional
Q-Bus
Rainbow
RSTS

Digital
RSX
RT
UNIBUS
VAX

Equipment

VAXcluster
VMS
VT
Work Processor

TABLE

CONTENTS
PAGE

CHAPTER

SYSTEM

INTRODUCTION

.
.
o
.
INTRODUCTION .1.1
.
.
.
SYSTEM COMPONENTS AND VARIATIONS
1.2
1.2.1
KDJ11-BF Processor Module
.
.
.
.
.
.
.
KTJ11-B UNIBUS Adapter ModulE
1.2.2
1.2.3
MSV11-JB/JC Memory Module
.
.
.
.
.
.
o
.
.
.
UNIBUS Terminator
1.2.4
1.2.5
Monitor and Distribution Module.
.
.
1.2.6
Minimum Load Module
.
.
.
.
.
1.2.7
Power Supply
.
.
.
.
.
.
.
.
.
.
Console Serial Line Board
1.2.8
.
.
.
.
.
Backplane Assembly .
1.2.9
.
.
.
.
.
Front Panel Assembly
1.2.10
.
.
.
.
Controller
Power
Cabinet
1.2.11
.
e
.
.
.
Cabinet Blower Unit.
1.2.12
1.2.,13
Box Cooling Fans
.
.
.
.
.
.
Additional Expansion and Memory Options.
1.2.14
1.3
SYSTEM SPECIFICATIONS.
.
.
.
.
.
.
o
.
.
.
.
RELATED DOCUMENTS.
1.4
CHAPTER 2

1-1
1-2
1-5
1-6
1-6
1-6
1-6
1-6
1-6
1-7
1-7
1-8
1-8
1-8
1-8
1-8
1-9
1-14

o
.
.

2-1
2-1
2-2

SITE PREPARATION AND INSTALLATION

.
o
.
.
.
.
SHIPPING SPECIFICATIONS
2.2
o
o
.
UNPACKING INSTRUCTIONS.
2.3
.
.
.
.
Cabinet Unpacking
2,3.1
.
.
.
.
.
Box Unpacking
2.3.2
2.4
SYSTEM INSTALLATION
.
o
.
.
Cabinet Mechanical Installation.
2.4.1
.
Box Mechanical Installation.
2.4.2
.
Console Serial Line Hookup .
2.4.3

.
.
SITE PREPARATION .
2.1
Cabinet Site Preparation
2.1.1
.
Box Site Preparation
2.1.2

o
.
.

.
.
.
.
o
.
o
o
o
.
.

2.4.4
Cabinet Switch Settings.
.
.
.
2.4.5
Box Switch Settings.
.
.
.
.
2.4.6
Cabinet Power Hookup
.
.
.
.
2.4.7
Box Power Hookup
.
.
.
o
2.5
SYSTEM CONTROLS AND INDICATORS
.
.
2.5.1
Front Panel.
.
.
.
.
o
o
2.5.2
Console Serial Line Distribution Board
2.5.3
Serial Communications Port .
.
.
2.5.4
Baud Rate Select Switch.
.
.
.
2.6
SYSTEM HARDWARE CONFIGURATION,
o
o
2.6.1
KDJ11-BF Module Configuration
.
.
2.6.2
KTJ11-B Module Configuration
.
o
2.6.3

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.

Monitor and

Distribution Module

iii

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.

.
.
.
.
.
.
.
.
.
.

.
.
.
.
.
.
.
.

Configuratio

2-4

2-5

2-5
2-5
2-5
2-6
2-6
2-8
2-9
2-11
2-13
2-13

2-14
2-14
2-17
2-17
2-17
2-18
2-19
2-19

2-20

-4

o
L]
e

o
]

2-28
2-31

3-37

2-31
2-32
2-33
2-34

]

Cabinet SPC Cable Routing

2=27

Box SPC Cable Routing

.
.

[}

.
.

SPC Backplane Locations
SPC MODULE INSTALLATION

]

Expansion Backplane Installation

NPG and BG Jumper Lead Routing
Backplane Power Connections .

2-23
2-24
2=25

EXPANSION BACKPLANE INSTALLATION

2-20

(-]

Minimum Load Module

[

MSV11-JB/JC Module Configuration

CABINET BATTERY UP UNIT INSTALLATION
BOX BATTERY BACK UP UNIT INSTALLATION

[

[}

[

L]
]

[
[
°
[]

L]
L]
L]
[]
[
e
[
[
L)
[]
®
[

o
o
o
&
o

Program Interrupt Request Register

Configuration and Dlsplay Reglster

CPU Error Register

Maintenance Register.

Page Control Register

STACK LIMIT PROTECTION.

.
o

.
.

Boot and Dlagnostlc Controller Status Regi

Line Frequency Clock and Status R‘aglstero

KERNEL PROTECTION

TRAP AND INTERRUPT SERVICE PRIORITIES
iv

Processor Status Word

ADDITIONAL CPU REGISTER DESCRIPTION

—

[

o
o
o
.

.
0
.
o

Hit/Miss Register

o
o
.
.

(D o

o
KDJ11-BF Cache Operatlons
KDJ11-BF Cache Organization .
o
.
Cache Control Register
er
Memory System Error Regist

KDJ11-BF CACHE

o
.
.
.
o

Memory Relocation

o
.
o
o
o

.
e

Memory Management Register O.
Memory Management Register 1.
Memory Management Register 2.
Memory Management Register 3,
Physical Address Construction.

o
o

)
,eoooooeooevooooeo

o
6

06 o

.
.

OJO UL

Page Descriptor Registers

[

.
.
.

(]

UNIBUS Device Interrupt Requests
PMI Data Transfer Address Cycle
.
PMI Data Transfer Protocol
PMI Data In Cycles (DATI) and
PMI Block Mode Data In Cycles

.
o

[}

.
.

"W N+
W+

L]
[
L.
]
®
e
e

.
.

PMI Data Out Cycles .
.
MEMORY MANAGEMENT .
ers
Regist
Page Address

[

® L] [} L] [ ] L} [} ® ] L J [ ] L] [ [
R
R R GG EGES KRG
RV RV

[]

[

]

oo~Joanese WK

DMA Requests

PMI BUS DESCRIPTION
PMI BUS Acquisition

INTRODUCTION

[ L) (] L} [ [ [ ] [ [
e o [ ] Ld [ ] [
L WWWWWWWWwWwioNNNDDNDN N
e L] ) ® L) . [ .
L] [} [ [ [ ] [

wwuwuwwwuuuwwwwwwww

CHAPTER 3 FUNCTIONAL DESCRIPTION

W
-

Read
MAPPING

[
.
[
[
[

3-71
3-76

Configuration Register
AND CONFIGURATION REGISTERS

MODE

ROM

PROGRAMMING

DESCRIPTIONS

¢
&
¢
&

[]

o
©
g
©
o
©
&
&
4
©®
o
©
¢
©®
¢

o
©
¢
o
e
®
e

[
TM
o
e
L]
.
[
)
[]
]
Ed
L4
©

List

Command
Setup Command
DIAGNOSTIC ERROR MESSAGES
BOOTSTRAP PROGRAMS

Bootstrap

[

o
8
o

Setup

Command

Setup

[

Setup

Command
Command

Command

Setup

Command
Command

Command

Setup

Command

Setup

Setup
Setup

DESC RIPTIONS

COMMAND

Command
Command

MODE

Setup

.
.

Command

Map
Test

Command
List Command
Setup Command

Setup

3-79
3-79

Command

Setup

3-76
3=-77

Setup

DIAGNOSTIC

COMMAND

[

3-65
3-67

Boot

Y
[.]

BOOTSTRAP AND

Help

Diagnostic Controller Status
Diagnostic Data Register.
Diagnostic DATI NPR Cycles
Diagnostic DATO NPR Cycles

[ J

®
°

.1
.2
.3
.4

s
O

OO0

Operations

3-62
3-63
3-63
3-64

DIAGNOSTIC

&
o
¢
o
®

[)

UNIBUS Mapping Registers.
Optional UNIBUS Memory
.

H
N
M WO

Cache

Memory

3-58
3-59
3-59
3-60
3-61

Enable/Disable.
Write Operations

DMA

SETUP

3-56
3-57
3-58

[]

> W+

DMA Cache
DMA Cache
UNIBUS

ADUTLEWN

I
I
N

3-54

COUNTER

INTRODUCTION

3-54

[

PMG

DIALOG

Status

UNIT

KTJ11-BF CACHE OPERATIONS .
KTJ11-B Cache Organization

4.1

LINE

¢«
o

Receiver

CHAPTER

SERIAL

Receiver Data Buffer.
Transmitter Receiver Status Reglster.
Transmitter Data Buffer Register.
Break Response
KERNEL/SUPERVISOR/USER MODE DESCRIPTIONS

B BB WWWWRNNRNRNDNFO:
BB

WWWWWwWLwWwWwuwWwwuwwwuwuwwwww
w

CONSOLE

[

[
L)
[
L]
[)
L]
[
[

L] [)

L]
°

4.6.5
4.6.6
ROM Data Organization
4.6.7
o
.
Jll1 MICRO ODT .
4.7
/ (ASCII 057) Slash .
4,7.1
<CR> (ASCII 015) Carr iage Return
4.7.2
KLF> (ASCII 012) Line Feed
4.7.3
d nat
$ (ASCII 122) Internal Register Desig
4,7.4
o
-~ G (ASCII 107) GO
4.7.5
P (ASCII 120) Proceed
4,7.6
Binary Dump
~S (Control-Shift-S)
4,7.7

[

Single ROM Programs .
Multiple ROM Programs
.
Program Headers .

ROM Addresses
ROM Formats .

o
.

.
o

Boot ROM Installation

000000.‘.0.0.00.

BOOT ROM FACILITY (M9312 compatible)

.
[ L)

Format

General Rules For EEP ROM User Bocts

4.6
4.6.1
4.6.2
4.6.3
4.6.4

EEPROM

[]

[

v U

CHAPTER 5 SYSTEM MAINTENANCE
INTRODUCTION

DIAGNOSTIC TYPES

CONSOLE TERMINAL ERROR MESSAGE FORMAT .
.
Console Error Message Description

.
.

o
o

Unexpected Trap and MMU Error Code Descriptions

Boot Program Error Codes/Messages
SYSTEM TROUBLESHOOTING AIDS

[ ]

[]

[

KTJ11-B UBA Module
Mimimum Load Module

[

.
.

FIELD REPLACEABLE UNITS

L ]

MSV11-JB/JC Memory Module

KDJ11-BF CPU Module

.
o

.
.

Front Panel
MDM Module

MODULE REPLACEMENT/REMOVAL PROCEDURES

General Module Removal/Replacement
CPU Module Removal/Replacement

POWER SUPPLY REMOVAL/REPLACEMENT

[ 2

Cabinet Power Supply Removal/Replacement
L[]
L
©

[}

-~ O O O

[]

Box Power Supply Removal/Replacement
CABINET BLOWER REMOVAL/REPLACEMENT
BOX FAN REMOVAL/REPLACEMENT
FRONT PANEL REMOVAL/REPLACEMENT

[]

5.12

[

[]

[

[)

Cabinet Front Panel Removal/Replacement
Box Front Panel Removal/Replacement .
.
.
CIRCUIT BREAKER REMOVAL/REPLACEMENT
ment
place
al/Re
Remov
er
Cabinet Circuit Break
1.1
Box Circuit Breaker Removal/Replacement .
5.11.2

[

CABINET POWER CONTROLLER REMOVAL/REPLACEMENT

SLU INTERFACE ASSEMBLY REMOVAL/REPLACEMENT
5.13
Cabinet SLU Assembly Removal/Replacement
5.13.1
Box SLU Assembly Removal/Replacement
5.13.2
.
CPU BACKPLANE REMOVAL/REPLACEMENT .
5.14

.5.14.1

Cabinet Backplane Removal
\Y i

.
.

[)

.
5.14.2 Box Backplane Removal
5.15 CABINET PERIPHERAL ACCESS .

.
.

APPENDIX A CPU INSTRUCTION TIMING

APPENDIX B PDP-11/84 and HARDWARE/SOFTWARE DIFFER@NCES
APPENDIX C PINOUT BACKPLANE TEST CONNECTORS J18 AND J19
.

APPENDIX F V7. - V6.0 ROM CODE DIFFERENCES

APPENDIX D BACKPLANE PIN ASSIGNMENTS .
APPENDIX E SYSTEM INTERCONNECT DIAGRAM

APPENDIX G MULTI BOOT CONTROL TRANSFER

APPENDIX H BOOT AND CONFIGURATION REGISTER MODIFICATION
APPENDIX I FLOATING POINT INSTRUCTION TIMING .
APPENDIX J SET-UP PARAMETER WORKSHEETS

vii

CHAPTER 1

SYSTEM INTRODUCTION

1.1

INTRODUCTION

The A

Series

PDP-11/84

(PDP-11/84-A)

high

performance

point
microprocessor with floating uctio
computer containing a J11 ssor
n
instr
1
executes the PDP-1
accelerator (FPA). The proce
n'’s
ratio
Corpo
ment
on Digital Equip
set. The system operates
t memory addressing capabiltiy.
18-bit UNIBUS with a 22-bi

The system is available in two configurations:

ion packaged in a
PDP-11X84: a kernel system configurat
of the
top portion
The
42-inch cabinet. (See Figure 1-1.)
lling
insta
for
cabinet provides a 10.5-inch enclosure
peripherals.

m configuration
PDP-11/84: an expansion box kernel syste
packaged in a 10.5-inch rackmountable enclosure. (See
Figure

1-2.)

NOTE

The "PDP-11/84" system
this

manual

designation

used

1in

implies that the context applies to

both cabinet and box configurations.

— Tt 11

X11%

»i

INTRODUCTION

SYSTEM

FIGURE

1-1

1-2

PDP-11X84

CABINET PRODUCT

PDP-11/84

1-2

BOX

PRODUCT

SYSTEM -INTRODUCTION

1.2 SYSTEM COMPONENTS AND VARIATIONS

cabinet and box product is shown
The system block diagramnelforsysthe
'
tem consists of:
in Figure 1-3. The ker
1.

A KDJ11-BF processor module (CPU)

-JC 2 MB

V11l
2. An MsV11-JB 1 Mb ECC), memory module(s), or an MsSv
ECC memory module(s

A KTJ11-B UNIBUS Adapter Module (UBA) ,
A Monitor and Distribution module (MDM), and
5. One or more Minimum Load Modules (MLM).

3.
4.,

vate Memory
through the high-speedbit Pri
The modules communicate usin
data lines.
g 22-bit address/l16Interconnect (PMI) bus

rd
munication standa
g the EIA RS-232 com
A console port supeportin
B
11KDJ
the
into
sol terminal to be connected
enables a con
processor module.
and the UNIBUS. n The
erfaces to the PMI bus
The KTJ11-B UBA intts
the
ications betwee
ress/data commun
por all addUNI
UBA module sup
In
.
ns)
tio
BUS periherals the(opCPU
all
processor memoryUBAand
the
of
end
serves as a terminator for
addition, the
UNIBUS.

CONSOLE

TERMINAL

i
|

KDJ11-BF
cPu.

-8
]|1 | xTat
UNIBUS

ADAPTER
MEMORY |, | (UBA)

msvit-s

oMl BUS

@ UNIBUS

MEMORY

<::>PER|PHERAL l
UNIBUS

Lfop'q 1/84-P SYSTEM CABINET AND 80X
FIGURE 1-3 PDP-11/84 SIMPLIFIED BLOCK DIAGRAM
1-3

SYSTEM

INTRODUCTION

The basic cabinet and box components are shown in Figures 1-4 and
1-5.

The following subsections briefly describe the basic system

components.

—

FRONT BEZELIBLANK)

POWER CONTROLLER

- CARD CAGE COVER

POWER SUPPLY
CIRCUIT BREAKER

CARD
CAGE

FIGURE

1-5

BASIC

BOX

HARDWARE

1-4

COMPONENTS

SYSTEM INTRODUCTION

Table 1-1 specifies the system variations.
TABLE 1-1 A-SERIES PRODUCT VARIATIONS

11/84-AA

KDJ11-BF, MSV1l1l-JB 1 MB

11/84-AB

KDJ11-BF, MSV11l-JB 1 MB

11/84-BA

Same as 11/84-AA except MSV11-JC 2 MB

11/84-BB

Sahe as 11/84-AB except MSV11-JC 2 MB

11X84-AA

KDJ11-BF, MVS1ll1l-JB (JD)

11X84-AB

KDJ11-BF, MSV11-JB (JD) 1 MB

11X84-BA

Same as 11X84-AA except MSV11-JC 2 MB

11X84-BB

Same as 11X84-AB except MSV11-JC 2 M

10.5-inch Box,

120 Vac

240 Vac

40-inch cabinet,

120 Vac

1 MB

240 Vac

1.2.1 KDJ11-BF Processor Module

The KDJ11-BF (M8190-AE) is a quad-height CPU

complete functionality of a PDP-11 processor.

module

having

the

The KTJ11-B UNIBUS

Adapter Module allows the CPU to interface with Digital's UNIBUS.

The module features a: J1ll microprocessor, FPA, 22-bit memory
management, 8KB cache memory, programmable line frequency clock,
console serial line unit, an alterable configuration EEPROM, and
boot and diagnostic ROMs.

In addition the KDJ11-BF has
diagnostic information during

six red
power-up

LED's for displaying
and bootstrapping. A

single green LED indicates dc power to the module.

INTRODUCTION

SYSTEM

1.2.2

KTJ11-B

UNIBUS

Adapter

Module

The KTJ11-B UNIBUS Adapter (M8191) is a
hex-height
module
that
interfaces
with
the
KDJ11-BF
processor and memory through the
PMI.
The
module
contains:
the
PMI
adapter
1logic¢,
UNIBUS
mapping,

1.2.3

and

four M9312

MSV11-JB/JC

compatible

Memory

uses

256K

capacity

MSV11l-JB

(M8637-B)

with

MSV11-JC

(M8637-C)

with a

The modules

byte/word,
the

PMI

sockets.

dynamic

RAMs,

and

versions:

two

ROM

Module

The quad-height memory module
available

boot

1MB

2MB capacity

provide error correction

logic, and

supports

write

double-word read, and block mode read operations over

bus.

uncorrectable

red

error;

LED

1indicates

the

occurance

a green LED indicates the presence of 5 Vdc

power.,

1.2.4

UNIBUS

The UNIBUS

Terminator

characteristic
end of

1.2.5

the

UNIBUS

Monitor

(M9302)

impedance of

and

1is

120

resistive

ohms.

and provides

the

Distribution

Module

network

with

The module terminates one

SACK

turnaround

feature.

The Monitor and Distribution Module (MDM) is a guad-height module
(M7677)
and
includes:
power supply voltage indicators, voltage
test points, fan/blower rotation monitor and
nonprocessor
dgrant
(NPG)

jumper

l1.2.6

Mimimum Load

The

selection

double-height

load
module

1.2.7

for

the

includes

Power

switches.

Module

Minimum Load

Modules

(MLM)

=15 Vdc and +5 VBB power
two power

supply

LEDs,

provide

one

for

each

minimum

Each

regulator.

Supply

Dc System power is provided by two power supplies:
H7202-KB.

supply regulators.

H7202-KA

and

SYSTEM INTRODUCTION

The H7202-KA power supply provides:

60 A at +5 Vdc,

+15

240

Vac

It also provides 3 A at +12 Vdc for
vde, +3 A at =15 Vdc.
The
fans/blower and up to 15 A at +5 Vdc to the PMI memory.
A
tion.
protec
ating
overhe
and
ltage
power supply provides overvo
either

120

Vac

The H7202-KB power supply provides power

for

additional

switch allows the user to

primary power operation.

expansion)

operated

backplanes.

overheating

power:

120

240

protection.

select

Similar
Vac,

the

H7202-KA,

can be

overvoltage

features

and

(i.e.,

and

The power supply provides the following

32 A at +5 Vdc, 2 A at +15 Vdc, and 3 A at -15 Vdc

1.2.8 Console Serial Line Board

an EIA
des:
The console serial 1line board (54-16058-) provi
for communication with the KDJ11-B, a
port
I/0
RS232-C
console I/0 port
ten-position rotary switch for selectingionthe
switch for selecting a
baud rate, and a two-position posit
restart mode.

1.2.9 Backplane Assembly

0650-01) is a
As shown in Figure 1-6, the backplane assemblyMDM(70-2
through 4 are
Module slots
13-module slot backplane.
through 11 support hexdedicated to the system kernel. Slots 5 oller
s (SPCs). Slot 12
Contr
or quad-height Small Peripheral
Backplane NPG
es.
supports only guad-height UNIBUS option12modul
d in a DIP
mente
are imple
jumper functions, for slots 5 through
switch located on the MDM module.

ROWS

(MDM) M7677

MOM
1

(XDJ11-8) MB190

(MSV11- J) MB837

M7858

IKTJ11-8) MB191

HEX OR QUAD UNIBUS OPTION

SLOTS 6
?

HEX OR QUAD UNIBUS OPTION
KEX OR QUAD UNIBUS OFTION

P2
L]

MEX OR QUAD UNIBUS OPTION

] PRIOR

¢ | MoDiReD
UNIBUS

"‘&‘:"“:‘s"

‘:}"g"‘l‘fs"

12 | UNiBUS
FIGURE

MEX OR QUAD UNIBUS OPTION

HEX OR GUAD UNIBUS OFTION
MEX OR QUAD UNISUS OPTION

OUAD UNISUS OFTION

MTS58

1-6 BACKPLANE ASSEMBLY
1-7

»”

SYSTEM

INTRODUCTION

1.2.10

Front

The

front

Panel

panel

Assembly

assembly

(70-21888-01)

includes

switches

and

indicators for status display and operator control of the system.
A keyed rotory switch selects one of four
power
states,
and
a
toggle switch selects system halt or restart modes.
1In addition,
three LEDs display the system status, and a two-digit
octal
LED
displays

1.2.11

The

diagnostic

Cabinet

cabinet

error

Power

status.

Controller

contains

either

877-D power

controller

for

120

Vac

operation,
or
an
877-F
controller for 240 Vac operation.
The
unit controls all AC power entering
the
cabinet.
It
provides
primary
power for all the power supplies, and the two AC outlets
located

1.2.12

The

the

top

Cabinet

cabinet

peripheral

Blower

Unit

cooled

enclosure.

blower

wunit

(12-22001-01)

mounted

below
the
<card cage.
Air is drawn through the top front of
cabinet, forced through the card cage by a
plenum,
through
power supply, and out through the rear of the cabinet.
The

blower

supply
must be

capable

cooling

and
an
optional
1installed
during

the

optional

expansion

UNIBUS ‘backplane.
The
operation
to
insure

kit

the
the

power

card cage cover
proper
module

cooling.

1.2.13

The

box

bezel.
directs
supply,

1.,2.14

The

Box Cooling

product

Fans

cooled

three

fans

The
fans
draw air through
the air horizontally through
and out the rear of the box.

Additional

Expansion

system supports

the

and

the

front

the front bezel and a
the
card
cage
and

plenum
power

Memory

mounted behind

Options

following

options:

Battery Back

Up Unit

H7231-E,

Cabinet

H7231-F,

Box Battery Back

Up Unit

DD1l11-CK,

4-slot Backplane

(PDP-11X84)

DD11-DK,

9-slot Backplane

(PDP-11X84)

1-8

(requires

M7677-YA)

ON
EM
' INTRODUCTI
SYST
1.3 SYSTEM SPECIFICATIONS

The following tables list the PDP-11/84 system specifications.
Table 1-2 through Table 1-4 1list the cabinet specifications;
specifications.
Table 1-5 through Table 1-7 1list the box
ned in the
contai
are
ns
icatio
Supported peripheral device specif
user's guide associated with that device.

TABLE 1-2

CABINET ENVIRONMEMTAL SPECIFICATIONS

Temperature:

Operating

10 deg C to 40 deg C

Nonoperating

-40 deg C

(storage)

Humidity:
Operating

(50 deg F to 104 deg F)
to 66 deg C

(-40 deg F to 151 deg F)

108 to 90% with max wet bulb temp.
28 deg C (82 deg F) and a min dew
point 2 deg C (36 deg F) non
condensing.

Vibration
Operating

Nonoperating

(packed for
shipment)

5 to 22 Hz:0.01 in DA; 22 to 500 Hz
0.25 Gpk. Sweep rate of 1.0
octave/min. All three axis.
Vertical Axis Random Vibration: 0.687

Grms overall from 10 to 200 Hz;
duration: 1 hr each axis.

Altitude:

ft)

Operating

0 to 2.4 km (8000

Nonoperating

9.1 km

Maximum operating
with altitude

maximum operating (40 deg C) should
be reduced 1.8 deg C/ 1000m

(30000 ft)

(1 deg F/ 1000 ft) above sea level

Shock:

Operating

Nonoperating

(packaged for
shipment)

10 Gpk for 10 ms

wave,

(+3 ms),

vertical axis only

1/2 sine

Flat drop from a 6 in height, three

drops total (vertical direction only)

SYSTEM

INTRODUCTION

TABLE

WD CED

Overall

N0 MO

D 4ED SN

1-3

CABINET

CED GEN TR AP S

dimensions

GED GED CED

MECHANICAL

WD G

GRS

IR GED GED

D G

TS T

SPECIFICATIONS

CH)

D TED WD O

G50 T

105.7 cm high X 53.9 cm wide X
76.2 cm long (41.64 in high X
21.25

in wide

X 30

Unpacked

150.5

(331

1b)

Packed

182.2

(401

1b)

long)

Weight:

TABLE

1-4

CABINET

ELECTRICAL

Characteristics
D

CED

SPECIFICATIONS

Description
R S

120 Vac operation:
Line voltage

CED S

132

47.5-63

Current

13.5

(rms)

Power

factor

Greater
and low

Start

Up Current

100 A,

Inrush

current

160

D e

CH)

D CED

D G

single-phase,

(120 Vrms

Frequency

GRS

Vrms,

and ground

(ac)

max

2880

BTU
240

'
Vac

Line

120

max

120

Vac,

V-A max*

operation:
186

- 264 Vrms, single-phase,
two-wire and ground (240 Vrms
nominal)

47.5-63

Current

6.7 A

(ac)

(rms)

load

usec duration

(peak)

Frequency

—

Vac

3519

voltage

two-wire

than 0.60 at full output
input voltage (93)

0.16

nominal)

duration

Power

max

240

Vac

0.16

usec

SYSTEM

(Cont)

TABLE 1-4
——

D TS A

INTRODUCTION

S W VS WP N GED VAR GED AR M W SR W G GNS D G

e e

Power

factor

Greater than 0.60 at full output lcad

Start

Inrush

and

Current

low input voltage

0.16

160 A

current

usec

(peak)

(186 Vac)

duration

max at

240 Vac, 0.16

duration
Power

2880

BTU

3519

Noise

Transient:

(both

line voltages)
1KV peak

High-energy

spike

containing

not

than 0.2 W of energy per spike

transients
Conducted

V-A max*

Cw-10

noise

Including mass

storage

TABLE

KHz

MHz,

3 Vrms

devices

1-5

BOX ENVIRONMEMTAL

Characteristic

SPECIFICATIONS

Description

Temperature:

Operating

5 deg C to 50 deg C
(41 deg F to 122 deg F)

Nonoperating

-40

(storage)

deg

(-40 deg F to 151 deg F)

Humidity:

Operating

10% to 95% with max wet bulb temp.
32 deg C (82 deg F) and a min dew
point 2 deg C (36 deg F) non
condensing.

usec

SYSTEM
TABLE

INTRODUCTION
1-5

(Cont)

Vibration:
Operating

5 to 30 Hz: 0.0l in DA; 30 to 500 Hz:

0.5 Gpk. Sweep rate of 1.0
octave/min. All three axes.

Nonoperating

(packed for
shipment)

Vertical Axis Random Vibration:
Grms overall from 10 to 200 Hz;
duration: 1 hr each.

0.687

Altitude:
Operating

Nonoperating

9.1

2.4
km

(8000

(30000

ft)

Shock:

Operating

Nonoperating

10 Gpk for 10 ms (+3 ms),
wave, vertical axis only
Flat

drops
Maximum

operating with
altitude

drop

from a

total

1/2

height,

sine

three

(vertical direction only)

Maximum operating (40 deg C)
be reduced 1.8 deg C/ 1000m

should

Mechanical:

Overall

dimensions

47 cm wide X 67.5 cm long X
26 cm high (19 in wide X 27
long X 10.44 in high)

Weight:
Unpacked

42.75

Packed

(130

(95

1b)

SYSTEM

TABLE

120

Vac

Line

1-7

BOX ELECTRICAL SPECIFICATIONS

operation:

voltage

and
47.5

Current

8.0

Start

(ac)

factor

Inrush

Current

current

132

Vrms,

ground

Frequency

Power

INTRODUCTION

(120

single-phase,

Vrms

(rms)

max

120

Greater

than

0.60

and

Vac

nominal

120
A,

two-wire

nominal)

0.16

usec

Vac

full

output

input

voltage

load

duration

80 A (peak) max at 120 Vac, 0.16 usec

duration
Power

650

BTU

2218

240

Vac

Line

W MAX

operation:

voltage

180

264

two-wire

Vrms,

and

single-phase,

ground

(240

Vrms

nominal)
Freguency

47.5

Current

5.0

(ac)

Power factof
Start

Inrush

Current

current

(rms)

max

Greater

than 0.60

-and

Vac

240
A,

0.16

usec

(peak)

max

650w MAX

240

nominal

duration
Power

Vac

full

ocutput

input

voltage

load

duration

240

Vac,

0.16

usec

SYSTEM INTRODUCTION

TABLE

1-7

(Cont)

Noise

transient:

(both line woltages)
High-energy

1 KV peak spike

transients

not more than 0.2 W of

energy per

Conducted noise

1.4

Table

1-8

containing

spike

CW-10KHz to 30 MHz,

3Vrms

DOCUMENTS

lists

the

TABLE

PDP-11/84

related documents.

1-8 PDP-11/84 RELATED DOCUMENTS

PDPl]l Bus Handbook

EB-17525-20

PDP-11/84-A Installation and Technical Manual

EK-1184A-TM

PDP-11/84 Site Preparation,
Installation

Unpacking,

and

EK-PDP84-1IN

Guide

PDP-11/84-A System Field Maintenance

Print Set
Cabinet:
Box:

MP-02199
MP-02198

KDJli—B User Guide

EK~-KDJ1B-UG

MSV11-J

EK-MSV1J-UG

User Guide

Chipkit Handbook

EJ-01387-92

DCJ11l

EK-DCJ11-UG

User Guide

EB-26085-41/85

Microsystem Handbook

1-14

SYSTEM

Printed

copies

Digital

Equipment

444

Whitney

Northboro,

ATTN:

the

above

listed

documents

may

Corporation

Street

Massachusetts

01532

Printing énd Circulation Services (NR2/M15)

Customer

Services

Section

INTRODUCTION

ordered

from:

CHAPTER
SITE

PREPARATION

AND

INSTALLATION

IMPORTANT

acceptance
and
installation
system
Following
testing,
refer
to
Appendix
J
and fill in the
Parameter worksheets.

Set-up

The completed worksheets are to remain
with
the
system
to
allow duplicating the original set-up

parameter selections on

KDJ11l-BF

replacement

CPU module.

2.1

SITE

PREPARATION

In order to
use
a
PDP-11/84
system;
the
space
requirement,
environmental
operating
limits
and
the
electrical
power,
available at the site, should be part of
the
site
preparation.
The specifications are listed in the following subsections.

2.1.1

Cabinet

Physical

Site

Space

Width
Height
Depth
Weight
Environmental

Preparation

Specifications

Requirements:

53.25

cm (21.2 in)
105 cm (41.6 in)
75 cm (31.5 in)
150 kg (331 1b)
Operating

Limits:

Operating Temperature:

Relative Humidity:
10% to 90% with max wet bulb
deg
C
(82
deg
F)
and
min
dew point 2 deg C
non-condensing

temp.
(36 deg

Storage

Temperature:

deg

151

104

deg

10 deg C to 40 deg C ( 50 deg

=-40

deg

2-1

deg

(-40

SITE

allowable
maximum
with Altitude:
Derating
Temperature
reduced by 1.8 deg C per
be
should
temperature
operating
(1 deg
every 1000 m the system is operated above sea level.

INSTALLATION

PREPARATION AND

per

1000

Electrical

Depending

ft)

Power

Reguirement:

the site

line voltage,

two

power

controllers

are

available:

877-D Power Controller:

Voltage (93

120

132

47.5

Frequency =

877-F Pdwer Controller:

Vac Nominal

Vrms)

63 HZ

Voltage - 240 Vac Nominal
(186

264 Vrms)

Frequency -

47.5

NOTE

A dedicated circuit
from
the
power
source
is
recommended for each system.
This circuit should
provide
an
isolated
ground
path
between
the
receptacle an the power source.
The power system
should be stable and free from electrical noise.

Do
not
connect
any
conditioners,
office
the

same

The user must
receptacle(s).
NEMA AC

circuit with

supply

Electrical

the

for

for 240V service:

120V service:

The power cord provided
either a NEMA L5-30P, or

2.1.2

Box

Site

following

Receptacle

eqgquipment
such
as
air
copiers, or coffee pots, on
the system.

electrical

and

Required:

NEMA L5-30R

NEMA 6-15R

(rated

30 A).

15 A).

is
approximately
14
a 6-15P plug attached.

Preparation

power

Specifications

feet

1long,

with

SITE

PREPARATION

AND

(41 deg F to

INSTALLATION

Physi&al Space Reguirements:
Width
Height
Depth

47.5 cm (19.0 in)
26 cm (10.4 in)
67.5 cm (27.0 in)
43 kg (95 1b)

Weight
Environméntal

Operating

Limits:

Operating Temperature:

deg F)

Relative Humidity:
deg

(90

deg
non condensing

deg

and

Derating

1000

(90

Frequency

the

Power
120

132

with

temperature

F pqr 1000 ft)

Voltage

deg

dew

C to

point

deg C

deg

(=40

operating

Electrical

minimum

=40

Tem&erature
every

50 deg C

10% to 95% with max wet bulb

Stoqage Temperature:
151

deg C

system

Altitude:

maximum

should

reduced

above

be
operated

sea

1.8

temp.
(36

deg

level.

Nominal

Vrms)
-

47.5

Voltage - 240 Vac
(180 to 264 Vrms)

Nominal

Frequéncy - 47.5 to 63 HZ
NEMA

EHlectrical

Receptacle

Requirement:

NOTE

fihen switching the power supply

input voltage

240 Vac operation, the power cord

must

from

the

120 Vac

(shipped

configuration)

changed.

IZQ Vac

service:

NEMA

5-15R

(rated

15A)

also

32
F)

allowable

deg

Requirement:

Vac

122

the

per

deg

SITE PRERARATION AND INSTALLATION

240 Vac service:

NEMA 6-15R (rated @ 15A)

a NEMA
75 inches long, with either grou
The power cord provided P isplug
nd is
attached. If an isolated
5-15 P, or a 6-15
ptacle numbers with "IG".
provided, prefix NEMA rece

2.2 SHIPPING SPECIFICATIONS

ucts (BOX and
SHIPPED information. Prodaine
This section provides AS
rs as shown
cont
d
boar
CABINET are shipped in reinforced card
in Figures 2-1 and 2-2.

Box Container:

Width:
Height:
Length:
Weight:

57.5 cm (23 in)
50.8 cm (20 in)
77.5 cm (31 in)
56 kg (125 1b)

FIGURE 2-1 BOX SHIPPING CONTAINER
Cabinet Container:

Width:

Heights:
Length
Weight

86 cm (34 in)

139 cm (55 in)
107 cm (42 in)
182 kg (401 1b)

FIGURE 2-2 CABINET SHIPPING CONTAINER
2-4

SITE

2.3

UNPACKING

PRERARATION

AND

INSTALLATION

INSTRUCTIONS

Read the following steps prior to unpacking the

<cabinet

box

product.

2.3.1

Cabinet

Unpacking

The
wunpacking
container.
To

instructions
are
1located
open the shipping container

inside
complete

the
the

shipping
following

steps.

IMPORTANT

Read

warning

labels

remove

plastic

Cut

Remove

top

directions

2.3.2

The

Box

and

outside

container.

strapping.

cover.

packed

inside

Unpacking

wunpacking

container.

instructions

open

the

are

shipping

1located

container

inside

the

shipping

complete

the

following

steps.
IMPORTANT

Read

warning

labels

remove

plastic

Cut

Carefully

Open

2.4

SYSTEM

and

cut

folded

sealing

top

directions

outside

container

strapping.
tape.

container.

packed

inside.

INSTALLATION

To install a cabinet or box read the appropriate
subsection
and
follow
the
procedures.
The
procedures
do not cover optional
device installation.
Option
installation
is
<covered
1in
the
manual supplied with the device.

2-5

SITE PRERARATION AND INSTALLATION

2.4.1 Cabinet Mechanical Installation

To install the cabinet complete the following procedure.
1.

Complete the

1inside

the

After rolling the cabinet down the ramps, position
cabinet on a level surface in the operational area.

the

Reverse step 6 of the unpacking instructions and lower

the

unpacking

shipping container.

instructions

located

four leveling feet. Each foot is lowered until the wheel near the foot - is raised approximately 1/8- to 1/4-inch
above the floor surface.
the

cabinet.

Level

Raise each top nut and tighten it against the cabinet frame
while holding the bottom leveling foot hex nut.

This completes the mechanical installation procedure.
2.4.2 Box Mechanical

Installation

To install a box in an ANSI/EIA standard 19-inch
the

rack,

complete

following procedure.

Locate and check hardware in the box shipping container.

Mount the chassis slide bracket by aligning the rack frame
Secure the bracket to the
holes with the slide bracket.
(no star
frame with a nut bracket and three no.l0 screws
2-3.)
Figure
(See
Tighten the screws.
washers).

Mount the three other chassis slide brackets
frame as

in step

the

rack

SITE

PRERARATION

AND

INSTALLATION

NUT PLATE

Fs/\-;\

“

r";\

FIGURE

Mount

the

2-3

MOUNTING

the

restraint

bracket

CHASSIS

holes

SLIDE

bracket

with

AND

RESTRAINT

the rack frame
rack frame holes,
chassis slide bracket.

the

holes above the mounted
tighten
three no.l0 screws
bracket.

into

the

nut

bars

BRACKET

aligning

starting

Thread
to

secure

two
and

the

Align the right chassis slide (front) clearance
hole
with
the
center
hole
of
the
mounted
chassis slide bracket.
Thread a no.10 screws (with
star
washer)
to
secure
the
chassis slide to the bracket.
Do not tighten.
Align

the

mounted

washers)

two

rear

bracket.

holes

chassis

securing
the
slide bracket.

Tighten

the

chassis

front

slide

Thread

screw

assembly

the

chassis

two

chassis
Tighten

no.l0

slide
the two

securing

bracket.
Secure

the

slide

screws

rear
to
screws.

the
front
front mounted

with

star

the

rear

end
of
the
chassis slide

the left chassis slide assembly to
the
1left
and
rear mounted chassis slide brackets by repeating
4 through 6.

2-7

the

(with

front

steps

SITE PRERARATION AND INSTALLATION

placing

the

Extend the stabilizer bar (if present) before

10.

Lower
forward:
Fully extend both chassis slide assemblies
the
ing
align
,
blies
assem
the box assembly onto the slide the box rail.

box on the slide assemblies.

FIGURE 2-4

11.

AR AR

Q...!QQ...‘......‘

)

chassis slide slot with the tab on

SECURING BOX INTO CHASSIS SLIDE ASSEMBLY

slides by aligning the front
Secure the box to the chassis aded
box hole. Thread a no.8
clearance hole with the thre
screw and tighten.

12.

the rear chassis slide
Slide the box rearward aligning
box bole. Thread a no.8
aded
thre
clearance hole with the
'
screw and tighten.

13.

e it to the rack frame
Slide the box to the rear and secur
screws to the restraint
by threading two, no.8 phillips l.
Tighten the screws.
bracket located on the box rear pane

This completes

the

installation of

standard 19-inch rack.

2.4.3 Console Serial Line Hookup

the box

1in an ANSI/EIA

Install the console serial line as shown in Figure 2-=5.
2-8

SITE PRERARATION AND INSTALLATION

TERMINAL -

CONSOLE

CABLE

]

TERMINAL

'
r

Sty

CONNECTOR —

S
V.,

mNNEflOR+—@L

—

]

J-I

FIGURE

2.4.4

Cabinet

2-5

SERIAL

Switches

Settings

switch

settings

The following

are

LINE HOOKUP

the

required for

-<cabinet

product.
NOTE

Switch settings must be verified before power
applied

the

Set the Forced Dialogue switch to OFF (0).

Set

Set the Baud Rate switch to match
the
(see Figure 2-6.)
console terminal.

Assure

the

baud

that

controller

rate

the

system.

the console terminal.

power

outlet

baud
matches

AC input power requirement.

rate
the

the
power

Model 877-D is

for

120 Vac operation and 877-F is for 240 Vac operation.
The
on a label located on the power
printed
is
number
model
controller.

SITE PRERARATION AND INSTALLATION
WA FTTITIRGTIRY

TR T E TR

;
|

SALO
-ex|

14D

200 | ~
4o
s = 2400

7 = 300

s = 1200

\
{ |

b
BULK HEAQ~

DIL00

[S4

)

{

©°

FIGURE

2-6

CONNECTOR

g //

{ |

SCREW (10}

sAUO

CABINET REARVIEW

Turn the power controller circuit breaker to
position.

See

Figure

the

off

(0)

2-6.

Set the front panel keylock switch

OFF.

(See

Figure

supply

circuit

2-110)

power
both
turn
door,
front
Open the
(See Figure 2-7.)
breakers to OFF (0).
This

completes

the cabinet switch set up.

MODULE

" COVER

v
POWER SUPPLY
CIRCUIT BREAKER

J‘\

\ifl
J

SLOWER

FIGURE 2-7 CABINET FRONTVIEW
2-10

SITE

2.4.5

INSTALLATION

Settings

Switch

Box

PRERARATION AND

The following switch settings are reqguired for the box product.
1.

Slide the box forward to the mechanical stop.

Remove the four top cover screws and lift

Set the power supply input AC voltage
to match
front,
supply
power
the

(See

Figure

cover

off.

2-8.)

(See

voltage.

the

2-8.)

Figure

on
located
switch,
AC power outlet
the

o ®?
oA
=

FIGURE

2-8

BOX

POWER

Reinstall

the

top

cover.

Set

the

Forced

Set

the

baud

rate

Set

the

Baud

Rate

switch

console

Dialogue

terminal.

the

See

SUPPLY

INPUT

switch

console

OFF

SWITCH

(0).

terminal.

match

Figure

SELECT

2-9.

the

baud

rate

for

the

N INSTALLATION
AND
SITE PREPARATIO

4
'\

BULKNEAD """

FIGURE

Set

the

Turn the

This

completes

front

panel

2-9

keylock

circuit breaker
the

box

BOX

switch

REARVIEW

switch

to OFF
set

to OFF.

(0).

See

up.

Qecuir
BAEAKER

FIGURE

2-10 BOX FRONT VIEW

2-12

Figure

2-10.

SITE PREPARATION AND INSTALLATION

2.4.6 Cabinet Power Hookup

Complete the following procedure.
CAUTION

Assure that the wall outlet voltage

line voltage selected for operation.

switch

Assure that all system

specified in subsection 2.4.4.

matches

the

are

settings

NOTE

If the power controller

turned

1is

off

(select

switch - OFF) all power transfer is inhibited.
.

Set the power controller select switch to REMOTE.

2 .

Plug the AC power cord into the AC power outlet.

Turn the power controller circuit breaker to ON

Open the front door and turn the main power supply

If an expansion backplane is installed, set

Figure

(1).

2-6.

breaker (right breaker) to ON (l).

power supply circuit breaker

See Figure 2-7.

(left breaker)

the

to ON.

Box Power Hookup

Complete the following procedure.

CAUTION

Assure that the wall outlet voltage

line voltage selected for operation.

Assure that all system

switch

specified in subsection 2.4.5.

matches

the

are

settings

circuit

expansion

This completes the cabinet AC electrical hook up.
2.4.7

See

SITE PREPARATION AND INSTALLATION

Plug

the

female

end

the

power

receptacle mounted on the rear of the box.

Plug

the male

end

the AC

power

cord

1into

the

See Figure

into

the

2-9.

power

outlet.

Remove

the

restraint

Slide

the

Slide

the box back

box out

circuit breaker

bracket

at the

approximately

rear of

the

box.

See

inches

Figure

and

turn

into the

rack

and

replace

the

restraint

electrical

hook

up.

to ON

(l).

2-10.

the

bracket

This

2.5

completes

SYSTEM

The

CONTROLS

following

indicators.
conditions.
Chapter

2.5.1

The

the

Front

box

AND

INDICATORS

subsections

describe

the

system

controls

and

The
functions
described
are for normal operating
If a problem occurs during normal operation refer to
System Maintenance.

Panel

front panel consists

of a keylock power switch,

HALT
Switch,
a
Start-up
Test
indicators.
Figure 2-11
shows
indicators.

LED
the

display, and
front
panel

RESTART/RUN/
POWER and
controls

)

ofe

dilgfilt]a]t

enane

SECURE

PDP-11/84

\_ sTanT.up TEST "

sTANDBY
CDocon

AESTART

D AUN

= RUN

CO sareny

HaLT
L

FIGURE

2-11

FRONT

PANEL

CONTROLS

2-14

AND

INDICATORS

RUN
and

INSTALLATION

SITE PRERARATION AND

of four power states.

ONE

select

each of the power switch selections.

used

switch

rotary

position

four

The Keylock Switch is a

Table 2-1 lists and describes

TABLE 2-1 KEYLOCK POSITION DESCRIPTIONS

Power supplies are turned off. DC power to the logic
and blower/fan assembly is off. However, AC power into

OFF

is present.

the power supplies

ENABLE

The ON position. Power supply voltages are present to

SECURE

Same as the ENABLE position except that the console
terminal Halt-On-Break feature and the HALT/RUN/RESTART

the logic and blower/fan assembly.

switch are disabled.

STANDBY

Power is supplied to the PMI memory, blower/fans
but other voltages are turned off.

—-——-—————-——-————

_‘—)-m—-——“-‘——fl-——_-----——-————--————-———-_--—

The HALT/RUN/RESTART switch functions are enabled only when the
keylock switch 1is in the ENABLED position. Table 2-2 lists the
switch positions and their functions.

TABLE 2-2 HALT/RUN/RESTART SWITCH

FUNCTION

POSITION

The CPU program is stopped and the incremented content
of the program counter is displayed on the console

HALT

terminal. The CPU enters J1l Micro-ODT.

RUN

Entering RUN from RESTART enables CPU operations to run.
Entering from HALT causes the processor to remain in
micro-ODT awaiting a command from the console terminal.

RESTART

This momentary switch position initiates processor
execution of bootstrap program instructions located
in the boot ROM according to the set up configuration
in the EEPROM., For modifying EEPROM configurations see
the EEPROM section

aED

was

CED

CED GER CER

GER

AID

YED

in this chapter.
R

CER

TED

CHD

ATR

CED

TEO

GNC

GED

SRR

GUD

CEP

SITE PRERARATION AND INSTALLATION

Three LEDs are located on the front panel.
the LED status and

functions.

_ TABLE

— .

FRONT PANEL

2-3

W G

U NS S W G CE GEE WD SN W M

Table

describes

2-3

INDICATORS

. 5 D CED CED WD D D A

O CHD D

S OO0 TN O D ) G

e wm e

m-——————

-————————-——————-——————--o--&—-am—'—'—na—‘n—-

RUN

OFF

The J1l1 processor is fetching and executing
instructions. This is the normal condition.
The processor is halted or waiting for an
interrupt. When the processor is in Micro-ODT
the RUN indicator blinks for each console

keystroke. The RUN LED also turns off during
extended DMA activity.

OFF

BATTERY

DC power is available to the logic and all
voltages are within specified levels.

DC voltages are not available to the logic or

voltages are present but not within tolerances.

Battery is present and charged to 80% or great-

Slow Blink
(1 Hz)

Fast Blink
(10 Hz)
OFF

capacity.

Battery is at less than 80% capacity and is
charging.

The ac power has failed; the battery is discharging, but the memory content remains valid.
Battery is either fully discharged or not pre-

sent in the system. Memory content will not be

preserved
—— A

if ac power fails.

= SN P R S D SED THI GHE GED IS G TS D G GED WD W

The two-digit Start-up Test LED

error

diagnostic
System Maintenance.

codes.

W G M

P D D D MR GO WD SER ED TED WD IO AT KNP D D D W SN G TR S e sEm o

display

provides

the

start-up

The codes are described in Chapter 5,

SITE PRERARATION AND INSTALLATION

2.5.2 Console

Serial Line Distribution Board

to
mounted
1is
The console serial line distribution board (SLU)
a
includes
SLU
The
products.
both
of
panel
back
inside
the

select switch
serial communications port connector, a baud rate
position for
mounting
SLU
and a Forced Dialogue mode switch. The
2-9.
and
2-12
Figures
in
shown
are
the cabinet and- box

8AUD

/-Wfl‘

S \\

BULK HEAQ~ e

SCAEW (104

{ ||

{
)

FORCED
DIALOG
PITCH

sLu

CONMECTOR

t Lt

FIGURE 2-12 CABINET BACKPANEL VIEW

2.5.3

Serial Communications Port

Figures
A serial line connector is located on the back panel.
It
or.
2-12 and 2-9 show the physical location of the connect
duplex
full
compliant
RS449
RS232-C,
EIA
provides an
communications 1link between the CPU and console terminal. Note
that 20 ma applications are not supported.
2.5.4 Baud Rate Select Switch

ng
The baud rate switch enables the operator to set the operati
rate
baud
The
system.
and
l
termina
console
the
between
rate
baud
is set for one of eight possible baud rates. Table 2-4 lists the
switch positions and their corresponding baud rates.
2-17

SITE

INSTALLATION

PRERARATION AND
TABLE

2-4

BAUD

RATE

SWITCH

DESCRIPTIONS

SWITCH

POSITION

BAUD

RATE

38400

19200

9600

4800

2400

1200

600

300

2.6 SYSTEM HARDWARE CONFIGURATION

system
the
n
Distributio
and
Monitor
the
to
dedicated
Slot MDM is
backplane.
Kkernel.
system
the
comprise
4
through
1
Slots
module (M7677).
through 12 support most UNIBUS compatible small
5
Slots
peripheral controllers (SPC). The following subsection describe
Figure 2-13 shows the location of the modules within

configuration details for the kernel.
ROWS

(MOM) M7677

MOM

)

(XDJ11-8) MB190D
(MSV11 . JI MBB37

M7556

3
(KTJ11-8) MB191

HEX OR QUAD UNIBUS OPTION

SLOTS 6

HEX OR QUAD UNIBUS OPTION

FIGURE

M&%“'JZD

HEX OR QUAD UNIBUS OPTION

”&?’B‘fs"

HEX OR QUAD UNIBUS OPTION

11|

MODIFIED

HEX OR QUAD UNIBUS OPTION

12|

UNBYS

2-13

QUAD UNIBUS OPTION

H9277-A

BACKPLANE
2-18

‘

M7556

MODULE

PRIOR

e
LOCATIONS

SITE PRERARATION AND INSTALLATION

2.6.1 KDJ11-BF Module Configuration

The KDJ11-BF module has three jumper groupings and one DIP switch
pack for hardware configuration. The jumpers should be installed
as shown in the Figure 2-14. The DIP switches should be- set to
OFF.
DCOK LED
1P SWITCH FOR
BAUD AATE SELECT AND (GREEN)
BOOT STRAP CONTROL
OIAGNOSTIC
/8 OFF

CONNECTOR
FOR CABLE TO
BAUD RATE SELECT
AND TWO-DIGIT DISPLAY

N //78 [/

CONNECTOR

wio

(A~SERIES}
H-A SOCKET
:w—‘_FPJ40—PIN
(P-SERIES)

TP110{Jo TP10

£53

{H1 BYTE} o] @

DCJ11 CPU HYBRID

15:08

€80

(LO BYTE) /'EEPROM

(SEE NOTE V)

wao

ARRAY

€35

TPa0O[)0" o TP42

@ CONTROL CONNECTOR

[53] {SID:II/

ROM

REMOTE SWITCH

——a

FOR CABLE TO ~—_|

CONSOLE SLU

LEDS (RED)

GATE

TP41

ARRAY

(SEE NOTE 2)

w20

10 TP210TP22
TP200{

]

NOTES: 1. WHEN 24-PIN EEPROM IS USED, INSERT PIN ONE OF EPAOM IN PIN 3 OF SOCKET.
2. WHEN 2X EEPROM 1S USED, TP40 IS CONNECTED TO TP41.
WHEN 8K EEPROM IS USED. TP41 (S CONNECTED TO TP42.

FIGURE 2-14 KDJ11-B JUMPER AND DIP SWITCH LOCATION
2.6.2

KTJ11-B Module

Configuration

The UBA module does not have any hardware jumpers or switches

for

sockets for the addition of M9312
four
has
It
socket
ROM
the
for
2-15
Figure
See
ROMs.

configuration.
compatible user
locations.

the
The M9312 compatible user ROMs are installed with pin one of
chip toward the left edge of the component side of the module.
W31 TYPE OFTION ROM SOCKF
TS (4)

2] eres
[~

ROM

SOCKET

17773000~ 17713178

f1e

11773400~ 17773878

72
¢«

tue

ADOWESS

17773700-17713376

17779000 V7773178

Ered

€143
#1142

FIGURE

2-15

n__

J___

KTJ11-B ROM SOCKET LOCATIONS
2-19

SITE

PRERARATION

2.6.3

AND

Monitor and

INSTALLATION

Distribution Module

Configuration

The guad-height Monitor and

Distribution

Processour Grant

This

Module

(MDM)

has

eight
switch
DIP pack.
The
eight
switches
correspond
to
backplane slots 5 through 12 and ‘are wired
to
the
UNIBUS
Non
(NPG)

line.

eliminates

the wire wrapping of

backplane pins for non DMA SPCs.
For non DMA SPCs the switch
turned
ON
(toward
module handles).
For UNIBUS DMA devices
turned

switch

OFF.

An audible alarm is mounted on
failure
2-17

for

the

module

and

sounds

box fan or the cabinet blower occurs.

switch

location

and

numbering.

(3o

D5 D4

::]”
{20 PINI

D3I

:N;|J‘

Qo000 Oksumne

O.__ AUDIBLE
ALARM

sLov
NUMBER
12

)

NPG

00000000

—1 swiTCH

)

PACK

D1
02 -

5 (MAINPOVER SUPPL
Y
+SVE8 AND « 12V OLOWE R+ ANS)

O4
19

. SOWE N Q1P v)
5V IF XPANSI
<15V (€ XPANSI)'. POWE R SUPPL Y

03 - <15V MAIN PUE R SUPPLY

FIGURE

2-16

MDM

DIP SWITCH

LOCATION

2.6.4 MSV11-JB/JC Memory Module Configuration

The guad-height fiéfibry module provides:

A red LED to indicate uncorrectable-errors

A green LED to indicate

Two switch packs for starting and CSR address selection

Four

See

Figure

factory-set
2-17

for

the presence of +5 VBB

jumpers.

LED,

switch pack,
2-20

and

jumper

See Figure

VOLTAGE TEST
POINTS

. |g gsv (‘.80 -58’3/

when

1is
the

layout.

SITE

PRERARATION AND

_J
1

INSTALLATION

T
—

@m%
O

w4 W3 03

LIl T
FIGURE

The
l -

2-17

MSV11-JB/JC

LAY,
)

LED/SWITCH

PACK/JUMPER

LAYOUT

starting address is configured using switch pack S1, switches
8 Table 2-5 lists the switch settings, starting addresses and

decimal

number.

TABLE

SWITCH
1

2-5

SETTING*
456

MSV11-JX

STARTING

ADDRESS

STARTING

DECIMAL

ADDRESS

Kwords

Kbytes

(Octal)

00000000

000O0O00O0

04000000

100000O00O
11000000

00000O0O00O

Switch
Switch

The

CSR address

The

base

plus

512

1024

10000000

1024

2048

14000000

1536

3072

on
off

is configured using switch pack S2, switches 1
address is 17772100.
Each successive address is the

Table

2-6

lists

all
2-21

sixteen

possible

CSR

addresses.

SITE

PRERARATION

TABLE

AND

2-6

INSTALLATION

MSV11-JB/JC.

CSR ADDRESS

SELECTIONS

CSR
[\

ADDRESS
P

—

CED

(OCTAL)
D

)

S D

17772100
17772102

17772104
17772106
17772110
17772112
17772114
17772116
17772120
17772122
17772124
17772126
17772130
17772132

17772134

17772136

configurations

jumper
(MSV11-JC)
factory-set

The

jumpers

TABLE

)

CED

SER

are

2-7

GED

GND

1MB
(MSV11-JB)
the
Assure
different.
specified in Table 2-7.

for

modules

memory

are

MSV11-JB/JC

CRD

GER

JUMPER

and

2MB

that

the

CONFIGURATIONS

GO0

TI0

AND

OE)

CER

CED

—

MSV11-JB
Wl

OouT

256K

Half-populated

Vertical

W3,wW4

Dynamic

Reserved

RAMs

for

module

future

use

MSV11-3JC
ouT

256K

ouT

Fully

Vertical
D

CET

WED

CER

GES

TEN

Dynamic

populated

Reserved
e

CED

Rams

for
I

module

future
O

GED

OO0

SED

AR eme

use
e

TGS

SITE

2.6.5
The

Minimum
MLM

loads
MLM

are

under

used

provide

the following

inserted

ensure

AND INSTALLATION

Module

modules

regulator
Qe

Load

PRERARATION

CPU

minimum

power

supply

conditions:

backplane

current

slot

drain

(rows

and

from

the

VBB

and

the

-15

Vdc

regulator.
An

MLM

inserted

to
ensure
regulator..
If

CPU

mimimum

expansion

installed,
an
backplane (rows
of 1 A from the

backplane

current drain

backplane

slot

(DD11-CK

MLM
1is
inserted
E and F) to ensure
-15 Vdc regulator.

(rows

from

DD11-DK)

in
the last slot
a mimimum current

of the
drain

NOTE

MLM

not

required

(CPU
or expansion) if
the minimum 1 A of -15

When

not

required,

the

Load

the

the
V.

last

backplane

installed

Modules

options

must

two

LEDs

slot

draw

removed

from

the

indicate

the

backplane.
As

shown

Figure

2-18,

presence

and

VBB

the

-15

MLM

has

1
FIGURE

2-18

Vdc.

RED

GREEN

]
MINIMUM

LOAD

2-23

[

LAY,
)

MODULE

LAYOUT

SITE PRERARATION AND INSTALLATION

2.7 EXPANSION BACKPLANE INSTALLATION

?wo types of expansion backplanes are available for
in the cabinet.

installation

They are:

DD11-CK 4-slot backplane

DDl11-DK 9-slot backplane

Both backplanes are shown in Figure 2-19,

1:l
)

| QuUAD wEiHY

/A/

ouoon

WODULES

m::mm

DD11-0K BACKPLANE

— e,

)

N/ VYV /

' / //

W/ A/
) [ /\/

7Zra

[ 1|

FIGURE 2-19 EXPANSION BACKPLANE SLOT ASSIGNMENTS

the UNIBUS
ectors contain allbeginnin
The standard UNIBUS A conn
g of the
the
and B of slot 1 are
connections. - Rows DD11-DK
BCll-A
the
by
pied
and should be occu
UNIBUS DD11-CK and
UNIBUS

in cable.

the
-DK, or of slot 4 eof slot
Rows A and B of slot 9of ofthetheUNIBDD11
s
Thes
e.
plan
back
the
on
US
DD11-CK are the end
or
inat
term
should be occupied by the BC1ll-A UNIBUS out cable or a
module (M9302 or M9312).

SITE

2.7.1
To

Expansion

install

following

the

expansion

the AC power

circuit

Remove

the

release
Lower

the

breaker
back

the

backplane

from

the

OFF

(0).

cover

door

panel

the

left

front-

lifting

cabinet

panel

the

side

and

two

Remove
metal

the

not

two

LEXAN
insert(s)

assembly,

power

using

Remove

INSTALLATION

pérform

controller

(5/32)

hex

after
side

from
by

(plastic)

unscrewing

cover

the

head

the

=-viewed

bottom.

setting

wrench

from

See

unscrewing

phillips

screws.
the

figure

the

cabinet

2-20.

four

shoulder

screws.

cover

behind.

over the backplane and the
Discard the metal insert, it 1is

reinstalled.

Position the expansion
align
the
two
tapped
four tapped screw holes

backplane
through
screw holes for the
for the DD1l1-DK.

the
front
DD11-CK, or

NOTE

The

backplane

harness

a
lug
attached
mounting screw.
If

the

fasteners.

bulkhead

screws

AND

Installation

steps.

Remove
the

Backplane

PRERARATION

there

modules,

jumpers
slots.

are

includes

must

sufficient

install

from

that

the

number

modules

backplane

pins
.

ground

installed

after

lead

with

under

the

NPG

jumper

removing

CAl-CBl1

for

NPG

all

and
the

T
e

-——y

63;7 :
47,
»//é%

SITE PRERARATION AND INSTALLATION

FIGURE 2-20 EXPANSION BACKPLANE MOUNTING

are supplied with the
Install the two/four 8-32 screws that
s.

backplane.

Do not tighten the screw

Install the backplane wiring harness . connectors

cabinet power distribution connectors
10.

Install two hex modules in each end slot of

the

into

the

backplane

to align the slots.

11.

Tighten the 8-32 screws installed in step 8.

12,

Remove the hex modules from the backplane.

13.

Replace the LEXAN (plastic) cover on the backplane.

14.

Replace the side panel using the four
two phillips head screws.

2-26

shoulder

bolts

and

SITE

15.

Replace
above

the

16.

the

side

shoulder

bolts.

the

mounting

17.

outer

the

rear

panel

bolts.

panel

PRERARATION AND

aligning

Lower

bulkhead

screws.

the

and

the

INSTALLATION

two

cover

brackets

tighten

the

onto

captive

Close the front door and lock using the hex key.

This completes the installation of a DD11-CK or DD11-DK

optional

backplane.

2.7.2
The

Expansion

NPG

line

Backplane
the

NPG/BG

UNIBUS

Jumper

grant

line

Lead

for

Routing

devices

performing

data

transfers
without
PDP-11/84 processor intervention.
Continuity
of the NPG line is
provided
by
wirewraps
or
jumpers
on
the
expansion backplane.
When

NPR

device

placed

wire
from pin CAl to pin
routing of the NPG signal
Figure

the

2-21.

DD11-DK

Grant

(slot

priority

has

slot,

the

corresponding

CBl of that slot must be
through
the
backplane
decreases

from

priority

and

highest

slot

jumper

removed.
The
1is
shown
1in
1

slot

has

lowest).

NOTE

The

bus

routed

NPR

device

removed

jumper

wire

grant

lines

(BG4

through

each

slot

decreases

from

from CAl

row

CBl

from

must

BG7)

for

Grant

slot,

the

reconnected.

non

NPR

priority

devices

for

each

NOTE

A bus grant jumper card G727 in row D,
or
G7273
in
row
C
and
D
must
be
installed
in
all
unoccupied SPC slots.
If an
SPC
slot
is
left

open,
bus
grant continuity will
system will not operate.

lost

and

the

are

level

ré

.’ N/

M h

RO WO,

\} NIVNN

g4 1

SITE PRERARATION AND INSTALLATION

NOTE

Routing wire
NPG
only.
backplanes
DIP

switch

on the

expansion
for
are
wraps
has NPG routing
CPU backplane®

MDM.

FIGURE 2-21 NPG JUMPER LEADS ROUTING
2.7.3

Backplane

Power Connections

a wire
thruogh
backplane
expansion
the
Power is supplied to
power distribution board with the power
the
connecting
harness
of
set
to a
The power wires run from the backplane
supply.
Mate~N-Lok connectors wired directly into the distribution board.
The power harness from the DD11-DK contains two 15-pin Mate-N-Lok

The DDl1-CK
6-pin Mate-N-Lok connector.
and one
connectors,
The
connector.
6-pin
one
and
connector
15-pin
one
backplane has
signal
the
and
2-22
Figure
in
shown
are
locations
pin
connector
and
(DD11-CK)
2-8
assignments for each pin are listed in Table
Table

2-9

(DD1l1-CK).

s 00t

imi

lak

k\w’oo"

'oc>at;

Yo o of

-\"O o of
o of
o

NJQ(D&:/

0 O
[0
|)

8§ o CTOR

)

W M CONmECTOR

FIGURE 2-22 BACKPLANE CONNECTOR DESIGNATIONS

SITE PRERARATION AND

TABLE

2-8

DD11-CK POWER CONNECTOR SIGNAL ASSIGNMENTS

B WD OWJOULD
WN K

15-Pin

Mate-N-Lok

+5 V
+15 V

Spare
+5

Connector
14
18

connected)

Spare (not connected)

(not connected)
(not connected)
‘

6-Pin

Red

18
l4
14

Green
Black
Black

14
18
18

=
Red
Blue
Brown
White

Mate-N-Lok

GND
LTC (line clock)
DC LO
AC LO
Spare (not connected)
Spare (not connected)

Red
Gray

Orange

Spare (not
+15 B
Ground
Ground
Spare
Spare
+5 B
-15 V
Spare
-15 B

INSTALLATION

18
18
18
18
-

Connector

Black
Brown
Violet
Yellow
=
=

SITE

PRERARATION AND

2-9 DD11-DK POWER CONNECTOR SIGNAL ASSIGNMENTS

TABLE

e M

S S

D D

INSTALLATION

M WU WED M GED

S G

D EN

D SR

D D W

S WD WS NS CH WM WP W

15-Pin Mate-N-Lok
+15

+15

GED WD S WP CHD GED G MED WD M MED R WD CH) GNP DR G

Connector

1
Red

14
18

Gray
Orange

Spare

Red

Ground

Black

Ground

Black

Ground

Black

Red

Brown

+5 V
Spare
Spare
Spare

Spare
+5

(not
(not
(not

(not

connected)
connected)
connected)

connected)

Spare

(not

connected)

-5V

Spare

(not

connected)

15-Pin
+5

Mate-N-Lok

Connector

Spare

Spare
+15

VvV

(not

Orange

(not

connected)

Spare

Red

connected)

Spare
+5 V

Red

White

(not connected)

Ground

Black

Ground

14
14

Black

Blue

Green

Ground

Spare
Spare
-15 V
Spare
-15 B

(not
(not

connected)
connected)

(not

connected)

6-Pin

Mate-N-Lok

Black

Connector
Black

GND

LTC

(line

Spare
Spare
D

D CED WER

TRR

D NS I emm e e

D GID G

GES

R G

clock)

Brown

Violet
Yellow

(not
(not
GED

connected)
connected)

AP SD G

GAR

AEC

D GED A

D G

D WD WD e

D SND

R CH

) e

D G

SITE PRERARATION AND
2.7.4

SPC Backplane

INSTALLATION

Locations

The
small
peripheral
control
sections
(C,
D,
E
and
F)
well as power
1lines as
UNIBUS
the
all
contain
collectively
voltages (+5 V, +15 V and -15 V).
These sections can be used
by

hex-

quad-height

peripheral devites.
the

SPC

backplane

modules

containing

Appendix D shows the

the control logic for

designations

for

connectors.

Appendix D also shows the pin designations of
the
standard
and
modified UNIBUS connectors.
The modified UNIBUS differs from the
standard UNIBUS in that certain pins have been redesignated.
2.8

SPC

MODULE

INSTALLATION

CPU backplane slots 5 through
12
support
the
installation
of
UNIBUS
SPC
modules..
Backplane slots 5 through 11 support both
hex- and quad-height SPC modules; slot
12
supports
quad-height
SPC modules onlv.

connector,

Row A of slot

Hex-height SPC modules

occupy all

supports

four

the UNIBUS out

rows

the

cable

Dbackplane

while
gquad-height
occupy
rows
A
through
C.
Quad-height SPC
modules, when installed, occupy the same backplane
rows
as
the
system CPU

and

To install

memory modules.

SPC module,

the

two handles

steps.

Grasp

Install the module in the backplane slot by sliding it into

When

card

following

the

the module

perform the

mounted

the

top.

cage guides.

the module

about three

quarters

installed,

grasp

the
handles
(toward
the
module
center)
and swing them
upwards, away from the module (see Figure 2-23).

FIGURE 2-23 SPC MODULE INSTALLATION
2-31

SITE

PRERARATION AND

INSTALLATION

and press
This action seats the module into

Continue to slide the module into the hackplane

the

handles

downward.

the backplane and secures

it in the card cage.

This completes the installation procedure for an SPC module.
2.8.1

Cabinet SPC Cable Routing

Use the following directions for proper cable routing.
1.

slot,
cable
the
and
connector
the
into
plugged
the SPC cables are

After installing an SPC in the appropriate backplane
is routed to the bulkhead assembly.

connectors mounted on the
edge of the module, are routed toward the right side

All SPC cables that plug into

front

of the card cage as shown in Figure 2-24.

When the connector is mounted on the top of the module, the
1is routed up and over the cable hanger assembly
cable
located above the card cage.

If the connector is mounted near the module handle the
installed cable 1is routed around the front of the card
cage.

FIGURE 2-24 CABINET SPC CABLE ROUTING
2-32

SITE

Located

2.8.2
Use

the

cable

clamps

bar

hang

Box

SPC

the

mounted
the

SPC

Cable

following

After

right

used

side

PRERARATION

AND

INSTALLATION

the
<card
cage
are
plastic
the SPC cable to the card cage.
horizontally behind the card cage and used

secure

cables

that

are

for

proper

routed

the

bulkhead.

Routing

directions

installing

the

SPC

routed

The

back

panel

and

top

cables

the

right

are

SPC

bulkhead

has

the

plugged

two

the

assembly.

from

routing.

appropriate

into

bulkhead

referenced

cable

backplane
connector and the

assembly

the

areas,

module

Cables

are

that

(installed
bulkhead.

routed

plug

in
See

into

toward

connectors

backplane)
Figure

FIGURE

2-25

the

are

2-25.

BOX

SPC

bottom

left

rear.

Cables that plug into ‘connectors mounted on the
the

slot

cable

lower

left

handle

bulkhead.

mounted

the

module

routed

the

upper right

CABLE

ROUTING

top

SITE PRERARATION AND INSTALLATION

2.9 CABINET BATTERY BACK UP UNIT INSTALLATION

To install the BBU complete the following procedure.
CAUTION

1lbs;

The weight of the BBU

lifting

positioning the BBU requires two people.

and

Unpack the BBU and installation kit.

Remove the BBU from the shipping container and place it

Set the front panel TOY (Time of Year) switch to OFF.

See

flat

Figure

surface.

2-26.

I I
TOY

FIGURE

I
VOLTAGE

ON/QFF

SELECT

Con

BBU

2-26

PANEL

FRONT

Set the BBU VOLTAGE SELECT switch to match

the

site

1line

voltage.

Set the rear BBU AC VOLTAGE SELECT to match the front panel
VOLTAGE SELECT switch setting.
BBU AC INPUT
CONNECTOR (422)

See

Figure

FAULT INTERFACE CONNECTOR (J20)
{FAILSAFE JUMPER}

@ @\

88U INPUT
AC VOLTAGE SELECT

GROUND STUD FOR
DC POWER OUTPUT

USER INTERIACE
COMNECTOR (J18)

SWITCH =——240

11§5—

DC POWER QUTPUT
CONNECTOR (J9)

POWER CONTROLLER
BUS CONNECTOR (J19}

FIGURE

2-27

BBU

2-34

REAR

PANEL

2-27.

SITE

Open

the

front

Turn

off

the

and

rear

power

PRERARATION

cabinet

supply

doors

and

power

AND

using

the

INSTALLATION

hex

controller

key.
circuit

breakers.
Unplug

the

power

cord

from

Remove the cabinet right
up from both sides.
See

the

outlet.

side panel by
Figure 2-28,

lifting

straight

14 SHOULDER SCREW (4)
e EMI SHIELD

=
=

SCREW (2)

SIDE PANEL

e 13

FIGURE

2-28

SIDE

10.

Remove the two
phillips
securing the EMI panel to

11,

Carefully
screws

lift

and

protruding

line
from

up
the

PANEL

REMOVAL

head
and
four
shoulder
the cabinet frame.

the

BBU

cabinet

2-35

enclosure
frame.

with the
Figure

See

screws

four
2-29.

SITE PRERARATION AND INSTALLATION

CARD CAGE
/‘ussemsw

U-NUT
REVAINER

" W/10-32 SCREW (4)

\Nzx

E®-

|
LINE

FILTER

10-32

KEPNUT
(4)

BATTERY BACKUP

877-0/F

POWER

CONTROLLER

(H7231-€)
UNIT NIT (H7231-

FIGURE 2-29 MOUNTING THE EBU
12.

13.

Position the BBU on the four mounting screws and
against the cabinet frame.

Install and
installation
to the

frame.

slide

the
(from
tighten four 10-32 hex nuts
BBU
the
ing
kit) on the mounting screws, secur

14.

Remove all cables from the installation kit.

15.

Install the two-position keyed jumper into mating connector

16.

Plug one end of the

17.

(J20) on the BBU rear panel.

keyed

cable

(7020396),

wire, into the BBU mating connector (J9).

with

ground

Place the
Remove the hex nut on the BBU ground stud. replac
e and
ground wire from the cable on the stud, and
tighten the hex nut.

18.

Plug the other end of the keyed cable, with ground
into the line filter bracket connector marked BB-J1l.
the cable ground wire on the stud.

19.

wire,
Place

Install a 10-32 hex nut (from the installation kit) on

stud.

Tighten the nut to secure the ground wire.
2-36

the

SITE

PRERARATION

AND

INSTALLATION

20.

Plug one end of the other keyed cable
(7008288)
into
the
mating
BBU power controller bus connector (J19).
Plug the
other end of the cable into the
877-D/F
Power. Controller
connector marked either J8 or J9.

21,

Plug
the.
(1700730)

the

top

ten
position
connector
of
the
signal
<cable
into
the
mating polarized connector located at

right

the

card

cage

assembly.

Attach the cable ground wire to the stud with the 10-32
nut provided.
Secure the wire by tightening the nut.
23,

Plug

the

other

connector
screws
24
.

end

(J18)

the

(D-sub)

the

BBU.

cable

Tighten

into

the

hex

mating

self-retaining

connector.

Plug the appropriate power cord

(120V or 240V) into the BBU

and
plug
the
other. end
of
the cord into the remaining
UNSWITCHED outlet on the 877-D/F power controller.

25,

Check each installed cable to
ensure
that
none
damaged during reinstallation of the EMI shield.

26
.

Reverse steps
side panel.

This

completes

2.10

BOX

the

BATTERY

through

installation

BACK

UNIT

reinstall

the

EMI

will

shield

and

procedure.

INSTALLATION

To install the BBU complete the following procedure.
CAUTION

The

weight of the BBU
1is
42
positioning the unit requires

Unpack

the

BBU

and

Remove

the

BBU

from

surface.

flat

Set

the

front

installation

See

panel

1bs;
1lifting
two people.

the

TOY

kit.

shipping

Figure

2=37

container

2-30.

switch

and

to OFF.

and

place

SITE PRERARATION AND INSTALLATION

I
TOY

FIGURE

VOLTAGE

ON/OFF

SELECT

—m

BBU

2-30

FRONT PANEL

site

line

Set the rear BBU AC VOLTAGE SELECT switch to match
See Figure 2-31.
front panel VOLTAGE SELECT switch.

the

Set the VOLTAGE

switch

SELECT

match

the

voltage.

88U AC INPUT

CONNECTOR (J22)

FAULT INTERFACE CONNECTOR (J20)

(FAILSAFE JUMPER)

{ooo}

/e
GROUND STUD FOR
DC POWER OUTPUT

BBU INPUT
AC VOLTAGE SELECT

USER INTERFACE
CONNECTOR (J18)

SWITCH =240

DC POWER QUTPUT

15—

CONNECTOR (J9}

POWER CONTROLLER
BUS CONNECTOR (J19)

FIGURE 2-31 BBU REAR PANEL
6.

Follow the directions supplied with the rack and

Turn the box circuit breaker off.

secure

the BBU

FIGURE

the

2-32

carefully

rack.

See Figure 2-32.

CIRCUIT BREAKER LCCATION
2-38

SITE PRERARATION AND INSTALLATION

Unplug the AC power cord from the AC outlet.

the
that secure
Loosen the four captive screws
See Figure 2-33.
cover, and remove the cover.

box

top

FIGURE 2-33 TOP COVER REMOVAL
10.

Remove the blank rear bulkhead panel Bl by loosening the
two phillips head screws that secure it to the bulkhead.
See

Figure

2-34.

BULKMEAD

suikneao—=1"/

FIGURE

2-34

BULKHEAD LOCATION
2-39

SITE PRERARATION AND INSTALLATION
11.

Remove the BBU panel from the installation kit.

12.

Route the two attached cables through the bulkhead

13.

Install the BBU connector panel (shown in Figure

that was occupied by panel Bl.

the

opening
2-35)

1in

slot

MDM

opening and tighten the two flat-head screws

bulkhead

into the bulkhead

frame.

]
FIGURE 2-35 BBU CONNECTOR PANEL
14,

Label and remove

through slot

the

cables

from

the

module

15.

Remove the five modules from the backplane.

16.

Plug the signal cable connector (10 position) 1into the
backplane PC board mating connector (J12). See Figure
2‘36 °

8ACKPLANE

FIGURE

2-36

BBU

CABLES
2-40

AND

LOCATIONS

SITE

17.

18,

PRERARATION

AND

INSTALLATION

Plug the other BBU cable connector (3
position)
into
the
panel-mounted
mating
connector located behind the rear of
the power supply.
:

Reinstall the five modules insuring that

they

are

properly
.in the

backplane.

19,

Plug

into

20,

Remove

21,

Install the two position keyed jumper into mating
(J20) on the BBU rear panel.
See Figure 2-37,

the

cables

the

their

remaining

two

88U AC INPUT
CONNECTOR (J22)

module

cables

seated

connectors.

from

the

installation

kit.

connector

FAULT INTERFACE CONNECTOR (J20)
(FAILSAFE JUMPER)

@
.

{ooo}

[erel=]

BBU INPUT

GROUND STUO FOR usehmenucs

AC VOLTAGE SELECT

DC POWER QUTPUT

SWITCH =—240

ns—

CONNECTOR (J18)

DC POWER OUTPUT

CONNECTOR (J9)

POWER CONTROLLER
BUS CONNECTOR (J19)

FIGURE

BBU

2-37

REAR PANEL

NOTE

BBU connector J19

22,

23.

Plug one end of the

wire,

cable

(7020396),
(J9).

with

ground

the
Place
stud.
ground
BBU
the
Remove the hex nut on
and
replace
and
stud,
the
on
cable
the
from
wire
ground
hex

nut.

Plug the other end of

into

the

keyed

cable,

with

the BBU bulkhead panel connector Jl.

ground wire
25.

keyed

into the BBU mating connector

tighten
24,

is not used with this system.

the

ground

wire,

Place the cable

stud.

Install a 10-32 hex nut (from the installation kit)
Tighten the nut to secure the ground wire.
stud.

the

SITE PRERARATION AND INSTALLATION

26
.

Plug the signal cable (1700730) into the mating polarized
connector located on the BBU bulkhead panel. Attach the
cable ground wire to the stud with the 10-32 hex nut
provided,

27.

Plug the -other end (D-sub) of the cable into the mating
Tighten the self-retaining screws on
connector on the BBU.
the

28.

and *ighten the nut.

connector.

Peplace the top cover of the box, and tighten

the

captive

screws.

29.

Plug the appropriate power cord (120V or 240V) to the BBU
the cord into the AC power
and plug the other end of
outlet.

This

completes the

installation of the BBU.

CHAPTER
FUNCTIONAL

3.1

DESCRIPTION

INTRODUCTION

The PDP-11/84 functional block diagram is shown

Figure

3-1.

KDJ11l-BF CPU, MSV11-JB/JC ECC memory and
three modules are:
The
J11
a
has
module
KDJ11l-BF
The
adapter.
UNIBUS
KTJ11-B
Private
memory,
cache
8KB
an
FPA,
integral
microprocessor with
Memory

Interconnect

(PMI)

EEPROM/ROM,

registers,

arbitration

configuration

1logic,

memory

registers,

management

a SLU

(serial

line unit), six red diagnostic LEDs and a green +5V power LED.

PMI
a
1into
divided
The KTJ11-B UNIBUS Adapter (UBA) module is
The handshake logic enables data
a UNIBUS section.
and
section
PMI
The
devices.
UNIBUS
and
PMI
transfers to occur between
section
has
diagnostic
registers and PMI arbitration/interface
UNIBUS
cache,
DMA
32-word
a
has
section
The UNIBUS
logic.
M9312-type
for
sockets
interface logic.

logic,
mapping
arbitration and

wuser

ROMs

and UNIBUS

The MSV11-JB memory module has a 1MB capacity, while the MSV11l-JdC
has
a 2MB capacity.
A maximum of two memory modules are allowed
in the

system configuration.

The modules

the

PMI

KTJ11-B

DATBI)
DATO,

transfer

and

module.

can

DATOB)

UNIBUS
PMI

data using

devices

read

the

wuse

be word

byte

Data

transfers

(i.e.,

DATI,DATIP,

PMI write operations

mode.

NOTE

The
PDP-11/84
UNIBUS
Power
slightly
different
from most
Appendix

for protocol

between

the Handshaking Logic on the

operations,

be word or block mode.

can

PMI.

up
protocol
PDP-lls.
Refer

description.

is
to

(

and

i.e.,

FUNCTIONAL DESCRIPTION

All communications between

through

standard

configured

the

UNIBUS

system.

éLL

devices

ROM

HAND
DIAG | __| SHAKE

DATA

;

PMI

| cache
MEMORY

INTERFACE

INTERFACE
b

‘

PMIARE

occur

may

PMI ARB
AND

MISC

INTERFACE

REG.S

gsze

Lodic

REG

]

_J
FPI11
FPA

UBA

the

devices

KTJ11-8 MODULE

MEMORY

--=
- EPROM

and

OQBus

MSV11-J MODULE

KDJ11-8F MODULE

SSTSOLE

UNIBUS

protocol.

:
t
]

:
!
§

UNIBUS
’r

AND

INTERFACE

UNIBUS

[ - MAPPING..
ROM

PMI

pCTAL

CONSOLE

DISPLAY

TERMINAL

MA-15296

FIGURE 3-1 PDP-11/84 FUNCTIONAL BLOCK DIAGRAM

3.2 PMI BUS DESCRIPTION

path
The PMI bus provides a high-performance communicationKTJ11B
the
and
,
Memory
between the KDJ11-BF (CPU), MSV11-JB/JC
PMI
to
unique
are
that
s
(UBA). The PMI consists of 14 signal
protocol. The signal lines are described in Table 3-1.
The KDJ11-BF CPU module is also used in QBUS systems and
the
therefore some of the signals retain their QBUS names, but
in
is
(UBA)
B
KTJ11a
when
change
s
signal
these
functionality of
the system.

Data and address information is multiplexed and uses

the same data/address lines as QOBUS protocol.

FUNCTIONAL

B IR I

BDAL

<21-00>

P NP WD W

PMI

3-1

TABLE

SIGNAL LINE DESCRIPTIONS

SmS w0 e =
GNP AP M GEE SR G SMD GED GED WIS WD NS GES D AT W WD GEN GED WS CAD SN SRR AP TE WS SR GED GES GHP UL GHD GHR G GMD GED QA TR GLP TP GER GNP MDE GHD b eSS

22 multiplexed bidirectional Data/Address
During

DESCRIPTION

Lines.

the address phase of a data transfer cycle,

the PMI master gates address information onto these
During the data phase of the cycle the slave
lines.
(DATI) or the master (DATO) gates data onto BDAL<K15-00>
and parity error/control information onto BDALK17-16>.

BBS7

Bank

Select

(I/O Page

Select).

When the PMI master gates an address onto BDAL<21-00>,
it asserts BBS7 to reference the I/0 Page (including the
I1/0 Page addresses reserved as non-existent memory).
When BBS7 is asserted, BDAL<K12-00> specify the I/O page
address,

BRPLY

Negation of BBS7 selects the memory address space.

This signal

is asserted by the UBA as a slave

during the PMI DATO(B)

vector
BDIN

Data

DATI

response

cycle and during the interrupt

cycle.

Input

This signal is used by PMI protocol during UNIBUS interrupt
The CPU asserts BDIN after gating the
grant cycles.
The UBA latches the
interrupt priority onto BDAL<03-00>.
interrupt priority on the leading edge of BDIN,

BIACKI

Interrupt

Acknowledge

This signal is used by PMI protocol during UNIBUS interrupt
When the UBA receives the assertion of BIACK
grant cycles.

(from the CPU),

signals.

it asserts one of the UNIBUS grant

(BGn)

FUNCTIONAL

DESCRIPTION

TABLE

3-1

(Cont)
nfi——__-—_—————-—---_—_—

——-m--n-——————-————-—_-—-———-—‘-‘!-fl—fl_d

—u---:—-_—_——-_———_-—_

‘d—m—_--:————————--——-——-——-———-—m——‘au-u-

Power OK

This signal is asserted and negated by the UBA in response

to AC LO on the UNIBUS following standard UNIBUS power-up/

down protocol.

UNIBUS devices and/or PMI memory may,

during power-up, prolong the assertion of AC LO/BPOK.

The following signals are asserted (low) and negated (high) by the
PMI

master:

PMI

PBCYC

Bus

Cycle

The PMI master asserts this signal at the start of a
PMI cycle and negates this signal at the end of that
cycle.

PBYT

PMI

Byte

BWTBT

Write

and

Indication

Wwhen the PMI master gates an address onto BDAL<21-00>,
it asserts or negates these signals to indicate what
type of data transfer will occur during the next bus
cycle:

BWTBT

L
H
L

H
L
L

PMI

PBLKM

PBYT

Block

Bus Cycle Type
DATI or DATBI
DATIP
DATO
DATOB

Mode

When a PMI master wishes to read more than two words
of data, it uses both PBCYC and PBLKM to control the
It
timing of the Block Mode Data In (DATBI) cycle.
DATBI
the
of
start
the
at
asserts both PBCYC and PBLKM
cycle. It negates PBLKM after reading two data words
_
and then reasserts PBLKM (unless the next two words
words,
two
last
the
reading
After
cycle).
will end the

the PMI master negates PBCYC (PBLKM is already negated).

GHD <O WIS CED G WP D S CHD G WD a5
- e D TED G D aTD W IO D G WER MR W WD SIS G MO W D SND NP WIS WD CH G S s - D D D O e D R D O W D O OO

FUNCTIONAL

TABLE

PMI

Write

3-1

DESCRIPTION

(Cont)

Strobe

The PMI master asserts this signal after gating data

onto BDAL<15-00>. The PMI slave latches the data into
its write buffer on the leading edge of the PWISTB

pulse.
QSACK

The UBA asserts this signal on the PMI in response to
from

SACK

DMR

the

UNIBUS.

The UBA asserts this signal on the PMI in response to
NPR from the UNIBUS or when the UBA is performing a DMA
cycle

its own behalf.

DMG

The CPU asserts this signal when PMI mastership has been
granted to the UBA in response to a DMG.

QBR7-4

The UBA asserts one of these signals in response to one

of the BR7-4 lines being asserted on the UNIBUS during
interrupt

request cycles.

The following signals are asserted and negated by the PMI slave:
PSSEL

PMI

Slave

Selected

The PMI slave (CPU or Memory only) asserts this signal
whenever it decodes a valid address on BDALK21-00>.
NOTE :

PHBPAR

When PUBMEM is asserted the PMI slave does not
PUBMEM is
respond to PMI control signals.
UNIBUS
that
e
indicat
to
UBA
the
by
d
asserte
UBA does
The
ed.
address
being
is
space
memory
The CPU ignores the
not assert PSSEL.
assertion of PSSEL if PUBMEM is asserted.

PMI High Byte Data Parity

This signal is generated by PMI memory during DATI and
DATBI cycles and provides odd parity for the high byte
data

PLBPAR

(on BDALK15-08>).

PMI Low Byte Data Parity

This signal is generated by PMI memory during DATI and
DATBI cycles and provides even partiy for the low byte
data

(on BDAL<07-00>).

FUNCTIONAL DESCRIPTION
TABLE

PRDSTB

3-1

(Cont)

Read Strobe

PMI

The PMI slave asserts and negates this line to control
data transfers during DATI and DATBI cycles. The PMI
master latches the first word of the received data on
the negating edge of this signal.

The PMI master

latches the second data word a specified time after

this signal

PSBFUL

is negated.

PMI Slave Buffer Full

A PMI slave asserts PSBFUL during a write cycle,

indicating that it's Write Buffer is full, and that it
can not respond to another cycle regquest. The new PMI

master may gate an address onto BDAL<Z21-00> while
PSBFUL is asserted, but it must not assert PBCYC until
PSBFUL

negated.

The following signals are used for communication between the
CPU and the UNIBUS adapter. PMI Memory modules do not use these
signals.

PMAPE

PMI UNIBUS Map Enable

The CPU module asserts this signal if Memory Management

Register 3 (MMR3) bit 5 is set and negates this signal
if MMR<O05> is clear. The UBA module enables the UNIBUS
Map if PMAPE is asserted and disables the UNIBUS Map if
if

PUBSYS

PMAPE

PMI

is negated.

UNIBUS

System

This signal is a static signal which indicates whether
the system is a UNIBUS system or a QBUS system and is
asserted by the UBA. The CPU follows PMI protocol for
data transfers whether PSSEL is asserted or not.

PUBMEM

PMI

UNIBUS

Memory

This signal line is asserted by the UBA to indicate
The
that the UNIBUS memory space is being addressed.
UBA asserts PUBMEM during the assertion of PBCYC.
NOTE

When PUBMEM is asserted the PMI slave does not
PSSEL is
respond to PMI control signals.
. The CPU
addressed
when
memory
asserted by PMI

ignores the assertion of PSSEL if PUBMEM is

asserted.

The UBA does not assert PSSEL.

FUNCTIONAL DESCRIPTION
TABLE 3-1(Cont)

————-——-——-——--—-——4--——

———-——-——_-———————-————-———-——-———————-——————

PUBTMO

PMI UNIBUS Timeout

This signal is asserted by the UBA in response to any of
the following conditions:

PBSY

A non-existent memory timeout occurs whens.
the UBA sends an address out on the Unibu

When a SACK timeout occurs during an

device has been
When an interrupting UNIBUS but
does not

interrupt cycle.

granted UNIBUS mastership,
execute an interrupt transaction.

PMI Busy

or UBA)
ed by the PMI masterted(CPU
This signal is assert
the PMI
by
nega
is
and
tership
when it gains PMI masuis
CPU is
The
ip.
ersh
mast
PMI
hes
master when it reling
power-up.
the PMI master on

3.2.1 PMI BUS Acquisition

PMI Bus master and
the CPU is the default
In the PDP11/84 systrem(UBA
er. This is
US
UNIB
ult
) is the defan the UBA ismast
pte
the UNIBUS Ada
not requestings
ion at power up.es Whe
always the conditthe
CPU arbitrat to become PMI master and hold
the PMI bus,
PBUSY asserted.
of the devices ones the
in the past, wfien none
Unlike other PDPll's
the UBA arbitrat to
UNIBUS are requesting use of theassebus,
.
rted
become UNIBUS master and holds BBSY

responding to a DMA
PMI mastership when
The CPU relinquishes rrup
UBA. Once the CPU has
t cycle from the rega
inte
request or an rol
the PMI, it canmet: in PMI mastership
relinquished cont owinofg cond
itions are
only when the foll
1. OSACK has been negated for 75ns minimum.
2. PBSY has been negated for Ons minimum.
3=-7

FUNCTIONAL DESCRIPTION

ences a memory or I/0 page
When the CPU, as PMI master, referresp
as the slave on the PMI
address on the UNIBUS, the UBA of onds
the data transfer as bus
while controlling the UNIBUS side
)

master.

CPU issues a DMG (DMA Grant)
The UBA becomes PMI master when the
or
. The UBA may accept the DMG the
or performs an interrupt cycle
at
er
mast
S
both PMI and UNIBU
interrupt gra. t, thus becoming may
pass the DMG or interrupt grant
it
ely,
nativ
Alter
same time.
UNIBUS
on to a requesting UNIBUS device, which would then become
master.

ws:

Mastership of the UNIBUS and/or PMI bus is requested as follo

an NPR
me UNIBUS master through
1. A UNIBUS device can beco
During
sfers over the UNIBUS. onds
request and control data, tran
as
the UBA is PMI master and resp
these data transfers
device accesses a PMI memory
UNIBUS slave if the UNIBUS
location or a UBA 1I/0 page

location, a PMI
location.

I/O page

a BR7-4
me UNIBUS master through
2. A UNIBUS device can becomast
data
rol
cont
can
ce
devi
the
reguest. As UNIBUS traner,
UBA
the
s
case
both
In
s.
sfer
and/or interrupt vector US slav
e. The device may perform an
will respond as UNIB access a PMI memory location,
interrupt vector cycle or a UBA 1/0 page location.
PMI I/O page location or

at the same
PMI and UNIBUS master PMI
3. The UBA can becomeandboth
and UNIBUS
As
interrupt requests.
time through DMG
PMI.
ct access to the
master, the UBA has dire

3.2.2 DMA Requests

can
ugh an NPR request to esthewithUBA,
A UNIBUS DMA device, throDATI
UBA
the
cycl
B
DATO
and
P, DATO

perform UNIBUS DATI, ion of the data transfer.
controlling the PMI port
NOTE

Unlike previous PDPll

systems,

the

CPU

unconditional
does not necessarily give
programmed
priority to DMA regquests. It 4)can to be give
itself
SETUP mode Chapter
(see
ing,
wait
r
afte
ests
priority over over DMA requ time, to perform
a
of
th
for this programmed leng
est.
requ
t
rrup
inte
an
r
hono
memory transfer or to

When

placed

transfers
UBA itself
cycle

test

mode

becomes

complete

The

following

master

the

PMI

control

the

PMI.

PMI

protocol

arbitrating

flow

and

DESCRIPTION

UBA

perform

the

without
a regquesting UNIBUS
is the requesting device and

has

when

diagnostic

FUNCTIONAL

the

DMA

the
DMA

UNIBUS

simultaneously

and

the

CPU

and

UBA

(NPR)

from

observed

Non-Processor

can

device.
1In this case
when
performing
a

Request

UNIBUS

device:

PMI

BUS

UNIBUS

The

UNIBUS

device

asserts

NPR.

the

UBA

UNIBUS

master

it negates BBSY after removing
address, data and control
information from the bus.

The

UBA asserts

the

The

PMI

DMR

(DMA Reqguest)

bus.

CPU bus arbitration logic
asserts DMG (DMA Grant) on the PMI
after receiving DMR and 75ns minimum
after the negation of QOSACK from a
previous PMI bus transaction.
UBA

receives

the

assertion

DMG.

The UBA asserts NPG
Processor Grant).

The
the
SACK

The

Note:

UBA

asserts

QSACK

the

PMI.

The UBA asserts PUBTMO instead of
QSACK (indicating No SACK timeout)

if
10
the
DMA

SACK is not
us after it

received within
asserts BGn on

UNIBUS. The CPU then cancels the
cycle and resumes arbitration.

(Non-

requesting device with
highest priority asserts
and

negates

NPR.

FUNCTIONAL DESCRIPTION

UNIBUS

PMI BUS
9-

The CPU arbitration logic receives
QSACK and negates DMG.

Note:

Because the UBA provides the
No SACK Timeout function on the
PMI, the CPU always asserts DMG
untill it receives QSACK or UBTMO.
10. The UBA negates NPG on the
UNIBUS.

11. The UBA asserts PBSY, after receivind

the negation of PBSY from the previous
PMI cycle,

and becomes PMI master.

12. After receiving the negation

of BBSY from the previous bus
master the UNIBUS device asserts
BBSY and negates SACK.

S master through an NPR
When a UNIBUS DMA device becomes USUNIBU
B
DATI, DATIP, DATO and DATO
UNIB
request, it can perform sses
1/0
PMI
a
,
tion
PMI memory loca
cycles. If the device acceS I/O aPage
location located on the UBA,
UNIBU
a
or
Page 1location
e. For PMI memory and PMI I/0
the UBA responds as the UNIBasUS slav
the PMI master, controls the PMI
Page accesses, the UBA
portion of the data transfer.

Data transfer cycles are described in section 3.2.5.
13. The UBA negates QSACK.

14. The CPU resumes arbitration 75 ns
minimum after receiving the
negation of QSACK.

15. The UNIBUS device removes

address, data, and control
information from the bus and
negates BBUSY.

16. After the PMI slave or the UBA has
removed all data and control information
from the bus, the UBA negates PBSY.
_-anmgaum-pcpa D D D ED D R D D D R D T WD CED O D
——-—-—_-n—-'es——--‘a@-—-—n—-:—————————-——-—q-m——

FUNCTIONAL

3.2.3

UNIBUS

CPU

The

and

arbitrating

e e

Device

UBA

inter-

PMI

Interrupt

observe
rupt

DESCRIPTION

Requests

following

the

protocol

flow

when

requests:

BUS

UNIBUS

The CPU receives the appropriate
request level on QBR7-4.

The CPU arbitration

The UNIBUS device asserts
the appropriate interrupt
request line BR7-4.

logic asserts

one of the four lines, DALK03-00>,
to indicate the level of the granted
interrupt.

The CPU asserts BDIN 150 ns minimum
after gating DAL<K03-00> onto the bus.

The CPU asserts BIAK 225 ns minimum

6.
7.

after

it asserts BDIN.

The UBA latches DAL<K03-00> on the

asserting edge of BDIN.

The CPU receives the assertion of
IACK on

the

PMI.

Note: The UBA compares the interrupt level being granted
with its own interrupt level and can block the grant.
In this case the UBA performs an interrupt or data
transfer cycle and has complete control of the PMI
and the UNIBUS simultaneously. In this case the BGn
line would not be asserted on the UNIBUS.
8.

The UBA asserts
UNIBUS Grant

DAL<03>= BG7,

the selected

(BGn)

line.

DAL<02> = BGS,

etc.

9.,

If the UBA was the UNIBUS
master it removes address,

data and control
from

BBSY.

the

bus

and

information

negates

FUNCTIONAL

DESCRIPTION

PMI

BUS

UNIBUS

___________________________________ I_...-_..._._...__...
___..__..._.._———_..-——

10.

The

highest

ing

device

assertion

priority requestreceives the

BGn

and

asserts

SACK.

l11.

12.

The

Note:

15.

UBA

asserts

The

device

negates

BRn.

QSACK.

The UBA asserts PUBTMO (indicating
No SACK timeout) if SACK is not
received on the UNIBUS within 10 us
after it asserts BGn.
When the CPU
receives the assertion of PUBTMO it
cancels the interrupt cycle and
resumes arbitration.

13.

The

UBA

negates

BGn.

14,

After receiving the negation of BBSY from the
previous bus master the
UNIBUS device asserts BBSY
and negates SACK.

After the UBA receives the negation
of PBSY from the previous PMI cycle
the UBA asserts PBSY and negates
QSACK.

16.

it's

The UBA now has control of the PMI bus
and may initiate a PMI data transfer
cycle(s) and/or an interrupt cycle.

NOTE

The CPU resumes NPR arbitration 75 ns
after
the
BR
resume
not
does
but
QSACK
of
negation
PSW
and
arbitration until it has updated the PC
to
complete
the
interrupt cycle or has aborted
the

interrupt

request.

FUNCTIONAL

PMI

BUS

DESCRIPTION

UNIBUS

__________________________________ B

When a UNIBUS device becomes UNIBUS master through
an- interrupt
request,
it
can perform Interrupt vector cycles or UNIBUS DATI,
DATIP, DATO and DATOB cycles.
If
the
device
accesses
a
PMI
memory
location,
a
PMI
1I/0 Page location or a UNIBUS I/0 Paqge

location, the UBA responds as UNIBUS slave. For PMI memory and
PMI 1I/0 Page accesses, the UBA as the PMI master, controls the
PMI portion of the data transfer. BDIN and BIACK being asserted
does not effect the data transfer.

Data transfer cycles are described in section 3.2.5.

The following sequence describes the interrupt transfer cycle:
17.

The interrupting device, as
bus master, gates its vector
onto the data lines and asserts
INTR.

18.

The UBA,

BRPLY on

as
the

PMI master,

asserts

PMI.

19.

The UBA as slave receives
the assertion of INTR and
latches the interrupt
vector.

20.

The

UBA asserts

SSYN.

21. The UBA gates the vector onto the
DAL

22.

lines.

The CPU latches the interrupt
vector 200 ns minimum after
receiving BRPLY.

23,

The CPU negates BDIN and BIAK.

24. The UBA receives the negation of
BIACK and negates

26.

The

UBA negates

BRPLY.

PBSY.

25.

After receiving SSYN, the
device removes it's vector
from the data lines and
negates INTR and BBSY.
:

FUNCTIONAL DESCRIPTION

3.2.4 PMI Data Transfer Address Cycle

iately after
addressing phase of the PMI cycle starts immed
ted PBSY on
asser
has
and
rship
maste
PMI
d
the CPU or UBA has gaine

The

the

PMI.

The

PMI bus acquisition phase is described in 3.2.1.
MASTER

The address

SLAVE

is gated out on

BDAL<21:00>, and BS7 is asserted
if the address is in the I/O page.
The signal lines BWIBT and PBYT
are asserted to indicate the
cycle to be performed:

BWTBT |

PBYT

Bus Cycle Type
——ac-

———————a—————————————————————-

DATI or DATB

DATIP
DATO
DATOB

L
H
L

H
L
L

When a valid address is
decoded by a slave, it responds as

The UBA asserts PUBMEM if the
address

UNIBUS

PBCYC

follows:

is UNIBUS memory,

I/0 page.

PMI memory and the CPU assert
PSSEL.

asserted.

How the cycle proceeds is dependent
on whether the CPU or UBA is master,
and what the response was from the
slave

follows:

a. When the CPU

is PMI master:

If PSSEL is asserted and PUBMEM is
negated, the CPU proceeds with a PMI

memory

cycle.

If PSSEL is negated, the CPU performs
a PMI cycle with the UBA responding

the

PMI

slave.

b. When the UBA is PMI masters:,

If PSSEL is negated, then the UBA aborts
the PMI cycle and does not respond as

UNIBUS

slave.

—n—————-—————u--—:—wn

—————_-—-————-——————-————————c—a—:———qawuafln———

FUNCTIONAL DESCRIPTION

3.2.5 PMI Data Transfer Protocol

, the data transfer
Following the data transfer address cycle
The transfer of data on the PMI can be grouped
cycle begins.
fer cycles:
into 3 general types of PMI data trans

The Data In (DATI) and Data In Pause (DATIP) cycles.

The Block Data In (DATBI) cycle.

The Data Out (DATO)

are used to read one or two words.

This is used to

to sixteen words.

and

Byte

Out

Data

read

(DATOB) .

These

data

transfer

cycles are used to write a single word or byte.

The following subsections describe each

These

the

cycles.

3.2.6 PMI Data In Cycles (DATI) and (DATIP)

, a PMI master
When accessing the PMI memory address space
two words of data.

or
the DATI(P) cycle to read either Sonememor
y, a
UNIBU
or
page
1/0
r
accessing eithe

PMI

master

uses

When
reads

single words only.

DATI cycle except that
The PMI DATIP cycle is identical to the
that the next cycle
indic
to
PBYT is asserted with the address cycle) ate
be a data out
will
nt
(immediately following the curre
cycle to the same address.

The following is a description of a DATI(P) data transfer cycle:
PMI SLAVE

PMI MASTER
PBCYC is asserted during the address-

ing phase of the cycle (described in

subsection 3.2.4).

Data from the specified
address is gated onto the
bus.

If the slave is PMI memory,

PHBPAR and

PLBPAR are

generated and gated onto
the

bus.

Note: These parity bits are
- e en wn e

—

. S R I D M D GED D W wmp D =

PR—

———-—--————--—-_-—_—---——_----———-----—-

FUNCTIONAL DESCRIPTION

PMI SLAVE _-_..._,..,_
PMI MASTER ______________ I._....__,_._......__._.
._._...-’_._

_____________________

generated only for memory

locations which are cached

on the CPU (i.e. PMI memory).
3,

PRDSTB is asserted.

PRDSTB is negated.

The first data word, with PHBPAR
and PLBAR, are latched on the
negating edge of PRDSTB. If only
one word is to be read, PBCIC

is negated and the cycle ends. If
two words are to be read, PBCYC
remains asserted. If a read-modifywrite (DATIP) is being performed a
DATO cycle will take place here.
The DATO(B) cycle is described in
section 3.2.8.

The second data word 1is
gated onto the bus 80 ns
maximum after the negation
of

PRDSTB.

PHBPAR and PLBPAR are gener-

ated for the second data
word and are gated onto the

bus 100 ns after the negation
of

PRDSTB.

The second data word, along with
PHBPAR and PLBAR, are received
145 ns maximum after the negating
edge of PRDSTB. PBCYC is negated

and the cycle ends. If a read-modify-

write (DATIP) is being performed,
PRCYC remains asserted, and a DATO

cycle is performed here. The DATO(B)
cycle is described in section 4.2.9.
9,

Data is removed from the
bus after receiving the
negation of PBCYC.

FUNCTIONAL

3.2.7

PMI

Block

When

accessing

PMI

Block

data.
accessing
The

PMI

the

Mode

master

following

Cycles

memory

address

(DATBI)

can

start

DATBI

data

=zero
04-01

and
are

flow

the
master
all equal to

describes

the

read

PMI
up

terminates
one.

during

the

uses

the

sixteen

words

cycle

when

even

word

boundaries.
01
and
00

This
must

the

transfer

when

PMI

SLAVE

cycle.

MASTER

asserted

the

specified

addressing

cycle.
The addressing
in section 3.2.4.

asserted.

master
to

transfers

DATBI

phase of the
is described

PBLKM

space

cycle

master
does -not
use
the
DATBI
the I/O page or UNIBUS memory.

PMI
____________ B

only and does not cross sixteen word
at the transfer start, address bits

both
equal
address bits

PBCYC

Data

PMI

Data

A
PMI
either

boundaries
means that

The

Mode

DESCRIPTION

phase

Data

from

address
bus.
3.

the

Note:

gated

slave

PHBPAR

and

gated

These

PLBPAR

parity

PMI

are

onto

generated

onto

the

memory,

generated

the

bus.

bits

are

memory
locations which are cached
on the CPU (i.e. PMI memory).

The

first

data

and PLBAR, is
negating edge

word,

with

latched on
of PRDSTB.

only

for

PRDSTB

asserted.

PRDSTB

negated

data
bus.

removed

The

second

onto

the

and

the

from

the

word

PHBPAR

the

after

the

data

bus

negation

gated

maximum
of

PRDSTB.

FUNCTIONAL DESCRIPTION

PMI MASTER

m
____________________________________ Jeemmm

PMI SLAVE

e ———m————————————

PHBPAR and PLBPAR are generated
for the second word and gated
onto the bus 100 ns maximum
after the negation of PRDSTB.

The second data word, with PHBPAR
and PLBPAR, is received 145 ns
maximum after the negating edge
of

PRDSTB.

10. PBLKM is negated after latching the
second data word.

11. The second data word is
removed from the bus after
receiving the negation of
PBLKM.

12. Data transfer cycles continue
in the same manner as steps 1
thru 11 above until two words
are left to be transferred.
The

last

two words

are

trans-

ferred with the same timing,
but the signal PBLKM is not
asserted by the master.

13. PBCYC is negated after latching
the last data word.

14. Data is removed from the
bus after recieving the
negation of PBCYC.

3.2.8 PMI Data Out Cycles

The PMI master uses the PMI Data Out (DATO or. DATOB)
transfer a single word or byte to a PMI slave

The following flow describes a DATO(B) cycle:

cycles

FUNCTIONAL

PMI

MASTER

PMI

DESCRIPTION

SLAVE

PBCYC is asserted during the addressing
phase of the cycle.
The addressing phase
is described in section 4.2.5.
1.

PBCYC
gated

PWTSTB

PBCYC

3.3

is asserted and
onto the bus.
is

is
is

MEMORY

data

asserted.

The assertion
received and
latched in.

of PWTSTB is
the data is

PSBUFL

asserted.

PSBUFL

negated.

negated.
negated.

MANAGEMENT

Memory management is used to relocate a 16-bit
virtual
address,
if
necessary,
and transmit the 22-bit physical address to cache

memory, or PMI memory.
Address modification is the PMI
function
of
memory
management.
The modification of addresses is called
relocation because it consists of adding a fixed
constant
to
a
virtual

address

to create a physical

address.

Memory management also allows the user to protect one section
of
memory
from
access
by
programs
located
in
another section.
Memory management divides memory into individual sections
called
pages.

Each page has a protection or access key associated with it
that
With
defines the type of access allowed on that particular page.
the memory management unit,
a
page
can
be
Kkeyed
nonresident
(memory
neither
readable
nor writable), no write operations to
memory,
or
read/write.
These
two
types
of
protection,
in
association
with
other
features,
enable the user to develop a
secure

operating

system.

It is often desirable to load a program into one area of physical

memory

memory,

and

for

execute

it as

example,

when

it were

3-19

located

several

in another area of

user

programs

are

FUNCTIONAL DESCRIPTION

When any one program 1is
simultaneously stored 1in memory.
processor as if it were
the
running, it must be accessed by
g at 0. This process is
beginnin
s
located in the set of addresse
called

relocation.

When the processor accesses virtual bus address 0, a base address
is added to it and the relocated 0 location of the program is
accessed. Typically this base address is added to all references
while the program is running. A different base address is used
in memory.

for each of the other programs

Memory management specifies relocation on a page basis, which
allows a large program to be loaded into nonadjacent pages in
memory. This capability eliminates the need to shuffle programs
It also minimizes unusable memory
to accommodate a new one.
to be loaded into a specific
users
more
allowing
fragments, thus

memory

size.

A program and its data can-occupy as many as 16 pages 1in the
The size of each page may vary and can be any multiple
memory.
This feature allows
1in length.
of 32 words up to 4096 words
small areas of memory to be protected (stacks, buffers, etc.),
and also allows the last page of program, exceeding 4K words,

the

adequate

length to protect and relocate the remainder of

program.

As a result,
fixed-length

the memory fragmentation problem inherent with
The base address of each page
pages is eliminated.

space,
address
can be any multiple of 32 words in the physical
The variable page
thus ensuring efficient use of PMI memory.
run
at
changed
dynamically
length also allows the pages to be
time.

use
for
Memory management provides three separate sets of pages
These
modes.
user
and
supervisor,
kernel,
processor's
in the

isolating
sets of pages increase system protection by physically
supervisor programs and the kernel
from service
user programs
program.

The service programs are also separated from the kernel

program.

time
the
reduce
sets greatly
register
relocation
Separate
of
sets
three
The
mapping.
necessary to switch context between
that
system
operating
an
designing
in
registers also aid the user
more
1is
and
modular,
is
communications,
has clearly defined
easily debugged and maintained.

of
The virtual bus address space is further divided, within each
and user pages, into instruction space
supervisor,
kernel,
the
I space contains code, that is,
and data space (I and D space).
word that is part of the program such as instructions, index
any
that
D space contains information
words and immediate operands.
3-20

FUNCTIONAL DESCRIPTION

can be modified, such as data buffers.

cate data and
management can reloaddr
By using this feature, esmemory
ess values.
with separate base
instruction referenc
program of 64K words
ible to have a user
Therefore it is poss
.
consisting of 32K of instructions and 32K of data
Address
registers consists of s 48(PDRPage
The memory management Page
and
s),
Descriptor Register registers four
Registers (PARs), 48
are
s (MMRO-3) . These g subsections
Memory Management Register
owin
located on the KDJ11l-BF module. The foll
»

describe each of the registers.
3.3.1 Page Address Registers

Address
(PARs) contain the 16-bit Page
The Page Address Registers spe
page.
the
of
ess
the base addr
cifies
Field (PAF). The PAR
are
s
ster
regi
e
-are read/write. Thes ruction. Thei
(See figure 3-2.) All bits
r
inst
ole start or a RESET

not affected by iscons
UNDEFINED.
state at power up

FIGURE 3-2 PAGE ADDRESS REGISTER FORMAT
3.3.2 Page Descriptor Registers

on relative
tain informatitro
r Registers (PDR,s) con
The Page Descripto
l. These
con
access
e length and
ansion, pagect
to page exp
a RESET
or
rt
sta
console
not aff edat by
registers are The
unused
All
.
NED
EFI
UND
power up is
state
instruction. zero ir
is
mat
for
er
ist
reg
The
n.
not be writteare
bits read asure 3-3;andbitcandes
3-2.
provided in Table
criptions
show in Fig

L
BYPASS
CACHE

BEDDEERE

PAGEYLENGTH

FIELD

PAGE
TEN
WRIT

Accest|é:&maou.

EXPANSION
DIRECTION

FIGURE 3-3 PAGE DESCRIPFTOR REGISTER FORMAT
3-21

FUNCTIONAL DESCRIPTION

TABLE

Bypass

3-2

Cache

(R/W)

14:8

Page

Length

Field

(R/W)

PAGE

DESCRIPTOR REGISTER BIT DESCRIPTIONS

This bit

implements a conditional

cache

bypass mechanism. If set, references to the
selected virtual page will bypass the cache. A
cache bypass causes the cache location to be
invalidated whenever a read or write hit occurs.
This field specifies the block numbe which
defines the boundary of the current page. The

block number of the virtual address is
compared against the Page Length Field to
detect length errors.’ An error occurs when
expanding upwards

if the block

number

Field, and
is greater than the Page Length
when expanding down if the block number is
less than the Page Length Field.

Page

Written

(RO)

or not this page
whether
indicates
bit
This
into) since
written
(i.e.
has been modified
(1 is
loaded
was
PDR
or
PAR
the
either
affirmative). It is useful in applications
which

involve disk

swapping and memory

which pages
It is used to determine
overlays.
have been modified and hence must be saved in

their new and which pages have not been
modified and can simply be overlaid.

This bit is reset to 0 whenever either the PDR
or the associated PAR is written into.

Expansion
Direction

(R/W)

This bit specifies in which direction the page
expands. If ED=0 the page expands upwards from
block number 0 to include blocks with higher
addresses; if ED=1, the page expands downwards
from block number 127 to include blocks with
lower addresses. Upward expansion is usually
used for program space while downward
expansion

Access

Control

is used

for stack

space.

This field contains the acces rights to
this particular pace. The access codes or
"keys" specify the manner in which a page may
be accessed and whether or not a given access
———'

--‘—----—---a-—--"“--——-—-—-—---‘-—-——--‘_--—-----—-—-———--v

FUNCTIONAL

TABLE

GER TED CED

IR NED

GNP

GND CHD

GNE

GED

should

GED

CED

00
01
10
11

Memory

Management

result

operation.

3.3.3

3-2

The

(Cont)

GER

GED

GER

GED

AED

GED

abort

access

GED

GAS

GED

the

codes

GED

STID

GED

current
are:

Non-resident - abort
Read only - abort on
Not used - abort all
Read/write

GHD

DESCRIPTION

all accesses
writes
accesses

(MMRO),

address

777

572,

contains
error flags, the page number whose reference caused the
abort, and various other status flags.
MMRO is cleared at
power
up,
by
a console start, and by a RESET instruction.
Figure 3-4
shows
the
register
format;
Table
3-3
contains
the
bit
descriptions.

ABORT: READ ONLY
ABORT: PAGE LENGTH
ABORT: NON-RESIDENT
PROCESSOR MOOE

PAGE SPACE
PAGE NUMBER
ENABLE RELOCATION

FIGURE

3-4

MEMORY

MANAGEMENT

FORMAT

FUNCTIONAL

DESCRIPTION

TABLE

BIT

3-3

MEMORY

MANAGEMENT

NAME

Abort Non Resident
(R/WO

BIT

DESCRIPTIONS

FUNCTION

Bit 15
a page

is set by attempting to access
with an Access Control Field

key egqual to 0 or 2.
It is also set
by attempting to use memory relocation with a mode (PS<15:14>) of 2.

Abort Page Length

This bit is set
a location in a

(R/W)

number

by attempting to access
page with a block

<12:6>)

(virtual address bits

that is outside the area authorized
by the Page Length Field of the Page
Descriptor Register for that page.

Abort -

This

Read

write

Only"

pages

Onlv

(R/W)

bit is
a

set

attempting

"Read

Onlv"

page.

have

access

keys

to
"Read-

NOTE: Bits <15:13> can be set by an explicit write;
however such an action does not cause an abort.
Whether set explicitly or by an abort, bits <«15:13>
cause memory management to freeze the contents of
MMRO <6:1>, MMR1l, and MMR2.
The status registers
remain frozen until MMRO <15:13> are cleared by an
explict write or any initialization sequence.

6:5

Processor
Mode (RO)

Page

Space

(RO)

These

bits indicate the processor mode
(kernel/supervisor/user/illegal) associated with the page causing the abort
(kernel = 00, supervisor = 01, user =
11, illegal = 10).
1If the illegal mode
is specified, an abort is ¢generated and
bit <15> is set.
This

abort
Number

bit

indicates

associated

3:1

Page
(RO)

Enable

This

Relocation
(R/W)

set to 1, all
When bit 0 is

the

address

with

the

page

space,

These three bits
the page causing

bit

allows

page

number

relocation.

When

addresses are relocated.
set to 0, memory manage-

ment is inoperative
not relocated.

and

the

space).

contain the
the abort.

address

space

causing

addresses

are

FUNCTIONAL DESCRIPTION

3.3.4

Memory Management Register

Memory Management Register 1

(MMR1l)

address

17777574

records

any auto increment or decrement of the general purpose-registers.
This register supplies necessary information
needed
to
recover
from a memory management abort.
MMR1l is read only.
Its state at
Figure 3-5 shows the register format.
power up is UNDEFINED.

VIRTUALADDRESS
FIGURE
3.3.5

Memory

3-5 MEMORY. MANAGEMENT REGISTER

Management

Figure

3-6

shows

T —

AMOUNT CHANGED

{2'S COMPLEMENT)

the

FORMAT

Memory Management Register 2 (MMR2), at
loaded
with
the
virtual
address
at
instruction fetch.
MMR2 is read only.
UNDEFINED.

address 17
777
576,
|is
the
beginning
of
each
Its state at power up
is

NUMBER

format.

AMOUNT CHANGED

{7'S COMPLEMENT)

~~—

NUMBER

FIGURE 3-6 MEMORY MANAGEMENT REGISTER 2 FORMAT

3.3.6 Memory Management Register 3

772 516,
17
at address
(MMR3),
Memory Management Register 3
enables or disables D space, 22-bit mapping, the CSM instruction,
and the I/0 map

(when applicable).

MMR3 is cleared at power

up,

Figure 3-7 shows
by a console start, and by a RESET instruction.
s.
description
the register format; Table 3-4 provides the bit

FUNCTIONAL DESCRIPTION

ENABLE UNIBUS MAP

ENABLE 22-81T MAPPING
ENABLE CSM INSTRUCTION

ENABLE KERNEL DATA SPACE

ENABLE SUPERVISOR DATA SPACE
ENABLE USER DATA SPACE

FIGURE 3-7 MEMORY MANAGEMENT REGISTER 3 FORMAT

TABLE 3-4 MEMORY MANAGEMENT REGISTER 3 BIT DESCRIPTIONS
NAME

BIT(S)
15:06

Unused.

2 =====

Enable UNIBUS
Map (R/W)

Enable

22-bit

Mapping

(R/W)

This bit enables the I/O Map for the
UNIBUS

Adapter.

This bit, when set, selects 22-bit memory

addressing. When this bit is clear, 18-bit
addressing is selected. (18 or 22-bit
addressing is actually enabled only when
MMRO bit 0

Enable CSM
Instruction

is set).

This bit enables recognition of the Call

Supervisor Mode instruction.

(R/W)

2:0

Enable Data
Space (R/W)

These three bits enable Data

Space mapping for kernel, supervisor,

and user mode, respectively.

3.3.7 Physical Address Construction

If UNIBUS map relocation is enabled (MMR3 bit 05 = 1), UNIBUS
er pairs
address bits <17:13> select one of 31 mapping regist
of the
t
conten
(corresponding to octal codes 00 thru 36)., The
address
UNIBUS
to
selected mapping register pair |is added

bits<12:00> to produce the memory

address.

UNIBUS

address

FUNCTIONAL

DESCRIPTION

37), the I/O Page is
code
(octal
ones
all
are
<17:13>
bits
=zeros,,
all
Memory address bits <21:18> are set equal
selected.
bits
address
UNIBUS
to
memory address bits <17:00> are identical
<17:00>,

and BBS7

is asserted.

See Figure 3-8.

UNIBUS ADORESS [

01 00

W
|

ADDRESS 8ITS 17-13

SELECT ONE OF 31

MAPPING REGISTER PAIRS

186

THROUGH

36
(OCTAL}

=
ADDER

L
FIGURE

3.3.8

Memory

3-8

PHYSICAL ADDRESS

INTERPRETATION

Relocation

When memory management is enabled, the normal 16-bit
direct-byte
address
is
no
longer
interpreted as a direct physical address
(PA) but as a virtual bus address (VBA) containing information to
be
used
in
constructing
a
new
22-bit
PA.
The information
contained in the VBA
is
combined
with
relocation
information
contained in the page address register (PAR) to make a 22-bit PA.
Using memory management, memory can be dynamically
allocated
1in
pages composed of from 1 to 128 blocks of 32 words each.
The starting PA for each page is a multiple of 32 words, and each
page
has
a
maximum
size
of 4096 words.
Pages may be located
anywhere within the PA space.
The set of 16 PARs to be
used
to
create
the
PA is determined by the current mode of operation of
the CPU (i.e., kernel, supervisor, or user modes ; ref subsection
3-10).

3.4

KDJ11-BF CACHE

The CPU has dual
concurrent
DMA

tag cache memories.
They
are
used
to
allow
a
activity,
and decrease system access time of

instructions and data.

The 8KB cache
3-27

is located on

the

KDJ1l1l-B

FUNCTIONAL DESCRIPTION

module.

UNIBUS memory

is not cached.

for

only

occur

operations

Cache

PMI memory cycles,

Figure 3-9 is a matrix showing the cache response for both DMA a
CPU data transfers from and to the PMI memory space. There are

The

two cache memory tags referenced in the matrix.

heading refers to DMA activity.

PMI activity

DMA

matrix

The CPU matrix heading refers to

involving the CPU tag.

DMA

READ
WARITE
WOROD

READ

MEMORY

INVALIDATE
CACRHE-WRITE
MEMORY

WRITE | INVAUIDATE

cru

READ

MEMORY

N/A

WRITE

N/A

WRITE
FORCE
wss

READ

MEMORY

WRITE

MEMORYINVALIDATE
CACHE

WRITE BCITH
CACHE AND

WRITE BOTH | mremORY

MEMORY

N/A

READ

CACHE

WRITE

READ
BYPASS

FORCE
MISS

AND ALLOCATE

OATA

WRITE BOTH
CACHE AND

CACHE-WRITE

BYPASS

READ CACHED | READ MENMORY

WRITE
MEMORY

8YTE

MEMORY

miss

Wit

MISS

CACHE AND

INO CACHE

INVALIOATE

READ MEMORY

INVALIDATE

RaCHE

CHANGE

MEMORY

-NO CACHE
CACHE AND
READ MEMORY | CHANGE

CACHE AND

WRITE

WRITE MEMORY |

READ

MEMORY

whiTe
MEMORY

oha ol

READ MEMORY | READ MEMORY

-NO CACHE
CHANGE

WRITE

MEMORY
~NO CACMHE
CHANGE

-NO CACHE
CHANGE

WRITE

MEMORY
~NO CACHE
CHANG:

FIGURE 3-9 CACHE RESPONSE MATRIX

Cache Parity Errors affect

the

Cache

Response

Matrix

the

following ways:

Error forces a
During DMA Write Cycles, a DMA Tag Parity
is invalidated.
location
Cache Hit response, and the cache

During CPU Read Cycles

During CPU Write Byte Cycles (Non-Bypass; Non-Force Miss),
a CPU Tag Parity Error forces a Cache Hit response, but the

(Non-Bypass),

Parity Error forces a Cache Miss

data is loaded with bad parity.

CPU

response.

Tag

Data

FUNCTIONAL

DESCRIPTION

During CPU Read Bypass or Write Bypass Cycles, a
Data
Parity
Error forces a Cache Hit Response.
location is invalidated.

For all Force Miss Cycles,
(Non-Bypass)

3.4.1

KDJ11-BF

Cycle,

Cache

The KDJ11-BF
cache
KDJ11-BF
addresses

Cache

and

Parity

for
is

the

CPU

CPU Tag or
The cache

Write

ignored.

Word

Operations

1is
PMI

1initially
flushed
memory
locations,

(emptied).
As
the
the
KDJ1ll-BF cache

begins
to
fill
with
addresses
and
data.
If
the
KDJ11l-BF
addresses
PMI
memory within an 8K memory space the cache fills,
as the addresses are accessed, to the 8K limit of the cache size.
This means that for each cache address location the data for that
address is a duplicate of the corresponding PMI address's data.

As each instruction is accessed by the KDJ1ll-BF it's
address
|is
compared
1in
<cache
to see if there are any matches.
If a match
occurs the PMI memory cycle is aborted and the data stored in the

cache
address
1is
wused by the KDJ11-BF.
1If a cache miss occurs
the PMI memory cycle is completed.
In addition to
filling
it's
cache monitors the PMI address lines for DMA
the
space
memory
writes

address

to PMI memory addresses.

If a write

into

PMI

memory

matches a cache address that particular cache address

invalidated.

The following cache options are available on the KDJ11l-BF:
l.

Conditional

made

cache bypass - selected virtual

pages

can

Bit <15> in the PDRs sets this

bypass the cache.

condition.

Unconditional

cache bypass - all CPU references

to bypass the cache.

sets

this

condition.

Bit <9>

Flush cache -

Lock
instruction
(ASRB,
TSTSET,
and
WRTCLK)
instructions guarantee a cache bypass reference.

3.4.2

KDJ11-BF Cache

all Valid bits

can be made

in the Cache Control register

in the cache are

cleared.
-

these

Organization

TAG
dual
The KDJ11-BF contains an 8K byte direct map cache with
The
Store which allows concurrent operations of the CPU and DMA.
sections:
distinct
three
1into
subdivided
Cache Memory can be
Data

Store,

CPU TAG

Store and

the

DMA TAG

Store.

FUNCTIONAL DESCRIPTION

The KDJ11-BF Cache interprets the CPU (or DMA)

shown

description.

Figure

3-10

and

Table

3-5

physical

contains

address

bit

the

BN
CACHE INDEX

CACHE TAG

BYTE
SELECTION

FIGURE 3-10 CPU/DMA PHYSICAL ADDRESS INTERPRETATION REGISTER
TABLE

3-5

CPU/DMA PHYSICAL ADDRESS INTERPRETATION BIT DESCRIPTIONS
S

D SED G

21:13

CED

D WD

Cache
(R/W)

D CHD

D e

Tag

1. During CPU read/write operations,

these bits are compared with bits 21:13
of the CPU Cache Tag Register (Figure 3-11)
to determine the cache hit/miss status.
2. During DMA read/write operations,

these bits are compared with bits 21:13
of the DMA Tag Register (Figure 3-12) to
determine the cache hit/miss status.

For either CPU or DMA operations a tag
hit occurs when the cache tag contents

matches the CPU/DMA tag register and the
CPU/DMA valid bit

12:01

Cache
(R/W)

Index

Byte

Selection

The High Byte
<15:08>.

is set.

The CPU cache interprets the CPU/DMA
physical address directly and selects
one of 4096 word cache memory locations.
During CPU/DMA write operatons setting
this bit selects writing into the high byte
cache memory location (Figure 3-13).

Parity

bit

reflects
3-30

odd

parity

data

bits

FUNCTIONAL

The Low Byte

Parity

bit

reflects

even

parity

DESCRIPTION

data

bits

<07:00>,

The CPU Tag Parity bit

reflects

odd

parity

CPU

Tag

bits

The DMA Tag Parity bit

reflects

odd

parity

DMA

Tag

bits

<21:13>.

The CPU and DMA Tag Valid bits are not
DMA Tag

parity

included

the

CPU

and

calculations.

[ T T T [ Jelofofofofelolefofofefefe]
TAG
¢PU

CPU TAG
PARITY (ODD)

CPU TAG
VAIID

FIGURE 3-11 CPU CACHE TAG REGISTER FORMAT

27 20

olololo]olo

olo

DMA TAG
OMA TAG
PARITY (ODO)

DMA TAG VALID

FIGURE 3-12 DMA TAG REGISTER FORMAT

o]olo

FUNCTIONAL DESCRIPTION

—

LOW BYTE

HIGH BYTE

DATA

HIGH BYTE
PARITY {ODDY

LOwW BYTE
.
PARITY (EVEN)

FIGURE 3-13 CPU CACHE DATA ORGANIZATION

3.4.3

Cache Control

(CCR), at address 17 777 746, controls
Two copies of the cache control
the operation of the cache.
register are kept on the KDJ11-BF. One copy is kept in the chip
The chip copy implements bits <10:0>
set:the other on the board.
as read/write but interprets only bits <9 and 3:2>. This copy is
The board
used as the source of data when the register is read.
copy.
write-only
‘a
is
This
>.
<10,8,7,6,0
bits
copy implements
shows the
3=14
Figure
accessed.
be explicitly
can not
It

The Cache Control Register

WRITE WRONG
TAG PARITY

UNCONDITIONAL

CACHE BYPASS
FLUSH CACHE

ENABLE PARITY
ERROR ABORT
WRITE WRONG
DATA PARITY

UNINTERPRETED

FORCE CACHE MISS
~

DIAGNOSTIC MODE

DISABLE CACHE
PARITY INTERRUPT

FIGURE

3-14

CACHE

CONTROL

FORMAT

FUNCTIONAL DESCRIPTION

TABLE

BIT(S)

3-6

CACHE CONTROL REGISTER BIT DESCRIPTIONS

FUNCTION

NAME

—--———————

——u—————--—---—-—--——--—--s--———-d———_—-—————-——---—-———-h-—

Always

15:11

Unused

Write Wrong
Tag Parity

(R/W)

read

cleared bits.

When this bit is set, the CPU and
Tag Parity bits are both written

as wrong parity during all operations
which update these bits. A cache tag parity
error will thus occur on
to that location.

Unconditional

cache

bypass

(R/W)

Flush

Cache

(WO)

Parity

Error

Abort

(R/W)

When

this

bit

Write Wrong
Data Parity
(R/W)

will

not

affect

set,

all

the

next access

references

memory by the CPU will bypass the cache
and go directly to main memory. Read or
write hits will result in the invalidation
of the corresponding cache location; misses

Writing a

"1"

the

into

cache

contents.

this bit clears

all

CPU Tag and DMA Tag Valid bits invalidating
the entire contents of the cache. Writing
a "0" into this bit has no effect. Flush
Cache always reads as zero. The KDJ1l1l-BF
requires approximately 1 msec to flush
the cache. During the period, DMA activity
is possible and CPU activity is suspended.
This bit is set for diagnostic purposes only.
When it is set, a cache parity error (during
a CPU cache read) will cause the CPU to abort
the current instruction and trap to parity error
vector 114. When this bit is clear, a cache
parity error (during a CPU cache read) results
in a force miss and data fetch from main memory.
The CPU will trap to 114 only if CCR bit <0> is
clear. DMA cycle cache parity errors will
cause a trap to 114 if CCR <7> is set or if
CCR <0> is clear. CCR <7> has no effect on
main memory parity errors which always cause
the CPU to abort the current instruction
and

DMA

trap

114.

When this bit is set, both the high and low
data parity bits are written with wrong parity
during all operations which update these bits.
This will cause a

cache data parity error to

occur on the next access to that location.

FUNCTIONAL DESCRIPTION

TABLE

3-6

(Cont)
FUNCTION

BIT(S)

NAME

03:02

Force Miss

When either of these bits is set, CPU reads

Diagnostic
Mode (R/W)

When this bit is set, a 10 usec nonexistant
memory timeout during a word write will not

(R/W)

will be reported as cache misses.

cause a nonexistant memory trap and will not
set CPU Error Register bit 05. All non-bypass
and non-forced miss word writes will allocate
the cache irregardless of the nonexistant

memory

timeout.

Disable Cache This bit controls Cache Parity Interrupts when
CCR <7> is clear (normal operation). If CCR <7>
Parity
is clear, a cache parity error (during a CPU
Interrupt

cache read) results in a force miss and data

(R/W)

fetch from main memory. The CPU will trap to
114 only if CCR bit <0> is clear. DMA cycle

cache parity errors will cause a trap to 114
if CCR <7> is set or if CCR <0> is clear.

Table 3-7 summarizes the effect of CCR

<7,0>

parity

errors

during CPU cache reads.

Table 3-7

CACHE PARITY ERRORS DURING CPU CYCLES

Cache Miss and Update Cache;

Cache Miss and Update cache;

Abort Instruction and Trap to ll4.

Interrupt

114.

Interrupt.

Table 3-8 summarizes the effect of CCR <7,0> on
errors during DMA writes.

DMA

Tag

Parity

FUNCTIONAL

3-8

TABLE

PARITY ERRORS DURING DMA CYCLES

CACHE

Result of Cache Parity Error

CCR<O>

CCR<7>

DESCRIPTION

Interrupt

Trap

The Cache Control Register

to 114.

Interrupt.

114.

is cleared by the negation of DCOK and

The Jl1 ODT
It is-not affected by BUS INIT.
by a console start.
cleared.
be
to
CCR
and
flushed
be
to
cache
command G will cause
3.4.4

Memory System Error Register

777 744,
The Memory System Error Register (MSER), at address 17
MSER
reflects the status of cache and main memory parity errors.
bits 14 and 13 are used by the KDJ11-BF Boot and Diagnostic
Figure 3-15 shows the
to test the Cache DMA Tag Store.
programs
register format; Table 3-9 contains the bit descriptions.
15

‘

}

DTS PAR

OTS CmP
CPU ABORT

CACHE HB DATA PARITY ERROR
CACHE LB DATA PARITY ERROR
CACHE CPU TAG PARITY ERROR
CACHE DMA TAG PARITY ERROR

FIGURE 3-15 MEMORY SYSTEM ERROR REGISTER FORMAT

FUNCTIONAL

DESCRIPTION

TABLE 3-9 MEMORY SYSTEM ERROR REGISTER BIT DESCRIPTIONS

CPU

P I

D G

S W SIS S

D D GER GED G

RO ADD WD G GED GED CEO WD OO N

NP b G N

This bit is set if a cache or main memory
parity error results in an instruction

Abort

(RO)

abort (i.e. only during the demand read cycle).
Cache parity errors cause an abort only if
CCR <7> is set. Main memory parity errors
always

DMA

Tag

Store

Comparator

(DTS

CMP)

(RO)

In Stand-Alone Mode (BCSR <8> set), this bit
indicates the output of the Cache DMA Tag
Store Comparator for the previous non-I/0 Page
reference with cache miss. When BCSR <8> is
clear, DTS CMP reads as a "O".

DMA Tag

cause an abort.

In Stand-Alone Mode (BCSR <8> set), this bit
indicates the output of the DMA Tag Store

Store

Parity

(DTS
(RO)

non—-I1/0

Parity Check Logic. for the previous

PAR)

Page Reference with cache miss. When BCSR <8>
is clear, DTS PAR reads as a "0".

These bits always read as

12-08

Unused

Cache HB
Data Parity
Error (R/W)

"0".

This bit is set if a parity error is
detected in the high data byte during a CPU

cache read. If CCR <7> is clear, MSER <7> is
also set by a low byte parity error and by the
set condition of MSER <5> or <4>.

Cache

0é

Parity

Data

Error

(RO)

high byte parity error and by the set
condition MSER bits <5> or <4>.

Cache CPU Tag
Parity Error

(RO)

m o

- - e

This bit is set if a parity error is detected
in the CPU tag field during a CPU cache read.
If CCR <7> is clear, MSER <7> is also set by a
high or low data byte parity error.

Note:

This bit is set if a parity error is detected
in the low data byte during a CPU cache read.
If CCR <7> is clear, MSER <6> is also set by a

- -

Cache parity errors are ignored (do not affect
MSER <7-5>), if either CCR <3> or <2> (Force Miss)
is set or if the CPU Tag Valid bit is clear.
D €

wH e

oD e

D o

- -

D SR G

D D

D WD WD

D S

TED D

S W

D N WD N

- D

R I

D A

GED

S S

) S

—

FUNCTIONAL

TABLE

3-9

BIT

(Cont)

NAME

FUNCTION

Cache

DMA

Parity

Tag

This

Error

(RO)

bit

the

DMA

set
tag

parity

error

field

during

write

Cache

MSER

parity

<4>),

set

Unused

errors

are

either

the

These

DMA

bits

ignored

CCR

<3>

Tag Valid

always

read

zero.

parity

occur

result

depending on
1If

CCR

trap

1If

CCR

during

abort

the

following

condition

<7>

(Parity

error
causes
set MSER <15>
to

which

instruction

thru
<7>

Error

CCR

<7>

error

Abort)

location

clear,

causes

and

the

and

CPU

DMA

tag

field

cause

trap

parity

location

relevant error bits MSER
vector location 114.
Cache

CPU

and/or

CCR

force

trap

CCR

bits

<7>

set,

<0>

access

may

location

114,

and

<0>:

cache

parity

instruction, to
MSER <7: 5>
and

also

force a
and
to

<0>
a

<7:5>.

which

114

CCR

set,

miss

CPU

occur

<K7>

clear,

cache miss,
trap
thru

cache

The

errors

abort
the
thru vector

Cache

1is

Miss)

clear.

114.

parity
error causes the CPU to
relevant error bits MSER <7:5>
location 114.
3.

detected

affect

CPU
to
to trap

the CPU to abort the current
and the relevant error bit(s)
vector

(Force

Cache

errors

not

always
cause
the
set
MSER <15> and

(do

<2>

bit

Main memory parity errors
current
instruction,
to
location 114.

DMA

operation.

Note:

03:00

DESCRIPTION

cache
and

does

not

during

set

any

cache

set the
vector

parity
set

trap

DMA

CCR

the

thru

cycle

<0>

clear.
The

Memory

reference.

System
It

unaffected

Error
also

RESET

cleared

power

instruction.

MSER

write

console

start.

FUNCTIONAL DESCRIPTION

3.4.5 Hit/Miss Register

This register, at address 17 777 752, indicates whether the six
most recent CPU memory references resulted in cache hits or cache

misses.

The Hit/Miss Register is read only.

Its value at

power

The Hit/Miss Register 1is not affected by
up 1s UNDEFINED.
The Hit/ Miss Register
console start or a RESET instruction.
will always read zero when the CPU is in console ODT mode.
Figure 3-16 illustrates the register format; Table 3-10 contains
the bit descriptions.

HIT/MISS REGISTER FORMAT

FIGURE 3-16

- TABLE 3-10 HIT/MISS REGISTER BIT DESCRIPTIONS

read as

zeros.

15:06

Unused

Always

05:00

Cache Hit

Bits enter from the right (at bit <0>) and are
shifted leftward. A set bit indicates a cache
hit, a cleared bit indicates a cache miss.

3.5 ADDITIONAL CPU REGISTER DESCRIPTIONS
The general CPU Registers

include:

Two sets of six working registers (RO-R5)

Kernel/supervisor/user stack pointers (R6)
Program counter

(R7).

Other major registers are described in the following subsections.

FUNCTIONAL DESCRIPTION

3.5.1 Processor Status Word

17 777 776, contains
The Processor Status Word (PS), at location
The PSW 1is
on the status of the processor. CONFI
information
GURATION
initialized at power up (depends on . EE ThePROM
uction
instr
RESET
options) and is cleared at console start
and
ter
regis
the
s
trate
does not affect the PS., Figure 3-17 illus
Table 3-11 contains the bit descriptions.
15

CARRY

PRIORITY

SUSPENDED

LEVEL

INSTRUCTION

OVERFLOW

- ZERO

SET

NEGATIVE

TRACE TRAP

MANAGEMENT MODE

PREVIOUS MEMORY

CURRENT MEMORY
MANAGEMENT MODE

. FIGURE 3-17 PROCESSOR STATUS WORD REGISTER

TABLE 3-11 PROCESSOR STATUS WORD BIT DESCRIPTIONS
BIT

NAME

15514

Current Mode

(R/W, protected)

FUNCTION

Current processor mode:
00 = kernel
01

= supervisor

10 = illegal

(traps)

user.

13:12

Previous Mode

Previous processor mode, same

General register set select:

(R/W, protected)

encoding as current mode.

0 = register set O

1 = register set 1.

D G P WD S S WP S GE G D D D IR G WD WD WP W W S W - D D AN G W S WD R SR NP GUY GED AU I W D )

S DW

- ED NN A SR G P WS WD

FUNCTIONAL

TABLE

DESCRIPTION

3-11

(Cont)

Suspended
Instruction(R/W)

Reserved

7:5

Priority
(R/W, protected)

Processor
level.

Trace

Trap

Set

(R/W,

protected)

3:0

Condition Codes

3.5.2

Program

The

Interrupt Request
implements
a
software

772,

Request

Program

interrupt
location

request
240,
responsibility to
exiting.
PIRQ is

future

interrupt

force

trace

Processor condition

(R/W)

Interrupt

for

use.

priority

trap.

codes.

(PIRQ),

interrupt

location

facility.

1is

When

777

program

granted,
the
processor
traps
through
is
the
interrupt
service
routine's
clear
the
appropriate
bit
in
PIRQ
before
cleared at power-up, by a console start and by
It

the RESET instruction.
Table 3-12 contains the

Figure

bit

3-18 illustrates
descriptions.

PIR7

)

PRIORITY ENCODED
VALUE OF BITS<15:9>

the

PRIORITY ENCODED
VALUE OF BITS<15:9>

PIR6

PIRS

PiR4
PR3
PIR2

FIGURE

3-18

PROGRAM

INTERRUPT

3-40

REQUEST

and

FUNCTIONAL

DESCRIPTION

TABLE 3-12 PROGRAM INTERRUPT REQUEST REGISTER BIT DESCRIPTIONS

15:09

Each bit, when set, provides one of

PIR 7-1

seven levels of software interrupt
corresponding to interrupt priority
levels 7 through 1.

07:05

Unused.

These three bits are set by the CPU
to the encoded value of the highest
pending interrupt request (bits 15:09).

Piority encoded
value of bits
<15:09>

03:00

Unused.

Piority encoded

The function of these bits is

value of bits

to bits

07:05.

identical

<15:09>

3.5.3

CPU Error Register

The Error Register, at address 17 777 766, identifies the

source

of any abort or trap that caused a trap through location 4. The
It is also
CPU Error Register is cleared when it is written.
It is unaffected by a
cleared at power up or by console start.
RESET instruction. Figure 3-19 shows the register format; Table
3-13

contains the bit descriptions.

ILLEGAL HALT ——‘
ADDRESS ERROR

NONEXISTENT MEMORY

1/Q BUS TIMEQUT
YELLOW STACK VIOLATION

RED STACK VIOLATION

FIGURE 3-19 CPU ERROR REGISTER FORMAT
3-41

DESCRIPTION

FUNCTIONAL

TABLE 3-13 CPU ERROR REGISTER BIT DESCRIPTIONS

Illegal

HALT

Set when execution of a HALT instruction
is attempted in user or supervisor mode.

Address

Error

Set when word access to an odd byte

(RO)

address or an instruction fetch from an

Non-existent

Set when a reference to main memory

Memory

times

internal register is attempted.

(RO)

out.

Set when a reference to the I/O page

I/0 Bus
Timeout

times

out.

(RO)

Set on a yellow zone stack overflow

Yellow Stack
Violation

trap.

(RO)

Set on a red zone stack overflow trap.

Red Stack
Violation

3.5.4 CONFIGURATION AND DISPLAY REGISTER
Configuration

The read-only Boot and Diagnostic

reflects the status of the eight edge-mounted switches at the top
All of the switches are also routed
KDJ11-BF module to allow them to be asserted

of the KDJ11-BF module.
on

connectors

the

Switches 1-8 control register bits 7-0 respectively.

remotely.

NOTE

All eight
and
restricted

OFF,

switches on

setting

the

any

special

KDJ11l-BF

these

applications.

module

switches

Refer

Appendix H for a more detailed description.

are

1is

Data bits 2-0 (switches 6-8) are also connected directly

three

baud

module to select the baud rate.
the

baud

purpose.

rate select lines of the console SLU on the KDJ11-BF
These

three bits always

control

console, and are not used for any other
the
rate
Dbaud
the
normally OFF to allow
are
Switches 6-8
3-42

FUNCTIONAL DESCRIPTION

select switch on the Console Serial Line board (rear of box or
cabinet) to select the baud rate. This eliminates the need to
gain access to the CPU module to select the baud rate.

The only time switches 6-8 would be used to select the baud
is

if the baud rate switch was not present.

for additional information.

rate

Refer to-Appendix H

Data bits 7-3 (switches 1-5) are read by the ROM code to define
by the ROM code after power up or
some of the actions to be taken
a detail description of each of
for
H
restart. Refer to Appendix
these bits.

Bits 15-8 are always read
The value of bits 7-0 depends on the position of the
as 2zeros.
switches on the CPU module, and any external switch which might

Figure 3-20 shows the register format.
be

connected.

X =

don't

care

FIGURE 3-20 BOOT AND DIAGNOSTIC CONFIGURATION REGISTER FORMAT

The write-only Boot and Diagnostic Display Register (BDR), at
address 17 777 524, allows the Boot Diagnostic programs to light
the front panel Start-Up Test LED display and the LEDs on the
These display bits are also available on an
KDJ11-B module.
Bits 05-00 are cleared on power up (all LEDs
external connector.
Figure 3-21 shows the register
negation of DCOK.
the
by
on)
format; Table 3-14 contains the bit descriptions.

8-817T
SWITCH PACK

X = dont't care

FIGURE

3-21

DISPLAY

3-43

FUNCTIONAL

DESCRIPTION

TABLE

3-14

DISPLAY REGISTER BIT DESCRIPTIONS

15::06

=—--

Unused

05::00

LED 5-0

These bits enable the boot and diagnostic
programs to light the LEDs located at the
top of the CPU module. Clearing any of
these bits lights the corresponding LED.

3.5.5

Maintenance

The Maintenance Register, at address 17
777
750,
accesses
the
16-bit word read by the Jl1 Chip Set (through GPO Code) test BPOK
H, read the power up option code, read the halt/trap option
bit.
Other
bits
in
the
maintenance
register,
not
used
by
Jll
microcode, contain information on
the
module
type
and
system
parameters
useful
to
operating system and diagnostic software.
Figure 3-22 shows the register format; Table
3-15
contains
the
bit

descriptions.

The

power up option

code

hard

wired

operation
(code
2).
The
PSW
1is set
begins
program
execution
at
address

for

standard

bootstrap

to 340 and the processor
173000.
The
Boot
and

Diagnostic
Code,
which
starts at that location, configures the
KDJ11-B and runs stand-alone diagnostics
before
acting
on
the
user
specified
power
up
option
stored
as part of the EEPROM
Configuration

Data.

Because the J1ll1 Microcode never sees
power
up
option
code
3,
selecting
a
start
location specified by register bits <15:09>,
these Maintenance
Register
bits
are
used
to
specify
system
parameters.
15

]

RESERVED

UNIBUS SYSTEM
FPA AVAILABLE

MODULE TYPE (FIXED)
HALT/TRAP OPTION

POWER UP OPTION (FIXED)
BPOK H

FIGURE

3-22

MAINTENANCE
3-44

FORMAT

FUNCTIONAL DESCRIPTION

TABLE 3-15 MAINTENANCE REGISTER BIT DESCRIPTIONS

AP TP GED GHD GED

P GED

D GED GRS WED WD

Reserved for future expansion.

15:11

Unused

Reserved

UNIBUS

This bit reflects the status of the extrenally
applied UNIBUS Adapter Line. A "1" indicates

System

Read

zeros.

for

future use.

(RO)

that the system includes a UNIBUS Adapter.

FPA

When set, this bit indicates that the FPA is

Available

available

for use.

(RO)
07:04

Module
Type

Halt/Trap

02-01

Power Up

(R/W)

Code

This 4-bit code is hard-wired as a n2v,
indicating a KDJ11-BF Module.

This read/write bit determines the response of
a processor to a Kernel Mode Halt instruction.
Setting the bit selects the Trap Option,
causing the CPU to trap to location 4. Clearing
the bit selects the Halt Option, causing the CPU
to halt and enter ODT. This bit is cleared by
the negation of DCOK and is set by the Boot and
Diagnostic ROM code if the Trap Option is
selected by a bit in the Configuration RAM. The
Trap Option is not intended for normal use and
is reserved for controller applications.
This 2-bit code is hard-wired as a "2". At

power up, the processor sets the PC to 173000

and sets the PSW to 370. It then starts program

execution at location 173000, which is the
starting location for the KDJ11-BF Boot and
Diagnostic ROM program. These programs test
out the KDJ11-BF Module and then implement

the user selected power up option specified in
the Configuration Data.

This bit is set (1) if the PMI BUS signal BPOK H
is asserted, indicating that AC Power is okay.

FUNCTIONAL

DESCRIPTION

3.5.6

Boot

The

and Diagnostic Controller
17
777
520, is both word
the
register
format;
Table

and

Diagnostic

Controller

Boot

address

3-23
descriptions.
programs

PMG

test

from

the

BCSR

response
17765776

alone

also
of

read/write

Halt

backup

Status
and

the

Break

set

Counter

feature

Boot

these
and

programs

Diagnostic

access the I/O
parameters, to

control

access

¢¢BCSR),

addressable.

bit
ROM

parameters

the

for

line

clock,

enter

disable
the
addresses 17765000 -

17773776

and

control

Page

can use the BCSR to alter
PMG
enable or disable the Halt on Break
to the ROM and and EEPROM memories.

PMG CNTY

FRC LCIE

PMG CNT2

OIS LKS
CLK SEL 1

RS3 WE

CLK SELO

RS3 85

ENB HOB

DIS 65

SA MOODE

3-23

oIS 73

BOOT

AND

exit

selectively

NOT USED

FIGURE

Figure

contains
the
and
Diagnostic

and

ROM's

at addresses 17773000 access to the EEPROM memory.

Programs which
and line clock
feature and to

byte

3-16
Boot

status,

Grant)

mode.

allows

the
and/or

allows

Mastership

Console

stand

BCSR

battery

(Processor

enable

The

Status

DIAGNOSTIC

CONTROLLER

FORMAT

FUNCTIONAL

TABLE
BOOT

AND

DIAGNOSTIC

DESCRIPTION

3-16

CONTROLLER

BIT

DESCRIPTIONS

Battery Backup Reboot Enable. When set, this
bit indicates that batterv backup failed to

maintain voltages to the memory system during the previous power failure. When this
bit is clear, it indicates that the system
does not feature battery backup, or that
battery backup maintained voltages during
the previous power failure. This signal is
received from backplane pin BH1l and latched
when

"1"

asserted.

"O".

Not

used

Could be a

FRC

LCIE

Force Line Clock Interrupt Enable. If this
bit is set, assertion of the signal selected
by BCSR <11,10> (Clock Select Bits 1 and 0)
will unconditionally request interrupts. If
FRC LCIE is clear, assertion of the selected
signal will request interrupts only if the
Line Clock Status Register bit <6> (LCIE)
is set under program control. FRC LCIE is
the

cleared by

DIS

LKS

negation of DCOK.

Line Clock Status Register Disable.
this

bit

set,

the

Line Clock

Status

Register (LKS) is disabled. If this bit
is clear, LKS is enabled and responds
to bus address 17777546. LKS DIS is
cleared by the negation of DCOK.
11
10

CLK SEL1
CLK SELZ2

Clock Select Bits 1 and 0. These two bits

select

the source of the

line clock

interrupt

request:

CLK SEL1

CLK SELO

Source of

Interrupt

0
1
0
1

External
On-Board
On-Board
On-Board

LTC Line
50 Hz
60 Hz
800 Hz

FUNCTIONAL DESCRIPTION
TABLE 3-16

ENB

HOB

(R/W)

(Cont)

Enable Halt on Break. When this bit is set, the
Console Serial Line Unit Halt on Break feature

is enabled. When this bit is clear the feature
is disabled. ENB HOB is cleared by the negation

of DCOK.
08

SA MODE
(R/W)

Stand-Alone Mode. When this bit is set, the
KDJ11-B operates in stand-alone mode, using its
Cache as main memory. External memory and
peripherals are all disabled. When SA MODE is
£, enabling
clear, Stand-Alone Mode is turned of
is set
MODE
SA
s.
heral
perip
and
external memory
by the negation of DCOK.

DIS 73
(R/W)

Disable 17773000. When this bit is set,

response of the 16-bit ROM memory to addresses
17773000 - 17773776 is disabled, allowing the
operation of an external ROM that uses those
addresses. When DIS 73 is clear, the 16-bit
ROMs respond to those addresses, using the
high byte of the page controcl register as the
most significant address bits. DIS 73 is
cleared by the negation of DCOK.

DIS 65
(R/W)

Disable 17765000. When this bit is set,

response of the Boot and Diagnostic 16-bit and
8-bit ROM memory to addresseS 17765000 17765776 is disabled, allows the operation of
external ROM which uses those addresses. When

DIS 65 is clear, the ROM memory selected by
BCSR <5> responds to those addresses, using the
low byte of the page control register as the
most significant address bits. DIS 65 is
cleared by the negation of DCOK.

RS3

(R/W)

ROM Socket 3 at 17765000. This bit selects
whether there is a 16-bit ROM in ROM sockets
one and two or there is an 8-bit ROM in ROM
socket three responds to addresses 17765000 17765776 (assuming that BCSR <4> is clear). If
RS3 65 is set, the 8-bit ROM is selected. If
RS3 65 is clear the 16-bit ROM is selected. In
either case, the low byte of the page control
register provides the most significant address
bits. RS3 65 is cleared by the negation of DCOK.
3-48

FUNCTIONAL

TABLE

D GNP I SED

P W T

D D VED D WD O S

(Cont)

IR GED IR CEP WD GES AP D WED G WYP GUD NI GED GNP WD GED WEP NS VRS NP D GED Gl

D GO GNP D CED GNP WL GH) GNP CED

D SUD WE CEN GED W

W WS G

ROM socket 3 Write Enable. If BCSR <6> (DIS 65)

RS3 WE

N W

3-16

DESCRIPTION

is clear, and if BCSR <5> and <4>

RS3 WE)

are both set,

(RS3 65 and

then the program can

write access ROM socket 3 which typically

contains an EEPROM. RS3 WE is cleared by Power

Up and by Bus

Initialize.

Unused

This bit always reads as "0".

02
01

PMG CNT2
PMG CNT1

Processor Mastership Grant Count bits 2, and
0. These three bits enable the PMG Counter and

PMG CNTO

select the length of time for PMG Counter

overflow. When enabled, the PMG Counter begins
counting when the KDJ11-BF must access an I/0O
Page

location or external memory.

overflow causes

Counter

the KDJ11-BF to suppress all

DMA Requests and give the processor bus

mastership during the next DMA arbitration
cycle. When the PMG Counter is disabled, the
processor is blocked from bus mastership as
long as DMA Requests are pending. All three
bits are cleared by the negation of DCOK.
PMG CNT2

PMG CNT1

PMG CNTO

Count Time

(Disabled)*

0
1
1
0
-0
1
1

0
0
0
1
1
1
1

1
0
1
0
1
0
1

0.4
0.8
1.6
3.2
6.4
12.8
25.6

usec
usec
usec
usec
usec
usec
usec

* The PMG count of 0 (Disabled) is not recommended
for most typical systems, and is reserved for
special

3.5.7

Page Control

applications.

a
1is
522,
777
17
addrress
at
Register,
Control
The Page
.
addressable
word
and
byte
both
is
that
register
read-write
the
3-17 contains
Figure 3-24 shows the register format:; Table
bit

descriptions.

FUNCTIONAL

DESCRIPTION

HIGH BYTE

FIGURE

3-24

LOW BYTE

PAGE CONTROL REGISTER FORMAT

TABLE 3-17 PAGE CONTROL REGISTER BIT DESCRIPTIONS

FUNCTION

BIT(S)

NAME

Not

14:09

High Byte
(R/W)
'

These six bits provide the most significant
ROM address bits when the 16-bit ROM sockets
are accessed by bus addresses 17773000 -

08:07

Not

Always

06:01

Low Byte
(R/W)

used

read

Always

zero.

17773776.

read

zeros.

These six bits provide the most significant
ROM (or EEPROM) address bits when the l6-bit
(or EEPROM)

or the 8-bit ROM

sockets are

accessed by bus addresses 17765000 - 17765776.

00
—— — S P

3.5.8

Not
AES P AR G

used

Always

R SR D M GO WS G MED GED R I YD D T

Line

read

) NS A G SR A GED WD GID TS G

Frequency Clock

zero.

D WP CEO R D W WD WD U

and Status

D M

I S

R ER SR GO SR GED GED WD GE GEG GMD T SUS MR mE m E S GO

The Line Clock provides the system
with
timing
information
at
determined by the UNIBUS LTC line or by the one
intervals
fixed
Boot
of the on-board KDJ1l1l-BF frequency signals as programmed by

and

Diagnostic

Controller

Status

bits

and

10,

Typically,
LTC
cycles
at
the
AC
1line
frequency,
producing
intervals
of
16.7
msec (60 Hz line) or 20.0 msec (50 Hz 1line).
The three on-board frequencies are 50 Hz, 60 Hz and 800 Hz.

The Clock Status Register

Clock
interrupts
to
be
control.
Alternatively,

(LKS),

at address 17777546,

enabled
line
3-50

allows Line

and
disabled
wunder
program
clock
interrupts
can
be

FUNCTIONAL

DESCRIPTION

unconditionally enabled by setting BCSR <13> (FRC LCIE).
Program
recognition of the Clock
Status
Register
can
be
disabled
by
setting BCSR <12> (LKS DIS).
The normal KDJ11l-BF configuration is FRC LCIE and
LKS
DIS
both
clear.
These
bits
are
set
up by the Boot and Diagnostic ROM

programs from -the KDJ11-BF Configuration Data.
Figure 3-25 shows
the register format; Table 3-18 contains the bit descriptions.

FIGURE

4-25

CLOCK

STATUS

FORMAT

TABLE 3-18 CLOCK STATUS REGISTER BIT DESCRIPTIONS

read

zero.

15:08

Unused.

Always

LCM
(R/W)

Line Clock Monitor. This bit is set by the
leading edge of the external BEVENT line (or
of one of the three on-board clock frequencies)
and by Bus Initialize. LCM is cleared
automatically on processor interrupts
acknowledge. It is also cleared by writes to
the LKS with bit <7> = "0".

LCIE
(R/W)

Line Clock Interrupt Enable -- This bit, when
set, causes the set condition of LCM (LKS <7>)
to

initiate

a program interrupt

request at a

priority level of 6. When LCIE is clear, line
clock interrupts are disabled. LCIE is cleared
by Power Up and by Bus INIT. LCIE is held set
INIT. LCIE is held set when BCSR <13> (FRC
LCIE)

05:00

Unused

Always

set.

read

zeros.

FUNCTIONAL

DESCRIPTION

3.6 STACK LIMIT PROTECTION

The KDJ11-BF checks kernel stack references against a fixedis limit
less
of 400(8). If the virtual address of the stack reference
the current
than 400(8), a yellow stack trap occurs at the end of
instruction.

stack
A stack trap can only occur in kernel mode ard only on a throug
h
nce
refere
5
or
4
mode
a
as
reference, which is defined
R6, or a JSR, trap, or interrupt stack push.

In addition, the J1l1 checks for kernel stack aborts during
of these
interrupt, trap, and abort seguences. I1f, during one initia
tes
sequences, a kernal stack push causes an abort, the Jller bit <2>,
a red zone stack trap by setting CPU Error Registr (R6) and
loading virtual address 4 into the kernel stack pointe PC and PS
trapping thru location 4 in kernel data space-. The old tively.
are saved in kernel data space locations 0 and 2 respec
NOTE

The J-11 treatment of yellow stack trap 1is
The 11/70 includes a
identical to the 11/44.
inclusive
stack limit register, and a more
Jll's
The
reference.
stack
of
definition
definition of a red stack trap is unigue.

3.7 KERNEL PROTECTION

In order to
interference,

mechanisms:

against
system
protect the kernel operating
ion
protect
ng
followi
the
rates
incorpo
BF
KDJ11lthe

In kernel mode, HALT, RESET, and SPL execute as specified.
In supervisor or user mode, HALT <causes a trap through
location 4, while RESET and SPL are treated as NOPs.

and

supervisor

All trap and interrupt vector references are

classified

Kernel stack references

In kernel mode, RTI and RTT can
<7:5>

freely.

<15:11>

alter

In supervisor or user mode, RTI and RTT can

only set PS <15:11> and cannot alter PS <7:5>.,

In kernel mode, MTPS can alter PS <7:5>.

user mode, MTPS cannot alter PS <7:5>.

irrespective of the memory man-=
references,
kernel space
trap or interrupt.
the
of
time
agement mode at the

are

checked

for

stack

overflow.

Supervisor and user stack references are not checked.
3-52

FUNCTIONAL

DESCRIPTION

3.8 TRAP AND INTERRUPT SERVICE PRIORITIES

In both traps and interrupts, the currently executing program 1is
which is
interrupted and a new program, the starting address ofed.
The
execut
is
,
specified by the trap or interrupt vector
is
V
vector
a
through
pts
hardware process for traps and interru
identical:

PS --> temp 1

lsave PS, PC in temporaries

0 --» PS <15:14>

| force kernel mode

M[V] --> PC
M[V+2] =-=-> PS
templ<15:14> --> PS<13:12>
SP-2 --> SP
templ --> M[SP]

ifetch PC from vector, data space
1 fetch PS from vector, data space
Iset previous mode
!selected by new PS
!push old PS on stack, data space

PC -->

SpP-2

temp

-->

tpush old PC on stack, data space

temp2 -=-> M[SP]

1go execute next instruction

NOTE

If an abort occurs during either the vector fetch
"or the stack push, the PS and PC are restored to
their original state (i.e. to the state prior to
trap sequence execution).

The priority order for traps and interrupts is as follows:
red

stack

address

trap

error

memory management violation
timeout/non-existent memory

parity error

trace (T-bit) trap
yellow stack trap
power fail
floating point
PIRQ

PIRQ

trap

interrupt level 7
interrupt level 6

interrupt level 5
interrupt level 4

PIRQ 3
PIRQ 2
PIRQ 1

halt

line

FUNCTIONAL

DESCRIPTION

NOTE

The halt line

is given highest priority when

processor hangs

3.9

CONSOLE

SERIAL

The console serial

-the

up.

LINE UNIT

line provides the KDJ11-BF

processor

with

The console serial
the console terminal.,
for
interface
serial
serial line is full duplex.
It provides an RS-423 EIA
interface

which

also RS-232C

compatible.

‘

This serial line interface is based on the DC319 Digital Link
For additional
(DLART).
Transmitter
Receiver
Asynchronous
1 under
Chapter
in
1listed
details refer to Chipkit handbook
additional

documents.

insure that the console serial receive and
The user should
identical and are determined by three
are
rates
baud
transmit
switches settings that are mounted on top of the KDJ11-BF Module,
via the external SLU distribution board and baud
or remotely,
rate switch. The switch settings should remain in the off
position.

settings
These switch settings, plus five additional switches
Facility
Diagnostic
and
Boot
the
via
read
(Switches 07-03) may be
and
Boot
the
on
a
is
07
switch
If
(BCR).
Configuration Register
Diagnostic

Programs

assumes

that

the

system

does not have a

console terminal and uses switches 06-00 to select a limited
Setting switch 07 does
range of KDJ11-BF and system parameters.
not disable the console terminal interface which runs at the baud
The settin of these switches,
reflected by switches 02-00.
rate
however, is determined by system configuration considerations.

the Receiver
There are four console serial line unit registers:
Status
Transmitter
the
Buffer,
Data
Receiver
Status Register, the
recognition
Program
Buffer.
Data
Transmitter
the
and
Register,
Each register is
these registers can not be disabled.
of
described

in the

following subsections.

3.9.1 Receiver Status Register

(at
Figure 3-26 shows the Receiver Status Register (RCSR) format
descriptions.
bit
the
contains
3-19
Table
address 17 777 560).

FUNCTIONAL

DESCRIPTION

RCV ACT ——J
AX DONE

RX IE

FIGURE

TABLE

15:12

3-19

3-26

RECEIVER

RECEIVER STATUS

Unused.

RCV ACT

(RO)

STATUS

Read

BIT

FORMAT

DESCRIPTIONS

zeros.

Receiver Active. This bit is set at the center
of the start bit of the serial input data and
is cleared at the expected center (per DLART
timing) of the stop bit at the end of the
serial data. RX DONE is set one bit time after
RCV ACT

cleared.

zeros.

10:08

Unused.

Read

Receiver Done.
This bit is set when an entire
character has been received and is ready to be
read from the RBUF register. This bit is
It
automatically cleared when RBUF is read.

DONE

(RO)

is
06

(R/W)

also cleared

Unused.

Power

Up.

Receiver Interrupt Enable. This bit is cleared
by Power Up and Bus INIT. If both RCVR DONE and
RCVR INT ENB are set a program interrupt is
requested.

05:00

Read

zeros.

FUNCTIONAL DESCRIPTION

3.9.2 Receiver Data Buffer

(RBUF) format
Figure 3-27 shows the Receiver Data Buffer register ins
the bit

777

ERR \ FRM

RCV

address

(at

descriptions.

OVR

conta

RECEIVED DATA BITS

BRK

ERR

3-20

Table

562).

ERR

FIGURE 3-27 RECEIVED DATA BUFFER REGISTER FORMAT
TABLE 3-20 RECEIVED DATA BUFFER REGISTER BIT DESCRIPTIONS

BIT(S)

NAME

ERR

(RO)

FUNCTION

Error.

This bit is set if RBUF <14> or <13> is

set. ERR is cleared if these two bits are

cleared. This bit cannot generate a program
interrupt.

14
13
NOTE:

OVR ERR
(RO)

Overrun Error. This bit is set if a previously
received character was not read before being

FRM ERR
(RO)

Framing Error. This bit is set if the present
character had no valid stop bit. This bit is

overwritten by the present character.

used to detect break.

Error conditions remain present until the next character
is received, at which point, the error bits are updated.
The Error bits are not necessarily cleared by Power Up.

Unused

‘This bit always reads as "0".

RCV BRK
(RO)

Received Break. This bit is set at the end of
a received character for the serial data input

10:08

Unused

These bits always read as "0".

07:00

Received

These read-only bits contain the last received

D -

Data Bits

D D W D D D T SN S DW

remained in the SPACE condition for all 11 bit
time. RCV BRK then remains set until the serial
data input returns to the MARK condition.

character.

G M T

D D S S D D TH S

- —— s D T CED D TD D A

A W P MU W TED N D GED M GHD AN SN WD w0 S e G e S

FUNCTIONAL

3.9.3

Transmitter

Status

DESCRIPTION

Figure 3-28 shows the Transmitter
(at
address
17
777
564).
descriptions.

Status
Table

MAINT

TX ROY

XMIT
BRK

FIGURE

TABLE

3-21

3-28

TRANSMIT

STATUS

BIT

FORMAT

DESCRIPTIONS

BIT(S)

NAME

FUNCTION

15:08

Unused

Read

TX RDY
(RO)

Transmitter Ready. This bit is cleared when
XBUF is loaded and sets when XBUF can receive

(R/W)

zeros.

another character. XMT RDY is set by Power Up
by

and

Bus

Transmitter

INIT.

Interrupt

Enable.

cleared by Power Up and by Bus

TX
is

RDY and TX
requested.

are

set,

INIT.

program

both

interrupt

05:03

Unused

Read

MAINT
(RO)

Maintenance. This bit is used to facilitate a
maintenance self-test. When MAINT is set, the
external serial input is disconnected and the
serial output is used as the serial input. This
bit is cleared by Power Up and by Bus INIT.

Unused

Read

XMIT BRK.

Transmit Break.

(R/W)

This bit

zeros.

zero.

serial output

XMIT BRK

When

this

bit

set,

the

forced to the SPACE CONDITION.

cleared

Power Up

and

by Bus

INIT.

FUNCTIONAL DESCRIPTION

3.9.4 Transmitter Data Buffer Register

Buffer Register (XBUF)
Figure 3-29 shows the Transmitter566.DataTable
3-22 contains the bit
17 777
format, at address:
descriptions.

XBUF

FIGURE 3-29 TRANSMITTER DATA BUFFER REGISTER FORM

IONS

TABLE 3-22 TRANSMITTER DATA BUFFER REGISTER BIT DESCRIPT
BIT(S)

NAME

FUNCION

15:08

Unused

Always read as zeros.

07:00

XBUF

These eight bits are used to load the

(WO)

transmited character.

3.9.5 Break Response

to
Unit may be configured either
The KDJ11-BF Console Serial Line
brea
a
when
onse
n or to have no resp e the processokr
perform a halt operatio
operation will caus
condition is received. A haltdebu
.
gging technique (ODT) microcodel
to halt and enter the octa
and
Boot
the
of
9
bit
selected via
The Halt on Break Option is us
During Power up oOr
Register.
Stat
er
roll
Cont
ic
Diagnost
will always set bit
ram
prog
nostic ROM
Restart, the boot and diag
k condition if the
Brea
on
Halt
the
9 to a 1. This will enableE position.
Keylock switch is in the ENABL

ved
tion at the end of a recei
The DLART recognizes a break condi
E
SPAC
the
in
ined
rema
character for which the serial. dataTheinput
1line
ion
gnit
Reco
Break
condition for all 11 bit times
t returns to the MARK
inpu
data
al
seri
the
l
unti
rted
remain asse
condition.

FUNCTIONAL

DESCRIPTION

3.10 KERNEL/SUPERVISOR/USER MODE DESCRIPTIONS

The PDP-11/84 processor family offers three modes
Kernel, Supervisor, and User.

execution,

Their use is to enhance the memory

and
flexibility
the
increase
to
protection scheme and
nts.
environme
g
ogrammin
multi-pr
and
ng
timeshari
of
functionality
Kernel mode is the most privileged of the three modes and

allows

In an operation system featuring
execution of any instruction.
is
system
multi-programming, the wultimate control of the
,
Typically
mode.
implemented in code that executes in Kernel
g
schedulin
job
s,
operation
I/O
this includes; control of physical
resource management.

and

Memory management mapping and protection allows these executive
elements to be protected from inadvertant or malicious tampering
If
by programs executing in the less privileged processor modes.
kernel
the
only
then
mode,
kernel
in
mapped
only
is
page
I/0
the
has access to the memory management registers to re-map or modify
the protection. This is because the memory management registers
themselves exist

in the I/O page.

In order for a user program to have sensitive functions performed
in its behalf, a request must be made of the executive program,
typically in the form of a software trap that vectors the

processor into kernel mode. Thus the executive code remains in
control and can verify that the function requested is consistent

with the operation of the system as a whole.

be
The supervisor mode is the next most privileged mode, and may
programs
of
execution
and
for the mapping
to provide
used

requiring protection from them.
shareable by users but still
s, logical I/O processors,
interpreter
This might include command
or

runtime

systems.

the
prohibits
and
mode
privileged
least
the
does
RESET as
HALT and
as
such
instructions
will
A multiprogramming operating system
Supervisor mode.
wuser programs to user mode to
of
execution
restrict
typically
prevent a single user from having & negative effect on the system
The user's virtual address space is set up such that
as a whole.
that
those
written are
be
the only areas of memory that can
as
protected
are
users
among
shared
Areas
that user.
to
belong
1is
User mode
of
execution

read-only,
3.11

PMG

execute only,

or for both read and execute access.

COUNTER

The PMG Counter enables the processor to become PMI master during

heavy

UNIBUS

DMA

activity.

This allows the processor to limit

To change
the hog mode control of the PMI during DMA activity.
setup
console
the
on
section
the
see
counter parameters
PMG
the
3-59

FUNCTIONAL DESCRIPTION

mode. The user can select from seven counter values and one
The PMG counter default setting is the Disabled mode,
disable.
The least PMG
with no DMA interruptions from the processcor.
mode, is
disable
counter timeout, with the exception of the
counter
PMG
selection 7. Selection 1 provides the, fastest
clock
of
number
per
timeout, most number of PMI interrupts
counter
PMG
eight
the
cycles. Table 3-24 provides a list of
selections.

Table 3-24 PMG COUNTER TIMEOUT LIST
Switch Pos.

Count Timeout

(Disabled)*

1
2

0.4 usec
0.8 usec

1.6

4
5

3.2
6.4

usec

usec
usec

12.8

usec

25.6

usec

* The PMG count of 0 (Disabled) is not recommended
for most typical systems, and is reserved for
special applications.

3.12 KTJ11-B CACHE OPERATIONS

The KTJ11-B DMA Cache is used to decrease PMI memory read access
The cache is divided into four
time for UNIBUS DMA devices.

sections, with each

section

capable

storing

eight

addresses.

The
Initially,the KTJ11-B cache is flushed (i.e., emptied).
device
DMA
UNIBUS
a
from
y
boundar
octal
an
on
first PMI read
causes the KTJ11l-B to read from memory and store that address and
the next 7 PMI address locations locations in section A. 1If the
next PMI read is one of the addresses stored 1in the cache, a
cache

hit

occurs.

If the next PMI read does not match any cache address (cache
miss), the KTJ1l-B does a memory read cycle for the requested
address - if that address is on an octal boundary - and the next
seven PMI memory addresses. These eight words are than stored in

-.the next available cache section (i.e., B, C or D).

DESCRIPTION

FUNCTIONAL

The KTJ11-B cache also monitors the

PMI

address

lines.

the KTJ11-B cache compares the
write into an address occurs,
When a match (hit)
address with it's stored cache addresses.
occurs the cache address location is invalidated.
3.12.1 KTJ11-B Cache Organization

The KTJ11-B DMA Cache contains thirty-two 16-bit data registers,
(A, B, C and D) of eight data registers
arranged in four sets
with each set is a Valid Bit and an
d
Associate
each (000-111).
The data registers are located in RAM
18-bit Tag Register.

memory as shown in Table 3-24.
located in the KTJ11-B
are
presented

in Figure

3-30.

The Tag Registers and Valid Bits
Refer to the format
Gate Array.

TABLE 3-24 RAM MEMORY DATA REGISTER LOCATIONS
RAM

Address

RAM

Address

00
01
02
03
04
05
06
07

Set A
Set A
Set A
Set A
Set A
Set A
Set A
Set A

20
21
22
23
24
25
26
27

Set C
Set C
Set C
Set C
Set C
Set C
Set C
Set C

10
11
12
13
14
15
16
17

Set B
Set B
Set B
Set B
Set B
Set B
Set B
Set B

O
1
2
3
4
5
6
7

30
31
32
33
34
35
36
37

Set D
Set D
Set D
Set D
Set D
Set D
Set D
Set D

——

TAG REGISTER

O
1
2
3
4
5
6
7

UNUSED

FIGURE 3-30 VALID BIT AND TAG REGISTER FORMAT (One of Four)
3-61

FUNCTIONAL

DESCRIPTION

physical
(or CPU)
DMA
the
interprets
The KTJ11-B DMA Cache
3-25
Table
and
register
the
1illustrates
3-31
Figure
address.
contains

the bit descriptions.

T TT LTI

—

I I T I T TITT]

TAG FIELD

)
INDEX
FIELD

BYTE
SELECTION

FIGURE

3-31

TABLE 3-25

PHYSICAL ADDRESS

UBA PHYSICAL ADDRESS

INTERPRETATION

21:04

Tag Field

These 18 bits comprise a field that corresponds
to the bits in the Tag Registers.

03:01

Index
Field

These three bits indicate if the address is on
an even eight-word boundary (index=0) and points
to one of eight data registers in a set (A-D).

Byte
Selection

Selects high or low byte write operations.
This bit has no effect during DMA operations.

3.12.2

DMA Cache

Enable/Disable

The KTJ11-B Memory Configuration Register
(KMCR)
(described
1in
subsection
3.13.3)
contains
both control and diagnostic status
bits

for

the

KTJ11-B

DMA

Cache.

When bit 06 of the KMCR is cleared, or
when
bit
05
of
Memory
Management
Register
3
is
<cleared
(i.e when the UNIBUS Map is
disabled), then the DMA Cache is disabled and initialized to
its
power
up
condition.
All four Valid Bits are cleared.
Set A is
the Next Available Set, followed by Set B, Sef: C, and Set D.
The
thirty-two
data
registers
and
the
four tag registers are not
cleared and contain random information.
3-62

FUNCTIONAL DESCRIPTION
Memory
and
06
When KTJ11-B Memory Configuration Register Dbit
is
Cache
DMA
the
set,
both
are
05
bit
3
Register
Management

enabled and operates as described in the
(See Figure

following

subsections.

physical

address

3-32.)

3.12.3 DMA Cache Write Operations

the

Dgring QPU and DMA write operations,

tag

bit for each
f;eld is checked against the Tag Register and Valid
Hit has
Cache
DMA
a
r
of the four Sets to determine whethe
caused
which
Set
the
then
d,
If a Cache Hit has occure
occur;ed.
is
Bit
Valid
its
and
Set
able
the hit becomes the Next Avail
cleared.

Otherwise, the DMA Cache is not affected.

MEMORY

UNIBUS

[

" onieus |
ggfics

MEMORY

MSV11-R

cru

UNIBUS

KDJ11-8

FIGURE 3-32 PDP-11/84 CACHE DIAGRAM

3.12.4 DMA Cache Read Operations

the
memory, the physical addrdess
During all DMA reads from PMI
for
bit
Vali
and
ster
Regi
nst the Tag
tag field 1is checked agai
has
Hit
e
Cach
DMA
a
her
whet
e
rmin
each of the four Sets to dete
ical address index field is checked for
occurred.

Also,

the phys

an even 8-word boundary (index

0).

and if the index field does
If a DMA Cache Hit has not occurre d,
essed memory location
not egqual

zero,

then the content of thee addr
is not affected.

is gated onto the UNIBUS.

The DMA Cach

if the index field
not occurred, and take
If a DMA Cache Hit has foll
place:
owing operations

equals zero, then the

ed 1into the Tag
ess Tag Field 1is load
1. The physical addrndin
g to the Next Available Set.
Register correspo
1is gated
2. The content of the addressed PMI memory location
onto the UNIBUS.

3-63

FUNCTIONAL

DESCRIPTION

The content of the addressed main memory location and of
the seven succeeding memory locations is stored in the data
registers of the Next Available Set.

If all eight data registers are successfully 1loaded, the
valid Bit corresponding to the Next Available Set is set
and that Set becomes the Least Available Set.

If a parity error occurs while reading one of the memory
locations, the corresponding Valid Bit is cleared and the
Set remains the Next Available Set.
NOTE

The KTJ11l-B contains no parity error indication.
Since the offending memory location is not stored
in the DMA Cache, the DMA device will receive any
and when it
if
indications
error
parity
n.
locatio
memory
that
s
accesse
specifically

If a DMA Cache Hit has occurred, then

the

following

operations

take place:

The Set (A-D) whose Tag Register caused the hit, along with
the physical address index field, selects a data register
whose contents is gated onto the UNIBUS.

If the Index Field equals 7 (the last cdata register in the
set has been read), the corresponding Valid Bit is cleared,
and that data register set becomes the Next Available Set.

If the Index Field does not equal 7, the Valid Bit remains
set, but the data register Set becomes the Least Available

Set.

3.13

UNIBUS MAPPING

The UNIBUS Map is the interface between the UNIBUS and PMI
It responds as a slave to UNIBUS signals and is used to
memory.
The
convert 18-bit UNIBUS addresses to 22-bit memory addresses.
signal
additional
an
by
d
accompanie
is
address
22-bit memory
line, BBS7 L. The assertion of BBS7 L disables the PMI address
decoding and selects the I/O Page.

UNIBUS address space is 256 KB of which the top 8KB addresses
always reference the I/0O page. The lower 248KB of UNIBUS address
space can be used by the UNIBUS map to reference physical memory.
(See

Figure

3-33.)

FUNCTIONAL DESCRIPTION

777 777
/0 PAGE .
(8K BYTES)
760 000

757 777

TO UNIBUS MAP
(248K BYTES)
000 000

18-8IT UNIBUS ADDRESSES

FIGURE 3-33 UNIBUS ADDRESS SPACE

gement Register
rammed, via Memory Manaled
The UNIBUS Map can be toprog
or relocation
run with relocation enab
Three (MMR3) bit 05,
disabled.
= 0), the UNIBUS Map
abled (MMR3 bit 05 bits
If relocation is dising
8) to the UNIBUS
=zeros (address memory21-1addr
appends four lead
ess. Memory
g the 22-bit
address, thus prod0ucin
bits 17-00.
ess
addr
US
identical to UNIB
address bits 17-0bits are
signal is
L
BBS7
the
,
3 are all ones
If memory address g the 17-1
'
I/O Page.
asserted, selectin
the UNIBUS Map
(MMR3 bit 05 = 1),
If relocation is enabled
select one of 31 mapping
ess Dbits 17-13 tocode
decodes UNIBUS addr
s 00 thru 36). UNIBThe
onding to octal er pair
register pairs (corresp
US
is added to
ist
cted mapping regmemo
content of the sele
US
UNIB
If
ess.
ry addr
uce the
address bits 12-00 3 toareprod
is
Page
1/0
the
37),
code
all ones (octal ry
address bits 17-1
ry
memo
,
rted
asse
1is
al to the memo
selected. The BBS7 L sign
tical to UNIBUS address bits 17-00 and
iden
are
0
17-0
address bits
are not asserted.
memory address bits 21-18

3.13.1 UNIBUS Mapping Registers

pairs of which only
32 mapping register on.
The UNIBUS Map contains
Figures 3-34
for address relocati ster Seepair
31 are actually e used
s may be
. The mapping regi
~and 3-35, and Tabl or 3-26
'
indirectly:
accessed directly

FUNCTIONAL DESCRIPTION

accessed
are
Direct Access - The mapping registers
Each
.
addresses
Page
I/O
their
through
individually
Register,
Address
Hi
a
of
consists
pair
mapping register
21-16 and a Lo
relocation address Dbits
which contains
address bits
n
relocatio
contains
which
Register,
Address
1 5-0 l ©

enabled,
1is
Indirect Access - When UNIBUS Map Relocation
UNIBUS address bits 17-13 select the appropriate mapping
18-bit UNIBUS
register pair to be used in relocating the
address.
15

0
]

;

RELOCATION ADDRESS
BITS 21-16

FIGURE 3-34 HI-ADDRESS REGISTER FORMAT
i5

0
Q

RELOCATION ADDRESS
BITS 15-01

FIGURE 3-35 LO-ADDRESS REGISTER FORMAT

TABLE 3-26 UNIBUS MAP REGISTER PAIRS

UNIBUS ADDRESSES
MAPPED VIA REGISTER

I/0 PAGE ADDRESSES
HI REGISTER
LO REGISTER

0
1
2
3

17
17
17
17

770
770
770
770

200
204
210
214

17
17
17
17

770
770
770
770

202
206
212
216

000
020
040
060

000
000
000
000

017
037
057
077

777
777
777
777

4
5
6
7

17
17
17
17

770
770
770
770

220
224
230
234

17
17
17
17

770
770
770
770

222
226
232
236

100
120
140
160

000 000 000 000 -

117
137
157
177

777
777
777
777

10
11

12
13

17 770 240
17 770 244

17 770 250
17 770 254

17 770 242
17 770 246

17 770 252
17 770 256

3266

PAIR

200 000 - 217 777
220 000 - 237 777

240 000 - 257 777
260 000 - 277 777

FUNCTIONAL

TABLE

3-26

DESCRIPTION

(Cont)

——<--————--—————-—-————---——-—-——————-——-———-————————-——'———-——

14
15
16
17

17 770
17 770
17 770
17 770

260
264
270
274

17
17
17
17

770 262
770 266
770 272
770 276

300 000
320 000
340 000
360 000

- 317
- 337
- 357
- 377

777
777
777
777

20
21

17
17

770
770

300
304

770
770

302
306

400
420

000
000

- 417
- 437

777
777

22
23

17 770 310
17 770 314

17
17

24
25
26
27

17
17
17
17

770
770
770
770

320
324
330
334

17
17
17
17

770
770
770
770

322
326
332
336

500
520
540
560

000
000
000
000

517
537
557
577

777
777
777
777

30
31
32
33

17
17
17
17

770
770
770
770

340
344
350
354

17
17
17
17

770
770
770
770

342
346
352
356

600
620
640
660

000
000
Q00
000

617
637
657
677

777
777
777
777

34
35
36
37 *

17
17
17
17

770
770
770
770

360
364
370
374

17
17
17
17

770
770
770
770

362
366
372
376

* Can be read or written into,

3.13.2

Optional

440 000 - 457 777
460 000 - 477 777

17 770 312
17 770 316

UNIBUS

700 000 720 000 740 000 1I1I/0 Page (No

717 777
737 777
757 777
Relocation)

but not used for mapping.

Memory

to install UNIBUS Memory instead of, or
The ability

addition

However, it differs somewhat
PMI memory, has been preserved.
to
assigned
UNIBUS address space is
from previous implementations.
memory in 8K byte segments, starting with the segment
UNIBUS
to

below the

I/O page and proceeding downward.

Those UNIBUS address

segments assigned

to UNIBUS Memory

can

not

Whenever the CPU
to access PMI memory via the I/O Map.
used
be
bv
memorv
PMT
disahle
will
KTJ1l-B
the
accesses UNIBUS memory,

asserting the PMI UBMEM signal. The KDJ11-B CPU Module does not
cache UNIBUS Memory, because it disables its cache when UBMEM is
asserted.

FUNCTIONAL

DESCRIPTION

NOTE

18-bit UNIBUS
PDP-11/84.

The

UNIBUS

memories

address

range

ONLY

are

each

supported

UNIBUS

the

memory

module

1is

determined
by
jumpers
or switches on that module.
The KTJ1ll-B
Memory Configuration Register
(KMCR),
described
1in
subsection
3.13.3,
within

must
accurately
system.

reflect

the

placement

UNIBUS

memory

the

The KMCR register is cleared by the assertion of
DC
loaded
by
the KDJ11l-B boot and diagnostic programs
by the KDJ11-B EEPROM Configuration Data.

LO
and
is
as specified

KMCR <04:00> specify the number of 8K byte address segments, from
0
to
31,
assigned
to
UNIBUS Memory.
KMCR <05> specifies the
location of the UNIBUS Memory from the viewpoint of the CPU.
See
Table
3-28.,
If KMCR <05> is clear (22-bit Mode), the top UNIBUS

memory location is 17 757 776.
If
KMCR
<05>
is
mode), the top UNIBUS memory location is 757 776.
If the system has no UNIBUS memory,
cleared.
1In this configuration:
l.

PMI memory, as seen
by
the
locations from 00 000 000 up

2.,

All

UNIBUS

DMA

devices

then

CPU,
to as

access

PMI

KMCR

set

<05:00>

(18-bit

must all

resides
1in
contiguous
high as 17 757 777.
memory

thru

the

UNIBUS

Map.

If the system contains UNIBUS memory only,
all be set.
1In this configuration:

UNIBUS memory,
‘locations

KMCR

resides
high

all UNIBUS DMA
from
address

<05:00> must

contiguous

757

777.

devices,
up to as

resides
high as

The UNIBUS Map
Register
Pairs
are
still
accessible
read-write
registers,
but
the UNIBUS Map is disabled
does not respond to the UNIBUS address
range
0
thru
777.

the

the CPU,
up

UNIBUS memory, as seen by
in
contiguous
1locations
address 757 777.

KMCR

as seen by

from address 0

then

system

<05>

UNIBUS

contains
clear

memory,

segments

both

(22-bit
as

assigned

PMI

seen

memory

mode),
by

3-68

UNIBUS

memory,

and

byte

then:

the

UNIBUS

and

as
and
757

CPU,

Memory

falls

within

KMCR

the

<04:00>.

UNIBUS

FUNCTIONAL

DESCRIPTION

Memory addresses are assigned downward starting with 8K
Table 3-28 lists the
byte segment 17 740 000 - 17 757 777.
KMCR bit
various
the
by
allocated
UNIBUS Address space
codes.

1in contiguous
resides
CPU,
the
PMI memory, as seen by
locations from address 00 000 000 up to as high as the last

KTJ11-B
The
address not assigned to UNIBUS memory.
residing
memory
the response of PMI
specifically disables
in locations assigned to UNIBUS memory by asserting the PMI

UNIBUS Memory

line

(PUBMEM).

section
the
The UNIBUS DMA devices access PMI memory thru
assigned
been
not
has
which
space
address
Map
UNIBUS
of the
UNIBUS
Each 8K byte segment assigned to
to UNIBUS memory.
Memory, disable its corresponding UNIBUS Map Register Pair.
read-write
as
accessible
still
are
pairs
Disabled
Map does not respond to their
UNIBUS
the
registers, but
assigned UNIBUS

address

space.

with
directly
The UNIBUS DMA devices access UNIBUS Memory
same
the
accesses
XXX
XXX
DMA Address
address.
18-bit
an
XXX.
XXX
17
address
CPU
by
accessed
UNIBUS Memory location
NOTE

of
number
the
on
1limit
The KTJ11-B places no
disabled by KMCR
be
may
which
pairs
register
software
system
typical
However,
<04:00>.
minimum of 5 or & register pairs to
a
requires
a
with
memory
PMI
allow DMA devices to access
'
moderate degree of efficiency.

If the system contains both PMI memory and UNIBUS memory, and

KMCR
1.

<05>

set

(18-bit mode),

1if

then:

UNIBUS memory, as seen by the CPU, falls within the 8K byte
UNIBUS
segments assigned to UNIBUS Memory by KMCR <04:00>.
8K
with
starting
downward
Memory addresses are assigned
the
lists
3-27
Table
777.
-- 757
000
740
segment
byte
UNIBUS Address space allocated
by
the
various
KMCR
bit
codes.

PMI memory
locations

as
seen
by
from
address

the
CPU,
resides
1in
000 000 up to as high

contiguous
as the last
address
not
assigned
to
UNIBUS
memory.
The
KTJ11-B
disables
the response of PMI memory residing in loca- tions
assigned to UNIBUS
memory
by
asserting
the
PMI
UNIBUS
Memory line (PUBMEM).

FUNCTIONAL

3‘

DESCRIPTION

PMI memory,

contiguous

locations

the last
this
1is
the

seen

the

UNIBUS

DMA devices,

from address

000

resides

to as

high as

address not assigned to
UNIBUS
memory.
Because
an 18-bit system, system software does not enable

UNIBUS

Map.

The UNIBUS DMA devices access UNIBUS Memory directly,
the same 18-bit addresses used by the CPU.
TABLE

3-27

UNIBUS

MEMORY

UNIBUS

KMCR
03

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

OKB
8KB
16KB
24KB
32KB
40KB
48KB
56KB

XX
XX
XX
XX
XX
XX
XX

740
720
700
660
640
620
600

000
000
000
000
000
000
000

XX
XX
XX
XX
XX
XX
XX

757
757
757
757
757
757
757

777
777
777
777
777
777
777

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

64KB
72KB
80KB
88KB
96KB
104KB
112KB
120KB

XX
XX
XX
XX
XX
XX
XX
XX

560
540
520
500
460
440
420
400

000
000
000
000
000
000
000
000

XX 757
XX 757
XX 757
XX 757
XX 757
XX 757
XX 757
XX 757

777
777
777
777
777
777
777
777

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

128KB
136KB
144KB
152KB

XX
XX
XX
XX

360
340
320
300

000 000 000 000 -

XX 757
XX 757
XX 757
XX 757

777
777
777
777

1
1
1
1

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

160KB
168KB
XX6KB
184KB

XX
XX
XX
XX

260
240
220
200

000
C00
000
€000

- XX 757
- XX 757
- XX 757
- XX 757

777
777
777
777

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

192KB
200KB
208KB
216KB
224KB
232KB
240KB
248KB

XX 160
XX 140
XX 120
XX 100
XX 060
XX 040
XX 020
XX 000

000
000
000
€000
000
000
000
000

- XX 757
- XX 757
- XX 757
- XX 757
- XX 757
- XX 757
- XX 757
- XX 757

777
777
777
777
777
777
777
777

(TR

eED

EED

aff

Bits
00

WED

GEN

GED

Memory
Size

GEd

GEb

GNP

GED

GWD

UNIBUS Memory
Address Range

GNP

GEP

GED

GEN GMN

VES

GED

GID

GED

GHL

GED

GAF

GND

VNS

WMD

TIO

FUNCTIONAL

DESCRIPTION

NOTE

for

3.13.3

The
777

for

KMCR

Memory

KMCR

<05>

"1"

Configuration

KTJ11-B Memory
734,
allows

"0"

(18-bit

(22-bit

mode)

Configuration Register (KMCR), at
the
KDJ11l-B
Boot
and Diagnostic

address

17
to

programs

configure the KTJ1l1l-B for the
memory
within
the
system.

distribution
of
UNIBUS
and
Main
Additional KMCR bits allow the DMA
Cache to be enabled and disabled, provide
diagnostic
status
of
the
Read
Buffer
and
provide
information on the system reboot
status.
Figure 3-36 shows the register format,
and
Table
3-28
contains the bit descriptions.

OMA CACHE
STATUS BITS

SELECT STATUS —
RBT PLS

CA ENB
18-8IT MODE

UNIBUS MEMORY SIZE

FIGURE 3-36 MEMORY CONFIGURATION REGISTER (KMCR)

TABLE

BIT(S)

15:09

3-28

MEMORY

CONFIGURATION

NAME

DMA

BIT

DESCRIPTIONS

FUNCTION

Cache

Status
(RO)

Bits

These

DMA
The

seven

bits

reflect

the

Cache. KMCR <15> is DMA
content of KMCR <14:09>

value

the

value

the

status

the

Cache Hit.
depends upon

KMCR

<08>

the

(Status

Select).
08

Status

(R/W)

Select

This

bit

selects

(See Tables

the

3-29 and

content

3-30.)

KMCR

<15-09>.

FUNCTIONAL DESCRIPTION

TABLE

Reboot Pulse
(RBT PLS)
(RO)

3-28

(Cont)

This bit is set by the front panel reboot pulse
,
which also generates a KTJ1ll-B Power
by
cleared
not
is
PLS
Down/Power Up Cycle. RBT
Power
KTJ11-B
the
during
the assertion of DC LO
Down/Power UP cycle initiated by the front
panel reboot pulse, but it is cleared by any
other DC LO assertion.

Cache Enable
(CA ENB)
(R/W)

18-Bit Mode
(R/W)

This bit, when set, enables the DMA Cache.

When CA ENB is clear, the DMA Cache
is disabled. CA ENB is cleared by the assertion
of

LO.

When this bit is set, the CPU can access UNIBUS
Memory only when address bits <21:18> = 00.
When this bit is clear, they can access UNIBUS
memory if address bits <21:18> = 17. This bit
is cleared by the assertion of DC LO. Write
access to this bit is disabled when DCSR <08>
(Diagnostic Mode)

04:00 UNIBUS Memory
Size

clear.

If the system contains main memory only (no
UNIBUS memory), these five bits, as well as

KMCR <05>, must be cleared.

If the system

contains UNIBUS memory only (no main memory),
then KMCR <05:00> must be

set.

If the system contains both main memory and
UNIBUS memory, KMCR <04:00> indicate the
number of 8K byte address segments assigned to
UNIBUS memory. As described in section 3.4,
UNIBUS memory is assigned downward, starting

with the segment below the I/O Page. These bits
are cleared by assertion of DC LO. Write access
to these bits is disabled when DCSR <08>
(Diagnostic Mode)

is clear.

_—n—u

s_@m-.‘m-‘a——-—--—
o OO D T - D D e D S W _—‘-’-——‘———-——-——--—--———m-n—:——:@-

If KMCR <8> (Status Select = 0, then KMCR <15-08> contain the DMA
2-bit Most Recently Used Set code, and the
the
Cache Hit bit,
four Valid bits. Figure 3-37 shows the field format; Table 3-29
contains

the bit descriptions.

FUNCTIONAL

DESCRIPTION

DMA CACHE BIT
UNUSED
SET A VALID
SET B VALID
SET

C VALID

SET D VALID

STATUS

FIGURE

TABLE

BIT(S)

SELECT

3-37

3-29

STATUS

SELECT

SELECT=0

FIELD

FORMAT

DESCRIPTION

NAME

FUNCTION

DMA Cache
Hit

This bit is updated during all writes to main
memory, and all reads from main memory. It is
set if a cache hit is detected, and cleared
if a cache miss is detected. This bit is
cleared when KMCR <6> 1is clear.

14-13

Unused

Always

Set A Valid

read

Reflects the current status of the Valid bit
corresponding
when KMCR <6>

Set

Valid

zero.

Reflects

the

corresponding
when KMCR <6>

to Set A.
is clear.
current

The

status

to Set B.
is clear.

The

bit

the

bit

cleared

Valid

Set

Valid

Reflects the current status
corresponding to Set C. The
when KMCR <6> is clear.

of the
bit ic

Valid

Set

Valid

Reflects

the

Valid

bit

the

corresponding
when KMCR <6>

If
as
of

current

status

to Set D.
is clear.

The

bit

cleared

bit
cleared

bit

cleared

KMCR 8> = 1, then KMCR <15-08> contain the DMA Cache Hit
bit
well as the six bits which determine the relative availability
the four sets (i.e., A, B, C, D).
3-73

FUNCTIONAL DESCRIPTION

is disabled, and
is clear, the DMA cache Set
When KMCR <6> (CA ENB) lity
A is the Next
are set.
the six Set Availabi by Setbits
D.
Set
B, Set C, and
Available Set, followed
e
e is enabled. If a DMAwritcach
When KMCR <6> is set, the ofDMAthecach
to
e
sets during a CPU or DMA
hit is detected for one
Set.
lble
Avai
Next
the
memory, then that set becomes

during a DMA
cted for one of the sets
1f a DMA cache hit is dete
t Available
Leas
set becomes the
read from main memory, them sthat
data registers are successfully

set'
Set. Similarly, if DMAa read
cache miss, then that set becomes the
a
g
owin
foll
ed
joad
Least Available Set.
the Dbit
Figure 3-38 shows the field format; Table 3-30 contains
descriptions.

A TOPS B

A TOPS C
A TOPS

B TOPS C
B TOPS

C TOPS

STATUS SELECT

FIGURE 3-38 SELECT STATUS = 1 FIELD FORMAT

TABLE 3-30 SELECT STATUS = 1 FIELD DESCRIPTION
-——-—————————;—-—————-——-——-_—p

———————--n——_—n-m—a——_n—-—————_————————————.-

w—fl—_---—‘-—G——-—Qafiu-fl

-—--———-‘—“‘w——--_--———--——_———-—-_—--—-—c—‘-

DMA Cache Hit

This bit is updated during all writes to main

memory, and all DMA reads from main memory. It
is set if a cache hit is detected, and cleared
if a cache miss is detected. The bit is cleared
when KMCR <6>

- ——— - D A IR D D (e D @D N I S A

S GRS D e Gy S

D IR G S G

is clear.

O S D D G GO 70 SN O

D O

B G O

D D G G WD S G YER G

e G

IO CHP O GOR EA O MO 6O

FUNCTIONAL

TABLE

Tops B
(ATPSB)

ATPSB

Set

3-30

set,

ATPSB

(Cont)

Set

DESCRIPTION

clear,

available

Set

than

available

than
when

Set A. ATPSB is set when KMCR <6> is clear,
Set A becomes the Next Available Set,
and when Set B becomes the Least Available Set.
ATPSB is cleared when Set B becomes the Next
Available Set, and when Set A becomes the Least
Available
13

A Tops C
(ATPSC)

A Tops

(ATPSD)

Set.

ATPSC

ATPSD

Set

Tops C
(BTPSC)

Set

ATPSD

Set

becomes

Tops

(BTPSD)

BTPSC

when

Set

and

when
is

Available
Available
C

Tops

(CTPSD)

available

than

clear,

set

the

Set

when

available
D

KMCR

<6>

Available

than
available

clear,

Set,

Set D becomes the Least Available Set.
cleared when Set D becomes the Next
Set,
Set.
is

and

set,

when

Set

becomes

Set

cleared

Set,
Set.

the

becomes
when

the
Set

and when

becomes

the

available

C is
KMCR

Least

than

more available
<6> is clear,

Available

Set,

Least Available
C

Set

becomes

the

becomes

Set.

the

Least

If BTPSD is set, Set B is more available than
Set D. If BTPSD is clear, Set D is more available
than Set B. BTPSD is set when KMCR <6> is clear,
when Set B becomes the Next Available Set,
and when
BTPSD is

Set C. If BTPSC is clear, Set
than Set B. BTPSC is set when

Available
Available
B

Set
is

than

BTPSC

set,

ATPSD

Available
Available
B

Set

when

and when
ATPSD is

set,

Set C. If ATPSC is clear, Set C is more available
than Set A. ATPSC is set when KMCR <6> is clear,
when Set A becomes the Next Available Set,
and when Set C becomes the Least Available Set.
ATPSC is cleared when Set C becomes the Next
Available Set, and when Set A becomes the Least
Available Set.

CTPSD

Set

than
when

Set
Set

Set D becomes the Least Available Set.
cleared when Set D becomes the Next

Set,
Set.
is

and

set,

CTPSD

when

Set
is

Set

clear,

becomes

more
Set

the

available
D

Least

than
available

C. CTPSD is set when KMCR <6> is clear,
C becomes the Next Available Set,

and when Set D becomes the Least Available Set.
CTPSD is cleared when Set D becomes the Next
Available Set, and when Set C becomes the Least
Available Set.

FUNCTIONAL DESCRIPTION

AND

DIAGNOSTIC

KTJ11-B

3.14

CONFIGURATION

REGISTERS

KTJ11-B Diagnostic and Configuration Registers are used with
tic
diagnostic programs to check out the KTJ11-B, both in Diagnos
stic
Diagno
and
Boot
KDJ11-B
The
d.
disable
UNIBUS
Mode, with the
Programs also use these registers to enable or disable the
KTJ11-B DMA Cache and to specify the presence and location of
UNIBUS

memory.

When operating in diagnostic mode, the KTJ11-B can be programmed
to perform diagnostic NPR cycles which test out its address and
data paths along with the UNIBUS Map.

3.14.1 Diagnostic Controller Status Register

Diagnostic Programs use the Diagnostic Controller Status Register
(DCSR), at address 17 777 730, to enter and to exit from
Diagnostic Mode, to select the source of the Diagnostic Data
Register (DDR) and to perform Diagnostic NPR cycles which test
the UNIBUS Map along with the KTJ11l-B address and data paths.
Figure 3-39 shows the register format; Table 3~31 contains the
bit descriptions.

|
DATI GO

DONXM ERR
DIAGNOSTIC MODE
DNPR DONE

BOOT ROM OIS

DOR SELECT

FIGURE 3-39 DIAGNOSTIC CONTROLLER STATUS REGISTER FORMAT
TABLE 3-31 DIAGNOSTIC CONTROLLER STATUS REGISTER BIT DESCRIPTIONS

DNXM ERR

Diagnostic Non-Existant Memory Error register.

This bit is cleared at the start of a
diagnostic NPR cycle and set if there is a
non-existant memory timeout during that cycle.
DNXM ERR is also cleared when DCSR <08>
(Diagnostic Mode)

cleared.

FUNCTIONAL

TABLE

3-31

DESCRIPTION

(Cont)

--—-———-—————-—--—————

—————-—-————-——.——————

——————-——-——-——————-——

Unused

These

Diagnostic

When

Mode

(R/W)

bits

always

Done

This

bit

NPR

cycles

the

DNPR

Done

Diagnostic

Boot

When

bits

ROM

this

Select

(WO)

3.14.2

Diagnostic

are

Done

"1"

no
is

bit

Diagnostic
cleared

00,

and

Data

INIT

Bus

any

(DDR).

completion

the

NPR Cycle.

read

zero.

set,

response

UBA

When

this

the

bit

those

cleared,

addresses.

assertion

the

UBA

boot

This

bit

LO.

The

DDR

Select

bits

are

the

cleared

INIT.

Writing a "1" into this bit sets up a
Diagnostic Data-In NPR Cycle and clears DCSR
bit 07. The NPR cycle is actually initiated by
the next CPU read cycle which accesses the PMI.
That cycle provides the address used in the NPR
cycle. The data fetched during that cycle is
loaded into the Diagnostic Data Reglster (DDR)
.

Data

Programs use the
777 732, along

Diagnostic Data
Register
(DDR),
at
with the Diagnostic Controller Status
(DCSR), to perform Diagnostic NPR cycles and to
monitor
state of various UNIBUS data, .address and control signals.

address
Register

the

there
DNPR

set

bit

operations.

DATI

for normal
assertion of

the

These two bits select the contents of
Diagnostic Data Register during read
Bus

configured

Diagnostic

always

responds

cleared

(R/W)

set

boot ROM at addresses 177773000 - 177773776
is disabled, allowing operation of any
external ROM which uses those addresses on the
UNIBUS.

DDR

set when

write

These

02:01

pending.

DCSR with

Unused

(R/W)

06:04

ROM

KTJ11-B

bit

LO.

write

Disable

zero.

this bit is set, the UNIBUS is disabled
the KTJll-B is configured for Diagnostic
Mode. When this bit is clear, the UNIBUS is

DNPR

and

enabled and the
operation. This

read

3-77

FUNCTIONAL

DESCRIPTION

Diagnostic

NPR

cycles

test

out

the

UNIBUS

Map

along

with

many

the
KTJ1l1l-B
address
and
data
paths.
During
Diagnostic
cycles, DCSR <02:01> are set
egual
to
0,
thus
selecting
Diagnostic
NPR
Register.
Following
a
Diagnostic Data-In

NPR
the
NPR
Cycle, the Diagnostic NPR Register contains the transferred
data
which
can then be read through the DDR.
Diagnostic programs set
up a Diagnostic Data-Out NPR cycle by
writing
the
data
to
be
transferred into the DDR.
Figure 3-40 shows the register format;
Table 3-32 contains the bit descriptions.
All

writes to the DDR access
information
accessed during
on DCSR <02:01>.
14

o1 { o | o1 | on

the Diagnostic
read operations

o1 | o1 | on

0/1

NPR

L_I

Al6

AV7

a
PB

SSYN
MSYN

FIGURE 3-40 DIAGNOSTIC DATA REGISTER FORMAT

Cdntents of the DDR when Select Code = 11
TABLE 3-32 DIAGNOSTIC DATA REGISTER CONTENT DESCRIPTIONS

" DDR SELECT BITS

CONTENT OF DIAGNOSTIC DATA REGISTER

Bit 02

Bit 01

Diagnostic NPR Register

UNIBUS Data Lines D15-00

UNIBUS Address Lines Al5-00%*

UNIBUS Address Lines Al7-16

and various UNIBUS Control Lines

* NOTE: Asserted address line Al6 during the Diagnostic
UNIBUS Address Lines read operation,
a parity error abort.
3-78

may cause

FUNCTIONAL

3.14.3

DESCRIPTION

Diagnostic DATI NPR Cycles

The execution procedure for diagnostic DATI cycles is as follows:
Diagnostic

mode

with

The KTJ11l-B must be running in

The diagnostic program writes a 1 into DCSR bit 00.

Select bits

(DCSR 02-01)

= O.

DDR

NOTE

At this point,

PMI

bus

I/0

page

any UNIBUS memory read access,

read or write access results in a

timeout.

The diagnostic program writes the test data pattern into
The KTJ11l-B latches address
the target memory location.
bits Al17-00 of this cycle.

The KTJ11-B then executes its diagnostic DATI NPR cycle,
storing the fetched data in the Diagnostic Data register.
The address used in this cycle in produced by the UNIBUS
The 18-bit address
using the latched 18-bit address.
Map,
may be used directly (UNIBUS Map Relocation disabled) or it
may be relocated to produce a 22-bit address (UNIBUS Map
.
enabled)

The diagnostic program verifies that
register contains the correct data.

the

Data

Diagnostic

3.14.4 Diagnostic DATO NPR Cycles

The execution procedure for diagnostic

DATO

NPR

cycles

follows:

The KTJ11-B must be running in Diagnostic mode.

The diagnostic program loads the data

into

the

Diagnostic Data register.

NPR cycle
the
for
Loading this register

primes the KTJ11-B for a diagnostic NPR cycle.
NOTE

At this point,

non

a bus

any UNIBUS memory read access,

PMI I/O page read or write access results in
timeout.

3-79

FUNCTIONAL

DESCRIPTION

The KTJ11-B latches
KDJ11-B

external

address

write

bits

to memory

Al7-00

address

from

space.

the

The KTJ11-B then executes its diagnostic
DATO
NPR
cycle,
The
using the data stored in the Diagnostic Data register.
Map,
UNIBUS
address.used in this cycle is produced by the
using

the

latched

18-bit address.

The diagnostic program

verifies

The

that

the

target

memory

If it wishes to check
contains the correct data.
location
before
so
do
must
it
register,
Data
Diagnostic
the
alter
would
which
operation
write
external
an
performing
the contents

that

CHAPTER
BOOTSTRAP

4.1

INTRODUCTION

The

CPU

contains

programs (ROM
up or restart

various
changed
The

two

AND

ROMs

DIAGNOSTIC

(read

ROM

PROGRAMMING

only memories)

which

also

data

contains

the

ROMs

EEPROM

permanent

to
be taken
registers are

Parameters

program
in
reguire the
can also be

the
user
used

the

power up or restart,
be configured.

EEPROM

can

and

the

cannot

(electrically

programmable
read
only
memory).
The
EEPROM is
parameters which the ROM program uses to determine
are
UBA

stores

code) used to test the CPU, UBA and memory at power
and to allow the starting of the user's software on

devices.
The
by the user.

CPU

and

changed

how

under

eraseable

used
what

to store
actions

various

CPU

control

and

ROM
called
Setup
mode.
Setup mode does not
to remove the CPU or UBA
modules.
The
EEPROM
to store customer bootstrap programs.

The diagnostic ROM program is automatically started
by
the
CPU
each
time
the
system
1is powered up or restarted by use of the
RESTART switch on the front panel.
The
ROM
program
will
run
tests
selected
by
parameters
1in the EEPROM.
After testing is
complete, parameters in the EEPROM
taken next by the ROM program.
In

typical

example

the

starts
a program from
referred to as booting

ROM

determine

program

what

action

automatically

After the user's software
entered again
wuntil
the

some

cases

after

testing

complete

4-1

the

ROM

program

1loads

the user’'s disk or tape.
This is
a program and this mode will
be

to
as automatic boot mode.
the ROM program will not be
powered up or restarted.

and

commonly
referred

is started
system
|is

enters

BOOTSTRAP

mode

AND

which

way

DIAGNOSTIC

allows
of

the

ROM

PROGRAMMING

user

keyboard

select

commands

what

action

entered

through

the

taken

console

terminal.

This
mode
will
be
refered to as Dialog mode.
the EEPROM determine
the
tests
to
be
run,
general
mode
to
be
entered
after testing is complete and
final configuration of certain
registers
on
the
CPU
and
parameters

module

'In
the

before

the

system

cases

the

ROM program enters

some

The
the
the
UBA

selections

the

software

EEPROM.

This

started.

Dialog
occurs

mode
if

regardless

the

user

types

of
CTRL

'C at the console terminal during testing, or the
boot
sequence,
or anytime the FORCE DIALOG switch is turned on.
Generally, this
is done by the user to allow changes to be made to the parameters

in
not

the
EEPROM,
or to
previously selected

The

FORCE

DIALOG

allow the user
by the EEPROM.

switch

allows

to boot

wuser

the

device

which

was

wunconditionally

override the selections in the EEPROM.
This override is provided
because there are certain modes which cannot be
aborted
because
the ROM program executes the modes too gquickly and is not able to
monitor the console terminal for a CTRL C typed by the user.

NOTE

All

user input is ignored at the console keyboard
until
the
"Testing
1in
progress - Please wait"
message is typed out by the ROM code.

The

description

the

commands

for

the

ROM code

assume

that

the

EPROMs
installed
are at Version 7.0 (V7.0).
Earlier PDP-11/84s
contain EPROMS with V6.0 ROM code.
The version of the
ROM
code
is typed out each time Setup mode is enetred from Dialog mode and
is displayed at the upper right corner of the
printout.
It
1is
not

necessary

version number.
version numbers.
Socket

Location

(M8190)

CPU

E116

(low

E117

(high

Differences

Appendix
The

the

CPU

following

Part

byte)

between

V7.0

module

lists

the

Number

V7.0

determine

ROM

part

Part

the

ROM

code

numbers

and

Number

V6.0

23-116E5-00

23-077E5-00

23-117E5-00

23-078E5-00

and

V6.0

ROM

code

are

described

1in

following

program

remove

The

illustrations

would

restarting

out

the

CPU.

are
the

examples
console

messages

terminal

during

the
power

ROM
up

BOOTSTRAP AND DIAGNOSTIC

ROM

PROGRAMMING

Figure 4-1 shows an example of a typical
system
booting
automatic
boot
mode.
In this case the user's software

and was booted

from device

DU unit

wup
1in
is RTI11

in progress - Please wait

Testing

Memory Size is 1024 K Bytes
9 Step memory test
Step 1 2 3 456 789

Starting

automatic boot

Starting

system

RT-11FB

(S)

from

DUO

V05.0

FIGURE

4-1

AUTOMATIC

BOOT

MODE

EXAMPLE

The messages that follow the line "Starting system from DUQ" come
by the ROM
generated
not
are
and
booted
software
the
from
all
At this point the ROM program is not executing and
program.
actions

are determined by

the

user's

Figure 4-2 shows an example of

software.

typical

system

powering

up,

running
the
internal diagnostics and then entering dialog mode.
to
1is
action
The ROM program waits for the user to select what
occur

next.

Testing in progress - Please
Memory Size is 1024 K Bytes
9

Step memory

Step

test

456

wait

Commands are Help, Boot, List, Setup, Map and
Type a command then press the RETURN Kkey:

FIGURE

4.2

DIALOG MODE

Dialog mode

4-2

SYSTEM

COMMAND

allows

the

POWERUP

DESCRIPTIONS
user

to:

DIALOG

MODE

Test.

EXAMPLE

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
a.

Boot a device

List boot programs available for the user

Execute ROM resident tests

Provide a map of all memory and I/O page locations

Enter setup mode.

When dialog mode is entered the ROM program prints out the
message shown in Figure 4-3 at the console terminal and waits for
the user to select a command.

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key:
FIGURE 4-3

DIALOG MODE COMMANDS

when dialog mode is entered the user has six commands
The

from.

choose

six commands are listed in the command line for user

convenience. The user may obtain a brief description of each
command by typing H followed by pressing the RETURN key or by
typing

only.

All of the commands may be executed by typing only the first
letter of the command followed by pressing the RETURN key. For
example, the Map command can be invoked by typing either M or Ma
or Map followed by pressing the RETURN key. On input all lower
case letters are converted to upper case and leading spaces and
tabs are

ignored.

If
Use the DELETE key to delete the previous character typed.
code
ROM
the
video
is
EEPROM
the
in
on
the terminal type selecti
will erase the previous character on the screen when the DELETE
key is depressed. If the terminal type is hardcopy the ROM code
The
will use slashes "/" to identify all deleted characters.
typing
by
user may at any time delete the entire command line
CONTROL

(CTRL)

NOTE

Typing a CTRL U
depressing the

(or CTRL
CTRL key

depressing the CTRL U (or R)

is performed by
R)
while simultaneously
key.

The user can also type CTRL R which will retype the command line.
4-4

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
CTRL
R
1is
normally
used when the terminal type is hardcopy to
clear up command lines where the DELETE key has been
wused.
For
both CTRL R and CTRL U the ROM code will print out a short prompt
first.
Figure 4-4 shows
an
example
of
CTRL
U
being
typed.

Neither
shows

CTRL

U or CTRL R is echoed by the ROM code.

an example of CTRL R use.

Figure 4-5
)

NOTE

following

the

user inputs

All

examples

are

examples

and

underlined.

The

RETURN

text

key

specified

the

<CR>.

Commands are Help, Boot, List, Setup, Map
Type a command then press the RETURN key:
KDJ11-B

and Test.
B DX5 CTRL U

FIGURE

4-4

CONTROL

EXAMPLE

Figure 4-4 shows an example of CTRL U being typed to clear up the

command

line

selection

Commands

without

are

Help,

Type a command
KDJ11-B

retyping

all

1it.

The

terminal

type

hardcopy.

Boot,

List,

then press

the

Setup,

Map and

RETURN key:

Test.

B DX/X/Ul

CTRL R

DUl

FIGURE

4-5

CTRL

EXAMPLE

Input is limited to 16 characters and spaces.
There are no cases
where any of the commands would need more than 16 characters.
1If
the user types more than 16 characters the ROM code
will
delete
all
of
the
input
and
retype
the KDJ11-B prompt and wait for

input.

Figure 4-6

character

Commands
Type

KDJ11-B

shows an an example.

equivalent

are

Help,

command

Boot,

then press

typing

CTRL

List,

Setup,

the

RETURN

Typing

Map
key:

and

the

Test.

12345678901234567

FIGURE

4-6

CTRL

EQUIVALENT EXAMPLE

4-5

seventeenth

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
The ROM code will

ignore

character,
or
the
printable character
echoed

Note

that

code

any

space

tab

typed

second tab or space typed
in between.
All tabs are

prior

in a row without a
converted
to
and

spaces.

these

rules

accepting

also

input

If
be

an invalid
typed out

input is
and more

example

Commands
Type

are

Invalid

entry

Commands

are

Type

any

time -the

ROM

user.

will
shows

entry.

Help,

Boot,

then

Help,

command

the

received an "invalid entry"
message
input will be requested.
Figure 4-7

invalid

command

apply generally

from

List,

Setup,

Map

and

the

RETURN

key:

List,

Setup,

Map

and

the

RETURN

key:

press

Boot,

then

press

Test.
<CR>

Test.

FIGURE 4~-7 INVALID ENTRY EXAMPLE

4.2.1 Help Command
This

command

commands.
typing ?
command.

types

out

brief

description

all

available

It
can
be
executed
by either typing H <CR>,
only.
Dialog mode is restarted
at
the
end
of
Figure
4-8 shows an example of the Help command

or by
this
being

executed.

Commands
Type

are

Help,

command

Boot,

then

Command

Description

Help
Boot

Type
Load

and

List

boot

Setup

Enter

Map
Test

Map memory
Continuous

Commands
Type

are

this

the

Setup,

Map

RETURN

key:

message
a program

start

from

and
H

Test.

<CR>

device

programs

Setup mode

Help,

command

List,

press

then

and I/O page
self test - Type

Boot,

List,

press

the

Setup,
RETURN

CTRL

Map
key:

FIGURE 4-8 HELP COMMAND DISPLAY
4-6

and

exit

Test.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
Boot

4.2.2

Command

This command allows a device to

bootstrapped.

The

command

If the device
arguments are the device name and the unit number.
it. If the
for
user
the
prompt
will
name is left off the program

1left off the program assumes that unit” zero was

1is

number

unit

desired. The unit number ranges from 0 0 to 255(10) depending on
The device name is a one or two
the device and the boot program.
In most cases the
letter mnemonic which describes the device.
device

name

two

letters.

and
when typing the Boot command the user may either type B <CR>
or
switches,
optional
then type the device name, unit number and

type B followed by a space and then type the

number and optional

device

name,

unit

switches.

The three optional switches used with the boot command are:

/A Request to allow the user to type in a non standard

CSR

for

unit

address

for the controller.

/0 The unit number is octal instead
numbers greater

than

decimal

/U If the boot exists in the base ROM and also on the UBA,
the base ROM boot and use the boot from the UBA
override
board or M9312 module.

The format when using a switch is to type the device name and
unit number followed by / and the switches. When there is more
than one switch,

use only one slash.

When the user types the Boot command without an argument, the ROM
code will prompt the user for additional information with the
following message:

Enter device name and unit number then press the RETURN key:

the ROM code would 1list the
At this point if the user typed ?
boot programs available and then retype the "enter device name
and unit number" message and wait for a selection.

Wwhen the ROM code has a device name it searches for the first
boot program with the same device name. The ROM code looks for
matches in the following order. The /U switch effectively tells
the ROM code not to look for the device name in the EEPROM or the

CPU ROM, but go directly to the UBA ROMs or the M9312

present.

lst area
2nd

to search

area to

EEPROM

CPU ROM code
4-7

module

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
area

3rd

to search =

UBA module

if present

4th area to search = M9312 module

boot
any
first,
searched
Note that since the EEPROM is always
as a
-name
device
same
the
with
EEPROM
the
into
1loaded
1is
that
This
boot.
that
replace
boot in the CPU ROM will effectively
replace a CPU ROM boot by
effectively
to
user
a
allow
would

boot

the

EEPROM with

the

same

name.

Table 4-1 describes how the ROM code interprets user input.
TABLE

USER

4-1

ROM

CODE

ACTION

ROM CODE ACTION

INPUT

5oL Boot DLO
B DL

Boot DLI

B DUS8

Boot DU unit 8

B DU10/0

Boot DU unit 8

B DU1O /A
Address = 17760400

Boot DUl1l0 with non standard CSR
address of 17760400

B DU 3/U

Boot DU3 using UBA or M9312

B DU1l1l/UO

Boot DU unit number 9 using UBA or

B DU 10:

Boot DU1l0

B DU11/U/0O

rom boot

M9312

BDUO

ROM boot

instead of CPU ROM.

Invalid format will cause invalid
entry

B DUO

instead of CPU ROM code.

error

message

Invalid format. No space allowed in

the device

name

DU.

Invalid format. There must be a

space between the Boot command and
the

device

name.

If the user types a colon after the wunit number it will be
.s The single letter device name of B
ignored (e.g., B DLl:)
g non DEC boot devices on the
supportin
of
method
a
s
implement

UNIBUS.

The letter B causes the ROM code to transfer control to

the address contained in location 17773024 of a ROM on the UNIBUS
s location 17773024 is not odd.
if the addresin
4-8

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
When

the

the CPU ROM passes control

CPU ROMs

and

ROMs

UBA

the

a unit number and Rl will
contain
will
RO
disabled,
be
will
table.
the translation
by
passed
was
address
an
contain 0 unless
ROM
the
odd
is
UNIBUS
the
on
17773024
location
in
the address
If

If
program will type out an invalid device message.
from
addresses
all
to
respond
not
does
device

17773776 the ROM program will also type

out

UNIBUS
the
17773000 to

invalid

message.

device

which
a module
The single letter device name of B is used when
to a
similar
17773024
a switch pack that responds at address
has
address
starting
the
Usually
M9312 module is used in the system.
would be set in the switch pack on the
desired
program
the
of
module.

Figure 4-9 shows shows an example of DL2 being booted
boot

using

the

command.

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: B DL2 <CR>
Trying

DL2

Starting

system

RT-11FB

(S)

.SET

QUIE

from

V05.01

DATIME

Date?

[dd-mmm-yy]?
FIGURE

4,2.3

List

DL2

4-9

DL2

BOOT

EXAMPLE

Command

The user enters

this command by typing

the

letter L

<CR>.

This

command
will
print
out
a
1list of all available boot programs
found in the CPU ROM, the CPU EEPROM,
or
any
M9312
type
ROMs
located
on
the
UBA
or
an
M9312
module
1if
present.
The
information listed is the
device
name,
allowable
unit
number
range,
source
of
the
boot program and a short device description.
The device name is normally a
two
letter
mnemonic.
In
some cases the name may be a single letter.
The device name must
always

letters

from A

At input,.the ROM program always converts all lower case
letters
to
upper
case.
The unit number range is the allowable range of
unit numbers that is valid for a particular
boot
program.
The
4-9

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

range varies from 0 to 255, depending on the device.

If the unit

number range information is blank, the ROM code will assume the
range limit is O to 255. The unit number range for M9312 type
ROMs

is always left blank.

The
The source lists where the actual boot program is located.
the
of
outside
the
on
description is intended to be the name
DL
of
name
device
a
for
device to be booted. An example would be
the description would be RL0O2.

Dialog mode is restarted at the completion of the 1list command.
The mnemonic for each ROM found on either the UBA or the M9312
If
will be checked against a list of mnemonics in the ROM code.
the mnemonic matches an item in this list the ROM code will print
If no match 1is found the
out a description of that device.
description will be left blank for that mnemonic. In order for a
M9312 type ROM to be listed it must be in a M9312 type format as
described in subsections 4.6.3 thru 4.6.6.

Figure 4-10 shows an example of a screen

display

for

the

list

command.

Commands are Hélp, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key:
Device Unit

name

numbers Source

0-255

CPU ROM

RD51, RD52, RX50, RC25, RA80, RA81, RA6O0
RLOZ

DL
DX

0-3
0-1

CPU ROM
CPU ROM

DD
DK
MU

0-1
0-7
0-255

CPU ROM
CPU ROM
CPU ROM

TU5S8
RKO05
TK50, TU8l

0-1

CPU ROM

<CR>

Device type
RLO1l,
RXO01

RX02

Commands are Help, Boot, List, Setup, Map and Test.

Type a command then press the RETURN key:

FIGURE 4-10 LIST COMMAND DISPLAY

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

NOTE

Figure 4-10 is an example and may

not

represent

the exact screen display.

4.2.4

Setup Command

all
This command enables the user to 1list and/or change
command
This
s.
parameter
boot
parameters in the EEPROM including
and all of the programmable parameters are discussed in detail in
Subsection 4.3

4.2.5

Map Command

d typing M <CR>. This command will
The user enters this commanby
try to identify all memory in the system and then map all
to
locations in the I/O page. Memory is mapped from location 0
for
mapped
not
is
Memory
s.
the 1I/0 page in 1,024 byte increment
every location. The routine will try to identify the size of
each memory, the CSR address for each memory if applicable, the
CSR type

(ECC or Parity)

and the general bus type.

It is important to note that if two memories share some common
addresses or have CSR's with the same address the map command

will not work properly.

During mapping of memory if two or more memories are present

they

are

not

contiguous

the

descriptions with a blank line.

ROM

code

will

separate

and

their

After all memory is mapped the ROM code will wait for the user to

press the RETURN key to continue the map, which will then typed
out all addresses in the I/O page that respond. The I/O page map
In addition, all
goes from addresses 17760000 to 17777776.
addresses that respond that are on the KDJ11-B or on the KTJ11-B
are provided with a short description. There is no des- cription
for addresses that respond and are on the external bus, with the
exception of memory CSR's,

if present.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

To
command.
Dialog mode is restarted at completion of the map
help prevent the data shown from being scrolled off the screen on
video terminals the ROM code will wait for the user to press <CR>
The ROM code always
the data might overflow the screen.
anytime
at least 24 lines of 80 coloumn
assumes the terminal can display
data.

Figure 4-11 shows an example of a map command printout.
Commands are Help, Boot, List, Setup, Map and Test.
M <CR>
Type a command then press the RETURN key:
Memory

Map

| Starting
Address

Ending

Size in

CSR

Bus

1024

17772100

Parity

PMI

address

K Bytes

address

00000000 - 03777776

type

Press the RETURN key when ready to continue <CR>
I/0 page

Map

Starting

Ending

Address

address

17765000

17765776

17770200

17770376

CPU

17772100

17772150

Memory

17772152

17772200
17772300

17772276
17772376

17772516
17773000
17774400

17773776
17774406

17777520

17777524

17777546
17777560
17777572
17777600

17777730
17777744

ROM or

Unibus Map
CSR

Supervisor I and D PDR/PAR's
Kernel I and D PDR/PAR's
MMR3
CPU ROM

BCSR,

UBA ROM

PCR,

BCR/BDR

Clock CSR
Console SLU
MMRO,1,2
User I and D

17777566
17777576
17777676
=17777734
17777752

DCSR,
MSER,

DDR,
CCR,

17777766
17777772

CPU Error
PIRQ

17777776

PSW

Commands

Type

are

Help,

command

then

EEPROM

List,

Setup,

Map

the

RETURN

key:

press

FIGURE

PDR/PAR's
KMCR
MREG, Hit/Miss

4-11

MAP

COMMAND

and

DISPLAY

Test.

type

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

4.2.6

Test

This

command

tests

runs

all

1is

Command

causes

the

ROM code

continous

applicable

complete:

tests

and

the

console.
print out
errors if

At
the time the test loop
the total number of
1loops
any.
also

type

the

test

most
code

test

the

power

test

after

error

typing

is exited
and
the

after

the

loop

general

loop

number

starts

restarts

occurs

The

user may

exit

run
ROM

then

an error

may

The

entered.

The

user

loop.

and
test

routine

CTRL

is
the

the ROM code will
total
number
of

test

command

and

if the test is applicable the ROM code will loop on that specific
test only until an error occurs or CTRL C is type.
If
the
test
number selected is not a loopable test the general test loop will
be entered and all loopable tests will be run.
NOTE

CTRL

console

Figure

4-12

command
by
user aborts

not

echoed

the

ROM

code

the

terminal.

shows

example

“the

user

entering

typing T <CR> which will run all loopable
the testing sequence after four passes by

the

test

tests.
typing

CTRL

The

Commands

Type

are

Continuous

Passes

Total

Errors

Commands

are

Boot,

then

self

Total

Type

Help,

command

press

test

List,

the

Type

Setup,

Map

RETURN

key:

CTRL

exit

and Test.

<KCR>

CTRL C

4
0

Help,

command

FIGURE

Boot,

then press

4-12

List,

the

Setup,

Map

and

Test.

RETURN key:

TEST COMMAND

EXAMPLE

Figure 4-13 shows an example of the user looping on only
The user aborts the test loop by typing CTRL C after 202

test 60.
passes.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

Commands
Type

are

Looping

test

Total

Passes

202

Errors

Type

SETUP

are

the

Type

CTRL

Help,

List,

press

Boot,

Setup,
RETURN

Setup,

Map
key:

FIGURE

4-13

LOOP-ON-TEST

entered by

and
T

Test.

CTRL

RETURN

press

exit

the

then

COMMAND

Map
key:

List,

command

MODE

Setup mode

Boot,

then

Total

Commands

4.3

Help,

command

and

<CR>

Test.

EXAMPLE

DESCRIPTIONS

typing

<CR>

dialog

mode.

Setup

mode
allows the user to list or change most ¢f the parameters in
the EEPROM.
Setup mode also
allows
changes
to
any
bootstrap
programs stored in the EEPROM.
Setup mode has fifteen commands.
After

power

restart

and

the

completion

all

code
loads
the
first
105
bytes
of
the
EEPROM
beginning at location 2000.
This area in memory is
as
the
Setup
Table.
The
setup
TABLE
contains
parameters

except

The EEPROM may
system.
The

the

EEPROM

resident

contain
various
first
105
bytes

boot

tests

the

ROM

into memory
referred
to
all
of the

programs.

types
of
information
for
is information needed by the

the
ROM

code to configure the KDJ11-B (CPU) and the KTJ11-B (UBA) and
to
determine
the
boot
device,
test
selections and modes.
Other
information in the EEPROM could be user bootstrap programs and
a
foreign
language
file.
Setup mode allows changes to the first
105 bytes and
to
the
user
bootstrap
programs.
The
foreign
language area if present cannot be changed in setup mode.

When

setup mode

first

entered

"types

out

commands
and
provides
a
short
description
of
Figure 4-14 shows an example of setup
mode
being
dialog mode after the user types S <CR>.

1list

all

each command.
entered
from

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: S <CR>

KDJ11-B ROM V7.0

KDJ11-B Setup mode
Command

Description

Exit

List/change parameters in the Setup table

List/change boot translations in the Setup table

List/change the Automatic boot selections in the table
Reserved
List/change the switch boot selections in the table

Initialize the Setup table

11
12

Delete an EEPROM boot
Load an EEPROM boot into memory

Save boot into the EEPROM

9
10

13
15

List boot programs

save the Setup table into the EEPROM
Load EEPROM data into the Setup table
an EEPROM boot
Edit/create
Enter ROM ODT

Type a command then press the RETURN key:

FIGURE 4-14 SETUP MODE COMMAND DESCRIPTIONS
NOTE

The version number of the ROM code is printed out
This
at the beginning of the Setup mode message.versi
on
is
code
ROM
manual revision assumes the
)

7.0 (V7.0).

iption of each
The following paragraphs provide a detailed descr
r followed
To execute a command, type the command numbetype
command.
CTRL C
may
by pressing the RETURN key. At any time the n user
of
ning
begin
the
to
retur
to return to dialog mode or CTRL Z to
setup mode.

NOTE

Never terminate a change of any parameter with
CTRL C or CTRL 2. If this is done the change is
Always use the terminating
ignored and lost.
character

RETURN

CTRL C or CTRL Z.

after

4-15

any change and then use

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

the
at
or
Z,
CTRL
typing
by
restarted
1is
When setup mode
Commands 2 thru 15, the ROM code will print out a
completion of

short command message instead of the full list of commands.

The

user may either type in a new command now, or press <CRY to list
command
short
the
shows
4-15
Figure
the full command menu.
‘

)

message.

KDJ11=-B

Setup mode

Press the RETURN key for Help
Type a command then press the RETURN key:

FIGURE

4.3.]1

Setup Command

4-15

SHORT COMMAND MESSAGE

This is the exit command for the set up mode and returns the user
to Dialog mode.
Dialog mode is also entered if CTRL C is typed.
4,3.2

Setup

Command

This command prints out the current status of various
parameters
and
allows
the user to change them if desired.
When setup mode
command 2

is entered

parameter

the ROM code prints out the

current

status

of
all
parameters,
repeats
the first parameter, and waits for
user input.
The user can type <CR>s to position the
program
at
the
desired
parameter
to
be
changed.
The
user can also go
directly to the parameter by typing the letter to the left of the
the

first

list.

NOTE

After changing any parameters
in the Setup Table,
Command

(Save)

should

executed.

To change a parameter the user types in the new value
and
<CR>.
Typing
<CR>,
Line feed or .
will cause the ROM code to proceed
to the next parameter.
Typing Or - will cause the
ROM
code
to
proceed
to
the previous parameter.
Any of these characters can
be

used

change

value.

Figure 4-16 shows an example of command 2
being
entered.
This
example
also
shows
the
values
of
the
parameters
if
the
"initialize setup table" command 8, is executed in setup mode.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
'

°*

KDJ11-B Setup mode

Press the RETURN key for Help

Type a command then press the RETURN key: 2 <CR>

List/change parameters in the Setup table
A - ANSI Video terminal
B - Power up
C - Restart

O=Dialog,
0=Dialog,

D - Ignore battery

(1)

- 0=No,
l=Yes
(1l)=Automatic, 2=0DT, 3=24
(l)=Automatic, 2=0DT, 3=24

E - PMG 0-(7) l=.4us, 2=.8,
F - Disable clock CSR
G - Force clock interrupts

H - Clock

I
J
K
LL
M

O -

P
Q
R
S

0=No,
. 0=No,
2=Dis 173,
0=No,
0=No,

Disable Setup mode

Disable

all

testing

- Enable UNIBUS memory
- Disable UBA ROM
- Enable UBA cache (1)
- Enable 18 bit mode

test

(1)

CTRL

exit or press

ANSI Video terminal

the

RETURN

(1)

FIGURE

0=No,

4-16

COMMAND

=1
=1

= §

=7
=0
= 0

= A\

l=Yes
l=Yes
3=Both
l=Yes
l=Yes

=1
=0
=0
=0
= 0

0=No,

List/change parameters in the Setup table

Type

l=yes

4=3.2,...7=25.6
0=No,
l=Yes
0=No,
l=Yes

O=Power supply, 1=50Hz, 2=60Hz, 3=800Hz

- Enable ECC test (1)
= Disable long memory test
- Disable ROM 0=No, 1=Dis 165,
- Enable trap on Halt
- Allow alternate boot block

N -

0=No,

3=1.6,

= 0

0=No,

l=Yes

0=No,
0=No,
0=No,
0=No,

l=Yes
l=Yes
l=Yes
l=Yes

=]
=0
=1
= 0

key

for

l=Yes

change

New =

EXAMPLE

NOTE

If 124 KW of UNIBUS memory 1is present,
the
last
two
parameters
will
not be present (Enable UBA
cache
and
enable
18-bit
mode).
When
this
condition occurs UBA cache is always disabled and
18-bit mode is forced unconditionally.
'

The

following

parameter

A - ANSI

paragraphs

specified

Video

terminal

detail

Figure

description of

each

Command

4-16.

present:

When set to 1 this indicates that the console terminal is an ANSI
video terminal.
When 0 it indicates that the console terminal is
ha;d copy
oOr
non
%NSI
compatible-.
When
video
terminal
1is
4-17

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
selected

the

DELETE key will erase

screen.

The

ROM

space,

then

backspace

terminal is
identifies

power up

code

selected
deleted

accom-

plishes

the previous character on the
this

the console

and the DELETE key
<characters by using

if ANSI video

terminal

sending

terminal.

backspace,

When hardcopy

1is
wused
the ROM
code
the slash character.
At

selected

fthe

ROM

code

VT52

will

the cursor at line 9
an ANSI screen clear and then position
send
ROM
The video terminal parameter is used only by the
coloumn 1.
This information is not used by the operating system.
code.
NOTE

VTS52's are not ANSI compatible.

present
you
must
set
this
parameter
to 0 to
prevent the Clear Screen command
from
disabling
the

Power

VT52.

up mode

and

restart mode:

started
When the ROM code is
These are two separate parameters.
it checks a status bit to determine if the unit is powering up or
if the front panet RESTART switch was activated.
The
ROM
code
then
uses the appropriate mode selected.
There are four choices
for the power up mode and the restart mode.
The user may
define
the the action taken by the ROM code at power up or restart to be
the

same

or different.

0 - Dialog mode:
At completion of the
diagnostics,
dialog
mode
1is
entered.
Dialog mode is also entered any time the
force dialog switch is set to the on position regardless
of
the
modes
selected
here.
(See
subsection
4.2
for
a
description

Dialog mode.)

1 - Automatic mode:
At completion of
the
diagnostics
the
ROM
code
enters an automatic boot routine that will try to

boot a previously selected device or device's.
The device's
are
selected
in
the EEPROM (refer subsection 4.3.4).
The
list of devices can be from
1
to
6
devices
1long.
Each
device
1is tried until a successful boot occurs or there are
no more devices to try.
The default list of devices
1is
A,
DLO,
MSO
and
MUO
1in this order.
"A" is a special single
letter mnemonic which causes the ROM code to boot the
first
disk
MSCP
device that it can.
Removable media devices are
tried

before

fixed media

devices.

2 - ODT mode:
At completion of a very limited set of
tests
the
ROM code executes a halt instructicn and passes control
to J11 micro ODT (refer to subsection
4.7).
If
the
user
types P at this point without changing any registers the ROM
code will contine normal testing and then enter dialog mode.
This mode would normally be used in debug environments.
The
ROM code will not change
any
1locations
in
memory
before
entering

ODT mode.

4-18

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
3

mode:

completion

limited

set

tests

the

ROM
code loads the PSW with the contents of location 26 and
then transfers control to the address
1located
1in
1location
24,
This
mode is used when non volatile memory is present
and power fail recovery is desired.
The ROM code
will
not
change any locations in memory before executing mode 24.

‘D -

Ignore battery:

This parameter
mode
1is
set
meaning

that

is used
to
24

only when the current power up or
restart
(3).
Normally this parameter is set to 0
the memory battery ok
signal
must
be
present
in

order
to execute mode 24.
If this parameter is set to 1 mode 24
is executed regardless of the status of the
battery.
At
power
up,
1f
the
mode
selected
1is
mode
24 and the ignore battery
parameter is set to 0
and
the
battery
status
indicates
that
voltages
were not maintained, the ROM code will ignore the power

up selection and use
selection

1is

the

also

mode

restart
24

the

selection.

ROM

code

will

the

default

restart

dialog

mastership

count

mode.

PMG

This
in
is

count:

parameter

the BCSR.
disabled.

sets
The
When

the

value

range is
set, the

the

processor

0 to 7.
When set to
count value enables

zero
the

the counter
KDJ11-B
to

suppress
DMA
requests
and
give
the
processor bus mastership
during
the
next
DMA
arbitration
<cycle
after
the
counter
overflows.
The
processor
will only take the bus for one cycle
before relinquishing control of the bus to a
regquesting
device.
The
following
table
shows
the
time needed for the counter to
overflow for
the
different
wvalues
of
the
PMG
count.
This
parameter is normally set to 7.

vValue

Time

1
2
3
4
5
6
7

for counter

to overflow

Disabled*
-

0.4
0.8
1.6
3.2
6.4
12.8
25.6

usec
usec
usec
usec
usec
usec
usec

The PMG count of 0 (Disabled)
for most typical systems, and
special applications.

is
is

not recommended
reserved for

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
Disable

F -

Clock CSR:

When set to 1 this parameter disables the clock CSR at address
When set to 0 the clock CSR 1is enabled. This
17777546.
.

parameter is normally set to O.
G -

Force Clock

Interrupts:

when set to 1 the clock will unconditionally request interrupts
when the processor priority is 5 or less. When set to 0 the
clock can request interrupts only if the clock CSR is enabled,
clock CSR bit 6 1is 1 and the processor priority is 5 or less.
This parameter is normally set to 0.
NOTE

If the command parameter Force

Clock

Interrupts

is selected the user should always disable the
clock CSR since the CSR has no control over the
clock.

H -

Clock

Select:

This parameter determines the source of the
The choices are listed below.

1
2
3
I

used.

Source

Value

<clock

Clock sourced from backplane pin BR1l. The power supply
normally drives this
Clock sourced on the
Clock sourced on the
Clock sourced on the

Enable

ECC

signal at 50 or 60 Hz.
KDJll-B at 50 Hz
KDJ11-B at 60 Hz
KDJ11-B at 800 Hz

Test:

When set to 1 this parameter enables the ECC memory test to be
run on any ECC memorys present except UNIBUS memory. If the
system contains a mix of ECC and non ECC memory the ROM code will
run the ECC tests only on the ECC memories. The ROM code uses
bit 4 of the memory CSR to determine if the memory is ECC or
If bit 4 is a read/write bit and can be written as a 1l
parity.
wWhen this
and a 0, the ROM code assumes the memory 1is ECC.
. This
bypassed
always
is
test
ECC
the
0
to
parameter 1is set
parameter is normally set to 1 even when ECC memory is not

This parameter would be reset if an ECC memory was
present.
installed whose ECC hamming code does not match that of an MS11-P
type

memory.

BOOTSTRAP

Disable

When

set

data

test

Long

AND

DIAGNOSTIC

ROM

PROGRAMMING

Memory Test:

this

parameter

bypasses

the memory

for all memory above 256 K bytes.

address shorts data test is run on all
parameter is normally set to 0.

address

shorts

When set to 0,

available

memory.
-

the

This

NOTE

If the long memory test is
disabled
and
parity
memory exists above 256 K bytes it is very likely
that memory
will
contain
parity
errors
after
power

Disable

up.

ROM:

This parameter allows the user to selectively disable all or part
of
the
ROM
code
after
the
selected
device has been booted.
Normally the ROM code on the CPU responds to two 256
word
pages
in the I/0 page.
One page responds to address's from 17773000 to
17773777, the other page responds to address's from
17765000
to

17765777.

up or

Both of

restart.

these.pages

After a

device

are automatically enabled at power
is

booted,

pages may be disabled by the ROM code.
the var-

set

iations

this

parameter.

one or

both

The following

This parameter

1is

Value

Rom

None

1
2

17765000-17765777

Pages

and

Disabled.

17773000-17773777
17773000-17773777

NOTE

If the ROM code is booting directly from a
M9312
type boot ROM located on either the UBA module or
the M9312 module, the ROM code will automatically
disable the CPU ROM in the 17773xxx address range
and will enable the ROMs on the board which
were
selected
for
booting.
This
action
1is
taken
regardless of the status of the disable
UBA
ROM
parameter (Q) and the disable ROM parameter (K).

L. -

Enable

Trap

Halt:

these

table lists

normally

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

If this parameter is set to 1 the processor will trap to location
4 if a halt instruction is executed in kernel mode. If this
parameter is set to 0 the processor will enter Jll micro ODT if a
halt instruction is executed in kernel mode. This parameter is
)
'
normally set to 0.
M - Allow Alternate Boot Block:

After the boot block of a device is loaded into memory the ROM
code looks at word locations 0 and 2 to see if the device looks
If the data is not correct, the ROM code will type out
bootable.
an error message indicating that the media is not bootable. When
this parameter is set to 1 the ROM code looks for location 0 be
If this parameter is set to 0 th ROM code
any non zero number.
looks for location 0 to be a value of 240 to 277 and for location
2 to be 400 to 777. This parameter is normally O but may have to
be changed to 1 to allow some user's operating systems to boot
properly.

N -

Disable Setup Mode:

enter
mode
dialog
in
setup mode from dialog mode. The command lines
command
the
types
user
If the
will not show the setup command.
If this parameter is set to 1 the user will not be able to
the response will be invalid command.

If Force Dialog mode 1is selected,
regardless
enabled
unconditionally

parameter.

unauthorized

This

entry

allows

parameter

into

Setup mode.

is
mode
setup
then
of the value of this

prevent

users

some

This assumes the user has

the force dialog switch under some type of physical control.

O - Disable all

testing:

If this parameter is set and Force Dialog mode is

the

ROM

not

program will bypass virtually all testing.

selected,

No location

in memory will be changed unless the selected boot program makes
This is a special parameter which should not be used
a change.

user
It has been provided for cases where the
unless necessary.
user
the
when
and
up,
response at power
immediate
almost
needs
needs the contents of memory to be left unaltered.
NOTE

If all

exists

testing

then

1is

disabled

and

parity

memory

is very likely that memory will

contain parity errors

after power up

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
P

Enable

UNIBUS

Memory

Test:

If this parameter is a 1 then any available UNIBUS memory will be
tested.
When
0 UNIBUS memory is not tested.
This parameter is

normally a 1.

‘Q

the

taken

Disable

This

UBA

parameter

boot.

normal

If UNIBUS memory
code.

ROM

is not present

then no action

ROM:

copied

to bit

this

when

bit

the

is 1,

DCSR of

the UBA after

address

range

of 17773000 to 17773776.

the UBA ROMs are enabled.
ignored.

in the

UBA

When this bit is

is normally 0.

boot either a UBA or M9312 ROM boot,

tries

This bit

the UBA ROMs are disabled.

This allows other ROM boards on the UNIBUS to show up

ROM

|is

When

user

this parameter 1is

‘
NOTE

M9312
If the ROM code is booting directly from a
the
module,
M9312
the
located on
ROM
boot
type
ROM
CPU
the
disable
ROM code will automatically
in the 17773xxx address range and the ROMs on the
The ROMs on the M9312 module will be
UBA module.
enabled
This
action
1is taken regardless of the
and
(Q)
status of the Disable UBA ROM parameter
the

R -

ROM parameter

(K).

UBA Cache:

Enable

When a 1,

Disable

this parameter causes

the UBA cache to be

enabled

and

to be tested by the ROM code.
1If a failure occurs during testing
of the UBA cache then it will be disabled.
When 0 the UBA
cache
is always disabled and is not tested.
This parameter is normally
a

Enable

bit Mode:

This bit

is copied

occurs.

This

this

4.3.3

to bit

5 of

the KMCR on the

causes 18 bit addressing only.

Setup

parameter

Command

normally a

When a 0,

UBA.

When

22 bit addressing

This command prints out the current contents of
the
translation
table
and
allows
the
translation
table
to
be changed.
The
translation table is used to allow devices to be booted using non
~

4-23

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

When the ROM program enters the boot
standard CSR addresses.
routine, RO contains the unit number and R2 contains the device
The ROM code tries to find a match in the
name (mnemonic).
If no
translation table for the device name and unit number.
address
CSR
default
the
use
match 1is found the boot program will
for the device. If a match is found the translation table will
define the CSR address to be used.

.Figure 4-17 is an example of this command.
KDJ11-B Setup mode

Press the RETURN key for Help

Type a command then press the RETURN key: 3 <CR>

List/change boot translations in the Setup table
TT1

blank

TT2
TT3
TT4
TTS
TT6
TT7
TT8
TT9

blank
blank
blank
blank
blank
blank
blank
blank

Type CTRL Z to exit or press the RETURN key for No change
TT1

blank
Device

name

FIGURE 4-17 SETUP COMMAND 3

EXAMPLE

The ROM code is now waiting for the user to enter a new device
If the user does not desire to change any items in the
name.

translation table
The
mode prompt.
entry by pressing
types
the user
CSR address.

he/she would Type CTRL 2 to return to the setup
user may skip over any entry and go to the next
To enter a new device or change an entry
<CR>.
in the new device name, the unit number and the

system that
In the example shown in Figure 4-18, the user has a
the standard
at
contrcller
UDA50
a
has one RA80 and a RA60 using
a KLESI-U
with
RC25
a
has
also
The user
address of 172150.
the same
share
KLESI-U
the
and
UDA50
the
Since
controller.
standard CSR address one of them must be

set

respond

1In this example the KLESI interface is set to
different address.
The RQZS has a unit number plug set
respond to address 17760500.
4-24

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
for units 4 and 5.
The RA80 is unit 0 and the RA60 is unit 1 and
2.
Since the RC25's interface is at a non standard
CSR
address
and
there
are two unit numbers there will be two entries in the
translation

table

for units

TT1
blank
Device name
Unit number
CSR address

DU4

TT1

TT2

=
=

and

DU <CR>
4 <CR>

= 17760500 <CR>
address 17760500

blank

Device

name

Unit number
CSR address
DU5S5
TT2
TT3
Device

FIGURE

<CR>
5 <CR>
17760500 <CR>
address 17760500

blank
name

4-18

CTRL

TWO-ENTRY TRANSLATION

TABLE

EXAMPLE

The translation table also provides a means of handling

multiple

For example if the user
RL02 controllers.
as
such
controllers
the
had two RL0O2 controllers with six drives of which 2 where on
second controller at address 17760400 the translation table could
first
the
on
be
would
0-3
Drives
be set up to handle this.
controller
at
the
standard
address
and would not require any
be
would
controller
second
the
on
1
Drives 0 and
entries.

labeled as drives 4 and 5 and entered into the translation table.
Since RL0O2 controllers only recognize unit numbers from
0-3
the
unit
numbers 4 and 5 would have to be translated to unit numbers
the
into
entries
Figure 4-19 shows an example of the
0 and 1.
translation table.
‘
blank
name
number

TT1

DL4

TT2

blank

DLO

Device name
Unit number

CSR address
TT2
DL5

TT3
Device

17760400

address

=
=

DL <CR>
5 ] <CR>

=
DL1

DL <CR>
4 0 <CR>

Unit
CSR address

unan

TT1
Device

<CR>

17760400

17760400 <CR>
address 17760400

blank
=

name

CTRL

FIGURE 4-19 UNIT NUMBER TRANSLATION EXAMPLE
|

4-25

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

4.3.4 Setup Command 4

This command allows the user to select the devices to be-tried in
the automatic boot sequence. The user creates a small list that
defines the devices and the order in which they are to be tried.
One entry is needed to define a device and its unit number. If
the same device is used more than once with different unit
numbers, then one entry is needed for each unit number.
NOTE

The selections for this command use the
in the EEPROM as command 6
locations

same
that

follows.

When Command 4 is executed the ROM code will prompt the user for
a device name. The user would then type in either the single or
double letter mnemonic associated with the device to be selected.
The ROM code will then prompt for the unit number. The ROM code
will continue prompting for all six entries in the table.

Figure 4-20 shows an example of command 4. In this example the
user adds the boot for the RX02 unit 1 (DY) by replacing the Exit
The exit
name (E) with DY and typing in the unit number next.
name

typed

for the

next entry.

BOOTSTRAPAAND DIAGNOSTIC ROM PROGRAMMING
KDJ11-B Setup mode
Press the RETURN key for Help
Type a command then press the

RETURN

key:

<CR>

List/change the Automatic boot selections in the Setup table
A =
B
E
L

Disk MSCP automatic boot

= External ROM boot
= Exit automatic boot
= Loop continously

Boot
Boot
Boot

1
2
3

Boot

MUO

Boot.5

blank

Boot

A
DLO
MSO

Type CTRL Z to exit or press the RETURN key for No change
Boot 1
Device

Boot

Device

Boot

= A
name

<CR>

=-DLO
name

MSO

Device

name

<CR>

Boot 4
Device

= MUO
name

<CR>

=
=

E
0

Boot

Device

name

<CR>

=1 <CR>

Unit number
Boot € = blank
Device name
Unit number

KDJ11-B Setup mode
Press the RETURN key

for

Help

Type a command then press the RETURN key:
FIGURE

4-20

SETUP COMMAND 4

EXAMPLE

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

Table 4-2

lists

names

the

and

the four special

associated

ROM

TABLE

mnemonic

device

4-2

ROM

CODE

ACTION

The ROM code will boot the first bootable disk MSCP device
it can find. The ROM code will try removable media units
first,

single-letter

action.

then

fixed media

units.

This mnemonic causes the ROM code to check for a UNIBUS
ROM board in address range of 17773000 to 17773776. If the
ROM exists and location 17773024 is not odd the ROM code
will disable the internal CPU ROMs and the UBA ROMs and
jump to the location specified in location 17773024 of the

UNIBUS ROM board. Usually this board
M9301 or user-supplied equivalent.

would be

M9312,

The only purpose of this mnemonic is to indicate to the
ROM code that there are no other devices to try in the
list. This is used when there are five or less devices in
the list. It follows the last device in the list to be
tried. If all six entries are filled in the list then this
mnemonic is not needed, the list will terminate
automatically after trying the last entry. When this
mnemonic is reached the ROM code will restart the boot
sequence from the beginning and print error messages for
each device that fails to boot as they are tried. After
the second pass through the list without successfully
booting a device the ROM code will enter dialog mode.

This mnemonic will also mark the end of the list but
when this mnemonic is reached the ROM code will restart
the boot sequence at the beginning of the list and
continue trying to boot each device in the list until
either a successful boot has occurred or the sequence is
terminated by the user typing CTRL C. All
messages are suppressed when the ROM code
the boot list.

boot error
is looping on

The action taken by the ROM
code
for
the
four
single
letter
mnemonics
A, B, E and L applies only to automatic boot mode with
the exception of B which can also be
executed
from
the
dialog
mode
boot command.
The dialog mode boot command would treat the
4-28

BOOTSTRAP AND DfAGNOSTIC ROM PROGRAMMING
single letter mnemonics of A, E and L as invalid devices if they
were used as the device name in the boot command. If the user
creates a bootstrap program and loads it into the EEPROM, that
program should not be given a device name of either A, B,E or L
All other single letter
since these are already defined.

mnemonics are

for use.

free

4.3.5 Setup Command 5

If this command
This command is reserved and is not used.
changes are made.
no
and
d
entered setup mode will be restarte
4.3.6 Setup Command

1is

This command allows the user to define the value of three of the
eight switches at the edge of the CPU module to boot specific
possible
This command defines six of the eight
devices.
combinations of switches 2-4, the other two combinations have a
fixed definition that cannot be changed. Refer to Appendix H for
additional

information.

Command 6 is

not

normally

switches might be defined is:

used.

The

only

time

that

these

and

If the system had cabling between J3 on the CPU module

The user desired to define six positions such that each
position causes the ROM code to enter Automatic boot mode

a remote 8-position rotory switch, and

after testing is completed, and attempt to boot only one
device which was defined by this command in Setup mode.

Normally the three switches are off. 1If automatic boot mode is
selected, the ROM code will use the list defined by command 4 in
Setup mode and try to boot each item in the list one at a time
until all selections in the list have been attempted.

When switches 2-4 are set to one of the six combinations shown in
the e EXample and Force Dialog mode is not selected the ROM code
will enter the auto boot mode and attempt to boot

device

selected

this commmand.

the

only

the ROM code will print out the normal error

message

and

dialog mode.

NOTE

The six selections in the table are stored in the
EEPROM as the six boot
the
of
area
same
selections decsribed in Command 4.
4-29

one

If the boot is unsuccessful

enter

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
Figure 4-21 shows an example of setup mode command 6
with
three
of
the
six
possible positions being defined to select DUO, DUl
and

DU2

and

the

other

three

all

KDJ11-B Setup mode
Press the RETURN key

Type

command

List/change

Switches
Switches
Switches
Switches
Switches
Switches
Type

Switches
Device

the

2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4

CTRL

then

for

Help

press

the

switch

on
on
on
off
off
off

2,3,4

boot

on
off
off
on
on
off

exit

name

being

defined

RETURN

key:

selections

off
on
off
on
off
on

press

select

DLO.

<CR>

the

Setup

table

= DUQ
= DU1
= DU2
= DLO
= DLO
= DLO
the

off

RETURN

key

for

change

DUO

FIGURE 4-21 SETUP COMMAND 6 EXAMPLE
4.3.7

Setup

Command

This command performs the exact same
in the List command in Dialog mode.
setup

mode

for

user

convenience,

function as
The command

see

detailed description of this command.
the completion of this command.

4.,3.8

Setup

This

command

Command

the List command
is duplicated in

Subsection

4.2.3

Setup

mode

contents

the

for

restarted

initializes

the

current

setup

table

in
memory
to
the default values.
This command does not affect
the contents of the EEPROM itself.
The setup save command 9 must
be
executed
1in
order
to save the setup table into the EEPROM.
This command only affects parameters associated with
commands
2
to
6
of
Setup mode and does not affect any data that is not in
the first 105 bytes of the EEPROM.
The

following

Command

All

items

list

the

value

the

parameters

after

entered:

parameters

are
set
which are

to
set

listed
0
to

under

setup

command

with
the exception of
1.
(See Figure 4-16.)
4-30

of
B,

setup
C,

mode
and

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
-

All
are

entries
cleared

The

automatic boot

will

set

in the translation table
and will list as blank.

to A,

selection

DLO,

MSO,

list

MUO,

under setup

wunder

blank.

setup

command

Since Setup Command 6 shares the same area as Command 4 it's list

parameter values

will

identical

that

Command

To enter this command the user must type 8 <CR>.
After
the
ROM
code
prompt, the user must type 1 <CR>.
Command 9 (Save) should
be executed after Command 8 if the
user
wishes
to
retain
the
defaults
in the EEPROM.
Figure 4-22 shows an example of Command
8

execution,

KDJ11-B

Press

Type

Setup mode

the RETURN key for Help
a command then press the

Initialize

the

Are you sure ?
Type a command

RETURN key:

<CR>

l1=Yes.
0=No,
then press the RETURN key:

<CR>

Setup

KDJ11-B Setup mode
Press the RETURN key

Type a command

FIGURE

4.3.9

Setup Command

table

for Help

the RETURN key:

then press

4-22

SETUP

COMMAND

EXAMPLE

This commands copies the current contents of the setup

table

memory into the EEPROM.
The command should be executed after any
changes are made to the EEPROM in Setup mode.
This is
the
only
that writes anything into the first 105(10) bytes of the
command
EEPROM.
When saving data into the EEPROM the ROM code will
only
write the locations that need to be written.
This command will always write a new and
correct
checksum
into
the
EEPROM
unless
a
failure
occurs.
If a location cannot be
written the ROM code will try
once
more
and
then
report
the
error.
It takes approximately 15 ms to write each location.
If command 9 is entered and no changes
have
been
made
to
the
setup
table,
the
ROM
<code
will print out a message saying no

change were made and

then restart Setup mode.

If changes are

prompt the user to make sure they
will
code
ROM
made the
be
desire to make the changes.
Figure~” 4-23
shows
an
example
of
Command

4-31

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
KDJ11-B

Setup mode

Press the RETURN key for Help
Type a command then press the RETURN
Save the Setup table
Are

you

sure

the

<CR>

the RETURN key:

<CR>

into the EEPROM

0=No,

l=Yes

Type a ¢ommand then press

Writing

key:

EEPROM

KDJ11-B Setup mode
Press the RETURN key for

Help

Type a command then press the RETURN key:
FIGURE 4-23 SETUP COMMAND 9 EXAMPLE
4.3.10 Setup Command 10

This command will restore the setup table in memory with the
values actually stored in-‘the EEPROM. This command allows the

user to restore the setup table after making some temporary
changes. It is also used to load the actual data from the EEPROM
into the setup table if an error occurred during the EEPROM
checksum

tests.

When an error occurs during the EEPROM checksum tests, the ROM
code assumes the data is bad and loads a set of default values
into the setup table and uses them. 1In this case the user could

load the actual data and then verify the data is OK before trying
to save

it back

into the

EEPROM.

Figure 4-24 shows an example of Command 10.
KDJ11-B Setup mode

Press the RETURN key for Help

Type a command then press the RETURN key:

10 <CR>

Load EEPROM data into the Setup table
Are you sure ?

0=No,

l=Yes

Type a command then press the RETURN key:
KDJ11-B Setup mode

Press the RETURN key for Help

Type a command then press the RETURN key:
FIGURE 4-24 SETUP COMMAND 10 EXAMPLE
4-32

1 <CR>

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
4.3.11 Setup Command 11

If this
This command allows the user to delete an EEPROM boot.
command is executed the ROM code will prompt the usef for the
device name of the EEPROM boot to be deleted. After the device
name is typed- in the ROM <code will look for the first boot
program in the EEPROM with that device name and delete it, 1if
If there are any boot programs following the deleted
found.

code will automatically move all of these
wuse the space made available by the deleted

program the ROM
programs up to
program.

(See Figure 4-25.)

KDJ11-B Setup mode
Press the RETURN key for Help

Type a command then.press the RETURN key:
an

Delete

11 <CR>

EEPROM boot

Type CTRL Z to exit or press the RETURN key for No change
= CC

name

Device

0=No,

Are you

sure

KDJ11-B

Setup mode

<KCR>
l=Yes

Type a command then press the RETURN key:

<CR>

Press the RETURN key for Help
Type a command then press the RETURN key:
FIGURE 4-25 SETUP COMMAND 11 EXAMPLE

4,.3.12 Setup Command

This command is used to copy an EEPROM boot program into memory.
command is executed, the ROM code prompts the user for
the
When
1in
1loaded
be
to
boot program
EEPROM
the device name of the
then be examined and/or edited using
program can
The
memory.
Figure 4-26 shows an example of Command 12.
Setup Command 13.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
‘
for Help

KDJ11-B Setup mode
Press the RETURN key

Type a command then press the RETURN key:
Load

EEPROM boot

12 <CR>

into memory

Type CTRL Z to exit or press the RETURN key for No change
=

name

Device

Are you sure

CC <CR>

0=No,

l=Yes

Type a command then press the RETURN key:
KDJ11-B

Press

1 <CR>

Setup mode

the RETURN key for Help

Type a command then press the RETURN key:

FIGURE 4-26 SETUP COMMAND 12 EXAMPLE

4.3.13 Setup Command 13

This command is used to either create a new EEPROM

boot

program

or to edit a program previously loaded with Command 12 above.
Command 13 allows the user to change the device name, the device
description, the allowable unit number range, the beginning and
ending addresses of the program in memory, and the start address
of

the

program.

When these changes are complete the ROM code enters ROM ODT which
is
is a ROM code version of J11 Micro ODT. When this command for
EEPROM
the
in
space
le
availab
the
list
will
it
entered
first
bootstrap

programs

Figure 4-27 shows an example of Command 13.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
KDJ11-B Setup mode

Press the RETURN key for Help

Type a command then press the RETURN key: 13 <CR>
Edit/create an EEPROM boot

Type CTRL Z to exit or press the RETURN key for No change
1410 Bytes free in the EEPROM

= AA

New = EA <CR>

= 000600

New = 10000 <CR>

Last byte address

= 000615

New = 10177 <CR>

start address

= 000600

New = 10000 <CR>

Device name

Beginning

address

Highest Unit number

= 3 |

New = 255 <CR>

Device Description

= EA BOOT

New = RM02,RM03 <CR>

Enter ROM ODT

xxxxxx/ = open word location xxxxxx if address even, byte if odd
= close location
RETURN
. or LF = close location and open next
close location and open previous

ROM ODT>
ROM ODT>

010000/000000 012705 <CR>
010002/000000 101 <CR>

ROM ODT> 010004/000000 12706 <CR>
ROM ODT> 010006/000000 1000 <CR>

etc.

‘

Type CTRL 2 exit back to the setup mode menu.
FIGURE 4-27 SETUP COMMAND 13 EXAMPLE

program in
The beginning address is the first location of the
of the last byte of
‘memory. The last byte address is the address
s of data +
code used in memory. If in doubt, use the last addres
it will
since
5 for this value. Do not use a much larger number
waste

EEPROM

space.

The start address is the address that the ROM code willsame©pass
as
The start address does not have to be the
control to.
range
the
in
value
a
and
the load address but it must be even
defined by the load and ending addresses.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
The highest unit number defines the allowable range of valid unit
If the value is set to 3 the allowable
numbers for this device.
Tf a unit
range is 0 to 3. The highest range is 0 to 255.
then a
range
in
not
is
it
and
time
number is typed in at boot
occur.
will
invalid unit number error

The device description is an optional but recommended description

The maximum length of this name is 11
of the device name.
be the name that
characters or spaces. The name should normally
is physically marked on the outside of the device (i.e. RLO2).
4.3.14 Setup Command 14

boot

program

saving a boot program into memory the device name of the

program

This command allows the user to save the

existing

located in memory into the EEPROM. This is the only command that
The other commands' only
actually writes a boot into the EEPROM.
When
change a copy of the boot program that resides in memory.

must not match the name of an existing program in the EEPROM.

the program name already exists the user must delete that program
If two or
first or change the name of the program to be saved.
name
same
the
with
EEPROM
the
into
written
more programs were
an
shows
4-28
Figure
used.
and
found
be
only the first one would
example

Command

14.

KDJ11-B Setup mode
Press the RETURN key for Help

Type a command then press the RETURN key:
Save

boot

into

the

14 <CR>

EEPROM

Type CTRL Z to exit or press the RETURN key for No change
Are you

sure

0=No,

l=Yes

Type a command then press

the RETURN key:

Writing the EEPROM - Please wait
KDJ11-B Setup mode
Press the RETURN key for Help

Type a command then press the RETURN key:

FIGURE 4-28 SETUP COMMAND 14 EXAMPLE

<CR>

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
executed where
Figure 4-29 shows an example of Command 14 being
the data in the setup table matches the data in the EEPROM, thus

changes

were made.

KDJ11-B Setup mode
Press the RETURN key for Help
Type a command then press the RETURN key:
into

the

already

Save

boot

Boot

<CR>

EEPROM
the

EEPROM

changes made

KDJ11-B

Setup mode

.
Press the RETURN key for Help
Type a command then press the RETURN key:
FIGURE

4.3.15

Setup Command

4-29

SETUP COMMAND

code

will

open

EXAMPLE

This command puts the user into ROM ODT

ROM

the

address

(see Figure

4-30).

The

defined by the beginning

address of the program.
ROM ODT is not the
same
as
Jll
micro
The only purpose of ROM ODT is to allow the user to create
ODT.
or edit a small bootstrap program to be stored in the EEPROM.

are
In ROM ODT the only allowable addresses that can be examined
other
Any
from 0-28 KW (0-00157776).
memory
of
addresses
the

addresses
and any
attempt
to
accessed
the
I/O
page
or
any
registers is not allowed.
Table 4-3 lists the ROM ODT commands.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
TABLE 4-3 ROM ODT COMMANDS

Prints contents of specified location or ifof
no address is defined then print contents
the last location that was opened. If
location opened is an odd number then print
out only the contents of the byte. If
location is even then mode is word, if
location is odd then mode is byte. Leading
zeroes are assumed. Only bits 15 through
zero of the address are used.

RETURN
LINE

FEED

<CR>

Closes an open location

<LF>

Closes an open location and then opens

Period

the next location. If word, increment address
by 2, if byte, increment address by 1.
Alternate character for line feed.

This command is useful when the terminal
is a VT2xx series terminal. It is also
convenient to use with the keypad.

Closes an open location and fthen opens
the previous location. If in word mode
then decrement by 2, if byte decrement

arror

Minus

Alternate character for Up arror.

This command is useful when the terminal
is a VT2xx series terminal. It is also
convenient to use with the keypad.

DELETE

Delete

Deletes the previous character typed.

Exit ROM ODT and return to setup mode.

The following -paragraphs present examples of ROM ODT use.
EXAMPLE

Location 200 is opened.
location

contents.

202 is

It is then closed with

changes

and

opened, which is then closed after changing it's

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

ROM ODT >

200/

ROM ODT > 000200/100000 <LF>.

ROM ODT > 000202/003333 44 <CR>
ODT

ROM

EXAMPLE

locations
Byte location 1001 is opened. It is then closed and chang
ed and
1002 and 1003 are opened. Location 1003's data is
then closed.

ROM ODT >

1001/

ROM ODT > 001001/101 <LF>
ROM ODT >

001002/104 <LF>

ROM ODT > 001003/113 141 <CR>
ODT

ROM

EXAMPLE 3

The user attempts to open location 170000 which
page,

and not allowed.

the

1I/0

ROM ODT > 77770000/
ODT

ROM

EXAMPLE

Location 150000 is opened and then closed.

by typing / only.

ROM ODT >

150000/

ROM ODT > 150000/032737 <CR>
ROM ODT > /

ROM ODT >

150000/032737

It is

then

reopened

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
KDJ11-B Setup mode

Press the RETURN key for Help
Type a command then press the RETURN key:
Enter

ROM

15 <CR>

ODT

Type CTRL Z to exit or press the RETURN key for No change

xxxxxx/ = open word location xxxxxx if address even, byte if odd

= close location
RETURN
= close location and open next
LF
. or
close location and open previous

ROM ODT>

010000,/000000

ROM ODT> 010002/000000
ROM ODT> 010004/000000
ROM

ODT>

CTRL

012705 <CR>

101 <CR>
12706 <CR>

KDJ11-B Setup mode
Press the RETURN key for Help

Type a command then press the RETURN key:

FIGURE 4-30 SETUP COMMAND 15 EXAMPLE
4.4

DIAGNOSTIC ERROR MESSAGES

information are
When an error occurs, the test number and other
of the current
number
the
always
The error number is
printed.

test number that the ROM code is running.

The test

numbers

corresponding error messages are described in Chapter 5.
4.5

BOOTSTRAP

and

PROGRAMS

Bootstrap programs may be found in various areas of

the

system.

The ROM code contains bootstrap programs for the following UNIBUS

devices:

Device
Name

DU*

DL
DX
DY
DD
DK
MU**

Device Type

RX50, RC25,

RLO1,
RX01
RX02
TUS8
RKOS
TU81

RA80, RA81,

RLO2

4-40

RA60

BOOTSTRAP AND DIAGNOSTIC ROM' PROGRAMMING

* DU refers to a general purpose boot program for
disk MSCP devices.

** MU refers to a general purpose boot program fortape MSCP devices.

For users who have devices not covered by the ROM code bootstrap
the ROM code also supports the use of M9312 type boot ROMs
list,
which are typically shipped with the controller module for

devices which can be booted. These ROMs are currently used in
all existing UNIBUS PDP 11 products. An example of this would be
a RKO7 disk drive which uses a M9312 ROM to allow the drive to be
booted. Table 4-4 lists the M9312 type boot ROMs currently
available.

The user may install the ROM in

either

the

UBA

module

optional M9312 module. The ROM code will list and boot any M9312
Subsection 4.5.1 contains
type ROM located in either module.
additional

information on M9312

type ROMs.

The ROM code also allows users to install bootstrap programs for
The user
new devices or for custom boot programs in the EEPROM.
using
by
EEPROM
the
into
programs
can install machine language
loaded
is
program
the
Once
15.
through
11
Setup mode commands
into the EEPROM, it will be avail- able to the user at any time.

the

assembles EEPROM boot programs in memory and then starts
program at a start address defined by the boot program.
EEPROM may contain more than one boot program depending on

the
The
the

for

the

There is one important difference between boot

programs

The EEPROM is an eight bit device which means
EEPROM and others.
they are
the programs cannot be executed out of the EEPROM as
always
code
ROM
The
type ROMs.
ROM code or M9312
from the

size

the

programs.

When a boot program is requested, the ROM code searches
boot program in the following sequence:
1.

Search the EEPROM on the CPU first.

Search the ROM code con the CPU next.

Search the ROM sockets on

Search the ROM sockets on the M9312 board next,

the UBA next.

if present.

BOOTSTRAP.AND DIAGNOSTIC ROM PROGRAMMING
4.5.1 Bootstrap List

Table 4-4 describes the M9312-type boot ROMs that are

available.

These ROMs are used on all UNIBUS processors. Some of the ROMs
listed are not required because the base ROM code in the 'CPU ROM
contains bootstraps for some devices.

Many of the devices listed are old and

today,

However,

they

generally

not

available

are included because many systems contain

In general, the ROMs needed to boot a device are
these devices.
For example,
shipped with the interface for the device itself.
r the ROM
controlle
RL11l
an
and
RLO2
an
purchased
if a customer

would come with the RL11l controller.

The CPU ROM code uses a two-letter
M9312 ROM to identify the ROM.
than one bootstrap program.

in each
mnemonic contained
Some of the ROMs contain more

Some programs require more than

ROM to fully implement a bootstrap.

one

TABLE 4-4 AVAILABLE M9312 TYPE ROMS
SUPPORTED DEVICES

23-761A9-00

TU60 cassette tape drive

DK
DT

23-756A9-00
23-756A9-00

RKO3, RKO5 disk drives
TU55, TU56 tape drives

Note: The RKO0S5 boot is also in
the

23=-752A9-00

23-755A9-00

CPU

ROM

RK06, RKO7 disk drives
RP02, RP03 disk drives. This ROM

mustbe

installed

in the KTJ11-B.

RP04, RPO5, RPO6, RMO2, RMO03

disk

drives. This ROM must be installed
in

the

KTJ11-B.

23-759A9-00

RS03, RS04 disk drives

23-757A9-00

TUl6, TEl6, TU45, TM02, TMO3, TU77

23-764A9-00

TS04, TS1ll, TU80, TS0S5 tape drives

23-758A9-00

TUl0, TEl10, TS03 tape drives

23-760A9-00

PCO5 High speed paper reader

23-760A9-00

tape drives

Low spedéd paper reader (Teletype)
4-42

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

23-E22A9-00

DECnet DEUNA ethernet interface

23-926A9-00
23-927A9-00
23-92849-00

DL11-E (DECnet DDCMP)
NOTE: Three ROMs are required

23-862A9-00

23-863A9-00
23-864A9-00

DMC11, DMR11l (DECnet DDCMP)
NOTE: Three ROMs are required
to implement this bootstrap.

23-868A9-00
23-869A9-00
23-870A9-00

DUll (DECnet DDCMP)
NOTE: Three ROMs are reqguired
to implement this bootstrap.

23-865A9-00

implement

DUPl1]l

this bootstrap.

(DECnet DDCMP)

‘NOTE :Three ROMs are erguired

23-866A9-00
23-867A9-00

implement

this bootstrap.

NOTE

In V6.0 and
identifies

which
routine
the
UBA or the M9312 will not

code,

v7.0

ROM

ROMs

on the

identify boot ROMs which use more

than
of this, these
from
started
boots will not list and can not be
code without using a small EEPROM
base
ROM
the
ROMs.
the
to
control
boot program to transfer
in
a
future
corrected
be
problem
will
This

correctly
one

for

ROM

release

the

the CPU

boot.

ROM code.
instructions

Refer to Appendix F for
the EEPROM to allow the
ROM boot on the UBA or
which is not compatible
for

The

ROMs

boot

listed

CPU ROM to handle

set

a multi

the
M9312,
or
any
ROM
with the M9312 ROM format

ROMs.

Table

4-5

are

similar bootstrap programs are

module.

Because

generally

located

not

needed

because

in the base ROM on the CPU

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

TABLE 4-5 CPU ROM BOOT PROGRAMS
—_————_c-———cn——-———

-:-smcxau————_—---n——--—-—:—c-————--—————————-q--

MNEMONIC

SUPPORTED DEVICES

DEC“PART NUMBER

drivee
tapedg
23-765m9-00 TUS8 cartri

23-756A9-00

RKO5 disk drive

23-751A9-00

RLO1, RL02 disk drives

23-767A9-00

(General boot for all Disk

23-753A9-00

RX01 floppy disk drive

23-81129-00

RX02 floppy disk drive

4.5.2

Format

EEPROM

The first 105 bytes

parameters
the ROM

for

code

selections

MSCP devices) RA80, RA81,
RA60, RC25, RX50 disk drives

and

the

EEPROM

stores

the

Dbase

determine

the

power

up/restart

the list of devices to try to boot.

following the first 105 bytes are four bytes which the

use

hardware

CPU, the UBA, and the information needed by

for any purpose such as storing a serial number.

bytes are never used by the ROM code.

mode,

test

Immediately
user

may

These four

The optional bootstrap programs follow immediately after these
four bytes. The EEPROM may also contain translations for some of
the ROM code messages for local language requirements for non

English users. The local language text, if present always starts
at the end of the EEPROM. Figure 4-31 1illustrates the EEPROM
layout.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

EEPROM size =
Start of

2048 bytes.

====-———-c====——eo—————————————=——-

EEPROM

Base

)

area.

CPU and UBA Hardware parameters Boot device information

105 Bytes

Translation table

4 Bytes

Reserved for customer use only*

variable length

Optional bootstrap # 1

Selection

expand towards beginning

Vvariable Length
|
|
End

EEPROM

information

optional Foreign language text or
UFD area if no foreign language

==
=s—
oo o- ===
~—=-c-mememe—m—mee——mms—

* The four bytes reserved for customer use may be accessed as
follows:

1. Insure that bit 6 is reset in the CPU BCSR'at 17777520.
2. Insure bit 5 is set in the CPU BCSR at 17777520.

3. Bit 4 in the CPU BCSR at 17777520 must be set to write
the EEPROM.

It need not be set when reading the EEPROM.

4. The low byte of the PCR must be 0 at 17777522.

5. The four bytes of data can now be read or written at
addresses 17765322 to 17765330. Each byte is accessed
in a 16-bit word where the data is in bits 7 thru 0.
Bits 15 thru 8 are not driven by the CPU and must be
ignored since their value will change.
FIGURE

4-31

EEPROM

LAYOUT

If a serial number 1is written to the four customer-reserved
the format could be to write up to a 24-bit number in the
bytes,
4.
first three bytes and write a checksum for the number in byte
the
to
up
is
format
actual
the
and
suggestion
is only a
This
user.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

When data is written to the EEPROM the user must wait at least 10
ms after the write cycle for each byte before proceeding. The
FEPROM can not be written more than 10,000 times. ~After any
write the data should always be checked after 10 ms to verify
that it was written correctly.

NOTE

It is strongly recommended that bit 4 cf the BCSR
the user is writing to the
set unless
not be
EEPROM, and that it be reset as soon as writes
This bit does not have to be set
are complete.
to

read

the

EEPROM.

4.5.3 General Rules For EEPROM User Boots

EFPROM boots are assembled into the lower 28 K words of memory by
the ROM code. If there are no errors such as checksum errors the
ROM code will pass ccntrol to the program according to the
starting address

in the boot program.

At the start of an EEPROM boot the following is true:

Memory management is disabled and 22 bit mode is off.

RO contains the unit number.

Rl will be 0 if no address was passed by the translation
table or the /A switch in the boot command. Rl will be an
alternate address for the program to use if the translation
table matches the boot device's name and unit number with
an entry in the translation table or the /A switch was used
in the boot command.

The ROM code loads a trap handler for timouts to location 4
The program is loaded into memory starting at
in memory.
location 1000 if the start address of the EEPROM boot
program 1is 10000 or greater. The program is loaded into
memory starting at location 17600 if the start address of
the EEPROM boot program is 0 to 7776. The rom code will

load the address of the timout handler into location 4 as
long as the EEPROM boot does not already occupy location 4
If a timout occurs during the boot program and the
itself.
timout handler is entered the handler will restart the rom
code with the non existent controller message in R5 and the

rom code will assume that the value in Rl is the address of

the controller that timed out.

BOOTSTRAP AND DIAGNOSTIC ROM- PROGRAMMING

if
The EEPROM may use memory management and restart the ROM code
Kernel
to only
the EEPROM program restricts the use of MMUmust
not use any
boot
The EEPROM

Rs 0-3 and 7.

Instruction PAR/PD
of the other PAR/ PDRs if the ROM code is to be restarted. The
In
bitO ="0).
ROM code should be re- started with MMU OFF (MMRO on
the
is
it
4,
locati
ps
overla
the case where the EEPROM boot

responsibility of the EEPROM boot to handle timeouts.

It is the responsibility of the user's program to boot the device
and check the boot block for a bootable secondary boot program.
It is recommended that EEPROM boot programs not be located 1in
memory between addresses 2000 to 2300, 16000 to 16040, and 20000
programs is
to 40000. The recommended location for EEPROM boot
cal address
(Physi
point
memory addresses above the g8Kk-word
.
00040000)

The following paragraphs describe the way user-written boot
programs should handle errors or success. It is recommended that
This will
the user write programs that adhere to these rules.
event that
the
allow the user to receive meaningful messages in
However, the user's boot
errors occur in the boot program.
program need not return control if it is not desired.

Once the EEPROM
complete

control

1is

boot

started

the CPU.

the

user

program

boot

has

The user's program would restart

the ROM code for one of the following three reasons:

An error occurred attempting to boot a device and the ROM
code 1is restarted to type out a general error message. This
allows the automatic boot mode to try another item for
booting.

To reenter the ROM

code

for

error

message

printing,

the

load RS5 with the error message
user's boot program would
- 4 of the BCSR are set to O,
7
bits
that
sure
make
desired,
with the MMU off.
165762
@
JMP
a
execute
then
and

The following list specifies the octal

value

the

error

‘message selection codes and the text of the message printed.
At the time the ROM code 1is restarted, RO should still
contain the unit number and Rl should contain the address of
the

controller.

270

= Drive

273

not

ready

271 = Non bootable media present
272 = No disk present or drive unloaded
No

tape present

274 = Non existent controller
275 = Non existent drive
4-47

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
= Invalid unit number
= Invalid device
= Controller error
= Drive error

276
277
300
301

the boot
1If the user's program monitors the keyboard during
is typed.
C
CTRL
if
code
ROM
return control to the
it could
reentered
be
would
code
The ROM
This is an optional feature.
same way as described in 1 above with the exception that
the
R5 should be an octal value not equal to 270 to 301 or 1.

successful

The boot is

and

the

ROM

code

1is

temporarily

print out the "Starting system from " message.
to
restarted
returns
code
After the message printout is complete the ROM
To reenter the ROM code to
user's program.
the
to
control

code would
wuser’'s
the
print the "Starting system message"
R5 with the number 1, make sure bits 7 - 4 of the BCSR
load
PC,
JSR
a
are 0 and then restart the ROM code by executing
@

165762 with MMU off.

When the ROM code has completed typing the message it returns

the user's boot at the instruction following the

control

existing

compatible with all
user's program should
the
code,
ROM
the
versions of

Reset bit

JSR instruction.
do

the

At this point, to be

following:

(register set

1 select)

in the PSW

Reset the display register by writing 000077
777

address

524,

Clear MMR3

(17 772 516) to make sure 22-bit mode is off.

4.6 BOOT ROM FACILITY (M9312 compatible)

The KTJ11-B Boot ROM Facility allows the user to install M9312
compatible boot programs written for UNIBUS devices which are not
directly supported by the KDJ11-B boot

programs.

ROM

programs

which run on the M9312 should work on the KTJ11-B. The M9312
compatible boot programs are implemented in from one to four 512
X 4 bit ROM's. Each ROM contains 64, l16-bit words of accessible
the last
code which are located in the first half of the ROM.
256 4-bit ROM locations are not used.

The KDJ11-B CPU Module can be configured to boot the system from
its self-contained boot programs, from the KTJ1ll-B Boot
one of
ROM facility, or a boot ROM option which resides on the UNIBUS.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
4.6.1 Boot ROM Installation

Digital - Equipment
meet
must
M9312 compatible Dboot ROMs
Corporation purchase specification 23-000A9-01 for 512 X 4
tri—-state PROMs. The ROM's must be encoded per the” Digital
Equipment Corporation specification K-SP-M9312-0-8.

programs.
boot
more
or
one
contain
A single ROM may
ROM's.
four
to
up
require
may
program
boot
Alteratively, a single
Dboot
each
keep
to
d
encourage
been
have
s
programme
However, ROM
program within a single ROM.

Table 4-6 presents the IC location of each ROM socket along
its

addres

with

range.

TABLE 4-6 ROM LOCATIONS AND ADDRESSES
——————--—————

«--—-——-——--———--———--—-——-———-————————-

ROM Number

IC Location

Addresses

T T B145
2

El44

17 773 000 thru 17 773 176

E143

17 773 400 thru 17 773 576

E142

17 773

17 773 200 thru 17 773 376
600 thru

17 773 776

4.6,2 ROM Addresses 17 773 000 - 17 773 776

thru
The KTJ11-B Boot ROM logic responds to addresses 17 773 000
subdivided
are
locations
As shown in Table 4-7 these
17 773 776.
the
into four, 64-word segments, each of which addresses one of
by
operation
read
a
to
responds
logic
ROM
The
four ROM sockets.
decoding a l16-bit data word from four successive locations in the
If an empty ROM socket is accessed,
4 bit ROM.
X
512
selected
the data word

4.6.3

ROM

read is

typically

161777.

Formats

This section summarizes the format
M9312

Specification K-SP-M9312-0-8.

information contained
Two types of

ROM formats

the
are

identified:
the format for one or
more
programs
contained
ia
single
ROM, and the format for one boot program contained in two

or more ROMs.
Specific
information
1is
given
on
headers and on the format of data within the ROM's.

4-49

the

program

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

4.6.4

Single

ROM Programs

ROM's which contain one or more programs in a single ROM conform
to the

following

format:

Each boot program must begin with a program header block as
described in subsection 4.5.2. The header block for the
first (or only) program must start at ROM Word Address O.

Word Address 24 of the ROM must remain reserved and be

Word Address 26 of the ROM must remain reserved and be set
(This location is required for systems which
to 000340.
reboot via the M9312 module and is not used by KTJ11-B

set

173000.

systems which reboot via the CPU module) .

Word Address 176 of the ROM must be a CRC-16 word

4.,

previous 63 words (omitting location 24 octal).

4.6.5

Multiple

for

the

ROM Programs

Some boot programs require more than a single ROM. The first ROM
would be formatted as described in Chapter 3. The continuation
ROM(s)

would have the following format:

The first word of each continuation ROM must contain 177776

Word Address 24 of the ROM must remain reserved and be

set
Word Address 26 of the ROM must remain reserved and be which
(This 1location 1is required for systems
to 340,
M9312 module and is not wused by KTJ11-B
the
via
reboot

octal.

set

173000,

systems which reboot via the CPU module) .

word for the
Word Address 176 of the ROM must be a CRC-16 locati
on 24).
previous 63 words (but omitting the word in

4.6.6 Program Header

As stated in section 4.6.4, the beginning of

must
as

contain a header section.

follows:

each

boot

program

This header section is formatted

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

The first word contains an ASCII identifier which consists
of two characters with a zero parity bit. The high and low
bytes contain the first and second characters respectively.
The characters are used by- the KDJ11-B Boot and Diagnostic
The
ROM programs to search for the selected boot program.
contain
bytes
these
of
both
that
KTJ11-B ROM codes requires
characters with ASCII octal values of 101 to 132 or 141
172

(A-2 or a-2).

The second word contains an offset from its address to the
start of the next program header. If the ROM contains only
one header, the second word, located in ROM Address 2,
contains 176, which points to start of the next ROM.

The third word address is the Power-up entry point for unit
zero, used by systems containing the M9312 to disable a
the boot
branch to diagnostics prior to running
point.
entry
this
use
not
do
systems
KTJ11-B

program.

The fourth word address is an alternative entry point for
unit zero, used by systems containing the M9312 to enable a
boot

branch to diagnostics before running the
KTJ11-B systems do not use this entry point.

The fifth word

contains

indicating

instruction located in the previous word.

wunit

program

for

the

The sixth word address is the entry point used by systems
for unit numbers other than zero.
containing the M9312

KDJ11-B uses this entry point after first loading the unit
number (zero or non-zero) into RO and then setting the PSW

Carry Bit (disabling the branch to M9312 diagnostics).

The seventh word contains the address of the Control/Status
Register of the device to be booted. It is used by the
instruction located in the previous word.

an instruction which saves the PC
The eighth word contains
branch to diagnostics on the next
which
in R4 for systems
uses this entry point when a non
KDJ11-B
The
instruction.
standard CSR address is passed in Rl.

The ninth word contains an instruction which branches to
M9312 diagnostics if the PSW carry bit is clear. KTJ11-B
systems always set the carry bit.

The tenth word contains

start of

the boot program.

10.

unconditional

branch

the

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

4.6.7 ROM Data Organization

Each 512 X 4 bit ROM contains 64,.16-bit words of accessible code
which are located in the first half of the ROM. Each l6sbit word
is stored in four successive ROM locations. Whenever the KTJ11-B
ucts the
ROM logic is addressed by a Data-In operation, it constr
4-7
Table
ns.
locatio
ROM
16-bit word from the appropriate

presents the
four nibbles.

location and polarity of bits within each group of
Note that bits 12, 11, and 10 are inverted, and

bits 08 and 00 are not stored in the expected order.
TABLE 4-7 ROM DATA ORGANIZATION

Data

03
07
11%*

02
06
10*

01
05
09

08
04
00

Bjt 2

Bit 3

Nibble Number 0
Nibble Number 1
Nibble Number 2

Nibble Number 3

Bit 1

Bit O

12*

* pata Word Bits 12, 11 and 10 are stored inverted
4.7

J11

MICRO ODT

J11 Micro ODT is entered anytime the CPU is halted by:

2.
3.

Placing the front panel toggle switch in the HALT position,
Executing a HALT instruction, if the halt mode is enabled,
and the system is in kernel, or

is setup to
Pressing the Break key, Iif the terminal panel
keylock
front
the
generate a Break character, and
switch

is set to ENABLE.

J11 Micro ODT allows

the

wuser

examine

and/or

change

any

page memory space.
location in the 22-bit CPU memory space Or I/0 start
a program,
In addition, J11 Micro ODT allows the user to:

step a program when
to reinitiate program execution and to single positi
on. Table 4-8
the front panel toggle switch is in the HALT

summarizes the J11 micro ODT commands.

BOOTSTRAP

TABLE

Slash

4-9

J11

MICRO

AND

ODT

DIAGNOSTIC

COMMAND

Opens

ROM' PROGRAMMING

SUMMARY

the

specified

location (n) and
its contents.
n
octal

Carriage

Line

Return

Feed

number.

<CR>

Closes

<LF>

Closes

and

then

Opens

open

location.

open

location
the next

opens

contiguous
Internal

outputs
is an

location.

specific

processor

Processor Status
Word

Opens the Processor Status

Designator

Must follow
R command.

Proceed

Resumes

Control-Shift-S

Manufacturing

Binary

the

Dump

Starts

program

the

execution.

program

execution.

use

only.

The

following paragraphs provide a detail description of each J11
Micro
ODT
command
specified in Table 4-9.
1In most cases, each
description is supplied with
an
example.
Note
that
operator
input is underlined.

When entering addresses or data,
they

will

When

entering

entered
A

(i.e.

filled

addresses

leading

zero's are not required,

ODT.
in

the

1I/0

page,

all

22bits

17776100).

?
will be printed whenever:
addresses
are
accessed
that
error is detected.

illegal

characters

result

are

timeout,

must

entered,
a

parity

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
4.7.1 / (ASCII 057) Slash

I/O device
This command is used to open a memory location,
word
status
processor
or
register,
processor
internal
register,
to specify a
register, and must be proceeded by octal digits
location,

or a tegister designator.

(i.e.
'In response to /, ODT prints the contents of that location
to
location
six characters) and waits for either data 33 for that
[/
The
<LF>.
or
<CR>
(i.e.)
be entered or a valid close command
the
of
contents
the
display
to
may be entered again immediately
previously opened

location.

Examples:

@1000/ 012737 <CR>

@100/ 000200 7422 <CR>

;Open memory location 00000100
;and deposit data (7422)
;close the location.

and

snew data.

(ASCII 015)

s The contents (012737) are
;displayed. <CR> closes the
:location without modification.

;Re-open the location and deposit

@/ 007422 6422 <CR>

4.7.2 <CR>

;Open memory location 00001000.

Carriage Return

location's
If a
This command is used to close an open location.
<CR> with
the
precede
should
user
the
changed,
contents are to be
If no change is desired, <CR> closes the location
the new data.
without altering

contents.

see previous examples.

Examples:

4.7.3

its

<LF>

(ASCII 012)

Line Feed

is
location
the open
except
This command is the same as <CR>
Memory
opened.
is
location
next contiguous
the
and
closed
are
registers
processor
and
2
by
incremented
addresses are
If the PS is opened it is closed and no new
incremented by one.
location

opened.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
Examples:

;Location 1000 is opened, the

@1000/ 012737 <LF>

<LF>.

with

;then closed

sThe <LF> caused the next

00001002 100200 0O <LF>

are

; The next location is opened

00001004 176100 <CR>

and

:to examine the contents
sthen closed with <CR>.

Internal Register Designator

or R (ASCII 122)

(ASCII 044)

the
In

;location to be opened and
;contents to be displayed.
;this case the contents
;changed the operator.

4.7.4 $

and

;contents are displayed,

Either character when followed by a register number 0 to 7 or the
If
S will open that specific processor register.
designator
PS
number
last
more than one number is typed after the R or §, the
typed

will

used.

NOTE

cannot

the

<4>)

(bit

The trace bit

modified
by
the user.
This is because ODT uses
the T bit for single-stepping.
The register
set
used
with the R command is determined by PS<11>.
If PS<11> is set to a 1, register set one will be
used.
PS<11>=0 register
set zero will be
used.
The SP (R6) that is used is determined
by
PS<15:14>.
4.7.5

This

(ASCII

command

entered

107)

used

immediately

start

before

program

the

execution

This

the LOAD
ADDRESS
and
START
switch
consoles.
The PC (R7)
is loaded with
if no data is entered), the following
zero:

PS,

System

Error

Status

the

HALT

the

command

position,

reentered

typed

MMRO<K15:13,0>,

and

address

Cache
is

the

typed

issued

the
PC

7777773000G

MMR3,

Cache

flushed
with

system
will

the

last

would

CPU

the

front

location

and

panel

switch

bits,

Memory

Floating

i.e.

Point

initialized.
in

the

ODT will

command

173000G.

other
PDP11
will be used
cleared
to

UNIBUS

The

sixteen

read

equivalent

initialized,

displayed.

4-55

Error

and

the

will

sequence
on
the address (0
registers
are

PIRQ,

Control

function

truncates

1if

the

user

Since

the

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
is disabled by the Go command, the
memory management unit
starting address is always in the lower 28 K words of memory (0 157776)

or the

I/O page.

Examples:

@1000G

:The program is started at location 1000.

@1000G

; The program is started with the Halt switch

@1000
4,7.6 P (ASCII

son. The CPU initializes registers and then
;halts without executing the first instruction.

:The PC is displayed and then the ODT prompt.

120)

Proceed

This command is used to resume execution of a program and
corresponds to the CONTINUE switch on other PDP11 consoles.
Program execution resumes at the address pointed to by the PC
The next instruction is fetched and executed, outstanding
(R7) .
interrupts will be serviced.

switch in the
If the P command is issued with the front panel
instruction
of
HALT position it 1is recognized at the end
will
(R7)
PC
the
of
execution and ODT is reentered. The content
ruction
single-inst
can
In this fashion, the user
be printed.
on the console
step through a program.and obtain a PC "trace"
terminal.

Example:

@R7/002464 1000 <CR>

¢sR7 (PC) is opened and the

scontents displayed. The new
saddress is entered in R7.

; The proceed command is issued

sand the program continues at

@p
001004

:The proceed command is issued
swith front panel switch in the
sHalt position. The PC is

;

001010

;location

1000.

;displayed.

;Etc.
;

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
4.7.7 S (Control-shift-S) Binary Dump

1is
oses by manufacturing and from
This command is used for testThepurp
ived
command is normally rece
not a normal user command.
It is
.”
inal
term
ole
not Dby the cons
another computer and
ole
cons
the
from
ed
issu
be
command NOT
recommended that thethis
code
23
I
ASCI
the
back
es
echo
console ODT
terminal because
oard to lockup, thus preventing data from
keyb
the
e
caus
may
and
on the screen.
being displayed

use
command from a terminal beca
There is no reason to issue this
ive
rece
to
nded
inte
the terminal is

and
it dumps the binary data
efficently
is intended to more the
and
comm
The
the ASCII data.
"/" and
g
usin
to
display a portion of the memory as compared
<LF> commands.
inals by
ly entered on many term
This command can be accident
LL" key
cases by the " NO SCRO
CTRL s or 'in many gene
typing CTRL S, cond
code.
23
I
rate the ASCI
itions normally
since all these
, it
exit
to
r
and, in orde
ly enters this commterm—
If the user accidentthe
a
"a"
type
and
- inal
user reset the
is recommended that
is
ODT
ole
cons
the
that
minimum of three times in order to insurecomm
and protocol 1is as
ready to accept commands ' again.

The

follows:

ands
1. After a prompt character, ODT receives a CTRL S comm
and echoes it.

of the serial 1line must
The host system at the other end
ting
rpreted by ODT as the star
send two 8-bit bytes s inte
byte
t
firs
The
ed.
echo
address. These two byte are not seco
bits
s
ifie
spec
byte
nd
the
specifies Dbits <15:08> andess.
16>
<21:
bits
ess
addr
Bus
<07:00> of the startina addr
to
icted
restr
is
nd
are always forced to 0, the DUMP commaThe starting address
the first 32K words of address space.

may be even or odd.

been received, ODT
After the second address byte has line,
starting at the
al
seri
outputs 10 bytes to the
t is finished
outpu
the
When
address previously specified.
ODT prints <CR>, <LF>, Q.

CHAPTER
SYSTEM

5.1

MAINTENANCE

INTRODUCTION

This chapter

error

removal

5.2

message
and

contains

troubleshooting

interpretation,

information,

diagnostic

and field replaceable unit (FRU)

replacement procedures.

TYPES

DIAGNOSTIC

The system supports three types

DECX1ll - provides
each
option
and

of diagnostic programs:

system tests to check the interaction
of
1isolate system failures to the subsystem

component

XXDP+ - provides tests that check
localize hardware failures to the

1individual
options
function level.

and

ROM Resident - CPU ROM-resident Start-up
diagnostics
test
various
functions
specific
to the system modules and PMI
bus, and isolate failures to the module or option level.

The.following XXDP+ diagnostic programs
are
available
to
test
various
functions
on
the three kernel modules.
To initiate an
XXDP+ diagnostic the system must first successfully complete
the
start-up

diagnostics.

OKDA??

(KDJ1l1l-BF)

OKTA??

(KTJ1l1l-B)

MAINTENANCE

SYSTEM

is
time
(Run
(MSV11-J)
VMJA??
minutes depending on memory size.)

approximately

The "??" at the end of
the
diagnostic
name
assures
latest diagnostic version is executed when called.

To load and execute a
diagnostic,
1issue
the
For example:
followed by the diagnostic name.
.

RUN

(R)

that

the

command

<KCR>

OKDA??

a
during
executed
are
The start-up diagnostics, listed below,
of
evaluation
quick
a
provide
They
system power up or restart.
the

three

kernel

modules.

The start-up diagnostics check the following system functions:
Processor:

Verify

CPU

and

FPA

functionality

and

test

Disables
communications between the CPU cache and the CPU.
(PMI)
the main
all data paths between system devices and
but

memory,

the

not

CPU

cache memory.

Tests the main memory using the PMI protocol.

Main Memory:

PMI
its
adapter,
UNIBUS
the
Tests
Adapter:
UNIBUS
and control paths with the
addressing
and
communication,
UNIBUS

disabled.

A failure at any point during these diagnostics halts the testing
and:

Displays an error code and an error message on the

Displays

terminnal

(if connected).

error

code

the

front

panel

console

START-UP

TEST

display.

Displays

the error code

in the CPU module diagnostic LEDs.

Normally, the system displays the same error information
in
all
three
locations.
If the console terminal is not working, refer
to the START-UP TEST display.
If neither
1location
1is
working,
refer

5.3

the

CPU module

CONSOLE TERMINAL

LEDs.

ERROR MESSAGE

FORMAT

A typical console error message is shown in Figure 5-1.

SYSTEM

Testing

Memory
9 Step

progress

Please

Size is 1024
memory test

Bytes

Step
Error

wait

Memory

See

CSR

Error

troubleshooting

Error

PC=

173436

documentation

PCR

page=

Program

listing

address=

060000

052525

100000

172100

040000

172300

Par3

Command

Rerun
Loop

Map
a

The
a.

command

Console

console
An

test
memory and

I/O

page

then

the

RETURN

error

5-1

probable

"See

Error
PC

ERROR

message

code

5-2

contains

following

octal

number

codes,

test

this

that

failed.

lists

the

error

causes.

lists

the

this

error

messages

and

documentation"

unexpected

the

traps,

5-3

start-up

descriptions,

description

their

and

descriptions.

specifies
ROM

program

the

message.

line - this address line
PC=), the page number in the

information:

one-line

address

case

EXAMPLE

the

troubleshooting

(Error

the

DISPLAY

Description

the address to reference
listing address=)
In

key:

MESSAGE

test

description
error.

Table

5-1

error

the

press

Error Message

error

Table

010000

test

diagnostic

172344
=

FIGURE

5.3.1

015436

Description

Type

MAINTENANCE

error

(PCR

the
error
page=), and

1listing

address

(Program

the

SYSTEM

MAINTENANCE

address

following

unexpected

the

instruction

which

caused

the

trap.

The content of R0O-R6 of register set 0, and the content
of
kernel
PAR
3.
The
tests
do
not
use
register set 1.
Register set 1 is used mainly by ROM code support routines.
For some

tests

the system displays

the

expected data, and the received data

failing address,

(bad data).

the

A command line which
describes
user-selectable
commands.
To
execute
a
command enter the associated command number
(e.g., 1, 2, etc.) followed by RETURN.
The commands are:

Rerun the test.

If the test passes

the

ROM

code

will

continue testing.
If all other tests pass, the ROM code
will display the total number of errors and enter dialog
mode regardless of the mode selection in the EEPROM.
Loop on

test.

This

option

causes

the

ROM

code

continuously
loop on the test that failed.
These loops
are generally very large and are not intended to be used
as

scope

loops.

The test runs until an error occurs or
end-of-test
has
been reached.
1In either case, the test is started again
and continues to loop until the user types CTRL C at the
console.
At
this point, the ROM code will display the
total
number
of
errors
and
the
total
number
of
successful passes if any.
Both the error counter
and
the
pass
counter
have
a
maximum
value of 65535.
If either counter reaches this
value the count will not overflow to zero, it will
stay
at

this

value.

Map memory and

I/0O page.

This

command

normally

used

if a memory error occurs.
If a memory is not configured
properly the MAP command may point to where
the
memory

actually is.
In

multi

memory

system

which

one

the

memory

fails this command can be used as a method of physically
identifying the failing memory, if it has a CSR.
This command is only available when the
bus
on.
The
command is not available for tests
76

through

56.

1is
turned
(or codes)

SYSTEM MAINTENANCE

This command allows the user
Advance to the next test.
and continue. This command
test
failing
to bypass the
generally
that are
errors
for
up
show
only
will
non fatal.

considered

If the error is fatal and field service would 1like to
bypass the error it is possible by typing CTRL O, 4 and
RETURN, and the command will be executed.
CAUTION:

wuser
all
unless
bypassed
Errors should not be
otected.
write—pr
or
removed
been
has
software

At this point the ROM code flushes it's input buffer of any
previously typed characters and waits for input from the user.
TABLE 5-1

ERROR CODES, TEST DESCRIPTIONS AND PROBABLE CAUSES

PROBABLE
CAUSE

ERROR
CODE

TEST
DESCRIPTION

Initially set to this
value

up.

power

The halt switch is ON at power
up.

BGn or NPG line

A UNIBUS

is open and SACK is being

asserted by the bus.
Check MDM module.

All grant

cards must Dbe

installed.

Terminator is faulty.
Power supply

First CPU

Turn MMU on.
and

CPU

MMU

M8190

Run MMU

M8190

tests,
tests

tests.

Turn on PMI and look
at the UBA RESTART bit.
Then

turn

off

PMI.

M8190,

M8191

faulty.

SYSTEM MAINTENANCE

TABLE 5-1

(Cont)
PROBABLE
CAUSE

TEST

——u—m—‘-———_———m_—n@———————-—

m:-xmu—n——-_—a-sena-—-_gn--——————-———-——————-———

Power up

NOT A FAILURE - Selected

to ODT.

Mode is ODT in EEPROM and
the system is in (J11)ODT
M8191

Power up to 24/26.

M8190,

EEPROM checksum tests.

EEPROM accidentally written,

restore data using Set up mode
commands, verify W40 installed

on M1890 module.
70

CPU ROM checksum and PCR

M8190

Miscellaneous CPU and EIS

M8190

tests.

Console SLU test 1 check for each register's

M8190

response

Console SLU test 2 transmit and receive data

M8190

Console SLU test 3 -

M8190

in maintenance mode.

check interrupts and
errors in maintenance
.
mode

Test MMU aborts.

M8190

Stand—-alone mode CPU

M8190

cache

tests.

Clock

test.

M8190

Clock from power supply

Floating Point Processor.

M8190

Unused.
—-—u—_mw——————_——nuw

—————————————————————————————— q-cu—c-—bwam—:

5-6

SYSTEM

TABLE

ERROR

TEST

CODE

DESCRIPTION

5-1

(Cont)

PROBABLE"

CAUSE

Exit stand-alone mode.
Check location of address
17760000for timeout.

M8190

UBA

M8191

response

test, check UNIBUS through
DDR for hung lines.

M8191

UNIBUS

failure

M8190
54

Memory

size

Check

memory

location
52

test.

UNIBUS

present

failure

PMI

memory

test.

PMI

memory/M8190

PMI

M8190

word

memory

Cache testing using
memory
.

Memory

tests

test

byte

Data

Memory

parity/ECC

Memory

address/shorts

tests.

test.

45
44

UBA

ROM

UBA map

path

UBA

PMI

memory

PMI

memory

test.

M8191

registers

data

M8191

unmapped
cycles test.
mapped

diagnostic

test.

UBA

floating

test

using

nostic

memory

response

test.

cycles

PMI

tests.

address/data

mapped

cycles.

diag-

M8191

MAINTENANCE

SYSTEM MAINTENANCE

TABLE 5-1

PROBABLE
CAIJSE

TEST
DESCRIPTION

ERROR
CODE
40

(Cont)

UBA address overflow test. M819l1
M8191
UBA cache data test.
PMI

memory

UBA cache LRU (Least

M8191

UBA cache floating

M8191

Recently Used)

test.

address test in TAG
store.

UBA cache parity error

M8191

UNIBUS memory data path

UNIBUS memory

detection testo.

test.

M8191

UNIBUS memory parity

UNIBUS memory

UNIBUS memory address/

UNIBUS memory

logic

test.

shorts

test.

NOTE

s 25, 22 and 6, codes
With the exception of error codelem
indicators and are
30 through 1 are bootstrap prob

not diagnostic errors.

, tape, etc.)
Some bootstrap problems (e.g.., diskrs
may be indimay be corrected by the user. Othe
cators of errors in the device being bootstraped
30

Test Exit Routine

Unused

wacflm--Qn

-am@@-nw@wufl‘gwa‘g@QGGfi

SYSTEM MAINTENANCE
TABLE

ERROR

CODE

5-1

TEST

DESCRIPTION
-

Air mover and voltage
regulator

test.

ED W WED N WD D M CED WA TR D G WIS CHR TS CHE A WL D MR

S W W W G

Cabinet blower
Box

fans

regulator module

H7213

MLM module not

installed

No memory module(s)

system.

Unused

XON not received after
XOFF,

To correct,

type

CTRL Q at the console.

Console terminal not ready
due to XOFF signal received
from terminal while attempting to print a message.

This is normally not considered a failure, because
the condition could be operator error. If the oper-

ator has typed CTRL S without following with CTRL Q
or the terminal is not
ready, (e.g. could have run
out of paper).

Console SLU transmit

ready bit
Drive

not

M8190

set.

error.

The device that the user is
attempting to boot is displaying an error code in its
error register. Verify that
media is in good condition
and

Controller

error.

bootable.

The UNIBUS

controller for

the device the customer is

attempting to boot is
displaying an error code:

SYSTEM MAINTENANCE

PROBABLE

TEST

CAUSE

a-s———c—:—cs—e-——————————

-n———————--nm—_-_———»—-—-nu-ne—c:—————-—————:———-

in its control and status
register (CSR). Ensure
that the NPG jumper was
removed if the device is a
DMA controller. Consult
the devices technical

manual for more
information.
17

Invalid

The mnemonic typed in for
the boot device is either
incorrect or the boot rom
for that device is not
installed .Go to the
dialog mocde and "LIST" the

device.

valid

unit

Invalid

Non-existent

Non-existent
controller

devices.

The unit number after the
mnemonic is not within
acceptable range for that
device. See that devices
technical manual for help.

number.

The drive number the user

drive.

is trying to boot
not on the 11/84.

The

controller

No disk present or drive
is not loaded correctly.

- cm - on wo e

present.

Non-bootable media
the

o - o

caD

s o

e oo D
" an

D TR D e

D D

No media

de-

) D

addressed

installed.

drive

LOAD button not

the

in.

The bootstrap data from
the device does not conform to the boot block
specifications. Ensure
that media is bootable.

tape

drive

drive.

B e

the

vice the user is trying to
to boot from is not on the
UNIBUS or is
incorrectly.

tape

for

from is

B I

D CED XD ORI

O WP W) WD

P IO D WD WD CED D Eb GEP GNP GED GHR ek D

D W W

SYSTEM MAINTENANCE

TABLE 5-1

(Cont)

PROBABLE

TEST

ERROR

CAUSE

DESCRIPTION

CODE

bootable. Change Setup
mode

to accept

non-standard boot blocks.

Drive not ready.

No media present in the

drive or the disk drive

has not completed its spin

up function.

Console disabled.-

Unused-.

Dialog mode.

Self explanatory.

The system is in dialog mode
and waiting for input from
the console terminal to
rewind.

UBA ROM boot in progress.

May take a few seconds.

EEPROM boot in progress.

May take a few seconds.

CPU ROM boot in progress.

Blank

May take a up to 5 minutes
for some devices.

Program control has been

transfered to: a secondary
boot,

an EEPROM boot,

UBA/M9312 boot.

or a

SYSTEM MAINTENANCE

TABLE 5-2 START-UP DIAGNOSTIC ERROR MESSAGE DESCRIPTIONS

DESCRIPTION

)

ERROR MESSAGE

M8190 CPU Cache Error

CPU cache logic error

M8190 FP Error

CPU Floating point error

M8190 CPU ROM Error

CPU ROM logic or checksum error

M8190 EEPROM checksum

CPU EEPROM logic or checksum error

Error

M8190 clock Error

CPU clock logic or power supply
clock

error

M8190 CPU Error

Other CPU errors

UNIBUS signal Error

A UNIBUS signal is always asserted

No memory in location 0O

Memory failed or is addressed

Memory Error

General memory test errors

Memory CSR Error

Memory errors during parity or
ECC

Other UBA errors

UBA Error

- This

Unexpected trap to

D T

is a general error message

that occurs during any unexpected

location

testing

UBA Cache error

Error

M8191 UBA Cache
M8191

incorrectly

traps. The address of
follows this message.

D D D D

O S

D WD o0 ATD CED D T

e D D S

D WA

D D

T e T

) D D D D G

the

trap

D 0 e G S0 S0 D W G SR e e

s o wes o S e

5.3.2 Unexpected Trap and MMU Error Code Descriptions

Figure 5-2 shows

example

the

error

code

and

message

The error number of
displayed when an unexpected trap occurs.
unexpected traps is always the current test number plus 100.
NOTE

Operator input is

wunderlined

examples.

5-12

the

following

SYSTEM MAINTENANCE

In the example the error code (or test number) is 62. The actual
The Start-up Test display will
error code is read as 162.
two-digit display.
a
only
is
it
display only 62 since

Unexpected traps are always considered fatal errors.
Testing in progress - Please wait
Error

162

Unexpected trap to location 250 MMU
See troubleshooting documentation

Updated PC= 173436
RO = 101365
R4 = 101367

PCR page= 15 Program listing address= 015436

Command

Description

Rerun test
Loop on test

R2 = 177746
R6 = 172276

Rl = 076410
RS = 000250

Type a command then press

FIGURE

5-2

R3 = 177744
Par3 = 052400

the RETURN key:

UNEXPECTED TRAP ERROR EXAMPLE

E
letter
single
For codes 76 and 75, the ROM code displays the
message
the
After
5-3.)
Figure
(See
followed by the test number.
only
The
is displayed, the ROM code will not except any input.

option

for

the

user

FIGURE

5-3

restart

the system or repair the

problem.

5.3.3

EXAMPLE

OF TEST

ERROR

Boot Program Error Codes/Messages

Error codes 21 through 10
with
the
boot
programs

(described in Table 5-1) are associated
for
disks, tapes, and DECNET devices.
5f13

SYSTEM MAINTENANCE

ROM-resident Dboot
These errors are applicable for all areCPUwritt
to pass these
programs, and any EEPROM boots thats 14, 16, en
and 17 apply to
errors back to the CPU ROM. Only error
UBA or M9312-type ROM boots.

Figures 5-4 and 5-5 show examples of an error. from a boot progr

when the BOOT command is used in Dialog mode

Test.
Commands are Help, Boot, List, Setup, Map and
<CR>
DL1
B
key:
N
RETUR
the
press
Type a command then
Trying

DL1

Message

No disk present, or drive is not loaded correctly
Description

Command

Reboot

Go to Dialog mode

Type a command then press the RETURN key:
FIGURE 5-4

BOOT PROGRAM ERROR EXAMPLE

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: B DL3 <CR>
Trying DL3

Message 15
Non existent drive

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key:
FIGURE 5-5

BOOT ERROR MESSAGE EXAMPLE

sequence all boot
When the ROM code enters the automatic boot pass
through the list
first
the
on
essed
error messages are suppr
booted on the
ly
ssful
succe
is
e
devic
no
of boot devices. If
boot sequence
first pass the ROM code will restart the automaticand
display all
and try to boot all of the selected devices again
applicable error messages.

SYSTEM

MAINTENANCE

When the ROM code has failed to boot any of the devices

automatic boot list, Dialog mode is entered.

the

selected

Figure 5-6

shows an example of a boot error display when the automatic boot
sequence failed to find a bootable device and Dialog mode 1is
entered.

Testing in progress - Please wait
Memory Size
9

Step

memory

1024 K Bytes

test

2 3456 7 89

Starting automatic

boot

Trying DUO

No disk present, or drive is not loaded

Trying DU2
Trying DU3

Drive not ready
Drive Error

Trying DUl

Trying DLO

Non bootable media in the drive

No disk present, or drive is not loaded

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key:

FIGURE 5-6 AUTOMATIC BOOT ERROR MESSAGE EXAMPLE
5.4

SYSTEM TROUBLESHOOTING AIDS

The system provides the following troubleshooting aids:
1.

LED monitors

Voltage

test points

Monitor

logic with audible alarm.

Figure
The LEDs are located on the front panel and the modules.
Figure 5-8
5-7 shows the front panel monitor LED labeled DC ON.
and
test points
The
LED.
shows the location of each module

monitor logic with alarm are located on the MDM module.
5.4.1

Front

Panel

The front panel indicator DC ON monitors the DC

output

voltages

the main power supply.(See Figure 5=7.) When the front panel
on
keylock switch is in the ENABLE, SECURE, or STANDBY positions, ac

power is supplied to the power supply.
5-15

SYSTEM MAINTENANCE

the

If the DC ON LED is OFF, the probable cause is one of

supply

regulators.

regulator

Each

located on the MDM module.

1]
dlilgli

power

LED monitor
has a specific

uane

SECURE

STANOSY

PDP-11/84
C

- RESTANT

Docon

b nun

L Lt
!_1
C O satreny
.
\ STANT-UP TEST
(@ LT

FIGURE

5-7

SYSTEM

FRONT PANEL

5.4.2 MDM Module

The MDM module provides the following troubleshooting aids:

voltages

LEDs that monitor most power supply

Test points for checking power supply voltages.

2.,

Blower/fan rotation monitoring logic.

(see

Figure

2-8).

Figure 5-9 shows the location.of the MDM

module

LEDs

test

and

LEDs D1 through D5 each monitor one or two power supply
points.
Loss of a voltage turns the associated LED off.
voltages.

checked
The tolerance for each voltage should be within +/- 10%,
If a voltage is found
on the test points located above the LEDs.
to be out of tolerance or not present, one of the power supply
regulators specified in Table 5-3 is the probable fault.
If the
The rotation monitor logic indirectly checks the +12 Vdc.
monitor
the
pulse,
sed
rotation-ba
a
send
to
fail
blower/fans
logic causes an audible alarm to sound and powers down the system
one

minute

later.

SYSTEM MAINTENANCE

TABLE 5-3 POWER SUPPLY REGULATOR FAULT ISOLATION

H7200

in H7202-KA

H7213

in H7202-KA

H7211

+5V EXPANSION POWER SUPPLY

H7200

in H7202-KB

+/-15V EXPANSION POWER SUPPLY

H7211

in H7202-KB

+5V MAIN

POWER SUPPLY

+5VBB AND +12V BLOWER/FAN
+/-15V MAIN

POWER SUPPLY

H7202-KA

CARD CAGE

TOP FOR CABINET
REAR FOR BOX

MOM

MDM (\7677)

wnnnnnnn-nn

D1 = +5V (MAIN POWER SUPPLY!

D2 = +5V BB AND + 12V (BLOWER FANS!

D3 = +15V AND - 15V (MAIN POWER SUPPLY}

D4 = +5V (EXPANSION PQWER SUPPLY)

05 = +15V and - 15V (EXPANSION POWER SUPPLY}

D1= ERROR LED

DIAGNOSTIC LEDs

DCOX POWER LED (GREEN:!

DIAGNOSTIC LEDs

/‘

-~
L=

IGREEN)

MINIMUM LOAD

MODULE (M7556) TM|}

||| el
s
|

LS8

D2 = +5V BB POWER

02= .15V (OFF)-

D1 = +5V B8 MAIN POWER SUPPLY (RED!
MSV11-J8:JC MEMORY (MB637-8A/CA)
KDJ11-8F (MB190}

f—MINIMUM LOAD MODULE (M7558)
—02= <15V (GREEN)

/.-—-01 = +5V MAIN POWER SUPPLY (RED)

FIGURE

WYY
YY el

5-8

MDM MODULE

LED

LAYOUT

SYSTEM MAINTENANCE

MDM

Module

Notes

¢ontains

system

the

An M7677-YA MDM must be used

I1f the MDM is the suspected problem, check the voltage test

H7231-E BBU.

points

the

and

NPG

module replacement.

configuration prior to

pack

switch

’

(See Figure 5-9.)

Loss of a voltage turns off the associated LED.

the
check
If an LED indicates 1loss of a voltage,
ement.
replac
tor
requla
corresponding test point prior to
switch
The setting of the NPG (non processor grant) select
switch
NPG
Each
.
status
NPG
pack is used to select
Figure
12.
h
throug
5
slot
ane
backpl
corresponds to a CPU
5-9 shows the location and slot number of the each NPG
switch.

For non DMA devices a CPU backplane slot the NPG switch
should be in the ON position. A common NPG problem occurs
when DMA devices are installed with the NPG switch ON
(arbitration mechanism is bypassed).

This causes an error code 20 when attempting to

device,

indicating

error.

controller

problem, turn OFF the NPG switch for that slot.

. 18: -ouv c.;o 58106/
(10 P

St[:"

’

{20 iy

g;] "

02 OV

go0Qo0 Oksu NUTE

O& AUDIULE
ALARM

SLOV
NUMSER

08000008

or¢

NG
o

Ng
PACK

wum;n

ROTE
-5 IMAIN FOVEH SUPPLY!

A 't ANS)
07 - +§VEB ARD « 12V (BLOWE
03 + +15V MAIN POLIE R SUPRLY
04 <5V tF RPANSIUL PUWE R SLIPBL V)

1%V (£ XPANSI()'. POWE R SUWPLY)

FIGURE 5-9 MDM MODULE LAYOUT
5-18

boot

that

To correct the

SYSTEM MAINTENANCE

5.4.3 KDJ11-BF CPU Module

The KDJ11-BF module provides:

A green POWER OK LED, indicating that dc power to

Six red error code LEDs, which correspond to
diagnostic error codes (see Figure 5-10).

module

the

CPU

is present.

front

In addition the error codes appear on the

the

Start-up

panel

Start-up

Test display. For example, if an error code 51 occurs during the
start up diagnostics, 51 appears on the front panel display and

the corresponding CPU module LEDs light (that is, 1 (LSB), 4, and
6).

suspected

If the KDJ11-BF module is the

module replacement,

assure that:

problem

and

prior

The module jumper configurations are as specified in Figure

The

5-10,

and

are OFF.

DIP switches

CONNECTOR
. FOR CABLE TO
BAUD AATE SELECT

0IP SWITCH FO
BAUO RATE SELECT AND
BOOT STRAP CONTROL
§/8 OFF

AND TWO-DIGIT DISPLAY

QE*\ 4N

CONNECTOR

FOR CABLE TO ]

CONSOLE SLU

ROM

{HY BYTE) =]
15:

wio

P16

(LO BYTE) =]

EEPRAOM

REMOTE SWITCH

1 CONTROL CONNECTOR

(A-SERIES)
:fl\. FPII1-A
40-PIN SOCKET (P-SERIES)

D €53 ..
|

¢)

DCJ1Y CPU HVPR'D
£80

GATE

TP40 00 o TPa2

/ Q?

Jo TP10

wao

(SEE NOTE 1)

DIAGNOSTIC

LEDS (RED}

LS8 !

[=5] I/llfl'l(ll/

5:08

07:00

DCOK LED
(GAEEN)

TPat

€3

GATE

. ARRAY

(SEE NOTE 2}

w20

O (I

| TP200{J0 TP210TP22

NOTES: 1. WHEN 24-PIN EEPROM IS USED. INSERT PIN ONE OF EPROM IN PIN 3 OF SOCKET.
2. WHEN 2K EEPROM (S USED. TPAQ IS CONNECTED TO TPAY.
WHEN 8K EEPROM IS USED. TP41 IS CONNECTED TO TP42.

FIGURE 5-10 KDJ11-BF JUMPER AND SWITCH PACK LOCATIONS
5.4.4

MSV11-JB/JC

Memory Module

The quad-height memory module provides:

A red LED to

indicate uncorrectable errors
5-19

MAINTENANCE

SYSTEM

A green LED to indicate the presence of +5 Vdc

Two switch packs for starting and CSR address selection

Four factory-set

jumpers.

LEDs,

both

check

problem,

If the module is the suspected

the

settings, and jumper configurations prior to module
See Figure 5-11 for LED, switch pack, and Jumper

switch pack
replacement.
layout.

= -

we w3 03

oo
FIGURE

The
1 -

5-11 MSV11-JB/JC LED/SWITCH

PACK/JUMPER LAYOUT

starting address is configured using switch pack S1l, switches
8 Table 5-4 lists the switch settings, starting addresses and

decimal number.
The
top
sixteen
entries
apply
to
the
1MB
(MSV11-JB) memory and the bottom sixteen entries apply to the 2MB
(MSV11-JC)

memory.
TABLE

—

CED

D WD

SWITCH SETTING*
1 23456 78

0
000O0O0CO0O
0000O0O0O01
0 000O0O0OT1O0
00000011
0000O01O00O
00000101

5-4
G

MSV11-JB/JC
D

D e

STARTING
D

STARTING
ADDRESS (OCTAL)

00000000
00040000
00100000
00140000
02000000
00240000

R W

ADDRESS

oD S

D GND

D SED

DECIMAL
(K bytes)

0
8
16
24
32
40

XD e

SYSTEM MAINTENANCE

TABLE'5—4 (Cont)
SWITCH SETTING*

STARTING

00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
0 000X XXX
0001 XXZXX
0010XXXX
0011 XXZXX
01 00XXXX
0101 XXXX
0110XXXX
0111 XXXX
1000XXXX

00300000
00340000 |
004000005
00440000
00500000 |
00540000
00600000 ;
00640000 !
00700000 |
00740000 !
00000000-00740000

ADDRESS (OCTAL)

1 2 7 4 56 7 8

1011XXXX
1100XZXXX
1101 XXXX
1110XXXX
1111XXXX

13000000-13740000
14000000+14740000
15000000-15740000
16000000+16740000
17000000 17740000

=
=

Switch

off

X = Switch

1152-1272

1280-1400

12000000-+12740000

1010XXXX

48
56
64
72
80
88
96
104
112
120
000-120
128-248
256-376
384-504
512-632
640-760
768-888
896-1016
1024-1144

05000000-05740000

1 001X XXX

(K bytes)

00100000-01740000
02000000-02740000
03000000-03740000
04000000-04740000

06000000+06740000
07000000-+07740000
10000000+10740000
©11000000+11740000

DECIMAL

1408-1528
1536-1656
1664-1784
1792-1912
1920-2040

can be either on or off

The CSR address is configured using switch pack $2, switches 1

Each successive address is the
The base address is 17772100.
4.
possible CSR addresses.
sixteen
all
lists
Table 5~5
base plus 2.
TABLE

CSR ADDRESS SELECTIONS

5-5 MSV11-JB/JC
G

WP SED TED WD GEN

IR GED GED GRS MR AND ED

SETTING

0000
0001
0010
0011

GED WED

D M) AP WEE GNP GNP

D WD

CSR

ADDRESS

(OCTAL)

17772100
17772102
17772104
17772106

SYSTEM MAINTENANCE
TABLE

S2 SETTING

1 2 3 4

5-5

(Cont)

CSR

ADDRESS (OCTAL)
17772110
17772112
17772114
17772116
17772120
17772122
17772124
17772126
17772130
17772132
17772134
17772136

0
1
0
1
0
1
0
1
0
1
0
1

1MB ({MSV11-JB)
The dumper configurations for the
Assure
memory modules are different.
(MSV11-JC)
Table 5-6.
factory-set jumpers are as specified in

JUMPER(S)

2MB
the

JUMPER CONFIGURATIONS

TABLE 5-6 MSV11-JB/JC
MODULE

and
that

POSITION

DESCRIPTION

meviloge T
wl

OUuT

256K Dynamic RAMs

Half-populated module

Vertical

Reserved for future use

w3,w4
MSV11-JC

ouT

256K Dynamic Rams

ouT

Fully populated module

Vertical

Reserved for future use

W3,wW4

5.4.5 KTJ11-B Module

support M9312 compatible
The module provides four sockets to cted
problem, check the ROMs
suspe
the
If this module is
ROMs.
Figure 5-12.
and their orientation as shown in

5-22

MAINTENANCE

SYSTEM
0312 TYPE OPTION ROM SOCKETS i4}

mOM

Ewes

177173200 17773378

- 17773576
17773400

Eve3

] e

ADDAESS

17773000- 17773176

£r144

SOCKET

17773600-177737%¢

e
Pin

NO.1

FIGURE 5-12 KTJ11-B ROM SOCKET LOCATIONS

5.4.6

Minimum Load

Module

The

MLM modules provide
minimum
under the following conditions:
e
cl

supply

regulator

An MLM is inserted in CPU backplane slot 3 (rows C
ensure
a
regulator.

power

MLM

minimum

inserted

to
ensure
regulator.

minimum

expansion

installed,

backplane

(rows

current

MLM

drain

CPU backplane
current
?

drain

backpflane

slot
of

370

(DD11-CK

12
mA

from

(rows
from

and

the

DD11-DK)

!inserted

to ensure

a minimum current

and

1loads

+5VBB

=15

the last slot of the

370 mA from the -15 Vdc regulator.

drain

NOTE
An MLM

not

required
in the

(CPU
or expansion) if the
the minimum lA of -15 Vdc
When

not

required,

the

load

last backplane

installed

modules

options

must

two

LEDs

slot
draw

removed

from

the

indicate

the

backplane.
As

shown

Figure

5-13,

presence

and

VBB

the

-15

MLM

has

Vdc.

5-23

SYSTEM MAINTENANCE

RED

GREEN

]
CYRIY

FIGURE 5-13 MINIMUM LOAD MODULE LAYOUT
5.5 FIELD REPLACEABLE UNITS

Table 5-7 lists the field replaceable units (FRU) .
TABLE 5-7 FRU DESCRIPTIONS
—---n—m—‘m_——m o -

m@ma-amma———pm—-—-—————————————————

PART NUMBER

DESCRIPTION

M7677-YA*

Monitor Distribution Module (MDM)

M8191

KTJ11-B, UBA Module

M8190~AE

KDJ11-BF, CPU - FPA Module

M8637-BA

MSV11-JB, 1 Mb ECC Memory Module

M8637-CA

MSV11-JC, 2 Mb ECC Memory Module

M7556

Minimum Load Module

M9302

Terminator Module

70-20650-01

CPU Backplane
muacauwamamgmamua@

- mau@gmummwmmnmmu——————c-—--—m—

SYSTEM MAINTENANCE

TABLE 5-7 (Cont)

————————--------———----—--—-—-—-—

H7202-KA

Power Suppiy

H7202-KB

Power Supp;y

54-16508

Console SL? Board

H7211-B**

+15,

H7213-D**

+12V,

H7200~-C**

+5V Regulaior Module

70-21888-01

Front Panei Assembly

12-22001-01

Blower

12-22271-02

Fan

877-D

Power Cont?oller 120V

877-F

Power ContLoller 240V

70-21116-01

Circuit

breaker assembly

H7231-E*

Cabinet

Battery

H7231-F*

Box

DD11-CK

4-slot

Backplane

DDll
-DK

9-slot

Backplane

-15V

Regulator Module

+5V Regulator Module

OPTIONS:

installed

the

BBU

option.

Specifies

5.6

MODULE

The

following

Set-up

H7231-E/F

subsections

Table

and

Unit

the

Unit

system contains

minimum etch revision.

REMOVAL/REPLACEMENT

removal

Back

M7677-YA must

module

Battery

Back

PROCEDURES

provide

replacement

selection

the

general

procedures.

procedure.

5-25

module,

and

the

CPU

Included

the

CPU

SYSTEM

MAINTENANCE

5.6.1 General Module

Removal/Replacement

module)

To remove any module listed in Table 5-7 (except the CPU
use

the

following procedure.

CAUTION

static sensitive.

Modules are

2.,
Always wear a properly
when handling modules.

Modules

they

anytime

must

their shipping

placed

removed

static

mat

a backplane or

from

static bags.

Open the cabinet front and rear doors using the hex key, or
slide

are

connected ground strap

the

box out of

the

rack.

Turn either:
a.

breakers

power

The cabinet power supply and
The

box

OFF,

breaker OFF.

circuit

the AC power cord

from the outlet.

Remove

Assure the ground strap is properly conneéted.

Remove all

Pull

cables

circuit

controller

from the module and label each one.

the module handles

out and slide

the module

from

the

backplane.

Place

the

module

the

static

mat.

This completes the removal of a module.
reverse

the

reinstall

module

procedure.

5.6.2 CPU Module

Removal/Replacement

replacement
The
case.
special
a
Replacing the CPU module is
module Setup Features must be confirmed, and if necessary revised
to the original CPU parameters and selections.

5=26

SYSTEM MAINTENANCE

have

should

user

the

installation,

During the initial system

eets supplied
recorded the setup feature selections on the J worksh
this manual.
of
ix
in the Installation Guide or in Append
original CPU
the
of
ions
select
the
Retrieve this form. Compare

module (as specified on

the

Confirm and/or revise the
procedure.

features

setup

the

with

worksheets)

defaults of the replacement module.

using

the

factory-set

following

NOTE

Dialog and Setup mode commands are

described

1in

subsections 4.2 and 4.3.

properly connected ground strap remove the
module from the backplane as specified 1in

Wearing a
defective

subsection 5.6.1.

Ensure that the replacement module jumper configurations
and DIP switch settings are as specified in subsection
5.4.3.

the

replacement

CPU

module

described

1Install

Set the FORCED DIALOGUE switch to ON.

Power up the system, and ensure that it passes the

subsection 5.6.1.

startup

diagnostics.

On successful completion of the startup diagnostics, the
(See Figure 4-3.)
system enters Dialog mode.
S <CR> on the console
Enter Setup mode by typing:

If the customer chose the factory defaults perform steps

Type: 8 <CR> to initialize the setup table to the factory
default values. Answer 1 <CR> to the ROM code prompt: Are
(See Figure 4-22.)
you sure? O0=No, l=Yes.

10.

Type:

9 <CR> to copy the

11.

Type:

2 <CR> to display the Setup Table parameters.

terminal.

and 10.

Answer:

(See Figure 4-14.)

Otherwise begin at step 1ll.

Setup

Table

1 <CR> to the ROM code prompt.

into

the

EEPROM.

(See Figure 4-23,)
(See

Figure 4-16.) Compare the replacement module parameters to
the original selections; revise as required.
5-27

SYSTEM MAINTENANCE

12.

Type: 3 <CR> to display the Translation Table parameters.
(See Figure 4-17.) Compare the parameters to the original
selections;

13.

Type: 4 <CR> to display the automatic boot selections.
(See Figure 4-20.) Compare the selections to the original:;
revise as

14.

revise as required.

required.

Type: 6 <CR> to display the CPU switch boot selections.
(See Figure 4-21.) Compare the selections to the original;
revise as required.

15.

Type: 9 <CR> to copy the revised parameters and selections
into the EEPROM. (See Figure 4-23.) Answer: 1 <CR> to the
ROM

16.

code

Type:

prompt.

1 <CR> to exit Setup mode and return to Dialog mode.

This completes the CPU module replacement and setup procedure.
5.7 POWER SUPPLY REMOVAL/REPLACEMENT

Both the cabinet and box products have a H7202-KA power supply
The regulator boards and
containing three regulator boards.
regulator boards are
the
that
power supplies are FRUs. Assure
not defective prior to replacing a power supply.
5.7.1 Cabinet Power Supply Removal/Replacement

To remove a power

supply

regulator

supply, use the following procedure.

board

the

main

power

Open the front and rear doors using the hex key.

Turn the power supply and power controller circuit breakers
OFF.

Remove the AC power cord from the outlet.

Loosen the two captive screws holding the blower assembly.

Slide

Slide the blower assembly out and up to remove it from

the

blower

assembly

out

about

disconnect the blower motor power cable.

cabinet assembly.

See Figure 5-14.

four

inches,and

the

SYSTEM MAINTENANCE

POWER SUPPLY

CIRCUIT BREAKER

PLASTIC
RETAINERS

FIGURE 5-14 BLOWER ASSEMBLY REMOVAL

Push the power supply tray lock
of

slide)

tray

the

in.

lock

the tray handle until the second tray

edge

engages.

See

5-15.
N\

Figure

left

(located on the

Slide the tray out by pulling on

OOOOOOOOOO[

0.0
COws
snacx¢

FIGURE 5-15 CABINET POWER SUPPLY REMOVAL
Loosen and
remove
the
power
supply
hold
down
located near the top left edge of the power supply.

Using a phillips head screwdriver and
bus

wires.

remove the

bracket

four

5 VDc

SYSTEM

MAINTENANCE

10.

Remove

11.

Using

3/8-inch

12,

Pull

the

power

the

two ribbon

cables

wrench
supply

and

remove

the

forward

input

ground

and

cable.

lug.

remove

£from

the

cover

cabinet.
13.

Loosen

the

three

captive

the power supply and

screws

remove

the

holding

the

top

cover.

See

Figure

5-16.

-5 1V

& *12V0C
uTED

H711)
VDL

SYAND OFFS

|Yo

FIGURE 5-16 POWER SUPPLY REGULATOR REMOVAL

14.

or the communications
(H7213)
To remove the memory/fan
option (H7211) regulators, gently lift them out by grasping
each corner standoff and lift up.

15,

supply over
To remove the H7200 regulator, turn the power
loosen
regulator,
the
supporting
while
and
(open side down)

the six phillips head screws securing it to the chassis.

16.

Remove the regulator from the chassis.

This completes the removal of the regulators boards
To reinstall, reverse the above procedure.
supply.

and

power

5.7.2 Box Power Supply Removal

To remove a power supply

regulator

following procedure.
1.

Turn the

circuit breaker OFF.

5-30

power

supply,

use

the

SYSTEM
Unplug

the

power

Remove

the

box

top

screws

and

lifting

Loosen

the

cover.
See

from

<c¢over

the

cover

outlet.

removing

Figure

the

four

the

power

and

lift

captive

off.

two phillips head screws
Slide
the
cover backwards

supply
remove it.

5-17.

FIGURE

cord

MAINTENANCE

remove

5-17

either

communications

out by grasping

option
the

POWER

SUPPLY

the

memory/fan

(H7211)

REMOVAL

(H7213)

the

regulators, gently lift them

two corner standoffs and lift up.

To remove the H7200 regulator, the
power
supply
must
be
removed
from
the box.
Loosen the four screws that secure
the power supply to the chassis shelves.
Lift
the
power
supply, out of the box. .See Figure 5-18.

STAND OGPS
®)

FIGURE

5-18

POWER SUPPLY
5-31

REGULATOR

REMOVAL

SYSTEM

MAINTENANCE

After removal, turn the power supply over (open side down)
and while supporting the regulator, loosen the six phillips
head screws securing it to the chassis.

Remove the regulator from the chassis.
NOTE

If the power supply 1is replaced, set the AC
120/240 voltage select switch to match the outlet

voltage.

This completes the removal procedure for

regulators.

reinstall

reverse the above procedure.

the

box

regulators

power

and

cupply

power

and

supply.,

5.8 CABINET BLOWER REMOVAL/REPLACEMENT

To remove the blower assembly use the following procedure.
1. Open the front and rear doors using the hex key.

Turn the power supply and power contrcller circuit breakers

Remove the AC power cord from the outlet.

Loosen the two captive screws holding the blower assembly,
slide the blower assembly out abcut four inches, and

OFF.

disconnect the blower motor power cable.

Slide the blower assembly out while lifting up, and
it from the cabinet.

FIGURE

5-19

See Fiqure 5-19.

BLOWER ASSEMBLY

5-32

REMOVAL

remove

SYSTEM MAINTENANCE

This completes the removal procedure for cabinet blower assembly.
Reinstall

the

blower

assembly

the

reverse order.

5.9 BOX FAN REMOVAL/REPLACEMENT

There are three fans used in the box product.
Two fans cool
the
module
cardcage and the third cools the power supply.
To remove
any one

the

fans

Turn

the

circuit

Unplug

the

use the

following procedure.

breaker off.

AC power

cord

Remove

the

four screws

Remove

the

bezel

from

from the

from the
the

outlet.

rear

the

box

flange.

box.

Loosen the six captive
of the fans.
Lift off

screws from the metal grid
the metal grid.

Loosen the two phillips screws
securing
the
fan
mounting position on the plenum.
See Figure 5-20.

Unplug the fan power cable and remove the fan.

front

its

new

SCREWS (4)

FIGURE

5-20 BOX FAN REMOVAL

CAUTION

When installing a
points toward the

fan insure
plenum.

the

airflow

When installing a replacement
fan,
tighten
mounting screws snug.
DO NOT OVERTIGHTEN.
This
fan,

completes the fan
reverse the above

removal procedure.
procedure.
5-33

arrow

the

reinstall

SYSTEM MAINTENANCE

5.10 Front Panel Removal/Replacement

cabinet

The

box

and

front

are

panels

identical,

different removal and replacement procedures.

but

have

5.10.1 Cabinet Front Panel Removal/Replacement

To remove the cabinet front panel use the following procedure.
1.

Open the front and rear doors using the hex key.

Turn the power supply and power controller circuit bhreakers
OFF.

Remove the AC power cord from the outlet.

Disconnect the cable from the front
Figure

panel

assembly.

See

5-21.

/’/flk 74k
MOUNTING
HARDWARE

—

m—

CANLE

FIGURE 5-21 CABINET FRONT PANEL REMOVAL

Remove the four 3/8-inch nuts holding the
the

¢to

front

panel

assembly.

door.

Remove the front panel off the standoffs.

This completes the removal of the cabinet front

To reinstall the front panel,

reverse the above procedure.

SYSTEM

5.10.2
To

Box

remove
Turn

Front
the

Panel

box

the

Remove

the

front

the box

Remove

from

panel

supply

Unplug

screws

Removal/Replacement

front

power

the

use

the

circuit

from

the

cable

following

breaker

procedures.

OFF.

outlet.

bezel

rear

loosening

that

plugged

the

four

Phillips

side.

(see Figure 5-22).

the

MAINTENANCE

and
Pull

removing

the

four

the

away

from

into

bezel

the

front

panel

assembly.
Loosen

the

and

front
the

front

the

panel

head

screws

securing

chassis.
assembly.

‘\!

Remove

remove

panel

SEZ

flfii
Lfaur
Z4-852

2411

£22gl)

g
, \

~.
TM~

FIGURE

5-22

FRONT

PANEL

REMOVAL

This completes the removal of the front panel.
box front panel, reverse the above procedure.

reinstall

the

SYSTEM MAINTENANCE

5.11 CIRCUIT BREAKER REMOVAL/REPLACEMENT

ers for the power supply on (s).
Both products have circuit break
the
mbly is located externally
The box circuit breaker asse
lower
breaker is located inside
right side. The cabinet circuit
: one for the main power supply
kers
brea
right side and has two
and one for the expansion supply.

5.11.1 Cabinet Circuit Breaker Removal/Replacement

remove

procedure.

the

circuit

assembly use

breaker

following

the

Open the front and rear doors using the hex key.

Turn the power supply and power controller circuit breakers

Remove the AC power cord from the outlet.

.
OFF

Unplug the cords connected to

the

assembly.

See

Figure

5-23.

POWER SUPPLY
CIACUIT SREAKER

PLASTIC
RETAINERS

FIGURE 5-23 CABINET CIRCUIT BREAKER REMOVAL

5.
6.

ng in on the
Remove the blower power connector ngby tthepushi
connector loose.

connector release clips, and pulli

it breaker assembly
Loosen the two screws securing the circu
e the assembly.

to the the cabinet support and remov

This completes the removal of the circuit breaker assembly.
5=-36

SYSTEM

To reinstall

the assembly,

reverse

the above

MAINTENANCE

procedure.

Ensure

that the power cable plugged into the unswitched power controller
inserted

outlet

5.11.2

Box Circuit

remove

the

into Jl.

Breaker Removal/Replacement

«circuit

breaker

assembly,

use

the

following

‘

procedures.

Turn

the

circuit

breaker off.

Unplug

A4,
through
Remove the rear 4 bulkhead sections marked Al
See Figure 5-24.
each section has two flathead screws.

the AC power

cord

from the outlet.

SCREWS (4}

CQIRCUIT
BREAKER

FIGURE

Remove
box.

Reach

the

5-24

four

the

CIRCUIT

screws

inside
the
release the three

Remove

BOX

securing

box
cable

circuit

BREAKER

through

clips

breaker

the

the
inside

REMOVAL

breaker

assembly

bulkhead
along the

through

the

access
and
box wall.

rear

bulkhead

access.

Remove

the

the four screws securing the wires
circuit breaker.
Label each wire.

the

back

This completes the replacement procedure for the circuit
breaker
assembly.
To
reinstall
the
<c¢ircuit
breaker,
reverse
the
procedure.

5-37

SYSTEM

5.12

MAINTENANCE

CABINET POWER CONTROLLER REMOVAL/REPLACEMENT

remove

the

877 power controller assembly,

wuse

the

following

procedure.

Open the front and rear doors using the hex key.

Turn the power supply and power controller circuit breakers
OFF.

Remove the AC power cord from the outlet.

Lift the left side panel straight up from both sides.
See Figure 5-25.
careful, the outside panel is heavy.

[

L SHOULDER SCREW (4)

et EMI SHIELD

%S{:REW 121
4!

FIGURE

Remove
the

EMI

the

5-25 CABINET SIDE PANEL REMOVAL

two phillips and

shield

the

Label each power plug and
plugs.

Loosen

See

the

Figure

its

screws

securing

side.

receptacle,

and

remove

the

5-26,

phillips

controller to the

four shoulder

cabinet

head

screws

cabinet bulkhead.

Grasp the CONTROLLER metal power cord
the controller from the cabinet rear.

5-38

securing

the

$ee Figure 5-27.
restraint

and

power

remove

N P

TTTIBVYY

SYSTEM MAINTENANCE

FIGURE 5-26 POWER CONTROLLER REMOVAL = SIDE VIEW
827.0/F
CONTROLLER

AEAR VIEW

FIGURE 5-27 POWER CONTROLLER REMOVAL - REAR VIEW
This completes the removal procedure for

power

the

controller.

To reinstall the controller reverse the above procedure.
5.13 SLU INTERFACE ASSEMBLY REMOVAL/REPLACEMENT

Both

products

contain

SLU

Interface

different removal and replacement procedures.

Assembly,

Dbut

use

5.13.1 Cabinet SLU Assembly Removal

To remove the SLU assembly use the following procedure.
1.

Open the front and rear doors using the hex key.

Turn the power supply and power controller circuit breakers

OFF.

5-39

SYSTEM

MAINTENANCE

Remove

the AC power

Loosen

the

ten

cord

captive

from the outlet.

screws

securing

the

bulkhead

the

frame.

Open

the

Unplug

Loosen and

Unplug
Figure

pulling down

the SLU cable

connector
8.

bullhead

remove
to

the

the cable
5-28.

(console

the

from the

terminal)

two

hex

top.

from the

standoffs

connector.

securing

the

cross member.
from

the

SLU

assembly

connector.

See

| stz scngms

FIGURE

5-28

e SCREW (21

CABINET SLU ASSEMBLY

REMOVAL

Hold the SLU assembly while removing the

10.

Remove the SLU assembly from the cabinet.

two

secure the SLU assembly to the cross member.

This completes the removal of the SLU assembly.
SLU assembly reverse the above procedure.

screws

that

To reinstall the

SYSTEM

MAINTENANCE

5.13.2 Box SLU Assembly Removal/Replacement

To remove the SLU assembly, use the following procedure.
1.

Turn the circuit breaker off.

Unplug the AC power cord from the outlet.

Remove the cable plfigged into the SLU connector.

Remove the two hex standoffs securing the connector to

the

Remove the four screws on the top

remove

the

back

panel.

and

cover,

cover.

Remove the connector plugged into the SLU assembly board.

Remove the two assembly mounting screws from

Remove the hex standoffs from the SLU connectors.

the box.

See Figure 5-29,.

the

rear

)

[]

1000

W (R

pe— r—/‘flt;ll'l

I
FIGURE

5-29

BOX SLU ASSEMBLY REMOVAL

Remove the SLU assembly from the box.

This completes the removal of the SLU assembly.
assembly reverse the above procedure.

To reinstall the

5.14 CPU BACKPLANE REMOVAL/REPLACEMENT

Depending on the number of options installed

the

system,

backplane replacement can be a time consuming task. It is
recommended that you replace the backplane ONLY if is clearly
known to be the faulty FRU.

5-41

SYSTEM

MAINTENANCE

5.14.1

Cabinet

Removal

remove the CPU backplane,

the

rear doors

and

front

use

following procedure.

using the hex key.

Open

the

Turn

the power supply and power controller circuit breakers

.
OFF

Remove the AC power cord from the outlet.
Remove and label all the module cables.

Remove

all

cabinet

number.

backplane slot

modules

Remove the right side panel.

each

1label

and

its

with

See Figure 5-30.

L SHOULDER SCREW (4)

—

EMI SHIELD

SCREW (2)

SIDE PANEL

\\.

Backplane

FIGURE

5-30

SIDE

PANEL

REMOVAL

Remove the two
phillips
head
and
four
shoulder
securing the EMI panel to the cabinet frame.
Remove

the

left

Remove

the

four shoulder

the

cabinet

side

screws

panel.

screws

frame.

5-42

securing

the EMI

panel

SYSTEM

10.

MAINTENANCE

Loosen the ten screws securing the bulkhead to the
See Figure 5-31.
frame and lower the bulkhead.

cabinet

SAUD
/mcn

BULK WEAQ,~

SCREW (10)

[

ettt

FIGURE 5-31 CABINET REAR VIEW

11.

Remove

four

the

black

plastic

retainers

plastic lexan cover over the space
backplane location. See Figure 5-32.

for

cru

SACKPLANE
SCREW (4}

METAL

PANEL

METAL

cry

BACKPLAKE

FIGURE

5-32

CABINET

5-43

BACKPLANE

REMOVAL

securing
the

the
‘

expansion

SYSTEM

12,

MAINTENANCE

an expansion

connectors.

cabinet
130

backplane

Remove

the

remove

the

power

left side

access.

Disconnect the power cables

Remove the six screws securing the
metal
panel
over
rear access to the backplane.
Remove the metal panel.

the

16.

Remove

17.

cable
to

the

card

clamps

the

four

the

expansion backplane.

15.

the

rear

access

for

covering

14,

Locsen

1installed

lexan cover through the

metal

panel

backplane.

flathead

screws

securing

the

backplane

Remove the backplane by pulling the it toward
the
rear and twisting it through the side panel access.

cabinet

This completes the
removal
procedure
for
the
backplane.
reinstall the backplane reverse the above procedure.

5.14.2
To

Box Backplane

remove
1:0

Turn

the

Removal/Replacement

backplane,

the

¢to

cage.

power

use

circuit

Unplug

the

power

Remove

the

screws

the

following procedure.

breaker OFF.

cord

from the

securing

the

outlet.

top cover,

and

remove

the

cover.

Unplug all the module cables and label each with its module
number.

Unplug

all

the modules

Remove

the

four

number.

cables.

Unplug

labeling

1/4-inch

the

nuts

the module

securing

two backplane cables.

with

the

its

four

See Figure

slot

power

5-33.

SYSTEM

FIGURE

BACKPLANE

card

cage.

Slide the card cage to the rear of the box.
Lift and
the card cage to the rear and remove from the box.

slide

Turn

the

card

cage

screws.

located

over

Remove

This

and

the

REMOVAL

Remove the

mounting

screws

BOX

two

5-33

MAINTENANCE

the

rear

remove

the

four

backplane

backplane.

completes the removal procedure for the CPU
backplane.
reinstall the backplane reverse the above procedure.

5.17

CABINET

PERIPHERAL

ACCESS

Always extend the front stabilizer bar before sliding
an. option
out
of
the
top
portion of the cabinet.
The bar keeps the the
cbainet from tipping forward.
(See Figure 5-38.)

SYSTEM

MAINTENANCE

FIGURE

5-38

STABILIZER BAR EXTENSION

APPENDIX A

CPU INSTRUCTION TIMING

CPU

INSTRUCTION

TIMING

A.1l

INTRODUCTION

The

execution

time
of

instruction

The

The mode of addreséing used, and

The

type

for

type

general,

the

instruction

memory

total

The

tables

this

referenced.

execution

section

on:

executed,

being

instruction
fetch/execute
calculation/fetch time.

depends

time

can

1is

the

plus

used

the

sum

the

operand(s)

calculate

the

base

address

length

an instruction in terms of microcycles (MC).
Tables A-1 thru A-8
list the standard and floating—-point instructions, their Op
Code
listing,
and
execution
times
(MC).
The
EXECUTION MC column
specifies the number of microcycles required to fetch/execute the
base
instruction.
The
R/W column specifies the number of read
microcycles (R) and write microcycles (W)
in
the
EXECUTION
MC
column.
Any remaining microcycles are non I/O (NIO).
If

the

instruction

operands,

destination

table)

TABLE

and

Fl1

The

numbers

involves

reference

DEST

made

TABLE.

the

calculation/fetch

the

The

separate

last

tables

table

column,

referenced

are

one

wusually
S1,

source
Dl

or
labeled

thru

D6,

thru F5.
The source/destination tables specify the number
of microcycles the source/destination calculation/fetch requires,
and how many of these are read or write microcycles.
As
before,
any remaining microcycles are NIO.
contained

the

tables

are

based

the

assumptions

that:
a.

A memory

read

A memory

write

must

last

must

last

minimum

four

CLK

eight

periods,

CLK

and
c.

Any

NIO

lasts

four

CLK

periods

(no

periods,

DMA).

wait

states caused by slower memory or a DMA transfer must be
to
the
total
instruction
time.
If
wait
states
are
required, the first wait state of
a
nonstretched
read
or
NIO
cycle
will
1last
four
<clock
periods,
and
can
continue
1in
increments
of
two
clock
periods.
Further
wait
states
for
stretched cycles occur in increments of two clock periods.

added

Floating-point instruction execution times are given
The actual execution time will vary depending on the

A-2

as a
type

range.
of data

CPU

being
The

operated

following

EXAMPLE

How long

does

INSTRUCTION

TIMING

on.
examples

illustrate

a MOV RO,@

2044

how to

use

instruction

the

tables.

last?

Step

From Table A-2 , the execution time for the MOV base
instruction
is
found
to be 1 MC, or four CLK periods.
This consists of one
read and no write microcycles (R/W
column).
Depending
on
the
type
of
memory
in the system, the microcycle may be stretched.
If so, the microcycle lasts at least eight CLK periods and may be
stretched thereafter in increments of two CLK periods.

Step

find

(RO),
mode 0

operand
Step

the

operand

refer
to
register 0

calculation/fetch

time

for

the

source

operand

Table
S-1.
From Table S-1, it is shown that a
calculate/fetch takes
0
MC.
Note
that
the

is already available

to the

DCJ1l

(in the register file).

To find the operand calculation/fetch time
for
the
destination
operand
(the
contents
of memory location 2044), refer to Table
D-3.
Table D-3, specifies that a mode 3
register
7
calculate/

fetch

requires

microcycle).

Note

(i.e.,

that

the

one

read microcycle

remaining

and one write

microcycle

1is

NIO

account.

microcycle.

The

type

memory

the

system must

taken

into

the
read
<cycle is stretched, the stretched cycle lasts at least
eight CLK periods and may be stretched thereafter
in
increments
of
two
CLK
periods.
The write microcycle lasts at least eight
CLK periods and
may
be
stretched
1in
increments
of
two
CLK
periods.

Step
For

4:
a

determination

microcycles.
16

CLK

periods

this
no

the minimum

example,

microcycle

time

required,

stretching

occurs).

total

wup

the

(which

INSTRUCTION TIMING

CPU

EXAMPLE

The

source

show

2 register
for one of

How long

Step
As

and

7 operations.
these.

does

instruction

From Table

Table

floating—-point

This

2000

example

column

shows

instruction

instructions

for certain mode

timing

calculation

last?

A-8,

the

base

instruction

time

for

the

CLRD

MC.

F-2,

the

PRECISION).

However,

add

read

calculation/fetch

This

instruction

memory

Step

CLRD

for

the microcycle

mode
base

specified

Step

destination tables

a negative number

reference)

means

that

time

for

the

shown

(-1

should

operand

under

subtracted

from

the

time.

for

cycles

the

memory

account

write

for.

operation.

There

are

(assumes

Total up the microcycles:
cycle

14 =1 +1 = 14 MC minimum

stretching).

TABLE

A-1

SINGLE

OPERAND

INSTRUCTIONS

TIMING
OP

MNEMONIC

INSTRUCTION

CODE

EXECUTION

SOURCE

DEST

TABLE

LISTING

R/W

TABLE

General

CLR(B)

Clear

0050DD

I/0

COM(B)
INC(B)
DEC(B)
NEG(B)

Complement (1l's)
Increment
Decrement
Negate
(2s complement)
Test

0051DD
0052DD
0053DD

1
1
1

I/0
I/0
I/0

D4
D4
D4

0054DD
0057DD

1
1

I/0
I/0

D4
D4

TST(B)

DOUBLE

TABLE A-1

TIMING

INSTRUCTION

CPU

(Cont)

Rotate and Shift

0060DD
0061DD

1
1

/0
I/0

0062DD

1/0

0055DD
0056DD
0067DD

1
1
1

(low bit interlocked)

0072DD

interlocked

0073DD

ROR(B) Rotate right
ROL(B) Rotate left

ASR(B)

Arithmetic

SWAB

shift right

Swap bytes

I/0
I/0
I1/0

D4
D4
D3

1/1

0003DD

D4
D4

Multiple-Precision

ADC(B) Add carry
SBC(B) Subtract carry
Sign extend
SXT
Multiprocessing
TSTSET Test and

set

WRTLCK Write

TABLE A-2

DOUBLE

OPERAND INSTRUCTIONS

TIMING

MNEMONIC

INSTRUCTION

OP CODE

EXECUTION

SOURCE

DEST

TABLE

R/W

TABLE

01SSDD
02SSDD
06SSDD
16SSDD

1
1
1
1

1/0
1/0
1/0
1/0

S-1
S-1
S-1
S-1

D3
D2
D4
D4

03SSDD

1/0

-1/0
1/0

S-1

S-=1
S-=1

1/0

LISTING

General

MOV(B) Move
CMP(B) Compare
Add
ADD
Subtract
SUB

Logical

BIT(B)

BIC(B)
BIS(B)

Bit test

(AND)

Bit clear
Bit set (OR)

04SSDD
05S8SDD

1
1

D4
D4

MUL

Multiply

0704SS

DIV

Divide

071RSS

22
(Notes

5,11

1/0

INSTRUCTION TIMING

CPU

TABLE A-2

(Cont)

shift
automatically
Arith shift
combined
Exclusive

(OR)

(Notes

6,7,12)

072RSS

1/0

073RSS

5}
(Note
1l

1/0

074RDD

TABLE A-3

GEN

S G

S GED A

S UM GED GED GED TED GED GED AED GEL

D GND

e GEE W

van

13)

BRANCH

INSTRUCTIONS

D G

N S

D W

I CHED GRS GED G

IR TS W

TIMING

MNMONIC

INSTRUCTION

BRANCH

NOT

TAKEN

CODE

TAKEN

LISTING

R/W

000400
001000
001400
100000
100400
102000
102400
103000
103400

2
2
2
2
2
2
2
2
2

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

4
4
4
4
4
4
4
4
4

2/0
2/0
2/0
2/0
2/0
2/0

020000
002400
003000

2
2
2

1/0
1/0
1/0

4
4
4

2/0
2/0
2/0

003400

1/0

2/0

101000
101400
103000
103400

2
2
2
2

1/0
1/0
1/0
1/0

4
4
4
4

0 77RNN

1/0

BRANCHES
BR

Branch

BNE

BEQ

BPL

BMI

BVC

BVS

BCC
BCS

Br
Br

SIGNED

if
if
if
if
if
if
if
if

(unconditional)
not equal (to 0)
equal (to 0)
plus
minus
overflow is clear
overflow is set
carry is clear
carry is set

CONDITIONAL

BRANCHES

BLT

BGT

if less than (0)
if greater than (0)

BLE

BGE

(to

greater

equal

less

equal

(to 0)
BRANCHES

UNSIGNED

CONDITIONAL

BHI

BLOS

if lower or same
Br if higher or same
Br if lower
Subtract 1 and branch

BHIS

BLO
SOB

higher

(if /= 0)

CPU INSTRUCTION TIMING

TABLE A-4 JUMP and SUBROUTINE
TIMING

MNEMONIC INSTRUCTION
JMP

Jump

RTS

Return

JSR
MARK

Jump to subroutine
from

subroutine
Stack cleanup

OP CODE

EXECUTION

R/W

DST

0001DD

(Note 4)

00020R
0064NN

5
10

3/0
3/0

(Note 14)

LISTING

004RDD

TABLE

TIMING

MNMONIC

INSTRUCTION

EMT Emulator trap
TRAP Trap
BPT Breakpoint trap
IOT 1Input/output trap
RTI Return from interrupt
RTT Return from interrupt

OP CODE

LISTING

EXECUTION

104000--104377
104400--104777
000003
000004
000002
000006

R/W

20
20
20
20
9
9

4/2
4/2
4/2
4/2
4/0
4/0

TABLE A-6 CONDITION CODE OPERATORS

TIMING

MNEMONIC INSTRUCTION
CLC
CLV
CLZ
CLN
CCC
SEC

Clear C
Clear V
Clear 2
Clear N
Clear all CC bits
Set C

OP CODE

LISTING
000241
000242
000244
000250
000257
000261

EXECUTION

R/W

3
3
3
3
3
3

1/0
1/0
1/0
1/0
1/0
1/0

CPU INSTRUCTION TIMING
TABLE

SEV
SEZ
SEN
SCC

A-6

000262
000264
- 000270
000277

Set V
Set 2Z
Set N
Set all CC bits

1/0
1/0
1/01/0

3
3
3
3

TABLE A-7 MISCELLANEQOUS INSTRUCTIONS

TIMING

MNEMONIC
HALT

OP CODE

LISTING

INSTRUCTION

EXECUTION

000000

Halt

R/W

DEST

TABLE

WAIT

Wait for interrupt

000001

NOP
SPL
MFPI
MTPI
MFPD
MTPD
MTPS

(No operation)
Set priority level to N
Move from previous instr space
Move to previous instr space
Move from previous data space
Move to previous data space
Move byte to PSW PS <- (svc)

000240

00023N
0056DD
1065SS
1066DD
1064SS

3
7
5
3
5
3
8

1/0
1/0
1/1
2/0
1/1
2/0
1/0

D-1
D-3
D-1
D-3
D-1

<~ PS <7:0>

1067DD

1/0

D-3

<- proc code

000007

1/0

RESET Reset external bus

MFPS

MFPT

CSM

Move byte from PSW (dst)

Move from processor (R0<7:0>)

000005

0070DD

Call to supervisor mode

3/3

TABLE A-8 FLOATING-POINT INSTRUCTIONS

TIMING

MNEMONIC INSTRUCTION

ABSD
ABSF

ADDD
ADDF
CFCC

Make Absolute
Make Absolute
Add
Add
Copy Floating

EXECUTION MC

OP CODE

LISTING

1706 fdst
fdst
1706
172 (AC) fsvc
172 (AC) fsve
A-8

MIN

23
19
41
31

TYPICAL

48
35

NON MODE 0
MAX

TABLE

24
20
119
102

D-1

CPU

CMPD

Compare

CMPF

Compare

DIVD

Divide
Divide
ILd & C

DIVF
LDCDF

from

173
173
174
174

(AC
(AC
(AC
(AC

+ 4)
+ 4)
+ 4)
+ 4)

177

(AC

177

(AC +

167

177

(AC)

src

LDCIF

Id & C
Integer

177

(AC)

src

LDCLD

ILd & C Long
Integer to D

177

(AC)

src

LDCLF

177
172

(AC) src
(AC + 4)

176
172

(AC + 4)
(AC + 4)

17
12

17
18
13

Status

1701

src

Separate

171

MODD

FPP

Program

Multiply and

MULF

Integer and
Fraction
Multiply
Multiply

NEGD

Negate

NEGE

Negate

MODF
MULD

SETD

SETF

Set

Floating

Set

Floating

Double

Mode

Set

SETL

Set
Mode

170011

Integer

170002

Mode

Long

Integer

+ 4)

171 (AC + 4)
171 (AC) fsrc
171 (AC) fsrc
1707 fdst
1707 fdst

170001

Mode
SETI

(AC

170012

202

217

268

115
173

165
56
22

LDFPS

LDF

Exponent

61
23

) 1)

LDEXP

) T

LDD

Load
Load
Load
Load

Long

tx)

Integer

PPTT

Integer

]

170000
1704 fdst
1704 fdst

LDCID

from

Dto
LDCFD

Codes

Condition
Clear
Clear

—_

CLRD
CLRF

(Cont)

TABLE A-8

INSTRUCTION TIMING

CPU

TIMING

INSTRUCTION

(Cont)

TABLE A-8

STCDF
STCDI

"STCDL
:

St & C from
D to F
St & C from
to Integer

& C from D
Long Integer
STCFD St & C from
F to D
STCFI St & C from F
to Integer
STCFL St & C from F
to Long Integer

St
to

STST

SUBD
SUBF
TSTD
TSTF

Store

(AC)

fdst

176

(AC)

fdst

176

(AC)

176

(AC)

175
175

STD
Store
STEXP Store Exponent
STF
Store
STFPD

176

174
175
174

F-2

F-5

fdst

F-5

fdst

F-2

(AC + 4)
'
(AC + 4)
(AC) £fdst
(AC) dst
(AC) fdst

F-5

12
16
8

F-2
F-5
F-2

FPP

Program Status
Store FPP
Status
Subtract
Subtract
Test
Test

1702

dst

1703

dst

173 (AC) fsrc
173 (AC) fsrc
1705 fdst
1705 fdst

47
37
11
9

SOURCE

MICROCODE

MODE

CYCLES

55
41

F-5

122
104
12
10

F-1
F-1
F-1
F-1

READ

MEMORY
CYCLES

0==7

1
2
2
3
3
4
4

0==7
0--6
7
0--6
7
0--6
7

2
2
1
4
'3
3
6

1
1
1
2
2
1
2

(Note

5
5

0--6
7

5
8

2
3

(Note

6
7

0==7
0-=7

4
6

2
3

CER SEP

F-5
'

SOURCE

GID

VD GFD

GED

CN0

GED

CAD

GED

GES

WED

GED SED

SND

GER

TEP

YED

D CED CHD

WER

GNb

CND

CPU

TABLE

D—-1

DESTINATION ADDRESS:

DEST INATION
MODE

DESTINATION
REGISTER

0
1
2
2
3
3
4
4
5
5
6

0--7
0==7
0--6
7
0--6
7
0--6

7
O=--F¢
7
0-=7

0-=7

READ-ONLY

MICROCODE
CYCLES

INSTRUCTION TIMING

SINGLE OPERAND

READ MEMORY
CYCLES

0
2
2
1
4
3
3

0
1
1
1
2
2

7
5
9
4

2
2
3
2

DESTINATION

MICROCODE

READ

MODE

CYCLES

(Note

MEMORY

0~=7

1
2
2
3
3
4
4
5
5
6
7

0==7
0--6
7
0--6
7
0--6
7
0--6
7
0==7
0=-=7

3
3
2
5
4
4
8
6
10
5
7

1
1
1
2
2
1
2
2
3
2
3

A-11

(Note

CPU

TIMING

INSTRUCTION

TABLE D-3

DESTINATION

ADDRESS

TIMES:

DESTINATION

MICROCODE

MODE

CYCLES

0
0
1
1
2
2
3
3
4

0--6
7
0--6
7
0--6
7
0--6
7
0--6

5
5
6
7

D-4

DESTINATION

ADDRESS

DESTINATION

DESTINATION
REGISTER

TIMES:

READ

CYCLES

READ

WRITE

0
1
0
1
0
1
1
1
0

0
0
1
1
1
1
1
1
1

1
2
1
2

1
1
1
1

2
6
2
6
4
3
3
7
5
9
4
6

MODE

MEMORY

0
5

0--6
7
- 0-=7
0=-=7

TABLE

WRITE-ONLY

MODIFY

| MICROCODE

WRITE

MEMORY CYCLES

CYCLES

Read

WRITE

0--6

0
1

7
0--6

5
3

1
1

1
2
2

7
0--6
7

7
3
7

2
1
2

1
1

3
3
4

0--6
7
0--6

5
4
4

2
2
1

1
1
1

4
5
5

7
0--6
7

8
6
10

2
2
3

1
1
1

6
7

0-=7
0-=7

5
7

2
3

1
1

TED

WHD

GER

CED

SED

AER

CED CER

CED

A-12

CED

€0

CED

«ED

CID

mED

GEP

GED

CMD

CED

GED

GNP

(Note

YER

GER

TED

GED

Gmb

TABLE

DESTINATION ADDRESS

TIMES:

JMP

DESTINATION

MICROCODE

MEMORY

MODE

CYCLES

READ

D-5

CEn

TED

CEN

whm

CES G

CWD

IR CID

COID

TIMING

INSTRUCTION

CPJ

CYCLES
WRITE

SRR

CED

GND

GED AED

CED

CHD

GED CUR €

(TN

G50

CED

LED

CER

<WD

CED

GED

€D

OO0

CEp

CED

€5

€ED

€00

WD WED

GED

MOD

RS GNP

OND

GID eED

GID

ofD

OwD

DESTINATION

MICROCODE

MEMORY

MODE

CYCLES

READ

WRITE

0==7

0-=7

3
3
4

0==6
7
0==7

10
)
10

3
3
2

1
1
1

0=-=7

0--6

0-=7

wED

FLOATING

MICROCODE

MEMORY

MODE

)

SOURCE

)

1--7

CER

)

TYD

MEMORY
€D

OIS

CYCLES
GED

F=-1

TABLE

CYCLES

A-13

READ
.

WRITE
e

aTD

CPU INSTRUCTION TIMING
TABLE

F-1

7
0--6
7
0--7
0--7
0--7

2
3
3
4
5
6
7

0--7

1
4
3
4
5
4
6

1
3
3
-2
3
3
4

0
0
0.
o
0
0
0

4
4
1
5
5
4
5
5
6

0
0
0
0
0
0
0
0

DOUBLE PRECISION

MICROCODE

MODE

1
2
2
3
3
4
5
6
7

5
5
0 (Note 15)
6
5
6
7
6
8

0-=7
0--6
7
- 0=-=6
7
0--7
0==-7
0-=7
0==7

1
2
2
3
3
4
5
6
7

MEMORY

0--7
0--6
7
0--6
7
0==7
0-=7
0-=7
0-=7

MEMORY

CYCLES

READ

WRITE

0
0
0
1
1
0
1
1
2

2
2
1
2
2
2
2
2
2

0
5
0
5
(-1) .(Note 15) O
1
6

4
4
1
4

3
3
1
4
3
4
5
4
6

DOUBLE PRECISION

1
2
2
3

0-=7
0--6
7
0--6

A-14

INSTRUCTION TIMING

CPU

TABLE F-2(Cont)

MICROCODE

MODE

MEMORY

(Note

MICROCODE

MODE

1
2
2
3
3
4
5
6
7

WRITE

READ

CYCLES

15)

MEMORY

CYCLES

READ

WRITE

0==7
0--6
7
0--6
7
0==7
O0==7
Q0==7
0==7

9
9
(-2)
10
9
10
11
10
12

4
4
1
5
5
4
5
5
6

4
4
1
4
4
4
4
4
4

(Note 15)

CPU

INSTRUCTION

TIMING

TABLE
D

RS G

F-4
—

INTERGER
-

SOURCE
€

GmS

MODES
G

1--7
WD

——

—

MICROCODE’

MEMORY

MODE

CYCLES

READ

WRITE

1
1

0
0

INTERGER

0-=7

2
2

0--6
7

2
0

3
3

0--6
7

3
2

4
5
6
7

2
2

0==7
0=-=7
0=--7
0==7

0
0

3
4
3
5

1
2
2
3

0
.0
0

LONG

(Note

15)

INTERGER

0==7

2
2

0--6
7

0--6

0
5

4
5

7
0==7
0=-=7

1
3

4
5
6

6
7

0--7
0--7

(Note

15)

3
2
3
3
4

MICROCODE

MEMORY

MODE

REGISTE

CYCLES

0-=7

2
2

0--6

2
2
2
3

READ

0
0
0
0
0

WRITE

INTERGER

0--6

A-16

0
0
0
1

1
1
1
1

INSTRUCTION TIMING

CPU

TABLE F-5

(Cont)

3
4
5
6
7
LONG

7
0-=7
0--7
0==7
0--7

2
3
4
3
5

1
0
1
1
2

1
1
1
1
1

0-=7
0--6
7
0--6
7
0--7
0=-=7
0-=7
0==7

4
4
2
5
4
5
6
5
7

0
0
0
1
1
0
1
1
2

2
2
1
2
2
2
2
2
2

INTERGER

1
2
2
3
3
4
5
6
7

A.2 SOURCE AND DESTINATION TABLE NOTES
1.

Subtract 2 MC and one read if both

source

if
or
PC,
autodecrement
modes
READ-MODIFY-WRITE mode 07 or 17 1is used.

and

destination

WRITE-ONLY

47
mode
destination
READ-MODIFY-~WRITE
READ-ONLY and
For
ns.
operatio
READ
3
perform
actually
references
bookkeeping purposes, one of the READs is accounted for 1in
the

EXECUTE,

FETCH TIMING.

57
mode
destination
READ-MODIFY-WRITE
READ-ONLY and
For
4 READ operations.
perform
actually
references
bookkeeping purposes, one of the READs is accounted for in
the EXECUTE,

FETCHING TIMING.

Subtract 1 MC if the link register is PC.

Add 1 MC if the source operand is negative.
Subtract 1 MC

if the source mode is not zero.

Add 1 MC if the quotient is even.

Add

2 MC

overflow occurs.

CPU INSTRUCTION TIMING

c.
Add

Add 5 MC and 1 read if the PC is used as

destination

Add 1 MC if source operand <15:6> is not zero.
10.

Subtract 1 MC if one shift only.

11.

Add 4 MC and 1 read if the PC 1is used as a destination
register, but only if source mode 47 or 57 is not used.

12,

pDivide by zero executes in 5 MC (see note 6).

13.

Timing for no shift. Add 1 MC if a left shift. (Notes 8,
9, 11 apply.) Add 2 MC for a right shift. (Notes 8, 10, 11
apply.)

14,

Add one MC if a register other than R7 is used.

150

Mode 27 references only access single word

excution

time

1listed

has

been

accurately compute the total execution time.

A-18

operands.

compensated

The

1in order to

APPENDIX

PDP-11/84

HARDWARE/SOFTWARE

DIFFERENCES

PDP-11/84

B.l

HARDWARE/SOFTWARE

UNIBUS

POWER

DIFFERENCES

PROTOCOL

DIFFERENCES

The Unibus Power up protocol on
different than on most PDP-lls.
With most

PDP-11

systems,

the

PDP-11/84
systems
(See Figure B-l.)

Unibus

signal

1is

INTIALIZE

held asserted for a minimum of 10 milliseconds
of DC LINE LOW (DC LO L) on power up.

after

PDP-11/84

for

systems,

a minimum of

power

up.

This

the

Unibus

signal

INIT

after

the

16 microseconds

difference

wil

not

affect

slightly

(INIT
the

negation

held

asserted

negation of

DCLO L on

any

system operations.

DC Power ok

DCLO L

INIT L XXXXXXXXXXXXX\

/
l
|
|

|
5 us min.

Most

XXXXXXXX

FIGURE

B.2

PDP-11/84

PDP-11/84-based

B-~1

Cache

Switch

Data

POWER

11/44

general

SPL,

MTPS,

Y----

PROTOCOL

TIMING

may

not

the

contain

PDP-11/44
the

following

certain
PDP-11/44

(17777754)

contain

MFPS,

DIFFERENCES

replace

does

DIFFERENCES

(17777570).

PDP-11/84-based products
present in the 11/44:
Dual

16 us min.
10 ms min.

HARDWARE

products

|
|

undefined

applitions.
However,
hardware features:
o

=
=

FDP-11/84
UNIBUS PDF-11ls

)---

the

following

functionality

set

TSTSET,

WRTLCK
B-2

instructions.

not

PDP-11/84 HARDWARE/SOFTWARE DIFFERENCES

implemented on the PDP-11/44.
used for testing by the CPU ROM

The following registers are not
the registers are
Primarily,

ROM
code, other diagnostics or system configuration by the CPU
software.
level
They are not normally used by the system
code.
o

Boot and Diagnostic controller register (17777520)

ROM page control register (17777522)

Configuration and Display register (17777524)

Diagnostic controller register

Diagnostic Data register

Memory configuration registér (17777734)

(17777730)

(17777732)

and

any

DMA

transfers

may

differences

between

the

DMA transfers may not occur between UNIBUS

registers

located

the

CPU.

DMA

peripehrals

transfers may only occur

between the UNIBUS peripherals and the UBA.

occur between UNIBUS periph erals and the addresses of the
also
ROM sockets located on the UBA (17 773 000~ 17 773 776).

Table

B-1

summarizes

the

hardware

PDP-11/44 and the PDP-11/84-based products.
TABLE B-1

11/84-11/44

DIFFERENCES

FUNCTION

ADDRESS

Added register set select

17777776

17777772

PIRQ

17777766

CPU Error

17777754

Cache Data

Not implemented

17777752

Hit/Miss

No difference

17777750

Maintenance

Hardware differences

17777746

Cache Control

Hardware differences

17777744

Memory Error

Hardware differences

bit<11>

No difference
Unibus monitoring bits

not

implemented

(see Chapter 3)

(see Chapter 3)
(see

Chapter 3)

PDP-11/84

HARDWARE/SOFTWARE

TABLE
—

e
— n-—-——

17777676

DIFFERENCES

B-1

-——-—-—-————

(Cont)

————-——

User Data PAR

-—-————'————-—

-—-—-——-—.4-——

No difference

17777760

17777656
to

User

17777640

PAR

Instruction

"No

didfference

difference

17777636
to

User

Data

User

Instruction

17777600

PDR

17777576

MMR2

difference

17777574

MMR1

difference

17777572

MMRO

PDR

17777620

17777616

Eliminated

maintenance

mode
17777570

Switch

17772516

MMR3

Not

implemented

difference

17772376
to

Kernel

Data

Kernel

Instruction

difference

17772340

PAR

Kernel

Data

difference

Kernel

Instruction

difference

PAR

17772360
17772356

17772336
to

PDR

17772320

17772316
to

PDP-11/84
TABLE

B-1

HARDWARE/SOFTWARE DIFFERENCES

(Cont)

17772300

17772276

Supervisor Data PAR

No difference

Supervisor

No difference

Supervisor Data PDR

No difference

Supervisor

No difference

17772260
17772256

to
17772240
17772236

17772220
17772216

17772200

PDP-11/84 -

B.3

11/70

HARDWARE DIFFERENCES

applications.
The PDP-11/84 may replace the PDP-11/70 in certain
hardware
PDP-11/70
following
the
<contain
not
does
it
However,
features:

Stack Limit Register (17777774)

Micro Break

System

System Size Registers

Physical Error Address Registers

Switch

ID Register

(17777770)

(17777764)

(17777760,

17777762)
(17777740,

(17777570).

The DCJll-based products contain the following
present

the

17777742)

functionality

not

11/70:

MTPS,

MFPS,

Bypass cache

MFPT,
bit

CSM,
in

TSTSET,

WRTLCK instruction

PDRs.

The following registers are not implemented
c¢nt
the
PDP-11/44.
for testing by the CPU ROM
wused
are
registers
the
Primarily,
code,
code.

other diagnostics or system configuration by
the
CPU
ROM
They are not normally used by the system level software.
B-5

PDP-11/84

DMA

HARDWARE/SOFTWARE

Boot

and

Diagnostic

ROM page

Configuration

Diagnostic

controller

Diagnostic

Data

Memory

control

controller

and

not

(17777520)

(17777522)

Display

configuration

transfers may

DIFFERENCES

(17777524)

(17777730)

(17777732)

occur between

(17777734)
UNIBUS

peripehrals

and

any

registers
located
on
the
CPU.
DMA
transfers may only occur
between the UNIBUS peripherals and the UBA.
DMA
transfers
may
also
occur
between
UNIBUS peripherals and the addresses of the
ROM sockets located ont the UBA (17 773 000 - 17 773 776).

Table
B-2
summarizes
the
hardware
differences
PDP-11/70 and PDP-11/84-based products.

TABLE

ADDRESS

17777776

B-2

11/84

11/70

DIFFERENCES

FUNCTION

between

DIFFERENCES

Added suspended
instruction bit
Limit

Not

<8>.

17777774

Stack

17777772

PIRQ

17777770

Micro

17777766

CPU

17777764

System

Not

implemented.

17777760

System

Size

Not

implemented.

17777752

Hit/Miss

17777750

Maintenance

Hardware

Break

Error

implemented.
difference.

Net
No

implemented.
difference.

difference.

(see
17777746

Cache

Control

Hardware

(see

differences

Chapter

differences

Chapter

the

PDP-11/84

TABLE B-2

DIFFERENCES

(Cont)

Hardware differences
(see Chapter 3)

Error

17777744

Memory

17777742

High

17777740

Low

Error

User

Data

User

Instruction

User

Data

User

Instruction

Error

HARDWARE/SOFTWARE

Not

implemented.

Address

Not

implemented.

PAR

difference.

Address

17777676
to

17777660
17777656
to

PAR

17777640
17777636
to

Added bypass cache,
eliminated access flags
and access modes other
than 0, 2, and 6.

PDR

17777620

17777616
to

PDR

17777600

Added bypass cache,
eliminated access flags
and access modes other
than

and

17777576

MMR2

No difference.

17777574

MMR1

No difference.

17777572

MMRO

Eliminated traps,
maintenarnce mode, and
instruction complete.

17777570

Switch

17772516

MMR3

Not

Added

17772376
to

implemented.

Kernel

Data

PAR

Kernel

Instruction

CSM enable

difference.

17772360
17772356
to

17772340

PAR

bit

<3>.

PDP-11/84

HARDWARE/SOFTWARE DIFFERENCES
TABLE

17772336

17772320

Kernel

B-2

(Cont)

Added bypass cache,

Data PDR

eliminated access flag and

access modes
2,

17772316

Kernel

17772300

Instruction PDR

and

Supervisor Data .PAR

eliminated access flag and
2,

17772276

than

Added bypass cache,
access

other

and

modes

other

than

No difference.

17772260
17772256

Supervisor

17772240

PAR

17772236

Instruction

Supervisor Data PDR

17772220

No difference.

Added bypass

cache,

access modes

other

eliminated access flag and
2,

and

than

17772216

Supervisor Instruction

PDR

17772200

Added bypass cache,

eliminated access flag and
access
2,

B.4

SOFTWARE

modes
6.

other

than

DIFFERENCES

Table B-3

summarizes

language

level)

PDP-11

and

family.

the programming differences

between

the

DCJ1ll

and

other

(at

the assembly

processors

the

PROCESSORS
ITEM

1. OPR %R, (R) +; OPR %R, — (R) using
the same register as both source and
destination: contents of R are incremented (decremenied) by 2 before being
used as the source operand.

OPR %R, {R) +; OPR %R, — (R) using the
same register as bolh register and destination: initial contents of R are used as
the source operand.

2. OPR %R, @ (R) +; OPR %R, @ — (R)
using the same register as both source
and destination: contents of R are incre-

mented (decremented) by 2 before being
used as the source operand.
OPR %R, @ (R) +; OPR %R, @ — (R)
using the same register as both source
and destination: initial contents of R are
used as the source operand.

3.0PRPC, X (R); OPRPC, @ X (R); OPR
PC, @ A; OPR PC, A: location A will conain the PC of OPR + 4.
OPRPC, X (R); OPRPC, @ X (R), OPR
PC A OPRADC @ A: location A will contain the PC of OPR + 2.
4. JMP (R) + or JSR reg, (R) +: contents
of R are incremented by 2, then used as
the new PC address.
JMP (R) + or JSR reg, (R) +: initial contents of B are used as the new PC.

23/24

LSIN

05/10 15/20 35/40

J-11

T-11

VAX

ITEM

23/24

LSI1

05/10 15/20 35/40

J-11

5. JMP %R or JSR reg, %R traps to 10

{Megal instruction).

JMP %R or JSR reg, %R traps to 4 (ilegal
instruction).

6. SWAB does not change V.
SWAB clears V.

7. Register addresses (177700-177717)
are valid program addresses when used
by CPU.

SOB, MARK, RTT, SXT instructions®
ASH, ASHC, DIV, MUL, XOR
Floating Point Instructions in base
machine.
MFPT Instruction.

The external option KE11-A provides
MUL, DIV, SHIFT operation in the same
data format.

* AT T instruction is available in 11/04 but is ditferent than other implementations.

' Register addresses (177700-177717) are handied as regular memory addresses in the 170 page.

2 All but MARK.

8. Basic instructions noted in PDP-11
processor handbook.

CPU or console.

0T-d

address by the CPU. Can be addressed
under console operation.

T-11

VAX

ITEM

23/24

LS4

05/10 15/20 35/40

J-11

The KE11-E (Expansion Instruction Set)
provides the instructions MUL, DIV, ASH,
and ASHC. These new instructions are
11/45 compatible.

The KE11-F (Floating Instruction Set)
adds unique stack ordered oriented point
instructions: FADD, FSUB, FMUL, FDIV.

SPL Instruction

T1-d

CSM Instruction

9. Power fail during RESET instruction is
not recognized until after the instruction
is finished (70 milliseconds). RESET
instruction consists of 70 millisecond
pause with INIT occurring during first
20 milliseconds.

Power fail immediately ends the RESET
instruction and traps it an INIT is in
progress. A minimum INIT of 1 microsecond occurs if instruction aborted.
PDP11-04/34/44 are similar with no
minimum INIT time.

Power fail acts the same as 11/45
(22 milliseconds with about 300 nanoseconds minimum). Power fail during
RESET fetch is fatal with no power
down sequence.

MFP, MTP instructions

The KEV-11 adds EIS/FIS instructions

T-11

VAX

ITEM

23/24

LSI11

05/10 15/20 35/40

J-11

T-1

VAX

RESET instruction consists of 10 microseconds of INIT folowed by a 90 microsecond pause. Reset instruction consists of a minimum 8.4 microseconds
folowed by a minimum 100 nanosecond
pause. Power fail not recognized until
the instruction completes.

10. No RTT instructlion
HATT sets the “T" bit, the “T" bit trap

¢T-d

occurs alter the instruction following RTT.

11. It RTI sets “T" bit, “T" bit trap is
acknowledged alter instruction following
RTI.

It RTI sets “T" bit, “T" bit trap is
acknowledged immediately following RTI.
12. If an interrupl occurs during an
instruction that has the “T" bit sel, the

“T" bit trap is acknowledged before the
interrupt.
If an interrupt occurs during an instruction and the “T" bit is set, the interrupt is
acknowledged betore “T" bit trap.

13. “T" bit trap will sequence out of WAIT
instruction.

“T" bit trap will not sequence out of WAIT
instruction. Waits until an interrupt.
'interrupts nol visible to VAX compatibility mode.

NA!

23/24

ITEM

05/10 15720 35/40

J-11

-1

VAX

14. Explicit reference (direct access) lo
PS can load “T” bit. Consoie can also
load “T" bit.

Only implicit references (RT!, RTT, traps
and interrupts) can load “T" bil. Console
cannot load “T" bit.

-2

Odd address/non-existent references
using the stack pointer cause a fatal trap.
On bus error in trap service, new stack
created at 0/2.

16. The first instruclion in an interrupt
routine will not be executed if another
interrupt occurs at a higher priorily level
than assumed by the first interrupt.

Qinnla annaral nuurnn

ictar

implemented.

Dual general purpose register set
implemented.
} Odd address/non-existent references using SP do not trap.
20dd address aboris 1o native mode.

H 9

The first interrupt in an interrupt service
is guaranteed to be executed.
=

£ET-4d

15. Odd address/non-existent references
using the SP cause a HALT. This is a
case of double bus error with the second
error occurring in the trap servicing the
tirst error. Odd address trap not implemented in LSI-11, 11/23 or 11/24.

ITEM

18. PSW address, 177776, not imple-

mented: must use instructions MTPS

(move to PS) and MFPS (move from PS).
PSW address implemented, MTPS and
MFPS not implemented.

PSW address and MTPS and MFPS
implemented.

19. Only one interrupt level (BR4) exists.

Four interrupt levels exist.

F1-d

20. Stack overflow not implemented.
Some soit of stack overflow implemented.

21. Odd address trap not implemented.

Odd address trap implemented.

22. FMUL and FDIV instructions implicity
use R6 (one push and pop); hence R6
:
must be set up correcily.
not
do
ons
FMUL and FDIV instructi
implicitly use R6.

23. Due to their execution time, EIS

instructions can abort because of a

device interrupt.

EIS instructions do not abort because of
a device interrupt.

24. Due to their execution time, FIS
instructions can abort because of a
device interrupt.

3 Can relerence PSW only lrom native mode.

23/24

LSit1

05/10 15/20 35740

J-1

-1

VAX
-3

ITEM

23/24

05/10 16/20 35/40

J-1

T-1

25. Due to their execution time, FP11
instructions can abort because of a
device interrupt*®
FP1t instructions do not abort because
of a device interrupt.

26. EIS instructions do a DATIP and
DATO bus sequence when letching
source operand.

E1S instructions do a DATI bus sequence
when felching source operand.

217. MOV instruction does just a DATO
S1-4

bus sequence for the last memory cycle.

MOV instruction does a DATIP and DATO
bus sequence for the last memory cycle.

-2

28. If PC contains non-existent memory
and a bus error occurs, PC will have
been incremented.

i PC contains non-existent memory
address and a bus error occurs, PC will

-3

be unchanged.
29. It register contains non-existent

-3

memory address in mode 2 and a bus
efror occurs, register will ba incramented.

Same as above but register is unchanged.

* Integral Hloating point assumed on 11/23 and 11/24; FP11E assumed for 11/60.

N implementation dependent.
2 MOV instruction does a DATI and a DATO bus sequence for lasl memory cycle.
3Does not suppont bus errors.

VAX

ITEM
30. if register contains an odd value in.
mode 2 and a bus errer occurs, registaer
will be incremented.

It register contains an odd value in mode
2 and a bus error occurs, register will be
unchanged.
31. Condition codes restored to original
values after FIS interrupt abort (EIS
doesn't abort on 35/40).

Condition codes that are restored after
EIS/FIS interrupt abort are indelerminate.
32. Opcodes 075040 through 075377

91-d

unconditionally trap to 10 as reserved

opcodes.

If KEV-11 option is present, opcodes
75040 through 07533 periorm a memory
read using the register specified by the
low order 3 bits as a pointer. If the
register contents are a non-existent
address, a trap to 4 occuwrs. If the
register contents are an existent address,
a trap {o 10 occurs.
33. Opcodes 210 thru 217 trap 10 10 as
reserved instructions.
Opcodes 210 thru 217 are used as a
maintenance instruction.

3Does not support bus errors.
4 Unprediclable.
! Traps to native mode.

23/24

LSIN

05/10 16/20

35/40

J-1

T-11
-3

VAX

23/24

iTEM

LSIN

05/10 15/20 35/40

J-1

T-11

VAX

34. Opcodes 75040 thwu 75777 trap to
10 as reserved instructions.
it KEV-11 options is present, opcodes
75040 thru 75577 can be used as
escapes to user microcode. It no user
microcode exists, a trap to 10 occurs.
35. Opcodes 170000 thru 177777 trap to
10 as reserved instructions.

Opcodes 170000 thru 1777717 are

implemented as floating point instructions.

Opcodaes 170000 thru 177777 can be

used as escapes 1o user microcode. I
no user microcode exists, a trap to 10

Opcode 076600 used for maintenance.
+1

36. CLR and SXT do just a DATO
sequence for the last bus cycie.

-2

CLR and SXT do DATIP-DATO sequence
for the last bus cycle.

37. MEM MGT maintenance mode MMRO
bl 8 is implemented.

MEM MGT mialtonancs mods MMNO bR
8 is not implemented.

38. PS<15:12>, non-kernel mode, nonkernei stack pointer and MTPx and
MFPx instructions exist even when MEM
MGT is not configured.

~1 Traps (o nalive mode.
+ Unprediclable.
2CLA and SXT do DATI-DATO.

hLY

LT—-d

OCCurs.

ITEM

PS<15:12>, non-kerne!l mode, nonkernel stack pointer, and MTPx and
MFPx instructions exist only when MEM
MGT is configured.

39. Current mode PS bits <15:14> set
to 01 or 10 will cause a MEM MGT trap
upon any memory reference.

Current mode PS bits <15:14> set 10 10
will be treated as kernel mode (00) and
not cause a MEM MGT trap.
Current mode PS bits <15:14> set to 10
will cause a MEM MGT trap upon any
81-¢€

memory reference.

40. MTPS in user mode will cause MEM
MGT trap if PS address 177776 not
mapped. It mapped, PS <7:5> and
<3:0> affected.

MTPS in non-user mode will not cause
MEM MGT trap and will only affect
PS <3:0> regardiess of whether PS
address 177776 is mapped.

41. MFPS in user mode will cause MEM

MGT if PS address 177776 not mapped.
It mapped, PS <7.0> are accessed.
MTPS in user mode will not trap regardless of whether PS address 177776 is
mapped.
1 Unprediclable.
2CLR and SXT do DATI-DATO.

23/24

LSit

05/10 156/20 35/40

J-11

T-1

VAX

ITEM

23/24

05/10 16/20 35/40

J-1

T-11

VAX

42. Programs cannol execute out of

internal processor registers.
Programs can execute out of internal
processor registers.

43. A HALT instruction in user or supervisor mode will trap thru location 4.
A HALT instruction in user or supervisor
mode will trap thru location 10.

-2

44. PDR bit <0> implemented.
< 0> not implemented.
PDR bit-

61-4

45. PDR bit <7> (any access)
implemented.

PDR bit <7> (any access) nol
implemented.

46. Full PAR <15:0> implemented.
Only PAR <11:0> implemented.
47. MMR0O< 12> —trap-memory

management—implemented.
< 12> not implemented.
MMRO0

48. MMR3<2:0> —-D space enable—
implemented.

MMR3 < 2:0> not implemented.

49. MMR3<5:4> —IOMAP, 22-bit
mapping enabied—implemented.

MMR3<5:4> not implemented.

VHALT pusi\es PC 8 PSW lo stack, loads PS with 340 and PC with < powerup address> + 40.

2Yraps 10 native mode.

23/24

ITEM

50. MMR3 < 3> —CSM enable—
implemented.

MMR3 < 3> not implemented.

51. MMR2 tracks instruction fetches and
interrupl -vectors.

MMR2 tracks only instruction fetches.
52. MFPx %6, MTPx when PS<13:12> =
10 gives unpredictable resulls.

MTPx %6, MTPx %6 when PS<13:12> =
10 uses user stack pointer.
55.

The ASH

0c-d

source

left
the

instruction with a

operand

of octal

times)

will

decimal

instead of

to be

left.

shifted

(shift

cause
right

S6. The ASHC instruction with an
octal value of 37 (shift left 31
decimal times) in source operand

bite 5:0 and bits

1516 of

operand being

zero,

non

the

will

the register to be shifted
instead of left.

cause

right

05/10 15/20

35/40

J-11

T-1

VAX

APPENDIX

BACKPLANE TEST CONNECTORS

BACKPLANE

TEST

CONNECTORS

NEW CONN
PIN #

SIGNAL

Jl8-34
J18-33
Jlg-32
Jlg-31
J18-30
J18-29
Jlg-28
Jl8-27
Jl8-26
J18-25
Jl8-24
J18-23

DCLO
ACLO
BR7 L
BR6 L
BRS L
BR4 L
PA L
PB L
MSYN L
SSYN L
ClL
CoO L

Al7

Jlg-21

Alé

J18-19
Jlg-18
J18=17
Jlg-16
J18=15
Jl8-14

Al4
Al3
Al2
All
AlO
AO9

L
L
L
L
L
L

Jig-12
Jig-11
Jlg-10
Jlg-9
Jl8-8

A07
A06
AOS5
AO4
AO3

L
L
L
L
L

J18-6
J18-5
J18-4
Jlg-3
Jl8-2
Jlg-1
Jl9-20
J19-19
J19-18
J19-17
J19-16
J19-15
Jl9-14
J19-13
J19-12
J19-11
Jl9-10
J19-9
J19-8
J19-7
J19-6
J19-5
J19-4
J19-3

A0l L
AOO L
BBSY L
NPR L
GND
GND
D15 L
D14 L
D13 L
Di2 L
D1l L
D10 L
D09 L
D08 L
DO7 L
D06 L
DO5S L
DO4 L
DO3 L
D02 L
DOl L
DOO L
INTR L
SACK L

J19-1

GND

J1l8-22

J18+20

J1l8-13

J1l8-7

Jl19-2

AlS L

AO8 L

A02

GND

APPENDIX

BACKPLANE

PIN ASSIGNMENTS

BACKPLANE PIN ASSIGNMENTS

GND

ARG

ASV

|ASSYN | asv

ABG

GND|

ASEL | GND

LTC

01s

A OUT | BR?

AY?

Low

D14

ASEL | BRE

013

ASEL | BRS

D11

012

B8R4

NPG

mu-

(1IN}

OUT)

°
-

€

f
"
!

AINT | D10

t
D09

A INT | DOB

ENSB

00?

D04

HALT | DOS

s
T
v
v

1DE

ROW

IN M
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82

V.7

V.6

APPENDIX

ROM

DIFFERENCES

COPE

V.7

V.6

ROM

CODE

F.1

INTRODUCTION

The

command

DIFFERENCES

descriptions

for

the

ROM

code

assume

that

the

EPROMs

installed
are
at
Version 7.0 (V7.0) Earlier PDP-11/84s contain
EPROMS with V6.0 ROM code.
The version of the ROM code is
typed
out
each
time
Set
up
mode is entered from Dialog mode and 1is
displayed in the upper right corner of the printout.
It
1is
not
necessary
to
remove
the
CPU
module to determine the ROM code
version number.
The following lists the
ROM
part
numbers
and
version

numbers.

Socket
on CPU

El116
E117

F.2
V6.0

BOOT
ROM

Location
(M8190)

(Low
(High

SUPPORT
code

Part

Byte)
Byte)

FOR TAPE

does

not

Number

V7.0

Part

23-116E5-00

contain

DEVICES

(TUS81)

built

tape

MSCP

the
ROM

TU81
tape
drive.
The TU81 could be booted if
tape MSCP boot was installed in the UBA board or

the

EEPROM.

V7.0

ROM

The

device

F.3

V7.0

In V7.0

code

has

name

DISABLE

built

tape

MSCP

bootstrap

for

a M9312
written

type
into

boot

program

for

the

has

been

added

allows

the

TUS8l.

MU.

SETUP

Setup mode

parameters

V6.0

23-077E5-00
23-078E5-00

23-117E5-00

MSCP

Number

command

MODE

PARAMETER

another parameter

(2).

This

command

user

the

disable

entry into Setup mode if force Dialog mode is not selected.
This
command
was added to prevent unauthorized entry into Setup mode.
This
<change
assumes
that
the
force
Dialog
mode
switch
1is
controlled or that switch 5 on the KDJ11l-B CPU is "ON" to prevent
unauthorized
When

all

access

Setup mode

references

will

cause

V6.0

Setup mode

F.4

V7.0

Setup

disabled

the

invalid

DISABLE

In V7.0 in
Parameters

can

ALL

mode.
and

Setup

the

ROM

command

are

command

always

TESTING

response

entered

code

Dialog

mode

eliminated.

Typing

Setup

from

is
the

Dialog

ROM

code.

mode.

PARAMETER

Setup
mode
Command
2.

another
parameter
has
been
added
to
When
set,
this parameter disables all
memory and cache test- ing if force Dialog
1is
not
set.
Force
Dialog causes all testing to be run.

F-2

F.5

V.6

V.7

ROM CODE

DIFFERENCES

FOR ROM BOOTS

MNEMONIC

In V7.0 under the B mnemonic for ROM boots the address located at
on the Unibus must be an even
type device
M9312
a
on
173024
In
data.
address
of the
check
only
This is the
address only.
odd.
be
could
but
greater
or
165000
be
must
address
V6.0 the
F.6

EDIT/CREATE

COMMAND

In V7.0 in the edit/create

command

boots, the highest unit number entry is now decimal.
an

user had to type in

was

which

EEPROM

In V6.0 the

converted

value.

decimal

F.7

number

octal

for

mode

Setup

TRAP TO

LOCATION

on either
In V6.0 - for UNIBUS systems only - if a ROM is found
in the
found
not
is
mnemonic
the
and
module,
M9312
the UBA or the
will
code
ROM
the
s,
description
device
for
table
Up
Look

to location 4 due to an error in the V6.0 ROM
trap
unexpectedly
This problem only occurs if the List command is executed.
code.

This problem does not affect the Boot command.

The ROM can still be booted even if there is
command.

list

1in

the

corrected

problem

The system does not hang and the user may reenter

This problem has been

Dialog mode by typing <CR>.
V700.

F.8

DISK

For V6.0

MSCP

BOOT

AUTO

ROUTINE

the boot

(device name A),

in the MSCP auto boot

will

Only drives attached

try fixed media units from 0 to 7.

program

then it will

try to boot removable media from units 0 to 7,

the

at the standard disk MSCP address (172150) are trieaq.

controller

The MSCP auto boot does not support unit numbers above 7, and the
will hang if the controller has a unit number greater
boot
auto
than

that responds.

the boot program will

For V7.0 in the MSCP auto boot,

remov-

able

media units

media

from 0

from

to 255.

try to boot

wunits 0 to 255, then it will try fixed
For

unit,

each

the

Dboot

program

present

Dbefore

to boot using the standard disk MSCP address, if this
attempts
fails the boot program will attempt the same urit number from the
first

floating

continuing

the

disk

MSCP

next unit

device

1is

number.

address
at
be
would
The first floating controller if present,
The main advantage
no devices from 160010 to 160330.
if
160334
F-3

V.7

ROM

V.6

CODE

DIFFERENCES

of V7.0 is that it allows a user to add a second disk MSCP device
making any entries into the translation table as long as
without
the controller address is
set
according
to
the
floating
CSR
address

F.9

rules.

DISK

MSCP

When trying

BOOT

DIFFERENCES

to boot a

device

wusing

the

Dialog

mode

Boot

the V7.0 code will automatically try the first floating

command,

controller also if the standard controller reports
an
error
of
type as long as the standard controller exists (no timeout).
any
If an error occurs on both controllers the
V7.0
ROM
code
will
error messages for each controller starting with the
out
print
standard

address

first.

Nonexistent error messages are not typed out unless the
unit
1is
If the second controller does
non- existent on both controllers.
not exist at the proper floating address the ROM code will
print
out only messages associated with the standard controller.
If the translation table is used, or the /A switch is
wused
then
only
one
controller is tried regardless of the existance of two

or more

controllers.

COMMAND

F.10

INITIALIZE

V7.0

has been changed

PMG

value

count
for

the

v7.0

ROM

F.11l

MEMORY

such

that

the

initialize

value to 7 as opposed to 0
PMG count

for

all

command

for V6.0.

sets

the

The recommended

KDJ11-B's with

both V6.0

and

code.

TESTING

In V7.0 code all consecutive memory starting from location
0
1is
written
at
least
once
at power up unless all testing has been
disabled.
In V6.0 memory above 248 KB may not be written if
the
long memory test is disabled or CTRL C is typed.
F.l12

POWER

UP OR

RESTART

MODE

SET

For V6.0, the ROM code checks for the presence of
Unibus
and
sets
up
the
KMCR
accordingly.
Before emulating
recovery trap through location 24, the ROM code:
1.

Reads

and

saves

the

contents

location

24,

memory
power

V.7 - V.6

ROM CODE DIFFERENCES

Executes a quick read/write test on location 24, and

Restores the orginal contents of location 24.

the
When the test is successfully completed the ROM code loads
ion
locat
the
and jumps to
contents of location 26 into the PSW ion
24 1is tested, ROM
locat
Since
24.
ion
locat
specified in
memory cannot be present in the lower portion of memory.

For V7.0, the ROM code does not check for Unibus memory and
assumes that when mode 24 was selected that the system had the
final configuration of memory already installed. Location 24 1is
not tested, and it is possible to have ROM in the lower portion
of memory. The ROM code loads the con- tents of location 26 into
the PSW and jumps to the location specified in location 24.
F.13 POWER UP SET TO 3 WITH BATTERY BACKUP
For v6.0

if:

3 at power up,

The selected mode

The battery indicates that the voltages are lost, and

The Ignore Battery function is not set, fthen

Go to Dialog mode regardless of the restart mode selection.

For V7.0

if:

is 3 at power up,

The selected mode

The battery indicates that the voltages are lost, and

The Ignore Battery function is not set, then

Execute the Restart mode selection if it

F.14

otherwise go

to Dialog mode.

not

mode

ENABLING HALT ON BREAK

V6.0 ROM code will not enable the Halt on Break bit in

the

BCSR

until either one break has been received and discarded, any valid
character has been received except XON, or the ROM code has given
up control of the CPU. This was done to allow the ROM code to
ignore the break that often comes from certain terminals when
they

are

powered

up.

V.7

V.6

V7.0

ROM

the

CODE

Halt

"Testing
1in
Since halt on
environment,
In

either

keylock

F.15

CTRL

this

bit
1is
set
Please
wait
generally enabled

feature

the

switch

Break

progress
break is

case,

the

DIFFERENCES

AND

Halt
is

CTRL

was
on

not

Break

the

needed
bit

SECURE

immediately
after
the
message" is printed out.
only
in
a
single-user

and

does

has

not

been

have

removed.

any

effect

position.

ECHOING

V6.0 during keyboard input CTRL R and CTRL U are echoed
as
R
U.
1In V7.0 these inputs are not echoed.
The functions still
work the same as before.
These functions are not echoed
because
the
wup
arror
""
<character
1is
not
always
available
on all
terminals.
and

F.16
In

SETUP

V7.0,

was

COMMAND

Command

originally

console

when

Setup

included

terminal

the

wuser

changed

mode

allow

has

deleted.

different

automatically

from

been

English

character

selected

text

Special

characters used in other
representations

fallback

Setup mode
command is

F.1l7
In

V7.0,

the

BOOT

SEQUENCE

text,

since
ASCII

the

ROM

code

local

all
text
characters

1langauges
are
represented
in
standard ASCII.
In V7.0

the description for Command
typed, it is ignored.

AUTOMATIC

command

sets

the

local

text to English.
The command is
not
required
printed
on
the
screen
uses only the standard
which are generally available on all terminals.

using

The

is:

Reserved.

by
in
the

MESSAGE

ROM

code will print out a
message
indicating
when
boot
sequence
1is started when auto boot mode is
message indicates that all
tests
are
complete,
and the ROM code is starting the auto boot sequence.
In V7.0 the
ROM code will print out the name and unit number
of
the
device
booted after the starting system message.

the
automatic
selected.
This

The

following

V6.0

example:

examples

illustrate

the

V7.0

and

V6.0

messages.

V.7

Testing

Memory

in progress - Please
size 1is 512 K Bytes

Step

memory

Step

Starting

V7.0

V.6

ROM

CODE

DIFFERENCES

wait

test

345

system

example:

Testing

Memory

size

Step

memory

Step

progress
1s
3

512
6

automatic

Starting

system

BOOT

single

Please

Bytes

wait

test

Starting

F.18

COMMAND

boot

from

LIST

DUO

ADDITION

letter mnemonic

(L)

has

been

added

the

list
in
V7.0.
L
causes
the
automatic
Loot
continously
loop
until
one
of
the
selected
successfully
booted.
Normally, the last device in

boot

command

sequence
to
devices
is
the auto boot

table is followed with the mnemonic E which terminates the table.
If
none of the previous devices where bootable the ROM code will
print out an error message and request input before proceeding.

follows the last device the ROM code will restart the
beginning
and continously try every device in the

the

until

one

booted

the

operator

types

CTRL

table
table

abort

the

sequence.

V6.0

ROMs do not
contain
this
feature.
However,
it
can
be
implemented
by
writting
a
small
EEPROM
booct
to emulate the
feature.
The feature is useful for fault tolerant booting for
a

system
The

must

following

loaded
V6.0

that

into

roms.

continously
the

source

the

EEPROM

that

This

program

try
code

until
and

allows
not

successful

description

the

needed

loop

boot

function

for Vv7.0.

the

occurs.
program

work

for

V.7

V.6

ROM

CODE

DIFFERENCES

.=10000

iProgram

relocatable

;address,
START:

tstb

@#177560

bpl

108

movb
bic

@#177562,r5
#177600,r5

cmp

any characters been typed
yNo-Go exit back to auto- boot
;Yes-Check the character
;Get the character from the RBUF
;Clear off all bits above bit 07
;1Is

208

the

character

;1 Yes-Then
;r5>

set

sboot

10¢%:

another

sHas

r5,#3

beqg

mov

#301,r5

movb

#100,@#177611

return

sLoad

will

CTRL

ROM

code

with

will

cause

the

which

sequence

;This

sand

aborted.

with value

make

fake

for drive

out

the

restart

the

ROM

error

code

auto

boot

;Sequence

20S:

bic

#760,Q#177520

jmp

@#165762

;Make sure
:the BCSR
sReturn to
;If

r5
; boot
sabort

;mode.

the

ROMs

are

selected

the ROM code.
301 then restart the auto
sequence. If r5 is 3 then
the sequence and go to Dialog
is

The following is an example showing the program being loaded
into
the EEPROM.
It assumes there is not already a boot with a device
name (mnemonic) of L.
If there
was,
the
user
would
have
to
delete or rename that boot before saving the
new program.

KDJ11-B

Press
Type

Setup

the
a

mode

RETURN

command

key

then

for

Help

press

the

Edit/create

EEPROM

Type

CTRL

exit

press

1410

Bytes

free

the

EEPROM

Device name
Beginning
address
Last byte address
Start address
Highest Unit number

RETURN

key:

boot
the

RETURN

key

for

New
New

New = L
= 10000
= 10047

= AA
=
=

000600
000615

000600

3
F-8

New

10000

New

377

change

V.7 - V.6 ROM CODE DIFFERENCES
Device

Description

ROM

ODT>

010000/000000

105737

ROM

ODT>

010002/000000
010004/000000
010006/000000
010010/000000
010012/000000
010014/000000
010016/000000
010020/000000
010022/000000
010024/000000
010026/000000
010030/000000
010032/000000
010034/000000
010036/000000
010040/000000
010042/000000
010044/000000
010046,/000000
010050/000000

177560

ROM

OoDT>

ROM

oDT>

ROM

ODT>

ROM

oDT>

ROM

oDT>

ROM

oDT>

ROM

ODT>

ROM

OoDT>

ROM

onT>

ROM oDT>
ROM

OoDT>

ROM

OoDT>

ROM

OoDT>

ROM

CoT>

ROM

oDT>

ROM

oDT>

ROM

OoDT>

ROM

oDT>

ROM

oDT>

BOOT

100007
113705
177562
42705
177600
22705
3
1405
12705

301
112737
100
177611

42737
760

177520
.
137
165762
~2Z (exit)

KDJ11-B Setup mode

Press the RETURN key for Help
Type a command then press the RETURN key:
Save boot
Are

you

into

sure

the

EEPROM

0=No,

l=Yes

Type a command then press the RETURN key:

Writing the EEPROM - Please wait
KDJ11-B Setup mode
Press the RETURN key for Help

Type a command then press the RETURN key:

F.19

LOCAL LANGUAGE SUPPORT

Local language translations are not supported in V6.0.
supports local language translations.

Only V7.0

"F.20 ADDITIONAL MAP COMMAND FEATURE

The MAP command in V7.0

has

an
F-9

additional

feature.

will

v.7 - V.6 ROM CODE DIFFERENCES

determine the speed of the J11 crystal. This is done by counting
the number of SOB instructions that can be executed out of cache
during one 20 ms cycle of the internal DLART clock.

The value is compared against a table of standard values, and 1if
it is within 0.1% of any of these then that value is printed out.
If the value does not match, then the actual value is printed
15.206, 17, 18, 19 and 20.
The standard values are:
out .
any errors have occurred during testing the speed will not
calculated.

If
be

APPENDIX

MULTI

BOOT ROM CONTROL TRANSFER

MULTI

G.l

CONTROL TRANSFER

BOOT ROM

INTRODUCTION

In V6.0 and V7.0 of the ROM code, the
routine
which
identifies
boot
identify
correctly
not
will
M9312
the
or
UBA
the
on
ROMs
ROMs which use more than one ROM -for the boot.
Because of
this,
not list and can not be started from the base
will
boots
these
ROM code without using a small EEPROM boot
program
to
transfer
This problem will will be corrected in any
to the ROMs.
control
future

G.2

releases

TRANSFER

the

CONTROL

CPU

ROM

code.

PROGRAM

The following is the simpified program used to
transfer
control
to any UBA ROM or M9312 ROM boot if needed.
The starting address
in location 010020 may have to be changed depending
on
the
ROM
and the socket it is located in.

bcsr

177520

decsr

177730

010000
010002

052737
000200

010004

177520

010006
010010

042737
000010

010012

177730

010014
010016
010020

000261
000137
173012

bis

#200,@#bcsr

bic

#10,@#dcsr

;
s
:

;
;s
H

sec
jmp

@#173012

Note:

The

ROM

on M9312

042737

052737.

module

then

make sure UBA ROMs
are enabled

;
;
s+
¢+

disable diagnostics
go start boot for ROMs
in sockets 1-3 of UBA.
Change 16/173012 to 173212

;

2—-4.

;

Note:

disable CPU ROMs in
173nnn address range

ROMs

change

are

010006

address

1730nn

for

socket

1732nn

for

socket

address

1734nn

for

socket

address

1736nn

for

socket

program

DMCl11/DMR11,

DUP11l,

will

work

DUll

numbers if the user types in
description
as follows when

for

and

the

DL11-E

the
the

DECNET

with

the

ROM

sockets

from

If ROM is not in socket 1 then address in 10020
be adjusted by 200 for each socket as follows:

address

UBA

must

boots

for

following part

correct device name
and
device
program is being loaded into the

G-2

MULTI

BOOT

EEPROM under Setup mode of the CPU ROM code.
numbers start with 23ROM PART NUMBERS

86229,

865A9,
868A9,
926A9,

863A9,

866A9,
869A9,
927A9,

864A9

B867A9
870A9
928A9

(e.g.,

23-86A9-00).

DEVICE NAME

XW
XU
XL

ROM CONTROL TRANSFER

Note that all

part

DEVICE DESCRIPTION

DMC11/DMR11

DUP11
DU1l1l
DL11-E

The same general program could be used for any multi ROM boot or
ROM boot which does not follow the M9312 ROM format
single
any
The starting address may have to be adjusted to start
standards.
the

boot.

the
of
an example
1is
following
The
G.3 EEPROM LOAD EXAMPLE
DMC11/DMR11
DECNET
the
for
EEPROM
the
into
loaded
being
program
boot

ROMs.

MULTI BOOT ROM CONTROL TRANSFER

KDJ11-B Setup mode
Press the RETURN key for Help

Type a command then press the RETURN key: 13
an

Edit/create

free

Bytes

1410

to exit or press

Type CTRL

EEPROM boot

address
Beginning
Last byte address
Start address
Highest Unit number

ROM

010000/000000
010002/000000
010004/000000
010006/000000
010010/000000
010012/000000
010014/000000
010016/000000
010020/000000
010022/000000

oDT>

ROM

OoDT>

ROM

ODT>

ROM

ODT>

ROM

ODT>

ROM

ODT>

ROM

OoDT>

ROM

oDT>

ROM

oDT>

ROM

OoDT>

KDJ11-B

Press

New

10000

000615
000600
3

New
New
New

10021
10000
15

New

DMR11/DMC11

052737

000200
177520
042737
000010
177730
000261
000137
173012
~2

Setup mode

into

Are you

sure

Writing

the

change

New

the RETURN key for Help

boot

000600

Type a command then press the RETURN key:
Save

for

Description

Device

RETURN key

the EEPROM

name

Device

the

EEPROM

0=No,

l1=Yes

Type a command then press the RETURN key:
EEPROM -

Please wailt

APPENDIX

CONFIGURATION REGISTER MODIFICATION

CONFIGURATION REGISTER MODIFICATION
H.l

INTRODUCTION

and . Diagnostic
Figure H-1 shows the format of the Boot
ons to-external
connecti
the
and
Configuration Register (BCR)
without
modified
be
to
values
switches which allow the register
of the
15-8
bits
Since
module.
CPU
the
to
gaining accessregister are not driven they may be read as 1 or 0.

In order for a register bit value to be remotely

controled,

the

switch which controls that bit on the KDJ11-B module must be OFF
Whian a
to allow control to be passed to the external switch.
grounded
is
line
nding
correspo
the
ON,
is
KDJ11-B module switch
which causes the register bit to always be read as a 0 regardless
of the position of any external switch.

PDP-11/84

Bits 7-4 <Switches 1-4> are not connected remotely

The bits must be set at the KDJ11-B module switch pack
systems.
unless a custom cable is built and connected to an external
switch

the

user.

bits

also connect
systems.

By connecting J3

external switches it would be
possible to remotely control
these four bits in custom
applications.

connects to the Force Dialog
mode switch on the rear panel
by way of
module.

connect

select

the

<Switches

2-0
to

switch on

the

panel by way of J2
KDJ11-B module.

dDm m e

KDJ11-B

6-8>

BAUD rate

rear

don't care
FIGURE H-1 BOOT AND

e L DL bl DD Dl Sttt

the

DIAGNOSTIC

CONFIGURATION

The 8-position switch pack is mounted at the handle end of the
6-8 select the baud rate for the DLART chip.
Switches
KDJ11-B.
read-only BCR at
the
Switches 1-8 correspond to bits 07-00 in
address

H.2

ROM

17777524.

INTERPRETATION

CODE

The following paragraphs describe how the ROM code interprets the
The ROM code only looks at
BCR when it is read.
the
of
values
register bits

7:3

<switches

1-5>.

NOTE

a
when
that
assumes
discussion
The following
pulled
is
it
to
connected
line
switch is OFF, the
If an external device is
HIGH by the CPU module.

grounding

considered

switch

1line

then

the

switch

1is

ON.

When using an

device

external

ocontrol

the

selections, any switch on the CPU that goes to an
to
external switch should be OFF to pass control
the

external

device.

Normally switches 1-5 are OFF and the EEPROM

contents

what action is to be taken at power up or restart.

When off,

Dialog

Switch 5 unconditionally forces

the ROM code

at the completion of the selected tests.

mode

cannot occur

Switch 5

determine
to

enter

Auto boot

is OFF.

and all
1is disabled
the console
If Switches 5 and 1 are ON,
be
cannot
mode
Dialog
1is suppressed.
output to the console
will
program
the
console,
the
at
occurs
input
any
If
entered.
transmit an error message to the console indicating the console
is

disabled.-

If Switch 5

is ON and Switches

2-4 are not equal to octal 0 or 7,

then Auto boot mode is selected with the device and unit number
to be booted determined by a table in the EEPROM and the value in
switches

2-4

(1-6).

system.
PDP-11/84
There are default values in the table for the
they
user
the
of
needs
the
meet
not
do
devices
default
these
If
The selections can be
can be changed in setup mode to any value.
The
or any EEPROM boots.
ROM boots
UBA
boots,
ROM
standard

CONFIGURATION

selections

are

changed using

setup

Command

Refer to subsection 4.3.4 for more information on

Setup

Command

Setup

Command

information on

for more

Refer to subsection 4.3.6
6.

Interpretation of

the

BCR by

the

X = Don't care

0 = ON

1 = OFF
12345¢6 738
76 54 3210

ROM code.

Switch number on KDJ11-B module
Register bit
OCTAL

ACTION

POWER

Console enabled. Unconditionally

X XXX1XXX

TAKEN AT

transfer control to dialog after
running tests. (FORCE DIALOG)

The Force Dialog switch - located at the rear of the box
cabinet

drives

bit 3 LOW (0)

when

Dialog switch is ON bit 3 is high (1)

KDJ11-B module

For the following,

baud

rate.

the

as long as Switch 5 on

the

OFF.

the console is enabled and switches

Auto

selections Switch Boot 1

boot

6-8

select

mode is automatically selected for

to Switch Boot 6

(SB n)

from Setup

mode

1 1110XXX
11100XXX
11010XXX
11000XXX
10110ZXXX
10100XXX
1 0010XXX
1 0000XXX

36X
34X
32X
30X
26X
24X
22X
20X

Dispatch according to EEPROM
Auto boot 6th selection from
Autp boot 5th selection from
Auto boot 4th selection from
Auto boot 3rd selection from
Auto boot 2nd selection from
Auto boot lst selection from
Power up to ODT immediately.

Setup
Setup
Setup
Setup
Setup
Setup

Command
Command
Command
Command
Command
Command

We N0 ) B0,

Command

When the Force

(o )% e )W

the

it is OFF.

CONFIGURATION REGISTER MODIFICATION

Dispatch according to EEPROM has four pocssible modes.

Auto

mode,

Dialog

Setup mode Command 4,

boot

Halt

mode

and

ODT

enter

(power fail recovery).

location 24/26

For the following the console is disabled and
Auto

used.

not

boot

mode

They

are

trying 1 to 6 devices defined by

through

vector

switches

6-8

are

automatically selected for all

1is

-selections.

45
4 3

7 8

Don't

care

Switch number on KDJ11-B module
Reg ister

ACTION TAKEN AT POWER UP

OCTAL

16X
14X
12X
10X
06X
04X
02X
00X

01110XXX
01100XXX
01010 XXX
01000XXX
00110 XXX
00100XXX
00010 X XX
0 00 0O0XXX

bit

boot

Auto
Auto

boot

Run

stand

according

6th
Auto boot 5th
Auto boot 4th
Auto boot 3rd
Auto boot 2nd
Auto boot lst

Command 4
Command
from Setup Command
from Setup Command
from Setup Command
from Setup Command
from Setup Command

Setup

selection
selection
selection
selection
selection
selection

from

alone mode tests

Setup

in a loop at

power up.

The following list specifies the default values for SB 1 to SB
if

the EEPROM is initialized in setup mode.

The

user may

change

the values to any they desire by using setup mode Command 6.
SB

MSCP Automatic

SB
SB
SB

2
3
4

DLO
MSO
MUO

SB
SB

5
6

RLO1, RLO2
TS11, TU8O
TU8l1, TKS50
(Not set)
(Not set)

boot

sequence

Table H~-1 shows how to select the baud rate for the

Console

SLU

Switches 6-8 on the
select switch.
Rate
switch
select
KDJ11-B module must be OFF to allow the Baud rate
when

using

the

Baud

to correctly select

the

Baud

rate.

= OFF

CONFIGURATION

MODIFICATION

TABLE

H-1

Baud

rate
Selected

38400
19200

the
Oor

H-2

BCR

position

bits

2:0

0
1

000
0 01

9600
4800

@
@

mem==———em=mmm——-

2
3

010
011

2400

m=m—e—-

————e——-

600

@ mmemm———

100
101
110

300

mee—e———-

111

select

the

—==——-—mmeee-

how

SELECTION

Switch

KDJ11-B module
has

shows

RATE

1200

Table

BAUD

the

Baud

removed

due

TABLE

H-2

KDJ11-B

baud

rate

select

with

failure.

SWITCH

OFF

SELECTION

ON)

KDJ11-B

BAUD

DATA

READ

MODULE

RATE

FROM

BCR

SWITCH

38400

0060

0
0

0
1

1
O

19200

9600

01
010

4800

011

1
1
1

0
0
1

O
1
O

2400
1200
600

101
110

300

111

100

the

switch

switches

not

present

APPENDIX

FLOATING

POINT

INSTRUCTION TIMING

FLOATING

POINT

INSTRUCTION

TIMING

Since the FPJ1l is a coprocessor operating in parallel
with
the
J11 chip set, the calculation of floating point instruction times
for Jll1 systems (usinf the FPJ11l option) must take this
parallel
processing

into

account.

TERM

DEFINITION

FPJ1l1l cycle

Two clock periods

J1l nonstretched cycle

Two FPJ1ll cycles

J11l

read cycle

(110 ns @
(220

J11 nonstretched cycle

Dependent

read

18 Mhz)
18 Mhz)

if cache hit.

access

time

systemif cache miss the minimum is
two J11 nonstretched cycles, after
which the J1l1 streches in 1/2-cycle
increments

" J11 write cycle

Instruction Decode

until

MCONT

asserted.

Dependent on write access time of

system(two J11
until MCONT)

cycles

1/2

cycles

A decode/prefetch cycle followed by
a MOV microinstruction that allows
the FPJ1l to assert DMR prior to the
start of the next microinstruction
(INPR

for

REG.

mode).This

time

equals

two nonstretched cycles if the prefetch
is a cache hit, otherwise nonstretched
plus

Address

Calculation Time

Transfer Time

read

cycle.

J1ll time required to calculate the address of the operand. This time is
dependent on the addressing mode of the
instruction, the frequency of the system
clock, and whether any indirect data
required is present in the cache.
(See

Argument

one

Table

I-1.)

J11 time required to load or store
floating point operands. This time is
one nonstretched cycle (address relocation ucycle) plus one read cycle per
l16-bit word read from memory for load
class instructions, or one nonstrechted
plus one write cycle per 1l6-bit word to
memory for store class instructions.

FLOATING POINT INSTRUCTION TIMING

DEFINITIONS

INPR

(Cont)

(featemp,TEMP)

J11 support code microinstruction execute for all FPJ1l instructions.
Moves the PC of the previous FPJll

to a TEMP register in case
instruction
that instruction resulted in a floating
point (FP) exception. If the FPJ1l is
still executing the previous instruction when the Jll reaches it's INPR
microinstruction the FPJll asserts
STALL causing the J1l11 INPR ucycle to
stretch.

The J11 then WAITs for the FPJ1ll to
deasset STALL signalling the SYSTEM
INTERFACE to assert MCONT before ex-

ecuting the next microinstruction
(OUTR)
.

WAIT

RESYNC

J11 time waiting for the completion by
the FPJ1l of the previous FP instruction. For Load Class or REG mode instructions, this time from when the
J11 INPR cycle streches at the trailing
edge of MALE until the FPJ1ll deasserts
STALL. This time equals zero if a stall
was not required or if the FPJ1ll deasserted the STALL signal after the INPR
cycle began but prior to the trailing
edge of MALE. Although the WAIT time
for the latter case is zero, RESYNC
time is required. For store class instructions the WAIT time equals the
time between the assertion of SCTL
(i.e., when the SYSTEM INTERFACE is
ready to execute the first write cycle
of a FP store) and the assertion of
FPA-RDY (data ready) by the FPJll.
For Load Class

and REG mode

instruc-

tions the time required to continue

a strechted

INPR.

This

is the

time

for the SYSTEM INTERFACE to recognize the deassertion of STALL and

assert MCONT, plus the time required
for the J11 to synchronize MCONT and

FLOATING

DEFINITIONS

POINT

INSTRUCTION

TIMING

(Cont)

advance to the next microinstruction.
Store class instructions normally do

not have RSYNC

time

since

the

-waiting in a stretched WRITE
and the continuation time is
WRITE c¢ycle. However, if the

executing

a previous

Jll

cycle
part
FPJ1ll

MODF/D or DIVD,

the

FPJ1l

will

stretch

non-I/0

cycle

prior

the

first

bus

WRITE.

This

allows

the

SYSTEM

assert

INTERFACE

limiting

the worst

when

waiting

case

WAIT

for
and

STALL

service

case

FPJ1l1l

DMA
time

order

DMA

thus

latency

output.

RESYNC

the stretched non-I/0 cycle
added to the effective execution
of the Store class instruction.

OUTR

(PC,

FEATEMP),

FPE

Last

J11

less

there

support
is

instruction.

this

associated

with

TESTPLA

is
time

microinstruction
FPE

from

Saves

the

address

un-

decode

in-

FEATEMP.
PRDC

SYNC

Time

required

by FPJ1l

struction tion and begin execution after
receiving PRDC. This time equals two or
three FPJ1l cycles depending upon synchronization. PRDC SYNC is not added to
FPJ1l instruction execution times when
the FPJ1l is executing a previous FP in-

struction

Floating

Point

Execution

Time

the

required

instruction
arguments.

once
For

assertion
FPJ1l
it

has

Store

PDRC.

complete

received

class

all

instructions

floating point execution time includes
the time from the start of the instruction
until the FPJ1l asserts
FPA-RDY indicating the first 16-bit word is available
for output.
(See Table I-2.)

Effective Execution
Time
Load

Total J11

time required to execute a FP

instruction.
class

Instruction
+

Argument

OUTR

Decode
Transfer

Address
+

INPR

Calculation
WAIT

RSYNC

FLOATING POINT INSTRUCTION TIMING
DEFINITIONS

(Cont)

Instruction Decode + INPR + WAIT + RSYNC

REG mode

OUTR

Instruction Decode + Address Calculation

Store class

+ INPR + Argument Transfer + WAIT + OUTR

Load class instructions require input data and deposit results to
REG mode instructions are FP
the destination FP accumulator.
accumulator to FP accumulator.

Execution of a Load class FP instruction by the FPJ1l

parallel

operation

Jll

with

occurs

and can be overlapped.(See Figure

I-1)

Store class instructions can be overlapped by the Jll as the
"FPJ1l will complete a previously started Load class or REG mode
instruction.
store
the
instruction and then continue to
Execution of the store class instruction must be completed before
thus eliminating further
the result can be stored to memory,
parallel processing for store class FP instructions.(See Figure
.

-2)

TABLE I-1 ADDRESS CALCULATIONS TIMES

MODE

LOAD CLASS

0
1
2
3
4
5

0
3
3
3 + RD*
4
3 + RD
3
3
2
2
3
4

6
7
27
37
67
77
-

D T

D D

D T

S G

J11

0
3
2
2 + RD
4
3 + RD

+ RDI
+ RDI
+ RDI + RD
D S T

D N

D D G O

D D D D A

Istream request
Read

Cycle
I-5

+ RDI
+ RDI + RD

2
3
2
1
2
4

+ RDI**
+ RDI + RD

D I GED D D GED G

* RDI = J11

STORE CLASS

+ RDI
+ RDI
+ RDI + RD
G

)

D D 5 X @b e

FLOATING POINT INSTRUCTION TIMING

TABLE

I-2 FPJ11l
(18MHz

INSTRUCTION TIMES
lllns

cycle)

INSTRUCTION

MIN
CYCLES

TYP
CYCLES

MAX
CYCLES

STRETCH
CYCLES

18MHZ
TYP(uS)

ADDF/SUBF

1.0

ADDD/SUBD

1.0

MULF

1.7

MULD

2.9

DIVF

2.7

DIVD

5.4

MODF

3.7

MODD

5.0

CMPF /D

0.4

LDF /D

0.3

LDEXP

0.2

LDCIF/D

1.1

LDCLF /D

1.1

LDCFD

0.4

LDCDF

0.4

STF/D

0.3

STCFI

1.1

STCFL

1.3

STCFD

0.4

STCDF

0.7

STEXP

0.6

0.3

0.4

TSTF/D,LDFPS
STFPS ,CFCC,SET

ABSF/D,NEGF/D

FLOATING POINT INSTRUCTION TIMING

NOTE: Stretch cycles indicate the number of cycles out
of max cycles that a data dependant stretch of one
additional cycle could occur with probability less
than 1% for each additional cycle.

FLOATING POINT

INSTRUCTION TIMING

Jl1

FPJ11

Load class instruction
is prefetched. This
occurrs during previous

instruction execution

!PRDC SYNC

instruction

Sun

!Prefetch next

Su=m

!Instruction Decode

IAddress

fase

Qum

Sum

Calculation

!Argument Transfer
!

FPJ11l loads
operands

!
!
!

_
if

any

f=n

feum

RSYNC

WAIT

{FPJ11
lexecution
!starts
Jun

{INPR
!
-

Swo

{OUTR

faup

instruction

O=w

FPJ11l

—-——-

only

stalls

instruction

The

FPJ1l

can

Gmn

Gum

!Decode

FP and REG mode!

overlap

the

loading of operands for
subsequent load class
instructions

!
!
!
i

--FPJ11l execution
unit done

FIGURE

I-1l

J11/FPJ11

INTERACTION

I-8

FOR

LOAD

CLASS

INSTRUCTIONS

FLOATING POINT INSTRUCTION TIMING

FPJ1l1

J1l1
Store class instruction
is prefetched. This
occurrs during previous
instruction execution

tInstruction Decode
iPrefetch next

instruction

IPRDC SYNC

!
!
i

Jom

{Address Calculation

OJems

IFPJ1]l starts
lexecutioon

gom

FPJ1l places
operands 1in
output buffer
sets FPA_RDY

! INPR
!

!Argument Transfer
J11 waits during first write
if FPA-RDY not asserted
completes

argument

transfer

O=o

1J11l

instruction

Oems

1Decode

Bem>

—

Geany;

1OUTR

FIGURE I-2 J11/FPJ11 INTERACTION FOR STORE CLASS INSTRUCTIONS

APPENDIX

SET-UP

PARAMETER WORKSHEETS

SET-UP PARAMETER WORKSHEETS

PURPOSE

the

set-up

initial

system

The purpose of the following worksheets is to record

parameter

selections contained in the EEPROM of the KDJ11l-BF CPU

module.-

The

worksheets

are

¢to

filled

out

installation, or revised when parameter selections are changed.
future
This information will be wused for programming any
The worksheets are to remain with the
replagement CPU module.
system for

future

reference.

Remove the worksheets from the appendix

required.

and

them

fill

out

Store the worksheets with other system docunentation.

Use a pen to fill out the CURRENT columns and pencil for the
columns.
NOTE

Use Set up Command

to exit set-up mode.

Use Set-up Command 9 to copy the contents of
'set-up table in memory into the EEPROM.
Command 9 should be executed
are made.

after

any

the

changes

NEW

SET-UP

PARAMETER WORKSHEETS

0=No,

ANSI

B -

Power up

0O=Dialog,

(l)=Automatic,

2=0DT,

3=24

O=Dialog,

(1l)=Automatic,

2=0DT,

3=24

Video

terminal

Restart

Ignore

PMG

Disable

Force

Clock

O=Power
ECC

0-(7)

1l=.4us,

clock

Disable

long

K -

Disable

ROM
trap

supply,

0=No,

l=Yes

0=No,

l=Yes

2=60Hz,

3=800Hz

0=No,

l1=Yes

0=No,

l1=Yes

2=Dis

173 4

3=Both

1=Yes

mode

0=No,

l1=Yes

testing

0=No,

1=Yes

0=No,

1=Yes

0=No,

1=Yes

0=No,

1=Yes

0=No,

l1=Yes

Allow

Disable

Setup

Disable

all

P -

Enable

UNIBUS

Disable

UBA

Halt

alternate

165,

0=No,

Enable

1=Dis

4=3,2,...7=25.6

1=Yes

test

l1=Yes

0=No,

Enable

UBA

1=50Hz,

(1)

memory

Enable

3=1.6,

CSR

test

R -

2=.8,

interrupts

—

clock

0=No,

battery

Enable

(1)

boot

memory

ROM

cache
bit

(1)

mode

block

test

(1)

SET-UP

PARAMETER WORKSHEETS

TT1
Device

name

Unit

#
CSR Address

TT2
Device name
Unit #
CSR Address

TT3
Device
Unit #
CSR

name

Address

TT4

Device

Unit
CSR

name

#
Address

TTS
Device name
Unit #
CSR Address

TT6
Device name
Unit #
CSR Address
TT7
Device

name

Unit

#
CSR Address

TT8
Device
Unit #

name

CSR Address

TTO
Device name
Unit #
CSR Address

=
=
=

SET-UP PARAMETER WORKSHEETS

CURRENT

Boot

Device

name

Boot 2
Device

name

Device

name

Boot 4
Device

name

Boot 5
Device

name

Boot 6
Device

name

Boot

NEW

SET-UP

PARAMETER WORKSHEETS

ED EED GE)

TED

GED

SED

SED CHD GED AID

GED

D G

GIp

GED

CEN

GER

GED

GND

TED WED

WWR

GO0

GER WAD

AEP

43D GED

VEP

GED

GMD

GND

Switches

SED

CED

CEp

GED GV

MND

GES

WED

GRS