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EK-1184A-TM-PR1

2000

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Document:	PDP-11/84 System Installation and Technical Reference Manual
Order Number:	EK-1184A-TM
Revision:	PR1
Pages:	322
Original Filename:

OCR Text

VEA
VM S
A

EK-1184A-TM~PR1

PRELIMINARY

PDP-1 1/84?
SYSTEM INSTALLATION
~

AND

—_—

il
i)

TECHNICAL REFERENCE MANUAL

diilgliltlall

EK-1184A-TM-PR1

PRELIMINARY

PDP-11/84

SYSTEM INSTALLATION
AND

TECHNICAL REFERENCE MANUAL

Prepared by Ecducalional

Services

Digital Equipmaent Compor

ation

First

Edition,

May

1985

n"‘.

C>ngita1 Equipment Corporation 1985.
All

Rights

Printed

Reserved.

U.S.A.

The
material
in
this
manual
purposes and is subject to change

Digital
for any
The

Word

is
for
without

informational
notice.

Equipment Corporation assumes no responsibility
errors which may appear in this manual.

manuscript

for

this

Preocessing System.

Educational
Services
Marlboro, MA.
The
following
Corporation:

are

book

Book

was

created

Development

trademarks

production

and

was

Digital

done

Publishing

Digital

Equipment

d]iffitlalt

Micro/PDP-11

DECmate

PDP

UNIBUS

DECUS
DECwriter

P/0S
Professional

VAX
VAXcluster

DIBOL

Q-Bus

VMS

LSI-11

Rainbow

MASSBUS

RSTS

Work

DEC

MicroVAX

RSX

Processor

TABLE

CONTENTS

PAGE

.
.

.
.
Module.

.
.

1.2.1

KDJ11-BF

1.2.2
1.2.3

KTJ11-B UNIBUS Adapter ModulE
MSV11-JB/JC Memory Module
.

1.2.4
1.2.5

UNIBUS Terminator
.
.
Monitor and Distribution

1.2.6
1.2.7

Minimum Load
Power Supply

1.2.8
1.2.9

Console Serial Line Board
Backplane Assembly .
.

Front

1.2.11

Cabinet

1.2.12
1.2.13

Cabinet Blower Unit.
Box Cooling Fans
.

1.4

CHAPTER

2.1
2.1.1

SITE

.
.

.
X

.
.

and
.

Memory Options.

PREPARATION

Site

.
.

Expansion

PREPARATION

.
.

DOCUMENTS.

Cabinet

.
.

Controller

SPECIFICATIONS.

SITE

AND

INSTALLATION

Preparation

.
.

2.1.2
2.2

Box Site Preparation
SHIPPING SPECIFICATIONS

.
.

2.3
2.3.1
2.3.2
2.4

UNPACKING INSTRUCTIONS.
.
.
.
Cabinet Unpacking
.
.
.
.
Box Unpacking
.
.
.
.
.
SYSTEM INSTALLATION
.
.
.
Cabinet Mechanical Installatlon.
Box Mechanical Installation.
.

.
.
.
.

.
.

.
.
.
.
.
.

2.4.1
2.4.2

.
.

2.4.3
2.4.4
2.4.5

Console Serial Line Hookup
Cabinet Switch Settings.
Box Switch Settings.
.

.
.
.

2.4.6

Cabinet

Power

Hookup

2.4.7
2.5

Box Power Hookup
SYSTEM CONTROLS AND

2.5.1
2.5.2

Front Panel.
Console Serial

2.5.3

Serial

2.5.4

Baud

2.6
2.6.1

INDICATORS

.
.

Board

;

2=-17

.
.

2=17
2-18

2-19

.
Line

Communications

Port

Rate

Select Switch.
SYSTEM HARDWARE CONFIGURATION
KDJ11-BF Module Configuration

2.6.2

KTJ11-B

Module

2.6.3

Monitor

and

Dlstrlbutlon

Configuration

Distribution

iii

Module

Configuration

SYSTEM

.
.«

—

Additional

1.3

Assembly

Power

|NMNNN?;)NNI\)NNN

1.2.10

l1.2.14

Panel

Module

Module
.
.

!
= |
> W WHHOYoOoOONOARULUTUTUL
& N - -

Processor

S R S B W

COMPONENTS AND VARIATIONS

| (R G W
— |
O 0000

SYSTEM

1.2

INTRODUCTION

1.1

O
O
e ol SV i ey
|
!
[ RO N I
R
A
VOO JJoahoaoanoanohonUt
N+

INTRODUCTION

SYSTEM

CHAPTER

2-14
2-17

2-19
2-20

.6.4
.6.5
. 7

MSV11-JB/JC

Minimum

Module

Load

EXPANSION

Configuration

2-23

INSTALLATION

2=-24

2-25

2=27

Module

BACKPLANE

7.1
.7

Expansion Backplane

. 7.2
7.

NPG

e /7.3
8

8 .2
9
10

Jumper

Routing

2-28

2-31

SPC MODULE INSTALLATION
.
Cabinet SPC Cable Routing

2-31

2=32

Backplane

SPC

CABINET

BOX

Locations

Cable

BATTERY

Routing

BACK

FUNCTIONAL

Connections

Box

Power

Installation

Lead

SPC

CHAPTER

3.1
3.2

Backplane

7.4

and

2=20

UNIT

.
INSTALLATION

INSTALLATION

2-33

2-34

3=37

DESCRIPTION

INTRODUCTION
.
.
PMI BUS DESCRIPTION
BUS Acquisition
Requests .
.

.
.

3-1
3=2

3.2.1
3.2.2

PMI
DMA

.
.

3-7
3-8

3.2.3
3.2.4

UNIBUS Device Interrupt Requests.
PMI Data Transfer Address Cycle .

.
.

3-11
3-14

3-15

(DATIP)

3-15

3.2.5

PMI

Data

Transfer Protocol

3.2.6

PMI

Data

3.2.7
3.2.8

PMI
PMI

Block Mode Data
Data Out Cycles

3.3
3.3.1

Cycles

(DATI)

In
.

.
and

Cycles
.
.

MEMORY MANAGEMENT .
.
Page Address Registers

.
.

.«
.
.

.
o

.
.

3-17
3-18

.
.

N
.

.
.

3-19
3=-21

3.3.2
3.3.3

Page Descriptor Registers
Memory Management Register

.
O.

.
.

3=21
3-23

3.3.4
3.3.5

Memory Management
Memory Management

1.
2.

.
.

3-25
3-25

.
.
.
.

3=25
3=-26
3=27
3=27

.
.

3-29
3-29

.
.

3-32
3-35

.
.

3-38
3-38

.
.

3-39
3-40

3.3.6
3.3.7
3.3.8
3.4

Memory Management Register 3.
Physical Address Construction.
Memory Relocation
.
.
.
KDJ11-BF CACHE
.
.
.

3.4.1
3.4.2
3.4.3
3.4.4

KDJ11-BF
KDJ11-BF

3.4.5
3.5

Hit/Miss
ADDITIONAL

3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8

Cache Operatlons
Cache Organization

Cache Control
Memory System

.
DESCRIPTIONS

Processor Status Word
.
Program Interrupt Request

.
.
Register

CPU Error Register
.
.
Configuration and Display
Maintenance Register.
.
Boot

Page
Line

.
.
.
.
.
Register
.
.
.
.
.
.
.
.
and Diagnostic Controller Status Register
Control Register
.
.
.
.
Frequency Clock and Status Reglster.
.

3.6

STACK LIMIT PROTECTION.

3.7

KERNEL

3.8

TRAP AND

PROTECTION

INTERRUPT SERVICE

PRIORITIES

3-41
3-42
3-44
3-46
3-49
3-50

3-52

3=-52

3=-53

LINE

UNIT

Transmitter Receiver Status
Break

Data

Buffer

WWWWENNODNDND D

COUNTER

KTJ11-BF
KTJ11-B

MODE

DESCRIPTIONS

CACHE OPERATIONS .
Cache Organization

DMA

Cache

Enable/Disable.

DMA

Cache

Write

DMA

Cache

Read

UNIBUS

Operations
Operations

MAPPING

UNIBUS

Mapping

Optional

Memory

Registers.

UNIBUS

Memory

Configuration

Diagnostic

Controller

W N

AND

Diagnostic
Diagnostic

Data

DATI

NPR

Cycles

DIAGNOSTIC

Response

KERNEL/SUPERVISOR/USER

Status Register.
Data Buffer.

Transmitter

bW+~

SERIAL

Receiver
Receiver

PMG

WWWLWwWwwuwuwwwwwuwwuwwwuwww
www

CONSOLE

Diagnostic

DATO

NPR

Cycles

CHAPTER

4.1
4,2

4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6

4.3
4.3.1

BOOTSTRAP

AND

Status

DIAGNOSTIC

INTRODUCTION
.
.
DIALOG MODE COMMAND

ROM

DESCRIPTIONS

PROGRAMMING

Help

Command

Boot

Command

.
.

.
.
.

.
.
.
.

.
.
]
.

.
.
.
.

.
.

List Command
Setup Command
Map Command .

Test Command
.
.
.
.
SETUP MODE COMMAND DESCRIPTIONS
Setup Command 1 .
.
.
.

Setup

Command

4.3.3
4.3.4

Setup
Setup

Command
Command

3
4

.
.

4.3.5

.
.

Setup

.
.

Command

.
.

4.3.6
4.3.7

Setup
Setup

Command
Command

4.3.8
4.3.9
4.3.10

8 .
9 .
10

.
.

)
.

.
.

.
.
N

4.3.2

4.3.11

Setup Command
Setup Command
Setup Command
Setup Command

4.3.12

Setup

Command

4.3.13

11
12

Setup

Command

4.3.14
4.3.15

Setup
Setup

Command
Command

14
15

.
.

4.4
4.5
4.5

DIAGNOSTIC

ERROR

BOOTSTRAP

PROGRAMS

Bootstrap

List

MESSAGES

4-48

4-49

ROM

]

4-49

4-50

o
¢
e

Formats

Single

Multiple

Programs

ROM

015)

Carriage

<LF>

(ASCII

01l2)

Line

$
G

(ASCII
(ASCII

(ASCII

122)
107)

SYSTEM

Boot

o
o

Return

Feed

Internal
GO
.

120) Proceed
(Control-Shift-S)

MAINTENANCE
.

TYPES

TERMINAL

Console

wN
-

(ASCII

]

ERROR MBSSAGE

Error Message

Unexpected

[]
[}

Slash

057)

(ASCII

<CR>

Trap

and

FORMAT

Description

MMU

Error

Code

AIDS

Front Panel
.
.
Module
.
.
KDJ11-BF CPU Module

Mimimum

Descriptions

Program Error Codes/Messages
TROUBLESHOOTING

MDM

.
.
MSV11-JB/JC Memory Module
KTJ11-B UBA Module
.
.

[

=
N

4-50
4-52
4-52
4-54
4-54
4-54

o
o

4-50

Load

Module

FIELD REPLACEABLE UNITS
.
MODULE REPLACEMENT/REMOVAL

.
.

WHN

[]

SYSTEM

[

CONSOLE

[]

Headers

INTRODUCTION

UL DB

Programs

ROM Data Organization
J1l1 MICRO ODT .
.

Program

e
®

W N

BB BRWWWWN -

ROM

DIAGNOSTIC

WWNVHHR~OOO

H WO O JJJ

Installation

ROM

ROM Addresses

SOV

T
N Y
N
N

.
.

Boot

o
0

NN uUNgNNNNoOO
oo ooy o
D

N
o
e

o
o

.
.

Format

BOOT

CHAPTER
gttt vttt
Lot LMoL

General Rules For EEPROM User Boots
ROM FACILITY (M9312 compatible)

4-44
4-46

EEPROM

POWER SUPPLY REMOVAL/REPLACEMENT
.
.
.
Cabinet Power Supply Removal/Replacement

Box Power Supply

Removal/Replacement

CABINET BLOWER REMOVAL/REPLACEMENT
BOX FAN REMOVAL/REPLACEMENT
.
.

.
.

FRONT

.1l

PANEL

Cabinet

REMOVAL/REPLACEMENT

Front Panel

Removal/Replacement

Box Front Panel Removal/Replacement .
CIRCUIT BREAKER REMOVAL/REPLACEMENT
.
.
1
Cabinet Circuit Breaker Removal/Replacement
.2
Box Circuit Breaker Removal/Replacement .
CABINET POWER CONTROLLER REMOVAL/REPLACEMENT
SLU INTERFACE ASSEMBLY REMOVAL/REPLACEMENT
Cabinet SLU Assembly Removal/Replacement
5.13.2
Box SLU Assembly Removal/Replacement
.
bt bt et et bt e

5.14

5.14.1

CPU

BACKPLANE

Cabinet

REMOVAL/REPLACEMENT

Backplane

Removal

4-55
4-55

4-57

5.14.2

5.15

Box

Backplane

CABINET

APPENDIX A CPU

Removal

PERIPHERAL ACCESS

5-42

5-43

INSTRUCTION TIMING

APPENDIX B

PDP-11/84 and HARDWARE/SOFTWARE DIFFERENCES

APPENDIX

PINOUT

APPENDIX

BACKPLANE

APPENDIX

SYSTEM

APPENDIX

V7.

V6.0

ROM

APPENDIX

MULTI

BOOT

CONTROL

BACKPLANE

TEST

CONNECTORS

J18

AND

J19

ASSIGNMENTS

INTERCONNECT

CODE

DIAGRAM

DIFFERENCES
TRANSFER

APPENDIX H BOOT AND CONFIGURATION REGISTER MODIFICATION

vii

CHAPTER
SYSTEM

1.1

INTRODUCTION

The

Series

PDP-11/84

computer
containing
a
accelerator (FPA).
The
set.
18-bit
The

INTRODUCTION

(PDP-11/84-A)

1is

high

performance

Jll
microprocessor
with floating point
processor executes the PDP-11l instruction

The
system
operates
on
Digital Equipment Corporation's
UNIBUS with a 22-bit memory addressing capabiltiy.

system

available

PDP-11X84:

PDP-11/84:

packaged
1in
Figure 1-2.)

kernel

4l-inch
cabinet.
cabinet
provides
.~peripherals.

two

configurations:

system

configuration

packaged

1in

(See Figure 1-1.) The top portion of the
a
10.5-inch
enclosure
for
installing

expansion box
kernel
system
configuration
10.5-inch
rackmountable
enclosure.
(See

NOTE

The

"PDP-11/84"

this

manual

both

cabinet

system

implies

and

box

designation

that

the context
configurations.

used

1in

applies

INTRODUCTION

SYSTEM

FIGURE

1-1

1-2

PDP-11X84

CABINET

PDP-11/84

1-2

BOX

PRODUCT

SYSTEM

1.2

SYSTEM

The

COMPONENTS

system block

Figure

1-3.

A KDJ11l-BF

An MSV11-JB
ECC

One

modules

console

enables
processor

and

module

box product

of:

shown

(CPU),

Adapter Module

Distribution

Minimum

communicate

(PMI)

port

and

Mb ECC memory module(s),

4.,

Interconnect

cabinet

or an MSV11-JC

module(s),

A KTJ1l-B UNIBUS

the

system consists

processor

memory

Monitor

for

kernel

The

AND VARIATIONS

diagram

The

INTRODUCTION

bus

module

Load

Modules

through

the

using

supporting

console

(UBA),

22-bit

(MDM),

and

(MLM).
high-speed

Private

address/l16-bit

data

the

EIA

terminal

RS-232

the

PMI

communication

connected

into

Memory

lines.
standard

the

KDJ11l-B

module.

The

KTJ11-B

UBA

module

UBA

interfaces

supports

processor

memory

addition,

the

and

UBA

all

bus

address/data

all

UNIBUS

serves

MSV11.y

and

the

UNIBUS.

communications

periherals

terminator

for

(options).

the

CPU end

UNIBUS.

CONSOLE
TERMINAL

|
l

KDJ11-8F

CPU.

MEMORY

)

KTJ11-8

UNIBUS

ADAPTER

(UBA)

UNIBUS

MEMORY

UNIBUS

L_Pop’n 1/84-P SYSTEM CABINET AND BOX

FIGURE

>
5

1-3

PDP-11/84

SIMPLIFIED

1-3

]

BLOCK

The

between

DIAGRAM

the

In
the

SYSTEM

The
1-5.

INTRODUCTION

basic
The

cabinet

and

following

box

components

subsections

are

briefly

shown

describe

Figures
the

basic

components.

|__— FRONT BEZELIBLANK)

POWER CONTROLLER

X e Y-- -

|~ CARD CAGE COVER

\\‘

POWER SUPPLY
CIRCUIT BREAKER
M

CARD

]

1-4

and

system

SYSTEM

Table

1-1

specifies

the

system variations.

TABLE

1-1

A-SERIES

PRODUCT

KDJ11-BF,

MSV11-JB

10.5-inch

Box,

Vac

KDJ11-BF,

MSV11-JB

10.5-inch

Box,

Vac

11/84-AA

11/84-AR

KDJ11-BF

Adapter

The

MSV11-JC

11/84-BB

Same

-AB

MSV11-JC

11X84-AA

KDJ11-BF,

single

MVS1ll1-JB

cabinet,

KDJ11l-BF,

(JD)

120

MSV11-JB

Vac

(JD)

cabinet,

11X84-BA

Same

-AA

except

MSV11-JC

11X84-BB

Same

-AB

except

MSV11-JC

Processor

(M8190-AE)
allows

features
8KB

cache

console serial line
boot and diagnostic
In addition
diagnostic

except

40-inch

Module

module

—-AA except

functionality

management,

240

KDJ11-BF

complete

120

Same

11X84-AB

The

VARIATIONS

11/84-BA

40-inch

l1.2.1

INTRODUCTION

240

Vac

Module
is

of
the

quad-height

PDP-11

CPU

Jll

interface

microprocessor,

memory,

unit,
ROMs.

CPU
processor.

programmable

alterable

module

The

with

having
the
KTJ11l-B UNIBUS

Digital's

FPA,

22-bit

UNIBUS.

memory

line

frequency clock,
configuration EEPROM,
and

the
KDJ1l1l-BF
has
six
red
information
during
power-up
green LED indicates dc power to the

LED's

for
displaying
bootstrapping.
A
module.

and

SYSTEM

1.2.2

The

INTRODUCTION

KTJ11-B

KTJ1l1l-B

UNIBUS

interfaces
PMI.
The
mapping,

1.2.3
The

UNIBUS

Adapter

Module

(M8191)

hex-height

that

four

M9312

MSV11-JB/JC

quad-height

vprocessor and memory through the
the
PMI
adapter
1logic¢,
UNIBUS
compatible boot ROM sockets.

Memory

Module

memory module

two

uses

256K

dynamic

MSV11l-JB

(M8637-B)

with

1MB

capacity

MSV11l-JC

(M8637-C)

with

2MB

capacity

modules

RAMs,

and

versions:

The

module

with
the
KDJ11-BF
module
contains:

and

available

Adapter

provide

error

correction

logic,

byte/word,
double-word
the
PMI
bus.
A
red

read,
LED

and block
1indicates

uncorrectable

green

LED

error;

mode
the

indicates

and

supports

write

read operations
occurance
of
the

presence

over
an
5

Vdc

power.

l1.2.4
The

UNIBUS

Terminator

characteristic
end

l.2.5
The

the

UNIBUS

Monitor

(M9302)

impedance

and

120

provides

Distribution

resistive

ohms.

the

The

SACK

network
with
a
module terminates one

turnaround

feature.

Module

(MDM)

gquad-height

module

(M7677)
and
1includes:
power supply voltage indicators, voltage
test points, fan/blower rotation monitor and
nonprocessor
grant
(NPG) jumper selection switches.

1.2.6
The

Mimimum

Load

double-height

load
for
the
module includes

l.2.7

Power

Dc system
H7202-KB.

Module
Minimum

Load

Modules

(MLM)

provide

minimum

=15 Vdc and +5 VBB power supply regulators.
Each
two power supply LEDs, one for each regulator.

Supply

power

provided

two

power

supplies:

H7202-KA

and

SYSTEM

INTRODUCTION

+15
at
2A
60 A at +5 Vdc,
The H7202-KA power supply provides:
Vde,
+3
A
at
-15
Vdc.
It
also provides 3 A at +12 Vdc for
fans/blower and up to 15 A at +5 Vdc to the
PMI
memory.
There
available for the user when one memory module 1is
watts
272
are
used, and

252 watts available when with two

240

memory

modules

are

supply provides overvoltage and over- heating
power
A switch allows the user to select either 120 Vac or

The
used.
protection.

Vac primary power

operation.

The H7202-KB power supply provides power

for
additional
(i.e.,
be
can
it
H7202-KA,
the
to
Similar
backplanes.
expansion)
operated
at
120
or
240
Vac,
and
features
overvoltage
and
The power supply - which connects to the
overheating protection.
877-D/F - provides

+15

Vdec,

1.2.8

The

and

Console

console

the

A at

following power:

-15

Serial

Line

serial

32 A at +5 Vdc,

Vdc

1line

Board

board

(54-16058-)

provides:

EIA

RS232-C
I1/0
port
for
communication
with
the
KDJ11-B,
a
ten-position rotary switch for selecting
the
<console
I/0
port
baud
rate,
and
a
two-position position switch for selecting a
restart

l1.2.9

mode.

Backplane

shown

Assembly

Figure

13-module
slot
dedicated to the
or
quad-height
supports

1-6,

the

backplane

assembly

(70-20650-01)

backplane.
Module
slots
MDM
through
4
are
system kernel.
Slots 5 through 11 support
hexSmall
Peripheral
Controllers
(SPCs).
Slot 12

only guad-height

UNIBUS

jumper

functions,

for slots

switch

located

the

option

through

modules.

are

Backplane

implemented

MDM module.
ROWS

(MDM) M7677

MOM

SLOTS

) ]

)

IXDJ11-8) MBS0

MSVI1

J) M8B3?7

KTJ11-8) ME19)

HEX OR QUAD UNIBUS OFTION

”

MEX OR QUAD UNIBUS OPTION

]

MEX OR QUAD UNISUS OPTION

MODIFIED
it

fi?&‘i

"&?’.’J?

12|

VRS

FIGURE

MEX OR QUAD UNIBUS OPTION

HEX OR QUAD UNIBUS OPTION

“EX OR QUAD UNISUS OPTION

QUAD UNIBUS OPTION

1-6

BACKPLANE

1-7

»”

M7se8

ASSEMBLY

PRIOR

in a

NPG

DIP

SYSTEM

INTRODUCTION

1.2.10

Front

The

front

panel

indicators

A keyed

toggle
three

for

rotory

switch
LEDs

displays

l1.2.11

The

assembly

status

Cabinet

cabinet

power
in the

1.2.12

Cabinet

cabinet

an
all

restart modes.

system

The

supply,

blower

Box

either

power

entering

Unit

cooled

out

capable

Cooling

1In

two-digit

controller

for
the

240 Vac

addition,
octal

LED

for

Vac

cabinet.

blower

unit

and

through
of

the

cooling

rear of
the

120

operation.

the

provides

two AC

outlets

(12-22001-01)

the

optional

The

Air is drawn through the top
the card cage by a
plenum,

mounted

front of
through

the
the

cabinet.
expansion

UNIBUS ‘backplane.
The
operation
to
insure

kit

power

card cage cover
proper
module

Fans

box product is cooled by
bezel.
The
fans
draw air

directs

the

air

horizontally

supply,

and

out

the

The

power

all the power supplies,
peripheral enclosure.

Blower

Additional

B77-D

controller

The

1.2.14

and

status.

supply
and
an
optional
must be
installed
during
cooling.

l.2.13

and

states,

and

system.

Controller

and

status,

power

switches

of the

system halt

below
the
card cage.
cabinet, forced through

power

control

four

877-F

for
top

includes

operator

error

Power

and

one

the

contains

controls

selects

(70-21888-01)

display

switch

diagnostic

primary
located

The

Assembly

display

operation,
unit

Panel

rear

Expansion

system supports

the

three

fans mounted behind the
through the front bezel and a

through
the box.

and

the

card

cage

and

front
plenum
power

Memory Options

following options:

H7231-E,

Cabinet Battery Back Up Unit

H7231-F,

Box Battery Back Up Unit

DDl11-CK,

4-slot Backplane

(PDP-11X84)

DDl1l-DK,

9-slot Backplane

(PDP-11X84)
1-8

(requires M7677-YA)

SYSTEM

1.3

SYSTEM

INTRODUCTION

SPECIFICATIONS

PDP-11/84
system
specifications.
following tables list the
Table
1-2
through
Table
1-4
list the cabinet specifications;
Table
1-5
through
Table
1-7
1list
the
Dbox
specifications.
Supported
peripheral
device specitications are contained in the

The

user's

guide

associated

TABLE

1-2

with

CABINET

that

device.

ENVIRONMEMTAL

SPECIFICATIONS

Temperature:

Operating

Nonoperating

(storage)

deg

(50

deg

-40

deg

(-40

deg

104

deg

151

deg

Humidity:

Operating

108

deg

90%
C

with max

(82

point 2 deg
condensing.

deg

wet

bulb

and

(36

deg

temp.

min

dew

non

Vibration

Operating

0.25

Hz:0.01

Gpk.

octave/min.
Nonoperating

for

(packed

shipment)

Vertical

Grms

Sweep

All

Axis

overall

duration:

DA;

rate

three

500

axis.

Random Vibration:

from

each

1.0

200

0.687

Hz;

axis.

Altitude;
Operating

Nonoperating

9.1

Maximum

maximum operating

with

operating

altitude

2.4

(8000

(30000

be reduced 1.8
(1 deg F/ 1000

Shock:
Operating

Gpk

wave,
Nonoperating

(packaged

shipment)

for

Flat drop
drops

vertical

ft)

ft)
(40

deg C/ 1000m
ft) above sea

(+3

axis

from a 6

total

deg

ms),

1/2

should

level

sine

only

in height,

(vertical

three

direction

only)

SYSTEM

INTRODUCTION

TABLE

Overall

1-3

dimensions

CABINET MECHANICAL

105.7

SPECIFICATIONS

cm high X 53.9

cm wide X

76.2 cm long (41.64 in high
21.25 in wide X 30 in long)

Weight:

Unpacked

150.5

(331

1b)

Packed

182.2 kg

(401

1b)

TABLE

1-4 CABINET ELECTRICAL SPECIFICATIONS

Description

Characteristics
120

Vac

operation:

Line voltage

93 - 132 Vrms, single-phase, two-wire
and ground (120 Vrms nominal)

Frequency

47 .5-63 Hz

Current

(ac)

13.5 A

(rms) max at 120 Vac

Power factor

Greater than 0.60 at full output load

Start Up Current

100 A,

Inrush current

and low input voltage

(93)

0.16 usec duration

160 A (peak) max at 120 Vac,
duration

Power

2880 V-A max*

BTU

3519

240 Vac

operation:

Line voltage

186 - 264 Vrms, single-phase,
two-wire and ground (240 Vrms
nominal)

Frequency

Current

(ac)

47.5-63 Hz

6.7 A

(rms) max at 240 Vac

0.16 usec

SYSTEM

1-4

(Cont)

Power

factor

TABLE

Greater than 0.60 at full output load
and

Start

Inrush

INTRODUCTION

Current

current

low

160

input

0.16

voltage

usec

(peak)

(186

Vac)

duration

max

240

Vac,

0.16

usec

duration
Power

2880

BTU

3519

Noise

Transient:

(both

line voltages)

High-energy

1KV peak

spike

transients

than

Conducted

V-A max*

CW-10

noise

Including mass

0.2

storage

TABLE

KHz

of
to

containing

energy
30

MHz,

per
3

not

spike

Vrms

devices

1-5

BOX

ENVIRONMEMTAL

Characteristic

SPECIFICATIONS

Description

Temperature:

Operating

5 deg C to 50 deg C
(41

deg

Nonoperating

-40

deg

(storage)

(=40

deg

122

deg
deg

151

F)
C

deg

Humidity:

Operating

10% to 95% with max wet bulb temp.
32 deg C (82 deg F) and a min dew
point 2 deg C (36 deg F) non
condensing.
--------------—---q--—.—---_-—----——-

SYSTEM

TABLE

INTRODUCTION

1-5

(Cont)

Vibration:

5 to 30 Hz:

Operating

0.01

in DA;

30 to 500 Hz:

0.5 Gpk. Sweep rate of 1.0
octave/min. All three axes.

Nonoperating

Vertical

(packed

Grms

for

shipment)

Axis

overall

duration:

Random
from

Vibration:

200

0.687

Hz;

each.

Altitude:
Operating

Nonoperating

9.1

Gpk

2.4

(8000

(30000

ft)

for

ft)

Shock:

Operating

wave,
Nonoperating

Flat

drop

drops
Maximum

with

be
(1

(+3

axis

from

total

Maximum

operating
altitude

vertical

ms),

operating

three

direction

(40

deg
ft)

sine

height,

(vertical

reduced 1.8
deg F/ 1000

1/2

only

deg

only)

should

C/ 1000m
above sea

level

Mechanical:
Overall

dimensions

cm high

long X

wide

67.5

(19

10.44

Weight:
Unpacked

42.75

Packed

(130

(95

1b)

long

wide

high)

SYSTEM

TABLE

1-7

BOX

ELECTRICAL

Characteristic

120

Vac

Line

Description

132

and
47.5

Current

8.0

(ac)

factor

Inrush

Current

current

Vrms,

ground

Fregquency

Start

SPECIFICATIONS

operation:

voltage

Power

INTRODUCTION

(120

single-phase,

Vrms

(rms)

max

120

Greater

than

0.60

and

Vac

nominal

120

two-wire

nominal)

0.16

usec

(peak)

max

Vac

full

output

input

voltage

load

duration
at

120

Vac,

0.16

usec

duration
Power

650

BTU

2218

240

Vac

Line

W MAX

operation:

voltage

180

264

two-wire

Vrms,
and

single-phase,

ground

(240

Vrms

nominal)
Fregquency

47 .5

Current

5.0

Power

Start

Inrush

(ac)

factor

Current

current

(rms)

max

Greater

than 0.60

and

Vac

240
A,

0.16

usec

(peak)

max

650W MAX

240
at

nominal

duration
Power

Vac

full

output

input

voltage

load

duration
at

240

Vac,

0.16

usec

SYSTEM

TABLE

INTRODUCTION

1-7

(Cont)

Noise

transient:

(both

line

woltages)

High-energy

transients

KV peak

not

spike

containing

more than 0.2
per spike

W of

energy

Conducted

1.4

Table

1-8

noise

lists

Bus

MHz,

3Vrms

DOCUMENTS
the

TABLE

PDPl11

CW-10KHz

1-8

PDP-11/84

documents.

RELATED DOCUMENTS

EB-17525-20

Handbook

PDP-11/84-A

Installation

and

PDP-11/84 Site Preparation,
Installation Guide
PDP-11/84-A

System

Field

Technical
Unpacking,

Maintenance

Manual

EK-1184A-TM

and

EK-PDP84-1IN

Set

Cabinet:
Box:

MP-02199
MP-02198

KDJ11-B

User Guide

EK-KDJ1B-UG

MSV11-J

User

EK-MSV1J-UG

Chipkit

Handbook

DCJ11l

User

Microsystem

Guide

Handbook

EJ-01387-92
EK-DCJ11-UG

EB-26085-41/85

SYSTEM
- INTRODUCTION

Printed

copies

Digital

Equipment

444

Whitney

Northboro,
ATTN:

the

above

listed documents may

Corporation

Street

Massachusetts

Printing

Customer

and

Services

01532

Circulation

Section

Services

(NR2/M15)

ordered

from:

CHAPTER

SITE

PREPARATION AND

INSTALLATION

and

wunpack
site,
your
prepare
This chapter describes how to
install the system, and verify its operational readiness.
2.1

SITE

PREPARATION

reguirement,
the 'space
system;
PDP-11/84
a
use
In order to
power,
electrical
the
and
limits
operating
environmental
preparation.
site
the
of
part
be
available at the site, should
The specifications are listed in the following subsections.
2.1.1

Cabinet

Physical

Space

width
Height
Depth
Weight
Environmental

Preparation

deg

53.25 cm (21.2 in)
105 cm (41.6 in)
75 cm (31.5 in)
150 kg (331 1b)
Operating

(82

deg

non-condensing

Limits:

Storage Temperature:
151

deg

10 deg C to 40 deg C

(

50 deg

Relative Humidity:

deg

Specifications

Requirements:

Operating Temperature:
104

Site

10%

to 90% with max wet bulb

and

=40

min

temp.

dew point 2 deg C (36 deg F)

deg C to 66 deg C

(=40

deg

SITE

PREPARATION

Temperature

AND

INSTALLATION

Derating

with

operating
temperature
every 1000 m the system
F per 1000 ft)

Altitude:

should
be
is operated

maximum

allowable

reduced by 1.8 deg C
above sea level.
(1

per
deg

AC Electrical waer Requirement:
Depending

the

site

line

voltage,

¢two

power

controllers

are

available:
877-D

Power

Controller:

Voltage

(93

120

132

Frequency

877-F

Power

Controller:

Voltage

Vac

Nominal

Vrms)
-

47.5

(186

Frequency

240

Vac

264

47.5

Nominal

Vrms)

NOTE

dedicated circuit
from
the
power
source
is
recommended for each system.
This circuit should
provide
an
isolated
ground
path
between
the
receptacle an the power source.
The power system
should be stable and free form electrical noise.

Do
not
connect
any
conditioners,
office
the same circuit with

The

user must

supply

the

eqgquipment
such
copiers, or coffee
the system.

following

as
air
pots, on

electrical

power

and

receptacle(s).
NEMA AC

Electrical

Receptacle

Required:

for

120V service:

NEMA L5-30R

for

240V service:

NEMA

The power cord provided
either a NEMA L5-30P, or

2.1.2

Box

Site

6-15R

(rated
(rated

@
€@

30 A).
15

1is
approximately
14
a 6-15P plug attached.

Preparation Specifications

Aa).
feet

1long,

with

SITE PREPARATION AND INSTALLATION

Reguirements:

Space

Physical

Width
Height
Depth

47.5 cm (19.0 in)
26 cm (10.4 in)
67.5 cm (27.0 in)
43 kg (95 1b)

Weight

]

Environmental Operating Limits:

Operating Temperature:

Relative Humidity:

deg

5 deg C to 50 deg C (41 deg F to 122

temp.

=40 deg C to 66 deg C (-40

deg

deg F) and minimum dew point 2 deg C (36 deg F)

(90

10% to 95% with max wet bulb

non condensing

Storage Temperature:

151

deg

allowable
maximum
Derating with Altitude:
Temperature
reduced by 1.8 deg C per
should be
temperature
operating
(1 deg
every 1000 m the system is operated above sea level.

F per

1000

ft)

Requirement:

Power

Electrical

Voltage - 120 Vac
(90 to 132 Vrms)

Voltage

(180

240 Vac
264 Vrms)

Frequency NEMA AC

47.5

Frequency -

47.5

Electrical

Nominal

Receptacle

Requirement:

NOTE
When

from
240

switching

the

Vac

the

120 Vac

operation,

power

(shipped

|
supply

the power

input

configuration)
cord

must

changed.

120 Vac

service:

NEMA 5-15R

(rated

€

15A)

voltage

to the

also

SITE

PRERARATION

240

Vac

AND

INSTALLATION

service:

NEMA

The power
5-15
P,

cord provided is 75
or
a
6-15
P plug

provided,

prefix

2.2

SHIPPING

This

section

NEMA

(rated

€

inches long,
attached.
1If

receptacle

numbers

15A)

with
either
a
NEMA
an isolated ground is

with

"IG".

provides

SHIPPED

information.

reinforced

cardboard

Products

(BOX

containers

Container:

Width:

57.5

Height:

50.8

(23
(20

Length:

77.5

(31

Weight:

(125

in)
in)

in)

1b)

FIGURE

Cabinet

SPECIFICATIONS

CABINET
are
shipped in
in Figures 2-1 and 2-2.

Box

6-15R

2-1

BOX

SHIPPING

CONTAINER

Container:

Width:

Height:

139

(55

Length

107

ecm

Weight

182

(42 in)
(401 1b)

(34

in)

FIGURE

in)

2-2

h\\\\\\\\\\

CABINET

SHIPPING

2-4

CONTAINER

and

shown

SITE

2.3

UNPACKING

Read

the

AND INSTALLATION

INSTRUCTIONS

following

steps

prior

to unpacking
-

product.

2.3.1

PRERARATION

the

cabinet

]

box

Cabinet Unpacking

The
unpacking
container.
To

instructions
are
1located
1inside
the
open the shipping container complete the

shipping
following

steps.

IMPORTANT

Read

warning

labels

remove

plastic

Cut

Remove

top

directions

2.3.2
The

and

Box

outside

container.

strapping.

cover.

packed

inside

Unpacking

unpacking

container.

1instructions

open

the

are

shipping

1located

container

1inside

the

shipping

complete

the

following

steps.

IMPORTANT

Read

and

warning

labels

remove

plastic

Cut

Carefully

Open

cut

folded

sealing

top

directions

outside

container

strapping.
tape.

container.
packed

inside.

2.4 SYSTEM INSTALLATION
To install a cabinet or box read the appropriate
subsection
and
follow
the
procedures.
The
procedures
do not cover optional
device installation.
Option
installation
1is
covered
1in
the
manual supplied with the device.

2=5

SITE

PRERARATION

2.4.1

Cabinet

install
1.

AND

INSTALLATION

Mechanical

the

cabinet

Installation

complete

Complete

the

shipping

container.

unpacking

the

1instructions

After

rolling the cabinet
cabinet on a level surface

3’

Reverse

four

step

leveling

the

feet.

near the foot above the floor

following

down

is raised
surface.

foot

instructions

the

Raise
while

each top nut and tighten it
holding the bottom leveling

2.4.2

Box

the

box

following

1inside

the

position

the

area.
and

until

1/8-

lower

the

wheel

1/4-inch

cabinet.

mechanical

Mechanical

install

the

lowered

approximately

Level

completes

ramps,
operational

This

located

the

unpacking

Each

procedure.

against the cabinet
foot hex nut.

installation

frame

procedure.

Installation

ANSI/EIA

standard

19-inch

rack,

complete

procedure.

Locate

Mount the chassis slide bracket by aligning the rack
frame
holes
with
the
slide bracket.
Secure the bracket to the
frame with a nut bracket and three no.l0
screws
(no
star
washers).
Tighten the screws.
(See Figure 2-3.)
Mount
frame

and

check

hardware

the three other
as in step 1.

chassis

the

box

slide

shipping

brackets

container.

the

rack

SITE

PRERARATION AND

INSTALLATION

NUT PLATE

FIGURE

2-3

MOUNTING

CHASSIS

Mount

the

restraint

SLIDE

bracket

AND

the

RESTRAINT

rack

BRACKET

frame

the
bracket
holes with the rack frame holes,
holes above the mounted chassis slide bracket.

tighten
bracket.

three

no.l0

screws

into

the

nut

bars

aligning

starting
Thread

secure

two
and

the

Align the right chassis slide (front) clearance
hole
with
the
center
hole
of
the
mounted
chassis slide bracket.
Thread a no.l0 screws (with
star
washer)
to
secure
the
chassis slide to the bracket.
Do not tighten.
Align the two rear
mounted
bracket.
washers) securing

chassis

slide

Tighten

the

chassis
bracket.
Secure

- .

bracket.

Tighten

front screw
slide
assembly

the

and
rear
4 through

holes on
the
Thread
two
the
chassis

left

chassis

mounted

chassis
slide
with
no.l0
screws
(with
slide
rear
to
the

the

two

screws.

securing

the

slide

chassis

2-7

the
front
front mounted

assembly

slide

the
star
rear

brackets

the

end
of
the
chassis slide

1left

repeating

front

steps

SITE

PRERARATION

10.

AND

INSTALLATION

Extend

the

stabilizer

box

the

slide

Fully

extend

bar

(if

present)

before

placing

the

assemblies.

both

chassis

slide

assemblies

Lower

assemblies, aligning
the box rail.

the

‘\‘l

fi\\\

), =N

the
box
assembly
onto the slide
chassis slide slot with the tab on

forward:

ll1.

FIGURE

2-4

Secure

the box

clearance

13.

hole

BOX

the

INTO

chassis

with the

CHASSIS

slides

SLIDE ASSEMBLY

aligning

the

front

threaded box hole.

Thread a no.8

Slide the box rearward
aligning
the
rear
clearance
hole
with the threaded box bole.

chassis
slide
Thread a no.8

screw and

12.

SECURING

tighten.

screw

and

tighten.

Slide

the

box

the

rear and

secure

to the

rack

frame

by
threading
two,
no.8
phillips screws to the restraint
bracket located on the box rear panel.
Tighten the screws.

This

completes

standard

2.4.3

Console

Install

the

installation

19-inch rack.

Serial

Line

the console serial

the

box

1in

Hookup

line as shown
2-8

in Figure

2-5.

ANSI/EIA

INSTALLATION

PRERARATION AND

SITE

CONSOLE
TEAMINAL -

——
CONSOLE

TERMINAL

EIA
SERIAL

LINE

CABLE

2-5

FIGURE

2.4.4

Cabinet

SERIAL

Switches

Settings

switch

settings

The following

LINE HOOKUP

are

reguired

for

the

cabinet

product.
NOTE

Switch settings must be
applied

the

verified before power

Set the Forced Dialogue switch to OFF

Set

Set the Baud Rate
console terminal.

Assure

the

baud

that

rate

the

1is

system.

the

console

terminal.

switch to match
the
(see Figure 2-6.)
AC

power

(0).

outlet

baud

matches

rate

the

power

controller
AC input power requirement.
Model 877-D is
120 Vac operation and 877-F is for 240 Vac operation.
model
number
controller.

1is

printed

label

located

the

for
The
power

SITE PRERARATION AND INSTALLATION
NOTE

When the power controller is turned

off

the AC

/==$CN

Sode

683

power circuit breaker 1is inoperable.

W |__FOACED
DIALOG

SWITCH

CONNECTOR

BULK NEAG,~
(108
SCREW

’

FIGURE 2-6 CABINET REARVIEW

the

Turn the power controller breaker switch

Set the front panel keylock switch

Open

ly breaker 1is
Assure that the expansion power supp
use.

position.

See Figure 2-6.

to OFF.

off

(0)

(See

Figure

supply

circuit

2-11.)

the

front

door,

breakers to OFF (0).

turn. both

power

(See Figure 2=7.)

if the expansion backplane is in

This completes the cabinet switch set up.

OFF

(0)

SITE

PRERARATION

AND INSTALLATION

MODULE

_~" COVER

T
POWER SUPPLY

CIRCUIT BREAKER

FIGURE 2-7 CABINET FRONTVIEW
2.4.5

The

Box

Switch

Settings

following

switch

Slide

box

the

settings

forward

Remove the four top
(See Figure 2-8.)
Set
the

are

FIGURE

(See

cover

2-8

Figure

BOX

for

the mechanical
screws

the power supply input
power
supply
front,

voltage.

required

and

AC voltage
to
match

the

box

product.

stop.

lift

the

switch,
the
AC

cover

located
on
power outlet

2-8.)

POWER

SUPPLY

2-11

INPUT

SELECT

off.

SWITCH

SITE

PRERARATION AND

Reinstall

Set

the

Forced

Set

the

baud

rate

Set

the

Baud

Rate

switch

console

the

INSTALLATION

top

cover.

Dialogue

terminal.

switch

the

See

console

OFF

terminal.

match

Figure

(0).

the

baud

rate

for

2-9.

BULKHEAD ="

FIGURE

Turn the circuit breaker to OFF
the

keylock

REARVIEW

Set

completes

front panel

BOX

This

the

2-9

box switch set

switch

up.

to OFF.

(0).

See Figure 2-10.

the

SITE PRERARATION AND INSTALLATION

(= [=V])]
SREAKER

FIGURE

2.4.6

Cabinet

Complete

the

Power

BOX

2-10

FRONT VIEW

Hookup

following

procedure.
CAUTION

Assure that the wall outlet voltage
line voltage selected for operation.
Assure that all system
specified in subsection

Plug

the AC

Turn

the power controller circuit breaker

This

2.4.7

cord

completes

Complete

Power

the

power

are

the

outlet.

to ON

(1).

See

2-6.

Open the front door
breaker to ON (0).

Box

into

settings

Figure

power

switch
2.4.4.

matches

the

cabinet

and
See
AC

turn the main power
Figure 2-7.
electrical

hook

supply

up.

Hookup

following procedure.
CAUTION

matches
Assure that the wall outlet voltage
line voltage selected for operation.
2-13

the

circuit

SITE

PRERARATION

AND

INSTALLATION

Assure

that all system
specified in subsection

Plug

the

receptacle
2.

Plug

the

female

end

mounted

male

end

switch

of
the

the

settings

are

2.4.5.

the

rear
AC

power

<cord

box.

See

the

power

cord

into

the

into

the

Figure

2-9.

power

outlet.

Remove

Slide

the
the

circuit
5.

Slide

restraint
box

out

breaker

the

box

bracket

2.5

The

(l1l).

Figure

the

rack

and

electrical

hook

up.

into

the

box

CONTROLS

following

AND

The

HALT

Front

front

box.

and

turn

the

restraint

2-10.

replace

subsections

describe

the

system

controls

and

are for normal operating
normal operation refer to

Panel

panel

Switch,

indicators.
indicators.

the

INDICATORS

indicators.
The
functions
described
conditions.
If a problem occurs during
Chapter 5, System Maintenance.

2.5.1

inches

See

back

rear

completes

SYSTEM

the

approximately

bracket
This

consists

Start-up

Figure

2-11

keylock

Test

shows
-

power

LED

the

switch,

display,

front

and

panel

RESTART/RUN/

POWER

dijaliltlall

s
SECURE

PDP-11/84

STANDeY

Oocon
O

START-UP TEST

FIGURE

2-11

[F—J-reemam
NP
/

OO sammeny ||=

FRONT

PANEL

CONTROLS

2-14

AND

and

controls

INDICATORS

RUN

and

SITE

PRERARATION AND

INSTALLATION

to
wused
switch
rotary
position
four
The Keylock Switch is a
describes
and
lists
2-1
Table
states.
power
four
of
ONE
select
each of

the power switch selections.

TABLE

OFF

2-1

Power supplies are turned off. DC power to the logic
and blower/fan assembly is off. However, AC power 1into
the power

supplies

present.

ENABLE

The ON position. Power supply voltages
the logic and blower/fan assembly.

SECURE

Same as

the ENABLE position except

terminal Halt-On-Break

switch

STANDBY

KEYLOCK POSITION DESCRIPTIONS

Power
but

are

present

that the console

feature and the HALT/RUN/RESTART

disabled.

is supplied to the PMI memory,

other

are

voltages

are

turned

off.

blower/fans

The HALT/RUN/RESTART switch functions are enabled only
when
keylock
switch
1is in the ENABLED position.
Table 2-2 lists
switch positions and their functions.

TABLE

HALT

The

CPU

2-2

program

HALT/RUN/RESTART

stopped

and

the
the

SWITCH

the

incremented

of the program counter is displayed on the
terminal. The CPU enters J1ll1 Micro-ODT.

content

console

RUN

Entering RUN from RESTART enables CPU operations to run.
Entering from HALT causes the processor to remain in
micro-ODT awaiting a command from the console terminal.

RESTART

This

momentary

switch

position

initiates

processor

execution of bootstrap program instructions located
in the boot ROM according to the set up configuration
in the EEPROM. For modifying EEPROM configurations see
the

EEPROM

section

this

chapter.

SITE

PRERARATION

Three

the

LEDs

LED

are

status

AND

INSTALLATION

located

and

~ TABLE

The

the

front

panel.

Table

2-3

describes

functions.

J1l1

2-3

FRONT

PANEL

processor

instructions.

This

The

processor

INDICATORS

fetching

the

halted

and

normal

executing

condition.

waiting

for

interrupt. When the processor is in Micro-ODT
the RUN indicator blinks for each console
keystroke. The RUN LED also turns off during
extended DMA activity.
DC

power

voltages
OFF

BATTERY

1is

available

are

within

the

logic

specified

and

all

levels.

DC voltages are not available to the logic or
voltages are present but not.within tolerances.

Battery is present
capacity.

and

Battery

than

charged

80%

great-

er
Slow

Fast

(10

Blink

less

80%

capacity

and

charging.

Hz)
Blink

Hz)
OFF

The

ac power has failed:; the battery is discharging, but the memory content remains valid.

Battery is either fully discharged
sent in the system. Memory content
preserved if ac power fails.

The two-digit Start-up Test
diagnostic
error
codes.
System Maintenance.

LED

The

display

codes

are

or not prewill not be

provides

the

described

start-up

Chapter

SITE
2.5.2

The

Console

console

Serial

serial

Line

line

PRERARATION AND INSTALLATION

Distribution

distribution

Board

board

(SLU)

1is

the
1inside
back
panel
of
both
products.
The
serial communications port connector, a baud rate

and a
the

Forced Dialogue mode switch.

cabinet

and- box

are

shown

The

mounted

SLU includes a
select
switch

SLU mounting position for

Figures

2-12

and

2-9.

STCM

CONNECTOR
.

FIGURE

2.5.3

Serial

serial

2-12

CABINET

Communications

line

and

2-12

connector

2-9

show

the

BACKPANEL VIEW

Port

located
physical

the

back

location

panel.
the

provides
an
EIA
RS232-C,
RS449
compliant
communications
1link
between the CPU and console
that 20 ma applications are not supported.

2.5.4
The

Baud

baud

Rate

rate

Select

switch

Figures

connector.

It
full
duplex
terminal.
Note

Switch

enables

the

operator

set

the

baud rate between the console terminal and system.
The
is set for one of eight possible baud rates.
Table 2-4
switch positions and their corresponding baud rates.
2=-17

operating

baud rate
lists the

SITE

PRERARATION

AND

TABLE

INSTALLATION

2-4

BAUD

RATE

SWITCH

SYSTEM HARDWARE

]

SWITCH

POSITION

2.6

DESCRIPTIONS

BAUD

RATE

38400

19200

9600

4800

2400

1200

600

300

CONFIGURATION

Figure 2-13 shows the location of the modules within
the
system
backplane.
Slot MDM is dedicated to the Monitor and Distribution
module (M7677).
Slots 1 through 4 comprise
the
system
kernel.
Slots
5
through
12
support
most
UNIBUS
compatible
small
peripheral controllers (SPC).
The following subsection
describe
configuration details for the kernel.
ROWS

FIGURE
‘

(MDM) M7677

MDM

SLOTS

(KDJ11-B) MB190

(MSV11

J) MB637

(KTJ11-8) MB191

M7556

HEX OR QUAD UNIBUS OPTION

MEX OR QUAD UNIBUS OPTION

HEX OR QUAD UNIBUS OPTION

g | MODIIED

MEX OR QUAD UNIBUS OPTION

”U%?;%ESD

HEX OR QUAD UNIBUS OPTION

Muczg"i"?

MEX OR QUAD UNIBUS OPTION

VoY

2-13

QUAD UNIBUS OPTION

H9277-A

BACKPLANE
2-18

M7586
MODULE

PRIOR

’s
LOCATIONS

SITE PRERARATION AND INSTALLATION

2.6.1 KDJ11-BF Module Configuration

The KDJ11-BF module has three jumper groupings and one D;P switch
The jumpers should be installed
pack for hardware configuration.
to
The DIP switches should be- set
as shown in the Figure 2-14.
OFF.
CONNECTOR

DiP SWITCH FOR

BAUD RATE SELECT

B00OT STRAP CONTROL

FOR CABLE 10

AND TWO-DIGIT DISPLAY

CONNECTOR

FOR CABLE TO ~—_|

CONSOLE SLU

\. I

DCOK LED

BAUD RATE SELECT AND

S/8 OFF

LEDS (RED)

LSB

(G REEN)

DIAGNOSTIC

REMOTE SWITCH

I (3] ‘glfllll

" CONTROL CONNECTOR

wi0

1-A (A-SERIES)
:«snm
40—PIN SOCKET (P-SERIES)

TP1r o Jo TPIO

ROM

(M) BYTE)

15:08

€117

€53

DCJ11 CPU HYBRID

(LO BYTE) /'EEPROM

€80

Wao

ARRAY

Tra1

GATE

(SEE NOTE 2)

ARRAY

ne————————

w20

TP200{J0 TP210TP22

NOTES: 1. WHEN 24-PIN EEPROM IS USED. INSERT PIN ONE OF EPROM IN PIN 3 OF SOCKET.
2. WHEN 2K EEPROM IS USED. TP40 1S CONNECTED TO TPaY.
WHEN BK EEPROM 1S USED. TP41 IS CONNECTED TO TP42.

FIGURE

2.6.2

KTJ11-B

2-14

Module

The UBA module
configuration.

compatible
locations.
The

chip
=

KDJ11-B JUMPER AND DIP SWITCH

does
It

user

LOCATION

Configuration

not have any hardware jumpers or switches for
has
four
sockets for the addition of M9312

ROMs.

See

Figure

2-15

for

the

M9312

ROM

socket

compatible user ROMs are installed with pin one of
the
toward the left edge of the component side of the module.
MR 17 T VEE OPTION RO SOCKS TS 16)

‘

ROM

SOCRET

Bes

EW3

ADORNESS
Irems- 1
IMIXD- NN

1777300~ 17I7I%e
ITmm-ITTe

-l

T
e
-

o IS

FIGURE 2-15

{ SN

ot A

ot SR

KTJ11-B ROM SOCKET LOCATIONS
2-19

SITE

PRERARATION

2.6.3

Monitor

AND

and

The

INSTALLATION

Distribution

Configuration

quad-height
eight
switch

Monitor

Distribution

backplane

slots

DIP

The

eight

Processor

Grant

(NPG)

This

eliminates

and
pack.

Module

through

and are

line.

wired

backplane pins for non DMA SPCs.
For
turned
ON
(toward
module handles).
switch is turned OFF.
An audible alarm is
failure
of
a
box
2-17 for the switch

Module
switches

(MDM)
has
correspond

the

UNIBUS

the

wire

wrapping

non DMA SPCs the switch
For UNIBUS DMA devices

ONNTS

110 P}

jiLZ/
DS D4

:”

00O O\qumt

{20 PNy

@ AUDIBLE
ALARM

SLOY
NUMBER

NPG

66065000 |

— oe
[v114

Pack

M}e7?

NOTE
S IMAIN PN
E R SUPSL v

D2
+S5ve8 AND 12V 8LOWE
R ¢ ANS)
DI - < 1SV MAIN PU ¢t & SUPPL Y
!, POWE & S Py vy
S5V if XPANS
D4
105

15V (E XPANSI). POWE & S )PP V)

FIGURE

2.6.4

The

2-16

MDM

DIP SWITCH

MSV11-JB/JC Memory Module

LOCATION

Configuration

quad-height memory module provides:

A red

A green LED to indicate

Two switch packs for starting and CSR address selection

Four

See

Figure

LED to

indicate

factory-set

2-17

Non

1is
the

mounted on
the
module
and
sounds
when
a
fan or the cabinet blower occurs.
See Figure
location and numbering.
vOLTAGE TLSY

for

uncorrectable

errors

the presence of +5 VBB

jumpers.

LED,

switch pack,
2-20

and

jumper

layout.

SITE PRERARATION AND INSTALLATION

wa W3 03

|4 o
FIGURE

The
l -

2-17

MSV11-JB/JC

rt
LED/SWITCH

L DALY,
4

PACK/JUMPER LAYOUT

starting address is configured using switch pack S1, switches
8 Table 2-5 lists the switch settings, starting addresses and

decimal

number.

TABLE

SWITCH
l

2-5

SETTING*®*
456

MSV11-JX

STARTING

ADDRESS

STARTING

DECIMAL

ADDRESS

Kwords

Kbytes

(Octal)

000O0O0O0DO

00000000

00O0O0O0DO

04000000

000O0O0O00O

10000000

1024

11000000

14000000

1536

1
0

=
=

CSR

address

The

base

plus

512

1024
-

2048
3072

Switch on
Switch off

The

base

configured

address

Table

2-6

using

17772100.

lists

all

2-21

switch

Each

pack

S2,

successive

sixteen

possible

switches

address

CSR

the

addresses.

SITE

PRERARATION

TABLE

AND

2-6

S2
1

The

jumper

MSV11-JB/JC

SETTING
2 3 4

memory

factory-set

jumpers

17772100
17772102
17772104
17772106
17772110
17772112
17772114

1
0

17772116
17772120

1
C
1
0
1
0
1

17772122
17772124
17772126
17772130
17772132
17772134
17772136

TABLE

2-7

for
are

the

POSITION

1IMB

(MSV11-JB)

different.

specified

MSV11-JB/JC

JUMPER(S)

SELECTIONS

.
CSR
ADDRESS (OCTAL)

modules

are

CSR ADDRESS

0
1
0
1
0
1
0

configurations

(MSV11-JC)

MODULE

INSTALLATION

Table

Assure

and

2MB

that

the

2-7.

JUMPER CONFIGURATIONS

DESCRIPTION

‘wsvii-ss

R
W1

OuT

256K

Half-populated

wW3,w4

Vertical

Dynamic

Reserved

for

RAMs
module

future

use

MSV11-JC
wl

OuT

256K

ouT

Fully

wW3,wW4

Vertical

Dynamic

Rams

populated

Reserved

for

module

future

use

SITE

2.6.5
The

Minimum
MLM

loads

AND INSTALLATION

Module

modules

regulator

Load

PRERARATION

are

under

used

the

provide

following

minimum

power

supply

conditions:

An MLM is inserted in CPU backplane slot 3 (rows C and
to
ensure
a
minimum current drain of 2 A from the +5

D)
VBB

regulator.
b.

MLM

inserted

ensure

CPU

mimimum

backplane

current

drain

slot

(rows

from

and

the

-15

Vdc

regulator.
c.

expansion

Dbackplane

(DD1l1l-CK

installed,
an
backplane (rows

MLM
1is
E and F)

1inserted
to ensure

-15 Vdc

regulator.

from

the

DD11-DK)

1in
the last slot
a mimimum current

of the
drain

NOTE

MLM

not

required

(CPU
or expansion) if
the minimum 1 A of -15

When

not

required,

the

Load

the

the
V.

last

backplane

installed

Modules

options

must

two

LEDs

slot

draw

removed

from

the

indicate

the

backplane.
As

shown

Figure

2-18,

presence

and

VBB

the

-15

L
FIGURE

2-18

MLM

has

Vdc.

MINIMUM

LOAD

2-23

-8 10308

MODULE

LAYOUT

SITE

2.7

PRERARATION

EXPANSION

AND

INSTALLATION

BACKPLANE

INSTALLATION

?wo types of expansion backplanes
in the cabinet.
They are:

DDl1-CK

4-slot

backplane

DDl1l1-DK

9-slot

backplane

Both

backplanes

are

shown

are

Figure

available

for

installation

2-19.

OD11-Cx BACKPLANE
Cx AOw

]

el /X

§=&/

—g

}M..::z
oouLes

JANNNN

—i

—

NN
i

L/
’ 7// /

’

JANNNN
Yy

777 [

-~ QuAD

—,
]

FIGURE 2-19 EXPANSION BACKPLANE SLOT ASSIGNMENTS

UNIBUS
the
all
contain
connectors
The standard UNIBUS
of the
g
beginnin
the
are
1
slot
of
B
and
A
Rows
connections.
BCll-A
the
by
occupied
be
should
and
DD11-DK
and
UNIBUS DD11-CK
UNIBUS

cable.

Rows A and B of slot 9 of the DD11-DK, or of slot 4 of the
DD11-CK are the end of the UNIBUS on the backplane. These slots
should be occupied by the BCll-A UNIBUS out cable or a terminator

module

(M9302 or M9312).

SITE

2.7.1

Expansion

install

following
1.

Backplane

the

PRERARATION

AND

INSTALLATION

Installation

expansion

backplane

assembly,

pérform

the

steps.

Remove
the

the

AC power

circuit

from the power

breaker OFF

Remove the back cover using
release the door fasteners.
Lower

the

bulkhead

Remove

the

front-

left

cabinet

Remove

the

side

screws

and

two

the

align
the
four tapped

side

(plastic)

(5/32)

unscrewing

hex

the

=-viewed

bottom.

setting

wrench

from

See

unscrewing

head

screws.
the

figure

the

backplane

harness

lug

attached

mounting

screw.

are

there

modules,
jumpers

slots.

that

four

shoulder

screws.

over the backplane and the
Discard the metal insert, it is

backplane

through

the

screw holes for the
for the DD1l1-DK.

includes
must

sufficient

cabinet

2-20.

front

DD1l1-CK,

NOTE

The

cover

behind.

expansion

cover

phillips

two
tapped
screw holes

after

from the

panel

two

Remove the LEXAN
metal
1insert(s)
not reinstalled.
Position

panel

lifting up

controller

(0).

number

1install
the modules
from
backplane
pins

ground

installed

lead

with

under

the

NPG

jumper

after removing
CAl-CBl
for

NPG
all

and

the

SITE

PRERARATION

AND

FIGURE

Install the
backplane.

10.

INSTALLATION

2-20

EXPANSION

BACKPLANE

MOUNTING

two/four 8-32 screws that are
Do not tighten the screws.

supplied with

the

Install
cabinet

the backplane wiring harness
connectors
power distribution connectors.

1into

Install

two

backplane

hex

to align the

modules

Tighten

12,

Remove

13,

Replace

the

LEXAN

14.

Replace

the

side

the

8-32
hex

two phillips

each

end

slot

the

slots.

11.

the

screws

modules

head

installed
from

(plastic)
panel

using

screws.

the

step

backplane.

cover

the

four

the

backplane.

shoulder

bolts

and

SITE

15.

Replace

the

outer

side

above
the
shoulder
the shoulder bolts.

16.

Close the rear
mounting

17.

This

panel

PRERARATION

bolts.

panel

aligning

Lower

bulkhead

the

and

AND INSTALLATION

the

two

cover

brackets

tighten

the

onto

captive

screws.

the

completes

front
the

door

and

lock

installation

using
a

the

DD11-CK

hex
or

key.

DDl11-DK

optional

backplane.

2.7.2
The

NPG

and

line

BG
is

Jumper
the

transfers
without
of the NPG line is
backplane.
When

wire

NPR

from

routing

Figure

2-21.

the

DD11-DK

UNIBUS

CAl

NPG

grant

placed

for

devices

slot,

the

that

slot

through

priority

has

line

performing

data

processor intervention.
Continuity
by
wirewraps
or
Jjumpers
on
the

CBl

signal

Grant

(slot

Routing

PDP-11/84
provided

device

Lead

the

corresponding

must

from

priority

and

1is

slot

jumper

removed.

backplane

decreases

highest

be
1

The

shown

slot

has

in
9

lowest).

NOTE

The

bus

routed

NPR device

removed

jumper

wire

grant

lines

(BG4

through

each

slot

decreases

from

from CAl

row

CBl

from

must

BG7)

for

Grant

slot,

the

reconnected.

non

NPR

priority

devices

for

each

NOTE

bus

grant

row

unoccupied
open,

bus
system will

jumper

and
SPC

G727

must

slots.

grant

not

card

If an
continuity

operate.

row

installed
SPC
will

G7273

all

slot
is
left
be lost and the

are

level

SITE

PRERARATION

AND

INSTALLATION

aow
ARLE TAE URar

[

[}

’

|« N N VNN v [

]

NPG

Routing

backplanes
DIP

wire

FIGURE

2.7.3

Backplane

Power

connecting

supply.

The

Mate-N-Lok

The

power

harness

one

assignments
2-9

and

has

connector

Table

2-21

NPG

for

the

JUMPER

power

wires

run

wired

the

one

6-pin

15-pin

from

DD11-DK

are

and

2-22

one

distribution

two

15-pin

connector.

é-pin

board.

Mate-N-Lok
The

DD11-CK

connector.

The

2-22

listed

and

Table

2-8

(DD11-CK)

_\floc:a‘

‘\w>o<w:;

FIGURE

the

Figure

o o oft”

B R GRRCYSR

wire

-\N"O o of

shown

into

contains

(DD1l1-CK).

thruogh

board with the power
backplane
to
a
set
of

Mate-N-Lok

are

backplane

the

connector

locations

ROUTING

distribution

directly

from

LEADS

expansion

the

each

are
for
expansion
backplane
has NPG routing

Connections

connectors

connectors,

backplane

MDM.

harness

CPU

the

Power

supplied

wraps

only.

switch

’

3 VK

NOT N

Segn

~J°°
-

o 0 O

CEEESCTOR

BACKPLANE

the

CONNECTOR

DESIGNATIONS

signal

and

SITE PRERARATION AND INSTALLATION

2-8

TABLE

DD11-CK POWER CONNECTOR SIGNAL ASSIGNMENTS

Mate-N-Lok

+15

Connector
14
18

Spare

+15

(not

connected)

Ground

Ground
Spare

-15

Spare
Spare

(not connected)

(not connected)
(not connected)

-15

Red

18
14
14

Green

14
18

Red

White

Black
Black

Blue
Brown

Spare

B
6-Pin

Mate~-N-Lok

GND

LTC

(line

Spare

Red
Gray
Orange

Spare

B WNHHOWOJOWU
& WM

15-Pin
+5

clock)

(not connected)
(not connected)

Connector

Black

Brown

18
18

Violet

Yellow

SITE

PRERARATION

TABLE

2-9

AND

INSTALLATION

DD11-DK

15~-Pin

POWER CONNECTOR

Mate-N-Lok

SIGNAL

Connector

ASSIGNMENTS

+15

Red

2
3

+15

Gray

Spare
V

Orange
Red

Spare
Spare

(not
(not

connected)
connected)

=
=

Spare

(not

connected)

Black

14
-

Black
-

6
7
8
9

Ground
Ground

10
11

Ground
Spare (not

connected)

Red

13
14

Spare
-5V

(not

connected)

=
Brown

Spare

(not

connected)

15-Pin
|

Spare

3
4

Spare
+5 V

Spare

+15

Spare

Ground

10
11
12
13
14
15

Mate~N-Lok

Connector
14

(not

connected)

Red

Orange
Red

White

Black

Ground
Spare (not connected)
Spare (not connected)
-15 V

14
18

Black
=
=
Blue

Spare
-15 B

Green

(not

connected)
|

(not

connected)

6-Pin

1
2
3

GND

5
6

Spare
Spare

LTC (line
DC LO

Mate-N-Lok

clock)

(not
(not

connected)
connected)

Connector

Black

18
18

Brown
Violet

Yellow

SITE
2.7.4

SPC

Backplane

PRERARATION AND

INSTALLATION

Locations

The
small
peripheral
collectively
contain
voltages

hex-

(+5 V,

control
sections
(C,
D,
E
and
F)
all
the
UNIBUS
1lines
as
well as power
+15 V and -15 V).
These sections can be used
by

quad-height

peripheral devites.
the

SPC

backplane

modules

containing

Appendix D shows

the

the control logic for

designations

for

connectors.

Appendix D also shows the pin designations of
the
standard
and
modified UNIBUS connectors.
The modified UNIBUS differs from the
standard UNIBUS in that certain pins have been redesignated.

2.8

SPC

MODULE

INSTALLATION

CPU backplane slots 5 through
12
support
the
installation
of
UNIBUS
SPC
modules..
Backplane slots 5 through 11 support both
hex- and quad-height SPC modules; slot
12
supports
quad-height
SPC modules

connector.

only.

Row A

slot

supports

the

UNIBUS

out

cable

Hex-height

SPC modules occupy all
four
rows
of
the
backplane
while
gquad-height
occupy
rows
A
through
C.
Quad-height SPC
modules, when installed, occupy the same backplane
rows
as
the

system
To

CPU

and

install

l.
2.

Grasp

memory

SPC module,

the

Install
the

card

When

the

modules.

module

the

module

cage

the

handles

two

the

following

backplane

steps.

mounted

slot

sliding

the

top.
it

into

guides.

module

the
handles
upwards, away

perform

about

three

quarters

(toward
the
module
from the module (see

FIGURE

2-23 SPC MODULE
2-31

installed,

center)
and
Figure 2-23).

INSTALLATION

swing

grasp

them

SITE

PRERARATION

Continue

the
the

AND

INSTALLATION

slide

handles
backplane

the

module

downward.
and secures

into

the

backplane

This action seats the
it in the card cage.

and

press

module

into

This completes the installation procedure for an SPC module.
2.8.1

Use

Cabinet

the

SPC

following

Cable

Routing

directions

for proper

cable

routing.

After installing an SPC in the appropriate backplane
the SPC cables are plugged into the connector and the
is routed to the bulkhead assembly.

All

SPC

cables

that

plug

into

connectors

mounted

front
edge of the module, are routed toward
of the card cage as shown in Figure 2-24.
When the connector
cable
1is
routed
located above

the

slot,
cable

the

right side

is mounted on the top of the module, the
up
and
over
the cable hanger assembly
card

cage.

the
handle
module
the
near
If the connector is mounted
the front of the card
around
routed
is
cable
installed
cage.

FIGURE

2-24

CABINET SPC CABLE ROUTING
2-32

SITE

PRERARATION AND

INSTALLATION

plastic
are
cage
<card
the
Located on the right side of
cable clamps used to secure the SPC cable to the card cage.
A bar is mounted horizontally behind the card cage and used
to hang the SPC cables that are routed to the bulkhead.

2.8.2

Use
1.

Box

the

SPC

Cable

Routing

following directions

for proper cable

routing.

After installing an SPC in the appropriate
backplane
the SPC cables are plugged into the connector and the
is routed to the bulkhead assembly.
The back panel has two bulkhead assembly areas,
and top right referenced from the rear.

Cables that plug into connectors mounted on the
the module

Cables

are

that

routed

plug

toward

into connectors

(installed
1in
Dbackplane)
bulkhead.
See Figure 2-25,

FIGURE

the

2-25

BOX

are

SPC

lower

left

slot
cable

bottom left

handle

bulkhead.

mounted

the

routed

the upper right
|

CABLE

ROUTING

module

of
top

SITE

2.9

PRERARATION

CABINET

install

AND

BATTERY

the

BBU

INSTALLATION

BACK

complete

UNIT

the

INSTALLATION

following

procedure.

CAUTION

The

weight of the BBU
is
42
1lbs;
1lifting
positioning the BBU requires two people.

Unpack

the

BBU

and

Remove

the

BBU

from

the

shipping

container

surface.
panel

TOY

(Time

Year)

flat

Set

the

Figure

front

installation

and

kit.

switch

place

OFF.

See

¢the

site

1line

rear BBU AC VOLTAGE SELECT to match the f:ont
SELECT switch setting.
See Figure 2-27.

panel

2-26.

and

| M |

FIGURE

Set

the

BBU

VOLTAGE

2-26

TOY

VOLTAGE

ON/OFF

SELECT

BBU

FRONT

SELECT

switch

PANEL

match

voltage.

Set the
VOLTAGE

88U AC INPUT
CONNECTOR (J22]

FAULT INTERFACE CONNECTOR (J20)
(FAILSAFE JUMPER)

= /[58 @&
88U INPUT

GROUND STUD FOR

AC VOLTAGE SELECT

DC POWER OUTPUT

SWITCH =240

15—

[&J
USER INTERFACE
CONNECTOR (J18!

DC POWER OUTPUT

CONNECTOR (J9)

POWER CONTROLLER
BUS CONNECTOR (J19)

FIGURE

2-27

BBU

2-34

REAR

PANEL

SITE

Open

the

front

Turn

off

the

and

rear

power

cabinet

supply

breakers.

doors

and

AND

using

power

the

INSTALLATION

hex

controller

Unplug

the

Remove

the

cabinet

PRERARATION

from both

power

cord

right

sides.

See

key.
circuit

from

the

side

panel

Figure

outlet.

lifting

straight

2-28.

SHOULDER SCREW (4)
EMI SHIELD

SCREW (2)

FIGURE

10.

Removg

the

securing

11.

Carefully
screws

two

the

SIDE

PANEL

REMOVAL

phillips

head

and

panel

the

cabinet

EMI

1ift

2-28

SIDE PANEL

and

protruding

line
from

up
the

the

BBU

cabinet

four

shoulder

screws

frame.

enclosure
frame.

with

See

the

four

Figure

2-29.

SITE

PRERARATION

AND

INSTALLATION

CARD CAGE

/ASSEMBLY

U-NUT

RETAINER
W/10-32 SCREW (4)

bG-

FIGURE

BATTERY BACKUP
UNIT (H7231-E)

877-D/F
POWER

LINE
FILTER

CONTROLLER

2-29

MOUNTING

THE

BBU

12,

Position the BBU on the four mounting
against the cabinet frame.

13.

Install

and

tighten

installation

the

Remove all

15.

Install

16.

17.

18.

19.

10-32

hex

and

nuts

on the mounting screws,

slide

(from

securing

the

the BBU

frame.

14,

(J20)

kit)

four

screws

cables

the

from the

two-position

the

BBU

rear

installation

keyed

jumper

kit.

into mating connector

panel.

Plug one end of the
keyed
cable
(7020396),
wire, into the BBU mating connector (J9).
Remove

the

ground

wire

hex

tighten

the

nut on

from
hex

BBU

ground

<cable on

stud.

the stud,

ground

Place

and

the

replace and

nut.

Plug

the other end of

the

cable ground wire

into the

the

with

the keyed

cable,

with

ground

wire,

line filter bracket connector marked BB-Jl.
on

the

Install a 10-32 hex nut (from the installation kit)
stud.
Tighten the nut to secure the ground wire.
2-36

Place

stud.

the

SITE

20.

Plug

one

end

the

other

PRERARATION AND

keyed

cable

INSTALLATION

(7008288)

into

the

mating
BBU power controller bus connector (J19).
Plug the
other end of the cable into the
877-D/F
Power= Controller
connector marked either J8 or J9.
21.

Plug

the.

ten

(1700730)

the
22,

top

Attach

nut
23,

right
the

Plug

the

screws

25.

26.

ground

end

the

BBU.

stud

with

tightening
<cable

Tighten

appropriate power cord
the

other.

Check

installed

each

signal

cable

located

10-32

hex

assembly.

wire

the

connector

the

1into

the

nut.
the

mating

self-retaining

connector.

outlet

damaged

during

Reverse

steps

BOX

wire

(D-sub)

polarized

cage

the

UNSWITCHED

end

the

cable

through

the

877-D/F

cord

power

ensure

reinstallation
6

(120V or 240V)

<¢f

the

into

remaining

controller.

that
EMI

reinstall

into the BBU
the

none

will

shield.

the

EMI

shield

and

panel.

completes

the

plug

side

card

Secure

(J18)

connector

mating

the

cable

other

Plug the
and

the

provided.

connector

24,

position

into

the

BATTERY

install

the

installation

BACK

BBU

UNIT

complete

procedure.

INSTALLATION

the

following

procedure.

CAUTION

The

weight of the BBU
1is
42
positioning the unit requires

Unpack

the

BBU

and

Remove

the

BBU

from

surface.

flat

Set

the

front

installation

See

panel

1lbs;
1lifting
two people.

the

TOY

kit.

shipping

Figure

container

2-30.

switch

and

to OFF.

and

place

SITE

PRERARATION

AND

INSTALLATION

I
FIGURE

Set

the

TOY

VOLTAGE

ON/OFF

SELECT

2-30

BBU

VOLTAGE

SELECT

rear

AC VOLTAGE

FRONT

switch

PANEL

match

the

site

1line

voltage.

Set

the

front

panel

BBU

SELECT

VOLTAGE

SELECT

switch.

8BU AC INPUT
CONNECTOR (J22)

FAULT INTERFACE CONNECTOR (J20)
{FAILSAFE JUMPER)

88U INPUT

GROUND STUD FOR

AC VOLTAGE SELECT

DC POWER QUTPUT

SWITCH =240
115 =

the

{cec}
3

switch
to
match
See Figure 2-31.

USER INTERFACE
CONNECTOR (J18)

DC POWER QUTPUT

CONNECTOR (J9)
POWER CONTROLLER

BUS CONNECTOR (J19)

FIGURE 2-31 BBU REAR PANEL
‘Follow

the

directions

supplied

secure

the

BBU

rack.

Turn

the

box

the

circuit

FIGURE

2-32

breaker

CIRCUIT
2-38

with

off.

BREAKER

the

See

rack

Figure

LOCATION

and

carefully

2-32.

SITE

Unplug

the

power

Loosen

the

four

cover,

and

remove

captive
the

FIGURE

10.

Remove
two
See

the

blank

cord

the

screws

cover.

2-33

rear

phillips
head
Figure 2-34,

from

PRERARATION

TOP

outlet.

that

secure

See

Figure

2-34

panel

that

BULKHEAD

2-39

the

box

top

loosening

the

2-33.

secure

by
it

BULKNEAD
"""

FIGURE

INSTALLATION

COVER REMOVAL

bulkhead
screws

AND

LOCATION

the

bulkhead.

SITE

PRERARATION AND

INSTALLATION

from the

installation kit.

11.

Remove the BBU panel

12.

Route the two attached cables through the bulkhead

13.

1in
2-35)
1Install the BBU connector panel (shown in Figure
screws
flat-head
two
the
tighten
and
opening
bulkhead
the

that was occupied by panel Bl.

into

the

bulkhead

]

opening

frame.

FIGURE 2-35 BBU CONNECTOR PANEL

the

cables

from

the

module

slot

MDM

14.

Label and remove

15.

Remove the five modules from the backplane.

16,

Plug the signal cable connector (10 position) 1into the
backplane PC board mating connector (J12). See Figure

through slot

2-360

BACKPLANE

FIGURE

2-36

BBU

CABLES
2-40

AND

LOCATIONS

SITE

17.

INSTALLATION

Plug the other BBU cable connector (3
position)
1into
the
panel-mounted
mating
connector located behind the rear of
the

18.

PRERARATION AND

power

supply.

Reinstall the five modules insuring that
properly
.in the

backplane.

19.

Plug

into

20.

Remove

21.

Install

the

(J20)

cables

the

remaining

the

their

two

the

two

position

BBU

rear

module

from

keyed

jumper

See

BBU AC INPUT

FAULY INTERFACE CONNECTOR (J20)

(FAILSAFE JUMPER)

the

seated

installation

into

Figure

CONNECTOR (J22)

are

connectors.

cables

panel.

they

mating

kit.

connector

2-37,.

g
N

Y
88U INPUT
AC VOLTAGE SELECT

SWITCH =240

1M§—

GROUND STUD FOR

USER INTERFACE

OC POWER OUTPUT

CONNECTOR (J18)

DC POWER QUTPUT
CONNECTOR (J9)

POWER CONTROLLER
BUS CONNECTOR (J19)

FIGURE

2-37

BBU

REAR

PANEL

NOTE

BBU

connector

Jl19

not

used

with

this

system.

22,

Plug one end of the
keyed
<cable
(7020396),
wire, into the BBU mating connector (J9).

23,

Remove

the

ground

hex

wire

nut

from

the

BBU

cable

ground

the

with

stud.

stud,

and

ground

Place

the

replace

and

tighten hex nut.
24,

Plug

the

other

end

the

keyed

into
the BBU bulkhead panel
ground wire on the stud.
25,

Install
stud.

10-32

Tighten

hex
the

nut
nut

(from
to

cable,

with

connector Jl.

the

secure

ground

Place

installation
the

ground

kit)

wire.

wire,

the

cable

the

SITE PRERARATION AND INSTALLATION

.
26

27.

Plug the signal cable (1700730)
connector
located
on
the BBU
cable ground wire to
the
stud
provided, and tighten the nut.
Plug

the -other

connector
the
28.

end

the

(D-sub)

BBU.

into

with

the

Tighten

the

bulkhead

the

<cable

the

mating

polarized
the
10-32
hex
nut
.

panel.

into

Attach

the

self-retaining

mating

screws

connector.

Peplace

the

top

cover

the

box,

and

tighten

the

captive

(120V or 240V) to
the
cord into the

the
BBU
AC power

screws.

29.

Plug

the

and

plug

appropriate

the

other

power

cord

end

outlet.
This

completes

the

installation

the

BBU.

CHAPTER
FUNCTIONAL

3.1

INTRODUCTION

The

PDP-11/84

The

three

KTJ11-B

functional

modules

UNIBUS

microprocessor
Memory

line

unit),

The

KTJ1ll-B

section

and

DESCRIPTION

diagram

are:

KDJ11l-BF

adapter.

The

with

Interconnect

registers,

block

integral
(PMI)

CPU,

shown

KDJ11l-BF

FPA,

MSV11-JB/JC

arbitration

8KB

Figure
ECC

and

J1l1

module

has

cache

memory,

1logic,

memory

registers,
a SLU
a green +5V power

UNIBUS

Adapter

UNIBUS

(UBA)

section.

module
The

divided

handshake

logic

Private

management

EEPROM/ROM,
configuration
six red diagnostic LEDs and

3-1.

memory

into

(serial
LED.
a

PMI

enables

data

transfers to occur between
PMI
and
UNIBUS
devices.
The
PMI
section
has
diagnostic
registers and PMI arbitration/interface
logic.
The UNIBUS
section
has
a
32-word
DMA
cache,
UNIBUS
mapping
1logic,
sockets
for
M9312-type
user
ROMs
and UNIBUS
arbitration and interface logic.

The

MSV11-JB

has
a
in the
The

memory module has a 1IMB capacity, while the MSV11-JC
2MB capacity.
A maximum of two memory modules are allowed
system configuration.

modules

transfer

data

using

the

PMI.

the
PMI
and
UNIBUS
devices
use
the
KTJ11-B module.
PMI
read
operations,
DATBI)
can
be word or block mode.
PMI
DATO,

DATOB)

can

word

byte

Data

transfers

Handshaking

mode.

NOTE

The
-

PDP-11/84

slightly

Appendix

UNIBUS

different

for

Power

between

Logic on the
(i.e.,
DATI,DATIP,
and
write operations ( i.e.,

protocol

from most PDP-lls.
protocol description.

Refer

is
to

FUNCTIONAL

All

DESCRIPTION

communications

through

standard

configured

the

between

UNIBUS

devices

UNIBUS

protocol.

system.

MSV11-J MODULE

ROM

gSSSOLE ~ v | fiocood
4

FPJ1I

INTERFACE

DIAG

HAND

DATA | | SHAKE

{

PMI

TM1 memory

INTERFACE

PMI ARB

UBA

occur
may

KTJ11-8 MODULE

MEMORY

CACHE

A
[
———

the

devices

KDJ11-BF MODULE

and
QBus

CACHE

)

UNIBUS

ARG
AN

BNIBUS-

_
I

MISC

:xBARB

REG.S

CONSOLE

TERMINAL

INTERFACE

‘

MAéfiNG

TMO3TZ

OCTAL
DISPLAY

MR 15296

FIGURE

3.2
The

3-1

PMI

PDP-11/84

BUS

PMI

FUNCTIONAL

BLOCK

DIAGRAM

DESCRIPTION

bus

provides

high-performance

communication

between
the
KDJ1l1l-BF (CPU), MSV11-JB/JC Memory, and the
(UBA).
The PMI consists of 14 signals that
are
unique
protocol.
The signal lines are described in Table 3-1.
The

KDJ11-BF

therefore

CPU

module

1is

also

used

OQBUS

path

KTJ1l1l-B
to
PMI

systems

and

some
of
the signals retain their QBUS names, but the
functionality of these signals change when a KTJ11-B (UBA) is
1in
the system.
Data and address information is multiplexed and uses
the same data/address lines as QOBUS protocol.

FUNCTIONAL

TABLE

BDAL

3-1

PMI

multiplexed

SIGNAL

LINE

bidirectional

DESCRIPTION

DESCRIPTIONS

Data/Address

Lines.

<21-00>

During

the address phase of a data transfer cycle,
the PMI master gates address information onto these
lines.
During the data phase of the cycle the slave
(DATI) or the master (DATO) gates data onto BDALK15-00>

and
BBS7

parity

Bank

When

the

error/control

Select
PMI

(I/0

Page

master

information

onto

BDALK17-16>.

onto

BDAL<21-00>,

Select).

gates

address

it asserts BBS7 to reference the I/0 Page (including the
I/0 Page addresses reserved as non-existent memory).
When BBS7 is asserted, BDAL<12-00> specify the I/0 page
address,
BRPLY

Negation

BBS7

selects

the

memory

signal is
during the PMI

vector

DATI

Data

Input

This

signal

grant

asserted

DATO(B)

by the UBA as a
cycle and during

space.

slave

the

cycles.

Interrupt

This
grant

used

The

CPU

PMI

protocol

asserts

BDIN

during
after

UNIBUS
gating

interrupt
the

UBA latches
BDIN.

the

Acknowledge

signal is
cycles.

(from the
signals.

response
interrupt

cycle.

interrupt priority onto BDAL<K03-00>.
The
interrupt priority on the leading edge of
BIACKI

address

This

BDIN

CPU),

used by PMI protocol during UNIBUS interrupt
When the UBA receives the assertion of BIACK

asserts

one

the

UNIBUS grant

(BGn)

FUNCTIONAL

DESCRIPTION

TABLE

Power

This
to

3-1

(Cont)

signal

asserted

the

UNIBUS

and

negated

following

the

standard

UBA

UNIBUS

down

response
power-up/

protocol.
UNIBUS devices and/or PMI memory may,
during power-up, prolong the assertion of AC LO/BPOK.

The

following

PMI

master:

PBCYC

signals

are

PMI

Bus

Cycle

The

PMI

master

PMI

cycle

and

asserted

asserts
negates

(low)

this
this

and

signal
signal

negated

at
at

cycle.
PBYT

PMI

BWTBT

Write

Byte

When

the

BWTBT

PMI

master

data

gates

negates

these

transfer

will

PBYT

DATI

DATIP

DATO

DATOB

When

that

address

signals
occur

onto

Block
a

PMI

BDAL<21-00>,

indicate

during

the

what

bus

Bus Cycle Type

PMI

the

Indication

cycle:

PBLKM

start
end

and

asserts

type

the
the

(high)

DATBI

Mode
master

wishes

read

than

two

words

of data, it uses both PBCYC and PBLKM to control the
timing of the Block Mode Data In (DATBI) cycle.
It
asserts both PBCYC and PBLKM at the start of the DATBI
cycle.
It negates PBLKM after reading two data words
and then reasserts PBLKM (unless the next two words
will end the cycle).
After reading the last two words,

the

PMI

master

negates

PBCYC

(PBLKM

already

negated).

FUNCTIONAL

TABLE

PMI

Write

3-1

DESCRIPTION

(Cont)

Strobe

The PMI master asserts this signal after gating data
onto BDALK15-00>.

its write
pulse.

QSACK

The

UBA

SACK
DMR

The

UBA

NPR

from

The

QBR7-4

asserts

from

cycle
DMG

buffer

this

the

UNIBUS

its

own

asserts

granted

The

asserts

UBA

PMI

the

slave

leading

latches

edge

signal

the

PMI

signal

the

PMI

the

when

the

UBA

following

PSSEL

signals

PMI

Slave

The

PMI

whenever
NOTE:

the

data

into

PWTSTB

response

performing

to
a

DMA

behalf.
this

UBA

signal

one

when

response

these

PMI

are

asserted

mastership

and

has

been

one

DMG.

signals

of the BR7-4 lines being asserted
interrupt reguest cycles.
The

UNIBUS.

asserts

CPU

the

The

response

the

UNIBUS

negated

the

during

PMI

slave:

Selected

slave

(CPU

Memory

only)

decodes

valid

address

When

PUBMEM

respond

asserted

PMI

control

asserted by the
memory space is

asserts

the

this

signal

BDALK21-00>.

PMI

slave

signals.

does

PUBMEM

UBA to indicate that
being addressed. The

not

UNIBUS
UBA does

not assert PSSEL.
The CPU ignores the
assertion of PSSEL if PUBMEM is asserted.

PHBPAR

PMI

High

This

signal

DATBI

data
PLBPAR

PMI

cycles

(on
Low

This
DATBI

data

Byte

Parity

generated

and

provides

PMI

odd

memory

parity

during

for

the

DATI
high

and
byte

BDAL<K15-08>),
Byte

signal
cycles

(on

Data

Parity

is generated
and

provides

BDAL<KO07-00>).

by PMI memory during
even

partiy

for

the

DATI

and

low

byte

FUNCTIONAL

DESCRIPTION

PRDSTB

PMI

TABLE

Read

3-1

(Cont)

Strobe

The

PMI slave asserts and negates this line to control
data transfers during DATI and DATBI cycles.
The PMI
master latches the first word of the received data on
the negating edge of this signal.
The PMI master
latches the second data word a specified time after
this signal is negated.

PSBFUL

PMI

Slave

PMI

Buffer

slave

Full

asserts

PSBFUL

during

write

cycle,

indicating that it's Write Buffer is full, and that it
can not respond to another cycle request.
The new PMI
master may gate an address onto BDAL<21-00> while
PSBFUL is asserted, but it must not assert PBCYC until
PSBFUL

negated.

The following signals are used for communication between the
CPU and the UNIBUS adapter. PMI Memory modules do not use these
signals.
PMAPE

PMI

UNIBUS

Map

Enable

The CPU module asserts this signal
Register 3 (MMR3) bit 5 is set and

if Memory Management
negates this signal

if MMR<05> is clear.
The UBA module enables the UNIBUS
Map if PMAPE is asserted and disables the UNIBUS Map if
if PMAPE is negated.
PUBSYS

PMI

UNIBUS

This

System

signal

static signal

which

indicates whether

the system is a UNIBUS system or a QOBUS system and
asserted by the UBA.
The CPU follows PMI protocol
data
PUBMEM

PMI

transfers whether
UNIBUS

PSSEL

asserted

is
for

not.

Memory

This signal line is asserted by the UBA to indicate
that the UNIBUS memory space is being addressed.
The
UBW asserts PUBMEM during the assertion of PBCYC.
NOTE:

When

PUBMEM

asserted

the

PMI

slave

does

not

respond to PMI control signals.
PSSEL is
asserted by PMI memory when addressed. The CPU
ignores the assertion of PSSEL if PUBMEM is
asserted. The UBA does not assert PSSEL.

FUNCTIONAL DESCRIPTION
TABLE

PUBTMO

PMI UNIBUS Timeout
This

signal

the

following

PBSY

non-existent

the

UBA

When

sends
SACK

the

UBA

response

memory
an

timeout

address

timeout

out

occurs

occurs
on

the

during

cycle.

Busy

This

signal
it

PMI

BUS

when

PMI

when

any

Unibus.

When an interrupting UNIBUS device has been
granted UNIBUS mastership, but does not
execute an interrupt transaction.

the

gains

master when

asserted

conditions:

interrupt

3.2.1

3-1(Cont)

asserted
PMI

master

the

mastership

relinquishes
on

PMI master

and

(CPU or UBA)

negated

PMI mastership.

the

PMI

The CPU

1is

power-up.

Acquisition

PDPl11/84

system

the

CPU

the

default

PMI

Bus

master

and

the
UNIBUS
Adapter (UBA) is the default UNIBUS master.
This 1is
always the condition at power up.
When the UBA is not requesting
the
PMI
bus,
the CPU arbitrates to become PMI master and holds
PBUSY

asserted.

Unlike other PDPll's in the past, when none of the devices on the
UNIBUS

are

become

UNIBUS

The

CPU

requesting

use

the

master

and

holds

relinquishes

PMI

mastership

request
or
relinquished

only when

an
1interrupt
control of the

the

OQSACK

PBSY

following

has
has

been
been

BBSY

negated

the

UBA

arbitrates

for
for

when

responding

are met:

75ns
Ons

3-7

asserted.

cycle from the UBA.
Once
PMI, it
can
regain
PMI

conditions

negated

bus,

minimum.

DMA

the CPU has
mastership

FUNCTIONAL

When

the

CPU,

address

while

DESCRIPTION

PMI

the

master,

UNIBUS,

controlling

the

UNIBUS

references
a
memory
or
UBA responds as the slave

side

the

data

I/O
page
on the PMI

transfer

bus

master.

The

UBA

performs

becomes

PMI

master

when

interrupt

the

cycle.

CPU

issues

The

UBA may

DMG

(DMA

the

Grant)

DMG

interrupt grant, thus becoming both PMI and UNIBUS master at
the
same time.
Alternatively, it may pass the DMG or interrupt grant
on

reguesting

UNIBUS

device,

which

would

then

become

UNIBUS

master.

Mastership

UNIBUS

the

UNIBUS

device

can

and/or

become

PMI

bus

UNIBUS

requested

master

follows:

through

NPR

request and control data transfers over the UNIBUS.
During
these data transfers,
the UBA is PMI master and responds as
UNIBUS
slave
1if
the
UNIBUS device accesses a PMI memory
location, a PMI
I/0
page
1location
or
a
UBA
I/O
page
location.
2.

A UNIBUS

The

3.2.2

device can become UNIBUS master
through
a
BR7-4
reguest.
As
UNIBUS
master,
the device can control data
and/or interrupt vector transfers.
In both cases
the
UBA
will
respond
as
UNIBUS slave.
The device may perform an
interrupt vector cycle or access a PMI memory
1location,
a
PMI I/O page location or a UBA I/0 page location.
UBA can become both PMI and UNIBUS master at
time through DMG and interrupt requests.
As PMI
master, the UBA has direct access to the PMI.

DMA

the
same
and UNIBUS

Reqguests

A UNIBUS DMA device, through an
NPR
request
¢to
the
UBA,
perform
UNIBUS
DATI,
DATIP, DATO and DATOB cycles with the
controlling the PMI portion of the data transfer.
NOTE

Unlike

PDPll

systems,

the

CPU

does not necessarily give
unconditional
priority to DMA requests.
It can
be
programmed
(see
SETUP
mode
Chapter
4)
to
give
1itself
priority over over DMA
reqgquests
after
waiting,
for this programmed length of time, to
perform a
memory transfer or to honor an interrupt request.

can
UBA

FUNCTIONAL

DESCRIPTION

When placed in diagnostic test
mode
the
UBA
can
perform
transfers
without
a reguesting UNIBUS device.
1In this case
UBA itself is the requesting device and
when
performing
a

DMA
the
DMA

cycle

and

has

becomes

complete

master

the

PMI

control

the

PMI.-

The following PMI
when
arbitrating

and

the

UNIBUS

simultaneously
-

protocol flow is observed by the
a
Non-Processor
Request
(NPR)

CPU
and
UBA
from a UNIBUS

device:

PMI

BUS

UNIBUS

- kb Gl GED D GED GEP W D D Gl GEP D G Gl D GED D G GED GIP D G G GED GEP GED GHD b GNP W WD GES ' - ) b olh G GED U GIP G GED GD D b G b GEb GP GND auh (I N WD TGP G Gib i GNP Gl R G AN G SN

The

UNIBUS

device

asserts

NPR.

the

UBA

it negates

UNIBUS master

BBSY after

removing

address, data and control
information from the bus.

The
on

4.,

UBA asserts DMR
PMI

the

The

CPU

bus

(DMA Request)

bus.
arbitration

logic

asserts DMG (DMA Grant) on the PMI
after receiving DMR and 75ns minimum
after the negation of OSACK from a
previous PMI bus transaction.
5.

The

UBA

receives

the

assertion

DMG.

The UBA asserts NPG
Processor Grant).

The

requesting

the

highest

SACK
8.

The

Note:

UBA
The

asserts

UBA

QSACK
if
10
the
DMA

QSACK

asserts

the

PUBTMO

(indicating

SACK is not
us after it

PMI.

instead

SACK

timeout)

received within
asserts BGn on

UNIBUS. The CPU then cancels the
cycle and resumes arbitration.

and

(Non-

device

priority

negates

NPR.

with

asserts

FUNCTIONAL

DESCRIPTION

PMI

BUS

UNIBUS

The CPU arbitration logic
QSACK and negates DMG.
Because
No SACK

Note:

PMI,

the UBA provides
Timeout function

the

untill

receives

CPU

always

receives

the
on the

asserts

QSACK

DMG

UBTMO.
10.

The

UBA

negates

NPG

the

UNIBUS.

1l1.

The

UBA

asserts

PBSY,

after

receiving

the negation of PBSY from the previous
PMI

cycle,

and

becomes

PMI

master.

12.

After receiving the negation
of BBSY from the previous bus
master the UNIBUS device asserts
BBSY and negates SACK.

NPR
an
through
master
a UNIBUS DMA device becomes UNIBUS
DATOB
DATO and
DATIP,
DATI,
perform UNIBUS
can
it
request,

When

If the device accesses a PMI memory location, a PMI

cycles.
Page

location

Page

accesses,

the UBA responds as the UNIBUS slave.

portion of
Data

the

the data

UBA

transfer.

the

PMI

For PMI memory and PMI I/O
master,

controls the PMI

transfer cycles are described in section 3.2.5.
UBA negates

QSACK.

13.

The

14.

The CPU resumes arbitration 75
minimum after receiving the
negation

QSACK.
15.

The

UNIBUS

After

the PMI

slave

or the UBA has

removed all data and control information
from the bus,

the UBA negates

PBSY.

device

removes

address, data, and control
information from the bus and
negates

l6.

I/0

or a UNIBUS I/0 Page location located on the UBA,

BBUSY.

FUNCTIONAL

3.2.3
The

UNIBUS
CPU

Device

and

arbitrating

UBA

observe

inter-

]

Interrupt

rupt

DESCRIPTION

Requests
the

following

protocol

£flow

when

requests:

PMI BUS

................................... ' o

l1.

UNIBUS

The

e o e

UNIBUS

device

asserts

the appropriate interrupt
request line BR7-4.
2.

The

CPU

receives

request
3.

The

CPU

one

level

the

arbitration

the

appropriate

on QBR7-4,.
logic

four

lines,

the

level

indicate

asserts

DAL<03-00>,

the

granted

interrupt.

The CPU asserts BDIN 150 ns minimum
after gating DAL<K03-00> onto the bus.

The

The UBA latches DAL<K03-00>
asserting edge of BDIN.

The CPU receives the assertion of

CPU asserts BIAK 225
after it asserts BDIN.

IACK

Note:

The

UBA

with

the

its

this

minimum

the

PMI.

compares
own

case

the

interrupt

the

transfer cycle
and the UNIBUS
line would not

level

UBA performs

level

and

being

can

block

interrupt

granted
the

grant.

data

and has complete control of the PMI
simultaneously. In this case the BGn
be asserted on the UNIBUS.

The

UBA

UNIBUS

asserts
Grant

DAL<O3>=

the

(BGn)

BG7,

selected
line.

DAL<02>

BGS6,

etc.

the

master

UBA was

the

removes

UNIBUS

address,

data

and

control

information

from

the

bus

negates

BBSY.

and

FUNCTIONAL

DESCRIPTION

PMI

BUS

UNIBUS

.....................

..............

10.

The

highest

ing

device

assertion

priority

receives
of

BGn

request-

the

and

asserts

SACK.

1l1.

12.

The

Note:

UBA

asserts

The

device

negates

it's

BRn.

QSACK.

The

UBA

asserts

SACK

timeout)

PUBTMO

(indicating

SACK

not

received on the UNIBUS within 10 us
after it asserts BGn.
When the CPU
receives the assertion of PUBTMO it
cancels the interrupt cycle and
resumes arbitration.

13.

The

UBA

14.

After

negates

receiving

tion of BBSY
previous bus
UNIBUS
and

15,

After

the

UBA

receives

the

asserts

SACK.

negation

of PBSY from the previous PMI cycle
the UBA asserts PBSY and negates
QSACK.

16.

The

UBA

now

has

control

and may initiate a
cycle(s) and/or an

the

PMI

bus

PMI data transfer
interrupt cycle.

NOTE

nega-

from the
master the

device

negates

BGn.

The CPU resumes NPR arbitration 75 ns
after
the
negation
of
QSACK
but
does
not
resume
BR
arbitration until it has updated the PC
and
PSW
to
complete
the
interrupt cycle or has aborted
the interrupt request.

BBSY

FUNCTIONAL

PMI

BUS

UNIBUS

...........................

......

When

UNIBUS

request,
DATIP,

DATO

memory

device

_can
and

becomes

perform

DATOB

location,

DESCRIPTION

UNIBUS

master

through

Interrupt

vector

cycles

cycles.

PMI

1I/0

the

Page

device

location

an-

interrupt

UNIBUS

accesses

or a

UNIBUS

DATI,
a

PMI

1/0

Paqge

location, the UBA responds as UNIBUS slave.
For PMI
memory
and
PMI
I/O
Page
accesses, the UBA as the PMI master, controls the
PMI portion of the data transfer.
BDIN and BIACK being
asserted
does

not

effect

Data

transfer

The

following

the

data

transfer.

cycles

are

described

sequence

describes

the

section
interrupt

17.

The

3.2.5.
transfer

interrupting

cycle:

device,

bus master, gates its vector
onto the data lines and asserts
INTR.

18,

The

UBA,

BRPLY

PMI

the

master,

asserts

PMI.

19.

The

UBA

slave

receives

the assertion of INTR
latches the interrupt

and

vector.

20.
21.

The

UBA

DAL

lines.

gates

the

vector

22.

The

23.

The

CPU

negates

BDIN

24.

The

UBA

receives

the

onto

asserts

SSYN.

the

and

negates

and

BIAK.

negation

BRPLY.

25.

26.

UBA

CPU latches the interrupt
vector 200 ns minimum after
receiving BRPLY.

BIACK

The

After

receiving SSY¥YN, the
device removes it's vector
from the data lines and
negates

The

UBA

negates

PBSY.

INTR

and

BBSY.

FUNCTIONAL

DESCRIPTION

3.2.4

PMI

Data

Transfer

Address

Cycle

the

addressing phase of the PMI cycle
starts
immediately
after
CPU or UBA has gained PMI mastership and has asserted PBSY on

the

PMI.

The

PMI

bus

acquisition

phase

described

3.2.1.

MASTER

SLAVE

The address 1is gated
BDAL<21:00>, and BS7

out on
is asserted

1f the address is in the I/0 page.
The signal lines BWTBT and PBYT
are asserted to indicate
cycle to be performed:

BWTBT

PBYT

the

Bus Cycle Type

DATI

DATIP

DATO

DATOB

DATB

When

valid

address

decoded by a slave,
sponds as follows:

The UBA
address
UNIBUS

PMI

How

the

I/0

page.

memory

and

asserted.
cycle

proceeds

dependent

on whether the CPU or UBA is master,
and what the response was from the
slave as follows:
a.

When the CPU is PMI master:
If PSSEL is asserted and PUBMEM

negated,
memory
If

the

CPU proceeds

with

PMI

cycle.
negated,

the

CPU

a PMI cycle with the
as the PMI slave.

PSSEL

UBA

responding

When the
If PSSEL
the

PMI

UNIBUS

UBA is PMI master:,
is negated, then the
cycle

slave.

and

does

not

performs

UBA

respond

aborts

re-

asserts PUBMEM if
is UNIBUS memory,

PSSEL.

PBCYC

1is

the

CPU

the
or
.

assert

FUNCTIONAL

3.2.5

PMI

Data

Transfer

DESCRIPTION

Protocol

Following the data transfer
address
«cycle,
the
data
transfer
cycle
begins.
The
transfer
of data on the PMI can be grouped
into 3 general types of PMI data transfer cycles:
|
1.
B

The

Data

(DATI)

are

used

read

and Data

one

The Block Data In
to sixteen words.

The Data Out (DATO)
and
cycles are used to write

The

following

(DATBI)

subsections

Pause

(DATIP)

cycles.

These

two words.

cycle.

This

used

Data
Out
Byte
single word or

describe

each

(DATI)

(DATIP)

read

(DATOB).
byte.

the

data

These

transfer

cycles.

3.2.6

PMI

Data

Cycles

and

When

accessing the PMI memory address space, a
PMI
master
the
DATI(P) cycle to read either one or two words of data.
accessing either I/0 page or UNIBUS memory, a
PMI
master
single words only.

The PMI
PBYT is

DATIP cycle is identical to the DATI
asserted with the address to indicate

(immediately

following

cycle

same

The

the

following

current

cycle)

cycle
except
that the next

will

that
cycle

data

out

address.
a

PMI

PBCYC

the

uses
When
reads

description

DATI(P)

data

MASTER

transfer

PMI

cycle:

SLAVE

is asserted during the address-

ing phase of the cycle
subsection 3.2.4).

(described

in
1.

Data

from

address

the

specified

gated

onto

the

bus.

2.,

the

PHBPAR

slave
and

generated

the

PMI

PLBPAR

and

memory,

are

gated

onto

bus.

Note: These parity bits are

FUNCTIONAL

DESCRIPTION

PMI

MASTER

PMI

SLAVE

___________________________________ I-------------f----_----—_-

generated only for memory
locations which are cached
on the CPU (i.e. PMI memory).

The

first

data

word,

with

PRDSTB

asserted.

PRDSTB

negated.

PHBPAR

and PLBAR, are latched on the
negating edge of PRDSTB. If only

one word 1is to be read, PBCYC
is negated and the cycle ends. If
two words are to be read, PBCYC
remains asserted. If a read-modifywrite (DATIP) is being performed a
DATO

The

cycle

will

take

DATO(B) cycle
section 3.2.8.

place

here.

described

The

second

data

word

gated onto the bus 80 ns
maximum after the negation
of
7.

PRDSTB.

PHBPAR

ated
word

bus
of

and

for
and

100

PLBPAR

are

gener-

the second data
are gated onto the

after

the

negation

PRDSTB.

The second data word, along with
PHBPAR and PLBAR, are received
145 ns maximum after the negating
edge of PRDSTB. PBCYC is negated
and the cycle ends. If a read-modifywrite (DATIP) is being performed,
PBCYC remains asserted, and a DATO

cycle
cycle

is performed here. The DATO(B)
is described in section 4.2.9.
9.

Data

removed

from

bus after receiving
negation of PBCYC,.

3-16

the

FUNCTIONAL

3.2.7

PMI

Block

Mode

Data

DESCRIPTION

In Cycles

When accessing the PMI memory address space a PMI master uses the
PMI
Block Mode Data In (DATBI) cycle to read up to sixteen words
of data.
A
PMI
master
does -not
use
the
DATBI
cycle
when
accessing either the I1/0 page or UNIBUS memory.
The

PMI

master

can

start

DATBI

data

transfers

even

word

boundaries only and does not cross sixteen word boundaries.
This
means that at the transfer start, address bits
01
and
00
must
both
equal
2zero
and
the
master
terminates the transfer when
address
The

bits

following

04-01

are

flow

o e

egqual

describes

PMI
— e

all

to one.

the

DATBI

cycle.

MASTER

PMI
o

SLAVE

B ke

PBCYC is asserted during the addressing
phase of the cycle.
The addressing phase
is described in section 3.2.4.
l.

PBLKM

asserted.
2.

Data

from the specified
address is gated onto the

bus.

the

PHBPAR

and
Note:

slave

gated

These

parity

The

first

data

and PLBAR, is
negating edge
)

word,

with

latched on
of PRDSTB.

the

bus.

bits

are

only for memory
which are cached

CPU

(i.e.

PMI

PRDSTB

asserted.

PRDSTB

negated

memory,

generated

data
bus.
6.

the

PMI

are

onto

generated
locations

PLBPAR

removed

and

memory).

the

from

the

word

PHBPAR
the

The

second

data

gated

onto the bus 80 ns maximum
after the negation of PRDSTB.

FUNCTIONAL

DESCRIPTION

PMI

MASTER

PMI

SLAVE

.................................... Jerr————ece——ccc——————————————

PHBPAR

after

The

second

and

PLBPAR

are

generated

for the second word and gated
onto the bus 100 ns maximum

data word,

with

the

negation

PRDSTB.

PHBPAR

and PLBPAR, is received 145 ns
maximum after the negating edge
of

10.

PRDSTB.

PBLKM

second

negated

data

after

latching

the

word.
ll.

The secend data word
removed from the bus

receiving

the

is
after
negation of

PBLKM.

12.

Data

transfer cycles

in the same manner as

continue

steps

thru 11 above until two words
are left to be transferred.
The

last

two

words

are

trans-

ferred with the same timing,
but the signal PBLKM is not
asserted

the

master.

13. PBCYC is negated after latching
the

last data word.

14.

Data is removed from the
bus after recieving the
negation of PBCXC.

3.2.8 PMI Data Out Cycles

The PMI master uses the PMI Data Out (DATO or

transfer a single word or byte to a PMI slave.
The

following flow describes a DATO(B)

cycle:

DATOB)

cycles

FUNCTIONAL

PMI

PBCYC

PMI

MASTER

asserted during

the

DESCRIPTION

SLAVE

addressing

The addressing phase
phase of the cycle.
is described in section 4.2.5.
l.

PBCYC

gated

onto

asserted

PWTSTB

the

and data

bus.

asserted.

The assertion
received and
latched

PWTSTB

PBCYC

3.3

MEMORY

is
is

of PWTSTB 1is
the data 1is

in.

PSBUFL

asserted.

PSBUFL

negated.

negated.
negated.

MANAGEMENT

Memory management is used to relocate a 1l6é-bit
wvirtual
address,
if
necessary,
and transmit the 22-bit physical address to cache
memory, or PMI memory.
Address modification is the PMI
function
of
memory
management.
The modification of addresses 1s called
relocation because it consists of adding a fixed
constant
¢to
a
virtual

address

create

a physical

address.

Memory management also allows the user to protect one section
of
memory
from
access
by
programs
located
1in
another section.
Memory management divides memory into individual sections
called
pages.

Each page has a protection or access key associated with it
that
defines the type of access allowed on that particular page.
With
the memory management unit,
a
page
can
be
keyed
nonresident
(memory
neither
readable
nor writable), no write operations to
memory,
or
read/write.
These
two
types
of
protection,
1in
association
with
other
features,
enable the user to develop a
secure operating system.

It is often desirable to load a program into one area of phySical

memory
memory,

and
execute
it
for
example,

when

3-19

were located in
several
user

another area of
programs
are

FUNCTIONAL

DESCRIPTION

simultaneously

running,

stored

must

located
1in the set
called relocation.
When

the

processor

1in

memory.

accessed

addresses

accesses

When

the

beginning

virtual

any

processor

bus

one

program

address

This

were

process

base

address

is
added
to . it
and the relocated 0 location of the program is
accessed.
Typically this base address is added to all references
while
the
program is running.
A different base address is used
for

each

Memory

other

accommodate

memory

programs

specifies

memory.

relocation

large
program
to be loaded
This capability eliminates the

fragments,

the

management

allows
memory.
to

thus

new

allowing

one.

also

users

into
need

page

minimizes

basis,

nonadjacent
to shuffle

loaded

which

pages in
programs

unusable

into

memory

specific

size.

program

memory.

and

The

its

data

size

can-occupy

each

page

many

may

vary

and

can

pages

any

1in

the

multiple

of 32 words up to 4096 words
1in
1length.
This
feature
allows
small
areas
of
memory to be protected (stacks, buffers, etc.),
and also allows the last page of program, exceeding 4K words,
to
be
of
adequate
length to protect and relocate the remainder of
the program.
As

result,

the

memory

fragmentation

fixed-length
pages is eliminated.
can be any multiple of 32 words in
thus
ensuring
efficient
wuse
of
length also allows the pages to be
time.
Memory

inherent

with

management

in
the
sets of

user

problem

The base address of each page
the
physical
address
space,
PMI memory.
The variable page
.
dynamically
changed
at
run

provides three separate sets of pages
for
use
processor's
kernel,
supervisor, and user modes.
These
pages increase system protection by physically
1isolating

programs

from

service

supervisor

programs

and

the

kernel

program.

The

service

Separate

programs
relocation

are

also

separated

sets

from

the

kernel
reduce

program.

time
necessary to switch context between mapping.
The three
sets
of
registers also aid the user in designing an operating system that
has clearly defined
communications,
1is
modular,
and
is
more
easily debugged and maintained.
The

greatly

the

virtual bus address space is further divided, within each
of
the
kernel,
supervisor,
and user pages, into instruction space
and data space (I and D space).
I space contains code, that
1is,
any
word that is part of the program such as instructions, index
words and immediate operands.
D space contains information
that

3-20

FUNCTIONAL

can

modified,

using

this

such

feature,

data

memory

buffers.
management

can

instruction
references
with
separate
Therefore it is possible to have a
user
consisting of 32K of instructions and 32K
The

memory

Registers
Memory

The

Page

on
the
each of

Page

Field

registers

(PARs),

Management

located
describe

3.3.1

management

Address

(PAF).

(See

figure

affected
at

Registers

PAR

All

power

data

and

These

The

©Page

Address

(PDRs),

and

registers

following

four
are

subsections

Registers

The

3-2.)

Registers

(MMRO-3).

KDJ1l-BF
module.
the registers.

relocate

base
address
values.
program
of
64K
words
of data.
-

consists

Descriptor

Registers

Address

not
state

DESCRIPTION

bits-are

console
1is

(PARs)

contain

specifies

the

base

read/write.

start

16-bit

Page

address

These

RESET

Address

the

reqgisters

instruction.

page.

are
Their

UNDEFINED.

PAR

FIGURE

3.3.2

Page

The

Page

page

3-2

Descriptor

PAGE ADDRESS

Registers

expansion,

page

(PDRs)

length,

contain

and

information

relative

These
registers
are
not
affected
by
console
start
or
a
RESET
instruction.
Their
state at power up is UNDEFINED.
All unused
bits read as zero and cannot be written.
The register format
1is
show in Figure 3-3; bit descriptions are provided in Table 3-2.

BYPASS
CACHE
FIGURE

PAGE
WRITTEN

LENGTH
PAGE"
FIELD

3-3

PAGE

DESCRIPTOR

3-21

access

control.

Accssa Ecg)maon.

EXPANSION
DIRECTION

FORMAT

FUNCTIONAL

DESCRIPTION

TABLE

Bypass

3-2

Cache

(R/W)

PAGE

DESCRIPTOR

This

bit

implements

BIT

DESCRIPTIONS

conditional

cache

bypass mechanism. If set, references to the
selected virtual page will bypass the cache.
cache

bypass

invalidated
14:8

Page

Length

Field

(R/W)

This

field

causes

the

whenever

specifies

cache

read

the

location

or write

block

defines the boundary of the
block number of the virtual

numbe

current
address

hit

occurs.

which

page.
is

The

compared against the Page Length Field to
detect length errors. An error occurs when
expanding upwards if the block number
is greater than the Page Length
Field, and

Page

Written

(RO)

when

expanding

less

than

the

down

Page

block

number

Field.

this

which

direction

the

page

This

PDR

expands.
If ED=0 the page expands upwards from
block number 0 to include blocks with higher
addresses; if ED=1, the page expands downwards
from block number 127 to include blocks with
lower addresses. Upward expansion is usually
used for program space while downward
expansion is used for stack space.

Control

specifies

the

Expansion

Access

bit

to 0 whenever either
PAR 1is written into.

Direction

(R/W)

2:1

the

This
bit
indicates
whether
or not this page
has been modified (i.e. written into) since
either the PAR or PDR was loaded (1 is
affirmative). It is useful in applications
which involve disk swapping and memory
overlays.
It is used to determine
which pages
have been modified and hence must be saved in
their new and which pages have not been
modified and can simply be overlaid.
This bit is reset
or the associated

Length

field contains the acces rights to
particular pacge. The access codes or

"keys" specify the manner in which a page may
be accessed and whether or not a given access

FUNCTIONAL

TABLE

should

result

operation.

3.3.3

Memory

Management

3-2

abort

access

Non-resident

Read

Not

Read/write

a console start, and
the
register
format;
descriptions.

only
used

number
flags.

shows

the

codes
-

abort

abort
abort

current

are:

on
all

all

accesses

writes

accesses

(MMRO),

contains
error flags, the page
abort, and various other status
up,

(Cont)

The

DESCRIPTION

RESET

Table

address

whose
MMRO

instruction.

3-3

777

Figure

3-4

the

bit

contains
B

ABORT: READ ONLY
ABORT: PAGE LENGTH

ABORT: NON-RESIDENT
PROCESSOR MODE
PAGE SPACE
PAGE NUMBER

ENABLE RELOCATION

FIGURE

3-4

MEMORY

MANAGEMENT

572,

reference caused the
is cleared at
power

FORMAT

FUNCTIONAL

DESCRIPTION

TABLE

BIT

15
-~

3-3

MEMORY

NAME

Abort -

Bit

Non

Resident

Page

Length

(R/W)

page

key

Abort

BIT

DESCRIPTIONS

FUNCTION

(R/WO

MANAGEMENT

set by

with

equal

attempting

tion

with

This

bit

location

number

attempting

Control

set

with

address

set

reloca-

attempting

page

(virtual

Field

also

(PS<15:14>)
by

use memory

mode

to access

Access

access

block

bits

<12:6>)

that is outside the area authorized
by the Page Length Field of the Page
Descriptor Reqaister for that page.

Abort

This

bit

set

Read

Only

write

"Read

Onlv"

page.

Only"

pages

have

access

keys

(R/W)

NOTE:

Bits

<15:13>

can

set

however such an action does not
Whether set explicitly or by an

attempting

to
"Read-

explicit write;

cause an abort.
abort, bits <15:13>

cause memory management to freeze the contents of
MMRO <6:1>, MMR1l, and MMR2.
The status registers
remain frozen until MMRO <15:13> are cleared by an
explict write or any initialization sequence.

6:5

Processor
Mode (RO)

Page

Space

(RO)

These

bits indicate the processor mode
(kernel/supervisor/user/illegal) associated with the page causing the abort
(kernel = 00, supervisor = 01, user =
11, illegal = 10).
If the illegal mode
is specified, an abort is generated and
bit <15> is set.
This
D)

abort
3:1

Page
(RO)

Number

Enable
Relocation
(R/W)

bit

indicates

associated

the

address

with

the

page

space,

These three bits
the page causing

space

causing

the

= D space).

contain the
the abort.

page

number

This bit allows address relocation.
When
set to 1, all addresses are relocated.
When bit 0 is set to 0, memory management is inoperative
not relocated.

and

addresses

are

FUNCTIONAL DESCRIPTION

3.3.4

Memory Management Register

Memory Management Register 1 (MMR1l) at address
17777574
records
any auto increment or decrement of the general purpose.registers.

This register supplies necessary information
needed
from a memory management abort.
MMR1l is read only.

power up

UNDEFINED.

Figure

3-5

shows

the

to
recover
Its state at
register format.

VIRTUALVADDRESS
FIGURE
3.3.5
Memory

Memory

3-5

MEMORY.

Management

loaded
with
the
instruction fetch.

virtual
MMR2 is

UNDEFINED.

3-6

Figure

(MMR2),

the

FORMAT

2
at

address
at
read only.

shows

address

—

(2°'S COMPLEMENT)

NUMBER

12'S COMPLEMENT)

NUMBER

Memory

Management

MANAGEMENT

1is

AMOUNT CHANGED

MEMORY

576,

format.

3-6

777

the
beginning
of
each
1Its state at power up
1is

AMOUNT CHANGED

FIGURE

3.3.6

MANAGEMENT

FORMAT

Memory Management Register 3
(MMR3),
at
address
17
772
516,
enables or disables D space, 22-bit mapping, the CSM instruction,
and the I/O map (when applicable).
MMR3 is cleared at power
up,
by a console start, and by a RESET instruction.
Figure 3-7 shows
the register format; Table 3-4 provides the bit descriptions.

FUNCTIONAL

DESCRIPTION

ENABLE UNIBUS MAP
ENABLE 22-BIT MAPPING
ENABLE CSM INSTRUCTION

ENABLE KERNEL DATA SPACE
ENABLE SUPERVISOR DATA SPACE

ENABLE USER DATA SPACE

FIGURE

TABLE

3-4

-—===-

Enable

Map

MANAGEMENT

BIT

FORMAT

DESCRIPTIONS

FUNCTION
Unused.

UNIBUS

This

(R/W)

Enable

bit

UNIBUS

22-bit

This

enables

bit,

when

addressing.

(R/W)

addressing

addressing
MMRO bit 0

CSM

This

Instruction

the

I/0

Map

for

the

Adapter.

Mapping

Enable

MANAGEMENT

NAME

15:06

MEMORY

BIT(S)

3-7

bit

set,

When

is
is

this

bit

selected.
actually
set).

enables

Supervisor

selects

Mode

22-bit

(18

clear,

18-bit

22-bit

enabled

recognition

memory

only

when

the

Call

instruction.

(R/W)

2:0

Enable Data
Space

These three bits ehable Data

(R/W)

Space

and

3.3.7
If

Physical

UNIBUS

map

Address

mapping

user mode,

for

kernel,

supervisor,

respectively.

Construction

relocation

enabled

(MMR3

bit

1),

UNIBUS

address
bits
<K17:13>
select
one
of 31 mapping register pairs
(corresponding to octal codes 00 thru 36).
The
content
of
the
selected
mapping
register
pair
1is
added
to
UNIBUS
address
bits<12:00> to produce the memory
address.
If
UNIBUS
address

FUNCTIONAL

DESCRIPTION

bits
<17:13>
are
all
ones
(octal
code
37), the I/O Page is
selected.
Memory address bits <21:18> are set equal
all
zeros,
memory
address bits <17:00> are identical to UNIBUS address bits
<17:00>,

and

BBS7

asserted.

See

UNIBUS ADDRESS l

Figure

3-8.

ADDRESS BITS 17-13

SELECT ONE OF D1
MAPPING REGISTER PAIRS

THROUGH

36
(OCTAL)

ADDER

B
FIGURE

3.3.8
When

Memory
memory

address
(PA) but

3-8

PHYSICAL ADDRESS

1]
00

INTERPRETATION

Relocation

management

is enabled, the normal 16-bit
direct-byte
no
longer
interpreted as a direct physical address
a virtual bus address (VBA) containing information to

1is
as

wused
1in
constructing
a
new
22-bit
PA.
The information
contained in the VBA
is
combined
with
relocation
information
contained in the page address register (PAR) to make a 22-bit PA.
Using memory management, memory can be dynamically
allocated
in
pages composed of from 1 to 128 blocks of 32 words each.
The

starting

page

has

anywhere

for

within

create

the

the CPU
3-10).

(i.e.,

3.4

KDJ11-BF

The

CPU

has

concurrent

instructions

each

maximum

the

page

size

space.

determined

kernel,

multiple

4096

The
by

set

the

supervisor,

words.

words,

Pages

may

and

each

located

PARs

current

mode

operation

user modes

;

ref

used

to
of

subsection

CACHE
dual

tag

DMA

and

cache

memories.

activity,

data.

The

and

8KB

cache

3=-27

They

decrease

are

used

system

located

access

the

allow
time

KDJ1ll-B

FUNCTIONAL

DESCRIPTION

module.

Cache

operations

UNIBUS

memory

not

Figure

3-9

matrix

CPU

data

transfers

activity

only

showing

from

the

and

cache

the

referenced

activity.

The

involving

the

CPU

MEMORY

CPU

READ

MEMORY

WRITE BOTH

MEMORY

Parity

READ MEMORY

CACME AND

~NO CACHE

READ MEMORY

CHANGE

WRITE MEMORY |

iS
ThO =2°

AEAD

READ MEMORY | READ MEMORY

MEMORY

-NO CACME

WRITE

WRITE
MEMORY-

WRITE

WSS

CACHE

Errors

affect

During

~NO CACHE

CHANGE

WRITE
MEMORY

MEMORY

WRITE
MEMORY

~NO CACME

CHANGE

CACHE

the

CHANGE

RESPONSE

Cache

MATRIX

Response

Matrix

DMA Write
Hit

Cycles,

response,

and

a
the

DMA

Tag

cache

Parity
location

Error
is

During CPU Read Cycles (Non-Bypass),
a
CPU
Parity Error forces a Cache Miss response.

During
a

CPU

data

the

WRITE

CACHE AND

ways:

Cache

INVALIDATE

N/A

3-9

CRANGE

READ

FIGURE

MEMORY

N/A

INVALIDATE

refers

WRITE

READ

FORCE

heading

oNO CACHE

FORCE

MISS

MEMORY

CACHE AND

BYPASS

following

WRITE BOT
CACHE AND

WRITE

CACME-WRITE | . MEMORY

N/A

DMA

CACHE

MEMORY

Cache

AND ALLOCATE

INVALIDATE

BYPASS

both

MISS

DATA

WRITE

N/A

for

space.
There are
The
DMA
matrix

READ CACHED | READ MEMORY

WRITE BOTH
CACHE AND

WRITE

cycles,

CPu

WRITE
MEMORY

MEMORY

matrix

HIT

INVALIDATE
CACHE-WRITE

READ

memory

tag.

MISS

READ

memory

the matrix.

WRITE
WORD

8YTE

PMI

response

PMI

DMA
MIT

READ

for

cached.

two cache memory tags
heading refers to DMA
PMI

occur

CPU Write Byte Cycles (Non-Bypass;
Parity Error forces a Cache Hit

Tag

loaded

with

bad

parity.

forces

invalidated.

Tag

Non-Force
response,

Data

Miss),
but the

FUNCTIONAL

During

CPU

Read

Bypass

Write

Data
Parity
Error forces
location 1is invalidated.

For all Force Miss Cycles,
(Non-Bypass)

3.4.1

KDJ11-BF

Cycle,

Cache

Bypass

Cache

DESCRIPTION

Cycles,

Hit

CPU

Response.

and

for

the

Parity

ignored.

CPU

Tag

The

cache

Write

Word

Operations

The KDJ11-BF
cache
KDJ11-BF
addresses

1is
PMI

1initially
flushed
memory
locations,

(emptied).
As
the
the
KDJ1l1l-BF cache

begins
to
fill
with
addresses
and
data.
If
the
KDJ1l-BF
addresses
PMI
memory within an 8K memory space the cache fills,
as the addresses are accessed, to the 8K limit of the cache size.
This means that for each cache address location the data for that
address 1is a duplicate of the corresponding PMI address's data.
As each instruction
compared
1in
cache
occurs

the

PMI

is accessed by the KDJ11-BF it's
to see if there are any matches.

memory

cycle

aborted

and

the

data

address
is
1If a match

stored

the

cache
address
1is
wused by the KDJ11-BF.
If a cache miss occurs
the PMI memory cycle is completed.
In addition to
filling
1it's
memory
space
the
cache
monitors the PMI address lines for DMA
writes to PMI memory addresses.
If a write
1into
a
PMI
memory
address
matches a cache address that particular cache address is
invalidated.
The

following

cache

options

are

available

the

KDJ11-BF:

Conditional cache bypass - selected virtual
made
to
bypass the cache.
Bit <15> in the

pages
can
be
PDRs sets this

condition.
2.

3.
4,

Unconditional

cache

bypass

all

CPU

references

to bypass

the

cache.

Bit

<9>

the

Cache

sets

condition.

this

Flush

cache

Lock

1instruction

instructions

3.4.2

The

KDJ11-BF

all

Valid

(ASRB,

guarantee

Cache

bits

the

TSTSET,

cache

cache
and

bypass

KDJ11-BF contains an 8K byte direct map
which allows concurrent operations of

Cache

Memory
Store,

can
CPU

be
TAG

are

made

cleared.

WRTCLK)

these

reference.

Organization

Store
Data

can

Control

subdivided
Store

and

the

1into
DMA

three
TAG

cache with
the CPU and
distinct

Store.

dual
DMA.

TAG
The

sections:

FUNCTIONAL

DESCRIPTION

The

KDJ11-BF

shown

Cache

1in

interprets

Figure

the

3-10

and

CPU

(or

Table

DMA)

3-5

physical

contains

address

the

bit

description.

CACHE INDEX

CACHE TAG

BYTE
SELECTION

FIGURE

3-10

CPU/DMA

PHYSICAL

ADDRESS

TABLE

CPU/DMA

21:13

PHYSICAL ADDRESS

Cache

Tag

(R/W)

INTERPRETATION

3-5

INTERPRETATION

BIT

DESCRIPTIONS

During CPU read/write operations,
these bits are compared with bits 21:13

of the CPU Cache Tag Register (Figure 3-11)
to determine the cache hit/miss status.
2.

During

DMA

read/write

operations,

these bits are compared with bits 21:13
of the DMA Tag Register (Figure 3-12) to
determine the cache hit/miss status.
For either CPU or DMA operations a tag
hit occurs when the cache tag contents
matches the CPU/DMA tag register and the
CPU/DMA valid bit is set.
12:01

Cache

Index

(R/W)
00

The

The CPU cache interprets the CPU/DMA
physical address directly and selects
one of 4096 word cache memory locations.

Byte

During

Selection

this bit selects writing into
cache memory location (Figure

High Byte

Parity

bit

CPU/DMA

write

reflects

<15:08>.
3-30

odd

operatons

parity

setting

the high byte
3-13).

data

bits

FUNCTIONAL

The

Low

Byte

Parity

bit

reflects

even

parity

DESCRIPTION

data

bits

CPU _.Tag

bits

<07:00>.

The CPU Tag Parity bit

reflects

odd

parity

<21:13>.

The DMA Tag Pafity bit

reflects

<21:13>.

The

CPU

and

DMA

Tag

parity

DMA

Tag

Valid

bits

odd

are

not

parity

included

DMA

Tag

bits

the

CPU

and

calculations.

CPU TAG

CPU TAG
PARITY (ODD)

CPU TAG
valmn

FIGURE

3-11

CPU

CACHE TAG

12
0

FORMAT

DMA TAG
DMA TAG
PARITY (ODD)

DMA TAG VALID

FIGURE

3-12

DMA TAG

olo]J]ojo|ojo]o]o|o}o

FUNCTIONAL

DESCRIPTION

]

HIGK BYTE

LOW BYTE

DATA

HMIGH BYTE
PARITY (ODD)

Cache

DATA

)

LOW BYTE
PARITY (EVEN)

FIGURE

3.4.3

Control

CPU

3-13

CACHE

DATA ORGANIZATION

The Cache Control Register (CCR), at address 17 777 746, controls
the
operation
of
the
cache.
Two copies of the cache control
register are kept on the KDJ11-BF.
One copy is kept in the
chip

The chip copy implements bits <10:0>
set;the other on the board.
as read/write but interprets only bits <9 and 3:2>.
This copy 1is
used

the source of data when the register is read.

copy implements bits <10,8,7,6,0>.

This is

‘a

The board

write-only

copy.

It
can
not
be
explicitly
accessed.
Figure
3-14
shows
register format; Table 3-6 contains the bit descriptions.

WRITE WRONG

TAG PARITY

UNCONDITIONAL

CACHE BYPASS
FLUSH CACHE

ENABLE PARITY
ERROR ABORT
WRITE WRONG
DATA PARITY

UNINTERPRETED
FORCE CACMHE MISS
DIAGNOSTIC MODE
DISABLE CACHE
PARITY INTERRUPT

FIGURE

3-14

CACHE

CONTROL

FORMAT

the

FUNCTIONAL

TABLE

15:11

Unused

Write
Tag

3-6

CACHE

Always

read

cleared

DESCRIPTIONS

bits.

Wrong

Parity

(R/W)

CONTROL

DESCRIPTION

When

this

Tag

Parity

bit

bits

set,
are

the

both

CPU

and

DMA

written

as wrong parity during all operations
which update these bits. A cache tag parity
error will thus occur on the next access
to that location.

Unconditional

When

cache
(R/W)

memory

bypass

this
by

bit

the

CPU

and go directly
write hits will

set,

all

will

references

bypass

the

to main memory. Read or
result in the invalidation

of the corresponding cache location;
will not affect the cache contents.
08

Flush

Cache

(WO)

Writing

CPU

and

Tag

"1"

the entire
a "0" into
Cache

into

DMA

this

Tag

reads

bit

Valid

contents
this bit

always

cache

clears

bits

misses

all

invalidating

of the cache. Writing
has no effect. Flush
as

zero.

The

KDJ1l1l-BF

requires approximately 1 msec to flush
the cache. During the period, DMA activity
is possible and CPU activity is suspended.
07

Parity

This

bit

Abort

When

(R/W)

a CPU cache
the current
vector 114.

Error

set

set,

for

diagnostic

cache

parity

purposes

error

only.

(during

read) will cause the CPU to abort
instruction and trap to parity error
When this bit is clear, a cache

parity error (during a CPU cache read) results
in a force miss and data fetch from main memory.
The

CPU

will

trap

114

only

CCR

bit

<0>

clear. DMA cycle cache parity errors will
cause a trap to 114 if CCR <7> is set or if
CCR <0> is clear. CCR <7> has no effect on
main memory parity errors which always cause
the CPU to abort the current instruction
and trap to 114.
06

Write

Wrong

When

this

Data

Parity

data

parity

(R/W)

during

bit

all

This

will

occur

bits

set,

both

are

written

with

which

update

operations
cause

the

high

and

wrong

these

low
parity

bits.

cache data parity error to
access to that location.

FUNCTIONAL

TABLE

3-6

DESCRIPTION

(Cont)

BIT(S)

NAME

03:02

Force

FUNCTION

When

either

(R/W)

Miss

will

these

Diagnostic
Mode (R/W)

When this bit is set, a 10 usec nonexistant
memory timeout during a word write will not
cause a nonexistant memory trap and will not
set CPU Error Register bit 05. All non-bypass
and non-forced miss word writes will allocate
the cache irregardless of the nonexistant
memory timeout.

Disable Cache
Parity
Interrupt
(R/W)

This bit controls Cache Parity Interrupts when
CCR <7> is clear (normal operation). If CCR <7>
is clear, a cache parity error (during a CPU
cache read) results in a force miss and data
fetch from main memory. The CPU will trap to
114 only if CCR bit <0> is clear. DMA cycle

reported

bits

cache

set,

CPU

reads

misses.

cache parity errors will cause a trap to 1l1l4
if CCR <7> is set or if CCR <0> is clear.

Table

3-7 summarizes

during CPU

cache

Table

3-7

the effect of CCR

<K7,0>

parity

CACHE PARITY ERRORS

DURING CPU CYCLES

Cache Miss and Update
Interrupt to 114.

Cache;

Cache

cache;

Table
errors

Abort

Miss

and

Update

Interrupt.

Instruction and Trap

3-8 summarizes the effect of CCR <7,0> on
during

errors

reads.

DMA writes.

DMA

114.

Tag

Parity

FUNCTIONAL

TABLE

CCRK7>

Trap

Memory

programs
register

the

cause

System

and

start.

will

Memory

reflects

bits

Control

Error

status

are

CYCLES

Error

114.

affected
be

the

flushed

negation

BUS

and

INIT.

CCR

address

DCOK

and

The

J1l1

ODT

cleared.

cache

and

used

the

(MSER),

main

)

memory

KDJ11-BF

to test the Cache DMA Tag
format; Table 3-9 contains

Parity

cleared

not

cache

DMA

Interrupt.

DURING

Cache

Interrupt

command

The

console

3.4.4

Result

ERRORS

Cache

CCRKO>

PARITY

Store.
the bit

parity

Boot

777

744,

errors.

MSER

and

Diagnostic

Figure 3-15 shows
descriptions.

L— DTS PAR

DTS CMP
CPU ABORT

CACHE HB DATA PARITY ERROR
CACHE LB DATA PARITY ERROR
CACHE CPU TAG PARITY ERROR
CACHE DMA TAG PARITY ERROR

FIGURE

3-15

MEMORY

SYSTEM

The

CACHE

3-8

DESCRIPTION

ERROR REGISTER

FORMAT

the

FUNCTIONAL

DESCRIPTION

TABLE

-Ed

GEP

JRD

GID

GUS

TED

CPU

3-9

TED

MEMORY SYSTEM

GED

GiD

DMA

GED

AFD

GED

GID

WED

GED

GRS

GED

TGl

GNP

AED

DESCRIPTIONS

GED

GhD

GEP

GED

GEP

aND

GEb

GEh

Tag

In Stand-Alone Mode (BCSR <8> set), this bit
indicates the output of the Cache DMA Tag
Store Comparator for the previous non-I/0O Page
reference with cache miss. When BCSR <8> 1is

(DTS
(RO)

DMA

BIT

This bit is set if a cache or main
memory
parity error results in an instruction
abort (i.e. only during the demand read cycle).
Cache parity errors cause
an abort only if
CCR <7> is set. Main memory parity errors
always cause an abort.

Store

Comparator

Abort

(RO)

ERROR

CMP)

clear,
Tag

Store

Parity

DTS

CMP

Stand-Alone

reads

Mode

(BCSR

"O".
<8>

set),

this

bit

(DTS PAR)
(RO)

indicates the output of the DMA Tag Store
Parity Check Logic for the previous
non-I1I/0
Page Reference with cache miss. When BCSR <8>
is clear, DTS PAR reads as a "O0".

12-08

Unused

These

Cache HB
Data Parity

This bit is set if a parity error is
detected in the high data byte during a CPU
cache read. If CCR <7> is clear, MSER <7> 1is
also set by a low byte parity error and by the
set condition of MSER <5> or <4>.

Error

(R/W)

Cache LB Data
Parity Error

(RO)

Cache CPU Tag
Parity Error

(RO)

Note:

bits

always

read

"0".

This bit is set if a parity error is detected
in the low data byte during a CPU cache read.
If CCR <7> is clear, MSER <6> is also set by a
high byte parity error and by the set
condition MSER bits <5> or <4>.
This bit is set if a parity error is detected
in the CPU tag field during a CPU cache read.
If CCR <7> is clear, MSER <7> is also set by a
high or low data byte parity error.

Cache parity errors are ignored (do not affect
MSER <7-5>), if either CCR <3> or <2> (Force Miss)
is set or if the CPU Tag Valid bit is clear.

FUNCTIONAL

TABLE

3-9

BIT

(Cont)

NAME

FUNCTION

Cache DMA Tag

Parity

This bit 1is set 1is a parity error
is detected

Error

(RO)

the

DMA

tag

Cache

MSER

parity

<4>),

set

Unused

errors

These

bits

always

Cache

parity

occur

result

1in

1If

errors

CCR

error

set

trap

CCR

set

which

always

read

zero.

during

<7>

(Parity

<15>
thru

<7>

and

the

vector

CCR

<7>

error

vector

error

DMA

tag

field

cause

trap

MSER

CPU

trap

CCR

bits

<7>

1is

set,
current

error

bit(s)

abort
the
thru vector

Cache

the

Miss)

clear.

CPU
to
to trap

abort

affect

access

may

location

114,

and

<0>:

cache

parity

instruction,

MSER

<7:5>

and

114.
CCR

CCR

force

<0>

also

force a
and
¢to

<0>
a

<7:5>.,

set,

cache

The

clear,

cache miss,
trap
thru

miss

CPU

cache
and

does

not

cache

set the
vector

parity
set

trap

the

thru

11l4.

parity

location

errors

which

114

CCR

occur

<7>

during
set

DMA

CCR

cycle
<0>

Memory

reference.

and

CPU

bits

location

Cache

the

and/or

relevant

and

clear,

causes

relevant

The

write

(Force

Abort)

location

clear,

<2>

cause
the
MSER <15> and

condition

Error

not

following

CPU

(do

bit

the

ignored

<3>

abort

MSER

clear.

DMA

Valid

instruction

causes

CCR

parity
error causes the CPU to
relevant error bits MSER <7:5>
location 114.
3.

during

Tag

DMA

memory parity errors
current
instruction,
to
location 114.

are

either

the

Main

depending

field

operation.

Note:

03:00

DESCRIPTION

System

Error Register is cleared
by
is-also cleared on power up or by

unaffected

RESET

instruction.

any
MSER
a console

write
start.

FUNCTIONAL

DESCRIPTION

3.4.5

Hit/Miss

This

most

recent

misses.
up
1is
console
will

the

address

memory

777

752,

references

indicates

resulted

whether

cache

The Hit/Miss Register is read only.
1Its
UNDEFINED.
The
Hit/Miss
Register
1is
start or a RESET instruction.
The
Hit/
3-16

bit

CPU

always

Figure

read

zero

illustrates

when

the

CPU

1is

format;

hits

the
or

six
cache

value at
power
not affected by
Miss
Register

console

Table

3-10

ODT

mode.

contains

descriptions.

FIGURE

TABLE

15:06

Unhsed

05:00

Cache

3-16

3-10

HIT/MISS

BIT

DESCRIPTIONS

Always read as zeros.
Hit

Bits

enter

from

the

right

(at

bit

<0>)

and

are

shifted leftward. A set bit indicates a cache
hit, a cleared bit indicates a cache miss.

3.5

ADDITIONAL

The

general

CPU

Registers

Two sets of

include:

six working registers

(RO-R5)

Kernel/supervisor/user stack pointers
Program counter

(R6)

(R7).

Other major registers are described in the following subsections.

FUNCTIONAL

3.5.1

Processor

Status

DESCRIPTION

Word

The Processor Status Word (PS), at location 17 777 776,
contains
information
on
the
status
of
the
processor.
The
PSW
1is
initialized
at
power
up
(depends
on
EE
PROM
CONFIGURATION
options)
and is cleared at console start.
The RESET instruction
does not affect the PS.
Figure 3-17 illustrates the register and
Table

3-11

contains

the

bit

descriptions.

SUSPENDED

—]
PRIORITY

INSTRUCTION

CARRY

LEVEL

OVERFLOW

2ERO

| REGISTER

SET

NEGATIVE

PREVIOUS MEMORY

MANAGEMENT MODE

TRACE TRAP

CURRENT MEMORY
MANAGEMENT MODE

FIGURE

TABLE

3-17

3-11

PROCESSOR

BIT

NAME

15:14

Current Mode
(R/W, protected)

STATUS

WORD

BIT

DESCRIPTIONS

FUNCTION

Current processor mode:
00 = kernel
01 = supervisor
10

=
=

illegal
user.

13:12

Previous Mode
(R/W, protected)

Previous
encoding

General

(R/W,

WORD

Set

protected)

(traps)

processor mode, same
as current mode.
register

set

select:

FUNCTIONAL DESCRIPTION
TABLE

3-11

BIT

(Cont)

NAME

FUNCTION

Suspended

Reserved

for

future

use.

Instruction(R/W)
7:5

3:0

Priority

Processor interrupt

(R/W,

protected)

level.

Trace

Trap

Set

(R/W,

protected)

Condition

Codes

force

Processor

trace

condition

priority

trap.

codes.

(R/W)

3.5.2

The
772,

Program

Interrupt

implements

Regquest

Request

software

interrupt

(PIRQ),

facility.

location
When

777

program

interrupt
request
1s
granted,
the
processor
traps
through
location
240.
It
is
the
interrupt
service
routine's
responsibility to
<clear
the
appropriate
bit
in
PIRQ
before
exiting.
PIRQ is cleared at power-up, by a console start and by
the RESET instruction.
Figure 3-18 illustrates the register
and
Table 3-12 contains the bit descriptions.

PIR7

PRIORITY ENCODED
VALUE OF BITS<15:9>

PIR6

PIRS
PIR4
PIR3
PIR2

PIRY

FIGURE 3-18 PROGRAM INTERRUPT REQUEST REGISTER

FUNCTIONAL

TABLE

3-12

15:09

PROGRAM

PIR

INTERRUPT

7-1

REQUEST

Each

bit,

when

set,

BIT

DESCRIPTION

DESCRIPTIONS

provides one

seven levels of software interrupt
corresponding to interrupt priority
levels 7 through 1.
08

Unused.

07:05

Piority

encoded

value of
<15:09>

bits

These

bits

are

set

the

CPU

Unused.

03:00

three

to the encoded value of the highest
pending interrupt request (bits 15:09).

' *¥

3.5.3

*r r .

encoded

The

bits

r. >

Piority
value of
<15:09>
¥*xr

CPU

¥y

r»*x

¥y

§FK

Error

function
bits

these

bits

identical

07:05.

The Error Register, at address 17 777 766, identifies the
source
of
any abort or trap that caused a trap through location 4.
The
CPU Error Register is cleared when it is
written.
It
1is
also
cleared
at
power up or by console start.
It is unaffected by a
RESET instruction.
Figure 3-19 shows the register format;
Table
3-13 contains the bit descriptions.

)

ADDRESS ERROR

i70 BUS TIMEOUT
YELLOW STACK VIOLATION

RED STACK VIOLATION

FIGURE

3-19

CPU

ERROR

3-41

FORMAT

FUNCTIONAL

DESCRIPTION

TABLE

3-13

CPU

ERROR

BIT

DESCRIPTIONS

FUNCTION

Illegal HALT

Set

1s
Address

Error

when

execution

attempted

Set

when

word

HALT

instruction

user

supervisor

access

odd

(RO)

address or an instruction fetch
internal register is attempted.

Non—-existent

Set

Memory

times

when

reference

main

reference

the

mode.

byte

from an

memory

out.

(RO)

I/0

Set when

Bus

Timeout

times

I1/0

page

out.

(RO)
Yellow

Stack

Violation

Set

yellow

red

zone

stack

overflow

trap.

(RO)
Red

Set

Stack

zone

stack

overflow

trap.

Violation

(RO)

3.5.4 CONFIGURATION AND DISPLAY REGISTER
The

read-only Boot

reflects

and

the status of

Configuration
Register
(BCR)
eight edge-mounted switches at the top

Diagnostic

the

All of the switches are also
routed
¢to
KDJ1l1l-BF module.
KDJ11-BF
module
to
allow
them
to
be
asserted
the
connectors
on
Switches 1-8 control register bits 7-0 respectively.
remotely.

the

NOTE

All

eight

OFF,

and

restricted
Appendix H

Data

bits

the

baud

2-0

switches

setting

the
KDJ1ll-BF
module
any
of
these
switches

special
applications.
Refer
to
for a more detailed description.

(switches

6-8)

are
is
to

are also connected directly

the

three
rate select lines of the console SLU on the KDJ1l1l-BF
baud
These three bits always
control
module to select the baud rate.
purpose.

rate

Switches

the

6-8

are

console, and are not used for any other
rate
baud
the
normally OFF to allow
3-42

FUNCTIONAL

select
switch
on
cabinet) to select
gain access to the

DESCRIPTION

the Console Serial Line board (rear
the baud rate.
This eliminates
the
CPU module to select the baud rate.

of box
need

The only time switches 6-8 would be used to select the,baud
is
for

1if the baud rate switch was
additional information.

Data

bits

some

7-3

the

restart.

(switches

actions

Refer

these

bits.

Figure

3-20

shows

1-5)

the

are

taken

Appendix

not

read

for

present.

the
a

the

ROM

code

detail

format.

Refer

code

power

description

Bits

15-8

are

FIGURE

The

3-20

don't

BOOT

write-only

address

each

always

AND

DIAGNOSTIC

and

524,

connector.

on)
by
the
format; Table

Bits

the

05-00

Display

Boot

Test LED
display

negation
of
3-14 contains

CONFIGURATION

Diagnostic

allows

the front panel Start-Up
KDJ11-B
module.
These
external

dont't

are

cleared

power

3-21

DISPLAY

3-43

the

care

FIGURE

light

display and
the
LEDs
on
the
bits
are also available on an

8-8IT

(BDR),

programs

DCOK.
Figure 3-21 shows
the bit descriptions.

X | X

FORMAT

Diagnostic

SWITCH PACK

read

of the
might

care

Boot

777

define

as
zeros.
The value of bits 7-0 depends on the position
switches on the CPU module, and any external switch
which
be connected.

rate

to-Appendix

after

or
to

(all

LEDs

FUNCTIONAL

DESCRIPTION

TABLE

15::06

——=—-=

05::00

LED

3-14

DISPLAY

BIT

DESCRIPTIONS

Unused
5-0

These

bits

programs

Maintenance

enable

the

boot

and

light

the

LEDs

located

top of the
these bits

3.5.5

diagnostic

CPU module. Clearing any
lights the corresponding

the
of
LED.

The Maintenance Register, at address 17
777
750,
accesses
the
16-bit word read by the J1ll Chip Set (through GPO Code) test BPOK
H, read the power up option code, read the halt/trap option
bit.
Other
bits
in
the
maintenance
register,
not
wused
by
Jll
microcode, contain information on
the
module
¢type
and
system
parameters
useful
to
operating system and diagnostic software.
Figure 3-22 shows the register format; Table
3-15
contains
the
bit descriptions.
The

power

option

code

hard

wired

operation
(code
2).
The
PSW
1is set
begins
program
execution
at
address

for

standard

bootstrap

to 340 and the processor
173000,
The
Boot
and

Diagnostic
Code,
which
starts at that location, configures the
KDJ11l-B and runs stand-alone diagnostics
before
acting
on
the
user
specified
power
up
option
stored
as part of the EEPROM
Configuration Data.

Because the Jl1 Microcode never sees
power
up
option
code
3,
selecting
a
start
location specified by register bits <15:09>,
these Maintenance
Register
bits
are
used
to
specify
system
parameters.
15

l 0

RESERVED

UNIBUS SYSTEM
FPA AVAILABLE

MODULE TYPE (FIXED)

HALT/TRAP OPTION
POWER UP OPTION (FIXED)
8POK H

FIGURE

3-22

MAINTENANCE
3-44

FORMAT
|

FUNCTIONAL

TABLE

15:11

3-15

Unused

MAINTENANCE

Reserved
Read

future

BIT

DESCRIPTIONS

expansion.

zeros.

Unused

Reserved

UNIBUS

This

for

future

use.

(RO)

bit reflects the status of the extrenally
applied UNIBUS Adapter Line. A "1" indicates
that the system includes a UNIBUS Adapter.

FPA

When

Available

available
- for

System

for

DESCRIPTION

set,

this

bit

indicates

that

the

FPA

"2",

use.

(RO)
07:04

Module

This

Type

indicating

Halt/Trap
(R/W)

4-bit

ROM

selected by
Trap Option
1s reserved
Power
Code

hard-wired

KDJ11-BF

Module.

This read/write bit determines the response of
a processor to a Kernel Mode Halt instruction.
Setting the bit selects the Trap Option,
causing the CPU to trap to location 4. Clearing
the bit selects the Halt Option, causing the CPU
to halt and enter ODT. This bit is cleared by
the negation of DCOK and is set by the Boot and
Diagnostic

02-01

code

the

Trap

Option

1is

a bit in the Configuration RAM. The
is not intended for normal use and
for controller applications.

This

2-bit code is hard-wired as a "2". At
power up, the processor sets the PC to 173000
and sets the PSW to 370. It then starts program
execution at location 173000, which is the

starting

location

Diagnostic

out
the
the

ROM

for

the

program.

KDJ1l1l-BF

These

Boot

programs

and
test

the KDJ11l-BF Module and then implement
user selected power up option specified
Configuration Data.

This bit is set (1) if the PMI BUS signal BPOK
is asserted, indicating that AC Power is okay.

3-45

FUNCTIONAL

3.5.6

The

DESCRIPTION

Boot

and

Diagnostic

Controller

Status

address
17
777
520, is both word
3-23
the
register
format;
Table

and byte
3-16

(BCSR),

addressable.
Figure
contains
the
bit

descriptions.
The
BCSR
allows
the
Boot
and
Diagnostic ROM
programs to test battery backup status, set
parameters
for
the
PMG
(Processor
Mastership Grant) Counter and for line clock, to
enable the Console Halt
from stand alone mode.
The

BCSR

also

allows

response

17765776

and/or

read/write

the

access

Programs which
and line clock
feature and to

these

Boot
at

and

Break

programs

Diagnostic

addresses

the

feature

and

enter

selectively

ROM's

17773000

disable

addresses

17773776

and

control

access the I/0 Page can use the BCSR to alter
PMG
parameters, to enable or disable the Halt on Break
control access to the ROM and and EEPROM memories.

LPMG CNTO

NOT USED-

PMG CNT!

FRC LCIE ———J

PMG CNT2

DIS LKS

CLK SEL 1

RS3 WE

CLK SEL O

RS3 65

ENB HOB

DIS 65

SA MODE

3-23

the

17765000

EEPROM memory.

88 RBE

FIGURE

exit

OIS 73

BOOT AND

DIAGNOSTIC

CONTROLLER

FORMAT

FUNCTIONAL

TABLE
BOOT

AND

DIAGNOSTIC

Battery

bit

3-16

CONTROLLER

Backup

indicates

DESCRIPTION

Reboot

Enable.

received
DC

batterv

DESCRIPTIONS

When

backup

set,

this

to
maintain voltages to the memory system during the previous power failure. When this
bit is clear, it indicates that the system
does not feature battery backup, or that
battery backup maintained voltages during
the previous power failure. This signal is
when

that

BIT

from backplane pin BH1l
OK.is

failed

and

latched

asserted.

Not

used

Could

FRC

LCIE

Force Line Clock Interrupt Enable. If this
bit is set, assertion of the signal selected
by BCSR <11,10> (Clock Select Bits 1 and 0)
will unconditionally request interrupts. If
FRC LCIE is clear, assertion of the selected
signal will request interrupts only if the
Line Clock Status Register bit <6> (LCIE)
is set under program control. FRC LCIE is
cleared by the negation of DCOK.

DIS

LKS

Line

Clock

this bit
Register

"1"

Status

"O".

Disable.

is set, the Line Clock Status
(LKS) is disabled. If this bit

1s clear, LKS 1is enabled and responds
to bus address 17777546. LKS DIS is
cleared by the negation of DCOK.
11

CLK

SELI

Clock

CLK

SEL2

select the source of
interrupt request:

CLK

Select

SELl1

CLK

Bits

SELO

and
the

bits

are

cleared

These

line

Source

0
1
0
1
Both

External
On-Board
On-Board
On-Board
by

the

two

bits

clock

Interrupt
LTC Line
50 Hz
60 Hz
800 Hz
negation

DCOK.

FUNCTIONAL

DESCRIPTION

TABLE

BIT(S)

NAME

ENB HOB

(R/W)

(Cont)

FUNCTION

Enable Halt on Break. When this bit is-set,

Console

Serial

Line

is enabled. When
is disabled. ENB
of DCOK.
08

3-16

MODE

Stand-Alone

(R/W)

KDJ11-B

Unit

Halt

Break

this bit is clear
HOB is cleared by

Mode.

operates

When

this

bit

stand—-alone

the
the

feature
negation

set,

mode,

the

feature

the

using

its

Cache as main memory. External memory and
peripherals are all disabled. When SA MODE is
clear, Stand-Alone Mode 1is turned off, enabling
external memory and peripherals. SA MODE is set
by the negation of DCOK.
07

DIS

Disable

(R/W)

DIS

17773000.

response

the

When

this

bit

16-bit ROM memory

set,

to addresses

17773000 - 17773776 1is disabled, allowing the
operation of an external ROM that uses those
addresses. When DIS 73 is clear, the 1l6-bit
ROMs respond to those addresses, using the
high byte of the page control register as the
most significant address bits. DIS 73 is
cleared by the negation of DCOK.

Disable

(R/W)

17765000.

response of

When

this

bit

the Boot and Diagnostic

set,

16-bit

8-bit ROM memory to addresseS 17765000 17765776 is disabled, allows the operation

and

of
external ROM which uses those addresses. When
DIS 65 is clear, the ROM memory selected by
BCSR <5> responds to those addresses, using the
low byte of the page control register as the
most significant address bits. DIS 65 is
cleared by the negation of DCOK.
05

RS3

ROM

(R/W)

Socket

whether there

17765000.

This

16-bit ROM

bit

selects

in ROM sockets

one and two or there is an 8-bit ROM in ROM
socket three responds to addresses 17765000 17765776 (assuming that BCSR <4> is clear). If
RS3 65 is set, the 8=-bit ROM is selected. If
RS3 65 is clear the 16-bit ROM is selected. In
either case, the low byte of the page control
register provides the most significant address
bits. RS3 65 is cleared by the negation of DCOK.

- e

GEp Gl

dED

GEF

GNP

()

D GID

GED

GED GNP

TED

aNh

TED

GEF

3-48

e r ----------------------- ‘D

e e

FUNCTIONAL

TABLE

RS3 WE

3-16

(Cont)

ROM socket 3 Write Enable.
is clear,

and

contains
Up

and

bit

If BCSR <6> (DIS 65)

if BCSR <5> and

RS3 WE) are both
write access ROM

<4>

(RS3

65 and

set, then the program can
socket 3 which typically

EEPROM.

Bus

DESCRIPTION

RS3

cleared

Power

Initialize.

Unused

This

always

reads

"O".

02
0l
00

PMG CNT2
PMG CNTI1
PMG CNTO

Processor Mastership Grant
O. These three bits enable

Count bits 2, and
the PMG Counter and
select the length of time for PMG Counter
overflow. When enabled, the PMG Counter begins

counting when the
Page

location

overflow
DMA

causes

Requests

KDJ11-BF must
external

the

and

KDJ11l-BF

give

the

access an

memory.

I/0

Counter

suppress

processor

all

bus

mastership during the next DMA arbitration
cycle. When the PMG Counter is disabled, the
processor is blocked from bus mastership as
long as DMA Requests are pending. All three
bits are cleared by the negation of DCOK.
PMG

CNT2

The

Page
Page

0
1

1
0

Time

(Disabled)*
0.4

usec

0.8

usec

1.6

usec

3.2

usec

-0

6.4

usec

12.8

usec

25.6

usec

PMG
most

count

typical

(Disabled)

systems,

and

not

reserved

recommended
for

applications.

Control

that

Figure

shows

3-24

Count

for

descriptions.

CNTO

read-write
bit

PMG

0
0

The

Control

CNT1

special

3.5.7

PMG

the

1is

addrress

both
format;

byte
Table

777

522,

1is

and word addressable.
3-17

contains

the

FUNCTIONAL

DESCRIPTION

TABLE

Not

14:09

High

3-17

used

Byte

(R/W)

—

HIGH BYTE

FIGURE

LOW BYTE

3-24

PAGE

CONTROL

Always

These

CONTROL

read

six

FORMAT

DESCRIPTIONS

zero.

bits

provide

the most

significant

ROM address bits when the 16-bit ROM sockets
are accessed by bus addresses 17773000 17773776.

08:07

Not

used

Always

06:01

Low

Byte

These

3.5.8

read

six

zeros.

bits

provide

the most

significant

(R/W)

ROM (or EEPROM) address bits when the 16-bit
or the 8-bit ROM (or EEPROM) sockets are
accessed by bus addresses 17765000 - 17765776.

Not

Always

Line

used

Frequency Clock

read

and

zero.

Status

The Line Clock provides the system
with
timing
1nformation
at
fixed
1intervals
determined by the UNIBUS LTC line or by the one
of the on-board KDJ1l1l-BF frequency signals as programmed by
Boot

and

Diagnostic

Typically,

LTC

Controller

<cycles

Status

the

bits

frequency,

and

10.

producing

intervals
of
16.7
msec (60 Hz line) or 20.0 msec (50 Hz line).
The three on-board frequencies are 50 Hz, 60 Hz and 800 Hz.
The Clock Status Register (LKS), at address 17777546, allows Line
Clock
interrupts
to
be
enabled
and
disabled
under
program
control.
Alternatively,
line
clock
interrupts
can
be

3-50

FUNCTIONAL

DESCRIPTION

unconditionally enabled by setting BCSR <13> (FRC LCIE).
Program
recognition of the Clock
Status
Register
can
be
disabled
by
setting BCSR

The

normal

<12>

(LKS

KDJ11-BF

DIS).

configuratioen

FRC

LCIE

and

LKS -DIS

both

clear.
These
bits
are
set
up by the Boot and Diagnostic ROM
programs from the KDJ11-BF Configuration Data.
Figure 3-25 shows
the register format; Table 3-18 contains the bit descriptions.

FIGURE

4-25

STATUS

CLOCK

TABLE 3-18 CLOCK STATUS REGISTER BIT DESCRIPTIONS

read

zero.

15:08

Unused.

Always

LCM

Line Clock Monitor.

(R/W)

This bit

is set by

the

leading edge of the external BEVENT line (or

of one of the three on-board clock frequencies)
and by Bus Initialize. LCM is cleared
automatically on processor interrupts

acknowledge. It is also cleared by writes to
the LKS with bit <7> = "0",

LCIE

(R/W)

Line Clock Interrupt Enable -- This bit, when

set, causes the set condition of LCM (LKS <7>)

to initiate a program interrupt request at a
priority level of 6. When LCIE is clear, line
clock interrupts are disabled. LCIE is cleared
by Power Up and by Bus INIT. LCIE is held set
INIT. LCIE is held set when BCSR <13> (FRC
LCIE)

05:00

Unused

Always

set.

read

zeros.

FUNCTIONAL

DESCRIPTION

3.6

STACK

LIMIT

The

KDJ11-BF

PROTECTION

checks

of 400(8).
If
than 400(8), a
instruction.

kernel

stack

references

against

reference,
which
1is
R6, or a JSR, trap, or

defined as a mode 4 or
interrupt stack push.

<checks

interrupt,
a

red
loading

the

J1ll

trap,

sequences,

limit

is less
current

A stack trap can only occur in kernel mode and only

addition,

fixed

the virtual address of the stack reference
yellow stack trap occurs at the end of the

and

kernal

for

abort

stack

trapping thru location 4
are saved in kernel data

sequences.

push

zone
stack
trap
virtual address 4

kernel

causes

stack

If,

the

one
Jll

during

these

initiates

Error

stack

pointer

in kernel data space.
space locations 0 and

stack
through

aborts

during

abort,

by setting CPU
into the kernel

reference

bit
(R6)

<2>,

The o0ld PC and
2 respectively.

and

NOTE

The

J-11

treatment

identical

definition
definition

stack

1limit

3.7

KERNEL

PROTECTION

order

In
In

set

vyellow

and

stack
red stack

¢the

The

kernel

RTI
In

<15:11>

and

trap

includes

inclusive

operating

incorporates

RESET

stack

11/70

reference.
The
trap is unique.

HALT, RESET, and
or
user
mode,

while

In kernel mode,
<7:5>
freely.

only

of
a

KDJ1l1l-BF

kernel mode,
supervisor

location
b.

the

11/44,.

protect

interference,
mechanisms:
a.

the

SPL

the

Jll's

system

following

SPL execute
HALT
causes

are

treated

against

protection

as
specified.
a trap through

NOPs.

and RTT can
alter
PS
<15:11>
supervisor or user mode, RTI and

and

cannot

alter

and
RTT

PS
can

supervisor

<7:5>,.

In kernel mode,
user mode, MTPS

All trap and interrupt vector references are
classified
as
kernel
space
references,
irrespective
of the memory management mode at the time of the trap or interrupt.

Kernel

stack

Supervisor

MTPS can alter PS <7:5>.
cannot alter PS <7:5>.

references

and

user

stack

are

<checked

references

3-52

for
are

not

stack

overflow.

checked.

FUNCTIONAL

3.8

TRAP

AND

INTERRUPT

SERVICE

DESCRIPTION

PRIORITIES

In both traps and interrupts, the currently executing program
1is
interrupted
and
a new program, the starting address of which 1is
specified by the trap or
interrupt
vector,
1is
executed.
The
hardware
process
for traps and interrupts through a vector V is
identical:
PS

-=>

temp

=-=>

temp

-->

!save

<15:14>

1 force

M[V] -=-> PC
M[V+2] ==> PS
templ<15:14> -->
SP-2 --> SP
templ --> M[SP]

kernel

temporaries

mode

l1fetch PC from vector,
| fetch PS from vector,
|I!set previous mode
!selected by new PS
!push o0ld PS on stack,

data
data

space
space

data

space

'push old

data

space

-->

SpP-2

PS<K13:12>

PS,

temp2 -->

M[SP]

PC on stack,

!go execute

instruction

NOTE

If an abort occurs during either the vector fetch
or
the stack push, the PS and PC are restored to
their original state (i.e.
to the state prior to
trap sequence execution).
The

priority
red

order

stack

address

for

traps

and

trap

error

memory management

violation
timeout/non-existent memory
parity error
trace (T-bit) trap
vyellow stack trap
power

fail
floating point trap
PIRQ 7
interrupt level 7
PIRQ 6
interrupt level 6
PIRQ

5
interrupt
PIRQ 4

interrupt
PIRQ 3
PIRQ 2
PIRQ

halt

line

level

interrupts

follows:

FUNCTIONAL

DESCRIPTION

NOTE

The

halt

line

processor

3.9

CONSOLE

SERIAL

given

hangs

up.

LINE

UNIT

highest

priority

when

-<the

The console serial line provides the KDJ1l-BF
processor
with
a
serial
1interface
for
the console terminal.
The console serial
serial line is full duplex.
It provides an RS-423 EIA
interface
which is also RS-232C compatible.

Link
Digital
DC319
the
additional
For
(DLART).
under
1
1in Chapter
1listed

This serial line interface is based on
Transmitter
Receiver
Asynchronous

details refer to Chipkit
additional

handbook

documents.

and
receive
serial
console
the
that
insure
The user should
identical and are determined by three
are
rates
baud
transmit
switches settings that are mounted on top of the KDJ11-BF Module,
external SLU distribution board and baud
the
via
remotely,
or

rate switch.

The

switch

settings

should

remain

the

off

position.

settings
switches
additional
five
These switch settings, plus
Facility
Diagnostic
and
Boot
the
via
read
be
may
07-03)
(Switches
and
Boot
the
on
a
is
07
switch
If
(BCR).
Register
n
Configuratio
a
have
not
does
system
the
that
assumes
Programs
Diagnostic
1limited
a
select
to
06-00
switches
uses
console terminal and

Setting switch 07 does
of KDJ11-BF and system parameters.
range
runs at the baud
which
interface
not disable the console terminal
these switches,
of
settin
The
reflected by switches 02-00.
rate
ns.
consideratio
n
configuratio
however, is determined by system

Receiver
the
There are four console serial line unit registers:
Status
Transmitter
Status Register, the Receiver Data Buffer, the
recognition
Program
Register, and the Transmitter Data Buffer.
Each register 1is
these registers can not be disabled.
of
described

in the following subsections.

3.9.1 Receiver Status Register

(at
_Figure 3-26 shows the Receiver Status Register (RCSR) format
Table 3-19 contains the bit descriptions.
address 17 777 560).

FUNCTIONAL

)

DESCRIPTION

RX DONE

RX IE

FIGURE

TABLE

15:12

3-19

3-26

RECEIVER

Unused.

RCV ACT

(RO)

STATUS

Read

BIT

Receiver Active. This bit is set at the center
of the start bit of the serial input data and
is cleared at the expected center (per DLART
timing) of the stop bit at the end of the
.
serial data. RX DONE is set one bit time after
RCV ACT

1is

cleared.

zeros.

Unused.

Read

Receiver Done.
This bit is
character has been received

DONE

(R/W)

also cleared

Receiver

Unused.

Interrupt

Power

Up.

Enable.

This

bit

cleared

by Power Up and Bus INIT. If both RCVR DONE
RCVR INT ENB are set a program interrupt is
requested.

05:00

set when an entire
and is ready to be

read from the RBUF register. This bit is
automatically cleared when RBUF is read.
is

DESCRIPTIONS

zeros.

10:08

(RO)

FORMAT

Read

zeros.

and

FUNCTIONAL

3.9.2

Receiver

Figure

(at

DESCRIPTION

3-27

Data

shows

address

Buffer

the

Receiver

777

Data

562).

Buffer

Table

3-20

(RBUF)

contains

descriptions.
15

TABLE

OVR
ERR

3-20

FRM

ACV

ERR

BRK

3-27

RECEIVED

NAME

DATA BUFFER

Error.

(RO)

set.

This

ERR

Overrun

FRM ERR
(RO)

BIT

FORMAT

DESCRIPTIONS

bit

these

cannot

This

character

set
if

the

bit
was

RBUF

<K14>

two

generate

1is

set

not

read

present

bits

conditions

detect
remain

<13>

are

program

previously

before

being

character.

Framing Error. This bit is set if the
character had no valid stop bit. This
used

Error

cleared

Error.

received

overwritten

NOTE:

FUNCTION

(RO)

RECEIVED DATA BITS

DATA BUFFER

ERR

OVR

)

‘l

cleared. This
interrupt.
14

]

FIGURE

BIT(S)

bit

l
ERR

format

the

present
bit is

break.
present

until

the

character

is received, at which point, the error bits are updated.
The Error bits are not necessarily cleared by Power Up.
12

Unused

This

bit

always

reads

RCV BRK

Received

bit

(RO)

for

the

Break. This
received character

"0".
set

at the end of
serial data input

remained in the SPACE condition for all 11 bit
time. RCV BRK then remains set until the serial
data input returns to the MARK condition.
~10:08

Unused

These

bits

always

read

07:00

Received
Data Bits

These read-only bits
character.
:

"0".

contain

the

last

received

FUNCTIONAL

3.9.3

Transmitter

Status

DESCRIPTION

Figure

3-28 shows the Transmitter
(at
address
17
777
564).
descriptions.

I 0

Status

Table

3-21

(XCSR)
format
contains
the
bit

TX RDY

MAINT

XMIT

BRK

FIGURE

TABLE

3-21

BIT(S)

NAME

15:08

Unused

RDY

(RO)

3-28

TRANSMIT

Read

(R/W)

STATUS

FORMAT

BIT

DESCRIPTIONS

This

bit

sets

when

XBUF

zeros.

Transmitter

XBUF

is
by

Ready.

loaded

another

STATUS

FUNCTION

and

character.
Bus

XMT

RDY

Interrupt

Enable.

by Power Up and

RDY

requested.

and

05:03

Unused

Read

MAINT

Maintenance.

(RO)

maintenance

cleared
set

Power

are

by Bus

set,

This

bit

INIT.

program

output is used as the serial input. This
cleared by Power Up and by Bus INIT.

XMIT BRK. Transmit Break. When this bit is set,
XMIT

both

This bit is used to facilitate a
self-test. When MAINT is set, the
serial input is disconnected and the

Unused

serial

interrupt

(R/W)

zeros.

external

Read

when

can receive

INIT.

Transmitter

cleared

serial
bit is

and

zero.

output

BRK

forced

cleared

the

Power

SPACE
and

the
CONDITION.,

Bus

INIT.

FUNCTIONAL

3.9.4

DESCRIPTION

Transmitter

Data

Figure

3-29 shows the
format,
at
address:
descriptions.

Buffer

Transmitter

Data
Buffer
566.
Table 3-22

777

(XBUF)
the bit

XBUF

FIGURE

3-29

TRANSMITTER

DATA BUFFER

FORMAT

TABLE 3-22 TRANSMITTER fiATA BUFFER REGISTER BIT DESCRIPTIONS

BIT(S)

NAME

15:08

Unused

Always

read

07:00

XBUF

These

eight

(WO)

transmited

3.9.5

Break

FUNCION

zeros.

bits

are

used

load

the

character.

Response

The KDJ11-BF Console Serial Line Unit may be configured either to
perform
a
halt
operation
or
to have no response when a break
condition is received.
A halt operation will cause the processor
to
halt and enter the octal debugging technique (ODT) microcode.
The Halt on Break Option is selected via bit 9 of
the
Boot
and
Diagnostic
Controller
Status
Register.
During
Power
up
or
Restart, the boot and diagnostic ROM program will always set
Dbit
9
to
a
1.
This will enable the Halt on Break condition if the
Keylock switch is in the ENABLE position.
The

DLART recognizes a break condition at the end of
a
received
character
for
which the serial data input remained in the SPACE
condition for all 11
bit
times.
The
Break
Recognition
1line
"remain
asserted
until the serial data input returns to the MARK
condition.
'

FUNCTIONAL

3.10

KERNEL/SUPERVISOR/USER MODE

The PDP-11/84

processor

DESCRIPTION

DESCRIPTIONS

family offers

three modes

execution,

Kernel, Supervisor, and User.
Their use is to enhance the memory
protection
scheme
and
to
increase
the
flexibility
and
functionality of timesharing and multi-programming environments.
Kernel

mode

the most privileged

the

three modes

and

allows

execution
of
any instruction.
In an operation system featuring
multi-programming,
the
wultimate
control
of
the
system
is
implemented
in
code
that
executes in Kernel mode.
Typically,
this includes; control of physical I/0 operations, job scheduling
and

resource

management.

Memory management mapping and protection allows
these
executive
elements
to be protected from inadvertant or malicious tampering
by programs executing in the less privileged processor modes.
1If
the
I/0 page is only mapped in kernel mode, then only the kernel
has access to the memory management registers to re-map or modify
the
protection.
This is because the memory management registers
themselves exist in the I/O page.
|
In order for a user program to have sensitive functions performed
in
1its
behalf, a request must be made of the executive program,
typically in the
form
of
a
software
¢trap
that
vectors
the
processor
into
kernel mode.
Thus the executive code remains in
control and can verify that the function requested is
consistent
with
The

the

operation

supervisor

mode

the

system

most

a whole.
privileged

used
to
provide
for
the
mapping
and
shareable by users but
still
requiring
This
might include command interpreters,

runtime

User

mode,

and

execution
protection
logical I/0

may

systems.

mode

1is

the

1least

privileged

mode

and

prohibits

execution
Supervisor

of
instructions
such
as
HALT
and
RESET
as
mode.
A
multiprogramming
operating
system

typically

restrict

prevent
as

the

single

whole.
only

The

areas

user

execution

from having

user's
memory

virtual
that

user
a

can

The

PMG
PMG

heavy

the
the

programs

negative

address

belong
to
that user.
Areas shared
read-only, execute only, or for both

3.11

of programs
from
them.
processors,

space

written

among
read

to user mode

effect
is

the

does
will

set
are

the

system

such

those

that
that

users are protected
execute access.

and

COUNTER
Counter

UNIBUS

enables the processor to become PMI master during
DMA
activity.
This allows the processor to limit

hog mode control of the PMI during DMA activity.
To
change
PMG
counter parameters see the section on the console setup
3-59

FUNCTIONAL

mode.

DESCRIPTION

The

user

can

select

from

seven

disable.
The
PMG counter default
with no DMA interruptions from
the

counter
timeout,
with
selection 7.
Selection
timeout,
most
number

cycles.

Table

selections.

3-24

Table

the
exception
of
1
provides
the,
of
PMI
interrupts

provides

3-24

Switch

PMG

Pos.

Count

3
4
5

6
7

PMG

KTJ11-B

CACHE

and

one

the disable mode, is
fastest PMG
counter
per
number of clock

the

eight

PMG

counter

LIST

Timeout

count

3.2

usec

6.4
12.8

usec
usec

25.6

usec

(Disabled)

for most typical systems,
special applications.

3.12

values

(Disabled)*
0.4 usec
0.8 usec
1.6 usec

1
2

The

list

COUNTER TIMEOUT

counter

setting is the Disabled mode,
processor.
The
least
PMG

and

not

reserved

recommended
for
-

OPERATIONS

The

KTJ11l-B DMA Cache is used to decrease PMI memory read
access
time
for
UNIBUS
DMA
devices.
The cache 1s divided into four
sections, with each
section
capable
of
storing
up
to
eight
addresses.

Initially,the

first

PMI

KTJ11l-B

read

cache

1is

flushed

(i.e.,

octal

boundary

from a

emptied).

UNIBUS

The

DMA device

causes the KTJ1ll-B to read from memory and store that address and
the
next 7 PMI address locations locations in section A.
If the
next PMI read is one of the addresses
stored
1in
the
cache,
a
cache hit occurs.
If the next PMI read does not
match
any
cache
address
(cache
miss),
the
KTJ1ll-B
does
a memory read cycle for the requested
address - if that address is on an octal boundary - and the
next
seven PMI memory addresses.
These eight words are than stored in
-the next available cache section (i.e., B, C or D).

DESCRIPTION

FUNCTIONAL

a
If
lines.
address
PMI
The KTJ11-B cache also monitors the
the KTJ1l1-B cache compares the
occurs,
address
an
into
write
invalidated.

occurs the cache address location is
3.12.1

KTJ11-B

Cache

(hit)

match

When

address with it's stored cache addresses.

Organization

The KTJ11-B DMA Cache contains thirty-two 16-bit data
registers,
(A, B, C and D) of eight data registers
sets
four
in
arranged
an
and
Associated with each set is a Valid Bit
each (000-111).
18-bit
Tag
Register.
The
data
registers
are located in RAM
memory as shown in Table 3-24.
The Tag Registers and Valid
Bits
are
located
in
the
KTJ1ll-B
Gate
Array.
Refer to the format
presented

in Figure

TABLE

3-24

3-30.

RAM MEMORY

DATA REGISTER LOCATIONS

RAM

Address

00
01
02
03

Set
Set
Set
Set

A
A
A
A

20
21
22
23

Set
Set
Set
Set

C
C
C
C

04
05
06
07

Set
Set
Set
Set

A
A
A
A

24
25
26
27

Set
Set
Set
Set

C
C
C
C

10
11
12
13
14
15

Set
Set
Set
Set
Set
Set

B
B
B
B
B
B

30
31
32
33
34
35

Set
Set
Set
Set
Set
Set

D
D
D
D
D
D

O
1
2
3
4
5

16
17

Set
Set

B
B

36
37

Set
Set

D
D

6
7

L
FIGURE

6
7

VALID

BIT

AND

TAG

3-61

TAG REGISTER
3-30

FORMAT

(One

UNUSED
of

Four)

FUNCTIONAL

DESCRIPTION

The KTJ11l-B DMA
Cache
1interprets
the
DMA
(or
address.
Figure
3-31
1illustrates
the register
contains the bit descriptions.

CPU)
physical
and Table 3-25

INDEX

TAG FIELD

BYTE

SELECTION

FIGURE

3-31

PHYSICAL ADDRESS

INTERPRETATION

TABLE 3-25 UBA PHYSICAL ADDRESS INTERPRETATION

21:04

Tag

Field

These

to
03:01

3.12.2

bits comprise a field that
bits in the Tag Registers.

the

Index

These

Field

an even eight-word boundary (index=0) and points
to one of eight data registers in a set (A-D).

By te

Selects

Selection

This

DMA Cache

three

bit

bits

indicate

high

low

has

effect

byte

the

corresponds

write

during

address

operations.

DMA

operatlons.

Enable/Disable

The

KTJ11-B Memory Configuration Register
(KMCR)
(described
1in
subsection
3.13.3)
contains
both control and diagnostic status
bits for the KTJ1l1l-B DMA Cache.
When bit 06
Management

of the KMCR
Register
3

is cleared, or
when
bit
05
of
is
<cleared
(i.e when the UNIBUS

Memory
Map is

disabled), then the DMA Cache is disabled and initialized to
1its
power
up
condition.
All four Valid Bits are cleared.
Set A is
the Next Available Set, followed by Set B, Set C, and Set D.
The
thirty-two
data
registers
and
the
four tag registers are not
cleared and contain random information.

3-62

FUNCTIONAL

DESCRIPTION

When KTJ11-B Memory Configuration
Register
bit
06
and
Memory
Management
Register
3
bit
05
are
both set, the DMA Cache is
enabled and operates as described in the
following
subsections.
(See

Figure

3-32.)

3.12.3

DMA

Cache

Write

Operations

During
field

CPU and DMA write operations,
the
physical
address
1is checked against the Tag Register and Valid bit for

tag
each
of the four Sets
to
determine
whether
a
DMA
Cache
Hit
has
occurred.
If a Cache Hit has occured, then the Set which caused
the hit becomes the Next Available
Set
and
its
Valid
Bit
1is
cleared.
Otherwise, the DMA Cache is not affected.

PMI

UNIBUS
DMA
DEVICE
(DISK)

UNIBUS
MEMORY

MEMORY
MSV1ii-R

UNIBUS

FIGURE

3.12.4

DMA Cache

Read

3-32 PDP-11/84 CACHE DIAGRAM

Operations

During all DMA reads from PMI memory, the
physical
address
is checked against the Tag Register and Valid bit
field
tag
Hit
each of the four Sets to determine whether a DMA Cache
occurred.
Also, the physical address index field is checked
an even 8-word boundary

(index = 0).

the
for
has
for

does
If a DMA Cache Hit has not occurred, and if the index field
not equal zero, then the content of the addressed memory location
is gated onto the UNIBUS.

The DMA Cache is not affected.

If a DMA Cache Hit has not

equals zero,

then the

occurred,

and

the

index

following operations take place:
Field

1loaded

1into

The physical address Tag

The content of the addressed PMI memory location
’
onto the UNIBUS.

the

field
Tag

to the Next Available Set.

3-63

1is

gated

FUNCTIONAL

DESCRIPTION

The

content

the

seven

registers
4.

all

Bit

that

the

eight

Valid
and

addressed

succeeding

memory

data

Available

registers

corresponding

Set

parity

becomes

error

locations,
Set remains

main memory

locations

stored

and

the

data

Set.

are

location

successfully

the

Least

Available

occurs

while

reading

the
<corresponding Valid
the Next Available Set.

locaded,

Available Set

the

set

Set.

one

Bit

the

cleared

memory

and

the

NOTE

The

KTJ1l1l-B

Since

the

DMA

Cache

DMA

Hit

The

the

accesses

has

error

location

device

indications

then

indication.
is

will

i1f

not

stored

receive

and

that memory

occurred,

place:

parity

Cache,

error

specifically

take

memory

DMA

parity

contains

offending

any

when

location.

the

following

operations

Set

(A-D)

whose

the
physical
whose contents

Tag

caused

the

address index field, selects
is gated onto the UNIBUS.

hit,

along

data

with

If the Index Field equals 7 (the last data register in
the
set has been read), the corresponding Valid Bit is cleared,
and that data register set becomes the Next Available Set.

the

set,

Index

but

Field

the

data

does

not

equal

Set

the

becomes

Valid

the

Bit

Least

remains

Available

Set.

3.13
The

UNIBUS
UNIBUS

memory.
convert
22-bit

MAPPING
Map

the

interface

between

line, BBS7 L.
The assertion of BBS7
decoding and selects the I/0O Page.
_UNIBUS

the

UNIBUS

and

PMI

It responds as a slave to UNIBUS signals and is used to
18-bit UNIBUS addresses to 22-bit memory addresses.
The
memory
address
1is
accompanied
by an additional signal

address

space

always reference the
space can be used by
(See Figure 3-33.)

256

L disables

which

I/0 page.
The
the UNIBUS map

the

top

PMI

8KB

address

addresses

lower 248KB of UNIBUS address
to reference physical memory.

FUNCTIONAL

DESCRIPTION

7177 777
I/0 PAGE .

(8K BYTES)

760 000

757 777
TO UNIBUS MAP

(248K BYTES)
000 000

18-BIT UNIBUS ADDRESSES

FIGURE

The

3-33

UNIBUS

ADDRESS

SPACE

UNIBUS Map can be programmed, via Memory Management
Register
(MMR3) bit 05, to run with relocation enabled or relocation

Three

disabled.

If relocation is disabled (MMR§ bit

ones,

appends
address,
address

memory

asserted,

four
thus
bits

0),

the

UNIBUS

leading
zeros
(address bits 21-18) to the
producing
the
22-bit
memory
address.
17-00
are identical to UNIBUS address bits

address

bits

selecting

the

17-13

are

I/0

Page.

all

the

If relocation is enabled (MMR3
bit
05
=
1),
dccodes
UNIBUS
address
bits
17-13 to select
register pairs (corresponding to octal codes 00

BBS7

Map

UNIBUS
Memory
17-00.

signal

1is

the
UNIBUS
Map
one of 31 mapping
thru
36).
The

content
of the selected mapping register pair is added to UNIBUS
address bits 12-00 to produce
the
memory
address.
If
UNIBUS
address
bits 17-13 are all ones (octal code 37), the I/O Page is
selected.
The BBS7 L signal to the memory
1is
asserted,
memory
address bits 17-00 are identical to UNIBUS address bits 17-00 and
memory address bits 21-18 are not asserted.

3.13.1
The
31

UNIBUS

Mapping

Registers

UNIBUS Map contains
are
actually
used

32 mapping register pairs of
for address relocation.
See

‘and 3-35, and Table 3-26.
The
mapping
accessed directly or indirectly:

which
Figures

pairs

may
|

only
3-34

FUNCTIONAL

DESCRIPTION

Direct
Access
The
mapping
registers
are
accessed
individually
through
their
I/O
Page
addresses.
Each
mapping register pair consists of a
Hi
Address
Register,
which
contains
relocation
address
bits
21-16
and a Lo
Address Register, which contains
relocation
address
bits
15-01.

Indirect Access
UNIBUS
address

When
bits

UNIBUS

Map
Relocation
1is
enabled,
select the appropriate mapping

17-13

to be

used

relocating

the

18-bit

UNIBUS

address.
1%

l 0

l
]
.

RELOCATION ADDRESS

BITS 21-16

FIGURE

HI-ADDRESS

3-34

RELOCATION ADDRESS

B8ITS 15-01

FIGURE

3-35 LO-ADDRESS

TABLE 3-26 UNIBUS MAP REGISTER PAIRS

I/0 PAGE ADDRESSES
HI REGISTER
LO REGISTER

UNIBUS ADDRESSES
MAPPED VIA REGISTER
PAIR

0
1
2
3

17
17
17
17

770
770
770
770

200
204
210
214

17
17
17
17

770
770
770
770

202
206
212
216

000
020
040
060

000
000
000
000

017
037
057
077

777
777
777
777

4
5
6
7

17
17
17
17

770
770
770
770

220
224
230
234

17
17
17
17

770
770
770
770

222
226
232
236

100
120
140
160

000
000
000
000

117
137
157
177

777
777
777
777

10
11
12
13

17
17
17
17

770 240
770 244
770 250
770. 254

17
17
17
17

770
770
770
770

242
246
252
286

200
220
240
260

000
000
000
000

- 217
- 237
- 257
- 277

777
777
777
777

3-66

FUNCTIONAL

TABLE

3-26

DESCRIPTION

(Cont)

770

260

770

262

300

000

317

777

15
16

17
17

770
770

264
270

17
17

770
770

266
272

320
340

000
000

337
357

777
777

770

274

770

276

360

000

377

777

20
21

770

300

770

302

400

000

417

777

770

304

770

306

420

000

437

777

22
23

17 770 310
17 770 314

17 770
17 770

312
316

440 000 - 457
460 000 - 477

777
777

24
25
26
27

17
17
17
17

770
770
770
770

320
324
330
334

17
17
17
17

770 322
770 326
770 332
770 336

500 000
520 000
540 000
560 000

30
31
32
33

17
17
17
17

770
770
770
770

340
344
350
354

17
17
17
17

770
770
770
770

342
346
352
356

600
620
640
660

34
35
36
37

17
17
17
17

770
770
770
770

360
364
370
374

17
17
17
17

770
770
770
770

362
366
372
376

Can

3.13.2
The

read

or written

Optional

ability
to

into,

UNIBUS

Memory

install

UNIBUS

but

517
537
557
577

777
777
777
777

000 000 000 000 -

617
637
657
677

777
777
777
777

700 000 - 717 777
720 000 - 737 777
740 000 - 757 777
1I/0 Page (No Relocation)

not

Memory

used

instead

for mapping.

of,

to
PMI memory, has been preserved.
However, it differs
from previous implementations.
UNIBUS address space is
to
UNIBUS
memory
below the I/0 page
Those

UNIBUS

be
used
accesses

in 8K byte segments, starting with
and proceeding downward.

address

segments

to access PMI
UNIBUS memory,

assigned

UNIBUS

the

Memory

addition

somewhat
assigned
segment

can

memory via the I/0 Map.
Whenever the
the KTJ11l-B will disahle
PMT
memorv

not

CPU
bv

The KDJ11-B CPU Module does not
the PMI UBMEM signal.
asserting
is
cache UNIBUS Memory, because it disables its cache when UBMEM

asserted.

FUNCTIONAL

DESCRIPTION

NOTE

18-bit UNIBUS
PDP-11/84.

memories

ONLY

are

supported

the

The
UNIBUS
address
range
of
each
UNIBUS
memory
module
1is
determined
by
jumpers
or switches on that module.
The KTJ11l-B
Memory Configuration Register
(KMCR),
described
1in
subsection
3.13.3,
must
accurately
reflect the placement of UNIBUS memory
within the system.
The KMCR register is cleared by the assertion of
DC
loaded
by
the KDJ1l1l-B boot and diagnostic programs
by the KDJ11-B EEPROM Configuration Data.
KMCR <04:00> specify
0
to
31,
assigned

the
to

LO
and
1is
as specified

number of 8K byte address segments, from
UNIBUS Memory.
KMCR <05> specifies the

location of the UNIBUS Memory from the viewpoint of the CPU.
See
Table
3-28.
1If KMCR <05> is clear (22-bit Mode), the top UNIBUS

memory
mode),

location is 17 757 776.
If
KMCR
<05>
1is
the top UNIBUS memory location is 757 776,

If the system has
cleared.
In this
l.

PMI memory,

locations
2.

All

no UNIBUS memory,
configuration:

then

CPU,

seen

from 00

UNIBUS

000

the

000

DMA devices

KMCR

(18-bit

<05:00> must

resides

up to as high as

access

set

PMI memory

1in

all

contiguous

757

thru

777.

the

UNIBUS

Map.

If the system contains UNIBUS memory only,
all be set.
In this configuration:
l.

UNIBUS memory,

locations
2.

seen

from address

the

CPU,

then

resides

0 up to as high as 00

UNIBUS memory, as seen by all UNIBUS DMA
in
contiguous
1locations
from
address
address 757 777.

The UNIBUS Map
Register
Pairs
read-write
registers,
but
the

does

not

respond

KMCR

<05:00> must

1in

contiguous

757

777.

devices,
up to as

resides
high as

are
still
UNIBUS Map

to the UNIBUS address

accessible
as
is disabled and
range
0
thru
757

777.

I1f

the

KMCR

system contains

<05>

UNIBUS

clear

(22-bit

memory,

segments

both

assigned

PMI

memory

mode),

seen

and UNIBUS memory,

then:

the

CPU,

to UNIBUS Memory
3-68

and

falls

within

by KMCR

the

8K byte

<04:00>.

UNIBUS

FUNCTIONAL DESCRIPTION
8K
downward starting with
Memory addresses are assigned
the
lists
Table 3-28
byte segment 17 740 000 - 17 757 777.
KMCR bit
wvarious
the
by
UNIBUS Address space allocated
:

codes.

1in -contiguous
resides
CPU,
the
by
as seen
PMI memory,
locations from address 00 000 000 up to as high as the last
KTJ11-B
The
memory.
to UNIBUS
assigned
not
address
the response of PMI memory residing
disables
specifically
in locations assigned to UNIBUS memory by asserting the PMI
(PUBMEM).

line

UNIBUS Memory

section
the
The UNIBUS DMA devices access PMI memory thru
assigned
been
not
has
which
space
address
of the UNIBUS Map
UNIBUS
Each 8K byte segment assigned to
to UNIBUS memory.
Pair.
Register
Map
UNIBUS
Memory, disable its corresponding
Disabled
pairs
are
still
accessible
as
read-write
registers,
but
the
UNIBUS
Map does not respond to their
assigned

address

UNIBUS

space.

The UNIBUS DMA devices access UNIBUS Memory
directly
with
DMA Address XXX XXX accesses the same
address.
18-bit
an
UNIBUS Memory location accessed by CPU address 17 XXX XXX,

NOTE

The KTJ1l-B places no
register
pairs
which
<04:00>.

However,

1limit
on
the
number
of
may
be
disabled by KMCR

typical

system

software

requires
a
minimum
of 5 or 6 register pairs to
allow DMA devices to access
PMI
memory
with
a

moderate degree

the

KMCR
1.

system contains

<05>

set

efficiency.

both PMI memory and UNIBUS memory,

(18-bit mode),

and

1if

then:

UNIBUS memory, as seen by the CPU, falls within the 8K byte
segments assigned to UNIBUS Memory by KMCR <04:00>.
UNIBUS
Memory addresses are assigned
downward
starting
with
8K
byte
segment
740
000
757
777.
Table 3-27 lists the
UNIBUS Address

space

allocated

the

codes.
PMI

memory

locations

various

KMCR

bit

.
as

seen

from

address

not

disables

the

address

assigned

response

CPU,

000

PMI

assigned to UNIBUS
memory
Memory line (PUBMEM).

000

resides

UNIBUS

memory
by

to as

1in

high

memory.

The

residing

asserting

contiguous

the

locaPMI

last

KTJ11-B

tions
UNIBUS

FUNCTIONAL

DESCRIPTION

PMI

memory,

seen

the

UNIBUS

DMA

devices,

resides

contiguous
locations from address 000 000 up to as high as
the last address not assigned to
UNIBUS
memory.
Because
this
1is
an 18-bit system, system software does not enable
the

UNIBUS

Map.

The UNIBUS DMA devices access UNIBUS Memory
the same 18-bit addresses used by the CPU.
TABLE

3-27

SELECTION

directly,

UNIBUS

MEMORY

Memory

UNIBUS

Memory

Size

Address

Range

UNIBUS

KMCR

Bits

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

OKB8KB
16KB
24KB
32KB
40KB
48KB
56KB

XX 740
XX 720
XX 700
XX 660
XX 640
XX 620
XX 600

000
000
000
000
000
000
000

0
0
0
0

0
0
1
1

0
1
0
1

64KB
72KB
8 OKB
88KB

XX 560
XX 540
XX 520
XX 500

000 - XX
000 - XX
000 - XX
000 - XX

0
0
0
0

1
1
1
1
1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

96KB
104KB
112KB
120KB

XX 460
XX 440
XX 420
XX 400

000 - XX 757
000 - XX 757
000 - XX 757
000 - XX 757

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

128KB
136KB
144KB
152KB
160KB
168KB
XX6KB
184KB

XX
XX
XX
XX
XX
XX
XX
XX

1
1
1
1
1

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

192KB
200KB
208KB
216KB
224KB

XX 160
XX 140
XX 120
XX 100
XX 060

000
000
000
000
000

1
1
1

1
1

1
0

232KB
240KB

XX 040
XX 020

000
000

0
1
1

24 8KB

000

- XX 757
- XX 757
- XX 757
- XX 757
- XX 757
- XX 757
- XX 757

360 000 - XX
340 000 - XX
320 000 - XX
300 000 - XX
260 000 - XX
240 000 - XX
220 000 - XX
200 000 - XX

000

757
757
757
757

777
777
777
777
777
777
777
777
777
777
777
777
777
777
777

757
757
757
757
757
757
757
757

777
777
777
777
777
777
777
777

XX
XX
XX
XX
XX

757
757
757
757
757

777
777
777
777
777

XX
XX

757
757

757

777
777
777

FUNCTIONAL DESCRIPTION
NOTE

XX = 17 for KMCR 05> = "Q0"
for KMCR <05> = "1" (18-bit

3.13.3

Memory

The

KTJ11l-B

777

734,

Configuration

Memory
allows

(22-bit mode)
mode)

Configuration

(KMCR),

the

Boot

Diagnostic

KDJ11l-B

and

address

programs

configure the KTJ1l1l-B for the distribution
of
UNIBUS
and
Main
memory
within
the
system.
Additional KMCR bits allow the DMA
Cache to be enabled and disabled, provide
diagnostic
status
of
the
Read
Buffer
and
provide
information on the system reboot
status.
Figure 3-36 shows the register format,
and
Table
3-28
contains the bit descriptions.

DMA CACHE
STATUS BITS

SELECT STATUS =
RBT PLS

CA ENB
18-8IT MODE

UNIBUS MEMORY SIZE

FIGURE

TABLE

BIT(S)

15:09

3-28

3-36

MEMORY

DMA

(R/W)

BIT

(KMCR)

DESCRIPTIONS

FUNCTION

Cache
Bits

(RO)

Status

CONFIGURATION

NAME

Status

MEMORY

These
DMA

seven

Cache.

bits
KMCR

reflect
<15>

the
DMA

status

This

bit

(See

Tables

selects

3-29

the

content

and

3-30.)

the

Hit.
depends upon

The content of KMCR <14:09>
value of the value of the KMCR
Select).
Select

Cache

<08>

KMCR

the
(Status

<15-09>.

FUNCTIONAL

DESCRIPTION

TABLE

3-28

Reboot Pulse

This bit

(RBT

which

PLS)

(RO)

(Cont)

is set by the front panei reboot pulse

also

Down/Power

the

Down/Power

Cache

Enable

(CA ENB)
(R/W)

This

18-Bit

RBT

Cycle.

Mode

When

(R/W)

when

UNIBUS
Size

Power

not

LO during

the

cycle

initiated

reboot pulse, but
DC LO assertion.
bit,

PLS

set,

enables

cleared

KTJ11-B
the

front

cleared

the

DMA

this

bit

set,

the

CPU

Memory only when address bits
When

Power

any

Cache.

assertion

LO.

this

bit

clear,

Memory

they

can

access

<21:18>

can

UNIBUS

= 00.

UNIBUS
memory if address bits <21:18> = 17. This bit
is cleared by the
assertion of DC LO. Write
access to this bit is disabled when DCSR <08>

access

is clear.

(Diagnostic Mode)

04:00

KTJ1l1-B

When CA ENB i1s clear, the DMA Cache
is disabled. CA ENB is cleared by the
of

assertion

panel
other
N6

generates

If the system contains main memory only (no
UNIBUS memory), these five bits, as well as
KMCR <05>, must be cleared. If the system

contains UNIBUS memory only (no main memory);
then KMCR <05:00> must be set.
If the system contains both main memory and
UNIBUS memory, KMCR <04:00> indicate the
number of 8K byte address segments assigned to
UNIBUS memory. As described in section 3.4,
UNIBUS memory is assigned downward, starting
with the segment below the I/0 Page. These bits
are cleared by assertion of DC LO. Write access

to these bits
(Diagnostic

disabled when DCSR <08>

Mode)

clear.

If KMCR <8> (Status Select = 0, then KMCR <15-08> contain the
Cache
Hit
bit,
the
2-bit Most Recently Used Set code, and

four Valid bits.
contains the bit

Figure 3-37 shows
descriptions.

the

field

format;

Table

DMA
the
3-29

FUNCTIONAL
12

DESCRIPTION

DMA CACHE HIT ———l
UNUSED

SET A VALID
SET

B VALID

SET C VALID
SET D VALID

STATUS

FIGURE

TABLE

DMA

SELECT

3-37

3-29

Cache

STATUS

This

bit

SELECT

SELECT=0

FIELD

updated

FORMAT

DESCRIPTION

during

all

writes

to main

Hit

memory, and all reads from main memory. It 1is
set 1f a cache hit is detected, and cleared
if a cache miss is detected. This bit is
cleared when KMCR <6> is clear.

14-13

Unused

Always

Set

Reflects the current status
corresponding to Set A. The
when KMCR <6> is clear.

of the
bit is

Valid

Reflects

the

Valid

bit

Set

A Valid

B Valid

read

the

corresponding
when KMCR <6>
10

Set

D Valid

KMCR

well

the

Valid

zero.

current

status

to Set B.
1is clear.

The

of the
bit ic

Valid

Reflects

status

the

Valid

bit

the

current

Set

when

clear.

KMCR

<6>

<8>

The

bit

cleared

Reflects the current status
corresponding to Set C. The
when KMCR <6> 1s clear.

corresponding

bit

cleared

bit
cleared

bit

cleared

= 1], then KMCR <15-08> contain the DMA Cache Hit
bit
the six bits which determine the relative availability
four sets (i.e., A, B, C, D).

3-73

FUNCTIONAL

When

DESCRIPTION

<6>

(CA

the
six
Available

KMCR

Set
Set,

Availability
bits
followed by Set B,

When

KMCR

<6>

hit

1is

then

DMA

for

that

cache

one

the

Similarly,

following

them
read

DMA

cache

are
set.
Set C, and
is

sets

the
for

during

data

cache

the

registers

then

and

the

DMA

cache

DMA write

Set.

sets

becomes

miss,

disabled,

a CPU or

Availble

one

set

Set
Set D.

enabled.

that

set's

DMA

the

cache

detected

memory,

Available

DMA

hit

Set.

during

Least

are

that

set

DMA

Available

successfully

becomes

the

Set.

Figure 3-38 shows
descriptions.

A TOPS

the

becomes

from main

Least

clear,

set

read
loaded

set,

detected

memory,
If

ENB)

the

field

format;

Table

3-30

contains

the

bit

TOPS
C

B TOPS

C TOPS

STATUS SELECT

FIGURE

TABLE

DMA

Cache

3-38

3-30

Hit

SELECT

STATUS

SELECT STATUS

This

bit

memory,

is
if

is
and

= 1

updated
DMA

all

FIELD

FORMAT

FIELD DESCRIPTION

during
reads

all
from

writes to main
main memory. It

set if a cache hit is detected, and cleared
a cache miss is detected. The bit is cleared

when

KMCR

<6>

clear.

FUNCTIONAL

TABLE

Tops

(ATPSB)

3-30

DESCRIPTION

(Cont)

If ATPSB is set, Set A is more available than
Set B. If ATPSB is clear, Set B is more available

than Set A.

ATPSB

set when KMCR

<6>

clear,

when Set A becomes the Next Availabde Set,
and when Set B becomes the Least Available Set.
ATPSB is cleared when Set B becomes the Next
Available Set, and when Set A becomes the Least
Available Set.
13

A Tops

(ATPSC)

If ATPSC is set, Set A is more available than
Set C. If ATPSC is clear, Set C is more availlable

than
when

Set A. ATPSC is set when KMCR <6> is clear,
Set A becomes the Next Available Set,
and when Set C becomes the Least Available Set.

ATPSC

A Tops

(ATPSD)

Available
Available

cleared when Set C becomes the Next
Set, and when Set A becomes the Least
Set.

ATPSD

Set

and when
ATPSD is

Tops

available

(BTPSC)

BTPSC

becomes

the

Set

<6>

Available

Set,
Set.
is

and

set,

when

Set

A becomes

available
is clear,

Set,

becomes

the

available

Set C. If BTPSC 1s clear, Set C is
than Set B. BTPSC is set when KMCR
when

than

Set D becomes the Least Available Set.
cleared when Set D becomes the Next

Available
Available
B

Set

Set D. If ATPSD is clear, Set D is
than Set A. ATPSD is set when KMCR
when

set,

Least

than

more available
<6> is clear,

Available

Set,

and when Set C becomes the Least Available Set.
BTPSC is cleared when Set C becomes the Next
Available Set, and when Set B becomes the Least
Available

Tops

(BTPSD)

BTPSD

Set

Set.
is

set,

BTPSD

Set

clear,

Set

available

than

available

than Set B. BTPSD is set when KMCR <6> is clear,
when Set B becomes the Next Available Set,
and when Set D becomes the Least Available Set.
BTPSD is cleared when Set D becomes the Next
Available Set, and when Set B becomes the Least
Available Set.

Tops

(CTPSD)

CTPSD

Set

set,

CTPSD

Set
is

than

Set

CTPSD

when

Set

becomes

and when
CTPSD is
Available
Available

clear,

more
Set

set when

available
D

KMCR

<6>

than
available

clear,

the Next Available Set,
Set D becomes the Least Available Set.
cleared when Set D becomes the Next
Set,

Set.

and

when

Set

becomes

the

Least

FUNCTIONAL

DESCRIPTION

KTJ11-B

Diagnostic

and

REGISTERS

CONFIGURATION

AND

DIAGNOSTIC

KTJ11-B

3.14

Configuration

Registers

are

used

with

diagnostic programs to check out the KTJ1ll-B, both in
Diagnostic
Mode,
with the UNIBUS disabled.
The KDJ11l-B Boot and -Diagnostic
Programs also use
these
registers
to
enable
or
disable
the
KTJ11-B

DMA

UNIBUS

memory.

-Cache

and

specify

the

presence

and

location

When operating in diagnostic mode, the KTJ1ll-B can be
to
perform
diagnostic NPR cycles which test out its
data paths along with the UNIBUS Map.

3.14.1

Diagnostic

Controller

Status

programmed
address and

Diagnostic Programs use the Diagnostic Controller Status Register
(DCSR),
at
address
17
777
730,
to
enter
and
to exit from
Diagnostic Mode, to select the
source
of
the
Diagnostic
Data
Register
(DDR)
and
to perform Diagnostic NPR cycles which test
the UNIBUS Map along with the KTJ1l1l-B
address
and
data
paths.
Figure
3-39
shows
the register format; Table 3-31 contains the
bit descriptions.
15

I
L

DNXM ERR

DATI GO
DIAGNOSTIC

MODE —

DNPR DONE

BOOT ROM DtS

DOR SELECT

FIGURE 3-39 DIAGNOSTIC CONTROLLER STATUS REGISTER FORMAT
TABLE

3-31

DIAGNOSTIC

DNXM ERR

CONTROLLER STATUS

Diagnostic
This

bit

DESCRIPTIONS

Non-Existant Memory Error
cleared

the

start

diagnostic NPR cycle and set if there is a
non-existant memory timeout during that cycle.
DNXM ERR is also cleared when DCSR <08>
(Diagnostic

Mode)

cleared.

FUNCTIONAL

TABLE

(Cont)

Unused

These bits always

Diagnostic

When

Mode

and the KTJ1l1l-B is configured for Diagnostic
Mode. When this bit is clear, the UNIBUS is
enabled and the KTJ1l1l-B is configured for normal
operation. This bit is set by the assertion of

(R/W)

3-31

DESCRIPTION

DNPR

Done

this

bit

read as

set,

Zero.

the

UNIBUS

disabled

LO.

This

bit

NPR

cycles

write

set

when

pending.

DCSR with

there
DNPR

"1"

are

Done

no
is

bit

Diagnostic
cleared

00,

and

any

write to the Diagnostic Data Register (DDR).
DNPR Done is set by Bus INIT or by completion
of a Diagnostic NPR Cycle.
06:04

Unused

These

Boot

When this

ROM

Disable

bits

always

bit

read

set,

boot ROM at addresses

zero.

response of

177773000 -

the UBA

177773776

is disabled, allowing operation of any
external ROM which uses those addresses

(R/W)

the

UNIBUS.
When this bit is cleared, the UBA boot
ROM responds to those
addresses. This bit is
cleared by the assertion of DC LO.
02:01

DDR

Select

(R/W)

These two bits select the contents of
Diagnostic Data Register during read

operations.
Bus

DATI

(WO)

3.14.2

Diagnostic

The

DDR Select

bits

are

the

cleared

INIT.

Writing
a "1" into
Diagnostic Data-In

this bit sets
NPR Cycle and

up a
clears

DCSR

bit 07. The NPR cycle is actually initiated by
the next CPU read cycle which accesses the PMI.
That cycle provides the address used in the NPR
cycle. The data fetched during that cycle is
loaded into the Diagnostic Data Register (DDR).

Data

"Diagnostic Programs use the Diagnostic Data
Register
(DDR),
at
address
17
777 732, along with the Diagnostic Controller Status
Register (DCSR), to perform Diagnostic NPR cycles and to
monitor
the state of various UNIBUS data, .address and control signals.
3-77

FUNCTIONAL

DESCRIPTION

Diagnostic

the

NPR

KTJ1ll-B

cycles

test

address

and

out

cycles, DCSR <02:01> are set
Diagnostic
NPR
Register.
Cycle,

the

Diagnostic

which

can

then

NPR

read

the

data

UNIBUS

Map

paths.

equal
to
Following

along

many

Diagnostic

NPR

thus
selecting
Diagnostic Data-In

the
NPR

During
0,
a

contains

the

with

transferred

through

data

the DDR.
Diagnostic programs set
up a Diagnostic Data-Out NPR cycle by
writing
the
data
to
be
transferred into the DDR.
Figure 3-40 shows the register format;
Table 3-32 contains the bit descriptions.
All

DDR

access

the

information
accessed
on DCSR <02:01>.

writes

the

during

read

l (V7

0/1

o/1 | on

0/1

Diagnostic

operations

NPR

from

the

DDR

c
P8

SSYN
MSYN

FIGURE 3-40 DIAGNOSTIC DATA REGISTER FORMAT
Contents of the DDR when Select Code = 11

TABLE

3-32 DIAGNOSTIC DATA REGISTER CONTENT DESCRIPTIONS

DDR

SELECT

Bit

BITS

Bit

CONTENT OF

DIAGNOSTIC DATA REGISTER

Diagnostic NPR Register

UNIBUS Data Lines D15-00

UNIBUS Address Lines Al5-00*

UNIBUS Address Lines Al7-16
and various UNIBUS Control Lines

* NOTE: Asserted address

line Al6 during the

UNIBUS Address Lines read
a parity error abort.
3-78

operation,

Diagnostic

may

cause

The

depends

FUNCTIONAL

3.14.3

The

Diagnostic

DATI

NPR

execution procedure

Cycles

for diagnostic

The KTJ11l-B must be running in

Select
2.

The

bits

(DCSR

diagnostic

DESCRIPTION

02-01)

DATI cycles

Diagnostic

mode

bit

follows:

with

DDR

program writes

into

DCSR

00,

NOTE

this

PMI

bus

The

point,

I/0

memory

write

read

access

access,
results

oOr
in

diagnostic

target
Al7-00

The

KTJ11-B

storing

program writes the test
data
pattern
into
memory
1location.
The KTJ11l-B latches address
of this cycle.

then

the

address

Map,
may
may

UNIBUS

read

timeout.

the
bits

The

any

page

using

executes

fetched
used

the

its

data

diagnostic

the

in this cycle
latched 18-bit

DATI

Diagnostic

NPR

Data

in produced
by
the
address.
The 18-bit

be used directly (UNIBUS Map
be
relocated
to produce a

cycle,

Relocation disabled) or it
22-bit address (UNIBUS Map

enabled).
The

diagnostic

3.14.4
The

Diagnostic

execution

program verifies

contains

DATO

procedure

the

correct

that

the

Diagnostic

Data

data.

NPR Cycles
for

diagnostic

DATO

NPR

<cycles

1is

follows:

The

KTJ11-B must

running

Diagnostic

mode.

diagnostic program loads the data
for
the
NPR
cycle
into
the
Diagnostic Data register.
Loading this register
primes the KTJ11l-B for a diagnostic NPR cycle.

NOTE

this

non

bus

PMI

point,
I/0

any

page

timeout.

UNIBUS
read

memory

read

write

access

access,
results

oOr
in

FUNCTIONAL

DESCRIPTION

The KTJ11l-B latches
address
bits
Al7-00
from
KDJ11-B external write to memory address space.
The

KTJ1l1l-B

using

the

then

data

executes.
its diagnostic

stored

the

Diagnostic

address.used in this cycle is produced
using the latched 18-bit address.
The
The

diagnostic

program

verifies

that

DATO

Data

the

NPR

cycle,

The

UNIBUS

Map,

target

memory

location
contains the correct data.
If it wishes to check
the
Diagnostic
Data
register,
it
must
do
so
before
performing
an
external
write operation which would alter
the contents of that register.

CHAPTER

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

INTRODUCTION

4.1

The CPU contains two ROMs (read only memories) which
stores
the
programs (ROM code) used to test the CPU, UBA and memory at power
up or restart and to allow the starting of the user's software on
various devices.
The data in the ROMs is permanent and cannot be
changed

the

user.

The
CPU
also
contains
an
EEPROM
(electrically
eraseable
programmable
read
only
memory).
The
EEPROM 1is used to store
parameters which the ROM program uses to determine
what
actions
are
to
be taken at power up or restart, and how various CPU and
UBA registers

Parameters
program

the

also be

used

require

can

are

the user

The diagnostic
each

time

selected

- complete,
taken

EEPROM
ROM

can

called

remove

store

system

the

changed

under

mode.

the CPU or UBA

1is

the

control

Setup mode

modules.

The

bootstrap programs.

is automatically started
powered

front panel.

ROM

Setup

customer

parameters

parameters
by

configured.

ROM program

the

RESTART switch on
tests

The

1in

the

restarted

ROM

EEPROM determine

the

CPU

EEPROM

by use

will

After

what

a
not

program

EEPROM.

does

testing

action

the

run
is

program.

In a typical example the
ROM
program
automatically
starts
a program from the user's disk or tape.
This

1loads
and
is commonly

referred

to
the

to as booting a program and this mode will
be
referred
as automatic boot mode.
After the user's software is started
ROM program will not be entered again
until
the
system
is

powered

cases

some

restarted.

after

testing

complete
L

4-1

the

ROM

program

enters

BOOTSTRAP AND

mode

which

way

terminal.

final

the

will

EEPROM

select

commands

mode

the

tests

determine

entered

after

certain

registers

the

ROM program enters

the

console

anytime
done by

the
the

software

EEPROM.

terminal

This

during

through

cases

the

action

refered

system

what

entered

the

selections

or
is

user

PROGRAMMING

before

some

the

ROM

keyboard

configuration of

module

'In

allows
of

This

parameters

general

DIAGNOSTIC

testing

Dialog
to

the

mode.

The

run,

the

complete

the

taken

console

and

the

CPU°~ and

UBA

started.

Dialog
occurs

testing,

mode
if

the

regardless
user

boot

types

of
CTRL

sequence,

FORCE DIALOG switch is turned on.
Generally, this
user to allow changes to be made to the parameters

in
not

the
EEPROM,
or to
previously selected

The

FORCE

DIALOG

allow the user
by the EEPROM.

switch

allows

to boot

wuser

the

device

which was

unconditionally

override the selections in the EEPROM.
This override is provided
because there are certain modes which cannot be
aborted
because
the ROM program executes the modes too gquickly and is not able to
monitor the console terminal for a CTRL C typed by the user.

NOTE

All

user

until

input

the

message

ignored

"Testing
typed

out

1in
by

the

console

progress the

ROM

keyboard

Please

wait"

code.

The description of the commands for the ROM code assume that
the
EPROMs
1installed
are at Version 7.0 (V7.0).
Earlier PDP-11/84s
contain EPROMS with V6.0 ROM code.
The version of the
ROM
code
is typed out each time Setup mode is enetred from Dialog mode and
is displayed at the upper right corner of the
printout.
It
1is
not
necessary to remove the CPU module to determine the ROM code
version number.
The following lists the
ROM
part
numbers
and
version numbers.
Socket

Location

(M8190)

CPU

Part

Number

V7.0

Part

Number V6.0

E116

(low byte)

23-116E5-00

23-077E5-00

E117

(high

23-117E5-00

23-078E5-00

byte)

Differences between V7.0 and
Appendix

V6.0

ROM

code

are

described

The following illustrations are
examples
of
messages
program
would
print out on the console terminal during
or

1in

restarting

the

CPU.
”

the
ROM
power up

BOOTSTRAP

Figure

4-1

automatic
and

was

shows

boot

mode.

booted

example

from

device

Testing

progress

Memory

Size

Step memory
Step 1 2 3 4

Starting

system

messages

that

ROM

PROGRAMMING

typical

system

booting

case

user's

software

unit

the

1in

RT11

DUO"

come

Please

Bytes

wait

boot

from

DUO

V05.0

FIGURE

The

DIAGNOSTIC

test
56

automatic

(S)

this

1024

Starting

RT-11FB

AND

4-1

AUTOMATIC

the

BOOT

line

MODE

"Starting

EXAMPLE

system

from

from
the
software
booted
and
are
not
generated
by the
program.
At this point the ROM program is not executing and
actions are determined by the user's software.

ROM
all

Figure

up,

4-2

running

The

ROM

occur

shows

the

example

program waits

diagnostics

for

the

user

typical

system

and

then

entering

select

what

powering
dialog

action

next.

Testing

Memory

Size

progress
is

1024

Step memory test
Step 1 2 3 456

Commands
Type

FIGURE

4.2

internal

DIALOG

Dialog mode

MODE

are

Help,

command

4-2

the

Please

Bytes

press

POWERUP

List,
the

DESCRIPTIONS

user

wait

Boot,

then

SYSTEM

COMMAND

allows

to:

Setup,
RETURN

DIALOG

Map

and

Test.

key:

MODE

EXAMPLE

mode.

BOOTSTRAP AND DIAGNOSTIC

ROM

PROGRAMMING

Boot

device

List

boot

Execute ROM resident tests

Provide

Enter

programs

a map of

available

for

all memory and

the

user

I/0 page

locations

setup mode.

When dialog mode is
entered
the
ROM
program
prints
out
message shown in Figure 4-3 at the console terminal and waits
the

user

select

Commands

Type

are

the
for

command.

Help,

a command

Boot,

List,

then press

FIGURE

4-3

the

DIALOG

Setup,

Map

and

Test.

RETURN Kkey:

MODE

COMMANDS

When dialog mode is entered the user has six commands
to
choose
from.
The
six commands are listed in the command line for user
convenience.
The user may obtain a
brief
description
of
each
command
by
typing
H
followed by pressing the RETURN key or by
typing

only.

All of the commands may be executed
by
typing
only
the
first
For
the command followed by pressing the RETURN key.
of
letter
example, the Map command can be invoked by typing either M or
Ma
or
Map
followed by pressing the RETURN key.
On input all lower
case letters are converted to upper case and leading
spaces
and
tabs are

ignored.

Use the DELETE key to delete the previous
character
typed.
If
the
terminal
type selection in the EEPROM is video the ROM code
will erase the previous character on the screen when
the
DELETE
key
1is depressed.
1If the terminal type is hardcopy the ROM code
will use slashes "/" to identify
all
deleted
characters.
The
user
may
at
any
time delete the entire command line by typing
CONTROL

(CTRL)

NOTE

Typing a CTRL U
depressing
the
depressing

the

CTRL
(or
CTRL
key

CTRL U

(or

R)
R)

while
Kkey.

performed

simultaneously

The user can also type CTRL R which will retype the command line.
4-4

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
CTRL

1is

normally

used

when the

terminal

type

hardcopy to

clear up command lines where the DELETE key has been
used.
For
both CTRL R and CTRL U the ROM code will print out a short prompt
first.
Figure 4-4 shows
an
example
of
CTRL
U
being
typed.
Neither
CTRL
U or CTRL R is echoed by the ROM code.
Figure 4-5
shows an example of CTPL R use.
NOTE

All

user

inputs

the

following

examples

are

examples

and

underlined.

The

RETURN

text

Commands
Type

key

are

Help,

command

KDJ11-B

Boot,

then

4-4

command

shows
is

Commands
Type

are

4-4

example

without
hardcopy.

Input

is
any

the

user

and

key:

Test.

DX5

CTRL U

clear

EXAMPLE

being

all

typed
1it.

List,

Setup,

Map

the

RETURN

key:

press

The

and
B

terminal

the

4-5

CTRL

characters

commands

types more

Commands
a

KDJ11-B

are

the
type

Test.

DX/X/Ul

than

would

CTRL

EXAMPLE

and

need

spaces.
more

characters

There

than

the

ROM

Help,

command

then

Boot,
press

List,
the

Setup,
RETURN

Map
key:

and

code

4-6

CTRL

EQUIVALENT

4-5

no cases

will

and wait for
seventeenth

Test.

EXAMPLE

1If

delete

12345678901234567

FIGURE

are

characters.

all
of
the
1input
and
retype
the KDJ11-B prompt
input.
Figure 4-6 shows an an example.
Typing
the
character is equivalent to typing CTRL U

Type

DUl

limited
of

Setup, Map
RETURN

CONTROL

Boot,

then

FIGURE

where

the

retyping

Help,

command

KDJ11-B

the

1line

selection

List,

press

FIGURE

Figure

specified

<CR>.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
The ROM code will

ignore any

character,
or
the
printable character
echoed

space

tab

second tab or space typed
in between.
All tabs are

typed

in a row without a
converted
to
and

spaces.

Note that these rules also apply generally at any
code

prior

accepting

input

from the

user.

time -the

ROM

If an invalid input is received an "invalid entry"
message
will
be
typed out and more input will be requested.
Figure 4-7 shows
an

example

invalid

entry.

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: MP <CR>

Invalid

entry

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key:

FIGURE 4-7 INVALID ENTRY EXAMPLE
Help Command

4.2.1

This command types out

description

brief

all

available

by either typing H <CR>, or by
executed
be
can
It
commands.
this
of
end
the
at
Dialog mode is restarted
only.
typing ?
being
command
Help
the
of
4-8 shows an example
Figure
command.
executed.

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: H <CR>
Command

Description

Help

Type

List
Setup

List boot programs
Enter Setup mode

Boot
Map

Test

this message

Load and start a program from a device
I/0 page

Map memory and

Continuous self test - Type CTRL C to exit

Commands are Help,

Type a command

Boot,

List,

then press

Setup, Map and Test.

the RETURN key:

FIGURE 4-8 HELP COMMAND DISPLAY
4-6

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
Command

4.2.2

Boot

This

command

name

is left off

allows a device

bootstrapped.

arguments are the device name and the unit number.

unit

number

the program will prompt

the

user

The

command

If the device

for

it.

the

1left off the program assumes that unit zero was

desired.
The unit number ranges from 0 0 to 255(10) depending on
the device and the boot program.
The device name is a one or two
letter mnemonic which describes the device.
In
most
cases
the
device
When

name

typing

two

the

letters.

Boot

command

the

user may

either

type

then
type the device name, unit number and optional
type B followed by a space and then type the
device
number

The

and

three

optional

/A Request
for

/0 The

unit

switches

the

used

with

the

boot

to type

command

in a

non standard

CSR

/U If the boot exists in the base ROM and also on the

number

UBA,

the

than

base

M9312

format when

octal

instead

decimal

ROM boot

and

use

the

using

When the user types
code
will
prompt
following message:
Enter device

this

point

programs

and

unit

switch

When

the

ROM

the
the

type

the

Boot command without
user for additional

name

and

the

user

unit number

typed

and

then

available

number"”

message

code

boot

from

the

UBA

module.

number
followed by / and the switches.
one switch, use only one slash.

boot

are:

unit

board

switches, or
name,
unit

controller.

greater

override

unit
than

and

for

numbers

The

<CR>

switches.

to allow the user

address

has

and

device

name

there

and

1is

an argument, the
information with

ROM code

retype

for

When

then press

the

wait

device

the

RETURN

would
"enter

ROM
the

key:

1list

the

device

name

the

first

selection.
searches

for

boot
program
with the same device name.
The ROM code looks for
matches in the following order.
The /U switch effectively
tells
the ROM code not to look for the device name in the EEPROM or the
CPU

ROM,

but

directly

the

lst

area

EEPROM

2nd

area

CPU

UBA

ROMs

present.

ROM

code

4-7

the

M9312

module

1if

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
3rd
4th

Note

that
boot

area
area

to search = UBA module
to search = M9312 module

present

that

since the EEPROM is always
searched
first,
any
boot
1is
loaded
1into
the EEPROM with the same device .name as a
in the CPU ROM will effectively
replace
that
boot.
This

would
allow
a
user
to
effectively
replace a
loading a boot in the EEPROM with the same name.

Table 4-1 describes how the
TABLE

USER

ROM code

4-1

INPUT

CPU

interprets user

ROM

CODE

ACTION

ROM

CODE

ACTION

ROM

boot

input.

s
Boot DLO
B DLl

Boot DLI

B DUS8

Boot

B DU10/0O

Boot DU unit 8

B DU10 /A
Address =
B DU

3/U

17760400

unit

Boot DUl0 with non standard
address of 17760400

CSR

Boot DU3 using UBA or M9312
rom boot instead of CPU ROM code.

DU1l1l/U0O

Boot DU unit number 9 using UBA or
M9312 ROM boot instead of CPU ROM.

Boot DU10

10:

B DU11/0/0

Invalid
entry

BDUO

cause

invalid

message

Invalid format. No space allowed
the

BDUO

format will

error

device

name

DU.

Invalid format. There must be a

space between the Boot command and
the

device

name.

Dbe
it will
the wunit number
after
If the user types a colon
B
of
name
device
letter
single
.s The
B DL1l:)
(e.g.,
ignored
the
on
devices
boot
DEC
non
implements a method of supporting
The letter B causes the ROM code to transfer control to
UNIBUS.
the address contained in location 17773024 of a ROM on the UNIBUS

if the address in location 17773024 is not odd.
4-8

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
and

When the CPU ROM passes control the CPU ROMs

UBA

the

ROMs

contain a unit number and Rl will
RO will
be disabled,
will
passed by the translation table.
was
contain 0 unless an address
the address in location 17773024 on the UNIBUS is odd the ROM
If

UNIBUS
the
If
program will type out an invalid device message.
to
17773000
from
addresses
all
to
respond
not
does
device
device
invalid
17773776 the ROM program will also type out an

message.

which
a module
The single letter device name of B is used when
a switch pack that responds at address 17773024 similar to a
has
Usually the starting address
M9312 module is used in the system.
would be set in the switch pack on the
desired
program
the
of
module.

Figure 4-9 shows shows an example of DL2 being booted
boot

command.

wusing

the

Commands are Help, Boot, List, Setup, Map and Test.
Type a command then press the RETURN key: B DL2 <CR>
Trying

DL2

Starting

system

RT-11FB

(S)

.SET

QUIE

from

V05.0l1

DATIME

Date?

[dd-mmm-yy]?
FIGURE

4.2.3
The

List

user

DL2

4-9

DL2

BOOT

EXAMPLE

Command

enters

this

command

typing

the

letter

<CR>.

This

command
will
print
out
a
1list of all available boot programs
found in the CPU ROM, the CPU EEPROM,
or
any
M9312
type
ROMs
located
on
the
UBA
or
an
M9312
module
if
present.
The
information listed is the
device
name,
allowable
unit
number
range,
tion.

some

source
of
the
boot program and
The device name is normally a
two

cases

always

input,

upper

unit

the

name may

letters

the

be
to

single

that

The

unit

1is

valid

short
letter

letter.

The

device descripmnemonic.
In

device

name

must

ROM program always

case.

numbers

from A

converts

number
for

range

all

particular

4-9

lower

the

case

allowable

boot

letters
range

program.

of
The

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
range varies
number range

from

0 to 255,
information is

range
limit
1is
0
ROMs 1s always left

depending on the device.
blank, the ROM code will

to 255.
blank.

The

unit

number

range

If the
assume

for M9312

unit

the
type

The source lists where the actual boot program is
located.
The
description
1is
intended
to
be
the name on the outside of the
device to be booted.
An example would be for a device name of DL
the description would be RLO2.
Dialog mode

restarted

the

completion

the

1list

command.

The
mnemonic
for
each ROM found on either the UBA or the M9312
will be checked against a list of mnemonics in the ROM code.
If
the mnemonic matches an item in this list the ROM code will print
out a description of that device.
If
no
match
1s
found
the
description will be left blank for that mnemonic.
1In order for a
M9312 type ROM to be listed it must be in a M9312 type format
as
described in subsections 4.6.3 thru 4.6.6.
Figure

4-10

shows

an example of

screen

display

for

the

1list

command.

Commands are Help, Boot,'List, Setup, Map and Test.
Type

command

Device

Unit

name

numbers

0-255

then

press

Source

CPU ROM

the

RETURN

Device

type

RD51,

DL
DX

0-3
0-1

CPU ROM
CPU ROM

RLO1l,
RXO01

0-1

CPU

ROM

RX02

0-1

CPU

ROM

TUSS8

DK
MU

0-7
0-255

CPU ROM
CPU ROM

Commands are Help,

Type

command

RKO5
TK50,

Boot,

then press

FIGURE

List,
the

4-10

RD52,

RLO2

key:

RX50,

RC25,

<CR>

RA80,

Tu8l

Setup,

Map and Test.

RETURN key:

LIST

COMMAND

DISPLAY

RA81,

RA60

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

NOTE

Figure
the

4.2.4

Setup

This

command

parameters
and all of

Subsection

4.2.5

Map

The

user

try

4-10

exact

screen

example and may

not

represent

display.

Command

enables

the

user

1list

and/or

change

in the EEPROM including boot parameters.
the programmable parameters are discussed

This
in

4.3

all

command

detail

Command

enters

this

identify

command
by

all

typing

memory

the

<CR>.

This

command

will

system

and

then map

all

locations in the I/O page.
Memory is mapped from location
0
the
1I/0 page in 1,024 byte increments.
Memory is not mapped
every location.
The routine will try to
identify
the
size
each
memory,
the CSR address for each memory if applicable,
CSR type (ECC or Parity) and the general bus type.

important

addresses

will

not

work

note

that

have

CSR's
properly.

of memory if two
are
not
contiguous
the
descriptions with a blank line.
they

all

press

out

all

memory

the

RETURN

mapped
key

two memories

with

During mapping

After

the

same

address

or more memories
ROM

ROM

continue

code

code
the

will
map,

will

to
for
of

the

some

common

the map

command

are

present

separate

wait

for

which

will

the

and
their

user

then

typed

addresses in the I/O page that respond.
The I/0 page map
from
addresses
17760000
to
17777776.
In addition, all
addresses that respond that are on the KDJ11-B or on the
KTJ11-B
are provided with a short description.
There is no des- cription
for addresses that respond and are on the external bus, with
the
exception of memory CSR's, if present.

goes

BOOTSTRAP AND

DIAGNOSTIC

ROM

PROGRAMMING

Dialog mode is restarted at completion of the
map
command.
To
help prevent the data shown from being scrolled off the screen on
video terminals the ROM code will wait for the user to press <CR>
anytime
the data might overflow the screen.
The ROM code always

assumes

the

terminal

can display
at

shows

example

least

lines

coloumn

data.

Figure

4-11

Commands
Type

are

Boot,

then

a map

List,

press

the

command

Setup,
RETURN

Map

printout.

and

key:

Test.

<CR>

Map

Starting
Address

00000000

Press

Help,

command

Memory

Ending
address

Size 1n
K Bytes

CSR
address

CSR
type

Bus
type

03777776

1024

17772100

Parity

PMI

the RETURN key when

I/0 page

Ending

Address

address

17765000

17765776

17770200

17770376

17772100

17772152
17772276

17772516
17773000
17774400

17773776
17774406

17777560
17777572
17777600
17777730

17777744

CPU

ROM

17772376

17777524
17777566
17777576
17777676
- 17777734

17777752

Unibus Map

Memory

17772150
17772200

17777520
17777546

<CR>

Map

Starting

17772300

ready to continue

EEPROM

CSR

Supervisor

MMR3
CPU ROM or

UBA ROM

Kernel

and

D PDR/PAR's

BCSR, PCR,
Clock CSR

BCR/BDR

MSER,

MREG,

Console SLU
MMRO,1,2
User I and D PDR/PAR's
DCSR, DDR, KMCR

CCR,

17777766
17777772

CPU Error
PIRQ

17777776

PSW

Hit/Miss

Commands are Help, Boot, List, Setup, Map and
Type a command then press the RETURN key:

FIGURE

4-11

MAP

COMMAND
~

DISPLAY

Test.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
4.2.6

Test

Command

This command causes the ROM code to run
most
of
the: power
up
tests
1in
a
continous loop.
The ROM code starts at test 70 and
runs all applicable tests and then restarts the loop
after
test

is complete.

entered.

console.

The

print out
errors 1if
The

the

the total
any.

user may

the

If an error occurs the general error routine

user may

test

also

exit

the

test

time

number of

type

test

applicable

test

loop

typing

is exited

1loops

and

the

number

after

the

the ROM code will

CTRL

C at

1is

the

the ROM code will

total

test

command

loop on

test only until an error occurs or CTRL C 1is type.
number selected is not a loopable test the general
be entered and all loopable tests will be run.

number

and

that specific
If
test

the
test
loop will

NOTE

CTRL C is not echoed
console terminal.

Figure

4-12

command
by
user aborts

shows

example

the

ROM

the

code

wuser

the

entering

typing T <CR> which will run all loopable
the testing sequence after four passes by

the

test

tests.
typing

The
CTRL

Commands

Type

are

Continuous

Total

Passes
Errors

Commands

are

Boot,

then

self

Total

Type

Help,

command

press

test

List,

the

Type

Setup,

Map

RETURN

key:

CTRL

exit

and

Test.

<CR>

CTRL C

{4
0

Help,

Boot,

command

then

press

FIGURE

4-12

TEST

List,

the

Setup,

Map

RETURN

key:

COMMAND

and

Test.

EXAMPLE

Figure 4-13 shows an example of the user looping on only
The user aborts the test loop by typing CTRL C after 202

test 60.
passes.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

Commands
Type

are

Looping

Passes

Total

Errors

Commands
a

are

SETUP

the

Type

CTRL

Setup,
RETURN

Map

and

key:

exit

Test.

CTRL

<CR>

202

Help,

command

Boot,

List,

Setup,

Map

the

RETURN

key:

then_press

4-13

MODE

COMMAND

entered by

Setup mode

List,

press

FIGURE

4.3

Boot,

then

test

Total

Type

Help,

command

LOOP-ON-TEST

and

Test.

EXAMPLE

DESCRIPTIONS

typing

<CR>

dialog

mode.

Setup

mode
allows the user to list or change most of the parameters 1in
the EEPROM.
Setup mode also
allows
changes
to
any
bootstrap
programs stored in the EEPROM.
Setup mode has fifteen commands.
After

power

restart

and

the

completion

all

code
loads
the
first
105
bytes
of
the
EEPROM
beginning at location 2000.
This area in memory is
as
the
Setup
Table.
The
setup
TABLE
contains
parameters except the EEPROM resident boot programs.

The

EEPROM may

system.

The

contain
first

various
105

bytes

types
is

tests

ROM

into memory
referred
to
all

information

the

needed

for
by

the

the
ROM

code to configure the KDJ11-B (CPU) and the KTJ1ll-B (UBA) and
to
determine
the
boot
device,
test
selections and modes.
Other
information in the EEPROM could be user bootstrap programs and
a
foreign
language
file.
Setup mode allows changes to the first

105 bytes

language

and

area

the

present

wuser

bootstrap

cannot

programs.

changed

When setup mode is first entered it "types
out
a
commands
and
provides
a
short
description
of
Figure 4-14 shows an example of setup
mode
being
dialog

mode

after

the

user

types

<CR>.

The

in setup mode.

foreign

1list
of
all
each command.
entered
from

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
Commands
Type

KDJ11-B

are

Help,

command

Boot,

then

Setup mode

Command

List,

press

the

Setup,
RETURN

Map

and

key:

Test.

<CR>

KDJ11-B ROM V7.0

Description

Exit

List/change

List/change boot

List/change the Automatic boot selections

parameters

the

translations

Setup

Reserved

List/change

List

Initialize

9
10

Save
Load

11
12
13
14

Delete an EEPROM boot
Load an EEPROM boot into memory

Edit/create
an EEPROM boot
Save boot into the EEPROM

Enter

Type

command

boot

table

the Setup

the switch boot selections

table

in the table
the table

programs
the

Setup

table

the Setup table into the EEPROM
EEPROM data 'into the Setup table

ROM ODT

then

FIGURE

press

4-14

the

SETUP

RETURN

MODE

key:

COMMAND

DESCRIPTIONS

NOTE

The version number of the ROM code 1is printed out
at the beginning of the Setup mode message.
This
manual revision assumes the ROM code
1is
version
7.0 (Vv7.0).
)

The

following

paragraphs

provide

detailed

description

each

command.
To execute a command, type the command number followed
by pressing the RETURN key.
At any time the user may type CTRL C

return

dialog

mode

CTRL

return

the

beginning

setup mode.
NOTE

Never

terminate

CTRL
C or CTRL 2.
ignored and lost.
character
RETURN
CTRL

CTRL

change

1If this
Always
after

2Z.

4-15

any

parameter

with

is done the change is
use
the
terminating

amry

change

and

then

use

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

When

setup

mode

completion

1is

restarted

Commands

short command message
user
may either type
the full
message.

Press
Type

4.3.1

This
to

Setup

the

Dialog

typing

CTRL

15,

the

code

will

ROM

the

out

Figure

4-15

shows

the

RETURN

key:

short

command

Setup mode

the
a

thru

instead of the full list of commands.
The
in a new command now, or press <CRY> to list

command menu.
'

KDJ11-B

for

Help

command

RETURN

then

press

the

FIGURE

4-15

SHORT

COMMAND

Command

exit

mode.

key

MESSAGE

command

for

the

set

up mode

and

Dialog

mode

also

entered

4.3.2

Setup

Command

This

command

prints

returns
CTRL

the

user

typed.

out

the

current

status of

various

parameters

and
allows
the user to change them if desired.
When setup mode
command 2 is entered the ROM code prints out the
current
status
of
all
parameters,
repeats
the first parameter, and waits for
user input.
The user can type <CR>s to position the
program
at
the
desired
parameter
to
be
changed.
The
user can also go
directly to the parameter by typing the letter to the left of the
parameter in the first list.
NOTE

After changing
Command

any

(Save)

parameters
in the

should

Setup Table,

executed.

To change a parameter the user types in the new value
and
<CR>.
Typing
<CR>,
Line feed or .
will cause the ROM code to proceed
to the next parameter.
Typing Or - will cause the
ROM
code
to
proceed
to
the previous parameter.
Any of these characters can
be used to change a value.

Figure 4-16 shows an example of command 2
being
entered.
This
example
also
shows
the
values
of
the
parameters
1if
the
"initialize setup table" command 8, is executed in setup mode.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
KDJ11-B Setup mode

Press the RETURN key for Help

Type a command then press the RETURN key: 2 <CR>

List/change parameters in the Setup table
A -

l=Yes

B
C
D
E

- Power up
O0O=Dialog, (1l)=Automatic, 2=0DT, 3=24
- Restart
O=Dialog, (1l)=Automatic, 2=0DT, 3=24
- Ignore battery
O0=No,
l=Yes
- PMG 0-(7) 1=.4us, 2=.8, 3=1.6, 4=3.2,...7=25.6

ANSI

Video

terminal

(1)

0=No,

F -

G
H
I
J
K
L

Disable clock CSR

=1
= 1
=0
= 7

- Force clock interrupts
0=No,
l=Yes
- Clock
O=Power supply, 1=50Hz, 2=60Hz, 3=800Hz
- Enable ECC test (1)
0=No,
l=Yes
- Disable long memory test
. 0=No,
l=Yes
- Disable ROM 0=No, 1=Dis 165, 2=Dis 173, 3=Both
- Enable trap on Halt
0=No,
l=Yes

= 0
= 0
=1
=0
= 0
=0

Allow

O0=No,

l=Yes

0=No,

l=Yes

N - Disable Setup mode
0=No,
O - Disable all testing
O0=No,
P - Enable UNIBUS memory test (1)
0=No,
Q - Disable UBA ROM
O0=No,
R - Enable UBA cache (1)
O=No,
S - Enable 18 bit mode
0=No,
List/change parameters in the Setup table

l=Yes
l=Yes
l=Yes
l=Yes
l=Yes
l=Yes

=0
=0
=1
=0
=1
=0

Type

CTRL

ANSI

Video

alternate

exit

terminal

boot

press

block

the

RETURN

(1)

FIGURE

0=No,

4-16

COMMAND

key

for

l=Yes

change

New =

EXAMPLE

NOTE

124

two

KW of

UNIBUS memory

following

parameter

A -

ANSI

When

set

paragraphs

specified

Video

will

terminal

this

not

present,

the

present

(Enable

last

UBA
cache
and
enable
18-bit
mode).
When
this
condition occurs UBA cache is always disabled and
18-bit mode is forced unconditionally.

The

parameters

detail

Figure

description of

each

Command

4-16.

present:

indicates

that the console
video terminal.
When 0 it indicates that the
hard copy
or
non
ANSI
compatible.
When
4-17

terminal

ANSI

console terminal
video
terminal

1is

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
selected

the

screen.

The

space,

then

terminal

is
identifies
power up if
send

key

code

will

accom-

backspace

selected

and

erase

the

plishes

the

this

console

screen

The

This

clear

video

and

terminal

information

not

then

position

parameter
used

character

sending

terminal.

the

DELETE key
1is
deleted
characters by using the
ANSI video terminal is selected

ANSI

coloumn
code.

DELETE
ROM

the

When

hardcopy

used

the

slash

character.

ROM

the

ROM

the

cursor

used

only

operating

the

backspace,

cdde

code

will
line 9

the

ROM

system.

NOTE

VI52's

are

present
prevent
the

Power

These

ANSI

compatible.

VTS52

1is

this
parameter
to 0 to
command
from
disabling

VT52.

up mode

are

not

you
must
set
the Clear Screen

two

and

restart

separate

mode:

parameters.

When

the

ROM

code

started

i1t checks a status bit to determine if the unit is powering up or
1f the front panet RESTART switch was activated.
The
ROM
code
then
wuses the appropriate mode selected.
There are four choices
for the power up mode and the restart mode.
The user may
define
the the action taken by the ROM code at power up or restart to be
the same or different.

Dialog mode:

completion

the

diagnostics,

dialog

mode
1is
entered.
Dialog mode is also entered any time the
force dialog switch is set to the on position regardless
of
the
modes
selected
here.
(See
subsection
4.2
for
a
description of Dialog mode.)
1l - Automatic mode:
At completion of
the
diagnostics
the
ROM
code
enters an automatic boot routine that will try to
boot
are
list

a previously selected device or device's.
The device's
selected
1in
the EEPROM (refer subsection 4.3.4).
The
of devices can be from
1
to
6
devices
1long.
Each

device

1is

no more

devices

tried

until
try.

successful
The

default

boot
list

occurs
of

there

devices

are

A,
DLO,
MSO0
and
MUO
1in this order.
"A" is a special single
letter mnemonic which causes the ROM code to boot the
first
disk
MSCP
device that it can.
Removable media devices are
tried before fixed media devices.

1is

ODT mode:
At completion of a very limited set of
tests
ROM code executes a halt instruction and passes control
to J11 micro ODT (refer to subsection
4.7).
If
the
wuser
the

types P at this point without changing any registers the ROM
code will contine normal testing and then enter dialog mode.
This mode would normally be used in debug environments.
The
ROM code will not change
any
1locations
1in
memory
before
entering

ODT mode.

4-18

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
the
tests
At completion of a limited set of
3 - 24 mode:
code loads the PSW with the contents of location 26 and
ROM
then transfers control to the address
located
1in
location
This mode is used when non volatile memory 1s present
24.
not
The ROM code will
and power fail recovery is desired.
24.
mode
executing
before
change any locations in memory
D -

Ignore battery:

This parameter

used

only when the

current power up or

restart

Normally this parameter 1is set to O
(3).
24
to
set
1is
mode
meaning that the memory battery ok
signal
must
be
present
1in
order
to execute mode 24.
If this parameter is set to 1 mode 24
is

executed

regardless

the

status

the

Dbattery.

power

mastership

count

up,
1f
the
mode
selected
1is
mode
24 and the ignore battery
parameter is set to 0
and
the
battery
status
indicates
that
voltages
were not maintained, the ROM code will ignore the power
up selection and use
the
restart
selection.
If
the
restart
selection
1is
also
mode
24 the ROM code will default to dialog
mode.

PMG

count:

This parameter sets

the BCSR.

The

is disabled.

suppress

the value

range

When set,

DMA

requests

the

and

the processor

to 7.

When set

give

the

time

count

value

enables

zero the counter

the

KDJ1ll-B

processor bus mastership

during
the
next
DMA
arbitration
cycle
after
the
counter
overflows.
The
processor
will only take the bus for one cycle
before relinquishing control of the bus to a
regquesting
device.
The

following

overflow for
parameter is

Value

table

shows

the
different
normally set to

Time

for counter

Disabled*

0.4

usec

0.8

3
4

1.6
3.2

usec
usec
usec

5
6
7

6.4
12.8

25.6

needed

the

for

PMG

the

counter

count.

to overflow

usec
usec
usec

The PMG count of
for most typical

special

values
7.

0 (Disabled)
systems, and

applications.

is
is

not recommended
reserved for

This

BOOTSTRAP AND

Disable

When

set

DIAGNOSTIC

Clock
1

this

parameter

When
set
is normally

Clock

Force

When

set

PROGRAMMING

CSR:

17777546.
parameter

ROM

to
set

disables

0
to

the
0.

the

<clock

clock

CSR

1is

address

enabled.
-

This

Interrupts:

the

clock

will

unconditionally

regquest

1interrupts

when
the
processor
priority
1is
5 or less.
When set
clock can regquest interrupts only if the clock
CSR
1s
clock
CSR
bit
6
1is 1 and the processor priority 1s 5
This parameter is normally set to 0.

to 0 the
enabled,
or less.

NOTE

the

command

parameter

Force

Clock

is
selected
the
user should
clock CSR since the CSR has no

1Interrupts

always disable the
control
over the

clock.

Clock Select:

This parameter determines the
The choices are listed below.
Value

<clock

used.

Source

Enable

ECC

When

set

run

any

the

Clock sourced from backplane pin BR1l. The power
normally drives this signal at 50 or 60 Hz.
Clock sourced on the KDJ11-B at 50 Hz
Clock sourced on the KDJ11l-B at 60 Hz
Clock sourced on the KDJ11l-B at 800 Hz

1
2
3

source of

supply

Test:

this

parameter enables the

ECC

memorys

ECC memory

present except

test

Dbe

UNIBUS memory.

the

system contains a mix of ECC and non ECC memory the ROM code will
run
the
ECC
tests only on the ECC memories.
The ROM code uses
bit 4 of the memory CSR to determine if
the
memory
1s
ECC
or

parity.
If
bit 4 is a read/write bit and can be written as a 1
and a 0, the ROM code assumes
the
memory
1is
ECC.
When
this
parameter
is
set
to
0
the ECC test is always bypassed.
This
parameter is normally set to
1
even
when
ECC
memory
1s
not
present.
This
parameter
would
be
reset 1f an ECC memory was
installed whose
type

memory.

ECC

hamming

code does

not match

that of an MS11-P

BOOTSTRAP AND DIAGNOSTIC

J -

Disable

Long

When set to

ROM PROGRAMMING

Memory Test:

this parameter bypasses

the memory

address

shorts

When set to 0, the
for all memory above 256 K bytes.
test
data
address shorts data test is run on all
available
memory. . This
parameter

1is

normally set

to O.

NOTE

I1f

the long memory test

disabled

memory exists above 256 K bytes it
that memory
will
contain
parity
power

This

Disable

and

is very
errors

parity
likely
after

up.

ROM:

parameter

allows

the

user

selectively disable

all

part

of
the
ROM
code
after
the
selected
device has been booted.
Normally the ROM code on the CPU responds to two 256
word
pages
in the I/0 page.
One page responds to address'’s from 17773000 to
17773777, the other page responds to address's from
17765000
¢to
17765777.
Both of these pages are automatically enabled at power
up or restart.
After a device is booted, one or
both
of
these
pages may be disabled by the ROM code.
The following table lists
the var- iations of this parameter.
This parameter
1s
normally
set

Value

Rom

Pages

Disabled.

None

17765000-17765777

17773000-17773777

17765000-17765777

and

17773000-17773777

NOTE

the

ROM

code

booting

directly

type boot ROM located on either the
the M9312 module, the ROM code will
disable the CPU ROM in the 17773xxx

from a

M9312

UBA module or
automatically
address range

and will enable the ROMs on the board which
were
selected
for
booting.
This
action
1is
taken
regardless of the status of the disable
UBA
ROM
parameter (Q) and the disable ROM parameter (K).

L -

Enable

Trap on

Halt:

BOOTSTRAP

this

AND

DIAGNOSTIC

parameter

halt

parameter

1is

Allow

After

the

set

PROGRAMMING

1instruction

set

halt
instruction
normally set to 0.

ROM

1is

Alternate
boot

the

processor

executed

processor

executed

Boot

block

the

1is

will

trap

kernel

enter

Jl1

in kernel mode.
'

location

mode.

micro

ODT

This

this
if

parameter
)

Block:
a

device

loaded

into

memory

the

ROM

code
looks
at word locations 0 and 2 to see if the device looks
bootable.
1If the data is not correct, the ROM code will type out
an error message indicating that the media is not bootable.
When
this parameter is set to 1 the ROM code looks for location
0
Dbe
any
non
2zero number.
If this parameter 1s set to 0 th ROM code
looks for location 0 to be a value of 240 to 277 and for location

2 to be 400 to 777.
This parameter is normally
be changed to 1 to allow some user's operating
properly.

N -

Disable

this

setup

Setup

Mode:

parameter

mode

0 but may have to
systems
to
boot

from

set

the

dialog mode.

user will

The

not

command

able

lines

enter

in dialog mode

will not show the
the response will

setup command.
1If the
be invalid command.

user

If
Force
Dialog
unconditionally

mode
1is
enabled

then
setup
mode
of
the
wvalue
of

parameter.

This

unauthorized

force dialog

O -

Disable

the

all

ROM

allows

some

Setup mode.

under some

type

This
of

This

necessary.

needs

almost
the

command

set

changed

and

Force

unless

a special
has

immediate

contents

assumes

the user has

prevent

control.

Dialog mode

the

testing.

selected

boot

for cases

response at power up,
to

left

selected,

No location

program

parameter which should

been provided

of memory

not

contain

the

and when

unaltered.

testing
1s
disabled
and
parity
memory
then
it
1is very likely that memory will
parity errors

after

power

makes

not be used

where

NOTE

If all
exists

is
this

users
physical

program will bypass virtually all

change.

the

testing:

unless
needs

into

switch

this parameter

in memory will

parameter

entry

the

selected,
regardless

types

the

user

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
P -

Memory Test:

UNIBUS

Enable

If this parameter is a 1 then any available UNIBUS memory will be
This parameter 1is
When O UNIBUS memory is not tested.
tested.
1is
If UNIBUS memory is not present then no action
normally a 1.

QO -

ROM

the

taken by

Disable

code.

UBA ROM:

This parameter is copied to bit 3 in the DCSR of the UBA after

boot.

when

address

range

normal

this

1is 1, the UBA ROMs are disabled.

bit

UBA

This allows other ROM boards on the UNIBUS to show up in the

ROM

of 17773000 to 17773776.

the UBA ROMs are enabled.

tries

This bit

When this bit is 1

is normally 0.

When

user

boot either a UBA or M9312 ROM boot, this parameter 1is

ignored.

NOTE

M9312
If the ROM code is booting directly from a
the
module,
M9312
located on the
ROM
boot
type
ROM
CPU
ROM code will automatically disable the
in the

17773xxx address

UBA module.

enabled
This
status of the
the

R -

Enable

When a

Disable

UBA

this

range and

the ROMs on the

The ROMs on the M9312 module will be
action
1is taken regardless of
Disable UBA ROM parameter
(Q)

ROM parameter

(K).

the
and

Cache:

parameter causes

to be tested by the ROM code.

the

UBA cache

to be

enabled

and

1If a failure occurs during testing

of the UBA cache then it will be disabled.
When 0 the UBA
cache
is always disabled and is not tested.
This parameter is normally
a

Enable

bit

Mode:

This bit is copied to bit 5 of the KMCR on the
this
causes 18 bit addressing only.
When a 0,
occurs.
This parameter is normally a O.

4.,3.3

Setup

Command

This command prints
table
and
allows
translation

table

UBA,
When
a
1
22 bit addressing

out
the

the current contents
translation
table

used

allow

devices
r

4-23

of
to
be

the
translation
be changed.
The
booted

using

non

BOOTSTRAP

AND

standard

CSR

DIAGNOSTIC

ROM

addresses.

routine, RO contains the
name
(mnemonic).
The

PROGRAMMING

When

unit
ROM

the

ROM

program

enters

the

number and R2 contains
the
code
tries
to find a match

boot

device
in the

translation table for the device name and
unit
number.
If
no
1s found the boot program will use the default CSR address
for the device.
1If a match is found the translation
table
will
define the CSR address to be used.

match

-Figure 4-17 is an example of this command.
KDJ11-B

Press
Type

Setup mode

the
a

RETURN

command

List/change

boot

TT1

blank

TT2
TT3
TT4
TTS

blank
blank
blank
blank

TT6
TT7

blank
blank
blank
blank

TTS8
TTO
Type

CTRL

FIGURE

The

ROM code

for

Help

press

the

translations

to exit

blank
Device

TT1

key

then

press

RETURN

key:

Setup

the

RETURN

<CR>

table

key

for

change

name

4-17

now waiting

SETUP

COMMAND

for

the user

EXAMPLE

to enter

new

device

name.
If
the
wuser
does not desire to change any items 1n the
translation table he/she would Type CTRL Z to return to the setup
mode prompt.
The user may skip over any entry and go to the next
entry by pressing <CR>.
To enter a new device or change an entry
the
user
types
1in the new device name, the unit number and the
CSR address.
In the example shown in Figure 4-18, the user has a
system
that
has
one RA80 and a RA60 using a UDA50 controller at the standard
address of 172150.
The user also
has
a
RC25
with
a
KLESI-U

controller.
standard

CSR

Since

address

different address.
respond to address

the

one

UDA5S50

and

them must

the

KLESI-U share

set

the

respond

same

¢to

1In this example the KLESI interface is set to
17760500.
The RC25 has a unit number plug set

4-24

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
for

units

and

The

RA80

unit

and

the

RA60

1is

unit

and

2.
Since the RC25's interface is at a non standard
CSR
address
and
there
are two unit numbers there will be two entries in the
translation table for units 4 and 5.

TT1
Device

Unit

blank
name
number

CSR

address

TT1

DU4

TT2

blank

17760500

address

name
number

CSR

address

TT2

DUS5

17760500 <CR>
address 17760500

blank

FIGURE

translation

controllers
had two RL0O2

name

4-18

CTRL

TWO-ENTRY

TRANSLATION

table also provides

second

controller

handle
at

address

this.

the

17760400

Drives

standard

entries.
Drives 0 and
labeled as drives 4 and

1
5

on
and

TABLE

a means of

such
as
RL02 controllers.
controllers with six drives

controller

<CR>

17760500

Unit

Device

set

DU <CR>
4 <CR>

Device

TT3

The

=
=

address

handling

multiple

For example if the user
of which 2 where on
the

the

0-3

EXAMPLE

translation

would
and

the
second
entered into

would

not

table

could

the

first

require

any

controller
would
be
the translation table.

TT2

DL <CR>
4 0 <CR>
17760400 <CR>
address 17760400

=
=

DL <CR>
5 1 <CR>

blank
name
Unit number
CSR address
TT1
DL4 =

TT1
Device

Since RL0O2 controllers only recognize unit numbers from
0-3
the
unit
numbers 4 and 5 would have to be translated to unit numbers
0 and 1.
Figure 4-19 shows an example of the
entries
into
the
translation table.
|

DLO

blank

Device name
Unit number
CSR

address

TT2

DL5

TT3

blank

Device

name

FIGURE

4-19

DL1

17760400

address

CTRL

UNIT

NUMBER

4-25

<CR>

17760400

TRANSLATION

EXAMPLE

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

4.3.4

Setup

Command

This

command

allows

the
automatic boot
defines the devices

One
the

the

user

entry
1s needed to
device is
used

same

numbers,

then

one

select

the

devices

sequence.
The user creates
and the order in which they

entry

define
more
is

a device and its
than
once
with

needed

for

each

be-tried

a small list that
are to be
tried.

unit number.
If
different
unit

unit

number.

use

the

same

that

NOTE

The

selections

locations
follows.

When

Command

device

name.

for
the

executed

The

this

command

EEPROM

the

user would

ROM

code

then

command

will

type

prompt

the

user

either

the

single

for

double letter mnemonic associated with the device to be selected.
The
ROM code will then prompt for the unit number.
The ROM code
will continue prompting for all six entries in the table.

Figure 4-20 shows an example of command 4.
1In
user adds the boot for the RX02 unit 1 (DY) by
name (E) with DY and typing in the unit number
name 1s typed for the next entry.

this
example
replacing the
next.
The

the
Exit
exit

AND DIAGNOSTIC ROM PROGRAMMING
BOOTSTRAP
KDJ11-B

Press
Type

Setup mode

the
a

RETURN

command

List/change
A =

Disk

External

E
L

=
=

Exit
Loop

for

Help

press

the

DLO

Boot

MSO

Boot

MUO

blank

Type

CTRL

Boot

exit

press

<CR>

Boot 2
Device

= DLO
name

<CR>

Boot 3
Device

<CR>

Boot

4
Device

<CR>

=
=

DY <CR>
] <CR>

=
=

E
0

MSO
name
MUO
name

RETURN

key

for

-Device name
Unit number
=

blank

Device name
Unit number

Type

the

name

Press

in the Setup table

boot

Device

KDJ11-B

<CR>

Boot

automatic boot
ROM

Boot.
5 =

Boot

key:

automatic boot
continously

Boot

RETURN

the Automatic boot selections

MSCP

Boot

key

then

Setup mode

the

RETURN key for Help
command then press the

FIGURE

4-20

SETUP

RETURN

key:

COMMAND

EXAMPLE

change

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

Table

4-2

lists

names

and

the

four

associated

special
ROM

TABLE

The

ROM

it can
first,

will

mnemonic

device

4-2

boot

ROM

the

CODE

first

find. The ROM code will
then fixed media units.

ACTION

bootable

try

disk

removable

MSCP

media

device

units

This mnemonic causes the ROM code to check for a UNIBUS
ROM board in address range of 17773000 to 17773776. If the
ROM exists and location 17773024 is not odd the ROM code
will disable the internal CPU ROMs and the UBA ROMs and
jump to the location specified in location 17773024 of the
UNIBUS
M9301

code

single-letter

action.

The

ROM
or

board.

Usually

user-supplied

only purpose

this

board

would

M9312,

equivalent.

this

mnemonic

indicate

the

ROM code that there are no other devices to try in the
list. This is used when there are five or less devices 1in
the list. It follows the last device in the list to be
tried. If all six entries are filled in the list then this
mnemonic is not needed, the list will terminate
automatically after trying the last entry. When this
mnemonic 1s reached the ROM code will restart the boot
sequence from the beginning and print error messages for
each device that fails to boot as they are tried. After
the second pass through the list without successfully
booting a device the ROM code will enter dialog mode.

This mnemonic will

also mark

the end of

the

list but

when this mnemonic is reached the ROM code will restart
the boot sequence at the beginning of the list and
continue trying to boot each device in the list until
either a successful boot has occurred or the sequence 1is
terminated by the user typing CTRL C. All boot error
messages are suppressed when the ROM code is looping on
the boot list.

The action taken by the ROM
<code
for
the
four
single
letter
mnemonics
A, B, E and L applies only to automatic boot mode with
the exception of B which can also be
executed
from
the
dialog
mode
boot command.
The dialog mode boot command would treat the
4-28

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
single
were

letter mnemonics of A,
used

the

device

name

and
in

L as
the

creates a bootstrap program and loads
program
should not be given a device
since
these
are
already
defined.
mnemonics

are

4.3.5

Setup

This

command

entered

free

for

Command

will

4.3.6

Setup

Command

This

command

allows

eight

switches

devices.

the

fixed

that

Command

they
user

it into
the
EEPROM,
that
name of either A, B, E or L
All
other
single
letter

not

used.

restarted

and

If
no

this

changes

command

user

define

edge of
2-4,

cannot

are made.

value

three

the

to boot specific

six

the

the CPU module

defines

switches

not

the

remote

of
the
eight
possible
other two combinations have a

changed.

Refer

to Appendix

normally

be defined

system

had

used.

for

only

time

these

that

is:

cabling

8-position

The

between

rotory

switch,

the

CPU module

positions

position

to enter Automatic

causes

after testing is
device which was
Normally the

three

the

ROM

code

completed,
defined by

switches

are

such

that

switches

the
will

e EXample
enter the

2-4

are

set

off.

one

boot mode

automatic

boot

the

six

combinations

and Force Dialog mode is not selected the
auto boot mode and attempt to boot
only

selected
code will

by
this commmand.
If the
print out the normal error

NOTE

same

six

selections
area

selections

the

decsribed

table

EEPROM

Command
L4

4-29

are
as

one

mode

1is

4 in
time

shown

ROM
the

code
one

boot is unsuccessful
message
and
enter

dialog mode.

The

each

and attempt to
boot
only
this command in Setup mode.

selected,
the ROM code will use the list defined by command
Setup mode and try to boot each item in the list one
at
a
until all selections in the list have been attempted.
When

and

The user desired to define six

device
the ROM

1is

information.

switches might
a.

1if
the

command

definition

1If

and
be

This
combinations
of

additional

command.

use.

reserved

setup mode

invalid devices

boot

stored
the

six

the
boot

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
Figure

of
and

4-21

the
DU2

shows

example

setup

mode

command

with

three

six
possible positions being defined to select DUO,
and the other three all being defined to select DLO.

DUl

KDJ11-B Setup mode
Press

Type

the

RETURN key for Help
command then press the

List/change

the

Switches
Switches
Switches
Switches
Switches
Switches

2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4

Type CTRL

Switches
Device

switch
on
on
on
off
off
off

boot

on
off
off
on
on
off

2,3,4

off
on
off
on
off
on

key:

selections

to exit or press

name

RETURN

=
=
=
=
=
=

the

off

<CR>

the

Setup

table

DUO
DUI1
DU2
DLO
DLO
DLO

RETURN key
=

for No change

DUO

FIGURE 4-21 SETUP COMMAND 6 EXAMPLE
4.3.7

Setup

Command

This command performs the exact same function as the List command
in the List command in Dialog mode.
The command is duplicated 1in
setup mode for user
convenience,
see
Subsection
4.2.3
for
a
detailed description of this command.
Setup mode is restarted at
the completion of this command.

4.3.8

Setup

Command

This

command initializes the current contents of the setup
table
in
memory
to
the default values.
This command does not affect
the contents of the EEPROM 1itself.
The setup save command 9 must
be
executed
1in
order
to save the setup table into the EEPROM.
This command only affects parameters associated with
commands
2
to
6
of
Setup mode and does not affect any data that is not in
the first 105 bytes of the EEPROM.

The

following

Command
-

All

items

1list

the

value

the

parameters

after

entered:

parameters

are
set
which are

to
set

listed

0
to

under

setup

command

with
the exception of A,
1.
(See Figure 4-16.)
4-30

setup

mode

P and

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
-

All

entries

are

cleared

and

command

The automatic boot selection list
under
setup
command
will be set to A, DLO, MSO, MUO, E, blank.
'

Since
of

Setup Command

parameter

To enter
code

the

this

prompt,

executed

values

the

must

KDJ11-B

Type

will

the

Press

list

command
user

after

defaults
1in
8 execution.

translation

will

type

sure

Type

command

key

then

the

you

commands

Command
of

that

After

the

<CR>.

Command

user

wishes

4-22

shows

4 it's

Command

Help

press

the

(Save)

list

should

retain

example

ROM
the

Command

then

4-22

RETURN

key:
8

<CR>

RETURN

key:

<CR>

RETURN

key:

table

0=No,

command

FIGURE

This

area as
to

type 8

for

Setup

KDJ11-B Setup mode
Press the RETURN key

Setup

setup

the

Figure

RETURN

Are

4.3.9

under

Setup mode

command

same

identical

EEPROM.

Initialize

Type

the

table

blank.

user must

Command

the

l=Yes

press

the

for

Help

press

the

SETUP

COMMAND

EXAMPLE

copies

the

current

contents

the

setup

table

memory into the EEPROM.
The command should be executed after any
changes are made to the EEPROM in Setup mode.
This is
the
only
command
that writes anything into the first 105(10) bytes of the
EEPROM.
When saving data into the EEPROM the ROM code will
only
write the locations that need to be written.
This

command

the
EEPROM
written the
error.

command

will

always

unless
ROM code
takes

write

new

and

correct

checksum

into

failure
occurs.
If a location cannot be
try
once
more
and
then
report
the
approximately 15 ms to write each location.
will

entered

and

changes

have

been

made

the

setup
change
be

table,
the
ROM
<code
will print out a message saying no
were made and then restart Setup mode.
If changes are
to
made
the
ROM
code
will
prompt the user to make sure they

desire

Command

to make
9.

the

changes.

Figure~’
4-31

4-23

shows

example

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
KDJ11-B

Press

Setup

the

Type

Save

the

mode

RETURN

command

Setup

Are

you

sure

Type

command

for

Help

then

press

the

RETURN

table

into

the

EEPROM

key

0=No,

then

Writing

the

KDJ11-B

Setup mode

Press

the

key:

<CR>

key:

<CR>

l=Yes

press

the

for

Help

RETURN

EEPROM

RETURN

key

Type a command then press the RETURN key:
FIGURE 4-23

4,3.10

Setup Command

SETUP COMMAND 9

EXAMPLE

the
in memory with
table
This command will restore the setup
This command allows the
in the EEPROM.
stored
actually
values
some temporary
making
after
table
setup
user to restore the
from the EEPROM
data
actual
the
load
to
used
It is also
changes.
EEPROM
the
during
occurred
error
an
if
into the setup table
checksum

tests.

the ROM
When an error occurs during the EEPROM checksum tests,
values
default
of
set
a
loads
the data is bad and
code assumes
could
user
the
case
this
1In
into the setup table and uses them.

load the actual data and then verify the data is OK before trying
to save

it back

into the

EEPROM.

Figure 4-24 shows an example of Command 10.
KDJ11-B

Setup mode

Press the RETURN key for Help
Type a command then press the RETURN key:

10 <CR>

Load EEPROM data into the Setup table
Are you sure ?

0=No,

l=Yes

Type a command then press the RETURN key:

KDJ11-B Setup mode

Press the RETURN key for Help
Type a command then press the RETURN key:

FIGURE 4-24 SETUP COMMAND 10 EXAMPLE
4-32

1 <CR>

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING
4.3.11

Setup Command

this
If
This command allows the user to delete an EEPROM boot.
ROM code will prompt the user for the
the
executed
is
command
After the device
to be deleted.
boot
EEPROM
the
of
name
device
for the first boot
look
will
code
ROM
the
in
typedis
name
if
1it,
delete
and
name
device
that
with
EEPROM
the
in
program

boot programs following the deleted
any
are
there
If
found.
program the
ROM
code
will
automatically
move
all
of
these
available by the deleted
made
space
the
use
to
up
programs
program.

(See

Figure

4-25.)

KDJ11-B Setup mode
Press the RETURN key

Type a

command

Delete

Type

CTRL

EEPROM

Are

you

sure

Type

command

KDJ11-B

Help

the

RETURN key:

or press

the

This

command

RETURN key

for

change

0=No,

l=Yes

then press

the

RETURN key:

<CR>

program

into

Setup mode

FIGURE

Setup

<CR>

Press the RETURN key for Help
Type a command then press the

4.3.12

boot

to exit

name

Device

for

then .press

4-25

Command

used

SETUP

copy

RETURN

COMMAND

EEPROM

boot

key:

EXAMPLE

memory.

When
the
command is executed, the ROM code prompts the user for
the device name of the
EEPROM
boot
program
to
be
1loaded
in
memory.
The
program
can
then be examined and/or edited using
Setup

Command

13.

Figure

4-26

shows

example

Command

12.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

KDJ11-B Setup mode
Press the RETURN key for Help
Type a command then press the

Load

EEPROM boot

Type

CTRL

Device

exit

name

Are

you

sure

Type

command

press

<CR>

the

)
RETURN

key

for

change

<CR>

0=No,

Setup mode
the RETURN key

key:

into memory

then

RETURN

l=Yes

press

the

for

Help

press

the

RETURN

key:

RETURN

key:

<CR>

KDJ11-B

Press
Type

command

then

' FIGURE 4-26 SETUP COMMAND 12 EXAMPLE
4.3.13 Setup Command 13
This command

is used to either create a new EEPROM
Dboot
program
or
to
edit
a
program previously loaded with Command 12 above.
Command 13 allows the user to change the device name, the
device
allowable unit number range, the beginning and
the
description,
ending addresses of the program in memory, and the start
address
of

the

program.

When these changes are complete the ROM code enters ROM ODT which
is
a
ROM
code
version of J11 Micro ODT.
When this command 1is
first entered it will list the available space in the EEPROM
for
bootstrap

Figure

programs

4-27

shows

an example of

Command

13.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

Setup mode

KDJ11-B

Press the RETURN key for Help
Type a command then press the
Edit/create

EEPROM boot

Type

CTRL

exit

press

1410

Bytes

free

the

EEPROM

Device

name

Beginning
Last

byte

address
address

RETURN

key:

<CR>
-

the

RETURN

key

for No

New

000600

New =

10000

<CR>

000615

New

10177

<CR>

change

<CR>

Start address

= 000600

New = 10000 <CR>

Highest Unit number

= 3 |

New = 255 <CR>

Device

New =

Enter

Description
ROM

EA BOOT

RM02,RM03

<CR>

ODT

xxxxxx/

open

word

RETURN
. or LF

=
=

close
close
close

location

location
location
location

and
and

xxxxxx

open
open

1if

address

even,

byte

odd

next
previous

ROM ODT> 010000/000000 012705 <CR>
ROM

ODT>

010002,/000000

101

ROM ODT>

010004/000000
010006/000000

12706

ROM ODT>

<CR>

1000

Type CTRL Z exit back to the setup mode menu.

etc.

FIGURE 4-27

SETUP COMMAND 13

EXAMPLE

1in
program
the
The beginning address is the first location of
of
byte
last
the
of
address
the
is
address
byte
last
The
memory.
code used

in memory.

for this value.

waste

EEPROM

in doubt, use

the last address of data +

Do not use a much larger number since it will

space.

The start address is the address that
the
ROM
<code
will
pass
control
to.
The
start address does not have to be the same as
the load address but it must be even and a
value
1n
the
range
defined

the

load

and ending

addresses.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

The

highest

numbers
range is
number

unit

1is

typed

invalid unit
The
of

number

1in

characters or spaces.
is
physically
marked

This

allows

allowable

boot

time

range

is
0

set
to

and

to 3
255.
not

valid

unit

the allowable
If
a
unit
range

occur.

then

)

an optional
The
maximum

but recommended description
length
of this name is 11

The name should normally be the name
that
on the outside of the device (i.e.
RL02).

Setup Command

command

the

the value
range is

number error will

device description
the
device
name.

4.3.14

defines

for this device.
If
0 to 3.
The highest

the

user

save

the

existing

boot

program

located in memory into
actually writes a boot

the EEPROM.
This is the only command that
into the EEPROM.
The other commands
only
change
a
copy of the boot program that resides in memory.
When
saving a boot program into memory the device name of the
program
must not match the name of an existing program in the EEPROM.
1If
the program name already exists the user must delete that program
first
or
change the name of the program to be saved.
1If two or
more programs were written into the EEPROM
with
the
same
name
only the first one would be found and used.
Figure 4-28 shows an
of

Command

14.

KDJ11-B Setup mode
Press the RETURN key for Help
Type a command then press the
Save

boot

into

Type

CTRL

the

to exit

Are

you

sure

Type

command

RETURN

key: 14

press

0=No,

then

the

RETURN

key

the

RETURN

key:

Setup mode

Press the RETURN key for Help
Type a command then press the

4-28

SETUP

RETURN

COMMAND

FIGURE

for No

l=Yes

press

Writing the EEPROM - Please wait
KDJ11-B

<CR>

EEPROM

example

key:

EXAMPLE

<CR>

change

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

Figure 4-29 shows an example of Command 14 being
the
data in the setup table matches the data in
no

changes

were

executed
where
the EEPROM, thus

made.

KDJ11-B Setup mode
Press

the

Type

Save

boot

Boot

RETURN

command

into

the

already

changes

KDJ11-B

Press
Type

Setup

This

command

ROM

code

command

puts

the

RETURN

key:

RETURN

key:

<CR>

EEPROM
the

key

then

4-29

Command

will

Help

EEPROM

mode

RETURN

FIGURE

4.3.15

for

made

Setup

the
a

key

then press

for

Help

press

the

SETUP

COMMAND

EXAMPLE

(see

the

user

into

ROM

open

the

address

ODT

Figure

defined

4-30).
the

The

beginning

address of the program.
ROM ODT is not the
same
as
Jll
micro
ODT.
The only purpose of ROM ODT 1is to allow the user to create
or edit a small bootstrap program to be stored in the EEPROM.

In
the

ROM

ODT

the

addresses

addresses
registers

only
of

allowable
memory

and any
attempt
is not allowed.

addresses

from

0-28

that

can

examined

(0-00157776).

¢to
accessed
the
Table 4-3 lists the

Any

are
other

I/0
page
or
any
ROM ODT commands.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

TABLE

Slash

Prints

4-3

ROM

contents

ODT

COMMANDS

specified

no address 1s defined then
the last location that was

location

opened

out

the

only

odd

contents

location

print contents
opened. If

number
the

then

byte.

location 1is even then mode is word, if
location is odd then mode is byte. Leading
zeroes are assumed. Only bits 15 through
zero

the

address

are

RETURN

<CR>

Closes

open

location

LINE

<KLF>

Closes

open

location

FEED

the next
by 2, if

Period

used.

and

then

opens

location. If word, increment address
byte, increment address by 1.

Alternate

character

for

line

feed.

This command is useful when the terminal
is a VT2xx series terminal. It is also
convenient to use with the keypad.

arror

Closes an open location and then opens
the previous location. If in word mode
then decrement
by 1.

Minus

Alternate

command

VI2xx

convenient
Delete

The

DELETE

Deletes

following -paragraphs

EXAMPLE

character

This
a

the

byte

for Up

useful

when

series

terminal.

with

use

present

the

decrement

arror.

the
It

also

keypad.

character

examples

terminal
is

ROM

typed.

ODT

use.

Location
location
contents.

200 is opened.
202 is opened,

It 1is
which

then closed with
no
is then closed after

changes
changing

and
it's

BOOTSTRAP

ROM

ODT

200/

ROM

ODT

000200/100000

<LF>

ROM

ODT

000202/003333

ROM

ODT

EXAMPLE
Byte

DIAGNOSTIC

ROM

PROGRAMMING

<CR>

location

1002
then

AND

and

1001

1003

are

opened.

then

Location

<closed

1003's

and

data

1locations

changed

and

closed.
ROM

ODT

1001/

ROM ODT > 001001/101 <LF>
ROM

ODT

001002/104

<LF>

ROM

ODT

001003/113

141

ROM

ODT

EXAMPLE

The

user

page,

attempts

and

not
ODT

open

location

170000

which

the

1/0

ROM

ODT

77770000/

Location 150000
by

allowed.

ROM

EXAMPLE

<CR>

is opened and then closed.

typing

ROM

ODT

150000/

ROM

ODT

150000/032737

ROM

ODT

ROM ODT

150000/032737

only.

<CR>

It is

then

reopened

BOOTSTRAP AND DIAGNOSTIC

KDJ11-B

Press

Setup

mode

for

Help

then

press

the

exit

XXXXXX/

open

word

location

RETURN

close
close

location
location

and

open

location

and

open

Type

the

ROM PROGRAMMING

command

Enter

ROM

Type

CTRL

RETURN

key

RETURN

press

the

RETURN

xxxxxx

ROM

ODT>

010000/000000

012705

ROM

ODT>

101 <CR>
12706 <CR>

ROM

ODT>

010002/000000
010004/000000

ROM

ODT>

CTRL

the

<CR>

key

for

address

change

even,

byte

odd

next
previous

<CR>

Setup mode

KDJ11-B
Type

ODT

Press

key:

RETURN

command

key

for

Help

then press

the

RETURN

key:

FIGURE 4-30 SETUP COMMAND 15 EXAMPLE
4.4
When

DIAGNOSTIC
an

error

ERROR MESSAGES
occurs,

the

test

number
printed.
error
The
test number that the ROM code

corresponding

error messages

4.5

PROGRAMS

BOOTSTRAP

Bootstrap programs may be

The

ROM code

contains

number

and

always

running.

the

found

various

bootstrap programs

Device

DU*
DL
DX
DY

DD
DK
MU**

Device
RX50,
RLO1,

RX01
RX02
TUS8
RKO5
TU81

Type

RC25,
RLO2

RA8O,

RA81,

RA60

information

are

number of the current
test
numbers
and
in Chapter 5.

The

are described

devices:

Name

other

areas

for

the

system.

following UNIBUS

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

DU refers to a general
disk MSCP devices.

MU refers
tape

For

users

list,

ROM

are

a general

for

purpose boot program

for-

MSCP devices.

who have

the

which

purpose boot program

devices

code

also

typically

not

covered

supports

shipped

the

with

use
the

the

ROM

M9312

code

bootstrap

type

controller

boot

ROMs

module

for

devices
which
<can
be booted.
These ROMs are currently used
all existing UNIBUS PDP 11 products.
An example of this would
a RKO7 disk drive which uses a M9312 ROM to allow the drive to
booted.

Table

4-4

lists

the

M9312

type

boot

1in
be

be
currently

ROMs

available.

The

user may

install

the

ROM

either

optional M9312 module.
The ROM code
type ROM located in either
module.
additional information on M9312 type
The

ROM

new
can

devices or for
install machine

code

also

allows

users

the

UBA

module

will list and boot
Subsection
4.5.1
ROMs.

install

bootstrap

custom boot programs in the
language programs into the

programs

EEPROM.
EEPROM

EEPROM

the

one

and

programs

from
the
assembles
program

important

others.

EEPROM

executed

cannot

ROM
<code
EEPROM boot
at

difference

The

start

program

between
an

out

eight

the

address

defined

than

boot

one

bit

programs
device

EEPROM

requested,

they

are

code always
starts
the

program.

The

the

ROM

searches

for

the

program

the

EEPROM

the

ROM

code

the

ROM

sockets

the

UBA

the

ROM

sockets

the

M9312

code

sequence:

the
on

boot

the

which means

depending

boot

following

the

loaded
time.

program

When

the

boot

or
M9312
type
ROMs.
The ROM
programs in
memory
and
then

EEPROM may contain more
size of the programs.
boot

for

The user
by
using

Setup
mode
commands
11 through 15.
Once the program is
into the EEPROM, it will be avail- able to the user at any

There

any M9312
contains

CPU

the

first.

CPU

next.

next.
board

next,

present.

BOOTSTRAP AND

DIAGNOSTIC

4.5.]1

Bootstrap

Table

4-4

These
listed

PROGRAMMING

List

describes

the

M9312-type

boot

ROMs
are used on all UNIBUS
are not required because the

contains
Many

ROM

bootstraps
the

devices

for

some

listed

ROMs

that

are

available.

processors.
Some of the
base ROM code in the_ CPU

ROMs
ROM

devices.

are

o0ld

and

generally

not

available
are included because many systems contain
these devices.
1In general, the ROMs needed to boot a device
are
shipped
with
the interface for the device itself.
For example,
if a customer purchased an RL0O2 and an RL11
controller
the
ROM
today,

would

The

However,

come

CPU

M9312
than

ROM

with

ROM
ROM

one

code
to

they

the

uses

controller.

two-letter

identify

bootstrap

fully

RL11

the

program.

implement

ROM.
Some

mnemonic
contained
1in
each
Some of the ROMs contain more
programs require more than
one

bootstrap.

TABLE

4-4

AVAILABLE

M9312

TYPE

tape

drive

23-761A9-00

TU60

cassette

23-756A9-00

RKO3,

RKO5

disk

23-756A9-00

TUS55,

TUS56

tape

Note: The RKO0S5
the CPU ROM

23-752A9-00

23-755A9-00

23-755A9-00"

drives
drives

boot

also

RKO6,

RKO7

disk

drives

RP02,

RP03

disk

drives.

mustbe
RP04,

installed
RPOS5,

drives.

23-759A9-00

RS03,

RS04

23-757A9-00

TUl6,

TElé,

tape

drives

RPO6,

This

disk

This

the

ROM

KTJ1l1-B.

RMO2,

ROM must

RMO3

disk

installed

drives

Tu45,

TM02,

TSO05

23-764A9-00

TS04,

TS11l,

TU80,

23-758A9-00

TUl0,

TE1l0,

TS03

23-760A9-00

PC0O5

High

23-760A9-00

Low

speéd

4-42

ROMS

TMO03,

tape

drives

speed

paper

reader

paper

reader

TU77

drives

(Teletype)

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

XE
XL

23-E22A9-00

DECnet

23-926A9-00
23-928A9-00

DL11-E (DECnet DDCMP)
NOTE: Three ROMs are required
to implement this bootstrap.

23-862A9-00

DMC11l,

23-863A9-00

NOTE: Three ROMs are required
to implement this bootstrap.

23-927A9-00

23-864A9-00

23-869A9-00
23-870A9-00
XW

DMR11

(DECnet

interface

DDCMP)

DUll (DECnet DDCMP)
NOTE: Three ROMs are reqguired
to implement this bootstrap.

23-868A9-00

DEUNA ethernet

23-865A9-00

DUPl1l

23-866A9-00

‘NOTE:Three

23-867A9-00

(DECnet

DDCMP)
ROMs are erquired

implement

this

bootstrap.

NOTE

v6.0 and
identifies

V7.0
ROMs

ROM

the

code,
UBA

the

routine
M9312

which

will

not
identify boot ROMs which use more
than
one
ROM
for
the
boot.
Because of this, these
boots will not list and can not be
started
from
the
base
ROM
code without using a small EEPROM
boot program to transfer
control
to
the
ROMs.
This
problem
will
be
corrected
in
a
future
correctly

release

Refer

the

CPU

to Appendix

ROM

for

the EEPROM to allow the
ROM boot on the UBA or
which is not compatible

for

The

boot

code.

instructions

set

CPU ROM to handle a multi
the
M9312,
or
any
ROM
with the M9312 ROM format

ROMs.

ROMs listed in Table 4-5 are
generally
not
needed
similar bootstrap programs are located in the base ROM on
module.

because

the

CPU

BOOTSTRAP

AND

MNEMONIC

DEC

TABLE

4-5

PART

NUMBER

PROGRAMMING

CPU

ROM

BOOT

PROGRAMS

SUPPORTED

DEVICES

23-765A9-00 TUS8 cartridge
tape drive
23-756A9-00

RKO5

23-751A9-00

RLO1,

23-767A9-00

(General boot for all Disk

disk

drive

RLO2

disk

drives

MSCP

devices)

RA60,

RC25,

RX50

RA80,

disk

RAS81,

23-753A9-00

RX01

floppy

disk

drive

23-811A9-00

RX02

floppy

disk

drive

EEPROM

first
ROM

drives

Format

105

parameters
the

ROM

4.5.2

The

DIAGNOSTIC

bytes

for

code

the
to

the

CPU,

EEPROM

the

determine

UBA,
the

stores
and

the

power

the

base

information

up/restart

hardware
needed

mode,

selections
and
the list of devices to try to boot.
Immediately
following the first 105 bytes are four bytes which the
user
use
for any purpose
bytes are never used

The

optional

such as storing a
by the ROM code.

bootstrap

programs

serial

number.

immediately

These

four

after

four

bytes.
The EEPROM may also contain translations for some of
the ROM code messages for local
1language
requirements
for
English users.
The local language text, if present always starts
at the end
layout.

the

EEPROM.

Figure

4-31

illustrates

the

EEPROM

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

Start

EEPROM

EEPROM size
2048 bytes.
==cececrcmrcc
e r em e
=
Base

CPU

.
105

Bytes

length

The

EEPROM

four bytes

parameters

Reserved

for customer use only?*

Optional

bootstrap

expand towards beginning
|
|

Hardware

Selection information

Variable Length

End

;

UBA

Boot device information
Translation table

Bytes

Variable

area.

and

Optional Foreign language text or
UFD area if no foreign language
~—cceccccccccccrccrrc
e rc e
e =

reserved

for

customer

use may be

accessed

follows:
l.

Insure

that

Insure

bit

Bit

the

EEPROM.

The

low

The

four

bit

the

reset

the

BCSR at

need

bytes

set

CPU
It

byte

addresses

€

the

not

the

CPU

BCSR

BCSR at

set

can

when

now

17765330.

set

reading

the

write
EEPROM.

17777522.

read

Each

17777520.

17777520 must be
be

PCR must

data

17765322

byte

written
is

accessed

in a 16-bit word where the data is in bits 7 thru
Bits 15 thru 8 are not driven by the CPU and must
ignored since their value will change.

FIGURE

serial

bytes,

the

first

three

This

1is

user.

number
format

bytes

only

1is

written

could

and

4-31

write

EEPROM

LAYOUT

the

write

checksum

suggestion

and

the

0.
be

four
to

for

24-bit

the

actual

customer-reserved
number

number

format

byte

the

BOOTSTRAP AND DIAGNOSTIC

ROM PROGRAMMING

When

the

data

after

written

the

write

EEPROM

cycle

for

the

each

user must

byte

before

wait

EEPROM
write

can not be written more
than
10,000
times.
the
data
should
always be checked after 10
it was written correctly.

that

least

proceeding.

The

-After
any
ms to verify
-

NOTE

not

strongly
be

set

recommended
wunless

the

that

bit

wuser

the

writing

EEPROM, and that it be reset as
soon
as
are
complete.
This bit does not have to
to read the EEPROM.

4.5.3

General

EEPROM

boots

Rules

are

ROM

code.

1If

ROM

code

will

pass

the

address

start

EEPROM

assembled

the

starting

For

there

in
an

User

Boots

into

the

lower

errors

are

control

the

program.

boot

EEPROM

boot

the

such

program

the

true:

Rl will be 0 if no address was passed
by
the
translation
table
or the /A switch in the boot command.
Rl will be an
alternate address for the program to use if the translation
table
matches
the boot device's name and unit number with
an entry in the translation table or the /A switch was used
in the boot command.

The ROM code loads a trap handler for timouts to location 4
in
memory.
The program is loaded into memory starting at
location 1000 if the
start
address
of
the
EEPROM
boot
program
1is
10000
or greater.
The program is loaded into
memory

starting

the

EEPROM

load

the

unit

address

program
of

bit mode

is off.

number.

location

boot

errors

according

Memory management
the

and

of memory by

checksum

contains

is disabled

the

writes
be set

K words

following

BCSR

the

17600

timout

the

to 7776.
handler

start

The

into

address

rom code will

location

long
as the EEPROM boot does not already occupy location 4
itself.
If a timout occurs during the boot program and the
timout
handler is entered the handler will restart the rom
code

with

the

non

existent

controller message

rom code will assume that the value
the controller that timed out.

the

and

address

the

BOOTSTRAP AND DIAGNOSTIC ROM' PROGRAMMING

The

EEPROM may

the

use

memory

EEPROM

program

Instruction

PAR/PDRs

other

PAR/

restricts

0-3

and

PDRs

the

ROM
the

code should be recase
where
the

responsibility

and

the

check

the

wuse

The

EEPROM

ROM

code

EEPROM

boot

the

user's

bootable

The

block

that

EEPROM

addresses
recommended

addresses

above

boot

2000

for

code

only

not

Kernel

use

any

restarted.

The

In
the

timeouts.

boot

the

secondary

boot

program.

not

16000

8K-word

ROM

(MMRO bit0 ="0).
location 4, it is

programs

location
the

MMU

program

2300,

the

boot must

handle

for

40000.

started with MMU OFF
EEPROM boot overlaps

boot

restart

the

between

memory

and

responsibility

recommended

memory
to

management

device

1located

16040,

and

EEPROM

boot

point

(Physical

1in

20000

programs

1is

address

00040000).
The following
paragraphs
describe
the
programs should handle errors or success.
the

user

write

programs that adhere to
wuser to receive meaningful

allow

the

errors

occur

program

need

not

Once

the

boot

return

EEPROM

boot

program.

control

way

user-written

recommended

these
rules.
messages in the
However,

not

boot

the

that

This
event

will
that

user's

boot

desired.

1is

started
the
user
boot
program
has
complete
control
of
the CPU.
The user's program would restart
the ROM code for one of the following three reasons:

error

code

allows

occurred

attempting

restarted

the

automatic

type

out

boot

boot
a

mode

booting.
To

reenter

user’'s

the

boot

ROM

desired,

make

and

then

execute

The

following

message

code

program

sure
a

list

selection

for

and
the
error message.

try

error

would

device

general

1load

another

message

with

the

item

for

printing,

the

error

message

that bits 7 - 4 of the BCSR are
JMP @ 165762 with the MMU off.

set

specifies

the

octal

the

codes

the

text

and

At the time the
ROM
code
1is
contain
the unit number and Rl
the controller.

should

270

Drive

271

Non

272

273
274

=
=

No tape present
Non existent controller

275

Non

not

the

message

contain

ready

bootable media
disk

value

restarted,

present

existent

drive

4-47

present
drive

unloaded

ROM
This

error

printed.

should

the

still

address

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

the

276

Invalid

277
300
301

=
=
=

Invalid device
Controller error
Drive error

unit

number

user's

program monitors

the

keyboard

during

the

boot

it
could
return control to the ROM code if CTRL C is typed.
This 1s an optional feature.
The ROM code would be reentered
the
same way as described in 1 above with the exception that
R5

should

The boot

successful

and

the

restarted

After

octal

the message

control

print
load

the

value

out

printout
wuser's

equal

the

ROM

the

301

1is

system

complete

program.

<code

"Starting

270

the

temporarily

the

ROM

code

the user's boot at the

completed

typing

code

code
would
of the BCSR

ROM code by executing

ROM

control

has

the

" message.
code
returns

ROM

reenter

from

the "Starting system message"
the
wuser's
R5
with the number 1, make sure bits 7 - 4

are 0 and then restart
@ 165762 with MMU off.

When

not

the message

JSR

PC,

returns

instruction following the

JSR instruction.
At this point, to be
compatible
with
all
existing
versions of the ROM code, the user'’'s program should
do

the

Reset

following:

bit

(register

set

select)

the

PSW

Reset the display register by writing 000077
777

address

524.

Clear MMR3

(17

772

4.6 BOOT ROM FACILITY

516)

to make sure

22-bit mode

off.

(M9312 compatible)

M9312
install
to
The KTJ11-B Boot ROM Facility allows the user
not
are
which
devices
UNIBUS
for
written
programs
boot
compatible
directly supported

the

KDJ11l-B

boot

programs.

ROM

programs

The M9312
M9312 should work on the KTJ11-B.
the
on
run
which
512
four
to
one
from
in
compatible boot programs are implemented

4 bit ROM's.

Each ROM contains 64,

16-bit words of accessible

code which are located in the first half of the
256 4-bit ROM locations are not used.

ROM.

the

last

from
The KDJ11-B CPU Module can be configured to boot the system
self-contained boot programs, from the KTJ11-B Boot
1its
of
one
ROM facility,

or a boot ROM option which resides on the UNIBUS.

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

The

first

word

contains

ASCII

identifier which

consists

of two characters with a zero parity bit.
The high and low
bytes contain the first and second characters respectively.
The
characters are used by- the KDJ11-B Boot and Diragnostic
ROM programs to search for the selected boot program.
The
KTJ11-B ROM codes requires that both of these bytes contain
characters with ASCII octal values of 101 to 132 or 141
to
172

(A-2

The

second

a-2).
word

contains

offset

from

its

address

the

start of the next program header.
1If the ROM contains only
one header, the second word,
1located
in
ROM
Address
2,
contains 176, which points to start of the next ROM.

The

third

word

zero,

used

branch

KTJ11-B
The

systems

fourth

the

systems

diagnostics

unit zero,
branch to
KTJ11-B

address

word

Power-up

containing

prior

not use

address

entry

the

running

the

this

entry

point.

point

M9312

alternative

for

boot

not

use

this

entry

program.

entry point

used by systems containing the M9312 to
diagnostics
before
running
the
boot

systems

unit

disable

for

enable a
program

point.

The fifth word
contains
0,
indicating
instruction located in the previous word.

wunit

for

the

The sixth word address is the entry point used
by
systems
containing
the
M9312
for
unit
numbers other than zero.
KDJ11-B uses this entry point after first loading the
unit
number
Carry

The

(zero
Bit

non-zero)

(disabling

seventh word

the

into

and

branch

M9312

contains

the

address

then

setting

the

PSW

diagnostics).

the

to be booted.
previous word.

Control/Status

used

the

The eighth word contains an instruction which saves the
PC
in
R4
for systems which branch to diagnostics on the next
instruction.
The KDJ11-B uses this entry point when a
non
standard

CSR

address

passed

Rl.

The ninth word contains an instruction
which
branches
to
M9312
diagnostics
if the PSW carry bit is clear.
KTJ11l-B

The

tenth

start

word
the

set

the

carry

contains

boot

program.

10.

always

systems

bit.

unconditional

branch

the

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

4.6.7

ROM Data Organization

Each 512 X 4 bit ROM contains 64, 16-bit words of accessible code
which are located in the first half of the ROM.
Each lé6sbit word
is stored in four successive ROM locations.
Whenever the KTJ1l1l-B
1logic is addressed by a Data-In operation, it constructs the
ROM
l16-bit word
from
the
appropriate
ROM
1locations.
Table
4-7
location and polarity of bits within each group of
the
presents
four nibbles.
Note that bits 12, 11, and 10
are
1inverted,
and
bits 08 and 00 are not stored in the expected order.
TABLE

4-7

ROM

DATA ORGANIZATION

Bit

J11

~Bit

02
06
10*

Bit

01
05
09

Nibble Number 0
Nibble Number 1
Nibble Number 2

03
07
11*

* Data Word Bits 12,

11 and 10 are stored

Nibble Number 3

4.7

Data

MICRO

Bit 0

08
04
00

12*

inverted

ODT

J11 Micro ODT is entered anytime the CPU is halted by:

Placing the front panel toggle switch in the HALT position,

Executing a HALT instruction, if the halt mode is

and the system is

enabled,

in kernel, or

Pressing the Break key, 1if the terminal is setup to
generate a Break character, and the front panel keylock
switch

set

to ENABLE.

J1]1 Micro ODT allows the user to examine and/or change any
location in the 22-bit CPU memory space or I/0 page memory space.
In addition, J11 Micro ODT allows the user to; start

program,

to reinitiate program execution and to single step a program when
the front panel toggle switch is in the HALT position. Table 4-8
summarizes the J11 micro ODT commands.

BOOTSTRAP AND DIAGNOSTIC ROM' PROGRAMMING

TABLE 4-9 J11 MICRO ODT COMMAND SUMMARY

Slash

Opens

the specified

location (n) and
n
its contents.
octal number.

outputs
1s an

Carriage Return

<CR>

Closes an open location.

Line Feed

<LF>

Closes an open location
and then opens the next
contiguous location.

Internal Register

$n or Rn

Opens a specific processor
register (n). n is an
integer from 0 to 7 or
character

Processor Status
Word Designator

the

Opens the Processor Status
Register. Must follow the
S

R command.

Proceed

Resumes program execution.

Control-Shift-S

Manufacturing

Binary

Dump

Starts program execution.

use

only.

The following paragraphs provide a detail description of each Jl1
Micro
ODT
command
specified in Table 4-9.
In most cases, each
description is supplied with
an
example.
Note
that
operator
input

When

underlined.

entering

they will
When

will
is

or data,

leading

zero's are

not

required,

ODT.

addresses

(i.e.

addresses
error

addresses
filled

entering

entered
A

the

I/0

page,

all

22bits

must

Dbe

17776100).
printed

are

whenever:

accessed

detected.

that

1illegal

characters

result

1in

are

timeout,

entered,

or a parity

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

4.7.1
This

(ASCII

command

057)

and

location,

Slash

used

open

memory

location,

I/O

internal
processor register, or processor
must be proceeded by
octal
digits
to
a

tegister

device

status word
specify
a

designator.

In response to /, ODT prints the contents of that location
six characters)
be entered or a

(i.e.

and waits for either data 33 for that location
valid close command (i.e.) <CR> or <LF>.
The

may
be
entered again immediately
previously opened location.

to display

the

contents

to
/
the

Examples:
@1000/

012737

<CR>

;Open memory

location

00001000.

+ The contents (012737) are
;displayed. <CR> closes the
:slocation without modification.

@100/

000200

7422

<CR>

;Open memory

location

00000100

sand deposit data (7422)
;close the location.

€/ 007422 6422 <CR>

;Re-open the location and deposit

4,7.2

<CR>

(ASCII

This command
contents are

the

see

<KLF>

This

command

location

no change

Return

Line

same

opened.

desired,

<CR>

closes

the

1location

examples.

Feed
<CR>

except

contiguous

incremented

by one.

contents.

012)

the

are

incremented

Carriage

and

addresses

015)

its

(ASCII

4.7.3

closed

1If

altering

Examples:

snew data.

i1s used to close an open location.
If a
1location's
to be changed, the user should precede the <CR> with

new data.

without

and

the

location
and

open

processor

is opened

1location

opened.

1is

Memory

registers

are

is closed and no new

BOOTSTRAP AND DIAGNOSTIC

ROM PROGRAMMING

Examples:

@1000/

012737

<LF>

sLocation
;contents
;then

00001002

100200

<LF>

s The

1000

opened,

are displayed,
closed with <LF>.

<LF>

;location

caused

the

to be

opened

the
and

next
and

the

;contents to be displayed. In
;this case the contents are
;changed

00001004

176100

<CR>

; The

the

operator.

location

opened

+t0 examine the contents
sthen closed with <CR>.

4.7.4

$ (ASCII 044)

Either

character

designator

more than one
typed will be

or R (ASCII 122) Internal Register Designator

when

and

followed

will

number
used.

open

that

typed

specific

after

the

number

processor

the

1If

the

last

number

NOTE

The

trace

bit

(bit

<4>)

the

cannot

modified
by
the user.
This is because ODT uses
the T bit for single-stepping.
The register
set
used
with the R command is determined by PS<11>.

PS<11l>

set

used.

PS<11>=0

used.

The

used

set

one

will

set zero will
is determined

be
by

PS<15:14>.

4.7.5

This

(ASCII

command

entered

107)

used

immediately

start

before

program

the

execution

This

function

the LOAD
ADDRESS
and
START
switch
sequence
on
consoles.
The PC (R7)
is loaded with the address (0
1f no data is entered), the following registers
are

Zero:

PS5,

System

Error

Status

the

HALT

the

command

position,

reentered

typed

MMR0O<15:13,0>,

and

address
in

the

Cache

is
the
PC

MMR3,

Cache

issued

flushed

with

system
will

PIRQ,

Control

and

the

will

CPU

the

front
be

4-55

panel

switch

bits,

Memory

Floating

i.e.

Point

initialized.

ODT

command

1730000G.

other
PDP11
will be used
cleared
to

UNIBUS

The

sixteen
read

location

and

initialized,

displayed.

typed in to the last
7777773000G it would be

Error

equivalent

the

will

truncates

the

user

Since

the

BOOTSTRAP
memory

AND

DIAGNOSTIC

management

starting

157776)

address

the

PROGRAMMING

unit
1is
always in

I/0

ROM

disabled

the

lower

page.

the

Go
command, the
words of memory (0 -

Examples:

@1000G

.;The program is started at location 1000.

@1000G

;The

program

is started

;on.

The

initializes

;halts

@1000

4.7.6

This

;The

(ASCII

command

corresponds
Program

120)

without

the

wused

the

P command

resume

CONTINUE

resumes

executing

displayed

(R7).
The next instruction
interrupts will be serviced.

with

and

printed.

step

through

issued

In - this
a

Halt

switch

and

the

first

instruction.

then

the

ODT prompt.

execution

switch

the

address

fetched

with

the

other

then

and

front

program

fashion,
and

obtain

the
a

consoles.

the
PC
outstanding

switch

can

single-instruction

"trace"

the

(PC)

is opened and

console

Example:

1000

<CR>

;R7
|

;contents
;address

displayed.
is

entered

the

The
in

new

R7.

sand the program
s location 1000.

command

issued

epP

s The proceed command

issued

001004

sHalt position.
sdisplayed.

;

001010

;

s The proceed

swith

;Etc.

the

end
of
instruction
of the PC (R7)
will

terminal.

@R7/002464

and

executed,

panel

user

program

PDPll

pointed

HALT
position
it
is
recognized
at
the
execution and ODT is reentered.
The content
be

the

registers

Proceed

execution

CPU

continues

front panel

switch

The

the

BOOTSTRAP AND DIAGNOSTIC ROM PROGRAMMING

4.7.7

(Control-Shift-S)

Binary Dump

This command is used for test purposes by manufacturing
and
1is
not a normal user command.
The command is normally received from
another
computer
and
not
by
the
console
terminal.”
It
1is
recommended
that
this
command
NOT
be issued from the console
terminal because the console ODT echoes back the
ASCII
and
may
cause the keyboard to lockup, thus preventing
being

displayed

There

the

no reason to

23
code
data from

screen.

issue this command

from a terminal

because

it
dumps the binary data and the terminal is intended to receive
the ASCII data.
The
command
1is
intended
to
more
efficently
display
a portion of the memory as compared to using the "/" and
<LF>

commands.

This command can be
accidently
entered
on
many
terminals
by
typing
CTRL
S,
CTRL s or in many cases by the " NO SCROLL" key
since all these conditions normally generate the ASCII
23
code.

the user accidently enters

recommended

that

minimum of three

the

times

user

this command,

reset

the

in order to

ready to accept commands

term-

in order to exit,

inal

and

type

"a"

it
a

insure that the console ODT is

again.

The

command

protocol

1is

follows:

After a prompt character,
and echoes it.

The host system at the other end of the
serial 1line
must
send
two
8-bit
bytes
interpreted by ODT as the starting
address.
These two bytes are not echoed.
The
first
byte
specifies
<07:00> of
are

the
may
3.

always

receives

bits
<K15:08> and the
the startina address.
forced

first 32K words
be even or odd.

address

After

the

outputs
address

ODT

second

address

bytes

previously

prints

<CR>,

the

specified.

<LF>,

€.

CTRL

commands

second byte specifies bits
Bus address bits
<21:16>

DUMP

command

space.

byte

the

The

has

serial
When

been

1line,
the

restricted

starting

received,

starting

output

address

ODT

the

finished

CHAPTER
SYSTEM

5.1

MAINTENANCE

INTRODUCTION

This chapter
c¢ontains
troubleshooting
information,
diagnostic
error
message
interpretation,
and field replaceable unit (FRU)
removal

and

replacement

5.2

DIAGNOSTIC

The

system

TYPES

supports

DECX1ll

each

procedures.

three

provides

option

and

types

system

diagnostic

tests

1isolate

check

system

programs:

the

failures

interaction

the

subsystem

component

XXDP+ - provides tests that check
localize

ROM

Resident

various
bus, and

The

following

various
XXDP+

hardware
CPU

XXDP+

functions

diagnostic

the

OKDA??

(KDJ1ll-BF)

OKTA??

(KTJ1l1-B)

function

Start-up

three

options

and

level.
diagnostics

test

to the system modules and PMI
the module or option level.

programs

system must

diagnostics.

individual

the

ROM-resident

functions
specific
isolate failures to

diagnostic

start-up

failures

are

kernel
first

available

modules.

successfully

test

initiate

complete

an
the

SYSTEM

MAINTENANCE

VMJA??

(MSV11-J)
depending

(Run
time
1is
on memory size.)

approximately

The "??" at the end of

the

name

that

To load and execute a

diagnostic,

minutes

latest

diagnostic

followed
.

The

by
R

the

three

The

start-up

kernel

executed when

1issue

name.

For

listed

below,

assures

called.

the

RUN

(R)

the

command

example:

<KCR>

diagnostics,

power

diagnostic

OKDA??

start-up

system

version

diagnostic

restart.

are

They provide

executed

a quick

during

evaluation of

modules.

diagnostics

check

the

following

system

functions:

Processor:
Verify
CPU
and
FPA
functionality
and
test
communications between the CPU cache and the CPU.
Disables.
all data paths between system devices and
the
main
(PMI)
memory,

but

not

Main Memory:
UNIBUS

the

failure

cache

memory.

Tests the main memory usifig the PMI protocol.

Adapter:

communication,
UNIBUS

CPU

Tests

and

the

UNIBUS

addressing

adapter,

its

PMI

and control paths with the

disabled.

any

point during

these

diagnostics

halts

the

testing

and:

Displays an error code and
terminnal (if connected).

Displays

an error

Displays

the error code

Normally,

the

code

system displays

an error message

the

front panel

the

START-UP display.

in the CPU module diagnostic
the

same error

console

information

LEDs.
in

all

three
LOcations.
If the console terminal is not working, refer
to the START-UP TEST display.
If neither
1location
1is
working,
refer

5.3

the

CONSOLE

A typical

CPU module

TERMINAL

LEDs.

ERROR

MESSAGE

console error message

FORMAT

shown

in Figure

5-1.

SYSTEM

Testing in progress
Memory Size is 1024
9

Step

memory

Step

test

CSR

=
=

PC=

173436

060000
100000

Command

PCR page=
R1
RS

=
=

Map memory

command

Console

console

=
=

172100
172300

R3 =
Par3

015436

172344
= 010000

test

then

press

5-1

Error

error

and

message

lists

the

probable

causes.

description

error

the

RETURN

key:

DISPLAY

5-2

"See

Description

contains

the

following

the octal
failed.

error

number

codes,

this

test

lists

the

error messages

troubleshooting

address

listing
In

information:
of

the

start-up

descriptions,

one-line

and

documentation"

and

description

the

reference

the

their

descriptions.

message.

Error address line - this address line
PC (Error PC=), the page number in the
the

EXAMPLE

error.

Table
A

the

Message

error code - this
diagnostic test that

5-1

I/O page

ERROR MESSAGE

Table

R2
R6

address=

test

FIGURE

The

Program listing

Description

Loop

052525
040000

Rerun

5.3.1

documentation

1
2

Type

Error

troubleshooting

Error
RO
R4

wait

Error
Memory

See

- Please
K Bytes

MAINTENANCE

specifies the
error
ROM (PCR page=), and

program

1listing

(Program

address=)
case

unexpected

|
traps,

5-3

the

error

address

the

SYSTEM

MAINTENANCE

address
following
unexpected trap.

the

instruction

which

The content of RO-R6 of register set 0, and
kernel
PAR
3.
The
tests
do
not
wuse

used mainly

some

tests

the

system

expected

data,

and

the

A
To

command

(e.g.,

line

execute

Rerun

which

etc.)

the

test.

ROM

displays

received

enter

followed

the

code

the

data

describes

command

caused

the content
register set

support

failing

(bad

associated

RETURN.

test

passes

of
1.

routines.

address,

the

data).

user-selectable

the

The

commands.

command

commands

the

ROM

number

are:

code

will

continue testing.
If all other tests pass, the ROM code
will display the total number of errors and enter dialog
mode regardless of the mode selection in the EEPROM.
2.

Loop

test.

This

continuously
1loop
are generally very
as scope loops.
The

test

runs

option

<causes

the

ROM

code

on the test that failed.
These loops
large and are not intended to be used

until

error

occurs

end-of-test

has

been reached.
1In either case, the test is started again
and continues to loop until the user types CTRL C at the
console.
At
this point, the ROM code will display the
total
number
of
errors
and
the
total
number
of
successful passes if any.
Both the error counter
and
the
pass
counter
have
a
maximum
value of 65535.
If either counter reaches this
value the count will not overflow to zero, it will
stay
at this value.
3.

Map memory

and I/O page.
This command is normally
used
if a memory error occurs.
-If a memory is not configured
properly the MAP command may point to where
the
memory
actually is.
In

multi

memory

system

which

one

the

memory

fails this command can be used as a method of physically
identifying the failing memory, if it has a CSR.
This

on.
76

command

The
through

is only available when
command is not available
56.

the
for

bus
tests

1is

(or

turned
codes)
|

SYSTEM

Advance

the

to
bypass
will
only

test.

This

command

MAINTENANCE

allows

the

user

the failing test and continue.
This command
show
up
for
errors
that
are.
generally

considered

non

fatal.

]

If the error is fatal and field service
would
1like
bypass
the error it is possible by typing CTRL O, 4
RETURN,

and

the

command

will

executed.

to
and

CAUTION:
Errors

should

software

this

point

previously

TABLE

has

the

typed

5-1

not

ROM

ERROR

CODES,

TEST

DESCRIPTION

Initially
value

flushes

TEST

unless

all

wuser

write-protected.

it's

charactersand waits

ERROR

bypassed

removed

code

CODE

been

for

1input

input

DESCRIPTIONS

buffer

from

AND

the

user.

PROBABLE

CAUSES

PROBABLE

set

- CAUSE

power

this

up.

The

halt

switch

BGn

NPG

up
.
A

UNIBUS

is open and
asserted by
All

grant

line

SACK is being
the bus.

cards

must

installed.
Terminator
Power

First

CPU

Turn
and

tests,

MMU

M8190

MMU

M8190

supply

on.

Run

tests.

Turn on PMI and look
at the UBA RESTART bit.
Then

tests

MMU
CPU

turn

off

any

PMI.

M8190,

M8191

faulty.
is

faulty.

power.

SYSTEM

MAINTENANCE

TABLE

5-1

TEST

PROBABLE

DESCRIPTION

Power

CAUSE

ODT.

NOT

FAILURE

Selected

Mode is ODT in EEPROM and
the system is in (J11)ODT
72

Power

EEPROM

24/26.

checksum

tests.

M8190,

M8191

EEPROM

accidentally

restore

data

using

written,

Set

commands, verify W40
on M1890 module.
70

CPU ROM checksum ahd PCR

up mode
installed

M8190

tests.

Miscellaneous

CPU

and

EIS

M8190

tests.

Console
check

SLU

for

test

each

M8190

response

Console

SLU test 2 transmit and receive
in maintenance mode.
Console

SLU

test

M8190
data

M8190

check interrupts and
errors in maintenance
mode
.
63

Test

Stand-alone

MMU

M8190

aborts.

cache

tests.

Clock

test.

mode

M8190

CPU

M8190
Clock

Floating

Point

Processor.

from power

supply

M8190

Unused.
............................

.. ’_------------------—---—-----

5-6

SYSTEM

TABLE

5-1

(Cont)

TEST

PROBABLE"

CAUSE

Exit

stand-alone

mode.

M8191

Check location of address
17760000for timeout.

M8190

UBA

M8191

response

test, check UNIBUS through
DDR for hung lines.

UNIBUS

failure

M8190
54

Memory

size

Check

memory

location
52

Cache

word

tests

PMI

memory

test.

PMI

memory/M8190

present

memory

testing

Memory

using

PMI

M8190

test
byte

Data

PMI

memory

PMI

memory

PMI

memory

tests.

Memory

parity/ECC

Memory

address/shorts

tests.

test.

45
44

UBA

ROM

UBA map

test.

M8191

registers

data

M8191

test.

UBA

unmapped

M8191

diagnostic

M8191

test.

UBA

floating

test

using

nostic

diagnostic

test.

UBA mapped

cycles

response

path

cycles

failure

memory.

UNIBUS

test.

address/data

mapped

cycles.

diag-

M8191

MAINTENANCE

SYSTEM

MAINTENANCE
TABLE

5-1

TEST

PROBABLE

DESCRIPTION

UBA

address

UBA

cache

CAUSE

overflow

data

M8191

test.

PMI

UBA

cache

Recently

UBA

LRU

(Least

Used)

test.

cache

address

M8191

floating

test

memory

TAG

store.

UBA

cache

detection

UNIBUS

parity

M8191

error

test.

memory

data

UNIBUS

path

memory

test.

M8191

UNIBUS

logic

memory

parity

UNIBUS

memory

address/

UNIBUS

memory

test.

UNIBUS

memory

shorts

test.

NOTE

With the exception of error codes 25, 22 and 6, codes
30 through 1 are bootstrap problem indicators and are
not

diagnostic

errors.

bootstrap

problems

Some
may

cators

Test

Unused

corrected
of

Exit

Unused

errors

Routine

by
in

the
the

(e.g.,

disk,

user. Others
device being

tape,

etc.)

may be indibootstraped

SYSTEM MAINTENANCE
TABLE

ERROR

5-1

TEST

CAUSE

Air

mover

regulator

and

voltage

Cabinet

blower

test.
Box

fans

H7213

regulator module

MLM module not installed
No memory

module(s)

system.

24
23

Unused
XON

not

XOFF,

CTRL

received

after

correct,

the

type

console.

Console terminal not ready
due to XOFF signal received
from terminal while attempting to print a message.
This is normally not considered a failure, because
the condition could be operator error. If the operator has typed CTRL S with-

out following with CTRL Q
or the terminal is not
ready,(e.g. could have run
out of paper).
22

Console

SLU

ready bit

Drive

transmit

not

M8190

set.

error.

The

device

that

the

user

attempting to boot is displaying an error code in its
error register. Verify that
media is in good condition
and bootable.
20

Controller

error.

The

UNIBUS
the device
attempting

controller for
the customer is

displaying an

boot

error

code

SYSTEM

MAINTENANCE

TABLE

TEST
DESCRIPTION

ERROR
CODE

5-1

(Cont)

PROBABLE
CAUSE

)

in its control and status
register (CSR). Ensure
that the NPG jumper was
removed if the device is a
DMA

controller.

Consult

the devices technical
manual for more

information.
17

Invalid

device.

The

mnemonic

typed

for

the boot device is either
incorrect or the boot rom
for that device is not

installed .Go to the
dialog mode and "LIST"
valid devices.
l6

Invalid

unit

Non-existent

number.

The unit number after the
mnemonic is not within
acceptable range for that

drive.

device. See that
technical manual

devices
for help.

The

the

drive

number

is trying to boot
not on the 11/84.
14

Non-existent

The

controller

vice

the user

to boot
UNIBUS

from

or is
incorrectly.

tape

disk present or drive
not loaded correctly.

is
11

present.

Non-bootable

the

drive.

media

the

tape

the

de-

for

is trying
is

not

to
the

addressed

installed.

No media in drive
drive LOAD button
The

user

from

not

the

in.

bootstrap data from
the device does not conform to the boot block
specifications. Ensure
that media is bootable.

SYSTEM

TABLE

ERROR

TEST

CODE

DESCRIPTION

5-1

(Cont)

PROBABLE
CAUSE

bootable.
mode

Change

Drive

not

Console

Unused.

Dialog

ready.

UBA

disabled.
-

Self

mode.

ROM

EEPROM

CPU

ROM

boot

The

boot
boot

in
in
in

boot

blocks.

No media present in the
drive or the disk drive
has not completed its spin
up function.

explanatory.

system

and waiting
the console
rewind.
3

Setup

non-standard
10

MAINTENANCE

progress.
progress.
progress.

Blank

dialog

for input from
terminal to

May

take

few

seconds.

May

take

few

seconds.

May

take

for

some

devices.

Program

mode

control

minutes

has

been

transfered to: a secondary
boot, an EEPROM boot, or a
UBA/M9312 boot.

5-11

SYSTEM

MAINTENANCE

TABLE

5-2

START-UP

ERROR

MESSAGE

M8190

CPU

M8190

Error

M8190

CPU

ROM

M8190

EEPROM

Cache

DIAGNOSTIC

ERROR

MESSAGE

DESCRIPTIONS

DESCRIPTION

Error

CPU

cache

CPU

Floating

Error

CPU

ROM

checksum

CPU

EEPROM

CPU

clock

logic

clock

error

logic

error

point

logic

error

checksum

logic

checksum error

Error

M8190

clock

Error
:

M8190
UNIBUS

CPU

Error

signal

No memory

Other

Error

location

CPU

UNIBUS

Memory

error

power

always

supply

errors
signal

failed

asserted

addressed

incorrectly
Memory

Error

General

Memory

CSR

Memory

Error

ECC

M8191

UBA Cache

M8191

UBA

Unexpected

Error

location

5.3.2

Unexpected

Figure 5-2 shows
displayed
when
unexpected traps

errors

test

during

errors

parity

testing

UBA Cache

Error
trap

memory

error

Other

UBA errors

This

general

error message

that occurs during any unexpected
traps. The address of the trap
follows this message.

Trap

and

MMU

Error

Code

Descriptions

an
example
of
the
error
code
and
message
an
unexpected trap occurs.
The error number of
is always the current test number plus 100,
NOTE

Operator input
examples.

underlined
5-12

the

following

SYSTEM

MAINTENANCE

The actual
In the example the error code (or test number) is 62.
will
display
Test
Start-up
The
162.
as
read
1is
code
error
display.
two-digit
a
only
is
it
since
62
only
display

Unexpected traps are always considered fatal errors.
Testing

in progress

162

Error

Unexpected

trap

- Please wait
250 MMU

to location

See troubleshooting documentation

Updated PC= 173436
RO = 101365
R4 = 101367

PCR page=

Rl = 076410
R5 = 000250

Command

Description

1
2

Rerun test
Loop on test

Type

command

then press

FIGURE

5-2

15 Program listing address= 015436
R2 = 177746
R6 = 172276

the

RETURN

R3 = 177744
Par3 = 052400

key:

UNEXPECTED TRAP

ERROR EXAMPLE

For codes 76 and 75, the ROM code displays the
single
letter
E
followed by the test number.
(See Figure 5-3.) After the message
is displayed, the ROM code will not except any input.
The
only
option
for
¢the
user
1is
to
restart
the system or repair the
problem.

FIGURE

5-3

5.3.3

Boot

Program Error

Error
with

codes 21 through 10
the
boot
programs

EXAMPLE

OF TEST

ERROR

Codes/Messages
(described in Table
for
disks, tapes,
5-13

5-1) are associated
and DECNET devices.

SYSTEM

MAINTENANCE

These

errors

are

applicable

programs,
and
any
EEPROM
errors back to the CPU ROM.
UBA or M9312-type ROM boots.

Figures
when

5-4

the

and 5-5

BOOT

for

show examples

command

all

CPU

ROM-resident

used

error

Dialog

mode.

from a

Commands are Help, Boot, List, Setup, Map
Type a command then press the RETURN key:
Trying

12
present,

disk

drive

Command

Description

Reboot
Go to Dialog

then

press

FIGURE

5-4

BOOT

Help,

Boot,

are

command

Trying

DL3

Message

Non

existent

then

not

loaded

correctly

press

the

RETURN

PROGRAM

List,
the

key:

ERROR

Setup,

EXAMPLE

Map

RETURN key:

FIGURE

error

the

and
B

Test.

DL3

<CR>

drive

Commands are Help, Boot, List, Setup, Map
Type a command then press the RETURN key:

When

and Test.
B DL1 <CR>

mode

command

Commands
Type

program

Message

boot

DL1

Type

boot

boots that are written to pass these
Only errors 14, 16, and 17 apply
to

5-5

BOOT

ERROR

MESSAGE

and

Test.

EXAMPLE

ROM code enters the automatic
boot
sequence
all
messages are suppressed on the first pass through the

boot

list
of boot devices.
If no device
1is
successfully
booted
on
the
first
pass the ROM code will restart the automatic boot sequence
and try to boot all of the selected devices again and display all
applicable error messages.
-

SYSTEM

MAINTENANCE

When the ROM code has failed to boot any of the devices
selected
Figure 5-6
automatic boot list, Dialog mode is entered.
the
in
shows an example of a boot error display when the automatic
boot
sequence
failed
to
find
a
bootable device and Dialog mode is
entered.

Testing in progress - Please
Memory Size is 1024 K Bytes
9

Step

memory

Step

Starting

wait

test

3456

automatic

Trying DUO
Trying DUl
Trying DU2
Trying DU3
Trying DLO

boot

No disk present, or drive
Non bootable media in the
Drive not ready
Drive Error
No disk present, or drive

1is not
drive

loaded

Commands are Help, Boot, List, Setup, Map
Type a command then press the RETURN key:

FIGURE

5-6

AUTOMATIC

BOOT

5.4

SYSTEM

TROUBLESHOOTING AIDS

The

system

provides

the

following

LED monitors

Voltage

test

points

Monitor

logic

with

The
5-7

LEDs are located
shows the front

shows the location
monitor logic with

5.4.1

Front

The

front

the

keylock

power

audible

ERROR

not

and

MESSAGE

troubleshooting

Test.

EXAMPLE

aids:

alarm.

on the front panel and the modules.
Figure
panel monitor LED labeled DC ON.
Figure 5-8

of each
module
LED.
The
test
points
alarm are located on the MDM module.

and

Panel

panel

indicator

monitors

main

power

supply.(See

Figure

switch

the

ENABLE,

supplied

the

power

SECURE,

supply.
5-15

the

5-7.)
or

When

output

the

STANDBY

voltages

front

panel

positions,

SYSTEM

MAINTENANCE

the

supply
located

LED

OFF,

the

regulators.
Each
on the MDM module.

probable

cause

regulator
.

has

—

one

the

power

specific LED monitor
-

BOE0030

st
SECURtE

PDP-11/84

Lsun-u' TEST

STANDSY
Cocow

—utsurr

O mm

_ - AUN

D BATTERY

E e ALY

)
RSNt

FIGURE

5.4.2
The

MDM

5-7

SYSTEM

FRONT

Module

MDM module

provides

LEDs that
2-8).

Test

Blower/fan

the

following

monitor most

points

for

power

checking

troubleshooting

supply

voltages

power

supply

rotation monitoring

logic.

Figure 5-9 shows the location.of the MDM

points.
voltages.

PANEL

LEDs D1 through D5
Loss of a voltage

aids:

(see

Figure

voltages.

module

LEDs

and

each monitor one or two power
turns the associated LED off.

test

supply

The

tolerance for each voltage should be within +/- 10%,
checked
on the test points located above the LEDs.
If a voltage is found
to be out of tolerance or not present, one of
the
power
supply
regulators specified in Table 5-3 is the probable fault.
The

rotation

monitor

logic

indirectly

checks

the

+12

Vdc.

the

blower/fans
fail
to
send
a
rotation-based pulse, the monitor
logic causes an audible alarm to sound and powers down the system
one minute later.

SYSTEM

+5V

MAIN

+5VBB
+/-15V

POWER
+12V

MAIN

FAULT

ISOLATION

SUPPLY

H7200

H7202-KA

BLOWER/FAN

H7213

H7202-KA

H7211

H7202-KA

H7200

H7202-KB

H7211

H7202-KB

POWER

EXPANSION

+/-15V

REGULATOR

SUPPLY

POWER

EXPANSION

SUPPLY

POWER

SUPPLY

CARD CAGE
TOP FOR CABINET
4

wnflflflflflflfl

D1 = ERROR LED

(RED)

MDM

"Nt

|
s

MDM iN7677

= +5V (MAIN POWER SUPPLY)
D2= +5V BB AND « 12V (BLOWER FANS!

REAR FOR BOX

)

D3 = «15V AND - 15V (MAIN POWER SUPPLY)
D4 = +5V (EXPANSION POWER SUPPLY!
DS = +15V and - 15V (EXPANSION POWER SUPPLY)
DIAGNOST!IC LEDs
~—==~DCOK POWER LED (GREEN:

DIAGNOSTIC LEDs

LS8

D2 = 5V BB POWER
(GREEN)

02
= -15V (OFF)
MINIMUM LOAD

MODULE cmsss)\'h‘

+5V

AND

SUPPLY

&/r-fl

POWER

9 .

5-3

TABLE

MAINTENANCE

D1 = +5v BB MAIN POWER SUPPLY (RED!

MSV11-J8.JC MEMORY (MBE37-BA/CA)

KDJ11-BF (MB190)

‘\l

==—MINIMUM LOAD MODULE (M7556)

~—D2= ~18V (GREEN)

/ —-01 = +5V MAIN POWER SUPPLY (RED)
O

UWVW
UL W
CLEYS TM

FIGURE

5-8

MDM

MODULE

5=17

LED

LAYOUT

SYSTEM

MDM
a.

MAINTENANCE

Module

Notes

An M7677-YA MDM must
H7231-E BBU.
If

the

points
module
Loss
If

of
an

MDM

and

the

(See

turns

setting

test

the

NPG

pack

Figure

off

the

1loss

point

the

problem,

switch

1indicates

corresponding
The

NPG

voltage

LED

used

suspected

the

replacement.
a

(non

check

contains
i
:

the

voltage

configuration

test

prior

5-9.)
associated

prior

system

LED.

voltage,

regulator

processor

grant)

check

the

replacement.
select

switch

pack
1is
used
to
select
NPG
status.
Each
NPG switch
corresponds to a CPU backplane slot 5 through
12.
Figure
5-9
shows
the
location
and
slot number of the each NPG

switch.
For

non DMA devices a CPU backplane
slot
the
NPG
switch
should
be in the ON position.
A common NPG problem occurs
when DMA devices are
installed
with
the
NPG
switch
ON

(arbitration mechanism is

bypassed).

This

causes an error code 20 when attempting to
device,
1indicating
a
controller
error.
To
problem, turn OFF the NPG switch for that slot.

YOLTAGE TTST

QFi//

- 19V¢ 18V GND 5 1V 5V

(0 PN

FOINTS

DJ’
(20 PNy

0 O D D D\u: NUTE
@ AUDIBLE
ALARM

SLo7

NUMSER

90000000
ors

i TCr
PACK

Me??

nOTE
D1

S 1AAIN POV E# SUPPL
Y

07- +$VB8 AND<12VlLM! s ANS)
D3- + 19V MAIN POVE R SUPPL
Y
DE

8V If XPANSIO, SOWE
R SUPP) V)

B \PL Y)
15V (€ XPANSIO. POWE

FIGURE

5-9 MDM MODULE LAYOUT

5-18

boot
that
correct the

SYSTEM MAINTENANCE
5.4.3

Module

KDJ11-BF CPU

The KDJ11-BF module

provides:

A green POWER OK LED, indicating that dc power to_. the

Six red error code LEDs, which correspond to
diagnostic error codes (see Figure 5-10).

module

CPU

present.

the

Start-up

In addition the error codes appear on the
front
panel
Start-up
Test display.
For example, if an error code 51 occurs during the
and
display
start up diagnostics, 51 appears on the front panel
the corresponding CPU module LEDs

light

(that

is,

(LSB),

6).

and
|

If the
module

KDJ11-BF module is the
suspected
replacement, assure that:

The module
5-10, and

The

DIP

jumper

switches

configurations

are

DIP SWITCH FOR

AND TWO-DIGIT DISPLAY

§/B OFF

FOR CABLE TO
BAUD RATE SELECT

(GREEN)

LEDS {(RED)

REMOTE SWITCH

@1 CONTROL CONNECTOR

oTJo TR0

(M) BYTE) \_

£53

15:08

40—PIN SOCKET (P-SERIES)

DCJ11 CPU MYBRID

AOM

pre———

£80

(LO BYTE) =

ARRAY

TP4 1

GATE

ARRAY

(SEE NOTE 2)

w20

Tr200)® TP210TP22

LM
]

NOTES: 1. WHEN 24-PIN EEPROM IS USED. INSERT PN ONE OF EPROM IN PIN 3 OF SOCKET.
2. WHEN 2K EEPROM IS USED. TGO IS CONNECTED TO TPa
WHEN 8K EEPROM IS USED. TPe1 1S CONNECTED TO TPe2.

FIGURE

5.4.4
The

5-10

KDJ11-BF

MSV11-JB/JC

gquad-height

Memory

JUMPER AND

SWITCH

PACK

Module

memory module

provides:
[ 4

red

LED

indicate

uncorrectable

5-19

errors

Figure

DIAGNOSTIC

\ | 58:4 l“lfl‘ll
wio

specified

prior

DCOK LED

BAUD RATE SELECT AND
BOOT STRAP CONTROL

comecr|on S \ b / 4
TP

and

OFF.

CONNECTOR

CONSOLE SLU

problem

LOCATIONS

SYSTEM

MAINTENANCE

A green

Two

Four

the

LED

switch

indicate

packs

factory-set

module

switch
pack
replacement.
layout.

the

for

the

presence

starting

and

CSR

Vdc

address

selection

jumpers.

suspected

problem,

check

both

LEDs,

the

settings, and jumper configurations prior to module
See Figure 5-11 for LED, switch
pack,
and
jumper

n0 w2

I
FIGURE

The
1 -

5-11

MSV11-JB/JC

LED/SWITCH

PACK/JUMPER

LAYOUT

starting address is configured using switch pack S1, switches
8 Table 5-4 lists the switch settings, starting addresses and

decimal number.
The
(MSV11-JB) memory and
(MSV11-JC) memory.
TABLE

SWITCH

SETTING*
123456 78

0000O0O0O 0O
00000O0O0 1
00000010
00000011
00000100
00000101

5-4

top
sixteen
entries
apply
to
the
the bottom sixteen entries apply to the

MSV11-JB/JC

STARTING

ADDRESS

DECIMAL

(OCTAL)

00000000
00040000
00100000
00140000
02000000
00240000

bytes)

0
8
16
24
32
40

1MB
2MB

SYSTEM

TABLE
SWITCH SETTING*
12345678

5-4

MAINTENANCE

(Cont)

STARTING
ADDRESS (OCTAL)

DECIMAL
(K bytes)-

00000110
00000111
00001000
00001001
00001010
00001011

00300000
00340000
00400000
00440000
00500000
00540000

48
56
64
72
80
88

00001100
00001101
00001110

00600000
00640000
00700000

96
104
112

00001111
0000XZX X X
0001XZXXX
0010XZX XX
0011XZXZXX
0100XXX X
0101XXZXX
0110XXXX
0111XXZXZX
1 000X X X X
1001XZXZXKX
1010XXXX
1011XXXX
1100XXZXX
1101XXZXX
1110XXKXX
1111XXZXZX

00740000
00000000-00740000
00100000-01740000
02000000-02740000
03000000-03740000
04000000-04740000
05000000-05740000
06000000-06740000
07000000-07740000
10000000-10740000
11000000-11740000
12000000-12740000
13000000-13740000
14000000-14740000
15000000-15740000
16000000-16740000
17000000-17740000

120
000-120
128-248
256-376
384-504
512-632
640-760
768-888
896-1016
1024-1144
1152-1272
1280-1400
1408-1528
1536-1656
1664-1784
1792-1912
1920-2040

1
0

= Switch on
= Switch off

Switch

can

The

CSR

address

The

base

plus

off

is configured using switch pack S2, switches 1
address is 17772100.
Each successive address is the

Table

TABLE

5-5

lists

all

MSV11-JB/JC

either

SETTING

sixteen

CSR

possible

ADDRESS

CSR

ADDRESS

(OCTAL)

00O

17772100

0001

17772102

0010
0011

17772104
17772106

CSR

SELECTIONS

addresses.

SYSTEM

MAINTENANCE
TABLE

S2
1

SETTING
2 3 4

5-5

CSR

ADDRESS

17772110
17772112
17772114

1
1

17772116
17772120
17772122

0
1
0

17772124
17772126
17772130

1
0
1

17772132
17772134
17772136

jumper
(MSV11-JC)

configurations
memory
modules

factory-set

jumpers

TABLE

MODULE

5-6

are

for

¢the

1MB
(MSV11-JB)
different.
Assure

are

specified

MSV11-JB/JC

JUMPER(S)

(OCTAL)

0
1
0
0

The

(Cont)

JUMPER

POSITION

Table

and
that

2MB
the

5-6.

CONFIGURATIONS

DESCRIPTION

‘wsvii-ss
wl

OuT

256K

Half-populated

W3,W4

Vertical

Dynamic

Reserved

for

RAMs
module

future

use

MSV11-JC
wl

ouT

256K

ouT

Fully

wW3,W4

5.4.5

KTJ11-B

Rams

populated

Reserved

module

for

future

use

support

M9312

compatible

Module

The module provides
ROMs.

Vertical

Dynamic

this

four

module

and their orientation as

sockets
is

the

shown

suspected problem,

in Figure
5=-22

5-12,

check

the

ROMs

SYSTEM MAINTENANCE
ME312 TYPE OPTION ROM SOCKETS (4

5-12

SOCKET

ADONRESS

)

Eres

17773000- 17773176

FIGURE

ROM

Eres

Jk//Jm

)

17773200- 17773378

Eres

- 17773876
17773400

Ee2

17772800-1777377%

KTJ11-B ROM SOCKET LOCATIONS

5.4.6 Minimum Load Module
The MLM modules provide
minimum
under the following conditions:
ae.

An MLM
ensure

power

supply

is inserted in CPU backplane
a
minimum
current
drain

regulator

slot 3
of
2

1loads

(rows C
and
D)
A from the +5VBR

regulator.

An MLM

ensure

inserted

in CPU backplane slot

current

minimum

drain

(rows

and

of lA from the -15V

regulator.

If
an
expansion
backplane
(DDl11-CK
or
DD11-DK)
is
installed,
an
MLM
1is
inserted
1in
the last slot of the
backplane (rows E and F) to ensure a minimum current
drain
of 1 A from the -15 Vdc regulator.

NOTE

An MLM

(CPU

not required

or expansion)

the minimum

1lA.

When not regquired,
backplane.

the

5-13,

shown

presence of

Figure

+5 VBB and

the

load modules

the

MLM

has

-15 Vdc.

5-23

last

backplane

slot

installed options draw

must

two

LEDs

removed

from

the

indicate

the

SYSTEM

MAINTENANCE

FIGURE

5.5

FIELD

Table

5-7

the

5-13

MINIMUM

[

»e 1320

LOAD

MODULE

LAYOUT

UNITS

field

TABLE

PART

D2
GREE"

REPLACEABLE

lists

D1
RED

replaceable

5-7

FRU

NUMBER

units

(FRU).

DESCRIPTIONS

DESCRIPTION

M7677-YA*

Monitor

Distribution Module

M8191

KTJ11-B,

M8190-AE

KDJ11-BF,

CPU

M8637-BA

MSV11-JB,

ECC

M8637~-CA

MSV11-JC,

ECC Memory Module

M7556

Minimum

M9302

Terminator

70-20650-01

CPU

UBA

(MDM)

Module

Load

FPA Module

Module

Backplane

Memory

Module

SYSTEM MAINT ENANCE

TABLE 5-7 (Cont)
DESCRIPTION

PART NUMBER
H7202-KA

Power

Supply

H7202-§B

Power Supply

54-16508

Console

H7211-B**

+15,

H7213-D**

+12V,

H7200-C**

+5V Requlator

70-21888-01

Front

12-22001-01

Blower

12-22271-02

Fan

877-D

Power

Controller

120V

877-F

Power

Controller

240V

70-21116-01

Circuit

breaker

H7231-E*

Cabinet

Battery Back

H7231-F*

Box

DD11-CK

4-slot

DD11-DK

9-slot Backplane

SLU

)
Board

-15V Regulator Module
+5V

Regulator

Panel

Module

Assembly

assembly

OPTIONS:

M7677-YA must
the

5.6

MODULE

remove

Battery

H7231-E/F BBU

Specifies

Unit

Backplane

installed

the

system contains

option.

minimum etch

REMOVAL/REPLACEMENT

any module

Back

up Unit

1listed

revision.

PROCEDURE

Table

5-7

wuse

the

following

procedure.

Open the cabinet front and rear
slide the box out of the rack.
5-25

doors

using

the

hex

key,

SYSTEM

MAINTENANCE

Turn

either:

The cabinet power
breakers OFF, or

The

box

circuit

Remove

the

4.,

Remove

all

cables

Pull

the

breaker

power

module

supply

cord

from

power

the

and

<circuit

module

out

<controller
'

OFF.

from

the

handles

and

outlet.
and

slide

label

the

each

one.

module

from

the

backplane.
This

completes

reverse

5.7

the

POWER

the

removal

module.

reinstall

module

procedure.

SUPPLY

REMOVAL/REPLACEMENT

Both the cabinet and box products have a
H7202-KA
power
supply
containing
three
regulator
boards.
The
regqulator boards and
power supplies are FRUs.
Assure that the
regulator
boards
are
not defective prior to replacing a power supply.

5.7.1
To

Cabinet

remove

supply,

l.
2.

Power

power

use

the

Supply

Removal/Replacement

supply

regulator

following

procedure.

Open

the

front

and

rear

Turn

the

power

supply

doors

and

board

using

power

the

hex

controller

main

power

key.
circuit

breakers

OFF.

Remove

the

Loosen

the

two

Slide

blower
assembly
out
the blower motor power

Slide

and

the
disconnect

power

cord

captive

from

screws

the blower assembly out
cabinet assembly.
See Figure

the

outlet.

holding

the

about
cable.

up
5-14.

blower

assembly.

four

inches,and

remove

from

the

SYSTEM

MAINTENANCE

POWER SUPPLY
CIRCUIT BREAKER

PLASTIC

Push

the

FIGURE

5-14

power

supply

tray

slide)

in.

until

the

the tray handle
Figure 5-15.

BLOWER ASSEMBLY

REMOVAL

lock (located on the
Slide the tray out by

second

tray

Loosen

located
Using
bus

and

near

5-15

[

F
CABINET

remove

the

a phillips
wires.

See

v
FIGURE

engages.

= 15

1lock

1left
edge
pulling on

the

top
head

left

POWER SUPPLY

power

edge

REMOVAL

supply
hold
down
of the power supply.

screwdriver

and

remove

the

bracket

four

VDc

SYSTEM

MAINTENANCE

10.

Remove

11,

Using

12,

Pull the power

the

two

ribbon

3/8-inch

Loosen

the

power

three

supply

FIGURE

14.

wrench

supply

cabinet.
.
13,

remove

5-16

the

cables

remove

the

forward

captive

and

screws

remove

the

POWER SUPPLY

memory/fan

input

ground

and

cable.

lug.

remove

-from

holding

the

top

cover.

See

Figure

the

cover

5-16.

REGULATOR REMOVAL

(H7213)

option (H7211) regulators, gently
each corner s;gndoff and l1lift up.

lift

the

communications

them out

by grasping

15.

To remove the H7200 regulator, turn the power
supply
over
(open side down) and while supporting the regulator, loosen
the six phillips head screws securing it to the chassis.

l6.

Remove

the

regulator

from

the

This completes the removal of the
supply.
To reinstall, reverse the

5.7.2

Box

Power

Supply

To remove a power

chassis.

regulators
boards
above procedure.

Turn

the

supply

circuit

power

Removal

regqulator

following procedure.
1.

and

breaker OFF
.«

5-28

power

supply,

use

the

SYSTEM

Unplug

the

power

Remove

the

box

top

screws

and

lifting

Loosen the

cord

from

cover

the

cover

the

outlet.

removing

cover

the

off.

four

captive

two phillips head screws

cover.
‘Slide
the
See Figure 5-17.

MAINTENANCE

backwards

the

power

and

1lift

supply

remove

it.

CAPTIVE
SCREws

FIGURE

5-17

POWER

SUPPLY

REMOVAL

To
remove
either
the
memory/fan
(B7213)
communications
option (H7211) regulators, gently
out by grasping

the

two corner standoffs

and

or
the
lift them

lift up.

To remove the H7200 regulator, the
power
supply
must
be
removed
from
the box.
Loosen the four screws that secure
the power supply to the chassis shelves.
Lift
the
power
supply, out of the box.
See Figure 5-18.

FIGURE

5-18

POWER

SUPPLY

5-29

REGULATOR

REMOVAL

SYSTEM

MAINTENANCE

After

removal,

turn

the

power

supply

over

(open

and while supporting
head screws securing

the regulator, loosen
it to the chassis.

Remove

from

the

regulator

the

side

six

down)

phillips

chassis.

NOTE

If the power
supply
1is
replaced,
set
the
AC
120/240 voltage select switch to match the outlet
AC

This

voltage.

completes

regulators.
reverse

the

removal

procedure

reinstall

the

above

procedure.

for

box

regulators

power

and

supply

power

an’

supply,

5.8 CABINET BLOWER REMOVAL/REPLACEMENT
To

remove

the

blower

assembly

use

doors

Open

the

front

and

rear

Turn

the

power

supply

and

the

following

using

power

procedure.

the hex

controller

key.
circuit

breakers

OFF.

Remove

Loosen the
slide
the
disconnect

Slide

the

power

cord

from

the

outlet.

two captive screws holding the
blower
assembly
out
about
the blower motor power cable.

blower

from the

assembly

cabinet.

See

out

while

Figqure

blower
assembly,
four
inches, and

lifting

5-19.

—

Y
PORER OFPL
oG

FIGURE

5-19

BLOWER

5-30

ASSEMBLY

REMOVAL

up,

and

remove

SYSTEM MAINTENANCE
This

completes

Reinstall

5.9

BOX

There

the

FAN

are

the

removal

procedure
assembly in the

blower

REMOVAL/REPLACEMENT

three

fans

used

module

cardcage

and

the

third

any

the

fans

Turn

the

circuit

Unplug

one

the

use

the

product.

Two

cool

the

supply.

the

four

screws

the

bezel

from

Loosen

the six captive
fans.
Lift off

power

fans

procedure.

from

from
the

the

outlet.

rear

the

box

screws from the
the metal grid.

metal

grid

Loosen the two phillips screws
securing
the
fan
mounting position on the plenum.
See Figure 5-20.

Unplug

fan

power

FIGURE

cable

5-20

flange.

box.

the

remove

off.

cord

Remove

the

box

cools

following

Remove

assembly.

the

breaker

power

for cabinet blower
reverse order.

and

remove

BOX FAN

the

front

its

new

fan.

REMOVAL

CAUTION

When

installing a
points toward the

fan

insure

the

airflow

When

installing a replacement
fan,
tighten
mounting screws snug.
DO NOT OVERTIGHTEN.

This

completes

fan,

reverse

the

fan

above

arrow

plenum.,

removal

procedure.

procedure.
5-31

the

reinstall

SYSTEM

MAINTENANCE

5.10

Front

The

cabinet

different

Panel

Removal/Replacement

and

removal

box
and

front

panels

are

identical,

but

have

replacement procedures.

5.10.1 Cabinet Front Panel Removal/Replacement
To

remove the

cabinet

front

Open

the

front

and

Turn

the

power

supply

panel

rear

use

doors

and

the

following

using the

power

hex

controller

procedure.

key.

circuit

breakers

OFF.

Remove

the

Disconnect the
Figure 5-21.

power

cable

cord

from

the

from the

outlet.

front

panel

assembly.

See

FIGURE 5-21 CABINET FRONT PANEL REMOVAL

Remove the
the door.

four

Remove

front panel

the

3/8-inch

nuts

off

holding

the

reinstall

the

front

panel,

reverse
L4

5-32

panel

¢to

panel

assembly.

standoffs.

This completes the removal of the cabinet front
To

front

the

above

procedure.

SYSTEM

5.10.2

Box

remove

Front

the

Panel

box

MAINTENANCE

Removal/Replacement

front

panel

use

the

following

procedures.

Turn the power supply circuit breaker OFF.

Unplug the AC power from the outlet.
Remove

the

front

bezel

rear

screws

from

the

(see

Figure

box

Remove

the

cable

loosening
side.

and
Pull

removing

the

four

the

away

from

bezel

5-22).

that

1is

plugged

into

the

four

Phillips

the

front

panel

assembly.
Loosen

the

and

front

remove

panel

the

head

screws

securing

chassis.

Remove the front panei assembly.

flzflq

[

ALH ok
e -—g2c. ==

z8opsih

(18
L
'flg =’g9%]!

VgV

;yf"

'b
~<

. '/, "
\\

FIGURE

This
box

completes
front

the

panel,

5-22

removal

reverse

the

FRONT

the
above

PANEL

front

REMOVAL

panel.

procedure.

reinstall

the

SYSTEM

5.11

MAINTENANCE

CIRCUIT

BREAKER

REMOVAL/REPLACEMENT

Both products have circuit breakers for
the
power
supply
(s).
The
box
<circuit
breaker
assembly is located externally on the
right side.
The cabinet circuit -breaker is located inside
lower
right
side
and
has two breakers; one for the main power supply
and one for the expansion supply.

5.11.1
To

Cabinet

remove

Circuit

the

Breaker

<circuit

Removal/Replacement

breaker

assembly

use

the

following

procedure.

l.
2.

Open

the

front

and

rear

Turn

the

power

supply

doors

and

using

power

the

hex

controller

key.
circuit

breakers

OFF
.

Remove

the

power

Unplug
5-23.

the

cords

5-23

from

connected

r——%_’_

FIGURE

cord

the

outlet.

the

assembly.

See

Figure

——

CABINET CIRCUIT BREAKER REMOVAL

Remove the blower power connector
by
pushing
1in
connector release clips, and pulling the connector

Loosen the two screws securing the circuit breaker assembly
to the the cabinet support and remove the assembly.

This

completes

the

removal

the
5-34

circuit

on
the
loose.

breaker assembly.

SYSTEM

MAINTENANCE

To reinstall the assembly, reverse the above
procedure.
Ensure
that the power cable plugged into the unswitched power controller
outlet is inserted into Jl.

5.11.2
To

Box

Circuit

remove

the

Breaker

<circuit

Removal/Replacement
breaker

assembly,

use

the

following

procedures.

Turn

Unplug

the

AC power

Remove

the

rear

each

the

circuit

section

breaker

has

cord

off.
from

bulkhead
two

the

outlet.

sections

flathead

marked

screws.

See

through

Figure

A4,

5-24.

CIRCUIT
BAEAKER

FIGURE

Remove

the

5-24

four

BOX

CIRCUIT

screws

securing

box.

BREAKER

the

REMOVAL

breaker

assembly

Reach inside
the
release the three
Remove

the

box

through
the
clips inside

cable

<circuit

breaker

bulkhead
the

along

through

the

-access

the

and

box wall.

rear

bulkhead

access.

Remove

the
This

the four screws securing the wires
circuit breaker.
Label each wire.

completes

assembly.
procedure.

the

replacement

reinstall

procedure

the

5-35

circuit

for

the

circuit

breaker,

back

breaker

reverse

the

SYSTEM

5.12

MAINTENANCE

CABINET

remove

POWER

the

877

CONTROLLER

power

REMOVAL/REPLACEMENT

controller

assembly,

procedure.

use

the

following

Open

the .front

and

Turn

the

supply

power

rear

doors

and

using

power

the

hex

controller

key.
circuit

breakers

OFF.

Remove

Lift

the

power

cord

side

panel

left

careful,

the

from

the

straight

outside panel

outlet.

from

heavy.

See

both

sides.

Figure

5-25,

L SHOULDER SCREwW (4!
bosee EMI SHIE LD

SCREwW )

SIDE PANEL

FIGURE

Remove

the

EMI

Label

plugs.
Loosen

two

shield

each

10
to

the

the
plug

Figure

the

CABINET

phillips

power

See

controller
Grasp

5-25

and

four

REMOVAL

shoulder

side.

and

receptacle,

its

screws

and

securing

remove

the

5-26.
head

cabinet

CONTROLLER metal

controller

PANEL

cabinet

phillips
the

SIDE

from

the

screws

bulkhead.
power

cabinet

5-36

cord

rear.

securing
See

Figure

restraint

the

power

5-27.
and

remove

SYSTEM MAINTENANCE

cash

-‘

\i/

IM\_«u

| E\:%
BANERC

{ n fi//LJtJ:\ °°

FIGURE 5-26 POWER CONTROLLER REMOVAL - SIDE VIEW
877.0/¢

CONTROLLER

REAR VIEW

FIGURE 5-27 POWER CONTROLLER REMOVAL - REAR VIEW

This completes the removal procedure for

power

the

controller.

To reinstall the controller reverse the above procedure.
5.13 SLU INTERFACE ASSEMBLY REMOVAL/REPLACEMENT

Both

products

contain

SLU

Interface

different removal and replacement procedures.

Assembly,

Dbut

use

5.13.1 Cabinet SLU Assembly Removal

To remove the SLU assembly use the following procedure.
1.

Open the front and rear doors using the hex key.

Turn the power supply and power controller circuit breakers
OFF.

5=-37

SYSTEM

MAINTENANCE

Remove

the

power

4.,

Loosen

the

ten

cord

captive

from

the

screws

outlet.

securing

the

bulkhead

the

top.

the

frame.

Open

the bulkhead

Unplug

the

Loosen

and

connector
8.

SLU

cable

remove

Unplug

the

Figure

5-28.

pulling

the

cable

down

(console
the

two

from

terminal)
hex

cross

member.

from

the

SLU

from

the

standoffs

assembly

connector.

securing

connector.

the

See

| wgx atwgms

|L SENE® (21

FIGURE

9.,
10.

5-28

CABINET

SLU ASSEMBLY

REMOVAL

Hold the SLU assembly while removing the
two
secure the SLU assembly to the cross member.

screws

that

Remove the SLU assembly from the cabinet.

This completes the removal of the SLU assembly.
SLU assembly reverse

the above procedure.

To reinstall the

SYSTEM

5.13.2
To

Box

remove

SLU
the

Assembly
SLU

Removal/Replacement

assembly,

use

the

following

procedure.

Turn the circuit breaker oéf.

Unplug tflé AC power cord from the outlet.

Remove

the

cable

Remove

the

two

back

MAINTENANCE

plugged

hex

into

standoffs

.
the

SLU

connector.

securing

the

connector

the

remove

the

panel.

Remove

the

four

screws

connector

the

top

cover,

and

cover.

Remove

the

Remove

the

Remove

two

See

the

assembly

Figure

hex

into

mounting

the

SLU

screws

assembly

from

the

rear

standoffs

from

the

SLU

reinstall

the

connectors.

FIGURE

9.
This

Remove

the

completes

SLU

the

assembly

reverse

5.14

BACKPLANE

CPU

Depending

backplane
recommended
to be

known

the

5-29

BOX

assembly

removal

the

board.

5-29.

box.

plugged

above

SLU

ASSEMBLY

from
the

the
SLU

’

REMOVAL

box.
assembly.

procedure.

REMOVAL/REPLACEMENT

number

replacement
that

you

the

faulty

options

can

time

consuming

task.

the

backplane

ONLY

1is

clearly

replace
FRU.

5-39

installed

the
if

system,

a
is

SYSTEM

MAINTENANCE

5.14.1

Cabinet

Removal

remove the CPU backplane,
1.

use

the

following procedure.

Open the front and rear doors using the hex key. _
Turn the power supply and power controller circuit breakers
OFF.

Remove the AC power cord from the outlet.
Remove and label all the module cables.

Remove

all

cabinet

backplane slot

number.

modules

Remove the right side panel.

and

1label

each

its

with

See Figure 5-30.

Ns=a

Backplane

SHOULDER SCREW (4)
EMI SHIELD

SCREW (2)

SIDE PANEL

FIGURE

5-30

SIDE

PANEL REMOVAL

Remove the two
phillips
head
and
four
shoulder
securing the EMI panel to the cabinet frame.
Remove

the

Remove

the four shoulder screws

the

cabinet

left

screws

side panel.

frame.
5-40

securing

the EMI

panel

SYSTEM

10.

Loosen
frame

the
and

ten

screws

lower

the

securing

bulkhead.

the

bulkhead

See

Figure

MAINTENANCE

the

cabinet

5-31.

T
T
T

In=

|__PORCED

Lrmrg I

IO O |

FIGURE

5-31

1l1.

V:fi&

CONNECTOR

Y O

CABINET

REAR VIEW

Remove
the
four
black
plastic
retainers
plastic
1lexan
cover
over
the
space
for
backplane

location.

See Figure

5-32.

FIGURE 5-32 CABINET BACKPLANE REMOVAL
5-41

securing
the
the expansion

SYSTEM

12,

MAINTENANCE

expansion

connectors.
cabinet
13.
14,

Loosen

the

cable

access

rear

16.

the

card

cover

remove

through

rear

and

completes

reinstall

5.14.2

Box

remove
Turn

the

power

for

the

expansion

metal

backplane.

panel

covering

the

screws

securing

the

backplane.

flathead

metal

Remove

screws

panel

the

securing

metal
the

over

the

panel.

backplane

cage.

twisting
the

Backplane

through

removal

the

side

panel

procedure

for

the

reverse

the

above

the

cabinet

access.
backplane.

procedure.

Removal/Replacement

backplane,

the

side

backplane.

the

four

power

left
-

cables

clamps

the

backplane

the

Remove the backplane by pulling the it toward

17.

six

Remove

the

This

the

access

installed

lexan
-

the

Remove

the

access.

Disconnect

rear

15.

backplane

Remove

power

use

circuit

Unplug

the

power

Remove

the

screws

all

the

all

the modules

the

following

breaker

cord

from

securing

procedure.

OFF.
the

the

outlet.

top

cover,

and

remove

the

cover.

Unplug

module

cables

and

label

each

with

its

module

number.

Unplug

labeling

the

module

with

1its

slot

number.

Remove

cables.

the

four
Unplug

1/4-inch
nuts
securing
the two backplane cables.

the

See

four
power
Figure 5-33.

SYSTEM MAINTENANCE

FIGURE

7.
8.

Remove
Slide

the
the

the

card

Turn

the

mounting
This

completes

reinstall

5.17

the

CABINET

Always extend
out
of
the

cbainet

two

5-33

screws

card

cage

card

cage

screws.
the

BOX

the

located

the

rear
over

Remove

removal

backplane

BACKPLANE

rear

and

rear

the

box.

from

remove

the

card

cage.

Lift

and

slide

the

box.

the

four

backplane

CPU

backplane.

procedure

reverse

the

remove

and

the

REMOVAL

the

for

above

the

procedure.

PERIPHERAL ACCESS

the
top

front stabilizer bar before sliding
an
portion of the cabinet.
The bar keeps

from tipping

forward.

(See

Figure

5-38.)

option
the the

SYSTEM

MAINTENANCE

FIGURE 5-38 STABILIZER BAR EXTENSION

APPENDIX

CPU INSTRUCTION TIMING

CPU

INSTRUCTION

TIMING

A.l1

INTRODUCTION

The

execution

time

for

instruction

depends

The type of instruction exécuted,

The mode of addressing used, and

The

type

In general,

the

of memory
total

being

referenced.

execution

instruction
fetch/execute
calculation/fetch time.

on:

time

plus

the

sum

the

operand(s)

base

address

The tables in this section can be used to calculate the length of
an
1instruction in terms of microcycles (MC).
Tables A-1 thru
A-8 list the standard and floating-point instructions,
their
Op
Code
1listing,
and
execution
times
(MC).
The EXECUTION MC
column
specifies
the
number
of
micro<cycles
required
to
fetch/execute the base instruction.
The R/W column specifies the
number of read microcycles (R) and write microcycles (W)
1n
the

EXECUTION
(NIO).
If

the

column.

instruction

Any

involves

remaining

the

microcycles

calculation/fetch

are

one

non

I/0

operands,
destination

a
reference
to
a
separate
table
(a
source
or
table)
is made in the last
c¢olumn,
wusually
1labeled
TABLE or DEST TABLE.
The tables referenc- ed are S1, D1 thru D6,
and F1 thru F5.
The
source/destination
tables
speci£fy
the

number
of
re- quires,

microcycles
the source/destination calculation/fetch
and how many of these are read or write
microcycles.

any

before,

The

numbers

remaining microcycles

contained

in the

tables

are

NIO.

are based on

the

assumptions

that:

A memory read must

last

a minimum of

A memory write must last a minimum of

four CLK periods,

eight

CLK

periods,

and

NIO

lasts

four

CLK periods

(no

DMA).

Any wait states caused by slower memory or a DMA transfer must be

added
to
the
total
1instruction
time,
If
wait
states
are
required, the first wait state of
a
nonstretched
read
or
NIO
cycle
will
1last
four
clock
periods,
and
can
continue
1in
increments
of
two
<clock
periods.
Further
wait
states
for
stretched cycles occur in increments of two clock periods.

Floating-point

instruction execution

A-2

times are given as

range.

INSTRUCTION TIMING

CPU

The

actual execution

being

The

oper-

ated

following

EXAMPLE

How

long

Step

time will

vary depending

the

type of

data

on.

examples

illustrate how to use

the

tables..

does

MOV RO,@

2044

instruction

last?

From Table A-2 , the execution time for the MOV base
1instruction
is
found
to be 1 MC, or four CLK periods.
This consists of one
read and no write microcycles (R/W
column).
Depending
on
the
type
of
memory
1in the system, the microcycle may be stretched.
If so, the microcycle lasts -at least eight CLK periods and may be
stre- tched thereafter in increments of two CLK periods.

Step

find

the

operand

calculation/fetch

time

for

the

source

oper-

and (RO), refer to Table S-1.
From Table S-1, it 1is shown that a
mode 0 register 0 calculate/fetch takes 0 MC.
Note that the
operand is already available to the DCJ1l (in the register file).

Step

find the operand calculation/fetch time
for
the
destination
operand
(the
contents
of memory location 2044), refer to Table
D-3.
Table D-3, specifies that a mode 3
register
7
calculate/

fetch
requires
3
microcycle).
Note

MC
that

(i.e.,
one read microcycle
the remaining microcycle is

and one write
an NIO micro-

cycle.
The

type

of memory

the

system must

taken

into

the
read
cycle is stretched, the stretched cycle
eight CLK periods and may be stretched thereafter
of
two
CLK
periods.
The write microcycle lasts

CLK periods
periods.

Step

For

and

may

stretched

account.

lasts at least
in
increments
at least eight

increments

two

CLK

the

(which

determination

the

minimum

time

required,

microcycles.
In this example, It is 1 + 0
16 CLK periods if no microcycle stretching

A-3

total

+ 3, or 4
occurs).

EXAMPLE

The

source

show

‘How

long

Step

and

number

tables

operations.

for

floating-point

the microcycle

This

example

shows

instructions

for

certain

timing

mode
c&lculation

CLRD

2000

instruction

last?

specified

in
1is

Table
14

A-8,

the

base

instruction

time

for

the

CLRD

MC.

From Table

F-2,

the

calculation/fetch

mode
2
register
7
reference)
PRECISION).
This means that 1 MC
base instruction time.

time

for

the

operand

1s
shown
as
(-1 under DOUBLE
should be subtracted
from
the

However, add 1 MC for the memory write
memory read cycles to account for.

Step

column

these.

does

instruction

Step

destination

negative

for

TIMING

INSTRUCTION

CPU

operation.

There

are

(assumes

Total up the microcycles:
cycle stretching).

TABLE

A-1

SINGLE

MNEMONIC

INSTRUCTION

-1

14 MC minimum

OPERAND

CODE

INSTRUCTIONS

SOURCE

DEST

LISTING

EXECUTION

R/W

TABLE

0050DD
0051DD
0052DD
0053DD

1
1
1
1

I/0
I/0
I/0
I/0

D3
D4
D4
D4

0054DD
0057DD

1
.1

I1/0
I/0

D4
D4

General

CLR(B)
COM(B)
INC(B)
DEC(B)

Clear
Complement
Increment
Decrement

NEG(B)

Negate

TST(B)

(1l's)

(2s complement)
Test

CPU
A-1

and

ROR(B)

Rotate

ROL(B)
ASR(B)

Rotate left
Arithmetic
shift right
Swap bytes

SWAB

Shift
right

D4
D4

0061DD

1/0
I1/0

0062DD
0003DD

1/0
I/0

D4
D4

0060DD

Rotate

TIMING

(Cont)

—

TABLE

INSTRUCTION

Multiple-Precision
Add

carry

0055DD

I/0

SBC(B)
SXT

Subtract carry
Sign extend

0056DD

1/0
1/0

---

D4
D3

0072DD

1/1

0073DD

1/1

0067DD

ADC(B)

Multiprocessing
Test

(low bit

and

set

interlocked)

WRTLCK Write
interlocked

OP
MNEMONIC

INSTRUCTION

CODE

EXECUTION

R/W

LISTING

TIMING
SOURCE

DEST

TABLE

nunumwn

TSTSET

General

02SSDD

06SSDD
16SSDD

BIT(B)

Bit

03SSDD

1/0

BIC(B)
BIS(B)

Bit
Bit

04SSDD
05SSDD

1/0
1/0

D2
D4

01SSDD

Compare
Add
Subtract

e
e

Move

CMP(B)
ADD
SUB

—

1/0
1/0
1/0
1/0

MOV(B)

(AND)
clear
set (OR)

nNnmw

test

Logical

D4
D4

DIV

Multiply

Divide

0704SS
071RSS

(Notes

1/0
5,11
1/0

D1l

CPU

INSTRUCTION

TABLE

A-2

TIMING

(Cont)

D CED

GED GEP

1/0

- Dl

1/0

Arith shift
combined

073RSS

074RDD

(Note
1

A-3

INSTRUCTIONS

(OR)

TABLE

6,7,12)

072RSS

Exclusive

(Notes

Sshift
automatically

SED GiD

GED

GEP

GED

D CIF G

GIP

GRS GED GIb

GEF

GND GNP

GEP

BRANCH

afd

IR GES

AP EES GNP GEF GRS

GEb

GER

13)

GIS WD CGED GiS GED

GG GIP

GID GiD

GED

GIP

GID (ED

GID

CED

GIP

GIP GBI

GIP

GEP

GNP

TIMING

MNMONIC

INSTRUCTION

BRANCH

NOT

TAKEN

CODE

TAKEN

LISTING

R/W

000400

1/0

001000
001400
100000
100400
102000
102400
103000
103400

2
2
2
2
2
2
2
2

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

4
4
4
4
4
4
4
4

020000
002400
003000

2
2
2

1/0
1/0
1/0

4
4
4

2/0
2/0
2/0

003400

1/0

2/0

101000
101400
103000
103400

2
2
2
2

1/0
1/0
1/0
1/0

4
4
4
4

0 77RNN

1/0

BRANCHES
BR

Brancfi (unconditional)

BNE

BEQ

BPL

BMI

BVC

BVS

BCC

BCS

SIGNED

BGE

if not equal (to 0)
if equal (to 0)
if plus
if minus
if overflow is clear
if overflow is set
if carry is clear
if carry is set

CONDITIONAL

BRANCHES

BLT
BGT

Br
Br

if less than (0)
if greater than (0)

BLE

(to 0)

greater

less

equal

or equal

(to 0)
UNSIGNED CONDITIONAL

BRANCHES

BHI

higher

BLOS
BHIS

Br
Br

if
if

lower or same
higher or same

lower

BLO

SOB

Subtract

(if /= 0)

and

branch

CPU

TABLE

A-4

JUMP

and

INSTRUCTION

TIMING

SUBROUTINE

TIMING

OP CODE

EXECUTION
MC

R/W

DST

0001DD

O004RDD

(Note

subroutine

00020R

3/0

(Note

14)

Stack

0064NN

3/0

MNEMONIC

INSTRUCTION

JMP

Jump

JSR

Jump

RTS
MARK

Return

LISTING

subroutine

from

cleanup

TABLE

TIMING

MNMONIC

OP CODE
LISTING

INSTRUCTION

trap

EXECUTION
MC

R/W

EMT

Emulator

104000--104377

4/2

TRAP

Trap

104400--104777

4/2

BPT
IOT

Breakpoint trap
Input/output trap

000003
000004

20
20

4/2
4/2

RTI

Return

from

interrupt

000002

4/0

RTT

Return

from

interrupt

000006

4/0

TABLE

A-6

CONDITION

CODE

OPERATORS

TIMING
MNEMONIC

INSTRUCTION

OP CODE
LISTING

EXECUTION
MC

R/W

CLC

Clear

000241

1/0

CLV

Clear Vv

CLZ

Clear

000242
000244

3
3

1/0
1/0

CLN
CCC

Clear
Clear

SEC

N
all

Set

000250
000257

3
3

000261

1/0
1/0
1/0

bits

CPU

INSTRUCTION

TIMING

TABLE

A-6

SEV

Set

000262

1/0

SEZ
SEN

Set
Set

2
N

000264
000270

3
3

1/0-

SCC

Set

all

000277

1/0

TABLE

A-7

bits

MISCELLANEOUS

1/0

INSTRUCTIONS

TIMING
MNEMONIC

OP CODE
LISTING

INSTRUCTION

HALT

Halt

WAIT

Wait

RESET
NOP

Reset external
(No operation)

SPL

Set

MFPI

Move

from

MTPI
MFPD

Move
Move

to previous instr space
from previous data space

for

interrupt

priority

level

Move

MTPS

Move

byte

MFPS

Move

byte

from

MFPT

CSM

MTPD

bus

000005
000240

1/0

00023N

1/1

D-1

0056DD
1065SS

3
5

2/0
1/1

D-3
D-1

1066DD

2/0

D-3

1064SS

1/0

D-1

1067DD

1/0

D-3

000007

1/0

supervisor mode

0070DD

3/3

D-1

TABLE

INSTRUCTIONS

PSW

(dst)

A-8

(R0<7:0>)

FLOATING-POINT

OP
MNEMONIC

(svc)

<7:0>

space

PSW

Move from processor
(- proc code

Call

space

DEST
TABLE

000000

instr

R/W

000001

data

EXECUTION
MC

INSTRUCTION

TIMING
EXECUTION MC

CODE

LISTING

NON
MIN

TYPICAL

ABSD

Make

Absolute

1706

fdst

ABSF
ADDD

Make
Add

Absolute

1706
fdst
172 (AC) fsvc

19
41

ADDF
CFCC

Add
Copy

172

(AC)

fsve

Floating

‘
A-8

MODE

MAX

TABLE

F-3

20
119

F-3
F-1

102

F-1

CPU

TABLE

A-8

(Cont)

CLRD
CLRF

Condition
Clear
Clear

.CMPD

Compare

173

(AC

CMPF

Compare

173

(AC

DIVD
DIVF
LDCDF

Divide
Divide
Ld & C

174
174

Dto

LDCFD
LDCID

Codes

5
14
12

F-1

(AC
(AC

+
+

4)
4)

160
59

167
63

F-1
F-1

177

(AC

F-1

177

(AC

F-1

177

(AC)

src

F-4

src

F-4

Ld & C
Integer

177

:
(AC)

LDCLD

Ld & C Long
Integer to D

177

(AC)

src

177

(AC)

src

172
176
172

(AC + 4)
(AC + 4)
(AC + 4)

LDD
LDEXP
LDF
LDFPS

Load
Load
Load
Load

Long

Integer

Exponent
FPP

Multiply

1701

src

171

(AC

Fraction

171

(AC

Multiply
Multiply

171
171

(AC)
(AC)

MULD
MULF

F-4

16
17
12

17
18
13

F-1
F-4
F-1

F-4

and

Separate
Integer

Program

Status

MODF

-F-2
F=2

from

Integer

LDCLF

from

170000
1704 fdst
1704 fdst

LDCIF

MODD

INSTRUCTION TIMING

202

217

268

F-1

115

F-1

f£src
fsrc

165
56

173
61

F-1
F-1

and

NEGD

Negate

1707

fdst

F-3

NEGE

Negate

1707

fdst

F-3

SETD

Set Floating
Double Mode

170011

SETF

Set

170001

170002

170012

Floating

Mode
SETI

Set

Integer

Mode
SETL

Set Long
Mode

Integer

CPU

INSTRUCTION

TABLE

A-8

STCDF

STCDI

D to
St &

F
C

STCDL

STCFD
STCFI
STCFL
STD
STEXP

(Cont)

from
from

176

(AC)

fdst

F-2

Integer

176

(AC)

fdst

F-5

St
to

& C from D
Long Integer

176

(AC)

fdst

F-5

176

(AC)

fdst

F-2

175

(AC

F-5

175

(AC

F-5

174

(AC)
(AC)

fdst

175

dst

12
16

F-5

174

(AC)

fdst

F-2

1702

dst

F-5

Integer

&«

Long

from
from

from

F
F

Integer

Store
Store

STF

Store

STFPD

Store

Exponent

©Store

Status

FPP

Status

1703

dst

Subtract
Subtract

173
173

(AC)
(AC)

TSTD

Test

TSTF

Test

1705
1705

SUBD
SUBF

F-2

FPP

Program
STST

TIMING

TABLE

S-1

SOURCE

fsrc
fsrc

fdst

55
41

11
9

fdst

ADDRESS

47
37

TIMES:

ALL

F-5

122
104

F-1
F-1

DOUBLE

SOURCE

MICROCODE

READ

MODE

CYCLES

OPERAND

MEMORY

0==7

1
2
2
3
3
4
4

0==7
0--6
7
O0--6
7
0--6
7

2
2
1
4
3
3
6

1
1
1
2
2
1
2

(Note

5
5

O0--=6
7

5
8

2
3

(Note

O==7

0==7

CPU

TABLE

D-1

DESTINATION

ADDRESS:

READ-ONLY

INSTRUCTION TIMING

SINGLE

OPERAND

DESTINATION

MICROCODE

READ MEMORY

MODE

CYCLES

0-=7

O0==7

O0--6

1
1

O0--6

3
4

3
3
7

7
O--6
7

(Note

5
5

0--6
7

5
9

2
3

(Note

O0==7

0--7

D-2

DESTINATION

ADDRESS

TIMES:

READ-ONLY

DOUBLE

OPERAND

DESTINATION

MICROCODE

READ MEMORY

MODE

CYCLES

O==7

0-=7

2
2

0--6
7

3
2

1
1

0--6

3
4

7
0--6

4
4

2
1

5
5

7
0--6
7

8
6

2
2

(Note

6
7

O==7
0--7

10
5
7

3
2
3

(Note

A-11

CPU

INSTRUCTION

TABLE

TIMING

D-3

DESTINATION

ADDRESS

TIMES:

DESTINATION

MICROCODE

MODE

CYCLES

WRITE-ONLY

MEMORY

CYCLES

READ

WRITE

0--6

1
1
2
2
3
3

0--6
7
0--6
7
0--6
7

2
6
2
6
4
3

0
1
0
1
1
1

0
1

0--6

5
5
6
7

TABLE

D-4

0--6

- 0=-=7

0-=7

DESTINATION

ADDRESS

TIMES:

READ

1
1
1
1

1
1

1
1
1
1

MODIFY

WRITE

CYCLES

DESTINATION

MICROCODE

MEMORY

MODE

CYCLES

Read

WRITE

0--6

1
1
2
2
3
3
4
4
5
5
6
7

0--6
7
0--6
7
0--6
7
O0--6
7
O--6
7
O==7
0=-=7

3
7
3
7
5
4
4
8
6
10
5
7

1
2
1
2
2
2
1
2
2
3
2
3

A-12

1
1
1
1
1
1
1
1
1

1
1

(Note

CPU
TABLE

D-5

DESTINATION ADDRESS

DESTINATION

MODE

INSTRUCTION TIMING

TIMES:

JMP

MICROCODE

MEMORY CYCLES

CYCLES

READ

WRITE

DESTINATION

MICROCODE

MEMORY

MODE

CYCLES

READ

CYCLES
WRITE

0--7

3
3

0--6
7

10
9

3
3

1
1

0-=7

5
6

0-=7
0--6

11
10

3
3

1
1

0--7

MICROCODE

MEMORY

MODE

CYCLES

0--6

READ

WRITE

CPU

INSTRUCTION
TABLE

TIMING

F-1

3
3

0--6

0-=7

0--7

2
3

o
0

0
0

0-=-7

0--7

DOUBLE

PRECISION

O==7

0--6

3
3

0--6
7

6
5

5
5

0
0

O==7
Q0==7

4
5

5
6
7

O==7
O==7

6
8

5
6

0
0)

TABLE

F-2

FLOATING

15)

DESTINATION

MICROCODE

MEMORY

MODE

CYCLES

SINGLE

(Note

MODES

READ

1--7

WRITE

PRECISIOCN

0=-=7

0--6

3
3

0--6
7

4
3

1
1

2
2

0==7

5
6

0==7
0-=7

5
4

1
1

2
2

O0==7

DOUBLE

PRECISION

0=-=7

2
2

0--6
7

5
(-1).(Note

0
O

4
1

0--6

A-14

15)

CPU

TABLE

INSTRUCTION

TIMING

F-2(Cont)

4
5

0-=7
0--7

6
7 .

0
1

4
4

0-=7

0--7

MICROCODE

MEMORY

MODE

CYCLES

READ

WRITE

SINGLE

PRECISION

0==7

0--6

3
3

0--6
7

6
5

(Note

15)

3
3

2
2

O==7

5
6
7

0=-=7
O=-=7
0==7

7
6
8

3
3
4

2
2
2

MICROCODE

MEMORY

MODE

CYCLES

READ

DOUBLE

WRITE

PRECISION

O0==7

O0--6

)

0--6

(-2)

(Note

15)

0=-=7

5
6

0=-=7
O0==7

11
10

5
5

4
4

0==7

- 6

CPU

INSTRUCTION

TIMING

TABLE

F-4

INTERGER

SOURCE

MODES

1--7

MICROCODE

MEMORY

MODE

CYCLES

READ

WRITE

INTERGER

0=-=7

2
2

O0--6
7

2
0

1
1

0
0

3
3

0--6
7

3
2

2
2

0
0

0--7
O0==7
O==7
0--7

3
4
3
5

1
2
2
3

5
6
7

LONG

(Note

15)

0
0
0

INTERGER

O0==7

0--6

3
3

0--6
7

5
4

(Note

15)

3
3

0
0

0--7
0==7

2
3

5
6

O==7

0-=7

MICROCODE

MEMORY

MODE

CYCLES

READ

WRITE

INTERGER

0--7

0--6

A-16

CPU

TABLE

F-5

0--7

2
3 4

1
1
1

0--7

0--6
7

0
0

0--6

)

3
4

7
0--7

4
5

1
0

2
2

0--7

6
7

0--7
0--7

5
7

1
2

2
2

0--7

6
7

LONG

AND

DESTINATION

and

TABLE

Subtract

modes

autodecrement

one

READ-MOLIFY-WRITE
READ-ONLY

and

bookkeeping

purposes,

READ-ONLY

FETCH

and

bookkeeping

purposes,

Add

Subtract

both

or
17

perform

the

link

source

the

READ

Add

the

Add

overflow occurs.

quotient

A-17

mode

operations.

accounted

destination

for

mode

READ
operations.
READs is accounted
for

source mode

WRITE-ONLY

operand

destination

READs

perform
one of the

and

used.

FETCHING TIMING.

source

READ-MODIFY-WRITE

actually

Subtract

one of
TIMING.

references

EXECUTE,

NOTES

PC,
07

READ-MODIFY-WRITE

actually

EXECUTE,

read

mode

references

the

INTERGER

SOURCE

the

TIMING

(Cont)

3
4
5

A.2

INSTRUCTION

PC.

negative.

not

even.

zero.

For

CPU

INSTRUCTION

TIMING

Add

MC and

Add

per

Add

read

but only

the

source mode

used

destination

is not used.

shift.

source
if

shift

1is

not zero.

Subtract

11.

Add 4 MC and 1 read if the PC
1is
register, but only if source mode

12.

Divide

13.

Timing for no shift. Add 1 MC if a left shift.
(Notes
9, 11 apply.) Add 2 MC for a right shift.
(Notes 8, 10,

zero

one

<15:6>

10.

operand

executes

only.

used
47 or

(see

as
a
destination
57 1is not used.

note

6).

8,
11

apply.)
14.

Add

one

15.

Mode 27 references only access single word
operands.
The
excution
time
listed
has
been
compensated
1in order to
accurately compute the total execution time.

A-18

than

used.

APPENDIX

PDP-11/84

HARDWARE/SOFTWARE

DIFFERENCES

PDP-11/84

B.l

HARDWARE/SOFTWARE

UNIBUS

POWER

DIFFERENCES

PROTOCOL

DIFFERENCES

The Unibus Power up protocol on
different than on most PDP-lls.
With

most

held

asserted

PDP-11

LINE

PDP-11/84

systems,

for

LOW

(DC

the

minimum
LO

systems,

Unibus

the

PDP-11/84
systems
(See Figure B-1.)

after

(INIT
the

negation

up.
signal

INIT

held

for
a minimum of 16 milliseconds after the negation
power up.
This difference wil not affect any system

DC Fower ok

slightly
)

INTIALIZE

milliseconds

power

Unibus

signal

1is

asserted

of DCLO L on
operations.

/
I
l

DCLO L

I
|
INIT L XXXXXXXXIXXXX\
/
l
l
I
l
l
I
| (=== 1¢-—-===-2) l
|
.
|
I
|
S us min.

Most

XXXXXXxxx

FIGURE

B.2

PDP-11/84

PDP-11/84-based

B-1

Cache

Data

Switch

16 us min.,
10 ms min.

Y----

|
|

undefined

POWER

11/44

PROTOCOL

HARDWARE

products may

applitions. However,
hardware features:
o

=
=

FDP-11/84
UNIBUS PDF-1ls

)---

DIFFERENCES

replace

it does

TIMING

not

the

contain

PDP-11/44
the

(17777570).

PDP-11/84-based products
in the 11/44:
Dual

general

SPL,

MTPS,

contain

MFPS,

certain
PDP-11/44

(17777754)

the

following

functionality

present
o

following

set

TSTSET,

WRTLCK
B-2

instructions.

not

PDP-11/84
The following registers are
Primarily,
the
registers
code,
code.

not
are

HARDWARE/SOFTWARE

DIFFERENCES

implemented
on
the
used
for testing by

PDP-11/44.

the CPU ROM
other diagnostics or system configuration by
the
CPU
ROM
They are not normally used by the system level software.

Boot and Diagnostic controller register (17777520)

ROM page control

Configuration

Diagnostié controller register (17777730)

Diagnostic

Memory

and

Data

Display

configuration

(17777522)
register

(17777524)

(17777732)

(17777734)

DMA

transfers may not occur between UNIBUS
peripehrals
and
any
registers
1located
on
the. CPU.
DMA
transfers may only occur
between the UNIBUS peripherals and the UBA.
DMA
transfers
may
also
occur
between UNIRBRUS periph erals and the addresses of the
ROM

sockets

Table

B-1

PDP-11/44

located

the

summarizes
and

the

(17

ADDRESS

B-1

773

000-

hardware

PDP-11/84-based

TABLE

17777776

UBA

773

differences

776).

between

products.

11/84-11/44

DIFFERENCES

FUNCTION

DIFFERENCBS

Added

set

select

bit<11>

17777772

PIRQ

17777766

CPU Error

Data

No difference
Unibus monitoring bits
not

implemented

Not

implemented

17777754

Cache

17777752

Hit/Miss

No difference

17777750

Maintenance

Hardware
(see

17777746

Cache

Control

Hardware
(see

17777744

Memory

Error

differences

Chapter

“Hardware
(see

differences

Chapter

differences

Chapter

the

PDP-11/84

HARDWARE/SOFTWARE

DIFFERENCES

TABLE

17777676

B-1

(Cont)

fiser Data PAR

No difference

User

Instruction

didfference

17777640

PAR

User

Data

difference

User

Instruction

difference

17777600

PDR

17777576

MMR2

difference

17777574

MMRI1

difference

17777572

MMRO

17777760

17777656

17777636
to

PDR

17777620
17777616

Eliminated maintenance
mode

17777570

Switch

17772516

MMR3

17772376
to

Kernel

Data

Kernel

Instruction

No difference

17772340

PAR

Kernel

Data PDR

No difference

Kernel

Instruction

No difference

PAR

Not

implemented

difference

17772360

17772356

17772336

to
17772320
17772316

PDP-11/84

HARDWARE/SOFTWARE

DIFFERENCES

(Cont)

TABLE B-1

17772300

17772276
to

Supervisor

Data PAR

No difference

17772260
17772256

to
17772240

Supervisor

No difference

17772236

to
17772220

Supervisor

Data

PDR

No difference

17772216

Supervisor

difference

17772200

B.3

PDP-11/84

The

PDP-11/84

may

replace

does

not

However,

11/70

HARDWARE

the

DIFFERENCES

PDP-11/70

contain

the

certain

following

applications.

PDP-11/70

hardware

features:

Stack

Limit

(17777774)

Micro

Break

(17777770)

System

Size

Physical

Switch

The

MTPS,

Bypass

Registers

the

©o

17777762)

Registers

(17777740,

17777742)

(17777570).

products

contain

MFPT,

cache

bit

registers

CSM,

the

following

functionality

not

the
registers
diagnostics or

code.

are

not

TSTSET,

WRTLCK

instruction

PDRs.

are

Primarily,
code, other
They

(17777760,

11/70:

MFPS,

following

(17777764)

Error Address

DCJll-based

present

not

implemented

ont

the

are
wused
for testing
system configuration by

normally

used
B-5

the

system

PDP-11/44.

by the CPU
the
CPU

level

ROM
ROM

software.

PDP-11/84

HARDWARE/SOFTWARE

Boot

and

ROM

page

Configuration and Display fegister (17777524)

Diagnostic controller register

Diagnostic

Memory

DMA

Diagnostic

control

Data

transfers

may

occur
sockets

Table

B-2

PDP-11/70

between

CPU.
and

UNIBUS
ont

summarizes

the

TABLE

ADDRESS

(17777730)

UNIBUS

DMA
the

(17

transfers
DMA

773

the. hardware

B-2

11/84

products.

peripehrals

UBA.

peripherals
UBA

PDP-11/84-based

(17777734)

between

the

(17777520)

(17777732)

occur

(17777522)

peripherals

located

and

17777776

not

registers
located
the UNIBUS

also

controller

configuration

between
ROM

DIFFERENCES

and
000

the
-

addresses
773

between

DIFFERENCES

Added suspended
instruction bit

Limit

Not

<8>,

17777774

Stack

17777772

PIRQ

No difference.

17777770

Micro Break

Net

17777766

CPU

No difference.

17777764

System

Not

implemented.

17777760

System

Size

Not

implemented.

17777752

Hit/Miss

17777750

Maintenance

Hardware

Error

implemented.

difference.

(see

17777746

Cache

Control

Hardware
-

(see

differences

Chapter

differences

Chapter

the

776).

DIFFERENCES

FUNCTION

any

may only occur
transfers
may

differences

11/70

and

the

PDP-11/84

TABLE

17777744

Memory

B-2

HARDWARE/SOFTWARE

(Cont)

Hardware differences

Error

(see

Error

DIFFERENCES

Chapter

Not

implemented.

Address

Not

implemented.

PAR

difference.

17777742

High

Address

17777740

Low

Error

User

Data

User

Instruction

User

Data

17777676
to

17777660
17777656
to

PAR

17777640
17777636
to

Added

bypass cache,
eliminated access flags

PDR

17777620

and

access

than

modes

and

other

17777616
to

User

Instruction

PDR

17777600

Added bypass cache,
eliminated access flags
and access modes other
than 0, 2, and 6.

17777576

MMR2

No difference.

17777574

MMR1

17777572

MMRO

difference.

Eliminated

traps,

maintenance mode,

instruction
17777570

Switch

17772516

MMR3

Not

implemented.

Added

CSM

enable

17772376
to

Kernel

Data

PAR

Kernel

Instruction

difference.

17772360
17772356
to

17772340

PAR

and

complete.

bit

<3>.

PDP-11/84

HARDWARE/SOFTWARE

TABLE

B-2

DIFFERENCES

(Cont)

17772336
to

Kernel

Data

PDR

Added

17772320

bypass

eliminated

access

modes

and

cache,

flag

other

than

and
0,

17772316
to

Kernel

Instruction

PDR

17772300

Added

bypass

eliminated

cache,

access

modes

and

difference.

flag

other

than

and
0,

17772276
to

Supervisor

Data .PAR

Supervisor

Instruction

No difference.

17772240

PAR

Data

Added

17772260

17772256

17772236
to

Supervisor

PDR

17772220

bypass

eliminated
access

modes

and

cache,

access

flag

other

than

and
0,

17772216
to

Supervisor

17772200

PDR

B.4

SOFTWARE

Table B-3
language

PDP-11

Instruction

Added

bypass

eliminated
access

modes

and

cache,

access
other

flag
than

and
0,

DIFFERENCES

summarizes the programming differences (at the assembly
1level)
between
the
DCJ1l and other processors in the

family.

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B-20

APPENDIX
BACKPLANE

TEST

C
CONNECTORS

CONNECTORS

NEW CONN

AO6
- A0S
AO4

A03
AQ2
A0l
A0O

BBSY
NPR

GND
GND
D15
D14
D13
D12

D11
D10
D09
D08
D06

D05
DO4

L
r‘

AO07

alololelalolololialiolial
ol ol ol ol

J18-34
J18-33
J18-32
Jl8-31
J18-30
Jl8-29
J18-28
J18-27
J18-26
Jl8-25
J18-24
Jl8-23
J18-22
Jlg-21
Jl18+20
Jl18-19
Jlg-18
J18-17
J18-16
J18-15
Jlg-14
Jl18-13
J18-12
Jl8-11
Jlg-10
Jl8-9
Jlg-8
J18=7
J18-6
J18-5
Jig-4
J18-3
J18-2
Jig-1
J19-20
J19-19
J19-18
J19-17
J19-16
Jl19-15
J19-14
J19-13
J19-12
J19-11
J19-10
J19-9
J19-8
J19-7
J19-6
J19-5
J19-4
J19-3
J19-2
J19=1

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BACKPLANE

DO3
D02
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INTR L
SACK L
GND

APPENDIX
BACKPLANE

ASSIGNMENTS

BACKPLANE

ASSIGNMENTS

ROW

IDE
PIN

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NPG

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BACKPLANE PIN ASSIGNMENTS

MODIFIED UNIBUS
Pin DESIGNATIONS

STANDARD UNIBUS
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APPENDIX
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V.7

V.6

APPENDIX

ROM

DIFFERENCES

COLE

V.7

V.6

ROM

F.1

INTRODUCTION

The

command

installed
EPROMS

out

CODE

descriptions

are

with

each

V6.0

time

displayed

.necessary

DIFFERENCES

the

ROM

code

7.0

(V7.0)

ROM

code.

The

version

Set

the upper

remove

version

number.

The

version

numbers.

the

Location
(M8190)

(Low

E117

(High

CPU

entered

Part

Byte)
Byte)

the

module

lists

the

EPROMs

PDP-11/84s

that

contain

ROM

from

code .is

Dialog

mode

printout.

the

Number

assume

Earlier

corner of

following

Socket

El16

mode

right

CPU

for

Version

part

V7.0

Part

and

1is

not

the

ROM

code

numbers

and

determine

ROM

typed

Number

V6.0

23-116E5-00

23-077E5-00

23-117E5-00

23-078E5-00

F.2 BOOT SUPPORT FOR TAPE MSCP DEVICES (TU81)
V6.0

the
ROM
the

ROM

code

does

not

contain

built

tape

MSCP

bootstrap

for

a M9312
written

type
into

TU81
tape
drive.
The TU81 could be booted 1f
tape MSCP boot was installed in the UBA board or
EEPROM.

V7.0

ROM

The

device

F.3

V7.0

In V7.0

code

has

name

DISABLE

built

tape

MSCP

boot

program

for

the

has

been

added

TU81.

MU.

SETUP

Setup mode

MODE

PARAMETER

another

parameter

the

parameters
command (2).
This command allows the user to disable
entry into Setup mode if force Dialog mode 1is not selected.
This
command
was added to prevent unauthorized entry into Setup mode.

This
change
assumes
that
the
force
Dialog
mode
controlled or that switch 5 on the KDJ11-B CPU is "ON"
unauthorized access to Setup mode.
When

all

Setup mode

references

will

cause

V6.0

Setup mode

F.4

V7.0

disabled

the

invalid

DISABLE

can

ALL

and

the

ROM

code

1in

Dialog

mode

Setup command

are

eliminated.

Typing

Setup

command

always

TESTING

response

entered

from

switch
1is
to prevent

the

ROM

code.

Dialog mode.

PARAMETER

In V7.0 in
Setup
mode
another
parameter
has
been
added
to
Parameters
Command
2.
When
set,
this parameter disables all
memory and cache test- ing if force Dialog
1is
not
set.
Force
Dialog causes all testing to be run.

F-2

V.7

F.5

MNEMONIC

In V7.0

under

173024

FOR

the

ROM

type

for

EDIT/CREATE

V7.0

the

F.7

V6.0

the

UBA

edit/create

LOCATION

for

This
The

boots

the

address

located

Unibus must be

even
In

command

number
octal

1in

Setup

entry is
number

mode

for

EEPROM

now decimal.
In V6.0
which
was
converted

the
to

systems

only

M9312

module,

and

the

for

device

the

trap

ROM

mnemonic

descriptions,

location

due

found

not

found

is
the

ROM

error

This problem only occurs if the List command
problem does not affect the Boot command.

ROM

DIFFERENCES

check of the
address
data.
or greater but could be -0dd.

UNIBUS

table

unexpectedly

code.

CODE

value.

TRAP

Look

ROM

COMMAND

boots, the highest unit
user had to type in
an
decimal

ROM

device

address only.
This 1s the only
V6.0 the address must be 165000

-F.6

V.6

BOOTS

B mnemonic

M9312

can

still

list
command.
Pialog mode by

booted

even

there

either

code
the

the
will

V6.0

ROM

executed.

problem

1in

the

The system does not hang and the user may reenter
typing <CR>.
This problem has been
corrected
in

v7.C.

F.8

DISK

MSCP

For

V6.0

AUTO

the

BOOT

MSCP

ROUTINE

auto

boot

(device

name

A),

the

boot

program

will
try to boot removable media from units 0 to 7, then it will
try fixed media units from 0 to 7.
Only drives attached
to
the
controller
at the standard disk MSCP address (172150) are tried.
The MSCP auto boot does not support unit numbers above 7,
auto
boot
will hang if the controller has a unit number
than 7 that responds.

and the
greater

For

V7.0

removmedia

the

able
units

from

attempts

fails

boot

the

MSCP
0

Dboot

first

160334

floating
no

boot,

from
to

disk
next

For
the

will
MSCP
unit

from

boot
to

each

then

unit,
disk

the

device

program will

255,

standard

attempt

try

will

the

MSCP

same

1if

try

boot

boot
fixed

program

address,

this

unit

number

from

the

1is

present

before

number.

controller

devices

the

wunits

255.

using

program

first
floating
continuing to the

The

auto

media

present,

160010

to
L4

F-3

would

160330.

The main

address
advantage

V.7

V.6

V7.0

without
the

ROM

CODE

that

making

controller

address

DIFFERENCES

allows

any

user

entries

address

into
set

add

the

second

translation

according

disk

MSCP

table

the

device

long

floating

as
CSR

rules.

F.9 DISK MSCP BOOT DIFFERENCES
When

trying

command,

the

boot

V7.0

code

device

will

using

the

automatically

Dialog

try

the

mode

first

Boot

floating

controller also 1f the standard controller reports
an
error
of
any
type as long as the standard controller exists (no timeout).
If an error occurs on both controllers the
V7.0
ROM
code
will

out

standard

error

address

Nonexistent

messages

for

each

controller

starting

with

the

unit

1is

first.

error

messages

are

not

typed

out

unless

the

non- existent on both controllers.
1If the second controller does
not exist at the proper floating address the ROM code will
print
out only messages associliated with the standard controller.

the

only
or

translation
one

table

controller

used,

tried

the

regardless

/A
of

switch
the

1is

wused

existance

then
of

two

controllers.

F.10

INITIALIZE

V7.0

has

been

COMMAND

changed

PMG
count
value
value for the PMG
V7.0

ROM

F.ll

MEMORY

such

that

the

1initialize

command

sets

the

to 7 as opposed to 0 for V6.0.
The recommended
count is 7 for all KDJ11-B's with both V6.0 and

code.

TESTING

In V7.0 code all consecutive memory starting from location
0
1is
written
at
1least
once
at power up unless all testing has been
disabled.
In V6.0 memory above 248 KB may not be written if
the
long memory test is disabled or CTRL C 1is typed.

F.12

POWER UP OR

For V6.0,

the ROM code

and
sets
up
recovery trap

RESTART MODE

Reads

checks

SET

for

the presence of

the
KMCR
accordingly.
through location 24, the

and

saves

the

contents

Unibus

Before emulating
ROM code:

location

24,

memory
a

power

Executes

Restores

the

When

the

test

contents

quick

read/write

orginal

the

ROM code

test

the

V.6

ROM

CODE

location

completed

into

specified in loca- tion 24.
‘memory cannot be present in
For V7.0,

contents

successfully

location

V.7

the

PSW and

DIFFERENCES

24,

and

24.

ROM

code

jumps

Yroads

the

Since location
24
1is
tested,
the lower portion of memory.

does

not

<check

for

Unibus

the

location

memory

ROM

and

assumes
that
when
mode 24 was selected that the system had the
final configuration of memory already installed.
Location 24
1is
not
tested,
and 1t is possible to have ROM in the lower portion
of memory.
the PSW and

F.13

POWER

For v6.0

The ROM code
jumps to the

SET

loads the con- tents of location 26
location specified in location 24.

WITH BATTERY

The

selected

mode

The

battery

indicates

The

Ignore

V7.0

Battery

power

that

the

function

Dialog

mode

regardless

up,

voltages

are

not

then

the

power

up,

that

the

set,

lost,

restart mode

and

selection.

if:

The

selected

mode

The

battery

indicates

The

Ignore

4.,

BACKUP

1f:

For

into

Execute

Battery

function

voltages

are

not

then

the Restart mode selection
go to Dialog mode.

set,
1if

lost,

not

Break

bit

and

mode

otherwlse

F.14

ENABLING HALT ON BREAK

V6.0

ROM

code

will

not

enable

the

Halt

the

BCSR

until either one break has been received and discarded, any valid
character has been received except XON, or the ROM code has given
up
control
of
the CPU.
This was done to allow the ROM code to
ignore the break that often comes
from
certain
terminals
when
they are powered up.
Ld

V.7

V.6

In V7.0

ROM

the

CODE

Halt

DIFFERENCES

Break

bit

1is

set

1mmediately after

the

"Testing
1in
progress
Please
wait
message" is printed out.
Since halt on break is gen- erally enabled only in a
single-user
environment, this feature was not needed and has been removed.
In either case, the Halt on Break bit does not have
the keylock switch is in the SECURE position.

F.15

CTRL

V6.0

and U.

work

the

AND

during

In V7.0
same

arror

CTRL

input

CTRL R and

inputs are

before.

1if

ECHOING

keyboard

these

any effect

These

character

CTRL U are echoed

not echoed.

functions

1is

not

are

always

The

functions still

not

echoed

available

because

all

terminals.

F.16

SETUP

COMMAND

In V7.0, Command 5 in Setup mode has been deleted.
The
command
was
originally
included to allow different character sets 1in
the

console

terminal

to be

automatically selected by

the

ROM code

when
the
user changed from English text to local text, or local
text to English.
The command is
not
required
since
all
text
printed
on
the screen uses only the standard ASCII charac- ters

which

are generally available

all

terminals.

Special characters used in other
langauges
are
represented
Dby
using
fallDback representations in standard ASCII.
1In V7.0 1in
Setup mode the descrip- tion for Command 5 is:
Reserved.
If the
command

typed,

F.17 AUTOMATIC

ignored.

BOOT SEQUENCE MESSAGE

In V7.0, the ROM code will print out a
message
indicating
when
the
automatic
boot
sequence
1is started when auto boot mode 1is
selected.
This message in- dicates that all tests are
complete,
V7.0 the
In
sequence.
boot
auto
the
starting
is
code
ROM
the
and
device
the
of
number
unit
and
name
the
out
ROM code will print
booted after

the starting

The following examples
V6.0

example:

system message.

illustrate the V7.0 and V6.0 messages.

V.7 - V.6 ROM CODE DIFFERENCES

Testing in progress - Please
Memory size 1s 512 K Bytes
9

Step

memory

Step

Starting

V7.0

wait

test

345

system

example:

Testing

progress

Please

Memory size 1is 512
9 Step memory test
Step 1 2 345 6

Starting

boot

automatic

wait

Bytes
‘
89

Starting system from DUO

F.18

BOOT

A single

COMMAND

LIST

ADDITION

letter mnemonic

(L)

has

been

added

the

boot

list
in
v7.0.
L
causes
the
automatic
boot
continously
1loop
until
one
of
the
selected
successfully
booted.
Normally, the last device in
table

followed

with

the

mnemonic

which

If
none of the previous devices where
print out an error message and request
If
at

command

sequence
devices
the

auto
table.
ROM code will
proceeding.

terminates

bootable the
input before

the

follows the last device the ROM code will restart the
the
beginning
and continously try every device in the

until

one

booted

not

the

operator

types

CTRL

to
is
boot

table
table

abort

the

sequence.

V6.0

ROMs

contain

this

feature.

However,

can

implemented
by
writting
a
small
EEPROM
boot
to emulate the
feature.
The feature is useful for fault tolerant booting for
a
system that must continously try until a successful boot occurs.
The

following

loaded
V6.0

1into

roms.

the

source

the

EEPROM

that

This

program

code

and

allows
not

description
the

needed

loop

function

for v7.0.

the
to

program
work

for

V.7

V.6

ROM

CODE

DIFFERENCES

.=10000

;Program

1is

relocatable

another

;address.
START:

tstb

@#177560

;Has

bpl

10S$

s NO-Go

any

characters

exit

s Yes-Check
movb
bic

. @#177562,r5
#177600,r5

cmp
beqg

the

been

typed

auto- boot

character

+Get the character from the RBUF
sClear off all bits above bit 07

rs5,#3
20$

+Is the character a CTRL C ?
;Yes-Then return to ROM code with
+r5 set to 3 which will cause the
;boot

10S:

back

sequence

mov

#301,r5

sL,oad

movb

#100,@#177611

+This

will

sand

with

make

value

fake

out

aborted.

for

drive

the

ROM

restart

the

error

code

auto

boot

; Sequence

20S:

bic

#760,@#177520

*Make
+the

jmp

@#165762

sure

the

ROMs

are

selected

s Return to the ROM code.
s If r5 1is 301 then restart the auto
;s boot sequence. If r5 is 3 then
;abort the sequence and go to Dialog
s mode.

The

following

the

EEPROM.

is
It

example

assumes

name (mnemonic) of L.
delete or rename that

KDJ11-B

showing

there

the

not

program being

already

boot

loaded

with

Setup mode

Edit/create an EEPROM boot

Type CTRL Z to exit or press the RETURN key for No change
free

in the EFEPROM

Device name

address
Beginning
Last byte address
Start address

Highest Unit number

= AA

= 000600
= 000615
= 000600
=

New

= L

New = 10000
New = 10047
New = 10000
New =

377

into

device

If there
was,
the
wuser
would
have
boot before saving the new program.

Press the RETURN key for Help
Type a command then press the RETURN key:

1410 Bytes

1in

BCSR

V.7

Device

Description

V.6

ROM CODE

DIFFERENCES

BOOT

]

ROM

ODT>

010000/000000

105737

ROM

ODT>

010002/000000
010004,/000000
010006,/000000

177560

ROM

ODT>

ROM

ODT>

010010/000000

ODT>

ROM

100007
113705

177562

010012/000000 42705
ROM
ROM ODT> 010014/000000 177600
ROM ODT> 010016/00000¢C 22705
ROM ODT> 010020/000000 3
ROM OoDT> 010022/000000 1405
ROM OoDT> 010024/000000 12705
ROM ODT> 010026/000000 301
ROM ODT> 010030/000000 112737
ROM OoDT> 010032/000000 100
ROM ODT> 010034/000000 177611
ROM ODT> 010036/000000 42737
ROM ODT> 010040,/000000 760
ROM ODT> 010042/000000 177520
ROM ODT> 010044/000000 137
ROM ODT> 010046,/000000 165762
ROM ODT> 010050/000000 ~2 (exit)
ODT>

KDJ11-B

Press

Setup mode

the

Type

Save

boot

RETURN

command

into

Are

you

sure

Type

command

for

Help

then

key

press

the

EEPROM

0=No,

then

Writing

the

KDJ11-B

Setup mode

Press

Type

F.19

the

LOCAL

Local

RETURN

press
-

key

for

SUPPORT

translations

MAP

command

V7.0

key:

the

are

RETURN

not

key:

supported

V6.0.

Only

V7.0

will

translations.

F.20 ADDITIONAL MAP COMMAND
The

RETURN

Help

LANGUAGE

language

the

Please wait

then press

local

key:

l=Yes

command

language

supports

EEPROM

RETURN

has

FEATURE
an

F-9

additional

feature.

V.7

V.6

ROM

CODE

DIFFERENCES

determine the speed of
the

number

during

one

SOB

The value is
1t is within

the

out .

value
The

the Jll

crystal.

instructions
cycle

the

that

can

internal

This
be

is done by counting

executed

DLART

compared against a table of standard
0.1% of any of these then that value

does

not match,

standard

‘any errors have
calculated.

values

occurred

then
are:

during

the

actual

15.206,

testing

the

out

cache

clock.

17,

values, and
1if
is printed out.

wvalue

18,

and

speed

will

printed
20.

1If

not

APPENDIX

MULTI

BOOT

ROM

CONTROL

TRANSFER

MULTI

G.1l
In

BOOT

ROM

CONTROL

TRANSFER

INTRCDUCTION
V6.0

and

ROMs

which

V7.0

the

UBA

use

ROM

code,

the

routine

these
Dboots
will
not list and can not be
ROM code without using a small EEPROM boot
control
"future

the

releases

G.2

TRANSFER

The

following

to
in

ROMs.

This

CPU

the

CONTROL

problem
ROM

the

socket

the

bcsr

177520

dcsr

177730

010000

052737

010002
010004
010006
010010

000200

simpified

Note:

will

from the base
to
transfer

corrected

any

code.

bis

program

#200,@#bcsr

bic

#10,@#dcsr

sec
jmp

@#173012

ROM

on M9312

042737

052737.

ROM

not

adjusted

used

control

transfer

1in.

177520

started
program

boot 1if needed.
The starting address
to be changed depending
on
the
ROM

located

042737
000010
177730
000261
000137
173012

010012
010014
010016
010020

1identifies

PROGRAM

any UBA ROM or M9312 ROM
location 010020 may have

and

which

or the M9312 will not correctly identify boot
than one ROM -for the boot.
Because of
this,

module

;

disable

173nnn

;

then

CPU

ROMs

address

s
s
:
;
¢+
s
s
s

make sure UBA
are enabled

;

2-4.

range

ROMs

disable diagnostics
go start boot for ROMs
1in sockets 1-3 of UBA.
Change 16/173012 to 173212
1f ROMs are in UBA sockets

change

010006

from
'

socket

200

for

then

each

address

socket

address

1730nn

for

socket

address
address

=
=

1732nn
1734nn

for
for

socket
socket

2
3

address

1736nn

for

socket

10020 must

follows:

The previous program will work
for
the
DECNET
ROM
boots
for
DMCl11/DMR11,
DUPl1l,
DUll
and
DL11-E
with
the following part
numbers if the user types in the correct device name
and
device
description
as follows when the program is being loaded into the
L4

G-2

EEPROM

under

numbers

ROM

The

Setup mode

start

PART

with

23-

NUMBERS

the

(e.g.,

MULTI

BOOT

ROM

code.

CPU

ROM

CONTROL

Note

that

23-86A%9-00).

DEVICE

NAME

all

part

DEVICE

DESCRIPTION

862A9,

863A9,

B864AS

DMC11/DMR11

865A9,

866A9,

867A9

DUP11

868A9,

869A9,

870A9

DU11l

926A9,

927A9,

928A9

DL11-E

same

TRANSFER

general program could be used for any multi ROM boot
or
ROM
boot which does not follow the M9312 ROM format
The starting address may have to be adjusted to start

any
single
standards.
the

boot.

G.3

EEPROM

LOAD

program
being
boot ROMs.

EXAMPLE

loaded

The

into

following

the

EEPROM

for

the

example

DECNET

the

DMCl1/DMR11

MULTI

BOOT

ROM

KDJ11-B

Press
Type

Setup

the
a

CONTROL

TRANSFER

mode

RETURN

command

key

then

for

Help

press

the

Edit/create

EEPROM

Type

CTRL

exit

press

1410

Bytes

free

the

EEPROM

Device

Last

byte

address

Start add ress
Highest U nit number

the

RETURN

10000

000615

New

10021

000600

New

10000
15
DMR11/DMC11

New

052737

ROM

000200

ROM

ODT>

ROM

ODT>

ROM

ODT>

ROM

ODT>

ROM

ODT>

010002/000000
010004/000000
010006/000000
010010/000000
010012/000000
010014/000000
010016/000000
010020/000000
010022/000000

ROM

ODT>

KDJ11-B

177520
042737

000010
177730
000261
000137
173012
~Z

S etup mode

Press

the

Type a command

RETURN

then press

Save

boot

the

into

Are

you

sure

Type

command

Writing

the

key

for

the

RETURN key:

RETURN

l1=Yes

then press

EEPROM

Help

EEPROM

0=No,

change

010000,/000000

ODT>

New

ODT>

for

New

ODT>

ROM

key

000600

ROM

De scription

Device

key:

boot

name

Beginning

RETURN

the

Please wait

key:

APPENDIX

CONFIGURATION

MODIFICATION

CONFIGURATION

H.l1

MODIFICATION

INTRODUCTION

Figure

H-1

shows

the

format

the

Configuration
Register
(BCR)
and
the
switches which allow the register values
gaining
accessto
the
CPU
module.
register are not driven they may be read
In order for a register bit
switch
which controls that
to allow control
KDJ11-B
module
which causes the

the

Bits

position

7-4

unless
switch

The

any

numbers

not

connected

set

built

KDJ11-B module.
connection

<Switches

There

the

and

KDJ1l1-B ====-=>

systems.
external

Diagnostic

<connections to-external
to be
modified
without
Since
Dbits
15-8 of the
as 1 or 0.

1-4>

remotely

KDJ11-B module

connected

PDP-11/84
switch

pack

external

the

PDP-11/84

By connecting J3 to
switches it would be

|
k

possible to remotely control
these four bits in custom
applications.

—c
v ———————
Yemm

mode switch on the rear panel
by

way

module.

the

KDJ11-B

by way

Drm

e ————

the

KDJ11-B module.

don't

FIGURE

care
H-1

the
OFF

switch.

are

must

bits

also

value to be remotely
controled,
bit on the KDJ11-B module must be

external

1-4>

bits

a custom cable
by the user.

Switch

and

to be passed to the
external
switch.
When
a
switch is ON, the corresponding line is grounded
register bit to always be read as a 0 regardless

<Switches

systems.

Boot

BOOT

:
AND

DIAGNOSTIC
L

CONFIGURATION

The

8-position

KDJ11-B.

switch

Switches

1-8

correspond

address

17777524.

H.2

ROM

CODE

The

following

values

pack
6-8

mounted

select

the

bits

baud

07-00

the

handle

rate

for

the

ROM

MODIFICATION

end

the

DLART

read-only

the
chip.

BCR

interprets

the

INTERPRETATION

paragraphs

the

bits

BCR

7:3

describe

when

<switches

how

read.

The

code

ROM

code

only

looks

1-5>.
NOTE

The

following

discussion

switch is OFF, the line
HIGH by the CPU module.
grounding
considered

ON.

When

using

switch

the
Normally

switches

what

action

When

off,

Dialog
cannot

external

Switch

mode
occur

Switches

1if

transmit

disabled.

Switch

then

Auto
booted

switches
There

are
these

can

2-4

switch

are

ocontrol

the

CPU that goes to
to pass control

and

the

EEPROM

OFF.

ON,

the

mode

forces

message

the

contents

the

ROM

selected

<console

1is

code

disabled

and

all

mode "cannot be
program
will

console

indicating

Switches

2-4

are

equal

selected
by

with

table

the
the

enter
boot

the

to
Auto

suppressed.
Dialog
at the console,
the

not

determine

tests.

device
EEPROM

the

console

octal

and
and

(1-6).

an
to

restart.

determined

default

1is

the
OFF

completion

and

default

ROM

device

unconditionally

the

is pulled
device is

on
be

power

console
1is
input occurs

Dboot

changed

standard

OFF

error

are

taken

Switch

and

1-5

the

output
to
the
entered.
If any

then

when

device.

be
5

1line

switch
should

that

connected to it
1If an external

external

selections, any
external switch

assumes

unit
the

number

value

values in the table for the
PDP-11/84
system.
devices do not meet the needs of the user they
setup mode

boots,

UBA

ROM

any

value.

boots

The

any

selections

EEPROM

can

boots.

The

CONFIGURATION

selections

Refer

are

changed

using

setup

Command

subsection

4.3.4

for more

information

Setup

Command

subsection

4.3.6

for more

information

Setup

Command

Refer
6.

23456

OFF

the

BCR

the

Switch

3210

code.

Don't

number

X XXX

ROM

ACTION

XXX

Force

Dialog

cabinet

Dialog

switch

TAKEN

the

enabled.
control

located

LOW

(0)

when

is ON bit

high

(1)

following,

baud

selections
Command 6.

rate.
Switch

POWER

Console

1is

transfer

bit

KDJ11-B module

For

switch -

drives

KDJ11-B module

bit

running

The

care

tests.

the

Unconditionally
to

dialog

(FORCE

rear of

OFF.

long

after

DIALOG)

the box
When

or
the

the
Force

Switch 5 on

the

OFF.

the

console

Auto

boot

Boot

1110XXX

36X

11100XXX
11010XXX
11000XXX
1 0110XXX
1 0100XXX
1 0010XXX
1
00 00 XXX

34X
32X
30X
26X
24X
22X
20X

enabled

mode

Switch

is
Boot

and

switches

6-8

(SB

from

Setup

Dispatch according to EEPROM
Auto boot 6th selection f rom Setup
Auto boot 5th selection from Setup
Auto boot 4th selection f rom Setup
Auto boot 3rd selection from Se tup
Auto boot 2nd selection from Setup
Auto boot l1st selection f rom Setup

Power up

to ODT

select

automatically selected

immediately.

for
mode

Command

Command
Command
Command

Command
Command

N O OOYON
OO

Interpretation

CONFIGURATION

Dispatch

according

EEPROM

has

Dialog
mode,
Auto
boot
mode
Setup mode Command 4,
Halt
and
location
For

the

not

24/26

(power

following

used.

fail

the

Auto

possible

trying

modes.

They
are
defined by

devices
or

ODT

enter

MODIFICATION

through

vector

recovery).

console

boot

four

disabled

mode

Don't

and

switches

automatically

6-8

selected

are

for

all

-selections.

OFF

=
8

456

ON
Switch

number

ACTION

TAKEN

Setup

110XXX

16X

Auto

boot

according

14X

Auto

boot

6th

selection

from

01
01

12X
10X

Auto boot
Auto boot

5th
4th

selection
selection

from Setup Command
from Setup Command

010XXX
000XXX

POWER

01100XXX

Command
Setup

Command

00110XXX

06X

Auto

boot

3rd

selection

from

Setup

Command

001

04X

Auto

boot

2nd

selection

from

Setup

Command

1st

selection

from

Setup

Command

00XXX

0010XXX

02X

Auto

boot

0000

00X

Run

stand

XXX

power

The

following

the

values

the

setup

mode.

The

user may

they

using

setup

mode

Command

boot

sequence

rate

for

desire

default

MSCP
RLO1,
TS11l,

TU81, TKS5O0
(Not set)
(Not set)

DLO
MSO

MUO

SB
SB

5
6

shows

correctly

loop

specifies

any

the

KDJ11-B module

initialized

wusing

H-1

tests

how

Baud

must
select

select
Rate

up.

when

alone mode

list

EEPROM

Table

KDJ11-B module

bit

OCTAL

care

Automatic

values

for

change
6.

RLO2
TUS8O

the

baud

select

be OFF to allow
the Baud rate.

switch.

the

Baud

the

Console

Switches

rate

6-8

select

SLU
the

switch

OOy OYOY OV OY

CONFIGURATION

TABLE

Baud

H-1

rate

Selected

38400
19200

9600
4800
2400
1200
600
300

Table

the
or

H-2

BCR

bits

—me-——---

0
1

00O

——m———-

@
@
=

m====-=m=me——memme—————————
0mm—e———-

2
3
4
5
6

010
011
1 00
1 01
110

=e——————

=
=

select

the Baud

removed

due

TABLE

H-2

the

baud

rate

rate with

select

KDJ11-B
= OFF

SWITCH SELECTION
0 = ON)

KDJ11-B

BAUD

DATA

READ

MODULE

RATE

FROM

BCR

SWITCH

O
0
0
0O
1
1
1
1

0
0
1
1
0
0
1
1

O
1
O
1
O
1
O
1

210

38400
19200
9600
4800
2400
1200
600
300

0 00O
0 01
010
011
1 00
1 01
110
1

the

switch

failure.

2:0

SELECTION

position

how

RATE

Switch

KDJ11-B module
has

shows

BAUD

switches

not present