Digital PDFs

EK-11001-HR-001

2000

70 pages

Original

15MB

view download

OCR Version

4.1MB

view download

Document:	PDP-11/45 Maintenance Reference Manual
Order Number:	EK-11001-HR
Revision:	001
Pages:	70
Original Filename:

OCR Text

PDP-11/45 maintenance
reference manual

dlilgliltiall

EK-11001-HR-001

./—\\

PDP-11/45 maintenance
reference manual
‘

digital equipment corporation - maynard. massachusetts

1st Edition, November 1972
2nd Printing, October 1973
3rd Printing, March 1975

The material in this manual is for informational purposes and is subject to change without
notice.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONTENTS
Pages

CPINSTRUCTION SET .+« + o v ee e oo e e 1—12
MEMORY MANAGEMENT

. « v

SEMICONDUCTOR MEMORY

o e

e e

e e e

1315

.+« + o v v eeoeeeee e

16-23

CORE MEMORY . .... o 24-25
FLOATING POINT PROCESSOR

OP CODE DETERMINATION

. « « + + v e eoveeee e e

. + .\ oo vee et

MEMORY MAP AND PROGRAM LOADERS

e e

26-48

e e e

. . .. .o oveee

5053

ADDRESS MODES .+« v oo e ... 54-56

CONSOLE | D B o 57
KB11-A BLOCK DIAGRAM
MODULE LOCATIONS

. « + « o oo i

. « « « v v o e e oee e

DEVICE REGISTER ADDRESSES

ASCILCODE

. o v oo oo

e e e

o v oo oo oo e

e e e

111

e e

58-59

e e e

.+« +

e e e

INSTRUCTION CARD LEGEND

OP Fields

~ Byte(1)/Word(0)

Time

Add 150 ns if Destination is an odd

Source Field — 6 Bits

byte, except where dst = R7 or where

Destination Field — 6 Bits

dst

applicable, is 0.

Floating Source — 6 Bits

Floating Destination — 6 Bits
Floating Accumulator — 2 Bits

mode

equals

and src, where

Add 90 ns/memory reference if memory management KT11 is in operation.

Offset — 8 Bits

Offset— 6 Bits

Count — 6 Bits

Count — 3 Bits
AND

Inclusive OR
Exclusive OR

Contents of

Condition Codes

Location
Becomes

Is Popped from Stack
Is Pushed onto Stack

Boolean Not

Conditionally Set
Not affected
Cleared

Set

GENERAL ADDRESSING MODES

| Format

Hkock

Mode@

*Direct/deferred bit for source and destination address

**Specifies how selected registers are to be used
*+*Specifies a general register

Mode

Name

Symbol

Auto-increment

@%R or (R)
-

(R)+

Function

Register contains operand.
Registe.r contains the address of the operand.
Register contains the address of the operand. Register
- contents incremented after reference.

Auto-increment
~

@(R)+

Deferred

by 2, even for byte instructions).

Auto-decrement

-~ —(R)

Auto-decrement
Deferred

@-(R)

instructions), then used as a pointer to a word
containing the address of the operand.

Index

+X(R)

Value X (stored in a word following the instruction)
is added to (R) to produce

the address of the

operand. Neither X nor (R) is modified.

Index Deferred
-

@+X(R)
or
@(R)
.

(X is an Index value )

Value X (stored in a word following the‘instruction)

and (R) are added and the sum is used as a pointer to
a word containing the address of the operand. Neither

X nor (R) is modified.

SPECIAL (PC) ADDRESSING MODES

A&k

Format

*®

Mode @

Hockk

*Direct/deferred bit for source and destination address
**Specifies how selected register is to be used

***Specifies register 7 (PC)

Mode

Name

Imme diate

Absolute

Symbol

Function

Operand follows instruction.

@#A

A follows instruction is the address of the operand.
(A = absolute address.)

Relative

A is the address of the operand. (A = Index value

'
7

following the instruction plus updated PC.)
Relative Deferred

- A is the address of a word containing the address of
the

operand.

Index

value

following

instruction plus updated PC.)

BRANCH ADDRESSING

OFFSET

EFFECTIVE ADDRESS

_ (effective address) — (updated PC)
5

= (offset
x two) + (updated PC)

Branching from location 500

OFFSET

470

373 .

474

- 375

479

476

500
502

504

Instruction
-

374

376

377
000

001

506

002

510

003

o
|

OFFSET — Number of words to branch
- from updated PC.

EFFECTIVE ADDRESS — The location

to branch too.
e

;

UPDATED PC — Location of instruction
plus two.

the

CONDITION CODES OPERATORS:
15

Format

OIO

OIO ‘O

O|O

1.0l1|

OPR
2

INIZIVlCJOOOZXX

Condition code operator set or clear condition code

bits. Indicated bits of the instruction word (3-0) if =
to a ONE, affect the indicated condition code bits
NZVC according to bit 4.

Bit 4 = 0 Clear condition code bits
Bit 4 = 1 Set condition code bits

Condition

Mnemonic

Instruction/Operation

OP Code

Code

Time

NZVC

—

- No Operation

CLC

CLear C
|

C<«0

CLV

600 ns

---0

600 ns

000242

--0-

600 ns

-0 --

600 ns

0---

600 ns

000257

0000

600 ns

CLear V
-

000240
000241

V<0

CLZ

CLear Z

000244
Z<0

CLN

CLear N

000250

N <0

CcCC

Clear all CC’s
N,Z,V,C<«0

—_—

No Operation

000260

600 ns

SEC

SEt C

000261

---1

600 ns

SEV

SEt V

000262

-1-

600 ns

-1--

600 ns

000270

l1---

600 ns

000277

1111

600 ns

C<«1

V<1

SEZ

SEt Z

000264

7 <1

SEN

SEt N
N« 1

SCC

Set all CC’s
N,Z,V,C<«1

Combinations of the above Clear instructions can be

~
—

ORed together to form combined Clear instructions.
Clear Vand C

000243

--00

600 ns

V,C<0

Combinations of the above Set instructions can be ORed
|

—

together to form combined Set instructions.

Set Nand V
N,V<«1

‘

000272

I1-1-

600 ns

CONDITIONAL BRANCHES: OPR loc
15

Format

(

0P CODE

OFFSET

The instruction causes a branch to a location defined

by the sum of the offset (multiplied by 2) and the
current contents of the program counter, if
conditions are met.

TIME: Branch 600 ns/No Branch 300 ns

~ Mnemonic

Instruction/Operation
BRanch (unconditionally)

OP Code
0004+XXX

PC < loc

BNE

(

Branch if Not Equal (zero)

PC <« loc if Z=0

0010+XXX

BEQ

Branch if EQual (zero)

0014+XXX

BGE

Branch if Greater or Equal (zero)

0020+XXX

PC < loc if Z=1

PC <loc if N=V

BLT

Branch if Less Than (zero)

0024+XXX

PC <« loc if N#V

BGT

Branch if Greater Than (zero)

0030+XXX

PC <« loc if Z=0 and N=V

(

BLE

Branch if Less than or Equal (zero)

0034+XXX

BPL

Branch if PLus
|
PC < loc if N=0

1000+XXX
-

BMI

Branch if MInus

1004+XXX

PC < loc if Z=1 or N#V

PC < loc if N=1

BHI

Branch if Hlgher
PC «loc if C=0 and Z=0

BLOS

Branch if LOwer or Same

1010+XXX
|

1014+XXX

- PC «<loc if C=1 or Z=1

(

)

BVC

Branch if oVerflow Clear

1020+ XXX

- BVS

Branch if oVerflow Set

1024+XXX

Branch if Carry Clear

1030+XXX

BCC

PC < loc if V=0
PC < loc if V=1
PC < loc if C=0

BHIS
|

Branch if Hlgher or Same

1030+XXX

PC «loc if C=0

BCS

Branch if Carry Set

BLO

Branch if LOwer

1034+ XXX

PC < loc if C=1
PC «1loc if C=1

1034+XXX

SINGLE OPERAND INSTRUCTIONS: OPR dst
.

Format

OP CODE

DESTINATION

Mnemonic
|

Condition

Instruction/Operation

OP Code

CLR(B)

‘

(dst) < ~(dst)

INC(B)

INCrement (Byte)
(dst) < (dst)
+1
|
DECrement (Byte)
(dst) < (dst) -1
NEGate (Byte)
(dst) < ~(dst) +1
ADd Carry (Byte)
|
(dst) < (dst) + (¢)
SuBtract Carry (Byte)
(dst) < (dst) - (¢)
- TeST (Byte)
(dst) <~ (dst)
ROtate Right (Byte)
(dst) < (dst) 1 place
right with (c)

NEG(B)

ADC(B)
SBC(B)
TST(B)

ROR(B)

n050DD
n051DD

0100

]

n055DD

Fhkk

300 ns

n056DD

300 ns

n057DD

FdkE
|
**00

n060DD

|
ASR(B)

| l

I l l—’l
|

Glolol

300 ns

1 ]

n062DD

I
300 ns

| 1

| ! |

| |

' n063DD

(dst) < (dst) shifted
1 place left

|
ok
0

Sign eXTend

300 ns
:

TR
-

SWAB

Arithmetic Shift Left (Byte)

] ]

SXT

(dst) < (dst) shifted
1 place right

Arithmetic Shift Right (Byte)

300 ns
|

300 ns

left with (¢)

300 ns
300 ns

n061DD

(dst) < (dst) 1 place

ok ok

‘I 1|

ROtate Left (Byte)

ASL(B)

] l

300 ns

n054DD

ROL(B)

Hkk
|
ko E

n053DD
o

300 ns
|

**01

n052DD

DEC(B)

Time

NZVC

CLeaR (Byte)
(dst) <0
COMplement (Byte)

COM(B)

Code

0067DD

().

300 ns

0003DD

**00

300 ns

(dst) < 0if N=0
(dst) < -1 if N=1

SWAp Bytes

(dst byte 0) « (dst byte 1)
(dst byte 1) < (dst byte 0)

DOUBLE OPERAND INSTRUCTIONS: OPR src, dst
15

Format

OP CODE

SOURCE

Mnemonic

DESTINATION

Instruction/Operation

Condition

Code

Time

n1SSDD

*%0 -

300 ns

CoMPare (Byte)

n2SSDD

hokk ok

300 ns

BIT(B)

BIt Test (Byte)
(dst) A (src)

n3SSDD
|
|

*%0 o

300 ns
L

BIC(B)

BIt Clear (Byte)

n4SSDD

**0 -

300 ns

BIS(B)

Blt Set (Byte)

n5SSDD

**0 -

300 ns

ADD

06SSDD

SUB

SUBtract

16SSDD

MOV(B)

OP Code

MOVe (Byte)
(dst) <« (src)

CMP(B)
"~

]

(stc)+~(dst)+1
‘(src) , (dst) unaffected

(dst) , (src) unaffected

(dst) <~ (src) A (dst)

(dst) < (src) A (dst)

NZVC

(dst) < (src) + (dst)

(dst) < (dst) + ~ (src) + 1

300 ns

Format

OP CODE

MUL

MULtiply

DIV

DIVide

ASHC

REG

Condition
Code

SR
Time

070RSS

*EQ*

3.3 us

071RSS

ok K

6.9-

072RSS

kokk ok

750 ns+

073RSS

ke ke

750 nst

<«

(R)x (src)

quotent R

(R), (RV1)

Arithmetic SHift
|

<«

(src)

(R)Arith

shifted N places
right or left

Arithmetic SHift Combined
R,RVlI

<«

]

|
OP Code

R,RV1

remainder RV1

SRC/DST

|
Instruction/Operation

o
Mnemonic

ASH

7.5 us

(R),(RV1)
Arith shifted
(two words) N
places right or left

Rdllq..ll.ll.l,H..l..1.111111
——>

R+1

R+1[

’

—

‘

R11'||’||1111||1|Illlllnllllxllllj‘—c
XOR

Exclusive OR

(dst)
<« RV (dst)
Note: Syntax format is XOR R, dst

074RDD

**0 -

300 ns

SUBROUTINE INSTRUCTIONS

Mnemonic

Instruction/Operation

Condition

OP Code

Code

JSR

Jump to SubRoutine
tmp

(dst)

Y(SP)
reg

<
<

(reg)
(PC)

<«

‘RTS

004RDD

OP CODE

[

REG

DESTINATION

OP CODE

‘

REG

PC
R5

<«
<«

1.2 us

1 OPR R

0064NN

<«

----

900 ns

C) + (2xN)
(RS
(SP)t

Note: NN=number of parameters

OP CODE

Format

‘

MARK

1 OPR R, DST

00020R

Format

MARK

1.5 us

ReTurn from Subroutine
|
PC
<« (reg)
reg
< (SP)?
'

(tmp)

Format

Time -

NZVC

’

j OPR NN

PROGRAM CONTROL INSTRUCTIONS
Mnemonic

Instruction/Operation

Condition

OP Code

Code

SPL

Set Priority Level

PSW(7-5)

<«

JMP

)

SOB

<«

600 ns

R
PC
PC

<«
<«
<«

,
DESTINATION

077RYY

‘

REG

] OPR DST

OFFSET

600 ns
'

(R)-1
'
|
(PC)-(2xOFFSET) if result # 0
(PC)ifresult=0
Note: Branch back only if R#0
9

OP CODE

]OPR.N

0001DD

Subtract One and Branch

----

OP CODE

Format

|
PC

[

OP CODE

JuMP

‘
Format

Note: Kernal mode only

00023N

Format

Time

NZVC

OPR R,A
11-1477

750 ns.

OPERATE INSTRUCTIONS: OPR

Condition

Instruction/Operation

Mnemonic

OP Code

Code

Time

NZVC

HLT

Hal.
T

WAIT

<«

Halt

- WAIT

000001

wait for interrupt
RTI

ReTurn from Interrupt

BPT

<«

(SP)t

PSW

<«

(SP)t

V(SP)
+(SP)
PC
PSW

BreakPoint Trap

PC
PSW
RESET

ORI
)

J(SP)
1(SP)

000002

Fkkk

15us

000003

Hekokk

2.25 us

000004

dkockk

2.25 us

(PSW)

(PC)

(loc 14)
(loc 16)

I/O Trap

I0T

(PSW)

(PC)

(loc 20)
(loc 22)

RESET

000005

10 ms

BUS INIT < TRUE for 10 ms-

RTT

ReTurn from Trap

EMT

<«

(SP)?

PSW

<«

(SP)t

1(SP)

{(SP)
PC

PSW

(PSW)

Hkookk

1.5 us

104000 -

ook ckok

2.25 us

104377

(PC)

(loc 32)

(SP)
W(SP)

(loc 34)

~ (loc 36)

PSW

000006

(loc 30)

TRAP

Notes:

EMulator Trap

Lo)

750 ns

000000

(PSW)

104400 -

Hokkok

104777

(PC)

1. HALT issued in SUPERVISOR or USER mode will generate a trap to vector 4.

2. SPL or RESET issued in SUPERVISOR or USER mode will be a NO OP.
3. BPT, IOT, EMT and TRAP push old PC and old PSW onto stack of mode you
are going to.

2.25us

PROCESSOR REGISTER ADDRESSES
GENERAL REGISTERS

R10

(000010)

R11

(000011)

R12

(000012)

| r13

(000013)

(000004)

R14

(000014)

~(000005)

RIS

(000015)

(000000)

(000001)

(000002)

(000003)

RS
R6

KERNEL SP

(000006)

R16

SUPER SP

(000016)

~(000007)

R17

USER SP

(000017)

(addressable only by console)
DISPLAY REGISTER
15

J (777570)

‘

11-1478"

SWITCH

11- 1479

PROGRAM BREAK REGISTER

(PB)

’

|(777770)'.

‘

PROGRAM INTERRUPT

7
_

REQUEST REGISTER

11—1480‘

NN
6

Y-

s
)

PIA

PIR

PROGRAM INTERRUPT ACTIVE
'
STACK
LIMIT REGISTER
15

(PIRQ)

'11—1481

(SL)
.

(777774)
11- 1482

PROCESSOR STATUS WORD

(PSW)

|
NOT USED

(777776)
-

L—CARRYOUT

OVERFLOW

ZERO

NEGATIVE
L— TRACE

| PROCESSOR PRIORITY 0-7

L_ GPR (0O SELECTS REG 0-5)
(1

SELECTS REG 10-15)

”
PREVIOUS MODE

CURRENT MODE

00=KERNEL

01 = SUPERVISOR

11 = USER
10=ILLEGAL
11-1483

'MEMORY PARITY CONTROL REGISTER

I— PARITY DISABLE
:

HALT

LOW 4K
|

ENABLE

} TYPE OF PARITY

— HIGH 4K

— PARITY ERROR
11-

1484

Addressing
00—

8K — 16K

772100

16K — 24K

772102

772104

24K — 32K

772106

32K — 40K

772110

40K —48K

772112

48K — 56K

56K — 64K

772114

64K — 72K

72K — 80K

772116

772120

772122

80K — 88K

772124

88K
— 96K

VRN

96K — 104K

772126

772130

104K
— 112K

772132

112K
— 120K

772134

120K — 128K

772136

Bits 11 and 10 are éssociated with the high-order 4K and low-order 4K of this memory address bank. When
set to a 1, they specify odd parity for their respective half banks; when clear, even parity.
When bit 9 is set, the machine will execute a halt if a parity error occurs; when clear, the machme W111
perform an etfective timeout and interrupt through location 4.

When bit 8 is clear, a parlty eITor W111 cause an interrupt (or halt as specifiedin bit 9) 1f it 1s set, no actlon

will be taken on a parity error.

When the machine is powered up, the status reglsters have bit 15 cleared to 0, and the remammg blts set to

1: halt, odd parity enable parity disable, and no error.

INTER-MODE COMMUNICATIONS: OPR dst or OPR src
6

[

Format

DST /SRC

OP CODE

11-1485

Condition

Mnemonic
|

Instruction/Operation

MFPI

Move From Previous
Instruction space

(temp)
MFPD

Code
NZVC

Time

0065SS

*#() -

1.2 us

(src)

(temp)

<«

WSP)

OP Code
,

Move From Previous

1065SS

*EQ -

1.2 us

0066DD
.

*EQ -

900 ns

*EQ -

900 ns
|

Data space

(temp)
MTPI

MTPD

<«

J(SP)

<«

(temp)

<«

Move To Previous
Instruction space

(src)

(temp)

(SP)?

(dst)
<«
Move To Previous
Data space
(temp)
<«
(dst)
<«

(temp)

|
1066DD

(SP)?
(temp)

KT11-C MEMORY MANAGEMENT STATUS REGISTER

Status Register0 (SRO)

B 83?55%2 SET
5

11
'

. ABORT :NON-RESIDENT —J

]

[}

10 9
%

ADDRESS::

777572

L ENABLE KT11-C

PAGE NUMBER

ABORT :PAGE LENGTH ERR

ABORT: READ

ADDRESS

ONLY VIOLATION

INSTRUCTION

TRAP :OPERATING
SYSTEM TESTER

MAINTENANCE

ENABLE MEMORY
MANAGEMENT TRAPS

Status Register 1 (SR1)

SPACE 1/D

'MODE OF OPERATION

TRAP:MEMORY MANAGEMENT

COMPLETE
MODE
11-1038

Status Register 2 (SR2)

Statfis Register 3 (SR3)

'SPARE——f—I

11-1039

e
l

KERNEL MODE

"1" ENABLES
D SPACE

SUPER

MODE

USER MODE
11-1041

" ACTIVE PAGE REGISTERS
15

Processor Status Word
I space

KERNEL (00)

e I o S

& T

0 R

N T

APRO

SUPERVISOR (01)

USER (11)

772340

772300

772240

772200

777640

777600

772342

772302

772242

772202

777642

777602

772344

772304

772244

772204

777644

777604

772346

772306

772246

772206

777646

777606

772350

772310

772250

772210

777650

777610

772352

772312

772252

772212

777652

777612

772354

772314

772254

772214

777654

777614

772356

772316

772256

772216

777656

777616

PAR

PDR -

PAR

PDR

PAR

PDR

)

- D space

772260

772220

777660

777620

772362

772322

772262

772222

777662

777622

772364

772324

772264

772224

777664

777624

772366

772326

772266

772226

777666

777626

772370

772330

772270

772230

777670

777630

772372

772332

772272

772232

777672

777632

772374

772334

772274

772234

777674

777634

772376

772336

772276

772236

777676

777636

PAR

PDR

PAR

PDR

PAR

PDR

772320

PAGE ADDRESS REGISTER
15

USER (11)

772360

.
,r’/ )

SUPERVISOR (01)

APRO

KERNEL (00)

PAGE LENGTH FIELD

‘

(PLF)

PAGE DESCRIPTER REGISTER
2

ACF

PAGE ADDRESS FIELD

(PAF)

11-1037

VIRTUAL
ADDRESS

FROM CPU

O NOT ENB

SRO<O>

PSW

KERNEL

<14:15>

SR3<0>

KERNEL
D APR

USER

SR3K 1>

KERNEL
I

APR

(

suPer

2yABORT

APR

SUPER

USER

APR

»
PER?MIT

I APR

CQMPLET,ON>

TRAP UPON

ACF

(

INT

BN>PLF

INT

)

lPA=PAR-1008+DF]

PHYSICAL
ADDRESS

TO UNIBUS
11-1487

Memory Management

gQee—— g¢——— gle——— je——g

Nl N

nN\I)/v
10¥1NOD

135 Y} —

VSOW

j¥V(YA—SVOW

4L .

OFI8W TOYLINOD
034y

VSOW e¥ —

g< — - —

TOlHIL8NSOND
|

7OLHLN8OWD

MOS Memory System Configuration
Memory

Capacity
-

MS11-BC

Option

p‘Z:-itg,

Option Type Number

| MS11-BD

‘Y;;f.‘,‘;;‘ t

wMsuuBM

wMmsi1-BP

Module Complement

(1)M8110

(1)G401

(1)M8110

| (DH746A

(1)H744A

(1) G401YA

12K -

12K

16K

]

1
8K

3
3

20K
p /—\\\

20K

24K

]

- 28K
|

1
1

B
1

32K

24K
28K

32K

4
4

5
5

MOS Matrix Selected Address Configuration (4 of 16K)

MAD

REQUIRED JUMPERS

MOS Matrix Memory

(MAD 14)

(MAD 13)

Address Assignment

0—4095

4096—8191

8192—12,287

12,288—16,383

MOS Matrix Control Level Generation and Selected Memory
Address Block (1 of 4K)

MAD
02

0
1

CONTROL LEVELS GENERATED
-

(MAD 02)

MOSA B

MOSA A

0—1023

MOSA D

MOSA A

20483071

MOSA B

MOSA D

(MAD 01)

Memory Address

’

MOSA C

Block Selected

1024-2047

- 3072—-4095

M8110 CONTROL

WRITE DATA (SMCD MEM DATA <17:00> H)

SMCC MAD <14: O1>

<:—

M8110 CONTROL

MAD <12,10:01>

DATA INVERSION
- MEM DATA <17:00> L

BN
EN

BEENEEEN

BIPB

10 09

7 06 05 04 03

02 01

HH_HLHHHHHL
1st 256

BIPC

je—

ADS

SEL

e—

CS1

e— CS2

2nd 256 L|0CATIONS
BIPF

le— CS1 RO

BIPE

j@«—

ADS

SEL

la—

CS1

¢—

CS2

EXPANDER

| ROW SELECTION

1-8A

—»{ADS SEL 1-8

RHY

le«— CS3 B

ADDRESS

e— CS3 A

l—‘ CS2

e— CS2 RO

LIOCATlONS

BIPD

CSt

BIPA

'
1-8B

ABCD

;

ATION

BiPJ !
X

+—

4th 256 LOCATION
|OC
S
BIPL

{0 09

CS2

WRITE PULSE
LOW/HIGH

e— CS3 D

BIPK

TTTTTTT] TTITTTTT]

17.16

MAD <14,13,11>

BIPH je— ADS SEL 1-8C

08 07 0605 04 03 02 Ot

ADS

SRSt
YR ARy

SEL

I—CENABLE

1-8D

BRD ENBL

L-CS3-

MODULE

SELECTION

BIPB

READ DATA (SMCE MEM SA <17:00> H)

WR EN
LO/ HI

M8110
CONTROL

11-1325

Bipolar Memory Matrix

Bipolar Memory System Configuration

Memory

Option Type Number

Capacity

MS11-CC

Option

With

Without

(1)M8110

Parity

(2)H744A

MS11-CM

Module Complement

(1)M8111

MS11CP
(1)M8111YA

|
3K

2
2

|
3

1
4K

2
6K

2
8K

Bipolar Matrix Selected Address Configuration (1 of 16K)
MAD
14 | 13

| (MAD14)

Required Jumpers

(MAD13)

(MAD11)

Memory Address
|

(MAD 10)

Assignment

0to 1023

1024 to 2047

12048 to 3071

3072 to 4095

4096 to 5119

5120
to 6143

6144 to 7167
7168 to 8191

]

8192 to 9215

0 |

9216
to 10,239

10,240 to 11,263

11,264 to 12,287

12,288 to 13,311

13,312
to 14,335

15,360 to 16,383

14,336 to 15,359

XIHLYW

AHOW3IN

73V1O8V1NYS3D
b

H3LSI93H QAT 2 quw xnw an 40Ws
d3IX3ITILINAN

‘
[»

|
y,

ANV

]

780>4:d<G81.

sSNAaINv

vS3NiA8vNIaTN

|Hsn108OasWiNSn18

7¥10GN38FOWL

snalsvd VIVa WOYd4

A -

H><O0:G)I

H %O TOMLNOD vo8n.

AaJ_nAvogS3SNINT1AS$&S3InE3HN8A4IY0VNav<

e 7 N3OV 4y3d 8080 [NdD

AAONsS

|g3Nin8SN8|9sInNsAS7W01 |SH3IAIOAYV JHOOWWSSWH3<W0V'S20H:<b0t>:Ga1v>an

Al Yvd

3OWS|108INOo8OWSd4Y3d7j———— mmiolo

H (1) HOLYT VS VOWS ——»f ALI¥YVd

(D7V3O1WY)Sd

has

ndo

MOS

B IPOLAR

SAPJ PA{2 H

SMCF FB

SAPJ PA{14 H —E
A
3

SMCF

SAPJ PA{1

MUX DEC 14 H

DECODE 14 H
SAPJ

MUX 13711 H

SAPJ PA13 H —E
7

DECODE

13 H

MUX DEC 13
H

v»

E67

/-\

15|

| 3 /"—\ 14

13|

SMCF

DECODE

SMCF

MUX DEC 14 H
SMCF FB
13/11

|7 /"\ 10

{3 H

MUX

SMCF

MUX 14/12
H

PA{{ H.

SAPJ PA13 H

sMcF FB

8/‘\

SMCF

SMCF FB

“l

6/"'\

SAPJ PA14

SMCF FB

4L U3

DECODE 14 H

SAPJ PA12 H

MUX 14/12 H

2/"\15

SMCF

MUX DEC 13
H

E67
11-1327

Fastbus Address Multiplexing {14:11), Required E67 Jumpers

SMCH UBAD O1 H
SMCH

UBAD

{5 H

SAPJ PA15
H
S

DAPB

BAMX

Of H

SMCF UB MUX MAD 12 H

]

SMCF UB

MUX

SMCF FB

MUX MAD 12 H

SMCF FB

MUX

MAD 15 H

MAD 15

E86

11-1328

MAD Multiplexing, Required E86 Jumpers

DECODE

SMCF
14 H

/\:]

4 /\‘_E"J

MUX

SMCH UBAD 11

SMCH UBAD {3

H ——E

- /‘\_‘_‘J

|7
SMCF
DECODE 13 H

sMCF 14712
uB

MUX

/—\_9J

SMCH UBAD 12 H

SMCH UBAD 14 H

SMCF UB

DEC 14 H

SMCF UB

MUX 13/ 11

SMCF
DECODE 14 H

SMCH

UBAD #{ H

SMCH

UBAD 13
H

SMCF UB

MUX DEC
13 H

—

—1!6___
o[

Y 14
3

/—\

SMCF UB

MUX

E78

DEC

14 H

SMCF UB

MUX

LT
N 10
SMCF
DECODE 13 H

smcF us

MUx 14712 H

\q a l_i

SMCH UBAD 14 H _E

BIPOLAR

el |

SMCH UBAD 12 H

)]

MOS

13/11

SMCF UB

MUX

DEC 13 H

11-1329

Unibus Address Multiplexing (14:11), Required E78 Jumpers

Fastbus/Unibus Memory Address (Assign and Decode)
Fastbus/Unibus

Address Decoder Bits

14 |

M8110 Jumpers (E87)

(NOTE 1, NOTE 2)

0—4K

48K

0
0

1
1

0
1

16—20K

20-24K

]

MOS

0—16K
|

X
X
16—32K

X
X

24-28K
28-32k

32-36K

8-12K
12—-16K

Assignment

Bipolar

Memory Address

32-48K

36-40K

40—44K

44—48K

48—52K

48—-64K

52-56K

56—60K

X |

60—64K

64—68K

68—72K

1
1

0
0

0
1

1
o

1
0

76—80K
80—84K

1
1

X
X

84—88K

88—-92K

92—96K

96—100K

100— 104K

104—108K

108—112K

112—116K |

116—120K |

120—124K

124—128K

NOTES:

64—80K

72-76K

|
80—96K

96—112K

112—128K

X
X

“X” denotesjumper to be cut.

Jumpers F and H are left intact for all MOS memory assignments.

X
X

MUX 14712, 13/11

+5V

MUX

<15:13> H

SAPJ

PALI7T:16>
H

MUX <15:13> H

SAPJ PAKIT:16>H

EB9/76

E77

E89/76

SMCF

DECODE <17:13>
{TO UNIBUS

DECODE CKT,

E67,E78)

Y J-M

L/
v
SMCF MEM H
11-1326

Simplified Memory Address Decode (SMCF)

MOS/Bipolar Module Addressing
Memory Address

)

Memory Address Bits

Remove Jumpers

Assignment

Fastbus/Unibus

FB MUX

14/12

FB MUX

13/11

MOS

Fastbus

Bipolar

Unibus

Address

Select

0—-4095

0-1023

4096—8191

1024 -2047

]

8192-12287

2048—-3071

]

1228816383

3072—-4095

Kon,

0
0

MOS/Bipolar Memory Addressing
| No. of Memory

Memory

Modules in

Capacity

- Memory*

MOS

Remove Jumpers

Bipolar

Fastbus

Unibus

~ Address

Address

Select

" Select

12K

JKL

NPR

16K

JKLM

NPRS

*Connected to one M8110 Control.

Ssn8gN1IANSI._om_lwrzoSTURNNRLTG-1353y13SSNl3eS—t1d|MOV1vLdS*—n]13534700

a1353971°0dVNLH]CHamL
_ avo | H

ou (s

sng 8d4<8:G[>a LNX |

< 11
Vd

8d.

ODZ2—MODOW;m

Ghigl MG 0

| . vlv1a-W1INN01H‘Spayrdunsyorqweigerq HNILI'OH .

Rsn8d2—001 nNOOIN1IDW3I7A1LN3SaaavivvrEvoomdl1l|11O'N0OHH sya3.H via1d|iy071TdEnwHyleG-l—igHl{|sA-B3MX3y|8a9SHS0XHIvA4IH81A1¥IE8I3L(1NI9SG1M1)S93Y(4w3Hl)9O00Y1S- G,l.

s
n
g
<
t
v
1
>
<
l
0
:
e
l
>
V
v
Sng <0 ><8l:.1>V

gti-81I

v¥i34vndag|

sVd<n0:/.g>ad

Device Address Jumpers (1)
Memory Bank

Machine Address

—

(words)

(1)

Al4(% A0l

AlS

Alé6

A17L

0—8K

000000-037776

8—16K

040000-077776

Out

16—24K

100000-137776

Out

24-32K

140000—-177776

Out

32-40K

200000-237776

Out

40—48K

48-56K

240000277776

300000-337776

Out

56—64K

340000-377776

Out

64—72K

400000—437776

Out

72-80K

440000—-477776

Out

80—88K

500000-537776

Out

88—96K

540000-577776

Out

96-104K

600000-637776

Out

104-112K

640000677776

Out

112—-120K

700000-737776

Out

120-128K

740000-767776

Out

WS and W10 must be installed and W9 must be removed.

-(2)

The memory can be interleaved as 16K only, using two adjacent contiguously addressed 8K

banks. When two 8K banks are interleaved, jumpers W7 and W8 must be in the configuration
shown by the dotted lines. Bit AO1 goes to the device selector gate controlled by jumper W6.
One 8K bank must have W6 installed and the other must have W6 removed.

When not interleaved, jumpers W7 and W8 must be in the configuration shown by the solid
lines. Bit A14 goes to the device selector gate controlled by jumper W6.

SNy
C)¥-—;;///k)

g o
Cj/f/——\\\?)
.

INTERLEAVED

NON-INTERLEAVED

(TWO 8K BANKS REQUIRED)

’

CONTROL MODULE G110

SHOWING PHYSICAL

COMPONENT

SIDE

LOCATION OF
JUMPERS

W5 o w3 Do
o
-

o wio Do

o wa o

o w2 o

o
we
Mo

o ws Yo

—

I
C

.AFV
v

CONNECTOR EDGE

*Jumper W1 is for test purposes only. It must be installed for normal operation.

**Jumper W11 should be removed for normal operation. When installed the memory
responds to DATI only,regardless of state of control lines COO and CO1.

NOTE:

Jumpers W5 ,W7,and W8 must remain in the -factory installed positions.

Device Decoding Guide

I-1149

dd b

|
2 QUOM

| QYOM

INIOdAHVNIS | | NOIS
,.

o o olo o olo o olo o olo o ololo olo o olo o ‘}o o o olo o olo

AHOW3N

k,‘

INTEGER=5

SHORT INTEGER (I)

LONG INTEGER (L)

fe———— W
—-.q |
15 14
ORD !
~

LT
[o o 1=

wono1“>|

h__

WORD 2——-1

CLTEET (e

er]

INTEGER=-5

SHORT INTEGER (I)

LONG INTEGER (L)

"5'
U WORD'-—-’!

Ll?lllfl

H—‘womfl“q

———

WORD 2 ————»

T
11- 0801

Integer Formats

le—

WORD

31 30

SINGLE -PRECISION

'FLOATING POINT (F)

» |l
|e

E.va |

WORD 2

FRACTION

o
|

POINT (D)

[

WORD

- WORD 1

DOUBLE-PRECISION
FLOATING

WORD

»+2+1t+ "0
54

16.

EXP

FRACTION

|
11-0802

S = Sign

EXP = Expone’nt in excess 200g notation
Fraction = 23 or 55 bit fraction in sign and magnitude format.
Binary point between bits 22 and 23 for F format or between bits

54 and 55 for D format.

Floating-Point Data Formats

INTERRUPT
15

MODE BITS

ENABLES

HER

FER_J

CONDITION CODES

nYa

[TITTITIIITT]
9

FID

NOT USED

NOT USED
FlUV
~

FIU

FIV

FIC
FD
I

FT
FMM
FN
Fz
FvVv
FC
11- 0806

Status Reg.ister Format
F ER — This bit indicates an error condition of the FP11.

result

FID (Floating Interrupt Disable) — All 1nterrupts by the

operation

the

same; however,

FD (Double-Precision Mode Bit) — This bit, when set,

FP11 are disabled when this bitis on.

specifies double-precision format and, when reset, speci-

FIUV (Floating Interrupt on Undefined Variable) — When

fies single-precision format.

this bit is set and a minus O is obtained from memory, an

interrupt occurs. If the bit is not set, minus O can be

treated as if it were a positive O.

(Long-Precision

Integer

Mode

Bit)

—

This

bit is

employed during conversion between integer and float-

loaded and stored; however, any arithmetic operation is

ing-point format. If set, double-precision, 2’s comple-

ment integer format of 32 bits is specified; if reset,

single-precision 2’s complement integer of 16 bits is

FIU (Floating Interrupt on Underflow) — When this bit is

specified.

set, an underflow condition causes a floating underflow

interrupt. The result of the operation causing the

FT (Truncate Bit) — This bit, when set, causes the result of
any floating-point operation to be truncated rather than

interrupt is correct except for the exponent, which is off
by 4005. If the FIU bit is not set and underflow occurs,

the result is set to zero.

of the

interrupt occurs.

rounded.

FMM (Maintenance Mode Bit) — This bit is used to enable
special maintenance logic.

FIV (Floating Interrupt on Overflow) — When this bit is

set, floating overflow causes an interrupt. The result of

FC, FV, FZ, and FN — These bits are the four floatingpoint condition codes, which can be loadedin the CPU’s

the operation causing the interrupt is correct except for
the exponent, which is off by 4005. If the FIV bit is not

C, V, Z, and N condition codes, respectively. This is

set, the result of the operation is the same; the only

accomplished by the Copy Floating Condition Codes

difference is that the interrupt does not occur.

(CFCC) instruction. To determine how each instruction

affects the condition codes, refer to the instruction

HC (Floating Interrupt on Integer Conversion Error) —

descriptionin the PDP-11 Handbook.

When this bit is set, and the Store Convert Floating to
Integer instruction causes FC to be set (indicating a

For

the

Store

Convert

Floating to Integer 1nstruct10n

(which converts a floating-point number to an integer), the

conversion error), an interrupt occurs. When a conversion error occurs, the destination register is cleared and

FC bit is set if the resulting integer is too large to be stored

the source register is untouched. When FIC is reset, the

in the specified register.

PROCESSING OF FLOATING-POINT EXCEPTIONS

A total of seven possible interrupts can occur. These seven possible interrupt exceptions are encoded in the
FP11 Exception Code Register (FEC). The interrupt exception codes represent an offset into a dispatch

table, which routes the program to the right error handling routine. The dispatch table is a function of the

software. The offset for each exception code is shown below followed by a brief description.
FP11 Exception Code

(Base 8)

Definition

Floating Op Code Error — The FP11 causes an

interrupt for an erroneous op code if the FID
bit is not set.

Fleating Divide by Zero — Division by zero
causes an interrupt if the FID bit is not set.

Floating Integer Conversion Error

/,—-\\

Floating Overflow

Floating Underflow

Floating Undefined Variable

Microbreak Trap

NOTE

The traps for exception codes 6, 10, 12, and 14 can be
enabled in the FPU’s Program Status Register.

In addition to the FEC register, the FP11 contains a 16-bit Floating Exception Addre'ss‘ register (FEA),
which stores the address of the last floating-point instruction that caused a floating-point exception.

DATA

DATA
ouT

EXPONENT

FRACTION

(16 BITS) {}

{}
SCRATCH

(32 BITS)

PAD

ACCUMULATORS

ACC O-5-GENERAL PURPOSE

EXPONENT

REGISTERS ACCES-

CALCULATION

SIBLE TO PRO
ACC
:

(16 BITS)

FRACTION

GRAMMER

LOGIC

CALCULATION

6-INTERNAL TEMPO-

LOGIC

RARY STORAGE
-

|
ACC

NOT ACCESSIBLE

(60 BITS)

TO PROGRAMMER

7-INTERNAL STORAGE

OF STATUS NOT
ACCESSIBLE TO
PROGRAMMER
EXCEPT VIA STORE

STATUS INSTRUC "TION

fi
DATA [N
(16 BITS)

f\LDATA OR EXPONENT

FRACTION

(16 BITS)
o
’

(32 BITS)

gy
11-0809

FP11 Simplified Block Diagram

FP11 INSTRUCTION FORMATS

F2 [

oC =17

0oC =17

0C=17

~ F3 r
15

F4 I

0C =17

F5 | - 0C =17
|

- FOC

FOC

| -

F1 r

FSRC/FDST

l AC I

FOC

SRC/DST

|I |

SRC/DST

FOC

]

|
|

FDST

A11—osoo‘

The 2-bit AC field (bits 6 and 7) allows selection of scratch pad accumulators 0 through 3 only If address
mode 0 is specified with formats F1 or F2, bits 2 through O are used to select the floating-point
accumulator. Only accumulators 5 through O can be accessed in this manner. If accumulators 6 or 7 are
specified, the FP11 traps if the interrupt is enabled.

The fields of the various instruction formats:

- Description

- Mnemonic

Operation Code — All floating-point instructions are

FOC

Floating Operation Code — The number of bits in this field
varies with the format and is used to spec:1fy the actual

designated by a 4-bit op code of 17g.

floating-point operation.

"SRC

Source — A 6-bit source field 1dent1cal to thatin a PDP 11

|
|

DST
.

FSRC

instruction.

Destination — A 6-bit dest1nat1on field identical to thatin a

PDP-11 instruction.’

Floating Source — A 6-bit field used only in format F1. It is

identical to SRC, except in mode O when it references a

floating-point accumulator rather than a CPU general
register.

FDST

Floating Destination — A 6-bit field used in formats F1 and
F2. It is identical to DST, except in mode O when it
references a floating-point accumulator instead of a CPU
|

general register.

Accumulator — A 2-bit field used only in formats F3 and
F1 to specify accumulators O through 3.

Instruction Format

Instruction

Mnemonic

ADDF FSRC, AC

ADD

- ADDD FSRC, AC
LOAD

LDF FSRC, AC

LDD ESRC, AC
SUBTRACT

SUBF FSRC, AC

COMPARE

CMPF AC, FDST

SUBD FSRC, AC
CMPD AC, FDST

MULTIPLY

MULF FSRC, AC
MULD FSRC, AC

MODULO

MODF FSRC, AC

MODD FSRC, AC
STORE

STF AC, FDST

DIVIDE

DIVF FSRC, AC

STD AC, FDST
DIVD FSRC, AC
LDCFD FSRC, AC

LDCDF FSRC, AC
W

LOAD CONVERT
STORE CONVERT

STCFD AC, FDST

CLEAR

CLRF FDST

TEST;

TSTF FDST

STCDF AC, FDST
CLRD FDST
TSTD FDST

ABSOLUTE

ABSF FDST
-

NEGATE

ABSD FDST
-

NEGF FDST

“NEGD FDST

LOAD EXPONENT

LDEXP SRC, AC

LOAD CONVERT INTEGER TO FLOATING

LCDIF SRC, AC
- LDCID SRC, AC

~
STORE EXPONENT

LCDLF SRC, AC

LDCLD SRC, AC
STEXP AC, DST

STORE CONVERT FLOATING TO INTEGER

STCFI AC, DST
STCFL AC, DST
'STCDI AC, DST
STCDL AC, DST

- LOAD FP11’s PROGRAM STATUS

LDFPS SRC

STORE FP11°s PROGRAM STATUS

STFPS DST

STORE FP11°s STATUS

STST DST

COPY FLOATING CONDITION CODES

CFCC

SET

'SETF

FLOATING MODE

SET INTEGER MODE

SETI

LOAD UBREAK REGISTER

LDUB

LOAD SHIFT COUNTER

LDSC

STORE AR REGISTER IN ACO

STAO

MAINTENANCE RIGHT SHIFT

MRS

STORE QR REGISTER IN ACO

STOO

SET DOUBLE MODE

D
SET

SET LONG INTEGER MODE

SET L

DOUBLE OPERAND INSTRUCTIONS: OPR FSRC, AC
OPR AC, FDST
15

Format

Fr1 r

0oC =17

FOC

FSRC/FDST

OP Code

Instruction/Operation

Mnemonic

171000 + AC * 100 + FSRC

Floating Multiply

MULF FSRC, AC

AC < (AC)* (FSRC) if [(AC)
* (FSRC)] LOLIM;

MULD FSRC, AC

else AC <0

FC <0

FV <« 1if (AC) > UPLIM; else FV <0
FZ < 1if (AC) =0;else FZ < 0
FN < 1if (AC) <0;else FN <0

171400+ AC * 100 + FSRC

MODF FSRC, AC

Floating Modulo

MODD FSRC, AC

AC V 1 < integer part of [(AC)* (FSRC)]
AC < fractional part of (AC)* (ESRC)
— (AC V 1)if
| (AC)
* (FSRC) | = LOLIM or FIU
= 1; else AC <0
FC <0

FV < 1if (AC) > UPLIM; else FV <0

FZ < 1if (AC)=0;else FZ <0
FN
< 1if (AC)<0;else FN <0
The product of (AC) and (FSRC)

bits in

single-precision

bits in

floating-point

format

double-precision floating-point format. The integer part

of the product [(AC) * (FSRC)] is found and stored in
AC V 1. The fractional part is then obtained and stored

in AC. Note that multiplication by 10 can be done with

zero error, allowing decimal digits to be stripped off
with no lossin precision.

- ADDF FSRC, AC

172000 + AC * 100 + FSRC

| Floating Add

AC < (AC) + (FSRC) if [(AC) (FSRC)] > UPLIM

ADDD FSRC, AC

else AC <0
FC <0

FV < 1 if (AC) > UPLIM; else FV < 0

FZ < 1if (AC)=0;else FZ <0
| FN < 1if (AC) <O0;else FN <0

LDF FSRC, AC

Floating Load

AC
LDD FSRC,

AC < (FSRC)

172400 + AC * 100
+ FSRC

FC <0
FV <0

FZ < 1if (AC)
= O else FZ <0
FN < 1if (AC)
<0;else FN <0
SUBF FSRC, AC

SUBD FSRC, AC

Floating Subtract

> LOLIM |
— (FSRC)]
AC < (AC)— (FSRC) if [(AC)
else AC <0

FC <0

FV < 1if (AC) > UPLIM; else FV <0

FZ < 1if (AC) =0;else FZ <0

FN < 1if (AC) < 0;else FN <0

173000 + AC * 100 + FSRC

DOUBLE OPERAND INSTRUCTIONS: OPR FSRC, AC (Cont.)
OPR AC, FDST
Mnemonic

CMPF FSRC, AC

Instruction/Operation

Floafing Compare |

OP Code

173400 + AC * 100 + FDST

CMPD FSRC, AC | (FSRC) — (AC)
FC <0

FV <0

FZ < 1 if (FSRC) — (AC)=0;else FZ <0
FN « 1if (FSRC) — (AC) < 0;else FN < 0

STF AC, FDST
STD AC, FDST

Floating Store
FDST <« (AC)

174000+ AC * 100 +
|

FDST

FC < FC
FV < FV
FZ < FZ

FN < FN

'DIVF FSRC, AC | Floating Divide
DIVD FSRC, AC

AC < (AC)/(FSRC) if [(AC)/(F SRC)] > LOLIM else

174400 + AC * 100+ FSRC

AC«<0
FC <0

FV < 1if (AC) > UPLIM
FZ < 1if (AC) =0;else FZ <0
FN < 1if (AC) < 0;else FN <0
STCFD AC, FDST
STCDF AC, FDST

Store

Convert from Floating to Double or Double to

176000 + AC * 100+ FDST
F.D — single-precision to double-precision
floating

Floating

FDST < C
(AC)
FC < 0
F.DVD,F

D,F — double-precision to single-precision
floating

FV < 1if (AC) > UPLIM; else FV <0
FZ < 1if (AC)
= 0; else FZ <0
FN < 1if (AC) <O0;else FN <0
LDCDF FSRC, AC

Load Convert Double to Floating or Floating to Double

LDCFD FSRC, AC | AC
<C
(FSRO)
FC
<0 F.DV D,F

floating

FV < 1if (AC) > UPLIM;else FV <0

- D,F — double-precision to single-precision
floating

FZ < 1if (AC)=0;else FZ <0

FN«<1if (AC)<O0;else N«
0
If the current format is single-precision floatlng point
(FD
= 0), the source is assumed to be a double-precision

number and is converted to single precision. If the

floating truncate bit is set the number is truncated;
otherwise,

is rounded.

177400+ AC * 100 + FSRC

F,D — single-precision to double-precision

If the

current format is

double-precision (FD = 1), the source is assumed to be a
single-precision number and is loaded left justified in the

AC. the lower half of the AC is cleared.

SINGLE OPERAND INSTRUCTIONS: OPR FDST
15

Mnemonic

|
Clear

CLRD FDST

FDST < 0

FOC

Instruction/Operation

CLRF FDST
-

0C =17

Format Fr2 l

FDST

OP Code

170400
+ FDST

FC <0
FV <0
FZ <1

FN <0

TSTFEF FDST

Test

TSTD EDST

FDST < (FDST)

170500 + FDST

FC<«<0
FV <0

FZ < 1if (FDST) =0;else FZ < 0
FN « 1 if (FDST) < 0; else FN < 0
ABSF FDST

Absolute

ABSD FDST

FDST <« — (FDST )if (F DST) <0; else FDST « (FDST)

170600 + FDST

FC <0
FV <0

FZ < 1if (FDST) = 0; else FZ <0
FN <0

NEGF FDST

Negate

NEGD FDST

FDST <« — (FDST)

170700 + FDST

FC <0
FV <0

FZ < 1if (FDST) =0;else FZ <0
FN < 1if (FDST) <O0;else FN< 0

DOUBLE OPERAND INSTRUCTIONS: OPR SRC
OPR DST
15

Format

Mnemonic
STEXP AC, DST

0C=17

]

"~ FOC

Instruction/Operation
Store Exponent

| [ AC.

DST < AC EXPONENT-200
FC <0

FV <0

FZ
< 1if (DST)=0;else FZ <0
FN
« 1 if (DST) <0;else FN <0
C < FC
V < FV
Z < FZ

N < FN

SRC/DST

- OP Code

175 000+ AC* 100+ DST

DOUBLE OPERAND INSTRUCTIONS: OPR SRC (Cont.)
OPR DST

Instruction/Operation |

Mnemonic

STCDI AC, DST
STCDL AC, DST

175400 + AC * 100 + DST

Store Convert from Floating to Integer

STCFI AC, DST

STCFL AC, DST

OP Code

| Destination receives converted AC if the resulting integer
number can be represented in 16 bits (short integer) or
32 bits (long integer). Otherwise, destination is zeroed
and C bit is set.
|

FV <0

FZ < 1if (DST) = 0;else FZ <0
FN <« 1if (DST) <0;else FN <-0

STCFI — Single float to single integer

C < FC

STCDI — Double float to single integer

V < FV

STCDL — Double float to long integer

STCFL — Single float to long integer

Z < FZ

N < FN

When the conversion is to long integer (32 bits) and
o

address mode O or immediate mode is specified, only the

most significant 16 bits are stored in the destination
register.
LDEXP SRC, AC

Load Exponent

176400+ AC * 100 + SRC

AC SIGN <« (AC SIGN)
AC EXP <« (SRC) + 200

AC FRACTION <« (AC FRACTION)
"FC <0

FV « 1if (AC) > UPLIM
FZ < 1if (AC)=0;else FZ=0
FN « 1if (AC) < 0;else FN=0
LDCIF SRC, AC

Load and Convert from Integer to Floating

LDCID SRC, AC

LDCLF SRC, AC

FC«0

LDCLD SRC, AC

FV <0

|
|

177000 + AC * 100 + SRC
LDCIF — single integer to single float
LDCID - single integer to double float
LDCLF — long integer to single float

LDCLD — long integer to double float

FZ < 1if (AC)=0;else FZ <0

FN < 1if (AC) < 0; else
FN < 0
CFL,FD specifies conversion from a 2’s complement
integer with precision I or L to a floating-point number
of precision F or D. If integer flip-flop IL = 0, a 16-bit

integer (I) is specified; if IL = 1, a 32 bit integer (L) is
specified. If floating-point flip-flop FD = 0, a 32-bit

floating-point number (F) is specified; if FD = 1, a 64-bit
floating-point number (D) is specified. If a 32-bit integer
is specified and addressing mode O or immediate mode is
used, the 16-bits of the source register are left justified,

and the remaining 16-bits are zeroed before the conversion.

OPERATE INSTRUCTIONS: OPR
15

Format

rs [

0C =17

FOC

Instruction/Operation

Mnemonic

CFCC

Copy Floating Condition Codes

OP Code
170000

C<«FC
V< FV
Z < FZ

N < FEN

SETF

Set Floating Mode

170001

FD <0

SETI

Set Integer Mode

170002

FL <0
LDUB

Load Microbreak Register

170003

This instruction is a maintenance instruction in which

the content of register R3 is gated into the UB register.

| When the control ROM address register matches the
contents of the UB register, a scope sync is generated. If
the FP11 is in maintenance mode (FMM=1), an interrupt
is also generated and the FPU traps to the Ready state.
A UB interrupt cannot be generated by the Ready state

or by the

states that are used to generate the UB

interrupt.

LDSC

Load Step Counter

|
This is a maintenance instruction in which the content

170004

of register R4 is gated into the step counter, if the FP11
is in maintenance mode (FMM=1). Whenever the step

counter is loaded by an LDSC, normal loading via the

microprogram is inhibited until the step counter is
incremented to zero. This allows partial quotients and

products

to be formed for diagnostic purposes. If

FMM=0, the LDSC acts as a NOP.
STAO

170005

Store AR in ACO
AC0(54:32) <« AR(57:35) it FD=0

ACO (54:0) <~ AR (57:3)if FD =1
MRS

Maintenance Right Shift

170006

AR < AR/2; QR < QR/2
STQO

Store QR in ACO

170007

BR < QR; AC(54:32) < BR (57:35if FD=0
ACO{54:0)«<BR (57:3)if FD =1
SETD

Set Floating Double Mode

170011

FD <« 1
Set Long Integer Mode

170012

FL <1

//T.

SETL

SINGLE OPERAND INSTRUCTIONS: OPR SRC
OPR DST
|

Format F4 L

Mnemonic

oC = 17

FOC

I |

Store FP11’s Program Status Word

]

170200 + DST

Store FP11’s Status

DST « (FEC)

SRC/DST

170100 + SRC

FPS < (SRC)
|

OP Code

Load FP11’s Program Status Word

DST <« (FPS)
STST DST

Instruction/Operation

LDFPS SRC |
STFPS DST

170300 + DST

DST + 2 <« (FEA) if not mode O or not immediate mode

"¢J[SaIpespouwr()utjewlIof[4 HJYTIDON 1N~ON Sd4.LS~O~ON
ONWS E[)
«1[B0AIU0d)g

dOA34~ID1NdS

START
STRG1+-0

*00(0)

10 (1)

SUB, SHIFT

QR3(DBL) | QR2 (DBL)

QR35(SNG) |QR34 (SNG)

STRe!

FUNCTION

RIGHT SHIFT QR,AR,INCREMENT SC **

AR<«—BR+AR,RIGHT SHIFT QR,AR,INCREMENT SC 3

RIGHT SHIFT QR, AR,INCREMENT SC

AR<—AR-BR,RIGHT SHIFT QR,AR,SET STRG1{,INCREMENT SC

AR<—AR+BR,RIGHT SHIFT QR,AR,RESET STRG1,INCREMENT SC

{

RIGHT SHIFT QR,AR,INCREMENT SC

AR<—AR-BR,RIGHT SHIFT QR, AR,INCREMENT SC

RIGHT SHIFT QR,ARINCREMENT SC

% For double precision format 00(0)=QR3,QR2,(STNG{)
For single precision format 00 (O)= QR35,QR34,(STNG
1)

%%Thg step counter is set to the two's complement of the number of bits in the multiplier and is checked
for zero after each incrementation.

11-0437

Multiply State Diagram

STAy

o1t

010

000 *
001

001

010

011

010

SUBTRACT

SHIFT

(RR

®* Three digits shown throughout state diagram refer to bits AR59, 58, and 57.
For example,

ARS57 =JRRO
ARS58 = RR1

ARS59 = RR2
11-0443

NOTE

BR is always positive and normalized.

State Diagram for Divide

<0:61>agI«,_ala—nl<suQ<g0>:GI>v8.I«va|
4 4dX jf&—

|_.<|su_gz|g>

| O¥3Z#Ol

S} 118

2MNJ01D01VvQd3Z v1ivyd 1lvd-H XHE 4|

] _ L K1+=272198]¥43dNSI<8:G|I>31A8|NOILIANODo-m8—3_0—0J19071
osbvi-i|

32 BIT

AC
A

ACO [3]

ACO [2]

Act [3]

Act

AC2 [3]

Ac2 [2]

AC2 [1]

AC3 [3]

AC3

[2]

AC3 [1]

AC3

AC4 [3]

AC4

[2]

AC4 [1]

AC4 [0]

ACS [3]

AC5 [2]

AC5 [ 1]

AC5 [0]

AC6 [3]

ACe [2]

Ace [1]

AcCe [0]

AC7 [3]

AC7 [2]

AC7 [ 1]

AC7 [0]

[2]

ACO [{]

’

Act

ACO [0]

[1]

ACt

[0]

Ac2 [0]
[0]

ACCUMULATORS fi
,

[3]

[2]

16 BITS

(1]

16 BITS

[o]

16 BITS

11-0805

32 BIT

as|4a7

WORD

=)
16 WORDS

’

|15

28|27

24(23 20119

16|15

12|11

8|7

413

8 "4-BIT WORDS" =
32 BIT WORD
11-0854

ALU
Control

Mode

0
0
0

1
0
1

1
1
0

0
1
0

~(AVB)

0
0
0

1
1
1

0
1
|

1
0
i

A plus B
B
AANAB
l

1
1
|
1

0
0
0
1

0
1
1
0

1
0
1
0

1
1

i
1

|
1

0
1

A plusB plus1

A minus1

AVB
A

X =don’t care

0= low

1 = high

~B
A minus B minus 1
ANA~B

16
17

“mnes

|~A

2
3
4

11
12
13
14

A minusB
0
~ (A AB)

5
6
7

Carry

ALUCO)

ALU ‘Sel t'L .

Function

Field

(ALUC3—

1
0
1

X
1
X

0
1
1

0
0
1
1
{

0
i
|

0
X
X

|
| Drive ALUS2 low

Drive ALUSO low

Drive ALUS]I low

|
X
X
X

X
X

%|egwos-loo7asn3aaw7sa,voje—1818 7727|.

121421€9,viwndve%NCws8do,1[fe°—VuxewL]|Vw]xYwAS|awydLSNy|4awy||awyd.L
\

1. S9 b ¢ L 0

(drr)

| 4vn T ||

TOnad~o\7oan7Ed G_74— ¢2|7-2 !2g|W7ou0118(O)€hI6vi-1}|
Zb

|u3Adw0onygl

6-Bit Branch Bits

UAF

If branch condition true,

Trap to Ready

crom 134

Selects multiplexers

CROM(12:11)

Selects inputs to multiplexers

UAF

UBR

—~——

‘

UBR

~—

UBR

UJp

~CROM (10:08)

The three UBR bits are applied to each of the six multiplexers and uniquely specify one of the inputs to the
multiplexer. If UBR bits 2, 1, and O are all 1s, the multiplexer output goes to 0, which indicates no
modification takes place. For all other combinations, the multiplexer output goes toa 1 if the selected
branch condition is true. The UAF bits specify the multiplexer(s) as follows:

UAF1
0

UAFO0

Multiplexers Selected

0 through 5 if UBR is even (UBRO on a 0)
2 through 5 if UBRis odd (UBRO onal)

0 Multiplexer selected

1 Multiplexer selected

Both O and 1 Multlplexers selected

Multiplexer Branching Conditions

FIRD?2

| FIRDI

FIRD4

B | FIR07 (1)

FIRO6 (1) | FIR11 (1) | FIR10 (1)

RNGI1

RNGO

FT (1)

BB1Z ( ‘1)

FIRDO
SD (1)

| BN (0)

F | FIRD6

FIRDS

FIR08 (0) | ARS8 (0)

ARS59 (0)

‘BZ (1)

H|O

Immediate

~ (FCAFIC) | FD (0)

~CONVSP | ~(FVAFIV)

SCF.60

| MO

(165) €—— Current ROM Address

STR Rounded Result
ALUS <« ~ A

;

this particular state

Inputs

FIU (1)

AR50 (0)

Multiplexer | D | 0

Symbolic name for‘

)/-—\\)\

A | SUB FRAC
C | RNG2

FIRD3

ACMX < FALUH
ACS [3:2] < ACMX
SET FCC (1)

~ ROM Next Address

\Branchjng conditions (certain

blocks will have no -branch conditions)

The branching conditions are designated as follows:
|

represents the octal decode of the

6F2

decode of microaddress field (bits 12

and 11 of control ROM)

microbranch bits (bits 10 through
8 of control ROM)

FRL
FRH

Fraction Data Path Low Order

M8115-0-01

Fraction Data Path High Order

M8114-0-01

FRM

FP ROM and ROM Control

FXP

Floating-Point Exponent Data Path

The FRL group of prints contains the following logic:

v R W

1. lower half of FALU
lower half of AR

lower half of BR
lower half of QR
floating-point status

ACMX

scratch pad (AC7-0)

8. BMX

The FRH group of prints contains the foliowing logic:

NovA W

1. upper half of FALU

upper half of AR

upper half of BR
upper half of QR

clock logic, times states, time pulses

. sign of source (SS) and sign
of destination (SD) logic
fractional control logic

The FRM group of prints contains the following logic:
. control ROM

. control ROM address register
. Scratch pad addressing logic
. ROM multiplexers

. ROM data buffer
6. interfact logic

The FXP group of prints contains the following logic:
. EALU

EMX

. Step counter
FIR

. BA register
. BD register

. U break register
. DIMX

BRanching Logic
ot

. Range ROM"

FRHE

. MRI and MRO register

‘

. MUL ARITH flip-flop
. Pause logic

. STRG I flip-flop
. AR control
. QR control

. MUL SUB f{lip-flop

. AR clock logic
[E—

. QR clock logic

. Sign bit

M8112-0-01

M&8113-0-01

EXPONENT CALCULATION LOGIC

uB <7:0>

FXPy

FPS<15:0> I I

FALUH

FALUL

I
.

(B)

FXPA,

sc<si0> ) }

FXPB

EMX

FALU<59:0>
(A)

01 2 3

FXPL

(8)

ACMX

3 FXPB

FXPA,

FRHB-FRHD,

FRLE-FRLK

FRLE

FRLA-FRLD

l
|

]

TrRLP IEALU

EALU<15:0>
" (A)

SCRATCHPAD | | FRACTION CALCULATION LOGIC

ACCUMULATORS

FRLK

CNST

BUS ADDRESS
-3

FXPK

~ DATA IN

I
I

C BD<15:o>j

FXPC

(

BA<I5:0> )

FXPC

FXPD

FRUN

AR<59.0>

Egtg

Fgfiggfiflg

lacH

N3MX 1 acL
5|

i=0 THRU 7

SLEALY

(

ACL [3:01<15:0>

_EXP

11-0820

DATA PATH DEFINITION

ACMX0(31) < ~BN; ACMXO0 (30) < BZ; ACMXO0 (29:16) + 37777; ACMX0(15:0) < FPS

ACMXI1 (31:16) < EALU (15:00); ACMX1 (15:00) < EALU (15:00)

(

ACMX2(31) <~ SD; ACMX2 (30:23) < EALU (07:00); ACMX2 (22:00) < FALU (57:35)

ACMX3 (31:00) < FALU (34:03)
~ BMXO0 (15:00) <EALU (15:00)

BMX1 (15:00)
< AC; [3] (15:00) or AC; [1] (15:00)
BMX2 (15: OO)<—AC [2] (15:00 or AC [0] <15:00)

BMX3 (15:08) <0; BMX3 (07: OO><—AC [3:2] (30:23) or AC; [01:0] (30:23)
EMXO0 (15:00) < BA (15:00)
EMX1 (15:00) < DIMX (15:00)
|

EMX2 (15:00) < CNST ¢15:00)

EMX3(15:06) < 0; EMX3 (05:00) < SC (05:00)
FMXO0 (02) < BR (35); FMXO0 (01) < BR (19); FMX0(00) < BR (3)

FMX1 (02) < AR (34); FMX1 (01) < 1; FMXO0 (00 < AR (02)

‘

LDQI = QR (59) < 0; QR (58) « 1 if AC; [3:2] (30:24) # 0 else QR (58) < 0
QR (57:35)
< AC; [3:2] (22:0)

LDQO = QR (34:3) < AC; [1:0] (31:0); QR (2:0) < 0

ENTER HERE
AFTER EXECUTION OF

‘ ~(101)

FOP0O

FET 00

(72)

RDY 20

FET 10
IRD 00

WAIT FOR NEXT FP INSTR

BACKUP PC; ENA. FP ATTN

LD FIR & INSTR ADDRESS

t, (BA<PCB)

DIMX<«DATA ADDRESS

FP ATTN ALLOWS TIMING

t, SHFR<PCB - 2

EMX<DIMX

TO ADVANCE TO T3

t, BEND

ALU'S<B

t, PCA<PCB - 2

ACMX+EALU

ts FP ATTN

WAIT FOR FP ATTN

PCB<PCA; SR<SHFR

t; FIR-DATA IN
t; SS+SD<0
REQ«1

FOP 10

(133)
RDY 30

LOOK FOR BREAK RE-

QUESTS SEND PC & OP
CODE TO FP11 WITH FP

(76)

LD INS. ADDRESS

ATTN

DIMX<+DATA ADDRESS
EMX+DIMX

t, DA<PCB .

ALU’S<B

t, (SHFR<BR)

ACMX+EALU
S, AC7[1]<ACMX

' S; ENABLE FP SYNC
IF ~CONV SP

RDY 60

(234)

NO MEM CLASS LD

CONTENTS OF GENERAL

FOP 20

REG.

{(174)

EMX<DATA IN

CLK. BREAKS; SEND PC &

ALU'S<B

OP CODE TO FP11 AND

BMX+<EALU

LOOK FOR FP READY

WAIT FOR FP ATTN

't; BA<PCB

AT T2 OF NEXT ROM STATE

t, (SHFR<BR)

‘FROM FP SYNC

" t, BRQ STROBE

t, BD<BMX

S; ENABLE FP SYNC

NOM 36

50 ns

(67)

LD DATA INTO FPS
—FP SYNC

FOP 30

S1 REQ+0
EALU+A

(173)

t, FPS<EALU

STEP PC AND GET FP11

RDY 00

STATUS
t, (BA<FP EALU); READ FP

ty PCA<PCB+2
t, BR<BUS

S1 REQ+0

PCB<PCA

ACMX<VFPS

$4 AC7(0]<ACMX

(211)

FOP 50

FP STATUS IN BR

LD FPS IN BD

FROM DECODE OF FIR

t, (BA<EALU)

WITH FCLD EN ONLY

t, (SHFR<DR)

ON [CFCC,STCFI,STEXP]

.- SCR OUT+AC7{0] .
BMX<ACL

t; BEND

t, BD<BMX

t, CCBR(FPCC)

RDY 20

IF ENABLED BY FP11

(362)

(72)

WAIT FOR NEXT FP INSTR
LD FIR & INSTR ADDRESS

PUT DEST REG INBR &
ENABLE FP ATTN

DIMX<+DATA ADDRESS -

EMX<«DIMX

t, (BA<EALU)

ALU'S+B -

t, SHFR<DR

ACMX<EALU

ty FP ATTN

WAIT FOR FP ATTN

BR<SHFR

t; FIRDATAIN.

(316)

FOP 70

(6)

l ,

RDY 10

LOAD CCSIF TOLD TO;

FOP 60

l (3

WRITE FPS IN SCRATCH

t, SHFR<PCB+2

t; SS+SD<0
REQ«1

SEND FP ATTN & WAIT
EP ATTN

FOR FP11

t, (BA<EALU)

t, SHFR<BR

FP SYNC
,

-FP SYNC

-FP REG WRITE

.
FPREGWRITE

(NEVER TRUE FOR
1o\ eTrUCTION)
1/

FOP 80

(376)

FOP 90

GET FP DATA

(375)

MODIFY DEST REG &
ENABLE FP ATTN

GO TO READY

t, (BA<EALU)

EP READ

—

t, (SHFR<BR)

t, (BA<EALU)
SHrReBR
o

t; GR[DF]<SHFR

t; FP ATTN

ts BRCBUS

11-1443

CP/FPP Interflow Mode 0
46

FET 00

RDY 20

(217

START FETCH NEXT

INSTR

DIMX<+<DATA ADDRESS

t; BA<PCB;BC<DATI

t, SHFR<SR—SR

EMX<DIMX

FP ATTN

ALU'S<B

t, BUST; CLEAR FLAGS

ACMX<«EALU

ty IR<SHFR

WAIT FOR FP ATTN

(260)

FIR<DATA IN

t; SS+SD«+0

REQ«1

GET INSTR & STEP PC

RDY 30

t, BA<PCB;BC<DATI

t, (SHFR<PCB+2)
t; BUS LONG PAUSE

EMX<+DIMX
ALU'S<B

PCB<«PCA

1RD 00

ACMX+EALU

S, AC7[1]+~-ACMX

(343)

'S5 ENABLE FP SYNC

IFVCONV SP

DECODE THIS INSTR &

RDY 70

STEP PCA BEYOND &

READ SRC & DST FIELD

GEN REGS
t, BA<PCB;BC<DATI

ALU’S+B
BMX<«EALU

"WAIT FOR FP ATTN

t; PCA<PCB+2

S; ENABLE FP SYNC

ty —SF7:SR+GS[SF]

SF7:SR<SHFR

LD 12

—DF7:DR+GD[DF]

DF7:DR«<SHFR

(241)

LD 1ST WORD OF SRC

(101)

IN AC6

-BACKUP PC TO POINT AT

INC ADDRESS

INSTR;ENABLE FP ATTN

FPC1<DATI

EMX<DATA IN

t, (BA+PCB)

ALU'S<\B

t, SHFR<PCB-2

ACMX<EALU

t; BEND

WAIT FOR FP ATTN

t; PCA+PCB-2

S, AC6[3]<-ACMX

ty FP ATTN

'ty SET FCC'S

PCB<PCA

ENBL -0 INTERRUPT

SR<SHFR

FOP 10

(254)

EMX<DATA IN

t, SHFR<PCB

LOAD CLASS INS

t; CONDITIONAL BUST

FOP 00

(76)

DIMX<DATA ADDRESS

PCA<+PCB+2

tg IRBUS:BR<BUS

l
LD INS ADRS

t; PRQ STROBE
~

(72)

LD FIR AND INS. ADRS

CLEAR INSTR REG

FET 10

‘

WAIT FOR NEXT FP INS.

S; ENABLE FP SYNC

(133

LD13

LOOK FOR BREAK RE-

(202)

QUESTS SEND PC & OP

LD 2ND WORD OF SRC

CODE TO FPU WITH FP

IN AC6

ATTN
INC ADDRESS

t, BA<PCB

FPC1<DATI

t, (SHFR<BR)

[)

EMX<DATA IN
ALU'S\B
ACMX<EALU

BRQOO

(174)

'WAIT FOR FP ATTN

S, AC6[2]<ACMX

CLK BREAKS; SEND PC & OP°

S, ENABLE FP SYNC

CODE TO FPU & LOOK FOR
FP READY

LD 22

t, BA<PCB

HALF OF ACS (AC6) AND

t; BRQ STROBE

4 GOTOLDF

$; REQ-0

-FP SYNC
FOP 30

(237)

READ MOST SIGN.

t, (SHFR<BR)

SCR OUT<+ACS[3:2]

(173

BMX+EXP
t, BA<BMX

STEP PC & GET FPU

t, QR+LDQ1

STATUS

t, SS<SCR OUT(31)
t, BR<QR

t, (BA<FP EALU)
READ FP
t, SHFR<PCB+2
t; PCA+PCB+2

ts BR<BUS
PCB<PCA’

Blch
11-1442-A

CP/FPP Interflow Mode 2 (sheet 1 of 2)

(5)

NOM 04

(111)

D12.80

lD I

DST ADRS INDR;SRC

READ LEAST SIGN. HALF

OPERAND IN BR & SR
CHECK STACK LIMIT

TO SD

OF SOURCE AC+MOVE SS

SHFR<+BR

t, QR<LDQO

CFCC,

t, BUST;GR[DF]

t, BR<QR

STCFI,

t; SR-SHFR

t, SD<SS

STEXP

CC+BR (FPCC)

NOM 06

IF ENABLE BY FPU

(135)

D12.70

SCR OUT«ACS[1:0] -

]

FCLD EN

t, BA+~DR;BC<BSOP1

‘

(21)

WRITE INTO MOST SIGN.
HALF OF DEST. AC

STEP DST FIELD
ALU'S<\B

FMX<BR
ACMX<FALUH

t, (BA<DR)
t, SHFR<DR+DSTCON
t; BEND

EMX<BA

AD2,AD1

S, ACD[3:2]<SCR IN

0 1
«—

BRQ STROBE

t, SET FCC (0)

ts PCA<~DR+DSTCON

RDY 00

GR[DF}<SHFR

t; DF7:PCB<PCA

(036)

{

FOP 40

(3)

WRITE FPS IN SCRATCH .

S, REQ«0
ACMX<\FPS

-DST ADRS TO BR

S, AC7[0]<ACMX

ENABLE FP ATTN

RDY 10

t, (BA<EALU)
t, SHFR<DR

(6)

- LOAD FPSIN BD

t, BEND

t; BR-SHFR

SCR OUT<+AC7[0]

FP ATTN

BMX<ACL

t, BD<BMX
FSV 20

‘

(225)

- SEND FP ATTN & WAIT

UNTIL FPU READY
FP ATTN

t, (BA<EALU)
t, (SHFR<PCB)
t, BRQ STROBE

FP SYNC

-FP SYNC

[FPSYNC

To _ -FPREQ
(F1]

FP REQ

V 00

(245)

DO BUS OP FOR FPU;

FOR DATO BR GETS GOOD
DATA FROM FPU TO

OuUTPUT

t, BA<DR;BC«~FC
FP READ

t, (SHF<PCB)
t; BUST;GD[0]
ts BR<BUS

FSV 10

FPC1 FOR DATI

(150)

FINISH BUS OP & STEP
DR;FOR DATI BR GETS

' DST OPERAND FOR FPU;
ENABLE FP ATTN

t, BA<DR;BC<FC
t, SHFR«<DR+2

INCR ADD

t; BUS LONG PAUSE
t, FP ATTN
DR<SHFR

BR<BUS

11-1442-8

CP/FPP Interflow Mode 2 (sheet 2 of 2)

IR
15

IR
14-12

IR
11-09

|
DOUBLE OPERAW'

(1 OF 2)
|

MOV

SRC. DST

2 CMP SRC, DST
|°
3

BIT

SRC, DST

BIC

SRC,DST

BIS

SRC,DST

IR
07-06

IR
05-03

O HALT

2 RTI

| PC AND PS CHANGE (1 OF 2)

IR
08

1
I {

— 0

4 JSR REG, DST

OFFSET

BEQ OFFSET
OFFSET
BLT OFFSET

II
II

|
|

|
I

DST

ADC

DST

REG, SRC

XOR

REG, SRC

SBC

ROR

1
2

ROL
ASR

MFPI

DST

DST
DST

0. RTS REG

RESERVEDI

2 RESERVED

3 SPL PRIORITY
5

3
O

l
|

CCOP MICROINSTRUCTION

- - - -

ASL
DST
MARK OFFSET
SRC

| 1 e WL ol

—_—— e

——

)

RESERVED

(2 OF 2)
2

CMPB

SRC, DST

BITB

SRC,DST

BICB

SRC,DST

BISB

SRC,DST

SuB

SRC,DST

—_—e

| O

)

DOUBLE OPERAND|

BPL' OFFSET

OFFSET

BLOS -OFFSET

BHI

| 9 BVS

OFFSET

QEREL

1 O BHIS OFFSET (BCC)

;'; -

| "l]

i BMI

BLO

OFFSET (BCS)

TRAP

CODE

SINGLE
OPERANDo (2 OF 2)
5

CLRB

DST

COMB

DST

DST
DST

NEGB
ADGB

DST

TSTB

DST

ROLB

DST

3
O

ASLB
DST
RESERVED

MFPD

SRC

MTPD

DST

7 RESERVED

|
|

b — ——— —— — — —

FLOATING POINT AC AND OPERAND-I

’

DST
DST

DST

3 RESERVED

| FLOATING POINT

| 0

— ©

O CFCC

2 SETI

4 LDSC

SINGLE OPERAND

RORB

2 ASRB

INCB
DECB

2 SBCB

o
2
3

NEG

MUL

6 RTT

L_ 7 so8 Ree oFfFseT
|
["PC AND PS CHANGE (2 OF 2)
]

7 RESERVED

DST

{ DIV REG, SRC
2
ASH
REG, SRC
3 ASHC REG, SRC

INC

—-,-—-—-—————:j

SWAB DST

3 TST DST

3 DEC DST

|
|_

O1 COM
CLR DST
DST

L__G_AEE_.SR_C'ESL_:| )

3 53:81‘
5 RESET

|, s e S

SINGLE OPERAND (1 OF 2)

3
5 - RESERVED

DST

OFFSET

——— —— — — — — — —

JMP

BGT OFFSET
BLE

1 WAIT

BNE OFFSET

BGE

IR
02-00

2 STFPS

SRC

FDST |

LDFPS

STST

{

TST (F/D)

DST

CLR (F/D)

DST

FDST

2 ABS (F/D) FDST

| FLOATING POINT OPERATE

—— O

— O

MOD(F/D)

ADD(F/D)

AC, FSRC

1 LD(F/D) AC, FSRC l
SUB(F/D) AC, FSRC
1 CMP(F/D) AC, FSRC

1 O ST(F/D)

AC, FDST |

10 STEXP

AC, DST'-—-—I

1 0

DIV(F/D) AC, FSRC

STC(F/D)MI/L)

LDEXP

LDC(F/D)D/F)

AC,

|
.

DST

STC(F/D){D/F)

AC, FDST

LDC(I/L)F/D)

AC, SRC

SETF

LDUB

STAO

6. MRS

| O MUL(F/D) AC, FSRC L 3 NEG(F/D) _FDSLI l ,

5 sTeo

a
5
:

3
2
5

—_—— e
:

SETD

SETL

|
__|

AC, FSRC |
11-0789

Determination of an Instruction from the Binary Code
49

15
T

- 000000

o 1

000002

INTERRUPT
&
TRAP VECTORS

000400
000402

USER & SYSTEM
A,

PROGRAM

STORAGE

NOTE
1

\ %% 7474

)

LOADER

STACK

*x% 7476

ABSOLUTE LOADER
A

Y Y

*x%7500

PROGRAM

STORAGE

% %7744

AJ
WV

BOOTSTRAP

LOADER

I/0 DEVICE WORD

*%k 7776

I
|

CORE

MEMORY

NOTE 1

| EXPANSION

12K

‘

760002

:L
-~

SIZE

® *®

760000

MEM

I/0 DEVICES AND

PROCESSOR'S

4 INTERNAL

" REGISTERS

16K

20K

28K

24K

777776
t1-1492

PDP-11 Typical Core Mémory Storage Map

START

)

LOAD R1 WITH
THE ADDRESS

OF THE INPUT

DEVICE'S

CONTROL
REGISTER

LOAD R2 WITH
CONTENTS OF
LOCATION %752

ENABLE INPUT
DEVICE TO
READ A FRAME

(BYTE)

MOVE FRAME
READ INTO
LOCATION

+ x 400
[R2]

INCREMENT
COMENTS OF
LOCATION %752

BRANCH TO
LOCATION %724
OF MAINTE
NANCE LOADER
11-1493

Bootstrap Loader, Flow Chart
Bootstrap Loader Coding
Location

Octal

Symbolic

*744

016701

746

750

012702

MOV *776, %1

MOV #352, %2

752

1352

754

005211

INC (1)

756

105711

TSTB (1)

760

100376

BPL.-2

762

116162

MOVB 2(1), *400 (2)

764

766

*400

770

005267

772

177756

774

000765

INC *752
|
BR.-24

*776

177560

(TK)

or, 177550

(PR)

for

12K

16K

117

20K

137

157

24K

for

28K

17476

000000

*%17500

012706

—
—

17724

012767

726

352

730

732

012767

734

765

736

- 740

000167

742
*17744

LOADER

177532

016701

012702

352

373

005211

353

MAINTENANCE

%
- OVERLAY

105711

100376

116162

BOOTSTRAP

LOADER

005267
177756

000765
17776

(TK) or (PR)

TK = 177560

Low-Speed Reader

PR =177550

High-Speed Reader

*Starting address of the Bootstrap Loader

**Starting address of the Maintenance Loader

°©
o

Qo
Qo
o O

Ov
Y

0O
o

00000000000 0000000000000D0COO0O0O0
Y

o Y
Y

Y
Y

LAST DATA BYTE _|

O
M

00O

°0O

Ker

IN BLOCK N-2

L START OF BLOCK N
CKSUM BYTE FOR BLOCK N-1

CKSUM BYTE
FOR BLOCK N-2

LAST DATA BYTE
IN BLOCK N-1
FIRST DATA BYTE

H1 ORDER BYTE

| L0AD

LO ORDER BYTE | ADDRESS
HI ORDER BYTE | gyTE COUNT
LO ORDER BYTE | FORBLOCKN-1
|

| }START OF BLOCK N-{

11-1461

Absolute Loader Tape Format

ADDRESSING MODES
MODE O

OPR %R

NOTES

L INSTRUCTION 1
GPR

OPERAND

]

MODE 1

L INSTRUCTION ]
GPR

— - ADDRESS J
-

OPERAND j

ADDRESS J

[

WORD

BYTE

MODE 3

OPERAND

OPR ®(R)H

l INSTRUCTION ]
GPR

._____*1

ADDRESS

OPERAND

]

R equals a number between Oand 7.

1H-14949

Addressing Modes (sheet 1 of 3)

MODE 4

OPR-(R)

[ INSTRUCTION

NOTES

I
GPR

ADDRESS

WORD

BYTE

l——’|‘GPRADDiESS I

ADDRESS

.
MODE 6

GPR

4y
INDEX:*

OPERAND

|
>~

'
ADDRESS

l—»[

GPR

I
[

INDEX: +X
|

OPERAND J

ADDRESS

]

]
+

»{

OPR*X(R)

PC L INSTRUCTION J
PC[
+2

]

|——or ADDRESS J
]

11-1495

'Addressing Modes (sheet 2 of 3)

PCl INSTRUCTION J
PC
+2

OPERAND:n:

MODE

OPR

®O#A

OPR

MODE 6

OPERAND

OPR A

PC [ INSTRUCTIONJ

INDEX
|

O#A=0PR D (7)+

J
!

r ADDRESS:A

NOTES

OPR #n=0PR (7) +

PC[ INSTRUCTIONJ

OPR # n

//-—.,\'

PC REGISTER ADDRESSING
MODE 2

‘a4 IEEXT INSTRUCTIO4NJ .

OPR A=0PR*X(7)

A minus updated PC=INDEX

OPERAND -

MODE 7

OPR @ A

INSTRUCTION J

PC
PC

INDEX

A minus updated PC=INDEX

'+4 FEXT INSTRUCTIOM
|
NOTE:

;

ADDRESS:

l:—Pl OPERAND J

The mode specified overrides the fact that the reqgister is the PC (register 7). EXAMPLE: 500/CLR-(7)
502/777
504/400
506/HALT

.2 [

OPR ®A=0PR D X (7)

Program causes halt at address 500 whose

content has been offered to=0s

11-1496

Addressing Modes (sheet 3 of 3)

¥IISVMM3SNN3IdNSINMIYVivO
AYI4SIA HILSIOIH

INMIN1T OHdAHd

o -~

auwasans1n1gHu3mddNnSsTvasNuMaIyNNGdD/-d4AHdSNOD
43S181N934

IsHNnY3vSHOdYE

XWHS

12}

{11)

xwe

0SB8 NHVW 13540

H4HS

[(»L2uS1])

¢[}"1S30 “LSN: QD dvil HO1J3A

3'0vy9)

sal(i1)9¢]?,m

2€| LavoTlAdIHS 1“3LH4O3l7Y

XWIN

([XBLi-N6)1

“XNON

WOM4 dd4 NIv3

€ Qv0ol L1 )

[(eO€1H-vLS€)] <a20v:'o$>lHa

0 i

(HA'3qvu9)

¥OdHS

11IT

a-s

XWHQ

€0| O¥13asN %2HQ070

w
o
u
m
:
h
o
z
n
.
w
(HY'I'qvy9) 2 ‘¥4HS:240 @9:L4a-

([»S2n5-y19a)G]

[

o
w
(2]

[

O~ NNT OO

.(H“d.va%e

-XWX

1X3x54@0

dd4 v1lva

AONYWNI:WOD

34ad)

TVN€LYdIANISvS33HA(ALVNYIVYN)

AHOWIW

< 0L ANOD-IN3S

ONOD-IW3S AHON3N

v1va WOd4

40- 4Q LJVYNOLLIGNOD 2 WON4/0LSNAIN
a9:

-avo

2€-§9:04S
L0 ON'YO3NH%SQ2:30Ls74-n9S

O.| S9H4HS

[6¥-05](21)80d

LN3AN3d3Q

8|0d

’ SNy

0Lst-2]o( xus(21)[09-19] €LHOIYavLd144S:I°_H1.S_.v0m&ivS4 -0A4S- LOAJS 20 OL3LNIONQM3LIHM

O dYMS S31A8
91) (SYILSIOIM 0€2 L4GOsN QG.S3_mSN v9L

[(1bLr)-3IsMtd)

Hom

1
]
232dNOS"LSNOJ .OONMJ0TO 41 |H14vOIoN}¥mJ_O0nT_D.01N8V 38 . ad MET[<]Im ue viva
¢Sdavay H3{1HSyId9)3y ouild/\¥F1aX

u1_V-1[BNU)Mu|E1a(ev0Lo)sl{£9]9%o0fTiYLN.1&wHfIJlLmN«IwemviSwiNHmveQIaL(S0I19‘IJYs-Wy1OdN1i)V14A%(e8fHdlO0L¢IMJS,aodBmH./ESmxEAi(uW2mOx1q¥)N:qS[w(LIa2ve-1[-a)m1a8avv(b)oo18(]sXlas&1-e)6Sn8rHu)Il.(ALqSIOAN(ouQdW)O.d(dJ4¥a7d4)QVN,s¥d:1KV—(4&qs—5W0Mdwx—)ItA,<OL310SN0Dviva-S1HOIM
O| MavIo0aTDON N m avo1n

©i ONavol201

.,1Quinog--ATS(Holvul:HOLVHINIO+—0L1TVSTINCON

vN3941[d2o1s-a#1]9TMONOY3903eI0w(Gp=h43i8)TVYNOILIONOJD04%I4N0O4D8_%(C84041)8M(HNM'OI4V'H3v0)VY),wavvN3gs|-oz|fe-WO<82:18>bLE——E2](—01v—y)avy)»=um:mvN3INID:|;

|JNS9&3W4NooOl0N¥1IvlE)LaI3N79H1810I2V4S-N16I52[%L4N034GN32d3Q.as§eN(O1V1I)SN[3O6OeLN-I0IUvGN]INOJO1IDLY1I3O0NO0Dnv|WwOM43z7o0_StNoOzDm)wV(#b{N3S=0i4O=3948I)3Z8=L1ID/1O'dN=(SH(OaTo'NV8DS2E3AnN'I0VM)8AdN0I0H)N8NOI-31dL0)48AIN.OD+VNO{DHLXNyTO4(g8:H'(R3OI0W4vLtvHa))dS3(0Hs'23N308_a_1—v@oyvy)eAoW1ON63_5<8b:(1961>)().vovy)(——il$eu;n_dH10HLN.OD«I—V|HIN0Iz0O1-1 :

2€ ¥V19O/13WpPSOHI—W4OOMdAJd+H4GIIH(04dH30S128JA)VGNI3XNV "HaOvLuoV)HI3N7I3D041

SWNAONI¥YdVA

OON1934V OON-3Snvd _

;

OHa2&2€v-O2iLT0N(3sY70SnN1JeO34-O3IN2NLs8O0VIn'D]8AHN)‘NI4ZO1{DAL13Y—1Iv2SNi'MNs038N3130Q3O4WYN€MoVONO¥1N'YSDNE:3S3N0vdD AMYIQ1SENSobil+dT¥d3OTN0A_SSNOD=(ti=4381)31S031SIdHNO)N-DVH%E034dS{.:ONAS SNOINVI.A:A ISINY3:SeWOU<:O¥:SOvN>INI(L89V¥.)=.==15:NJaVvdfe—N,— IV Y3.1S1934: ;|A‘ ,S
<.:.M[EIUI)0S0[0NUO)‘UOI93SJo[gwreiSer(q
eE—|

WyOeYy F<Wf—0—9Oe:(v€YO9vH>)

SVH1ivoVQdL

—NOILIGNO:D ¥.)—

9_B0#—A'.2=0I37.YLW1ZH4'3IO4JDSNYduIVd4 yfuz.mo:l”_m,:oB2NnwmM—>3<f1uz4m3iNw0om9— W0S8noNngu1QTL&(Iv340AoNIdNOnMN18Id3TWOXiD)/01

(<27W.—V|6o:-1O—veSY36]H>)0

L 2d0se L

2 10Na3sn 2 sne-3snvd
ALINOINdHOLVH18¥Y .

fe] WO <B0:11> . —J(aovy)

Mav(F<fWt8—bYA0L:3oO1i—Sd61->)9l3y HvO—yNT L3Nb£OI'0L—VSNI'WLSe ]{3Sb94i0LudS)3EYAHauJz]V-ou.e(’<.N—A9cl01tOc:—vmV6u¥Yl1—)>o1bB]- &:;uf&l—Ii¥9dzN3mvAM4Sa

MAINT

“CLock | UmBUS A | TERM

FRH (M8114)

FRL (M8115)

FLOATING POINT

FRM (M8112)

~ FXP (M8113)

DAP (M8100)

< 'ON 10[S
I

UBC (M8106)

SAP (M8107)

TIG (M8109)

MEM CTRL (M8110)

PHK ()
A

MTRX (Bipolar=M8111 & MOS=G401)
MTRX (Bipolar=M8111 & MOS=G401)

" MTRX (Bipolar=M8111 & MOS=G401)
MTRX (Bipolar=M8111 & MOS=G401)
‘

‘
MEM CTRL (M8110)

MTRX (Bipolar=M8111 & MOS=G401)

ON10IS—»> 87 LT 9T ST vT €T

6l - 81

L1 91 ¢1

~ SSR (M8108) or SJB (M8117)

MTRX (Bipolar=M8111 & MOS=G401)

SEMICONDUCTOR
MEMORY

MTRX (Bipolar=M8111 & MOS=G401)

DEVICE |

UNI A CABLE

DEVICE 2

UNI B CABLE

DEVICE 3

UNIBUS B TERM

Module Layout

opIS utd

CENTRAL

PROCESSOR

€1

PDR (M8104)

TMC (M 8105)

¥1

Il Ol

RAC (M8103)

IRC (M8102)

GRA (M8101)

DEVICE REGISTER ADDRESSES

Device

CSR

DBR

Vector

Teletype Keyboard

777560

777562

60 BR4

Teletype Printer

777564

777566

64 BR4

Reader (PC11)

777550

777552

70 BR4

Punch (PC11)

777554

777556

74 BR4

Line Clock (KW11-L)

777546

—

100 BR6

Line Printer (LP11)

777514

777516

200 BR4

DECtape (TC11/TU56)

777340

777350

214 BRS

Control

777342

Word Count

777344

Current Address

777346

DECdisk (RC11/RS64)
|

777444
777446

Look Ahead

777440

Disk Address

777442

Word Count

777450

Current Address

777452

Maintenance

777454

DECdisk (RF11/RS11)

777456
-

777460

777472

777462

Current Address

777464

777466

Disk Address Extended

777470

Maintenance

777476

DEC Disk Pack (RP11/RS03)
Word Count

776714

—

Current Address

776720

776722

Disk Address

776724

Device Status

776710

~Error Register
Maintenance Registers

776712
776726
776730

776732

Card Reader (CR11/CM11)
|

777160

777162

Magnetic Tape (TM11/TU10)

777164

772522

Byte Count

772524

Current Address

772526

Status

772520

Device Interface (DR11)

772414

Word Count

772410

Current Address

772412

204 BRS

254 BRS5

776716

Disk Cylinder Address

210 BRS

Word Count

Disk Address

- 772530
|

772416
~

ASCII

ASCH |

ASCII

Octal
- Code

Char

Octal
Code

- Char.

Octal
Code

Char.

| Octal
Code

- Char.

000

NUL

040

100

140

001

SOH

041

101

141

002

STX

042

102

142

003

ETX

043

103

143

004

EOT

044

104

144

005

ENQ

045

105

145

006 |

ACK

046

106

146

007

BEL

047

’

107

147

- 050

110

150

011

051

111

151 -

012

052

112

]

152

013

053

113

153

014

054

114

154

015

055

115

155

016

056

116

156

017

057

117

157

020

DLE

060

120

160

021

DC1

061

121

161

022

DC2

062

122

162

023

DC3

063

123

163

024

DC4

064

124

164

025

NAK

065

125

165

026

SYN

066

126

166

027

ETB

067

127

167

030

CAN

070

130

170

031

071

131

171

032

SUB

072

132

172

033

ESC

073

;

133

[

173

(

034

074

134

174

035

075

135

]

175

)

036

076

136

)

176

037

077

137

<«

177

| DEL

7-Bit

010

7-Bit

DIGITAL EQUIPMENT CORPORATION
MAYNARD, MASSACHUSETTS 01754