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XX-C5B4B-92

December 1980

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Document:	108216 EK-OEBOX-UD-006 EBox Unit Description Jul 80 Sm
Order Number:	XX-C5B4B-92
Revision:	0
Pages:	245
Original Filename:	108216_EK-OEBOX-UD-006_EBox_Unit_Description_Jul_80_Sm.pdf

OCR Text

blL

EK OEBOX-UD-006

EBOX

INSTRUCTION EXECUTION UNIT
'UNIT DESCRIPTION

digital equipment corporation « marlborough, massachusetts

i R

1st Editon, May 1976

2nd Edition. January 1876
314 Edinon. December 1976

4th Edison. December 1977
5th Edihon. May 1980

Copyisgh € 1976, 1977_ 1980 by Digtat Equipment Cotoporation
Tany

Ak Rughts Reserved

The matena! in thus manual s {or informauonal purposes and

Digital Equipment Corporation assumes no responsibility for

any errors which may appear i this manual

A
in US
Punted

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of

Digitsl

Equspment

Corporation, Maynard. Massachuseits

DIGITAL
DEC

DECsystem-10
DECSYSTEM-20

MASSBUS
OMNIBUS

PDP

DiBOL

0s/8

DECUS

EduSystem

UNIBUS

DECLAB

VAX

VMS

RSTS

RSX

1AS
MINC-11

B facht

15 subject to change without notice

CONTENTS

Page
PREFACE

SECTION t

OVERVIEW

1.1
1.2
121

INTRODUCTION......coenr.ee

....EBOX/1-1

BASIC FUNCTIONAL BLOCKS

EBOX/1-6

Instruction Register-Dispatch-Main Control Store....................... EBOX/1-13

122
123

Fast Memory
Address Path

EBOX/1-14
EBOX/)-21

1.24
124}
1242
1243
1244
1.2.5
126

Request and MBox Control
K1 Style Paging

EBOX/1-24
EBOX/1-25

KL Paging
MBox Error Conditions
VMA Control
EBus Control and PI Control
Data Path
Information Flow To and From Memory

1.2.6.1
1.26.2

EBOX/1-28
EBOX/1-43
EBOX/1-43
EBOX/1-47
EBOX/1-50
EBOX/1-50

information Flow 1/0 and Priority Interrupt.......................... EBOX/1-55

SECTION 2

FUNCTIONAL DESCRIPTION

2.1
22
221
222
223
224

INTRODUCTION
EBOX/2-1
MICROPROGRAM STATES AND PROCESSOR CYCLES................ EBOY 12-1
EBox Reset
EBu . 2-1
Microprogram Halt Loop
EBOX/2-6
Microprogram Running
EBOX/2-9
Microprogram Wait State
EBOX/2-10

2258
226
227
23
23.1
232
233
234
235

Microprogram and EBox Frozen
EBOX/2-10
Microprogram Deferred
EBOX/2-14
Microprogram Orgauization
EBOX/2-17
BASIC MACHINECYCLE
EBOX/2-23
Instruction Cycie - NICOND Dispatch to XCTGO............cc...c.
..EBOX/2-31
Indirect Word Request
EBOX/2-31
MBox Response to Indirect Word Request
EBOX /2-38
Address Calculation Continues
EBOX/2-38
A READ Dispatch - Set Up Data Fetch and Prefetch.................... EBOX /2-38

236
237
238

‘

MBox Response to Data Read - Prefetch Begins ... EBOX /245
Executor - Set Up for Store Cycle
EBOX /245
Finish Store Cycle - Perform NICOND Dispatch..............ccounn.e.n. EBOX /249

CONTENTS (CONT)

24
24.1
242

25
25.1
252
253
26
2.6.1
2.6.2
263
264
27
271
2172

213
27.3.1

2132
274
2.74.1
2742
2.743
2744
2745

28
29
29.1
292

293
294
295
295.1

CONTENTS (CONT)

PAGE FAIL CYCLE INTRODUCTION .....................
Page Fail Handling - Functional Flow

Page

.....EBOX /249

VMA Field ... et
raaensEBOX/2-114

..EBOX /2-55
Process Table References
EBOX/2-59
TRAPCYCLE - INTRODUCTION. ......cormreirrerennr e s EBOX/2-59
Trap Handhing. . . . . .c vemene rnencrce meceren enemr nms e
s evscess e
..EBOX /2-59
AdAress GENErBtion.........covveeeerieerreeeneeereroressenrereseeseesssesessesses EBOX/2-63
PT Reference for Trap Instruction
EBOX/2-63
INTERRUPT CYCLE-INTRODUCTION ...
EBOX /2-63
Duration of Uninterruptable Intervals
EBOX/2-66
Interruptable Instructi
o
EBOX /2-66
General Interrupt Sequencing..........ooevveeveneeennnene..
EBOX /2-66
Interrupt Dialogue
EBOX/2-67
BASIC MACHINE MODES INTRODUCTION
EBOX/2-70
Mode Initialization ~ Private Instruction
EBOX/2-76
Loading Flags and Changing Mode
EBOX/2-76
User Public Mode.
.
EBOX/2-76
Entry from User Public Mode 1o User Concealed ................... EBOX/2-81
Concezled Violation Data Reference
EBOX/2-81
Restoration of Programs by the Supervisor
EBOX/2-81
Restoring a Concealed Program
EBOX/2-81
Restoring a Kernel Program
EBOX/2-85
Restoring a User Public Program
EBOX/2-85
Saving Flags and Leaving User
EBOX /2-86

UserC

led

ADDRESS PATHS
DATAPATHS ...ocecterereteteasesesce
Virtual Memory Address Register

EBOX/2-86

EBOX/2-88
setsmse s sssssens asssssens EBOX/2-92
EBOX/2-93

Program Counting
Loading PC

EBOX/2-93
EBOX/2-97

General Data Path Organization

2952

ADA Field

2953

EBOX/2-99
EBOX/2-100
EBOX /2-100
EBOX/2-107

ADB Field

2954
2955

AR Field
ARX Ficld
BRIl
BRX Field
FMADR Ficid
SCAD Field
SCADA Field
SCADB Field
SCField ...oor
SH Field
The AR Mixer Mixer (ARMM)

EBOX/2-107

2956
29517
2958
2959
295.10
295.11
295.12

29.5.13
295.14

General Data Path Mixer Selection
AD Field

..ot

EBOX/2-108
EBOX/2-111
EBOX/2-112
EBOX/2-112
EBOX/2-112
EBOX/2-112
EBOX/2-113
EBOX/2-113

EBOX/2-113
EBOX/2-114
EBOX72-114

MQFieid
..o,
EBOX/2-114
EBOX INSTRUCTION SET FUNCTIONAL OVERVIEW .............. EBOX/2-114
Effective Address Calculation
EBOX/2-119
Indexing ...

EBOX/2-120

No Indirection or Indexing

EBOX/2-128

Indirection

Fetch Cycle
Instructions That Do Not Reguire (E)
Instructions That Require (E)
Execution Cycle
EBox Data Store Cycle

EBOX/2-120
EBOX/2-125
EBOX/2-128
EBOX/2-131
EBOX/2-137

EBOX/2-141
Basic Four Mode Type Instructions...............cccocecereeeenecsan. EBOX/2-141
SKIP, JUMP Compare Instructions
EBOX/2-157
Store Cycle for Other Instructions
EBOX/2-158
INTERFACE CONTROL
EBOX/2-158

Introduction

MBOX CONLIOL.......oeieecrcen

EBOX/2-158

e ener e resssasescssee s eeepssasmstases EBOX/2-160
DATA FETCH REQUEST EN - Begin EBox Cycie ............ EBOX/2-163
Begin MBox Cycle - End Current EBox
Cycle and Start Next
EBOX/2-163
SETUP PREFETCH - Wait for MBox Response ................ EBOX/2-167
MBOX RESPONSE RECEIVED
EBOX/2-167
General Memory Cycle Control
EBOX/2-167
EBUS INTERFACE CONTROL
EBOX/2-167
EBus Signal Lines
EBOX/2-173
EBus Interface Organization
EBOX /2177
Interrupt Handling - Loading the Req
EBOX/2-177
Testing the Request
EBOX/2-177

Requesting the EBus
Beginning the Dialogue
Interlocks and Dislogue Completion
Basic Input Output Control
Requesting the EBus

Dialogue Overview
Functional Breakdown
PI and EBus to Microcode Interface

Sensing the Interrupt
Requesting the EBus
Beginning the Dialogue
Terminating the Dialogue
Entry to the PI Handler

E£BOX/2-177
EBOX/2-178
EBOX/2-178
EBOX/2-178
EBOX/2-178
EBOX/2-178
EBOX/2-182
EBOX/2-183

EBOX/2-183
EBOX/2-191
EBOX/2-191
EBOX/2-195
EBOX/2-195

CONTENTS (CONT)

Page

LOGIC DESCRIPTIONS

APPENDIX A

UNDERSTANDING THE MICROCODE

INSTRUCTION REGISTER LOADING ANDCONTROL ................. EBOX:3-2
DRAM and IRAC Control
EBOX/3-i10
DRAM Addressing and Selection
EBOC/3-1]
IR TEST SATISFIED..............
EBOX /3-13
INtroduction..........cooeeeceeeeeer e
EBOX /3-13

APPENDIX B

ABBREVIATIONS AND MNEMONICS

APPENDIX C

KL10-PV EBOX DIFFFRENCES

Implementation

EBOX/3-13

PROCESSOR TIMING
EBOX/3-20
Clock OVEIVIEW ........coonirerierectsee et cstsae e see e eeess e eae s sennas EBOX/3-20
Crobar and Clock Initialization
. . . . . . .c e ve men n. .
...EBOX/3-22
EBUS RESCL... .o
ceeae e neesnn et sas e ereee
EBOX/3-24
Initialization Clock Pulse Generation
EBOX/3-24
EBox Clock Control
EBOX/3-24
Error Detection
EBOX/3-27
Clock Control Logical and Skew Delays
EBOX/3-30
ARITHMETIC PROCESSOR FACILITY
EBOX/3-32

Introduction

EBOX/3-32

Address Break
EBOX/3.32
Address Break INH and Saving Flags..........c..coooooevinienenncl EBOX/3-38
Address Break INH and Loading Flags
EBOX/3-38
Arithmetic Processor Status Register......
EBOX/3-38

SBus Errors
Nonexistent Memory
Other External Errors
Input/Output Page Failure Error
Power Fail
SWEEP and SWEEP DONE
Processor Identification
Cache Refill RAM Facility
MBox Error Address Register
CONTROL RAM ADDRESSING
Pushdown Stack
Current Location Register (CRA LOC)......
Control RAM Dispatch Field
Miscellancous

EBOX/3-39
EBOX /343
EBOX 343
EBOX/3-44
EBOX /344
EBOX/3-47
EBOX/3-53
EBOX/3-54
EBOX/3-56
EBOX/3-57
EBOX /3-57
EBOX/3-62
EBOX /3-62
EBOX 7/3-62
EBOX /3-65
EBOX/3-65

CR Address Gates

Special
CR Address Modification Considerations.
CLK FORCE 1777

CONCONDADR 10. . . .oi ceve nerce nene
MUL DONE
AREAD Logic
CRA Dispatch Parity

neteenen EBOX/3-65
EBOX/3-65
EBOX /3-65
EBOX/3-69

C.d

INTRODUCGTION. ..ot
er et st e ve e ste e renaeEBOX/C-1

KL!10-PY EBOX MODULE UTILIZATION

Ci3

FUNCTIONAL DIFFERENCES............

Cii
C32
Ci3

C4
C4i

C42
C43
C43.
C432

Higher Clock Rate
Extended Addressing

EBOX/C-3
EBOX/C-3

New Instructions and Considerations
EXTENDED ADDRESSING ~ EFFECTIVE ADDRESS
CALCULATION
Instruction Format
Indexing
INQITECLION
c.ce eini iece e necrererecrnensene
Local Format Indirect Word
Global Format Indirect Word

EBOX/C-3

EBOX/C-5
EBOX/C-$

EBOX/C-5
EBOX/C-7
EBOX/C-7
EBOX/C-7

Ca4

Examples

C4s

immediate Instructions

EBOX/C-10

AC References

EBOX/C-10

C46

CS
C5.1
CS5.1.1

EBOX/C-8

NEW INSTRUCTIONS. INSTRUCTION MODIFICATIONS,
AND CONSIDERATIONS

EBOX/C-11
Speciai-Case Instructions in Nonzero Sections...........cceeveverrevveveas EBOX/C-11
PC-Storing Instructions
(PUSHJ, ISP, ISR, POPJ)

C5.1.2
€513

EBOX/C-11
EBOX/C-t

Byte Instructions
Stack Instructions
(PUSH, PUSHI, POP. POPJ, ADISP)
LUUO (Op Codes 1-37)

EBOX/C-12
EBOX/C-12

MUUO (Op Codes 0, 40-77,
Al Undefined Op Codes)
BLT
EXTEND-STRING Operations

EBOX/C-13
EBOX/C-14
EBOX/C-14

AOBIN
JSA JRA

EBOX/C-15
EBOX/C-15

CS5.1.10

BLKI.BLKO

EBOX/C-15

C5.1.11

XCT

C5.14
C5.1.8
C5.16
Cs5.1.7
Cs.1.8
Cs5.19

C52
Cs3
€531

EBOX/C-15

PI Handling
New Instructions..........
XMOVEI - Move Extended Address
{Op Code = SETMI)

EBOX/C-1
EBOX/C-3

vii

EBOX/C-15
EBOX/C-16
EBOX/C-16

CONTENTS (CONT)

FIGURES (CONT)

Page

C5.6.1
562
Cs5.7
Cé6
Cs6.1

Overview

EBOX/C-23

C6.2

Detailed Circuit Description

EBOX/C-23

C.6.2.1
Ce6.22
€623
C6.24

CROBAR and Ciock Initialization
EBOX/C-23
EBox Clock Control
EBOX/C-23
Error Detection
EBOX /C-27
Clock Control Logical and Skew Delays ..........c.ccccveiccvevennens EBOX/C-27

C?
C8
c9

MODULE M8540, SHIFT MATRIX
EBOX/C-28
MODULE M8541, CONTROL RAM ADDRESS
EBOX/C-28
MODULE M8542, VIRTUAL MEMORY ADDRESS........ccooroeeen EBOX/C-28

C.i0
C.11

MODULE M8543, EBOX CONTROL NO. I.....oovreerecerccmnnnccanrenes EBOX/C-28
MODULE M8544, MEMORY CONTROL
EBOX /C-33
MODULE M8545, APR
EBOX /C-33
MODULE M8548, 2K CONTROL RAM
.EBOX /C-33

C.12
C.13

FIGURES

Figure No.
1-1
-3
14
-5
1-6
1-7
1-8
1-9
1-10

Tite

Page

EBox Simplified Block Diagram
EBOX/1-3
Control Pyramid
EBOX/1-5
DRAM 1/0, JRST.
EBOX/1-5
DRAM Organizstion
EBOX/1-7
EBox RAM Structures, Interfaces, and Controls Block Diagram.............. EBOX/1-9
EBox Overail Block Diagram
EBOX/1-11
Instruction, Dispatch, and Control Formats
EBOX/1-15
Microprogram Main Loop
EBOX/1-17
Basic Fast Memory Structure ...
ie cr ecenriceceniescseimeconeinsn ans
EBOX/1-18
VMA Structure Simplified
EBOX/1-22

viii

1-28

e o e e

C5.S
Cs56

ghpsseey

Cs536
Cs54

290~

C535

Page

PC 4 T FUNCUON (et
nine et esen st srecesananesEBOX/1-23
MBox-VMA-EBUS Control Simplified
...EBOX/1-24
Page Table Access
EBOX/1-25
K1 Style Paging
EBOX/1-26
Physical Memory Address Format ...............
EBOX/1-27
Page Fault Overview
EBOX/1-27
KL Paging Layoul........coveceemeeniinvceicnicrinnens
EBOX/1-29
Page Mapping (Virtual to Physical)
EBOX/1-30
Typical Paging Path
EBOX/1-30
Immediate Section Pointer
EBOX/1-31
Shared Section Pointer
EBOX/1-32
Indirect Section Pointer
EBOX/1-32
Pointer Interpretation {(Normal Section Pointer; Shared).........c.cccvervansen EBOX/1-33
Pointer Interpretation (Indirect Section Pointer).
EBOX/1-34
Pointer Interpretation (Indirect Page Pointer)
EBOX/1-3§
Pointer Interpretation Flow Diagram
EBOX/1-36
KL Core Status Tables Updating Flow Diagram
EBOX/1-42
Basic Address Transiation
EBOX/1-44
Virtual Address Mapping, K110 Paging Mode
EBOX/1-45
Simulianeous interrupts
EBOX/1-47
Pl Dialogue Overview
EBOX/1-48
APl Word Format
EBOX /149
1/0 Instruction Dislogue Overview
EBOX /149
KL10 Register Interconnection Diagram
EBOX/1-51
Core and Fast Memory Information Flow.
EBOX/1-53
Loading ARX
EBOX/1-57

XJEN - Restore Flags and Program Counter
" and Dismiss (JRSTE.)......ooeeeeeerrereererene
e reeseee e anaas EBOX/C-17
XPCW - Save then Restore Flags and
Program Counter (JRST 7,)
reevvenenvrnneenrenn EBOX/C-17
XSFM - Save Flags in Memory (JRST 14.)....ccneecncneennennn EBOX/C-18
Compatibility Summary
EBOX /C-18
Testing for Section 0
EBOX/C-20
Old Instructions.
EBOX/C-20
JRSTF - Jump and Restore Flags
EBOX/C-20
JRSTX.E
EBOX/C-20
Special Considerations for ACs.
EBOX/C-20
M8526-YA CLOCK MODULE
EBOX/C-23

OrlCaeiae

C.53.3
C534

XBLT - Extended Block Transfer
(EXTEND
Op Code 020}
e
EBOX /C-16
XJRSTF - Restore Flags and Program Counter (JRSTS,)..... EBOX :/C-16

1D B0 B I I e e e e
bN
e

C5.3.2

Title

Figure No.

EBox Data Paths Simplified Paths Diagram
input/Output Priority Interrupt Information Flow
EBox Functional Block Diagram

EBOX/1-59
EBOX/1-63
EBOX/2-3

Primary Hardware Cycles
Microprogram Static States
Microprogram Halt Loop
Run-Hali-Continue Logic
Dispatch Path State Diagram
Basic Microprogram Address Control
CRAM Address Inputs Simplified
Wait State
MBox Wait and EBox Clock
MBox Weit on Prefetch from Fast Memory.
P1 40 + 2n Skip
M Program Modules
Startup and Stop Interface
Effective Address Manager
Data Fetch Manag
Dispatch Table Ficlds.

EBOX/2-5
EBOX/2-6
EBOX/2-7
EBOX/2-8
EBOX/2-9
EBOX/2-11
EBOX/2-12
EBOX/2-12
EBOX/2-13
EBOX/2-13
EBOX/2-17
EBOX/2-18
EBOX/2-19
EBOX/2-19
EBOX/2-20
EBOX/2-20

Executor

Data Store Manager
Page Fault Handler

EBOX/2-21

EBOX/2-22
EBOX/2-22

FIGURES (CONT)

Title

FIGURES (CONT)

Page

Input/Output Handler...........oviieiiiinieninai
e, EBOX2.23
Basic Machine Cycle Overview ........
EBOX2-24
KL 10 Processor Sequence of Operation
EBOX/2-27
Instruction Cycle: NICOND Dispatch - XCTGO
EBOX/2-33
Set Up and Make Indirect Work Request ...
EBOX/2-35
MBOX CYCIE
. oeiener r mrecsnaseres s sestese
nse as era
EBOX/2-38
MBox Response to Indirect Request
EBOX/2-39
Address Calculation Continues
EBOX /241
AREAD Dispatch Setup Data Feich
EBOX/2-43
MBox Response with Dats Word Requested
EBOX/2-47
Hardware Sciection of ARM Data
EBOX/2-49

2-65

Executor Setup for Store Cycle
EBOX/2-51
Finish Store Cycle, Perform NICOND Dispaich
EBOX /2-53
Page Fail Handling
EBOX/2-56
EBox Priorities
EBOX/2-58
Process Table PF Location
EBOX/2-59
Trap Cycle
EBOX /2-61
Central-Server Model (Round Robin Priorities)
EBOX/2-63
Interrupt Level Operations
EBOX/2-64
Typical Interrupt Priority Chain
EBOX/2-65
Basic Interrupt Sequencing
EBOX/2-67
Interrupt Dialogue Overview
.EBOX /2-68
Mode Structure and Hicrarchy.......
EBOX/2-T1
Mode Transfer
EBOX/2-73
Typical Virtual Address Space Configuration
EBOX/2-78
Mode Initialization
EBOX/2-77
Private Instruction Recirculation Path Simplified
EBOX/2-78
Setting Private Instruction
EBOX/2-78
User Mode Functional Flow
EBOX/2-79
User Mode Public Initial Reference
EBOX/2-80
User Mode Public Second Reference
EBOX /2-80
Typical Concealed Page Table Format (Half Tabie Entry)......ccceecvucneneand EBOX/2-81
Supervisor Mode Functional Flow
EBOX/2-83
Leaving User
EBOX/2-85
Restoring Kernal Program
EBOX /2-85
Mode Hierarchy
EBOX /2-87
Concealed Mode Functional Flow
EBOX/2-88
EBox Address Paths Simplified Path Diagram
EBOX/2-89
Typical VMA 13-17 Manipulations.
EBOX/2-91
EBox Data and Address Paths
EBOX/2-95
VMA Inputs
EBOX/2-97
Program Count Loop
EBCX/2-97
PC Loading or Inhibit
EBOX /2-98
ALU Overview
EBOX/2-102
ADA Example
EBOX/2-104
ADB Example
....EBOX/2-104
Function A
EBOX/2-105
Function AB
EBOX/2-106
Function AB
EBOX/2-106

Figure No.

2-70
2.1
21
2-713

Tide

Page

Function A ..o
e et
een e e EBOX /2. 107
AR Sclection ...
.
EBOX /2-109
ARX Selection .......
ettt
ere e e stene e e
....EBOX/2-111
MQ Selection
EBOX/2-115
Instruction Set Divisions ..........cccoocorievnrcevrncnricnerannenns
EBOX/2-117
Major Machine Cyche. ..o
EBOX/2-119
Basic Instruction FOIMat.............oocooeeececer
et veae eEBOX/2-119
In-Out Instruction Format
EBOX/2-119
Effective Address Cslculati
EBOX/2-121

Page Fault During Diverted Indirect Reference
EBOX/2-123
EBox Data Fetch
EBOX/2-124
Fetch Minor Cycle
EBOX/2-125
Address-Fetch-Execute-Siore General Memory References.................. EBOX/2-127
Execute-Register-MBox Control and Miscellaneous General
Memory References
.
EBOX/2-133
EBox Execution Cycle Overview
EBOX/2-139

2-9]
2.92
293
2-94
295

2-96
297

298
299
2-100
2-101
2-102
2-103
2-104
3

3.2
33
3.5
3.6
33
38
39
3-10

Microstack Operation
£Box Dats Store
M Box-EBox-EBus Control

EBOX/2-141
EBOX/2-142
EBOX/2-143

Basic Machine Cycle Summary
Subcycie Summary
Hardware Cycie Summary
Genceral Memory Request Control Simplified
Begin EBox Cycle Data Fetch Reg
EBox Request Fast or Slow
Basic EBox Clock Period
Begin MBox Cycle, End Current EBox Cycle,
Begin Next EBox Cycle
Setup Prefetch Waiting for MBox Response
Receive MBox Response, End Current MBox Cycle,
End Current EBox Cycle, Begin Next EBox Cycle,
Begin MBox Cycle
General Memory Cycle Control Flow
EBus Interface Functional Block Diagram
EBus Control Functions
EBox PI Board to Microcode Interface
EBus Control Hybrid Flow
Time State Generator Control
Pl Timing
EBox Module Utilization
IR DRAM Control (Part 1)
IR DRAM Control (Pan 2)
IR Loading Vis AR (COND/LOAD IR)
Loading IR Via FM (COND/LOAD IR)
DRAM Loading Following COND/LOAD IR
NICOND Dispatch and Waiting
1R Text Satisfied
IR Test Equal
IR Test Satisfied Logic

EBOX/2-159
EBOX/2-159
EBOX/2-160
EBOX/2-161
EBOX/2-164
EBOX/2-165
EBOX/2-165

EBOX /2-166
EBOX/2.168

EBOX/2-169
EBOX/2-171
EBOX/2-175
EBOX/2-179
EBOX/2-18S
EBOX/2-187
EBOX/2-191
EBOX/2-193
EBOX/3-3
EBOX/3-§
EBOX /3-7
EBOX/3-9
EBOX/3-10
EBOX/3-11
EBOX/3-12
EBOX/3-15
EBOX/3-17
EBOX/3-17

FIGURES (CONT)

Figure No.
311
312
3-13
3-14
115
3-16
3-17
3-18
319
321
322
3-23
324
3-25
3-26
3.27
3.28

3-30
33
3.32
3-33

Title

FIGURES (CONT)

Page

Basic Clock Module Layout and Distribution...........ccccooeineiene EBOX/3-21
Clock So
Simpl
EBOX/3.22
Basic Clock Block|Dugram
..EBOX/3-22
Basic Source Selection
-.EBOX/3.23
Free-Runming ClOCKS ..ot
e e
coeren e s s s FEBOX/3-23
Basic Rate Selection
. . . . . .c veremevevin nen n .
EBOX 73-23
Clock Initialization
EBOX/2.34
EBus Reset and Clock Initialization
EBOX/3-25
Power Up Timing
EBOX/3-26
Simplified Diagram, MBox Clock. Sync. EBox CP EBOX /3-26
EBox Cycle
EBOX/3-26
EBox Clock Control Block Diagram
EBOX/3-28
Basic MBox Cycle Timing
EBOX/3-28
Clock Error Stop
EBOX/3-29
Logical Delays and Skew
EBOX/3-30
EBox Ciock Fanout
EBOX /3-31
MBox Clock Fanout
EBOX/3-31
Clock Control, EBox Clock Control Timing
EBOX/3-33
Address Break Facility
EBOX/3-35
APR Register and Interrupt Enables
-.EBOX /341
APR Register Breakdown
EBOX/3-43
NXM Timing Overview
EBOX/3-44
NXM Error Overview
EBOX/34$
External Error Conditions (M Box, SBus)
EBOX/3-46
ERA Word
EBOX /3-46
SWEED LOBIC .ottt
ss e rer s sessasesessessre e ceene EBOX/3-49
APRID Format
EBOX/3-53
Alignment Step |
EBOX/3-54
Alignment Step 2
EBOX/3-54
Refill RAM Overview
....EBOX/3-55
CR Addressing Overview.
EBOC/3-59
Stack Operation EXample.............oveereeeeneeeeieeceeeereneeeeeeseeeveeeeeeeserens EBOX/3-61
CRADR Gaies
EBOX/3-63
Example CRADR 08-10
EBOX /3-64
COND and Dispatch Layout and Control...........co.ooeevvinicercmenereeenan EBOX/3-67
MUL Done
EBOX/3-69

Contro! RAM Addressing

EBOX /3.7

Sample Microcode Listing
EBOX/A-1
CRAM Board Logic Pbys:ul Bit Position Derivation.............................. EBOX/A-S
Actual CRAM Physical Bit Position to
Microword Bit Position Correlation
EBOX /A-7
MOVE Instruction Flow Diagram...........c..ccocevuvemmemvereeeeennn.
.EBOX/A-12

Figure No.
A-S
A-6

A-7

Title

Page

Microcode Address 52 ... ..t EBOX/A-13
Microcode Address 160 ..............cooeiiiiiiiiceir e
EBOX/A-13
DRAM Word200........
EBOX/A-13
Microcode Address 45..
EBOX/A-13
Microcode Address 100....
EBOX/A-13
Microcode Address 175 ... e
EBOX/A-14
ADD Instruction Flow Diagram ... EBOX/A-18
Microcode Address 160, 161.........
EBOX/A-16
DRAM Word 270 ...
e,
EBOX/A-16
Microcode Address
45
EBOX/A-16
Microcode Address 504 ...........
EBOX/A-16
Microcode Address 175..........ooooieii,
EBOX/A-16
Microword “s” Ficld
EBOX/A-16
Microword *b" Field
EBOX/A-17
Microword **¢” Field........cooevereruencirnnnc.
EBOX/A-17
Microword *dTM* Field
EBOX/A-18
Microword **¢* Field.
EBOX/A-18
Microword *'I Fieid
EBOX/A-19
Microword “'g" Field (Magic Numbers)
EBOX/A-20
DRAM Word Format
EBOX/A-23
KL10-PV Module Utilization
EBOX/C-2
Extended Addressing, Effective Address Calculation Flowchart ..............EBOX/C-6
Instruction Format
EBOX/C-7
Local Format Indirect Word
EBOX/C-7
Global Format Indirect Word
EBOX/C-7
Byte Pointer Format
EBOX/C-11
LUUO Information Format
EBOX/C-13
UUO Information Format
EBOX/C-13
EXTEND-STRING Instruction Format
EBOX/C-14
Flags and PC Double-Word Format
EBOX/C-16
XPCW Information Format
EBOX/C-17

Basic Source Selection
EBus Reset and Clock Initialization
EBox Clock Control Block Diagram
EBox Cycles
Clock Control, EBox Clock Contro! Timing
Module M8542
CRAM Physical Bit Position Layout
CRAM Microword Bit Position Layout

EBOX/C-24
EBOX/C-28
EBOX /C-26
EBOX/C-26
EBOX/C-29
EBOX /C-31
EBOX/C-34
EBOX/C-3%

Position Derivation
KL10-PV EBox CRAM Bit Moduie Layout Chart

EBOX/C-37
EBOX/C-39

KL10-PV EBox CRAM Module Physical Bit

xiii

TABLES

Title

Table No.

Page

AREAD

FM Selection
.EBOX ‘119
Memory Information FIOW ........covveiioeeciieeiensectee e
ceee e e e eeeeane EBOX/1-54
EBox Main Loop/1raditional Machine Cycle Comparison ..........c.cc..... EBOX 2.9
Error Stop Enables......
... cuiieeevireieiiceceneiee e
ceate e
.FBOX /2-14
INICOND PROTIES. .......cocreeecreiieieceatreeececrsee e eene e s ee e ate et cesaenaen EBOX/2-15

1-3
21
22
23
24

.....EBOX 1-14

Address Caleulation ........... ceooreicomiiviceieriecccee e

EBOX/2-31

2.5
26
27
28
2.9
210
211
212
213
2-14
215
216
217
2-18
219
220
2.21
2.22

MBox Cycle REQUESES ..o
Flags EfFcting MOGE
Virtual Address Classification
Dats and Address Path Breakdown
ALU Functions
.
ALU Functions With Carry

Skip, Jump, Compare Controls ..o
iaeveeerceeercna EBOX/3-17
Test Controls
.
EBOX/3-18
CONSX and BLKX Controls
EBOX/3-18
Fetch Control MOdifiers..........ooeocioenr
v
et creaescesne e EBOX/3-19
CRYO Generation (MACRO)
EBOX/3-19
Marker Generator FUNCUON......
..o
et ccen e cecssensenccnnacen EBOX /3-27
CCA Summary
...EBOX /347
Sample AlBOTIthm
...t EBOX/3-56
EBox Module Utilizstion Changes..................
EBOX/C-2

33t

34
35,
37

38
C-1
C-2

e cceenceeamre e e

EBOX 72-37
...cnoceeerecrnmecarnrenscnesesencensascrussorcescassasnsacses EBOX/2-78
EBOX /2-92
EBCX/2-99
EBOX/2-10%
EBOX/2-102
EBOX/2-107
EBOX /2-108
EBOX/2-112

ADA, ADXA Sclection
ADB, ADXB Selection
SCAD Field
SCADA Mixer Selection
....EBOX 72-113
SCADB Mixer Selection
EBOX/2-113
AREAD DISPaCh...
e cnrestnnonssnsne s asesen EBOX/2-126
Skip, Jump, Compare Instructions
EBOX/2-157
Request Summary
e EBOX7 2-160
Data Transfer Signals
EBOX 2173
Table Data Transfer Commands.............cccooocvoeen
EBOX/2-173
Priority Transfer Signals
Priority Transfer Commands

EBOX/2-174
EBOX/2-174

Compatibility SUMMATY ....oeer

et EBOX /C-18

xiv

PREFACE
This manual contains three leveis of EBox theory descriptions. The three levels are:
Overview ~ The overview identifies and introduces, in a simplificd fashion, the basic hardware and firmware organization of the EBox. The major clements are presented without

many details to provide a capsule view of the EBox structure.
Functional Description - This section describes the primary EBox function, which is to execute the KL10 instruction set and thus provide the specified functions, which generally
include the following:
Memory Reads and Writes
Internal Operations
EBus Operations

The functional description is the most comprehensive part of the EBox Theory. Here the
basic elements of the EBox are described in the context of how they implement the primary
EBox function.
Logic Description
- This section provides
a detailed logic description of each of the board
types that comprise the EBox. These descriptions are written to support the functional
description. The logic description section is the most detsiled part of the EBox. This matenial is presented to expand the functional description so that the information provided in the
functional description can be directly reiated to the engincering logic diagrams.

Appendix C has been added. which detsils the differences and changes that have been incorporated
into the Model B CPU EBox (called KL 10-PV EBox). Appendix C should be used in conjunction with
this document tc understand the KL10-PV EBox.

" SECTION 1
OVERVIEW

1.1 INTRODUCTION
The EBox is the instruction execution unit in the KL10 system. A central processor is formed when a
memory interface unit (MBox), 10-11 interface unit (DTE), and PDP-11/40 processor are interfaced
with the EBox. The MBox is the memory interface unit in the KL 10 system to which the EBox directs
its core memory requests. The PDP-11/40 is the front end processor that provides console functions
and bootsirapping facilities and drives the standard PDP-11 peripherais. The DTE is the interface
between the EBox and the PDP-11/40 console processor. The EBox communicates with the DTE, and
hence the console processor, over a 36-bit dats bus called the EBus, and uscs three function lines
(FOO-F02). seven controller select lines (CS00-06), and two additional signal lines (Demand and
Transfer) for arbitration and control of data transfers between the EBox snd its internal and external
devices. A pseudo-interface, which consists of a 23-bit address, 36-bit data, a number of request type
qualifiers, and additional signals (including request and response), provides for arbitration and control
of data transfers between the EBox and MBox.

The EBox contains the following (Figure 1-1):
1.

A data path that consists of an Arithmetic Register (AR), Arithmetic Register Extension
(ARX), Adder (AD), Adder Extension (ADX), various other registers, and s shift matrix.

An address path that consists of a 23-bit Program Counter (PC) and 23-bit Virtual Memory
Address register (VMA).

Eight fast register blocks, each containing 16 X 36-bit words: each block of 16 registers is
program-assignable.

A 13-bit Instruction Register (IR), which accepts the 9-bit operation code and 4-bit accumulator address.

Two somewhat autonomous control clements to provide control between the MBox and
EBox. as well as the EBus and EBox. These are the MBox control and EBus control, respectively (Figure 1-1),

A control section storing and aiding the implementation of KL 10 instructions.

EBOX/1-}
.

The control portion of the EBox comprises two Random Access Memories (RAMzs). The first is calied
the Dispatch RAM (DRAM); it consists of storage for 512 decimal words, one word for each KL 10
instruction. During instruction execution, the content of theDRAM word provides information about
the type of memory references required by the executing instruction. It slso provides an index into the
main control programs contained in & second control memory called the Control RAM (CRAM). The
CRAM consists of storage for 1280 microinstruction words that are structured into a sophisticated
control program. The main program consists of 8 main loop and a number of subroutines or handiers.
The structure provides for the implementation of s wide variety of internal register transfers, arithmetic and logical control, memory interface, and EBus control functions. The control program is generally
referred to as the “microcode.” Amocisted with the microcode and CRAM is & hardware pushdown
stack, which enables the control program to make subroutine calis up to four levels doep. while performing various KLIO instructions. The basic machine control flow may be viewed as a pyramid, as
shown in Figure i-2. The instruction initially enters the IR consisting of two sections. One section, bits
0-8, holds the op code of the instruction, and the other, bits $-12, holds the Accumulator (AC)
address. During the instsuction fetch cycle, the IR is unlatched via Load IR. During this time, it sets up
with the op code. When the fetch cycle terminates, Load IR is removed and the IR latches.
Because of the provision for prefetching, instructions may enter IR during the execution ofthe current
instruction. This implies that, for these cases, the information provided by IR for the currently executing instruction must be somchow saved, while aliowing IR to set up with the op code of the next
instruction. This is accomplished by selecting an appropriate word from the DRAM,

The op code contained in the IR is used to address & corresponding DRAM word, and a Next Instruction Condition (NICOND) unlziches the DRAM register during this time. Encoded in the DRAM
register ficlds (A, B, and J) is all information necessary for operand fetching, storing, and the microprogram executor jump address. Therefore, those instructions that prefetch an instruction do not
require the IR to be reliable beyond the point of loading the DRAM register.
Input/output (1/0) instructions never prefetch. The device select code and operation for these instructions are specified directly in the [R. This must be made available to the microcode 1/0 handler during
the instruction’s execution cycle.
A special case in DRAM addressing is concerned with the JRST instruction. Because the JRST
instruction encodes its JRST type in IR 9-12, these bits can be used directly as part of the DRAM
word for this instruction. Normally, the DRAM address is as shown in Figure 1-3.

Included in the EBox is the master clock, which provides a time base for system operztion. It distributes clock and sync pulses to the MBox, DTE, internal devices, system buses, and to the EBox
itsclf. All operations in the KL-based system are synchronized to the master clock, which runs a1 50
MHz. The master clock can be started, stopped, single stepped, and otherwise controlled by the console processor via the diagnostic control logic. This logic is distributed between the EBox and the
DTE. Besides controlling the master dock, the diagnostic control logic provides & means for monitoring processor status and diagnostic registers in both the EBox and the MBox. The master clock is
divided to supply a8 25 MHz clock to the MBox and a 6.25 MHz clock to the EBus and SBus.

EBOX/1-2

wns

SELECT LINES | CONTROL

cLocx

nsTR 00-12

clock

—

AC 1012 (SWEEP)

CONTROL

TiurR

mw|

70 8US (ERROR STATUS PAGE £k o STATUS

i
o

Joconmno_fcowreoc |mew

H-

cONTHOL femus cru | consmo fu0ATA

CON

ERROR CONDS.

cau

PROCESSOR

|SONTROL

fe—]

Ar)

opss
e

on e
|

DEV PG
=

Figure 1-1 EBox Simplifie¢ Block Diagram

EBOX/1-3

Figure 1-2

rre

Control Pyramid

RN, 1% DEvE
RAND. LR

T€T 1 INTERWAL

)

12 LI

IT DEVICE | f GuRt T e

[ SPSPLLLE
LI S I
QinEs » CRO

INSTRUS TGS

23¢
2%a

CT=ER M:i(RO

INSTRUC TS

FRpEvey

Figure I-3

DRAM 1/0, JRST

Figure 1-4 illustrates the organization of the DRAM. By sharing portions of the DRAM between
cven ‘odd instruction. the shared pieces become half the nonshared. Therefore, the A, B, and J7-10
portions consist of 10 X 512 words and the P, J4, J1-3 portions consist of § X 256 words. This saves
essentially S X 256 words of DRAM storage. In addition, for JRST DRAM COMMON, bit 4 is made
zero and DRAM J7-10 is replaced by IR 9-12, again yielding a savings. Here the savings is $ X 16
words of DRAM storage. The areas allocated by the DRAM are indicated in Figure 1-3.

The EBox clock is variable and controlled by the microcode. The EBox and MBox are composed of
emitter-coupled logic (ECL), while the DTE and external devices are composed of transistor-transistor
logic (TTL). These two forms of logic are not directly compatible so the EBus is interfaced to the DTE,
as well as external devices, via s special controllable logic-level shifter called the Transiaior. This is
siecred by the EBox and provides for both ECL to TTL transfer and TTL to ECL transfer.

EBOX/1.5

The normal program flow may be interrupted through the use of one of eight interrupt control lines
(P10-7). This allows the servicing of peripheral devices and controllers, as well as internal devices,
while executing the main program. The central processor contains six internal devices that are program
selectable via KL10 1/0 instructions. These devices are:

Priority Interrupt (PI)
Arithmetic Processor Status (APR)
Paging (PAG)
Cache Clearer (CCA)
Meter (MTR)
Timer (TIM)
Instructions, comprising a program, are maintainedin core and/or fast memory. These instructions
are fetched and executed by the EBox. The control program within the EBox evaluates ficlds of infor-

mation that are part of theinstruction curn:ndy being performed. Usingvarious registers, fast memo-

ry. and adders, together with the VMA register and associated logic, the control program calculstes an
cffective address; fetches any required operands; performs the instruction-dependent functions (e.g..
those functions specifiedin the op code); stores the generated results; snd fetches the next instruction.
The logical data path between the instruction itself and the MBox is formed by the AR and ARX,
together with various suxiliary registers, and the several adders contained on the Data Path Board
{EDP). The IR receives the op code and accumulator address (IRAC) effectively for each instruction,
while the ARX receives the entire instruction word consisting of the op code, accumulator address,
Indirect bit, and Index register address, as well as the initial address supplied with the instruction
referred 10 as the Y address. The control program contained within the DRAM passes through a welldefined *“loopTM consisting of microcode handlers, each of which performs a portion of the overall
instruction execution. These correspond closely with the traditional processor cycles of Instruction,
Address Calculation, Data Fetch, Execution, and Data Store with auxiliary cycles being Interrupt,
Page Fault, and Trap.

NOVNEWN
-

1.2 BASIC FUNCTIONAL BLOCKS
The seven basic EBox functional blocks (Figures 1-5 and 1-6) are:
Instruction Register-Dispatch-Main Control Store
Fast Memory
Address Path
Data Path
Request and MBox Control
EBus and PI Control
EBox Control Logic

EBOX/1-6

oo
R

OP CODE

”

AC FIELD

Iz
1R+ URST
~10 —=DRAM

10 —=DRAM
o|

1©

2
s

* OPCODE

00-08

ADR » SEE NOTE 1

Rooo

[\ 00D

Pwace

000

HALF

§ 00-07

ADR

[~ common [— common f—{ common

EVEN

HALF

EVEN

HALF

EVEN

HALF

I
o

ORAM REC

HALF

A
NOTE®

8
1

For 10 instructions 1he
ORAM ADDRESS is form

-0

[

follo

DRAM ADR 03-05 =—
y
ORAM ADR

06-08 =— 1R 10-12

x*For interncl devices IR 03-06+0, this mokes x « 7

For externe! device, IR 03-06

#0, this mokes x * IR 07-09
1018

Figure 14

DRAM Organization

EBOX/1-7

—

Zcontmon
o

Figure 15

EBox RAM Structures, Interfaces,

and Controls Block Diagram

EBOX/1-9

contea

f=cri

cioce

¥ -

i
ac mer
wox cate wwh 2.3
cara

eg 38

Cacre

o1 v
Conras

weor

oo,

[
T
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—

urewoo—

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siomenr

veren

wrn

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T

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e
on

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Roctor
VA
| ose 3

e
oseo7
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seost

i
Figure 16

’!—V

EBox Overall Block Diagram

EBOX/I1-11

1.2.1 Iastruction Register-Dispatch-Maia Control Store
The Instruction register is the center of all processor control. Instructions are fetched from Main
Memory or Fast Memory. The instruction enters ARX while the op code and AC address enter the
Instruction register. The op code (bits 00-08) is used to address & word in the DRAM that is unique for
cach instruction in the KL10 instruction set. This word contains three fields of information and a
parity bit. The Instruction, Dispatch, and Control formats are illustrated in Figure 1-7.
Because all instructions do not require the same types of data fetches, execution states, or data storage,

they are handled uniquely for each instruction or, in some cases, for each class of instruction.
The A field (0-2) of the DRAM generally specifies the data fetch requirements, if any, as well as
whether the next instruction in the sequence may be fetched early (prefetched). The B field (3-5)
generally specifies where (o store the results produced during execution; but in the case of Test, Skip,
Jump. and Compare instructions, it is used to determine whether to skip the next sequential instruction
or jump. The J field (14-23) is used to enter at the appropriate point in the Executor Microprogram
and is generzlly instruction-dependent.
Specific microroutines are used for each class ofinstruction. Amsociated with the DRAMis a register
that buffers the word selected for the instruction currently being performed. This register is loaded
soon after the instruction is placed in the Instruction register.
The microprogram is contained in a 1280 X 75-bit RAM called the CRAM. Both the DRAM and
CRAM are loaded when the KLIO system is powered up. This is accomplished by the PDP-11/40
processor vis the DTE and makes use of disgnostic control logic within the EBox. Associated with the
CRAM is a register
that buffers cach word or microinstruction read from the CRAM. This register is

called the Control register and its contents
are decoded to pmwdemlleonuol of the seven major
functional blocks describedin Subsection 1.2. in addition, the Microprogramis structured into what
might be called a main loop. This loop, which is passed through regularly, is illustrated
in Figure 1-8.

When an instruction is fetched, the op code
and sccumulator address are placed in the IR and the
entire instruction word is placed in one
of the Data Path registers
called the ARX. Movement from
one routine (or Aandler) in the microprogram 1o another is made via 8 microcode Dispatch function.
The Control register contains many fields that are used for different types of control. Two such fields
that are used to control this movement are Jump Address and Dispatch Field. The Dispardi fupction
enabics various hardware conditions to be coasidered
whea an instruction has been fetchea
and
cnables
the most important condition to prevail. Two such conditions that are illustrated in Figure 1-8
are Priority Interrupt Request Pending and Trap Request Pending. The hardware is arranged insuch a
{ashion that priority interrupts have highest priority, followed by traps; the current instruction has
fowest priority. The dispatch that takes the microprogram to the Process Instruction Block is catled the
NICOND and is given after a Fetch request for the next instruction. If no priority interrupts or traps
are pending. the microprogram enters the next block to calculste the effective address. Here the dispatchis called Effective Address Modification (EAM OD) and enabies the hardware to sampie indirect
ficld bit 13 of ARX together
with indexing field bits 14-17. The KL 10 instruction specification allows
multilevel indirect addressing with indexing st each level where indexing, if specified, is performed
first. The microprogram evaluates bits 14-17; if nonzero, the contents of bits 14-17 are used to accees
the specified 36-bit Index register. The right-most half
of the Index rogister (bits 18-35) is added
to the
Y ficid of the instruction
word (bits 18-35);
the right-most 18 bits of this result are used in the next step

of the cffective address calculation. Simultancously, the state of ARX bit 13 is tested and, if equal to s

1. s memory request is generated to the MBox control portion of the EBox. Each time a word is
fetched in this fashion
and has bit 13 equal 10 1, the same sequence occurs until finslly a word is
ferched with bit 13 equal to 0. Then, one more level of indexing may be specified and the result is the
effective address. At this time, the A READ dispatch is given
and the A ficid of the DRAM is evaluated 1o enable
a required operand to be fetched; if specified, a prefetch is also set up st this time.
Table 1-1 lists the A field codes and the specific function required.

EBOX/1-13

!
|

Table 1-1

AREAD

DRAMA 3-Bit Code

MEM/AREAD

DISP/AREAD

Immedute class instiuction. prefeich disabled.

DRAM J DISP

1
2

Immediate class instruction: preteich enahled.
Not used

DRAM J DISP
32

Writecheck the paging. prefeich disabled

4
s
[

Data read requised.: prefetch disabled.*
Data read required: prefeich enabled.*
Data read required as separate ¢vcle. also wnte~hedh the

44
£

paging: prefeich disabled.

7
*Thexe two cases are

Data read modify wnte required. prefeich disabled.
ished onls by digeiching to

aff:

de loxatwrs The mictinode entered 2t locatme

4% prefetct
o, that al 44 Soes not.

The next block is entered to perform the specific execution function or functions for the particular
instruction by the microprogram giving ¢ DRAM J dispatch. Remember that each instruction has its
own DRAM word with 2 unique Jump field specifying where to go for that instruction’s execution.
The execution is very complex and is described in detail elsewhere in this manual. Basically, it performs
all required arithmetic, logical, or other types of functions required, and may also, in some cases, fetch
additional operands as required. Upon completion of this portion of the microprogram, the next
instruction may be started, provided that no data storage is required. If storage is required, two basic
cases must be considered. Those instructions that do not know where to store their data utilize the B
ficld of the DRAM as an index into the final block to store results. After storing results, the next
instruction is fetched and 2 NICOND dispaich is issued. Instructions that know where 10 go specifically in order 1o store their data do so by jumping to a specific Jocation in the microprogram, but may use
the B field of the DRAM to decode additional types of memory requests as required. This completes
the basic loop.
122 Fast Memory
An instruction word has only one 18-bit address field for addressing any location throughout afl of
memory. Most instructions, however, have two 4-bit fields for addressing the first 16 locations of
memory. These 16 locations consist of a set of 16 general-purpose, high-speed integrated circuit registers grouped locally into eight physical blocks, which arc softwarc-assignable by block. Non-1/0
instructions have an sccumulator address field that can address one of these 16 locations as an accumulator. Every instruction has 2 4-bit Index register address field that can address 15 ofthese locations
for use as Index registers in modifying the 18-bit memory address. (A zero Index register address
specifies no indexing.) The factor thst determines whether one of the first 16 locrtions in memory isan
accumulator or an Index register is not the information it contains, nor how its contents are used, but
rather how the Jocation is addressed. The eight blocks of fast memory are contained physically on the
data path board within the EBox. This allows much quicker acceas to these locations whether they are
addressed as accumulators, Index registers, or ordinary memory locations. They can even be addressed
from the program counter, gaining faster exccution for a short but ofien repeated subroutine. Of the
eight blocks contained within the EBox, block 7 is permanently assigned to the microcode. Referring
to Figure 1-9, the monitor uses an assigned AC block in the same way that a user program described in
the following paragraphs would. The microcode uses the assigned AC block when executing compiex
instruction algorithms. From the remaining blocks (0-6), two can be assigned under program control
(DATAO PAG) as the current and previous context AC blocks. The current context AC biock is used
by the user program for indexing in effective address calculation and for general storage as specified by
the AC field of the instruction and/or by the effective virtual sddress (location 0-17).

EBOX/1-14

INSTRUCTION

VETCe

STORE ) E

DIPATCn A

/e
[

can

30 %

A ar 4y

scaon [ jmaos

as s

SR AT R

iSA A

Svnc ot

ELY

ey e er
|

wewmw

]

rore
owwe

VA4

Vot ek
o

sy
Fie il

vyl
%

ety

Facks
As
R

Figure
-7 Instruction, Dispatch,

and Control Formats

ElOX/I-IS.

1040 wSTRUCTION wORD
At meas e

T
[ExTac

i
.«

TCer

cawie

aman

i K
I
|

Figure 1-8

Microprogram Main Loop

EBOX/1-17

Table 1-2

FM ADR Field -[
3]
]

I
1

KM Selection

FM ADR 10.4.2.1 Source

FM ADR BLK 4. 2.1 Source

Current Blwk

AL +]

ARN 14 17

[

VM4 3T

[

CRAM =05 Ox

Curtem Block

XR Block®

VMA Blewck®

AL +?

Current Bloch

]

Current Binch

AC 44

“DNaw may wiect esther the current of presmsus AC

Current Bhwdk
CRAM =02

bl
b addiiw

The selection of AC, AC+§, AC+2, and AC+3 is & function of the class of KL10 instruction being
performed. All non 10 instructions specify an accumuistor address in the instruction word, bits 9-12.

Figure 1-9

Basic Fast Memory Structure

The previous context AC block is used by the monitor to aliow the monitor to reference the previous
user's address space to pass arguments, data, or status information between the user program and the
monitor. This is normally done when the user program executes a monitor call for some type of
SCTVICE.

The microprogram running within the CRAM may select eight possible sources to be the word address
for fast memory; these sources are indicated on the figure as follows:
AC
AC+I
AC+2
AC+3
AC+4
ARX 14 - 17
VMA 32 -35

CRAM 05 - 08
The sclection of the sppropriate source is a function of the 3-bit microinstruction FM ADR FIELD.
The block 1o be used is selected by the same FM ADR FIELD 2nd corresponds to three block sources
as indicated in Table 1-2.

EBOX/1-18

The iogical mstructions - Logical Shift Combined (LSHC) and Rotate Combined (ROTC) - specify
the use of both AC and AC+1. Similarly, itbe fixed-point arithmetic instructions Multiply (MUL),
Divide (D1V), and Arithmetic Shift Combined (ASHC) specify use of AC and AC+1. The double
integer arithmetic instructions Double Add (DADD), Double Subtract (DSUB), Double Multiply
(DMULY), and Double Divide (DDIV) specify use of AC, AC+1, AC+2, and AC+3. As pointed out
previously. the microprogram is permanently assigned AC block 7 for its own use. During extended
instruction processing, the microprogram addresses words
in AC block 7 by using magic number field
bits 05-08, while selecting AC block ? with magic number ficld bits 02-04. These ACs provide temporary working storage for the microprogram. Similarly, the microprogram addresses AC+4 by combining the AC address taken from IR AC9-2 with bits of the magic number field in an adder network
to produce AC+4
For selection of AC, AC+1, AC+2, AC+3, or AC+4, the current block is always used. Whenever a
main memory reference
is made, the microcode references
the fast memory locstion given by VMA
32-35, enabling the hardware 10 switch the reference to fast memory, if necessary. When the instruction’s effective address is calculated, the microprogram aliows the specified Index register wo be
addressed in fast memory by ensbling ARX 14-17 to address the word. For both cases, i.c., VMA
32-35 or ARX 14-17 sddressing fast memory, the AC block may be either the current block or the
previous block, but is a function of the context of the instruction.
If an executive XCT is performed in response to 8 user's call (MUUO), then the previous physical
block and current physicsi block will be made to be different unless the operating system saves the
user’s current AC block and then wishes to use the same block once again, which is unlikely. As an
example, assume the user is assigned AC block 1; his previous AC block would initially be | aiso.
If the
user then performs an MUUO, the executive subroutine entered may safely load the curreat AC block
with some other block number and the previous user block wiil remain unchanged. The operating

system may perform an executive XCT utilizing the user's previous block and an AC within that block.
The hardware cuables the sclection at the time of the previous block for indexing. In addition, the
operating system may also reference the user’'s AC block (previous context block | in the example)
from the VMA_ In this case (referring to Figure 1-9), mixer selection 3 is enabled and the microword
FM ADR ficid specifies VMA.
During normal instruction processing, if VMA bits 13-31 are equal to 0, the address in bits 32-3Sisan
FM address.

EBOX/1-19

Some examples using the current AC block in various selections are given below. Assume the following
is performed by the operating system:

EXAC =1

This will detanlt 1o | xed block

HRLES EXAC. 102200

JYoad Mt cunent Bih=2

0. AC=]

Previous B =2

DATAO PAG.FXAC

Jaad the curtent BIL= = 2 and the
Previeus Bh== 2

JRST 2 ¢« USRPOWD

Pick up user mande. flaps. and
arn on aset

The following codes are for the user;
ACT =]

Tlus wall be 1n BIk=2

AC2 =2

.Ths will be 1n Bik=2

MOVEL AC1. 777777

The word 0.777277 te AC'L

HRLEM ACT, AC2

The word 777777777777 10 AL

SETCMM. AC1

The one’s comp of the word i ACT to AC2

which 1 equal 10 7777770
PUSH ACT, 3ACD)

This mstruction attempts o

push the contents ot ACZ inte
Jocation ACE. 1t will cause PDOVE

and this generates

TRAP=2

in the example, the symbol EXAC is defined as the number 1. Assume, for this example. that EXAC is
referenced as an AC accumulator in executive block 0. The first use of EXAC is in the instruction
HRLEI EXAC, 102200. This instruction takes the number in the Y field of the instruction, which, in
this example, is the eflective address, and places it in the left half of EXAC (which is executive AC1),
with the sign of the right haif of the word 0.102200 extended in the right half of EXAC. In this
instruction, the current AC is referenced in bits 9-12 of the instruction, and the mixer selection is 0. To
load the user AC blocks, both current and previous, it is necessary now for the executive to perform
the indicated DATAQ PAG instruction.

The left half-word in EXAC contains the necessary bits to enable the loading of the current and
previous blocks (EBus bits 6, 7, and 8 for the current block &nd bits 9, 10, and 11 for the previous
block). Next, we assume location USRPCWD contains the appropriate bit configuration to start the
user for whom we loaded the AC biock numbers. The instruction JRST 2, @ USRPCWD makes an
indirect reference 10 location USRPCWD. The resulting word will then contain the user mode bit (bit
5). possibly the public mode bit (bit 7), any other relevant flags in the remaining left half-word, and the
user virtual address in the right half-word. The user has defined the symbols ACI and AC2 as having
the values | and 2, respectively. As indicated in this example, these correspond to ACl and AC2 in
block number 2. The first instruction performed by the user is MOVEI ACI, 777777, which places the
number 0,777777 in accumuiator 1. On the next instruction, the word in AC1 as addressed by instruction field bits 9-12 is read out. Remember that during the effective address calculation, the AC number
is loaded from ARX 9-12 into register AC in the EBox.

EBOX/1-20

The FM ADR ficld of the microword that is performing the fast memory reference will specify a field
function of 0. which will select the current block as weli as register AC which, as pointed out, contains
the value of AC 1 (1). The operation, specified by the instruction, is to take the right half of AC1 and
store it into the left half of AC2 with its sign extended into the other half-word. Because the sign of the
right half-word in AC1 is negative, the result is the word 777777,777777. Notice that we must now
relerence AC block 2, location 2, by using VMA bits 32-35. This operation is specified with a different
microcontrol word and at a different time than the fetch of the word from AC1. Actually, the content
of AC1 is obtained by performing a READ: the word T77777,777777 is stored into AC2 on B WRITE.
The next instruction, SETCMM, reads the word from AC1 as addressed by VMA, takes the I's complement of it, and stores the result (777777,0) back into AC) again as addressed using VMA. Thus, the
same sddress is used for read as well as write. Finally, the PUSH instruction performs an indexing
function using the current AC block. The number 3, which is the Y field in the instruction, is added to
the number contained in AC2, as addressed in the example. using the mixer selection of 2 (XR).
Thus, the address is taken from ARX 14-17 during the effective address calculation. The number 3 is
added to the number 777777,777777 and the right half of the result (2) is used as the effective address.
Then the instruction attempts to push the aumber 777777,777777 onto the stack as addressed by the
updated right half of the word in ACI. The updating takes place first. The word is fetched from AC}
using the curreni block and the address in the EBox register AC. Then, this word has +1 added to both
haives and, if the left word is such that the sddition causes a carry from bit 0, & pushdown list overflow
trap occurs.

1.2.3 Address Path
The EBox performs a program by executing instructions retrieved from jocations addressed by the PC,
a 23-bit register contained in the EBox dats path. At the beginning of cach instruction, PC is
incremented by one so that it normally contains an address one greater than the current instruction.
Sequential program flow is altered by changing the contents of PC, either by incrementing it an extra
time
as in a Skip instruction, or by replacing its contents with the value specified by a Jump instruction. Instructions may be fetched either from core memory, which is external to the EBox, or from fast
memory, which is internal to the EBox.

Generally, instructions provide at least two operand addresses to the EBox. One address is that of an
internal sccumulator, and is addressed by bits 9-12 of the instruction. The other address, also supplied
by the instruction, may be used to address either core or fast memory and is contained in bits 13-35 of
the instruction word. This is a composite address, such that bit 13 specifics the type of addressing, i.e.,
direct or indirect; bits 14-17 specify an index register for use in address modification; and bits 18-35
address a virtual memory location.
Because the PC is used to keep track of where in the program the EBox is executing instructions,
an
additional register is provided to handle addresses that can be generated during effective address
calculations, during operand reads and/or writes, and at other times. This 23-bit register, also contained in the EBox data path, is calied the VMA register.
Figure 1-10 illusirates the basic path connections from the PC and AD. A control field consisting of
two bits in the microinstruction is provided to select the source of input to VMA. This ficld is called
the “VMA field.” In addition, two other fields are used 1o provide alternate input to the VMA as well
as provide the ability to increment or decrement the VMA directly. These ficlds, also a part of the
microinstruction word, are called the “condition field” and “magic number ficld.”
Referring to Figure 1-10, to load the VMA from AD, the microinstruction VMA field is coded symbolicaily as “*VMA/AD.” The field format is indicated at the lower right of the figure. The AD is
enabled into the input of the VMA register by the function VMA «~ AD, and the input to VMA is
enabled for any of the followine junctions: VMA ~ PC, VMA « PC+1, or VMA ~ AD.

EBOX/1-21

Similarly, to update the PC (Figure 1-11), the microinstruction VMA field is coded to specify the

function "VMA /PC+1." This disables VMA — AD, and 30 the VMA defauits to VMA « VMA AD a3
input. At this time, the COND ficld must not be VMA « § if it is desired 1o enable the VMA AD to
impiement the function A+B. The A input to VMA AD
is from PC bits 13-35. The B input is forced to

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+1if- PC+1 INH is true, and if the VMA field specifies the function “VMA/PC+1."
The input to
VMA is cnabled for PC+1 as well. Certain instructions such as JUMPXX, AGJXX, or SOJXX conditionally load VMA with either E or PC+1. Instructions such ss SKIPXX, TEST, CAIXX, and
CAMXX conditionally skip an instruction, so VMA may be loaded with cither PC+1 or PC+2. In
general. the VMA is loaded with PC+1 for most instructions by the microinstruction following the
cffective address calculation (sssuming no special instructions and not loading VM
A from AD). Those
instructions that perform an instruction prefetch will enable the VMA from PC+1 on the A READ
dispatch function. This function is used to trigger the Fetch cycle and, conditionally, the microprogram enters the wait state until the operand srrives when the data is fetched from the M Box. If this
is the case. and the prefetch condition is truc. the VMA input will be PC+ 1; when the M Box responds,
restarting the EBox clock, the VMA loads with PC+1.

weoroarezr-ys

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DLTREMEIN?

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Instructions such as MOVEI, ADDI, SUBL, and HXXXI fetch no operands during A READ: instead,
they use the effective address as data. These instructions prefetch the next instruction and the micro-

program does not enter the wait state at all. Thus, the VMA is loaded with PC+1 as the microprogram

passcs through A READ dispatch.

ENABLE G'vES PCet ¢
OR & COVENAT:ON OF 1

oMA,

LOAD

vMA AD

SPECIAL CONDIT:ONS
|

’

TWiSC

conps”

LTVMA = 4D hi2

;

The function VMA
+1 is used by such instructions as double MOVE, JSA. and JSR. Here, the micro-

instruction VMA field is not used, but the function VMA +1 is enabled by the condition field coded as
COND/VMA INC. The VMA register itself contsins logic for the incrementation. Similarly, the
function VMA - | is used by bytc and ADJBP instructions in cases where & word must be fetched from
E - 1. Once again, the VMA field is not used; instead, the condition field is coded COND/VMA DEC.

A e—
AD

Tus

@ AND MISCELLANEQUS |

N ey

;

This is also a VMA built-in function.

—

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o

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Figure 1-10

VMA Structure Simplified

(Ses nores

CAMA AD

.
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VMR

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ok roemay Fa 30 3CEPY T e Yioceing

T AIIOND

eaponn

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Figure 1-11

EBOX/1-22

PC + I Function

EBOX/1-23

R
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INFLT

The special number, magic number, and miscellaneous conditions shown on VMA AD in Figure 1-10

1.2.4.1 Kl Style Paging - For each MBox request iavolving a virtual address translation, the MBox
must verify that the virtual address is legal. In general, the physical page must be in core for a read and
be writable for a write. In addition, the address space to which it belongs must correspond to that
being referenced. i.c., a public program cannot read or write into a private address space.

are used during LUUQ, MUUO, and Pl handling to gencrate a range of special addresses 1o reference
the user or executive process tables in memory. During these types of functions, the VMA AD is
controlled by VMA §, which enables the Boolean function “B.” MVA AD B input bits 27-35 are
manipulated, while bits 18-26 are clcared; this aliows for the generation of process table word addresses in the range of 000-777. Note, however, that addresses in the range of 40-510 only are currently
generated by hardware,
<

Two styles of paging are implemented: the first is patterned after the K110 processor's memory management scheme: the second after the KL10 style.

1.2.4 Request and MBox Coatrol
In general, most of the EBox memory request type operations are controlled by the 4-bit MEM field in
the microinstruction (Figure 1-12). This may be used alone or with the DRAM A or B field values for
most reads and writes. In addition. the 5-bit special microinstruction field (SPEC) can spexify a function SP MEM CYCLE, which is sometimes used with the magic number field (a 9-bit microinstruction
ficld) to modify MBox read and write operations, e.g., for MUUO or LUUO. Note that the basic
MBox activity involves a request, 8 virtual address, and M Box qualifiers consisting of a multitude of
control signals that qualify the type of request being made. This is foliowed by:

The MBox contains two base registers that can be loaded via the EBox. These registers are used as the
base address of core page tables during virtual memory address transiation. The base registers are 13
bits wide. The User Base Register (UBR) is loaded by performing s privileged 170 instruction
(DATAO PAG). similarly, the Executive Base Register (EBR) is loaded by performing another privileged 1/0 Instruction (CONG PAG). These registers are normaily loaded by the operating system st
predetermined times. For example, the EBR is normally loaded once when the operating system is
bootstrapped. Also, each time a user is started in a normal multiprogramming environment, i.c., more
than one user program resident in core memory, the UBR is reloaded to point at the User Page Table.

1.
2.
3.

A response from the MBox with the data when the request is successful,
PF HOLD foliowed by MBox response IN and no data on a page fault, or
MBox response IN with data followed by MB PAR ERR, for an MB parity error condition.

Additional conditions are covered elsewhere in this manual.

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EBOX/1-24

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Figure 1-13

Page Table Access

Each time the EBox makes 3 memory reference 10 the MBox (Figure 1-13), the MBox evaluates the
virtual address. The details of this operation can be found in the M Box chapter of the KL/0 Theory of
Operation Manual. Basically, the page number supplied in VMA 18-26 is used as an index into a
hardware page table within the MBox. The MBox looks for the referenced page in this table. If it is not
found, the MBox uses the appropriate base register (UBR or EBR) with the virtual page number
supplied in VMA to form a 22-bit physical memory address, as indicated.

N
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Figure 1-12

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The appropriate entry is obtained and then written by the MBox into a hardware page table within the
MBox. (Actually. cight haif-word entries are fetched at a time, but for this level of explanation, only
one is considered.)

EBOX/1-28

The five bits A, P, W, S, C (generally called use bits or page descriptor bits) are tested against the
qualificrs sent by the EBox during the reference. Then the M Box, using the physical address. looks in
the cache for the word requested. If it does not find the word., it concatenates the physical page address
-{Figure 1-14) with the virtual word address provided in VM
A bits 27-35 and makes a second physical
memory reference. This address is indicated in Figure 1-15.

vSER

CoawA

Figure 1-15

BASE

Physical Memory Address Format

QEG
S TER

NOTE

LSER PROCESS

EXTCOTWE

A quadword is a block of fowr comtiguous words
whose sddrem differs only ia the two least significant

Bast

bits.

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In practice. address bits 14-33 specify a 4-word block called a guadword: bits 34 and 3§ specify which

word within that quadword is required by the EBox, or is being written by the EBox.
Once the address
translation process has been succeasfully completed for & virtual page, subsequent
references to that
same page causc the M Box to fill in the corresponding words
in the cache within the M Box. Each time
a reference finds
a valid word in the cache during a read, it is placed on the EBox cache data lines and
MBox response
is issued. Page faults occur as follows: For the initial reference,
the MBox looks
in the
hardware page table in the MBox, does not find the physical page sddress. and performs
the subsequent process table reference (refill cycie) for the haif-word containing the use
bits and physical page
address. Then, upon receiving the eight half-word entries from core memory, the MBox finds
the
access bit tumned off, i.c., 0: then a page fault is generated. The eight half-words are always written
in
*‘re MBox hardware page table (directory) whether or not the access bit in the associated word is
on.

However, when the access bit for the associated word is off, the MBox asserts PAGE FAIL HOLD.
The MBox loads an internal register (EBus register) with & page fail status word that describes the
type
of fault and also contains information about the user's virtual address. Referring to Figure 1-16, the
EBox detects the PAGE FAIL HOLD level from the MBox, and forces the CRAM address logic
to
CRAM location 1777. Here the page fault handler is entered. It performs the indicated functions
(Figure 1-16), and enters an Executive routine to handie the fault.

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EBOX/1-27

ane

In addition, the MBox asserts MB PARITY ERR five MBox ticks after issuing MBOX RESPONSE
IN., This sets APR MB PAR ERR, which causes an interrupt. The remaining errors set appropriate
APR error flags and likewise cause interrupts on the assigned APR interrupt channel.

1.2.4.2

USE
R BASTE REGISTER

KL Paging - The KL paging facilities suppornt sophisticated operating system features such as

efficient program working set management and demand paging, and extensive shanng of data and
programs on s page-by-page basis. Much of the paging mechanism is implemented by the KL microcode, rather than just specific hardware. This combination of microcode and hardware is referred 1o as
the KL 10 pager of TOPS-20 paging.

Refer to Figure 1-17. Each user’s virtual address space comprises 32 equal sections of 256K words per
section (512 pages of 512 words per page). A section is represented by one of 32 section pomters
located in the User Process Table (UPT). For EXEC sections, the 32 section pointers are in the EXEC
Process Table (EPT). The monitor can divide the EXEC address space into “'per-processTM and *perjobTM arcas through the use of indirect pointers; no such division is built into the Pager.

UBIA PROCESS TABLE

PAGE TASLE

PRIVATL PAGE

PP
PRIVATE

==
:

=)
l THARID PAGES TAN ¢

PAGE TARE

A section pointer eventually addresses s page table that represents all pages in a 256K virtual address
space. The section pointer may be Immediate, Shared, or Indirect, but must yield a physical address of
a page table that represents all pages of the section.
The page pointer is divided into three sections: Type Code, Access Bits, and Storage. Figure 1-18
illustrates the basic page pointer format and Figure 1-19 shows the sequence of steps in its
interpretation:

A virtual memory reference addresses 3 section pointer in the UPT or EPT for EXEC
operation.

The section pointer is used to fetch an entry from the SPT (this is a pointer 10 a page table).

The SPT entry points to a location within a page table representing $12 pages by one page
pointer for cach page.

HARLD PAOE

PRIVATE PAGE

1+ MOIRECTY
wr

The page table holds the physical page number required to complete the virtual to physical
address mapping.

These steps describe the most elementary and immediate reference type. The complexity of other
reference types requires a discussion of pointer types.
Page Pointers - The pointer type is encoded in bits 0-2 of the page pointer word (Figure 1-18). Again

the pointer types are:

w20

Code

Fuaction

0
I
2
2

No Access
Immediate or Private
Shared
Indirect

4-7

Figure 1-17

KL Paging Layout

Not Used (reserved)

EBOX/1-28

EBOX/1-29

STORAGE ADDAIES®
(MIMEDIATE POMTER ONL Y3

[T [ Loeme]

CO0E

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PAGE IN MEMORY

1822 - MUST BL 2ER0

MMALOIATE

PAGE NOT 1N CORE

121240

Z SHMARLD
RESERVED INOY USED)

TS
13 W MAY

8Ff

The Indirect Pointer (Figure 1-22) identifies both another page table and a new pointer within the page
table. This allows onc page to be exactly equivalent to another page in a separate address space. The

STORAGE ADDRESS
stews wah &
oy © o the ha possten’
*

(SPT). The SPT Base Register (SBR: reserved AC block) points to the beginning of the SPT. The sum

URD YO

HOLD OIBK O OTHER BACKUP

L
0221

The Shared Pointer (Figure 1-21) contains an index that addresses into the Special/Shared Pages Table
of the SPT index and the SBR points to a word contsining the storage address of the desired page. The
word number from the virtual address is used to complete the reference. Regardless of the number of
page tables holding a particular shared pointer, the physical address is recorded only once in the SPT.
Therefore. the monitor can move the page with only one address 1o update.

I3 PHVYSICAL PAGE NO

0 MO ACCESS

!
32100

CODE

The Immediate Pointer (Figure 1-20) holds a storage address in bits 12-35. The pointer is called &
private pointer because it is “'privateTM to the particuiar page tabic containing the pointer. This should
not be confused with the Public bit, which describes the type of access aliowed.

object page is locatsd by using the SPT index.

rosLc
Noloronas
pnly trom the

Like a Shared Pointer, the SPT index in the Indirect Pointer allows the physical address of the page
table to be stored in just one place. if the associated page is in memory, the page number ficld of the
Indirect Pointer is used to select a new pointer word from the page table. This pointer can be any one
of three types previously described, or no access and the access bits are ANDed with the access bits of
the Indirect Pointer.

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8

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The Indirect chaining may be arbitrary in depth, but the Pl will break out of indirect chain and restart
afier the Pl to service & priority interrupt in the case of long direct chains or indirect loops.

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e amrs

Figure 1-18

Page Mapping (Virtual to Physical)

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-1

fUSEM PROCESS TARLE)

PAGES TABLES

PAGE

POINTER

DATA PAGE

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PAGE TABLE ADORESS

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¢

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POINTER

Some examples (Figures 1-23 through 1-25) of pointer interpretation follow: a fiow chart (Figure 1-26)
s provided to aid in working through the examples.

Typical Paging Path

wwe
the Castn

NOTIL

Outum e Page Tate Addren

SIT3 12 M CONTAW A “STORAGE ADDRESE"

Figure 1-20

EBOX/1-30

Whon omt sBpws Sags A5R0 W0 e oMot

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Immediate Section Pointer

EBOX/1-31

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Figure 1-22

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Figure 1-21

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Figure 1-23

Pointer Interpretation (Normal Section Pointer; Shared)

Indirect Section Pointer

EBOX/1-32

EBOX/1-33

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EBOX/1-34

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Figure 1-24

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Figure 1-25

SEPISE.

Pointer Interpretation (Indirect Page Pointer)

EBOX/1-35

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Figure 1-26

Pointer Interpretation Flow Diagram (Sheet 1 of §)

EBOX/1-36

Figure 126

Pointer Interpretation Flow Diagram (Sheet 2 of 5)

EBOX/1-37

PIPAGE
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Figure 1-26

Pointer Interpretation Flow Diagram (Sheet 3 of 5)

EBOX/1-38

Figure 1-26

Pointer Interpretation Flow Diagram (Sheet
4 of 5)

EBOX/1-39

Specisl/Shared Pages Table (SPT) - The Special/Shared Pages Table (SPT) contains the physical
addresses of pages that are shared by many page tables. or of pages used in a special way, i.c., as page
tables. They are stored in one common location to aliow modification to the pages by changing a single
entry. The SPT index is added to the STP base address to form a physical address of the associated
entry.

]

Core States Table (CST) - Virtual memory management requires information about memory references generated by each user’s processes. Adding the Core Status Table (CST) base register to the
physical page number from a storage address permits the monitor to address and update information
regarding the page reference. Figure 1-27 shows the flow of updating using a CST entry. This enables
pages to be ordered by “age” (time of last reference) and classified by the type of process referencing
the page.

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The reference indication is carried by assigning one bit to each sctive process. By placing a 1 in that bit
positon in the pager data word, then, when a reference is made, the 1 is placed in the CST word in the
bit position assigned to the process making reference. The modified bit (35) is set if the page is modified. permitting the monitor to avoid swapping out of pages to which only read references are made.

Paging Hardware Support — The paging hardware is transparent to the user. All memory, both virtual
and physical in user and monitor space, is divided into pages.
The virtual address comprises 23 bits, five (5) bits for section numbers, nine (9) bits for virtual page
numbers, and nine (9) low-order bits (line number), which address the location within the page. The
virtual page number is first usd as an index into s hardware page table that contains up to 512 direct
virtual-to-physical address transiations. If the 13-bit physical address is found in the hardware page
table, a 22-bit physical sddress is formed by concatenating the 13-bit physical address with the 3-bit
line nuinber. If the entry does not exist in the hardware page table, & sequence of translations is
initiated (o locate a page table in memory that contains a physical address (if one exists) for the virtual
page.

Cached Paging Data - The hardware page table referred t0 st the beginning of this section is effectively
a cache
of paging dats (not to be confused with the memory data cache) that has been sccumuiated by
previously feiching the data from memory, or by previous poinier interpretation. A virtual address is
first checked against the current contents of this hardware pager and, if found, immediately returns &
physical address. If the physical address is not found, the pointer interpretation (Figure 1-26) fetches
informstion from memory to resolve the virtual address. Upon completion, this transiation may be
placed in the hardware page table forming the cache of recently used page sddresses.

AR V CSTDATA

STORE

!
PWSEC PAGE NO
PAGING CACHE

The hardware page table is loaded by the microcode. The paging cache is implemented as 512 entries,
one for each page of a user’s virtual address space. The EXEC and USER are offset from each other,
but they share the same 512 entries. Therefore, at any given time, the paging cache holds translation
information about most of the sctive pages. A guarantee that the 512 most recently used pages will be
addressed by the paging cache cannot be made. However, the last page used will aiways be in the
paging cache.

r Load pagng mamory {aagung coche;

b= — — ={ wnn the rmoives
VMA 10

PMAA tansiston

@———- Revtart ol referonce
0 261wl

Figure 1-26

Pointer Interpretation Flow Diagram (Sheet S of §)

EBOX /140

EBOX/1-4)

Cars Stonun Tatdes

When the monitor takes any action that would invalidate information about existing virtual-to-phys-

K ath sddromed
by page teonbior |

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csT 1

oY 2

st 2

csre

csT8

ical address translation, the paging cache must be either partially or completely cleared. Examples of
such insiances are:

Change of user process - clear entire paging memory (entire user address space has
changed).

One page removed from core - clear the entire paging memory (several Shared and Indirect
Pointers may have used the page).

MICRO CODE

SYORAGE

STATUS

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cst

Pointer is removed from UPT - clear the entire paging memory (association for many pages
through UPT is changed).

Monitor mapped page to EXEC space for iocal use
- only one entry cleared (When page is
unmapped. only that one pointer must be cleared. Because this facility is provided by the
pager, it may be used to reduce reload overhead.)

If the paging data is not found, the flow in Figure 1-26 is followed. A special trap is initiated and the
microcode saves vuinerable EBox data before starting on the pointer tracing algorithm. If the
algorithm is successful, the resolved pointer and associated information are loaded into the paging
memory, the EBox registers are restored, and the memory request is again issued.

- = = Page % wacomabiy

The microcode must also handie the first Write Request trap, inhibiting the write until the modified bit
can be set. The pager maintains this modified bit. The microcode implements this as follows.

AT BLOCKS

Wt O

During a paging memory reioad, the write access bit (W) is set in the paging memory only if the current

m‘:‘“v

csTMSx

:
P

memory reference is & write (and a write is legal for the page). Thus, if the first reference toa pageisa
read, the W bit in the corresponding paging memory entry sets to 0. A subsequent write reference

= e
f 591 ot

causes another trap to the microcode. On this second trap, the pointer interpretation is repeated and
the paging memory is reloaded, this time with the W bit set.

¢ totds abeut Qurrent relerenee

Womd )}

1.2.4.3 MBox Esrror Conditions
- In addition to the page fault mechanism, the following five types of
errors can be generated by the MBox 10 the EBox:

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ACBLOCK
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RE 5 EALNCE

avmrm

[T T T e mesdeder

Cache Address Perity Entor
MBox Address Parity Error
SBus Ervor
Nonexistent Memory
MB Parity Error

The MB Parity Error is handled similar to a page fault. The AR Parity Network, upon detecting s
parity error in a data fetch or an instruction fetched from the MBox, causes the page fault handier to
be called.

:—I
STURE

(23]

ENTRY

O o0

Figure 1-27

}.
2.
3.
4.
S.

1244 VMA Comtrol - Two basic types of virtual addresses can be passed to the MBox for core
memory references. The first type is consistent with Ki-style paging: the second is consistent with KLstyle paging. In both forms of addressing, note that the VMA jines actually consist of 23 bits. For KIstyle paging. bits 13-17 are unused and forced to 0. In the logical sense, the virtual address may be
viewed for Kl-style paging as consisting of |8 bits of addressing information. The basic address trans{ation mechanism is indicated in Figure 1-28.

KL Core Status Tables Updating Flow Diagram

EBOX/1-42

EBOX /143

Actually, the virtual address in K110 paging mode is derived from the instruction Y field. which may
be modificd during the effective address calculation. This consists of 18 bits. The additional five bits
(VMA 13-17) are present 10 facilitate KL paging mode, which can generate a 23-bit
virtual address.
However, the MBox docs utilize the high-order part of the VMA as indicated in Figure 1-29 to generate a Hashed Page Table address for internal use. The hashing technique is basically an associative
process, but precludes the necessity for hardware associative memory.

The VMA can be loaded from the ADDER or VMA ADDER. Generally, during caiculations for the
effective address, it is loaded with the contents of ARX via the ADDER. At this time, ARX contains
an intermediate address {Y + C(XR)) or E.

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Basic Address Translation

EBOX/1-44

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Virtual Address Mapping,

K110 Paging Mode

EBOX/1-45

1.2.8 EBus Costrol and Pl Coatrol
The EBus control consists primarily of two major sections. One section is used exclusively for priority
interrupt handling (P1 CONTROL) and the second is used for 1/0 instruction handling (EBUS CONTROL). Each KL10 controller (except the DIA20 1/O Bus Adapter) is assigned a device code. This
code is seven bits wide (IR 3-9). In addition, each device controller is wired to contain a physical
device number that relates 10 a preassigned scheme, and is slot dependent. Thus, Massbus controliers
hoid physical numbers in the range of 0-7; DTE20 numbers 10-13; and DIA20 number 17,. This
provides a physical priority scheme that supplements the programmabie priority interrupt system.

In the situation illustrated in Figure 1-30, both DSKs are amsigned to the same P{ level (level 5). This is
accomplished by the operating system with a CONO Pl to the Pl system enabling the processor to
accept interrupts on level 5. In addition, the operating system performs 8 CONO DSK, assigning the
DSK to level S. For the situation where both DSKs interrupt simultaneously, the EBox arbitrates the
priority interrupt levels and then physical device numbers are requested from both DSKs. These are
arbitrated according 1o the fixed scheme discussed previously. The DSK with physical No. 0 has
highest priority in this situation.

asse.

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Figure 1-30

tes

Simultancous Interrupits

The basic dialogue is shown in Figure 1-31. Once the priority interrupt system has been turned on and
set up by the operating system 10 handle interrupts, the EBox control automatically carries out all
dialogues necessary to obtain the API funciion word. When the AP functionis on the EBus and
transferis received from the device, the FBus control asserts PI READY, signaling the microprocessor
to take over. The microprocessor looks at this line, however, only at specific times during normal
instructions. One such instance is at NICOND Dispatch, which aiways occurs at the beginning of each
instruction. If at NICOND time, the Pl RDY conditionis true (INT REQUEST sets), the PI HANDLER is calied. To prevent furtherinterruptions until the function can begin, the microprocessor
sets
the Pl CYCLE flag. This causes the EBus Control to defer any further PI READYs. The Pl HANDLER evaluates the API function word (Figure 1-32) and performs the indicsted service. As long as P1
CYCLE is on, other interrupts are not honored by the microprocessor. The time that PI CYCLE is
clearedis dependent upon the service performed. If theinterrupt is a standardinterrupt to 40 + 20, the
instruction in 40 + 2n should save the hardware state of the EBox,i.c., the flags, PC word. Appropriate instructions are JSR and MUUOQ. Bad choices are JSP and PUSHJ which use ACs. The choiceis
particularly bad because at the time of the interrupt nothingis known sbout their contents.

EBOX/1-47

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1/0 Instruction Dislogwe Overview - For 1/0 instruction transfers, the basic concept is illustrated in

Figure 1-33. The EBus Driver is called from the I/0O HANDLER to generate the appropriate EBus

dialogue. First, the EBus is requested. This is necessary because the EBus is also used by the Pl system.

SuNC PLADR N

1f the EBus is free. the EBus driver sets 8 CP GRANT flag to hold control of the EBus; if the EBus is in

use, the EBox waits.

CONTRGL.ER SELECT

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Generally, a JSR instruction is placed in 40 + 2n for calls to the operating system Pl HANDLER. This
instruction causes PI CYCLE to clear. At this time, a pending interrupt may request microprocessor
attention and can raise PI READY. In general, for the other cases, the equivalent of one instruction is
provided before Pl CYCLE is cleared.

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Pl Dialogue Overview

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Figure 1-33

EBOX/1-48

170 Instruction Dialogue Overview

EBOX/1-49

2 1

Basically, a sequence of microinstructions is performed having the condition field coded as
COND/EBUS CTL and the appropriate bits coded in the magic number field (a 9-bit microinstruction

field). Specific patterns in the number field with EBUS CTL true cause appropriate action in terms of

the dialogue. IR bits 3-9 are used to develop device controller select bits CS 00-07. IR 10-12 specify
the function to be performed by the EBus control logic, i.c., DATAO, CONO, etc. Upon completing
the transfer, the device generates 8 transfer. The EBus is released and this completes the dislogue.
1.2.6 Data Path
Referring to Figure 1-34, the logical data path consists of the following registers and adders:
Arithmetic Register
Arithmetic Register Extension
Buffer Register
Buffer Register Extension
Multiplier Quotient Register
Fast Memory
Adder
Adder Extension

Also included is fast memory and a 36-bit shift matrix that can implement various shifting operations
on data in AR, ARX, or the combined AR and ARX. The above registers and adders constitute the
arithmetic logic in the EBox. This logic is used to handle words in logical operations, data traasfers,
and fixed-point arithmetic (including effective address calculation). In these operations, fast memory is

used as a passive register; its output is the contents of the addressed Index register or Arithmetic
register. In association with the full word registers listed above, the shift counter (SC) and shift matrix
(SH) provide shifting in shift instructions, byte manipulation and, where required, in various instructions. The SC, with its adder (SCAD), and the floating exponent register (FE) are used for handling
floating-point exponents and various other special functions.
Double-precision floating-point and double precision integer operations require use of ARX. ADX,
and MQ, where ADX is a 36-bit extension of the main AD and ARX is a 36-bit extension of AR. Thus,
the registers AR, ARX, BR, BRX, together with AD and ADX, can constitute a 36-bit, & 72-bit, and
with MQ, a 108-bit paith where necessary. In addition, ARX is used as a buffer for instructions ferched
from memory. The main data buffer, for words coming from or going to core or fast memory, is the
AR.
1.2.6.1 Informstion Flow To and From Memory - Referring to Figure 1-35, this simplified block
diagram illustrates those paths that sre used in transferring information into and out of fast memory,

as well as to and from core memory via the MBox. Because of the structure of the EBox and design of
the microcode, a specific type of information will always enter or leave a given register. Table I-3 lists
the type of request, type of information, source or destination, and comments.
All memory operations that load either AR or ARX require an M Box request cycie. The generation of
thit request cycle, together with the necessary request qualifiers (¢.g.. Read, Read PSE Write, Write, or
Read-Write), is based upon the code specified in one of the ficlds of the microinstruction word. This
field is called the MEM field and is 4 bits wide. Some of the types of requests that can be initiated by
this ficld are: instruction fetches, indirect word fetches, dats fetches, and data writes.

EBOX/1-50

Figure 1-34

KL10 Register Interconnection

Diagram

EBOX/1-51

[

Table 1-3

Memory Information Flow

‘..’..’-’-....O......-..

L
4
[]

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o s e

4
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CACHE DATA LINES

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Core and Fast Memory Information Flow

EBOX/1-53

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Fast Memory

AR.ARX.

toaded vaa cache data lines 1)50 core mem-

ot hoth

ary or via AD trom fast memory.

Data

Read

Indstect

Word

Core Memary

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;

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.

;

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Laaded via cache data hines i ftom core mem-

+ o ory of via the AD a trom Iast memory,

Fast Memorny

AR goes to the

FM and to the cache.

regardless of which reads it

}ast Memory

ARX

AR. VMA

Lisded via vache data hines of from core mem-

ory o via AD if from fast memory.

The

of the

add

d Index

1ead into the ADDER “BTM input where it is

added o the current value of Y. The sum i3

loaded nto both AR and VMA under micro-

code control.

The microinstruction contains a number of separate fields for register selection including a 3-bit AR
ficld and a 3-bit ARX ficid. In addition, three fields are provided for controlling the adder; two of
these, the ADA (3-bit field) and ADB (2-bit field), select various inputs to the adder. The third field,
AD (a 6-bit field). controls the adder directly. The actual selection of the source ot destination registers
depends on the following:

1.
2.

The microinstruction register select field function
The source or destination memory (e.g., fast memory or core memory).

e ivied o 18 $raw-ng

(INDEX REGISTLR:

Figure 1-35

{

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-~ -b--b> INDEXED ADDRESS

Fast Memary

ARX

Comments

—o—o
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—

Core Memory

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Destination

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apR

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D Tn

CACHE DATA LINES

ADH

Type of
Reyuest

As an example, consider an instruction fetch (not a prefetch) from fast memory. Refer to Figure 1-36.
The MEM ficld function ofthe microinstruction desiring the word is coded as FETCH. From this, the
term MCL LOAD ARX is produced and routed to EBox Control No. i, where it partially enables the
ARX SELect § and ARX SELect 2 Mixer Selection logic.
The final sclection
is a function
of the
address contained in VMA. If this address is & fast memory address {¢.g., VMA 13-31 = 0), then the
ARX SELect 2 tline is fully enabled and the ARX SELect 1 line is inhibited by VMA AC REF.
Similarly, if the address in VM
A is a core memory address, VMA AC REF will be false, inhibiting the
ARX SELect 2 line and enabling the ARX SELect | line.

EBOX/1-54

Asindicated in Figure 1-36, there are cight inputs to the ARX. The microinstruction may select any of
these eight inputs, if required, simply by coding the ARX field appropriately. The AR and its associated mixer are very similar to the ARX. In the case of reading a word of dats into AR from core
memory, the MEM field function, LOAD AR, is laiched into the request qualifier register in the
memory control, partially enabling the AR mixer select 11 and select 2 lines to the AR mixer. Once
again, the selection is a function of the address in VMA. If bits 13-31 of the virtual address are equal to
zero, the adder is enabled into the AR number 2 input, but if the address in bits 13-31 of VMA is
nonzero, the cache data lines are enabled into the AR number 2 input. As with ARX, the microinstruction may select any of the cight inputs oa the AR mixer, if required. Figure 1-37 is a simplified
version of the EBox data paths. The basic path connections and the direction of transfers are indicated.
Along the bottom of the figure is the portion of the microinstruction word format that controls the
data path. The simplified path does not show shift left or shift right connections.
1.2.6.2 iaformation Flow [/O aad Priority Interrupt - Figure 1-38 is a simplified path diagram used by
1/0O and priority interrupt operations. The major path is the shaded area, including the AR, adder,
EBus, translator external or internal devices, and MQ. The portion that is cross-hatched may be
generically called the “inspection and control path”TM and includes the SH, SC, SCAD. FE, and CRAM
address logic. The remaining paths and registers are used as working registers; the usage depends on
the specific operation.
Note that internal device intormation flow (control data) is not transiated, but rather utilizes the
internal ECL EBus. External device information, however, entering or leaving the EBox, must be
translated in the direction TTL to ECL or ECL to TTL. If the operation being performed is 8 CONI or
DATALI the destination register is AR. If the operation is CONO or DATAO, the source is AD. The
processing of interrupts is more complex. The destination for the API function word is initially AR,
but the function performed in response to the decoding of this word may involve an instruction fetch, a
data read and writc, & date out, or a dats in operation. The microprogram begins to process the

interrupt when the AR contains the API function word transmitted from device and the EBus handshake has been completed.

The microprogram places a copy of this word into MQ for use later and performs s SHIFT Dispatch
on the API function code to the appropriate routine in the microprogram. To implement this dispatch,
the AR is enabled into the shift matrix; then the output bits (SH 00-03) are sampled in the CRAM
Address Control logic. In addition, another type of dispatch can be performed; this is called AR 00-03
Dispatch.
When the API function specifies a standard interrupt (API FCN 0 or 1) an instruction is fetched from
40 + 2n, where n is equal to the interrupting channel 1-7. These interrupt locations generally contain &
JSR instruction that must be performed in order to preserve the flags and PC of the interrupted
program. In addition, the current ACs must not be disturbed and the interrupt handler (monitor
routine) must be entered for polling of devices. In these situations, the microcode forms the correct
address in VMA (40 + 2n) and begins an instruction fetch by issuing a microinstruction with MEM
equal to FETCH. This fetch is from the Executive Process Table (EPT) and requires that the request
qualifier, EBox EPT, be asserted in order that the MBox access the EPT for the instruction.

EBOX/1-5§

wicko [

INSTR

]

FIELD

FETCH

OR LOAD &R

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TTING CLK RESP

£80x REQUEST

ViRToR ADoRESS

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Figure 136

Loading ARX

EBOX/1-57

PROC SERIAL #

MAIN DATA TRANSFER REGISTER
ATHS. SHOWN IN FIG 1-4

36
i
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3

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12-17

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BOOLEAN

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e P abe|
INPUT

|27-29 |

an | an|

sec | sec | sew

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MICRO INSTRUCTION DATA PATH CONTROL
=

Figure 137

EBox Data Paths

Simplified Paths Diagram

EBOX/1-59

When the API function specifies a dispatch (APl FCN 2), the virtual address of an interrupt instruction (JSR) is provided by the device In this situation, the request does not assert the qualifier EBox
EPT because the address is not an EPT address, but rather somewhere in the virtual address space. For
the situations described up to this time, the instruction will enter ARX. Control is passed to the main

microcode loop for processing. The API function (Pl increment or PI decrement) is slightly different,
in that a word must be fetched from the virtusl address provided by the device. This word is then
incremented or decremented as specified in the AFI word and the result is written back into memory.

Here the AR is used both for the read and write operations.

API functions 4 and S require 8 DATAO and a DATAL, respectively, to be performed to the device.
Prior to performing the specified DATAO, & word is fetched from the virtual address provided in the
APl word and this word is loaded into AR. The path is now from AR 10 AD and then to the EBus,
which is controlied for the DATAO by the microcode. For the specificd DATAL, the operation is the
reverse. The required word is obtained from the device via the EBus under microcode control (EBus
dialoguc) and the word is loaded into AR. Next, the contents of AR must be written into the virtual
address supplied by the APl word. Of the remaining functions, only APl FCNG is used and this is
reserved for the DTE20 (10-11 interface). Examines and deposits, as well as byte transfers, may be
requested by the DTE. This subject is covered in Section 2.

EBOX/1-61

INSPECTION AND CONTROL

|
|
|
|

To=3

Figure 1-38

Input/Output Priority Interrupt
Information Flow

EBOX/1-63

SECTION 2
FUNCTIONAL DESCRIPTION

2.1

INTRODUCTION

Figure 2-1 illustrates the major functional elements of the EBox. The purpose of this drawing is to
support the functional descriptions contained in this section. The major data and address paths and

the individual controls introduced in the previous section are shown on this diagram with some additional detail. Major interfaces are also shown in some detail.

The interface between the EBox and the M Box is not a bus, but is functionally shown and described as
if it were, because its operation is similar to that of a bus.

As described in Section 1. the EBox serves as the Instruction Execution Unit for the KL10 system.

Access to main memory is logically controlled by the MBox; therefore, as the EBox requires memory
operands or instructions, it performs MBox cycles 10 obtain these words. These cycles take place over
the E/M interface. In a similar fashion, access to 1/O devices is via the EBus. Devices may communicate with the EBox over the EBus by utilizing the priority interrupt system. In addition, as the EBox
requires status or data from devices connected to the EBus or wishes to tranamit data or control
information to devices on the EBus, it does 30 by performing EBus cycles. These cycles take place over
the EBus. Figure 2-2 illustrates these primary hardware cycles. The implementation of MBox or EBus

cycles is via the microprograms stored in the CRAM.

2.2 MICROPROGRAM STATES AND PROCESSOR CYCLES
Referring to Figure 2-3, the EBox microprogram can be in one of the following states at any time:
Microprogram Running
Microprogram Wait State
Microprogram Halt Loop

Microprogram and EBox Frozen
Microprogram Deferred
EBox Resct (Power Up Sequence)

A discussion describing how to read and understand the microcode is provided in Appendix A.
2.2.1

EBox Reset

During the power up sequence, the EBox, MBox, and all controllers are reset to known states. The

EBox, MBox, EBus, and SBus clocks are initialized and the CRAM register is cleared. This clearing
action places the EBox in the diagnostic state, because the dispatch field is equal to zero

(DISP/DIAG). A program running in PDP-11 memory then initializes the EBox, loads the Dispatch
RAM and verifies it, loads the CRAM and verifies it, and starts the microprogram into the Halt Joop.
In general, at this time, the system must be bootsirapped; to accomplish this, a number of diagnostic
functions are necessary. This is discussed in Section 3 and in the system and interface descriptions.

EBOX/2-1

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Figure 2.1 EBox Functional Block Diagram }
EBOX/23

Figure 2-3

222

Microprogram Static States

Microprogram Halt Loop

The Halt loop is entered following a NICOND Dispatch, when RUN and P CYCLE are found clear.

Figure 2-4 is the flow diagram. Referring to Figure 25, the EBox contains a synchronizer (CON
START), which is set for three clock periods when CONTINUE is pressed. In addition, it also contains a flag (CON INSTR GO), which is set by CONTINUE and remains set until a HALT instruction
is performed. The RUN flag in the EBox consists ofa RUN source enabled by DIAG SET RUN and
CON INSTR GO true. Referring to Figure 2-4, assuming a HALT instruction has just been performed

vy via

nocero

(JRST 4) and the RUN flag has been found clear at NICOND Dispatch time, the Halt loop is entered.

wTH MunE:
2 WICOND

mom

icoND.

The following occur immediately:

oraten
Tt

The AR is cleared.
The HALT fNag is set.
The current value of PC is loaded into VMA
The current value of VMA is placed in PC

EBOX 2-6

AR WAY ALSO

DIAGNOSTIC FUNCTION

Figure 2-4

Microprogram Hait Loop

EBOX /27

Microprogram Running

Thus. if the HALT instruction was fetched from location 600, and the effective address supplied in the
HALT instruction was 100, PC would become 100 and YMA would become 601 (the updated PC
value). The START flag is tested to determine if CONTINUE was pressed. In this case, START will
be clear. If an interrupt is pending, the PI Handler is entered to service this interrupt.

2.2.3

When this is donc the next instruction is requested. This is followed by a NOOP microinstruction.
Finally. the State register {a hardware register in the EBox) is initialized clear. Then VICOND Dis-

the FBox In general, the relationship is as shown in Table 2-1.

Once the microprogram is running. it may enter any of the other states (Subsection 2.2). Normally, the
microprogram passes through a regularly defined sequence consisting of at least the five main dispatches (Main loop) shown in Figure 2-6. Between each dispatch, some number of microinstructions is
performed. A rough equivalence exists between the traditional computer machine cycles and those of

patch is issued and the Halt loop is entered again.

If no interrupts are pending, the “Tight loopTM is entered, continually checking the ST~V T flag and
interrupt requests. Note that HALT INSTR does not clear the RUN source, but merely < ars INSTR

GO. which removes the CON RUN signal (Figure 2-5).

Table 2-1
-

EBox Main Loop/Traditional Machine Cycle Comparison
-

FBox Dispatch Main Loop

NECOND Dispatch

Traditional Machine (voles

Imntructum

t AMOD Dnvpatch

Address

A RI AD Dnpatehs

betls

DRAM J tSe \ote)
BTN

CIA UM R -

o a6 man stc

oAz mew IR

4ue

noInte

. D

Facaate

B WRITE Disparch

‘
S

[

Sty
TR

NOTF

This dispatch is referred to 1n the Micrucode as IR Dispatch

~3E

COM Tom

LELEL
T

AT 2d S

Canyiwk

engee
s tesm ¥B 3

tag

T
L

Figure 2-5

T.ie

JfE

Run-Halt-Continue Logic

The HALT instruction is a *‘privileged instructionTM; therefore, the EBox must be in cither diagnostic,
USER 10T. or KERNEL mode to clear CON INSTR GO. The PDP-1] may clear the RUN source at
any time by issuing {via the 10-11 Interface} DIAG RUN CLR. This causes the Tight loop to be
entered at the next NICOND Dispaich (assuming no interrupts are pending).
If it is desired 10 execute a single instruction, the AR may be loaded with the desired instruction by use
of the prescribed DIAG function, issued via the 10-11 Interface. Afier the AR has been loaded, the
START flag is enabled by issuing DIAG CONTINUE. The AR is tested for 2 nonzero value. If it is
nonzero, the contents of AR are executed; upon its completion, the Halt loop is once again entered.

It should be noted that PC+1 INHIBIT is true during the Execute function, to prevent the PC from

being updated. Similarly, by ciearing AR and pressing CONTINUE while CON RUN is disabled. one
instruction may be fetched at a time and executed, or the program may be resumed if CON RUN is

true after performing the instruction in AR. For this function, the microcode. at XCTW, is used to
fetch the instruction and wait for it. This instruction is performed, and the PC is allowed to be updated
by +1. At the end of the instruction, NICOND Dispatch is issued and the state of CON RUN is tested
together with other hardware conditions, to determine what to do next.

QOOOC

[

STORIE

Figure 2-6

EBOX/2-8

Dispatch Path Siate Diagram

EBOX /29

Altogether, there are 16 dispatches. The five basic dispatches constitute the main loop: an additional
cleven are. in general, instruction dependent and usually. if issued, follow an IR Dispatch (DRAM J
DISP). Each time an EBox clock tick occurs, the CRAM register is loaded with a8 microinstruction.
This microinstruction then contols formation of the next microins:ruction address. This is accomplished by the particular coding of the appropriate microinstruction fields. In general. there are four
types of

CRAM address modifications (Figure 2-7):

DISPATCH

Branch On Condition
Branch On Condition With Skip
Skip
Jump

CRAM Ri GISTER-

MICRO
INSTROC THON

The CRAM address logic samples conditions { Figure 2-8) supplied by various portions of EBox logic.
together with the current microinstruction 1, COND, and Dispatch ficlds, and then generates the next

CRAM address (CR ADR 00-10).

coos

2.2.4

Microprogram Wiit State

As indicated in Figure 2-3. the Wait state (MBOX WAIT) occurs during memory requests involving
the M Box. In general (Figure 2-9), three main uses of the Wait state exist. The first is to assure that the

LAAM ADR
tRAM 00 10

hold off a second MBox cycle when the MBox has not yet responded to the first MBox cycle.

oisraten

)

Vv (RA 0010

microprogram waits for an M Box responsc after having started an MBox cycle. The second use is to

DHAN B

[

In WAY FRANCH
POMSMIBLE

As shown in Figure 2-10, the EBox clock control samples the following signals:

vIE

NORM

| fauocD

A TVRE

MBOX WAIT
VMA AC REF

RESP MBOX

"BWAY BRANCHTM

CRAM ADR-

POSSIBLE

CRAM X0 10V

chaoe 1B

If an MBox cycle is started, MEM CYCLE sets, as enabled by the request. It remains set until XFER is
generated. When the request is to the MBox, and VMA 13-33 is nonzero, the XFER is generated as a
direct result of MBOX RESPONSE IN. If. however, VMA 13-33 is zero, VMA 32-35 is 2 fast memory
address and the EBox aborts the cycle. The XFER is a result of FM XFER. a signal generated from
within the EBox itself. If VMA AC REF is true, the EBox clock ignores MBOX WAIT. However,
when VMA AC REF is faise and MBOX WAIT is true, the EBox clock may be inhibited.

The third case involves instruction prefetches from fa<t memory (Figure 2-11). For this situation, the

microinstruction generating NICOND Dispatch also asscrts MB WAIT. This is necessary because the

EBox hardware requested the next instruction from the MBox rather than from fast memory. The
M Box detects that the VM
A address contzined a fast memory address and aborts the cycle. The EBox

hardware switches the ARX input to the AD output, thus reading from fast memory.
NOTE
XFER = MB XFER v FM XFER

2.2.5

]

52} Aooo

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AD~O

31
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Microprogram and EBox Frozen

CONTROLLED

The microprogram and EBox frozen state occur in practice when any ofthe following events occur:

DRAM Parity Error while the EBox clock is running.

CRAM Parity Error while the EBox clock is running.

Fast Memory Parity Error while the EBox clock is running.

EBOX:2-10

BY Tt SKiP
CONDITION

Figure 2-7

Basic Microprogram Address Control

EBOX/2-11

Di1
i

w
T

Figure 2-10

MBox Wait and EBox Clock

“

Figure 2-9

Wait State

Figure 2-11
EBOX/2-12

MBox Wait on Prefetch from Fast Memory
EBOX/2-13

Associated with each of these error conditions is an enable that must be activated prior to the occurrence of the error 1o be detected. The three enables are listed in Table 2-2.
FError Stop Enables

Table 2-2

Enable

CLK FM PAR CHICK
CLK CRAMPAR CHFECK
CLK DRAM PAR CHIFCK

;

FBws Bit

Function

x
33
34

DIAG TUNC 346
DIAG FUNC 146
DIAG FUNC 036

—_

The DRAM words are coded in a specific fashion for each instruction. If a DRAM parity error occurs

undetected, it implies that the DRAM word has picked up or dropped an even number of bits. Suppose, for example, that the DRAM J field picked up & bit, which changed the Jump address from 200
1o 500. The microprogram would perform properly up to the point where it dispatched to the executor.
Here. instead of jumping 10 the MOVE microprogram, it jumps to the half-word microprogram with

erroncous results stored in the specified AC. In a similar fashion, & bit could be picked up <t dropped
in the DRAM A or B ficlds with equally disastrous results. The microprogram is a structured entity; an
erroneous variation of any of its bits in the CRAM r=gister causes errors in the execution of instructions and could cause the microprogram to lose control of the EBox. As an example, assume a micro-

instruction is loaded into the CRAM register. The Dispatch ficld, originally coded as DISP/DRAM B,
because of a dropped bit, becomes instead DISP/SIGNS. Thus, the next CRAM address will be
computed based on the signs of AR, BR, and AD instead of using the B ficld of the DRAM word: and
this would create the wrong CRAM addresses.

In general, all instructions in the KL10 Instruction Set utilize fast memory in some way. In addition,
the microprogram always uscs fast memory to set up the indexing function. If fast memory parity
errors were not detected, bad data could be generated and possibly erroncous instructions fetched
from fast memory.

2.2.6

Microprogram Deferred

The microprogram samples the EBox hardware only at specific times for pending priority interrupts or
pending traps. One such time is at NICOND Dispatch. Currently, eight possible conditions can occur

(Table 2-3). Three of these are related to interrupts, two are related to traps, one is for a halted
condition, and t%e remaining two are the more general cases. Here, the deferred condition is taken to
mean that upon finding an interrupt or a trap pending, the microprogram defers the pending instruction and instead handles the interrupt or trap first. In terms of iriterrupts, the highest priority condition
is with PI CYCLE (1). This implies that on the previous NICOND Dispatch INT REQ was true and
the microprogram diverted to the PI Handler to perform the first part of a standard (40 + 2n) interrupt. For example, assuming device (n) interrupts, the Pl system carries out the necessary dialogue and
asserts PI READY. This results in the assertion of INT REQ, which is sampled at NICOND Dispatch
time. Now assuming PI CYCLE (0) and RUN (1), the PI Handier is entered. The handler reads the
API function word on the EBus into AR and processes it. Here we will assume it specifies a standard
interrupt (40 + 2n). Assume the conditions shown in Figure 2-12.

EBOX/2-14

NICOND Priorities

Table 2-3
b

CToma

I
ol

T8
P

wio

e
YR

FYPTR

nder

AN DR B

NiCoN [ NOND [NICOND | SicoN [NicowD
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e
il
el
W

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353
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EBOX/2-15

Figure 2-12

PI 40 + 2n Skip

The P! Handler sets Pl CYCLE, interlocking the microprogram and PI Poard, and temporarily, at
least. preventing any further INT REQs from being sampled by the microprogram. The Pl Handler
forces an instruction fetch from 40 + 2n; note that NICOND is not now generated. The SKIP instruction in 40 + 2n is performed and one of two possible actions results (in this case) from the state of the
DONE flag:

DONE (1) - Perform the instruction in 41 + 2n; this instruction must be of such a nature that Pl

CYCLE is cleared (JSR is such an instruction.)

DONE (0) - Dismiss the interrupt and clear PI CYCLE.

For this example, assume the instruction should be fetched from 41 + 2n [DONE (1)]. The dispatch,
therefore, is back 1o the PI Handler for the second part of the interrupt.
When the P! Handler releases the Pl system, NICOND Dispatch finds PI CYCLE still set. Because

this is the highest priority condition at NICOND time, the dispatch is back to the PI Handler for the
second part of the interrupt. The PI Handler generates the appropriate 41 + 2n address and causes the
instruction to be performed, once again omitting 8 NICOND Dispatch. The instruction fetched must
be one of the following:
JSR

JSp
PUSHJ}

Changes the ACs; use
not recommended

MUUQ

[P (will be satisfied)
SK

All of these instructions cause PI CYCLE to be cleared.
2.2.7

Microprogram Organization

The basic control program modules are illustrated in Figure 2-13. The symbol containing the Data
Storage Manager illustrated in Figure 2-13 represents a predefined process. Examples of such predefined processes include software and hardware subroutines, the Unibus dialogue, and even functions
of an alarm clock.

In the microprogram context, the predefined processes represent functional arcas of the microcode.
Figures 2-14 through 2-21 represent the hardware that controls branching to each of the handicrs

illustrated on Figure 2-13.

EBOX/2-17

These may be grouped as follows:

ADR

The Startup and Stop Interface (F gure 2-14) evaluates initial hardware conditions and dispatches io
the appropriate handler. The nature of the condition could be a pending priority interrupt. hait condition, etc. Upon completion, all instructions must pass through this process. The mnemonic for the

1
H

CORTE Y

Baw

dispatch to this process is DISP/NICOND (Next Instruction Condition).

The Effective Address Manager (Figure 2-15) evaluates indirect address flag bit 13, index field bits
14-17 in the ARX (which contains the current instruction), and certain hardware conditions such as
Pls or page failures. It either dispatches to the appropriate handler or calculates the effective address
by requesting the necessary fast memory (Index) cycles or M Box Indirect (I) cycles. The mnemonic for
the dispatch to this process is DISP/EAMOD (Effective Address Mode).

UKL

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R

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Figure 2-15

4 CcowpsT:
;
.

(secin) wicomn

[EEEEEERERPPPPPERTE

SNSRI

Mojor CipaIches - S0k gt 2 -6

Figure 2-13

HLh CWARE

Z0N5

TITNS

M Program Modules

Effective Address Manager

The Daia Fetch Manager (Figure 2-16) evalustes the 3-bit A (FETCH) ficld (for the current instruction). which is in the Dispatch Table. The code in the 3-bit ficld defines the type of data fetch or write
or combination operation (if any) required. The Data Feich Manager takes the proper action, i.e.,
enabling the EBox clock 10 stop as appropriate, dispatching directly to the executor, or initiating an
instruction prefetch. Note the Instruction register is used 1o address the proper location in the Dis.
patch Table (DRAM) based upon the op code for the instruction.

EBOX/2-18

EBOX/2-19

of the microprogram. 1t contains a number of somewhat
The Executor routine (Figure 2-18} is the bulk
n specific functions, ¢.g.. move & half-word from
autonomous routines used to execute the instructio
2 subroutine stack.
one register 10 another or push a word onto

when called from
dispatches on the DRAM B field. In addition,
The Data Store Manager (Figure 2-19)
it defines the appropriate MBox control sigthe executor as a subroutine only, ¢.g., MEM/WRITE,
in the
. When the Data Store Manager is entered
nals and dialogue and initiates the write operation
to that process from the Executor. Finally, a
context of a store cycle, co..rol generally passes
NICOND Dispatch is generated and control passes to the Startup and Stop Interface.
gram. Interrupts
d 10 or from discrete points in the micropro
The Priority Interrupt Handler is dispaiche
during certain
and
address,
effective
the
g
computin
while
,
Dispatch
NICOND
during
scanned
are

BTSN
L

Jonger instructions, such as BLT.

(Figure 2-20) routine from the Effective Address Manager
Contro! is passed to the Page Fault Handlerasserts
8
PF HOLD prior to an MBox response during
MBox
the
when
Manager
or Data Store
failure,
access
an
i.¢.,
,
occurred
violation
address
memory
a
that
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ion
implicat
memory request. The
when implementing KL10-style paging. PF
write protection violation, or similar violation. In addition,
from the MBox. The implication here is
EBox
the
to
asseried
be
may
E
HOLD with EBOX HANDL
mictoprogram rather than in the MBox
via
shed
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that the paging address translati
s.

S
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itscif. The Page Fault Handler is also used for certain error condition

e HAMN
TIGPLT

The Dispaich Table (Figure 2-17} consists of four ficlds:
DPAM A - Bits 0-2; defines the type of operand fetch cycle.
1.
2.

DRAM B - Bits 3-5; defines Jump, Skip, and Compare conditions {or certain instructions,

or result store mode, etc.

DRAM P - Bit 11: parity bit (parity is normally odd).

address of the executor routine. The
DRAM J - Bits 14-13; jump address. This is istheIRentry
DISP (DRAM J) (Instruction Register
mnemonic for the dispatch to the executor
Dispatch).

Data Fetch Manager

[ ___,.___.

Figure 2-16

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e i by

mCRMAL

TROG 08

0
012343

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Figure 2-18

.
-

Executor

.
Y

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Figure 2-17

veas

Dispatch Table Fields
EBOX,2-20

FBOX 2-2i

i3
:

woc t2|

The Halt Handler routine is entered from the Startup and Stop Interface when the RUN flip-fion is
clear at NICOND Dispatch time. The RUN flip-flop can be cleared by various mechanisms. For
example, when a HALT instruction is executed, RUN is disabled. On power up, RUN must be set by a
diagnostic function initiated from the DTE20.

The 1°0 Handler (Figure 2-21) is dispatched vis IR Dispatch from the Dispatch Table on DATAO,
CONO after the data or status has already been fetched, or directly on DATAI CONI, CONSO, or
CONSZ. The handler calls the EBus driver, which generates the necessary EBus dialogue with the
device. On BLKI or BLKO, the pointer has been fetched but must be updated, stored back at E, and
the first word fetched. This is performed in the 1/0 Handler first. When the data has been fetched, the
EBus driver is called. On DATAI or CONI, the EBus driver is called 10 negotiate the transier from the
selected device over the EBus to the EBox. The 1/0 Handier then passes control to the Data Store

2.3 BASIC MACHINE CYCLE
’
The basic machine cycle for & typical instruction is illustrated in Figures 2-22 and 2-23. The cycle
begins at the EBox clock following NICOND Dispatch snd terminates at the trailing edge of the next
NICOND Dispatch. In this example, assume that the instruction MOVE 3 @ 200 (1) has been fetched
from core memory symbolic location PC. The following information relstes to the example:

'bt
. Figure 2-19

PC;

PC+1:

300
100~
1!

Data Storc Manager

MOVE 3@ 200(1)

Current Instruction

000000, 000 100
174717, 11111
000000, 000100

Indirect Address = 300
Effective Address = 100
Index Register = |

NEXT INSTRUCTION

A
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Manager where the data is stored.

Figure 2-20

Page Fault Handler

DiSPAT(m
Raw

Figure 2-21

EBOX/2-22

Input/Output Handler

EBOX/2-23

LOCATION INSTRUCTION.

WOVE 3@ 20011)

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Figure 2-22

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Basic Machine Cycle Overview (Sheet 1 of 2)
EBOX/2-24

EBOX 2-25

Figure 2-23

KLI0 Processor Sequence

of Operation (Sheet | of 2)
EBOX/2-27 "

Figure 2-23

KL10 Processor Sequence

of Operation (Sheet 2 of 2)

EBOX/2.29

I1gures 2-24 through 2-33 illustrate the microprogram steps and basic EBox hardware used to perform

the example instruction. Figure 2-22 can be used 1o follow the various operations at each microinstruction step.

2.3.1

Instruction Cycle - NICOND Dispatch to XCTGO

The instruction enters the ARX through the ARX mixer (ARXM) via the cache data lines. Although
not shown, the MBox response enables the mixer sclection and the EBox clock (CLK DP) loads the
ARX on the Data Path Board with the instruction. The NICOND Dispatch for this example is to
symbolic location XCTGO: Figure 2-24 indicates the major microinstruction fields. The Jump address
contains the base address of 8 4-word block used to calculate the effective address. Each microinstruction in this block is used for 8 different form of address calculation, and is selected based upon
the state of ARX14-17 and ARX13 when EA MOD DISPATCH is given. The EBox hardware utilizes
ARX14-17 and ARX13 to modify bits 09-10 of the CRAM address. This yields the possibilities listed
n Table 2-4.

Address Calculation

Table 24

CRAM Address ¥

ARNIG 17

i ARXI}

Funcoon

1
]

]

[}

TOARN

COMPE A«

Nonzets

(]

‘

Perrorm indewng as specitied by ARXIS 17

COMPLACY

Pertorm mdnecon VMA -+ ARXIA 38

Peetatm i desmg as specified by ARX14 17 then
pertorm ndirechion VMA » ARXI® 38 + (XK}

COMPEA

COMPE A3

Nontsere

While at XCTGO., to speed things up. the indexing operation is started. The fast memory address field
in the microinstruction causes the FM control to address fast memory utilizing ARX14 -17, which in
the example is I. The ADA input is enabled 10 select the ARX as input to the ADDER A input. This is
controlled by the micrainstruction ADA field. Similarly, the ADB field enables the ADB input to
select addressed FM location 1. The microinstruction AD field specifies the ADDER function as
A +B. Thus, the ADDER begins to add the contents of location 1 in fast memory to the instruction in
ARX. Al this time, the Buffer register extension is enabled from ARX by the microinstruction BRX
ficld.

NOTE

The IR comtains the op code of the imstruction
MOVE, which is 200, and the AC field, which is 3.

The op code value (200) is used to address the DRAM to obtain the appropriate word for this instruction. This word is indicated on the input to the DRAM register (5.5, MOVE).
2.3.2

Indirect Word R

For an Indirect Word request, the CRAM register contains the microinstruction fetched from COMPEA + 3 as indicated in Figure 2-25. The Jump address now specifies a direct jump to symbolic location
INDRCT. The AD. ADA, ADB, and FMADR fields are maintaining the indexing calculation and the
calculated address 000300 is forming at the input to the YMA. The MEM microinstruction field is
coded as A IND. This enables the memory cycle control to set up and generate an MBox cycle (Figure
2.26). This begins with the assertion of EBOX REQUEST IN, together with the qualifier EBOX
READ. Table 2-5 lists the MEM field function that generates requests. An IND is a function that may
be followed by a microinstruction having the MEM field coded as MB WAIT.
EBOX/2-31

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Figure

2-24

Instruction Cycle:

Dispatch « XCTGO
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Table 2-§

MEM 02 T MEM Fcld
o

)

a®

;

Function

COARIAD

FeuhtGode

Store (v de

G
i!

]
i

OREGFUNG

i
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MBox regnter retrrence

Yes

Indirect reterence dunng

AIND

: Yo

elfectve address caloulation
1

i
E

BYTLIND

LUAD AR

Indirect rercrene tor hvie
nstruction spevial

Data read dunng

Yes

exccution, loads mto AR

i1
:

; No

LOAD ARX

Dats 1esd dunng excauton,

Yes

AD FUNC

Not used

BYTI RD

Data read duning hyie

A S8

mtucton beh

MBox Wait

HETCH

i‘

Causes

BWRII

)
.

MEM 00 i

MBox Cycle Requests

execution hads intu AR
and ARX

WRITE

laads into ARX

Store data dunng execation,

Yes

waites from AR

RPW

Initiates a read PSE wine

oycle. data loads into AR

.
;

Yes

)

The time field for the microinstruction at location COMPEA
+3 specifies a period between the EBox

;

clock that loaded the microinstruction from COMPEA
43 and the next EBox clock. It allows sufficient |
time for the access of fast memory to be completed. Note that EBox request and EBox sync are
concurrent (Figure 2-26). The earliest time that the MBox can clear the request is on the MBox clock
following EBox sync. In Figure 2-26, EBox sync occurs one MBox clock prior to where the time fieid
indicates EBonx clock can occur, but hzezuse M Box wait is true and the MBox has not yet responded,
the EBox clock is postponed as indicated.

EBOX/2-37

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2.3.3

MBox Cycle

MBox Response 1o Indirect Word Request

Figure 2-27 illustrates the microinstruction fetched from symbolic location INDRCT. Again, 2 direct

Jump is sfiecified (in this instance, to INDLP). A response from the MBox is anticipated. ARX

MEM is a MACRO statement. It specifies MEM tc be MB WAIT and also selects FM as addressed by
VMA 32-35. The ARXM is actually input from both AD on the 2 input and the cache data on the |
input. The MBox response causes the EBox hardware to generate MB XFER, which selects the correct
input. In this example, the cache data lines containing the indirect word 000000,000100 are loaded into
ARX.

2.3.4

Address Calculation Continues

Referring 1o Figure 2-28, the CRAM register contains the microinstruction fetched from symbolic

location INDLP. This sctup is once again to perform indexing as though it were really specified. At
this time. ARX contains indirect word 000000,000100; ARX14-17 and ARX13 are zero. Thus, even
though the microinstruction specifies the calculation of indexing, the hardware calculates the proper

CRAM address based upon ARX14-17 = 0 and ARX13 = 0.

The basic jump address is COMPEA and this is the next CRAM address. The dispaich is EAMOD
and. on the next EBox clock. the microinstruction from COMPEA is fetched. Note, too, that the
DRAM register is latched and contains the A, B, and Executor Jump address.

2.3.5

A READ Dispatch - Set Up Data Fetch and Prefetch

Refer to Figure 2-29. Once the effective address has been calculated, what has been traditionally called
the Fetch cycle follows. The CRAM register contains the microinstructios fetched from COMPEA.
The } field is zero in this case. The EBox hardware, upon detecting a Read Dispatch, inspects the
dispatch A ficid and forces the CRAM address 1o 40 + A. Thus, in this example, the address becomes
45. Address 40 + A is defined by hardware. The cffective address in ARX18-35 is enabled into the
ADDER A input by the AD ficld coded as A, with ADA selecting ARY. To begin the data fetch, the
MEM ficld is coded as A READ and this, with the A field, generates EBOX REQUEST and EBOX
READ. On the next EBox clock, the effective address is loaded into AR.

EBOX/2-38

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MBox Response to Indirect Request

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Figure 2-29 AREAD Dispatch Setup Data Fetch
EBOX/2-43

2.3.6

MBox Response to Data Read - Prefetch Begins

Figure 2-30 illustrates the CRAM register containing the microinstruction from location 45. The: jump

address once again is zero, because the actual jump address is provided by the DRAM register jump
field. In the case of MOVE, the symbolic address is “MOVE." This location contains the first microinstruction in the executor for the MOVE instruction. Only one microinstruction is required for the
execution of the basic MOVE. This dispatch field contains DRAM 1, enabling the CRAM address
control to utilize the jump address in the dispatch register. Thus, for the basic MOVE, symbolic
location “MOVETM contains the desired microinstruction. The MEM field is coded as fetch to enable
the memory cycle control to begin the prefetch by asserting EBox request with EBOX READ.

Until the MBox response o the data read is received, the VMA is latched and only the VMA input
contains the updated PC value. When the MBox response is received, the VMA is lnaded with the
updated PC value (PC+1). At the same EBox clock, the data on the cache data lines is clocked into AR
(000100). Referring 1o Figures 2-30 and 2-31, the FMADR field enables FM to be addressed via VMA
12-35, even though in this example VMA address 000100 is not an FM address. I'M location 0 is
actually accessed and enabied via ADDER B into the AR mixer.

The Memory Cycle Control asserts LOAD AR. The address in VMA is checked ir. the VMA Control
and. because it is not a fast memory address, -VMA AC REF is asserted. Thir is passed to EBox
Control No. | logic and inhibits the generation of FM XFER.

MBox RESPONSE IM is passed to the EBox clock control where it becomes {on the next M Box clock)
RESPONSE MBox. This, with LOAD AR, enables the selection of ARM SEL 1, which enables the
cache data into AR. The EBox clock then strobes the AR register. This clock also clocks the next
microinstruction from symbolic location MOVE into the CRAM register.
2.3.7

Executor - Set Up for Store Cycle

For the basic MOVE instruction, the data word in AR must be stored in th: FM location specified in
the AC field of the currently executing instruction. The microinstructiop J field contains the base
address for the data storage microprogram. This is symbolic location STO. The Dispatch field is coded
as DISP B, which enables the B ficld of the DRAM register to modify the low-order three CRAM
address bits (CRAM 08~10). The B field is § for MOVE and this yields symbotic location STAC. If, for
example, STO was physically 60, the resulting address would be generated by logically ORing 60 with §
for a result of 65, symbolically STAC.

Referring to Figure 2-32, IRAC contains AC address 3, and is enabled to address FM because the
microinstruction FM ADR ficld is coded as ACO. This is the AC specified by AC 09-12. The MEM
field specifies B WRITE, but no request is issued. This is because the memory cycle control samples the
DRAM B field and inhibits an EBox request when DRAM BO! is a zero.

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MBox Response with

Data Word Requested

EBOX /247

Figure 2-31

2.38

Hardware Selection of ARM Data

Finish Store Cycle - Perform NICOND Dispatch

The CRAM register now contains the microinstruction from symbolic location STACK (Figure 2-33).
The J field specifies the base address NEXT and the Dispatch field contains NICOND Dispatch. This

completes the basic machine cycle by reentering the instruction cycle once again.

The FM ADR field maintains the FM address
via IRAC and theCONDfield is coded
as FM WRITE
10 write the contents of AR into FM location 3. The MEM field is coded as MB WAIT for the cases
where the next instruction has been prefetched from memory. This forces the EBox to wait until the
instruction enters the ARXM and MBOX RESPONSE is received. If the instruction is being fetched
from fast memory, MB WAIT has no effect and the microprogram selects the appropriate microinstruction to load ARX from fast memory as addressed by VMA 32-35.
2.4

PAGE FAIL CYCLE INTRODUCTION

Normally. primary memory is the MBox cache memory, secondary memory is core memory, and the
auxiliary memory is a disk or drum. Information is moved into the core only on demand (Demand
Paging). i.c., no attempt is made to move a page into core memory, and consequently words into the

cache, until some program references it. Information is returned to core memory in accordance with a

hardware algorithm in the MBox hardware. Information is returned from core memory 1o auxiliary
system's paging algorithm. Information movement across the
Storage at the discretion of the operating

gap bridging the level between auxiliary storage and core memory-cache memory is called page traffic.

The MBox, in a sense. is an interface between the EBox (processor) and the SBus. It provides individual mapping (relocation) of cach page (12 words) of both user &nd monitor address spaces, using
separate maps for cach. The MBox uses hardware siorage to access and load the mapping information.

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Finish Store Cycle,

Perform NICOND Dispatch
EBOX/2-53

h also contains a 2048 word cache for holding the data for the mapped references. On each memory
request from the FBox, the nine high-order bits of the virtual address and the type of request (read,
write} are compared with the contents of the hardware tables in the MBox. If 8 match is found, the
location containing the match also contains 13 high-order address bits to reference the physical page in
the cache. If no match is found. a $12-word “Page TableTM in physical core memory is referenced. The
word selected in this page table is determined by a d:spatch based on the original nine high-order
address bits. The 13 high-order address bits and use bits found in this word are written into the MBox
hardware table: the use bits are checked against the type of EBox reference. Four possible cases exist
bty
—

concerning the disposition of the use bits:
The page is not in core.

The page is protected from the type of request.
The page is nonexistent.

The page is in core and is compatible with the type of request.

For the first three cases. a page fault (trap) occurs; for the fourth case, the requested word is fetched
from core memory {actually words are fetched four at a time, differing only in the two least significant
address bits) and written into the cache. Concern here is with the page fault situations. The MBox
constructs a page fault word in one of its internal hardware registers, the EBus register. The word
contains information relating to the type of fault that occurred. The EBox is waiting for an MBox
response 1o its request; the MBox, therefore, asserts PF HOLD. and some time later asserts MBOX
RESPC NSE IN. When the EBox recognizes the PF HOLD signal, it forces the CRAM address to
1777. ~ his is the first microinstruction in the micropage fault handler. The EBox does not issue an

EBox Jock until the CRAM address has had time to set up. Once the address is stable, a single EBox

clock is issued to the

CRAM board to access the microinstruction.

Page Fail Handling - Functional Flow

2.4.1

Figure 2-34 is a functional flow of the microprogram page fault handler. The EBox contains a 4-bit
state register. This register, during certain instructions, hoids a number that may be used to modify the

state of the CRAM address. For instructions that do not use the State register, it contains zero.

Generally, the STRING, EDIT, and BLT instructions require cleanup following a page fault so that
they may be properly terminated. For these cases, the State register contains & value in the range of
1-7. The more genersl case is discussed here; this is where the State register contains zero. For both
cases, INSTR ABORT (coded in the condition field of the microinstruction fetched from CRAM
address 1777) performs the following functions:
TRAP REQ 1~ TRAPCYCLE |
TRAP REQ 2 ; TRAPCYCLE 2
ADR BRK INH ~ ADR BRK CYCLE

These actions are necessary to assure that the PC flags reflect the state of the EBox when a page fault
occurs during the fetch of the trap instruction, during its execution, or during an address break page
fault. A State register dispatch is given, but because the State register is clear, the base address is used
10 obtain the next microinstruction. A priority interrupt has & higher priority than a page fault (Figure
2-35); therefore. a pending interrupt is checked for first. If INT REQUEST is true, the PI Handler is

entered to service the interrupt. If no interrupts are pending. the page fault is handied. The third level
of priority is given to traps and finally to all other events being processed by the microprogram.

A page fault occuring in response to an APl interrupt function is a fatal error. Thus, when the page
fault handler finds PI CYCLE set, it sets the 1/O Page Failure flag, dismisses the failing interrupt. and
then. if possible. restores the EBox to tie state it was in prior 10 the interrupt. The seiting of IOPF
eventually causes an interrupt on the APPR error channel. The PF Handler now attempts an instruction
fetch.

FBOX . 2.5

Figure 2-34 Page Fail Handling (Sheet 1 of 2)

Figure 2-34 Page Fail Handling (Sheet 2 of 2)

EBOX/2-56

EBOX/2-57

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Process Table PF Location

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2.4.2

TRAP

Process Table References

The VMA is loaded with low-order process table location 500 and an EBox request is issued to write
the PF word (concurrently in AR) into process tabie location UBR +500. The next microinstruction is
loaded and EBox clock sets MEM CYCLE, causing MBOX WAIT. The AR is enabled from the old
PC word; the input to VMA is now 501. As soon as the MBox responds, MBOX WAIT is removed
and the cycle is repeated. This time the EBox request is to write the old PC word (now in AR) into
process table location UBR +501. Once again, the next microinstruction is ioaded and EBox clock sets

PF HANDLER

L2233

REQ

H
TRAFP HANDLTR

OTHER ACTIVITY

MEM CYCLE. causing MBOX WAIT. The VMA input is now 502. As soon as the MBox responds,
MBOX WAIT is removed and the cycle repeats, in this instance for reading a8 new PC word from
process table location UBR +502. The new PC word places the EBox in a specified mode and the first
instruction is fetched from the sppropriate handler. This completes the page fault cycle.
2.5

TRAP CYCLE - INTRODUCTION

A Trap is produced by setting either of two trap request flags in the EBox (TRAP REQ! or TRAP
REQ2). The programmer knows these flags as TRAP2 and TRAPI. The cenditions that set TRAP
REQI are equivalent to the arithmetic overflow conditions that set SCD OV. TRAP REQ2 is set by
the various pushdown overflow conditions: the left half of the pointer is counted down to -1 (no carry
out of bit 0) in a POPX, or is counted up to zero in a PUSHX. (The condition for this is the presence of
a carry out of bit 0, but the condition is detected by the microprogram and the trap request flag is set.)
Figure 2-35

EBox Priorities

Obtaining snd Adjusting the PF Word - Assuming P1 CYCLE is clear, the AR is cleared and the ECL
EBus is requested. This is to transfer the PF word from the MBox EBus register (o the AR register in
the EBox via the EBus. Because the Pl system and external or internal devices can also use the EBus,
the microprogram must force its relcase. When the ECL side is obtained, the EBox reads the PF word
into AR. The PF word, as it is constructed by the MBox, contains the physical page number in bits
14-26. The EBox must replace this with the virtual address and siso clear bit 13. The current virtual PC
is temporarily placed into ARX; the failing VMA is placed into AR while the old PC is saved in BRX.
The ECL EBus is then released. The ARX and AR are shifted to adjust bits 13-26 to be the VMA
13-26.

Figure 2-36 shows the three locations in the user process table dedicated to page fault handling.

EBOX/2-58

2.5.1

Trap Handling

The Trap Handler (Figure 2-37) is entered at NICOND Dispatch time providing its priority is highest
of the major priority events. The microprocessor NICOND Dispatch, together with four queues
arranged in a round robin priority structure, is shown in Figure 2-38. The TRAP request is served only
when no priorily interrupt requests are pending and no pag- fault is pending. It does, however, pre-

empt the normal instruction cycle. Both the user and exec process tables contain dedicated locations
for processing traps. These locations are XXX 421 for arithmetic overflow (TRAPI), XXX 422 for
pushdown overflow (TRAP2), and XXX 423 for the programmed trap (TRAPJ). XXX is replaced by
the appropriate base register (UBR or EBR), which resides in the MBox. The base register used by the
MBox is determined by the state of the qualifiers sent during the EBox request. The MBox fetches the
appropriate trap instruction and places it on the cache data lines while issuing MBOX RESPONSE
IN. The EBox then executes the trap instruction. It is possible for the EBox request for the trap
instruction to cause a page fault. If this occurs, the page fault handler is entered at CRAM address
1777 and the trap cyclc flags are pushed into the trap request flags so that the trap flags may be saved;
the 1rap cycle properly reenters at a later time.

EBOX,2-59

TRAP

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Trap Cycle

EBOX/2-61

Figure 2-38

Central-Server Model (Round Robin Prioritics)

252

Address Generation

253

PT Reference for Trap Instruction

Referring to Figure 2-37, the VMA is enabled to be input from the VMA ADDER. The condition field
of the current microinstruction cnables the number field 10 generate the process table low-order
address 420; the low-order two bits of VMA AD 34 and 35 assume the state of the trap flags.

The next microinstruction must generate the EBox request and enable the appropriate qualifiers to
appear on the E/M Interface lines. The page table reference control samples the state of the USER,
together with the special function and number bits and then asserts either MCL VMA UPT and MCL
PAGE UEBR REF for a USER trap situation or asserts MCL EPT and MCL PAGE UEBR REF for
an EXEC trap situation. The MEM field is coded to load ARX and enable the EBox request.

Assuming no page fault occurs, the MBox fetches the instruction,
places it on the cache data lines, and

asserts MBOX RESPONSE IN. The MEM cycle control samples the MEM field function LOAD

ARX 10 enable one leg of theARXM and CLK RESP MBOX enables the other leg. Thus, the instruc-

ARX on the next EBox clock. Next, op code and AC field of the instruction in ARX must
tion enters
be cnabled into the ADDER and then latched into IR. The condition field of the current micro-

instruction COND/LOAD IR unlatches the IR for one EBox cycle, allowing the AD to load into IR.

On the next EBox clock, it latches again. The final step is to perform the trap instruction. This completes the trap cycle.

2.6

INTERRUPT CYCLE - INTRODUCTION

The system must possess a true priority interrupt system that is flexibly structured and controlled. Its
operation in establishing priorities and recording and sequencing interrupt requests is essentially
instantaneous and independent of EBox action. Interrupts of high priority must be permitted to interrupt partially completed responses o those of lower priority. To maintain fast responsc, interrupt
requests should require no decoding action on the part
of
he EBox to determine
their source or
nature. Capability for dynamically varying the priority structure to meet the demands of
i
cnvironment must be available. In addition, no other system element may be designed such that its
time.
of
period
any
for
system
interrupt
priority
the
of
proper operation requires inhibition

EBOX/2-63

The basic priority interrupt level has four mutually exclusive states that can be described as Disarmed
(-P1 ON), Armed (PI ON), Waiting (Pl REQ), and Active (Pl HOLD). Figure 2-39 shows the basic

concept of the interrupt system for two channels. It is arranged in four groups, the interrupt state, the
FF configuration for two of the seven possible channels, the level enable, and the source of change
signal. In the Disarmed state, the interrupt level rejects all incoming interrupt trigger signals. By

performing a CONO Pl and specifying the appropriate bits, the priority interrupt system can be armed

or disarmed for any or all channels.

program counter, and the channel 2 subroutine continues. Interrupt channels are organized
into seven
basic levels, which are software assignable (armed): the lowest number has the highest priority within
the numbered sequence (Figure 2-40). Each channel is subdivided into finer levels or priority by hardwircd physical device numbers. As indicated, the first eight physical numbers (0-7) are assigned 10 1-8
Masshus controllers in the system. The next four physical numbers (8-11)
are assigned to 1—4 DTE20s
(10711 Interfaces). and numbers 12-14 are reserved for expansion. Finally, physical number 15,0 is
assigned 10 the 1/0 bus adapter (one exists per system, if needed).

In Figure 2-39, the processor (CPU) peri ,zms a CONO Pl and arms both channels. In the armed state,
the interrupt level accepts a trigger signal from an outside source o from an internal source, <.g.. the
APR. and moves to the waiting state (REQUEST STATE), where it remains until it is acknowledged
by the EBox. All waiting and enabled requests
are input {0 & priority network where they are compared
with the current state of the priority interrupt system. In this example, both channel | and channel 2

uesting

When service has been completed, the service routine dismisses the interrupt, restores the flags and

service, and both channels have previously been armed by a CONO PI instruction. In

addition, an interrupt is shown holding on channel 2. Thus, until it is dismissed by the processor. the
channel 2 request pending is held in abeyance. Furthermore, the channel | request causes the device
subroutine for channel 2 to be interrupted, diverting the processor to the device subroutine for channel
1. The first instruction that will be exccuted asa result of an interrupt (subroutine type service) is a JSR
instruction. This instruction saves the processor flags, program counter value, and also holds the
interrupt

Fach interrupt channel has a dedicated pair of unique locations within the EPT. These locatis
be indicated as 40 + 2n, and 41 + 2n, where n represents
the channel number. When
a device
initi
an interrupt in the KL10 system and is selected for service, the device places onto the EBus a special

function word hereafter labeled API function. This function contains information that specifies the

1ype of service required. Figure 1-32 in “ates the format of this word. Note that the format varies
from device to device, but the functions that can be specified in bits 3-5 are common to all system
devices. Function codes of0, 1, and7 cause instruction fetches from 40 + 2n initially and, depending
upon the type of instruction
+ 2n, may at some point perform
an instruction fetch from
41 + 2n.
In general, 40 + 2n contains one of the following types of instructions:
JSR
Jspe
PUSHJ*
MU0

05 CONTAG
LLCA 91420

AR THMETIC MROSESSOR STATUS REG
Bevice ox-20

EFERRED

icntn o

Figure 2-40

WAL

Figure 2-39

Interrupt Level Operations

EBOX/2-64

Typical Interrupt Priority Chain

uctions should not be used because nothing is known about the ACs when the interrupt occurs. JSR
or MUUO

are better choices.

EBOX 2-65

provided in the API function word. The dispatch is into the device handler for the Massbus devices.
The type of API function requested varies with the device or controller responding.

It is possible for the processor 10 gencrate 8 program request for an interrupt on any of the seven
channels. This permits the processor to carry out the highly time-sensitive portion of the interrupt
response. and to then create for itself 8 low priority interrupt to call for the deferred servicing of the
less time-sensitive portion at a less pressing time.

2.6.1

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Duration of Unisterruptable Intervals

Such an interrupt system is of little value if the CPU can remain in an uninterruptable state for any
significant period of time. Under normal operating conditions, the longest uninterruptable interval
must be kept short. In addition, no malfunctioning peripheral hardware or software can be sliowed to
“hang up” the CPU in a noninterruptable state.
2.6.2

All of these instructions save the flags and PC, a requirement when entering the device service routine.
If the instruction at 40 + 2n is 8 BLKX instruction, a specified number of transfers are performed, one
transfer at a time, each time returning to the interrupted program or to # higher level subroutine. On
the last transfer, the return to the interrupted program is “NOT SKIPPEDTM and an instruction is
fetched from 41 + 2n. In a similar fashion, if 40 + 2n contains a SK1P class instruction: when the skip
condition is satisfied. a return 1o the interrupted program takes place. If the skip is not satisfied. the
instruction in 41 + 2n is executed instead of the return. The API function generated by the Massbus
controller is always a function code of 2 in bits 3-5; this implies a dispatch to the physical address

Interruptable Instructions

To ensure that the Jongest uninterruptable interval that the EBox may experience in normal operation
is short, some long instructions have been designed so that they may be interrupted during execution.
First, all instructions are interruptable at indirect references during the effective address caiculation.
Second, instructions that consist of two parts may be interrupted between the two parts, a PC flag
being set to record this for later, when only the second part will be done. Third, iterative instructions,
such as BLT, may be interrupted at any point, as an AC pointer defining work still to be done is beng

AIT et

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SEXAN

The mechanism for handling the various levels of interrupt priority in the hardware, and the relation
between this mechanism and the device subroutine call and return sequence as it might occur in practice arc shown in Figure 2-41. Three channels are armed by setting their PION flags. Channel 2 has
highest priority, followed by channel 3, and finally by channel 4. Note that the execution of a CONO
Pl instruction caused the PION flags to set. Three separate interrupts occur simultaneously on channels 2. 3, and 4. The priority network is shown arbitrating the three priorities. The lowest channel
In this example, all three channels are requesting and no channels are currently holding interrupts;
thus, the channe}! with the lowest number is selected. As a result of the arbitration, the sclected channel
number is combined with the appropriate constant to form the address 44{40+2X (2)]. In Figure 241,
the device subroutine is entered by fetching and executing the instruction in EPT location 44, which in
this instance is a JSR. The request is not cieared until the program issues CONO, DEV. Notice during
the entire service routine (in this example), the requests on channels 3 and 4 are waiting for the processor. The last instruction 10 be executed in the device subroutine is @ JEN (JRST 12); this restores the

flags saved by the JSR instruction executed in 40 + 2n and dismisses the interrupt on channel 2, which
is holding off channels 3 and 4.

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Figure 2-41
2.6.4

Basic Interrupt Sequencing

Interrupt Dialogue

The handling of the EBus dislogue and processor bus requests during 1/0 instruction execution and

priority interrupts is provided by the Priority Interrupt Board, which compriscs the necessary inter-

facing logic, control logic, and registers. Initially (Figure 2-42), assume that the appropriste PION
flags have been set on the PI Board and it is now capabie of accepting interrupts. For this example, the
DTE20 will generate an interrupt for a byte of data. The drawing is divided into three sections: EBox,
control activity, and DTE20. The control activity consists of control action taken by either the EBox
or the DTE20, as appropriate.

EBOX,2-66

.
RS

Geseral Interrupt Sequencing

(highest priority) is serviced, provided it is of higher priority than the curreat level.

updated continually.

2.6.3

f
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EBOX 2-67

The DTE20 asserts one of its interrupt lines P1 1-7; this level enters the P1 Board where, as indicaied, it

is arbitrated with any other incoming requests and any holding interrupts. The Pl Board now commences a dialogue between all candidates on the selected interrupt channel. The selected channel
number is encoded in controller select (CS) lines 04-06. The function “Pl1 STRVEDTM is encoded in

CONTROL
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ns later the P] Board asserts the
function (F) lines 00-02. These signals are placed on the EBus and 200

INTERNAL

: DYt 28

PRIORITY

signal DEMAND. This signal instructs the device (DTE20) to place its physical controlier number on
a prespecified bit position of the EBus (bit positions 8-11). Each controlier, therefore (including the
1°O bus adapter. bit position 15, disks or drums, bit positions 0-7) on the selected channel does the
same. Approximately 400 ns later, the EBox drops DEMAND; however, the controller select and
function lines do not change for an additional 150 ns after DEMAND is removed. The physical
controller numbers received by the EBox over the EBus are arbitrated in much the same way as the

NTERNAL

INTERRUPY

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channel priorities. An exception is the ARP, which is an internal KL10 device, and does not fall inte
quite the same type of scheme, i.e., it does not place & physical number on the EBus; obviously this is
not necessary because it is already within the EBox. Rather, it provides a physical number directory on
the board. This device vies with the device that is selected on the basis of physical number highest
priority (Figure 2-40). Basically, the lower the numeric value of the EBus bit position onto which the
device is hardwired to place its physical number, the higher the priority of that bit. The highest physical number priority, therefore, is given to bit position 0, and the next to bit I, and so on. The highest
priority physical number (in this example only) is assumed to be that of the DTE20 (one of four such

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The P] Board now asserts the encoded physical number of the selected controlier (DTE20) in controlier select (CS) lines 00-03, the interrupting channel number encoded in CS lines 04-06, and the
function Pl ADDRESS IN" is encoded in function lines (F) 00-02. Again, the EBox waits & period of
200 nis and then asserts DEMAND. At this point only, one controller has been selected; it compares its
physical number (hardwired on its backplane) to the number received on EBus bits 00-03. Upon
determining that it is the sclected controller, the DTE20 places the required API interrupt function
onto the EBus data lines and asserts ACKNOWLEDGE and TRANSFER to the EBox. The
ACKNOWLEDGE signal causes the 1/0 bus adapter to ignore the function code “Pl ADDRESS
IN.” In the absence of ACKNOWLEDGE, Pl ADDRESS IN would enable the 1/0 bus adapter to
send its API function te the EBox, because no decoding and comparison logic exists in the adapter.
This logic does exist in the DTE20 and other devices. The TRANSFER signal specifies to the EBox
that the appropriate device has responded, and alerts the EBox that an interrupt is set up and pending.
If the API function is sent during &8 DTE20 to 10 byte transfer, this could specify that the EBox
perform a DATAI function to the DTE20; in this way, a byie of dats is picked up as indicated in

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Figure 242

Interrupt Dialogue Overview
EBOX/2-68

The case of DTE20 byte transfer is somewhat unique in that the DTE20 holds onto the EBus until the
EBox transmits the appropriate function, in this case DATAI encoded in function sciect lines 00-02 (at
this time CS00-06 = 0). The byte is picked up by the EBox, and the DTE20 generates ACKNOWLEDGE and TRANSFER once again. This completes the operation. Note that ACKNOWLEDGE
informs the 170 bus adapter not to respond to the functions being carried out. Because the requests on
channels 3 and 4 have been pending during the service routine, when the interrupt that has been
holding on channel 2 is dismissed, the priority net arbitrates between channels 3 and 4 and selects 3 for
service. This generates the address 46 (40 + 2n), and this time the instruction is an MUUO. As with the
ISR during the execution of the MUUO, the request is transferred to the channel 3 bold flag. Note that
in the example, the request on channel 4 is still waiting for service. Finally, the JEN instruction at the
end of the channel 3 service routine restores the flags and priority interrupt system, dismissing the
interrupt on channel 3. In the same fashion as with the other interrupts, the priority net generates the
address 50 (40 + 2n). In this case, however, location 5O contains a BLKO instruction, which cannot
save the flags or PC of the interrupted process. This type of instruction behaves in 8 special manner
when used in an interrupt location; the BLKO instruction performs a series of transfers to a specific
device; however, after each transfer, return is passed to the current PC value, whatever it is. This
continues until the last transfer is completed, when the instruction in EPT location 51 (41 + 2n) is
EBOX/2-69

executed. This instruction should be of the type that saves the flags and PC. and will generally enter a
subroutine probably 10 set up a new block pointer, because the current one has been expended. Note
that in the beginning some main program, perhaps the monitor, was interrupted, and now control is
passed back to it.

2.7

BASIC MACHINE MODES INTRODUCTION

In general, the KL10 permits the operation of a number of different programs, all resident in the
machine simultaneously, without interference or undesired interaction among them whether duc to an
inadvertent program bug or maliciousness. The operation of the machine is divided into two modes.
User mode and Exec mode, cach with two submodes. User mode consists of Public mode and Concealed mode. Exec mode consists of Supervisor mode and Kernel mode. The machine mode structure
and hierarchy are illustrated in Figure 2-43.

Basically, the programs of individual users operate in Public User mode, where the program can have
access 1o one of two possible virtual address spaces. If KL10 paging is in effect, the user hasaccesstoa
virtual address space of 256K words via an 18-bit virtual address, which may not be referred to by any
other user (without the cooperation of the monitor). If K110 paging i turned on, the program has
access 1o a virtual address space of 256K addressed via a 18-bit virtual address, which as previously
pointed out cannot be referenced by any other user without the monitor’s cooperation. All instructions
e
e D

that do not compromise the integrity of the system are legal: this includes the following:

CALL tMUUO}

I
I

PR‘VATE———.‘

=ll‘

l‘—————PUBLIC

READ WRITE ..

1 XFER CONTROL -7

cALL

PASS THRU | gxec

PORTAL

READ

LSELF

READ

AFER
CONTROL

WRITE

wart

XFER
CONTROL

CONTROL

The halt instruction (JRST 4)

Any instruction attempting to affect the Pl system (JEN)
Any 1/0 instruction directed at devices with device select codes below 740
Any reference to the concealed address space except for feiching of a portal instruction
All illegal instructions or op codes.

The user’s address space (when KL10 paging is in effect) is divided into 32 (decimal) sections; each
section contains 512 {decimal) pages and each page consists of 512 (decimal) words. The existence of
these pages is nominally invisible to the user program. However, the smount of physical address space
available is actually & number of these pages (at least one page), none of which need be contiguous
either in physical core or in the user’s virtual address space, although it is desirabic from a machine
standpoint 1o do so. Each of these pages can be designated public or writable by a 1 in bit 1 or 2,
respectively, in the page table word for the page. Pages that are not designated writable cause an
instruction, which attempts to write them, to trap to the monitor as & write protection violation page

tion Public bit a | in the PC word), which atiempis to transfer to a location in & nonpublic area not
containing any Portal instruction, or an instruction in Public mode which attempts to read, write, or
execute a location in a nonpublic area, traps to the monitor as a concealed violation page failure. A
Public mode program can only transfer to a Concealed mode program by transferring to locations that
contain Portal instructions. A Concealed mode program can read, write (if writing is allowed), execute,
or transfer 1o any user location designated public. Concealed mode is provided to allow the loading of
a proprictary software package together with a user’s program and data while preventing the user’s
program from copying information discerning the structure of the proprictary software. This provides
protection of proprictary software without complicated protective overlay or transfer schemes
involving the monitor and allows direct interaction between user and software package with virtually

ST CALL (MUUO)

N
LEGEND
K ] KERKEL

S | SUPERVISOR

C | CONCEALED
~C | NON CONCEALED

101613

Figure 2-43

Mode Structure and Hierarchy

no overhead.

EBOX/2-70

USER

READ XFER CONTROLIS

failure. A program running in pages designated public is in Public mode. A program running in pages

not designated public is running in Concealed mode. Whether an instruction is performed from Public
or Concealed mode is determined by the Last Instruction Public bit of the PC word (bit 7). The Last
Instruction Public bit is copied from the Public bit of the page map word for the page from which the
instruction was fetched. An instruction in Public mode (that is, one performed with the Last Instruc-

ALL

SELF

EBOX/2-71

The monitor operates in Exec mode. It is responsible for scheduling users, allocating memory and
other facilities, servicing interrupts, and performing actual 1/0. At any instant, the monitor has access
10 paging mode) or 256K (for K110 paging mode)
10 an effective address space of up to 8192K (for KL
words and by overt action may address any portion of physical memory. The monitor can be divided
into two parts: a normally small part, which operates in Kernel mode and is resident. and a larger part.
which operates in User or Supervisor mode and may be swapped as necessary.

The Kernel mode part of the monitor handles the PI system, performs the direct 1/0 for the system,
performs page management, and performs all other functions that affect all users of the system. The
Supervisor mode part of the monitor performs the general management of the system (such as MUUO
handling and dispatch) functions which affect only one user at & time. The Supervisor mode and
Kernel mode of the monitor are analogous to the Public mode and Concealed mode of the user’s
programs in that the Supervisor runs in that part of the Exec address space designated public and the
Kernel runs in that part of the Exec address space which is designated nonpublic; this simplifies iliegal
reference detection logic. Each address from 20 through 337,777 is broken up into pages. but these
addrasses can be made to refer 10 the same addresses in the physical memory space by making the
virtual page address equal to the physical address portion in the corresponding page table entry. The
entire Exec address space is broken into pages of 512 words which may be designated either accessable
or not access:ble, public or nonpublic, and writable or nonwritable and can be swapped out. An
instruction in Supervisor mode that attempts to write into a page which is not writable will trap as a
page failure. An instruction in Kernel mode may write (5. any Jocation whether or not it is designated
public. An instruction in Supervisor mode (that is, one performed with the Last Instruction Public bit
a | in the PC word) that attempts to transfer to & location in an Exec nonpublic area not containing &
Portal instruction traps to the monitor as a page failure. An instruction in Supervisor mode that
attempts to read, write, or execute a location in an Exec nonpublic area traps to the monitor. In each
instance, the trap is a K ernel violation page failure. A Supervisor mode program can only transfer.i.c..
jump to a Kernel mode program, by transferring to locations that contain Portal instructions (JRST

PUBLIC

PRIVATE

0__/‘/

~.JRST 2
\.OR MUUO

INST9e—1
7

1 —=USER

MuuC OR

10T

1~ USER

.-~
JRST 4 (PORTALY

PRIVATE

1—=PUBLIC

PUBLIC =1

INSTRe—D

SUPERVISOR

MODE

PRIVATE INSTRe— 1\\

USER e

USERe—@ ",

Puauco-fl’\

PUBLIC=—1
PRIVATE INSTR=Q/

USER CAN CLEAR BY

PUBLIC T}

JRST 2 817 6 {0}, 8UT

CAN NOTY SEV T BY
PLACING BI!T 6 (O} AND

(SSUING A JRST 2

PUBLIC (1)
PRIVATE

INSTRe—1

USER (t}

JRST 2

1
PUBLIC

PRivATE

PRIVATE

INSTRe@

INSTRe—1t

PUBLIC=—D

USER (1)

1).

BIT

A Supervisor mode program can also reach Kernel mode (or any other mode) by performing an
MU UO or other instruction that causes a trap, if the appropriate trap new PC word indicates that the
next instruction is in Kernel mode. A Kernel mode program can read, write, execute, or transfer to any
location designated public, i.c., in Supervisor mode; all instructions illegal in User mode are also iliegal
in Supervisor mode.

CONTROL OF

ASSIGNMENTS

NOTES

| B1TOS | BiTO6 | 81707

USER MODE

USER TOT

PREVIOUS CONTEXT

PUBLIC MULOE

IN USER MODE

SOSGEN

EXEC MODE

The mode control logic consists of the following:

B 107

Figure 2-44

User Mode
Public Mode
User 10T
Private INSTR

Miscellancous Combinaticnal Logic

The mode control exerts a powerful influence over the disposition of the processor. It monitors
instruction fetches from Public mode to prevent illega’ entry to cither Concealed mode from User
Public mode or Kernel mode from Supervisor. In addition, it detects the fetch of a Portal instruction
and adjusts the state of the mode logic accordingly. The relationships between the various modes and
their transfer instructions are shown in Figure 2-44. In general, two instructions allow flags that affect
processor modes to be manipulated. These instructions are:
MUUO
JRST
2

EBOX/2-72

Mode Transfer

Of the two, only the MUUO can cause transfers to any mode from any other mode. The JRST 1
(Portal 1) simply allows entry to a Private mode from 2 Public mode. Each time an instruction fetch is
cpecified and the reference is to a nonpublic page, a test for illegal entry must take place 10 maintain
integrity in the system.

Refetring 1o Figure 2-44, assume a User Public program has been started by a monitor routine that
performed a JRST 2 (a jump and restore flags). To place the processor in User Public mode, bits 7 and
5 of the flag’s PC word must be set; this results in the setting of Public mode and user mode, respectively. The processor is now in User Public mode. Assume that the User execules some miscellaneous
instructions and then performs an instruciua fetch from s nonpublic area. The following test takes
place: instruction fetch is decoded from the microinstruction MEM field or specified as a prefetch in
the DRAM A field. The E/M Interface asserts EBOX READ and loads the address into VMA. Note
EBOX/2-73

that if a reference 1o a private address for a read or write of data is atiempted, it page fails on the
attempted reference because PAGE TEST PRIVATE is asserted. However, in this case, the fetch must

be allowed from the private address space. Its identity is checked in the EBox and, if it is not a JRST |

(portal), a page failure occurs on the very next memory reference. This is implemented by delaying

generation of the signal that would cause a page failure to be generated by the MBox (PAGE ILLE-

GAL ENTRY), until the instruction fetch is completed. When the MBox responds with the level PAGE TABLE PUBLIC (PT PUBLIC), this signal with the MB response sets PRIVATE INSTRUCTION. This causes the generation of PAGE ILLEGAL ENTRY. I the instruction which is decoded
by the hardware is not a Portal, Public mode remains set maintaining PAGE ILLEGAL ENTRY
which
enables a page fault on the next MBox reference for whatever reason. If the instruction fetched

contains information specific to individual users and whose mapping accompanies the user page map.

1n other words, the physical memory corresponding o these virtual pages can be changed simply by
switching from one user to another, rather than the operating system changing its own page map. The
Kernel mode program can access all of the unpaged area without restriction and can reference all of
the accessible paged area both public and concealed, with the usual restriction that it cannot alter a
write protected arca. As in the case of Concealed mode, fetching an instruction from a public area
returns control to Supervisor mode.

isa portal (JRST 1), then Public is cleared and the processor enters Concealed mode.

All user references and concealed references are paged. The difference between the types of paged
references is that user paged references are public while concealed refesences are nonpublic when
referencing the concealed address space and may be public when referencing the users address space
Executive references are paged, this includes both Kernel and Supervisor references. Supervisor mode
programs must be capable of reading both User Public and User Concealed address spaces. To bypass
the portal mechanism normally necessary for any public program to reference a nonpublic program
area, a bypass exists, which is under control ofthe Kernel; when operational, the Supervisor is allowed
10 read and possibly write the concealed area as necessary, remembering, of course, that the supervisor
is part of the operating systema and it is performing job-related tasks within that context.

Normally a public program is only allowed to fetch an instruction from a nonpublic area and this
instruction must be a portal (JRST 1) instruction; however, this is necessary for the supervisor to
perform its system tasks. Basically, the process for checking a User Public program's reference to a

concealed address is as follows. The mode is User Public and an instruction fetch begins. EBOX
REQUEST is issued to the MBox, together vith the appropriate paging qualifiers and any other

appropriate signals. The MBox performs the necessary check of the page descriptor bits; then the state
of the Public bit
he page table is asserted
over the E/M Interface where, together with signal MB

XFER and a signal indicating an instruction fetch is being performed, it is used to enable the setting of
Private instruction. If the Page Table Public bit is off, Private instruction is set on the clock occurring
concurrently with MBox response. PAGE ILLEGAL ENTRY is not asserted. The response given by
the MBox was given at the same time it placed the desired instruction onto the cache data lines; this
insizuetion is now in ARX. If the instruction is indeed a portal instruction (JRST 1), the Public mode
will be c!=area, rzmoving the PAGE ILLEGAL ENTRY signal. This procedure then has effected the
proper eu ry 10 Concealed mode. If the instruction was not a Portal, then the PAGE ILLEGAL
ENTRY signal will not be removed nor will Public be cleared, which constitutes an illegal state in the
EBox. On the very next MBox request by the EBox \providing VMA AC REF is false), a page fault
occurs and an appropriate code is placed in the EBus register in the MBox identifying the disposition
of this fault. This will shortly be followed by a trap o the operating system as a concealed violation
page failure. This same procedure is applied to a Supervisor reference to the Kernel address space, and

in this way the integrity of the system is protected from any unwarranted references. Figure 2-4S shows
a typical layout of the virtual address space for the various modes. The space shown is for K110 paging
‘mode (256K, made up of 512 pages numbered 0-777 octal). Any program can address locations 0-17
as these are in a fast memory block and are completely unrestricted (although the same addresses
may
be in different blocks for different programs). The Public mode user program operates in the public
area, part of which may be write protected. The Public program cannot access any locations in the
concealed area, except 1o fetch instructions from prescribed entry points. The Concealed mode user
program has access to both the public and concealed areas, but it cannot alter any write protected
location whether public or concealed: fetching an instruction from the public arca autor atically
returns the processor to Public mode. The Supervisor mode program is confined within the paged arca
of the address space. Part of the public area in this space may be write protected, but the program can
read information in the concealed area. It cannot, however, alter any location in a concealed area,
whether that area is write protected or not. Pages 340-377 constitute the per process area, which
EBOX 2-74

Figure 245 Typical Virtual Address Space Configuration
EBOX 2-75

271

Mode Initialization - Private Instruction

When the KL10 system is powered up, the power control issues the signal CROBAR for approx-

imately § seconds. This results in the generation of RESET, which causes LEAVE USER to be
asserted. LEAVE USER enables the clearing of USER, USER 10T, and PUBLIC and sets PRIVATE
Figure 2-46, cach time an
INSTRUCTION. This action places the KL10in Kernel mode. Referring to
instruction s fetched from either Fast Memory or Core Memory (via MBox), the private instruction

recirculation path is broken (Figure 2-47)

1f the instruction is fetched from a nonpublic address space (-PUBLIC PAGE), or the mode of the
‘machine is not public (-PUBLIC), then the private instruction is enabled to be set once again (Figure 2-

48).

Note that if data is read or written, the upper recirculation leg (Figur= 2-48) is not disabled. The
Private Instruction flip-flop is used with additional logic that (with the exception of previous context
references) detects references to Public mode; together, these clements detect entry 10 a privileged
address space. The Kernel may access any part of the address space regardless of ts type. Because the
Kernel does not operate in Public mode, illegal entry has no significance.

272

Loading Flags and Changing Mode

Tvo instructions can change the mode of the machine. These instructions are MUUO and JRST with
AC bit 11 set. ie., JRSTF.

As indicated in Tabic 2-6, AR hits 05 and 07 are used in various combinations to enter appropriate
submodes.

In addition, for Direct User 1/0, bit 06 (USER 10T) is available to allow the running of privileged
user programs with paging in effect. This mode provides some protection against partially debugged
infrequently used device service routines as a user job. Dircct
monitor routines, and permits running
control by the user program of special devices is particularly ‘mportant in real-time applications. A
special MUUO is available to enter USER 10T mode, but i, s privilsged because time-sharing is

effectively stopped while in this mode.
273

User Public Mode

Once the processor is in User Public Mode (Figure 2-49), the user program can frecly read and write
data in the user public address space with the cooperation of the system. When demand paging is in
effect, each reference to a previously unreferenced page causes an access page fault. The operating
system page manager must assess the fault, obtain the page from mass storage, and build an entry in
the user's process table.

Assuming that the current user's process table (PAGE TABLE PART) is initially clear, the first refercace causes a NOT IN CORE page fault (Figure 2-50). The EBox, upon detecting the PAGE FAIL
HOLD signal from the MBox, enters a microcode page fault handling routine that communicates the
requests the page from
failure 1o the operating system. Next, the page manager or a related routine

mass storage. When the page is in core, the appropriate process table is constructed and the reference

by the user program may be tried once again (Figure 2-51).

The MBox performs the reference to the process table; the use pits now reflect the following:
PAGE IS IN CORE A = |
PAGE IS WRITABLE W = |
PAGE IS PUBLIC P = |
PAGE SHOULD BE CACHED C = |
Figure 2-46
EBOX2-76

Mode Initialization

EBOX 2-77

A
o

L occun

Instruction being performed is MUUO JRSTF (Sex Note)

Enable

PREVCONTXT

User 10T | Flag Bits | _Effecting Modes

AROS | AROY

ARO6

O T

)

]

Figure 2-49

ustn oot
CONCIALLD

User Mode Functiona! Flow

NOTE

user by placing bit 05 (0) but an MUUO may
A JRSTF may not clear

EBOX/2-78

EBOX 2-79

The entry (one of cight half-word entries fetched) is written into the page table in the MBox, the MBox

then performs the data reference part of the request. This can involve reading or writing and depends

upon the type of EBox request. During the reference, PAGE ILLEGAL ENTRY was not asserted
hecause the reference made by the user program was to a public page and it was for an instruction.
2730 Entry from User Public Mode to User Concealed - To correctly enter User Concealed mode,
the User Public program must exccute a Portal instruction (Figure 2-49) from the concealed address
space. The EBox generates the EBox request and provides the MBox via VMA with the concealed
address. The MBox either finds the page entry and use bits in the MBox Page Table (hardware) or
performs a refill cycle to obtain it from core memory. Figure 2-52 shows the typical Concealed Page
Table format_ Presumably, the entry is nonpublic and write protected, and may of may not be cached.

Figure 2-52

Typical Concealed Page Table Format (Half Table Entry)

The MBox asserts PT PUBLIC (0) and MBOX RESPONSE IN to the EBox. Referring to Figure 2-48,
MB XFER resulting from MBox response and -PUBLIC PAGE resulting from PT PUBLIC (0)

cnables the setting of Private instruction. The instruction fetched by the MBox is in ARX at this time.

If st is a JRST 1 (Portal). its execution clears Public and the processor enters User Concealed mode. If
the instruction is anything else, Public remains set and the next MBox reference occurs with PAGE
ILLEGAL ENTRY true, PUBLIC PRIVATE INSTR (1); this causes a page failure.

2732 Concealed Violation Data Reference - If a User Public program references the concealed
ddress space for read or write, PAGE TEST PRIVATE is asserted during the EBox request and
results in an immediate page fault. Page Test Private is a signal composing Public and -INSTR
FETCH

2.7.4

Restoration of Programs by the Supervisor

The Supervisor portion of the operating system deals with those tasks which affect one job ata time. It
must. therefore, have the ability to restore various programs o an operational status, ¢.g.. by executing
that picks upna PC word consisting of the appropriate flags in the left half and a
2 instructio
+ JRST
virtual PC in the right half of the word.

Figure 2-51

User Mode Public Second Reference

2741 Restoring a Concealed Program - The Supervisor may restore a concealed program providing
it also sets User. Referring 1o Figure 2-53, while executing a JRST 2 instruction, LOAD FLAGS is
is off
field of bit 04, and this together with -User (User
in the magic number
derived from the presence
in Supervisor mode), and AD bit 05 (which will set User) generated CLR PUBLIC. Thus, on the next
clock pulse, Public clears and User sets, restoring Concealed mode. Figure 2-54 shows the necessary
conditions. Note that performing a JRST 2 cannot generate Leave User, unless the processor is in
Kernel mode

EBOX /2-50

EBOX 2-81

|§

ves

PAGE TEST

PRIVATE- 1

PusLIC-

ILL ENTRY- 1

ILL ENTRY(N)

[sups AVISOR]
o

NEXT MBOX REF

PAGE FAULT
WILL OCCUR ON

PRIVATE
INSTR- 1

AC REFERENCES.
NOT EFFECTED.

]

SEE NOTE

CLEAR PUBLIC

usen oD wo E

WILL PAGE FAIL

- O
ILL ENTRY

THIS REF

PRIVATE

INSTR- )

KERNEL MODE

ARo7()

USER MODE

ruBLIC

ARO7(Y) & AROSIY)

USER MODE

CONCEALED

USER MODE

PUSLIC 10T)

AROS(

USER 1ODE

CONCEALED (10T)

NOTE 1

IF THE SUPERVISOR FETCHES
AN MUUO, MODE CHANGES.
ACCORDING TO FLAGS.
101623

Supervisor Mode Functional Flow

EBOX/2-83

Figure 2-54

2742

Leaving User

Restoring a Kernel Program ~ The restoration of a Kernel mode program from Supervisor

mode is somewhat different in its mechanics than the restoration of the Concealed program. Basically,
the Supervisor must first perform a JRST 2 instruction; this instruction restores all flags except for
Public. The JRST must enable the fetching of a Portal instruction that clears Public, placing the
machine in Kernel mode. This is a safeguard in the event that the Supervisor mi
restore some random set of bits and cause the Kernel 10 be disturbed. In addition,

Kernel mode at a known and unique entry point. Figure 2-55 shows
that it is not possible for a JRST2

instruction to clear Public while

not setting User as well. Note that a JRST 2 instruction does r.0t

generate Leave User unless it is given in Kernel mode. The conditions which enable Leave User are
indicated on Figure 2-54

Figure 2-55

2743

Restoring Kernal Program

Restoring a User Public Program - To restore a User Public program, the Supervisor gives a

JRST 2, which sets User. This is the only requirement because botk Supervisor and the User Public
program run with Public set. The special field function SPEC FLAG CTL, together with magic num-

ber 04(1) enables SPEC/LOAD flags which, with AD bit 05, enables User 10 set on the next clock.

EBOX 2-85

2.7.44

Saving Flags and Leaving User - It is not generally known at just what moment an interrupt

will occur with respect to execution of a given instruction. The microprogram governs the handhing of
interrupts by looking for interrupts only at certain times. In general, an interrupt is sampled for
between each instruction and during certain classes of instructions. The following classes of instructions can be interrupted:

ergct o

{

USEM PUBLIC,

LINSTRLCTION

INSTR FLAGS

Byte Instructions
Block Transfer Instruction
Input/Output Instructions

3
{
:

In addition, for any instruction. an interrupt is sampled during the portion of the microprogram that
performs indirect addressing (INDRCT). An interrupt has higher priority than a Page Fault and thus,
upon entry to the Page Failure microroutine, an interrupt condition is tested for: if found. a dispatch

r— ENTRY TO XERNEL

When an interrupt occurs and the Pl logic has completed the handshake, it informs the EBox by
asserting a signal PI READY. This results in the microprogram generating a skip 10 a microinstruction
that asserts SPEC/SET P1 CYCLE. As a result, Kernel cycle (normally false as long as PICYCLE is
clear) sets. and MCL VMA PUBLIC is disabled. This is necessary to disable the MCL PAGE ILLEGAIL. ENTRY signal when Pl CYCLE sets because the interrupt instruction, which will be fetched
from a Kernel address, must not generate a page fault.

When the interrupt instruction is being fetched, User and Public may be set, or Public alone may be

®ERNE.

MULO

would be set at this time and represent **Previous Context User.” This is an indicator to the hardware
that previous context references must be in User mode. In any event, the processor enters Kernel mode
and begins to handle the interrupt.

[

USEN CLEARS
PRIVATE

InSTR SETS,

romta

SoRTAL

PUBLIC CLEARS |

PRIVATE

iwstmsris.

PUBLIC CLEARS

USER

KERWEL

SUPERVISOR

RXERNEL

CONCEALED |

REANEL

®”
RERNEL

KERNEL

{ COMCEALED

USER

+
i

;

{suseAvisom |
:

RESTORE A USER PUBLIC PROGRAM

RESTORE A

LEU-PEOL
xFER

77T T

;._____ ]

{meap om vmiTE paTa
[

N
JRERD DATA ]
:

:
i

FETCH

READ OR WRITE DATA

LEVEL

XFERA

READ OR WR:TE DATA

PORTAL

INSTR

L I¥i51e]

|
i

USER

RESTORE A USER
IC PROGRAM
PUBL

CONCEALED

}

KERWEL

CONCEALED PROGRAM

weuBLi

USER

(PUBLIC)

10-1826

without allowing the user to discern the composition of the concealed program. For example, assume a

Figure 2-56

Mode Hierarchy

read or write into this program.

In some computer systems, complex overlays in core memory are necessary to assure conceslment of
the program from its users. In the K110, this program has been solved by creating two submodes from
User mode. each with separate powers and cach separate from the other. Both modes, however, run
with User on. Figure 2-56 indicates the hierarchial structure present in the KL10 processor. The User
Public program can only transfer to a concealed program at a sclected entry called a Portal. The
instruction fetched must be a Portal instruction (JRST 1). The concealed program can read or write
data to the Public area. Figure 2-57 is the Concealed mode functional flow diagram.

EBOX2-86

wNODE

2.7.4.5 User Concealed - This mode is useful for running certain proprictary programs in User mode
user has developed a program that performs circuit analysis. The user is a time-sharing house and
desires that this program be available to users for execution only, that is, the user must not be able to

NEW

MODE

SUPERVISOR

xsgr

why MCL PAGE ILLEGAL ENTRY is disabled (by setting PI CYCLE). At the time of the interrupt,

detaches the feedback path for User, User 10T, and Public. In addition, if User were set, User IOT

FFECY
B ’“_“‘NO EFFEC

MuuO

FETCH

INSTA SETS

. ugo

|READ OR wR:TE Data

CLEARS,
| PUBL(C
I::?‘:.ST(!\’S

IAELLANAY

INSTR

LEVEL

BUyo

:
B

- PORTAL

set. In the last instance, a page fault would result if some action were not taken 10 prevent it. This is
the state of the current user ACs is unknown. The instruction in 40 + 2n, therefore, must not disturb
the ACs in any way while transferring the flags and PC to the Kernel mode subroutine. Therefore, JSR
is a likely instruction for use in 40 + 2n. The JSR instruction causes the flags and current PC 10 be
stored in the effective address of the JSR instruction and then enters the subroutine by performing an
instruction feich from E + 1. After calculating the effective sddress for the JSR instruction, the microprogram performs a write test which, if successful, is followed by a branch via the DRAM J field to the
executor. Now the flags and PC are loaded 10 be copied into the AR for storage and are then disabled.
The microinstruction asserts SPEC FLAG CTL; this with PI CYCLE generates LEAVE USER, which

CLERR PRIVATE

WUUO

;

T PUBLIC AND USER |

RESTORE &

T KERNEL PROGRAM

to the microroutine for interrupt handling is given.

AND PRIVATE

}i
T

EBOX.2-87

USER MODE
CONCEALED
P
e———

-————

ne ‘
)

ves
i

,"'

;

vis

i ovis

; SEY NOTE 1

suBLIC Y

PRIVATE INSTR - O
T

*
—————————
USER MODK

NOTE Y

THE CONCEALED PROGRAM MAY

FRELLY ALAD DATA FROM Taf
S SPACH AND
PUBLIC ADDRE
MAY WRITE (NTO 1T

PROVIDING

THE ADDRESS SFPACE 1S wRITE
ENABLED

PuBLIC

Figure 2-57

2.8

Concealed Mode Functional Flow

ADDRESS PATHS

The address paths contained within the EBox are illustrated in Figure 2-58. Thesc paths are implemented to facilitate the formation of the appropriate MBox virtual address. This address is transiated
by the M Box for KI paging mode and by the microprogram snd the MBox for KL paging mode. The
MBox can generate the following two basic forms of physical addresses:
1.
2.

Refill Address (Relocated)
Physical Page Address (Paged)

The VMA serves as a source of data when loading the following MBox registers:
1.
2.
3.

User Base Register (UBR)
Executive Base Register (EBR)
Cache Clearer (CCA)

In addition, it serves as an address and data source w hen loading the cache refill RAM. As indicated in
Figure 2-59, the VMA has the three jollowing basic sources of input:
1.
2.

Previous Context Section register (PCS)
Vintual Memory Address Adder (YMA AD)
Adder (AD)

The following two major addressable areas are addressed by the VMA:
1.
2.

MBox
Fast Mcaory (FM)

EBOX/2-88

vean

RUCHCULATID

HO0 BEOE

0
v

woor

wanma

WAz 38
TM ADONISS.

ywar

woot

wan no
AR
¥ ADORLSS.

usta PURCE

wwan

wan

sicr

SR PUBLIC

KL PAGING

——

I PAGING

s
ac

€

TM ADDRISS

WAL
v ADORESS

USER COMCEALLD,

USUR CONCEALED.

wan

1 17 siCT
WA

170

A
1 26
VIRTUAL PAGE

THESK REGISTERS MAY ACTIVELY BEINVOLVED
1% SOME FORM OF ADDHESS CALCULATION WHICH

OUAD wORD.

USER CONCEALED.

D
INTO VWA
WILL ULTIMATELY BE PLACE
USED DURING KL10 STYLE PAGING ONLY

VA2 35

“

non

USER CONCHALLD

THISIS THE GENERAL SORMAT ONLY

T0 FORCE PC+1 0K PC+3
USED

Figure 2-58

EBox Address Paths

Casnep
e

b
£

’ °
g Q
:

!
?
i

TRCI
T
Y

ot
seochison intiss )

Figure 2-59

wontow

srass

a0 v wouo

|
ms

Typical VMA 13-17 Manipulations

EBOX/2-91

|
|

|
|
|

The MBox may be addressed logically by two types of addresses. Within each type (18-bit and 23-bit
addressing) is a class of process table addresses. These addresses arc identified to the MBox by the
qualifiers asserted during the EBox request (Table 2-7).
Tsable 2-7

Addressing Information Supplied

Class

Type of Address

VMA 1L 17=0

K1 Paged

15-Bit

K1 Provess Tabke Peterence

1.8t

Virtual Address (lassification

‘

K1 Paged

K1 Provess Tahie Retetence

VMA I8

26 = Virtual Pace

VMA 27

3% = Quad Wand

VMA 13

17 = MBos Jenoues

VMA 18

26 = MBon fgnores

VMA 27

38 = Pravess Tablke Bond

YMA 2

17 = Virtual Sectien

VMA IS

26 = Vintual Page

VML 27

3 = Quad Wand

VMA 13

17 = MBon Ignores

VMaA (% 26 = MBox lenores
VMA 2T 38 = Prawess Lable Retetetne

NOTE

There are several other special YMA combinstions. These will
be covered elsewhere.

Virtual Memory Address Register

The VMA is loaded during an EBox request and remains latched until the M Box responds (Figure 261). The VMA is a 23-bit register that accepts input from a double mixer arrangement. Thus, the
incrementing or decrementing is performed in the register itself. When both VMA SEL 2 and 1 are
clear. the lower mixer is enabled into VMA. The level VM
A « AD selects AD as input. The default is
VYMA AD as input.

In general. the VMA AD) contains one of the following:
PC (18-3%)
PC+1 (18-38) + (1}
PC+2 (18-15) + (2)
Process Table Address (27-35)
Fast Memory Address (32-35)

The AD contains one of the following:
Effective Address
@ Word Address
Some Special Address

The VMA Held register is loaded during each M Box memory request [MEM 02 (1)]. The left-most 12
bits of VMA Held are loaded with the request qualifiers, type of paging, context of the reference, and

various other signals asserted during the request. The right-most 23 bits of VMA are preserved in
VMA Held right. The contents of VMA Held are used during KL Paging mode to buffer the request
state while the page fault handler sets up an MBox Page Refill cycle. This operation is generally
described in Subsection 1.2.4.2, KL Style Paging and is described lster in greater detail.
The first three selections (Subsection 3.2.1) enable the output of VMA into the VMA register for any
of the following seiect codes:

For lh;se process table references the EBox supplies valid addressing information only on VMA bits

27-35. The MBox replaces VMA 13-26 with the PMA mixer 14-26 to generate a proper physical
address.

2.9.1

DATA PATHS

The specific address and data paths in the EBox are iliustrated in Figure 2-60.
The functional ciements in the address path between the VMA at the MBox/EBox Interface and the
primitive address source involved in forming the virtual addresses are:
Virtual Memory Address Register (VMA)
VMA Held or PC Mixer

VMA SEL 2 (0) and VMA SEL | (1) - Increment
VMA SEL 2 (1) and VMA SEL 1 (0) - Decrement

VMA SEL 2 (1) and VMA SEL | (1) - Hold

292 Program Cownting
The PC is normally loaded from VMA at NICOND Dispaich, except when PI Cycle is true; this
prevents alteration of PC during priority interrupt handling. When the processor is ready to fetch an
instruction in sequence, the incremented PC address is supplied to VMA via the VMA AD. The VMA
then supplies the address 1o PC. Thus, program counting is effected by the loop
of
VMA AD

VMA. and back to the PC (Figure 2-62).

P of PC.

)

When a skip condition is satisfied, this loop is used to advance the PC during the instruction execution
cycle. The PC, therefore, is automatically updated at NICOND time and if the skip is satisfied, it is

VMA Held Register
VMA Previous Section

updated a second time, pointing PC to the location two beyond the current locstion.

VMA Mixer
VMA Adder (VMA AD)
SCD TRAP Mixer
ADDER (AD)

Arithmetic Register Extension (ARXM!)
Arithmetic Register (AR)
Program Counter (PC)
Microinstruction Number Field
Other Miscellaneous EBox Registers

The PC output is available to the AD for saving a return address in a subroutine call JRST, MUUO,
or similar instruction. Generally, the address saved should be for s return to the next instruction, i.e.,
the instruction that would have been performed had the call or jump not occurred. However, if an
instruction is terminated because of a page fault or interrupt, the current address must be saved for a
later return to the beginning of the interrupted instruction.

The appropriate virtual address is formed by the VMA under explicit control of the VM
A control and
the microprogram.

EBOX/2-92

EBOX/2-93

THIS PAGE

CONTINUED AND/OR
ENLARGED TO
THE RIGHT

|
‘

[
|
(|

I
1

;

‘ |

Figure

£4

= T 0 4 & = I3 w
o

MA g% of
o

EBox Data and Address Paths

EBOX 2.95

Figure 261

Figure 2-62

293

VMA Inputs

Program Count Loop

Loading PC

New addresses are always supplied to PC via the VMA regardless of the point of origin. The update of
the PC or its inhibition is controlled by the microprogram. The following conditions cause PC+1 INH

1o set, inhibiting the update of PC via VMA AD:
Priority Interrupts - Setting PI Cycle

Console Instruction Execution

Halting the Processor - Halted

Performing the Trap instruction in prccess table location 421, 422, 423
EBOX 297

1 i€ PC is loaded at NICOND Dispatch time

(Figure 2-63). providing Pl CYCLE is clear. In addition,

the special field function LOAD PC may also be used to load PC from VMA. During page fault
handling. the SPEC/LOAD PC function is used to save the failing virtual address (VMA) in PC while
saving the current PC value in ARX. Basically, the MBox builds a page fault status word in its EBus
register. The physical page number is stored in bits 14-26 of this word, The EBox page fault handler

niust replace this address with the virtual page number in VMA 14-26 and then store the updated page
fault word in user process table location S00. The operation is a: follows

Simplified Microprogram Steps Re” PF Handler
1.

294

General Data Path Organization
ded into four major area

The data path (Figure 2-60) 15 diy
1

Fast Memory and Fast Memory Address Logic

Virtual Memory Address, Program Counter and related logic. 23- and 18-bit logic
3

Anthmetic logic - 36-bit logic

Instruction register - 12-bit logic

All of these areas derive control functions from specific fields in the microinstruction.

ARX« old PC, PC . failing VMA
AR «-EBus Register: PF word

BRX~ARX; old PC- ARX AR; PF WORD

Table 2.8

Data and Address Path Breakdown

Major Area

AR« PC: failing * MA

s listed in Table 2-8.

Microfield
FMADR [yl

At this time, the / R and ARX are Ref PF Handler shifted in such a way as to discard the
physical page numcer and align the proper virtual page number in AR 14-26

COND M Wore

Virtual

Menms

VMA bield

- =
CONDVMA

A second case is where SPEC/LOAD PC is used while halting the EBox. In this case, either a Console
Halt was issued via the 10-11 interace, or a Halt instruction was performed in either user IOT mode or
Kernel mode. The VMA is loaded vith the current PC and the PC is loaded with the effective address.
currently held in VMA. At the time «f the halt, the PC value in VMA points o an address one greater
than the location containing the Hal' and the PC contains E. PC+1 INHIBIT is set to prevent premature incrementation of the jump ¢ ddress now in PC

+ 1y fsee Note)
CONDVAA DEC

CONT

W MA TN

COND/LDVMA HILD

VMAKLLD

COND AD

WOFLAGS
Y LEET

Flags

CONDPOF

SPECLOAD

WCRIGHTY

DISPNICOND with PICycle (0)

[

COND/LOAD IR

SCAD Field
|

Anithoersc

36-Bit

Logc and 7281t Logic

SCADA Ficld

SCADB Field
SC

Field

AD Field
ADA

Field

ADB Field
AR Field
728t Operations Requite SPEC

ARX Field

AD Long

BR Field

BRX Field
MO Ficld
|

St Field

ARMM Faeld
NOTE

of the
by the kow order three bits
1 is & constant sekected

Figure 2-63

PC Loading or Inhibit

EBOX/2-9%

COND code

EBOX,2-99

Table 29
295

General Data Path Mixer Selection

The microinstruction or microword consists of 75 bits including parity. It is organized into variable
length ficlds that are used to control the data path and control sections of the EBox. In the following
pages cach field is described functionally in terms of the particular logic with which it is associated

29.5.1 AD Field - This field consists of six bits and is used to control the main adder (AD and
ADX), that is constructed of type 10181 Arithmetic Logic Units. Table 2-9 lists the ALU functions
The low-order four bits specify one of 16,0 functions. These functions are Boolean or Arithmetic as a
function of bit 1 (the mode bit). If bit 1 is a one, the functions are Boolean; if zero, the functions are

ALU Functions

BOOLEAN
aN

BOOLEAN
S

FUNCTION

CARRIES

AWE

AHABI

AHAB)

[

Arithmetic. Bit 0 is the carry in, when true it adds +1 1o any Arithmetic function

For Boolean functions, the carry in can cause a carry out if the corresponding Arithmetic function for
the same S-bits would have produced a carry given the appropriate inputs. For example, assume the

AvH

AVE

AHAVE)

AD function to be performed is A and the A input equals 777777777777, The Boolean function A
peforms the Is complement of the A input, which yields a result of 000000,000000. The corresponding
Arithmetic function is A and thus, if carry is true, this yields A + 1. Using the existing A input

777777.777777 +1 gives a sum of 000000,000000 and a carry. If the Boolean function A is given and

carry in is true, assuming the same A input as above, the function out is 000000,000000 and a carry 1s
gencrated.

The 10181 may be thought of as concurrently performing the Arithmetic operation specified and the

Boolean operation specified; the sum, however, is not aflected when the Boolean functions are implemented. yet the state of Carry Generate and Carry Propagate will reflect the Arithmetic result that

TR |
T

[

)

Woe

AVH

(AB)
+ (AVB)

AVE

\OK

ABI

(AVE)
+ (AB)

AVE

A+ IAVE)

ABI

o«

would have formed the sum.

-64 is an overview diagram ofthe ALU logic. Tablc . 10 lists the ALU functions, with carry
GEN = A (S B + 5,B)
PROP = A +S,B +S:B

Signals GEN and PROP are used in each digit to generate the output

al Fn. In the logic mode,

carries are inhibited on the output stage, and the logic function F is gi
¥ GEN v PROP (XOR)

(The output function is the Exclusive-Or of the two internal signals GEN and PROP).
When adding two numbers, in the absence ofaCARRY IN, the Exclusive-Or function is the function

required. A CARRY IN signal always complements this in this circuitry by controlling the final Exclusive-Or on the output stage.

ARITHMETIC

1 Arithmetic Logic Unit Description

CARRIES

FUNCTION

A +IAB)

At AB)

A(AB)

20A

AVE

AVB

(AB)
+ (AVB)

AvE

A+B

ALAVB)

A+(AVB)

AVE

AB1

(AVE)
+ (AB)

A+ (AVE)

-t

)

CIRL T

NOTE.

3%A

1 CIN i true, 884 +1 10 the given arithmetsc functson. Camy outis true & the adder .
extended left, would need carry ia 10 gemerate the correct fusction.
give the mme.
FUNCTIONS
Carry Out i mot affected by the mode (Le.. BOOLEAN

carry ay the ARTTHMETIC FUNCTIONS).

EBOX 2-100

EBOX 2-101

The MC 10181 carries out an addition by converting the two numbers at A and B 10 two alternative
gnals GEN and PROP, given by
GEN

PROP =

1.5,
= 0)

A+B

1.5:=0)

Fou exvemple

then

0011

0101

01l

0001

SUM

1000

A+B

(GEN)

(PROP)

Adding any two numbers A and B is equivalent to adding the two functions AB and A +B. However,

the ads antages of the second part are that one (AB) shows when carries should be generated. while the
other (A +B) shows when carries should be propagated. The final sum is the XOR of the two numbers
(AB and A+B), complemented by the CARRY IN signal.
GEN = A(S,B + 5.B)
PROP = A + S, +S.B

Figure 264

ALU Overview

These two equations show that PROP is generated whenever A is true, which is a requirement for
GEN 10 be truc, i.c.. GEN implies PROP, and thus whenever GEN is a one, PROP
is also a one, and
thus GEN plus PROP must generate a carry.

Table 210

+
1

ALU Functions With Carry

PROP
o

Asithmetic

T CARRY LOW

ArAB
anap

CARRY HIGH

Avl

{
|

A Al

Asi

)

A v|

AHAVE)

A HAVER |

AB
A

ABAVE)

0
AR

AVE
ABI

AB
A

AVE

AB
AB

ABsAVE)

AMAVE)
1

AB |

SRS SRR RS, e
|

Al B

)

GEN s sufficient indication of carry generation. Similarly. PROP is sufficient indication of curry
propagate

High Logic

LogkFn|

VBl

Actually. the circuil was designed 1o promote understanding for low logic, and the descriptions and

tables given in the literature are far clearer for this case.

Although the circuit does give the correct answers for high logic, the circuit does operate on the low
signals. Thus. an addition can be considered as an addition of the zeros,
with carry generated from the
addition of two zeros, and propagated. as before, by the XOR of the two numbers.

00110

ABrAVEN
A HAVER

o011

NOR

10001

AR
A"
A

11101

PROP

COUT-

10000+

Gatlow

COUT=

10001

Cany (high)

NOTE
z

sl ih e exceps
GEN and PROF.

EBOX 2-102

EBOX 2-103

The correct answer. therefore, occurs when Cin is asserted to the least significant bit. This can be
viewed in two ways:

Carry is asseried high. In this case, the function considered above is Fn = A plus B and carry

input adds a one. This is simple, but GEN and PROP meanings become obscure {especially

when passed through the LOOK-AHEAD CARRY biock).

Generate = > (G = High and P = High)

the microcode.

Example: A - Function 20

Intial Conditions: AR = 010]10l, 101010
ADA Field Function = 0

The function A performs the Is complement of the data in AR (Figure 2-67). The AD function output

Propagate = > (G = High)

The following examples illustrate various operations that might be performed using EBox registers and
the ADA or and ADB input mixers. No guarantee is made that the operations illustrated are used in

Carry is asserted low. In this case. the above function is Fn - A plus B plus 1. and the carry
input subtracts a one, but hardware is simple to follow:

1s 767676.676767. Note that ai this time the Carry In is false. No carries are generated in this example
because the corresponding carries function is A (Table 2-9).

Fxample: AB - Function 24

Innial Conditions: ARX = 777772,7177777
FM = 7777771777776

Generate = > (G = Low)
Propagate = > (P = Low)

To functionally describe the use of the various Boolean and Arithmetic functions, it is first necessary 1o
define two other microinstruction ficlds which are used to enable various data to the AD A and B
inputs. The first field is ADA, a 3-bit ficld. ADA can select the inputs shown in Figure 2-65.

.»
twak

ADA Field = 2
ADB Fieid = 0

TfIl

wa e

LHPE LY

VA
=

Figure 2-45

ADA Example

Figure 2-67

The sccond field is ADB, a 2-bit field. ADB can select the inputs shown in Figure 2-66.
3D Iulfy

TALT WEWOR>

LN
aw

FORR)

swoBES. B ante

Pa0 2 ety AlvE
ey

Fee

Function A

The Beulean function A B performs the logical AND f the complement of A with the complement of
B (Figure 2-68). The value in ARX is selected on the ADA input mixer (777777.777777) and the value
in some addressed fast memory location is selected on the ADB input mixer (777777.777776). The
result presented to the function output is 000000,000000. Referring to Tabie 2-9, the corresponding
Boolean carries function is A v B; carries are generated for the given values of A and B. For any values
of A and B, no carries are generated.

Example: AB - Function 36
Initial Conditions: AR 000000, 100001
BR 000765.100070
ADA Ficld 0
ADB Field 2

Figure 2-66

ADB Example

EBOX/2-104

EBOX/2-108

The Boolean function A produces (at the function output) the value 8t the ADA input (Figure 2-70). In
this example. the result is 000000,000100, but notice that the corresponding carries function is A - 1.
Subtracting 1 from 000000000100 is equivalent 10 adding -1, which is 777777.777777 in 2's complement notation. The result gives a carry out of the most significant bit of the AD (CRY 0). Thus,

ENCTON

although the sum represents the ADA input 000000,000100, a carry is generated.

PRV

FNIT N

B EIET 38 341

Figure 2-68

Function AB

The Boolean function AB performs the logical AND of A and B (Figure 2-69). The value in AR
(000000,100001) is ANDed with the value in BR (000765,100070) and the result presented to the

Figure 2-70

function output is 000000,100000. Referring to Table 2-9, the corresponding carries function is AB - 1

and. given the existing inputs, it can be demonstrated that a carry from the most significant bit results
if the AND of any two values results in a nonzero sum. The following demonstrates this:
000000 10000

1oe

2.9.52 ADA Field - This ficld consists of three bits and is used with the main ADDER. Referring to
Table 2-11. the low-order two bits select AR(0), ARX(1), MQ(2), and VMA HELD or PC(3). The
high-order bit is used as a disable. This bit also controls ADXA. When the high-order bit of the ADA
field is zero. ADXA selects ARX and when it is one, it selects zeros.

2000765, 100070
OO

2.9.8.3 ADB Field - This field consists of two bits and is used in a similar fashion to that of ADA in

conjunction with the main ADDER. Referring to Table 2-12, the selection is as follows: FM(0),

TITITIITIINIT

BR*2(1). BR(2), and AR*4(3).

0000 NiTITT

AB Example: A - Function 37
tnitial Conditions: ARX = 000000,000100
ADA Field = 2

Tabdle 2-11

CRAM

:
[

i
i

CRRRY S

GENERATED

Fin

QTR

]

I g

T
i

- f %08

ADA, ADXA Selection

- ———— {.

Function A

i
I

AUS

;

ADASource

T AKA

)

ARN

P
[iN

‘.

ar I [#he 24 L RIelne2 o) I

Figure 2-69

Function AB

EBOX,2-106

_—— -

EBOX/2-107

—
[P

ARX

!
|

AR\
[

SEIN

APXA Source

Table 2-12

CRAMADE

ADB. ADXB Selection

ADNB Source

ADB Source

ARN®4

BRe:

—

tutiuwedt

;

HRAS?

BRYS

ARA®3

In addition, ADB directly controls ADXB utilizing the same 2-bit ficld. Here the selection is unused
(0). BRX*2(1), BRX/2(2) and ARX®*4{3). Although AD and ADX together with ADA,ADXA, ADB,
and A DXB normally function concurrently, information in ADX does not affect AD unless so specified. Carries from ADX must be specificaily enabled to AD in order 1o affect its sum.

2.9.54 AR Field - This field consists of three bits. Figure 2-71 details the breakdown of various
combinations of CRAM AR Seclection and hardware controlied selection. Generally, the CRAM AR
field specifies selection as follows: ARMM(0). CACHE(]), AD(2), EBUS(3), SH(4), ADX*2(5),
ADX(6) and ADX/4(7).

AR register loading is controlled by cither the hardware or microcode. Normally, the AR register
recirculates its contents. Sclecting any of the AR select lines CRAM ARM SEL 4, 2, or | enables
loading AR. The selection of none of the CRAM ARM SEL lines enables the AR mixer to sclect
ARMM. The loading of AR is then 8 microcode function.

During reads from core, the signal CLK RESPONSE MBOX, sclects ARM SEL | to enable the cache
data lines into AR. Similarly, on reads from fast memory via AD. FM XFER selects ARM SEL 210

enable the AD into AR. Various combinations of clearing of AR are possible depending on the conditions. This information is given in table form on Figure 2-71.

EBOX/2-108

FuNcTION

ANABLES LOADING 0 INTO
4800 08

TuNCTION

Anow

1L COND ARLL

ENABLES MICRO CODE TO.
17 INT 0
LOADPCSECT 13

crmeG e o

10a0

AR ICOND REG CT:
oCOND ARLK
10A0

on AnLstLazt

cram s a2t

ENABLES MICRO COOF 10
1 AR NO *
cnam =01

O ENARLE LOADING
AOR 17 WHEN ANY

L 124

i anm o ion

o0
e
oA
e

o
-

o=
Toncrion

@
CrAGe

10 INABLE LOADING AR
AR
ANY N
00 08wHE

| [coanaser

o
)

conruxttnr
SN

Cromai e =

1O AR
LGk an iantxeemon
| Vo
|

cxant
us
Usts on
vAO

e
orow

Sturcva
v
| T
oy

s
oo
5V oR Ao A0

Com a1

READWITH
'DURING
TALSECTL.
hoo 31ACLeAR

WCLLOADARA || DIAGNOSTIC FUNC
Cxmesn

R0 o0k MsTCONTROL

T O CCASION
A0
W oATAvIAracy MimoR

INTO
# 10 BE LOADED

A
8M

TO
LY
USED
CTLCONO/ARRLOAD | CURRENT

ENABLE SER < INTO ARR.

croammsiiazy

INDEPENDENT OF AR 08 36

|
1

criam LoaD

ON ANY ARM SEL 427

ENABLE LOADING AR 1835

acioaoan

CrUAR NOSELZ |

CURRENTLY USED TO ENABLE

O INABLE AR 00 08 10
ARRM
ViA ED
W4 LOAD

et 1ok0 A1
Cikmiamax

[riey——
| onoNTavAmoR

"
==
=
i

anv

PR
T
sche | a0
cacee E8us

o amnas

DIAL LOAD AR

| [z

‘

"
:

——

CrLanL stz

ENZBLES LOADING 0 INTO.

NABLES MICRO COOE 10,
AR
D
ARMM INTO
LOA

an
con

ent

T ARR LR

stz

AR
INTO T
LOAD PCSEC

rucTION

wonaL

ANABLES MICRO COOE LOAD
ARMM INTO AR |CONDREG.

ENABLES LOADING 0% INTO

|| [conmxrenn
RSN

o EXTENOND £ CALCY

L
l
SL

onon

rowt
;
-

CLEAR DIAGHORTIC

AowsmcRoco0t 10
| G
O

AciowsARwemo
INDK-10
00. 17oot
CLEAR

ooy

INSTR ONATOCCASION
WEAD
wtiORY
OnATAVIA

CTUO@ARIAD | ENABLKEVIAADINIOARR

)

crms

e ans 08wo n
Cham

FowU CLAAR OR DUAGNOSTIC

JRp
INOE
R
AR 1838——
CLEA
Fnotmy
THIS

PAGE

CONTINUED AND/OR
ENLARGED 1O
THE RIGHT

FACTION

EXAMPLE
OUS
USES FOR
VARI

AR
INTOG
IN
AN INSTR
LOAD

t |
ron txecomon
ko

WICRO CODE UST CONTROL

CTLARL INDSEL

OF THESE
ONE S
SELECT
CACHE € 8US, AD"2 ADA

READ INSTR ON OCCASION

MCLLOAD AR A

CLK REP MBOX

OB DATA VIAMBOX

WL LOAD AR

‘DIAGNOSTIC FUNC

e s
Lo

THIS FIGURE

CONTINUED FROM
FRAME AT LEFT

Figure 2-71

AR Selection

EBOX/2-109

2.9.55

ARX Field - This field consists of three bits. Figure 2-72 details the breakdown of various

combinations of CRAM ARX selection and hardware controlled selection. Generally, the CRAM
ARX field specifies selection as follows: UNUSED(0), CACHE(1), AD(2), MQ(3), SH(4), AD*2(5),
ADX(6). and ADX 4(7). ARX register loading is controlled by cither the hardware or microcode.

. the ARX register recirculates its contents. Selecting any of the ARX select lines CRAM
ARXM SEL 4.2, or | enables loading ARX. The selection of none ofthese lines currently defaults to
an unused input (0). As with AR, during reads from core,CLK RESPONSE MBOX, selects ARXM
1. to enable the cache data fines into ARX. Similarly, on reads from fast memory via AD, FM
selects ARXM SEL 2 to enable the AD into ARX. Generally, the ARXis cleared via ARL
IND and number 03. The various combinations are shown on Figure 2-72 in table form.

sowaL

rotion

croanxcin

Sonns

ONE OF Thist
ChAMARKMSCLA | SILLCTING
0 207 ADX D4

g
Croanxsi

S TARLE BELOWCTL ARKR

croanxsio)

ST YA BELOW CTL ARXR

o mstr

WL H CLLAR OW DIAG FUNC

croanxcin

S TARCECTUARR CLn

creamowo

TowcTion
TOCLEAR ARX WL OPERA

ON AR
TING

T AR

CORD,

{

o0
L

anx

cuic op—

crau ae

cace

avxez

Avasa

cramsiz

—l_

oeTion

i LoD ARX

20w ADX ADKA

WL L0AD ARX

L LOAD ARX

AEAD OF WSTR NOIRECT

FonTIOn

WORD OB DATA ViA MBOX
OF WeSTR, WOIRECT
WEAD

uAGOSTIC FUNC

OEOF THESE
ChRwARXMSELY | SeLECTIvG
Chcwt wa ADX'2 ADKA

OR OATA ViA FAST
WORD
Siuony
Figure 2-72

SanaL

Cix At wnox

ChAM ARXWSILZ | SULLCTINGONEOF THESE
conrm xrn

ARX Sclection

EBOX/2-111

2.9.5.6 BR Field - The BR field consists of one bit and is used to select one of two possible sources as
input to the Buffer Register (BR). The following sources may be selected: BR(0), AR(1).

2.9.5.10 SCADA Field - The SCADA field consists of three bits and is used to select various sources
as input to the SCADA Input. The following sources may be selected: FE(0), AR POS{1), AR EXP(2),

2.957 BRX Field - The BRX ficld consists of one bit and is used to select one of two possible sources
as input to the Buffer Register Extension (BRX). The following sources may be selected: BRX(0).

The floating-point exponent register (FE) is & 10-bit register. The AR position field is used in byte

ARX().

2958

FMADR Field - The FMADR field consists of three bits and is used in the selection of source

addresses for fast memory. Basic selection is as follows:
1.

#3). SCADA sclections of 4-7 disable SCADA producing zeros as output.

instructions and consists of AR 00-05. The AR exponent field consists of AR bits 00-08 and the magic
number field is a 9-bit control RAM field used to implement various cperations. The SCADA mixer
selection is shown in Table 2-14.

Table 2-14

ACO(0). (IRAC 7-12),

SCADA Mixer Selection

ACI{1). (IRAC 9-12)+1 Modulo 16,

XR{2). (ARX 14-17),

VMAQ3), VMA 32-35,

AC2(4). (IRAC 9-12)+2 Modulo 16,

AC3(5). (IRAC 9+2)+3 Modulo 16,

CB##6) current ac block and selection within it is via § field,

#BK7). this is some block selected by # field.

2.959 SCAD Field - The SCAD field consists of three bits and is used to control the Shift Counter
Adder (SCAD) during various microinstruction operations. It is wired to implement eight functions as
iltustrated in Table 2-13. The input mixer structure is similar to that for the AD or ADX in (hat there
are two input mixers labeled SCADA and SCADB. These mixers are selected via two control RAM
fields labeled SCADA and SCADB.

12|71

O 0 0
{01
o
of1]|o

1 o fo

{11

{01

{110

Vojr

SCAD Field

SCAD Function

sxj N

1) 1]

{

¢}

u | 0

0 v

)

Uil
v}
01

A-B

A+l

AxB

AandB

Function Breakdown
sS4

AR
A+B

Source

ARO

ARIXP

011

)
1
1

v
1

6
1
1

i
te
1

0
1o
0

o l 1
1

e "]

2.9.5.11 SCADB Field - The SCADB field is a 2-bit field used 1o select various sources as input to the
SCAD B input. The following sources may be selected in the SCADB mixer: SC(0), AR SIZE(D),
ARO0-08(2), and &3). Selection of 4-7 disables SCADB, producing zeros as output. The SCADB
mixer selection is shown in Table 2-15.

Table 2-15

SCADB Mixer Selection
Source

CRAM SCADB

Table 2-13

CRAM SCAD ]

CRAM SCADA

AR®

AR OCG 0%

k-2

The shift counter (SC) is a general-purpose 10-bit register used in shift counting operations such as
performed in floating-point instruction and shift instruction execution. It aiso contrcls the shifter
when the SH-ARMM field is zero (SH AR and ARX). The AR SIZE field is used in byte instructions
and consists of AR bits 06-11. The AR00-08 is used in string and edit functions. The magic number
field is a 9-bit general-purpose CRAM ficld used for various functions.

2.9.5.12 SC Field - The SC ficld consists of one bit and is used with the special field function SCM
alternate. With SC and SCM alternate, four possibie sources may be selected as follows:
With the special field function SCM ALT and SC field equal 10 zero, FE is selected. Similarly, with

SCM ALT and SC field equal to one, AR SHIFT is selected. AR SHIFT consists of bits 18 and 28-35
of AR, which are derived from the effective address for shift instructions. If bit 18 is set, the shift
specified is a right shift; otherwise, it is a left shift.

EBOX/2-112

EBOX/2-113

29513 SH Field - The SHIFTER ficld consists of tn bits and is used to select four possible inputs
10 the shifter. The sclection is as follows: the combined AR. ARX(0). AR(1). ARX(2), and AR
SWAPPED(3). When shifting AR, ARX left (which is the only way SH shifts physically), SC can
Specify up 1o 350 shifts. Any number less than 0 or greater than 35,0 selects ARX as output.
2.9.5.14

—

]

The AR Mixer Mixer ARMM) - The AR Mixer Mixer (ARMM) ficld consists of two bits

and is used with other control signals and the absence of ARM SEL 4, 2, and | to select various.

2
o sec

—

i‘f;:;

o seL 1

sources as input 10 AR mixer.

The ARMM comprises three parts: bits 00-08, bit 12, and bits 13-17. The same field that controls SH
controls ARMMO0-08. The following may be selected as input to ARMMO0-08: K0). AR SIGN

SMEAR(1), SCAD EXP(2). and SCAD POS(3). AR SIGN SMEAR is AR0O-8 from ARO. SCAD

EXP is ARO-8 via SCAD, and SCAD POS is ARO-5 via SCAD.

ARMM bit 12 is controlled by CRAM SH-ARMM SEL | when transferring the previous section to
AR for certain operations. ARMM bits 13-17 are also under control of CRAM SH-ARMM SEL |
but the signal is actually MCL PREV SECT to ARMM. The default value for ARMM 13-17 is PC

13-17 and the selected value is VMA previous section 13-17.

29515

~ wow se 1

VMA Field - The VMA field consists of two bits and is used 10 select various sources as

HEHHIE

input to VMA. The following are specified by the CRAM field VMA(0), PC(1), PC+1(2), and AD(3).
Address control is presented in Subsection 2.4 and a path diagram is provided to show various combinations in Figure 2-58.

2.9.5.16

— oM SEL 2

MQ Field - The MQ field consists of one bit and is used in combination with the following:

DISP/MUL
DISP/DIV
SPEC/MQ SHIFT
SPEC/REG CONTROL

wosaz

wose

MAGIC NUMBER FIELD

cono

tc the

minor machine cycles and to the microcode dispatch RAM decoding. The figure shows sev-

basic areas as follows:

Group

Class of instruction

Address Caleulation

. @B, Y

Data Fetch

IMM, Read,

Execution

36-Bit Data Path (DP), 18-Bit Address Path

Special Conditions

Can cause PI. Trap

Store Data

Write

Interruptable

i o il el

.
Read-Write, Write, Read, Pse Write

(AP), 23-Bit AP. 10-Bit AP

EBOX/2-114

CONTROLLING F1ELDE

wicwa | o | owe

olofolalols|

Figure 2-74 breaks down the KL10instruction set into several functional areas. These areas are related

SELLCTED CONTROL SIGNALS

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inations.

for vark

210 EBOX INSTRUCTION SET FUNCTIONAL OVERVIEW

273

ofafolofolafolalq

jgure

a|ofolo|

Relcsto Figure2:73 forvarious combinations

[oroe

iy
Figure 2-73

MQ Selection

EBOX/2-118

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war [ men e | wm

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o coons

Figure 274

Instruction Set Divisions

EBOX 2117

Once the instruction has been loaded into IR and ARX, the major machine cycle begins; this is shown
in Figure 2.75

Three functional flows and two tables are included 1o supplement the functional descriptions ofthe
address. fetch. and store cycles that follow

Figure 275

2.10.1

Major Machine Cycle

Effective Address Calculation

Figures 276 and 2-77 illustrate the instruction word formats.
13-35 have
the same format in every
instruction whether the instruction addressss a memory location or not. Bit 13 is the indirect bit, bits

14-17 are the Index register address and, if the instruction must reference memory, bits 18-35 are the

memory address Y. The effective address E of the instruction depends ofthe values of I, X, and Y.

”

21w

USRS TP—

Figure 2.76

Basic Instruction Format

loevice coor] I | @
T

o
o

Figure 2-77

In-Out Instruction Format

EBOX/2-119

2.10.1.1 Indexing - If the Index register address is nonzero, the contents of the specified Index register are added to the Y address to produce a modified virtual address.

Referring to Figure 2-78, the EBox tests ARX 14-17; if it is nonzero, the contents of the specified
Index register are added to ARX 00-35. The result in AD 18- 35 is loaded into AR 18-35 with AR

00-17 clcared, and also loaded intc VMA 18-35 while VMA 13-17 is recirculated.

2.10.1.2 Indirection - Whether indexing is performed or not, if ARX 13 is equal 10 1, indirection will
be performed. Two cases are to be considered. The first is where no indexing was performed. Here
(indicated on Figure 2-78 as (A) ) YMA 18-35 is loaded via AD with ARX 18-35. In the second
case. indexing is performed and the VMA is loaded via AD with AR. Here AR holds the sum of ARX
18-35 and FM 18-35 effectively, with AD bits 00-17 clear.

In either case, VMA 13-17 is recirculared while VMA 18-35 will be loaded via AD. The microinstruction MEM field function for the indirect request is MEM /AIND. This function has MEM 02 =

0. so MBOX WAIT is conditionally a function of the next microinstruction.
Testing for Interrupts

The microinstruction causing the EBox request also tests for a pending priority interrupt. If an interrupt is pending, the CRAM address is modified to allow entry to the Pl Handler (Figure 2-79).
The request, which is made both to fast memory and core memory via the MBox, is ignored as long as
it does not page fault. MBOX WAIT is false, 30 the EBox clock does not stop at this time. The EBox
ignores an indirect reference when an interrupt is pending, but the EBox hardware remembers s page
fault (if one occurs) undil the page fault handler has been calied. After the PF Handler is called, Force
1777 will be cleared.

Referring to Figure 2-80, assume the indirect request has been started. Because the indirect reference is

always a “READ," the only types of page faults that can occur in K1 paging mode are no access {page
nol in core) of proprictary violation,

The requesting microinstruction detects the interrupt and the microprogram branches (via CRAM
Address) to the Pl Handier.

If the page fault occurs (for example) because of no access, the MBox must first read from the in core
process table to obtain the paging information (use bits A, P, W, 5. C and physical page). Reading this
can take between 600 and 1000 ns. During this period, the PI Handler is -etting up the requested Pl
service.

Eventually. a read, write or instruction fetch occurs, caused by the handler. When MBOX WAIT

becomes true, the clock board {which remembered the Page Fail Hold level) forces the microprogram
1o the page fault handler.

Now the page fault handler detects the pending interrupt and the microprogram branches back to the
PI Handlzr or to the instruction cycle. Thus, the entry to the page fault handler satisfied the clock
board “'page fail hold conditionTM and this condition now clears. Should the EBox make 8 second
MBox reference before the page fault occurs, the EBox waits.

EBOX,2-120

Twor oot v
Lt o 11

Vikons momo.

Figure 278

Effective Address Calculation
EBOX/2-121

[

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|
|

Figure 2-79

Page Fault During Diverted Indirect Reference

Normal Case - No Interrupts, MBox Request
When the EBox request is made specifically to the MBox, no interrupts are pending, the micro-

instruction following that which made the request (MEM /AIND) has its MEM field coded as ARX MEM_ This function, together with MEM Cycle (1), will generate MBOX WAIT.

Assuming a page fault does not occur, the word loads into ARX. Now as indicated on Figure 2-79, the

loop is reentered once again.

Normal Case - No Interrupts, Fast Memory Request

When the hardware determines that the VMA contains a fast memory address, it asserts VMA AC

REF. This signal is used 1o inform the MBox that the EBox request is not to be handled by the M Box.
Note that the fast memory address control uses VMA 32-35 to access fast memory even though the

virtual address may be a core memory address. The hardware directs the use of the information
accessed in this

manner.

The effective address manager

(Figure 2-15) branches within

itself using the information provided

from ARX 13 and 14-17. In addition, each time it samples this information it should branch to a

microinstruction that enables the correct registers to be loaded: it may, however, invoke certain “don't
careTM operations, providing the next microinstruction executed performs the proper action. For
cxample, assume a microinstruction is to always perform the indexing function in AD, but dispatch to
a microinstruction that uses this information only if ARX 14-17 = 0. This approach simplifies the

design of the logic

The table at the bottom of Figure 2-78 lists the four possible conditions resulting from indirect refer-

ences to either MBox or fast memory.

EBOX/2-123 |

2.10.1.3 No Indirection
or Indexing - For this case, ARX 18-35 contains the effective address. Here, it
remains only to load AR 18-35 via AD with E and clear AR 00-17. The Fetch cycle is now entered.
2,102 Fetch Cycle
Once the effective address has been calculated, the second minor machine cycle is entered. This is the
Fetch cycle and is illustrated in Figure 2-81

Figure 2-81

Fetch Minor Cycle

After the effective address kas been calculated. the microprogram effective address manager gives “A
READ DISPATCH" and control is passed to the Data Fetch Manager.

In general, two major classes of instructions exist in terms of the Data Fetch cycle. These two classes.
are those instructions that require the contents of the effective address and those that do not. Within
cach of these two categories are a number of divisions. The flow of the Fetch cycle is illustrated in
Figure 2-80,

21021

Instructions That Do Not Require (E) - Three general groups form this category.
Complex or PC change instructions
Immediate non-PC change instructions
Instructions that write in E

For these three groups, the DRAM A field is coded 0, 1. and 2, respectively. The AREAD Dispatch
functions are listed in Table 2-16.
Complex or PC Change Instructions
The DRAM A field is coded
as 0, and no data is requested. In addition, the next instruction
is not
prefeiched. The AREAD/Dispatch dispatches
directly to the execute code. This consists
of a table
lookup, where one discrete entry exists for each instruction. Thus, for example,
the move instruction
indexes
into location 200" in the DRAM. The organization of theDRAM is illustrated
in Figure 1-4.
Immediate and Non-PC Change Instructions
The DRAM A ficld
is coded as 1, and no data is requested. The next instruction is prefetched and
loads into ARX when the instruction becomes available. The AREAD/ Dispatch dispatches directly to
the execute code.

Figure 2-80

EBox Data Fetch

EBOX/2-124

EBOX 2-125

Table 2-16
DRAM A

AREAD Dispatch
Reguire (1)

MEM/AREAD

DISP/AREAD

chetid

Executor

St Preterch

Executor
Notused

Symbolic Address 43%

LOAD AR

Symbolic Address 4%

Symbolic Address 45%

“LOAD
Symholic Address $6°

Symbolic Addiess 47%

LOAD AR READFALSEWRITE

LOAD AR WRITE 1181

Yes

—l
*The Dt

etk manages w4 comben

AR PREFITCH

o hadane seonh
om MCY. s

That Write in E

The DRAM A field is coded as 3 and a write page test is

=l
the wbrnpvogam

usstg o

<
41

ted. I the address is not writable, a page
dicated in Figure 2-80.

failure occurs. This action causes a transfer to the page fault handler

The appropriate Fetch EBox Qualifiers may be determined by referring to Figure 2-82. For DRAMA
= 3 the following qualifiers are specifically asserted
EBOX REQUEST
EBOX PSE
EBOX WRITE

In addition, the state of the qualifiers is more complex and may depend on the previous history of the
EBox. The state is indicated by an asterisk (). Once again referring to Figure 2-80, if the write page
test is successful, the EBox fetches the contents of the addressed fast memory location (via IRAC

09-12) and then dispatches via the DRAM J field to the executor.

EBOX,2-126

EBOX REQUEST QUALIFIERS
>

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AREAD

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TNDIRECT WORD READ, MAY BE T0 MBOX OR

ToF.
. VA AC REF 1 e——
S
INSTR FETCH MAY OCCUR FOLLOWING A

READ WITH DRAM A=10R § TOGETHER WITH
MEWFETCH

FOR JRST 0 H IR-RSTO)
sTRFETC

PICYCLE 1S CLEAR, USED WHERE NO PREFETCH

AN INSTR FETCH.
TO CAUSESUED
yasiS

DATA READ ISSUED BY INSTRUCTIONS REGUIRING
THE (€) AS FOLLOWS. COMPLEX
OR PC.CHANGE
C CHANGE INSTRUCOR SIMPLE NONTIONS
INSTRUC

oD ASSERTED IF ATTEMPTING TO READ DATA

FROM A PRIVATE ADDRESS SPACE WITHOUT PROPER
PROTOCOL. MBOX READ PAGE TESTS.

DATA READ-WRITE ISSUED BY INSTRUCTIONS

FETCH

AREAD

X|x

X % % n|n

AEQUIRING THE (E) WHICH CONDITIONALLY WRITE
INTO E. THESE INSTRUCTIONS ARE AS FOLLOWS:

(@) % | %| % | NON READ PSE WRITE TYPE D ASSERTED IF

ATTEMPTING TO READ DATA FROM A PRIVATE

'ADDRESS SPACE WITHOUT PROPER PROTOCOL.
MBOX READ AND WRITE PAGE TESTS. AR LOADS.
DATA READ PSE WRITE ISSUED
BY INSTRUCTIONS
REQUIRING THE (E) WHICH WILL UNCONDITIONALLY

WRITE INTO
£ (3)ASSERTED
IF ATTEMPTING
TO READ

FETCH

AREAD

X XXX |%|%|%|n

DATA FROM A PRIVATE ADORESS SPACE WITHOUT

READ AND WRITE
OPER
PROTOCCL. MBOX
(@|% | % | % | THEPR

PAGE TESTS. IF CACHT IS DISABLED
FOR THE CYCLE
MBOX WAITS
FOR WRITE PORTION
OF CYCLE. LE. PT
CACHE (0) OR CACHE LOAD (0)A NOT FOUND.
AR
LOADS

BY A PUBLIC PROGRAM FROM A PRIVATE ADDRESS SPACE, AND THE INSTRUCTION 1S NOT A PORTAL. ILL ENTRY WILL CAUSE THE
o IF AN INSTRUCTION IS FETCHED
MBOX TO PAGE FAIL ON THE NEXT MBOX REF

* THESE QU/ LIFIERS ARE TRUE O FALSE DEPENDING ON THE SPECIFIC TYPZ OF REQUEST BEING MADE

Figure 2-82 Address-Feich-Execute-Store
General Memory References (Sheet 1 of 2)
EBOX/2-127

cveLe

MEm

DRAM

CACHE LOOK,

PAGE ADR COND.

CACHE LOAD

PAGE TEST PRIVATE

PAGE ILLEGAL ENTRY.

PAGING MODE
K1

VMA
AC REF

MAY BE PAGED

E£BOX USER

£BOX WAITE

£80X PSE

FBOX READ

E£BOX AEQ

£BOX REQUEST QUALIFIERS

REMARKS

/4
DATA WRITE PAGE TEST ONLY. ISSUED BY

INSTRUCTIONS NOT REQUIRING (.} BUT WHICH

FETCH

AREAD

WILL WRITE INTO € () ASSERTED IF ATTEMPTING

TO WRITE DATA INTO A PRIVATE ADDRESS SPACE
WITHOUT THE PROPER PROTOCOL. MBOX WRITE
PAGE TESTS.

AND WRITE DATA)
DATAWAITE WRITE PAGE TEST

USED BY THE GENERAL § MODE TYPE INSTRUC

STORE

BWAITE

TIONS 1 €., IMM, BASIC._ MEM, SEL FOR BOTH. SELF
MODE STORES CONDITIONALLY IN £ WHILE BOTH
'MODES ALWAYS STORE IN €. IN ADDITION BOTH
MODES STORE UNCONDITIONALLY IN AC WHILE
SELF € MOOE STORES CONDITIONALLY IN AC

AS @
STORE VIA AR (B SAME

BYTE POINTER INDIRECT WORD READ. USED AFTER
BYTE POINTER HAS BEEN FETCHED
WHEN BIT 13

EXECUTE

IS 1 USED ONLY BY BYTE TYPE
OF THE POINTER

BYTEIND

INSTRUCTIONS. ACTS LIKE EBOX READ TO MBOX.

MBOX READ PAGE TESTS. BOTH AR AND ARX ARE

LOADED
(® SAME AS
@

EXECUTE

1€ DATA READ. USED AFTER BYTE INDIRECT
BY
HAS COMPLETED. USED BY BYTE TYPE INSTRUC.

BYTE RO

ACTS LIKE EBOX READ TO MBOX. MBOX
TIONS.
READ PAGE TESTS. BOTH AR AND ARX ARE LOADED.
DsaME AS®

GENERAL PURPOSE WRITE. USED MANY PLACES.
'SOME EXAMPLES WOULD BE INSTRUCTIONS WHICH
SUCH AS DOUBLE
'STORE MORE THAN ONE OPERAND,
TYPE INSTRUCTIONS. INSTRUCTIONS WHICH SKIP.

EXECUTE
STORE

WRITE

OR MODIFY AND SKIP BUT DID NOT FETCH (E! AND

MISC

TO WRITE INTO £ MBOX TREATS AS
ARE GOING

WRITE WRITE PAGE TESTS.

EXECUTE

LOAD AR

o IF AN INSTRUCTION IS FETCHED
BY A PUBLIC PROGRAM FROM A PRIVATE ADDRESS SPACE, AND THE INSTRUCTION IS NOT A PORTAL. ILL ENTRY WILL CAUSE THE
MBOX TO PAGE FAIL ON THE NEXT MBOX REF

ON THE SPECIFIC TYPE OF REQUEST BEING MADE
* THESE QUALIFIERS ARE TRUE OR FALSE DEPENDING
Figure 2-82

Address-Fetch-Execute-Store

General Memory References (Sheet 2 of 2)
EBOX/2-129

2.10.2.2

Instructions That Require (E) - Under this category are four general groups. These groups

are as follows:

Complex or PC change instructions

Simple non-PC change instructions

Non<{read-PSE-write) type instructions

Recad PSE write type instructions

For these four groups. the DRAM A field is coded 4. 5. 6, or 7, respectively.
Complex or PC Change Instructions

The DRAM A field is coded as 4. causing a dispatch to location 44. A read page test is performed by
the MBox. If the address is not accessible (not in core), the MBox performs a refill cycle and then
checks the use bits.

If the access bit is clear, a page fault occurs and the EBox t-ansfers to the page fault handler {microcode page fault handler). Otherwise, the requested word is loaded into AR. For the appropriate EBox
qualifiers, refer to Figure 2-83. Finally, s DRAM J dispatch is performed to the executor.
Simple Now-PC Change Instructions

The DRAM A field is coded as S, causing a dispatch to location 45. The basic read is the same as for
DRAM A = 4, If no page fault occurs, the MBox issues MBox RESPONSE with the data word. Now
the VMA loads with the prefetch address and this cycle begins. This MBox cycle will run in parallel
with the Execution cycle, which may not use ARX. Finally, s DRAM J dispatch is performed at
location 45; the VMA is loaded with PC + | and the prefetch begins.
Noa-Resd PSE Write-Type Instructions

A number of instructions are in this category; s few examples follow.

The first example is SETMB. This instruction (Boolean Group), reads & word from memory and
unconditionally stores it in memory and AC. Because writing the word back into the same address is

r=dundant, only a write page test is required to assure that the word (if in core memory) is writable. If
this page fails. then the operation is aborted anyway. Otherwise, the word read is stored only in fast
memory as addressed by IRAC 09-12. The read-write (separate cycles) may be thought of as consisting
of a read and conditional write. If the write cycle is really desired, the MEM field function
MEM /Write may be used to write (Figure 2-82).

The second example concerns instructions such as IDIVM, IDIVB, DIVM, and DIVB. These instruc-

tions reference memory for both read and can generate no divide. This aborts the division operation. If

the class of instruction is read PSE write and the cache is disabled for the reference, then the MBox
waits for the write portion of the cycle; the EBox performs an unnecessary write operation.
A third cause is for BLKI and BLKO 1/O instructions. Here a pointer word is fetched from the
effective address. This pointer is normally updated and stored back in the effective address.

One problem is that the legality of performing the 1/O instruction is tested afier the pointer has been
fetched. This is necessary because the pointer is fetched during the Fetch cycle, while legality (10
LEGAL) is tested during execution. Should the BLKX instruction be illegal in the current EBox mode,
an unnecessary pointer back off and write would be necessary.

Other cases are concerned with very long instructions, which could hold up the MBox.
EBOX/2-131

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Figure 283 Exccute-Register-MBox Control
and Miscellancous General Memory References
(Sheet 1 of 2)

EBOX/2-133

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Figure 2-83 Execute-Register-MBox Control
and Miscellancous General Memory References
(Sheet 2 of 2)

EBOX/2-135

The DRAM A field is coded as 6, causing a dispatch to location 46; the MBox performs both a read
and write page test. The address must be both accessible and writable, even though this portion of the
operation only reads a word. If a page failure occurs, the EBox transfers control 1o the page fault
handler. Otherwise, the word enters AR and then a DRAM J dispatch is issued.
Read PSE Write Type Instruction

The DRAM A field is coded as 7 causing 8 dispatch to location 47; the request qualifiers are shown on
Figure 2-82. The MBox performs both a read and write test, and if no page fault occurs, reads a word
from the specified (Xlated) address.

If the cache is disabled for the reference and the word requested was not in the cache (a Refill cycle was
necessar first), then the MBox is held waiting until the EBox issues the write portion of the cycie. The
word requested loads into AR and a DRAM J dispatch is issued to enter the Executor.

2.10.3

Execution Cycle

The Executor is entered from the Fetch cycle. While in the Fetch cycle, the (E) or (AC) is fetched in
accordance with the DRAM A field. In addition, read and/or write page testing is performed while in
the Fetch cycle. The EBox Execution cycle overview is in Figure 2-84.

Early in the Instruction cycle, the DRAM is acoessed using one of three basic types of addresses.
Referring to Figure 2-84, if the instruction is JRST 0-17, then the IR address is used to address the
DRAM initially as indicated. Thus, the JRSTs handler is entered at location 254 for JRST and 255 for

JFCL.

From the initial dispatch into the handler, the IRAC is used to redispatch within the handler for the
proper type of JRST. For JFCL, a JUMP i made 10 a separate handler from the initial dispatch

Hf the instruction is an 1/O type, then the DRAM address is formed by the hardware such that the
dispatch is in the range of 700-777. Once the 1/O handlei has been entered, a determination must be
made as 1o whether the instruction is legal in the current processor mode. If it is determined that the
instruction is not legal, the MUUO executot is used to store the illegal instruction and PC word in the

user process table. Following this, & new PC word is fetched. This new PC word causes the processor to
cnter an executive routine in core memory. If the 170 instruction is legal, use of the EBus is obtained
and the appropriate EBus dialogue is carried out. The specific actions evoked depend upon the device
and the type of 170 instruction being performed.

The remaining instructions index into the DRAM utilizing the op code in IR bits 00-08. Two general

categories exist as foliows:

Simple Type - stores in AC, E, or both

Complex Type - may store in AC, AC+1, E via normal store cycle or elsc store via a special
handier, or may do some of each

The complex instructions may nest microcode subroutines up to four levels deep.

Referring 10 Figure 2-85, the mechanism consists of CRA LOC, a register that is loaded with the

*current micrainstruction address.” This register is loaded at the same time that the CRAM register is
loaded with a new microinstruction. In addition, a 4-word stack is provided. The contents of CRA

LOC are pushed onto the top of the stack when the call has been asserted by the microinstruction. To

return from a subroutine, the returning microinstruction asserts DISP/Return. This pops the top entry

off of the stack and onto the

CRAM address mixer lines, where it is logically ORed with theJ field of

the microinstruction, asserting DISP/Return.

EBOX/2-137

Figure 2-84

EBox Execution Cycle Overview

EBOX/2-139

Figure 2-85

Microstack Operation

Some of the complex instructions, such as DMUL, which stores in AC, AC+1, AC+2, and AC+3, use
4 separate handler for storing multiple operands. This type of instruction does not pass through the
normal store cycle. Other complex instructions, such as MULB, which stores in AC, AC+1 and E,
store multiple operands via the normal store cycle.

2.10.4

EBox Data Store Cycle

The flow for the EBox Store cycle, illustrated in Figure 2-86, is used by most of the instructions
exccuted by the microprogram Executor. Exceptions to this are certain instructions such as DMUL,

which stores more than two ACs. For these instructions. a special handler exists that is entered from

the executor. This handler stores 41 the operands and then issues an instruction fetch followed by a
NICOND Dispatch. In this »

more general calegories (which do use the normal store cycle) are

covered

2.10.4.1

Basic Four Mo

“wtructions - This type of instruction may have one of four basic

modes as follows:
I

Immediate or Basic - store in AC only

Memory - store in £

Both - store both in AC and E

SELF - store in E and conditionally store in AC. Note that if writing back in E is redundant,
the write cycle is

skipped.

Writing for these four mog instructions is controlled by MEM/DRAM B and the DRAM B field
code. The store cycle is dispatched with DISP/DRAM B. Thus, the dispatch RAM B field (three bits)
15 used 1o form the low-order three bits of the Store cycle address.

Immediate
or Basic Mode

Referring to Figure 2-87, the DRAM B field is coded as S. The contents of AR are written into fast
memory. which is addressed via IRAC 09-12. Because a large number of these instructions prefetch
the next instruction, it i necessary to assert MB WAIT in the event MEM cycle is set waiting for a
response from the MBox. This has no affect if MEM cycle is clear. NICOND Dispatch enables entry
1o the instruction cycle if no priority interrupts, page faults, or traps are pending.

EBOX 2-141

Figure 2-86

EBox Data Stor

EBOX 2-142

Figure 2-87

MBox-EBox-EBus Control
(Sheet 1 of 7)
EBOX/2-143

Figure 2-87

MBox-EBox-EBus Control
(Sheet 2 of 7)

EBOX/2-145

avos

wn-0788

Figure 287

MBox-EBox-EBus Control
(Sheet 3 of 7)

EBOX/2-147

Seres con A

10-17528

Figure 287

MBox-EBox-EBus Control

(Sheet 4 of 7)
EBOX 2-149

Figure 2-87

MBox-EBox-EBus Control
(Sheet 5 of 7)
EBOX/2-151

bosere
can
My

conmimmt woot |
progethy

{

o7 e
com icon
e e

com et ms.

wR-o7s2

Figure 287

MBox-EBox-EBus Control

(Sheet 6 of 7)

EBOX/2-153

5 aon

lrwam.

Figure 2-87

MBox-EBox-EBus Control

(Sheet 7 of 7)

EBOX/2-15§

Memory or Both Mode

The DRAM B field is coded as 6 for memory mode instructions. If VMA 13-313 is clear, storing is to
fast memory. Otherwise. an MBox request is made to store AR in cache memory. VMA AC REF
notifies the MBox to abort the cycle when it is to fast memory. An unconditional instruction fetch is
cnabled at this time. The VMA input is via VMA AD (PC+1) and. as soon as MBox RESPONSE is
received, this is latched into VMA.

To allow VMA addressing to stabilize in case the instruction is being fetched from fast memory, &
NOP microinstruction is performed. This is followed by MB WAIT, state register clear (in casc the
instruction fetch page fails), and finally NICOND Dispatch is issued.
For Both Mode. DRAM B is coded as 7. Here, the departure is made afler storing the AR in E. The
AR is also stored in fast memory as addressed by IRAC 09-12. Now MB WAIT is asserted while

clearing the state register and NICOND Dispatch is issued.
SELF Mode

Once again referring to Figure 2-87, the DRAM B field is coded as 3. SELF mode instructions are

generally read/ write type; this means that the virtual address was read and write page tested during the
fetch cycie.

Writing is allowed only if not redundant, or as specified by IRAC being nonzero. AR is stored in E, the
instruction feich is siarted. and the AC ficld of the instruction is tested (in IRAC). If IRAC is nonzero,
the AR is stored in the addressed fast memory location (as addressed vis IRAC). If IRAC is zero, no
storing in fast memory is performed. In either case, a microinstruction NOP is performed. This guarantees one EBox clock between the instruction fetch and the NICOND Dispatch to follow, allowing

adequate setup time for the NICOND logic to detect & fast memory reference (VMA AC REF) for
those cases where the instruction fetch is to fast memory.

2.10.4.2 SKIP, JUMP Compare Instructions - The following instructions listed in Table 2-17 fall into
this category.

Table 2-17
Main Group
-

Skip, Jump, Compare Iastructions
Conditional Store

Unconditions! Store

Inste
——t

Stores Nothing

Op Code

330137

Anthmene Skaps

SKIPXX

Nos

Yes # IRAC # 0
Yes st IRAC # 0
No

ht
No

350 357
370 317

Conditnmal Jumps

JUMPAX
AGIXX

Nat
Yes

e
o

Yes
Nar

320 327
330 347
160 367

AOSXXN
SOSXX

SUXXN

Anthmet. Testing

Compares

Yer
Yos

Nav

Yeu

282

AORIP

Yey

AGBIN

Yoy

Nov

Nar

253

CANX
CAMAX

N
Na

toNe
DN

Yes
Yeu

300 307
0 317

—

FBOX/2-157

No Results Stored - CAIXX, JUMXX

Referring to Figure 2-87, because CAIXX and JUMPXX store no results, preparations are made for

entry 10 the instruction cycle. The state register is cleared, MB WAIT is asserted, and a NICOND
Dispatch is issued. Depending upon the outcome of Test Satisfied, the next instructionfetch is from
PC+1, PC+2, or E

Conditional Storage in AC - SKIPXX AOSXX, SOSXX

IRAC is sampled and if nonzero, ARis stored in fast memory as addressed via IRAC 09-12. Depending upon the outcome at Test Satisfied, the next instruction fetch is from PC+1 or PC+2 and this is in
progress. The state register is cleared, MB WAITis asserted, and a NICOND Dispatch is issued.
Unconditional Storage - SOJXX, AOJXX, AOBJX

These instructions all store unconditionally, in fast memory from AR, as addressed via IRAC, then
prepare to enter the Instruction cycle. The state register is cleared, MB WAIT is asserted, and
NICONDCDilpllch is issued. Both SOSXX and AOSXX unconditionally store in E and conditionally
store in AC.

Figure 2-88

Basic Machine Cycle Summary

2.10.4.3 Store Cycle for Other Instructions - Generally, the remaining instructions that use the Store
cycle fall into two groups. These are instructions that store results
in AC, AC+1 and E, and those
instructions that store results in AC and AC+1 only. All these are complex instructions.
Complex and Store Both
For these instructions, the store flow is entered with a write request already in progress 1o store the

Figure 2-89 1s the subcycle summary and Figure 290 is the hardware cycle summary.

high-order result of some operation and MB WAIT is asserted (MEM/MBWAIT). Also, the shift

counter (SC) contains 35, enabling alignment of the low-order word with the sign ofthe high-order
word later in this
flow. The AR is now stored in fast memory as addressed via IRAC and the sign is
smeared in AR 00-35. At this time, AR contains
sign bits and ARX contains the low-order word
left-justified. The instruction fetch begins. The AR and ARX are shifted left 35 places and the result
(correctly signed) is loaded into AR via SH. Now the state register is cleared and the low-order word
(in AR) is stored in IRAC + 1. The EBox hardware facilitates the incrementation of IRAC by +1.
Finally, the appropriate entry to the instruction cycle is made.
Complex and Store in AC, AC

The basic difference here is that

these instructions bypass the storage into E. Otherwis=. the operation

is identical to that for Complex and Store Both.
2.11

INTERFACE CONTROL

2111 Introduction
Figure 2-88 illustrates the major functional cont:ol elements of the EBox. The purpose of this drawing
is to support the functional descriptions contained in this section. In addition, it is provided to support
the E/M interface control and E/E interface control functional descriptions to follow.

The EBox is associated with two interfaces, the EBox/MBox Interface and the EBox/EBus Interface.

The E/M interface is treated as a pseudo-bus because in many ways it behaves as a bus. In the first
portion of the functional description, the basic organization and function of the firmware microprogram was described. In addition, the major machine cycle was defined and described in terms of its

Figure 2-89

Subcycle Summary

functional clements.

Thus, the individual microprogram modules (Figure 2-13), taken collectively, comprise the main
microprogram. The blending of this program with certain pieces of EBox hardware constitutes the
basic machine cycle (Figure 2-88).

EBOX/2-158

EBOX/2-159

Figure 2-90

Hardware Cycle Summary

Next, the basic subcycle was presented in terms of a functional flow with additional graphics to support the description; in the interface section, the relationship of the hardware 10 the internal EBox
cycles was described. These basic cycles were introduced in Subsection 2.1 as EBox, MBox, and EBus
cycles. For example, the fetch cycle can be viewed as composed ofa number of EBox and MBox cycles.
2.11.2

MBox Control

Referring to Figure 2-91, a number of functional elements work together to implement the basic MBox

cycle. The grouping of the interface signals

shown is as listed in Table 2-18.

To exercise the functional areas illustrated on Figure 2-91, a basic data fetch is covered in four steps.
These steps are related to EBox timing in terms of occurrence.

Table 2-18

Request Summary

Grouping

Basc FBox Request Handuiuahe

Stgnals
tBoxRIOUIST
CSHIBOX 10

CSHIBOX RETRY RIQ
PENOLD

MBOX RESPONST 1N
Address and

\diiess

VMA TS

Caniteod

VMA AC REF
Timing

FBOX SYAC
MBOX (LOCK

Ty
pe Reguest

EBONUSIR
FBOX READ
EBOX PSH
FBOX WRITE

PAGE TEST PRIVATH

Address Violation Logic

J
EBOX /2-160

PTPUBLIC
PAGE ILLEGAL ENTRY

PAGH

ADDRESS COND

veox

E
oot

conTaL

Figure 291 General Memory Request
Control Simplified

EBOX/2-161

2.11.2.1 DATA FETCH REQUEST EN - Begin EBox Cycle (Figure 2-92) - The flow is entered st an
E-Box clock and the CRAM register loads. The microinstruction begins to be decoded. Note that the
MEM field is the major input 1o the MBox control logic. Assume that the effective address has been
calculated. the MEM field is coded as AREAD, and the dispatch RAM A field is . In Figure 2-91 at
@ . the MEM field function AREAD is a code of 4. This enables MBOX CYCLE REQ. In addition, if MEM 01 = |, then REQ EN is asserted to enable the request qualifiers to be latched on the
next EBox clock. MBOX CYCLE REQ enables the EBox request to be asserted on the next MBox
clock. As indicated on the flow, this is a fast cycle. Two basic classes exist: fast and slow. The timing is
illustrated in Figure 2-93.

Signal

CLK SYNC EN must wait to occur, so that (for a {ast cycle) EBOX SYNC scts at the same time

as EBox request.

Referring to Figure 2-91, the VMA ficid, with other signals, enables LOAD VMA. In addition, the
effective address must be input 1o VMA via AD so the VMA code (3) generates VMA ~AD.
The basic period between the leading edge of one EBox clock and the ieading edge of the next is
controlled by the T field of each microinstruction, along with certain other hardware signals. The basic
puise width of the positive EBox clock is fixed a1 32 ns but the time between clocks is variable. EBOX

SYNC occurs one MBox clock prior to the MBox clock that causes EBox clock to occur. The basic

relationships are indicated in Figure 2-94.

2.11.2.2 Begin MBox Cycle - Ead Currest EBox Cycle and Start Next (Figure 2-95) - As soon as
SYNC EN is true, EBOX SYNC scts and MBOX CYCLE REQ (FAST CYCLE) enables EBox

1equest 1o set (referto (3 on Figure 2-91). At this point, MBOX WAIT is tested and found clear.

(This function is described in basic terms is Subsection 2.2.4.)

To summarize, the EBox request is then issued, and the VMA input mixer is set up and enabled to load
with E via AD. The request type logic is enabied to assert the appropriate combination of EBox Read,

PSE. and/or Write (which occur on the EBox clock to come at (3 ). In addition, the Address

Context Control is enabling the proper combination of its qualifiers also to be asserted at a.

Now another MBox clock occurs () : simultaneously, an EBox clock occurs. The following sctinns
resuft:

EBOX CLOCK «~ |
EBOX REQ ~ | (REDUNDANT)

MEM CYCLE « 1; MBOX WAIT
« 1

VMA LOADS AND LATCHES

CRAM ~ NEXT MICRO INSTR
EBOX QUALIFIERS LATCHED

Thus, we have passed through one EBox cycle and now reenter the flow to begin a second EBox cycle.

EBOX:2-163

Figure 2-94

Figure 2-92

Basic EBox Clock Period

Begin EBox Cycle Data Feich Request

EBOX,2-164

EBOX/2-165

21123

SETUP PREFETCH - Wait for MBox Response - Referring 1o Figure 296, the flow is

reentered at

(3) where the EBox clock generated loads the second microinstruction (Figure 2-91

3 ). Now the MEM field function is FETCH and MEM 02 = 1. If the MBox has not responded
with the word requested (E), MEM cycle
s still set. The combination of MEM 02 (1) and MEM Cycle
(1) generates MBOX WAIT. Providing that the request is not o fast memory. the EBox stops until the
MBox response occurs,

This is true whether a page fault occurs or not, although PF hold is asserted 5 MBox clocks before
MBOX RESPONSE
i asserted when a page fault has occurred. In this example, assume that the
MBox 1s working on the request, but has not yet responded.

Referring to the flow (Figure 2-96), the current microinstruction MEM field function fetch is a code
of

6 Note, however, that because a priority interrupt takes precedence over any other activity, PI
CYCLE
is checked before enabling the MCL MBOX CYCLE REQ. Here PI CYCLE is clear, so

3) points to a “Fast Request.” Again, a wait

for SYNC EN, as defined by the T field, takes place.

The state of the SYNC EN during MBOX WAIT is always true; this keeps EBOX SYNC true until the
response is received

The MBox continues to run during the waiting period. Thus, MBOX CLOCK sets EBOX REQUEST

«even though the VMA is still latched up with E. During the waiting period, the VMA input receives
PC+1 via VMA AD.

The EBox now loops, wi
2.11.2.4

for MBOX RESPONSE to restart the EBox clock.

MBOX RESPONSE RECEIVED - Referring to Figure 2-97, MBOX RESPONSE enables

the EBox clock. Thus, EBOX CLOCK becomes true and, simultancously, EBOX SYNC becomes

false. The

microinstruction is now loaded into the CRAM register (Figure 2-91

3 ) and is

decoded. In
addition, the VMA is loaded and latched with PC+1, the request qualifiers are latched
and now. with the requested data word in AR, a DRAM J dispatch is issued.

21125 Geueral Memory Cycle Control - Figure 2-98 contains all combinations of the MEM field
that can generate MCL MBOX CYCLE, and hence EBOX REQ. In general, the following functions
are of the “Slow Cycle” type:
B WRITE

Pl FETCHES
SKIP SATISFIED FETCHES
REG FUNCTIONS
SP MEM CYCLES

A Slow cycle is required during MEM/REG FUNC because the MBox requires additional time to

decode the type of request. In all the “slow" cycle types, the EBOX does not necessarily have time to
determine whether to make the request (or not) before EBOX SYNC. Thus, the decision, and therefore
the request, is delayed purely for hardware timing reasons.
2,12

Figure 2-95

Begin MBox Cycle. End Current EBox Cycle, Begin Next EBox Cycle

EBOX/2-166

EBUS INTERFACE CONTROL

The 1/0 system for the K L10 processos includes
the EBus, the peripheral equipment with its interfaces
10 the EBus, and various control logic. The EBus interface may be controlled cither by the EBox
during input or output instruction execution, or by the PI system during priority interrupt handling.
Subsection 2.8.1 gives a basic summary of the EBus signals. This is followed by 3 functional description of the interface, which is covered at two levels. The first level describes the basic functional
organization and operation of the Pl board and other related logic. The second description deals with
the microprogram to Pl board interfacing. This description attempts to give insight into the manner in
which the hardware and the microprogram interact to carry out various interface related functions.

EBOX/2-167

Sets up Prefeich Waiting for MBox Response
68

Figure 297

Receive MBox Response, End Current MBox Cycle, End Current EBox Cycle, Begin

Next EBox Cycle, Begin MBox Cycle
FBOX

/2-169

Figure 2-98

General Memory Cycle

Control Flow

EBOX/2-171

2.12.1

EBus Signal Lines

The EBus consists of 60 signals. All devices, including the KL10, are connected to these lines in
paraliel. The bidirectional nature of 36 of the signals permits some information to flow in both directions. These lines are the data lines. The remaining 24 signals are used for control functions. Table 2-19
lists the data transfer signals.

Table 2-19
—————

Data Transfer Signals

Name

Mnemonic

Number of Lines

Data

Iy 353

Controller Select

CSeny 06y

Fanctn

100 .02y

Vemand

DIV

R}
1

Achnawmicdge
Tianster

ACK
XEIR

1
1

DATA LINES D(00:35) - The 36-data Enes transfer information between the EBox and its devices.
The most significant bit is bit 00; the least significant bit is bit 35.

CONTROLLER SELECT LINES CS(00:06) - These seven lines select the desired controller for a data
transfer. Each controller has a unique select code hardwired on the backplane of the device.
FUNCTION LINES F(00:02) - The function lines specify the type of data transfer (or non data transfer) to take place. Table 2-20 lists the functions impiemented.

Table 2-20

Table Data Transfer Commands

F0O

FOI

FO2

Openation

o
1

(ONO
CON]

[

BATAO

DATAI

DEMAND (DEM} - This line causes the addressed controller to inspect the CS and F lines and decode
theit meaning. Upon implementing the specified function, Transfer and Acknowledge are asserted in
response and data is placed onto or taken from the EBus as specified by the decoded function.

ACKNOWLEDGE (ACK) - This signal line notifies the 1/0 bus adapter not to respond to the current
operation. If it does not detect ACKNOWLEDGE within some period foliowing assertion of
DEMAND, it attempts to perform the transfer. it does not decode the CS lines as the standard KL10
devices do.

TRANSFER - This line is asserted by the selected controlier when it is ready to exevute the specified
function as decoded in F(00:02).

EBOX. 2-173

PRIORITY TRANSFER LINES - To perform priority interrupts between the KL10 and its devices,
the same basic set of signals is used in a slightly modified form. Table 2-21 lists the nccessary signals as
they are used.

Table 2-21

Priority Transfer Signals

Name

Mnemonic

Contralicr Select

CSU8 06)

Number of Lines

3
K
!
1
1

CH 0
+H00:02)
DIM
ACK
\H R

Contratler Select
Function
Demand
Achnuwledge
Transter

CONTROLLER SEL CS (04:06) - During interrupt arbitration, these three lines represent the octal
encode of the interrupting channel.

CONTROLLER SEL CS(00:03) - These four lines specify the controller or device that the EBox is to
honor during this interrupt seauence. This is, of course, only a single device or controller, even though
several may be interrupting on the same channel. This code also corresponds to the hardwired physical
device number of the appropriate controller or device. In CONTROLLER SEL CS(00:03), the range is
0 through 17.

)

FUNCTION F(00:02) - Two functions are generated during the interrupt dialogue. The first is a code

of 4 in F(00:02) and specifies 10 the interrupting controllers that those controliers being addressed by

Channel number in CS(04:06) shouid send their Physical Controller number by placing them onto the
EBus upon sensng DEMAND. The second function is a code of § in F(00:02) and specifies to the
interrupting controllers or devices that one has been selected. The selected controlier will see CS(00:03)
as the same number as its physical controller number.

ACKNOWLEDGE (ACK) - Same as for data transfers.

TRANSFER (XFER) - In the case of interrupts, the device selected for service by the EBox places a
special function on the EBus data lines D(00:35). Figure 2-99 is the EBus interface functional block
diagram. Table 2-22 lists the priority transfer commands.

Table 2-22

Prority Transfer Commands

FoO

FO1

FO2

Operation

1
1

0
0

Q
1

Pl SERVED
Pl ADDRESS IN

EBOX/2-174

oaa £om can

1
1
1

1
1
|
I

LEL

TTeanoers $1ars

1oh

]
]
|

|
som con oo

o s e

B
S

ore 30

PO,

2y SO P2 CYCLE 4 cow
P

igure 2:99

EBus Interface Functional
Block Diagram

EBOX/2-175

2.12.2

EBus Interface Organization

Referring to Figure 2-99, the interface consists basically of six functional elements. These clements are

as follows:

A A e N

Pl Request Decoding and Control
P! Request Counter and Control
EBus Request and Control
kBus Dialogue Control
Pl Timer and Time State Control

Time State Generator

The EBus request control and EBus dialogue control are used both by the EBox to carry out 1/O
transfers and by the Pl sysiem in response to an interrupt. During priority interrupt handling, the
FBus dialogue is carried out in asynchronous fashion. This operation is controlled by the PI timer and
time state control, together with the time state generator.

To obtain the use of the EBus dialogue control, the Pl request decod'ng and control logic must compete with the EBox. No priority exists, and control is obtained on & firsi-come. first-served basis. Once
the EBus has been granted to the EBox, the priority interrupt must wait until the EBox releases the
bus.

11 the PI system obtains the EBus, the EBox may “*demandTM the EBus if a page fault occurs (EBus
Return).

2.12.3

Interrupt Handling - Loading the Request

Referring to Figure 2-99, there are two cases. The first is an interiupt request from some device on Pl
1-7. This may be from any K L10 device, including the APR. The second case is an interrupt from the
DTE20 on channel 0. Only the DTE20 may generate channel 0 interrupt requests.

In cither case, the Pl request enters the Pl request decoding and control logic. Here there is a variation
in priority. The Pl system must be turned on in order for a request on channel 1-7 to be inspected,
while interrupts on channel 0 will always be inspected whether the Pl system is on or off. The ring

counter controls the sampling of PI requests and also determines when a particular request (the highest) is ready to be serviced. In general, “Pl LOAD" enables all active requests 0-7 into a request
register, providing corresponding PI ON ensbles are on for channels 1-7.

A programmer may disable interrupts on selecte. hannels by clearing PI ON for each channel he
desires to inhibit (note PIONO is in ihe DTE20). This is done by performing a CONO P1 instruction.
While the ring counter advances through “WAIT 1TM and “WAIT 2,TM the priority network srbitrates
all incoming priority interrupt levels and seiects the one with the highest priority (numerically lowest
number).

2.123.1 Testing the Request - Next, PI TEST is asserted with Pl REQ to request the EBus. PI TEST
remains true until EBUS PI GRANT scts, giving the EBus to the Pl system. Once PI GRANT sets, the
PI TEST condition is cleared and the ring counter is disabled until the entire EBus dizlogue is carried

out and Pl CYCLE is "'set and clearedTM by the microprogram.

2.12.3.2 Requesting the EBus - Setting EBUS PI GRANT begins the EBus dialogue by enabling the
assertion of CS 04-06 as the selected channel and FOX4) as function P1 SERVED, and aiso causes the
Pi umer to begin its sequence by setting Pl CYC START.

In general, all external devices that connect to the EBus are presumed to be composed of TTL logic.
The P! and EBox logic consist of ECL logic. To temporarily connect these two different types of logic
requires use of a logic level shifter. This device is called a translator. The translator must be notified of
1he conversion direction, TTL 10 ECL or ECL to TTL. Actually, only the data portion of the EBus is
switched from one level 1o the other. The control signals are connected to fixed level shifting logic. For
exampie, EBUS DEMAND is a unidirectional signal and it is connected to 2 noncontroilable level
shifting gate on the translator module (ECL 1o TTL).

EBOX2-177

2.12.3.3 Beginning the Dialogue - The setting of PI EBUS PI GRANT asserts the level Pl GATE
TTL TO ECL. which causes translation of incoming data from TTL logic levels to ECL logic levels.

The PI timer and time statc control manipulates the time state generator such that each time state is
held for the appropriate length of time. The following relationships exist between the dialogue signals
and the time state logic:

CSH 04-06: EBUS PI GRANT
F00: EBUS Pl GRANT
DEMAND: sent at T2, TS, and T6
LATCH INCOMING PHYS numbers: T3
CS00-03: T3
F02: T4

EBUS TRANSFER: WAIT AT TS5 FOR TRANSFER
Pi CYCLE: WAIT AT T6 FOR Pl CYCLE TO SET

2.12.3.4 Interocks and Dialogue Completion - Upon entering TS, the timer is inhibited from

incrementing the count until EBUS TRANSFER is received or forced. While waiting, the timer holds
the loaded count. As soon as TRANSFER is received and recognized by the Pl logic. the timer is once
again allowed to count down TS.

Thus, while TS is counted down, the APl word is stabilizing on the input to AR. Next, T6 is entered
and here the absence of Pl cycle causes STATE HOLD to be asserted. This time the timer may count
down and even gencrate TIMER DONE. If this point is reached and PI CYCLE is still false, the timer
loads the count specified by T6 and continues 10 count while waiting for PI CYCLE 10 set. The Pi
board must not begin to service a second interrupt before the microprogram has a chance to look at
the first one. Hence, the timer is prevented from entering T7 COMP, until the microprogram has set Pl
CYCLE. This also enables the ring counter to perform load.

Assuming Pl CYCLE sets, the time state generator proceeds through T7 and into complete (COMP).
Note that the EBus dialogue control removes DEMAND some time before removing the CS and F
lines. This avoi ‘s the possibility of misselection of a device. The generation of COMP enables Pl
EBUS PI GRANT to clear, removing FOO and CS04-06.

2.12.4

Basic Input Output Control

Referring 1o Figure 2-99, the implementation of 1/0 operations is similar to interrupt processing, if
taken at the point where the EBus is requested. The difference is that instead of a hardware arbitration
process taking place, followed by a single request subsequently asking for the EBus. the microprogram
170 handler (part of the executor) requests the EBus. This is accomplished utilizing the condition field
function COND/EBUS CTL, together with a particular pattern in the magic number ficld all in the
same microinstruction. Only the resulting signal is indicated on the figure (APR EBUS REQ) but the
various other signals are simply formed by combinations of COND/EBUS CTL and an appropriate
magic number.

2.12.4.1 Requesting the EBus - The EBus request control treats both an EBox-EBus request (APR
EBUS REQ) and a Pl EBus request cqually. Whichever request is seen by the EBus request control
first receives the EBus.

The microprogram is waiting for an indication that it has been granted the EBus. The indacation of this
condition is EBUS CP GRANT. The microprogram loops, waiting for this signal to become true.
Once this occurs, the next sten in the operation may be performed.

2.12.4.2

Dialogue Overview - Basically, the EBox decodes bits 10-12 of the instruction to determine

which type of 1/0 operation is to be performed. Eight possible combinations exist: these are indicated

in Figure 2-100 at the bottom left. The logical mapping of 1/0 op code intc appropriate DRAM
addresses is also illustrated in Figure 2-100.

EBOX/2-178

mecms

fresroemindl

oata

Figure 2-100

EBus Control Functions
(Sheet 1 of 2)

EBOX/2-179

_/‘.a_r_h.-

comma
m

Figure 2-100

EBus Control Functions
(Sheet 2 of 2)

\
EBOX 2181

10100

The dispatch to the proper operation is obtained by mapping bits 10-12 into DRAM ADR 06-08,
while the device address 3-6 is mapped into DRAM ADR bits 03-05. Thus, for example, a DATAI

APR with op code 701 is mapped into DRAM address 701. Similarly, BLKO PAG, with op code 722
is mapped into DRAM address 722. This is device 010y; therefore, the type of operation performed is

determined in advance and the DRAM jump address is coded to cause a jump to the appropriaie
group of microinstructions. The device sclect code is in bits 3-9 of IR and must be used to address the
device. This addressing is accomplished by converting 3-9 to CS00-06 in the proper form. The function is controlled by the combination of two F3ox control signals, APR EBOX SEND F02 and APR
EBUS FOL. With these two signals, all combinations of input and output operations may be performed
as indicated on Figure 2-100. Notice that EBus F0O is not used for any of the operations. This signal is
generated dunng priority interrupt dialogue for the function Pl SERVED (Function 4) and for Pl
ADDRESS IN (Function 5).

baliad il

2.12.43 Functional Breakdown - Figure 2-100 is essentially composed ofthree sections. The first1s a
breakdown of the EBus microcode operations into four basic suboperations as follows:
Basic EBus operation as uscd by all {/0 instructions.
ECL EBus acquisition and subscauent release
Generation of the DATAO function followed by the basic EBUS operation
Generation of the DATAI function followed by the basic EBus operation

The second section illustrates how the operation specified in IR 10-12 and a portion of the device
select code IR 03-05 are mapped into the DRAM words that periain to 1/0 operations.
Finally, the third section consists of a simplified flow of the basic EBus operation. including the
handshake between the microprogram EBus driver and the PI Board.
Basic EBus Operation
This is illustrated in the flow on the bottom right of Figure 2-100. Five basic COND/EBUS CTL
functions are generated from particular magic number bits. The first is to request the EBus from the P1
Board. This consists of asserting APR EBUS REQ.

The microprogram now loops, waiting for an indication that it has obtained the EBus. The indication
consists of receiving EBUS CP (Central Processor) GRANT from the PI Board. This moves the microprogram to the next logical step which is IO INIT. Here magic number 5 enables the function lines FOI
and F02 10 be driven from -APR AC10 and APR F02 EN, respectively. The table of 1/0 operations
given at the bottom left on Figure 2-100 shows that FOI is true whenever AC10 is false. This is true for
DATAO. DATAL BLKO, and BLKI. Conversely. F02 is true whenever AC10 is true, or both ACI10
and ACI] are false.

Finally, DEMAND is removed by issuing the function CLR EBUS DEMAND. Notice that number
4
holds the function lines up. It is necessary to remove DEMAND first while still maintaining the
function and CS lines in order to prevent a spurious misselection. Now the function and CS lines are
dropped and the EBus is relinquished by issuing RELEASE EBUS. This action causes EBUS CP
GRANT 1o clear.

Pl Handler and EBus Operation

Once again referring to the flow on Figure 2-10C. note that after issuing EBUS REQUEST and while
testing for CP GRANT, an interrupt is tested for. ¥ an interrupt is pending, the Pl Handier is entered.
This means that EBUS P1 GRANT was set when EBUS REQUEST was issued and EBUS CP
GRANT could not set anyway.

The PI Board has ncgotiated with the device for the AP function word th:t is now on theinput to AR.
The PI Board is holding in T6, waiting for Pl cycle to be set.

Examine. Deposit. or Byte transfers requested by the 10-11 interface require separate control of the
controller select and function lines. For these cases, SET DATAO or SET DATALI is issued independently. Then the EBus routine is entered at the point where the CS and F lines are setting up. If the
aperation is DATAO of TO1! transfer, the AR is placed onto the EBus vis AD. The remainder of the
EBus operation is identical to that for basic EBus operation.

ECL EBus Acquisition - A1 various times, the ECL portion of the EBus is required for some form of

transfer. Some examples of this requirement would be processing interrupts for internal devices such as
APR, PISYSTEM, or TIM. Also, performing 1/0O instructions involving these devices would require
the use of the ECL EBus. A second example is the case of page fault handling in the microcode. At
some time, the MBox-EBus register must be read over the EBus into AR. Thus, the ECL EBus is

necessary for this operation. The function necessary to acquire the ECL EBus is COND/EBUS CTL
with magic number bit 0 set. This actually takes the EBus away from the Pl system. It does not abort
the Pl operation (if any) but merely causes it to be dealyed. The signal APR EBUS RETURN causes
the P1 imer and time state generator to HOLD and it clears EBUS Pl GRANT. The ECL EBus is
relinquished by issuing RELEASE ECL EBUS, which takes away APR EBUS RETURN. Now the P}
may conzinue from the point at which it was held.
2.12.8

Pl ead EBus to Microcode Interface

related hardware with the Pl Handler and EBus Driver. Both of these handlers are microprograms.
Figure 2-101, illustrates the basic signal interfacing between fucntional elements of the PI Board,
Control Number | Board, and various EBox hardware used during EBus transactions with the Microcode Pl Handler and EBus Driver. Figure 2-102 generally relates the Pl Handler and EBus Driver

functions to the Pl Board hardware for given operations. Figure 2-103 is supplied to support function-

Magic number 4 is used 1o latch the particular function (HOLD IT). Note that duning the 10 INIT
period, IR 03-09 is passcd to the Pl Board to become CS00-06. A fixed delay is generated by the

microcode at this time to allow the controller select lines to set up at the device.

Next, SET EBUS DEMAND is issued, while holding the previous function lines FOl and FO2 as

previously set up. Once again, the microprogram waits a predetermined period. The waiting is controlled by the lime field and the number of successive microinstructions issued. Thus, two successive
microinstructions with T = 5 is approximately 300 ns.

Now the microprogram loops, waiting for TRANSFER from the device. This signal indicates that the
device has completed the specified transaction and has cither taken or transmitted status, data, or
control over the EBus. At this time, if the operation was CONSO, CONSZ, CONI, BLK1 or DATAIL
the EBus is loaded into AR. If the operation was CONO, BLKO or DATAO, during 10 INIT the AD
is enabled to the EBus. The AD contains the contents of AR.

EBOX/2-182

Figures 2101, and 2-102 are concerned with the interaction of the P1 Board and certain other EBox :

al descriptions to follow.

2.12.5.1 Sensing the Interrupt - Initially, assume that the PI Board is enabled and idle. Two devices
(DSK) assert interrupts on the same priority interrupt channel; DSKA on channel $ and DSKB on
channel 5. Thus. based on the fixed physical number scheme, the range of physical numbers is 0-7.
Further, assume that DSK
A is wired to be physical number | and that DSKB is wired to be physical
number 7, and that DSK
A is the device selected.

Referring to Figure 2-101, Pl Level § is received from both devices and is loaded into Pl Request
register 5 for arbitration. Because both DSKs are interrupting on the same channel, the Pl Network
need only check those channels holding interrupts. If none is holding on 5 through 1 (0 is DTE20 and
never holds), then channel § is selected. The next phase begins by asserting REQ to obtain use of the
EBus.

EBOX/2-183

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[

Figure 2-101

EBox Pl Board

10 Microcode Interface

EBOX/2-185

ro-yrsia

Figure 2-102

EBus Control Hybrid Flow

(Sheet
1 of 2)
EBOX 2-187

Figure 2-102

EBus Control Hybrid Flow

2)
(Sheet 2 of
EBOX/2-189

Figure 2103

Time State Generator Control

21252 Requesting the EBus - To obtain use ofthe EBus, the Pl logic must set EBUS PI GRANT.
This s illustrated on Figure 2-102. Note that the following requirements must be fulfilled to set EBUS

Pl GRANT:
PI test must come up.

REQ must be true (PI 4, 2, | = some selection).

The Ebox may not be halted or there are no interrupts selected on 1-7.
EBUS PI GRANT is currently clear.
The Pl Board is not trying 1o set CP Grant.

1f all five conditions are satisfied, EBUS P GRANT sets. If the conditions are not currently satisfied,

the interrupt waits.

2.12.53

Beginning
the Dialogue — At this time, several events take place. The setting of EBUS PI

GRANT enables setting of cycle state, which begins the dialogue. In m-uu. the PI Timer (— the
table on Figure 2-104)is loaded with 25, which defines the duration of the time state entered,in this

case time |. Thtnmtn‘ulm\lldw&mlheEludub‘uefmqumu.wmphm EBUS
PI

GRANT forces FO0 to a 1. This function (4) is PI served and is issued together with CS 04-06,

which are encoded 10 be the selected channel (5). The interrupting devices (in this example two DSKs)
decode
the function lines F00-02, together with the controller select lines CS 04-06. The PI timer
counts from 25, to 37 then generates TIMER DONE. The devices have now had sufficient time to
decode the CS and F lines so the next phase of the dialogue begins. The timer is now loaded with 11y,
Time T1 is removed and T2is entered.

EBOX 2-191

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Figure 2-104

Pl Timing

EBOX/2-193

Time 2 enables EBUS DEMAND. Note that the function PI served and controller select lines are
maintained. The DSKs are commanded to place their **hardwired” physical numbers onto the EBus,
bit | for physical number 1 and bit 7 for number 7. Referring to Figure 2-103, DEMAND is held up
through Time 2 and then removed while the F and CS lines are maintained. It is good procedure to
remove the DEMAND signal before attemping to change the function lines; this avoids any spurious
misselection. The timer is next loaded with 25, and T3 (a brief time state) is entered. Here, two fur~tions are performed:
1.

The physical numbers, by now on the inputs to a register on the PI Board, are clocked into
that register for arbitration.

The Pl Board is timing out a period of time until it is safe to change the function lines.

The next part of the dialogue is begun when Time 4 is entered.

Here, FOO and F02(5) are asserted; CS00-03 reflect the encoded physical number that has highest
priority (#01) and CS04-06 still reflect the Pl channel being served. When Time 4 is removed and TS
sets, DEMAND is asserted once again. This time DSKA is selected as the DSK 10 be serviced.
DEMAND commands DSKA to place its APl word on the EBus and to assert EBUS TRANSFER to
the EBox. The Pl Board waits in Time 5 until TRANSFER is received, or forced. I, for example, the
interrupting device (DSKA) can respond to most of the dialogue but cannot send EBUS TRANSFER,
the PI Board waits. If TRANSFER is not forthcoming, TRANSFER is forced and the EBus (which

contains zeros) is treated as an API function of 0. This ultimately causes a 40 + 2u interrupt on the
interrupting channel. The DSKs service routine must then decide what weat wrong. Assume that the
DSKs succeed in placing the appropriate APl function word on the EBus and generate TRANSFER.
The timer is loaded with 35, and Time 6 is entered where Pl READY is asserted. At this point, the Pl
Board is notifying the EBox microprogram that the APl word is currently on the AR mixer inputs.

2.12.5.4 Terminsting the Dislogwe - With the assertion of PI READY, the Pl Board waits in Time 6
until the Pl Handler (microcode handier) looks at the interrupt. PI READY enables INT REQ to set
in the EBox and when the Pl Handler detects this, it sets Pl CYCLE. Now the timer continues by
entering Time 7, drops DEMAND and finally enters COMP, where the CS and FUNC lines, together
with EBUS Pl GRANT, are removed. This completes the Pl Boards dialogue.

2.12.5.5 Eatry to the Pl Handler - Referring to Figure 2-102, the handler is entered at symbolic
location INTRPT, with the API word loading into AR, and PI CYCLE no! yet set. Thus, the Pl Board
i a1 this time in Time 6, waiting for PI CYCLE to be sex. The shift counter is loaded with 2, in order to
enable the APl word in AR to be shifted left two positions, bringing the function code in bits 03-05
into bits 01-03. PI CYCLE is set and then a shifi dispatch is given; depending upon the function 0-7,
the dispatch is to one of eight routines within the main handler.
Function 00 - STD INTERRUPT NO TRANSFER
The word is buffered in MQ. The VMA is loaded with the appropriate 40 + 2n address. This address is
implemented via the SCD TR AP mixer (refer to Figure 2-60) and derived from number with PI 4,2, 1.

PI 4, 2, 1 is simply t} » octal equivalent of the channel on which the interrupt was taken. Thus, the
instruction is fetched from 40 + (2 X 5) in the example cited in Subsection 2.8.5.3. This yields an
address in VMA of 0000050.

The program branches to Execute Wait (XCTW) where the microprogram waits for the instruction
fetched to load into AR. This instruction should be a “JSR,TM which saves the flags and PC and then
enters a subroutine in main memory to deal with the situation. The performing of a JSR causes
SPEC/SAVE flags, which clear Pl cycle and set Pl HOLD, 10 hold the interrupt.

EBOX/2-195

Function 01 - STD INTERRUPT K110, KA10 Device via 1/0 Bus Adapter or K1.10 Device via EBus
The implementation of this function is identical to that for Function 00. The difference between the
function codes is that Function 01 is a premeditated request for a *STD INTERRUPT.” where Function 00 is a bus failure condition.
Functioa 02 - VECTOR INTERRUPT
The word is buffered in MQ. The API word contains an address in bits 13-35 and an address space
qualifier in bits 0-2. The address is loaded into VMA. Now a dispatch is given on AR00-03. The API
word format is presented on Figure 2-102. Note that only threc address spaces may currently be
specified:
0 - EXEC PROCESS TABLE (EPT)
I - EXEC VIRTUAL ADDRESS SPACE
4 - PHYSICAL ADDRESS
A routine is called for the storage operation PILD (illustrated in Figure 2-102).

Fetching from EPT - T
VMA bits 27-35 receive the AR bits 27-35 via AD. The EBox makes an EPT reference. Referring to

Figu.e 2-83, the qualifiers asserted to the MBox are as follows:

EBOX REQUEST
VMA EPT

PAGE UEBR REF
The hardware normally looks at a combination of SPEC/SP MEM cycle with magic number and user
enable to sclect cither VMA EPT or UPT. depending on the state of user. In this case, however, user
must be disabled to enabie a direct reference to EPT. The AR is loaded with the instruction fetched
from CPT. This instruction is either the first of a series of instructions in a service routine or an
instruction directing entry to a service routine. As with 40 + 2n interrupt instructions, the instruction
should be a JSR 10 save the flags and PC. By performing 8 JSR. SPEC/SAVE flags clear PI CYCLE
and set P HOLD on the Pl Board. This holds the interrupt.
Fetching from EXEC Virtual Address Space
The APl word is buffered in the MQ. For this case, the address in bits 13-35 of the APl word is a
complete virtual address. In fetching from EPT, only bits 27~35 of the address in bits 13-35 contain
address information. The MBox appended a base address (EBR) to this 9-bit address. Here the request
qualifiers are as follows:
EBOX REQUEST
EBOX READ

Function 03 - PI INCREMENT
This function causes a word in the specified address (AP] word bits 13-35) to be incremented or
decremented as a function of the Q BIT in the API word. If Q = 1, the function is decremented;
otherwise, it specifics increment. Referring to Figure 2-102, the APl word is buffered in MQ and Q is
tested. If Q = O, the contents of the address specified in the APl word 13-35 are fetched and
incremented. The incremented word is then stored back in the same address and an instruction fetch is
performed from PC. This contains the interrupted program. Note that the microcode must set Pl
HOLD in order to hold an interrupt on the Pl Board. This is done when the 40 + 2n or vector function
fetches and performs a JSR or similar instruction. Here, after completion of the storage operation, the
interrupt is dismissed and Pl CYCLE is cleared. Pl CYCLE is cleared with SPEC/FLG CTL and
number 02.
Fuaction 04 - PI DATAO or EXAMINE
The 10-11 interface may perform an Examine function 10 cither core memory or fast memory. In
addition, the address supplied in the APl word may be a relocated address or not depending on the Q
BIT in the APl word. Associated with the Examine operation are two words of information for each
10-11 interface in the system. These word pairs are in predefined areas in the EPT. One word of the
pair is a protection constant, which limits the address of the virtual address sent in the APl word. The
number of pages specified in bits 13-26 may be less than or equal to the value of the protection
constant, but not greater than that value. The microprogram utilizes the low-order 2 bits of the physical number supplied to the APl word (bits 7-10) and forms an address 140 + 8n, where n is the loworder 2 bits of the physical number for the interrupting 10-11 interface. The physical numbers are
hardwired as 10y~13,. This gives low-order 0, 1, 2, or 3. The EPT location thus obtained is accessed for
the protection constant and the comparison is made. If a violation occurs (protection violation), a
word of zeros is transmitted to the 10-11 interface via the EBus. If no violation occurs, the relocation
word is fetched from EPT and added to the address supplied in 13-26 of the API word. This address is
now treated as a physical reference and it is not paged. The word is obtained and transmitted via
DATAO function to the 10-11 interface. Upon completion of the EBus dislogue, the PI CYCLE is
cleared. Note that for the 10-11 interface Examine function, the interrupt occurs on channel 0.

This channel is implemented solely to enable the 10-11 interface to utilize the Pl facility at any time,
whether it is on or off for DMA type transfers. No HOLD flip-flop exists for PIO, so clearing Pl
CYCLE effectively releases the P10 interrupt. Devices other than the 10-11 interface may utilize this
operation under the classification PI DATAO. Two diflerences in its implementation from that of
Examine exist. First, no protection or relocation is applied and hence no violation can occur. A page
fault, however. can occur. If this occurs, the PF Handier sets IOPF and transfers control to the operating system. The sccond difference is that other devices interrupt on channels in the range of 1-7.
Once again, holding the interrupt for this one time transfer is unnecessarv and only clearing Pl
CYCLE is necessary to release the Pl Board. Other than these differences, the vperation is identical to
Examine.

The MBox translates the address and supplies the instruction that loads into AR. Once again, transfer
is to XCTW, 10 wait until the instruction actually loads into AR. Then the instruction is performed as
with the previous EPT reference.

Fetching from Physical Memory
Here, the address contained in the APl word bits 13-35, contains a physical address in bits 22-35 while
bits 13-17 are clear. To cause a physical reference to occur, the magic number field is coded with

Functioa 05 - Pl DATAO or DEPOSIT
In terms of the 10-11 interface, this operation is the reverse of Examine, except that after the 10-11
interface sends the AP function (which contgins the address), the EBox must perform a DATAIL
function to obtain the 36-bit word to deposit in the specified address. A second difference is that if &
violation occurs, after performing the protection check a violation occurs, no word is stored in the
specified address. With these exceptions, the operation is basically the same from the point where the
36-bit word is obtained from the 10-11 interface to the completion of the operation.

number 08 set and this, together with SPEC/SP MEM cycle, inhibits the qualifier MAY BE PAGED.
If this signal is not present during EBus request, the MBox does not page the address. The instruction

loads into AR as before and then performs. Once again, SPEC/SA
VE flags clears PI CYCLE and sets
Pl HOLD.

EBOX/2-196

EBOX/2-197

Function 06 - Pl BYTE TRANSFER

This function can only be carried out between a 10-11 interface and the EBox. This function is initiated
on Pl channel 0 as are Examine and Deposit. The transfer is part of either a TO11 or TO10 byte transfer
occurring in the 10-11 interface. The information being transferred is cither a byte right-justified in
EBus bits 28-35, or a word right-justified in EBus bits 20-35. The APl word specifies whether the
transfer is TO10 or TO11 by the state of the Q BIT. If Q = 1, the transfer is TO10; otherwise. it isa TO11
transfer. In addition, the Pl Board is supplying the physical number in bits 07-10 of the EBus while the
API word is present. The other portions of the word 0-2, 11-35 are ignored.

T010 Byte Pointer Fetch, Byte Read, and XFER

The low-order two bits of the physical controller number O, 1. 2, or 3 are obtained and combined with
EPT base location 14X to form the EPT location of the TO11 byte pointer. Next, the byte pointer is
obtained from the EPT and updated. The pointer is a standard KL
10 byte pointer. The microcode for
load byte instryctions is used for the pointer update. Note that the byte pointer may specify indirection
and/or indexing. Once the effective sddress has been calculated, the updated byte pointer is stored
back in its slot in EPT and the byte is obtained by performing an EBox request. Finally, the byte now
in AR is transferred via the EBus (DATAO) to the 10-11] interface and PI CYCLE is cleared.
TO10 Byte Pointer Fetch, Byte Transfer and Storage
The byte is initially requested by issuing a DATALI to the 10-11 interface. The byte is then picked up via
EBus 28-35 and loaded into ARX and into BRX. Next, the low-order two bits of the physical controller number 0, 1, 2, or 3 are obtained and combined with EPT base location 14X to form the EPT
location of the TO10 byte pointer. The byte pointer is obtained from the EPT and updated. The pointer
is a standard KL
0 byte pointer. For the T011 XFER, the microcode for deposit byte is used for the
pointer update and, as with the byte pointer for T0O11 XFER, may specify indirection and /or indexing.
Once the effective address has been calculated, the updated byte pointer is stored back in its siot in the
EPT and the byte is stored in the pointer’s effective address. Finally, PI CYCLE is cicared and this
terminates the operation.
Function 07 - UNASSIGNED
This function is unassigned and currently behaves the same as function 00.

EBOX/2-198

SECTION 3
LOGIC DESCRIPTIONS

In this scction, a selection of the twelve board types comprising the EBcx are described in detail.
Wherever possible, a functional perspective is given to highlight the particular functions a board or

portion of 4 board implements, and multiple boards are shown interconnected to aid in tracing various

control signals from one functional arca to another.
PHYSICAL CONFIGURATION
The EBox consists of a total of 23 modules, configured as indicated in Figure 3-1. A brief description
of each module is contained in the following paragraphs.
Module M8532, Priority Interrupt Control { PIC} - One board, illustrated on customer prints PIC
1-6, contains Pl ON register 1-7, P GEN register 1-7, PI REQUEST Register 07, Pl HOLD
register 1-7, and the Pl ACTIVE flip-flop. In addition, it contains the priority interrupt networks
for arbitration of priority interrupt requests, EBus dislogue logic. control and internal timing,
and the assignment registers for the ABR: PIA APR 1,2,4 and Meter PIA 1,24,

Module 8526, Clock {CLK] - One board, illustrated on customer prints CLK 1-6, contains the
crystal-controlied master clock oscillator and crystal-controlled margin clock oscillator, as well as
Source and Rate Selection registers and their associated logic. It contains logic and counters to
produce the EBus clock, SBus clock, MBox clocks, and EBox clocks. In addition, it contsins
single step, burst, normal, and diagnostic mode logic and registers. It also contains MR reset,
EBus reset, crobar logic, error detection logic, page fail, and MBox request logic.
Module 8539, Arithmetic Processor Status (APR) - One board, illustrated on customer prints
APR-7, contains an 8-bit APR Status register, 8-bit Interrupt Enable register, and associated
interrupt request detection logic. It contains the EBus dialogue control logic used while performing 1/O instructions. In addition, it contains the address break compare enable bits, fetch
comp, read comp, write comp, and user comp. It contains a 5-bit section register, fast memory bit
36. RAM storage, and parity network. it also contains the fast memory block and word addressing logic. mixers, adder network and current, previous XR, and VMA Block Selection registers. It
also contains MBox control and MBox register function decoding logic.
Module 8525, EBox Control No. 2 {CON) ~ One board, illustrated on customer prints CON 1-6,
contains CRAM condition field decoding: COND and SKIP enables; and VMA select lines CON
VMA SEL 1 and 2. [t contains meter, interrupt request and interrupt reguest detection logic, run
and continue logic, IR strobe, DRAM strobe, start logic, various flip-flops, and associated sychronizer logic. It also contains the NICOND decoding and COND ADR bit 10 logic. It containsa
4-bit State register, diagnostic function decoding logic, Parity Enable register, Cache Strategy
register, paging tnable, trapcnable bits, and /0 costrol signals for CONO APR, CONO PI,
CONO PAG. and DATAO APR. It contains the Load AC blocks and Load Previous Context
signals, 4-bix Microcode State register, AR and ARX bit 36 with associated logic, fast memory,
write Jugic, various Pl control signais, and associated logic.

EBOX/3-1

Maodule 8527. EBox Control No.l {CTL} - One board, illustrated on customer prints CTL 1-4,

contains CRAM dispatch, field decoding, some adder carry control logic, and register mixer
sclection cantrol logic for AR, ARX. MQ. and PC. It also contains the majority of the diagnostic
decoding logic and the translator enables T to E enable and E to T enable.

Maodule 8523 Virtual Memory Address (VM A) - One board, illustrated on customer prints VMA
I1-6. contains an 18-bit VMA adder, YMA AC reference detection logic. a 23-bit VMA register,

and associated input mixing logic. It also contains s 23-bit Address Break register, associated
match logic, 23-bit Program Counter register, 23-bit VMA Held register, and AR Mixer Mixer

(ARMM) logic bits 13-17.

Module 8512, Data Path (DP) - Six boards, illustrated on customer prints DP 1-$, each contain

six bits of a full 36-bit data path. Each board contains the following mixers: AR Mixer (ARM),
ARX Mixer (ARXM), MQ Mixer (MQM), ADA Input Mixer, ADB Input Mixer, ADXA Input
Mixer, and ADXB Input Mixer. In addition, each board contains the following registers: Arithmetic Register (AR), Arithmetic Register extension (ARX), Buffer Register (BR), Buffer Register
extension (BRX), and Multiplier Quotient register (MQ). It also contans fast memory, the adder
(AD), and adder extension (ADX). In addition, it contains the fast memory, write pulse generation logic. and fast memory, write pulse generation logic, and fast memory parity network.
Module 528, Control RAM (CR) - Five boards, illustrated on customer -rints CR 1-7, each

contain 14 bits of the control word (microinstruction) stored in RAMs containing 1280 words. In
addition, each board contains CRAM address ga‘ing and 14 bits of the CRAM output register
(CRAM register).
Module 8511, Control Ram Address {CRA) - One board, which is illustrated on customer prints
CRA 1-6. This board contains the circuitry to generate the address of the next CRAM word. This

inciudes the microcode pur -down stack, plus the Dispaich and Skip logic.

Module 8510, Shift Mairix ISH | - One board, illustrated on customer prints SHM 1-5, contains
shift counter decoding logic, shift matrix, and AR and ARX parity networks.
Module 8530, Memory Control (MCL) - One board, illustrated on customer prints MCL 1-7,
contains CRAM MEM field decoding: memory request enable logic; request type decoding, e.g..
MCL VMA Read, MCL VMA Pause, MCL VMA Write. It also contains User and Public
Enable logic. as well as all the request-type qualifiers. It contains bits 1-12 of the VMA Held or
PC Mixers, together with various VMA Control and Selection logic.

Module 8522, IR. DRAM. and Carry (IRD} - One board, illustrated on customer prints IRD }-$,
contains the 13-bit Instruction register (IR), 4-bit IRAC register, DRAM address mixers,
DRAM, and 15-bit DRAM Output register. In addition, it contains the IR Test Satisfied logic
and normalization CRAM address bits (IR NORM 08-10). It also contains the AD and ADX

carry anticipation networks (CARRY SKIPPER).

Module 8524, Shift Counter Adder {SCA D) - One board, illustrated on customer prints SCD 1-6,
contains the 10-bit Shift Counter registe: and associated input mixer, 10-bit Floating Exponent
reg.ster, and associated input mixer, AR Mixer Mixer (ARMM) bits 0-8, and SCD TRAP Mixer
(32-35). It also contains the 10-bit Shift Counter Adder (SCAD) as well as the Program Counter
Flags register and mode control logic.
INSTRUCTION REGISTER LOADING AND CONTROL
Refer to Figures 3-2 and 3-3. The IR is composed of 13 mixer latches as illustrated. The defauit
selection is AD selected by -CLK MB XFER. The slternate selection is the cache data lines selected by

CLK MB XFER. Because the IR consists of laiches (DC devices), the clock is used indirectly to
synchronize unlatching and latching of IR. This is done by ORing the EBox clock with the control
signal on the IR Board. Unlatching the IR may be accomplished in one of three ways.

EBOX/3-2

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Figure 3-2

IR DRAM Control (Part 1)

EBOX/3-5

Figure 3-3

IR DRAM Control (Part 2)

EBOX/3-7

During an instruction fetch, a logic level MCL FETTH
is developed together with EBox Read. These
gualifiers are latched at the same time that the VMA is latched during the EBox request. They are
Latched until the next EBox request. Each time a memory cycle is begun for any reason, MEM CYCLE

sets. It remains set until one of two events occurs. Either MBXFER occurs in response to an MBox
orcle, or FM XFER occurs in response to an internal fast memory cycle. Either of these decouples the
fecdhack path for the MEM CYCLE flip-flop. Note that while MEM CYCLE and MCL VMA

FETCH are true. the IR is unlaiched because -CON LOAD IR becomes false removing HOLD IR.
A second method for unlatching the IR is via the microinstruction COND field function
COND LOAD IR. This may be used in cases where an instruction is loaded into AR 10 be executed.
The micrownstruction selects the AD function as “*ATM while selecting the AR on the ADA input.

Because the default selection for IR is the AD., the instruction in AR would appear on the IR input
mixer.

The operation of unlatching and loading in this manner 1akes one microinstruction as indicated in

Figure 3-4 Note that CLK IR is logically ORed with -CON LOAD IR on the IR Board.

L2 R

€873

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Figure 3-4

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[‘A.._,_(g

IR Loading Via AR (COND/LOAD IR)

By using diagnostic console function 014 (STROBE IR), information previously loaded into AR of
ARX may be loaded into IR. This provides a powerful diagnostic tool. In addition, this function is
used to address the DRAM while loading it.
When fetching instructions from fast memory via AD, it is sometimes necessary to use the COND/IR
LOAD function to enable AD to IR. Referring 1o Figures 3-2 and 3-5, VMA bits 32-35 address fast
memory as specified by the microinstruction FM ADR field. At the same time (for example), the ARX
field selects AD while the AD field selects “*BTM. The ADB field function is FM and once again the
COND field is LOAD IR.
Once again, note that the unlatching and latching of IR is in step with the EBox clock (CLK IR).

EBOX/3-9

LYOS -]

AZprw

YRR

ars

) ¢

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2wk :'.

N AT ey

hEA

;-n.w::n.

Figure 3-5

Loading IR Via FM (COND/LOAD IR)

1o
3.1.1 DRAM and IRAC Control
The DRAM register is controlled in a manner similar to that of IR. The DRAM register consists of 19
mixer latches. Refer to Figure 3-3; unlaiching the DRAM register may be accomplished in one of three
ways. As with IR, note unlatching and latching of the DRAM register is synchronized by ORing *" .
EBox clock with the control signal on the IR Board.

Each time that the COND/LOAD IR function is used to unlatch ihe IR, it also enables the generation
of CON LOAD DRAM on the next EBox clock. Thus, the IR unlatches beginning with the trailing
edge of one EBox clock and latches on the leading edge of the next. Similarly, the DRAM register
unlatches beginning with the trailing edge of the EBox clock that laiched IR, and latches once again on
the leading edge of the following EBox clock. The timing is illustrated in Figure 3-6.
A similar operation takes place following NICOND Dispatch. Referring to Figures 3-2 and 3-7,
NICOND is latched into a flip-flop on the control board at the same time that the microinstruction
selected by the NICOND Dispatch loads into the CRAM register.

LikAL

3 e

1B Od 0

Figure 3-6

CATCwE D

1;1-_]

DRAM Loading Following COND/LOAD IR

3.1.2 DRAM Addressing and Selection
Assume [IR EN 10, JRST, and IR EN AC are set. The DRAM addressing logic maps the incoming
instruction code into the DRAM register as indicated in Figure 3-3. Note that 1/0 instructions address
the DRAM in a slightly different fashion than non-I/O instructions. 1/0 instructions have bits 0-2 of
IR equal to 7; this is detected on the IR Board as IR INSTR 7XX and enables the DRAM ADR 1o be
formed as follows:
DRAM ADR 00-02 IR 00-02
DRAM ADR 03-05 [IR 7-9 v111]
DRAM ADR 06-08 IR 10-12
Asndicated on the figure, for /O instructions, IR 3-9 is the device select code. If bits 3-6 are equal to

Here we assume the case where some instruction has completed its swore cycle. An earlier microinstruction generated MEM /FETCH which started the EBox Request.

2ero. the device is local to the processor, i.c., in the EBox. Currently, there are six local devices:

EBOX/3-10

EBOX/3-11

APR: DEV 000
Pl: DEV 004
PAG: DEV 010
CCA: DEV 014
TIM: DEV 020
MTR: DEV 024
(UNUSED: DEV 000)

CRAM RE

SLE NTE 7

—

‘

3.1.3

IR TEST SATISFIED

3.1.3.1
Introduction - The IR TEST SATISFIED logic is illustrated in Figure 3-8. It is used with the
following types of instruclions:
CAMXX
CAIXX
SKIPXX

JUMPXX
TXXXX
BLKX
AOSXX
SOSXX
AOQJXX
SOJIXX
AOBIX
JECL

In general. these instructions test some condition or conditions and, depending upon the result of the
test. fetch an instruction. The fetch can be from PC+1 or PC+2, (in the case of CAIXX, CAMXX,
SKIPXX. AOS. TXXXX, and BLKX), or from E or PC+1 (in the case of JUMPXX, AOJXX,
SOIXX. AOBIX).

RESPONSE

o
WBIY

wbUF

WTES

Maac teats Bisert wg NIZOND
©4p OrC Wsit.ng for jasty

Mo |

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1 NIIOND Dap

Figure 3-7

NICOND Dispatch and Wailing

If IR bits 3-6 are nonzero. the device is external to the processor. This includes device select codes 034
to 774,
All other op codes in the range of 000-677 address locations in the DRAM that correspond to locations 000-677. This is illustrated in Figure 3-2. DRAM address 00-02 is formed from IR 00-02, while
DRAM address 03-08 is formed from IR 03-08.

3132 Implementation - To suppiement this section, five tables are presented (Tables 3-1 through 35). which aid in understanding the table presented in Figure 3-8. Table 3-1 is Skip, Jump, Compare
controls. This table is divided into four areas. Eight Skip, Jump, Compare controls arc indicated.
These are microcode mnemonics for the indicated coding of the DRAM B ficld and imply the type of
Skip, Jump. or Compare condition being tested. For example, the instruction CAIE compares the
effective address with the contents of AC and skips the next instruction in the program sequence if the
condition is satisfied. The DRAM B field mnemonic is **SICE.” which is & vaiue of 1 in DRAM B. The
coding of DRAM BO controls the sense of the skip. Thus, referring to Figures 3-9 and 3-10, IR TEST
SATISIFIED is the Exclusive OR of DRAM B0 with the signal indicated on the figure as “resultant.”
In the current example, because DRAM BOO0 is equal to zero, the IR TEST SATISFIED signal is true
only if the “resultantTM hine is true.
As indicated in Figure 3-9, the combination of AD = 0 with DRAM B 0] (0) and CRAM #07(1)
enables “‘resultant”TM to be true. This yields IR TEST SATISFIED. Referring to Figure 3-8, the VMA

contains E, which it received at AREAD time. The YMA field function is PC+1 [CRAM YMA SEL 1
(0) ACRAM VMA SEL 2(1)]. Because PC+! INHIBIT is false at this time, the “B" input to YMA

AD is equivalent to +1, while the VMA AD function is “A+B." The MEM field function is
“FETCH,” and the magic number ficld function is “COMP FETCH," which is coded as #201. Thus,

#01 (1) with “"FETCHTM and IR TEST SATISFIED gives MCL SKIP SATISFIED. Providing Pl

CYCLE is clear, MCL VMA INC increments the VMA AD SUM, which is now PC+1, 10 a value of
PC+2.

DRAM register bits 00, 05, and 06 are missing in the hardware (Figure 3-3). This prevents DRAM J
Dispatch from accessing certain CRAM locations.

Note that either bit of the CRAM VMA field enables one side of the MCL. VMA 1,6 gate and that IR
TEST SATISFIED or -MEM/COND JUMP enables the other side. This is necessary to allow IR
TEST SATISFIED to inhibit loading the VMA during Jump-type instructions. VM
A contained the
yump address prior to the test. Note that the magic number field function and MEM field function for
Jump-type instructions is different than that for Skips and Compares. It is necessary 10 prevent PC+2
from occurring and this is accomplished by blocking the term MCL SKIP SATISFIED. Because the
magic rumber field function for jumps, which is “JUMP FETCH,” has #01 (0), the gate is inhibited. If
the test .- not satisfied, VMA loads with PC+1 and program operation continues.

EBOX/3-12

EBOX/3-13

AC decoded jumps JRST and JFCL reference locations in the DRAM that correspond to their numerical op codes (254 and 255, respectively). The DRAM register is loaded specially for JRST. Note that
IR JRST (Figure 3-3) forces DRAM register J4 1o zero while enabling DRAM J07-10 10 be input frem
IR 09-12. This enables the microcode for JRST to be entered at the appropriate location relative to the
type of code in IR 09-12.

———iE

VMA

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Figure 3-8

IR Test Satisfied

EBOX/3-15

e
Figure 39

Figure 3-10

IR Test Equal

IR Test Satisfied Logic

Table
-1 Skip, Jump, Compare Controls

DRAM B Fiekd 1; Skip. Jump, Compare Controbs 1 Controls Sense of Skips. Jumps, and Compares
|

DRAM BOO

sic

SICLE

SICA

SIct

s
——

0
1

SIGE

RSN

1
o

NOTE
Sce Table 3-4. uses Skip or Jump fetch with varsous AD

EBOX/3-17

Table 3-2

Test Cnntrols

DRAM B Field

Test Controbs

4
0
0
s

17~

[ Controk Sense of Test

Actua! Instruction T Microi

CAMXNX.( AINX

COMP FETCH

INE
TMA

i
]

i}
0

SKIPX\

SKIPFETCH

171
124

i
;

I}
)

BLKO.BIKJ.

TEST FFICH

17N

;

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1
1

Table 3-4

DRAM BOO

1C-

1Ct

TCA

I(‘:l

(‘)

TOA

CONSO. CONS/Z.
TXXNXN
JUMPXX

MEM Field

Magic No. Field

FETCH

201

HTCH

Lorrien

203

FETCH

102

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1

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tion F

Using

Fetch Control Modifiers

Instruction That Uses

NOTE -

Table 3-§

CRYO0 Generators Used

AD Field Function

BLKI. BLKO

TEST BRL

TIST AR-BR

CRY A-B=0

JEST

TEST AR-ACO

CRY A-B=0

TEST

NO CRY

SETCA

CONSO, CONSZ

See Table 34 uses TEST fetch with various AD functions.

CRY® Generation (MACRO)

Additional Signal

ORCB+!

GENCRY 18

Table 3-

DRAMBField | CONSX.BLKX

CONSX and BLKX Coatrols
\

Sense

consx BLYK Ship
DR..AM 800

Figure 3-10 illustrates the actual logic that develops IR TEST SATISFIED. The uscof

;

o Shp
.

BLXI

aEa

BLKO

TEST FETCH

TEST BRL

the E,G, L and

X portions is indicated. The result of the test in the AD determines one of the conditions on each gate.

For Equal (E), the term is straightforward AD = 0. In the case of Greater (G), the Exclusive OR of the
h

sign of AD (AD00) with a carry out of the AD sign (AD CRY -02) produces the A >B output when
AD is performing the Exclusive OR function. For example, assume CAIG AC, 010101,
AR = 000000, 010101

;0.E

AC = 000000, 007777 {AC)

The function performed in AD is:

ADB+~FM; (AC)
ADA~AR: O, E

CONSO

TST FETCH

CONSZ

THST FETCH

Note that while the AD performs the logical function XOR, the carry function is A-B-1 (Table 2-8,

TEMT AR BR

ALU Functions). Therefore, the ADB input is 000000,007777 and the ADA input is 000000,010101.
The operation is as follows:

TEST AR BR

AD = XOR

15 complement of ADB input

ADCRY-02

EBOX/3-18

000000010101 <=t ADA Input

T~ 777777 770000
000000 000101 = Adding the 15 complement
of BloA=A-B-1

EBOX/3-19

owzo

-B-1 = B+l -1

(TN

wrwins

-B =B+l

Note that the following relation is true:

-B-1 = B, which is the 1s complement of B.
XORing AD CRY -02 with AD0O, which is 0, should indicate A >B.

The remaining term (X) is used during TEST, BLKI, BLKO, CONSO, and CONSZ instructions. The
AD carries function is AB-1. For example, assume the instruction is CONSO DEV. 1. At the time of
the test, BR contains 000000,000001, the effective address, and AR contains the bits (if any) from the
device. The implementation follows:
:O.F
:assume the bit was set in the device

]

|
|

BR = 000000,000001
AR = 000000, 000001

) SRy

ADOO.

500 B

The function performed in AD is ADA AR, AD = A and effectively the (AR) is compared 10 zero
because any negative value in AR satisfies the SKIP until a value
of zero is placed in AR. This turns off

AR = (E)

R 0 S

X: SKIPL 0, E

(E) = 777777, 777774 : 4

For less than (L), the term is ADO0O, and this indicates the AD result as a negative value. Skips utilize
the Boolean AD function A. Here, the carries function is really A-1. Thus, if the instruction is SKIP L
0. E. the contents of E arc compared with zero and a SKIP occurs if (E) is any negative value. The
implementation follows:

1L 1

000000,000001

000000 000001

1511

HANDTM

000000,000001

For the carnes tunction add - 1
ADCRY -02+

000000000000

Here ADCRY-02 inhibits the (X) function but DRAM BO is coded to enable the IR TEST SATISFIED condition. The PC is updated by +2 and loaded into VMA (Figure 3-9). If the instruction were

2 ano
omiv aoams

CONSZ DEV, 1 and the device
flag was not set, the AD function [000000,000000-1] yields
-1 and -AD

CRY-02. This satisfies the (X) function and DRAM BO is clear. Once again, the IR TEST SATISFIED condition is satisfied and the SKIP occurs.
32

sca e
-5 moame

PROCESSOR TIMING

The KL10 is a synchronous machine. Figure 3-10 illustrates the basic clock layout and distribution.
32,1

Clock Overview

The clock resides in the EBox and contains a selectable source (Figure 3-12). This source can be a
crystal controlled 50 MHz oscillator, for norinal processor operations, but may be an external source
for special applications or a 56 MHz crystal-controlled oscillator for speed margining.
Basicall. the clock consists of three other rather distinct

sections. the clock control, the EBox clock

control 4ad the clock diagaostc control ocled (D« (@ o (D« repactivey,in Figure 3-13
EBOX 320

Figare 3-11

Basic Clock Module Layout and Distribution

EBOX 321

awn e

or
souktt

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e ot

Figure 3-12

Clock Source Simplified

sous cuoc

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Figure 3-14

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wowerse

[
1

Figure 3-15

cnowesn

sTRoBC
0500-07

oyOy

[

0504-06

T gy O

o v raee

Basic Source Selection

Free-Running Clocks

The 50 MHz FREE clock source is next passed 10 a rate-selectable mixer. However, because the Rate
register may initially be in an undefined state,
the selected ratc is apt not to be the 50 M Hz source. This
presents no
because the inputs to the mixer (50 MHz FREE. 25 MHz FREE, 12.5 MHz

FREE, or 6.25 MHz FREE)
are all even multiples: the rate is not critical during the power up phase of
operation. The mier is shown in Figure 3-1€ Its output is labeled 2°Rate Selected: however, it is not

ure 3-13

322

Basic Clock Block Diagram

twice the input frequency. but twice the clock select frequency output.

Crobar and Clock Initialization

When the KL10 system is powered up, the EBox clock board must be initialized to a known state. In
addition, the device controllers on the EBus must be initialized and a series of MBox, EBox, SBus, and
EBus clocks must be

generated for varjous initializtion purposes. First, the power controller asserts

CROBAR for approximately 5 seconds. This signal is passed to the clock diagnostic control logic,
where it enables the initialization process. The clock di
ic logic contains a 2-bit source selection

register. a 2-bil rate selection register, and various other registers and logic. During power up, the state
of these registers is undefined. To avoid an improper source selection, the clock CROBAR signal is
used directly to select the S0-MHz oscillator as the clock source to be used during the power up

initialization phase (Figure 3-14).

NOETNED
|

The selected 50-MHz source is now divided down as indicated in Figure 3-15 to provide 25-MHz, 12.5MHz, and 6.25-MHz free-running clocks.

EBOX/3-22

Figure 3-16

Basic Rate Sclection

EBOX/3-23

323 EBus Reset
Referring to Figure 3-18, the CLK CROBAR signal enables the counter to subtract one on each 12.5

MHz clock pulse. Once again, the initial state of the counter is undefined. During
the crobar period

(approximately 5 seconds), the counter is decremented toward zero. When zero is reached, a carry is
generated and ifCROBARis false at this time, the -1 functionis disabled and the counter is loaded
with zeros. This removes EBUS RESET. In pracuce, the counter passes through zero many times until

finally CROBARis removed by the Power Eontrolier logic. Signal EBUS RESETis a 1280 ns square
wave.

3231 Initialization Clock Pulse Generation - As shown in Figure 3-18, CROBAR is shifted four
places into the shift register, activating the CLK SS stage. This, with the Clock Selected flip-flop.
enables the gated clock. It is this signal (GATED CLK) that becomes the source of the clocks generated via the clock control and EBox Clock Control. When CROBAR is removed, 4 CLK selected

pulses later. CLK SS is also removed. The approximate sequence is indicated in Figure 3-17. Figure 319 shows the power up timing. Note that this shift register also serves to synchronize CROBAR.

‘
:
g

324 EBox Clock Control
The EBox Clock Control provides a source of clocks for the EBox boards together with an MBOX
Sync Point (EBOX SYNC), which s always asserted one MBOX Clock prior to the generation of the
EBox clock (Figure 3-20).
Depending upon the nature of the EBox cycle (a period extending from the rising

edge of one EBox

clock to the rising edge of the next), the period between EBOX CLOCK pulses may be extended by
some multiple of 40 ns, i.c., 80, 120, 160, 200, etc.

Refer to Figure 3-22, this drawing illustrates the functional structure of the EBOX CLOCK Control. It
consists of an MBOX CLOCK counter/marker generator, a clock phase sync detector, an EBox sync
source, and an EBox clock source, The CRAM time field (T00, TO1) specifies the duration of the EBox
cycle (Figure 3-21).

:
:

The marker generator consists of a shift register that may be loaded with zeros when EBOX CLK EN
is true or have ones shifted in (beginning with the 40-ns stage) for each MBOX CLK generated, as long

DiaGetane

as EBOX CLK is false. Table 3-6 describes the marker generator.

@ rzswmi rote
Ocnowsan

@ cx

=2stconos]

Figure 3-17

Figure 3-18

EBus Reset and Clock Initialization

Clock Initialization

EBOX/3.24

EBOX/3-25

TIMe 36

Duration

MBOX

sowsrme_NAMANAAARAAALIALIN

e ome T MLALTLMLTLALAL UL
12

con oy meser

\llri« (knnl.t !-flloi

;

EBOX

SYNC

=l
o

]

0
o

120

T
TM

]

s
1

The clock phase sync detector compares the marker generator content with the CRAM time field

(loaded at EBOX CLOCK TIME) whenever EBOX CLOCK EN is false. If the marker count compares with the bit combination in the time field, SYNC EN is asserted and the next MBox clock sets
EBOX SYNC. EBOX SYNC then enables EBOX CLOCK EN and similarly disables the detector.
This completes one cycle.

Note that with MBOX WAIT true, -EBOX CLK EN is also true and EBOX CLK EN is false (Figure
3.22). This enables the MBox clock counter/marker generator to keep shifting 1s from the 40-ns stage
toward the 120-ns stage. Similarly, the detector
1s enabled and when the marker compares with the bit
combination in the time field of the CRAM word, SYNC EN will be asserted and remain so until the
MBox responds or aborts the cycle. Thus, one MBOX CLK after SYNC ENis asserted, EBOX SYNC
will set. In other words, EBOX SYNCis asserted one MBOX CLOCK prior
to where EBOX CLOCK
would have been asserted.

Figure 3-20

Simplified Diagram, MBox Clock, Sync, EBox Clock

With SYNC EN true when MBox response is received (Figure 3-22) EBOX CLOCK EN becomes true
allowing the marker to reset to 000, and SYNC EN is removed allowing EBOX SYNC to clear on the
next MBOX CLOCK. At the same time, EBOX CLK EN becomes true and EBOX SOURCE EN is
also true; thus, when EBOX SYNC is cleared, EBOX CLOCK sets (Figure 3-23).
325

Error Detection

Figure 3-24 illustrates the logic that stops all clocks in the event of any of the following:

Figure 3-21

EBox Cycle

A DRAM parity error occurs.

A CRAM parity error occurs.

EBOX/3-26

A fast memory parity error oecurs.

EBOX/3-27

w01

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wnor
cowmor

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Figure 3-22 EBox Clock Control Block Diagram

wav ras e _fl—1
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hifcar=——t= S
N

Figure 323

Figure 3-24 Clock Error Stop
.

Basic MBox Cycle Timing

The timing shown is for a CRAM parity error. The CRAM register is clocked by CLK CRM; sometime later, the parity network settles and asserts <CRAM PAR 16. This indicates that the CRAM word

has dropped or picked up bits and is not correct. The signal -CRAM PAR 16, together with an enable
previously set by a diagnostic cycle (CLK CRAM PAR CHECK), enables the generation of CLK
ERROR HOLD.

1f it is desired to stop on parity errors, CLK ERROR STOP EN must have been set by the console. In
this case, on the next occurrence of CLK EBOX SOURCE EN, the CLK ODD gate will be latched
false, inhibiting all clocks and freezing the system.

EBOX/3-28

EBOX/3-29

326

Clock Control Logical and Skew Delays

Figure 3-25, illustrates the delays necessary 1o assure that the proper timing relationship exists between
the actual MBOX CLOCKS, EBOX CLOCKS, and the sampling of the CRAM time field. The lumped delay of =128 ns consists of fixed logic delays, gate and wire delays. The output is CLOCK ODD
and is used to clock a 10141 Shift register, which has & propagation delay of 2,65 ns.
NOTE
The times given here are approximate times only.

cimcut o

wwureo oy

Figur 3-25

Logical Delays and Skew

The output of the Shift register feeds various gates and the various EBox boards receive their clocks

o
-

from these gates. Delay X allows for lining up the outputs of the gates, “deskewing"” the EBox clocks.

The delays are actually etch
paths near the fingers on the board and once the delay has been ascertained, a permanent connection is made at the proper point. Figure 3-26 shows the EBox clock fanout:
Figure 3-27 shows the MBox clock fanout.

To cancel the effect of the 10141 circuit propagation delay, a fixed 2.65 ns have been inserted in the
path between the lumped DLY and the MBOX CLOCKS. Connected in this path also is DLY Y.

which performs the same function as DLY X does for the EBOX CLOCKS.

cox o

— V,Eg g
—

Figure 3-27

EBOX/3-30

MBox Clock Fanout

EBOX/3-31

cumoam

All the EBOX CLOCKS and the MBOX CLOCKS are lined up leaving the clock board. In order to
synchronize the CLK BOARD with the other boards, CLK CLK is passed out through the eich
connection on the board. It then reenters the board at DLY 2 where it is deskewed via a coaxial cable.
as are all the other CLK signals.

Figure 3-28 illustrates the basic timing for the clock board. Six basic cycles are presented: clock startup, EBox cycle T = 01,, EBox cycle T = 10,, EBox cycle including a memory cycle T = 00;, EBox
cycle T = 00; and finally EBox cycle including a memory cycle and a page fault.
3.3

ARITHMETIC PROCESSOR FACILITY

3.3.1

introduction

This facility controls and contains logic relating to the following hardware in the EBox.
Address Break Facility
Arithmetic Processor Status
Processor Identification
Cache Refill RAM Facility
MBox Error Address Register

Fast Memory Addressing and Control

These arcas arc set up via four KL10 instructions as follows:

DATAO APR - Sets up address break facility.

CONO APR - Sets selected flags in the APR STATUS REG. and/or enables interrupts to occur
on selected APR priority interrupt channel.

APRID - Reads the following information from the EBox:
Microcode options
Microcode version number
Hardware options
Processor serial number

RDERA - Reads the ERA register located in the MBox
33.2

Address Break

One possible use of this hardware in the EBox is associated with the SET BREAK command. which
may be issued to the monitor by a user (c.g., during the debugging process). This is primarily useful
when the piogram that is being debugged:

Will not fail when DDT has been loaded

Destroys DDT when DDT is loaded

Destroys the contents of a memory location at an unpredictable point during program

execution.

1t is possible to break when the specified location is read from, written into, and/or fetched. It is also
possible to break on monitor references to items in the user's address space.

Figure 3-29 contains the address break logic. A break may occur at three places in an instruction:
On Instruction FETCH

On DATA FETCH
On DATA WRITE

EBOX/3-32

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Address Break Facility

EBOX/3-35

In addition, the reference may be further qualified to a user or executive reference. The address break
conditions are loaded into the EBox hardware by performing a DATAO APR instruction. The left haif
of (E) specifies the following:
Bit 09: Address Break on FETCH
Bit 10: Address Break on DATA READ
Bit 11: Address Break on DATA WRITE
Bit 12: Address Break on USER REF

The right half of (E) specifies the break address in bits 13-35, where 13-17 represents the virtusi
section number and 18-35 the virtual page number, line number.
The Address Break Inhibit logic, illustrated in Figure 3-29, may be set up to inhibit an address break
by performing any of the following instructions:
JRSTF - JRST2
JEN - JRST 12
JRST 10
MUUO

he PC word provided by these instructions must have bit 8 = I 10 set SCO ADR BRK INH. Ifa
STF is given setting SCD ADR BRK INH, the NICOND Dispatch occurring during the JRSTF
transfers the set state of SCD ADR BRK INH into SCD ADR BRK CYC, while clearing ACD ADR
BRK INH. Thercfore, for the duration of the next instruction, address breaks cannot occur. This is
useful, for example, when continuing from an address which subsequently caused an address break.
Consider the following example:

677

SETO 3,

ADDM 3,300

{ADD TO TABLE

701/
702/

AOS 700
HRRZ 4,700

;ADD 1 TOTABLE ADR
;PUT CURRENT TABLE

700/
703/
704/

CAIE 4,1000
JRST 700

JPUT-1INAC3

{ADRINAC4
‘WHENITIS 1000 ALL DONE

NOTE
This sample program illestrates the wse of ADR
BRK INH aad is not meast to be a well-structured

program.

The sample program adds -} to a table beginning at location 300y and ending st location 1000,. A bug
exists, however, in this program. Note that the AOS instruction in location 701 is incrementing the
table address in the right half of location 700. The problem occurs when the right half of the instruction in 700 becomes 700. At this time, the instruction becomes ADDM 3,700 and this wipes out the
instruction in location 700. Several references to location 700 are in the program. First the monitor is
requested from a terminal to set ADR break on data write for address 700 to assure that the AOS
instruction is working correctly, i.c., attempting & write into 700. The monitor performs a DATAO
APR, which scts USER COMP, WRITE COMP, and loads the address break register with 700. At this
time, ADR BRK INH is cicar and when the EBox performs the write request, the comparator will

satisfy the OR gatc labeled (1)
1.
2.
3.

because the following conditions are true:

VMA 13-35 = ADR BRK register 13-35
MCL VMA WRITE = WRITE COMP
MCL YMA USER = USER COMP

EBOX/3-37

At this time, both SCD ADR BRK INH and SCD ADR BRK CYC are clear; therefore, the signals
MCL PAGE ADR COND and MCL PAGE ILL ENTRY are asserted together with all other necessary request qualifiers. The MBox detects this condition and places a page fail word in its EBus register
(indicating an address break page failure) and asserts PF HOLD 1o the EBox. The EBox senses this,
and enters the microcode page fault handler. Now the EBox flags must be gathered for storage in user
process table location 501. Because SCD ADR BRK INH is one of the processor flags, it must be
made available; however, at this time it is clear. Regardless of this, the process of obtaining this flag
will be discussed. Upon entry to the microcode, CON INSTR ABORT is genzrated to cause proper
termination of the faulting instruction. Referring to Figure 3-29, CON INSTR ABORT enables SCD
TRAP CIR. which breaks the recirculation paths for both SCD ADR BRK INH and SCD ADR BRK
CYCLE: it also transfers the state of SCD ADR BRK CYC into SCD) ADR BRK INH. This makes
the flag available for storage in 501. The page fault handler reads the MBox EBus register and stores a
page fail word in user process table location 500, stores the flags PC word (PC is now 701) in 501 and
then fetches a new PC word from uaser process table location 502. The processor now enters Execute
mode and handles the page failure appropriately.
Eventually, after evaluating the page fault word in 500 and other data, the monitor informs the user at
his terminal that a write was attempted to location 700. If after giving the problem some thought, the
user requests a break on the same address for write but now suspects that somehow the instruction in
700 is being overwritten by itself, the break can be inhibited. Now the monitor wishes to continue the
program by performing the entire AOS instruction to ascertain that it works but also must avoid
thewrite page fault associated with this instruction.
The monitor can perform a JRSTF instruction that sets ADR BRK INH and restores the old PC of
701 for the AOS instruction via user process table Jocation 501. Referring to Figure 3-29, during the
execution portion of JRSTF, SCD LOAD flag sets SCD ADR BRK INH. During the JRSTF instruc-

tion NICOND Dispatch occurs and transfers the set state of SCD ADR BRK INH into the BRK
CYCLE flip-flop while clearing SCD ADR BRK INH. The AOS instruction is successfully fetched
from 701 and the *AOS write referenceTM 10 700 is prevented from causing MCL PAGE ADR COND

because this is blocked by SCD ADR BREAK COND (L). The next NICOND Dispatch clears SCD
ADR BRK CYCLE, enabling the ADR BREAK to occur if a write is performed to 700. Eventually,
through many tries, the overwrite of the instruction in 700 wil! be detected by this method. Note this is
only a simple example and is not necessarily a practical one.

33.2.0 Address Break INH and Saving Flags - The signal CON COND INSTR ABORT
is generated
by the microcode whenever external conditions require the microcode to abort a partially completed
instruction. If this occurs during an address break cycle, this signal copies the state of SCD ADR BRK
CYC back into SCD ADR BRK INH, thus making it available to save as a bit in the flag's PC word.
3.3.2.2 Address Break INH and Loading Flags - SCD LOAD FLAGS can be generated in a number
of ways: JRSTF, JRSTI0, JEN, JRST, and MUUO can set SCD ADR BRK INH. The 10-11 interface
can place the flags PC word in AR and perform a console start. This causes the microcode (o generate
SCD LOAD FLAGS. During a JFCL instruction, the flags are read and the specified flags cleared.
Then the microcode reloads the flags using the signal SCD LOAD FLAGS.

The arithmetic processor status register consists of two 8-bit registers and associated control logic. One
register receives the error or status signals and the other register enables or inhibits the generation of
an interrupt when one or more of these error or status flags scts.
Figure 3-30 provides the basic format for the CONO APR word, the basic organization of the error or
status flag and the interrupt enable or inhibit for the two registers. In addition, the bit assignments are
provided in two tables, as well as the source of the error or status signals available to set the appropriate flags in the APR register.

The basic organization of the APR s illustrated in Figure 3-31. The register is broken down into four
sections based on the origin of the error. The first five flags set as & result of an error condition
involving some memory activity. Three of the flags: {SBus Error, Nonexistent Memory (NXM) Error,
and S ADR Parity Error] originate in the memory adapter (DM A). The remaining two originate in the
MBox. The flag IN-OUT PAGE FAIL (IOPF) sets because of an external stimulus, but the actual
setting takes place by the microprogram, in response to a page failure that occurred during a priority
interrupt. The power failure flag sets when the power controller detects a low voltage condition. The
sweep done flag signais the completion of & cache sweep operation. This operation is the result of
performing a sweep instruction.
Once again referring to Figure 3-30, to enable interrupts for any or all of the cight onnditions, a CONO
APR is performed with bit 20 equal to | and ones in bits 24 through 3t for the desired flags. Similarly,
to disable interrupts for any of the eight flags, which have previously been enabled, place bit 21 equal
to | and ones in bits 24 through 31 for the flags to be disabled. This means that once the processor has
been powered up, and providing a power failure condition has not occurred, that once an interrupt
enable has been set. it must be specifically cleared as indicated above,
Any of the cight flags can be sclectively set or cleared by placing bit 23 or 22 on, respectively, together
with those bits in 24-31 to be changed.

33.3.1 SBus Errors - Two error lines are available from the DMA to the MBox. These are SBUS
ADR PAR ERR and SBUS ERR. If the DMA starts a memory cycle and also detects bad address

parity, it sends SBus Acknowledge (SBUS ACKN) to the MBox, acknowledging receipt of the address
and within 125 ns transmits SBUS ADDRESS PAR ERR. The MBox now latches the error address
register (ERA), which contains the address in question and additional bits which specify information
associated with “data parity error conditions.” These two bits specify which of the four memory
buffers (M Bs) the parity error is associated with. The address used to address memory specifies which
word is to be transmitted (for a write) or received (for a read) first. This information is contained in
bits 34 and 35 of the address. If, for example, the address in the ERA is 101 [bit 34(0) and bit 35(1)) and
the address in the PMA used to address memory is 100, the indication is that the word requested by the
EBox. for exampl. was not the word actually causing the data parity error. Thus, in this example, the
EBox requested the contents of location 100, received it, and how, while fetching a word from 101 (of 3
quadword group), an error occurred associated with that word.

33.3 Arithmetic Processor Status Register
This facility enables special internal conditions to signal the monitor on a priority interrupt channel
assigned to the processor. Condition 1/0O instructions are used to control the appropriate flags and to
inspect the conditions of interest.

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Figure 3:30

APR Register and Interrupt Enables

EBOX/3-41

Figure 3-31

APR Register Breakdown

In addition, a 3-bit code ndenufm the origin of the data in the memory buffer register and indicates the
type of reference, i.c.

id, write. etc. As the MBox latches the ERA, it transmits MBOX RESPONSE

IN and MBOX S ADR PARITY ERROR to the EBox. MBOX S ADR PARITY ERROR occurs
concurrently, with an MBox clock and, therefore, on the next MBox clock (that will be also an EBox
clock) APR S ADR PARITY ERROR sets. Providing the SBUS ADR PARITY ERROR INTERRUPT enable is set, an interrurt will be requested on the APR channel. In addition, to prevent the
MBox error condition from being changed, the APR error flag which sets
is sent over the E/M interface 10 recirculate the MBOX SBUS ADR PARITY ERR COND; also, APR ANY EBOX ERR sets
and is passed to the MBox to hold the ERA. As a result of the interrupt, the monitor determines that
the APR was the source of the interrupt via a condition 1/0 instruction (CONSO, CONSZ, CONI,
APR), make a determination, and finally clear the error flag, releasing the MBox ERA and associated
error logic.

3332 Nosexistent Memory - Each time
the EBox makes a memory reference, the MBox interprets
the request qualifiers and performs all the steps necessary 1o satisfy the request. A core memory
reference must be issued by the MBox in order for NXM to occur. When the MBox issues 2 memory
request 10 read or write
a word to core memory via the memory adapter (DMAD), it starts
timeout (32
4s) and waits for SBUS ACKN from the DMA indicating acceptance ofthe request and address. If 32
s elapse and SBUS ACKN is not forthcoming, the MBox sets MEM ERR (Figure 3-32).. An additiona1 32 s elapses and if SBUS ACKN has not been received by the MBox, MBox NXM error is asserted
together with MBOX RESP IN.
Referring to Figure 3-33, MBOX NXM ERROR is loaded into the APR register with APR CLK. I
the NXM ERR interrupt enable is set, APR INTERRUPT is asserted to the PI Board. To preserve the

ERA and NXM ERROR in the MBox, the APR NXM flag is recirculated back to the MBox. In
addition, PAR ANY EBOX ERR sets, holding the ERA information in the ERA register.
3333 Other External Errors
- Referring to Figure 3-34, all five external error conditions set the
appropriate APR ERROR flag and request interrupts (if enabled)
on the error channel assigned. Also,
all the indicated error flags recirculate to the MBox and all causc APR ANY EBOX ERROR 1o set,

preserving the contents of ERA. Of the five errors, one, MB PAR ERROR, is handled as if it were8
page fault. That is, it causes control to be passed to the microcode page fault handler, where it is
evaluated. The status word is obtained from the ERA in the MBox. The format for this word is
initially as indicated in Figure 3-35.
The page fault microcode places a code
in bits 0-5 of 26y and places
the virtual address for the refer-

ence in bits 13-35 where bits 13-17
are 0 for KI paging mode; this word is stored in user process table
locaion
500, The remainder of the opeation s identicalwit that for s pag uilure and s coverd n
ion

EBOX/3-43

333.4 Input/Output Page Failure Error - During a priority interrupt [PI CYCLE (1)]. page failures
are not expected 10 occur for interrupt instruction fetches or PI dispatches. This is regarded s a fatal
error, and it causes an interrupt on the assigned APR error channel. The page fault handler sets IOPF
inthe APR register and then dismisses the interrupt. The PC is placed in VMA and an instruction fetch

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NXM Timing Overview

EBOX/3-44

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3335 Power Fail - The power controller asserts the signal POWER WARN whenever the power
Supplies reach a marginal value. This results in the setting of theAPR POWER FAIL flag and requests

begins while waiting for the Pl system to honor the interrupt for the APR.

Figure 3-33

NXM Error Overview

3336

SWEEP and SWEEP DONE - The MBox contains
a section of logic called the Cache Clearer

(CCA). This is addressed as if it were a device (014), using 1/0 instructions. Six operations may be
initiated. These are listed in

Table 3-7.

Table 3-7
—

New Moemonic 1
SWRIA
SWPVA

SWPLA
SWFIO
SWPVO

|
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Okt Mocmonic

——

DATAICCA
BLKO (CA

CCA Summary

Function

SRR

Invahidate all cache data, do not update core
Sweep cache. validate core, leave cache valid

pataocea
conicea
CONSZCCA

‘
|

Unload all pages updating core. vahidate the cache.
Invalidate une page of the cache.
do not validate core.
Sweep cache.
validate one page of core. leave cache valid

CONSOCCA

Cnload unc pase. update core. ivabdate the cache

To request CCA cycles * m the MBox as a function of one of the six instructions in Tabie 3.7, the
EBox places the virtual page number into VMA 27-35, verifies that the performance of the Sweep
instruction (which is privileged) is legal in the current mode
of the processor
and then cither begins the
operation or, if illegal, performs an MUUO.
Figure 3-36 illustrates the various logic associated with the sweep operation. Three basic operations
v e
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Figure 3-34

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InTEmeLET

can be specified in various combinations by the six types of Sweep instructions. These are illustrated in
Figure 3-36 in the table at the upper left
In the cache, associated with each word of a four word block (quadword),
are two bits labeled valid
and written. If the valid bit is off for any of the four words, these words are considered to contain
incorrect
data and, if referenced (for example by the EBox), the words must be fetched from main
‘memory. Similarly. if the written bit is on for any of the valid words, these words contain different data
than the copy in main memory and the cache copy is correct. At some point, the written words must be
fNushed from the cache into core memory. On power up, the cache must be invalidated, clearing all the

Pa CRK INT 8

External Error Conditions (MBox, SBus)

entries. For this case, the DATAI instruction
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sets up the request utilizing the MEM field function MEM/REG FUNC together with the magic
number field coded as LOAD CCA (6014). To follow
the memory request, it is best to refer to Figure 2-

98 which can be fourd in Subsection 2.7.2.5. Note that onFigure .36 MEM /REG F UNC (07) has bi

01 equal to 1 and this generates MCL REQ EN. This signal is used to enable the various registers
involved in the EBox request to load with the appropriate information prior
to latching the VMA. The

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Signal Generated

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EBOX/3-46

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Sweep Logic (Sheet 1 of
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EBOX/3-49

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Sweep Logic (Sheet 2 of 2)

EBOX/3-51

The basic timing for the CCA request as well as CCA termination is illustrated in Figure 3-36. The

VMA must contain the virtual page number in VMA 27-35 for CONI, CONSZ, or CONSO CCA
operations. In the current example (DATAI CCA), the MBox cache clearer does not use this informa-

tion because the entire cache is to be invalidated. However, the cache clearer has an associated register

that is loaded by the MBox with VMA 27-35. IRAC bits 10-12 are similarly loaded into the MBox
control logic that directs the type of operation carried out. Each time a CCA cycle is completed in the
MBox. an idle period occurs where the channels or EBox can obtain an MBox cycle. The EBox can
continue to execute instructions but must guard against defeating the purpose of the Sweep operation,

ic.. wrile new data into already swept words in the cache. Summarizing, three of the six instructions
operate on one page of the cache (S12 words). For these three instructions a different set of sweep
functions is

available: these are: invalidate, writeback all written words in the specified page, or per-

form both. Similarly, three instructions operate on the entire cache (2048 ,o words) but the operations.
are the same as with the other three. In all cases, the EBox performs an EBox Request providing
the
appropriate qualifiers and the VMA contains (in bits 27-35) the page number. The MBox loads its
(CCA register and then asserts MBox CCA Request together with MBOX RESPONSE IN. Now the

EBox is free to perform operations while waiting for SWEEP DONE to generate an APR interrupt. If

a second sweep instruction is started by the EBox before the first is completed, the MBox begins the
second sweep just as it would another instruction; however, it reloads the CCA register with the new
information supplied by the second sweep instruction and does not complete the first.
334 Processor Identification
The processor identification consists of four parts:
Microcode options
Microcode version number
Hardware options

Processor serial number

This information is obtained by performing what was traditionally a BLKI APR, now called APRID.
The format is illustrated in Figure 3-37.

icRO CODE

MICRO CODE

PTIONS.

PROCESSOR

Figure 3-37

SEHAL

VERSION WUMBCH

NowBLE

APRID Format

This is not strictly a visible hardware function, but rather a combination of microcode and hardware.
The microcode
for a given version
is coded in such
a fashion that the version number is obtained
utilizing the magic number ficld and the function AR00-08— number. The microcode obtains the
processor serial number that is hardwired to the0 input of the ADXB mixer and places it in AR. Next,
the microcode version number is obtained and adjusted as follows. The serial number in AR is copied

10 BR and the version number is loaded into AR00-08; next, the ARX. At this time the BR, AR, and
ARX are as indicated in Figure 3-38.

EBOX/3-53

e e

Figure 3-38

Alignment Step |

The shift counter is loaded with 9,0 and now the combined AR and ARX are shifted left 9 places with
the result placed in AR as indicated in Figure 3-39.

The version number is placed in AR 9-17, the serial number in AR 24-35, and the resulting word it

Figure 3-40

stored in location E.

27 20

Refill RAM Overview

When the instruction is legal, the microcode performs a MEM/REG FUNC with the magic number

field coded as WR REFILL RAM. The APR logic decodes the REG FUN during the EBox Request:

vr -

st -

APR EBOX READ REG

APR EN REFILL RAM WR

Figure 3-39

335

Alignment Step 2

Cache Refill RAM Facility

The cache refill RAM in the MBox must be loaded with a set of bit patterns called the refill algorithm.

by the MBox with a use table and other associated logic to manage the cache refill
This RAM is used
operation. Generally speaking, when the cache fills up with words, it becomes necessary Lo displace old
words for new ones. It is desirable to displace the words used most infrequently. To do this, an

algorithm was develop=d that specifies which word is to be displaced each time a refll cycle must write

into the cache. Figure 340 illustrates the basic structure of the MBox Refill RAM and also indicates
the format of the effective address provided by the BLKO APR instruction (new mnemonic WRFIL).

The microcode executor is entered with the effective address (E) in AR. Because the instruction is
privileged. legality is checked first. If the instruction is legal for the current mode of the processor

(Kernel or User with 10T set), the instruction is performed; otherwise, an MUUO is effectively per-

formed with the illegal instruction stored in the user process table location 424 in the place where the
MUUO is normally stored.

The MBox writes the three high-order bits (18-20 of VMA) into the refill RAM at the location’

addressed by bits 27-33 of VMA. Writing the entire algorithm requires a loop using the basic instruction BLKO APR as a focal point. The following is an example:

RAMI

SETZBZ.AC

:CLEAR REGISTERS

MOVE AC, TABLE(Z)
BLKO APR.(AC)
CAINZ 127

A WORD
ICK UP
WRITE THE FILL RAM
;DONEALL 12810 WORDS?

AOSZ
JRSTRAMI

Z FOR NEXT
;NO, UPDATE
;PICK UP NEXT WORD FROM

ISR DONE

JYES

THE TABLE

In the sample program, table through table+127 contain the appropriate entries 10 be written into the
MBox Refill RAM. These words are in the format indicated on Figure 3-40. The refill algorithm
may
be adjusted by changing the sequence of the bit patterns. By doing this, portions of the cache may be
bypassed as appropriate. Normally, all four cache quarters would be used equally. Table 3-8 is reproduced as extracted from the MBox theory section simply as an example.

EBOX/3-54

EBOX/3-58

3
339

10 47
P

6 63

64 71
72-79

80 X7

8 95
9% 103
104 111

1219
120 127

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CONTROL RAM ADDRESSING

Figure 3-41 contains an overview of the CR addressing logic, while Figure 3-47 contains a more

detailed version. The CR addressing logic consists of the following general parts:

Refill RAM Contents

Refill RAM Locations

07
518
16 23

Sample Algorithm

Table 38

&
2
R

5
9

&
%

&
85
M2

5
4
00
4

45
1
0
S
0

17
&
x93

&
0
6

7
Y

7
7

s
17
0

&
6

Pushdown Stack, 4 words X 11 bits
Current Location register (CRA LOC)

CRAM dispatch field for holding the dispatch bits
Miscellancous CR address gates
Diagnostic register

Dispatch decoding register 0-3 EN, 0-7 EN, 30-37 EN

CRAM loading logic
CRAM address output gates.

The type of function being performed on the CRA board determines the portions of the above-mentioned logic that are used. These functions are broadly classified as:

3
1
0

Diagnostic register

Control RAM dispatch field

Write logic

The MBox contains a number of registers that can be loaded and read by the EBox. These registers arc
an error and for modifying the physical memory
address registers for storing the address in the event of

c.
d.

ally the Stack

Optionally the A READ Logic
Dispatch decoding register

address in response to certain request qualifiers. The registers are:
a.
b.

Decoding the Jump, Dispatch, and Cond (Skip) fields ofa microinstruction
Mixers

MBox Error Address Register

336

Loading into the CRAM dispatch

User Base Register - UBR
Executive Basc Register - EBR

Forcing a special CR address during a page fault
CR address output gates.

Cache Clearer Address - CCA
Error Address - ERA

The ERA register can only be read by the EBox. In sddition, the EBox can also read the contents of
the page table to transform (map) the virtual address to the physical address and load the cache refill
RAM with the cache refill algorithm.

A status word is formed and stored by the MBox in the event that an error is discovered. The error
address is basically a status word that is formed and stored by the MBox when an error is sensed. In
error flags are sct and the error
the case ofa parity, time-out, or an NXM error, the corresponding
address and associated status bits are loaded into the ERA register. The format of this word was
shown in Figure 3-35. This register is read by the EBox when an RDERA (BLKI, PI) instruction is
executed.

In addition 10 these three classes, diagnostic logic is present on the CRA board for reading various

registers, mixers, and signals onto the EBus. This logic is described in a separate section on EBox
diagnostic logic.

Pushdown Stack

341

The pushdown stack, consists of eleven clocked shift registers configured as an 11-bit SILO. Two

control signals, CTL SPEC/CALL and CTL DISP/RET, control the stack. Figure 3-42 illustrates the
basic operation for a sequence of two subroutine calls followed by two subroutine returns. The

example presented on the figure is not a practical example of subroutine calling and return, but &

to the call and return control signals. In practice, each
of how the stack behaves in response
example
subroutine consists of a number of microinstructions. For convenience, these additional instructions

have been omitted. In the example the first microinstruction (J = A) asserts the first call. Note that

during the first microinstruction, the CR address is “A", which is the address of the next microinstruction. When CRA CLK occurs, three significant events occur.

The CR address “A" is clocked into the current address buffer (CRC LOC).

The second microinstruction at location A" is clocked into the CRAM register.

EBOX/3-56

The decoding of this microinstruction begins and, in particular, enables the stack to push

CRA LOC on the next CRA CLOCK.

EBOX/3-57

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CR Addressing Overview

EBOX/3-59

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Figure 3-42

Stack Operation Example

EBOX/3-61

Now the CR address becomes “B" as specified by the second microinstruction. Normally, this is the

address of the first microinstruction in the subroutine. In the example, it contains a second call (J = B).

occurs; CRA LOC “B" is pushed onto the stack (Q0) while the previous contents of QO, which is A,

waw

address is coded 50 as to modify the address that will be popped off the stack on the next CRA

‘are pushed one level deeper into QI as indicated on the figure. Also, on this clock, the address “C" is
clocked into CRA LOC. This time the microinstruction specifies the return function and the Jump
CLOCK. For example, if the return is to be to the microinstruction following the one that made the

deod

call and the top address on the stack is “B" then the least significant bit of the “modifier,” which is

simply the Jump field of a returning microinstruction, s 1. Thus, the CR address is the logical OR of
the address popped off the stack, **B,” with the modifier 1, producing the return address B+1. Contin-

uing the example, CRA CLK pops “B" from the stack, clocks the previous CR address (modifier 1)

CRA LOC, and returns to the microinstruction at B+1, which is a second return. Once again, the
into

return is decoded and will enabi the address “ATM now at the top of the stack to be popped off and

(once again +1) producing a CR address of A+1. This completes the
logically ORed with the modifier

example.

vivivivivly)

indicated above, with the difference being that
The next CRA CLOCK again enables the three events
the CR address is now “B." CRA LOC contains “A." At the next CRA CLOCK, a second push

s s0s —

Nore

In this example, A and B are assumed to be even
numbers.

3.42

Current Location Register (CRA LOC)

This register consists of 11 clocked D-type flip-flops. Its two main functions
1.

._‘D_ cuaoe o7

To provide the current address for the pushdown stack

To provide the current address for diagnostic purposes.

i
+

343 Control RAM Dispatch Field
The majority of the control storage for the microprogram is on the CRM board. However, the dis-

patch ficld, 1280 words of § bits, s contained on the CRA board. The Diagnostic register on the CRA
as well.
board is used to address the entire CRAM, and this includes the portion on the CRAM board
Diagnostic functions are used to enable loading data placed on the EBus into the appropriate portion
0-6
c as input to theCRADR
register is selected
ofthe CRAM. Refer to Figure 3-41. The Disgnosti

and 7-10 mixers following power-up. This is true because the entire CRAM register is reset to zero

051,
ic
functions 052 and
field of zero. Using diagnost
during MR RESET, and this provides a dispatch
the Diagnostic register may be loaded from the EBus. This address now selects

word in the CRAM

for loading or reading.

3.44

w407

Miscellancous CR Address Gates

Refer to Figure 3-43. Functionally, there are four sections of gating:

CR Address 00-06

CR Address 07-10
CR Address 08-10
CR Address 10

/::> i

:>‘"-

This grouping corresponds to the way in which portions of the CR address lines may be controlied.

Figure 3-43 CRADR Gates

EBOX/3-62

EBOX/3-63

The CRAM, of course, sees only an address 0-10.

The fact that the CR address gates are OR gates should be kept in mind when trying to determine an

CR output address from a particular input condition or set of conditions. To enable a particular

address line only requires one ofts input lines to be true. For example, consider the example presented
in Figure 3-44, which shows the mixers that are used 10 select conditions to modify CR address bits

3.45

1.
2.

08-10. In the example, the dispatch function is effective address modification (EA MOD), which ..

encoded in the dispatch field as 36;. Note that in the example theJ field (CRAM J 08-10) is 4 in bits
08-10. The four possible combinations of ARX 13 and SH indexed allow any of the following:
No modification to CR ADR 09 and 10
Modification to only CRADR 10

Modification to only CRADR 09
Modification to both CRADR 09 and 10.

Because CRAM J 08 is a 1, the respective output gate, CRADR 08, will be & 1 even though the open

pin on that mixer (input 6) is effectively

Special CR Address Modification Considerations

Three special CR address modification considerations are:

CLK FORCE 1777
CRA MUL DONE

CON COND ADR 10.

3451 CLK FORCE 1777 - This signal originates on the clock board and is used to force the output
gates CR address 01-10 to the address 1777,. This event occurs during a page fault. The page failure
microcode handler begins at CRAM location 1777. Thus, the EBox, as controlled by the clock, enters
a prearranged page fail sequence. Loading the first microinstruction from the page fault handler, CLK.

FORCE 1777 forces
the CRAM address
lines, as indicated, and then issues a single CRM CLK, which

loads the microinstruction into theCRAM register. At this point, EBox's normal
ion continues.
Note that CLK FORCE 1777 does not affect CR ADR 00, and thus may force the microcode to either
1777 or 3777. The first step of the page fault handler is duplicated in these two locations.

Note, also, that at the same time as the CLK board is forcing CLK FORCE 1777, the CTL board is

forcing CTL SPEC CALL in order to place the return address on the pushdown stack.

3.4.52 CON COND ADR 10 - This external signal is formed on the CON board and routed to CRA
2 as CON COND ADR 10. Refer to Figure 3-45, which shows the boards involved in decoding the
and Dispatch ficlds. Note that each board contains tables indicating those functions that are
Cond

decoded on that board. The signal CON COND ADR 10 is formed when Skip 60-67 or Skip 70-77 are
decoded. The various hardware conditions involved are indicated on the tables.

3.453

the Dispatch function, MUL, the state of the sign of FE, as well as
MUL DONE - During

MQ34 and MQ3S, are used to modify the CRAM address in the multiply loop. When the sign of FE
becomes false an exit is made from the multiply loop. This is done via CR ADR 08. Simultancously,
MUL DONE (Figure 346) is generated to force address bits 09 and 10. This is done merely to save
microcode words Without this logic, MUL DISP would be
.vey branch: with this logic, it is 8 5-

S DD

way branch.

346

AREAD Logic

Refer 10 Figure 3-47. The AREAD logic is shown on the lower right-hand side. It consists ofa mixer

0isp

and various gating elements. Basically, this logic is controlled
by bits of theDRAM A field. Specifical-

02-08

ly, when the DRAM A field bits 00 and 01 are Os; then the AREAD logic AREAD 01-04 and AREAD
0 become equivalent (bit for bit) to DRAM J01-04 and DRAM J07-10. When DRAM A00
or 01
is a 1, then AREAD 01-04 and 07-10 generate 40, +A, dispaiching
to location 42 through 47 in the
microcode.

The outputs of the AREAD logic (to be able to modify the CR address lines) must be sclected in the

appropriate mixers. Once again referring to Figure 3-47, the mixers involved
are those
00-06 and 07-10. These mixers will select the AREAD function when the dispatch

Figure 3-44

Example CRADR 08-10

EBOX/3-64

EBOX/3-65

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CONTROL RAM REGISTER ——————————————a]
Figure 3-45

COND and Dispatch

Layout and Control

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Figure 3-46

3.4.7

MUL Done

CRA Dispatch Parity

Control RAM dispatch parity is computed using a 10160 parity circuit. This circuit (except during
periods when MR RESET is truc) sampies CRA DISP bits 00-04 and computes CRA DISP parity.

Normally the combined CRAM parity is 0odd, when correct. The clock board monitors the state of
CRAM parity, which inciudes the parity for the dispatch field. If the CLK CRAM PARITY CHECK
flag is set on the clock board (via diagnostic function 044), then any CRAM parity error stops sll
clocks. This will occur on the EBox clock following the CRAM parity error.

During the power up sequence MR RESET scts and remains set. This generates the signal DISP
RESET PARITY, which forces the state of the dispatch parity network to indicate odd parity
although the parity of the dispatch field (which now contains all zeros) is even. This, together with the
remainder of the control RAM register which is clear, yields odd parity. The effect is to make the
parity of the CRAM register appear to be odd following MR RESET. This logic assures that the
ciocks have no chance of stopping in the event that CLK CRAM PAR check is true when a CONO
instruction is issued after the EBox has been powered up and this instruction causes MR RESET of
similarly if a diagnostic MR RESET is issued.

EBOX/3-69

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Figure 3-47 Control RAM Addressing
EBOX/3-71

APPENDIX A
UNDERSTANDING THE MICROCODE

The control portion of the EBox comprises the DRAM and the CRAM. The DRAM has storage for
$12 decimal words, one for cach KL instruction. During instruction execution, the DRAM word
provides information about the type of memory references by the executing instruction. It also provids an index into the main control programs contained in the CRAM.

The CRAM provides storage for 1280 microinstruction words that are structured into a complicated
control program called the “microcode.” This section defines and explains the microcode. Although
many figures of sampie listings from the microcode listing are used throughout the discussion, an
assumption is made that the reader has an up-to-date copy of the microcode listing (either hard copy

or microfiche). The examples shown here refer to specific sections of the listing: the reader may wish (0
follow the examples through the actual listing while reading this section.

The discussion begins by introducing the microcode and describing field, value, label, and microinstruction definitions. This leads into defining macros, pseduo-operators, and location control. Then,
two instructions (MOVE and ADD) are illustrated, leading the reader through the microcode listing.

Figures A-17 through A-23 (located at the end of this appendix) complement
the discussion and define

all the CRAM and DRAM fields. Refer to these figures whenever necessary.

The microcode is presented in groups, with each group (designated a through g) representing four octal
digits as they appear in the listing. Each group represents one or more fields. For example, the listing
for microcode address 0724 is shown in Figure A-1.

vore

| moe

omo

wes

omr

samm

cowol

aofala

amsm

Iafs

CHAM tocaton

mte

whech tha

o« St

Figure A-1

Sample Microcode Listing

EBOX/A-1

~rieo

Each of the group’s coding is defined in the respective figures listed below:
Figure

Group

AN -

A-17
A-18
A-19
A-20
A-21
A-22

<
j

L B

A-23-25

The DRAM contains storage for each instruction. During instruction execution, the DRAM word
(Figure A-4) provides information about the type of memory references required by the executing
instruction and also provides an index into the main control program locsted in the CRAM.

Variable

Definition

SXCT = |

Enables special XCT instruction, which allows disgnostics to
generate large addresses. (Do not need SXCT with extended
addressing. Cannot do it in Model B hardware.)

EXTEND = }

Enables the extended instruction set.

DBL.INT = 1

Enables double integer instructions.

ADIBP = |

Enables adjust byte pointer.

RPW = |

Enables Read-Pause-Write cycles for non-cached references by

some instructions.

WRTST =0

Enables Write-Test cycles at AREAD time for instructions such
as MOVEM and SETZM.*

Conditional Assembly Variable Definitions

The Conditional Assembly variables observed in the microcode listing are listed and defined below.
(The definitions are presented for the variable set to |. The values shown are the normal settings.)
Variable

Definition

TRACKS = 0

Enables storing the PC after every instruction and creates
DATAL/O PI, to read/setup the PC Buffer address.®

OPCNT =0

Enables code to build a histogram in core to count the usage of
each op code in both USER and EXEC mode.®

OP.TIME =0

Enables code to accumulste time spent by each op code.®

FPLONG = |

Enables KA style double p.ecision floating-point instructions
{c.g.. FADL, FSBL). This feature is not supported in systems
running the TOPS-20 monitor.

MULTI =0

KLPAGE = 0

If operating a multiprocessor system, this suppresses cache on
unpaged relerences; paged references are left up to EXEC.*
Enables the KL-Paging mode, for systems running the TOPS-20

monitor.

MODEL.B=0

Indicates extended addressing hardware, primarily a 2K
CRAM, rather than a 1280 word CRAM.*

XADDR =0

Enables extended addressing microcode. (Cannot do extended
addressing without Model B; Cannot have extended addressing

BACK.BLT = 0
SET/INSTR STAT = 0
Field Definitions

The actual (physical)

Enables optimization of IMULI to take only nine multiply
steps.

Enable instruction statistics code.®

CRAM bits are derived from the CRAM Board logic. However, no logical

relationship exists between the physical bits and the respective microword bit names. Figures A-2 and
A-3 are located at the end of the introductory discussion, just before the two examples. Figure A-2
shows how the physical CRAM bits are derived. Figure A-3 shows the physical bits and the corresponding microword bit position (and name). The microcode listing is ordered with respect to the
microword bit positions, not the actual CRAM order.

Microcode field definitions have the form SYMBOL/ = J, K, L, M. The J parameter is only meaningful when “D" is specified as the default mechanism. The K parameter defines the field size in the
number of bits (in decimal). The L parameter defines the field position (in decimal) as the bit number
of the right-most bit of the field; bits are numbered from 0 on the left. Note that the position of bits in
the microcode word (Figure A-3) bears no relation to the ordering of bits in the hardware microword,
where ficlds are often broken up and scattered. The M parameter is optional; it sclects & defsult
mechanism for the field. The legal values of this parameter are the characters D, T, P, or +, where:

Indicates that J is the default value of the field if no explicit value is specified.

Is used on the time field to specify that the value of the ficid depends on the time
parameters selected for other fieids. Within the microcode, T1 parameters are used to
specify functions that depend on the sdder setup time; T2 parameters are used for
fi:’ncficm that require additional time for correct selection of the neat microinstruction

without KL page).*
IMULIOPT = 0

Enables BLT to decrement addresses on each step if E < RH

{AC): breaks many programs.®

address.

Is used on the parity field to specify that the value of the field should default, such that

parity of the entire word is odd. If this option is sclected on a field where the size (K) is
zero, the microassembler attempts to find a bit somewhere in the word for which no
value is cither specified or defaulted.

*This feature is not supported.

EBOX/A-2

EBOX/A-3

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CRAM Board Logic Physical Bit
Fosition Derivation

EBOX/A-S

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Figure A-3

Actual CRAM Physical Bit Position to Microword Bit Position Correlation

ESOX/A-7

Is used on the jump address field to specify that the default jump address is the address
of the next instruction assembled (not, in general, the current location of +1).

In general, a field corresponds to the set of bits that provides select inputs for mixers or

Label Definitions
A microinstruction may be labeled by a symbo! followed by a colon preceding the microinstruction

definition. The address of the microinstruction becomes the value of the symbol in the feld titled *J."
For example:

decoders, or controls for ALUs. For example:

AR/ = 0,3, 26, D: the microcode field that controls the AR mixer (and, therefore, the data
to be loaded into AR on each EBox clock) is three bits wide. The right-most bit is shown in

the listing as bit 26 of the microinstruction. If no value is specifically requested for the field.

TOP:

This is a microinstruction whose J field (Jump Address) contains the value “TOP.TM It also defines the
symbol “TOP" to be the address of itself. Therefore, if executed by the microprocessor, the micro-

the microassembler ensures that the field is zero.

instruction would loop on itself.

ADy/ = 0,6, 17; the field that contains the AD is six bits wide, ending on bit 17. The fourth
parameter of the ficld is omitted, so that the ficld is available to the microassembler (if no
value is explicitly called out for the field) for modification to ensure odd parity in the entire

Comments

A semicolon anywhere on a line causes the remainder of the line to be ignored by the assembler; it is
purely information to the reader. For example:

word.

AD/0.6,17

Value Definitions

Following any field definition, symbols may be created in that field to correspond to values of the field.

The form is

J/TOP

:field definition in which following symbols

sexist.

Only AD.0, 6. 17 is relevant 1o the assembler; that data following the semicolon is useful information
to the reader.

SYMBOL = N, T1, T2
where:

{Octal) is the value of SYMBOL when used in the field:

T1 and
T2

Are optional and specify parameters in the time field calcultation for microinstructions
in which this field/SYMBOL is used. The microassembler computes the sums of all the
T1s and T2s specified for field/SYMBOL specifications in a word and uses the maximum value of the two sums as the default value for the ficld whose default mechanism
is T. For example:

AD/ =0,6, 17
XOR
= 31
A+B=¢61

; field definition is which of the following
: symbols exist.

Here, the symbols “XOR" and “A + BTM are defined for the AD ficld. To the assembler, therefore, writing “AD/XOR"TM means *place the value 31 into the &-bit ficld
ending on bit 17 of the microword.TM The symbols are chosen for mnemonic significance. Therefore, reading the microcode would interpret “AD/XOR" as “the output
of AD shall be the exclusive OR of its A and B inputs.” Similarly, “AD/A + B" is
interpreted as “AD produces the sum of A and B.” The second parameter in the defini-

tion of A + B is a control to the microassembler’s time-ficld caiculation. which telis the
assembler that this operation takes longer than the basic cycle and, therefore, that the
time field should be increased.

AR/ =0,3,26 D

:field definition for following symbols

AR =0
AD =2

Microinstruction Definition

A word of microcode is defined by specifying a ficld name, followed by a slash (/), foliowed by a value.
The value may be a symbol defined for that field, an octal digit string, or a decimal digit string
{distinguished by the fact that it contains 8" and/or 9TM and/or is terminated by a period). Several
ficlds may be specified in one microinstruction, by separating field/value specifications with commas.
For example:

ADB/BR, ADA/AR, AD/A + B, AR/AD

In this example, the field named “ADB" is given the value named “BRTM {(to cause the mixer on the B
side of AD to select BR); field “ADATM has the value “AR;” field has the value “A + B,” and field
“AR" has the value “AD."
Coatisustios

The definition of a microinstruction may be continued onto two or more lines by breaking the definition after any comma. That is, if the last nonblank, noncomment character on a line is a comma, the
instruction specification is continued on the following line. For example:
ADB/BR, ADA/AR,
AD/A + B, AR/AD

By convention, continuation lines are indented on extrs tab.

Macros
.
A macro is a symbol, the value of which is one or more field /value specifications and/or macros. A
macro definition is a line containing the macro name followed by a quoted string that is the value of
the macro. For example:

Here, the symbols “AR" and “AD" are defined for the ficld named “AR.” which
controls the AR mixer. Because only the default case is used, the AR does not change
unless a specific request to do so is made. Therefore, the field definition specifies zero
as the default vslue of the field. If the AR is loaded from the AD output. AR/AD is

iselect AR and BR as AD inputs
:take the sum into AR

AR + BR

“ADB/BR, ADA/AR, AD/A + B, AR/AF"

The appearance of a macro in a microinstruction definition is equivalent to the appesrance of its value.

written to set the mixer selects 1o pass the AD output into the AR.

EBOX/A-8

EBOX:A-9

Psewdo-Operators

The microassembler contains ten pscudo-operators:

This specifies that the two low-order bits of the address must both be ones. Because there are
no zeros in this constraint, the assembier finds only one location meeting this constraint.

.DCODE and .UCODE Sciect the RAM into which subsequent microcode is

-2

loaded and, therefore, the field definitions and macros
that are meaningful in subsequent microcode.

=11

(ooeee

This specifies an address in which the 40, bit is zero. Due to the implementation of this
feature in the assembler, the default address progression applies only to the low-order five
bits. Therefore. this constraint finds one word in which the 40, bit is 0 and does not attempt

.TITLE

Defines a string of text to appear in the page header.

.TOC

SET

Defines the value of a conditional assembly parameter.

Microcode Examples

.CHANGE

Redefines a conditional assembly parameter.

.DEFAULT

Assigns a value to an undefined value.

MOVE and ADD. The requirements that the microcode is loaded and running (i.c., in the HALT
loop) arc assumed. A dispatch (test for an interrupt) occurs during a HALT loop. Once an interrupt is
present, the microcode leaves the HALT loop and goes to the first microinstruction.

Enables assembly if the value of the parameter is not

MOVE Instrection

Defines an entry for the Table of Contents at the

zero.

IFNOT

10.

.ENDIF

Enables assembly if the parameter value is zero.
Re-enables assembly if suppressed by the parameter

named.

Location Control

A microinstruction labeled with a number is assigned to that address. The character **=" at the beginning of a line, followed by a string of Os, Is, and/or *s, specifies a constraint on the address of the
following microinstructions. The number of characters in the constraint string (excluding the “*="') is
the number of low-order bits contained in the address. The microassembler attempts to find an unused
Jocation whose address has zero bits in the positions corresponding to Os in the constraint string and
one bits where the constraint has Is. Asterisks denote “‘don’t careTM bit positions.

If any zeros are in the constraint string, the constraint implies a block of (2 * ® N) microwords, where
N is the number of 0s in the string. Ali locations in the block have 1s in the address bits corresponding
to Is in the string. Bit positions denoted by °s are the same in all block locations.

In such a constraint block, the default address progression is counting in the “0" positions of the
constraint string, but a new constraint string occurring within a block may force skipping over some
locations of the block. Within a block, a new constraint string does not change the pattern of default
address progression, it merely advances the location counter over those locations. The microassembler
fills them in later.

A NULL constraint string (** =" followed by anything except 0, 1, or ®) serves to terminate a constraint
block. For example:

to find onc where that bitisa |.

beginning.

This specifies that the low-order address bit must be zero. The microassembler finds an even-

The following paragraphs lead the reader through the microcode, while defining two instructions:

Refer to Figure A-4. The initiat dispatch is a NICOND Dispatch. It is a decision starting at microcode
address 140 that is used to decide which condition (e.g., TRAP, NICOND) is satisfied. Looking up
Next Instruction Dispatch in the microcode listing Tabie of Content refers the reader to line 2549 in
the listing. The decision begins at line 2549. Notice that the actual decisions and respective implementations begin at microcode sddress 140 (NEXT), and assuming 8 NICOND Dispatch is present, the
listing refers the reader to NEXT + 12 (microcode address 152).

The NICOND Dispatch is the normal case; the instruction is in the ARX and begins execution.
Location NEXT + 12 leads (jump to the correct decision) the reader 1o microcode address 152

{(XCTGO), line 2606. Notice in the listing (and Figure A-5):

At XCTGO, cn line 2606, the comments state “save the instruction, sign extend Y and calculate the
effective address (EA).” The macros define all the things that happen here. Initially, one should consider where to go next. That information is contained in:

§.

The J-field, which typically contains the “suggestedTM next address. In this example, it is 160,

The Dispatch {(or SPEC) field.

Whether that is used or not depends on item 2.

The SPEC field follows the *TM* column in the microcode listing (Figure A-22). Specifically, the ficld

observes the last two digits of the " column. In this example, those digits are **36.” Going to Figure
A-22, notice that a decoded 36 in the SPEC ficld is an EA MODE Dispatch.

An EA calculation is called for, which indicates that under certain conditions the J-field (160) may not
be the actual next address. These conditions are Indexing (bits 14-17 of the instruction), Indirection
(bit 13), both conditions, or neither condition. In this case, EA MODE dispatch looks at those bits of
information in the instruction and then ORs them with 160 (the J-field). Because this simple MOVE
instruction uses neither indexing nor indirection, go directly to 160. This appears on line 2647 (if you
cannot easily locate this, go to the index at the rear of the listing, ook up address 160 and find that line
2647 is where microcode address 160 appears). Refer to Figure A-6.

odd pair of locations and places the next two microinstructions into them.

EBOX/A-10

/’

EBOX/A-11

SIART

Codwe NU TGO

THALT LOOTM

Foafesiipmar

cve

342

[ UNOFE ]
L

RET

METER

190,

L33

r’l..o |
COMPEA

ted

TRACK

1%t

BRN

ARN AR

BRI NRET
TT N ¥T

ARNSET ACCOUNT BN

SAVE

NREAMODDISE FCOMPEA

INSTR S ENTEND
Y,

COCRICULATE LA

Microcode Address 152

O} GNRNEORIO
SO iRt oukKe

Figure A-6

13T

COMPE A

GIN AR

A READ

1ox AL

Microcode Address 160

Again looking at the " column, observe the SPEC field is “02." Checking Figure A-22, SPEC code
02 indicates doing an A READ Dispatch by stating DRAM A RD. Go to the microcode listing index
for DRAM words (it appears just bxfore the microcode address index). The MOVE instruction is op
code 200. Find 200 and notice it refers you to line 2782. Refer to Figure A-7.

Oupetch

INXTY

1 F

Figure A-5

Owcrwan Muts s

140

FETRTY ST TR

193

182

154

WICOND

] IOO’AVO'] I
l
e

TRAP

b Tt TRAYT TRR3S) 3

l I ADONESS

RPEOM

Figure A-7

FMWIN

BAsi send

DRAM Word 200

This is the DRAM word for the basic MOVE instruction. The A-field is a **$TM (Figure A-26). This 5"
is ORed with 40 (a constant used whenever an A RD DISPATCH is performed) and the J-field (0000)
of microinstruction 160. This results in a *45." Turning again to the index, look up microcode address

45. The index indicates line 2711; see Figure A-8.

[RESSONTTYVIS IERE FURRYS
| TS RSVING 3 1081

1) S

Figure A-8

TIEHBR ARSINNEER TFEICH.

GET OPERAND PREBRTCH.

Sl
O

ASTARTENRCUTE

HIME 31 IR ISP J O

Microcode Address 45

This part of the microcode states: get the operand (from the MBox), begin & prefetch of the next
instruction, and begin instruction execution. Notice also in the macros, that an IR Dispaich is called.
Looking now at the SPEC field, it is “01;” looking this up in Figure A-22 states DRAM J DISwhere 10 go by taking only the J-fieid of the
ing
PATCH.A DRAM J DISPATCH dictates
DRAM word as the address. In the case of the simple MOVE instruction (look back st Figure A-T),
notice the A-field is **S,” the B-field is “5,” and the J-field is “100.”

Looking up microcode address 100 in the index leads the reader to line 2819 (Figure A-9).
102004

L orae
ol "o okl (RNEKLOUODAKRIS
ORI ooy

Figure A-4

MOVE Instruction Flow Diagram

EBOX/A-12

Figure A-9

Sx
v MOME

MORE AS IS § ROM AR

Microcode Address 100

EBOX/A-13

The SPEC field is 33 and, again referring to Figure A-22, now a DRAM Bis called. DRAM Bis the
actual “store the operand.” The MOVE began by fetching the operand and placing it in the AR.
Finally. it is placed in a particular AC. The DRAM B Dispatch takes the B-field of the DRAM word
(5) and ORs it with the J-field (170) of the current microinstruction (address 100). This results in: 170 V
§ = 175. The index takes the reader to line 2749; sce Figure A-10.
L0078 (130300 V0000403

10060000

2749 STAC

STARY

ACH_ARSNANTINSTR . NORMAL ANDIMMEDIAT Mol s

Microcode Address 175

Figure A-10

Observing the SPEC field indicates *06;TM t‘hil is a NICOND Dispatch. Also, the J-field is 140, taking
the reader to the original decision matrix. Again, all the possibilities are considered when the next
instruction arrives and the process continues.

Not all fields were discussed here, only the major ficlds. All ficlds are illustrated and defined in Figures
A-17 through A-26. It is left to the reader to check the unmentioned code ficlds with the respective
defining figures.

ADD Instruction

Many of the assumptions used in the MOVE example are used again here (refer to Figure A-11).
Assume that the last instruction was 8 NICOND Dispatch; go through the decision matrix to microcode address 152. Assume Indexing this time, this leads the reader to address 161. Locate address 161
on line 2648 of the listing (sce also Figure A-12).

Indexing is handled at this time. The AR is added to the contents of the XR (Index register) to generate
the EA. Also. an A READ Dispaich is called out. The A READ leads to the next microcode instruction, which is where the operand is located. Assume AC3 is being used (for example) and its content is
*50;" assume the Y-field contains *100.” This results in EA = 150.

140 ‘

12 l

152

a4 l

Y e S G =
wl

INEITHERS

[anmu]au'ls

Again, because of a COMP EA (EA calculation), a “40" is forced into the J-field by the hardware
during the A READ Dispatch. Figure A-13 shows the DRAM word for the ADD (270) instruction.
Use the DRAM index to locate line 4091.
The A-field of the DRAM word is **5.” This, ORed with the forced “40,” results in *45.” This is
microcode address 45, just as in the MOVE example. Locate address 45 on line 2712; this is where the
operands are fetched (see Figure A-14).

A *01" is in the *f" column of the SPEC field, s DRAM J Dispatch. Looking back at Figure A-13,
notice that the J-field of the DRAM word is “*504." Go to the microcode address index and locate
address 504 at line 4098 (see Figure A-15).

This is where the ADD takes place. The macros state “°A plus B (the two operands) into the AD.” The
SPEC field (Figure A-13) is a *5.” The J-field of the current microinstruction is 170. These two are
ORed, resulting in 175. Using the index again, locate address 175 on line 2749 (see Figure A-16).

The operand is stored in ACO and the J-field leads the reader back to location 140 again, the NICOND
Dispatch. The microcode is now ready for the next instruction.

Figure A-11

EBOX/A-14

ADD Instruction Flow Diagram

EBOX/A-15

P
v

188

ot I

1016 (R 301000 000

01T R (0007 S0

0000 263

COMPLA GAN AR ARIAD
GEN AR

XK CINDENUD AREAD TOCAENTTS AR
weromono |

Figure A-12

R
3

A0A ADXA

Aowaoxs

Microcode Address 160, 161

AR R

fwfw]|mfada|a

Figure A-13

L4KRN 390 08 U2 AL 0900

713

DRAM Word 270

-4

BROAK LIS ALK T IO 30 T OM RAND FRELL IO

TN S LRI

“

S STARTIALC
1)

anee

treplenrent

Figure A-14

Microcode Address 45
»
»

150170

Figure A-15

ADDAK

SKTACU

AT ASE

ADTEAGS AT

»
»

Microcode Address 504

2
»
»
»

10178 0140 4001 00000307
000 1N 00

3739

Figure A-16

STAC

AR NTINSTR

NOKMAT

Figure A-18

Jruo

]

Microcode Address 175

wicno coot wast avomess

FosiTion

AN INMEDIATE MODES

wcno womo

Microwor

anx
=

19 o

rores
1

o| |

The S FIELD Gutines the bam sddrem
10 o

10 20m

thn ot
s

Figure A-17

Microword

uarcam
et
o

Moz

mom

" conomec

Figure A-19

EBOX/A-16

mose

womsL

Microword “c" Field

EBOX/A-17

ruaon
i

)
H

s rory

eno woRD

e rimon

sca0 | scao

s
.

cant

n
n

2
»
»

PosiTION

]

wu.

@ | w
o

SurFTARARX

3 a0

anx

answar

w11

ow|

»
¥

xiora

Microword """ Field

sion

scapex

scapros

A0 LONG.
“r wirory

Figure A-22

Anw

Antwo|

w | sw|

| s

EETTTTEL]

mcnowono |7

»
=

wasons

sumerae |l

assereece

p—

SHUKEEYE

gereEcgssat
e

rean

o|lolelalulalfedalala

rosiTion

o
s

—

[

evaun-o

|w|»|ow|o|laofofla]s]e]|ao

EBOX/A-1%

EBOX/A-19

ENABLE AEOUIRED

naBLE REQURED

ngnd

CRO wORD.

rosiTION

w|ln

n|l

wu
ragen

USED T0 ADORE S5 £ AST MEMORY

srenaen

@
“

cono e wsT
»

o
ok

o7
w3

g
B

cow
Test

uwcono

wew

I—

A caic

e e[
A

;
=

w1 cac

NOT XAODW

oMo st i

W
s

=
.

——
e

Src
evew

Byges~~-

cacHt
T
wr
e

seco

oxc

[ o [
[
R

TEET

[ & [Soed]
T

RGP
N

W REFLL
AN,

Loapcea

loaoyen

loaoren

COND MBOX CTL
Figure A-23

Microword

(Magic Numbers)
(Sheet | of 3)

'g"

Field

m‘:‘.

: ::::u

rom

romw

Figure A-23 Microword g
(Magic Numbers)
(Sheet
2 of 3)

EBOX/A-20

EBOX 'A-21

Sevmatran

ORAM

oKD

ECEEEECOEGE T

ous cTi

oATAG

O
conortus T

'
2
.

lin

(ORI
Zhis

OATAIPAG (L)

COND/DIAG FUNC

OATAQ PAG

scmRen

wrawm

conomTR

cumrenr

comorm

EUR

Moobw)

woramw

Figure A-24
Figure A-23

DRAM Word Format

Microword “g" Ficld

(Magic Numbers)
(Sheet 3 of 3)

EBOX/A-22

EBOX/A-23

- boEB)
>

APPENDIX B

ABBREVIATIONS AND MNEMONICS

AC
ACKN
ACT
AD
ADA
ADB
ADR
ADX
AF
ALT
AlLU
APR
AR
ARL

ARM

ARMM
ARR

ARX
ARXL
ARXM

ARXR

BOOLE
BR
BRK
BRX
BUF

Accumulator
Acknowledge
Action
Adder
Adder A
Adder B
Address
Adder Extension
Action Flag
Alternate

Arithmetic Logic Unit
Arithmetic Processor
Register
Arithmetic Register
Arithmetic Register
Left
Arithmetic Register
Mixer
Arithmetic Register
Mixer Mixer
Arithmetic Register
Riglt
Anthmetic Register
Extension
Arithmetic Register
Extension Left
Arithmetic Register
Extension Mixer
Arithmetic Register
Extension Right

B
Boolean
Buffer Register
Break
Buffer Register Extension
Buffer

CRAM
CRY

CSH

CTOM
CTR
CWSX
cYc

C
Control RAM
Carry
Controller Select
Cache
Control
Controlier-to-Memory
or Cache-to-Memory
Counter

Called With Special Execute
Cycle

DIAG
DIR
DIS
DISP

DIV
DRAM

EtoT
EBR

EBUS
ECL
EDP

ENA
ERR
ERA
EPT
EX
EXP
EXT TRA
REC

EBOX/B-1

Effective Address

ECLto TTL
Executive Base Register
Execution Bus

Emitter-Coupled
EBox Data Path
Enable
Enable
Error
Error Address

Executive Process Table

Extension
Exponent
External

External

Transfer Receiver

FE
FE
FLG
FM
FOV
FPD
FPD
FUNC
FXU

F
Function
Floating Exponent
Front End
Flag
Fast Memory
Floating Overflow
First Part Done
Floating Point Divide
Function
Floating Exponent
Underflow

Gated

GEN

INC
INH
INSTR
INT
INTR
INVAL
10T
IR

G, H

Greater or Equal
Generate
High

MR
MTR

NICOND
NXM
NXT
oP
OVN

PA
PAG
PAR
PC
PCF__¢#

I
Increment
Inhibit
Instruction
Internal
Interrupt
Invalid

Input/Output Transfer
Instruction Register

MB
MBC
MBX
MBZ
MCL
MEM
MHz
MIX

MQM

Memory Buffer
M Box Control
MBox Control
MBox Control
Memory Control
Memory
Mega Hertz
Mixer
Muitiplier Quotient
Multiplier Quotient
Mixer

SBUS

Next Instruction
Condition
Non-Existent Memory
Next
Operation (code)
Overrun

sC
SCAD
SCADA
SCADSB
SCD
SCM

P.Q
Physical Address

SH
SHRT
SIM
sp
SPEC
SR

Pager
Parity
Program Counter
Previous Context Flags

from Number
Previous Context Public
Program Counter
Performance
Page Fault
Page Refill
Priority Interrupt
Priority Interrupt
Assignment
Priority Interrupt
Hold
Physical Memory

SEL

S
Storage Address Parity
Subroutine
Storage Bus
Shift Count
Shift Count Adder

Shift Count Adder A
Shift Count Adder B
Shift Count Adder
Shift Count Mixer
Select
Shifter
Shift Right
Simulate
Special
Special
State Register
Synchronize

TtoE
TE
TRA

TTL

UBR
UCODE

RE
REC
REF
REG
REL
REQ
RESP
RET
RIP

EBOX/B-2

uv
User Base Register
Micro Code
Valid

VMA

Virtual Memory Address
Transfer
Index Register

XFER
XR

Ww.X.Y,Z

WARN

Warning
Word Count

Word

Write

Previous
Page Table
Powet

RAM

T
TTLwo ECL
Transmit ECL
Time
Transfer
Transistor-Transistor
Logic

VAL

Address

Least Recently Used

SADRP

SBR

N, O

J.K, L
Jump
Low
LRU

Master

Mecter

R
Random A ccess Memory
Read

Receive ECL

Receive

Reference
Register
Release
Request
Response
Return
Request in Progress
Request

EBOX/B-3

APPENDIX C
KL10-PY EBOX DIFFERENCES

SECTION 1

C.1

OVERVIEW

INTRODUCTION

This appendix details the differences and changes that have been incorporated into the Model B CPU
EBox (calied KL10-PV EBox). It should be used explicitly with the current EBox Instruction Execution
Unit Description (EK-EBOX-UD-004) to completely understand the KL10-PV EBox.

The KL10-PV EBox differs fundamentally from the Model A CPU (KL10-PA) EBox as follows:
1.

The KL10-PV EBox main source clock operates at 30 MHz and provides a “‘speed marginTM
clock source which operates at 31 MHz.

The KL10-PV EBox implements a virtual address space of 32 sections of 256K words (8

New memory “hooks" are provided by maintaining a fixed delay (factory adjusted) from the
point where the EXTERNAL CLK signal enters the CLK control module to where it exists.
The EXTERNAL CLK signal is now the main clock frequency as opposed to twice this

million words). To provide access to this virtual address space. certain instructions have
been modified or deicted and new instructions have been added and implemented.

frequency in the KL10-PA EBox.

The control RAM (CRAM) definitions (Figures A-17 through A-23) have been modified for
the KLI0-PV and are noted in Appendix A. However, since the microcode is subject to
change. always refer to the Istest Microcode Listing for complete accuracy.
The CRAM now provides storage for 2048 microinstruction words in the KL10-PV.

The KL10-PA is designated the basic machine; the KL10-PV is designated the extended machine.
C.2 KL10-PV EBOX MODULE UTILIZATION
Figure C-1 shows the new KL 10-PV EBox module utilization. Refer 1o Figure 3-1 for the KL10-PA
EBox module utilization.

Table C-1 and the following paragraphs summarize the new KL10-PV modules, their downward compatibility with the KL10-PA EBox modules, and their equivalent modules.

EBOX/C-1

25 os]
1|32

|30]2n]ec| 1] e2fe3 fuu as] ae] ] s as s

There are & module types (12 modules) for the KL10-PV CPU EBox that are completely new

1] s3] s3] ]

KL10-PV

Qty/CPL

KL10-PA

MRS26-YA
M8540

1
1

MBRS26
MES10

MBRSs43
MES44
MBES4s
MES48

1
1
1
S

M8s27
M8530
MB8539
MES2%

Total

MBs41
MB8S542

1
:

MS8SI1
M8s23

Total

Module

Min Rer Level

M8s12

noTo>®

There are six module types for the KL10-PV that are downward compatibie

M8s22

MB8S524
Figure C-1

MB8S525
M8s32

KL10-PV Module Utilization

MBS38

#If Rev € s used, clock frequency soldered jumpers must be
changed: it 1 desirable 10 use Rev E because i uses jumper

plups

Tsble C-1

EBox Module Utilization Changes
€3

Min Rev Level

Module

for KL10-PV

Qty/CPU

MBS12
M8s22
M8524
M8525

B
A
D
H

6
1
1
1

M8532

MB526-YA

MBS38*
M8540
M8541
M8542
M8543
MB544

c
A
A
A
A
A

MB548

M8545

Equir

C.3.1

Module
M8512
ME522
M8524
M8525

yes
yes
yes
yes

FUNCTIONAL DIFFERENCES
Higher Clock Rate

A new module (M8526-Y
A) provides a main source clock rate of 30 MHz and a “'speed marginTM clock
rate of 31 MHz to the KL10-PV CPU. Section 3 of this appendix describes this new module and the

clock distribution in greater detail.
€32

Extended A

1
1
1
1
1
'

M8526
M8532
M8538
MB510
M8S11
M8523
M8527
M8530

no
yes
yes
no
no
no
no
no

The KL10-PV CPU implements a virtual address space of
32 sections of 256K words
(8 million words).

M8528

In addition to differences in effective address calculation, certain instructions are affected in other

MB8S39

Subsection C.4 details the extended addressing effective address calculations.

A discussion of the KL paging for this virtual address space is provided in Section 1, Subsection 1 4, of
this document. To understand the K L10-PV EBox, read these subsections in conjunction with Section

3 of this appendix, which provides a detailed description of this implementation and the hardware

changes and differences of each module 1o accomplish extended addressing
€33

New lnstructions
and Considerations

ways by extended addressing. These considerations are detailed in Subsection C 5.

*Requires soldered jumper changes. It is desirable 1o use Rev E

EBOX /C-2

EBOX/C-3

SECTION 2

FUNCTIONAL DESCRIPTION

C.4 EXTENDED ADDRESSING - EFFECTIVE ADDRESS CALCULATION
The calculation of the effective address (E) is the first step in the execution of every instruction. At
system startup the pager is off, therefore all references are to physical address space. The effective
address calculation for the basic machine is detailed in Subsection 2.10.1 of this document.

Even in an extended processor. an effective addreses calculation performed in section 0 is done exactly

as outlined in Subsection 2.10.1. All addresses and displacements are taken as 18-bit quantities con1ained in bits 18-35 of an instruction word, an index register, or an indirect word. When a program is
running in section 0. it can never make a reference to a nonzero section exc+pt by calling the monitor.
1n terms of addressing. section 0 of an extended processor is entirely compati..le with the single section
of a basic processor.

Evervthing in the following discussion refers to execution of instructions with the PC in a nonzero
section. (Refer to Figure C-2, Extended Addressing Effective Address Calculation Flowchart.)
C.4.1

Instruction Formsat

The format of a machine instruction (Figure C-3) is the same as on a basic machine. The effective
address computation is dependent on three quantities from the instruction: the Y (address) field. the
X (index) field, and the I (indirect) field. These are 18 bits, 4 bits, and 1 bit, respectively.

Depending on the format (global or local) of the index and indirect words, the effective address al-

gorithm will perform cither 18-bit or 30-bit address computations. When a 30-bit quantity is indicated
by the index or indirect word format, an explicit section number is being specified and the address is
catled a global address. When an 18-bit quantity is indicated by the index or indirect word format, the
section field is defaulted from some other quantity (e.g.. the PC), and the address is thus local to the
default section and is called a local address. (Default is defined as the assumed value.)

in the simplest case, consider an instruction which specifies no indexing or indirection:

3..400/

MOVE

T.1000

Here the cffective address computation yields a local address 1000, and the section used for the reference is section 3. the section from which the instruction itself was fetched. The address is taken from
the default section. The default section will always be the section from which the last instruction or
indirect word was fetched.

C.4.2

lndexing

The first step in the effective address calculation is to perform indexing. if specified by the instruction.
The calculation peformed dencnds on the contents of the specified index register (X):

1.
2.

Ifthe left half
of the contents of X is negative or 0. the right half of X is added to the Y field

(from the instruction word) to yicld an 18-bit local address.

If the left half of the contents of X is positive and nonzero, bits 6-35 of X are added o Y
(sign extended) to yield a 30-bit global address.

Index registers may be used to hold complete addresses which are referenced via indexed instructions.
A Y field of 0 will commonly be used 10 reference the exact address contained in X. Small positive or

negative offsets (magnitude less than 2°*17) may aiso be specified by the ¥ ficld. ¢.g.. for referencing

data structure items in other sections.

EBOX ‘C-$

SEaw W
ion

Figure

C-3

Instruction Format

43
1f indirection 1s specified by the instruction, an indirect word 1s fetched from the address determined by

Y and indeving (if any). The indirect word is considered to be “local formatTM if bitO is a 1. and “global

¥ is siGMD

OisrLACEMINT

formatTM if bit 0 is a 0.

g ey

bocn

C.43.1

Local Format Indirect Word (Figure C-4) - This word contains Y. X, and I fields in bits

13-35. Bit Omust bea 1. bit | must be 0 (its use 1s reserved for future hardware); bits 2-12 are reserved.

l GLosaL

avoness
wa

REPACSENTS THE CONTENTS.

OF INOKX REGISTER X

Figure C-4

Local Format Indirect Word

C.432 Global Format Indirect Word - This word contains Y. X, and 1 fields in a different format,
allowing a full 30-bit address field (Figure C-5)

PaGE Fan

Thar

If indexing 15 specified 1n this indirect word, bits 6-35 of X are added 10 the 30-bit Y to produce a
global address

0008 01 GLoBAL

808w

SBTE et

scion.

T GLomaL!

Figure C-5

Global Format Indirect Word

ooness
“vna

(XTENOED EFFECTIVE ADDRESS CALEULATION

Figure C-2

Extended Addressing. Effective Address Calculation Flowchart

EBOX C-6

EBOX C-7

Global indexing

C.4.4 Examples

In any (nonzero) section:

Simple instruction referenced within the current PC section:

3..400/

MOVE

JRST

T,1000

MOVE
ADD

Jumps to 3002000

2000

Local tables may be scanned with standard AOBJIN loops:
LP:

MOVSI

X.-SIZ

JRST
AOBIN

FOUND
X.LP

CAMN

T.TABLE(X)

LP:

CAMN
JRST

CAIGE
AOJA

X.0

T.@ [Global®* TABLE
X]
FOUND

adds the 100th location of data block starting at 22,1000 i e . Jocation 22..1100.

:TABLE in current section

In any {nonzero) section:
MOVE
ADD

:TABLE(X)in global format

of bit 18.

Global indirection

X.S1Z-1
X.LP

In any {nonzero) section:

Word in argument list:

MOVE

T.6[30..1000]

loads T with the contents of location 1000 in section 30.

@ VAR(X)

.indexing and indirecting if

sspecified will be relative to the
:section in which this pointer
;resides, i.e., the section of the
wcaller

*1ocal rep
ind
word as for
d in Figure C-4.
*(ilobal represents indicect word as formatted in Figure C-5

Global indirection with indexing
MOVE]
MOVE

Array in another section:

LOOP:
1.100
T1.100(1)

moves 22,,1100 to T1, i.e.. 100th entry in array starting at 1000 in current section (22).

J.100

T.6IGLOBAL 30.1000(J)}

loads T with the contents of location 1100 in section 30.

Local indexing

In section 22:
MOVEI
MOVE

T.[22..1000]
T1,-100(T)

adds the -100th location of data block starting at 22.,1000, i.c.. location 22..700. In global
indexing, the control block can cross a section boundary since carries are not suppressed out

Subroutine argument pointer may be passed to subroutine in another section:

Local*

THLIOXT)

Global indexing with negative offset

Global tables may be scanned with full address and index:

MOVEI

T.[22..1000]

MOVE
ADD
SOJGE

C.[2000000-1}
T.6[GLOBAL 30,100(C}}

:2 sections worth

c.Loop

adds the 512K array from 30..1000 through 32,.777. Even if the array had been less than 27
words long and did not cross any section boundaries, it would still not be possible to use
AOBIN for the loop. because the entire index register is always added in global indirect

Negative indexing

word, and the left haif cannot be used for the AOBIN loop count.

In section 22:

Negative indexing a large array

1 OO0P:

MOVNI
ADD
AQJL

1.100
T.1000(1)

LOOP:

L.LLOOP

adds locations 22,.700 through 22..777 in the current section, i.e., section 22.

MOVE

C.[-2000000+1]

AOQJLE

C.LOOP

ADD

T.6{GLOBAL 32.1000(C)}

.2 sections worth

adds the $12K array from 30,,1001 through 32.,1000.

Refer 1o Subsection C.5.1.3 for example of instruction format indirect word used with extended push-

down stack.

EBOX/C-8

EBOX 'C-9

All effective address computations yicld a 30-bit address defaulting the section if necessary. as described above. However. immediate instructions use only the low-order 18 bits of this as their operand:

C.5 NEW INSTRUCTIONS, INSTRUCTION MODIFICATIONS, AND CONSIDERATIONS
The existence of extended addressing has no effect on most of the defined instructions. e.g.. MOVE,
ADD. Those instructions for which there are other considerations are described in this subsection.

which they are executed.

The following terminology is used in this subsection:

Immediate Instructions

C.4.5

hence. instructions such as MOVEL, CAIL, etc., produce identical results, regardiess of the section in

Two immediate instructions are implemented which do retain the section field of their effective ad-

Global PC - The one-word program counter containing a global address: bits 0-5 are zero.
No flags are included.

dress.

XMOVEI (op code 415, same as SETMI} Extended Move Immediate - This instruction
loads the entire 30-bit effective address into the designated AC, setting bits 0-5t0 0. If no
indexing or indirection is specified. the current PC section will appear in the section field of
the result. This instruction would replace MOVE!] where an address (rather than a smail

indexing format.

constant or in-section address) is being loaded.

Example:

as caller):

calling a subroutine in another section (assuming argument list in same section
MOVEI
PUSHJ

AP.ARGLIST
P.G[SUBR]

The subroutine could reference arguments as:

MOVE

global address in AP. The actual section of the effective address is determined by the caller,
and is implicitly the same as the caller if an IFIW is used as the argument list pointer, or is
explicitly given if a global indirect word is used.

XHLLI (op code 501) -~ This instruction replaces the left half of the designated accumulator
with the section number of its effective address. It is convenient where global addresses must
be constructed.

C.4.6

Global stack pointer - A one-word pointer to the end of the stack. which may be in any
section. The LH is greater than 0 and is a global address: no stack length is included.

Local byte pointer - A one-word byie pointer (as on the KL10-PA) with the addition that bit
12=0. Indexing and indirection follow the rules for snstructions.

Global byte pointer - A two-word byte pointer in which bit 12=1. The second word con-

E - Effective address

tains a giobal address.

C.5.1

Special-Case Instructions in Nonzero Sections

TG 2AP)

In both cases. the argument list pointer would be found in the caller’s section because of the

T.@1{A0)

or could construct argument addresses by:

XMOVEI

Local stack pointer - A one-word pointer to the end of the stack in the current PC section.
The L.H has a8 negative count of the number of words lefi until overflow and is in local

C.5.1.1 PC-Storing lastructions (PUSHJ, JSP, JSR, POPJ; - When the PC is in a nonzero section,
these instructions will store a 30-bit PC without flags in order to accommodate the 30-bit address. New

instructions (see below) are available to provide access to the processor flags. When the PCisin 8
nonzero section, POPJ will restore the 30-bit PC from the stack word. Thus, machine-independent
subroutines can be written which run in section 0 and in nonzero sections.

C.5.1.2 Byte Instructions -~ Representing the P and S fields and the full memory address requires
more than 36 bits of byte pointer. Therefore, & byte pointer will be taken as a two-word quantity
{shown in Figure C-6) if bit 12 of the first word is one. The address of the word containing the byte is
computed from the second word as an indirect word.

AC References

Any reference to a local address in the range 0~17, will be made to the hardware ACs. Also. any global
reference to an address in sections 0 and 1 in the range 0-17; (i.e., 0-17, and 1000000~ 1000017) will be
made to the hardware ACs. Global references to locations 017, in any section other than section 0 or
1 will reference memory. Thus:

Local addresses referenced in the usual AC range will be reference ACs as expected. e.g..
MOVE 2.3 will fetch from hardware AC3 regardiess of the current section.

To pass a global pointer to an AC, a section number of | must be included.

Very large arrays can cross section boundaries. they will be referenced with global addresses

which will always go to memory, never to the hardware ACs.

ol 1 l x
o0

l 1[

AVALL TO SOF TWARE

1N SECTION ADDRESS

SECTION

0m 08
o2

10 00T

Figure C-6

Byte Pointer Format

PC references are always considered local references: hence. a jump instruction which vields

an effective address of 0-17 in any section will cause a code to be execuced from the ACs.

EBOX/C-10

113

1112 13

EBOXC-11

If bit 12 of the first word is 1. bits 13-35 of the first word would be 0 and the second word would
specify the entire address. Incrementing a byte pointer of this format when incrementing the word
address will increment the second word only. Carries from the RH of the second word will propagate

ot 08

FLAGS

UPY -420

into the LH so that strings can cross section boundaries.

For convenience, bit 12 of the first word may be set to zero: then the second word need not he present.
The byte reference will be 1o the section specified by the effective address, and incrementing a hyte
pointer will increment the RH of the first word with no carry out of bit 18.

1213

177 1

]

OF CODE

UPT <421

OLD PC BT

ey -427

EFFECYIVE ADR OF VLO

UPY 423

NEWPC IO BT

% 27

30 31

C.5.13 Stack Instructions (PUSH, PUSHJ, POP, POPJ, ADJSP) - The present format of the stack
pointer (half-word count, half-word address) is insufficient to hold a full address but is convenient

10 2002

when the stack is local and small. Therefore, in nonzero sections the stack instructions will recognize

Figure C-7

either of two forms of the stack pointer:

Local stack pointer - If the left half of the stack pointer is negative or 0 before incrementing
or decrementing, the right half will be taken as an address within the section specified by the
PC. Incrementing and decrementing the stack pointer will modify both halves of the pointer.
Any carry out of bit 18 is suppressed so that local stacks will not cross section boundaries.

Global stack pointer ~ If the left half of the stack pointer is positive and nonzero before
incrementing or decrementing, the entire pointer will be taken as a 30-bit stack address with
no count field. The pointer will be incremented and decremented as a single quantity. Stack
overflow and underflow detection is expected to be programmed by setting a restricted

WARNING
PUSHing on a local stack which has previously overflowed (i.e., 0.8 before PUSH) will result in storing
in section 1 ti.e., 1,,N+1).

LUUO Information Format

Hence. execution of an LUUO will cause the processor PC and flags 1o be stored. the op code. AC. and
effective address of the LUUO to be stored. and the processor to begin operation at the location
specified by the “new PC.” The processor flags will not be changed. In section 0. the LUUO mechanism will work as on the KL10-PA and so will invoke 8 separate LUUO handler. which must be in
section 0.

access on the pages at either end of the stack, since the absence of a count prevents an
explicit hardware check. Carries out of bit 18 are not suppressed. thus. a stack can cross
section boundaries. This format is expected to be used as the standard in extended sections.

Machine-independent subroutines can be written which run in section 0 and in nonzero sections on the
KLI0-PV. Only the code which initializes the stack pointer needs to know the section. The above two
formats are the same as the index register formats and behave in an analogous manner.

At l

WARNING

Toe use of LULOs by 8 programmer will probably

prevent him from interfaciag with another programmer's code which aiso wses LUUOs, ualess there is
prior agreement between the two programmers.

In exec mode. an LUUO in a nonzero section will do an MUUO. Monitors do not generally use
LUUOs.

C.5.1.8 MUUO (Op Codes 0, 40-77, All Undefined Op Codes) - Execution of an MUUO will cause
the UUO information 1o be stored in a 4-word block beginning at location 424 of the UPT (Figure C8).

Example of pushdown stack pointer before and after
INSTR.

PUSH
PUSH
PUSH

STACK POINTER AC
AFTER
BEFORE

-6.100
-1..105
32,.100

-5..101
0..106
32..10)

:stack in PC sect.
:overflow
sstack in sect. 32

C.5.1.4 LUUO (Op Codes 1-37) - It is desirable to be able 10 execute LUUOs in any section and
invoke common code. Therefore, when the PC is in a nonzero section, all LUUOs will trap to the same

tocation. as explained by the following description. Word 420 in the user process table (UPT) will

contain the address of a 4-word block for LUUQ information. The information is formatted as in

FLAGS

©°

OPCODE

[

EFFECTIVE ADR OF UUO

30 3

» 27

17 18

12 13

]

PROCESS CONTE XY WORD

(23]

Figure C-7.

10 3008

Figure C-8

EBOX/C-12

UUO Information Format

EBOX/C-13

The new PC word will be selected from a block of eight words at UPT +430 according to the context in
which the MUUO was executed just as on the KL10-PA. The new PC word wili be taken as a 30-bu
global address with no flags. The hardware ‘microcode will compute the proper settings of PCU and
PCP (previous context user and previous context public), and will ciear the rest of the processor flags.
In order to facilitate the use of AC operands with LUUOs and MUUOs, the following rules govern the

effective address word stored in the UUO block:

If bits 18-31 of the effective address of the UUOQ are zero {(a local address). but bits 6-12 are
nonzero, store | in the section field of word 2: store bits 18-35 in the RH of word 1.

Otherwise, store the full 30-bit effective address in word 2.

C.5.1.8 AOBJN - The two half-word format of the AOBJN - AOBIJP pointer is insufficient 1o specify
a giobal address. However, the format may be used for indexing as described ahove because the left
half is normally negative. it is therefore useful for scanning local 1ables (within the same section) and is
retained without modification. For scanning tables in an arbitrary section. the programmer will typically use an index containing a global address and will not employ AOBJN in this case,

C.5.1.9 JSA,JRA - These instructions use a format which does not allow the storing or specification
of a global address. Since they are also considered an obsolete and unrecommended method for subroutine calling. they will work the same as on the KL10-PA. They will work in nonzero sections. but
will be useful only for intra-section calls, since only an 18-bit PC is stored.

C.5.1.10 BLKI, BLKO - These instructions usc a pointer format which does not allow the specification of a global address. For diagnostic compatibility, the KL10 will support these instructions by
defining that the pointer address aiways refers to the PC section. See Subsection C.5.2 for BLK1 in Pl

This same set of rules also applies to XMOVEL

location.

C.5.1.6 BLT - The present format of BLT operands is insufficient to specify three full addresses:
therefore. a new instruction, XBLT, will be specified (see below). However, the existing BLT instruction is useful for intra-section data moves and is specified to work as follows:
1.

The source address is taken to be the left half of the contents of AC in the same section as the

C.8.1.11 XCT - The defauit section for the object instruction shall be the section of the effective
address of the XCT. However, PC storing instructions will store the PC section rather than the section
specified by the effective address of the XCT. This maintains compatibility with the KL10-PA (which
stores the PC+1). Local stack pointers will also assume the PC section rather than the section specified

effective address (which can specify any section).

by the effective address of the XCT.

The destination address is taken to be the right half of the contents of AC in the same section

Example of XCT of code in another section.

Data is moved until the destination address is equal 1o the effective address. Carries out of

as the effective address (which can specify any section).

In section 22:

bit I8 are suppressed so that the BLT stays in the same section by wrapping around.

Location 1000 in section 30:
MOVE

The source and destination sections are always the same, as specificd by E, which can be different from
the PC. References by BLT to addresses in which 18-31 are O will always be AC references.
C.5.1.7

EXTEND-STRING Operations - To support extended addressing, a 6-word block will be

used in all sections, consisting of two 3-AC blocks, as formatted in Figure C-9.

COUNT

AC »3

BYTE PYA FIRSTY PARY

AC 2

280 WORD (F EXTENDED PTR

AC )

COUNY

AC -8

SYTE PTA FIRSY PARY

AC 8

IND WORD IF EXTENDED

In section 22, location 100:

XCT

Location 1000 in section 30:
PUSH

EBOX/C-14

PSUBR

section 22, not 30. The PC stored on stack is 22,101, not 30,.1001.
Pl Handling

Initiation of a Pl cycle will cause the execution of an instruction in the EPT. For extended support, the
recommended instruction is X PCW (save then restore flags and program counter) defined beiow. This
instruction saves the current flags and 30-bit PC and establishes new flags and PC. The interrupt is
dismissed by execution of another new instruction, XJEN, (restore flags and program counier) which
restores the global PC and flags.

10 J00J

EXTEND-STRING Instruction Format

©(30.,1000]

transfers to subroutine SUBR in section 30, not 22. If C(P) is local, stack is assumed to be in

C5.2

Figure C-9

T.2000

Example of stack and PC storing under XCT.

AL+ 0

©[30,,1000}

will load T with contents of location 2000 in section 30, not section 22.

Byte pointers are in the one- or two-word format described above. If bit 12 of the pointer in AC+1
(AC+4) is 0. AC+2 (AC+5) is ignored.

XCT

When an instruction is being executed as a Pl instruction, the default section for computing the effective address is taken to the exec section O, cather than the actual PC section. Therefore. if a BLKI.
BLKO, or JSR is executed as a Pl instruction. it will work for programs (e.g.. diagnostics) not using

extended addressing.

EBOX:C-15

C.53

New Instructions

The new instructions which are required o properly handle extended addressing are described 1n the
following subsections.

C.53.1 XMOVEI - Move Extended Address (Op Code = SETMI) - This instruction moves its entire
effective address into the designated AC. It is generally used to find the effective address of a pointer
chain and make it available for indexing. It is the immediate mode instruction which has an operand
greater than 18 bits. Bits 0-5 are always zero. If the effective address specifies a hardware AC. the
effective address will be converted to the section-independent form. i.e., 1..AC. Thus, the result of an

This format is used by LUUOs, MUUOs, and additional instructions defined below. Unlike JRSTF,
no indirection is needed. Bits 13-17 must be zero because they are reserved for future hardware. Both
words are fetched before the flags take effect. XJRSTF works in all KL modes and sections.

Example of CPU independent flag code.

If AC is positive, the block addresses in AC+1 and AC+2 are the lowest addresses of each block and
identify the words which are transferred first. The transfer proceeds by incrementing addresses in
AC+1 and AC+2 after cach transfer and decrementing AC until it reaches zero.
If AC is negative. the block addresses in AC+1 and AC+2 are greater, by one. than the highest
addresses of each block. The transfer proceeds by decrementing the addresses in AC+1 and AC+2
before each transfer and incrementing AC until it reaches zero.

AC+1,AC
AC+2,AC

SETZM

:get section no.

SKIPN
JRSTF
XJRSTF

SECTNO
6FLGPC
FLGPC

;is this KL ext. sect.?
:no, restore flags and PC
:yes, restore flags and PC

The above code works on both

TSECTNO
17.ACBLK
12,17

:save for test
:restore all ACs
:including 17

CPUs, KL10-PA, KL10-PV, KL section 0, and KL extended sections.

C.53.4 XIJEN - Restore Flags and
Counter and Dismiss (JRSTS6,) -~ This privileged instruction performs all the functions of XJRSTF and in addition dismisses the current Pi level. It is intended
to be used in place of JEN GE under extended addressing.

XJEN works whenever 10 instructions work in exec section 0, traps in user section 0 (except user IOT
mode), and traps in user extended sections (except user IOT mode).
C.53.5 XPCW - Save thea Restore Flags and Program Cowmter (JRST 7,) - This privileged instruction is intended to be used in interrupt locations. It references a 4-word block at its effective address,
formatted as in Figure C-11.

The current flags and PC are stored in the first double word and new flags and PC are established from

Since XBLT is interruptable, results are indeterminate if AC, AC+1, or AC+2 is in either the source
or destination block. Otherwise, the effect of XBLT on ACs is equivalent to:
ADD
ADD

T.20

HLLZM
MOVSI
BLT

XMOVEI can be stored or moved to another section and still have the same address. This is analogous
to the effective address stored by MUUOs and LUUO:s. If this instruction is executed without indexing
or indirection, e.g.. XMOVEI 1,20, it will move the current section into the left half of the designated
AC (E must be 20 or greater). MOVXA is also used to test for section 0 {see Subsection C.5.5).

€532 XBLT - Extesded Block Transfer (EXTEND Op Code 020) - XBLT is a member of the
extended instruction set, used under extended addressing. XBLT traps as an MUUO in section 0. but
otherwise moves data from any virtual address 10 any other. The number of words transferred is
specified by AC, the address of the source block is given by AC+1, and the address of the destination
block is in AC+2. Both addresses are always global.

XMOV}

the second double word. Dismissing an interrupt initiated with XPCW would typically be done with
XJRSTF addressing the same block. The 4-word block must be in section 0. since the default section is
0 for instructions executed in an interrupt location. XPCW works in exec section O, traps in user
section 0 (except user IOTF mode). works in extended exec sections, and traps in extended user sections
texcept user IOT mode).

C.53.3 XJRSTF - Restore Flags and Program Counter (JRSTS,) - This instruction restores the flags
and PC double word from E and E+!. The double-word format is shown in Figure C-10.
00

06 08

17 18

17 13

OLD PC (I0-BTE!

NEW FLAGS®

IGNORED

05 08

OLD FLAGS!

NEW RC 120 BITSE

PrC

10 3004

Figure C-10

Flags and PC Double-Word Format

EBOX/C-16

Figure C-11

XPCW Information Format

EBOX/C-17

C.5.3.6 XSFM - Save Flags in Memory (JRST 14,) - This instruction saves the flags in biin 0-12 of

Table -2 Compatibility Summary (Cont)

in the same format as the flags in the flags and PC double word. XSFM works in exec section 0, trips

User &

Exec

User

Feature

sect=0

sect>0

isave AC

zis this KL Extended sect?

Zwordbytepointer

(use 2nd word if bit 12=1%)

ignored

yes

“here with flagsin LHofT

treference other sections?)

EXTEND-STRING

yes

AOBIN, AOBJP

-PA

yes

JSAIRA

-PA

yes

in user section 0 (except user FOT mode). and works in exec and user extended sections.
Example of CPU independent flag test code
MOVEM

TSAVEAC

XMOVEl

T.20

:get section 4. orO LH

PRI A

TLNN

T.l

(tables in current section?)

C.5.4 Compatibility Saummary

Table C-2 shows how each of the new features works in exec and user mode in section 0 and in

extended addressing sections. The criteria for compatibility are as follows in decreasing importance:
1.

User code which runs on the KL10-PA must run in the KL compatible section, section 0,

(18-bit PC only}

continues program.)

{current PC section)

BLKILBLKO

-PA

yes

It should be easy and natural to write subroutines following a standard which can run in
section 0 and in extended sections. The loader can take care of any differences so that a

)
XCT
{default section from E of XCT?)

-PA

yes

XMOVEI(LH)

section

XBLT

trap

yes

XJIRSTF

yes

trap

yes

trap

XPCW

trap

yes

trap

XSFM

trap

yes

rap

tray

0 only*®

yes

including saved core images. (Trap on bit 12 of byte pointers does not violate this. if monitor

single REL file works for all three cases.

Exec

Code in user section O can use new instructions except those added solely for extended

addressing. However, code cannot reference or transfer 1o other sections. except through

monitor calls.

treference any section?)
(transfer to any section?)

Table C-2 Compatibility Summary
Caer &
;

Exec

Feature

sect=0

Indexing

-PA®

XJEN
Exec

Caer

(transfer to any section?)

sect>0

(transfer to any section?)

new

new
new

Indirection
Hardware ACs use

-PA
-PA

new
new

PUSH.PUSHIJ,
etc.
h

-PA

yes

LUUO

-PA

MUUO

yes

BLT

-PA

yes

(Global if LH of AC greater than 0)
(extended PC)

(reference section specified by E?)

EBOX/C-18

flags?)
{read d flags?
JRSTF
(iransfer control?)
PC; setting

(transfer 1o any section including 07)

*.PA indicates user code 1 executed as on K1 10-PA CPU

** s¢ mstruction XJRSTF 1o get to any section.

EBOX/C-19

C.S.5 Testing for Section 0
The code to dictinguish section 0 from KL extended sections is:
XMOVEI
TLNN

C.5.6

T.20
TI17777

Example of XCTing shadow ACs
XCT

will execute the instruction in memory at 30..2, not AC2. This is desirable since 1ables of instructions

:PDP-6
shere if KL extended section

is casily done with XMOVE]L.

shere if section0 or KLKA, or

Old Instructions

are exevuted and this data should be able to be anywhere tn memory. just like any other kind of data.
However, an interpreter running in a separate section must check for the PC getting into the ACs. This

Example of subroutine calling from ACs

C€.5.6.1 JRSTF - Jump and Restore Flags - In nonzero sections, JRSTF will give an iflegal instruction
trap because JRSTF is usually used with an indirect word which contains PC flags in the left half.
These flags might mistakenly appear to be 8 global indirect word if bit 0=0.
C.5.62 JRSTX.E - This is the AC field. or JRST, if being used to encode new op codes which do not
need an AC field. Unused bit combinations will trap. The following AC bit combinations are defined.
existing exec and user mode.

Op Code
JRST

AC
10

Op Code
jump and restore int.

JRSTF

JEN

HALT

XSFM

PORTAL

illegal

XJRSTF

XPCW

PUSHJ
EXP

return

PSUBR
arglist

SUBR:

MOVE

AP.@(P)

:fetch memory 20,3

unless SUBR picked up the word following the PUSH):

AC
0

2
3

would not work correctly if the following straightforward code was performed:

The new op codes were selected because they have the halt bit on and so are least likely to be used in

@{30..2]

:get current section number
non-zero section?

XJEN1

SUBR:

illegal

XMOVEI
MOVE

APg(P)

APO(AP)

:get address 0,310 AP
getarglistfromAC3

However, this is a rarely used calling technique and calis to subroutines are not usually made from the
ACs.

illegal

ilicgal

illegal

C.5.7 Special Considerations for ACs
The hardware ACs appear as the first 20, locations of any section referenced with a local effective

address. Instruction fetches specified by the PC are always local, even if a transfer instruction to a

global address.

Example of jumping to shadow ACs [14]

JRST

@[30..2)

jumps to section 30, location 2. However, the PC fetch will come from AC2 (since PC fetch is always
Jocal). This should not be a problem since the loader will load code starting at 20 in each section, rather
than 0.

Example of JSR to shadow ACs
ISR

@[30..2)

stores the PC in memory in 30,2 and changes the PC to 30..3. The next instruction is feiched from

AC3, not memory. This should not be a problem since the loader will load code starting at 20 in cach
section, rather than 0.

EBOX/C-20

EBOX/C-21

SECTION 3

€6

MES26N A

€61

Ovenien

DETAIED

LOGIC DESCRIPTION OF MODULE DIFFERENCES

CLOCK MODLTY

one of two crystal contr

s an the FBos )
fed oscigators

11 illustrates the hasic

«lock module layout and distobution for the KL10 processor.

The clock module res:

margiming 1t also
Clock Diagnostic€
€62

conse
onteol

1410
one

I heee sectioms
Labeled ne 1 1w

4 selectable source which can cither be external or
llator for normal operation, the other for speed

the Clock Control. the EBox Clock Control, and the
i) and three (1), respectively in Figure 3-13. Figure 3-

Detailed Circuit Description

621 CROBAR and Clock Initialization (Refer to Figure C-12) -When the KL10 system is powered
up. the EBox clock control module must be
initialized to a known
state. In addition, the device controllers on the EBus must be initialized and a senes of MBox, EBox. SBus. and EBus clocks must be
generated for various initialization purposes First, the power controller logic asserts CROBAR for

approximately § seconds [All EBus signals are false (low) at this time.] CROBAR is passed to the
clock diagnostic control logic where it enables the initialization process. The CLK CROBAR signal is

used

directly 1o select the “normal” oscillator as the clock source to be used during the power up

initialization phase because this signal asserts MIX SEL 4
1.

EBus Reset (Figure C-13) - The CLK2 CROBAR signal enables the counter 1o subtract one

cach clock pulse. The initial state of the counter is undefined. During the CROBAR period
(approximately § seconds), the counter is decremented toward zero. When zero is reached, a

generated. If CLK2 CROBAR is

false at this time, the -1 function is disabled and

the counter is loaded with zeros. This removes CLK EBUS RESET. In practice, the counter
passes through zero many times until finally CROBAR is removed by the power controller
logic. Therefore, a series of EBus reset pulses are generated during the CROBAR period.

Initialization Clock Pulse Generation (Figure C-13) - CLK CROBAR L asserted is shifted

four places into the shi register. The asserted shift register output, ANDed with the signal
CLK RATE SELECTED (which has been asserted by this time), generates the CLK1

GATED H signal that becomes the source of the clocks generated via the clock control and

EBox clock control. (The 5.0 ns delay is inserted to ensure that the CLK GATED signal is
not sliced.) When CLK2 CROBAR is removed, four main
source clock pulses later, the 4-bit
shift register output goes false and disables the CLK GATED signal. This shift register also
serves to synchronize CROBAR by the CLK1 MAIN SOURCE clock input.

€622 EBox Clock Control (Figure C-14) - The EBox clock control provides a source of clocks for
the EBox modules together with an MBox sync point (CLK EBOX SYNC), which is always asserted
one MBox clock (CLK ODD) prior to the generation of the CLK EBOX CLOCK (Figure 3-20).
Depending upon the nature
of the EBox cycle (a period extending from the rising edge of one EBox
clock 1o the rising
edge of the next), the EBox clock pulses may be extended by some multiple of the
main source clock period (Figure C-15).

The functional structure of the EBox clock control consists of an MBox clock counter, clock phase
sync detector, EBox sync generator, and an EBox clock source. The CRAM time field (T00, TOI),
specifies the duration of the EBox cycle (Figure C-15).

EBOX/C-23

et
Auwavs

A
st

oRMAL

xra

conTROLLED

wore

cux cous eser

0-10aD

cuxachoman.

awr

sz emes ——fcun COMTER
ox

crock.

cuzcnonan
s —d
ot

mam

Soomct

xTaL

CONTROLLED.

GaTtoN

sounce

ous
b

stcecTion

ciock

AEGISTE

[aen

conraor | cw
wiTIAL STATE

veusmRee.

¥ CLR 2 CROBAR
15 FALSK &

CARRYOUT DIARLES THE

wwox

CRvETAL 1 50t

“ KLIOPA “NORMAL®
CRYSTAL IS 50 MHZ AND

Figure C-12

cix

Basic Source Selection
EBus Reset and Clock Initialization

EBOX /C-24

EBOX C-25

[
wwox

Jeu

|ooo

o aam

The clock phase sync detector compares the MBox clock covnter output with the CRAM time field

(loaded at EBox clock time) whenever CLK3 EBOX CLOCK EN L is false. If the counter output

«compares with the bit combination in the time field (T00, T0i;, CLK3 SYNC ENL is asserted and the

next MBox clock sets CLK3 EBOX SYNC L.

With CON MBOX WAIT true. -CLK EBOX CLK EN L is also true and CLK3 EBOX CLK EN Lis
false (Figure C-14). This enables the MBox clock counter to continue to be incremented. Similarly, the

cuxz

waox

clock
weox i) G

—an

cuock
fore

_cuasmcon:

[ ouren | SYNC

———
curt
Cunzmmox

oeTecron

Jour

detector s enabled, and when the counter output compares with the bit combinationin the time field
of theCRAM word, CLK3 SYNC EN L will be asserted and remain asserted until the MBox responds

180x

vne

Gin

CLK3 EBOX SYNC L will set. In other words, CLK3 EBOX SYNC L is asserted one MBox clock

With CLK3 SYNC EN L true when MBox response (CLK| RESP MBOX) is received (Figure C-14),

coox

clock. At the same time when EBOX CLK EN becomes true, CLK3 EBOX SRC EN H also becomes

coxent

S woTE

prior to where EBOX CLOCK is asserted.

EBOX CLOCK EN L becomes true and thereby resets MBox clock counter to 000 and disables the
detector. CLK3 SYNC ENL is removed, allowing CLK3 EBOX SYNCL to clear on the next MBox

svnc
cu

CLK3 (00X CLRTRT,

(CLK RESP MBOX)
or aborts the cycle. Thus, one MBOX CLK after CLK3 SYNC EN L is asserted,

tho svwc ¢

cur3cmox
sac v m

con mmox wAT

true; thus, when CLK3 EBOX SYNC L is cleared. CLK EBOX CLOCK (EBOX CLK) sets (Figure 323)

Cona
nese Maox

€623

cuocx
wox

wore

CLxa (80X CLx EN L

N -0 (FALSE)
SYNCS
LIE
€K
IMP

Figure C-14

cx 000

—8]

CINERATOR

— cux cox cuocx

EBox Clock Control Block Diagram

Error Detection - Figure 3-24 illustrates the logic that stops all clocks in the event of any of

the following
1.

A DRAM parity error occurs.

2.
3.

A CRAM parity error occurs,
A fast memory parity error occurs.

The timing shown is for a CRAM parity error. The CRAM register is clocked by CLK CRM; some-

time later, the parity network settles and asserts CRAM PAR 16. This indicates that the CRAM word
has dropped or picked up bits andis not correct. The signal -CRAM PAR 16, together with an enable

previously set by a diagnostic cycle (CLK CRAM PAR CHECK), enables the generation »f CLK
FRROR HOLD,

If it 1s desired 1o stop on parity errors, CLK ERROR STOP EN must have been set by the console. In

this case, on the next occurrence of CLK EBOX SOURCE EN. the CLK ODD gate will be latched
false, inhibiting all clocks and freezing the system

€624

Clock Control Logical and Skew Delays - Figure 3.25 illustrates the delays necessary to

assure that the proper timing relationship cxists between the actual MBox clocks. EBox clocks, and the
sampling of the CRAM time field. The lumped delay consists of fixed logic delays and gate and wire

delays. The output is CLOCK ODD and is used to clock a 10141 shift register. which has a nominal
propagation delay of 2.65 ns.

The output of the shift register feeds various gates and the various EBox boards receive their clocks
from these gates. Delay X
Figure C-15

EBox Cycles

The delays are

allows for lining up the outputs of the gates, “deskewing” the EBox clocks.

actually etch paths near the fingers on the board

and once the elay has been ascer-

tained, a permanent connection is made at the proper point. Figure 3-26 shows the EBox clock fanout;
Figure 3-27 shows the MBox clock fanout.

in order 1o compensate for the effect of the 10141 circuit propagation delay. a fixed 2.65 ns has been

inserted in the path between the LUMPED DLY and the MBox clocks. Connected in this path also is
DLY Y, which performs the same function as DLY X does for the EBox clocks.

EBOX/C-26

EBOX C-27

All EBox clocks and M Box clocks are lined up leaving the clock control module. In order to properly
synchronize the clock control module with the other moduies. these signals are passed out through the
ctch connectors on this module and then routed to all other modules through a set of equal fixed length
{equal time delay) coaxial cables.

Figure C-16 illustrates the basic timing for the clock module. Five basic cycles are presented
EBox cycle T=01,
EBox cycle T=1{0,
EBox cycle including a memory cycle T=00,
EBox cycle T=00,
.
EBox cycle including 8 memory cycle and page fault.

C.7

MODULE M8540, SHIFT MATRIX

The MB8540 module. shift matrix, replaces the M8510 module for the KL10-PV processor EBox. It
contains: shift counter decoding logic. shift matrix control, the shift matrix. and the AR and ARX
parity networks, as does the M8510. In addition, it contains logic to shift the index field for the global
indirect word and local indirect word and detection logic to detect an index register > 0 in the left half
or a 30-bit address (bits 6-17).

C.8

MODULE M8%41, CONTROL RAM ADDRESS

This module is used in the KL10-PV. Functionally it performs similarly to the M8511 module. except
that it contains a 16-word X 1}-bit pushdown stack, whereas the M8511 module contains a 4-word X
11-bit pushdown stack. The M8541 module includes a 6-bit decode field (a CALL bit is added) using
1K RAMs containing 2048 words, whereas the M8511 module contains a $-bit code dispatch field
using 256 RAMs, containing 1280 words. Also, the M8541 module’s control RAM address lines 7. 8,
and 10 (CRA2 ADR 07, 08, and 10} have additional and slightly different input conditions (refer to
drawing 8541-0-CRA2) which are:

CRO7: ARX00 OR -CON2 LONG EN

CRO8: ARX0! OR -CON2 LONG EN

CR10: MCLPC Section 0 or -VMA Local AC Address

in order to implement the additional microcode and extended addressing.
C.9 MODULE M8542, VIRTUAL MEMORY ADDRESS
(Refer 1o Figure C-17.) This module functionally performs the same as the M8523 module to generate
the virtual memory address to the E/MBox interface. 1t contains an 18-bit VMA adder. VMA AC
reference detection logic, a 24-bit VMA register, in contrast to the M8523 module’s 23-bit VMA
register. a 24-bit program counter register, (which contains an extra PC section 0 identifying bit), a 23bit VMA held register. and AR mixer (ARMM) logic bits 13-17. Section detection logic which stores
the previous section (which the M8523 module does not provide) is also added.
C.10 MODULE M8543, EBOX CONTROL NO. 1
This module performs the exact logic functions as the M8527 module, which it replaces. except for the

following logic change in order to implement extended addressing and stack instructions.

The CTL INH CRY ISL output input terms now include CRAM AD CRY L and MCL4 SHORT
STACK H in addition to the previous input conditions.
The M8543 module has also been revised to incorporate all rework and ECOs that were made to the
original M8527 module.

EBOX/C-28

CLK CLK

CLX MBOX CLK
ABCDEF

CLK EBOX SOURCE

am)

CLK EBOX SOURCE EN
CLK EBOX CLK EN

CLK CRM

BEAN

A { vrv,)

R
ey

CRAM TOO
CRAM TO1t

0
N

‘—
pnny

MCL MBOX WAIT

CLK RESP MBOX

MBOX RESP IN

INCR

vy, S

‘:

)

CLK SYNC EN | T

CLK SYNC HOLD

INCR

{

1
I

INCR

EBOX CLK

CLK EBOX SYNC

INCR

L. 4> 1] 7

RESET~0

| aa—

|
-

¥1

—

I
M
T

PAGE FAIL HOLD

CLK PAGE FAIL EN
CLK PAGE FAIL

‘

o !
1

vty

: I }

i ]

! —
;!1,

o |

by
I

INCR

r—
J

I¥

CLKODDABC,

CLK MBOX ABC

-ol

4 !

] E ! 1 |
14

ra E

P—L

[

T V3bl
¥
v
R

T
LT

Tt
Ll

a.a1.1

PFOLYD A

R
T
1

CLKPFDLYD B

CLK FORCE 1777

H
f

FORCE 1777

CLK SBR CALL

CLK 1777EN

CLK INSTR 1777

jo—

T = 01, —0f@e——
T = 10, ———§8— T = 00 .. MEMORY CYCLE ——=jo— T = 0D,

9 je- T = 00, MEMORY CYCLE. PAGE FAULT 990~1777—e

Figure C-16

Clock Control,

EBox Clock Control Timing

EBOX/C-29

1
1
1
]

{

Loag e

a0 vwa ety

1
moBnDMAZH

VMA HELD

]

AL PRCL CONTERT

s
M

TR
s

vua

—)D>—wn
[
_»

A0R BREAK
7

'
1

1
1

|
|

)

)
[}

VA TN

10-2978

Figure C-17

Module M8542

EBOX/C-31

C.11

MODULE M8544. MEMORY CONTROL.

The MES44 memory control {(MCL) module replaces the MX530 module in the KLI10-PV EBox. 1t
contains CRAM MEM ficld decoding. memory request enable logic. request type decoding.
MCLVMA READ, MCLVMA PULSE. MCLVMO WRITE. It also contains user and public enable
logic. as well as all the request type qualifiers. It contains bits 1-12 of the VMA held or PC mixers,
together with VMA control and selection logic (changed radically from the M&533 module in order to
provide extended addressing). and MBox cycle request logic.

This module no longer implements the SXCT instruction: however. it contains hardware to implement
the PXCT instruction in nonzero sections.
C.12

MODULE M8545, APR

Maodule M8545 replaces the M&539 module and contains the following additional logic to the M8539
module: a 128 X | RAM to store whether the index left halves are greater than 0: and an ALU which
enables the microcode to address AC plus any number for double word byte pointers for the STRING
instructions.

In the MES4S module, CRAM bits 00, 07, 08=1, and 6, are decoded to be APR EBOX SPARE and
APR EBOX CCA. respectively, as contrasted 10 the M8539 module which decodes these bits to be
APR EBOX CCA and APR EBOX SPARE, respectively.

C.13 MODULE M8548, 2K CONTROL RAM
The MBS48 module replaces the M8528 module in the model KL 10-PV processor.

Functionally, the M8548 and M8528 modules are similar. Each M8548 module contains 14 bits of the
control word (microinstruction} stored in the RAMs comtaining 2048 words. Each M %548 module
contains CRAM address gating and [4 bits of the CRAM output register (CRAM register).
Figure C-18 shows the CRAM physicat bit position layout. Figure C-19 shows the actual CRAM
microcode bit position correlation. Figure C-20 shows the M8548 module physical bit position derivation for the KLI0-PV EBox. Figure C-21 shows the CRAM bit/module layout for the KLI0-PV
kFBox.

Figures A-17 through A-23 show the microword bit position and field definition.
No logical relationship exists between the physical bits and respective microword bit names.

EBOX /C-33

MICHG WORD.

Ccram mvsicaL
ey

FOSITIONS
90 16

ATEH AD 13010,

DrsPaTCH KO 110 100

CRAM PHYSICAL

|oae
T

moout ADA 53 ADA

|41

wcho woRo
FOBTIONS 1631

Y
e
Wil
e B
Je
e

wcaon | schon | ia

Cuaw PHYSICAL
mrs e

| saham|

L Schontel7 wakn 3117 AR
i

SHL

samams

cHO woRD.
PosITIONS 1247

FITh

ElEREI
|

AoAs

aom 1

IR
B

wiv | oww | e

| e

MIM (0aD CONO LOAD COND ADm « *¥

aon B

Cuam pHvsicAL
wrsears

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anw

sz MU

T ko|

ADN | COND
gy | MU

cHO woRD.
POsITIONS 4863

s MY s MU s

[

wcHo

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OB TIONS
4 79

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anw | amw

T)
P

[
[
T
[ml.a
e | oem | o | e
[

Era

POBITIONS 8083

nrseres

=
prems

Figure C-18

CAO wORD

Chaw psicAL

CRAM Physical Bit Position Layout

Figure C-19

EBOX C-34

CRAM Microword Bit Position Layout

EBOX 'C-3§

1Y)
DA
SEL
ScA

11
- scavmsEL

)
5w

21
SEL A
40+ SCAD

37 SKIPCOND (3.
57

FMADR 12,

A
sone

rrom

cnomour
e o
22

2
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B
) SR

e zoin

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enneour

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= 12 cna - o0 @D

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12 cunn 2 0 @D

cnon our o4

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cunn

cnoamestrn 27

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cnonour mess n-21]

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@
a0 0oLt

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S howsi i
SEL 01
26ARXM

0
21+ A0 8L

- a0a 018

Vot

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- cnan
30-cnam - 3

om0

- 8
3= caam

22~ a0s0Ln

2n-a0secin

O
27+ ADASEL
3= ChAM - 2

- cham - o

- CrAM - 5
e cnam

0= Ao SEL
30+ Coam -

- cnam

< w40 416
HOWS

Figure C-20

KL10-PV EBox CRAM Module

Physical Bit Position Derivation

EBOX/C-37

7_ [=_u_u_ :

nl_:T

sLors2

EERET

u:____:

](ol

Geow

£80X
CONTROL

Loic

o
E£RROR

DETECTION
102978

Figure C-21

KL10-PV EBox CRAM Bit

Module Layout Chart

EBOX/C-39

INDEX
—

Abbreviations, B-i
AC, 1-14, 1-19, C-10, C-13, C-14. C-16, C-18,
C-20. C-21.C-28
Shadow, C-20, C-21
Special Considerations, C20
ACKNOWLEDGE, 2-69,2-173
AD Field, 2-100
ADA, 2107
ADB. 2-107
ADXA, 2-108
ADXB. 2-l108
ADD Instruction Example, A-14
Address
Break, 3-32, 3-35
Break INHIBIT, 3-38
Calculation, 2-31, 2-38
Generation, 2-63
Global, C-5-C-7. C-10. C-11, C-14, C-16,
C-18,
C-20
Local, C-5.C-6.C-14, C-20
Modification, 3-65
Path, 1-21, 2-88, 2.9
Physical Page, 2-88
Refill, 2-88
Translation,
1-44
Virtua! Classification, 2-92
ALU
Description, 2-100
Functions, 2-101
AOBIN, C-15.C-19
AOBJP. C-15.C9
APL. 1-55, 2-69
Word Format,
1-49
APR, 2-43,.C-28
AR Mixer Mixer, 2-114
Arithmetic Processor
Facility, 3-32
Status Register, 3-38
ARMM, 2-114
AR Selection, 2-109
ARX Field,
1-13, 2-111
A READ
Dispatch, 2-38, 2-1285, 2-126
Logic, 3-65

B
Basic Machine Modes. 2-70
BLKI, BLKO, C-15.C-19
BLT, C-i18
BR Field, 2-112
BRX Field, 2-112
Byte Instruction, C-11, C-12
Byte Pointer, C-12
C
Cache, 2-55
Clear (CCA), 288
Paging Data.
1-4)
Refill RAM Facility, 3-54
CCA, 2-88
Clock
Basic Rate Selection, 3-23, C-23, C-24
Basic Source Selection, C-23
Diagram, C-24
Control Block Diagram, C-26
Control Diagnostic, C-23
Control Logic, 3-30, C-23-C-28
Control Timing, C-29
EBox, C-23-C-28
Fanout, 3-31
Generator, C-2¢€
EBus, C-23,C-25
Initialization, 3-22, C-23, C-25
Main Source, C-1.C-3
MBox, C-23,C-27,C-28
Fanout, 3-31
Module (M8526-YA), C-23,C-28
Overview, 3-20
Codes
A Ficld, 1-14
COMPEA, 2-37.2-38

Control RAM Address Module (M8540), C-28
CRAM, -2, 1-13, i-18, 1-27, 2-1, 2-14, 3-29,
A-1, C-1,C-33
Address Inputs, 2-12
Addressing. 3-57
Dispatch Field, 3-62
Field Definitions, A-3
Parity Error, 2-10, C-27
Physical Bit Assignments, A-$, C-34, C-37,
C-39

EBOX/INDEX-]

Pushdown Stack,

EBox, 1-3
Clock, 2-13, 3.9, 3.24, C.23, C-26
Control No. 1 Module (M8543), C-28
Cycle, C-23,C-26
Data Fetch, 2-124
Data Paths, 1-59
Data Store Cycle. 2-14]
Execution Cycle Overview, 2-139
Frozen., 2-10
Instruction Set, 2-114
Main Loop, 29
Module Utilization
KLIO-PA, 3-1
KL10-PY, C-1-C-3

3-57

Time Field, C-23, C-26, C-27
CROBAR. 3-22,C-23
CRYO Generation, 3-19
I-1
CS.
CST. 141
Cycles
Basic Machine, 2-23
Begin MBox, 2-163
EBox Clock., C-23, C-26, C-28
EBox Data Store, 2-141
Execution, 2-137
Fech, 2-125
Finish Store, 2-49
Hardware, 2-§
Interrupt, 2-63
MBox. 2-37
Page Fail, 249
Processor, 2-1
Trap, 2-59

Priorities,

REQUEST IN, 2.31
Reset, 2-1
EBR. I-15, 2-88
EBus
Basic Operation, 2-182
Control, 1-47
ECL Acquisition, 2-183
Interface Control, 2-167
Interface Organization. 2-177
Requesting, 2-178, 2-191
Reset, 3-24, C-23. C-25
Signal Lines, 2-173
Effective Address
Calculation, 2-119, 2-120, C-3, C-§, C-10,
C-16, C-17
Manager.
2-18
EPT. 1-28, C-15
ERA Word, 3-46, 3-56
Error
CRAM Parity, 2-10. C-27
Detection, 3-27, C-27
DRAM Parity, 2-10, C-27
External, 343
1/0O Page Fail, 3-44

Data Fetch
EBox, 2-124
Manager, 2-88
REQUEST EN,

2-163
Data Path, 1-50, 2-92, 2-99
General Organization, 2-99
Mixer Seclection, 2-100
Data Store Manager, 2-21
Data Transfer Signals, 2-173
DEMAND, 2-69

Dispatch
A READ, 2-38, 2-125, 2-126
CRA Parity, 3-69
DRAM J, 1-14
IR,
|-13

NICOND, 1-2, 1-13, 1-14, 2-6, 3-12
Siate Diagram, 2-9

Table,

DRAM.

2-20

1-2, I-14, 2-14, 2-137, 3-10, A-1

Addressing and Selection,
Organization, 1-7
Parity Error, 2-10, C-27
Register Fields, 1-2
Word Format, A-23
DTE20, 2-67, 2-69

EA Calculation, A-{l
EA MOD, 1-13, 2-18

3-11

2-58

MBox,

143

MBox Address Register, 3-56
NXM Overview, 345
SBus, 3-39
STOP Enables. 2-14
EXEC Virtual, 2-196
Execution Cycle, 2-137
Executor, 2-21, 2-45
Extended Addressing. C-3, C-5, C-1S, C-17,
C-18
Extend String Operations, C-i4, C-19

EBOX/INDEX-2

F
Fast Memory,
1-14. 1-50
1-19
Address Field,
Addressed by VMA, 2.92
ADR Field, 2-112
Information Flow. 1-53
Parity Error, 2-10
Re- e 24123
Fetch Cycic, 2-125
1-13
Field,
ARMM, 2-114
I (Indirect). C-§
Microword, A-16
MQ. 2114
SC, 2-113
SCAD, 2-112
SCADA, 2-113
SCADB. 2-113
SH, 2114
SPEC, A-ll
VMA,

Hardware

Cycle Summary,
Page Table,

I 'structions,

C-5
C.5

Flags, 2-76, 2-89, C-12-C-14, C-17-C-19
Function
00, 2-195
01, 2-196
02, 2-196
03,
2-197
04,

05.
06,
07

2-197
2-197
2-198
2-198

Funv;tional Blocks, 1-6
G
General Interrupt Sequencing, 2-66
Global
Address, C-5-C-7, C-10, C-11, C-14, C-16,
C-18, C-20
Byte Pointer. C-11
Format, C-$-C-7
Indirection, C-9
Indirect Word, C-20
Indexing,

C-9

Stack Pointer,

Table,

C-8

C-11,C-12

H
Halt
Handler, 1-13, 2-23
Loop. 2-¢

2-160

Immediate Instructions, C-10, C-16
Indexing, 2-120, C-5-C-7, C-10, C-16, C-18
Negative, C-8, C-9
Index Register, C-5. C-6, C-9
Indirect Addressing, C-17, C-20
| (Indirect) Field, C-5
Indirection, 2-120, C-5-C-7, C-10, C-18
Inialization, C-23

2-114

X Address,
Y Address,

141

1-6

AC References, C-10
AOBIN, AOBJP, C-15,C-19
Basic Four Mode Type, 2-141
BLT. C-14,.C-18
BYTE, C-11,C-12
Complex, 2-12§
Immediate, 2-128, 2-141, C-10, C-16
JSA.JSR. C-15,C-19
New, C-3,C-11
XBLT, C-14,C-19
XMOVEL, C-16. C-19
Non-PC Change, 2-125
Non-Read PSE, 2-131
Not Requiring (E), 2-125
OoLD
JRSTF, C-20
JRSTFE, C-20
PC Change, 2-125
PC Storing, C-1}
PCXT, C-13
Read-PSE-Write, 2-137
Requiring (E), 2-131
Special Case in Non-Zero Sections
Byte, C-11,C-12

PC Storing (PUSHJ, JSP, JSR, POPJ),
C-11

Stack (PUSH. PUSHJ, POP, POPI),
C-12

STACK, C-12,C-21
STRING. C-28
SXCT, C-13
XBLT, C-14.C-19
XCT, C-19
XMOVEIL, C-14,C-19

instruction Set
Divisions, 2-117
Overview, 2-114

Interface Control,

EBOX/INDEX-3

2-158, 2-167

Interlocks,
Interrupts,

Dialogue,

Microcode. 1-41, 2-17, A-1, C-1, C-33
Example. A-11, A-14
Field Definitions. A-2, C-33. C-3§
PI and EBus Interface, 2-18%

2-178
1-6, 1-47, 2-63
2-67

General Sequencing, 2-66
Handling, 2-177
Instructions, 2-66
Priority Chain, 2-65
Scosing, 2-183
Simultaneous, 1-47
Testing For, 2-120
Introduction, 1-1
1;0
Basic Control, 2-178
Handler. 2-23
IR
AC Control, 3-10
DRAM Control, 3-§
Loading and Control,
Test Satisfied, 3-13

Sample Listing. A-I
Variable Definitions, A-2
Microinstruction,
1-54

Microprogram, 1-17. 2-9, A-l
Address Control, 2-11
Deferred, 2-14
Frozen, 2-10
Halt Loop. 2-6
Organization, 2-17
States, 2-1,2-6
Wait, 2-10
Microstack Operation,
Mnemonics, B-1
Mode

3-2, 3-9

Control Logic,

JRSTF, C-20
JRSTFE. C-21
JSA, JSR, C-18.C-19
K
C-l. C-14, C-15, C-19

KL10-PA EBox,

KLI10-PV EBox,

KL Paging.

C-1,C-3,C-32,C-33

C-3

L
Local
Addrest, C-5.C-6.C-14,C-20
Byte Pcmter, C-11
Format, C-§
indexing, C-8
Stack Pointer, C-11.C-12,C-15
Tables, C-8
Lines
1-1.2-173
CS,
DATA. 2-173
EBus Signal, 2-173
Function, 2-173
Priority Transfer, 2-174
Loading Flags. 2-76
Logic Descriptions, 3-1
LUUO, C-12,C-14,C-16,C-18
M
Memory Cycle Control, 2-167
Memory Control Module (M8544),
Memory Hook,

C-1

Memory References.
Memory Request,
MBox, 2-93

2-127, 2-133

1-24

[4]
Overview
Basic Machine Cycle, 2-24
Clock. 3-20
EBox Differences (KL10-PV),
Execution Cycle, 2-139
1-49
1/0 Instruction,

Program Counting. 2-93
Pushdown Stack, 3-57

Module Utilization
KL10-PA EBox. 3-3
KLIO-PV EBox. C-1.C-3
MOVE Instruction Example.

C-28

A-11

Field, 2-114
Selection. 2-11§
MUUO, 2-69, 2-72, 3-54, C-13, C-14, C-16.
C-17
N

New Instructions, C-3, C-11
XBLT, C-14.C-19
XMOVEL, C-16, C-19

1-27

2-81

Concealed Program,

Kernel Program, 2-8§
Programs by Supervisor,

User Public Program,

2-81
2-85

S
Saving Flags, 2-86
SBus Error. 3-39
SC Field, 2-113
SCAD Field, 2-112
SCADA Field, 2-113
SCADB Ficld, 2-113
Section Detection Logic. C-28
Section Pointer,
1-28
Sctup Prefetch, 2-167
SH Field, 2-114
Shift Matrix Module (M8540), C-28
Skew Delays, 3-30
SPEC Ficld, A-1l
Special Case Instructions
in Non-Zero Sections, C-11 C-12
SPT Index, 1-31, 141

Page Fault, 2-5§
Handler, 2-21
Overview, 1-27
Page Mapping. 1-30

Page Pointers,
1-28
Immediate,
1-28, 1-31
Indirect,
1-24, 1-31
Shared. 1-24, 1.3t
Page Table,
1-25, 1-2R, 2-63
Paging
Hardware Support,
141
KI.
1-25, 1-26. 143
KL,
1-28.1-29, 143, C-3
Path,
1-30

Stack Instructions (PUSH, PUSHJ. POP, POPJ,

C-3.C-5, C-6. C-10, C-21

Global,

3-53

.20

Page Fail
Cycle. 249
Handling, 2-5§
Word Adjusting, 2-S8
PAGE FAIL HOLD, 1-27.2-76

PC.

Timing.

Restoring

2-141

2-72

Cycles, 2-)
identification,

Quadword,

C-1

Page Fault,
1.27
Pl Dialogue,
1-48

Initialization. 2-76
Memory, 2-157
SELF, 2-187
Structure, 2-71
Transfer, 2-73
User Concealed, 2-86
User 10T, C-17
User Public, 2-60, 2-76, 2-79
Module
APR (M8545), C-33
Control RAM Address (M8541) C-28
Memory Control (M8544), C-33
M8540, C-28
M8511, C-28
M8527, C-28
Mgs28, C-33
M8530, C-33
M8539, C.-33
Shift Matrix (M8540), C-28

FBOX/INDEX-4

Processor

Instruction Set. 2-114
Interrupt Dialogue, 2-68

Vertical Memory Address (M8542),
2K Control RAM (M8548), C-33

C-33

NICOND.
-3, 1-13. 1-14, 2-6, 2-14, 2-15.
3-12. A-1H
Nonexistent Memory, 3-43

C-11

Loading. 2-97, C-11
Loading or Inhibit, 2-98
Loop, 297
String Instructions (PUSHIJ, JSP,JSR, POPJ
- non Zero sections), C-11
PCXT Instruction, C-33
1-55
Pl,
1-47
Control,
Cycle. C-15
Handler, 2-17. 2-21, 2-120, 2-183, C-15
Timing, 2-193
Pointer Interpretation,
1-34
Power Fail, 3-44
Power Up Timing., 3-26
Priority Transfer Lines, 2-174
Process Table References, 2-59

AQJSP). C-12,C-28
Stack Pointer, C-12
Startup/Stop Interface. 2-18
String Instruction, C-28
SWEEP. 347
SWEEP DONE, 347
SXCT Instruction, C-33
T
Timing

Clock Control, 3-33, C-23-C-29
Power Up, 3-26, C-23
TCI10 Byte Pointer Fetch, 2-198
Transfer., 2-69, 2-173

Translator, 1-5
Trap
Cycle, 2-59

Handling,

FBOX'INDEX-S

2-59

X Address Field, C-§
XBLT. C-14,C-16,C-19
XCT. C-15.C-19.C-21
XCTGO., 2-M
XCTW, 2-195
XJEN, C-15,C-17.C-19
XJRSTF, C-17,C-19
XMOVEL C-14, C-19. C-21
XPCW, C-15.C-17,C-19
XSKFM, C-18.C-19

UBR, 1-25, 2-88
UPT. 1-28,C-12, C-13
User 10T Mode, C-17
v

Violation, 2-81
Virtual Address, 1-2§
Adder. 2-88
Classification. 2-92
Effective, 1-14
Space Configuration, 2-75
Virtual Memory Address Module,
VMA, 1-21. 1-26, 293, C-3, C-31
Control,
1-43, C-28
Field, 2-114
Register, 2-93, C-28

C-28
Y

Y Address Field.

C-§

Wait,

2-12

MBox,

2-13,C-27

Word Request,

2-31

0-9
2K Control RAM Module {(M8541),

EBOX/INDEX-6

C.33