This document is a technical manual titled "EBOX INSTRUCTION EXECUTION UNIT UNIT DESCRIPTION" (EK-EBOX-UD-006) for the Digital Equipment Corporation (DEC) KL10 system. It provides a detailed description of the EBox, which functions as the Instruction Execution Unit (IEU) of the KL10 CPU. The manual covers the architecture, functionality, and low-level logic implementation of the EBox, including updates for the KL10-PV EBox model (5th Edition, May 1980).
The document is organized into three main sections and several appendices:
- Overview: Introduces the EBox's role in the KL10 system, its interfaces with other components like the MBox (memory interface), DTE (console interface), and EBus (I/O bus). It outlines the EBox's core functional blocks, including its data paths (Arithmetic Register, Adder, Shift Matrix), address paths (Program Counter, Virtual Memory Address register), fast memory, instruction register, and various control elements managed by microcode stored in Dispatch RAM (DRAM) and Control RAM (CRAM).
- Functional Description: Explains how the EBox executes instructions, manages memory operations (reads, writes, paging), handles I/O, interrupts, and traps. It details the various processor cycles (instruction fetch, address calculation, data fetch, execution, data store), microprogram states (running, halt loop, wait, frozen, deferred), and the mechanisms for handling page faults and priority interrupts.
- Logic Descriptions: Provides a detailed technical breakdown of each hardware module comprising the EBox. This section describes specific modules (e.g., M8532 Priority Interrupt Control, M8526 Clock, M8539 Arithmetic Processor Status, M8540 Shift Matrix) and their associated logic, illustrating how these components work together to implement the EBox's functions.
- Appendices:
- Understanding the Microcode: Explains the structure and interpretation of the EBox's microcode, detailing the fields and values within the DRAM and CRAM.
- Abbreviations and Mnemonics: A glossary of terms used throughout the manual.
- KL10-PV EBOX Differences: Highlights the enhancements and changes in the KL10-PV EBox compared to the earlier KL10-PA model, such as a higher clock rate (30 MHz), extended virtual addressing capabilities (32 sections of 256K words), and increased CRAM microinstruction storage (2048 words).
In summary, the document is a comprehensive engineering reference for anyone needing to understand the detailed internal workings, instruction execution logic, memory management, and control mechanisms of the DEC KL10 EBox, particularly with emphasis on the microcode and hardware specifics.