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MDL-A-1D-45-00D

2000

146 pages

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Document:	PDP-1D-45 Master Drawing List
Order Number:	MDL-A-1D-45
Revision:	00D
Pages:	146
Original Filename:	PDP-1D-45_engrDrws.pdf

OCR Text

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CODE

EQUIPMENT

CCRPORATION

MAYNARD, MASSACHUSETTS

DWG. NO.

BS | D-1D=45-2
|BS | D-1D-45-3
BS

| D-1D-45-4

BS | D-1D-45-5
BS | D-1D-45-6
BS

[NO. OF

REV.

LET.

lshEets

TITLE

B | 1
1

|LCH & DCH-IDA & IDC CONTROL
| MEM. EXTENSION CONT, TYPE 15A

| MEM.

| SH/RO LOGIC,

RENAME

1 | RESTRICT MODE & MEMORY PROTECTION LOGIC

| D-1D-45-7

BS | D-1D-45-8

MASTER DRAWING LIST

| D-1D-45-9

PROGRAM FLAG & RING MODE

| SBS TYPE 20 CONTROL

ACCUMULATOR REG.

| IN-OUT

INPUT MIXER

BS | D-1D-45-10

| IN-OUT MIXEK OPTION

BS | D-1D-45-11

| TRAP BUFFER

| D-1D-45-12

| STANDARD IN-OUT TRANSFER CONTROL

| D-1D-45-13

| OPTIONAL IOT CONTROL

BS | D-1D-45-15

| SKIP,SWAP & MID LOGIC SH/RO PULSE GEN INST,
BK_LOGIC

| D-1D-45-16

| D-1D-45-18

| ACCUMULATOR CONTROL

| D-1D-45-32

| INSTRUCTION REGISTER & DECODING

D=1D-45-33

MA,_MB, IO & PC TRANSFER LOGIC

| D-1D-45-51

| PROGRAM COUNTER

| D-1D-45-52

|MEMORY ADDRESS REGISTER

| D-1D-45-53

| MEMORY BUFFER REGISTER

| D-1D-45-54

| I0 REGISTER

| SBS TYPE 20 PRIORITY CHAIN

| CcLOCK

| AUTOMATIC MUL/DIV

BS | D-1D-45-55
BS_|

D-1D-45-56

BS | D-1D-45-57

| GENERAL CONTROL

D=1D-45-61

| D-1D-45-62

| PUNCH CONTROL

| D-1D-45-63

| TYPEWRITER CONTROL

| D-1D-45-64

| D-1D-45-79

| OPERATOR CONTROL PANEL

| D-1D-45-82

| SPECIAL MICRO PROGRAMMED

e S

WD | D=1D=45-22

D-1D-45-25

CONTROL

MEMORY BUS

WD | D-1D-45-21

WD |

READER

& TIMING

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INTERFACE

CLTT

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MYgA.

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1B-PC FF,

L,."»-

IOT&ICT COMMAND

1C-AC CONTROL

| 1p-4&55 pc,SH/RO-1E-PF,SH/LOGIC-1F-IR
BREAK

WD | D=1D-45-30

€

| 1

WD | D-1D-45-26

REV.

ECO

360

ENG

321

365

367

DATE

| 1nL-I.CH
& DCH CONTROL
| 2y-27Z MEM,

EXT.,

TYPE 15A RENAMG.&PROT.LOGI

MADE BY 8/31/64 | CHECKER ’7#’*7% ENG

£ P __Nh2/17/64] P. Daigneault %‘ffiffiim,_ P

[F,P.&B.M.4/23/65]

TITLE

w.,M, | 6/3/65
W.M.

|7/19/65f

PDP-1D-45

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DWG. NO.

A-1D-45

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CODE

EQUIPMENT
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WD | D-1D-45-24
WD | D~1D=-45-46
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MASTER DRAWING LIST

A
A

TITLE

‘4

1 | 2A-AC SHIFT-2B-AC FF-2C-AC LOGIC
l | 2D~-MB FF-2E MBG,
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WD | D-1D-45-47

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wp_|

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WD | D-1D=-45-31

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33,

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WD | D-1D-45-28

3L, IN-OUT MIXER OPTION

WD | D-1D-45-2¢

| TAPER PIN

PANELS

DT IONAL

EQUIPMENT

WD | D-1D-45-49

R1A,R1B,R1C~-BREAK SYSTEM PRIORITY CHAIN
TYPE 20

WD | D-1D-45-50

D-1D-45-65

WD | D-1D-45-81

WD | C-21009

WD | D-1D-45-83

|
FD

| D~1D-45-17

| R1D BREAK SYSTEM CONTROL TYPE

]11A-11B-11C READER PUNCH & TELETYPECONTBQ*
| SCR DRIVER 823-RACK 1llF
|

SWITCH PIATE

| SPECIAL MICRO PROGRAMMED IOT&IOT COMMAND

|
A

WIRING

| CYCLE ZERO & DEFER CYCLE

| D-1D<45-19

| CYCLE ONE FLGW DIAGRAM:

FD | D=1D=45-23

| SPECIAL CYCLES

CD | D-1D-45-14

| CABLE DIAGRAM

| c-1Dp-45-14

| CABLE DIAGRAM

| A-1D-45-35

| INTERFACE BETWEEN 630-3 &

CL| A-1D-45-36

12 | IM 0-17 IN

| A=1D-45-37

| DISPLAY 30A

CL | A-1D-45-38

| CLOCK IOM_

CL | A-1D-45-39

| PDP-1D-45 TO 23

CL | A-1D-45-40

| sBS

CL.

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CL | A-1D-45-44

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| A-1D-45-45

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CLL

| A-1D-45-58

| TA LINES

cI.

| A-1D-=-45-59

| pC

CL | A-1D-45-60

| MSC

REV.

ECO

ENG
S

DATE

8BS

PDP-1D-45

PLUG 5

LOGIC

INDICATORS

ENG

MADE BY 8/31/64 | CHECKER
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TITLE

PDP-1D-45

FOR

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CL| A-1D~45-66
CL | A-1D-45-67

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READER INTO READER LOGIC

CL | A-1D~-45-72
CL| A-1D-45-73

MBD IOT

4113 INVERTERS

CL| A-1D-45-74
CL | A-1D-45-75
CL

| A-1D-45-77

| A-21810

| A-21413

| A-21416

TYPEWRITER INTO TYPEWRITER LOGIC
PDP-1D

SOCKET WIRING

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TYPE

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| A-20059-12

| A-20059-13

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~ SPECIAL MICRO PROGRAMMED IOT&IOT COMMAND
EXPLANATORY NOTES FOR CYCLE DIAGRAMS

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| A-20062

| 1D-1B=1F

| A~20063

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TYPE

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| A-20307

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CL | A-20040
CL

_FOR_SBS

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20 PDP-1

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I

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®ERMINATORS FROM NAC & MEMORY LITES

NAC & MEMBRY LITES

CL | A-21417
CI.

4| DIODES FOR PDP-1D-45

CONTROL SW'D

A-~1D-45-71

| A-1D~-45-76

TITLE

PF_INDICATORS SENSE SW. SINGLE INSTRUCTION]
SINGLE STEP

CL | A-1D-45-70

|seets

_PPBP-1D TERMINATIONS
IR INDICATORS

CL | A<1D-45-68

MASTER DRAWING LIST

REV. |[NO.
OF

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D-8-2-81

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D-8-1-B6

D-8-1-87

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D-8-1-B4

0-8-1-85

D-g-1-B5

D-8-1-Bb

D-8-1-B7

D-3-1-68

D-8-2-81

D=§-2-B2

D-8-2-83

D-g-z-84 | D-8-2-B5

D-8-2-85

D-8-2:86

D-8-2-07

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D-8-2-88

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D-8-1-87

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D-8-1-88

D-8-2-B2

D-8.2-B3

D-8-2-83

0-8-284 | D-8-2B5

D-8-2-86

D-8-2-B6

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D-8-1-C7

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36 | anp
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mriBav

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142 |anp

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W/RED (R) - R1D3W

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MBD A

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MBD]'D

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LOCATION, LENGTH, ROUTE

JACK

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NAME

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//////////////

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120

W/ORN (O) | 3mo3an-r

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W/YEL (Y) | oND

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DRAWN

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10/7,/64

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NAME

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axp

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27 |EpC 3

W/BLK (X) |

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W/ORN (0) | 15239

4 | sc-4

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1 of

- 8L=SP~JT-V-S

Pg.

FLOW DIAGRAMS

(D-1D=-0-2, D-1D-0-3)

These drawings

show a chronologlcal

flew of PDP-1

from state to

state. Time runs from top to bottom of the drawings with a non-linear
scale.
The true time scale is indicated at the right edge of the cycle
zero drawing.
All events (changes in the state of the machine) which
may be initiated by a particular time pulse, are enclosed by horizontal
lines which include that time pulse number at the left of the drawings.
Because of the built-in delay of the flip-flops, the state does not
change until 0.1 usec after the start of the initiating pulse.
If more
than one event is conditioned for a given time pulse, these events occur
simultaneously, even though one event may bde drawn above another.
Each instruction the machine performs starts with a cycle-zero.
This
1is the memory cycle which brings the instruction from that memory address

contained in the Program Counter.
Certain instructions { jmp,jsp,opr,shift,
ekip,law,iot & spe) are completed in this memory cycle.
Shift may overlap
the next cycle-zero {(or break cycle ome) vubt vhis is of no interest
programmer unless he 1s operating the machine "single step".

All

two

cycle instructions

proceed

from”cycle»zero

the

to cycle-one unless

a deferred (indirect) address is called for. In the later case, one or more
defer cycles occur between cycle-zero & cyole-one.
Jmp & jsp may also include defer cycles.,
-

The instruction Execute (xct)

The one cycle instrnctions,

is changed in the early part of its oycle-

one to cycle-zero of the instruction to be executed.
Thus Execute may take
two or three cycles depending upon the instruction executed.
Both the Execute
instruction and the instruction executed may include defer cycles,

S=A=1D=
-

At the completion of each instruction, a sequence break may occur.
break consists of break cycle one, two & three.

This

BL-SH ~QT=V*S

Accumulator

Break cycle counter

BREAK
CODER

A network whose output i= four times the number of the
sequence which has priority.

carry

The second step of a two sfep adad

eye

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af 1

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df 2

a ff which indicates a second defer cycle is to be perforfied

dis shift-a special shift left at Ac & 10 AC;—» AC
( see notation)

11ip-flop

In Out Register

ioh

a ff indicating an in out halt is in progress

AC—C—s IO,

Imstruction Register (5 bits)

Memory Address Register

Memory inhibit ff

‘MBVHM-’jfiemory‘Buffer’Register
Mr

~ Memory read ff

Memory write ff

pad

The first step of a two step add (xor of MB & AC)

Program Counter

run

a ff which connects time pulse 10 to TP zero

oBS

Sequence Break System

Sh/Ro

Perform a shift or rotate step

Mus Shift-Shift right of AC & I0. ACsz# AC Zfi»«Ac
B

10, 4ropped
|

3 of 3

NOTATION:

~—

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_+1 —

PC——
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complement

the AC

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put the

zeros

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AC——fl——-'. MB

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put the ones of MB bits 6 thru 17 to AC bits 6 - 17

'.,3-AC'

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EQUIPMENT

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MAYNARD, MASSACHUSETTS

GENERAL RIBBON CABLE LIST
TITLE
SPECIAL MICRO PROGRAMMED IOT
& IOT COMMAND

AddV

"003

CHECKED

'ON

Maureen Mariano 7/21/65

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(W)

10:{4
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| £9%-91 80 Qlfif |

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REMARKS

REV.LTR.

DWG NO
A-1D-45-84

SHEET

CgBE

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[ LocATION, LENGTH, ROUTE

MALE

FEMALE

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| NAME

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GENERAL RIBBON CABLE LIST

Maureen Mariano 7/ 21/65
EQ U IPME NT
CORPORATION

TITLE

SPECIAL MICRO PROGRAMMED
IOT & IOT COMMAND

‘'ON "003

417

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MAYNARD, MASSACKHUSETTS

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" REV.

Lir. | ECO. NO.|

orig.|

362

DATE | ENG.

l72268

mln
191

d| |

GENERAL WIRING SHEET

Be=rs

EQUIPMENT
CORPORATION

—_—

SPECIAL MICRO PROGRAMED
IOT & IOT COMMAND

MAYNARD, MASSACHUSETTS

DRAWN

M. Mariano 7/21/65

4 CHECKED
G

PROD.

REV.

CODE |DRWG. NO.
CL

SHEET 23

ADIST.

A-1D-45-84

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