PDP-1D-45 Master Drawing List

This document is a "Master Drawing List" from Digital Equipment Corporation for the PDP-1D-45. It categorizes and lists various drawings by code (BS, WD, FD, CD, CL, S, WL, MDL, UML), drawing number, revision letter, number of sheets, and title.

The list covers a wide range of components and functionalities for the PDP-1D-45 computer, including:

• Control and Logic: LCH & DCH-IDA & IDC control, memory extension, restrict mode & memory protection, SH/RO logic, SBS type 20 control, general control & timing, accumulator control, instruction register & decoding, MA, MB, IO & PC transfer logic, program counter, memory address register, memory buffer register, IO register, clock, automatic multiply/divide, special micro programmed IOT&IOT command, cycle zero & defer cycle, cycle one flow diagram, special cycles & LCH & DCH cycles, break system priority chain, and break system control.
• Hardware Components: Racks, taper pin panels, cable diagrams, diodes, terminations, inverters, and series resistors.
• Input/Output Devices: Reader, punch, typewriter, operator control panel, in-out input mixer, trap buffer, standard in-out transfer control, optional IOT control, reader punch & teletype control, and SCR driver.
• Registers and Indicators: Accumulator register, IO register, MA.EMA indicators, PC indicators, MSC indicators, IR indicators, PF indicators, control switches, sequence break indicators, IO buffers, RDR buffers, TW lines, AC indicators, IO indicators, RDR indicators, PUN & TYPE indicators, and IR/IO registers.
• Memory and Processors: Core memory processor, memory rename, and utilization module locations.

The list also includes revision history (ECO, Engineer, Date) and indicates that the document is part of a larger set of drawings. The appended pages provide actual circuit diagrams and utilization module location maps for some of the listed items, showing detailed logic gates, signal paths, and component interconnections.