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PX-TCMEM-32

May 1967

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Document:	EOP Class Instructions
Order Number:	PX-TCMEM-32
Revision:	0
Pages:	25
Original Filename:	32.pdf

OCR Text

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and
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Dig

ita

rotrhgoriren
e

-e

PDP-X Technical Memorandum %

Title:

EOP

Author:

H, Burkhardt

Index Keys:

Double Precision

Class

Instructions

Floating-Point
Instruction

Software

Set

Specifications

Distribution

ATTE A

Keys:

A,B,C,D

Obsolete:

None

Revigion:.

None

Date:

December 6, 1967

‘

?r used in
w'-vo:e‘ors ir?
:

manufact

!p';?; 22

with

et vt

tis et

]

Introduction

PDP-X

architecture includes a class ofinstructions, the
Extended OPeration codes, that may either cause a program
trap

or may be

executed directly

the

processor

hardware,

class of instructions may ke divide
into three
d
depending upon their function:

This

sub-classes.
'

User communication with the IO monitor or supervisor

2.
~

User communication with himself.
(405<Dp1<{100,)
‘

Arithmetic or logical operations,

processor

functions,

(100g<<D1<400g)

etc,

special multi-

- ECP's
in the first sub-class will be defined by the software
‘'system.,

the

User

second

tem).
ware

programs will

sulk-class

(for

and

define

the functions in
Fortran Operating Sys-

the

The third sub-class will be defined by specific hard-

implementation

PDP-X/II

has

by universally

Precision

operations.

implement

accepted

conventions,

implemented EOP'as
s described in -PDP-X

Technical Memorandum #29,
class of EOP instructions,

use

example,

these

This

document will

i.e.,
some

operations

define a further
floating-point
and double-

the

later date,

in hardware,

but

may

for

possible
.

the

present,

these operations will be performed by resident softwar
e.
From
the user's point of view, there is essentially
no difference
except that:

The floating~point instructions will take
performed by

execute when

software, -

longer to
-

The software to execute the floating-point operations
requires

that

space

allocated

some

portion

for

their

the

available

memory

residence.

~ .Commonly used functions such as floating-p
add
oint
will be
defined

as EOP

class

instructions

since:

They may be

The

calling

sequences

for

the EOP

instruction),

assembled with the

normal

are concise

assembler,

(i.e.,

2 words

The addition of hardware to execute these instructions will
existing

not

necessitate

software.

the

alteration
-

of any

Double-Precision Operations

. Double-prrecision instructions operate upon signed (2's

complement) double-precision integers (programming conventions allow these quantities to be interpreted as
signed binary fractions) as described in PDP-X Technical
Memorarndum #29, section 2,2.1.

...

‘-Double~§recision quantities are addressed by the addres
of
s
the high-order word (which .must ke.even).
If

a double-precision quantity is not even,

~error will

occur

~will
e .set.
EOP

class

to be

and

All

bit

the

the addres
of.
s

an address exception

Program Status

double-Word.
.
instructio
are long ns
form . field indicates the operation.

double-precision

instructions,

The D1

performed,

- - -

Most dbuble—precision operations are between one operand in-

"~ the accumulators
located
by the

(AC-fie
of ld
the instructioh}!
and one operand
effective address (in.the accurulators or in

fixgmain_stonage).'“The“AG—fieidwofwsuch.instructions(must be even
2

or- an ‘address

exception

err
willor
occur

‘gram Status double-Word will be
When referring

- tive double-word"
effective

address,

mnem

_120"

-DLDA

bit

set,

double-precision

will

and

operations,

imply the double-word

the

the Pro-

term

"effec-—

located
by the

...

Definition

Doukle-precision LoaDAccumulator.,
The
double-word accumulator specified by the

AC-field

of the instruction (must be even)
loaded with the effective doukle-word,
The condition code bits remain unchanged.

o121

122

... DSTA

DADD

Double-precision
STore Accurulator,
The
double-word accumulator specified by the
AC-field of the instruction (must be =ven)
replaces the effective double-word. . The
condition code bits remain unchanged.

Double-precision ADD.,
. The sum of the doutleword accumulator specified by the AC-fiel
-d
of the instruction (must ke even) and the
- effective doukle-word replaces the doulkleword accumulator.
The addition is carried
out

ment

following

the

rules

two's

comple-

arithmetic.

condition

code

bit

set

bit

wise

carry out
cleared other- ..

Definition

mnem

D1 -

122 .(cont.)

-1 is set if negative result,

cleared otherwise

is set if non-zero result, cleared otherwise

The arithmetic error bit (2)
"set if the

of the PSW is

sign of the result does not agree

- .
with the signs of the operands (add overflow).

123

'DSUB

Double-precision SUBtract.
The effective
double-word is subtracted from the doubleword accumulator.
The result replaces the
- double-word accumulator specified
by .the -

AC-field of the

instruction

(must be even).

The subtraction
is carried out following
the rules of two's complement arithmetic,

‘

condition code bit O is set if carry out of_
bit O, cleared otherwise

l is set if negative re-

sult, cleared otherwise

S
'

)

set if non-zero result, cleared otherwise

The arithmetic error bit (2)
be set by this instruction.

of the PSW may.

mnem

Definition

General double-precision memory modification

instruction:

theAC

bits specify a

particular

operation.

is changed

only by the two rotate

tions @C

= 4,5).

-Condition

bit

instruc-

Condition code bits 1 and.

2 are

set as- follows for

tions:

.....

code

all modify instruc:

set

negative

cleared
2:

set

result,- -

otherwise

if non-zero-result,
---=

- cleared

otherwise

AC Operation
T

.DTST

)

Double-precision TeST,

‘

condition

code

bits

operation

but

and-2-are set to

reflect" the state-of the effective double~
word,

DCOM

Double~precision

effective

. DNC
'

a bit-by-kit

the

complemented

basis,

the

effective

double-word,

Double-precision NEGate, the effective
double-word

negated

then incremented).

- ‘DRR

2= Double-precision iliCrement, one is.added
to

DNEG

logical COMplenment,

doulkle-word

(complemented

May cause arithmetic erroz

Double-precision- Right Rotatg

the ef-

fective doudble-word and condition code
bit
O are rotated together as a 33-bit
register

one

place

-condition code bit
of the mflmory word
bit

-~ DIR

the

right,

O from bit 31 and bit O
from condition code
'

Double~precision Left Rotate,
tive

double~word

are

rotated left

and

the effec-

condition

together

loading condition

code bit 0O 33-bit

code

bit

from kit

of
bit

DCLR

0 of the memory word and bit 31
the memory word from condition code

Double~precision ClLeaR,

operation.

double-word

cleared.

the

effective

125

mnem -

Definition

DCMP

Double-precision ColPare,

the double-word

accumulator and the effective double-word
are algebraically compared.
-Neither the
accumialator nor the effective double-word

- are changed, but condition code bit 1 and
2

e :

are

set according:
to the result.

condition code bit

)

0 remains unchanged
1l

set

if:

accumulator
< effective doubleword

if;

cleared
San

accumulator”,
ef-

fective double-

word

set

if:

accumulator = effective doubleword
|
cleared

if:

accumulator = ~ffective

doultle-

word

126

DMUL

- Double-precision MULtiply,

the

effective

double-word is algebraically multiplied
by
the low-order double-word of the quadrupleword specified byaC, IfAC is divisibkle by

four,

the quadruple-word product replaces

the quadruple-word at AC and
is properly
signed,
If the specified accumulator (R)

.
-

is not divisible by four, the high~-aorder
double-word of the product is discarded.

The multiplier

as
-

signed

and

multiplicand are-treated-

quantities,

remain unchanged.

May

The

condition

cause

codes

arithmetic. error..

Example:

DMUL

The

300

double-word

located

locations

is multiplied
by the double-word
at

locations

is placed

300,

301l.

The

locations 4,

6,7

located -

signed product

mhem

Definition

126~(cont.)

DMUL

300

- As above,»but the high-order product'
is

discarded

location

DMUL

and the
6, 7.

low-order

placed

300

Illegal

DMUL

301

Illegal

127

DDIV
.

Double-precision DIVide,

the

quadruple~word beginning at

signed

the

arithmetic

specified

accumulator
(AC) is algebraically divided’

by the

effective

double~word

double-word. The

quotient replaces

double-word

and

same

as the

dividend,

order

part.,

dividend

quotient

signed
curs,

the

When
and

cannot

number, a
no

remainder,

the

divisor
lost,.

IfAC

divisible

isnot

the

relative

magnitude

divide

dend may ke

signed

its high-

such.that

expressed

takes

signed
low-order

replaces

divisor
be

the

32-bit

overflow-trap ocplace and

four,

the

divi-

the correspond-

ing even double-word is filled to produce.
a two's complement quadruple-precision
dividend.,
The divide then proceeds normally.
The

condition

codes

remain unchanged.

Example:
DDIV- 4,

1136

‘Divide the contents of 4, 5, 6, 7 by
the

contents

remainder
6, 7.
DDIV

1136,

1137,

in 4,

5 and

the

Place

quotient
o

the

1136

Divide the sign-extended double-word
in

locations

by the

contents

mnem

127 (cont.)

Definition

1136,
4,

1136

Illegal

DDIV

1137..
Place the remainder
and the quotient in 6, 7.

DDIV

Illegal

1137

The ébuble—precision instructions
DADD

DSUB
DNEG

DDIV
DMUL

may

cause

being

set,

arithmetic

the

errors

and

result

bit

the

PSW

traps are enableg, a-trap
will occur with.
location 1l6g receiving the
Program Counter pointing
to the
instruction which caused
the error,
:

The

conditions which cause
arithmetic errors in the
se in|
are analogous to these
single-precision counte
rparts

~structions

.SUB
NEG.
DN.

MUL

and the reader is referred
to section
nical Memorandum %29 or
its revisions
tails,
.

2,9
for

of PDP-X Tech~
further de-

Floating-Point Operations

Floating-point instructions operate upon single or double precision floating-point quantities as described in
ArithPDP-X Technical Memorandum #29, section 2.2.3,
metic operations are performed with one operand in a

floating-point register (see below) and another either
The result is developed
a register or from storage.
in
in a register (with the exception of STORE and MCDIFY

operations).

‘

There are four floating-point accumulators, each 64
Floating-point double-precision operations
bits long.
use all 64 bits of the accumulators while single-precision

operations use the high-order 32 bits (0-31).

The floating-point accumulators may be addressed only by the floating-point instructions. No other instruc-

tion class can access them,

Floating-point quantities may be either single-precision

(32 bits,

2 PDP-X words) or double-precision (64 bits,

4 PDP-X words).

The addresses of single-precision floating-

point quantities in storage must be even (effective ad-

dress bit 15 a zero) or an address exception error will

occur (bit 5 of the PSW is set).

The addresses of double-

precision floating-point quantities in storage must be

divisible by four (effective address bits 14 and 15 zero)

The effective
or an address exception error will occur.
be greater
must
addresses of floating-point instructions
floatingthe
address
than 17745 unless they are used to
In that case, the effective address of
point accumulators.,
either a single-precision or a double-precision floating"point instruction must e O, 1, 2, 3.
The floating-point accumulators have addresses of 0,1,

2, 3 in the floating-point address space (memory as seen
They may ke adby the floating-point instructions).
dressed either by the generated effective address or by

the AC-field
of the instruction (instruction bits 4, 5).

In each of the 12 floating=point instructions, the highorder AC-bit (instruction kit 3) is used to specify either
a single-precision operation (0) or a double-precision
operation (1),

10
The

effective-address

space

of PDP-X

thus:

77777

Floating Instructions

00200

%%
%

All Cthers

00200

Illegal

00004

Accumulator 3'
00003

Accumulator 2

¢2002
Accumulator

Accumulator

00001
-

00000

Odd addresses

00000

illegal:

for

(instruction kit 3 = 1),

four,

double-precision

instructions

address must be divisible by

0, 1, 2, 3 used to address accumulators in double and
single precision instructions (in effective address
).

BT Effective addresses such that 38<:EFA<:2008 are illegal,

(Continued)

A quahtity is represented with the greatest precision
when

is normalized.

number has

digit,
zero,

A normalized

floating-point

a non-zero high-order hexadecimal

fraction

If one or more high-order fraction digits are
the number is said to be unnormalized,
The process

normalization consists

(4 bits at a time)

shifting the

fraction

left

until the high-order hexadecimal digit

is non-zero and reducing the exponent by the number
of hexadecimal digits shifted.
A zero fraction cannot
be normalized and
its associated exponent, therefore,
remains unchanged when normalization is called for,
|
Since normalization applies to hexadecimal digits, the

three high-order bits

a normalized number may be

zero,

A number with a

sign

called

zero

exponent,

a true

zero,

zero

fraction

and plus

A true

zero may arise as
operation because of the

the result of an arithmetic
‘particular magnitudes of the operands. A true zero
is
forced when the fraction becomes zero during an arith-

metic operation
tions and

true

- all operations,

(FNA,
zero's

quotient with zero

fraction

established by the
signs,
All

FNS,

FDIV,
as

The sign of a sum,

zero

FUA,

participate
fraction

resulting

rules

FMUL).
normal

Zero fracnumbers

difference,

positive,

product

The

sign
from other operations is
algebra from the operand

floating-point

instructions are long form, EOP class
Since all floating-point operands are
four PDP-X words, immediate mode is meaning-

instructions,

either two or
less,
Since the
in the effective
tions

are

floating-point accumulators are addressable
accumulator-accumulator instruc-

address,
possible.

[p1ofac [ XT 7 b1 " 7

I 7

- select
_
floating-point
accumulator a
sub-function
selection

L0 -

-y

SRR

SRV VY

SO DI

effective address
A
-

select operation,

single-precision

- double-precision

see below

D1
130

_mnem

F(s)Lp,

Definition

F(D)1D

Floating-point_LoaD accumulator,

’

The

by
is

floating-point accumulator

theAC-~kits (instruction

selected

bits 4 and 5)

loaded with the single or double precision word located at the effective

address.
If

(These words remain unchanged.)

single-precision

fied,

the

effective

operation
double-word

is speciis loaded

into accumulator bits 0-31 and hits
32-63 of the accumulator are cleared.
The

condition

codes

remain unchanged,

Examples:
"

FSLD

| Single-precision load accumulator 2
with the

contents

(A must ke even).

of 3,

A +

FDLD 3,
2
Double-precision load accumulator 3,
with the

" FSLD 2,

contents

accumulator

Illegal, effective address is less
than

2005

and greater

than

3g.
8

FDID 1, B
Double-precision
with the

contents

+ 3

by four).

131

"F(s)iN,

F(D)LN

load

accumulator

of B,

accumulator

The float-

selected by the

AC-bitginstruction bits 4 and 5)
with the

negative

precision

quantity

address,

This

F1D

except that

of the

single

located

operation
bit

(B must be divisible

Floating=-point LoaD Negative.
ing-point

the

is loadec
doutle
effective

same

the selected

accunulator
is complemented
loaded,

after

[

gN
O T T X

1R
00N
T
T 11
O

mnem

132

F(s)sT, 'F(D)ST‘

Definition

Floating-pointSTore accumulator,
The
floating-point accumulator selecteéed by

the AC-bits (instruction bits 4 and 5)

replaces

the

single

or double pre-~

cision floating-point word
the

effective

address.

located by

The

selected

accumulater remains unchanged.
If a
single processor operation is specified, accumulator bits 0-31 replace
the two PDP-X words specified by the

effective

address.

operation

bits

replace

0-63

specified by the
condition

a double-precision

specified,

code

accumulator

the

four PDP-X words
effective address.
The

remains

unchanged,

-Examples:

FDST 2,

Double~precision

tor

into

A+

store

accumula-

locations A, A + 1,
3 (A must be lelSlble

by four)

FSST 2, 100
Illegal:;

than

effective

2008

FSST 2,

address
and greater than

Single-precision

lator
bits

133

F(s)Na,

F(D)NA

store

32-63

sum of

accumulator

remain

the

double

effective

The

floating-point

selected by the AC-bits

precision word

address

accumulator,

ACy

unchanged,

(instruction bits 4 and 5)

accumu-

into accumulator 3.

Floating-point Normalized Add.
normalized

less

38‘

The

and the single

located

replaces

the

by the

selected

effective words

re-

main unchanged (unless they are also
modified in theAC-field).
If a single

Dl
.

133

mnem

Definition

(Cont.)

precision operation is specified,
the

high-order bits

the

only

ac-

cumulator participate,
Floating-point

addition

exponent

comparison

dition.

The

consists

and

exponents

fraction

the

two

adop-

erands are compared and the fraction
“with the smaller characteristic right
shifted with its exponent increased by
one for each hexadecimal digit of shift,
until the exponents agree,
The fractions
are then added algebraically to form
|
b

‘

intermediate

TR i eB .

'(i

overflow

right

one

hexadecimal

shifted

and

the

The

single

exponent

sum is

digit

increased by one.*

precision

intermediate sum
hecadecimal digits

seven

possible

carry.

The

low-order

digit is a guard digit retained from

the fraction which was shifted right,

There

cipates
N

intermediate

and

the

consists

sum,

carry occurs,

‘

shift
The

one

guard digit which partiaddition.
If no right

the

occurred,

the

guard digit

double-precision

consists

a possible

14 hexadecimal
carry.

intermediate

guard

O,
sum

digits

and

digit

- retained.

The

intermediate

“tion:
;

are

sum is

left-shifted

as necessary to form a normalized fracvacated

filled

low-order

with

zeros

digit

and

the

positions
exponent

is reduced by the amount of shift.*
The

sign

the

sum is

derived

from

the

rules of algebra,
The sign of a sum
with zero result fractlon is always positive.

*¥*if

this

causes

underflow,

the

exponent

overflow or

arithmetic

error bit

(bit 2 of the PSW)
may

occur

enabled,

set and a trap

mnem

/133 (Cont.)

Definition

Condition code.bits are set as follows:

bit

134.'V'F(S)UA, F(D)UA

0 remains unchanged

set for a negative result,
cleared otherwise.

set

for a non-zero fraction,
clsared otherwise

Floating-point Un-normalized Add,
operation

identical

FNA

This

(above)

except that no post-normalization of
the intermediate result occurs (exponent

135

F(s)Ns,

F(D)NS

FNA),

“Floating-point Normalized Subtract. The

normalized difference of the floatingpoint accumulator selected by the AC-bits

A ot

b Al oA G

sk v

overflow may occur as

e R

(instruction bits 3 and 4)

dourle

precision word

and.the single

located

i =i okt TR

by the
effective address replaces the selected
accumulator,
FNS is identical to FNA
except that the sign of the floating-~
point word located by the effective address is inverted before addition (exponent

overflow

as in FNA).

136

F(S)MP, F(D)MP

underflow may

occur

Floating-point MultiPlication.
The
normalized algebraic product of the
_
multiplier (specified by the effective

address)

by the

and the multiplicand

low-order AC-bits of

the

(specified
instruc-

tion) replaces the multiplicand.
single~precision,

the

operands

1In

are

bits long (i.e., the low~order bits of
the accumulator are ignored).
In doubleprecision,

the

operands

long,

are

Floating-point multiplication
formed in five steps:

The

bits

operands

are

(if necessary)
modified

per-

pre-normalized

and their exponents

accordingly,

136 (Cont.)

mnem

Definition

The exponents are added and the

sum minus

100g

ponent

the

The

becomes

the

ex-

intermediate product.

operand fractions are multiplied
to form the fraction of
intermediate product.
In both

together
the

single and double precision, the
product fractio
is
n calculated to
14, hexadecimal digits.
The

intermediate product

{if necessary)

characteristic

and the

is normalized

intermediate

is reduce
by
d one

for each left shift,
The

final product is-stored.
double-precision operations,

product

1In

the

replaces bits 0-63 of the
multiplicand.
In single-precision
operations, the product replaces

bits

Bits

0-31 of the multiplicand.
32-63 remain unchanged,

When all

bits

set

result

fraction

digits

are zero, t%e product sign and exponent
are

Exponent

The
of

The

underflow

operation
the

gram

to zero.

PSW

overflow may

occur.

completed but bit 2
set and may cause a pro-

trap.

condition

code

remains unchanged,

140

mnem

F(s)bv,

F(D)DV

Definition

Floating-point DiVision.
The normalized
algebraic.
quotient of the dividend

(specified by the low-order AC-bits
of

the

instruction) and the divisor
(specified by the effective address)
replaces
the dividend.
1In single~precision,
the operands are 32 bits long
(i.e.,
the low-order bits of the accumula
tor

are

ignored

and

words

are

fetched

starting at the effective addr
ess),

~In

double~precision,

bits

g ———
R
R

a.'

four

division

The operands are pre-normalized

(if necessary)

The

difference

and

divisor

termediate
Dividend

the

quotient

shift may be
ad justed

100

in=

quotient,

normalized

termediate

dividend

exponent of the

fraction

termediate

between the
exponents plus

divisor fraction.

not

and their exponents

accordingly.

becomes the

are

is performed

steps:

modified

operands

Floating-point
in

the

long,

The
a

need

right

necessary,
this

The

in-

exponent

shift

in-

fraction
but

quotient

for

dividegd

(if

taken).

The

quotient fraction is truncated
single-precision (if a single-

Precision

tient

cision

bits

32-63

occur.

operation

the

program

SOr

zero,

set

and

the

When

the

PSW
trap.

bit

operation

dividend

the quotient will
The

the

quo-

single

preaccumulator

underflow
or
2

and

remain unchanged,

The

bit

cause

1In

operations,

Exponent
and

operation)

stored.,

to.

condition

code

overflow may
is completed
is

set

and may

the

divi-

the

PSW

terminated,

fraction

be a true
remains

zZero,

zero,
unchanged,

[N ]

1L U

Definition

mnem

F(s)cM,

F(D)cM

Floating-point _CoMpare.
fied accunulator and the

are

speci-

effective word

algebraically compared.

accurmulator

changed,
and

The

Neither
effective word are
condition code bits 1

nor

but

are

condition

set

according to

code bit

the

O remains

set

result.

unchanged

if.

accumulator <ef-

fective word
cleared

if.
~accumualt
=efor
fective word

set

ife
accumulatoref-.
fective word

éleared if.

accumulator=ef-

fective word

In single~precision, the low-order bits

- of the two operands
The

comparison

into

account

fraction
ponent

algebraic,

the sign,
is

not

determination

tions may be different,

taking

exponent

of each operand.

inequality

magnitude

are ignored.

and

ex-

decisive

since

the

for

frac-

AR
b i
e
vt

muem

Definition

142

Floating-point Modify Group.

two

low-order

one

four

AC-kits are

possible

The

select

used

instructions,

The

high~order AC-kitH{instruction bit 3)
is used to select single or double precision mode,

142- F(s)Ts, F(D)TsS
I

Floating-point TeSt.
point quantity

by the eftested and conand 2 set ac-

fective address is
dition code bits 1

cordingly.
be zero if

The floating-

selected

A number is said to
is a true zero or

if the fraction is zero,
condition code bit

0 unchanged
1l

set

if <O

‘cleared if =0

2 set if % O
’
142

vods T

cleared if = O

F(S)NG,

F(D)NG

Floating-point NeGate.

The floating--

point

quantity

- fective
*

address

operation

version

Condition

set

142

F(s)aB, F(D)AB

selected

the

is negated.

performed

the

sign

bit

code

bits

the

(bit

and

ef-

The
in-

0).
are

in FTS.

Floating-point ABsolute value.

The

floating-point quantity selected
by
the effective address is made posi-

tive.
The operation
by clearing the sign

Condition code bits
set as
"code

in FTS.

bit

result
of this

Sl WR

result cannot

0).

condition

set

operation

(bit

1 and 2 are

(Note,
never

performed

bit

the

since

negative.)

the

mnem

Definition

AC
%

142

F(s)cL, F(D)CL

Floating-point Clear,
point

number

fective

The floating-

specified by the

address

ef-

cleared to a
true zero,
Condition code bits
l and 2 are set as in FTS.
(Note,
condition codes 1 and 2 are always

cleared
by this instruction since
the result is positive and is

T
A

zero, )

‘

[

JUNSL LA AONGLAOL AU

0 AL

L0 LA

AL O

- Floating-Point Operations Summary:
For the convenience of the programmer, two mnemonics
are
" provided for each floating-point instruction.
One mnemonic
“indicates
a
-the other

single-precision

indicates

operation

a double-precision

(i.e.,

bit

operation

= .0)

(i.e,,

[R5 BRI s
R
e

L RS L S

seEatier E

These'inStructions are summarized in the attached table.

and

bit

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