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XX-BA6E3-DB
May 1967
15 pages
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Document:
09
Order Number:
XX-BA6E3-DB
Revision:
0
Pages:
15
Original Filename:
09.pdf
OCR Text
CONFIDENTTIA . N PDP-X Technical Memorandum #9 - Title: . Bus to Bus Adapter Authof(s): H. Burkhardt | L. Seligman Index Keys : Bus | Communications Interprocessor I0 Peripherals Distribution - Key: A, B, Obsolete: None Revision: None Date: July C 14, 1967 , AL Overall Description The Bus to Bus Adapter_is a device used to connect two processors be used for processor control and together through interprocessor configurations. communications IO processors. ' Memorandum #6, pages It will between (See 8-9, the IO Bus. communications the the also be will used for arithmetic processor Appendix 20). It in multi- ; PDP-X Technical 1. General*SpeCifications 1.5 General Performance . - The Bus to Bus Adapter consists of two receiver— transmitter pairs. This each pair is identical so that in the described. It -will be operated system is full duplex independently. FEach following only one is to be understood in pair of that is the pairs that the processor doing the recelv1ng may s1maltaneovsly be transmlttlng Both the receiver and the transmitter have status registers that may be sensed to determine the operational ‘state will it of the transmit of the receiver of its it In guantity and will process 1If, normal a command memory begin. the pair. to list nature the receive of this some reason, of data about of it. not 1In either case, sent The iode or holds until the to be receiver for the control the sent by of of allows operated the it in transfer will transmitter, or receive none lost but to The a portion cannot handle the it the data is not transmitter may be under and allocate the receiver may selectively receive portions transmitter informing following data. list, data the receiver the command for quantity operations, to the is mer ely be. either programmed multiplexor channel. The same receiver. The receiver~transmitter pair may be 1ocatea together or separated bus is if the significant. is placed between See Appendix. distance between the In this case, transmitter and the a two / separate the transfer receiver, Bdd may be processors 3.0 Programming 3.1 Instructions 3.1.1 Transmitter The transmitter responds o IOC and IOX instructions to set or alter the SR (Status Register). The transmitter SR may be read or tested with IOS and IOT instructions. instruction may be used to transfer one byte to the transmitter data buffer. the REQ bit cleared, is cleared. If the REQ bit in the receiver is Bits transferred to bits 8, 9 of the receiver SR. the receiver SR is set; and the BUSY bit of these events becomes a zero. 10 of the transmitter SR are the REQ bit loaded repeated. UNUSUAL Dbits When a transmitter mitter it has or 13 to to or inform the its SR When the data has REQ will be reguested. set in The trans- receiver of the nature of the data to I0C and IOX instructions IO0S these bits will have no SR becomes a one, of data. The read. The one byte just REQ allow another data transfer receiver operation, data Bits 8, read IOR When the REQ bit in instruction may be used SR contains bit 9, Attempts the status should then be of the cleared to from the transmitter data buffer data buffer. is effect. and to The receiver SR may and IOT instrwctions. of the receiver SR may only be reag or sensed. data byte to the set. (Status Register). tested with receiver read SR are events received. alter to alter the LOW and - Receiver be read 11, same the a low interrupt The receiver responds set the The Mode bit in the transmitter SR serves no function but 3.1.2 in the receiver SR service routine can now respond to and service this interrupt. that None operation, receiver data buffer, SR and cleared. overfliow ocgcurs, in the transmitter ~been accepted by the the channel in into the transmitter data buffer during a multiplexor channel are SR is take place until the REQ bit is The REQ bit in the transmitter SR is in the transmitter If data is transferred to the recelver data buffer. set information The BUSY bit in the SR is set, the transmitter data buffer 9, of The IOW During a multiplexor channel from the receiver"data buffer and - placed into memory whenever REQ becomes a onég-and ENABLE is set. REQ is then cleared overflow occurs. REQ is the SR may be not to enable In that cleared. sensed another case, trams fer unless UNUSUAL amd LOW are channel set and The MODE and TRANSMITTER OVERFLOW bits to determine the stattus of the data of transfer. 3.2 3.3 Maintenarnce Instructions There are no Data Formats Each byte una;tered special maintenance instructions. sent by the form. The format application. Since transmitter of the data | each transfer transmission of is received depends -t in upon sequence will bepreceeded by the a command list, a format should be designed for the particular application. The minimum information contained is of 3.5 bytes about Operator There are to be in the command transferred, Controls no the | operator controls. list the number P 3.6 Status Régisier The Status Registers for the Bus to Bus Adapter appear as: Receiver ES : N | OVER- FLOW | ) | MODE | UNUSUAL | | O REQ 11 12 ‘ LOW ENABLE 14 15 - ok 8K\\\\ \\\ 10 (transfer 5 N \ \\ f AN N !h‘\\\ T‘ihsmitter | //"g . % >/ ’ MODE UNUSUAL 1 8 9 10 11 (X indicates The function ! 5 REQ 12 RUSY LOW 13 14 ) ; 15 permanently zero) of these bits is described in Section i ENABLE ; 3.1. 3.7 Programming Elther operate in the the Examples receiver channel mode. In initialized with byte may be or programmed either its case, REQ transferred the transmitter transfer bit to mode the or or both may in receiver cleared so the multiplexor should be that the first data it. | The examples presented will be Lor multiplexor channel operation 3.7.1 of both the Transmitter transmitter and the receiver. Routine Assume that the main operating proqram develops a command list LIST: of Byte the form: Pointer -Number Of To Data Bytes Of Block Data 3 Control Byteé The 2 bytes position ~list has transmitter of this of the been routine will command list data block) received, (i.e. to in to lock the transmitter LOCK indicates zero value that indicates the it will In the following routine, used the that transfexr it will transfer but the first not transfer receiver. the After the the command data block. the register labeled LOCK is service routine. transmitter the all is transmitter A zero value still busy. A non- routines free. are 4 INITIALIZE LOCK COM LOCK TRANSMITTER 29 CLR L3] LOCK CLEAR LOCK SET ROUTINE -0 BAL -e CALLING SEQUENCE POINTER ~0 ~e “~e ; TRNSMIT RETURN WITH TO COMMAND LIST TRANSMISSION STARTED LOCK TO -1 ‘ LOCK BZ, TRNSMT STA LOCK LDA @(2) STA SDATA SAVE POINTER LDA (2) GET LDA 1(3) TEST LOCK FOR DONE IF %ERO — STILL BUSY SAVE ACCUMULATOR 3 GET POINTER POINTER TO DATA BLOCK | TO COMMAND LIST ~e FROI ~4 SAVE SIZE OF DATA LIST ~e GET NUMBER OF DATA BYTES GET POINTER TO COMMAND LIST 3 ~e X Y] -8 -~ ~4 ~4 ST TURN IT INTO A BYTE 3 ~e : TRNSMT STA SSIZE IDA (2) COMMAND TIST LOCK CLR LOCK 10C XMT, [131] - LDA ~e XMTINT ~e STA 5 ~e [-5] LIST STORE ~e LDA STORE RESTORE ACCUMULATOR 3 e XMTINT-+L MAR® -~ (177776 SET MODE, BYTE IN POINTER TO COMMAND CHANNEL COMMAND IN BYTES CHANNEL ROUTINE BUSY ENABLE, -y ~e LOCK: EXI' FROM ROUTINE ROUTINE ~e 1(2) OTEER 0 ~ BUSY -e P -1 —~ FREE BITS LOCK REQ CLEAR ; ENTER HERE WHEN CHANNEL OVERFLOWS BZ xur, [100] XMTDUN ~é ioT TEST MODE BIT. IF ZERO- DATA.TRANSFER DA SDATA ~e COMPLETE MODE =1 - COMMAND HAS BEEN DA SSIZE STA XMTINT I0C [3;1 PSD ~e XMTINT+1 SENT, ~3 STA- SET UP - e 2 SET REQ, X3 XMTSER: a1 ~e SERVICE ROUTINE FOR TRANSMITTER‘INTERRUPT DISMIS NOW SEND DATA CHANNEL ENABLE CLEAR REST 10 _: 3f 7. 2“ Receiver Routine The normal of'initialized state of the receiver ‘is with its channel locations into its command list buffer. e CelVEO. the receiver set service up.to receive After the 5 command bytes command routine will list call a to allocate memory space for the following data. available for allocatlon the data, the calling location +1. If _will it has not channel will be routine which will return until then memory is subroutine set-up not been If space is return control spact¢ has by to the the available, control been made available. ¥ INPUT 3, SAVE ILDA 3, [-5] STA 3, RCVINT LDA 3, [2%COMLST] STA 3, RCVINT+1 IDA 3, SAVE I0C Rcv, [ 1] ENTER HERE WHEN RCVSER:IOT RCV, -BZ I0T CHANNEL " [200] ERROR RCV, RECEIVER [100] ~e STORE TN CHANNEL ENABLE EXIT FROM SUBROUTINE ACCUMULATOR INPUT TEMPORARY STORAGE INTERRUPT OVERFLOWS -9 ] FCR GET POTNTER TO COMMAND LIST SET ENABLE, CLEAR OTHER BITS TO ? ROUTINE CHANNEL RESTORE . SERVICE IN TEST T) - O STORE BIT, ~e ~a SAVE: GET BYTE COUNT -4 B SAVE AN ACCUMULATOR LT} .o ~e ~8 ~e ~e STA IF NOT SET - DATA WAS LOST -e INIT: uECETVER -8 IWITlALIZ“ NOW - TRANSMITTER IF SET TEST OVERFLOW OK MODE BIT “e ALLOC END OF COMMAND LIST CALL CHANNEL SINCE REQ IS SET, TRANSFER ~e Towe BAL IF LY ) '~ RCVDUN me [ 1] Rcv, ZERO, END ROUTINE OF TO DATA SET UP FOR DATA TRANSFER WONT BEGIN.UNTIL IT IS CLEARED RETURN WITH CHANNEL SET UP - TURN ON ENABLE RCVDUN : BAL OF RECEIVER INIT LOC INTERRUPT RE~-INITIALIZE DISMIS RESERVE INTERRUPT DATA TRANSFER PSD ; ~e END - HERE AT ~ e COME RCVINT BLOCK 2 B RCVSER - r . CHANNEL LOCATIONS -8 ; DISMIS ~o PSD CLEAR REST OF BITS ~e ~a - 10C 11 ~e 'BZ TM~ e ~ TWO WORDS FOR HIGH CHANNEL LOW INTERRUPT BRANCH TO SERVICE ROUTINE Since data transfers to the receiver may be stopped by leaving REQ set, the data may be read in many short records. 12 Appéhdix>_f§. fL¢¢¥$w;fl* 1. General Organization Processor i e s e W R — H 3 i b g ek Processor | ;_ R _ ; fBus to | > Adapter et ee Bus TO Bus 2. Detailed Organization to Bus Bus - ?Trahsmitter ! 1 Adapter P . ¢ Receiver i 4 — e - INNSEnE S [T A Receiver l i — e — —— —— —— —_— I0 Bus 3. 13 Single Pair T0 Receiving Processor A | A V — R | ,Status Reglqter§ ; | | Data | Reglster - | | ________ i -.;.2 Status J [ I | Bits ; 8 bits t i | 1 i | r ; 1 i ¢ ¢ fData ! 7o | | L i ! V Registe Transmitter f ;Status Register | ] o et | G h 2 ee i BU BN ! ! e O e et e U To Transmitting Processor 14 ¥ e Long Distén_éé S [ _ Transmitter %:,D?lver,mSN | Receliver fi Bus im_.:fi__.p\ece 1vez | i { : . > - Ty Bus | S 1 -Rece1ve~m9fi - ;"\““Drlver < s) 4. N ( . 1 Z Receiver | é Transmitter . 13 Single'Péif% To Receiving Processor A { i l/:\\__..,..‘.-_._._;..a.-/: ;\. T qJ sT Y 7} OO — | Status i v/ i _,...__.._... e Register 1 t i | }Dat a Register || ] | . i Data Register ansmitter H ! — gStatus Reglster I bits \‘}' To Transmitting Processor O’) 8 Recelver 5 B te H3 l ,....-... T 3.
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