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July 1967

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CONFIDENTTIATL

PDP-X

Technical Memorandum # 6

Title:

Author (s) :

PDP-X System Architecture

Index Key (s):
|

Burkhardt
Seligman

Architecture | _
System

Design Decisions

Distribution
Key:

Obsolete:
Revisions:
Date;

None
-

None
July

1967

PDP-X System Architecture

Introduction
The

term

system

architecture

intended

to convey the

concept of logical structure as opposed to its physical

realization ‘or implementation.

The PDP-5 architecture,

for example, has been re-implemented several times; the

~last,

PDP-8/1I,

of the

the fastest,

implementations,

least expensive,

executes

and smallest

the same programs

runs the same peripherals as its predecessors.

and

The life-

time of the architecture with its system and diagnostic software,

internal options,

and training,
thus,

peripherals,

customer acceptance,

is far longer than that of any implementation;

company's

architectural design

far higher.

The overall

system architectural description contained

this document,
found

stake

associated

implementations

Since

the

able.

good

together with the more detailed descriptions

single processor;

models,

documents,

PDP-X

varying

architecture

many of the

The first

lends

do not merely define
itself

complexity

constant

same programs

number

and

relative

across

expected

the

PDP-9

costs.

several peossible

and peripherals

implementation of PDP-X falls

complexity range

are

applic-

in the cost/

replacement;

future

implementations are possible, with the smallest very much

‘competitive with PDP-8/I and the largest falling in the
current

gap between the

large

and small

computers

available from DEC.
PDP-X has
computer
levels

grown out
lines,

features

added

ways

PDP-X is

word

structure

important

shows

the

experience with DEC's

the

strives

a basically

and basic

simple

over

the

structures.

small

through

optional
In many

sharing the

same basic

but

that will make

several years.

evolution of bagic DEC

and

structure.

instructions,

advances

large

to achieve performance

largest machines

a refinement of PDP-8,

design

other products

the design

comparable

now

small

also

including

competitive with

The

appendix

computer OP Code

TM~

The major.chafacteristics.of PDP-X include:
efficient memory utilization
structure

wide

amenable

range

software

fourth

and

hardware

implementation

integration

real-time

and multiuser

processor

mcedule

modular

generation

of possible processor performance
environment

concept

implementations

integrated

option

design

Details of the initial implementation must await rexperience
gained
prablem

from PDP~8/1I,
areas

which,

and potential

is hoped,

packaging

will

traps.

expose IC
PDP-8/T

will

also expose the new cost relationships so that PDP-X
‘design strategy can focus effectively on achieving minimum
manufacturing cost.
|

Efficient_Membry.Utilization
One of

the more obv1ous

de51gns has been

their

problems with

inefficient

cmrvent

small-machine

use @f core memory,

system resource whose

cost has been risimg relative

'cost ©of the processor

logic.

Indeed,

a major

a .

to the

cost-reduction

technlque used in PDP-8/5 design was the: development of
a

j*far less
expen51ve memory as 1s indicatexd3 by the cost
Td;n in the appendix.
PDP-X architrecture makes more
uht use of available core memoty tihrough the introductlon of
_istrucLure

a more powerful instruction stet and an addleSSlng
that

in sector

eliminates

addressing and

the .(sometimess

single

hidden)' memory waste

accumulaitor

small-computer

- designs.

The great majority of instructions writt:en for and executed
by small computers,
the

PDP-8

little

regardless

repertoire.

information,

1In

addition,

index quantities,

(16-bit)

representation

complete

instruwction set,
most:

fall

address bits

into

contain

they usually reference memory words

the lowest words in memory
permits

(32-bit)

to the

program

counter,

(sector 0).

PDP-X allows compressed

instructions

where possible

representatiorr

and

when necessary.

Hence,

although such an instruction set has mucih: of the potential
power
sary

and

to express

address
task

scope of

all

most

of memory

32-bit processor,
instructions.
easily,

facing the programmer by

when

only 16-bits

The

ability

necessary,

eliminatimg

linking structures
as found, for example,

the

are necesdirectly

simplifies
need

for

the

complex

in the PDP-9.

1In

addition, the more casual customer or amplication programmer
can generate working pfograms far more uickly.
The appendix
contains

a more detailed

analysis

the

instruction formats.

The ultimate test of the efficiency
of ihe structure lies in
the programming package

supplied with

ttae hardware.

Since

no manufacturer of a PDP-9 class machine has been able to
supply a version

such

as well

of FORTRAN

compiler would
as

for

4K word-memory

represent

major :competitive

testify
to the accomplishmenic

system,

design

advantage
goal.

Wide Range
The

architecture

whose price
‘market

an
and

Possible

a model

controller

span

the ‘architecture

particular model also

entire

enough

selector

processor
small

use

charnel.

possible

leads

exhibits

in several
the

small

re- 1mplementailon should be

years

Perforimance

is implementable

and performancé

and .include

device

Processor

many

computer

part

Smooth

over

the

range

of
.

evolution

mew models,

fairly wide

models

several

each

of perfor-

mance depending on the number and type of internal options and
peripherals purchased.
To avert prbliferation of software
systems,

however,

certain

standard

configurations

will

defined and the software written around them.
The

major

reasons

performance

for

the

range

of possible

processor

are:

large,

wvariable

partially

use

implemented,

number
of

associated
c.

wide

main

interrupt

©P

code

levels

set

with

resister” sets
core memory

replace

hardware

registers
d.

facility

for

multi

configurations
to basic
e.

use

ROS

drastic

alterations

processor
to

controllers®

user/multiprocessor

without

create

dedicate

OEM

Sofuware

and

Hardware Integration

pPDP X systems will consist of many diverse configurations
ranging

the

from

the

1arge

small,

dedicated

real-time/multiuser

system

software

fully

realizing

should

data

gathering

115bal}otlon~

be ava11able-to &id

the potenc117 powbr

useful

each

of'his

system

user in

particular

“conflgufaLlon
1}

.Ease

goals

use,

rather

the

ventions,

than

software

command

sophlstlcatlon

systemn.

relatively

included

data

-assembler

and

major

clean
for

systems

error

major

data

asrecorded

will

be written

©f

configurations.”
and

and

the

also

accessible

for

detailed

information

external

and

plces

will

data

useir.

not modify
a

Refer

with

available

will be

done ‘through

the

media.

Programs

alterable

will be

con-

recovery

mochar

face

input/output

major

calling

minimal versions will be

instructions

the

the users will

such

the

All

~appendix

will be parity-checked,.

located.
that

and

detection

systems

All I0

sequences;

smaller

themselves;

the

or both

calling

the

compiler.

check-summed,
The

all

formats,

Since most

inexperienced,

one

BewilderF
ing numbers of

mnemonics,

Sequences are to be avoided.
be

independently

common
to

required

inter-

the
software

components.

The

importance

overstressed;

portions

many

customers

the

software

maintenance

will

become

for hardware.

today

internal

will wamt

system.

important

lany of

alter

employee

results

solved

concurrent

cannot

modiL fy

performance

the

the problems

training,
by

Software

documentation,
can be

&ocumentation

turnower,
Qe"“mn

and

years

and
and

few

unexpected
documentation.

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Real-time

and

Real-time

usage has

. PP

AL
L
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Multiuser

and applications;

out.

The first

cost

the

S S

[ - TR

important

dedicated

(e.g.,

)

factor

three very distinct

the

device

I L

Environment

become

sales

on-line

particle

usages

response
in

time,

addition,

optimized
some

good

high

the

accelerator)

code,

allow

extwemely

core memory,

software package

arighmetic

1evel

order

speed

sort’ of

the

interfaced

PDP-X
fast

and

fast

includes

set

and utility routines,
this

stand

system where

to'the computer far outweighs the later®s cost.
hardware provides

computer

interrupt

system;

of highly

re—entrant

real Lzme usage.

“The second is used by an OEM who requ1r s the smallest and
simplest processor possible

customers
in

will

dedicated

The third

use much

together

occupy
time.

laboratory
The major

only

programs

problems

core

overhead

for

feature

Such

for

rapid

such

the peak
been due

service
to

optional hardware,

few

processor

status

map.

With

interrupt

explicit ly

the

saved

of both

intent

sets

of PDP-X

interrupt)

general

addition

will

and

The

combination

(due

cases

demands.

User

The

switching

allow

discussed.

absolute minimum by providing multipie
memory

real-time,

low overhead

already beer:

reduce problem

core memory to

g¢onsiderations.

system.

prok:iem switching.

usage have

hardware

traditional

software

sufficient

always

available

required

to handle

has

the

(DEC®s

multiuser

interrupt response,
and

resident

fraction

customer

environment,

switching users,

design

product.

same hardware
used by DEC
a

small
the

looks

fast

and

Here

hardware

implies

software

the

his

controllers.

user)

non-dedicated

change

imbed in

usage occurs where several real-time operations

processor

This

require

this

that

restored.

A complete

set

models,

adding

these

advantages
status

dual

the

and

registersfi'hardware on the

each

interrupt

is easily

automatlcally

double-word,

user

registers

map provides

rather

general

provided

the

accumulators,

real

time

than ,relocation,

bit per bloe has

been

set

The

and feStorlng
and

irdex

the

program

mapping registers

protection bit

since

per

word,

leads

is most

The

for

Mapping

protection

simplified

system programming and better c¢ore usage, facilitates

shared code,

registers.

monitor program.

selected

larger

cost

outweiched by the

saving

separate

lewel.

and as the most general of the above systems,

llnery

fit

customer's

partreular needs.
]

Processor module. concept
As

advanced

engineering/manufacturing methods

computer

arithmetic processors

relative

them.

etc.,

almost

difficult

powerful

interfaces,
processor

Today,

complex

one

command

finds

the

tape

and

1nterference these

systems,

arithmetic

including

less main

controllers

and

demand
more

certainly

for

still

flexible

(arithmetic)

must

grow even more

complex.
¥

The most common approaéh to increasing the IO controller

capability while reducing system costlas been the imbedding

part

the

success

this

processor

simple

time

controller
stolen

controllers,

assistance,

approach has

the arithmetic
been

relative

processor.

limited by
the

costs

the

The

amount

saved.

Extremely

relying heavily on main processor

have been very unsuccessful

for

reasons

efficiency.

A new approach may be termed the procéssor module concept.
Here,

the

specialized

controllers

general purpose processors

the
is

special purpcse hardware
replaced

Devices

which,

implementation

appropriate

their

are

dedicated

normally

software

control.

found

and

complexity,

replaced by
IO

lend

ROS

in the

small,
Much

controllers

programming.

themselves to

this

include:

Magtape

DECtape

Display

It
not

Multistation

teletype

control

Line printer

control

and buffer

should

general

processors

noted,

however,

that

the

purpose multiprocessing.
will

sold

only

intent
These

just happens

to be

Since,

most

new software

however,
to

operation,
to

aid

this

achieve

it would

of
some

the

form of

appear

multiprocessing

whose

systems. are

simultaneity of

the

time

standard processor.

that hardware
is

this

dedicated

controllers

implementation

designed

subsystem

explicitly designed

natural

or'

grows

displays,

processor

satisfy user

structures,

higher bandwidth,

the cost

the cost of I0 controllers

to manufacture.
IO

shrink

extension

current design.

'(f

vehicle

systems.

for

PDP-X architecture permits

software

Multiprocessors offer:

optimization
through

system

over

dynamic

size

units,
S

development

it to serve as a

general multiprocessor,

diverse problem mixes
restructuring

scales,

over

of more

adding identical
extremely wide performance

range

extreme

rellablllty

lowers system
A

typical

appendix.

system

since

malfunctlon

capacity.

component

interconnection

merely

’
is

given

the

‘Modular Implementations-

-One of the most dbvious, and perhaps expected, facts of. digital system manufacture is that the lazbor cost and time
of

test

rises
as a

module count.
~to

justify

accurate

law rathe
than linearly
r with

Some statistics are presented in the appendix

these

square

conclusions;

one might

desire,

although
the

they

general

are

trend

not
is

as
clear.

Independent subassembly construction and testing seems to

begone effective method
of minimizing system manufacturing
cost

and

‘were

in-process

small

construction

fraction

time..

system cost,

Indeed,

the

even

test

(un)availability

of properly skilled.manpower strongly influences the production
rate.

labor costs

rise and component costs drop,

for modular construction techniques

increases.

the need

A PDP-X

processor

(memory, or major option) is paxrtitioned into a
number of independent subassemblies which are small enocugh
to be

suitable

reduce

the

for

number

subassemblies

are

automated
and

assembly

construction
replaced,

personnel.

not

level

test

considered

they

are

cost

equipment

yet,

interconnections.
repairable

and,

repaired,

only

like most of
by

system

which
These
the

todays

test

sub-

modules,

and maintenance