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XX-A53D5-68

June 1967

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Document:	04
Order Number:	XX-A53D5-68
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Pages:	3
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,\.

CONFIDENTTA

PDP-X Techniczal Memorandum #

Titlé;

.'_

er——

PDP-X Design Decisions

Auéhor(s): L. Seligman

Inéex Keys:

Design Decisions

Distribution

Keys:

A, B,

Obsolete:

None

RevisiQn:

Dété:

)

None

June ié, 1967

~‘
|

Having had discussions with DEC personnel,

several customers,

and

others,‘we-have arrived at the following processor design deciéions:
a.

The basic word léngth has been chosen to be 16 rather than 18

bits in order

to maintain compatibility with

new#r computérs;.especially IBM.

the majority of the

The byte and charactér are 8 bits
A}

long;

a double word consists

with hexadecimal

The word,

radix,

of 4 bytes;

consists

16 bits of data,

addressable

unit although

bits, bytes,

doublewords,

floating point word,

of either 4

data bytes.

has been chosen to be the basic

instructions

etc.

are

as data.

available

which

reference

Doubleword instructions

need not fall on doubleword boundaries although double data words
v

. must.

The basic structure contains multiple accumulators/index reg-

isters. The general register structure simplifies the order code }'
and proves

greater programming

power

over

conventional

’

single]

)

accumulator organiza"cions_,,:/~ The floating point registers,
more of
a programming

convention

than hardware

the general

registers.
| v/>kx

base

registers

addressing

©No

capable
short

format.

long

are

used

feature,

con v

relatively,

addressing,

indexed,

format permits

direct

are

distinct

;

instructions

and to page

specification

‘word anywhere in the entire memory system as well
immediate

form,

data.

all are

The most

available

common

long

instructions

form.

are

from

are

in
of

the
any

as indexed or
available

short

The basic unit of IO data is the byte.

This unit is natural-

. for paper tape periphérals, the most common types, as well as the
tele£ype; ‘The bus organization permits the transmission of a full
-~

‘word! whenever necessary..
S

[ERT—

: priorityA%

»
.

interrupt system which

ermits direct device recodg»

nition is provided as standard.

Separate register sets for the

interruptélevels are provided to maximize IO bandwidth.
g.

A standardized, unified IO structure common to all processors

" permits both program controlled and channel controlled transfers
over the same bus with a minimum of device hardware.