PDP-X Design Decisions

This document, PDP-X Technical Memorandum #4, dated June 18, 1967, outlines key design decisions for the PDP-X computer, influenced by discussions with DEC personnel, customers, and IBM. The core word length chosen is 16 bits for compatibility, with an 8-bit byte, a 4-byte double word, and floating point words of 4 or 8 data bytes. The 16-bit word serves as the basic addressable unit, though instructions can reference bits, bytes, and doublewords, with doubleword instructions not requiring boundary alignment. The architecture incorporates multiple accumulators/index registers for simplified code and improved programming, with floating point registers distinct from general registers. Addressing is flexible, supporting relative, indexed, and page 0 addressing in short format, and direct memory access in long format without using base registers. I/O data uses the byte as its basic unit, suitable for peripherals like paper tape and teletype, with the bus allowing full word transfers. A standard priority interrupt system with direct device recognition and separate register sets maximizes I/O bandwidth. Finally, a standardized, unified I/O structure across all processors enables both program and channel-controlled transfers over a single bus with minimal hardware.