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XX-3794D-5F

January 1967

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CONFIDENTTIAL
PDP-X Technical

Memorandum #

Title:

PDP-X Design

- Auth(s)
or
:

Keys:

Goals

E. deCastro
L.

Index

Seligman

Design

Goals

Distribution
Key:

Obsolete:

Revision:
Date:

April

25,

1967

PDP-X

design goals

This memo outlines the gozls of the PDP-X project.
bj tives

are reasonably firm,

implementation are

still very

the

techniques

much under

%o be

Vhile the

used in

study.
%

1. Yodern processor design
Se

Current DEC

$mall computer desighd are limited
e

available
1

technology.

For example,

the necessary hardware

to0

both the PDP-8I and the PDP-g
imvlement

)p Code structure prohibits this,

PIP-X architecture

be.

Over the past few
-

memory and

restore

the

digital

balance

3.,

logic

e A

has

thus

years

shifted.,

the relative costs of

TDP-X

minimizing total

architecturs
.

sysien costs.

‘the

without unduly ircreasing centrsl processcr complexity.

Ths

+ o)

fda

principval method will be

should

Code set should, for éxemple, Teature more vowerful insiruciions
and a more

flexible addressing struciure.

PDP-X basic configurations must

over a far wiger range

than current producte.

exvahd neatly

Use

of read only:

storage (RCS) for Op Code expangion and specigl perhipheral
controllers

cogt.

should permit

increasing svstem

The addition of integrated,

speed interrupt

processing as well

capa bility at moderate

active memory arrays will
as

the more

complex

insiructions.

If the design sells well, one can reasonable exvect
C
to eveniually
offer
ksl

3 processors,

would replace

the

all of which use

present PDP-8,

the same srchitecture,

PDP.g, and, PDP-24,

These

The érc%luec,u*e should be imdlémented around

hardware re adilyavailable at the begining of procsssor
-

should also.be

to the use

internal

scratech vad memories,

‘S,

-3

gate arrays, and ofihQA(omms of large scale integrat on (13T
[

amenable

ife but

Cur current experience in the hardware necess & Ty
o

for complex sofiwars systenms (eg; background/fdregroufid monitor)
imbedded into

essily,

tadked on

[}

‘—‘

ruction trapvs,

fi'

ots

P—-‘
D

then

r for dynapicmemory

}-—’

2llocation/vrotectio
be

design rather

The hard
f‘.

an afterthought.

the basic

rmust be

etc.,

should

but optionall:

2. Fourth ganc;atgon design
(3

The basic

building 1051 of thes next

processor, if it is to be ths basic
severa 1 years products,

exvand into the next generation designs.

must

essily
;

Hultiprocessing

capability in itsmost general (and effective) form still lies
.5

veyond the

reach

of ¢

nttechnigues:

however,

should

vossidle to implement the larger perhipvherzl devices (ezt Vagtave)
using the basic processor and

suit
suitable
a

RO0S.

Such "mini-multivroceszer

design should also help break the produciion boiitleneck on

An ultimate goal

todav,

verhipherals that we face

is the Ffacility for horizontal

gystem expansion;

adding additional,
goal

3.,

liegs

far

ability to

increase

identical processors.

svelem performance by

‘The

attainment

of this

ahead.

Standardized IO

o minimize, the
c 21

processor,

’

the

cost

hardware must be uged

A standard byte

interface

the

simpler perhivheral

with gll verdions of.the

is the mos:

likely chéice

While the software goals still

stages have beern culled From

Larry Portner

ted competition,

o
{.fl

gjci

a
O

stage

the following thres

lack much deitz

1 -~ basic assembler

editor

stage

3 - keyboard monitor
ES

extended monitor (as required)
Stage 1 goftware should be oriented zround a

minimam configuration,

the

stages 2,3 avound az PDP-9 class systen

software

should be modular =0 that it can

be eventually run in a monitor environment end require as little
-

s pos=ible to
. be simuliansously core resident.

6. Anticipated schedule

Aor

'es

prototype rumning

July 1

'68

)

software

simulator

stage 1 basic

basic diagnostic
HJ

'
diagnostic
inal processor

Dec

1 47

Mar

1 'A%

Feb

1 '68

ept

systen

prints for basic

vrototype constructed

svstem architecture

hardware
Y

-+t should also

Coe

f_-_ o fiddoumen€gtion

architecture

Sept 1 '47

specification®

Sept 1

'68

user

Jan

'69

handbook

documentation
will be concurrent with development
referg to detailed IC timing,
be used in contiracts,

etc.,

sufficiently