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EK-TJU16-MM-002

May 1975

182 pages

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Document:	-002 TJU16 Magnetic Tape Subsystem Maintenance Manual Apr75
Order Number:	EK-TJU16-MM
Revision:	002
Pages:	182
Original Filename:	EK-TJU16-MM-002_TJU16_Magnetic_Tape_Subsystem_Maintenance_Manual_Apr75.pdf

OCR Text

EK-TJU 16-MM-002

T JU16 magnetic
tape sul:;lsystem
maintenance manual

digital equipment corporation • maynard. massachusetts

First Edition, December 1974
2nd Printing (Rev), April 1975

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

FLIP CHIP

PDP
FOCAL

DIGITAL

COMPUTER LAB
4175-15

CONTENTS
Page
CHAPTER 1

SYSTEM AND PHYSICAL DESCRIPTION

1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.2.3

1.6.2.1
1.6.2.2
1.7
1. 7.1
1.7.2
1.7.3

GENERAL . . . . . . . . . . .
Scope
........ .
Related Documentation
BUS INTERFACES . . . . .
Unibus· .
Massbus
Slave Bus
....... .
RHll MASSBUS CONTROLLER
Register Access Control Path
............... .
DMA Data Path
TUI6/TM02 TAPE SYSTEM
. . . . . . . . . .
MAGNETIC TAPE FUNDAMENTALS - DEFINITIONS
TUI6/TM02 RECORDING TECHNIQUES
NRZI . . . . . .
Definition
Format ..
PE (Phase Encoding)
Definition
Format . . . .
TJU16 SPECIFICATIONS
Data Format . . . . . . . . . .
TUI6/TM02 Specifications
RH11 Controller specifications

CHAPTER 2

MASSBUSINTERFACE

2.1
2.2
2.4
2.4.1
2.4.2
2.5

GENERAL ., .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DATA BUS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CONTROL BUS . . . . . . . . . .
COMMAND INITIATION . . . . .
Non-Data Transfer Commands
Data Transfer Commands
MASSBUS PHYSICAL DESCRIPTION

CHAPTER 3

OPERATION AND PROGRAMMING

3.1

GENERAL ., . . . . . . .
DEFINITIONS . . . . . . . . . . . . . . . . . . .
INTERRUPT CONDITIONS . . . . . . . . . . . .
TERMINATION OF DATA TRANSFERS
TJU16 COMMANDS . , . . . . . . . . . . . . . . .
Non-Data Transfer Commands .
Data Transfer Commands
Write Data Transfer
Read Data Transfer
Write-Check Data Transfer
Data Transfer Rates
REGISTER DESCRIPTIONS
Control and Status 1 (MTCSI) Register 772440

1.3
1.3.1

1.3.2
1.4
1.5
1.6
1.6.1
1.6.1.1
1.6.1.2

1.6.2

2.3

3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4

3.6
3.6.1

iii

1·1
1·3
1·3
1·3
1·3
1-3
1-3
1-6
1-6
1-6
1-6
1-8
1-9
1·9
1·9
1-9
1·9
1-9
1-10
1-10
1-10
1-10
1-13

. . . . ..

2-1
2-1
2-1
2-3
2·4

24
2-4

3-1
3-1
3-3
3·3
34
3-4
3-4
3-8
3·8
3-8

3·8
3-9

. . . 3-10

CONTENTS (Cont)

Page
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.6.8
3.6.8.1
3.6.8.2
3.6.9
3.6.9.1
3.6.9.2
3.6.1 0
3.6.11
3.6.12
3.6.13
3.6.14
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.8

Word Count (MTWC) Register (772442) . . . . . .
· . . . . . . . . . . . . . . 3-10
Unibm Address (MTBA) Register (772444) . . . .
· . . . . . .
. 3-10
Frame Count (MTFC) Register (772446)
.... .
· . . . . .
. .. 3·13
Control and Status 2 (MTCS2) Register (772450) . . . . · . . . . . .
. 3-14
Drive Status (MTDS) Register (772452) . . . .
· . . . . .
. 3-14
...... .
Error (MTER) Register (772454)
· . . . . . . .
. 3-14
Attention Summary (MTAS) Register (772456)
· . . . . . . . . . . . . 3-25
Setting the Attention Active (AT A) Bit
· . 3-26
Clearing the Attention Active (AT A) Bit .. .
· . . . . . . . . . . . . 3-26
Character Check (MTCC) Register (772460) . . . .
· . . . . . . . . . . . . 3-27
CRC Character Storage . . . . . . .
. . . . .
· 3-28
Dead Track . . . . ' . . . . . . . . . . . . . . . . . .
· 3·28
Data Buffer (MTDB) Register (772462)
........ .
· 3.. 28
Maintenance (MTMR) Register (772464)
..... .
· 3-29
Drive Type (MTDT) Register (772466)
.......... .
· 3-34
Serial Number (MTSN) Register (772470) . . . . . . . . . .
· 3-34
Tape Control (MTTC) Register (772472)
.... .
· . 3-34
. . . . .. .. 3-34
PROGRAMMING EXAMPLES
..... .
Write Data Transfer
· . 3-39
Read Data Transfer
· . 3-40
Space Operation . . . . . .
· . 3-40
Tape Mark Operation
· 3-40
SUGGESTED ERROR RECOVERY
. . . . 3·40

CHAPTER 4

TJU16 COMMAND REPERTOIRE

4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10

INTRODUCTION . . . . . . . .
REWIND ., .
SPACE . . . . . .
ERASE . . . . . .
PE DATA READ .
NRZ DATA READ
PE DATA WRITE
NRZ DATA WRITE
WRITE TAPE MARK
ERRORS . . . . . .

CHAPTERS

THEORY OF OPERATION

5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.3.1
5.3.2
5.3.3
5.4

GENERAL . . . . . . . . .
REGISTER CONTROL PATH
Writing a Local Register
Reading a Local Register
Writing a Remote Register
Reading a Remote Register
DMA DATA PATH
..... .
Write Record Transfer . . . .
Read Record Transfer
Write-Check Record Transfer
WRITE FLOW DIAGRAM DESCRIPTION

4-1
4-1
4-1
4-3
4-4
4-6
4-6
4-9
4-9
. 4·12

5-1
5-1
5-1
5-3
5-3
5-3
5-3
5-7
5-9

5-11
5-11

CONTENTS (Cont)

Page
5.4.1
5.4.2
5.5
5.5.l
5.5.2
5.6
5.6.1
5.6.2

Unibus Flow Description . . . , ..
Massbus Flow Description . . . . .
READ FLOW DIAGRAM DESCRIPTION
Massbus Flow
Unibus Flow . . . . . . . . . . . .
WRITE CHECK FLOW DIAGRAM DESCRIPTION
Massbus Flow Description
Unibus Flow Description . . .

CHAPTER 6

DET AILED LOGIC DESCRIPTION

6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.:<'
6.2.6
6.2.7
6.2.8
6.2.9
6.2.l 0
6.2.l1
6.2.12
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.6
6.6.1
6.6.2
6.6.3
6.7
6.7.1
6.7.2
6.7.3
6.8

GENERAL . . . . . . . . . . . . .
BCTA LOGIC DIAGRAM . . . . .
Local/Remote Register Selection
RSEL Signals . .
Decoder Inputs . . . . .
Decoder Outputs . . . .
Word or Byte Addressing
Control Lines
..... .
ODD BYTE L Signal .. .
Device Select (DE V SEL) Logic
Deskew Demand (DESK DEM)
Register Strobe (REG STR)
Control Out (CTRL OUT) Signal
Gate Control (GATE CNTL) Signal
LOGIC DIAGRAM BCTB . . . . . . .
Deskew Demand (DESK DEM) Logic
Response from Drive . . . .
SSYN Logic . . . . . . . .
Gating Address Onto Unibus
Data Buffer Out Clock ....
LOGIC DIAGRAM BCTC
Clocking Bus Address Register
Address Bit 00 . . . . . . . .
Count Down (CNT DW) Flip-Flop
Bus Address Outputs . . . .
LOGIC DIAGRAM BCTD, BCTE
Word Count Registers
Word Count or Bus Address Selection
Clear Logic . . . . . .
Word Count Overflow
LOGIC DIAGRAM BCTF
Interrupt Request
Bus Request
Interrupt Done .. .
LOGIC DIAGRAM BCTH
NPR Arbitration "
Acquiring Bus Mastership
Completion of NPR Cycle
LOGIC DIAGRAM BCTJ

· 5·11
5·14
· 5·15
· 5·15
· 5·17
· 5·17
5·19
· 5·19

6·1
6·1
6·7
6·7
6·7
6·7
6·8
6·8
6·8
6·8
6·8
6·8
6·8
6·8
6·8
6·8
6-8
6·9
· 6·10
· 6-10
· 6-10
· 6·11
· 6-11
· 6-11
· 6-11
· 6·11
· 6-11
· 6-11
· 6-12
· 6-12
· 6-12
· 6·12
· 6·12
· 6-13
· 6-13
· 6-13
· 6·14
· 6-14
· 6-14

CONTENTS (Cont)
Page
6.8.l
6.8.2
6.8.3
6.8.4
6.9
6.10
6.10.1
6.10.2
6.10.3
6.10.4
6.1 0.5
6.1 0.6
6.11
6.11.1
6.11.2
6.11.3
6.11.4

6.11.5
6.11.6
6.11.7

6.11.8
6.11.9
6.11.10
6.11.11
6.12
6.12.1
6.12.2
6.12.3

6.12.4
6.12.5
6.12.6
6.12.7
6.12.8
6.12.9
6.12.10
6.13
6.13.1
6.13.2
6.13.3
6.13.4
6.13.5
6.13.6
6.13.7
6.13.8
6.13.9
6.13.10
6.13.11

6.13.12
6.13.13

MB INIT Signal
................
. . . . . .
· 6~14
Gating High Byte of CSI/CS2 . . . . . . . . .
. .... .
· .. 6~t4
MXF Error Flip-Flop . . . . . . . . . . . . . . .
. . . . . .
· 6·14
AC LO and DC LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
· . 6-14
BCTK LOGIC DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
· . 6-15
LOGIC DIAGRAM CSRA . . . . . . . . . . . . . . . .
. ........ .
· . 6-15
Data Transfer Command Logic ..
· . 6-15
· . 6~16
RUN Flip-Flop '" . . . . . . .
BUSY Flip-Flop
. . . . . .
· . 6-16
Port Select Flip-Flop . . . . . . .
· . 6-17
CS 1 Clocking Logic
· .. 6·17
Interrupt Requests . . . .
· .. 6-17
LOGIC DIAGRAM CSRB
· 6·17
,. 6-17
CS2 Clocking Signals . . .
Program Clear Bit . . . . . .
· 6-17
Bus Address Increment Inhibit
· 6-17
Unit Select Number
· 6-18
, 6-18
Parity Test Mode .
Function Load ..
· 6-18
Non-Existent Drive
· 6-18
Transfer Error
. . . . .. . . . . . . . . . . . . . . . . . .
· 6-18
Program Error Flip-Flop . . . . . . . . . . . . . . . . . . . . . .
· 6-19
End of Sector (EOS) Flip-Flop . . . . . . . . . . . . . . . . . .
· 6-19
. . . . .
Unibus Parity Error (UPE) Flip-Flop . . . . . . .
· 6-19
LOGIC DIAGRAM DBCA . . . . . . . . . . . . .
· .. 6-19
NPC MASTER Signal
..... .
· .. 6-20
ADDR TO BUS Signal
· .. 6~20
MSYN DESKEW .. ,
. . . . . . . . . 6-20
MSYN Inhibit Conditions
. . . . . . . . . 6·20
MSYN Timeout . . . . .
. . . . . . . . .
. . . . . 6-21
DAT AWAIT and MSYN WAIT One-Shot Multivibra tors
· . 6-21
CYCLE COUNT and NEXT CYCLE Flip-Flops ..
· . 6·22
ERROR Conditions . . . . . . . . . . . . .
· .. 6-22
I-Cycle Jumper
· . 6-22
BUS HOG Mode ..
· . 6·22
LOGIC DIAGRAM DBCB
. . . . 6-23
Silo Input Logic
· . 6-23
Silo Output Logic
· . 6-24
Error Flip-Flop .
· 6·26
Generation of INH CLK L ..
· 6-26
SILO CLR Generation . . . . .
· 6-26
Write Clock
· 6-26
Gating Synchronous Data . . . . . . . .
· 6-26
Data Requests (Write Command)
· 6-26
Data Requests (Read or Write-Check)
· 6-26
NEXT SIGNAL (Write) . . . . . . . . .
· 6-26
NEXT SIGNAL (Read or Write-Check)
.. . . .
· 6-27
Word Count Increment (Write Conunand) . . . . .
· 6-27
Word Count Increment (Read or Write-Check) .. .
. . . . 6-27

CONTENTS (Cont)

Page
6.13.14
6.13.15
6.14
6.15
6.16
6.17
6.18
6.18.1
6.18.2
6.18.3
6.19
6.19.1
6.19.2
6.19.3
6.20
6.20.1
6.20.2
6.20.3
6.20.4
6.21
6.22
6.23
6.24
6.24.l
6.24.2
6.25
6.26
6.27
6.27.1
6.27.2
6.28
6.29
6.30

EXCEPTION ERROR (Write Command) . . . . . . . . . . . . . . . . . . . . . . . 6·27
EXCEPTION ERROR (READ or WRITE·CHECK) . . . . . . . . . . . . . . . . . . 6·27
LOGIC DIAGRAM OBCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·27
LOGIC DIAGRAM DBCD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·28
LOGIC DIAGRAM DBCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·28
LOGIC DIAGRAM OBCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·28
LOGIC DIAGRAM DBCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·28
Parity Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
74157 Parity Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·29
8234 Control Une/Data Buffer Multiplexing . . . . . . . . . . . . . . . . . . . . . 6·29
LOGIC DIAGRAM DBCJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·29
Start Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·29
CSl/CS2 Gating Onto BUSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·29
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
M7297 PARITY CONTROL MODULE (PACA) . . . . . . . . . . . . . . . . . . . . . . . 6·29
Synchronous Massbus Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Read or Write-Check Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·30
Write Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·30
Asynchronous Massbus Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
M5904 MASSBUSTRANSCEIVER MBSA, MBSB, MBSC . . . . . . . . . . . . . . . . . . 6-31
UNIBUS A CABLE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
UNIBUS B CABLE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·32
M9300 UNIBUS B TERMINATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
NPR Arbitration and Issuance of NPG . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
Prevention of NO-SACK TIMEOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
G727 GRANT CONTINUITY MODULE
. . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
M688 POWER FAIL DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33
M5904 MASSBUS TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . 6·35
75113 Dual Differential Driver Chip . . . . . . . . . . . . . . . . . . . . . . . . . . 6.35
75107B Dual Differential Line Receiver Chips . . . . . . . . . . . . . . . . . . . . . 6·35
H870 TERMINATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
M8838 UNIBUS TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . 6-37
UNIBUS TERMiNATION . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . 6-37

CHAPTER 7

INSTALLA nON AND MAINTENANCE

7.1
7.2
7.2.1
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.3
7.2.4
7.2.4.1
7.2.4.2
7.2.4.3
7.3

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7·1
Electrical .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·1
Power Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1
Unibus Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1
Massbus Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7-3
AC LO, DC LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7-6
Small Peripheral Controller Slots . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-6
Jumper Configurations . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. 7·6
BCT Module . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . . 7·6
DBC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7·10
CSR Module
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7·10
VISUAL INSPECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

vii

CONTENTS (Cont)

Page
7.4
; 7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.S.5
7.5.6

INSTALLATION PROCEDURE FOR A TJU16 ADD-ON
RHll Installation . . . . . . . . . . .
TM02 and TU16 Installation . . . . . .
RH 11/TM02 Massbus Cable Installation
TM02/TUI6 Slave Bus Cable Installation
Markup of Masshw; and Slave Bus Cables
DIAGNOSTIC MAINTENANCE . . . . . . .
Data Reliability Diagnostic DZTUA
TM02/TU 16 Basic Function Diagnostic DZTUB
TM02/TUI6 Control Logic Test DZTUC
TM02 Drive Function Timer DZTUD
TU16 Utility Driver DZTUE
Data Tape Create DZTUF . . . . .

APPENDIX A

INTEGRATED CIRCUIT DESCRIPTION

. 7-11
7-11
7-11
7-13
7-13
7-17
. 7-17
7-17
7-18

7-18
7-19
7-19
7-19

ILLUSTRATIONS
Figure No.
1-1
1-2
1·3

14
1-5
1-6
1-7
1-8
1-9
1-10
2-1
3-1
3-2

3-3
34
3-5
3-6

3-7
3-8
3-9
3-10
·3-11
3-12

3-13
3-14
3-15
3-16
4-1

Title
RJTU16 Simplified System Diagram
TJU16 Simplified Block Diagram
RHll Multiport System . . . . . .
RH 11 Combined with Unichannel IS System
RHII Simplified Data Path Diagram . . . . . .
Reference Edge of Tape . . . . . . . . . . . . .
Track-Bit Weight Relationship for Nine-Channel Transport
NRZ Format (Nine-Channel)
PE Recording Format
Data Formats
Massbus Interface Lines
Device Register . . . .
RH 11/TM02 Register Summary
Control and Status Register I-Bit Usage
Word Count Register Bit Usage
Unibus Address Register Bit Usage .. .
Frame Counter Bit Usage
...... .
Control and Status Register 2-Bit Usage
Drive Status Register Bit Usage
Error Register Bit Usage . . . . . . .
Attention Summary Register Bit Usage
Check Character Register Format
Data Buffer Bit Usage
Maintenance Register Bit Usage
Drive Type Register Format
Serial Number Register Bit Usage
Tape Control Register Bit Usage
Rewind Operation Flowchart

viii

Page

1-1
1-2
14
1-5
1-7
1-8
1-8
1-9
1-11
1-12
2-2
3-2
3-9
3-10
3-12
. 3-13
3-14
3-14
3-17
3-20
3-26
3-28
3-29
3-30
3-34
3-36
3-36
4-2

ILLUSTRATIONS (Cont)
Figure No.
4-2
4-3
4-4

4-5

4-6
4-7
4-8

4-9
5-1
5-2
5-3

54
5-5
5-6
5-7
5-8
5-9
5-10
6-1
6-2

6-3
6-4

6-5

6-6
6-7
6-8
6-9
6-10
6-11

6-12
7-1

7-2

7-3
74
7-5
7-6

7-7
7-8

7-9
7-10
7-11
7-12
7-13

Title
Space Operation Flowchart
Erase Operation Flowchart
PE Dat1 Read Operation Flowchart
NRZ Data Read Operation Flowchart
PE Data Write Operation Flowchart
NRZ Data Write Operation Flowchart
Write Tape Mark Operation Flowchart
Error Termination . . . . . . . .
..... .
Register Control Path
Writing Remote Register Interface
Reading Remote Register Interface
DMA Data Path Block Diagram
Write Cycle Interface Diagram ..
Read Cycle Interface Diagram
Write Check Cycle Interface Diagram
Write Command Flow Diagram
Read Command Flow Diagram . . .
Write Check Command Flow Diagram
Write Unibus Timing Diagram
Read & Write Check Unibus Timing Diagram
Write Massbus Timing Diagram . . . . . . .
Read & Write Check Massbus Timing Diagram
Unibus Power Fail Drivers Schematic
Typical Differential Driver/Receiver Connection
Driver Termination . . . . . . . . . . . . . . .
Driver Chip Simplified Schematic . . . . . . .
Dual Differential Driver Pin Connection Diagram
Simplified Line Receiver Logic Diagram
75107B Differential Receiver Pin Connection Diagram
M8838 Unibus Transceiver Pin Connection Diagram
RHll Module Utilization
.......... .
Single Port Unibus Configuration
........ .
Dual Port Configuration - Memory on Unibus B
Dual Port Configuration - Memory & Processor on Unibus B
Massbus Cable System Configuration
........... .
Typical Power Fail Configuration for RHll & Options Mounted
in Same. Expander Box . . . . . . . . . . . . . . . . . . .
Typical Power Fail Configuration for Two RHlls Mounted
in Same Expander Box . . . . . . . . . . . . . . . . .
Typical Power Fail Configuration for RHll and CPU
Moun ted in Processor Box . . . . . .
Jumper Summary
.......... .
RH11 /TM02 Massbus Cabling Diagram
TM02/TU 16 Slave Bus Cabling Diagram
Massbus Cable Stamp
Marked-Up Massbus Cable . . . . . . .

Page
4-3
4-4

4-5

4-7
4-8

· 4-10
· 4-11
· 4-13

5-2

54
5-5
5-6
5-8
5-10
5-12
5-13
5-16
5-18

6-3
64
6-5
6-6

6-34
6-35
6-35
6-36
6-36
6-37

6-37
6-38
7-2

7-4
7-4

7-5
7-5

7-7
7-8

7-9
7-14

7-15
7-16

7-17
7-17

TABLES
Table No.
I-I
2-1

3-1
3-2

3-3
3-4

3-5

3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14

3-15

3-16
3-17
3-18
3-19
3-20

6-1
7-1
7-2

7-3

Title
Related Documentation
Massbus Signal Cable Designations
RBll and TM02!TU16 Device Registers
Results of Program-Controlled Clearing
Command Function Codes . . . . . . .
TJU16 Commands and Required Parameters
Control and Status Register Bit Assignments
Word Count Register Bit Assignments
Unibus Address Register Bit Assignments
Frame Counter Bit Assignments . . . . . . .
Control and Status Register 2 Bit Assignments
Drive Status Register Bit Assignments
Error Register Bit AsSignments . . . . . . . .
Error Conditions . . . . . . . . . . . . . . .
Attention Summary Register Bit Assignments
Check Character Register Bit Assignments
Data Buffer Bit Assignments . . . . .
Maintenance Register Bit Assignments
Drive Type Register Bit Assignments ..
Serial Number Register Bit Assignments
Tape Control Register Bit Assignments
Error Recovery Procedures . . . . .
Listing of RH11 Logic Diagrams ..
TU16 Backplane, Regulated Voltages
P4 Connector, Unregulated Voltages
TM02 Voltage Check . . . . . . . .

Page
1-3
2-4
3-3
3-4

3-5
3-7

3-11
3-13

3$13
3-14

3·15
3-18

3-21

3-25
3·27
3-29

3-29
3-30

3-35

3-36
3-37
3-42

6-2
7-12

7·12
7·13

CHAPTER 1
SYSTEM AND
PHYSICAL DESCRIPTION
1.1 GENERAL

The TM02 Tape Controller controls the tape motion and
read/write operations of the TU16 Tape Transport. It also
converts Massbus data (16-bit words) into tape characters
and vice versa. In addition, the TM02 provides formatting
control for data written on and read from tape. The TU16
Tape Transport transfers digital data to and from magnetic
tape as commanded by the TM02 Tape Controller.

This manual describes the TJU16 Magnetic Tape System
manufactured by Digital Equipment Corporation. This
system' consists of an RHII Massbus Controller, a TM02
Tape Controller(s), and TU16 Tape Transport(s) as shown
in Figure 1-1.
The RHII Massbus Controller interfaces with any PDP-II
processor via the Unibus and interfaces with the TM02
Tape Controller via the Massbus. The TM02 Tape Controller, in turn, interfaces with the TU16 Tape Transport
via the slave bus.

System capability will allow up to eight TM02 Tape
Controllers to be connected to one RHll Massbus Controller. Each TM02 Tape Controller, in turn, can have up to
eight TU16 Tape Transports connected to it as shown in
Figure 1-2. This provides a maximum capability of 64
TU16s for each Massbus Controller.

The RHll Massbus Controller provides an extremely
reliable mass storage system for large-scale data transfers.

PDP-11
CENTRAL
PROCESSOR

UNIBUS

-...,
I
I
MEMORY

RH11
MASSBUS
CONTROLLER

MASSBUS

--+-. . . /

I
I

I
~

I
I

TM02
TAPE
CONTROLLER

I
I

,L,7 L_
'v'

TU16
TAPE
TRANSPORT

I
I

TO OTHER DRIVES
II -.2620

Figure 1-1 RJTU16 Simplified System Diagram

1·1

PDP-l1
CENTRAL
PROCESSOR

UNIBUS A

CONTROL 6 DATA

MEMORY

RH11
D
DEVICE
A
CONTROLLER

UNIBUS B

MASSBUS

TM02
TAPE
CONTROLLER

TM02
TAPE
CONTROLLER
#N

SLAVE BUS

TUI6
TAPE
TRANSPORT

I~N!:7

TUI6
TAPE
TRANSPORT
#P

TUI6
TAPE
TRANSPORT

TU16
TAPE
TRANSPORT
#P

11-2621

Figure 1-2 TJU16 Simplified Block Diagram

1.1.1 Scope
This manual is designed to provide Digital's field service and
customer maintenance personnel with sufficient installation, operation, and servicing information to install and
maintain the RHll. Because the RHII is used with the
TU16/TM02 Tape System, a brief description of the
TU16/TM02 is included in this manual. Detailed information on the TU16/TM02 can be found in the TU16/TM02

A third configuration which may be employed occurs in a
multiprocessor environment. Figure 1-4 shows the RHll
system interfaced to a Uni-channel 15 system and a remote
processor. In this type of configuration. for example. the
PDP-} 5 can direct the PDP-II to transfe r da ta from
common memory to the tape drive. The da ta can then be
transferred to another memory bank associated with the
remote processor on Unibus B.

Tape Drive System Maintenance Manual.
1.2.2 Massbus
The Massbus provides a parallel data path between the
RHll and the TM02 Tape Controller, and has a maximum
cable length of 120 ft, allowing 15ft between TM02
Controllers if the "daisy-chain" configuration (with a
maximum of 8 controllers) is employed. The Massbus
comprises two sections: an asynchronous control bus and a
synchronous data bus for high-speed data transmission.

1.1.2 Related Documentation
Table 1-1 lists related documentation that supplements the
information in this manual.
Table 1-1
Related Documentation
Title

Document Number

PDP-II Peripherals and
Interfacing Handbook

112.01071.1854

TUI6/TM02 Tape System
Main tenance Manual

DEC-00-HTUI6-A-D

Digital Logic Handbook

058.00173.2505

The asynchronous control bus:

1.2 BUS INTERFACES
The PDP-II Unibus provides the interface between the
PDP-II central processor and the RHII Massbus Controller
(Figure I-I). The Massbus provides the interface between
the RHII Massbus Controller and the TM02 Tape Controller. The slave bus provides the interface between the
TM02 Tape Controller and the TU16 Transports (designated slaves). These buses are described briefly in the
following paragraphs.

Transmits commands and information from the
controller to the drive to read or write drive
registers.

Notifies the controller when an unusual (attention) condition exists in one or more drives.

Transmits status information from the drive to
the con troller, and

Provides a master reset to all drives from the
controller.

The synchronous data bus transmits blocks of data at high
speed between the RHl1 Controller and the TM02 Controller and controls the initiation and termination of block
transmissions. Because the data and control buses operate
independently, the Massbus controller can monitor drive
status on the control bus while a data transfer operation on
the data bus is being performed. Additional details on the
Massbus can be found in Chapter 2.

1.2.1 Unibus
All data transfers between memory and the RHII are
accomplished via the NPR data transfer facilities of the
Unibus. The RHII contains two Unibus ports: one
designated a control port, the other a data port. Data may
be transferred through either port using the NPR transfer
facility. For normal operation, with memory connected to
Unibus A as shown in Figure 1-2, the data port is not used
and the control port serves for both control and data
transfers. When memory is connected to Unibus B, a
programmable port select bit can cause data to be routed
through the data port. Figure 1-3 shows a system configuration using multiport memory and both the control and data
ports.

1.2.3 Slave Bus
All TU16s controlled by a TM02 are "daisy-chained" on
the slave bus (Figure 1-2). Essentially, this means that the
TU16s are configured parallel to each other. The slave bus
consists of slave select lines, write data lines, read data lines,
transport control lines and various TU16 status lines. The
various signals on the slave bus are tabulated in the

TU16/TM02 Tape Drive System Maintenance Manual.

1-3

UN' BUS B (DATA)

,--

--,

MOS/BIPOLAR
MEMORY

IL_

_.J

MULTIPORT
CORE
MEMORY

U
N
I

B
U
S
A
PDP-11
CENTRAL
PROCESSOR

UNIBUS A (CONTROL or DATA)

RH11
MASS BUS
CONTROLLER

TM02
TAPE
CONTROLLER
(1 TO 8)

TU16
TAPE
TRANSPORT
(1 TO 8 PER
TM02)

11 -2622

Figure 1-3 RHII Multiport System

ruN~A;;EL~
SYSTEM

- - - - - -

I
I
I
I

I
I

TO ANOTHER
PROCESSOR'S
MEMORY

CORE
MEMORY

I
I
I
I
I

MEMORY
BUS

I
I
I
I
I
I

-l

MX15-B
MULTI PLEXER

U
N
I
B
U

S
B

I
18- BIT UNIBUS

IIO BUS

PDP-15
CENTRAL
PROCESSOR

DRI5-C
DR11-C
INTERRUPT
LINK

RH11
MASS BUS
CONTROLLER

TM02
TAPE
CONTROLLER
(1 TO 8)

TU16
TAPE
TRANSPORT
(1 TO 8 PER
(TM02)

PDP-11
CENTRAL
PROCESSOR

L___________ .J
11-2623

Figure 1-4 RHl1 Combined with Unichannel 15 System

1.3 RHll MASSBUS CONTROLLER
ll1e RHll
Controller, in conjunction with the
TU16/TM02, provides a fast and reliable mass storage
system that can be employed in timesharing or real-time
data storage applications. The following major functions are
performed by the RHII :
a.

Interfaces with one or two Unibus cables and
signals.

Communicates directly with the main memory
to fetch and store data.

Communicates with the central processor to
receive commands, provides error and status
information, and generates interrupts.

Interfaces with one to eight tape controllers.

The controller places a register select code on
the Register Select lines.

The controller asserts CTOD H (Controller-ToDrive).

The con troller places data on the Control lines.

The controller then asserts DEM H.

The selected TM02 responds to OEM II and CTOD H
asserted by loading the selected register with the data on
the Control lines. Then it asserts TRA H. The controller
responds by negating OEM H, which causes the TM02 to
negate TRA H; the write operation is thereby terminated.
A TM02 register is read in a similar manner except that
CTOD H is negated (step 3) and step 4 is eliminated l11e
selected TM02 responds to OEM II asserted and CTOD H
negated by gating out the contents of the selected register
onto the Control lines. The TM02 then asserts TRA H to
the controller. The controller then strobes in the data on
the Control lines and negates OEM H. TIle TM02 responds
by negating TRA H, thereby terminating the operation.

The RHII is divided into two major functional groups: the
register access control path, and the DMA (direct memory
access) data path (Figure 1-5). The register access control
path allows the program to read from or write into any
register con tained in the RHl1 or in the selected tape drive.
There are a total of four registers in the RHl1, nine
registers in each TM02, and one shared register which is
partially contained in the RHll and partially contained in
the selected TM02.

Accesses to a TM02 register via the control bus portion of
the Massbus do not interfere with data transfer operations
occurring over the data bus portion of the Massbus.

TI1e DMA data path functionally consists of a 66-word by
IS-bit first-in, first-out memory and associated control
logic. The major function of this memory (hereafter
referred to as the Silo) is to buffer data to compensate for
fluctuations in NPR latency time on the Unibus.

1.3.2 DMA Data Path
The DMA data path is used for the act.ual transfer of blocks
of data and functionally consists of the synchronous (data)
portion of the Massbus, a Silo memory, and the Unibus
NPR logic. The Silo memory compensates for fluctuations
in NPR latency times by buffering data between the Unibus
and Massbus data bus during DMA transfers.

1.3.1 Register Access Control Path
When a PDP-II instruction addresses the RHII to read or
write any device register in the RHll or in the drive, a
Unibus cycle is initiated and this data is routed to or from
the RH II (refer to Chapter 3 for a detailed description of
the registers). If the register to be addressed is local
(contained within the RHll), the register control logic
immediately gates the data to or from the appropriate
register.

Figure 1-5 is a simplified block diagram of the DMA data
path. A single Unibus configuration is shown with Unibus A
serving as both the control port and the data port.
1.4 TUI6/TM02 TAPE SYSTEM
The TU16/TM02 is a Massbus-compatible, versatile tape
drive system, consisting of a TM02 Tape Controller and
TU16 Tape Transport(s). The rUI6/TM02 records and
reads digital data in industry standard PE or NRZ mode at a
maximum data transfer rate of 72,000 tape characters per
second. Tape density and tape character format are
program selectable. Forward/reverse tape speed is 45 in/sec,
while rewind is performed at 150 in/sec. The TUI6/TM02
Tape Drive System also has forward and reverse read/space
capability.

If the register to be accessed is remote (contained in the
TM02 Controllers), the register access control logic initiates
a Massbus control bus cycle. TM02 registers are loaded in
the following manner:

The controller places the drive select code of
the desired TM02 on the Drive Select lines.

1-6

RH 11

I/O CONTROLLER

r;E~T~ A~S~O~O~AT;-

--------

I
I

I
PROGRAM
CONTROLLED
TRANSFERS

I
I

RH 11

DEVICE REGISTERS

MTCS 1 CONTROL AND STATU S 1
(shored with the drive)
REGISTER
ACCESS
CONTROL

I
I

LOCAL
REGISTERS

MASSBUS
CONTROL
BUS
LOGIC

MTCS 2 CONTROL AND STATUS 2
MTD8 DATA BUFFER
MTWC WORD COUNT
MTBA BUS ADDRESS

REMOTE REGISTERS

I
L....

ro MAD ATA pATH (DiRECTMEMORYACCESS)

U
N
I

NPR

TRANSFERS

OBUF
OUTPUT
BUFFER

I
I
I
I
I
I

MASS BUS
CONTROL BUS

I
M

I
I

S
S
B
U
S

..J
I

UNI B,...U_S_-'-___

- - - -l

DATA TO MASSBUS

DATA TO

OBUF
FULL
FLAG

ORDY (OUTPUT READY FLAG)
LAST CELL~------------------------------~--------~

1-----64 WORD
SILO
(FIRST IN,
FIRST OUT)

SILO
CONTROL
LOGIC
I ROY ( I NPUT READY FLAG)

IBUF
INPUT
BUFFER

DATA FROM
UNIBUS

DATA FROM MASSBUS

MASSBUS
DATA BUS
CONTROL

I
I
I
I

--~-II -2633

Figure 1·5 RHII Simplified Data Path Diagram

The TU16/TM02 Tape System performs the following
functions:
a.

Records and plays back data.

Generates tape marks to separate files.

Provides clock signals to synchronize data
transmission between drive and controller.

Maintains error and status indicators and
generates an Attention signal when exceptional
conditions occur.

TAPE
LEADER

..4"1...---- SUPPLY
REEL

Locates data records by the spacing function.
10-1265

Provides mechanisms
diagnostic testing.

for

maintenance and
Figure 1-6 Reference Edge of Tape

Performs error detection on the data and
provides error correction in PE (phase-encoded)
mode only.

BIT WT TRACK

The major assemblies of the TU16(fM02 Tape System
include the TU16 Tape Transport, the TM02 Tape Con·
troller, the H740D Power Supply for the TM02, and the
861 Power Controller which controls power in the
TUI6/TM02 Cabinet.
1.5 MAGNETIC
DEFINITIONS

TAPE

22 - 1 -

RD 0

20 - 2 -

RD 1

24_- 3 -

RD 2

P --4-

RD 3

25 -5-

FUNDAMENTALS

28 - 6 -

RD 5

27_7-

RD 6

2'-B-

RD 7

23 - 9 -

RD P

READ AMPS

Reference Edge - The edge of the tape as defined by
Figure 1.6. For tape loaded on a TU16, the reference edge
is toward the observer.

READ HEAD
10-1264

Figure 1·7 Track·Bit Weight Relationship for
Nine-Channel Transport

BOT (Beginning Of Tape) Marker - A reflective strip
placed on the non-oxide side of the tape, against the
reference edge, 15 ft (± 1 ft) from the beginning of the
tape.

File - An undefined number of records (minimum = zero,
no maximum).

EOT (End Of Tape) Marker - A reflective strip placed on
the non-oxide side of the tape, against the nonreference
edge, 2S to 30 ft from the trailing edge of the tape.

Interrecord Gap (IRG) - A length of erased tape used to
separate records (0.5 in. minimumJor nine-track; maximum
IRG is 2S ft).

Nine-Channel Recording - Eight tracks of data plus one
track of vertical parity. Figure 1-7 shows the relationship
between track and bit weight for a nine-channel transport.

Extended IRG - A length of erased tape (3 in. minimum)
optionally used to separate records.. It must be used
between BOT and the first record.

Tape Character - A bit recorded in each of the nine
channels.

Tape Speed - The speed at which tape moves past the
read/write heads; normally stated in inches per second.

Record - A series of consecutive tape characters.

1·8

Cyclic Redundancy Check Character (CRCC) - A check
character that is written four character spaces after the last
character of an NRZ record (nine-channel only). CRCe is
derived by a complex mathematical formula applied to the
characters written in the record. The resul t of this
manipulation (CRCC) can be used to recover a lost bit in a
record read from tape. CRCC error recovery hardware is
not available. in the TU16/TM02, but CRce is written for
purposes of compatibility.

Tape Density - The density of sequential characters on the
tape. It is normally specified in bytes per inch (bpi), which
is equivalent to characters per inch (cpi), since 800 bpi
means that there are 800 tape characters per inch of tape.

Write Enable Ring - A rubber ring which must be inserted
on the supply reel to allow the transport to write on the
particular tape. This safety feature helps prevent accidental
destruction of previously recorded data.

Longitudinal Parity Check Character (LRCC) - A check
character written four character spaces after CRCC (ninechannel). LRCC consists of one bit of even parity for each
track of data. For example, if track 1 had an odd number
of Is written in a record, then a 1 must be written in the
LRCC bit associated with track 1.

Tape Mark (TM) - A record written on the tape to
designate the end of a file; sometimes referred to as a file
mark (FMK). In the TU16/TM02, the tape mark is always
preceded by an extended IRG.

Tape Mark - A nine-channel NRZ tape mark consists of
one, tape character (23 8 ), followed by seven blank spaces,
and then LRCe (23 8 ), (CRCC is not written.) Figure 1-8
illustrates nine-channel NRZ tape format.

1.6 TUI6/TM02 RECORDING TECHNIQUES
1.6.1

NRZI (Non-Return to Zero - Change on a 1)

1.6.1.1 Definition - NRZI is a recording technique which
requires a change of state (flux change) to write a 1, and no
change of state (no flux change) to write a O.

1.6.2 PE (Phase Encoding)
1.6.2.1 Definition - Phase encoding is a recording
technique in which a flux reversal occurs for each bit of
information written on the tape. A 1 can be defined as a
positive level followed by a negative transition, while a 0
can be defined as a negative level followed by a positive
transition.

1.6.1.2 Format -- A record is a minimum of 12 characters.
A CRCC character occurs four character spaces after the
record. An LRCC character occurs four character spaces
after the CRCC (Figure 1-8).

OXIDE SURFACE

TAPE MARK

•
I
I
IL _ _ _ _ ....I

REFERENCE
EDGE
BOT MARKER
ON OTHER)
SIDE OF
(
TAPE

EXTENDED
IRG

EOT MARKER
TAPE MARK
CHARACTER

CRCC

(

ON OTHER)
SIDE OF
TAPE
10-1263

Figure 1-8 NRZ Format (Nine-Channel)

1-9

Sequential flux transitions on the tape are either at the data
rate or at twice the data rate. Sequential Is or sequential Os
will cause flux reversals to occur at twice the data rate:

II
I

Zeros in the preamble are used to set the window in
position when reading in a forward direction, while Os in
the postamble perform this function when reading in the
reverse direction. The all-Is character in the preamble and
postamble is used to mark the beginning of data.
Tape .Mark - A PE tape mark consists of forty Os in tracks
2, 5, and 8 (bit positions 0, 5, and I) with tracks 3, 6, and 9
(bit positions 4, 6, and 3) erased.

I
0

010

Identification Burst (IDB) - The lOB identifies the tape as
a PE tape. It consists of alternating Is and Os in the parity
track (track 4) with all other tracks erased. The lOB is
located at BOT, and has a minimum length of 1.7 in. Figure
1-9 illustrates PE tape format.

10-1271

Alternate Is and Os cause flux reversals to occur at the data
rate:

1.7 TJU16 SPECIFICATIONS
This paragraph defines the parameters in the TJU16
Magnetic Tape Subsystem.

~I
I I I I I y

1. 7.1 Data Format
Data Format is selected by the format select bits (FMT
0-3) in the tape control register as follows:

10-1269

FMT (0-3)

1.6.2.2 Format - To ensure proper extraction of PE data
from the serial stream of transitions coming off the tape,
PE data must be recorded in a precise format. A PE record
consists of preamble, data, and postamble.

Data - The data consists of flux reversals for each bit of
information. Negative flux reversals designate Is while
positive flux reversals designate Os.

r+ r+ r-h rh rf,
t t l 1 Ll t
o

~
1 WIL
.JiU1LJIUlUILJ

Normal Mode
Core Dump
15 Mode

---....-.-..----

Packing Density
200,556,800, and 1600 bpi; program selectable.
Tape Speed
Forward/Reverse: 45 in/sec (1.14 m/sec)
Rewind: 150 in/sec (3.8 m/sec)
Maximum Transfer Rate
72,000 characters/sec
Tape Motion Times
Start: Normal operating speed is reached within 9 ms
after initiation of forward or reverse command.

ffi-rtl--h+-rh-HI
0

0
1
0

1.7.2 TU16/TM02 Specifications

The PE read electronics uses a data window to isolate data
transitions. For example,

DATA TRANSITION

0
0

Figure 1-10 shows the three modes in the TJU16 system normal mode, core dump mode and 15 mode. In 15 mode,
bit 15 in memory corresponds to Massbus data bit DO, and
bit 0 in memory corresponds to Massbus data bit D17.

Postamble - One character of 1s in all nine tracks followed
by 40 characters of Os in all nine tracks.

WINDOW

2
1
1
1

Preamble - Forty characters. of Os in all nine tracks
followed by a character of Is in all nine tracks.

DOT'

Mode

Bit
3

Stop: Motion stops in less than 8 ms after removal of
forward or reverse command.

10-1270

1-10

!.7"MIN.

~TENDED lRG
IRG
'.O"MIN.-~-----RECORD -----~---0.6" NOMINAL----e.i

PREAMBLE: 41 CHAR.

\ 4 - - - - - DATA ----~i

0.5"MIN.

2 3 9 I I I I I I I I I I I r II I I

)1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - - - - - - - - - 1 1 "

8 I III I III III II II I

)11111111111111111------------1111111

7 II II II I I I I 1111 I I

I I I I I I I III I I I I I II

II I I I I ~

2 6 6 I II I I I I I I III I I I I

}tlllllllllllllill

5 I I I II I I I I I II I II I

11111 II 1111 I " 1 1 1 - - - - - - - - - - - - 1 1 I II I II

41111111111111111

1111111

11111111111111111------------1111111

~ IIIIIIIIIIIIIIIII------------IIIIIII~

IDENTIFICATION BURST

~ II I I I I I I I II I I I I I I

r--------lI
:L. _BOT
TAB :
_ _ _ _ _ -"'

........-::LEAST SIGNIFICANT

III I I I I

? I I I I I I I I I I I I I I I I I - - - - - - - - - - - - I l l 1111

TRACK NUMBER
NOTE

........-::-:=MOST SIGNIFICANT

I II

I
1111111111111111111111

f.ot-- POSTAMBLE : 41 CHAR.

REFERENCE EDGE

1. TAPE IS SHOWN WITH OXIDE SIDE UP.
10-1280

Figure 1-9 PE Recording Format

Electrical Skew
Write deskew only. Read skew mechanically aligned.
Recording Method
NRZI or PE recording; industry-compatible.
Transport Mechanism
Single capstan; vacuum columns
Read/Write Heads
Dual gap, read after write.
BOT, EOT Detection
Photoelectric sensing of reflective strip
Interrecord Gap
0.5 in. minimum, 0.65 in. nominal
Tape
Width: 0.5 in.
Thickness: 1.5 mils
Take-up Reel
Diameter: 10-1/2 in. (For 1600 BPI mode, the tape
should be certified at 3200 flux changes per inch.)

Voltage Requirement
TUI6: 115/230 Vac ± 10% at 50/60 Hz ± 2%
TM02: 90-135 Vac; 180-270 Vac at 47-63 Hz
Power Dissipation
TUI6: 1000 W max
TM02: 300 W max
TU16 Transport (without cabinet)
Depth: 25 in. (0.64 m)
Width: 19 in. (0.48 m)
Height: 26 in. (0.66 m)
Weight: 150 lb (70 kg)
TM02 Tape Controller
Depth: 23 in. (0.58 m)
Width: 19 in. (0.48 m)
Height: 7 in. (0.17 m)
Weight: 45 lb. (21 kg)
TM02 Power Supply (H740D)
Depth: 8 in. (0.18 m)
Width: 19 in. (0.48 m)
Height: 5 in. (0.13 m)
Weight: 24 lb. (11.2 kg)

Capacity: 2400 ft
Power Control
861 Power Controller

1-11

PDP-"
CORE WORD
LSB

MASSBUS
DATA WORD

BIT WEIGHT

~00}

I" CHARACTE R
WRITTEN

DB}
1
MSB

2nd CHARACTER
WRITTEN

2 1S

.. 015
016
017

R15

o. Normol Mode

MASSBUS
DATA WORD

PDP- "
CORE WORD
LSB

BIT WEIGHT

~ 00}
+ 1st CHARACTER

2°

WRITTEN

or }

2"d CHARACTER
WRITTEN

DB}
+
on

3rd CHARACTER
WRITTEN

MSB

012} 4th CHARACTER
WRITTEN
II 015
016
017

R15

b. Core

Dump Mode

PDP-15
CORE WORD
LSB

MASSBUS
DATA WORD

BIT WEIGHT

~ 00 } 2 nd CHARACTER

N17

2°

WRITTEN

MSB

2 15

08
~ } 1st CHARACTER
WRITTEN

.. 016

.. 017

2 15

015

Mode
10-1326

Figure 1-10 Data Formats

1-12

861 Power Controller
Depth: 8 in. (0.20 m)
Width: 19 in. (0.48 m)
Height: 5 in. (0.13 m)
Weight: 101b (4.54 kg)
Environmental Limits
Temperature: 60° to 95° F)
(15° to 35° C)*
Relative Humidity: 20 to 80% (no condensation)*
1.7.3 RUll Controller Specifications
Mechanical
Consists of a double hex-height system unit that mounts in
a BAll-FA, BAll-FB, BAll-BA, or BAll-BB mounting
box (not supplied). Module usage is as follows:
RHll Logic: 2 hex-height, 2 double-height modules.
Massbus Controller Transceivers: 3 double-height
modules.
Unibus Cable Slots: 4 double-height cable slots.
Power Fail: 2 single-height modules.
Small Peripheral Controller Slots (spares): 3 quad-height
module slots available.
Electrical
Power Requirements (RHll):
+5.0 ± 0.25 Vdc at 19.0 A max
-15.0 ± 1.5 Vdc at 0.58 A max
Logic Voltage: H ~ +3 V, L ~ 0 V

Power Requirements (Small Peripheral Controllers):
+5.0 ± 0.25 Vdc at up to 6.0 A max for three small
peripheral controllers (SPC).
Also, -15 Vdc, LTC, & +15 Vdc are provided for SPC
use.
Environmental
Temperature: 32°-122° F (0° _50° C) Qass C
Relative Humidity: 8% to 90%, no condensation
Vibration Shock: 1.89 G nns, 10-300 Hz
20 G, half sine, 30 ms duration, any
plane
Data Transfers Memory/Controller
Accomplished via the NPR facility of the Unibus. Data
can be transferred on either of two Unibuses (program
selected). An 18-bit data path is optional (PDP-IS
configuration uses Unibus PA and Unibus PB lines as
data).
Data Transfer Controller Tape Drive
All controller/disk transfers are accomplished as l8-bit
parallel words over the synchronous section of the
Massbus.
Recoverable Error Rate
Less than one recoverable error in I X 108 bits read. A
recoverable error is defined as an incorrect transfer of
data from tape that occurs only once in four successive
retries.
Non-recoverable Error Rate
Less than one error in 1 X 10 9 bits transferred.

*Magnetic tape operation is more reliable if the temperature is
limited to 65° to 75° F (18° to 24° C) and the relative humidity to
40 to 60%.

1-13

CHAPTER 2
MASSBUSINTERFACE

2.1 GENERAL
The Massbus provides the interface between the RHII
Controller and the TUI6/TM02 Tape System. The Massbus
can be up to 120 ft in length and up to eight drives may be
connected in a daisy-chain configuration. The Massbus
. consists of two sections - a data bus section and a control
bus section. These buses are described in the following
paragraphs.

End-of-Block (EBL) - This signal is asserted by the drive
for one word time at the end of each sector (after the last
SCLK pulse). For certain error conditions, where it is
necessary to terminate operations immediately, EBL is
asserted prior to the normal time for the last SCLK. The
data transfer is terminated prior to the end of the sector in
this case.
Exception (EXC) - This signal is asserted when an abnormal condition occurs in the drive. The drive asserts this
signal to indicate an error during a data transfer command
(Read, Write, or Write-check). Exception is asserted at OJ
prior to assertion of EBL and is negated at the negation of
EBL.

2.2 DATA BUS
The data bus section of the Massbus consists of a 19-bit (18
data bits plus parity bit) parallel data path and six control
lines (Figure 2-1).

Parallel Data Path - The parallel data path consists of an
I8-bit data path designated DOO through D17 and an
associated parity bit (DPA). The data path is bidirectional
and employs odd parity. Data is transmitted synchronously,
using a clock generated in the drive.

Sync CLK (SCLK), Write CLK (WCLK) - These signals are
the timing signals used to strobe the data in the controller
and/or in the drive. DUring a read operation, the RHII
strobes the data lines on the negation of SCLK and the
drive changes the data on the assertion of SCLK. During a
write operation, the controller receives SCLK and echoes it
back to the drive as WCLK. On the assertion of WCLK, the
drive strobes the data lines and on the negation of WCLK,
the controller changes the data on the data lines.

RUN - After a data transfer command has been written
into the con trol register of a drive, the drive connects to the
data bus. The controller then asserts the RUN line to
initiate the function.

2.3 CONTROL BUS
The control bus section of the Massbus consists of a 17-bi1
(16 bits plus parity) parallel control and status data path,
and 14 control lines (Figure 2-1).

Occupied (OCC) - This signal is generated by the drive to
indicate "data bus busy." As soon as a valid data transfer
command is written into a drive, and the command is
accepted, the drive asserts OCC. Various errors may cause a
drive to be unable to execute a command. The controller
will time out in these cases due to no assertion of OCC or
of SCLK, and the MXF (Missed Transfer Error) will be set
in the controller. OCC is negated at the trailing edge of the
last EBL pulse of a transfer.

Parallel Control and Status Path - The parallel control and
sta tus path consists of a 16-bit parallel data path designated
COO through CIS and an associated parity bit (CPA). The
control and status lines are bidirectional and employ odd
parity.

2-1

DATA AND PARITY

[0 (17 : 00) a OPAl

RUN
;

OCCUPIED (OCC)
DATA
BUS

-"
V

ENo-OF-BlOCK lEBl)
~

EXCEPTION (EXC)
SYNC ClK (SClK)
WRITE ClK (WClK)

(
RH"
CONTROllER

CONTROL. STATUS 8 PAR ITY [C (15:00) 8 CPA]

)

....

II'"

DRIVE SELECT (0502 - oSOO)

Po..

DI$,<
DRIVE

)

v
CONTROL TO DRIVE (CTOo)
REGISTER SELECT (RS04: RSOO)
CONTROL
BUS

lot..

)
II'"

DEMAND (OEM)
TRANSFER (TRA)
ATTENTION (ATTN)
INITIALIZE {IN IT)
FAil

Figure 2-1 Massbus Interface Lines

Drive Select DS (2:0) - These three lines transmit a 3-bit
binary code from the controller to select a particular drive.
The drive is linked to the control bus when the (unit) select
number in the drive corresponds to the transmitted binary
code.

Register Select RS (4:0) - These five lines transmit as-bit
binary code from the con troller to the selected drive. The
binary code selects one of the drive registers.

Controller-ta-Drive (CTOD) - This signal is generated by
the controller and indicates the direction in which control
and status information is to be transferred. For a controHer-to-drive transfer, the controller asserts CTOD. For a
drive-to-controller transfer, the controller negates this
signal.

NOTE
Ten registers (including the MTCSI register) are
present in the TM02 Tape Controller designated
by codes 00 through 11.' If a register code
higher than 11 is selected, an Illegal Register
(ILR) Error occurs.

2-2

The AT A bit in a drive may be cleared by the followin~
actions:

Corresponds To:
Massbus
Address

00
01
02
03
04
05
06
07
10
11

Control & Status 1 Register
Drive Status
Error
Main tenance
Attention Summary
Frame Count
Drive Type
Check Character
Serial Number
Tape Control

Unibus
Register Address
Mnemonic (octal)
MTCSI
MTDS
MTER
MTMR
MTAS
MTFC
MTDT
MTCK
MTSN
MTTC

a. Asserting INIT on the Massbus (affects all eigh'
drives).

772440
772452
772454
772464
772456
772446
772466
772460
·772470
772472

b. Writing a 1 into the Attention Summary register (ir
the bit position for this drive). This clears the AT)
bit; however, it does not clear the error.
c. Writing a valid command into the Control registel
(with the GO bit set). Note that clearing the ATA bi1
of one drive does not always cause the ATTN line tc
be negated because other drives may also be assertin!
the line.

Demand (DEM) - This signal is asserted by the controller
to indicate a transfer is to take place on the control bus.
For a controller-to-drive transfer, Demand (DEM) is
asserted by the controller when data is present and settled
on the control bus. For a drive-to-controller transfer, DEM
is asserted by the controller to request data and is negated
when the data has been strobed off the control bus. In both
cases, the RS, DS, and CTOD lines are generated and
allowed to settle before assertion of DEM.

NOTE
There are three cases in which AT A is not reset
when a command is written into the Control
register (with the GO bit set). These are: (a) if
there is a Control Bus Parity Error on the write,
(b) if an error was previously set, or (c) if an
illegal function code (ILF) is written.

Initialize (INIT) - This signal is asserted by the controllel
to perform a system reset of all the drives. It is asserted
when a 1 is written into the CLR bit (bit 05 of MTCS2) 01
when Unibus INIT is asserted on Unibus A. When a drive
receives the INIT pulse, it immediately aborts the execution
of any current command and performs all actions described
for the Drive Clear command.

Transfer (TRA) - This signal is asserted by the drive in
response to DEM. For a controller-to-drive transfer,
Transfer (TRA) is asserted when the data is strobed and'is
negated when DEM is negated. For a drive-to-controller
transfer, IRA is asserted after the data is asserted on the
bus and negated when the negation of DEM is received.

Fail- When asserted, this signal indicates a power-fail
condition has occurred in the controller. In particular, the
drive inhibits reception of the INIT and DEM signals at the
drive.

Attention (A TTN) - This line is shared by all eight drives
attached to a controller; it may be asserted by any drive as
a result of an abnormal condition or status change in the
drive. An ATA status bit in each drive is set whenever that
drive is asserting the ATTN line. ATTN may be asserted due
to any of the following conditions:

2.4 COMMAND INITIATION
To initiate a command ina drive via the Massbus, the
controller (or the central processor via the controller)
writes a word in the MTCS 1 register which causes a word to
be written into the drive's Control register (00). The word
. contains a command function code in bits 05 through 01
and a GO bit in bit 00. The GO bit is set when initiating a
command. If the command specified is valid, the drive
which has been addressed by the program executes the
command.

a. An error while no data transfer is taking place
(asserted immediately).
b. Completion of a data transfer command if an error
occurred during a data transfer (asserted at the end of
the IRA).
c. Completion of a non-data transfer command (such as
a space).

2-3

Table 2-1 shows the Massbus signals and their associated pin
assignments.

:ommands are of two types: non-data transfer commands
:such as Drive Clear, space) and data transfer cOnullands
~such as Read, Write, and Write-check). The command
t-unction code bits (05 through 00 including GO in MTCS 1)
ue 018 through 478 for non-data transfer commands and
are 518 through 778 for data transfer commands.

Table 2-1
Massbus Signal Cable Designations
Pin*

Cable
2.4.1 Non-Data Transfer Commands
Non-da ta transfer commands have effect only on the state
of the drive~ The controller merely writes the command
word (with GO bit set) into the drive's Control register. At
the completion of the command execution, the drive
typically asserts the ATTN line to signal its completion.

Massbus
Cable A

1
2
3
4
5
6
7
8

K
L

B
C

D
E

If the non-data transfer command code written into the
drive is not recognized by the drive as a valid command, the
drive will immediately signal an error by asserting the
ATTN line. The megal Function Error (ILF) is set.

M
N
P
R
S
T
U

2.4.2 Data Transfer Commands
When any data transfer command code (with the GO bit
set) is written into the drive's Control register, the
controller expects data transfer on the data bus to begin
soon thereafter. The controller resets its ROY (Controller
Ready) bit as soon as the data transfer command code is
written into a drive. The drive normally responds by
asserting the OCC line. The controller asserts RUN and then
data is transferred to Of from the specified drive.

Polarity

Designation

MASS 000

+
+

MASS DOl

MASS D02

+
+

MASS 003

MASS 004

+
+

MASS 005

MASS COO

+
+

MASS COl

9
11

12
13
14
15
16
17
V
18
W
19
X
20
Y
21
Z
22
AA 23
BB 24
CC 25
DO 26
EE 27
FF 28
HH 29
11
30
KK 31
LL 32
MM 33
NN 34
pp
35
RR 36
37
SS
TT 38
UU 39
W 40

If an error occurs in a drive during a data transfer
command, the drive asserts the EXC line. This line remains
asserted until the trailing edge of the last EBL pulse. The
RHl] Controller always negates the RUN line when it
detects EXC asserted, so that data transfer is terminated at
the end of the record in which the error was signaled.

2.5 MASSBUS PHYSICAL DESCRIPTION
The Massbus consists of 56 signals including data, control,
status, and parity. These signals are routed between the
RHII and the drives by three 40-conductor flat cables.
Since Massbus signal transmission (with exception of the
FAIL signal) is accomplished by differential transmitter!
receiver pairs, each cable can accommodate 20 differential
signals.
On the drive end, the cables are plugged into M5903
Massbus Drive Transceiver modules (slots A, B4, 5, 6 in the
TM02). The last drive has M5903-YA modules which
terminate the buses. On the controller end, each cable plugs
in to a M5904 Massbus Controller Transceiver module
(described in subsequent paragraphs). Each M5904 module,
in turn, plugs into a slot (slots C, 0-4, 5, 6) in the RHII
backplane to complete the signal path.

,..,---

MASS CO2

+
+

MASS C03

MASS C04

+
+

MASS COS

MASS SCLK

+
+

MASS RS3

MASS ATTN

MASS RS4

+
-

MASS CTOD

MASS WCLK

MASS RUN

SPARE
GND

... Alternate pin designation schemes

Note: Massbus cables are to be installed per markings on the

Table 2-1 (Cont)
Massbus Signal Cable Designations

Table 2-1 (Cont)
Massbus Signal Cable Designations
Pin*

Cable
Massbus
Cable B

Polarity

2
C
3
D
4
E
5
F
6
H
7
J
8
K
9
L
10
M
II
N
12
P
13
R
14
S
15
T
16
17
U
V
18
W
19
X
20
y
21
Z
22
AA 23
BB 24
CC 25
DD 26
EE 27
FF 28
HH 29
JJ
30
KK 31
LL 32
MM 33
NN 34
PP 35
RR 36
SS
37
TT 38
UU 39
VV 40

+
+

A
B

+
+
-

+
+

Cable

Designation

Massbus
Cable C

MASS 006
MASS 007
MASS D08
MASS 009
MASS 010
MASS D11

+
+

MASS C06
MASS C07

+
+

MASS C08
MASS C09

+
+

MASS CIO
MASS CII

+
+

MASS EXC
MASS RSO

MASS EBL

MASS RSI

+
-

+
+

MASS RS2
MASS INIT

MASS SP}

SPARE
GND

Pin*

Polarity

1
2
3
4
5
6
H
7
J
8
K
9
10
L
M
11
N
12
P
13
R
14
S
15
16
T
U
17
V
18
W
19
X
20
y
21
Z
22
AA 23
BB 24
CC 25
DD 26
EE 27
FF 28
HH 29
11
30
KK 31
LL 32
MM 33
NN 34
PP 35
RR 36
37
SS
TT 38
UU 39
VV 40

MASS D12

+
+

MASS D13

A
B
C
D
E
F

*Alternate pin designation schemes

2-5

Designation

MASS DI4

+
+

MASS D15

MASS D16

+
+

MASS D17

MASS DPA

+
+

MASS C12

MASS C13

+
+

MASS CI4

MASS C15

+
+

MASS CPA

MASS OCC

+
+

MASS DSO

MASS TRA

MASS OSl

+
-

MASS OS2

+
+

MASS OEM

MASS SP2

MASS FAIL
GNO

CHAPTER 3
OPERATION AND PROGRAMMING
Ready, Drive Ready (RDY, DRY) - RDY is the "ready"

3.1 GENERAL
Fourteen 16-bit registers are employed to interface the
RHl1 Massbus Controller to the TM02/TUI6 tape system.
These registers are loaded and read under program control
via Unibus A (the control port of the RHll). Data may
sometimes be transferred over a second Unibus (Unibus B)
called the 'data port' of the RHl1. The tape system is
monitored by status and error indicators in these registers.
Figure 3 -1 shows the· various device registers and their
locations. Four of the fourteen registers are located entirely
in the RHll and nine are located entirely in the TM02. The
fourteenth register (MTCSI control and status register) is
shared by both the RHl1 and the TM02. Bits 15 through
13 and bits 10 through 6 of this register are stored in the
RH 11 while bits 12, 11, and 5 through 0 are generated by
the TM02. Table 3-1 shows the various subsystem registers
and their respective addresses. The following paragraphs
describe the registers and their bit usage in detail.

indicator for the RHl1 controller. When RDY is asserted,
the RHII is ready to accept a data transfer command. DRY
is the "ready" indicator for each drive. To successfully
initiate a data transfer command, both of these bits must be
asserted. However, a non-data transfer command (e.g.,
Search, Drive Clear) may be issued to a drive any time DRY
is asserted, regardless of the state of the RDY bit.
When a data transfer command is successfully initiated,
both RDY and DRY become negated. When a non-data
transfer command (such as Search) is successfully initiated,
only the DRY bit becomes negated. Some non-data transfer
commands (such as Drive Clear) take so little time to
execute, that the program will never see the negation of the
DRY bit.
The assertion of RDY after the execution of a data transfer
command will not occur until the DRY bit is set and the
controller (RHll) is done.

3.2 DEFINITIONS
This paragraph describes one of the Massbus signals that are
used to operate status information.

If any command other than Drive Clear is issued to a drive
which has ERR (a summary error bit located in each drive)
asserted, the command is ignored by the drive. If a data
transfer command is issued to a drive that has ERR
asserted, the drive does not execute the command, and the
missed transfer error (MXF, bit 9 in the CS2 register)
occurs in the RH 11.

Attention Active (ATA) - The ATA bit is a TM02 bit that
indicates that the TM02/TUI6 requires servicing l.because
it has become ready after completion of a non-data transfer
operation, 2. because of an error condition, or 3. because
of an important internal status change (paragraph 3.7.8).

Clearing Methods

Transfer En-or (TRE) - The TRE bit is located in the
RH 11 and indicates that an RH 11 error or a TM02 error
has occurred while a data transfer is in progress. Writing a 1
into TRE does not affect the ERR bit in any drive.
Similarly, a Drive Clear command does not affect TRE in
the RHl1.

Controller Clear - Controller clear is the action of writing a
1 into the CLR control bit (bit 5 of MTCS2). This causes
the following to be cleared:
a.

All controller errors (MTCS2, bits 15 through
8, MTCSl, bits 15 through 13).

Silo buffer

Special Condition (SC) - The SC bit indicates that a TRE
has occurred or that AT A has set on one of the drives.

3-1

TM02 #0

RH 11 CONTROLLER
15

MTCSI

13;211 10

6 5

c::=:r:= """'TL----rl - =: =: := := J

MTWCI

MTBA I~====================~
MTFC [

:= =: =: := =: := := =: = := =: =: := =: := ~

________________________~

~,ncs, [

MTWC

MTER

r - - - - - - - - - - - - - - - 1

MTAS

MTCK

:~: t~ ~ ~ ~ ===~ =~ ==~ =~] I

6 5

==: C] =: := := =: -,Ir------.,I
:= =- := =- := =- := =- =: := := =: =: =- := J

r---------------,

MTDB L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J

_______________ j

MTDB [
MTMR IL..____________________--'

MTMR~I______________________~

MTDT rL -_ -_ _
- _
- _
- _
- _
- _
- _
- _
- _
- _
-_
-_
-_
-,J

MTDT I~______________________~

MTDT ~I_______________~

M~RL

MTSN [
MTTC [

-= -= -= =: =: =: -= =: =: =: =: -= =: -= -= J

=: =: ==: ==: =: =: =: =: =: ==: ==: J

'~r

MTSN

~I_______________________~

MTSN ~I__________________________~

_____________________~

MTTC ~I___________________'

MTTC I~

~_ _ _ _ _ _ _ _ _ _ _ _ _ _- - - -_ _ _ _ _ _ _ _ _ _ _ _~

~ =: := := =:= =:= := := := =:= := := =1
=: =: =: =: =: =: =: =: =: =: ==: =: =: =: ]

~ ======: ==: ==: =: =-= =: =J

=: =: =: =: =: ==: =: =: =: =: =: ==: =: J

13 12 '1 10

MTBA ::::
MTFC ~I________________________~
MTCS2 [
MTDS

~ ===============~ I

=- := := := := =- := =- := =- := =- =: := =- ~
MTDS :=:====================~

MTDS
MTER rL _
- -_ _
- _
- _
- _
- _
- _
- _
- _
- _
- _
- _
-_
-_
- 1J

6 5

:= =: r=.J =: := =: := """"-----.1
MTWC ~ := =: := := := := := := := := := := := := := j
MTBA := ==:= =: =: =: := =: ====: =: =: =:]
MTFC

TM02 #1

1312 11 10

MTCS2 [

MTCS21~________________________~

MTAS

15
MTCS1 ~

('~

~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J

MASSBUS
NOTES'
1. MTCS1 shared between RH11 and TM02
bits 15-13
10-6 are stO!ed in RHH
bits 12, ", a 5-0 are generated by TM02

2. Each drive is assigned an attention summary
bit in the bit location corresponding to it's
unit no.
3. Location of registers denoted by solid lines;
dotfed lines ore for reference only

MTCS1, MTCS2 - Control and Status
MTWC - Word Count
MTBA - Unibus Address
MTFC - Frame Count
MTDS - Drive Status
MTER - Error
MTAS - Attention Summary
MTCK - Check Character
MTDB - Data Buffer
MTMR - Maintenance
MTDT - Drive Type
MTSN - Serial Number
MTTC - Tape Control
CP-t323

Figure 3-1 Device Register

MTBA Unibus Address register and A16, A 17

Upon assertion of attention or oCl'urrcncc of a

controller crror (while the controller is not
d.

Unit select U(02:00), IE, PSEL, BAI and PAT
bits

Errors, function code, and DA register in all
drives connected to the RH 11 (by assertion of
the Massbus INIT signal).

busy and interrupt enable is set).
Interrupt=(SC+-l )o(RDY)o(IE)
c.

When the program writes 1s into IE and RDY
at the same time.
Interrupt=(IE+-l )0 (RDY+-l )

Table 3-1

RHll and TM02/TU16 Device Registers

Inemonic

fTCSI *

Control and Status 1
(shared by RHll and TM02)
Word Count
Bus Address
Frame Count
Control and Status 2
Drive Status
Error
Attention Summary
Check Character
Data Buffer
Maintenance
Drive Type
Serial Number
Tape Control

lTWC*
lTBA*
lTFC
lTCS2*
lTDS
fTER
lTAS
lTCK
lTDB*
lTMR
lTDT
lTSN
lTTC

CAUTION
Read-Modify-Write instruction (BIS, BIC,
etc.) with IE bit set will cause an immediate interrupt.

Unibus
Address
772440

3.4 TERMINATION OF DATA TRANSFERS

772442
772444
772446
772450
772452
772454
772456
772460
772462
772464
772466
772470
772472

A data transfer that has been successfully started may
terminate in the following ways:

Assertion of RDY - This is the normal termination and is
caused by detection of the inter record gap.

Controller Error - An error is asserted in the CS2 register
as indicated below:
Error
Class

Bit
15
14

RH 11 Registers

13
12
11
10
9

RH11 Error Clear - RH 11 error clear is the action of
writing a 1 into the TRE bit (bit 14 of MTCSl). This causes
all controller errors to be cleared (MTCS2, bits 15 through
8 and MTCSI bits 14 and 13).

Drive Clear - Drive Gear is a command code (11s) that

DL T (Data Late)
WCE (Write Check Error)
UPE (Unibus Parity Error)
NED (Nonexistent Drive)
NEM (NoneXistent Memory)
PG E (program Error)
. MXF (Missed Transfer Error)
MDPE (Massbus Data Parity Error)

A
A

A
A
A
B
A

causes errors and the function code to be cleared in the
drive selected by U(02:00).

Any of these errors sets TRE. The RH 11 terminates the
data transfer immediately, but waits for DRY which occurs
at the inter-record gap before becoming Ready.

Table 3·2 shows the various methods used to clear the
magnetic tape system.

Drive Error - An error occurs in the drive. The drive sets
ERR in the MTDS register and at least one bit in the MTER
register. The ERR bit causes TRE, SC, RDY, DRY, and the
AT A bit to be asserted.

3.3 INTERRUPT CONDITIONS
The RHll generates an interrupt in the PDP-II CPU due to
the following conditions:
a.

Program-caused Abort - By performing a controller clear
or a reset instruction, the program can cause Massbus INIT
to be asserted by the RHIl, which aborts all operations on
all drives attached to the controller. (A program-caused
abort can also be caused by Drive Clear.) Status and error
information is lost when any of the above conditions occur.
The RHl1 and TM02/TU16 become Ready immediately.

Upon termination of a data transfer (if
interrupt enable is set when the RH11 becomes
"ready").
Interrupt=(RDY+-l)o(IE)

3-3

Table 3-2
Results of Program-Controlled Clearing
RESULTS

--ro-'

Clear BA. U(01:00).
IE. PSFL. PAT. 8AI

Clear All

RH II Errors

Clt-ar Silo

AI(',:\\7

Unihus .\ INIT
(Reset instruction
execution or
(ons(1le reset)

Cuntroller Clear

Action

(Bir :; 111 !'.1TCS2--\ )
bSUL' :.i

Oa ta

Assert Masshus
INIT

---

Clear (;0. ATA. ERR.
lind l'rrors in tIll' ..triw
X

CI ear SSt.'

----

(all 8 drives)

(all 8 tra nsports)

X
(all 8 drives)

X
(all 8 tramports)

Tr~tP,(cr (llmmanLl

Rill I Err(1r Clear
(HIl i4 in .\ITCSI-I)

Dr·ye· CiC:H

X
(selected
drive only)

d U'idlOn cutle with
C;O = \ 1 R)

X
(5 elected

tr'ansport
l) nly)

-----.-----~------------

3.5 TJU 16 COMMANDS
T.n f} 6 commands arc classified as data transfer ur non-data
transfer commands. Table 3-3 lists all the commands with a
brief description of each. Before a command is initiated,
.:ertain parameters are specified by the program for each
.:ommand. Tbese parameters are listed in Table 3-4. For
ex.ample. in ,In Erase operation, it is only necessary to
specify the Tt-.102 and the TU16.

(on different drives), an interrupt will occur only on the
assertion of RDY even though the Atten tiOIl bit (asserted
on completion of the non-data transfer command) may be
asserted before the RDY bit. Data transfer cI)mmands are
read, write, and write check and cause the trlllsfer of data
over the data bus (synchronous) portion of the Massbus .
TIle parameters specified by the prograt1l during the
issuance of these commands are described as follows:

3.5.1 !'ion-Data Transfer Commands
'\un-data transfer commands do not cause the RH 11 to
become husy (RDY asserted). Therefore, other commands
can be issued to other drives while a non-data transfer
command is in progress. A non-data transfer command is
terminated when the Attention bit for the specified drive is
asserted. The assertion of the Attention bit, upon completion of a non-data transfer command, will cause an
interrupt if the IE bit is set and RDY is asserted,

Bus Address - The bus address represents the starting
memory location that the data will be read from (for J
write) or written into (for a read). The address occupies the
16 bits of the MTBA bus address register and bils 9 and 8
of the MTCSI control and status register (Chapter 3).
Selected IM02 Tape Controller - The TM02 is selected by
writing the MTCS2 register in the RH 11. Bits 0 through 2
of the register arc the unit select bits that specify the
desired TM02.

3.5.2 Data Transfer Commands
Data transfer commands cause the RH 11 to become busy
(RDY negated). No other commands can be issued while a
data transfer command is in progress. Termination of a data
transfer command is indicated by the re-assertion of RDY.
Assertiun of RDY, upon completion of a data transfer
command, will cause an interrupt if IE is set. If a data
transfer and a non-data transfer command are in progress

Word Count - TIle word count is a count of the number of
words to be transferred to or from the tape drive. The
MTWC word count register is loaded with the two's
complement of the number of words to be transferred and
is incremented toward zero for each word transferred to or
from memory. Overflow to zero terminates the Unibus
transfer.

3-4

Table 3-3
Command Function Codes
Function Code F(O-S)
(octal)

Description

Operation

NoOp

Performs no operation. Clears GO bit in Control register.

Rewind Off-line'"

Initiates a rewind on selected transport and places
it off-line.

Clears GO bit.

Sets the following bits in the Status register:
Drive Ready (DRY)
Slave Status Change (SSC)
Attention Active (AT A)
Rewind off-line causes one interrupt only
indicating rewind underway and transport off-line.

Rewind

Initiates a rewind to BOT marker on selected
transport and clears the GO bit.

Sets DRY, PIP, and ATA bits in the Status register
during rewind.

When BOT is sensed, sets SSC and clears PIP.
Rewind causes two interrupts:
a.

Rewind underway

SSC when BOT is sensed (rewind 'job
done').

Drive Clear

Similar to Initialize. Resets all TM02 and selected
transport logic only. Does not affect unselected transports.

Erase

Erases approximately 3 in. of tape. Clears GO bit and
sets ATA on termination.

Write Tape Mark

Writes a special tape record on the selected transport.
Clears GO bit and sets ATA bit on termination (Paragraph 1.6.1.2).

Space Forward

Moves tape forward (toward EOT) on the selected
transport over the number of records specified by the
Frame Count register. Aborts space operation if TM or
EOT is detected prior to specified frame count. Clears
GO bit and sets ATA on termination.

*Requires manual intervention to return transport on-line.

3-5

Table 3-3 (Cont)
Command Function Codes
Function Code F(O-S)
(octal)

Operation

Description

Space Reverse

Moves tape in reverse (toward BOT) on the selected
transport over the number of records specified by the
Frame Count register. Aborts space operation if TM or
BOT is detected prior to specified frame count. Clears
GO bit and sets ATA on termination.

Write Check Forward

Does a word-by-word comparison of specified memory
locations with the tape record read from tape in the
forward direction.

Write Check Reverse

Same as write-check forward except for reverse tape
motion.

Write Forward

Writes forward one tape record on the selected
transport. Record length is determined by Frame Count
register. Clears 'GO bit on command termination.

Read Forward

Reads forward one tape record on the selected transport.
Clears GO bit on command termination.

Read Reverse

Reads reverse one tape record on the selected transport.
Clears GO bit on command termination.
NOTE
Do not use this mode unless whole
PDP-tt data words were written in the
record.

Frame Count - The MTFC frame count register specifies

Normally, the frame count register is set to twice the word
count in normal and 15 mode. In core dump mode, the
frame count is set to four times the word count. If less than
two frames of the last word are desired in normal or 15
mode, the frame count register may be loaded with an odd
number. Ifless than four frames of the last word are desired
in core dump mode, the frame count register may be loaded
to 1, 2, or 3 less than four times the word count. For
example, if 21 frames were to be transferred in normal
mode, the frame count register is set to the two's
complement of 21 and the word count register is set to the
two's complement of 11. Frame count would overflow
before word count and the last byte would be transferred as
Os. No FCE occurs in this case. Frame count need not be
specified in a read operation or a write-check operation and

the number of frames (bytes) to be written on tape. Each
sLxteen-bit PDP-II word is divided into two frames.
Consequently, the frame count register is loaded with twice
the number in the MTWC register for normal or 15 mode or
four times the number in the MTWC register for core dump
mode. The frame count register is loaded with the two's
complement of the number of frames to be written.
Overflow to zero tenninates transfers on the slave bus.
Since the frame count register is located in the TM02 tape
controller, writing this register requires the RH 11 to
perform a Massbus cycle. If the frame count register
overflows before word count, the transfer may be terminated by FCE (see below). If word count overflows before
frame count, the rest of the record is zero-filled.

3-6

is automatically reset in these cases. At the end of a read or
write-check operation, the frame count is equal to the
number of frames read from tape.

through 2 of this register are slave select bits which select
the appropriate tape transport (designated slave). Bits 4
through 7 of this register are the format seled bits which
specify Massbus-to-tape character formatting during a write
(or tape character-to-Massbus formatting during a read
operation). Bits 8 through 10 of this register specify the
tape density (phase-encoded or one of four possible non
return-to-zero formats).

Selected Tape Transport, Format Character Packing and
Tape Density - These parameters are specified by the
program by writing the MTTC tape control register. Bits 0

Table 3-4
TJ U 16 Commands and Required Parameters
Word
Count

Slave
Select

Read.
Read Reverse

Write

Write-check.
Wri te Check Reverse

Command

Frame
Count

Bus
Address

Unit
Select

Density

Format

Function Code

Space

Erase

Rewind,
Rewind Off·line

Write Tapemark

Nap

X
X

Drive Clear

Notcs:

(I)

Frame count for a space operation is
loaded with 2's complement of number
of records to be spaced.

(2)

GO bit must be loaded last.
The order of specifying the other
parameters is immaterial.

(3)

X indicates that the item must be specified,
e.g .. word count specified for read, write,
and write check.

3-7

3.5.2.) Write Data Transfer - After the above parameters
arc specified, the data transfer is initiated by loading a write
command function code in the MTCS 1 register in the RH 11
and setting the GO bit. This process logically connects the
data portion (s,ynchronous) of the TMO::! to the RH 11 as
this is the path that the data will be transferred over.

The data transfer is initiated by loading a Read command
function code in the MTCSI register in the RH 11 and
setting the GO bit. This process logically connects the data
portion (synchronous) of the TM02 to the RH t 1 as this is
the path that the data will be transferred over.
11le Run line is asserted by the RH 11 and when the tape is
up to speed, the TM02 receives two tape characters from
the TU16 tape transport, assembles them into a 16-bit
word, and sends it to the RHll accompanied by SCLK.
The TM02 waits for the next two characters and, on the
negation of SCLK, transfers the second word to the RH 11.
The process continues until the inter-record gap is detected.
At this point, the TM02 sends EBL to the RH 11 to
terminate the data transfer.

Unibus NPR cycles are initiated by the RHII and the data
words from memory are transferred to the input buffer
(lBUF) of the Silo (Figure 1-5).
NOTE
The RH 11 may perform either single cycle or
back-to-back memory references per NPR
request.
For each data word transferred, the word count is
incremented by 1 and the bus address is incremented by 2.
111e data words are clocked in to and "bubble" through the
Silo. \\11en the first data word reaches the top, it is
autol1utically docked into the Silo output buffer (OBUF).
When the Silo is filled and a word is in OBUF, the RH 11
asserts the RUN signal which signals the TM02 to begin
assembling characters and writing on tape.

NOTE

If the Word Count register overflows before the
inter-record gap, only the number of words
designated in the Word Count register will be
transferred. In this case, the RH n will ignore
the remaining words and wait for EBL in the
drive to terminate the data transfer. If EBL
occurs before word count overflow, a frame
count error (FCE) is flagged.

111e TM02 accepts the first data word, converts it into two
tape characters, and outputs it to the TU16 tape transport.
It then sends a sync clock (SCLK) signal to the RHII
requesting another data word. The RHll receives SCLK
and echoes it back as write clock (WCLK) along with the
next data word. The TM02 assembles this into two tape
characters, transfers it to the TU16, and issues another
SCLK. The process continues until frame count overflow is
detected indicating that the desired number of characters
have been transferred.

3.5.2.3 Write-Check Data Transfer -- The third type of
data transfer is a write-check and is initiated when a
write-check function is specified in the MTCS 1 register and
the GO bit is set. In this operation, a record which has
previously been written onto the tape is read from the tape.
This data is compared to the data in memory originally
used to write on the tape. The comparison is accomplished
by Exclusive OR gates, and if any of the bits fail tc
compare, a write-check error occurs. 111is method allow~
automatic verification that the data on tape agrees with tht
contents of memory.

NOTE
If the word count register is set to less than
twice the frame count, word count overflow
will occur first. This causes the un line to be
negated and will cause Os to be written in the
rest of the record. If the word count register is
set to more than twice the word count, frame
count overllow will occur first and may cause a
frame count error (FCE).

3.5.2.4 Data Transfer Rates - The data transfer rate from
the drive is determined by the frequency of the data on
tape. The basic data transfer rates are listed below:

3.5.2.2 Read Data Transfer - In a read operation, the data
words are transferred from the tape drive to memory via
the TM02 and RH 1]. The data path functionally consists of
the Unibus NPR logic, the Silo memory in the RH 11, and
the data bus portion of the Massbus (Figure 1-5).

3-8

1600 BPI --- 14 Ils/character

NRZ

800 BPI - 28 Ils/character
556 BPI - 40 Ils/character
200 BPI - 112 Ils/character

3.6 REGISTER DESCRIPTIONS
The following paragraphs provide a description of each bit in the RH 11 and TM02 registers. Figure 3-2 shows each
register and the associated bits in each register.

772440
MTCS1
(Table 3-5)
772442
MTWC

MTBA

(Table 3-6)
772444
(Table 3-7)
772446

MTFC

(Table 3-8)

MTCS2772450
(Table 3-9)
772452
MTDS

MTER

772454

772456
MTAS

MTCK

(Table 3-13)
772460
(Table 3-14)
772462

MTDB

(Table 3-15)

772466
MTDT
(Table 3-17)
772470
MTSN

(Table 3-18)
772472

MTTC

CP-1324

Figure 3-2 RH 11 /TM02 Register Summary

3-9

before the register is written. ('While till' RDY bit is
negated, the RHll prevents program modification of th~sl'
control bits even when the write is done into the odd byte.)

3.6.1 Control and Status 1 (MTCS 1) Register 772440
TIle MTCS1 register is a read/write register used to store
tape commands and operational status. The commands are
stored in bi ts 1. through 5 in this register and are designated
function command code bits Fl through F5, respectively.
Bit 0 in this rcgil\ter i~, the GO bit which must be asserted
when a command is issued to the TU16/TM02 tape
subsystem. TIle command specified in bits 1 through 5 is
transferred to the TM02 designated by bits 02 through 00
in the MTCS2 control and status 2 register.

Figure 3-3 shows the MTCSI bit format and Table 3-5
provides a description of each bit.

3.6.2 Word Count (MTWC) Register (772442)
TIlis register is loadcd by the program with the 2's
complement of the number of words to be transferred.
During a data transfer, it is incrementcd by 1 each time J
word is transmitted to or from memory.

Data transfer commands arc designated by 518 through
77 8 . Other commands arc designated from 018 through
478 and arc called non-data transfer commands. All data
transfer and non-data transfer commands are odd command
cocks since the GO bit (least significant bit) must be
assertcd. The command codes and a brief description of
each is provided in Table 3-3.

Figure 3-4 shows the MTWC bit format. and Tahle 3-6
proVides a description of each bit.

3.6.3 Unibus Address (MTBA) Register (772444)
This device registcr is used by the RBI 1 to address the
memory location in which a transfer is to take place. Thc
MTBA register forms the lower 16 bits of address which
combine with MTCSI bits 09 and OS to create the IS-bit
memory address. This register should be loaded by the
program with the starting memory address. During forward
operations, this register is loaded with the lowest value
memory address, while in reverse operations, this register is
loaded with thc highest valuc memory address. Each time a
DMA transfer is made, the register is incremcnted by 2. For
read reverse operations, the register is decremented by two
for each DMA data transfer. If the HAl (Bus Address
Increment Inhibit) bit (bit 03 of MTCS2) is set, the
incrementing of the MTBA registcr is inhibited and all
transfers take placc to or from the starting memory address.
Figure 3-5 shows the MTBA bit usage, and Table 3-7
provides a description of each bit.

Only data transfer commands cause the RH 11 to become
busy (ROY bit negated). While the RH11 is busy, no
further data transfer commands may be issued (see PGE bit
lOin MTCS2). Non-data transfer commands, however, may
be issued at any time and to any drive which is not busy
(DRY asserted).

While a data transfer is in progress, unit select bits U(02:00)
in the MTCS2 register may be changed by the program to
issue a non-data transfer command to another drive. This
will not affect the data transfer.
When a non-data transfer command code is written into
MTCS 1 while a data transfer is taking place, only the even
(low) byte of MTCS] should be written. This will prevent
the program from unintentionally changing MTCSI status
bits (A 16, A 17 and PSEL) if the transfer is completed just

~--~

__-+____

LOCATED IN
CONTROLLER

__+-__

LOCATED IN
DRIVE

____

____L____

LOCATED IN
CONTROLLER

F~~OJ

LOCATED IN
DRIVE
cp- 1325

Figure 3-3 Control and Status Register I-Bit Usage

3-10

Table 3-5
Control and Status 1 Register Bit Assignments
Bit

Set By/Cleared By

Remarks

SC
Special condition
Read only

Set by TRE, ATTN, or Massbus
control parity error. Cleared by
Unibus A INIT, controller clear, or by
removing the ATTN condition.

SC=TRE+ATTN+MCPE

TRE
Transfer error
Read/write

Set by DLT, WCE, UPE, NED, NEM,
PGE, MXF, MDPE, or a drive error
during a data transfer. Cleared by
Unibus A INIT, controller clear, RHll
error clear, or loading a data transfer
command with GO set.

TRE=DLT+WCE+UPE+NED+NEM
+PGE+MXF+MDPE+(EXC· EBL)

MePE
Massbus control
bus parity error
Read only

Set by parity error on Massbus control
bus while reading a remote register
(located in the drive). Cleared by
Unibus A INIT, controller clear, RHil
error clear, or loading a data transfer
command with the GO bit set.

Parity errors that occur on the
Massbus control bus while writing a
drive register are detected by the drive
and cause the PAR error (MTER
register, bit 03) to set.

Not used

Always read as a O.

DVA
Drive available
Read only

Always a 1 in the TM02 when read
from an existing drive.

PSEL
Port select
Read/Write

When PSEL= I, data transfer is via
Unibus B; when PSEL=O, data transfer
is via Unibus A. Cleared by Unibus A
IN IT, controller clear, or by writing a
o in this bit position.

A Unibus select control bit. This bit
cannot be modified while the RH 11 is
performing a data transfer (RDY
negated).

09
08

AI7
A16
Unibus address
Read/write

Upper extension bits of the MTBA
register. Cleared by Unibus A INIT,
controller clear or by writing Os in
these bit positions.

Control bits. These bits cannot be
modified while the RH 11 is performing a data transfer (RDY negated).

RDY
Ready
Read/only

RDY normally=!. During data transfers, RDY=O.

When a data transfer command code
(518-778) is written into MTCSl,
RDY is reset. At the termination of
the data transfer, RDY is set.

3-11

Table 3-5 (Cont)
Control and Status 1 Register Bit Assignments

(X)

Bit

Set By /Cleared By

Remarks

IE is a clmtrol bit which can be set
only under program control. When
IE=l, an interrupt may occur due to
RDY or A TIN being asserted (Paragraph 3.4). Cleared by Unibus A INIT,
controller clear, or automatically
cleared when an interrupt is recognized by the CPU. When a 0 is written
into IE by the program, any pending
interrupts are cancelled.

A program-controlled interrupt Illay
occur by writing Is into IE and RDY
at the same time.

F4-FO are function (command) code
control bits that detennine the action
to be performed by the RHl1 and
TM02/TU16 as shown below.

The function code bits arc stored in
the selected drive. Data transfer
commands, defined as F4-(F3+F2),
always cause the RH 11 to become
busy.

Interrupt cnablc
Read/write

05--00
F4-FO
and GO bit
Read/write

03
()7
11

25
27
31

33
SI

F4 F3 F2 Fl FO GO
0 0 0 0 0 I
0 0 0 0 I
0 0 0 1 1 1
0 0 1 0 0 1
0 1 0 I 0 1
0 I 0 I I I
0
0
I

57
61
71
77

1
1
1

1
I
0
0
I

t
I

I
I
0

1
1

0
0

0
0
I

I
I
1

1
0
0
1

I
I

Function
No operation
Rewind off-line
Rewind
Drive clear
Erase
Write tape mark
Space forward
Space reverse
Write check forward
Write check reverse
Write forward
Read forward
Read reverse

The GO bit (MTCS 1, bit 0) must be
set to cause the controller or drive to
respond to a command. The GO bit is
reset by the drive after command
execution.
Cleared by Unibus A INIT or controller clear (will abort command
execution in all drives).

I ~~

. L -_ _.-L____

~ ~
__

__
CP-1326

Figure 3-4 Word Count Register Bit Usage
3-12

Table 3-6
Word Count Register Bit Assignments

Bit

15-00

we
Word count
Read/write

Set By/Cleared By

Remarks

Set by the program to spccify the
number of words to be transferred (2's
complement form). This register is
cleared only by writing Os into it.

Incremcnted foi" each data transfer"

CP-1327

Figure 3-5 Unibus Address Register Bit Usage

Table 3-7
Unibus Address Register Bit Assignments

Bit

Set By/Cleared By

Remarks

15-01
BA 15-01
Unibus address
Read/write

Loaded by the program to specify the
starting memory address of a transfer.
Cleared by Unibus A IN IT or by
controller clear.

The BA register is incremented by 2
by the RHl1 after each transfer of a
word to or from memory.

Not used.

Always read as a O.

incremented each time a tape character is recorded. Normal
write data transfer tennination is accomplished when the
frame count register overflows to zero. For a space
operation, the frame count register functions similarly to a
write, except it is loaded with the 2's complement of the
number of records to be spaced and is then incremented
each time a record is detected. Space termination is
accomplished when the register overflows to zero. For a
read or write check operation, this register is automatically
reset prior to read initiation. The register is then incremented each time a tape character is read. The register is
not incremented for check characters (LRCC, CRCC).
lhus, at the end of the read operation, the frame count
register contains a count of the number of characters read.

3.6.4 Frame Count (MTFC) Register (772446)
TI1e frame count register is a 16-bit, read/write register that
counts tape events. During a data transfer operation
(read/write), this register is incremented each time a tape
character is transferred to or from the tape. However,
during a space operation, this register is incremented each
time a record is detected. The register output may be read
by the controller at any time; but the controller can only
write into this register when the transport is not performing
a space or data transfer (GO negated).

For a write operation, the frame count register is loaded,
prior to write initiation, with the 2's complement of the
number of tape characters to be written. In NRZ mode, the
minimum number of characters that can be written is 13.
During the writing process, the frame count register is

Figure 3-6 shows the frame count register bit usage and
Table 3-8 provides a description of each bit.

3-13

12
11
14
13
I -F-e~----~--~--~

[II
15

DIJ

--~----~--~----~--~--~----~--~----~--~----~--~--~----

cp·· 1321'!

Figure 3-6 Frame Counter Bit Usage

Table 3-8
Frame Counter Bit Assignments
Bit
15-00

Set By/Cleared By

Remarks

Cleared by writing Os in the bit locations

Designates in 2's complement form the
number of records to be spaced over,
characters to be written, or characters
that have been read. Initiating a write
or space command when the frame
count register is loaded with zeros
implies a count of 21 6.

Fe 15-00
Frame count
Read/write

3.6.5 Control and Status 2 (MTCS2) Register (772450)
111is register indicates the status of the controller and
..:ontains the drive unit number U(02:00). The unit number
specified in bits 02 through 00 of this register indicates
which drive is responding when registers are addressed that
are located in a drive.
These arc:
MTCS 1 (bits 5 through 0, 12 and 11)
MTDS
MTDT
MTER
MTCK
MTMR
MTTC
MTFC
MTSN

3.6.6 Drive Status (MTDS) Register (772452)
This register contains the various status indicators for the
selected drive. The status indicators displayed are those of
the tape drive which is specified by the unit select bits
(02:00) of the MTCS2 register. The register is a read-only
register. Figure 3·8 shows the MTDS bit usage, and Table
3-10 provides a description of each bit. Writing into this
register will not cause an error and will not modify any of
the status bits.

3.6.7 Error (MTER) Register (772454)
111ere are 16 different error conditions that can be detected
in the TM02/TU16 tape drive system. The error register is a
16·bit, read-only register which stores all of the tape system
error indications.

Figure 3-7 shows the MTCS2 bit usage, and Table 3-9
provides a description of each bit.

EjWCE

I UPE

NED

I NEM I PGE I MXF jMDPE I OR

CLR

PAT

BAI

Iu~~
Cp··'1329

Figure 3-7 Control and Status Register 2-Bit Usage

3-]4

Table 3-9
Control and Status Register 2 Bit Assignments
Bit

Set By/Cleared By

Remarks

DLT
Data late
Read only

Set when the controller is unable to
supply a data word during a write
operation or accept a data word during
a read or write-check operation at the
time the drive demands a transfer.
Also set when the controller is performing a data transfer operation over
the second Unibus (pSEL= 1) and a
Unibus B INIT is received on that
port. Cleared by Unibus A INIT~
con troller clear, RH 11 error clear, or
loading a data transfer command with
GO set.

DLT causes TRE. Buffering is 66 10
words deep in the con troller, and a
DL T error indicates a severely overloaded bus. Can also be set by the
program reading or writing the MTDB
register (paragraph 3.15).

WCE
Write check error
Read only

Set when the controller is performing
a write-check operation and a word on
the tape does not match the corresponding word in memory. Cleared
by Unibus A INIT, controller clear,
RHll error clear, or loading a data
transfer command with GO set.

WCE causes TRE, If a mismatch is
detected during a write-check command
execution,
the
transfer
terminates and the WCE bit is set. The
memory address displayed in MTBA
[and extension] is the address of the
word following the one which did 110t
match (if BAI is not set). The mismatched data word from the tape
drive is displayed in the data buffer
(MTDB).

UPE
Unibus parity
error
Read/write

Set if the Unibus parity lines indicate a
parity error while the controller is
performing a write or write-check
command. Cleared by Unibus A INIT
controller clear, RHl1 error clear, or
loading a data transfer command with
GO set.

UPE causes TRE. When the Unibus is
selected to do I8-bit data transfers,
the UPE error is disabled. When a
Unibus parity error occurs, the MTBA
register contains the address +2 of the
memory word with the parity error (if
BAI is not set). This bit may be set by
program control for diagnostic purposes.

NED
Non-existent drive
Read only

Set when the program reads or writes a
drive register CSl, DS, ER, MR, FC,
DT, CK, TC, or SN) in a drive
[selected by U(02:00)] which does
not exist or is powered down. (The
drive fails to assert TRA within 1.5 IlS
after assertion of DEM.) Cleared by
Unibus A INIT, controller clear, RBll
error clear, or loading a data transfer
command with GO set.

NED causes TRE.

3-15

Table 3-9 (Cont)
Control and Status Register 2 Bit Assignments
Bit

Remarks

Set By/Cleared By

------------------+------------------------------------+----------------------.-------11

NEM
Non-existent
memory
Read only

Set when the controller is performing
a DMA transfer and the memory
address specified in MTBA is nonexistent (does not respond to MSYN
within 10 /ls). Cleared by Unibus A
INtT, controller clear, RHll error
clear, or loading a data transfer command with GO set.

NEM causes TRE. The MTBA ~ontains
the address +2 of the memory location
causing the error.

PGE
Program error
Read only

~t when the program attempts to
initiate a data transfer operation while
the RH 1] is currently performing one.
Cleared hy Unibus A INIT, controller
dear, RBI 1 error clear, or loading a
data transfer command with GO set.

PGE causes TRE. The data transfer
command code is inhibited from being
written.

MXF
Missed transfer
Read/write

Set if the drive does not respond to a
data transfer command within 250 ms.
Cleared by Unibus A INIT, controller
clear, RH 11 error clear, or loading a
data transfer command with GO set.

MXF causes TRE. This bit can be set
or cleared by the program for diagnostic purposes. This error occurs if a
data transfer command is loaded into a
drive which has ERR set, or if the
drive fails to initiate the command for
any reason (such as a parity error).

!vtDPE
_\1assbus data bus
parity error
Read only

Set when a parity error occurs on the
Massbus data bus while doing a read or
write-check operation. Cleared by
Unibus A INIT, controller clear, RHll
error clear, or loading a data transfer
command with GO set.

MDPE causes TRE. Parity errors on
the Massbus data bus during write
operations are deteded by the drive
and cause the PAR error (MTER
register, bit 03).

OR
Output ready
Read only

Set when a word is present in MTDB
and can be read by the program.
Cleared by Unibus A INIT, controller
clear, or by reading DB (paragraph
3.6.1 0).

Serves as a status indicator for diagnostic check of the Silo buffer. An
attempt to read the DB register before
OR is asserted will cause a DLTerror.

IR
Input ready
Read only

Set when a word may be written in the
DB register by the program. Cleared
by reading the DB (paragraph 3.6.10).

Serves as a status indicator for diagnostic check of the Silo buffer. An
attempt to write the DB register
before IR is asserted will cause a DLT
error. This bit is for diagnostic purposes only.

CLR
Controller clear
Write only

When a 1 is written into this bit, the
RH 11 and all drives are initialized
(paragraph 3.2).

Unibus A INIT also causes controller
clear to occur.

._.__________

---------------------_---1'--------------_.--3-16

Table 3-9 (Cont)
Control and Status Register 2 Bit Assignments
Bit

Set By/Cleared By

Remarks

PAT
Parity test
Read/write

While PAT is set, the RBI1 generates
even parity on both the control bus
and data bus of the Massbus. When
clear, odd parity is generated. Cleared
by Unibus A IN!T or controller clear.

While PAT is set. the RIIll checks fur
even parity received on the data bus
but not on the control bus.

BAI
Unibus address
increment inhibit
Read/write

When BAI is set, the RH 11 will not
increment the SA register during a
data transfer. This bit cannot be modified while the RHll is doing a data
transfer (RDY negated). Cleared by
Unibus A IN IT or controller clear.

When set during a data transfer, all
data words are read from or written
into the same memory location.

These bits are written by the program
to select a drive. Cleared by Unibus A
IN IT or controller clear.

The unit select bits can be changed by
the program during data transfer
operations without interfering with
the transfer. The CSl, OS, ER, MR,
FC, DT, CK, TC, and SN registers
contain bits that come from the
selected drive.

02-00
U 02-00
Unit select
Read/write

CP-1330

Figure 3-8 Drive Status Register Bit Usage

TM02/TU16 errors are categorized as class A and class B.
Class B errors will temlinate an in-progress data transfer; a'
class A error will not. However, the Massbus controller is
notified of any error during a data transfer by the
immediate assertion of EXC H on the Massbus. If the
TM02/TU16 is not performing any operation, or is performing a rewind (i.e., the GO bit is clear), the controller is
immediately notified of an error condition by the assertion
of ATTN H on the Massbus.

Figure 3-9 illustrates the error register bit usage and Table
3-11 provides a description of each bit. Table 3-12 lists the
various operations and the associated error conditions
which can occur during normal operation of the system.
After performing one of the operations listed at the left of
the table, only errors indicated by an X may be present in
the MTER register. Presence of any other errors indicate a
hardware malfunction.

3-17

Table 3-10
Drive Status Register Bit Assignments

Bit
15

ATA
Attention active
Read only

Set By/Cleared By

Remarks

Sct by the drive when there is an
attention condition in that drive.
Cleared by Unibus A INIT, controller
clear, drive clear, loading a command
with the GO bit set, or loading a 1 in
the MTAS register in the bit position
corresponding to the drive's unit
number. (The last two methods of
clearing the AT A bit will not clear the
error indicators in the drive.)

An attention conditinll indicah.'s one
of the following:

The TM02 and the selected
transport require servicing due
to sse (see bit 6 in this Table).

The TM02 and the selected
transport have become rcady
after a non-data transfer operation.

At the completion of any operation wi th EOT asserted.

This bit is the logical OR of all the bits
in the MTER register. This bit is not
cleared by loading a command other
than drive clear. While ERR is
asserted, commands other than drive
clear are not accepted by the drive.

ERR
Error summary
Read only

Set when one or more of the error bits
is set in the MTER register of the
selected drive. Cleared by Unibus A
INIT, controller clear, or by drive
clear.

PIP
Positioning in
progress
Read only

Set by the drive while the space or
rewind command is under way.
Cleared at the completion of the
operation.

MOL
Medium on-line
Read only

Set when the selected slave is loaded
and the on-line switch activated. 111is
condition is necessary for response to
any commands - if GO= 1 and
MOL=O, the command is aborted and
UNS and AT A are asserted. This bit is
not affected by drive clear or INIT.

Indicates selected slave is ready for
immediate use. Any change in status
of MOL will set ATA.

WRL
Write locked
Read only

Set whenever a reel of tape without a
write enable ring is loaded on the
selected slave. This bit is not affected
by drive clear or INIT.

Indicates that the selected slave transport is write protected.

EOT
End of tape
Read only

Set when the EOT marker is recognized during forward tape motion.
Cleared when the EOT marker is
passed over during reverse tape
motion. This bit is not affected by
drive clear or INIT, however, execution of a rewind command causes EOT
to be cleared.

3-18

Table 3-10 (Cont)
Drive Status Register Bit Assignments
Bit

Set By/Cleared By

Remarks

Not used

DPR
Drive present
Read only

Always set in the TU16/TM02 system.

This bit is a hardwired 1.

DRY
Drive ready
Read only

Set by INIT or at the completion of a
command. Cleared whenever a valid
command (with the GO bit asserted) is
loaded into MTCS 1.

Indicates that 'the drive is on-line and
prepared to accept a command. It does
not necessarily indicate that the slave
is ready to accept a command (see
SPR, MOL, PIP).

SSC
Slave status change
Read only

Set when any slave transport requires
attention due to one of the follOWing
conditions:

Setting SSC causes AT A to be asserted
as soon as DRY becomes asserted.
ATA is asserted immediately jf DRY is
asserted. More than one slave can be
asserting SSC simultaneously. Each
drive must be polled (for changes in
SPR, MOL, PIP), in turn, and after
servicing, a drive clear should be used
to clear the SSC on that slave. AU
drives must be polled when SSC is
serviced since an interrupt will only
occur on SSC transitioning to a 1.

a)
b)
c)
d)

Completion of rewind
Power failure
Coming on-line
Going off-line

Cleared by INIT. Drive clear will clear
this bit if the SSC condition was raised
by the selected slave and no other
slaves are posting SSC.

PES
Phase encoded
status
Read only

Set when the selected slave is in PE
mode. Cleared when the selected slave
is in NRZI mode. This bit is not
affected by drive clear or INIT.

Reflects the format mode in which the
formatter is operating.

SDWN
Slowing down
Read only

Set during the period when tape
motion is stopping. This bit is not
affected by drive clear or INIT.

DRY is asserted on the leading edge of
SDWN.

IDB
Identification burst
Read only

Set in PE mode on recognition of the
PE identification burst. Cleared ·when
another command is issued, or cleared
by drive clear or INIT.

In the forward direction, the bit
remains set through the reading,
writing, or spacing operation. On a PE
tape, IDB should be asserted after any
tape motion operation which began
from BOT.

3-19

Table 3-10 (Cont)
Drive Status Register Bit Assignments
Bit

Set By/Cleared By

Remarks
Indicates detection of tape mark. The
phase encoded tape mark written by
the TUI6 consists of 40 characters
with zeros in physical tracks 1,2,4,5,
and 8 with tracks 3, 6, 7, 9 dc erased.
The NRZI filemark wri tten by the
TUI6 consists of a single character
record followed by the LRCC for that
record. CRCC is held 0 for 9-track
recording of tape mark. The single
character contains octal 023. TM
should be asserted after the completion of a write tape mark command.

TM
Tape mark
Read only

Set when a tape mark is detected and
remains set until the next tape motion
operation is initiated. Cleared by INIT
or drive clear.

BOT
Beginning of tape
Read only

Set when the selected slave detects the
BOT marker. This bit is not affected
by drive clear or INIT. Cleared by
passing BOT (Beginning of Tape) in
the forward direction.

SLA
Slave attention
Read only

Set by a selected slave which requires
attention due to coming on-line.
Cleared by drive clear or INIT.

15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
ICOR/'~--~----r---~--~----~---~----r-~~--~----~--~----~--~~

CRC

CP-1331

Figure 3-9 Error Register Bit Usage

3-20

Table 3-11
Error Register Bit Assignments
. Bit

Set By/Cleared By

Remarks

COR/CRC
Correctable data
error /CRC error
Read only

PE mode - set on a tape character.
ll1erefore, PE error correction logic
was able to correct the data on-the-fly
and good data was transferred to
memory.
NRZ mode - set when the eRC
character generated from read back
data does not agree with the CRC read
from tape. Oeared by drive clear or
INIT.

In the PE case, when the single dead
track is accompanied by a parity error,
the data bit in the dead track is
inverted. COR/CRC is a class A error.

UNS
Unsafe
Read only

Set if the GO bit in the MTCS1
register is set, the MOL bit in the
MTDS register is reset, and a command
code other than drive clear is issued.
Also set if the TM02 detects an imminent power fail condition (AC LO
asserted, DC LO not asserted).

UNS is a class B error.

If UNS is caused by GO= 1 while
MOL=O, it is cleared by RHll CLR or
DRIVE CLEAR. If UNS is caused by a
transient voltage-low condition, it can
be cleared by INIT or drive clear when
voltage returns to an acceptable level.
If UNS is caused by a permanent
voltage - low condition, it cannot be
cleared.
13

OPI
Operation
incomplete
Read only

A read or space operation indicates
that a tape record has not been
detected within 7 sec from command
initiation. A write operation indicates
that a read-after-write tape re>cord has
not been detected within 0.7 sec from
command initiation. Can also indicate
that NSG > 0.08 inches. Cleared by
INIT or drive clear.

3-21

OPI is a class B error. Also, OP} can be
set when a rewind command is issued
at BOT.

Table 3·11 (Cont)
Error Register Bit Assignments
Bit

Set By/Cleared By

Remarks

OTE
Drive timing error
Read only

Set (l) during a write operation if
WCLK was not received from the
RH II in time to provide a valid tape
character, or (2) when a data transfer
is attempted when the bus of the
Massbus is already occupied (OCC=1).
Cleared by INIT or drive clear.

When OTE is asserted, the drive also
asserts EBL and EXC and aborts the
command.
Case 1 can be distinguished from case
2 by monitoring the MTFC frame
count register. In case 1, this register is
incremented at least once since it was
loaded. In case 2, this register will
contain the same number with which
it was loaded prior to the issuance of
the data transfer command. During a
read operation, OTE can occur only
due to case 2. OTE is a class B error.

NEF
Non-executable
function
Read only

Set when:

NEF is a class B error.

A write operation is attempted
on a write-protect transport.

A space reverse, read reverse, or
write check reverse is attempted
when the tape is at BOT.

The OEN 2 bit in the tape
control register does not agree
with the PES status bit (i.e.,
selected drive not capable of
selected density).

A space or write operation is
attempted when FCS=Q in the
tape control register.

A read or write operation is
attempted with DEN2=Q in the
tape control register and the 2's
complement of a number less
than 13 is in the frame count
register.

Cleared by drive clear or INIT.
--------.------------~-------------.--------------------~----------------------,---"----

3-22

Table 3-11 (Cont)
Error Register Bit Assignments
Bit
10

CS/ITM
Correctable skew/
illegal tape mark
Read only

Set By/Cleared By
In PE mode, this bit is set when
excessive but correctable skew is
detected in data read back from tape.
It is a warning only, and does not
indicate that bad data was read from
tape.
In NRZ mode, this bit is set when a bit
pattern is detected on tape which has
the general characteristics of an NRZ
fUemark (specifically, two single
characters separated by seven blank
character spaces) but which does not
contain the exact data expected in an
NRZ fUemark. Cleared by drive clear
or INIT.

Remarks

When such a bit pattern is detected in
NRZ .mode, both tape marks in the OS
register and CS/IFM in the ER register
will become asserted.

FCE
Frame count error
Read only

. Set when a space operation has terminated and the frame counter is not
cleared. Also set when the RHll fails
to negate RUN when the TM02 asserts
EBL. Cleared by drive clear or INIT.

FCE is a class A error .

NSG
Non standard gap
Read only

Set after a data transfer operation
whenever any tape charaCters are read
while the read head is scanning the
first half of the interrecord gap.
Cleared by drive clear or INIT.

NSG is a class A error.

PEF/LRC
PE format
error/LRC
Read only

Set in PE mode when an invalid
preamble or postamble is detected. Set
in NRZ mode when the LRC character
generated from readback data does not
match the LRC character read from
tape. Cleared by drive clear or INIT.

PEF /LRC is a class A error.

I NC/VPE
Incorrectable datal
vertical parity error
Read only

A PE read operation indicates that one
of the following has occurred:

INC/vpE is a class A error.

1.
2.
3.

Multiple dead tracks
Parity errors without dead tracks
Skew overflow

During an NRZ read operation,
indicates that a vertical parity error
has occurred or that data has occurred
after the skew delay is over. Cleared
by drive clear or INIT.

3-23

Table 3-11 (Cont)
Error Register Bit Assigrunents

Bit
05

DPAF
Data bus parity
error
Read only

Set By /Cleared By

Remarks

Set when a parity error is detected on
the Massbus data lines during a write
operation. Cleared by drive clear or
INIT.

DP AR is a class A error. Can be forced
set by the PAT bit (bit 04 of MTCS 2).

FMT
Format error
Read only

Set when a data transfer is attempted
with an incorrect format code (Le., the
tape format code loaded in the MTTC
register is not implemented on that
TM02). Cleared by drive clear or INIT.

Tape motion is inhibited; EXC and
EBL are asserted. DRY and ATA are
asserted on the negation of EBL FMT
is a class B error.

CPAR
Control bus parity
error
Read only

Set when a parity error is detected on
the Massbus control lines during a
control bus write operation. Cleared
by drive clear or INIT.

Detection of CPAR does not interfere
with the register write sequence except
during a write to the MTCS 1 register
which suppresses setting of the GO bit.
CPAR is a class A error. Can be forced
set by the PAT bit (bit 04 of MTCS 2).

RMR
Register modification
refused
Read only

Set when the controller attempts to
write into any implemented· TU16
register except the maintenance
register or the attention summary
register while the GO bit is asserted. If
RMR occurs, the addressed register is
not modified. Cleared by drive clear or
INIT.

RMR is a class A error.

ILR
megal register
Read only

Set when a read or write from a
non-existent register is attempted.
Cleared by drive clear or INIT.

No register modification should occur.

On a control bus read, all zeros are
gated onto the control lines. ILR is a
class A error.

ILF
megal function
Read only

Set when the GO bit is asserted and a
function code not implemented by the
TM02/TU 16 is attempted. Cleared by
drive clear or INIT.

3-24

ILF is a class B error.

Table 3-12
Error Conditions
OPERATIONS

ERRORS

Ot::

::!

Ot::

WRITE TO ANY REGISTER'"

READ FROM ANY REGISTER

LI..

::!

CII::

r:-

~
LI..

CII::

<:"

Q..

~
u
~

Ot::

....l

Q..

CII::

E-<

U
LI..

LI..

til

5 ~

til

LOAD NO-OP WITH GO= 1

LOAD REWIND OFF LINE WITH GO= 1

LOAD REWIND ON LINE WITH GO= I

LOAD DRIVE CLEAR WITH GO= 1

LOAD WRITE FMK WITH GO= 1

LOAD ERASE WITH GO= 1

LOAD SPACE FWD WITH GO= I

LOAD SPACE REV WITH GO= 1

LOAD WRITE CHECK FWD WITH GO= I

~
a::
0

X
X

LOAD WRITE CHECK REV WITH GO= 1

X
X

LOAD WRITE FWD WrTH GO= 1

LOAD READ FWD WITH GO';" 1

LOAD READ REV WITH GO=l

MASS BUS INIT
WRITE TO AS OR MT REG

X
X

"'Except MTAS or MTMR registers
TM02 operations with errors that could be detected during those operations and remain asserted after the operation is complete:
1

Most likely a programmer-caused error.
Possible operator errors (WRL, off-line).

3.6.8 Attention Summary (MTAS) Register (772456)
The attention summary register is a read/write "pseudoregister," which consists of from one to eight bits depending on the number of TM02s in the system. The term
"pseudo-register" refers to the fact that only one register
bit position is physically contained in each TM02. This bit

position reflects the state of the ATA status bit for that
TM02. Hence, bit position 0 of the attention summary
register is generated by the AT A bit of TM02 0, bit position
1 is generated by the ATA bit of TM02 1, and so on to bit
7. Bits 8 through 15 are not used.

3-25

Jnlike the other drive registers. the attention summary
·cgister is directly selected by the RH 11 controller without
lrst addressing a particular TM02. Thus, for a single
lttention summary register read operation, every TM02 in
the system responds by placing the state of its AT A bit in
the appropriate bit position on the control bus and
disa bling its remaining 15 control bus transmitters. Tlus
control bus cont1guration appears as a single register output
which collectively informs the controller of all TM02s that
require attention (Le., ATA=l). The programmer can then
selectively examine the error or status registers of each of
the affected 1M02s to determine the cause of the individual
attention conditions.

3.6.8.1 Setting the Attention Active (ATA) Bit _. The
ATA bit is displayed in bit 15 of the MTDS register .. and
indicates that the TM02/TU 16 requires servicing l \)
because it has become ready after completjon of a non-data
transfer operation (2) because of an error condition, or (3)
because of an important internal status change. AT A is
asserted only if the DRY (drive ready) bit is asserted. The
setting of the ATA bit docs not in itself prevent execution
of commands. If the ERR (bit 14-MTDS) or the sse (bit
06-MTDS) transitions from the negated to asserted state
while the DRY bit is set, the AT A bit will become asserted.
The ATA bit will also be asserted if the DRY bit,transitions
from the negated to the asserted st':lte at the time one of
the following conditions is met:

The programmer can also write into the attention summary
register; however, the significance of the bits being written
is unusual. Writing a 1 into a bit position resets the AT A bit
in the TM02 assigned to that bit position; however, writing
a 0 has no effect. This unique writing scheme allows the
controller to reset, after inspection, all summary bits that
were set, without accidentally resetting those bits that may
have become set in the meantime. The following table
illustrates the effects of writing into an attention summary
bit position.
ATA Bit
Before

Summary Bit
Written

ATA Bit
After

0
1
0

0
0

Figure 3-} 0 shows the bit usage of the attention summary
register and Table 3-13 provides a description of each bit.

[I
'--_.-

ERR is asserted

sse is asserted

The function code in the MTCS 1 register
denotes a space, erase, write tape mark, rewind
or read-in preset command.

EOT is asserted.

3.6.8.2 Clearing the Attention Active (ATA) Bit - The
AT A bit may be cleared by writing a 1 into its position in
the attention summary register. Parity is checked during the
control bus transfer which controls the writing of the AT A
bits, and if a parity error is detected, the ATA t-it will be
set at the completion of this transfer. The AT A bit will also
be cleared by issuing a valid drive clear command, by
asserting the [NIT line, or by loading a GO bit into the
MTCS 1 register while the ERR bit is negated.

0
0

ATA

I ir-I I I

ATA

IA:: I

A~TA]
01

--y

NOT USED
CP-1332

Figure 3-10 Attention Summary Register Bit Usage

3-26

Table 3-13
Attention Summary Register Bit Assignments
Bit

Remarks

Set By/Cleared By

15-08

Not used.

07-00
ATA 07-00
Read/write

Each bit sets when the corresponding
drive asserts its ATA bit. All bits are
cleared by Unibus A IN IT , drive clear,
or controller clear. Individual bits are
cleared by loading a function code
with the GO bit in the corresponding
drive or by writing a 1 in the AT A bit
positions of this register. Writing a 0
has no effect.

The description below applies only to clearing the AT A bit
by writing a 1 into it.
•

Clearing the AT A bit while ERR is asserted will
result in negation of AT A but will not affect
the status of the error register. No commands
except drive clear can be executed until the
error register is' cleared.

•

Clearing the AT A bit when the attention
condition is caused by normal completion of a
space, rewind, 'read-in preset or write tape mark
operation will, result in negation of ATA and
will result in no other drive status changes.

•

Clearing the AT A bit when the attention
condition is caused by assertion of SSC will
result in negation of ATA. SSC will remain set,
and unless it is cleared by drive clear or IN IT ,
completion of the next command will cause
AT A to become set.

of a power failure, issuance of drive clear may
(and INIT will) succeed in clearing SSC while
leavin'g a broken slave on the master-slave bus
waiting to abort the next command issued it.
BECAUSE OF THIS, SSC SHOULD NEVER
BE CLEARED BEFORE A DECISION IS
MADE TO POLL ALL AVAILABLE SLA VES
TO DETERMINE THEIR STA TVS.
•

Clearing the ATA bit when the attention
condition is caused by assertion of DRY while
EaT is asserted will result in negation of AT A
and will leave the drive ready to accept another
command. Note that detection of EaT during
tape motion will not generate an AT A and will
not cause an abort. The EaT flag is a warning
only, and it is the programmer's responsibility
to go no more than 10 feet beyond the EaT
marker.

3.6.9 Character Check (MTCC) Register (772460)
The check character register is a nine-bit, read-only register
that permits the programmer to check the validity of a data
transfer. At the end of an NRZ read operation, this register
contains the eRC character for that operation. Hence, the
programmer can determine if the CRCC generator logic is
functioning properly. At the end of a PE read operation,
however, this register contains a dead track indication
(DT= 1j of any track which may have dropped one or more
bits during the operation.

Note that SSC can be generated by up to eight
slaves in the TM02/TU16 tape system and that
its assertion may indicate status changes in
several slaves including the selected slave. Thus,
while a drive clear command will clear SSC and
SLA in a selected slave, unselected slaves could
continue to assert SSC. Moreover, if an unselected slave caused SSC to be asserted because

3-27

.6.9.1 CRC Character Storage - At the end of an NRZ
tead or Write operation, the CRC character read from tape
~ill be stored in bits through 8 of the MTCC register. The
~ast significant bit will be stored in bit 0, and the most
ignificant bit in bit 7 of this register.

Figure 3-11 illustrates the check character register bit usage
for both NRZ and PE modes and Table 3-14 provides a
description of each bit.

3.6.10 Data Buffer (MTDB) Register (772462)
This register provides a maintenance tool to check the Silo
data buffer (DB) in the RHll. A total of 66 10 words is
accepted before the Silo data buffer becomes full. If the
program attempts to write into the data buffer while it is
full, a DLT (data late error) is posted. If the program
attempts to read the data buffer when it is empty, a DLT
error will be posted. Successive reads from the DB read out
words in the same order in which they were entered into
the Silo.

NOTE
The check character register will contain the
check character described above at the end of a
read or write operation when DRY transitions
from a 0 to a 1. Bits 00 through 08 are
guaranteed true only as long as DRY is equal to
1.

The IR (input ready) and OR (output ready) status
indicators in the MTCS2 register are provided so that the
programmer can determine when words can be read from or
written into the MTDB. IR should be asserted before
attempting a write into DB; OR should be asserted before
attempting a read from DB.

3.6.9.2 Dead Track - The dead track register is normally
lsed for maintenance to determine which tracks are
~iropping data bits. The dropped data bits (read data) are
Driented with the following binary weights.
Dead Track

Binary Weight

DTO

2°

DT]

DT2

22
23
24
2s
26
27

DT3

DT4
DTS
DT6
DT7
DTP

The MTDB register can be read and written oniy as an
entire word. Any attempt to write a byte will cause an
entire word to be written. Reading the DB register is a
"destructive read-out" operation: the top data word in the
Silo buffer is removed by the action of reading DB, and a
new data word (if present) replaces it a short time later.
Conversely, the action of writing the DB register does not
destroy the "contents" of DB; it merely causes one more
data word to be inserted into the Silo buffer (if it was not
full). Figure 3-12 shows the MTDB bit usage, and Table
3-15 provides a description of each bit.

)

y---

[0 I

CRC
CHARACTER

.-1

NOT USED

C~1~~

NRZ
FOHMAT

FORMAT

-----y---

IDTP IOT7 IOT6 lOTS IOT4 Ion

I..

)

NOT USED

---y

1m OT1F~
-..l

DEAD TRACK
CP-i333

Figure 3·11 Check Character Register Format

3·28

Table 3-14
Check Character Register Bit Assignments
Bit

Remarks

Set By/Cleared By

15-09

Not used.
Contains the CRC character and parity
bit in NRZ mode or the dead track
register in PE mode.

08-00
CCD
Check character /
dead track
Read only

CP-1334

Figure 3-12 Data Buffer Bit Usage

Table 3-15
Data Buffer Bit Assignments
Bit

Set By/Cleared By

Remarks

15-00
DB 15-;-00
Data buffer
Read/write

When read, the contents of OBUF
(internal RH 11 register) are delivered.
Upon completion of the read, the next
sequential word in the Silo will be
clocked into OBUF. When written,
data is loaded into IBUF (internal
RH 11 register) and allowed. to
sequence into the Silo if space is
available.

Used by the program for diagnostic
purposes. When the register is written
into, IR is cleared until the DB is
ready to accept a new word. When the
register is read, it will cause OR to be
cleared until a new word is ready.
During a write-check error condition,
the data word read from tape which
did not compare with the corresponding word in memory is frozen in
MTDB for examination by the
program.

3.6.11 Maintenance (MTMR) Register (772464)
The maintenance register is a 16-bit read/write register
which performs the following functions:

Provides data wraparound paths for checking
the data formattin·g logic in the TM02.

Provides a means for testing error detection
circuitry within the TM02.

Acts as a storage buffer for the longitudinal
parity check (LRC) character when operating in
NRZ mode and performing a forward read or
forward write operation.

Figure 3-13 shows the maintenance register bit format and
Table 3-16 provides a description of each bit.

3-29

)

y
MAINTENANCE
DATA FIELD

~~----------y~-------~
MAINTENANCE
CP-1335
OPCODE

Figure 3-13 Maintenance Register Bit Usage
Table 3-16
Maintenance Register Bit Assignments
Bit

Set By/Cleared By

15--7

These bits buffer the data generated
during wraparound operations. At the
end of normal NRZ transfers (except
read reverse), these bits contain the
LRC of the last record. MDF 0 con~
tains the parity bit for the maintenance data character. MDF 1 contains
the LSB of the maintenance data
character and the remain bits are
contained in order in MDF 2 through
MDF8.

MDF 8-0
Maintenance
data field
Read/write

Remarks

BPICLK
Two-hundred
BPI clock
Read only

Displays a clock signal derived from
the crystal oscillator in the selected
slave. The clock frequency is dependent on the read/write speed of the
selected slave and is equal to the
frequency at which a continuous
succession of characters is written on
tape when operating at 200 characters
per inch density.
BPICLK is displayed to aid in monitoring of drive functions during maintenance mode operations".

MC
Maintenance clock
Read/write

Cleared by drive clear or IN IT .

3-30

This bit controls the sequencing of
data through the TM02 data paths
when operating in maintenance mode.
If the GO bit is asserted and a maintenance op code of 4 8 , 58, or 6 8 is
contained in MOP bits 0 through 3,
the MC bit changes state each time a
control bus write to the maintenance
register is executed. If the GO bit is
asserted and an op code of 3 8 is
contained in MOP bits 0 through 3,
the MC bit changes state after each
read strobe occurs. The maintenance
op code is described under bits 4
through 1 in this table.

Table 3-16 (Cont)
Maintenance Register Bit Assignments

Bit

Remarks

Set By/Cleared By

4-1

These bits control the maintenance
function which will occur when the
MM bit is set to 1 and the TM02 is
loaded with the appropriate command.
The following op codes will be implemented:

MOP3-MOPO
Maintenance
op code 03-00
Read/write

a.
h.

3-31

0000 - Null code
0001 - Interchange read
In NRZ mode, this op code
causes a more stringent skew
check to be made on data during
read or write-check operations.
In PE mode, this op code suppresses on-the-fly correction of
data errors resulting from a
single dead track.
0010- Even parity
Causes an even pari ty bi t to be
associated with data sent from
the TM02 to the controller on
either the da ta or con trol bus
lines, thereby causing the controller to detect parity errors.
0011 - Data Wr . lparound,
Global
Causes execution of a write forward .command to be executed
as follows:
Data is brought in on the data
lines, divided into bytes using
the algorithm defined by the
format code in the tape control register, formatter as
either NRZ or PE write data,
multiplexed into the read circuitry and deposited in the
maintenance register data
field.
In PE mode, every other character generates a read strobe
to allow the programmer sufficient time to write and
monitor a loop.

Table 3-16 (Cont)
Maintenance Register Bit Assignments
Bit

Remarks

Set By/Cleared By

4--1 (('ont)

3-32

0100
Data Wraparound.
Partial
Causes execution of a write forward command to be executed
as follows:
Data is brought in on the data
lines, divided into bytes using
the algorithm defined by the
format code in the tape control register, formatted as
either NRZ or PE write data,
and deposited in the maintenance register data field.
0101 -- Data Wraparound,
Forma tter Write
Causes execution of a write forward command to be executed
as follows:
Data is brought in on the data
lines, divided into bytes using
the format code in the tape
control register, and deposited in the maintenance
register data field.
OlIO-Data
Wraparound,
Formatter Read
Causes executjon of a read command to be executed as follows:
Data is taken from the maintenance register data field,
multiplexed into the formatting logic byte-by-byte,
formed into data bus words
using the a1gorithm defined
by the format code in the
tape control register, and
transmitted to the RH 11 controller.
In addition, this op code suppresses reception of the Massbus
WCLK signal. Thus, an attempt
to perform a write operation
with this op code in the main tenance register will result in detection of a .drive timing error
(DTE).

Table 3- 16 (Cont)
Maintenance Register Bit Assignments
Bit

Remarks

Set By/Cleared By

4-·1 (Cont)

MM
Maintenance mode
Read/write

Must be set to a 1 when any maintenance mode function is desired.
Setting the MM bit to 1 does not
initiate any action on the part of the
drive but alters the manner in which
the drive executes various commands.
The manner in which the command
execution is altered depends on the
maintenance op code in bits 4 through
1 of this register.

3-33

0111
Cripple Reception of
OCC
An attempt to perform any data
transfer operation with this op
code in the maintenance register
will result in detection of DTE.
1000 - In NRZ mode, this op
code suppresses initialization of
the CRC checking logic, resulting in CRe errors.
In PE mode, this op code suppresses detection of data in
logical track 1.
100 1 - This op code causes bit
5 of tape data bytes to remain in
the asserted state.
In PE mode, this op code suppresses detection of data in
logical tracks 1 and 2.
1010 - Maintenance Mode End
of Record
This op code is used to signal the
end of a maintenance mode
operation causing the GO bit to
become negated.
1011 - Causes logical bit 1 of a
PE preamble and postamble to
be inverted during a write forward command, resul ting in
generation of invalid preambles
and postambles.

must loop on RDY and DRY to establish when the job is
done. This method is impractical in a sophisticah.'d programming environment since it requires a dedicated CPU.

3.6.12 Drive Type (MTDT) Register (772466)
The drive type register is a 16-bit read-only register, the
content of which identifies the particular type of storage
device (transport) being used. Bits 0 through 8 (DT 0-8) of
the drive type register identify the type and status of the
selected transport. If a nonexistent transport is selected or
if the selected transport is not powered up, DT 0-8 will
contain 010 8 , If the selected transport is powered up, but is
not a TUI6, DT 0-8 will contain 0128 to 017 8 , depending
on the type of transport. If the selected transport is a TU16
and is powered up, these bit positions will contain 011 8 •

Device-Interactive with Unmonitored Stahls- In this
method the programmer assumes the correct status exists
(WRL, MOL, SPR, PIP) and issues a command without first
checking status. If the wrong status exists, the command
will abort and the system must have the facility to cause
error correction through the error handler. This method has
two disadvantages: (1) the error handler must be expanded
to allow the status error recovery, and (2) IE should only
be set when a command is to be executed: consequently,
the system does not become aware of status changes
through the interrupt facility. As a result, dequeuing of
requests to a multi-transport system is not p(.:rmally
possible without use of a real time clock (RTC') and status
polling.

Figure 3-14 shows the drive type register bit usage and
Table 3-17 provides a description of each bit.
3.6.13 Serial Number (MTSN) Register (772470)
TIle serial number register is a 16-bit, read-only register
which contains a BCD representation of the four least
significant digits of the transport serial number.

Device-Interactive with Monitored Status - In this method.
the software checks the status previous to issuance of a
command. The disadvantage is that IE should only be set
during command execution and "mUlti-transport" dequeuing is not possible without use of a real time clock and
polling of slave status.

Figure 3-15 shows the serial number register bit usage and
Table 3-18 provides a description of each bit.
3.6.14 Tape Control (MTTC) Register (772472)
The tape control register is a 16-bit read/write register
which selects an existing transport, the data format, and the
density.

Monitored Status via Intermpt Facility .- In this method,
IE is always set except while actually servicing an interrupt.
Because the system is always monitoring "slave-sta tus
changes" and "attention active" on all TU 16s and TM02s,
dequeuing may occur as soon as the device becomes ready.

Figure 3-16 shows the tape control register bit usage and
Table 3-19 provides a description of each bit.
3.7 PROGRAMMING EXAMPLES
The T1U 16 tape system allows the software to monitor the
status of all transports at all times (via SSe) and to monitor
the readiness of all drives to receive new commands (via
ATA bits). This, however, is a programmer's option.
Actually there are four ways to program the TJU16 system.

NOTE
This method is capable of controlling multi·
drives and multi-transports simultaneously. In
the other three modes. if dequeuing is to be
done it must be done via the "system clock"
facility, and the RH 11, TM02, and TU 16 must
an be assigned to the user.

Dedicated Processor - In this mode the interrupt enable bit
(IE) is never set and the processor must check status on the
RHll controller, TM02 tape controller and the TU16
transport before initiating each command. The program

The following paragraphs show several typical programming
examples. These are write, read, space, and tape mark
operations.

Figure 3-14 Drive Type Register Format

0·1

D[l;J
~

v
DRIVE TYPE

3-34

(08-00)

CP-1336

Table 3-17
Drive Type Register Bit Assignments'
Bit

Set By/Cleared By

Remarks
Neither drive clear or INIT affect this bit.

NSA
Not sector
addressed
Read only

Always set to indicate that the device
is not sector addressable.

TAP
Tape
Read only

Always set to indicate that the device
is a tape transport.

MOH
Moving head
Read only

Always negated to indicate that the
device is not a moving head unit.

7CH
7 Channel
Read only

Asserted if the selected transport is a
7-channel unit. Always negated if the
selected transport is a TUI6.

DRQ
Drive request
required
Read only

Always negated to indicate that the
device is a single-port device.

SPR
Slave present
Read only

Asserted when a transport is powered
up and has been assigned the selection
code contained in the MTTC tape
control register.

Not used.
Contains the drive type number for
the selected slave (118 for the
TM02/TUI6). If no slave is assigned in
bits 0-2 of the MTTC tape control
register, the drive type code readback
is 010 8 . If a slave has been assigned a
select code in bits 0- 2 of this register,
the drive type code will be a code
from 118 to 178 . Drive clear or INIT
do not affect these bits.

08-00
DT 08-00
Drive type
Read only

3-35

SN1;]N
01

~--~--~----~--~----~--~--~----~--~----~--~--~----~--~--,

'------v-------''-------..v.--------)'------'''''''v.--------)'-------y-------.J
10

diOlt

0
10 dlOlt

dlOlt

CP-'331

Figure 3·15 Serial Number Register Bit Usage

Table 3-18
Serial Number Register Bit Assignments

' - - - - - - - - - - - - - , . - - - - - - - - - - - - - - - -__r---------------'"""'-,..._Bit

Set By/Cleared By

Remarks

15-12
SN15-SNI2
Read only

Most significant BCD digit (10 3 ) of
slave serial number.

11-08
SN11-SN08
Read only

102 digit of slave serial number.

07-04
SN07-SN04
Read only

10 1 digit of slave serial number.

03-00
SN03-SNOO
Read only

Least significant BCD digit of slave
serial number.

___

~,~L ~~~~ ~~~~~ ~~~~S,~~0J
' - - - _ - - - . . J I . ._ _ _ _ _ _ ,._-------'

--y----

DENSITY
SELECT

FORMAT
SELECT

'------...v,------J
SLAVE
SELECT
CP-1338

Figure 3·16 Tape Control Register Bit Usage

3-36

Table 3-19
Tape Control Register Bit Assignments

Bit

Remarks

Set By/Cleared By

ACCL
Acceleration
Read only

Set when the transport is not actively
reading or writing data.

ACCL is not affected by drive dear nr
INIT.

FCS
Frame count status
Read only

Normally set at the end of a write into
the frame count register. Cleared when
count register overflows.
frame
Cleared by drive clear or INIT.

Loading a space or write command
with the GO bit asserted and FCS
equal to 0 will cause a non-executable
function (NEF-bit 11 of drive status
register) to be asserted and will cause
the command to be aborted. No tape
motion will occur.

TCW
Tape control write
Read only

Set when a control bus write operation
to the tape control register is performed. Cleared by the. initiation of
any command requiring tape motion.

TCW is used by the TM02 to determine whether or not to wait for the
completion of the settle down process
(SOWN-bit 4 of the drive status
register). If TCW is asserted, SDWN
should be negated before issuing a new
command to the selected slave.

EAODTE
Enable abort on
data transfer errors
Read/write

This bit, when written to aI, will
cause a data transfer operation to be
aborted as soon as one of the following errors is deleted:
a.
b.
c.
d.

DPAR-bit 5 of MTER register
COR/CRC-bit 15 of MTER
register
FMT/LRC-bit 7 of MTER
register
INC/VPE-bit 6 of MTER register

Not used.
Specifies the tape character density
during read or write operations as
follows:

10-08
DEN2-DENO
Density select

DEN2

DENl

DENO

0
0
0
0

0
0

0
1
0

Density
(bpi)

200 }

556
800
800

NRZ

1600

1
0

}

Reserved

Drive clear and INIT do not affect the
density select bits.

3-37

Table 3-19 (Cont)
Tape Control Register Bit Assignments

Bit

Set By/Cleared By

Remarks

07-04
FMT SEL 3-0
Format select
Read/write

Specifics Massbus-to-tape character
formatting during a write operation, or
tape character-to-Massbus formatting
during a read operation (para. 1.7.1).
If the FMT SEL bits specify a format
not implemented on a TM02/TU 16
system and a valid data tramfer command is loaded in the MTCS 1 register
with the GO bit asserted, the format
error bit (FMT-bit 4 of the MTER
register) will be asserted and the operation will abort (Figure 1-10).

If this bit is set in NRZ mode, even
parity will be written on tape and even
parity is expected on read-back. If this
bit is reset, odd parity will be written
on tape and will be expected on
read-back. When the TM02 is operating in NRZ with EV PAR set, it will
not allow an all zeros character to be
written on tape. If an all zeros character is presented to the TM02, the
TM02 will invert binary bit 4 and the
parity bit before writing the character
on tape. This converts 000 8 to 020 8 .

EV PAR
Even parity
Read/write

This bit is ignored in phase encoded
(PE) mode (DEN2=1). In PE mode,
odd parity is always used.

02-00

Specifies the unit number of ihe transport to be used. Drive clear or INIT
does not affect SS2-0.

SS2-0
Slave select
Read/write

3-38

3.7.1 Write Data Transfer
The write data transfer causes data words from memory to
be transferred to the RH 11 Massbus controller, then to the
TM02 tape drive where they are converted into tape
characters and finally to the slave transport where they are
written on tape. A typical sequence of steps necessary to
initiate a write data transfer is enumerated below. It is
assumed that this is the first record to be written on tape.
As a result, additional steps are required that would not be
necessary when writing subsequent records.

NOTE
If the tape is not at BOT, issue a rewind

command. However, the DRY bit rnust
be set. To issue the rewind command,
load a function code of 078 (GO bit
asserted) into the MTCS 1 control Tl'gistcr.
The DRY bit will temporarily be negated
and will be reasserted as soon as the
rewind function is transmitted to the
slave. This allows the drive to accept
another command before completion of
the rewind.

Issue an RH 11 clear by setting bit 5 in the
MTCS2 register in the RH 11. (First time only
error bits should be cleared by the error handler
and ATA bits by the interrupt handler).

Select a TM02 tape drive by writing bits 0
through 2 of the MTCS2 status register in the
RHll.

Read the MTDT drive type register in the TM02
to see what type of drive is specified. In this
case, bit 14 (TAP) should be set indicating a
tape drive.

Read bit 12 (non-existent drive) of the MTCS2
status register to see if the drive that was
addressed is an actual drive.

Read the following bits in the MTDT drive type
register.

Examine the MTER register for errors. If the
error is a TM02/TVI6 error, a drive clear
should be issued which clears only the selected
drive. The drive clear is issued by loading a 118
function code in the MTCS 1 control register
with the GO bit asserted. If the error is an
RH II error, an INIT should be issued. The
INIT is issued by setting bit 5 (CLR) in the
MTCS 1 register.

When rewind is completed, the slave will assert
SSC which will cause the TM02 to raise ATTN
on the Massbus. In addition, the PIP bit will be
negated and BOT asserted. The clear can be
accomplished by performing a drive clear to the
TM02.

Read the MTDS drive status register and monitor the following bits.

Bit 10 (SPR) - This bit is set if the slave
specified in bits 0 through 2 of the MTTC tape
control register is powered up and properly
assigned.
Bits 0 through 7 - These bits specify the drive
type and are designated 0118 for the TV 16
slave transports.
6.

Bit 15 (ATA) - This bit will set immediately (if
DRY is set) to indicate status change (completion of the rewind operation). If DRY is
negated, ATA will be asserted as soon as DRY
is asserted.
Bit 14 (ERR) - If this bit is set, it indicates an
error condition that can be detennined by
reading the MTER error register. At this point,
the software should enter the error recovery
procedure.
Bit 6 (SSC) - This bit will be sct indicating
completion of the rewind operation.
Bit 1 (BOT) - This bit is set since the selected
slave detects the BOT marker when the rewind
is completed.

Read the following bits in the MTDS drive
status register.
Bit 12 (MOL) - If the medium on-line bit is
set, the drive is powered up and ready to go.
Bit 11 (WRL) - If the write locked bit is set,
the write operation is inhibited and it is
necessary to insert the write enable ring.
Bit 07 (DRY) - If this bit is set, it indicates
that the drive has concluded a previous operation (if one was specified) and is prepared to
accept or send data.
Bit 01 (BOT) - This bit is set if the tape is at
the BOT.

10.

3-39

Select the format, density and type of parity by
writing the MTTC tape control register in the
TM02. The format is written into bits 4
through 7 of the MTTC register (paragraph
1.7.1).

The density is selected by writing bits 8
through lOin the MTTC register and is
described in Paragraph 3.6.14. The parity can
be specified even or odd for NRZI operation by
writing bit 3 of the MTTC register. If this bit is
set, even parity is read or written from tape.
Odd parity is always performed during PE
operation.

11.

Select the starting memory address by writing
the MTBA bus address register in the RH 11.

12.

Select the number of 16-bit data words to be
transferred by writing the MTWC word count
register in the RH 11 with the two's complement of the number of words to be transferred.

13.

Load the MTFC frame count register in the
TM 02 with twice the word count for normal
format and with four times the word count for
core dump format. For normal format, two
tape characters are generated for each I6-bit
word, and, for core dump, four tape characters
are generated for each I6-bit word.

The read function code of 718 (with GO bit
asserted) is loaded in the MTCS 1 register
instead of the write function code.

If it is desired to do a read reverse operation,
the MTBA bus address register should be loadrd
with the start of the buffer plus the size of the
record since the RHl1 decrements the bus
address in a read reverse whereas it increments
the bus address in a read forward operation.
3.7.3 Space Operation
When a space operation is desired, the software must
specify the spacing length by loading the MTFC frame
count register with the two's complement of the number of
records it is desired to space.
A space operation will terminate either due to frame count
overflow (desired records are spaced over) or when BOT,
EOT, or TM (tape mark) is detected (signifying the end of
the me). The space operation allows random access of any
record within any file on tape.

3.7.4 Tape Mark Operation
To perform a write tape mark operation (to indicate the
end of me for example), it is merely necessary to load a
278 function code (with GO bit asserted) into the MTCS 1
control register. This can be monitored by reading bit 2
(TM) of the MTDS drive status register. When the bit is set,
the tape mark is detected.

14.

Load the MTCSI register in the TM02 with the
write function code (GO bit asserted) of 61 8 • If
the interrupt facility is employed, set the IE bit
(bit 6 of the MTCSI register in the RHII).

15.

Read bit 4 (IDB) of the MTDS drive status
register. Upon completion of writing the
record, this bit should be set if PE density is
selected and should be cleared if NRZI density
is selected.

Tape marks can be used to indicate logical end of tape. A
single tape mark indicates termination of the previous file
while two tape marks indicate the logical end of tape (no
more data has been written).

1rus procedure will cause one record to be written on tape.
ff it is desired to write another record, it is merely
necessary to reload the MTBA bus ad.dress register, the
MTWC word count register, and the MTFC frame count
register. Then the data transfer can be implemented by
loading the MTCSI register with the 618 write function
~ode (GO bit asserted).

3.8 SUGGESTED ERROR RECOVERY
Table 3-20 gives the suggested procedures for recovering
from drive or controller errors. The numbers in the column
titled "Recovery Procedure" are keyed to the following
steps:

3.7.2 Read Data Transfer
In order to do a read data transfer, a similar operation to
that just described is followed with the exceptions listed
below.
1.

It is not necessary to write the MTFC frame
count register, as this is automatically cleared
[or a read data transfer.

If not programmer or operator error, then this
condition is fatal. Disconnect from drive, report
error to operator.

Tape position is lost, three possible recovery
procedures are indicated.
a.

340

If physical position of desired record i~
known, Rewind, Space Forward to
desired record and retry.

The error classes are:
Oass A: EXC is asserted immediately but
transfer to the end of the current sector is
completed and normal EBL is asserted.

If neither alternatives a or b are possible
or practical, consider error fatal.

Class B: EBL and EXC are asserted immediately. Data transfer stops.

Step
a.

Read Reverse

Read Forward

Repeat steps a and b until successful or
re-try count overflows (suggest 20
re-tries)

NOTE

If each record contains an identifiable
label (or sequence number), Read FWD
and/or Read REV commands may be
used to re-establish tape position.

If re-try count
operator

The numbers in the "Possible Operator Error" column are
keyed to the following steps:
Possible Operator Errors
1.

Wrong unit number (plastic button) plugged
into TM02.

Dirty read/write heads or tape path (operator
PM). Also could be bad tape.

Operator did not insert rubber write-ring before
mounting tape which was to be written on.

Wrong unit number (plastic button) plugged
into TVI6, or tape not loaded with vacuum on.

overflows, report to

Step
a.

Back-space

Erase

Re-write record

Repeat steps a, b, and c until successful
or re-try count overflows (suggest 20
re-tries)

If re-try count overflows, report error to
operator

Operator did not load tape to BOT, program
initiated a rewind, and tape unloaded. Power
was removed from TV 16.

Report failure to operator

3-41

Table 3-20
Error Recovery Procedures
- - , - - - - - - - -_._-----_._-MTER
Bit Position

Namc

Ik"-·~iption

rapc Position
Lust

Possihle
Operator Error

rypc

Bad Data
I Transferred

Class B

Program is selecting function
code not implemented on
TJUI6_

! Class A

Program is selecting a register
which does not exist on TM02.

None

Program did not check for
DRY = I before writing a
register (other than AS or MR).

Class A

None

None if programmer is nut usmg
Maintenance register.

Class B

None

Programmer is selecting a format
code which does not exist.

I Class A

Yes

None

None if programmer is not using
PAT bit in RHII.

WE READ)-3

Yes

None if programmer is not using
Maintenance register.

(NRZ READ)-3
(NRZ WRITE)-4

Yes

None if programmer is not using
Maintenance register.

_ _~

Indicat~, lltilt all illq~aII"III1L-

Illegal Function (llF)

-,--

Recovery
Procedure

;

11011 ,ode lias neell Irall"lIlJtlcd.

Possible Programmer Error

IlIlii(att's Ihal a read or wrile
IrUIll a 11011,' XlstClit re~lstcr
is art~mpkd

Illegal Register (ILR)

I
02

Ind".:al~" 'It"I while a trans·

port "pl'fatl,Hl is in p[(l~ress
(;0 = I J. a write into one
01 lilt: registers is allempled.
(o.. ..:~ lIot ..IPI,ly for the
Mailltenanc~ or Attention
Summary registers.)

Indicates that a data transfer with an incorrect format
cude is attempted.

Format (FMT)

Indicates Ihat incorrect data
bus parity has occurred during a write data transfer
(i.e., bad data transferred
to the TM02 and written on
tape.)

Data Bus Parity Error
(DPAR)

:; Class A
i
I
I
I

!
I

I
I

II
Class A

During a PE data transfer
operation, indicates that an
incorrectable data error has
occurred.

Incorrectable Data Error
or Vertical Parity Error
(lNC/VPE)

Indicates that incorrect COlltrol bus parily was detected
during an attempt io write
a TM02 register.

Control Bus Parity «(PAR)

I
I

During an NRZ data transfer
operation, indicates that a
vertical parity error has
occurred or that data has
occurred after the skew
delay is over.

II
I
I

I (PE WRITE)-4

Table 3-20 (Cont)
Error Recovery Procedures

MTER
Bit Position

Description

Name
Format Error or LRC
(PEF/LRC)

TYI,e

Recovery
Procedure

Tape Position
Lost

Bad Data
Transferred

Pos.~ihle

Operatof Error

~(I

During a PE da ta transfer
operation, indicates that an
incorrect preamble ur postamble is dete~lcd_

('lass i\

(PI' READ) -3
(PE WRITE) -4

Maybe
Yes

Indicates thai the LRCe
which was written on tape
does not agree with the
LRCC calculated on the
data during a "read" command execution or during
the read after write operation which happens on a
"write" command execution_

Class A

(NRZ READ)-3
(NRZ WRITE)---4

Maybe 2
Yes

Possible Programmer Error
None if programmer is not
utilizing Maintenance register_

Nonstandard Gap (NSG)

Indicates that a tape character is detected during the
first half of the inter-record
gap_ (i.e., tape unit thought
it saw end of record but
detected more data after
shut-down process began.)

Class A

(READ)--3
(WRITE)-4

Maybe I
Yes

None if programmer is not
utilizing Maintenance register_

Frame Count Error (FCE)

Indicates that either:
I) a space uperation has terminated and the Frame
Counter is not cleared.
(This is not a hardware
failure if space operation
was terminated by TM,
EaT, or BOT if that
termination was expected_)

Class A

(SPACE)-2

Yes

Programmer loaded wrong frame
count on space command_

(WRITE)-I

Yes

None

Programmer loaded a word count
value which was not proportional
to the frame count.

2) A write command was
executed and the frame
count overflowed before
the word count.
3) A read command was
executed and the end of
record was detected before
word count overflow.

Table 3-20 (Cont)
Error Recovery Procedures
...

_. _._--,------,---------.---

MTER
_B_il_P_llS_·i_tio_n_+-_ _ _ _N_·a_m_e_ _ _ _-+_ _ _ Oeso:riPlioll
10

Currectable Skew ll[ lHe~al
Tape Mark ((,S(ITM)

D\lf1Il~ ,,1'1-. d"!J ('Jnsler opcration. indicates til;l! l'xc~ssive
but corrcctahlc '~l'W is detected
for read. (ThiS condition is only
a warnin!! alld d",'s ml! indicate
bad data.) For a wllte, it indicates that data I,f '1ucstionable
quality was wfllten and the
record should oe re-written.

Nonexecutable Functiun
(NEF)

Recovery

Bad I)ala

Ty_p_e_-+_ _P_n_)c_ed_u_r_e_ _ _+-T_r_a_r~_'_~~m'l

(I'I: RFADI None
(I'E WRITE) 4

Cia,s A

Tap~-;():~:-r-- Possible
Lust

_._~ Ollerator Error

,,~-----

----2---1-,1'

Pos.'>ible Programmer Error

--N-on-e--------

None

Software lost track of tape
position

None

Programmer did not check WRL
status.

None

Program did not keep track of
tape position.

(NRZ Read or Space)
TMK expected· None

( NRZ Read or Space)
TMK not expected--5

Yes

Y~s

Yes

Program selected a transport
incapable of density mode
specified_

4) b
A space ori
writeL
operation l
is
attempted when FCS = 0 in
the Tape Control register.

Program is trying to write
without specifying record
length.

5) An NRZ write operation is
attempted with the 2s complement of a number less
than 13 in the Frame Count
register.

Program is specifymg record
length shorter than minimum of
13 characters.

In NRZ mode, indicative of
illegal tape mark written on
tape after 3 "write tape mark"
comlnand, or Rl;"ad from tape
after a Read or Space command_

i
I

. . . !I

IndIcates one ot the tollowmg:
Class B
I) A write operation is attempted
on a write.protected transport.

2) A Space Reverse, Read reverse,!1
or Write Check Reverse is
I
attempted when the tape is
I
at BOT_

I
I (NRZ Write TMK)-4
I

11.1

3) The DEN2 bit in the Tape
Control register does not
agree with the PES status

I
I
I
I

Table 3-20 (Cont)
Error Recovery Procedures

Name

Description

Type

Drive Timing Error (DTU

Indicates one of the followillg:
I) During a write operation,
the controller did 1I0t supply a tape character to
TM02.in time for it to be
written.

Class B

2) A data transfer (read/write)
was attempted when the
data bus of the Massbus
was already occupied (i.e.,
transfer in progress on
some other drive).

Operation Incomplete (OPI)

I) During a read or space
operation, indicates that
a tape record has not
been detected within
7 sec from command initiation. Assume that the
drive is beyond valid data
on the tape.
2) During a write operation,
indicates that a read-afterwrite tape record has not
been detected within 0.7
sec from command initiation. Assume write operation
has failed.
3) Additional data has been
detected after minimum gap
length has been traversed.
This condition causes a loss
of tape position.
4) Rewind command initiated,
tape already at BOT

Class B

Possible
Operator Error

Bad Data
Transferred

Tape Position
Lost

Yes

None

Program did not check controller "ROY" before issuin~
data transfer command.

Yes

None on a write operation.
On a Read or Space, programmer
did not keep track of tape position.
On a Rewind operation, programmer did not check for BOT
before issuing command.

Recovery
Procedure

MTER
Bit Position

Possible Programmer Error

Table 3-20 (Cont)
Error Recovery Procedures
_. .__
MTER
Bic Position

Dco,criptinll

Name

-----...:-----------'-----_._-_. _.
14

Unsafe (l'NSl

._._[

r~ 11C
._---

----r=:Recllverv
Procedure

---------

...

Bad Data
Transferred

h_h·· . -

------.----! ----.-.---

Indll•.:alco; IHIt~ nt tht' fuiill'WlIl;!

Yes
I
(If tramfer '

I) A progr'lIl1-<:olltrnlleJ opera·
lion" alll'lIlllled 011 a sck(·
led t.camport which IS rwt
jJowcJ\,d lip oll·IIIIC. V,Klll1l1l

wa, In
progress)

.• -

Tapt' 1)lIsililln
Losl
.____

Yc's

Pu\.sible

L ~~per;~tnr_~~.~-'- Possible Programmer Error

I
I
I
!

I
I

Program did not check MOL
before issuing cummand.

Oil.

2) An imminent IlI.wer failure
is dell'clcd (AC to l.).

Correctable DatJ Error
or CRC' Error (COR/CR(')

During a PI·: rcad o~ralion,
indlcatcs Ihat J ,lOgic dead
track has occurred. (Data is
co~rected, Ihis is .mly a
warning.)
PE Wnte - questionable
quality. Re·write.
During an NRZ operation,
indicates that the CRCC
read off the tape does not
match the CRCe computed
from the data read off the
tape.

(PE READ) .. ~one
t PI' WRITE)--4

Yes

(NRZ READI-3
(NRZ WRITE)-·-l

Maybe 2
Yes

I
:

None

I
I
I

Table 3-20 (Cont)
Error Recovery Procedures
-"-

MTCS2
Bit Position

Recovery
Pron-durt>

Name

Oescritpion

TYPl'

Masshus Data Bus Parity
Error (MDPE)

Set when a parity <!rror occurs
on the Massbus data bus while
doing a read or write-check
operation.

Cia" A

Missed Transfer (MXF)

Set if the drive does not respond
to a data transfer command
within 250 ms.

Class B

ProGram Error (PGE)

Set when the program attempts
to initiate a data transfer operation while the RHII is currently
performing one.

Class A

Non-Existent Memory
(NEM)

Set when the controller is
performing a OMA transfer
and the memory address
specified in MTBA is nonexistent (does not respond
to MSYN within 10 [J.S.

Bad Data
Transferred
Yes

Tape Position
lost

Possible
Operator Error

Possible Programmer Error

:-.Jo

:-.Jone

None if programmer IS not
using PAT bit in RIIII.

No
(No data
has been
transferred)

:-.Jone

Programmer loaded a data
transfer command into a
drive which has ERR set.

None

Program did not check ROY
prior to issuance of data
transfer command.

Class A

Yes
(Transfer
incomplete)

None

Program specified memory
loca tions (via WC & .BA
registers) which did not
exist.

Non-Existent Drive
(NED)

Class A
Set when the proglam reads or
writes a drive register (CSI, OS.
ER, MR, FC, OT, CK, TC, or SN)
in a drive [selected by U(02:00)J
which does not exist or is powered
down. (The drive fails to assert
TRA within 1.5 [J.S after assertion
of OEM.)

Program attempted to read or
write a drive register on a drive
that did not exist.

Unibus Parity Error (UPE)

Set if the Unibus parity lines
indicate a parity error while the
controller is performing a Write
or Write-check command.

Class A

Yes

None

Table 3-20 (Cont)
Error Recovery Procedures
!Je:.;::jiH

-----------

MTCS2
wll

Wntc Chcd; bror (WeE)

lh~ (t)nt":I~~-r-~~-1

Set when
pcrformlllg a wrlle-check
operation and a wort! 011
the tape docs 1I0! lIlatdl
the correspondmg word
in memory_

Data laTe (DLT)

Set when the COlltroller is
unable to supply J data
word during a Wfltc operation or ac.:cpt a data word
dunng a read or wnte-,heck
operation at the lim" the
drive denlands a transfer_

Type
('lass A

Recovery
I Pwcedurt'
I

Bad Data
Transferred

Yes

r--;a;~::::_r_PI)~,ible

I Possible Programmer Error

Lost

t---;,---r-N~~:---- --+-I-Non-e- - - -

I
I
I

I
I

! Class A

IWRITE--4
READ-3

Yes

I or~rator Error

I
I

None

I
I
Program issued UNIBUS B
I INIT
while PSEL 1_
=

I
MTCSI
Bit Position

Name

Description

Massbus Control Bus
Parity Error (MCPE)

Set by parity errOr on
Massbus control bus while
reading a remote register
(located in the drive).

Transfer Error (TRE)

Set by DLT or WCE or UPE
or NED or NEM or PGE or
MXF or MDPE or a drive
enor during a data transfer.

Type
Class A

Recovery
Procedure

Bad Data
Transferred

Tape Position
Lost

III

Pombk
Operator Error
None

Possible Programmer Error
None if programmer is not
using maintenance register.

See a~ciated
error bits
.. bove

Notes:

Ilf the programmer knows how many frames shouldha\le
been read and the Fe equals that number and there are
no other errors, the data is valid.
2 Possibility exists that

CRee character is in err~r so if

software checksum tallies, data is valid.

CHAPTER 4
TJU16 COMMAND REPERTOIRE

(150 in./sec) rewind operation. The TU16 completes the
rewind operation independently, and the Massbus Controller and TM02 may divert attention to other transports.

4.1 INTRODUCTION
This chapter contains a description of the T1U16 commands and provides a flow diagram of each command
showing the interaction between the RHII Massbus Controller and the TU16/TM02 Tape System.

When the reflective beginning-of-tape (BOT) marker is
detected, the TU16 terminates its high-speed reverse
motion, but will overshoot the BOT marker. The TU16
then initiates forward tape motion at read/write speed (45
in./sec). When it encounters the BOT marker again, the
capstan motor is deactivated. When the TU16 has completed its rewind operation, it asserts SET SSC (Slave Status
Change) on the slave bus and clears PIP. This causes the
Attention bit in the TM02 to be set, which results in A TIN
H being asserted on the Massbus thereby notifying the
Massbus Controller. If the Interrupt Enable (IE-hit 6 of
MTCSl) bit is set, the RHII will in terrupt the CPU.

4.2 REWIND
A program-controlled rewind operation may be initiated by
one of two commands from the processor. One of these
commands (07 8 ) performs the rewind operation and retains
the transport on-line. The other command (03 8 ) places the
transport off-line immediately after command initiation.
Following completion of the 03 8 command, the operator
must use the ON-LINE/OFF-LINE switch on the transport
to return it to the on-line status.
To initiate a program-controlled rewind operation, the
address of the desired TM02 is placed on the Drive Select
lines of the Massbus via the MTCS2 Control and Status 2
Register in the RHll (see Figure 4-1). The RHll then
performs a register write into the MTTC Tape Control
register, selecting the slave TU16 desired to perform the
rewind operation. The TM02 places the Slave Select bits of
the Tape Control register on the slave bus. The RHII
Massbus Controller then writes the operational function
code of the rewind command (03 8 or 07 8 ) into the MTCSI
Control and Status 1 register. The TM02 decodes the
function code and asserts RWND L on the slave bus. (If a
rewind/off-line operation has been specified, the TM02 also
asserts WRITE L.) It then checks for errors, and, if there
are none, initiates tape motion. The TM02 asserts DRY
(drive ready) which, in turn, asserts ATA and PIP (bit 13
MTDS register). If the Interrupt Enable (IE-bit 6 of MTCSI
register) bit is set in the RHll, the ATTN will cause the
RHll to interrupt the CPU.

4.3 SPACE
To initiate a space operation, the address of the desired
TM02 is placed on the Drive Select lines of the Massbus via
the MTCS2 Control and Status 2 Register in the RH 11 (see
Figure 4-2). The RHll then performs a register write into
the MITC Tape Control register selecting the slave TU16
desired to perform the space operation. The TM02 places
the Slave Select bits of the Tape Control register on the
slave bus.

The RHII Massbus Controller then loads the 2s complement of the number of tape records to be spaced into
the TM02 Frame Count register. Following this, the RHII
loads the MTCSI Control and Status 1 register with the
operational function code of the space command (31 for
space forward, 33 for space reverse). The TM02 decodes the
function code and asserts FWD L or REV L on the slave
bus. It then checks for errors and, if there are none,
initiates tape motion.

The TU16, enabled by its address code on the Slave Select
lines (SS 0-2), activates the capstan drive for a high-speed

4-1

LOAD CONT.
& STATUS 2
REGISTER

SELECTS
TM02

LOAD TAPE
CONTROL
REGISTER

SELECTS TU16

LOAD COMMAND
INTO CONTROL
REGISTER

REWIND
COMMAND

YES

COMMAND
ABORTED - SEE
ERROR FLOW

INITIATE TAPE
MOTION
(GO OFF-LINE*)
REWIND
OFF-LINE

TERMINATE
TAPE
MOTION

sse,

ASSERT
CLEAR PIP

TM02 ASSERTS
ATTN

RH11 INTERRUPTS
PU IF IE BIT SET

*THESE EVENTS DO NOT OCCUR IF REWIND GOES OFF-LINE.
1 '-2624

Figure 4-1 Rewind Operation Flowchart

4-2

LOAD CONT
& STATUS 2

If end-of-tape (EOT), beginning-of-tape, or tape mark is
detected, tape motion is temlinated. If not, spacing
continues until the interrecord gap (lRG) is reached. TIlis
causes the MTFC Frame Count register to increment and a
motion delay to occur which terminates tape motion. If the
frame count is not equal to zero, or EOT or BOT is not
detected, tape motion is initiated again until an in terrccord
gap is detected again which reincrements the Prame Count
register. This sequence continues until the Frame Count
register is equal to zero or until EOT or BOT is detected
indicating that the desired number of records has been
spaced over. The space operation is performed at a constant
speed of 45 in./sec.

SELECTS
TM02

When frame count overflow, or EOT or BOT is detected,
the TM02 asserts DRY indicating completion of the
operation by the drive. nle TM02 also asserts ATIN to the
RIn1. If the Interrupt Enable (IE-bit 6 of MTCSl) is set,
the RHII will interrupt the CPU.

COMMAND
ABORTED
SEE ERROR
FLOW

4.4 ERASE
To initiate an erase operation, the address of the desired
TM02 is placed on the Drive Select lines of the Massbus via
the MTCS2 Control and Status 2 Register in the RHII (see
Figure 4-3). The RHII then performs a register write into
the MTTC Tape Control register selecting the slave TU16
desired to perform the erase operation. The TM02 places
the slave select bits on the Tape Control register on the
slave bus. The RHl1 then loads the MTCS 1 Control and
Status 1 register with the operational function code (25 8 )
of the erase command. The TM02 decodes the function
code and asserts FWD L and WRITE L on the slave bus. It
then checks for errors, and, if there are none, causes the
TU16 to energize the write and erase heads and initiates
tape motion.

INCREMENT
FRAME COUNT
REGISTER

TERMINATE
TAPE
MOTION

ABORT
TERMINATION
SEQUENCE

The TU16, which is enabled by its address code on the
Slave Select lines, responds to SLAVE SET Pulse by
activating the capstan drive (starting forward tape motion)
and by activating the write and erase heads.

Since the erase head is activated and the write heads receive
no data input during an erase operation, all the tape moving
past the erase head will be dc erased.
The erase operation is terminated by the TM02 asserting
STOP L on the slave bus which deactivates the capstan
motor in the TU16. When tape motion has ceased, the write
and erase heads are deenergized. The TM02 asserts DRY
indicating completion of the operation by the drive. The
TM02 also asserts ATTN to the RHII. If the Interrupt
Enable (IE-bit 6 of MTCSl) bit is set, the RHII will
interrupt the CPU.

RH11 INTERRUPTS
CPU IF IE BIT SET

11-2625

Figure 4-2 Space Operation Flowchart

4-3

[]l0CONT

SELECTS
TM02

[ ; 0 TAPE

SELECTS
TU16

& STATUS 2
REGISTER

CONTROL
REGISTER

LOAD COMMAND
INTO CONTROL
REGISTER

4.5 PE DATA READ
To initiate PE read operation, the address of the desired
TM02 is placed on the Drive Select lines of the Massbus via
the MTCS2 Control and Status 2 register in the RH II (sec
Figure 44). The RIl11 then performs a register write into
the MTTC Tape Control register specifying the sekcted
TU16 slave, tape character format, and tape density ( I hOO
bpi for PE).

ERASE
COMMAND

YES

The TM02 places the slave selects (SS 0--2) and density
(DEN 0-2) bits of the Tape Control register on the slave
bus. The RB11 then loads the MTCSI Control and Status 1
register with the operational function code of a read
operation (718 read forward, 77 read reverse, 51 write
check forward, or 57 write check revenic) and asserts RUN
on the Massbus. The TM02 decodes the function code and
asserts FWD L or REV L on the slave bus. It then checks
for errors, and, if there arc none, asserts OCC on the
Massbus to notify the controller and other drives that it is
occupying the data bus of the Massbus. The TM02 then
transmits SLAVE SET Pulse to the TUI6.

COMMAND
ABORTED-SEE
ERROR FLOW

ENERGIZE
WRITE AND
ERASE HEADS
INITIATE
TAPE
MOTION

The TU16, which is enabled by its address code on the
Slave Select lines (SS 0-2) of the slave bus, responds to
SLAVE SET Pulse by activating the capstan drive motor
and initiating tape motion.

~
I

The TU16 read amplifiers arc on con ti n uous]y. Even as the
tape accelerates, the TM02 PE read circuitry checks for a
PE identification burst (IDB) and begins looking for a
preamble. When the tape is at speed, the preamble will be
detected and read; the tape characters immediately after
the preamble a11-1 s character are data characters.

TIle characters are assembled in to 18-bit words and placed
on the data bus of the Massbus. This action continues until
the first character of the postamble is detected.

TERMINATE
TAPE MOTION

TURN OFF WRITE
& ERASE HEADS

TM02 ASSERTS
DRY

TM02 ASSERTS
ATTN

The TM02 reads the postamble which signifies the end of
the record and asserts EBL B (end-of-block) on the
Massbus. When the gap has been detected, the TM02
terminates tape motion, asserts DRY, and negates EBL. 'nle
negation of EBL causes the RBIl to go to the RDY
(Ready) state causing the RBl1 to interrupt the CPU if the
Interrupt Enable (IE-bit 6 of MTCS1) bit is set.

RH11 INTERRUPTS
CPU IF IE BIT SET

11-2626

Figure 4-3

Erase Operation Flowchart

4-4

LOAD CONT.
& STATUS 2

SELECTS TM02

CONVERT DATA
CHARACTERS
INTO 18 BIT WORD

LOAD BUS
ADDRESS

TRANSMIT WORD

LOAD TAPE
CONTROL
REGISTER

SELECTS
TU16

LOAD COMMAND
INTO CONTROL
REGISTER

READ
COMMAND

TM02 ASSERTS
EBL

COMMAND
ABORTED·SEE
ERROR FLOW

RECEIVE
RUN H
TM02
TERMINATES
TAPE MOTION

TM02
NEGATES
EBL

RH11 INTERRUPTS
PU IF IE BIT SET

RH11~RDY

TM02
ASSERTS
DRY

INITIATE
TAPE
MOTION

IF ALL DATA
TRANSFERRED
TO MEMORY

DETECT/READ
PREAMBLE

11·2627

Figure 4-4 PE Data Read Operation Flowchart

4-5

CRCC is encountered next, and strobed into the Check
Character register, but otherwise it is ignored. No C'RC or
LRC' error is gCllerated. Then the data is rl'ad; asst'lllhly of
characters into data words Illay ditTcr when rcading in thl'
reverse direction, but this depends Oil the data forl1lat
selected.

4.6 NRZ DATA READ

To initiate an .NRZ read operation, the address of the
desired TMO:2 is placed on the Drive Select lines of the
l\bssbus via the MTCS2 Control and Statns '2 register in the
RH 11 (sec Figure 4-5). TIle Rllll then performs a register
write into the MTTC Tape Control register, specifying
selected slave TUI6, tape character format, and tape data
densi ty. The TM02 places the slave select (SS 0-2) and
density (DEN 0-2) bits of the Tape Control register on the
slave bus. TIle RHII then loads the MTCSI Control and
Status 1 register with the operational function code of a
read operation (71 8 read forward, 77 read reverse,S 1 write
check forward, or 57 write check reverse) and asserts RUN
H on the Massbus. The TM02 decodes the function code
and asserts FWD L or REV L on the slave bus. The TM02
then checks for errors, and, if there are none, asserts OCC
on the Massbus to notify the controller and other drives
that it is occupying the data bus of the Massbus. The TM02
then transmits SLAVE SET Pulse to the TU16. The TU16,
which is enabled by its address code on the Slave Select
lines (SS 0-2) of the slave bus, responds to SLAVE SET
Pulse by activating the capstan drive motor and initiating
tape motiol1.

When the data and LRCC/CRCC have been read, the TM02
asserts EBL. When the interrecord gap is detected, the
TM02 asserts DRY, terminates tape motion, and negates
EBL. TIle negation of EBL causes the RHI1 to go to the
RDY (Ready) state and will cause the RHIl to interrupt
the CPU if the Intermpt Enable (IE-bit 6 of MTCS 1) bit is
set.

4.7 PE DATA WRITE
To initiate a PE write operation, the address of the desired
TM02 is placed on the Drive Select lines of the Massbus via
the MTCS2 Control and Status 2 regist(~r in the RHll (see
Figure 4-6). The RHl1 then performs a register write into
the MTTC Tape Control register, specifying selected slave
TU16, tape character format, and tape data density
(PE - 1600 bpi). The TM02 places the slave select (SS
0-2) and density (DEN 0-2) bits of the Tape Control
register on the slave bus. The RHll then loads the 25
complement of the number of tape charactels to be written
into the TM02 Frame Count register. FollOWing this, the
RHII Controller loads the MTCSI Control and Status 1
register with the operational function code (61) of the data
write command. The TM02 decodes the function code and
assets FWD L and WRITE L on the slave bus. It then checks
for errors, and, if there are none, asserts OCC on the
Massbus to notify the controller and other drives that it is
occupying the data bus of the Massbus.

When a tape character is detected by the TU16, it is
multiplexed onto the slave bus Read Data lines and is
strobed in to the TM02. LRCC and CRCC are generated
from the data and will be used to check the validity of the
data read.
The TM02 assembles the characters into 18-bit data words
and places them on the data bus of the Massbus. When a
data word is assembled by the TM02, the TM02 notifies the
RHll which strobes the word from the data bus. The
assembling of data characters into I8-bit words continues
until the end of the data record as represented by an a11-Os
tape character.

When the RHll has data available for transfer, it asserts
RUN H on the Massbus. The TM02 responds by asserting
SLAVE SET Pulse on the slave bus and accepting the first
data word from the RHli.

During a forward read, the rest of the read circuitry
continues its operation, reading the CRCC and strobing it
in to the Check Character register, and then reading the
LRCC. Discrepancies between generated CRCC/LRCC and
detected CReC/LRCC cause their respective error bits to be
set.

The TUI6, which is enabled by its address code on the
Slave Select lines (SS 0-2) of the slave bus, responds to
SLAVE SET by activating the capstan drive motor for
forward tape motion and by turning on the write and erase
heads. The first data word, loaded on the Massbus when
RUN is asserted, is accepted by the TM02.

During a reverse read, the LRCC character is encountered
first at the start of the read operation, but is ignored. The

4-6

LOAD CONT.
& STATUS 2
REGISTER

SELECTS
TM02

READ n DATA*
CHARACTERS

LOAD WORD
COUNT

CONVERT DATA
CHARACTERS TO
la-BIT WORD AND
TRANSMIT WORD

LOAD BUS
ADDRESS

LOAD TAPE
CONTROL
REGISTER

SelECTS
TU16

LOAD COMMAND
INTO CONTROL
REGISTER

READ
COMMAND

ASSERT EBL

COMMAND
ABORTED SEE
ERROR FLOW

RECEIVE
RUN H

INITIATE TAPE
MOTION

DRY

TAPE MOTION

IF ALL DATA
TRANSFERRED
TO MEMORY

RH11~RDY

CPU IF IE BIT SET

11-2628

Figure 4-5 NRZ Data Read Operation Flowchart

4-7

LOAD CONT.
& STATUS 2

SELECTS
TM02

lOAD BUS
ADDRESS

LOAD TAPE
CONTROL
REGISTER

WRITE
PREAMBLE

SELECTS TU16

CONVERT DATA
WORD TO TAPE
CHARACTERS
GENERATE
WRITE CLOCK

LOAD FRAME
COUNT
REGISTER

LOAD COMMAND
INTO CONTROL
REGISTER

WRITE
COMMAND

RECEIVE
DATA WORD

COMMAND
ABORTED
SEE ERROR FLOW

~-:=--=-~
TM02 ASSERTS
EBl

___J

TURN ON
WRITE AND
ERASE HEADS
START TAPE
MOTION

TM02 NEGATES
EBl

RHll-'>RDY
RECEIVE
DATA WORD

RHl1
INTERRUPTS
CPUIFIE
BIT SET

Figure 4·6 PE Data Write Operation Flowchart

4·8

TM02 ASSERTS
DRY

When the TU16 is up to speed, it transmits a WRT CLK
signal to the TM02. Upon receipt of WRT CLK, the TM02
begins generating a preamble. When forty all-O characters
and one all-l characters have been written, the TM02 begins
disassembling the first data word il1to characters. When it
has disassembled the first data word, it requests the next
data word from the RHll Massbus Controller and continues to do so until all the data words have been
transferred. Each time the TM02 generates a character, the
Frame Count register is incremented, a vertical parity bit is
generated, and the tape character is converted to PE mode
and transmitted to the write circuitry of the TUI6. When
the Frame Count register overflows to zero, the TM02
generates a postamble which is written on tape and asserts
EBL. During the entire operation, the TUI6/TM02 read
operation is active and reads the record being written.

When the TU16 is up to speed, it transmits a WRT CLK
signal to the TM02. Upon receipt of WRT CLK, the TM02
begins disassembling the first data word into characters.

When the TUI6/TM02 read circuitry detects the end of the
record. the TM02 asserts DRY, terminates tape motion, and
negates EBL. TIle negation of EBL causes the RHll to go
to the RDY state, and causes the RHll to interrupt the
CPU if the Interrupt Enable (IE-bit 6 of MTCS1) bit is set.

During the time that the tape is moving at speed, the
TUI6/TM02 performs a read-after-wri te operation.

When it has disassembled the 11rst data word, it requests the
next data word from the RBI 1 Massbus Controller, and
continues to do so until all the data words have been
transferred. Each time the TM02 generates a character, the
Frame Count register is incremented, a vertical parity bit is
generated, the CRCC is generated, and the tape character is
transmitted to the write circuitry of the TU16 where it is
converted from binary to NRZ mode (1s become transitions) and written on the tape. When the Frame Count
register overflows to zero, the TM02 transmits EBL
(end-of-block) to the RHII. It then generates the timing to
write the generated CRCC and the LRCC.

When the TU16/TM02 read circuitry detects the end of a
record, the TM02 asserts DRY, terminates tape motion, and
negates EBL. When tape motion stops, the write and erase
heads are deenergized.

4.8 NRZ DATA WRITE
To initiate an NRZ write, the address of the desired TM02
is placed on the Drive Select lines of the Massbus via the
MTCS2 Control and Status 2 register in the RHll (see
Figure 4-7). The RHll then performs a register write into
the MTTC Tape Control register specifying selected slave
TUI6, tape character format, and tape data density. The
TM02 places the slave select (SS 0-2) and density (DEN
0-2) bits of the Tape Control register on the slave bus. The
RH 11 then loads the 2s complement of the number of tape
characters to be written into the TM02 Frame Count
register. Following this, the RHII loads the MTCSI
Control and Status 1 register with the operational function
code (61) of the data write command. The TM02 decodes
the function code and asserts FWD L and WRITE L on the
slave bus. It then checks for errors, and, if there are none,
asserts OCC on the Massbus to notify the controller and
other drives tha t it is occupying the data bus of the
Massbus.

The negation of EBL (end-of-block) causes the RHll to go
to the RDY (Ready) state and causes the RHll to interrupt
CPU if the Interrupt Enable (IE-bit 6 of MTCSl) is set.
4.9 WRITE TAPE MARK
To initiate a write tape mark operation, the address of the
desired TM02 is placed on the Drive Select lines of the
Massbus via the MTCS2 Control and Status 2 register in the
RHII (see Figure 4-8). The RHII then performs a register
write into the MTTC Tape Control Register, selecting the
slave TU16 to perform the write tape mark operation and
the density at which the tape mark characters are to be
written. The TM02 places the slave select (SS 0-2) and
density select (DEN SEL 0-3) bits of the Tape Control
register on the slave bus.

When the controller has data available for transfer, it asserts
RUN H on the Massbus. The TM02 responds by asserting
SLA VE SET Pulse on the shive bus and accepting the first
data word from the RHII.

The RHll Massbus Controller then loads the MTCSI
Control and Status 1 register with the operational function
code (27) of the write tape mark command. The TM02
decodes the function code and asserts FWD L and WRITE
L on the slave bus. It then checks for errors, and, if there
are none, issues SLAVE SET to the TU16.

The TUI6, which is enabled by its address code on the
Slave Select lines (SS 0-2) of the slave bus, responds to
SLA VE SET by activating the capstan drive motor for
forward tape motion and by activating the write and erase
[leads. The first data word, loaded on the Massbus when
RUN is asserted, is accepted by the TM02.

The TUI6, which is enabled by its address code on the
Slave Select lines, responds to SLAVE SET by activating
the capstan drive (starting tape motion) and by activating
the write and erase heads. As tape moves past the heads, it
is erased. After a 3 inch acceleration delay, the TM02
generates the tape mark.
4-9

LOAO CONT.
& STATUS 2
REGISTER

SELECTS
TM02

CONVERT DATA
WORDS TO TAPE
CHARACTERS

RECEIVE DATA
WORD

SELECTS TU16,
DENSITY
FORMAT

LOAD FRAME
COUNT REGIST:J

LOAD COMMAND
INTO CONTROL
REGISTER

WRITE
COMMAND

COMMAND
ABORTED - SEE
ERROR FLOW

CHARACTERS
AND WRITE

[

SPACE 3
CHARACTERS
AND WRITE
LACC
TM02 TERMINATES
TAPE MOTION

TERMINATE
TAPE MOTION
ERASEIRG
TURN OFF WRITE
& ERASE HEAC)S

TURN OFF
ERASE AND
WRITE HEADS

INITIATE
TAPE
MOTION

ERASE IRG

~NH;:RRUPTSJ I- RH1~~~Y I

CPU IF IE
BIT SET

ERASE
IRG
RECEIVE
DATA
WORD

TURN OFF WRITE
& ERASE HEADS

11-2630

Figure 4-7 NRZ Data Write Operation Flowchart

4-10

LOAD CONT.
& STATUS 2
REGISTER

SELECTS
TM02

NO
LOAD TAPE
CONTROL
REGISTER

LOAD COMMAND
INTO CONTROL
REGISTER

SELECTS rU16 DENSITY

WRITE TAPE
MARK
COMMAND

TM02
ASSERTS
DRY

COMMAND
ABORTED
SEE ERROR FLOW

TERMINATE
TAPE
MOTION

TM02
ASSERTS
ATTN

TURN OFF
WRITE AND
ERASE HEADS

RH11 INTERRUPTS
CPU IF IE BIT SET

TURN ON WRITE
AND ERASE
HEADS

INITIATE TAPE
MOTION

GENERATE
AND WRITE
TAPE MARK

GENERATE
WRT CLOCK

11-2631

Figure 4·8 Write Tape Mark Operation Flowchart

4·11

. the TU16/TM02 is operating in PE mode. slave bus write
nes WD 3, 4, 6, and 7 are forced high. while PE Os are
~ncratcd for WD 0, 1, 2, and 5. At the same time record
ulses (40 X 2 = 80) are transmitted to the TU16. As a
!sult, forty Os are written in tracks I, 2, 4, 5, and 8, and
1e remaining tracks are erased.

4.10 ERRORS
. TM02 errors may occur at comnland initiation or at
command execution. The error handling for each type is
described below.

Command Initiation - Any error that occurs when a
command is initia ted (GO bit asserted) will causc an
immediate abort. The error will assert EXC (if it is a dat<l
transfer command) and during command initiation will also
assert ATIN and EBL (see Figure 4-9). The assertion of
EBL and ATTN will cause the RHl1 to interrupt the CPU
if the IE bit is set. The assertion of EXC causes TRE in the
RHl1 to set. TRE is monitored in bit 14 of the MTCSI
register.

the TUI6/TM02 is operating in NRZ mode, the tape
lark character is forced onto the slave bus WD lines, and a
::cord pulse is transmitted to the TU16. The TU16 is then
[lowed to erase seven character lengths of tape at which
me it receives LRC STROBE on the slave bus and writes
n LRCC (which will· be the same as the tape mark
haracter ).

Command Execution - During the execution of J command, Class A or Class B errors may occur and arc handled
in the following manner.

~.fter writing the NRZ or PE tape mark, the TU16/TM02

Class A: If a class A occurs during execution of a
data transfer command, EXC is raised immediately
but the command will not temlinatc until the
operation is completed. This occurs at the cnd of the
record when ATTN and EBL are asserted. Note that
EXC asserts TRE which can be monitored via hit 14
of the MTCS1 register.

l)ntinues to erase tape. As the write tape mark operation is
lerformed, the read circuitry performs a read-after-write.

\fter the read circuitry has detected the written tape mark,
he TM02 transmits STOP L to the TU16. This signal
kactivJ tes the capstan motor to terminate tape motion.
\'hen tape motion has stopped, the write and erase heads
lIT deenergized. The TM02 asserts DRY indicating that the
hive is ready to perform another function. The TM02 also
is'icrts ;\ TTN t(~ the RH 11. The RH 11 will interrupt the
,'I'll if the Interrupt Enable (IE-bit 6 of MTCSI) bit is set.

Class B: If a class B error occurs during execution of
a command, EXC, ATTN and EBL arc raised
immediately and the command is terminated. If the
command is a data transfer command, EXC is also
asserted which sets TRE in the RBlI.

4-12

CPU

RHll

TM02

lOAD FUNCTION
CODE & GO

lOAD FUNCTION
CODE - CLEAR
ROY IF DATA
TRANSFER
FUNCTION

o z
z 9
<l:

::E ~
::E~
0u~

EXC (IF DATA TRANSFER COMMAND)

ATTN, EBl

I
I

SET TRE

I
I

I
z
z<l: ~

00
:,?:::>

::E ~

oX
UUJ

I
I
I

TERMINATE
OPERATION
CLEAR GO

EXC (IF DATA'TRANSFER COMMAND)
ATTN,EBl

SET TRE

I
I

SET ROY,
INTERRUPT
CPU IF IE
T

ATTN (IF CLASS A ERROR), EBl

TERMINATE
OPERATION

11-2632

Figure 4-9 Error Termination

4-13

CHAPTER 5
THEORY OF OPERATION

5.1 GENERAL

supplied to the register decoders to select one of the local
registers. RSEL 04:00 is also supplied to the Massbus
control logic, but is inhibited from the Massbus because a
'write local register' function is specified and REM remains
unasserted.

This chapter describes the theory of operation of the RHII
Controller in two functional groupings - the register
control path and the DMA path. These are described in
detail in the following paragraphs.

Unibus control lines AO, CO, and Cl specify the direction
of transfer and also specify byte or word addressing. When
writing a register, the CO and C 1 lines are encoded for a
DATO or DATOB (if byte addressing is specified). The AO,
CO, and C 1 control lines are supplied to a direction control
network which generates IN, OUT, HI BYTE, or La BYTE
signals depending on the cycle desired. These signals arc fed
to the register decoder where they are used in decoding the
various register enable signals.

5.2 REGISTER CONTROL PATH
The register control path provides the interface that enables
th~ program to read from or write into any register in the
RH 11 or associated drive. Specific bits in these registers are
designated as follows: 'read only' bits indicate that the
program can read the status of these bits but cannot load
them: 'write only' bits indicate that the program can load
them but will read back a 0; 'read/write' bits indicate that
the program may load them and read back the stat us.

The Unibus A data lines are connected to the RH 11 and
contain the data used to load the desired register.

The RH 11 examines Unibus address bits 17 through OS (17
through 06 if there are a total of more than 16 registers) to
determine if the register being addressed is an RHll register
(Figure 5-1). The address field can be defined by a set of
jumpers within the RH 11. The Unibus address is compared
with the set of jumpers and, if the two match, the
addressed register is a valid RH 11 register which enables the
circuitry for a register function. If the Unibus address does
not compare with the jumpers, the RHll will not accept
the address and will not initiate a data transfer with the
processor.

When BUSA MSYN is received from the central processor
(150 ns after the data, control and address are placed on
the Unibus), a DEV SEL (device select) Signal is generated
which enables the register decoder to generate the appropriate enable signal for the register specified. Signal REG STR
is created 85 ns later and is ANDed with the HI BYTE or
La BYTE signal and the specified register enable signal
from the register decoder. The signals designated with IN
are used for writing local registers; the signals designated
OUT are used for reading local registers. For example, if it
was desired to write into the WC (word count) register, the
register decoders specify the WC IN L signal, which is
ANDed with HI BYTE or LO BYTE and REG STR to
generate a clock used to load the WC register. The data is
clocked into the WC register at the time of REG STR. The
trailing edge of this signal, which is 135 ns long, causes
SSYN to be asserted. The central processor receives SSYN
and lowers MSYN, which deselects the RHII from the
Unibus. The lowering of MSYN then causes SSYN to be
lowered, and 75 ns after the lowering of MSYN, the address
lines change and the cycle is completed.

5.2.1 Writing a Local Register
Unibus address bits 04 through 00 (05 through 00 if more
than 16 registers are employed) select a cell in a read only
memory (ROM) which specifies a unique register. The ROM
outputs are register select signals (RSEL 04:00), two coded
bits (M6 and M7), and a LOCAL/REM signal. Since this
description involves accessing a local register (one contained
in the Rlll1), LOCAL is generated at the output of the
ROM as LaC/REM H. When this signal is unasserted or low
and a register operation is being performed, a remote
register is selected. Signals RSEL 01 :00 and M6 and M7 are

5-1

A 1-(\

u___~

MUX

"A,,0I

MUX

OS (2011

DB OU-;-

BA OUT
(FROM DECODER)

wmJ
I I

DBCH
CNTRL OUT

DBCJ
BCTJ

'-::C-:-S-'-+-+--+--+L-C-S-2~ OUT

OUT

UNIT
SELECT

'FROM

(FROM DECODER) -II~'FROM
S)
DECODER) D~~~~~R)
DECODER) . . . - - - - - - , C (M'5A. S
OO
C (!5 :O~O:..:.)...:..IN~_ _ _ _-I--+-_'--_ _ _~
I

CSRA
BA
BUS
ADDRESS

BUSA
SSYN

WC
WORD
COUNTER

BCTC

I REGiSTER--CLOcK'LOG'iCl
tiC IN L
FROM
DECODER

BCTD,E
CLOCK

CLOCK
BA

~_-:r~;..:.;;...J

_-....,J;,,---...

HI, LO BYTE

L __ .

...§!~E

N
I

I
I

CLOCK
DB

__ -.-J ~--r~,:,,:,;;..J

DRIVERS

MASS
C(l5:00)

MBSA, B,C

U
CLOCK

H
R

o
N
a
U
s
M

A
BUSA
MSYN

A
S

REG STR

RECEIVERS-+_ _....:.::.::..:..;:.:....-_ _ _....

S
B

S
MASS

TRA

,-OCAl
BUSA
A(17:05J

BUSA
AO,CO,C!

WC IN L, WC OUT L
DECODER

AS IN L, AS OUT L
CSI INL,CSI OUTL

LOCAL

BUSA
A(04:00

r~~-~-~~~~../

(REGISTER
SELECT)

CS2 IN L, CS2 OUT L
DB IN L, DB OUT l

aCTA

B.A!N L. BA OUT L

MASSBUS

RSEL(04~~ CONTROL

L ______ ._______________~R~E:.:.M:.:_.O::...:.T.E -----e4

DIR TRANS
(FROM DIR. CaNTRall
REG SELECT

MA.5S CTOD
DRIVERS

MASS RS(4:0)
MASS OEM

)£ MAND

i - -_ _9_C;...~...;B;...!r..--· - - - - - --.-...- - - - - - - -

MBSA ,B.C
11-2372

Figure 5-1

~. 2.2 Reading a Local Register
The process of reading a local register is the same as that
described for writing a local register (Paragraph 5.2.1) with
the following exceptions:

The CO and Cl Unibus control lines arc
decoded for a DATI or DATIP operation.

When reading a local register, the register
"OUT" signals of the register select decoders
gate the contents of the register on the BUSI
lines for transmission to the processor via
Unibus A.

DEV SEL signal which causes DEM to drop. This action. in
turn, causes TRA from the drive to go unasscrtcd. The
address and data is then removed from the Unibus and
Massbus to complete the cycle.
5.2.4 Reading a Remote Register (Figure 5-3)
The process of reading a remote register is similar to that of
writing a remote register with the following except ions:

5.2.3 Writing a Remote Register (Figure 5-2)
;\ remote register is defined as a register located in the
drive. The data path for writing a remote register is from
Unibus A via data lines DOO-D 15 IN 1-1 on to the Massbus
via cont rol lines MASS COO-C 15 I I, where the data is
received by the selected drive and loaded into the specified
register in that drive. A CTOD (Controller to Drive) signal
Oil the Massbus specifies the direction of transfer to the
drive.
5.3

Thc data path for reading a remote rcgiskr is
from the drive to Massbus cOlltrol lines COO
through C 15 H, to the RH 11 open-collector
multiplexers (8234), to the BUSI lines, alld
then to the Unibus A data lines 000 --D 15.

Upon receipt of TRA when writing a remote
register, SSYN is immediately sent to the CPU.
When reading a remote register. however. SSYN
is delayed 220 ns from transfer (TRA) to
ensure that the data is presen t and sett led on
the Unibus.

DMA DATA PATH

Figure 5-4 is a block diagram of the DMA da ta path. The
diagram shows three basic data flows·· write. read, and
write-check. Thesc are briefly described below.

The upper address bits of the Unibus address are compared
\vith d set of jumpers in the RBI1 to enable the register
selection 10giL:. prcviously described. Unibus address bits 04
through 00 (O~ through 00 if marc than 16 registers are
clllplu~'ed in thl' s;.-·stel11) select a cell in the ROM (read only
memory) which specifies a particular register. The outputs
of the ROM are register select signals RSEL (04:00), two
coded bits (M6 and 1'.17), and the LOCAL/REM signal. The
selected drive. whose unit number. was preloaded by the
programmer in the CS2 register. is specified by device select
lines DSOO through DS02 on the 1'.1assbus.

Write --- Data is routed from the Unibus through two
multiplexcrs (DMX and IMX) and into IBUF. The
D1'.1X multiplcxer selects the data from Unibus A or
Unibus B. If SEL BUS A is prcsent. Unibus A is
selected; if this signal is not asserted, Unibus B is
selected. The IMX multiplexer selects the data from
the DMX or from the Massbus dcpending on the
function being performed. For a write function, thc
data at the output of IMX is from the Unibus and for
a read or write-check function, the data is from the
1'.1assbus. The data words arc gated into IBlIF and
bubble through the Silo to OBUF. For the write
function, the data from OBUF is supplicd to drivcrs
and then to the Massbus data lincs (MASS
DOO-D17).

When the MSYN signal is received over the Unibus by the
RIll! . the DEV SEL signal is enabled and a delay of 220 ns
occurs before the RH 11 issues DEM to the Massbus. This
delay allows the select and data lines to settle and be
decoded on the Massbus before the drive strobes the
Masshus control lines. When the drive receives DEM and
recognizes the unit address as its own and when the data
has been clocked into the appropriate drive register, it
issues transfer (TRA) to the RHIl. When the RBI1
receives TRA indicating that the drive has obtained the
data, it issues SSYN to the processor. SSYN signals the
processor that the slave (RH 11) has finished the cycle, and
the processor removes MSYN which, in turn, causes SSYN
to go unasserted. Also MSYN going unasserted, removes the

Read - Data is routed from the Massbus data Iincs
(MASS DOO-D17) to IBUF through thc IMX multiplexer. Just as in the write function, the data from
IBUF bubbles through thc Silo into OBUF. From
OBUF, the data is gated onto Unibus A if SEL BUS A
is present; otherwise, the data is gated onto Unibus B.

5-3

CENTRAL
PROCESSOR

R H \ 1 CONTROLLER

TM02/TU16

JUMPER
CONFIGURATION

BUSA A (1705)

J\.

XOR

v
BUSA A (0401)

....

RSEL

-----

MASS RS (0400lj\.

.r:~

L..REMOTE

BUSA 0 (15:00)

MASS DS (20) ....
DRIVER$

(0200)
CS2

ENCODER
(ROM) I

hi H

-----

JDIRECTION
CONTROL

BUS A AOO

DIR TRANS

DRIVER
ENABLE
LINE

EQUAL

•

MASS CTOD-,"

----c:

I
I
I

!50NS

MASS C (15:00~

~ ,..----

BUSA C (0100)

D-l J

~DEV SEL

BUSA MSYN

85NS
DELAY

135NS j-~REG
STR
~

REMOTE- I -

MASS OEM

OEM
STROBE
DATA
iNTO
REG.

l.(l
~

BUSA SSYN

MASS TRA

SET SSYN

""'""-._-

J DESELECT
l (DEV SEL')

BUSA MSYN

-1--

CLR OEM

MASS OEM

SSYN

MASS TRA

BUSA SSYN

-""

DE~LECT
L

TM02

* AL.L EVENTS WITHIN BRACKET OCCUR
AT APPROXIMATELY SAME TIME.
CP-l340

Figure 5-2 Writing Remote Register Interface

5-4

CENTRAL
PROCESSOR

RH 11 CONTROLLER

TM02/TU16

rCONFIGURATION
JUMPER

,..

BUSA A (17:05)

XOR
-V

...

BUSA A (04:01)

-V

r(O~~~Ol~

17"

RSEL

ENCODER
(ROM)
r

",DIRECTION
CONTROL

BUS A AOO

DIR TRANS
EQUAL

MASS RS (04:00),

~ 1-----

150;NS

MASS CTOD

DRIVER
ENABLE

~
I

BUSA+MSYN

-----

L.REMOTE
BUS A C (0100)

MASS OS (2:0) ....
DRIVERS

~DEV SEL

85NS
DELAY

I •

135NS
DELAY
~

MASS OEM

REMOTE
OEM

GATE
DATA
TO
BUS

L...-A

BUS A 0 (1500)

lRECEIVERSI
,
DRIVERS

"'-

':"

r SET 1
1 SSYN r

BUSA SSYN

I 220NS I

MASS TRA

I DELAY r

J DESELECT
-, (oEV SEL)

BUSA MSYN

MASS C (1500)

CLR OEM

SSYN

BUSA SSYN

MASS OEM
MASS TRA

1 IJDESELECTI
TM02

* ALL EVENTS WITHIN BRACKET OCCUR
AT APPROXIMATELY SAME TIME.

CP-1341

Figure 5·3 Reading Remote Register Interface

5·5

A17, Al6
BITS q R

RECEIVERS!
DRIVERS

BUSA
0(17:00)

D(170001lN

OBCF

DRIVE WORD
COUNT
~
OVERFLOW
BCTE

r--

fr:'D I

DRIVERS

WRITE

WR OR WR CHK

DBCD

WRITEOBUF (17:00)

OBUF
OUTPUT
BUFFER

ERROR

DBCD

WRITE - CHECK

READ

SEL
BUSA

BA(t7:01)

~K=
BUSA
0(17:00)

WRITE-CHECK

RSBA
A"50'

I RSC~~~cll M\'~BVC'~C I

BUSA
A(17:00)

MASS 0(17:00)
WRITE

MBSA,B,C

DRIVE WORD SYNC
COUNT
CLOCK
(DRWC) ~
BeTO,E

RECEIVER

MASS
SCLK

I+-MBSA

Y
N

C
H

64 WORD
,
X 20 BIT
FIRST IN-FIRST
SILO
OUT SERIAL
MEMORY (SILO)!4-- CONTROL

I+- OVERFLOW

DBCB

BCTE

rBUF
INPUT
BUFFER

NPR
CONTROL

WORD
COUNT
WC

DBCA

WORD
COUNT

o
N
o
U

0.,

BUSB
A(17:00)

BA(17:01)

~Vt

~rv- RECEIVERSI
DRIVERS

A
S
S

DBCC,D

f4-- SEL BUSA
BUSB
0(17:00)

DBCC,D

READ

IMX

WRITE OR WRITE CHECK

~ Ig:;c,;S;.J~:"'-

LOAD
FUNCTION_
CODE IN
CSI

UNIBUS!
MASS BUS

=)V DMX (17:00)

____

...J

_ - - -.... MASS

LEBl
MASSBUS
CONTROL

MSYN10,Cl
BBSY

)~ ___
~~ SY_N_C~D~"~7_:0~0~)~I~N

_____

UNIS 0(17:00) IN

B
U

BCTO,E

BCC.D

BUSB
0{17:00)

______

MBSB~

_ - - -.... MASS
RUN
DRIVER

J
II
I

CSRA B

r RECEIVER LEB~

"R'u"'r{.

MBSA

~-R-E-C-E-IV-E-R-S~O~D(17:00)

READ OR WRITE CHECK
MBSA,B,C

~____D_B~C~EJ;_-----------------------~

11-2375

Figure 54 DMA Data Path Block Diagram

Write-Check - In the write-check function, the data
that has previously been written onto the disk is
compared with the contents of the memory locations
that were the source of this data. In this way, errors
in transmission can be easily detected. The datu from
the Massbus is fed through the IMX multiplexer into
IBUF. From IBUF, the data bubbles through the Silo
into OBUF and to a series of write-check ExclusiveOR gates. The second input to these gates is from the
DMX multiplexer which contains data from the
corresponding Unibus memory location. If the data
from memory does not compare to the data read
from tape, a write-check error is flagged indicating a
transmission error.

NOTE
When a write command and the GO bit are
loaded, the RHII becomes busy and cannot
accept another data transfer command. and the
TM02 causes the TU 16 to initia te tape motion.
The drive then waits for the RUN assertion
from the Massbus. The RUN signal is asserted
by the RHII when the Silo has been filled with
a prescribed number of words, depending on
the Silo capacity selected.
When the RH11 decoded the write command code from the
program, it issued an NPR data request on the selected
Unibus.

NOTE
The NPR request allows the RH II to acquire
bus mastership in order to transfer data directly
to or from memory. This sequence is described
in detail in Paragraph 6.7.

Figure 54 shows the bus address used to address memory
on the Unibus. This is obtained from the BA register and
from bits 9 and 8 of the CSI register to form the 18 bit
Unibus address. Both the word count (WC) and drive word
count (DRWC) logic is shown. The word count keeps track
of the number of words transferred between the Unibus
memory and RH 11 while the drive word count keeps track
of the number of words transferred between the RH 11 and
the drive via the Masshus. When the WC register overflows,
the RH 11 ends the Unibus transfer; when the DRWC
register overflows, the RHll ends Massbus transfers.

When bus mastership is granted to the RHl1, the RHll
sends a memory address [stored in the bus address (BA)
register and in bits 8 and 9 of the CS 1 register] to memory
via the Unibus. The RHll asserts BUS MSYN 200 ns after
the address is placed on the Unibus. The specified memory
location responds with the data word in that location and
the SSYN control signal. The data word is clocked into the
IBUF register in the RHll, the WC register is incremented
by 1, and the BA register is incremented by 2.

In order to describe the data transfer operation of the
RH 11 in more detail, the following paragraphs present each
function (read. write, write-check) as it interfaces between
the Unibus and Massbus.

NOTE
The we register is initially loaded with the 2's
complement of the number of words to be
transferred and is incremented toward 0 for
each word transferred. The BA register is
incremented by 2 since the RH II is a wordoriented device and the PDP-II memory system
is byte-oriented.

5.3.1 Write Record Transfer
Figure 5-5 is an interface diagram showing the action of the
RHll during a write data transfer. Initially, the bus address
(BA) selected unit, word count (WC), and frame count (FC)
are specified by the program. The bus address and word
count are supplied to the RHII and are monitored by
circuitry in the RHII. The program, in this case, also
specifies a write command code with the GO bit set (bits 5
through 0 of the CSI register). The RHII transfers the
write command code and the GO bit to the selected drive
and also examines the command code to enable the
appropriate logic (memory reference, Silo control, data
path, and Massbus control). The write command code and
GO bit, which are sent to the drive, are stored in the drive's
function register (bits 5 through 0 of CS1) and are decoded
by the drive in order to determine the function to be
performed.

If the first word of the Silo is empty at this time, the RHII
will initiate a second memory reference. If the first cell of
the Silo is full or if this was the second memory reference
of back-to-back NPRs, the RHll will release control of the
Unibus and will wait for IBUF to be empty before initiating
another NPR request. When word count overflow occurs or
an error is detected, the Unibus memory references are
terminated.
NOTE
The RHII can perfonn single-cycle or back-toback memory references for each NPR request.

5-7

MEMORY!

CPU

RH11

DRIVE

BA,WC
WRITE, GO

WRITE,GO

UNIBUS CYCLE
(BUS ADDR, MSYNI

·------------~·~I____S_ET__B_US_Y__~

DATA, SSYN

SILO FILLS UP WITH DATA
WORDS FROM MEMORY

•

••
YES

RUN

SCLK

DATA,WCLK

CHANGE DATA

TERMINATE
MASSBUS
TRANSFER

SET END OF
SEGMENT

EBL PULSE

CP-1342

Figure 5-5 Write Cycle Interface Diagram

5-8

5.3.2 Read Record Transfer
Figure 5-6 is an interface diagram showing the action of the
RHII during a read data transfer. Initially, the bus address,
selected unit, and word count are specified by the program
as in the write block transfer, however, the frame count
need not be specified. TIle program then loads a read
command code with the GO bit set (bits 5 through 0 of the
CSI register). The RHll transfers the read command code
and the GO bit to the selected drive and also ex~mines the
command code to enable the appropriate logic (memory
reference, Silo control, data path, and Massbus control).
TIle read command and GO bit, which are sent to the drive,
are stored in the drive's function register (bits 5 through 0
of CS 1) and are decoded by the drive to determine the
function to be performed.

The data word which was clocked into IBUF from memory
is automatically transferred to the bottom cell of the Silo if
this cell is empty. If the cell is full, the data word in IBUF
remains in IBUF until the data word in the bottom cell of
the Silo has propagated to the next cell. Once a word is
input to the Silo, it "bubbles" through the Silo to the last
empty cell. Once a data word appears at the last cell of the
Silo, it is clocked into the OBUF register, provided OBUF is
empty. If OBUF is not empty, the data word remains in the
last cell. Successive data words stack up in the Silo in a first
in/nrst out (FIFO) sequence.
Each time a data word is input into IBUF, a start counter is
incremented to determine how many words will be stacked
in the Silo before the drive is signaled to begin the data
transfer by the assertion of the RUN signal on the Massbus.

NOTE
When a read command and the GO bit are
loaded, the RHtt becomes busy and cannot
accept another data transfer command and the
TM02 causes the TUl6 to initiate tape motion.

NOTE
There are four different Silo capacities which
can be selected (Paragraph 6.19).

When the write command code is decoded, the drive
initiates tape motion. After RUN is asserted and the IRG
has been found, the drive issues synchronous clock (SCLK)
signals on the Massbus. TIle SCLK is received by the RHII
and re-driven on to the Massbus as a write clock (WCLK)
signal. The data word in OBUP is transferred to the drive
on the leading edge of WCLK (leading edge of SCLK plus
cable delay). The drive accepts the data word on the leading
edge of WCLK. On the trailing edge of SCLK, the RHII
writes over the previous data word in OBUF with the word
in the l~st cell of the Silo. A drive word count register
(DRWC), which was initially loaded with the same value
contained in the WC register, is incremented by 1 toward 0
for each word transferred. Successive words are transferred
in this manner and when the required number of words are
transferred. drive word count overflow occurs and the RUN
line goes unasserted. The TM02 converts each data word
into two or four frames (depending on mode) and transfers
them to the TU16.

The RHII now asserts the RUN line on the Massbus to
connect the RHll to the drive. The TM02 then assembles
two or four frames (depending on mode) into a data word
and presents this word accompanied by SCLK on the
Massbus. At the trailing edge of SCLK, the RHII loads the
data word into IBUF. In addition, the DRWC register is
incremented. From IBUF, the data word automatically
sequences through the Silo to the OBUF register. Successive
words are transferred in this manner until the DRWC
register overflows. When overflow occurs, the RUN line is
negated and all remaining words in the sector are disregarded by the RHll. The drive indicates completion of
the record by issuing an EBL (End of Block) pulse. If the
RUN line is unasserted when EBL occurs, the data transfer
is terminated and the RHII becomes Ready as soon as the
remaining Unibus memory references have been completed.

The data words input to IBUF are propagated through the
Silo. When the first data word reaches OBUF, an NPR
request on the selected Unibus is issued and the WC register
is incremented toward O. This register is loaded with the 2's
complement of the number of words to be transferred and
incremented each time a word is loaded in OBUF.

TIle drive signals completion of the record with an EBL
(End of Block) pulse. When the RUN signal is unasserted
with the EBL pulse present, the data transfer is temlinated
and the RHII transitions to the Ready state. If the run line
remains asserted at the trailing edge of EBL, frame count
error (FCE-bit 9 of MTER) is asserted.

5-9

MEMORY/CPU

RH11

DRIVE

SA,WC
READ, GO

READ, GO
DECODE

RUN
ACCELERATE

DATA, SCLK
LOAD DATA INTO
ISUF AT TRAIL·
ING EDGE OF
SCLK

RECORD FOUN~.J

UNIBUS
CYCLE
(DATA,
BUS ADDR,
MSYN)

SSYN

EBL PULSE

CP-1343

Figure 5-6 Read Cycle Interface Diagram

5-10

NOTE
The NPR request allows the RH 11 to acquire
bus mastership in order to transfer data directly
to or from memory. This sequence is described
in Paragraph 6.7.
When the RHll acquires bus mastership, it sends a memory
address (stored in the BA register and in bits 8 and 9 of
CS 1) and data (stored in OBUF) onto the Unibus. The
RHll issues BUS MSYN 200 ns after the data and address
are placed on the Unibus. Memory acknowledges receipt of
the da ta by asserting SSYN. The RH 11 then removes
MSYN and waits 75 ns before changing the data and
address. After the data word has been transferred, the Bus
Address register is incremented by 2 since the RHII is
word·oriented and the PDp·II memory reference system is
byte·oriented.

supplied to the RHil. The data word in OBUF is compared
with its original counterpart from memory. If any bits do
not compare, the WCE (Write-Check Error) bit is set and
the word is 'frozen' in OBUF so that the program can
examine the data word in error from the tape. If the hits do
compare, the write-check operation continues until the
record is checked or until an error is detected.
When the RHll becomes bus master and requests a data
word from memory, memory issues the data word on the
Unibus accompanied by SSYN. When the RHII receives
SSYN, it waits 125 ns to deskew data on the Unibus and to
allow the data to propagate through the XOR ga tes before
MSYN is cleared.
5.4 WRITE FLOW DIAGRAM DESCRIPTION
Figure 5-8 is a detailed flow diagram of the write data
transfer. Initially, the RHl1 is in the Ready state and the
program specifies the bus address, word count, frame
count, and selected unit (specified in CS2). A Writc
command is loaded in bits as through a1 of CS 1 and the
GO bit is set in bit 00 of CSl. The Ready state in the RHll
is then cleared and the Silo is initialized. At this point the
flow diagram divides into two asynchronous paths - one
for the Unibus sequence of events and one for the Massbus
sequence of events. The Unibus flow is discussed first
inasmuch as a START signal, generated in this path, is
necessary to i.nitiate the Massbus flow.

If there is a word in the top cell of the Silo when the data
word is transferred from OBUF, the RHII will maintain
control of the Unibus for a second memory reference. If a
word is not stored in the top cell of the Silo, or if this
transfer is the second word of a back·to-back memory
reference, the RH 11 releases control of the Unibus and
does not initiate a new NPR request until OBUF becomes
full again.
NOTE
The RH II can perform single-cycle or back-toback memory references for each NPR request.

5.4.1 Unibus Flow Descnption
When the Write command is loaded in CSI, DATA REO is
set. This signal asserts the BUS NPR line to request a
Unibus cycle. The processor acknowledges the NPR by
returning NPG (non-processor grant). The RH 11, in turn,
clears NPR and asserts SACK, indicating acknowledgment
of the NPG. If a cy cle is already in progress, the RH II
waits until BBSY and SSYN become negated. When this
occurs, the RH II asserts BBSY, indicating it is now bus
master and negates BUS SACK. In addition, NPC MASTER
is asserted which initiates the timing for the NPR cycles.

When word count overflow occurs or an error condition is
present, the Unibus memory references are terminated.
When the Unibus memory references are terminated and
the drive reaches the end of the record, the RHll
transitions to the Ready state.
5.3.3 Write-Check Record Transfer
Figure 5-7 shows the interface diagram for a write-check
operation. In a write-check operation, data written on tape
is validated by comparing it with the data in memory used
to write it on the tape. This operation will reveal the
addition or loss of any bits in the transmission process from
memory to the tape via the RHl1. This operation is similar
to the read data transfer where the data is successively read
from the tape, gated into IBUP (on the negation of SCLK),
and propagated through the Silo. When the first data,word
reaches OBUF, an NPR request is initiated and a Unibus
cycle allows the original data word from memory to be

The Bus Address (BA) register and bits 9 and 8 of CS 1 are
then gated onto the Unibus in order to access the specified
memory location. The C lines (CO and C I) are encoded for
a DATI cycle (data into the RHII, which is the master
device). A delay of 200 ns is provided for deskewing on the
Unibus. This deskew period allows the address and Clines
on the Unibus to settle and also allows time for the
memory to decode them.

5-11

MEMORY/CPU

RH11

DR!VE

BA,WC
WRITE CHECK,
GO

WRITE CHECK,
GO

DECODE

RUN
SET BUSY

DATA, SClK
lOAO DATA INTO
IBUF AT TRAil,
ING EDGE OF
SClK
UNIBUS
CYCLE
(BUS AODR,
MSYN)

DATA, SSYN

EBl PULSE

CP-1344

Figure 5-7 Write Check Cycle Interface Diagram

5-12

UNlaUSFLOW

MASSBUS FLOW

CSRA

DBCa
BCTH

CSRA
PROGRAM LOADS

we,BAs. Fe

BCTA
BCTB

CSRA

DBCJ

BCTH
BCTA
CSRA

DBCJ

CSRA
BCTH
CLEAR READY;
CLEAR SILOI!o
SILO CONTROL

DBCB
DaCJ

CSRA
oaCB

oece

BCTH

BCTJ

OBCC,OBCD
DSCS

BCTH

BCTJ
CSRe

DBCB
OSCS

CSRA

BCTB, BCTC
DSCA

YES

DBCB

CSR8

DSCA

BCTO
BCTE

OBCA

YES
DBCA

ASSERT ROY

CSRA

I
l

DBCA

SCTO.BCTE

OSCS

DSCA

DBCS
CSRA
DSCS
CSRB

F
DSCS
DSCC.DBCO

DBCA

DBCA
CSRB

CSRB

DBCB

CP-1346

OBce
OSCC.OBCD

CSRB
NO
OBCS

CSRS
CSRA

OBCA

DBCA

Figure 5-8 Write Command Flow Diagram

After the 200 ns deskew, the RBi i asserts BUS MSYN and
increments the Word Count (We) iegistei. The p~q 11 then
waits for SSYN to be returned from memory with the first
data word. If SSYN does not occur within 10 ps of MSYN,
the RHII sets NEM (non-existent memory) error and TRE
(transfer error). A 125 ns ~~}ay is provided for deskewing
data on the Unibus and also provides time to allow the data
to be internally gated to IBUF. After 125 ns, a DATA STR
(data strobe) signal is generated. The leading edge of DATA
STR clocks the data into IBUF and sets IBUF FULL. Also
the status of the first cell in the Silo is checked (IRDY)
and, if empty, NEXT CYCLE is set to allow back-to-back
memory references.

aiready is the second memOry reference of Ci bCick-to-back
cycle, BBSY is negated and the RHII waits for IBUF
FULL to clear before reinitiating an NPR sequence at point
o in the flow diagram. The dotted input shown indicates
that both parallel branches must complete before the flow
can sequence to point D.

The Unibus flow divides into two paths at this point. The
first path checks to see if the START signal should be
asserted; the second path provides the signals required to
complete the present Unibus cycle and to start the new
one. In addition, the second path allows the data from
IBUF to be gated into the Silo and bubble up to the top;
the second path will be described first, since the first path is
used to initiate the Massbus flow when START is present.

NOTE
If TRE sets, START is asserted and generates
the RUN signal which the drive is waiting for.
On the first SYNC ClK from the drive, the
RHII sets an ERROR flip-flop. When ERROR
is set, the synchronous bus data drivers are
disabled, no more words are clocked out of
OBUF, and RUN is negated at the next EBl
assertion (which occurs at frame count overflow).

The first breakpoint in the flow previous1y described will
now be discussed. It must be understood that this operation
is occurring in parallel with what has just been described.
DATA STR increments the START counter which counts
up to 64. START is asserted when the counter reaches 64,
or word count overflow occurs, or TRE sets.

MSYN is negated and a 75 ns delay is provided to allow the
memory to deselect. This branch of the flow then divides
into two simultaneously occurring operations. When
BUBBLE IN is set, it triggers the logic to look for Input
Ready (IRDY) at the input to the Silo. When IRDY is
present, a SHIFT IN pulse is generated which clocks the
data from IBUF into the Silo. If a word is in the first cell of
the Silo, IRDY is inhibited until the word bubbles up to the
next cell. When the Silo accepts the word from IBUF, it
clears IRDY and the word begins to bubble up the· Silo.
When IRDY clears, BUBBLE IN and IBUF FULL clear.
When the data reaches OBUF, it is ready to be transferred
to tape. However, the drive is not connected to the RHII
until the START signal is asserted.

S.4.2 Massbus Flow Description
If the conditions causing the START assertion are not met,
then this branch of the flow terminates until entered with
the next Unibus memory cycle. When the START Signal is
asserted, the Massbus flow is initiated. With START
asserted, the RHll waits for OBUF FULL and then asserts
the RUN line. By waiting for OBUF FULL, the RHll
ensures that a data word is available on the Massbus for the
drive to accept.
When the RUN signa) is set, the RHll is connected to the
drive and the RHll now waits for the first SYNC CLK
from the drive. If a SYNC CLK does not occur after
200 ms, the MXF (missed transfer) error is set which, in
turn, sets TRE. This action clears the RUN line and returns
the RHII to the Ready state. When the SYNC CLK signal
is received by the RH 11, it is returned to the drive as a
WRITE CLK signal. The data from OBUF has been gated
on the synchronous bus data lines. On the trailing edge of
SYNC CLK, OBUF FULL is cleared, BUBBLE OUT is set,
and the Drive Word Count (DRWC) register is incremented.
The DRWC register is checked for overflow. If there is
overflow, the synchronous bus data drives are disabled
which effectively writes Os in the remaining word slots in
the record and the RUN signal is negated. The RHII then
walts for EBL. On the trailing edge of ESL, the RHll sets
the internal EOS (end of segment, or record) signal and
returns to the Ready state.

This branch of the flow not only inputs data to the Silo but
also shows the completion of the Unibus cycle. The Bus
Address (BA). register is incremented by 2 to point to the
next sequential memory word. The RH 11 examines the WC
f<lr~ord counter overflow and also examines TRE. If word
count has overflowed or if TRE is present, the second
memory cycle is not performed, the address and C lines are
removed from the Unibus, and BBSY is negated, which
allows another device to become bus master. The RHt1
waits for the drive to finish the transfer before going back
to the Ready state. If TRE or word count overflow is not
present, the status of NEXT CYCLE is checked and, if
asserted during the first memory cycle of the back-to-back
references, the flow then goes to point E to start the second
memory cycle. If NEXT CYCLE is not asserted, or if it

5-14

If drive word count overflow did not occur, the RHll
examines ORDY (output ready) at the trailing edge of
SYNC
This is done to ensure that a word is in OBUF
in time for the next transfer. If ORDY is not asserted, a
DLT (data· late) error is raised which, in turn, causes TRE.
The synchronous bus data drivers are disabled which causes
Os to be written in the remaining words in the sector. The
RHII then waits for the EBL signal from the drive, clears
the RUN line, asserts the EOS signal, and returns to the
Ready state.

eLK.

If ORDY is asserted, the Silo data is clocked into OBUP
and OBUF FULL is set. When the data word is gated from
the Silo to OBUF, ORDY is cleared and BUBBLE· OUT is
cleared to prevent the next word in the Silo from being
clocked into OBUP. When the next data word bubbles up
to the top cell, ORDY is again asserted. If TRE is not
present, the Massbus flow loops back and the RH 11 waits
for the next SYNC CLK from the drive, indicating the next
word is to be transferred.
If TRE was set, the RHII waits for the SYNC CLK
negation before synchronizing the error condition. At this
point the Massbus data drivers are disabled to cause a
zero-fill in the rest of the record. In addition, RUN is
negated. At the trailing edge of EBL, End of Segment
(EOS) is set and the RHII returns to the Ready state.

S.S READ FLOW DIAGRAM DESCRIPTION
Figure 5·9 is a detailed flow diagram of the read data
transfer. Initially, the RHll is in the Ready state and the
program specifies the bus address, word count, and selected
unit (specified in CS2). A read command is loaded in bits
05 through 01 of CSI and the GO bit is set in bit 00 of
CSt. The Ready state in the RHII is then cleared, the RUN
line is asserted which logically connects the RHII to the
drive, and the Silo and Silo control are initialized. At this
point the flow divides into two asynchronous branches the Massbus flow and the Unibus flow. The Massbus flow is
described first because it is necessary to provide the first
data word (ORDY assertion) to begin the Unibus flow.
5.5.1 Massbus Flow
The RHll sits in a Wait state waiting to receive SYNC CLK
signals from the drive.

NOTE
If there is no SYNC ClK after 200 ms, MXF
error and TRE are set. The RUN line is cleared
and the RHII returns to the Ready state.
SYNC CLK is issued after the TM02 has initiated tape
motion and has a word ready. The leading edge of SYNC
CLK informs the RHII that the drive has asserted a data
word on the Massbus. On the trailing edge of SYNC CLK,
the Drive Word Count (DRWC) register is incremented
which indicates the number of words received from the
synchronous bus. Also, the RHII checks IBUF FULL.
If IBUF FULL is asserted indicating a word in IBUF, a DLT
(data late) error is posted since there is no place to store the
incoming data word. The RHll then clears RUN. On the
trailing edge of EBL, the EOS (End of Segment) is set and
returns the RHII to the Ready state.
If IBUF is not full, the data word from the Massbus is
clocked into IBUF and the IBUF FULL flag is asserted.
After alSO ns delay (to allow the data in IBUF to be
available to the Silo) the BUBBLE IN flip-flop is set. If
Input Ready (IRDY) is not asserted (indicating the presence of a data word in the bottom cell of the Silo), the flow
waits for IRDY to be asserted. As soon as IRDY is asserted,
the BUBBLE IN flip· flop enables the data word to be
clocked from IBUF into the Silo. When IRDY is negated,
the IBUF FULL flag and BUBBLE IN are cleared, allowing
a new word to be loaded into IBUF.
Each new data word from the drive is accompanied by
SYNC CLK and on the trailing edge of each SYNC CLK,
the drive word count is incremented indicating receipt of
another word. The Drive Word Count register is loaded in
parallel with the Word Count register. Both registers
contain the 2's complement of the number of words to be
transferred. DRWC register is now checked for overflow. If
drive word count has not overflowed and there is no TRE,
the flow loops back to point C and waits for the next
SYNC CLK and the next data word. With TRE set or drive"'
word count overflow, the RUN line is cleared. The RHII
waits for EBL, sets EOS on the trailing edge of EBL, and
returns to the Ready state when the Unibus flow is
completed.

0--.J

MASSBUS FLOW

RH11 READY

PROGRAM LOADS

WC&OBA

DBCB

NO SYNC CLK
ASSERTION FOR
200MS

CSRA

BCTA
BCTB

UNIBUS FLOW

FIRST WORD

:~~B~=~~RU

)-_

IBUF (MASS DATAI/
BCTJ
BCTA
CSRA

DBCB
BCTJ
CSRB

BCTD

' -_ _-,._ _ _ BCTE

CLEAR READY;
CLEAR SILO 8.
SILO CONTROL

CSRA
DBca

DBCA

CSRA

YES
CSRA

oeCA
DBCB
DBCC,DBCD r------a------~
DBCB
CSRB

OBCB

Dace

NEGATE BUS 'A'
BUS 'C' 8. BUS
'0' LINES

BCTB, BeTe
DBCA

oaca
DBCB

CSRA
OBCB

DBCB

oace,oacD

,(
NEGATE IROY
IBUF FULL -.0
BUBBLE IN-O

ASSERT BUS BBSY
8. NPC MASTER,
NEGA TE BUS SACK

OBCB

.,.-

osee,oaeo

BCTH

DBea

I
I

BCTo, aeTE

I
I

I
I
I
I

YES
CSRA

CSRB

CSRA

I
CSRB

oeCA

I
I
I
I
I

CSRa

l
oeCA
CSRB

Figure 5·9 Read Command Flow Diagram
5·16

oeeB

'"
CP-1346

5.5.2 Unibus Flow
The Unibus flow is waiting for the first data word to be
clocked to the top cell of the Silo. When this occurs, ORDY
(output ready) is asserted. Since this is the first word,
OBUF is not full and the data word is gated into OBUF, the
OBUF FULL flag is asserted, BUBBLE OUT is cleared
(previously initialized set), and ORDY is cleared. The word
count is incremented. The condition of OBUF FULL being
asserted causes DATA REQ to set, whicn enables the RH11
to assert BUS NPR. The RH11 waits for NPG (nonprocessor grant); upon receipt of NPG, the RH11 is the
next device to gain control of the bus and asserts BUS
SACK acknowledging receipt of NPG. BUS NPR is also
cleared. The RH11 is waiting for BBSY and SSYN from the
previous Unibus cycle to be removed. When this occurs,
SACK is cleared and the RHII asserts BBSY and becomes
bus master.

present with TRE or word count overflow, the ~Ji11 ~
to the Ready state. Both the Massbus and Unibus 10
must complete before the RH11 goes to the Ready statt
is at this point that the two asynchronous loops merge
order to set Ready.

The RH11 then asserts an NPC master signal, gates the bus
address to the Unibus address lines, encodes the control
lines (CO and Cl) for a DATO cycle, and gates the data
from OBUF to the Unibus dat~ lines. The RH11 now waits
200 ns to deskew the address, control, and data lines before
BUS MSYN is asserted.

The second branch, which begins after the 75 ns del:
allows data to be bubbled out of the Silo and into OBl
register. This is shown by OBUF FULL being cleared a
BUBBLE OUT set to allow the data word in the top cell
the Silo to be transferred to OBUF. When ORDY
asserted, the Silo data is transferred to OBUF and OBl
FULL is set. The dotted lines indicate that this operati
(OBUF FULL setting) allows the first branch to contim
When ORDY is negated, the BUBBLE OUT flip-flop
cleared and the we register is incremented. The flow th
ends until the next memory cycle causes this branch to
reentered.

The RHll asserts BUS MSYN and waits for memory to
respond with SSYN. If the memory location specified by
the bus address does not respond within 10 ps, the RHll
sets a NEM (non-existent memory) error, which causes TRE
to set.

If there is no transfer error or word count overflow, the
address is incremented, and if this is the second mem
cycle or NEXT CYCLE is not set, BBSY is cleared. At 1
point, the flow stops and waits for OBUF FULL to
before looping back to point E and reinitiating an N
cycle.

If the bus cycle was not the second one and the NE
CYCLE flop is set, the RHll waits for the next data w(
(OBUF FULL asserted) before starting the second back·
back cycle. At this point, the flow loops back to point F.

SSYN :indicates that the memory has accepted the data
word. At this time, MSYN is negated and the status of the
Silo is checked (ORDy) to determine if another memory
reference can be performed. If ORDY is asserted, NEXT
CYCLE is set.

5.6 WRITE CHECK FLOW DIAGRAM DESCRIPTION
Figure 5-10 is a detailed flow diagram of the write-che
operation. This operation reads data from the device via t:
Massbus and stores the data in the Silo. When the da
propagates through the Silo to OBUF, a Unibus cycle
performed to read the corresponding word in memory. Tt
word is compared with the word from the drive which h
propagated into OBUF. The comparison is accomplished 1
a series of Exclusive-OR gates. If the two words are equ
(indicating no transmission errors), the OBUF FULL flag
cleared, and successive data words are compared until ,
error or until. all words have been compared. If the two a
not equal, the WeE (write-check error) bit is set which se
TRE, the word is frozen in OBUF, and the OBUF FUL
flag remains asserted. Either the word read from the devi(
and stored in OBUF or the word read from the Unibl
could be in error. Since it is more difficult to access tt.
word from the drive, this word is held in OBUF in the ever
ofa WeE.

The RH11 then waits 75 ns after MSYN is negated before
the address is removed or changed. The 75 ns deskew
ensures that the memory is properly deselected. The flow
now divides into two branches. The first branch finishes the
Unibus cycle while the second branch allows data to bubble
out of the Silo into the OBUF register. The first branch will
now be described.

If a transfer error or word, count overflow occurs, the
address, control lines, and data a.re removed from the
Unibus, the bus address is incremented by 2, BBSY is
cleared, and the RH11 waits for the EOS produced by the
trailing edge of EBL from the Massbus flow. If EOS is

5-17

UNIBUS FLOW

PROGRAM LOADS
WCa.eA

DBCB

NOSYNCCLK
ASSERTION FOR
200MS

BCTA
BCTB

FIRST WORD

'r-

BUBBLE THRU
SILO FROM
IBUF IMASS DATAl,'!

BCT J
acTA
CSRA

DBCB
eCTJ
CSRB
BCTD

'----""T'"--~ BCTE

DBCD
CSRe
CLEAR READY;
CLEAR SILO&
SILO CONTROL

CSRA
DeCB

CSRA

YES
CSRA

DBCB
DBCC,DBCD

DBCA
oeCB
CSRB

DBCB

oece

IF WCE· 0

DBCB

CSRA

OBCB

NEGATE BUS 'A'
'" BUS 'C' LINES

acTS, BeTC
DeCA

OBCC,OBCO
oaCB

NEGATE IRDY
IBUF FULL ... O
eUBBLE IN-O

DBCB

ASSERT BUS BBSY
'" NPC MASTER
NEGATE BUS SACK

BCTH

BCTC

oaCB
DBCC,OSCO

Dace
BUS 'A'·- BA
BUS 'C' - DATI

acTe, eCTC
Dec A
BCTO, BCTE

CSRA
DeCA
CSRB
DBCA

CSRB
DeCA

Dec A
oeCA
CSRe

OBCB

DeCA
CSRB

Figure 5·10 Write Check Command Flow Diagram
5·18

DBce

5.6.1 Massbus Flow Description
The description of the Massbus flow for the write-check
operation is identical to the read operation (Paragraph
5.5.1 ).
5.6.2 Unibus Flow Description
'The description of the Unibus now for the write-check
operation is similar to that for the read operation
(paragraph 5.5.2) with the following exceptions:
a.

A DATI Unibus operation is performed to
receive data from the specified memory location.

5-19

Upon receipt of SSYN from memory, the
RHll generates a 125 ns delay to deskew the
data on the Unibus and to allow the data to
propagate through the Exclusive-OR gates so
that it may be compared with OBUF, and

If the data from menlory and the data from the
drive (stored in OBUF) do not compare, the
WeE is posted and the parallel branch of the
flow which transfers data from the Silo to
OBUF does not occur.

CHAPTER 6
DETAILED LOGIC DESCRIPTION
6.1 GENERAL
This chapter provides a detailed description of the RHl1
logic diagrams. These descriptions should be used in
conjunction with the flow diagrams in Chapter 5 to provide
both an overall and detailed understanding of the RHII ~
The diagrams described in this chapter are tabulated in
Table 6-1.

jumper Exclusive-OR gates whose outputs are collectorORed. If any orthe output of these gates goes low, it forces
the output line low as in the case where the Unibus address
does not match the selected address of the RH 11. The
addresses to which the RH 11 responds can be reloca ted by
modifying the jumpers. If a jumper is left in, it represents a
logic 0 and if it is cut, it represents a logic I. The register
address bits are asserted low on the Unibus. For example,
address bit 12 is low at the input to the 8838 Unibus
receiver. The output of this gate goes high. This is
compared to the jumper intact which is low. The output of
the Exclusive-OR gate, after inversion, is low and this drives
the collector-ORed output line low to inhibit DEV SEL. On
the other hand, if the jumper is out, (representing a I), the
Exclusive-OR gate compares two high inputs yielding a high
output which enables the DEV SEL signal for that bit.

The M7295 module is designated BCT and is used for bus
control: the M7296 module is designated CSR and is used
for control and status~ the M7294 module is designated
DBC and is used for data path routing; and the M7297
module is designated PAC and is used for parity generation
and checking.
Detailed timing diagrams (Figure 6-1,6-2,6-3, and 64) are
also included in this chapter and may be used in conjunction with the detailed logic descriptions to show timing
relationships between signals. Figure 6-1 is the Unibus
timing diagram for a write operation; Figure 6-2 is the
Unibus timing diagram for a read or write-check operation;
Figure 6-3 is the Massbus timing diagram for a write
operation; and Figure 6-4 is the Massbus timing diagram for
a read or wri te-check operation.

Bits 4 through 1 of the Unibus address are supplied to a
32-cell read only memory (ROM). A low logic level is
supplied to the fifth address input to the ROM via the
jumper selection at E3 and thereby allows 4 address bits to
specify one of 16 cells in the ROM. The contents of the
specified cell represents a specific pattern on the eight
output signals (MO through M7) of the ROM.
These outputs are used to provide the appropriate register
signals. Each cell represents a different register address. If
more than 16 registers arc required for a particular RBI I
system, the jumpers at E3 shown below the address jumpers
are selected to feed bit 5 of the Unibus address to the
ROM. As a result, one of 32 cells in the ROM can be
specified, and Unibus address bit 5 is not compared at the
Exclusive-OR gates which enable a DEV SEL signal.

6.2 BCT A LOGIC DIAGRAM
This diagram contains the register selection logic used by
the program to select local RHII registers or remote
registers in the associated drive. The register address is
supplied to 18 Unibus receivers (8838) via the Unibus. Bits
17 through 13 of the register address are asserted designating the I/O area. Bits 12 through 5 are fed to a series of

6-1

Table 6-1
Listing of RH 11 Logic Diagrams
Logic Print

Functions

BCTJ
BCTK
CSRA
CSRB

Register Sch:-ction
Unibus A Address Drivers; SSYN; DEMAND
Bus Address. Register
Word Count Register (07:00)
Word Count Register (15 :08)
Interrupt Control
NPR Control
MXF; Data Out MPX; MB INIT
PROM Truth Table
Control and Status Register CSI
Control and Status Register CS2 and Error Status

DBCA
DBCB
DBCC
DBCD
DBCE
DBCF
DBCH
DBCJ

NPR Control Logic
Silo Timing Control
Silo Data Path (II :00)
Silo Data Path (I 7: 12)
Unibus B Da ta Transceivers
Unibus A Data Transceivers
Unibus Parity Control and Data Out MPXs
Start Control and Data Out MPXs

PACA

Parity Control (Massbus Parity Detection and Generation)

MBSA
MBSB
MBSC

Massbus Transceiver (Massbus Cable A)
Massbus Transceiver (Massbus Cable B)
Massbus Transceiver (Massbus Cable C)

BUSA
BUSB

Unibus A Cable Diagram
Unibus B Cable Diagram

M9300

Unibus B Terminator

G727

Grant Continuity Module

BCTA
BeTn

BCTC
BCTD
BCTE
BCTF
BCTH

6-2

CSRA GO CLR L

SINGLE CYCLE
SILO NOT READY

=ti

CSRA WRITE L
DBCB DATA REO L ~

BACK TO BACK CYCLE

I-

-I
DONE *EOS--.r-

t4"__IB_U_F_F_U_L_L_ _ _ _ _ _ _ _ _ _ _ _ _r---l...____________1

...

DBCB CLR DREO L ~

L.....Jr-------------....,LJ

CLR BBSY ~

BUS NPR L ~...--J
BUS NPG H

~r-J
r1r,..._ _ _ _ _ _ _ _ _ _ r H- ,...._ _ _ _ _ _ _ _ _ __
-J

BUS SACK L

BUS BBSY L
(NPC MASTER Ll
DBCA ADDR TO BUS H
DBCA DESK MSYN H _ _ _ _ _ _ _~

DATA REO*CLR DREQ ~r-1

r....,

4,J

~rI

--------'1'. . .

DBCB INC WC L

----l

~---

----.j

51 NGLE CYCLE
WC OVERFLOW

_r--__- 200 NS

,,"--------'

DESK MSYN

BCTEWCOFLO(1)H ___________~-----------------------------------------_-J
BCTE DONE (I}H ____________=+__________________________________________________________
DBCA MSYN (1) H _ _ _ _ _ _ _ _-"

~r-,""

_______.....rl---1...__________Jrr-,...______

DBCA DATA WAIT (1) H
DECA MSYN WAIT (1) H
(DATA STR H)
DBCA END CYCLE (1) H

\.r7L

r-:t---,. .____

r-:r--,

BCTH NBC SSYN H _ _ _ _ _ _........... _ _~~~~r--,

...Jn_

r1_

--!f"'(4-""
__'_2_5_N_S__________

('P.
('--

':r! .

--!f1'4= lOONS

----.,

r--: 200 NS

--------

r I...____

DBCA CY.CLE COUNT (1) H
DBCA NEXT CYCLE (1) H ________________.....t;:: IRDY AT MSYN WAIT
OBCA CLR BBSY L
DBCB CLK IBUFH

END CYCLE .. CYCLE COUNT=-L...J END CYCLE*NEXT CYCLE ~
MSYN WAIT~

..:::r-

~~r-'lI~----'~r----'1
~L.

DBCB IBUF FULL (\) H
DBCB BUBBLE IN (1) H ___________________~...
__I,
DBCBSHIFTINH
OBCB IRDY H

IR~*BUBBLE IN~ I

_______

L.J

-...Jr------i..~=======~~:~~~~_-:_~_~"----_.
_r--l

~~__________~~'__ _~------~-~

rt:::t

- .. . .__..or

I'"300 -'''' 400 ..,
NS

NS
11-2351

Figure 6-1 Write UNIBUS Timing Diagram

SINGLE CYCLE
SILO NOT READY

1+----

!+---- BACK TO BACK CYCLE------i

SINGLE CYCLE
WC OVERFLOW

---1

f--

--1

CSRA GO CLR L ~

CSRA READ+WR CHK H ~
DBCB DATA REQ L
DBCa CLR DREQ L
BUS NPR L

.l.;.._~~r--,.--~==O=B=U=F=F=U=L=L=======:;::~:;=:::::n
\L.J
BaSY~

CLR

DATA REQItCLR DREQ~~

BUS NPGH __________~~~~________~----------------~~~~------------------~~~~----------_ _ _ __

L.J

BUS SAC K L

BUS BBSY L
(NPC MASTER Ll

H_~~

M~~~;:::~"OOT~ ~

DBCA ADDRTO BUS

r=1L---_------'r=1~

~wo~~~------------~~~--------------

BCTE WCOFLO (l)H _______________
~~---------------------------------~

aCTE DONE(l)H ___________-+_______________________________________

~~' - - .

DBCA MSYN (1) H _ _ _ _ _ _ _ _ _ _ _

~-~

Jr--,~_ _ _ _ ____Ir~~________. . .r~~______
~t---"-J
~r---,~_______
~ 125NS
n
n~________
~100NS
n
n

(~~r---,

BCTH NPC SSYN H

'\.r('

DBCA DATA WAIT (1) H

':=rl
i( '----~---.........

DBCA MSYN WAIT (t)H
(DATA STR H)
DBCA END CYCLE (1) H

(

!
iI

DBCA CYCLE COUNT (1) H

:..r--l

r-1

~ 200NS

_ _ _ _ __

rI~

____

DBCA NEXT CYCLE (1) H _ _ _ _ _ _ _ _ _ _ _ _ _ _..,....---ORDY AT MSYN WAIT
DBCA CLR BBSY L
DBCB ClK OBUF H
DBCB OBUF FULL (\) H

END

YCLEitCYCLE COUNT

END CYCLE-NEXT CYCLE

nL_______..Jn~_______________"'n
~r----------(3U
U
~r----------.~
LtJ~__________)r---,~
~~L___________~-----lL__________

\/fl

DBCB BUBBLE OUT (11 H
ORDY'It- (
DaCB SHIFT OUT H BUBBlE ~)

250
NS

-I

_____

_______

r=1
-----'L...____

DBCB ORDY H ~~

14 _14

....

~~----~~~------II· 2358

450NS

Figure 6-2 Read & Write Check UNIBUS Timing Diagram

MASSBUS
DATA WORDS
IN BLOCK

~-----FIRST BLOCK WRITTEN
...
1ST

2 NO

3 RO

------..t.1

NTH

INTER
BLOCK
GAP

1
...~-----lAST BLOCK WRITTEN ------~.I
3 RO

NTH

eSR' GO elR l L 1 ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CSRA WRITE L

-6_

DONE *EOS-----",--

DBCJ START H --i~~SllO FillED
CSRA RUN (llH~~~----------------------------------------.-D-R-W-C-OF-l-O-~~L----___- - - - - - - - - - - - - - - -____

MBSB EBl H __________

__________________________

~~~

_____________________________________

CSRB EOS (l)H

. . .- - - - - -

DBce WRITE ClK H -~I~~~~~t_y....rr-,----------Jrry~ra....;...r~~r-,
DSCS DRIVE ClK H~r

~~~~~~~-------------~~r~~~,~--------~----~------

eCTE lWRD H ________~--------------------------------------------------~
eCTEDRWC OFlO(1)H ________~------------------------------------------------~
REMAINING DATA WORDS
IN BLOCK WRITTEN AS ·O·S

DSCB GATE svNCD H --~-WRI E

~::::~~.===============:-I~I~~~J~--~~L--~--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DBeB

BUBBlEOUT(1)H---<~~

ORDy*eUB~lE

M~S~"O~H~~--------------------~~
DBCB ORDY H ----1~f-

~______________________________

___ _

DBce DlTH _____________________________

__-_-_________________________________________________

~!_-_-_-_-_-_-

"-23!!6

Figure 6-3 Write MASSBUS Timing Diagram

MASSBUS

IioI.~---

_I
FIRST BLOCK READ .-.. -----.--.----.----.~

!NTER

B~~~K

I0Il•. . . - - - - - - - lAST BLOCK R E A D - - - - - - - - e -..I

DATA WORDS l I ST
2ND
3 RD
I NTH
1ST
2ND
3 RD
NTH
CSRA GO ClRl IN BlOrC~K~________________________________________________________________________________________________

eSRA READ+WRCHK
CSRA RUN

H~~------------------------------------------------------------------------------------D-O-N-E-*--E-O-S-==+L-----~

(1)H~~-------------------------------------------------------D~RW-C--O-F-l-O~=~.~,__________________________________

. . .r~~~~~~~L--------

MBSA SYNC ClK H _ _lr~~~~~~...,L..--------

MBSB E8l H ________________------------------------~~~------------------------------------------------~
CSRB EOS (I) H __________________________________________________________________________________________\~'~

DBCB DRIVE ClK H _ _-4IL..r''L..,..r'~..., ---------~ru-L~~~MAINING WORDS IN BLOCK IGNORED
BCTE lWRDH ________~---~-----------------------------------------------------J~~~-----------------

+-__________________________________________________- J

___________

BCTE DRWCOFlO(1)H ______

DBCB ClK IBUF H _ _ _ _ _ _~ JI.-----'

'--_~

DBCB ISUF FUll (t) H _ _ _ _ _:11
DSCS BUBBLE IN (1) H _ _ _ _ _ _~
IRDY

-r---------------n-----s'-' r-------------------------

DBCB SHIFT IN H _*.;.;....;;.B..;.,U.;;..BB;;,;l:;;:E::..-;,;..;IN

DBCBIRDYH
DBCBDlTH ____________________________

__
-_-_-_-___
-___
- ________________________________________________

~~_-_-

11-2355

Figure 64 Read & Write Check MASS BUS Timing Diagram

In addition, the four most significant address bits which are
applied to the ROM are compared against a jumper setting
which define the exact number of registers used in the
system. Each of these jumpers is weighted by the value
assigned to it. If a jumper is removed, the RHll will
respond to the number of registers designated by the
removed jumper. This number is added to the base address
set by the address select jumpers on the Exclusive-OR gates.
For example, if 12 registers are used in the system, the
jumpers weighted 8 and 4 are removed. A Unibus address
between the base address and the base address +11 words
would be a valid register address. A Unibus address equal to
or greater than the base address +12 words will cause the
Logal REG output of the comparator to go unasserted, thus
preyenting the SSYN response.
NOTE
MSYN is delayed for 150 ns by the processor to
allow the jumper Exclusive-OR gate decoder
sufficient time to decode the address of the
selected register. The MSYN signal then keys
the DEY SEL signal which starts the register
strobing sequence.

6.2.3 Decoder Inputs
Inputs' DO, D 1, and D2 to the decoder specify one of 8
outputs from 0 through 7 (outputs 3 and 7 arc not used).
RSEL 00 and RSEL 01 are applied to inputs DO and 01 of
the decoder, respectively, and specify one of the three
above mentioned registers. BUSA ('1 is applied to input D2
of the decoder and specifies an input or output function.
When BUSA Cl L is asserted, the D2 input to the decoder
is low enabling the register codes on outputs 0, 1, and 2.
This indicates a DATa or DATOB where the data is
transferred from the master (processor) to the slave
(RH11). The register Signal names incorporate the word
"IN" denoting a 'write register' operation. When BUSA C1
L is not asserted, the D2 input to the decoder is high
enabling the register codes on outputs 5, 6, and 7. This
indicates a DATI or DATIP where the data is transferred
from the slave (RHl1) to the master (processor). The signal
names are designated with the word "OUT" denoting a
'read register' operation. Input D3 is asserted low if the
LOCAL REM H signal indicates a local register is addressed
and DEY SEL H is asserted.

6.2.4 Decoder Outputs
With input D3 low, outputs 0 through 7 are enabled. If
input 03 is not asserted, the outputs from 0 through 7 are
inhibited and the decoder outputs are switched to 8 and 9
which are not used. Since the RSEL 04 through RSEL 00
signals are not used for selecting a drive register when the
LaC/REM H .signal is asserted, it is possible to redefine the
two bottom bits of the ROM (RSEL 00 and RSEL 01) to
be used as inputs to the decoder.

6.2.1 Local/Remote Register Selection
In addition to encoding the register address, the ROM
asserts the LOC/REM H signal if a local register is being
accessed. The Massbus handshaking sequence necessary to
access a register located in a drive is inhibited in this case. If
a remote register is being addressed, the LaC/REM H signal
is not asserted (the Massbus handshaking sequence is
enabled) and the DEMAND signal is initiated.

NOTE
The CS 1 register. is shared by the RH 11 control
and the associated drive. The LOCAL/REM H
signal is not asserted to address this register. If
LOC/REM H is asserted, the Massbus handshaking sequence is inhibited. This would prevent access to the portion of the CS 1 register
located in the drive.

The upper decoder is similar to the lower one with a few
exceptions noted below.

6.2.2 RSEL Signals
The RSEL 04 through RSEL 00 signals from the output of
the ROM are supplied to the Massbus which will be
decoded in the drive to select a specific register. In
addition, RSEL 00 and RSEL 01 are supplied to the lower
of two 7442 BCD-to-decimal decoders and are used when
the LOCAL/REM signal is asserted. The lower decoder
decodes the CS2, DB, and BA registers and whether an
input (from processor to RHI 1) or output (from RHll to
processor) function is to occur.

6-7

•

Input D2 operates exactly the same as
described for the lower decoder.

•

ROM outputs M6 and M7 are used to decode
the registers (WC, AS, CSl) associated with the
upper decoder and are applied to inputs DO and
D1, respectively.

•

Input D3 is enabled when DEY SEL L is
asserted. LaC/REM H is not required since the
M6 and M7 outputs of the ROM are not dual
defined and may be used anytime.

6.2.5 Word or Byte Addressing
The logic network with the AO, CO, and Cl inputs
determines whether word or byte addressing is required and
whether an input or output function is occurring. The
n~twork implements the chart ~;hown below.

the one-shot. The positive-going trailing edge of this
one-shot triggers a second one-shot with external components chosen for a delay of 135 ns. A positive-going pulse
of 135 ns from the 1 output and a negative-going pulse of
135 ns from the 0 output are available.

o
o

6.2.9 Deskew Demand (DESK DEM)
The output of the second one-shot is designated DESK
DEM (1) H or DESK DEM (0) H and proVides a total delay
of 220 ns before DEMAND is issued to the Massbus (see
logic diagram BCTB).

DATI
DATIP
DATa
DAToB

if AOO =0, low byte is
specified.

6.2.10 Register Strobe (REG STR)
A REG STR signal is generated 85 ns after MSYN and is
used for clocking the local registers.

if AOO = I , high byte is
specified.

6.2.11 Control Out (CTRL OUT) Signal
The CTRL OUT L signal is used when reading a remote
register in the drive. CTRL OUT L is generated when the
LaC/REM H signal is not asserted (remote mode), DEV
SEL is asserted, and the BUSA C1 L signal is not asserted.
This signal switches the multiplexer on logic diagram DBCH
to gate the Massbus asynchronous data to the Unibus data
lines making the register information available to the
program.

. 6.2.6 Control Lines
The CO and C 1 lines from the Unibus generate the DIR
TRANS (direction of transfer) signal. When this signal is
asserted, the direction of data transfer is from the RHll to
the drive register via the Massbus. When the signal is not
asserted, the direction of data transfer is from the drive
register to the RH 11, and then to the Unibus to be made
available to the program. The DIR TRANS signal is used to
form the CToD signal on the Massbus.

6.2.12 Gate Control (GATE CNTL) Signal
The GATE CNTL H Signal is used when writing into a
remote register in the drive. GATE CNTL L is generated
when DIR TRANS and DEV SEL signals are asserted and
gate the Unibus data signals to the Massbus control lines.

6.2.7 ODD BYTE L Signal
The ODD BYTE L Signal is asserted when performing a
DATOB to the high byte and is used to generate DIS DEM
(disable demand). This is done to prevent the low (even)
byte of the C51 register from changing to the upper byte
when the program is doing a byte operation (this is
necessary since the Massbus does not implement byte
operations and write able bits in the low byte of CS 1 are
located in the drive).

6.3 LOGIC DIAGRAM BCTB
This sheet contains the DEMAND, SSYN, and NED logic
and also contains the Unibus A address drivers used to gate
the bus address to the Unibus.

6.2.8 Device Select (DEY SEL) Logic
The upper portion of BCT A shows the DEV SEL logic and
the deskew demand logic. Bits 17 through 5 of the Unibus
A address are used to generate DEV SEL L when MSYN
occurs. MSYN is delayed from the address ISO ns to allow
the address to be properly decoded by the jumper
Exclusive-OR gates.

63.1 Deskew Demand (DESK OEM) Logic
1 he Dl SK DEM (0) H signal from sheet BCT A is delayed
2 ~O ns (rom MSYN and sets the SET DEM flip-flop. When
Sl t, this flip-flop causes DEMAND to be set, provided the
1 RANS (transfer) Signal is not present on the Massbus. The
1 RANS signal is generated in the drive when the drive is
r 'ady to accept data or has data for transfer to the RBll.

The negative-going edge of the DEV SEL L signal triggers
one-shot muItivibrator E63. The external components
associated with this multivibrator are chosen to provide an
85 ns delay. Consequently, the negative-going edge of DEV
SEL causes an 85 ns negative-going pulse at the 0 output of

6.3.2 Response from Drive
TRANS generates RESP L (response), indicating that the
drive has responded to the controller. If no response occurs
within 1.5 jJ.S, a non-existent drive has been accessed. In tills
case, the NED (non-existent drive) flip-flop on BeTB is set.

6-8

Setting SSYN-Access Local Registers - SSYN is set during
the access of local registers as a result of REG STR II and
DIS DEM H being asserted. REG STR H is generated 85 ns
after MSYN on logic diagram BeTA and is used as a strobe
input to the local register being accessed. Signal DIS DEM
H indicates that the Massbus cycle is inhibited and a local
register is being accessed. At the trailing cllge of thr REG
STR signal, SSYN is set indicating that data has been
accepted or is present on the Unibus when writing or
reading a local register.

6.3.3 SSYN Logic
The SSYN logic is used to determine when SSYN is sent to
the Unibus. Each of the various methods of setting SSYN is
described below.
Setting SSYN-Writing Remote Register (register electrically
located in the drive) -- When the program writes a remote
register via the RH 11, the unit select bits, the RSEL 04
through 00 signals, and the data are gated onto the
Massbus. The unit select bits select the specified unit and
the RSEL 04· through 00 signals select the appropriate
register in that unit. If the RHII is writing into a remote
register, DIR TRANS H is asserted. After a 220 ns deskew
period, the RH 11 asserts DEMAND on the Massbus. When
the drive sees DEMAND and recognizes its own unit select
code and register address, it takes the data and issues
TRANS which generates RESP in the RHl1. Consequently,
since DEMAND (1) H is asserted (accessing a remote
register), DIR TRANS H· is asserted (controller-to-drive
transfer), and RESP L is asserted, gate E83 at zone D-6
generates SET SSYN L which is applied to the direct set
input of the SSYN flip-flop.

One-Shot Multivibrator (1.5 IlS) -- The 1.5 IlS one-shot
muWvibrator (E93) shown in zone C-6 serves two purposes.
First, it checks whether a non-existent drive has been
accessed. The one-shot is fired when DEMAND is asserted.
When the drive responds with TRANS which generates
RESP L, the one-shot is cleared. As previously described,
RESP L either generates SET SSYN L or DESK DATA L,
depending on the state of the DIR TRANS H signal. Either
of these signals direct clears the 1.5 IlS one-shot, causing a
positive-going edge at the output. This edge tries 10 clock
the NED flip-flop set, but the same signal that direct clears
the 1.5 IlS one-shot also direct clears the NED flip-flop.
When the RHll issues DEMAND and receives TRANS from
the drive, the 1.5 IlS one-shot is cleared. In addition, the
NED flip-flop is inhibited from setting. If the drive did not
respond, the SET SSYN L and DESK DAT A L signals are
both inhibited from clearing the one-shot, causing the
one-shot to time out. At this time, the positive-going edge
clocks the SSYN flip-flop set. The NED flip-flop also sets if
the register being accessed is not the Attention Summary
register.

NOTE
The Attention Summary register is a I-bit
pseudo register. When this register is accessed,
more than one drive may respond. Therefore,
the TRANS signal cannot be used to indicate
the availability of data. In order to ensure that
all drives have. their respective Attention
Summary bits loaded, a 1.5 IlS delay is incorporated before the setting of SSYN.
Setting SSYN-Reading Remote Register - If the RHll is
reading a remote register (accepting data from the drive),
the drive after recognizing its unit select code, register
address, direction of transfer, and DEMAND, issues TRANS
which generates RESP L in the RH11. Since DIR TRANS H
is unasserted at this time (drive-to-controller transfer), a
200 ns one-shot multivibrator (E93) is fired. The external
components are selected to provide the 200 ns pulse. This
delay is designed to allow the data from the drive to
propagate to the RHll and onto the Unibus before SSYN
is set. In other words, SSYN cannot be asserted on the
Unibus until the data from the drive has been transferred to
the Unibus and has stabilized. Consequently ,when the
one-shot fires, the a output goes low for 200 ns forcing the
clock input to the SSYN flip-flop low for this period. At
the end of 200 ns, the positive-going trailing edge of the
200 ns pulse sets SSYN which is asserted on the Unibus.

NOTE
The DEV SEL H signal is applied to the direct
clear input of the one-shot and NED flip-flops.
If set, the flip-flops are cleared after the Unibus
cycle is completed and the addressed register
has been deselected.

A second function of the one-shot is to provide a 1.5 IlS
waiting period to allow the Attention Summary register in
the various drives to be properly read from or written into.
In this case, the one-shot times out because the RESP Signal
is inhibited and at the end of 1.5 IlS, SSYN is set. NED is
not set since the flip-flop is set only when a register other
than the Attention Summary register has been addressed
and no RESP is received.

6-9

DIS DEM disables the DEMAND signal from being asserted
on the Massbus and is generated under the following
conditions:
1.

If the LaC/REM H signal is asserted indicating
local mode, DIS OEM is generated to inhibit
the Massbus handshake sequence.
DIS OEM is generated if the access is to the odd
byte (ODD BYTE L) in the CSI register (CSI
IN L). The CS1 register is shared by the RHI1
and the drive with the odd byte being in the
RHII and the even byte being in the drive.
ODD BYTE Land CSI IN L generate DIS OEM
to inhibit the Massbus handshake sequence in
order to prevent altering the even (low) byte of
the CS 1 register located in the drive when the
program is doing a byte operation to the odd
(high) byte in the RHI1. This is necessary
because the Massbus cannot differentiate byte
from word operations.

At this time, the RH 11 is connected to Unibus A. During
NPR operations, if PSEL is asserted, the RH 11 is connected
to Unibus B. The RHll is always powered up in the
condition where PSEL is cleared indicating the RH 11 is
connected to Unibus A.
6.3.5 Data Buffer Out Clock
The DB OCLK H Signal is used to release data at the output
of the Silo when the DB register is read by the program.
The BCT A CO L signal is used to inhibit the assertion of
DB OCLK during Unibus DATIP operations. This is
necessary so that a read-modify-write instruction does not
falsely remove data from the Silo. DB register selection is
used for maintenance purposes when verifying the operation of the 66-word Silo Buffer register. Signal DB OC'LK is
asserted when the RHII responds with SSYN to the
register operation (if not a DATIP) and is released when the
processor removes MSYN.
6.4 LOGIC DIAGRAM BCTC
This sheet contains the logic for the 16-bit Bus Address
register and the 2 extension address bits located in the CS 1
register. The register functions as an up-down counter and
consists of four 74193 chips, providing outputs labeled
BUSB AOl L through BUSB Al5 L. The inputs to the chips
come from the Unibus A data receivers, shown on sheet
DBCF. The register is loaded when the BA IN L signal,
REG STR H, and HI BYTE or LO BYTE signal is available,
depending on whether the high byte or low byte is to be
loaded. If the register is to be loaded as a word, both HI
BYTE Hand LO BYTE H signals are asserted.

The STOP DEM L signal is asserted when the
processor tries to load a function code specifying a data transfer operation into the drive
while the RHI1 is already busy executing a
data transfer function with that drive or some
other drive. For example, if unit 0 is doing a
read data transfer and the processor tries to do
a read or write data transfer in unit I, the STOP
OEM L signal from CSRB prevents the function
~ode from being transferred to unit I; otherwise, there would be the OR condition of data
from unit 0 and unit 1 on the synchronous
Massbus and the program could not distinguish
unit 0 data from unit 1 data.

In addition, the DEMAND signal is inhibited when the LEG
REG (legal register) signal from BCT A is not asserted. This
prevents a SSYN response by the RHll which indicates to
the processor that the Unibus address was not recognized
by the RHll.

A fifth chip processes bits 9 and 8 of CS 1 which are
extension bits of the Bus Address register. These bits are
designated A16 and AI7. The chip is loaded when CSI IN
L, REG STR H, and HI BYTE H are asserted. The RDY
signal must also be asserted to load this chip in order to
prevent bits A16 and A17 from being changed unless the
RHII is in the Ready state, since other commands can be
passed through the dynamic CSI register to drives not
doing transfers.

6.3.4 Gating Address Onto Unibus
The remainder of the sheet shows the Unibus drivers which
gate the contents of the Bus Address (BA) register and A16
and AI7 of CS1 onto the Unibus address lines. This is
accomplished when the RHII is bus master and doing NPR
cycles. Signal ADDR TO BUS H is used to gate the address;
signal SEL BUSA H from the CSR module (sheet A) is
asserted when the PSEL bit in the CSI register is cleared.

The 74193 chip has a load input. When this input goes low,
the data on the input lines is loaded into the register. The
chip also has a CLR input which clears the register to all Os
when CLR H is asserted. The register functions as an
up-down counter which counts on the positive-going
trailing edge of the ADDR TO BUS H strobe. If eNT DW
(1) H is asserted, the register counts down; if CNT DW (0)
H is asserted, the register counts up.

6-10

6.4.1 Clocking Bus Address Register
The ADDR TO BUS H clock can be inhibited by setting the
bus address increment inhibit bit (BAI bit 08) in the CS2
register. When the BAI bit is set, it prevents the bus address
from changing during transfers, and the transfers will
always occur from that same memory location. This feature
might be used when refreshing a display. Normally, BAI (0)
H is asserted at the input to AND gate E88 in zone A-7 to
enable the ADDR TO BUS H strobe used to increment or
decrement the Bus Address register.

a similar arrangement for the lower eight bits of the Drive
Word Count and Word Count registers and contains an
additional two quad-input multiplexer chips for selecting
the lower bits of the Bus Address or Word Count register.
6.S.1 Word Count Registers
The Drive Word Count (DRWC) register counts words
transferred between the RH 11 and the Massbus and is
invisible to the program. This register detects when the
RUN line should be unasserted on the Massbus. The Word
Count (WC) register is a programmable register which
counts words transferred between the RH 11 and memory
on the Unibus; Both registers are loaded in parallel with the
2's complement of the number of words to be transferred
and are incremented toward 0 for each transfer.

6.4.2 Address Bit 00
Address bit 00 is not implemented making the bus address
always even (word addressing). This results in only three
bits being implemented in the low-order 74193 chip. Since
the carry and borrow lines are based on four bits in the
chip, two external gates are employed as decoders - AND
ga te E 21 in zone B-6 to detect a carry condition (all 1s) and
NOR gate E20 in zone C-6 to detect a borrow condition (all
Os).

The load input to both registers is the logical AND of WC
IN H (Word Count register specified), REG STR H and HI
BYTE Hand LO BYTE H. The Drive Word Count register is
incremented by DRIVE CLK H on sheet BCTD. This signal
is a synchronous clock and occurs if there is no word count
overflow or no error condition. The Word Count register is
clocked by the INC WC L signal from sheet DBCB. The
registers count on the trailing edge (positive-going) of the
DRIVE CLK signal and INC WC Signal. A carry out of one
chip of the Word Count register is rippled to the count
input of the next successive chip. When a carry occurs out
of the chip with the most significant bits, word count
overflow occurs. The Drive Word Count register is configured in the same manner and when the carry occurs out of
the chip with the most significant bits, drive word count
overflow occurs. Note the absence of a clear input to both
registers. Since the registers are preloaded at the start of a
data transfer, a clear is not necessary.

6.4.3 Count Down (CNT DW) Flip-Flop
A CNT DW flip-flop is shown in zone A-4 of the diagram
and is employed for future capability when reverse writecheck and reverse read operations may be implemented.
When a reverse function code is loaded (defined by a
combination of GO CLR and data bits DOl and D02), the
CNT DW flip-flop sets, and reverse write-check and reverse
read operations can be implemented.

6.4.4 Bus Address Outputs
The bus address outputs from the MTBA Bus Address
register are multiplexed with the outputs of the MTWC
Word Count register on logic diagrams BCTD and BCTE for
transfer to the Unibus data lines when the register is read
by the program.

6.S.2 Word Count or Bus Address Selection
The output from the Word Count register is applied to
8234 multiplexer chips. These chips switch either the
contents of the Word Count register or Bus Address register
to the output. When the SO input is low, the B inputs (BO,
Bl, B2, etc.) are switched to the F outputs (FO, FI, F2,
etc.). This condition occurs when the Bus Address register
is selected from the register select logic on sheet BCT A.
When the SI input is low, the A inputs (AO, AI, A2, etc.)
are gated to the F outputs. This condition occurs when the
Word Count register has been selected by the register select
logic on sheet BCT A. Since SO and S 1 are supplied from a
decoder, both cannot be low at the same time. If both
inputs are high, the output is disabled and floats high unless
asserted by another chip wired in parallel. The multiplexer
is open-collector and can be bused together with other

The BA register and address extension bits (AI6 and AI7)
are also driven onto the selected Unibus (A or B) when the
RHll is performing NPR transfers. This selects the memory
location to be accessed by the transfer. The Unibus A
address drivers are located on sheet BCTB, while the Unibus
B address drivers are located on sheet BCTC.
6.S LOGIC DIAGRAM BCTD, BCTE
Logic diagram BCTE contains the upper eight bits of the
Drive Word Count register, the upper eight bits of the Word
Count register and two quad-input multiplexer chips (8234)
used to select the word count or bus address when the
program reads these registers. Logic diagram BCTD contains

6-11

If an error occurs (TRE asserted), then the DONE signal
will be asserted at the end of the DATA REQ. The RH 11
waits for the EOS (end. of scgmen t) before going to the
Ready state. The DRWC OFLO flip-flop and Drive Word
Count register function the same as the WC OFLO flip-nop
and Word Count register. The carry output of the Drive
Word Count register generates a LWRD H (last word) signal,
indicating that the RBI 1 is not to anticipate receipt of
another word. When the RHl1 does a write data transfer, it
normally makes sure that a word is available for transfer
before the next SYNC ClK from the drive. When LWRD is
generated, this operation is bypassed. LWRD is checked at
the trailing edge of DRIVE CLK and will disable OLT (data
late error).

multiplexers. The output feeds an internal bus (BUSI)
which is used to sum up data from all the registers and
prepares it for input to the Unibus drivers which drive
Unibus A.
6.5.3 Clear Logic
Zones D-3 and D-2 on BerD contains the logic for both
Unibuses which detem1ine when a Clear signal is generated.
BUSA INIT L or BUSA DC La L, when asserted, generates
INIT + DC LO L. The BUSA INIT L signal initializes the
RHII ~lfId the drive. The BUSA DC La L indicates no
power on the Unibus. INIT + DC La L creates MB INIT H
(Massbus initialize) which initializes the registers in the
drive. Thus, a no-power condition on the Unibus is
implemented to initialize the Massbus.

6.6 LOGIC DIAGRAM BeTF
This diagram contains the interrupt control logic to prepare
the Unibus to do an interrupt. The logic . . ontained herein is
similar to that on the M7821 Interrupt Control module
which can be found in the PDP-Ii Pen'pherals and

The three signals that follow generate CLR + GO CLR H
and CLR. GO CLR is used to clear the NPR logic, and CLR
is used to clear the RH 11 and the associated drives.
1.

INIT + DC La L - This signal is the OR of
BUSA initialize and DC LO L.

Interfacing Handbuok.
6.6.1 Interrupt Request
The interrupt control logic is initiated by INTR REO H
(interrupt request) and IE (1) H. The IE (Interrupt Enable)
bit is set by the programmer by loading a 1 in bit 6 of the
CSI register. This allows interrupts to occur upon completion of an operation or upon detecting an error condition
when INTR REO H is asserted.

GO CLR L - This signal is asserted when a data
transfer command is loaded with the GO bit in
the CS 1 register.

pc; CLR L - This signal is asserted by setting
the CLR bit in bit 05 of the CS2 register, and is
used to clear the RBIl and the drive registers.

6.6.2 Bus Request
With the above conditions satisfied, BUSA BR L is asserted
at the output of gate E65 in zone C4. The other input to
this gate is enabled because the SACK and BBSY flip-flops
are reset. The BUSA BR L signal is applied to a priority
jumper plug (zone D-6) configured at priority levelS. This
causes BUSA BR5 L to be asserted at the output of the
plug. The other BR outputs from the plug are unasserted at
this time. BUSA BR5 L causes a bus request on the Unibus.
When the processor is ready to allow the RH lIto become
bus master, it returns BG IN H (bus grant) shown in zone
C-8. This signal performs the following functions.

CLRB H is similar to the CLR H signal and is generated as a
result of BUSB INIT or BUSB DC La L. This signal does
not dear the RBI} registers as they are not connected to
Unibus B.
If data transfers are being performed on Unibus B when
CLRB is asserted, a DLT (data late error) is posted to
terminate the transfers.
On sheet BCTE the CLR + GO CLR H signal resets the WC,
DRWC OFLO, and DONE flip-flops.

6.5.4 Word Count Overflow
When the Word Count register overflows, the carry output
goes low and is applied to the we OFLO flip-flop as a
clock. The positive-going trailing edge of this signal clocks
the WC OFLO flip-flop set.
When the WC OFLO flip-flop is set and the last data
transfer is completed (trailing edge of DATA REQ),
flip-flop E74 is set, causing the DONE assertion which
indicates the completion of the data transfer on the Unibus.

6-12

It is applied as a clock to the GRANT tlip-flop.
The positive-going edge tries to clock GRANT
set. However, the set input to GRANT is
disabled by BBSY being reset and IE (I) Hand
INTR REO H being asserted. These conditions
hold the input to NAND gate E47, pin 2 low,
forcing the output high. The other input (pin I)
to the gate is from the BUSA NPR logic. With
no NPR request, pin 1 is held high. AND gate
E16 and inverter E64 which feed NAND gate

1.
E47 are designed to improve the Unibus
(Cant) latency. The jumper at the input to gate E16,
when cut, disabJes the circuit.
2.

The BG IN H signal is used to direct clear the
GRANT flip-flop when GRANT is negated.
However, at this time, note that the GRANT
flip-flop is still reset.

BG IN H also sets SACK 100 ns after the
G RANT is received. The 100 ns delay is provided by the external components at the input
to the 7408 AND gate in zone B-6. The delay
provides the required time for the GRANT
flip-flop to decide whether to block the grant
or pass it on to the next device. Note that the
set input to SACK is enabled as a result of the
Bus Grant signal and because the GRANT
flip-flop is still reset.

6.7 LOGIC DIAGRAM BCTH
This diagram contains the NPR control logic I~ecessary to
initiate NPR requests and to gain control of the Unibus in
order to do NPR cycles. The logic on this sheet is similar to
the logic contained on the M7821 Interrupt Control
module described in the PDP-}} Peripherals and Interfacing
Handbook.

6.7.1 NPR Arbitration
The logic is initiated by DATA REQ H being asserted at the
input to AND gate E15 (zone D-5). This signal is held
asserted during the entire cycle for single cycle NPRs or is
held asserted for both cycles when performing back-1 a-back
NPR cycles. The other input to the AND gate is CLR
DREQ L, wruch is normally held high during the cycle and
enables the gate. The output of this AND gate qualil1es
AND gate E25 (zone B-3). The other two inputs to this gate
are enabled by the SACK and BBSY flip-flops being reset.
The output of AND gate E25, pin 12 is supplied to two
gates (E33), (zone D-2) to raise an NPR request on the
Unibus which has been selected. This sheet will be
described assuming that Unibus A has been selected. In this
event, the BUSA NPR L signal is asserted on the Unibus.
The processor arbitrates the NPR requests and returns a
BUSA NPG IN H signal when it wishes to to grant the bus
to the RHll. The BUSA NPG IN II signal clocks the
GRANT A flip-flop, but the flip-flop does not set since the
three inputs to gate E7 (zone D-3) are rugh causing the
D-input to the flip-flop to remain low. Consequently, the
GRANT signal is blocked and is not passed to the other
devices. The BUSA NPG IN H signal is also applied to
mUltiplexer E26. Since Unibus A has been selected, the
multiplexer inputs at pins A3 through AO are present at the
output. If Unibus B is selected, the inputs at pins B3
through BO are present at the output. The BUSA NPG IN H
signal clocks the SACK flip-flop after 100 ns. Since
GRANT L is not asserted, the other input (pin 11) to E7 is
high and provides a low input to the SACK flip-flop causing
it to set. The 100 ns delay network consisting of the
resistor and capacitor network at the input to AND gate
E15 (zone C-5) ensures that the SACK flip-flop will not be
prematurely set until the GRANT signal has been blocked.
Setting the· SACK flip-flop causes the BUSA SACK L signal
to be asserted on the Unibus and also causes the RH II to
drop the BUSA NPR L signal. This acknowledges the fact
that the RH 11 has received the RUSA NPG IN I { signal
from the processor. SACK prevents the processor from
further arbitrating NPRs.
.

When the BG IN H Signal is unasserted and
SSYN IN Hand BBSY IN Hare unasserted
indicating completion of the current cycle,
BBSY is set. Note that the set input to BBSY is
enabled since SACK is set.

Consequently, the interrupt control logic is initiated, a bus
request is sent to the processor, a bus grant is returned from
the processor, and the SACK flip-flop is set after a 100 ns
delay. When the SACK flip-flop sets, the BUSA BR5 L
Signal goes unasserted and when the processor completes its
current cycle, BBSY is set indicating that the RHll has
control of the bus. When BBSY sets, the set input to the
GRANT flip-flop is enabled and the GRANT flip-flop will
be set by the next BG IN H signal. The grant will be passed
to the next device on the bus. In addition, setting BBSY
causes the SACK flip-flop to clear, and also generates INTR
MASTER L. This signal causes the BUSA INTR L signal on
Unibus A to be generated and also gates the 7-bit interrupt
vector to the Unibus. The vector is jumper selectable. If the
jumper is left in, the corresponding bit is a 1; if the jumper
is cut, the corresponding bit is a O.
6.6.3 Interrupt Done
When the processor has accepted the interrupt vector, it
returns SSYN IN H which generates INTR DONE H. Tins
signal clears the latch in zone C-7 which allows the
interrupt sequence to terminate. Also, INTR DONE H
clears BBSY to allow another device to gain control of the
bus.

6-13

6. i.2 Acquiring Bus Mastership
MUltiplexer E26 monitors BBSY and SSYN for the selected
Unibus (BUSA, in this case). When both BBSY and SSYN
from the device currently acting as bus master are unasserted, NOR gate E32 (zone B-6) is qualified. This enables
AND gate E15 (zonc B-5). The other input to this gate
qualifies the gatc when the processor drops BUSA NPG IN
H. The output of this gate clocks the BBSY flip-flop set
since SACK is still asserted. When BBSY sets, it asserts
BUSA BBSY L via gate E40 (zone B-2) and also asserts NPC
~1ASTER L, indic.lting that the RHII is now bus master.'
This initiates the sequencing logic for an NPR cycle (see
sheet DBC A). The 0 output of the BBSY flip-flop disqualines AND gate £25 (zone B-3) which keeps the RUSA NPR
L signal unasserted. Also, when SACK ENB Hand BBSY
(I) H are asserted, the SACK flip-flop is cleared.

Signal MB INIT H is also generated if the CLR bit in CS2 is
set by the program. This ca uses a PG CLR L signal to be
generated which fires 400 ns one-shot multivibrator E85
(zone D-6). The output of the one-shot is a 400 ns negative
pulse which is used to enable the other input to gate ER7 in
zone D-4.

If a device on Unibus B desires to become bus master prior
to the RHl1 acquiring bus mastership, the logic in the
RHII must pass the grant to the next device. The BUSB
NPG IN H signal clocks the GRANT B flip-flop set. Since
the SEL BUSB H signal is unasserted, the D-input to the
flip-flop is high and the flip-flop is set allowing the GRANT
signal to be passed to the next device. When the BUSB NPG
IN H signal is dropped by the processor, the clear input of
the GRANT B flip-flop is brought low, thus removing the
BUS NPG alIT signal to the next device.

6.8.3 MXF Error Flip-Flop
The lower portion of sheet BCT] shows the SET MXF and
MXF flip-flops and a 250 ms one~shot. When the RH II
goes into the busy state (RDY H not asserted), the 250 ms
one-shot (E85 in zone B-7) fires indicating that the RHII is
attached to the synchronous bus. The 250 ms one-shot is
retriggered on every SYNCCLK signal from the drive. If
the RHl1 is busy, and a SYNC CLK pulse docs not occur
within 250 ms, the trailing edge of the 250 ms pulse clocks
SET MXF flip-flop E86 (zone B-5) set which, in turn,
causes MXF flip-flop E86 (zone B-3) to be direct set.
Normally, the D-input to the SET MXF flip-nop is at
ground which allows the flip-flop to set. If jumper W19 is
cut, however, the high input applied to the D-input
prevents the flip-flop from setting. This jumper is used for
maintenance purposes. The MXF flip-flop can be set under
program control by setting bit 9 (MXF error) of the CS2
register and by generating the appropriate gating Signals (HI
BYTE H, REG STR H, and CS2 IN L).

6.7.3 Completion of NPR Cycle
The NPR cycle(s) is completed when CLR DREQ L is
asserted, causing AND gate E15 (zone D-S) to go low. This
action causes the NPR cycle to end and BBSY flip-flop to
reset, releasing the bus to the next device.

6.8 LOGIC DLAGRAM BCT]
This diagram contains the MB INIT logic, the logic used to
gate out the high byte of the CSI or the CS2 registers, and
the logic to set the (Missed Transfer Error) MXF flip-flop.

MB INIT Signal
When an initialize (INIT) signal or a power fail condition
(DC La L) occurs on Unibus A, a MB INIT H (Massbus
jnitialize signal) is generated and initializes all the drives.
Both INIT and DC La are guaranteed to be a minimum of
400 ns, and the assertion of either signal qualifies gate E87
(zone D-4) to produce MB INIT H.
6.8.1

6.8.2 Gating High Byte of CSl/CS2
The two 2-to-l multiplexers (E59 and E(0) in the center of
sheet BCTJ are used to gate out the high byte of the CS 1 or
CS2 register. CSl OUT L, when asserted, gates the high
byte of the cst register through the multiplexer and CS2
OUT L, when asserted, gates the high byte of the CS2
register through the multiplexer. The output of the
multiplexer is the internal data bus (BUSI) which feeds
Unibus A.

The 250 ms one-shot and the SET MXF flip-nop are direct
cleared by the CLR H signal, the BUSY flip-flop being in
the Reset state, or the OCC (occupied) line on the Massbus
being asserted. The MXF flip-flop is direct cleared by the
CLRERR L signal.
6.8.4 AC LO and DC LO
Power supply signals AC La and DC LO are actively pulled
up so that they may be used as inputs to the two M688
Power Fail Driver modules.

6-14

9 BCTK LOGIC DIAGRAM
le BCTK print provides the truth table for the register
lection ROM shown on sheet BCT A.
10 LOGIC DIAGRAM CSRA
1is logic diagram contains the data transfer command
gic. the RUN flip-flop, the BUSY flip-flop, the PSEL
lort select) flip-flop, the CSI clocking logic, and the
terrupt request logic.
10.1 Data Transfer Command Logic
le data transfer command logic consists of the Write,
ead, and Write-Check flip-flops (E3 pin 6, E15 pin 6, and
15 pin 8, respectively). These flip-flops decode the Write,
ead, or Write-check commands that are being passed
.rough the controller into the drive. The commands are
~coded in the RHll to let the RHII know what type of
)eration is to be implemented. In addition, these comands are also supplied to the drive where they are again
~coded in the drive's function register. All other comands are not decoded in the RHII but are merely
!coded in the drive.
f1e D-input to the Write flip-flop represents the range of
Inction codes that define the Write command. These codes
.nge from 60 through 67. The D-input to the Read
ip-flop represents the range of function codes that define
Read command. These codes range from 70 to 77. The
'-input to the Write-check flip-flop represents the function
)des that define a Write-check command. These codes
mge from 50 to 57. For example, the D-input to the Write
ip-flop is enabled when D03 IN L is unasserted and D04
I.J" Hand D05 IN H is asserted in gate E6 pin 12. This bit
attem corresponds to the digit 6, specifying function
)des from 60 through 67. The other flip-flops are decoded
1 like manner.
'he C-input to the flip-flop accepts the positive-going
railing edge of the GO CLR L signal to clock the flip-flop
pecified by the appropriate data bits which comprise the
llnction code. Signal GO CLR L is used to initialize the
,ilo and NPR logic for a data transfer, and is also used to
.irect set the BUSY flip-flop in zone B-6, indicating a data
ransfer command is in progress. Signal GO CLR L is
sserted at the output of NAND gate E17, pin 6 if CLK
:SI LO H, 000 IN H, and a data transfer command (Write,
tead, or Write-check) has been decoded by NAND gates E6
lin 12, E14 pin 12, or E14 pin 6. Signal CLK CSI LO H is

asserted when the program is loading data into the low byte
of the CSI register, and DOO IN H is asserted when the GO
bit is set by the program. As previously mentioned, the
write block code is 60 through 67. Since 000 IN H is
asserted to generate GO CLR L which. in turn, is used to
clock the data transfer flip-flops. the function l:odc for each
data transfer command consists of only the odd function
codes within the group. For example, the write function
codes are 61, 63, 65 and 67. The even codes do not start a
data transfer function since the GO bit (DOO IN H) must be
asserted.

The outputs of the data transfer flip-flops are applied to
various gates to generate signals for internal use. Gate E20,
pin 4 generates the Ready Signal when there is no Read,
Write or Write-check command being processed, meaning
that the RHII is capable of accepting a data transfer
command. This fact is reflected in bit 7 (RDY) of the CS 1
register. NAND gateEl, pin II generates WRITE L after
the function command has been loaded in the drive. This is
done for the following reason: When the Write command is
asserted, a DATA REQ signal is initiated, causing a memory
access on the Unibus. To prevent this access from occurring
when the RHII is trying to access a non-existent drive, the
WRITE flip-flop is ANDed with FCTN LOAD (1) L. Signal
FCTN LOAD (1) L inhibits the Write command from
initiating a memory access until the command has been
loaded into the drive. In this way, the memory cycle is not
performed for a non-existent drive. Should a non-existent
drive be accessed, an NED (non-existent drive) error is
raised which disables the DATA REQ signal from initiating
an NPR cycle. Inverter E13, pin 10 merely provides a
buffered output of the Read signal. Gate E5, pin 3 ORs the
output of the Read and Write-check flip-flops to create the
Read or Write-check Signal. Inverter E13, pin 12 buffers the
Write-check signal from the WR CHECK flip-flop. When the
data transfer is complete for a particular operation, the
appropriate data transfer flip-flop is cleared by gate E8, pin
3. This gate is asserted by BUSY (0) Hand DEV SEL L not
asserted or by CLR L being asserted. BUSY (0) H is
asserted when the BUSY flip-flop is cleared, indicating that
the RHll is no longer busy. This flip-flop is described in
subsequent paragraphs. The DEV SEL L signal is asserted
when the program is reading or writing a register and
prevents the program from looking at the ready bit during
the time the bit might be changing. When the data transfer
flip-flops are cleared, the RHII goes to the RDY state.

6-15'

trailing edge of EBL. If RUN is cleared 0
unasserted, the transfer is terminated. If RUN i:
asserted, the drive does the transfer for the nex
sector.

6.10.2 RUN Flip-Flop
In a write operation, the RHII transfers the Write
command to the function register in the drive and then
turns the drive on by setting the RUN flip-flop which
asserts the RUN signal. The drive seeks the address specified
by the program and starts accepting data words as a result
of the SYNC CLK Signals. Before the RUN Signal is
asserted, however, the RHII prefills the Silo with data
words so that data is available to the drive immediately.
This logic is implemented by NAND gate E19, pin 6 which
is enabled by WRITE H, START H, and OBUF FULL (1)
H. The START H signal is asserted when the number of
words specified by the start counter have been loaded in
the Silo. If only one or just a few words are to be
transferred, the RHll ensures that a word is in OBUF as a
result of OBUF FULL (1) H. In this case, the START H
signal is asserted as a result of WC OFLO (1) H and not due
to the start counter indication of words loaded in the Silo.
Note that it takes from 0 to 32 JIS for a word to propagate
from the bottom cell of the Silo to the top cell with a
typical time of 16 JIS. Because of this time delay, the logic
is designed to ensure that a word is in OBUF before the
RHII turns on the drive. The TRE (1) L input to gate E19,
pin 8, if asserted, also sets the RUN flip-flop. This is
necessary because the data transfer command has already
been loaded for writes when errors occur before the signal
ST ART in the RH 11 is asserted, and the only way to
terminate the operation is to set the RUN flip-flop and wait
for the end of the first block or sector (designated by EBL).
At this time, the error condition clears the RUN signal. On
the trailing-edge of the EBL (end-of-block) signal, the drive
looks at the cleared RUN signal and terminates its
operations.

If a data transfer command is to be loaded int<
a non-existent drive. This condition is imple
mented by FCTN LOAD (1) H and NED H vi:
NAND gate E9, pin 3.

If a clear (CLR L) or missed transfer signa
[MXF (1) L] occurs.

NOTE
The conditions described in 1, 2, 3 to
clear the RUN flip-flop are synchronized
to the drive. The conditions described in
4. and 5 are not synchronized to the drive
since there is no guarantee that a valid
drive has been accessed or that the drive
will respond.
6.1 0.3 BUSY Flip-Flop
The BUSY flip-flop is set during a data transfer commanl
and remains set until reset by one of the followini
situations:

In the case of a read or write-check operation, it is desired
to set the RUN signal immediately in order that the drive
can start filling up the Silo. This is accomplished by gate
E19, pin 8.

The RUN line, when cleared, disconnects the RHll from
the drive. This line is cleared under the following conditions:
1.

If an exception (EXCP L) occurs (sce gatc E27
pin 8). When the drive has an error it raises thl
EXCP line which clears RUN upon receipt a
the EBL signal. This indicates the end of thl
current sector. An exception is caused by an~
of the error conditions defined in the EF
register.

When drive word count overflow [DRWC
OFLO (1) LJ is asserted. This occurs when the
desired number of words have been transferred.

When the RHll is doing a data transfe
command, the BUSY flip-flop cannot bl
cleared and the operation cannot be terminate(
until both the Unibus and Massbus cycles havi
been completed. This is indicated by DONE (1
and EOS (1) applied to NAND gate E 1. Whel
both signals are asserted, the BUSY flip-flop i
cleared via gate E8 pin 8.
t

If an error exists in the RBI! and the drive has
asserted a SYNC CLOCK (SCLK). The logic is
implemented by inverter gate E9, pin 6, which
is enabled when an error occurs. In this
situation, the RUN flip-flop is direct cleared
and the drive looks at the RUN line on the

6-16

The CLR or MXF (1) signals which clear Rill
are also used to clear BUSY.

The BUSY flip-flop can be clocked clear by .
data transfer command being loaded into
non-existent drive. This is accomplished b~
NAND gate E9, pin 3, which is qualified b~
FeTN LOAD (1) H and NED H.

TRE, an ATTN signal from the drive, or MCPE
(Massbus Control Parity Error). The RDY H
signal ensures that the RHII is in the Ready
state before it initiates an interrupt. For
example, if a drive asserts ATIN while the
RHll is busy doing a data transfer with
another drive, the interrupt would not be
allowed to occur until the RH 11 has completed
the current data transfer and returned to the
Ready state.

6.1 0.4 Port Select Flip-Flop
The Port Select (PSEL) flip-flop in zone B-6 is a programmable bit which selects Unibus A or Unibus B. If the
flip-flop is set, Unibus B is selected~ if the flip-flop is
cleared, Unibus A is selected. The output of the PSEL
flip-flop feeds driver ES, pin 6 which generates the SEL
BUSA H signal used to control the data path for the
Unibus.
A second input to ES, pin 6 is a jumper which overrides the
PSEL bit. PSEL is set or cleared via CSl IN H, REG STR H
and HI BYTE H only when the .RH11 is in the Ready state.
This prevents changing of the data path during a data
transfer. These signals are asserted when the program is
loading the upper byte of the CSl register. With these
conditions asserted and the RHll in the Ready state, AND
gate Ell, pin 3 is qualified and clocks the PSEL flip-flop
set if D lOIN H is asserted.
6.10.5 CSt Clocking Logic
The CLK CSI HI Hand CLK CS1 LO H signals are
generated by AND gates E23, pin 6 and E23, pin 8,
respectively. These signals are clocking signals for the high
byte and the lo.w byte of the CS 1 register. Signals HI BYTE
H, REG STR H, and CSl H create CLK CSl HI H. Signals
LO BYTE H, REG STR H, and CSt H create CLK CSl LO

H.
6.10.6 Interrupt Requests
Interrupt requests are allowed to occur if the interrupt
facility is enabled. The facility is enabled by the program
loading a 1 in bit position 6 (interrupt enable bit) of the
CS 1 register. This sets the IE (Interrupt Enable) flip-flop
and generates IE (1) H. If an interrupt occurs (with the
interrupt enable set), the IE bit is cleared by INTR DONE
H which occurs when the processor has been interrupted,
has acknowledged the interrupt, and is preparing to execute
the' interrupt service routine. Signal INTR DONE II is
generated on sheet BCTF and clears the IE bit to prevent
interrupts from occurring while the service routine is being
executed. The IE bit can also be cleared by CLR L which
may occur during a Unibus initialize sequence, a power fail
assertion, or by setting program clear bit 5 on the CS2
register.

If the IE bit is set and the RHII changes from
the Busy to the Ready state, the INTR flip-flop
sets and generates INTR REQ H, indicating
completion of the data transfer and initiating
the interrupt.

The program can force an interrupt by loading
bits D06 H (IE) and D07 H (RDY) in the CSl
register which direct sets the INTR flip-flop.

6.11 LOGIC DIAGRAM CSRB
This diagram contains the logic associated with some of the
error conditions and status indicators.
6.11.1 CS2 Clocking Signals
The program loads data into the CS2 register by the CLK
CS2 HI Hand CLK CS2 LO H signals. CLK CS2 HI H
causes the program to load data into the high byte of the
CS2 register, and CLK CS2 LO H causes the program to
load data into the low byte of the register. REG STR Hand
CS2 IN H are enable signals to AND gates E27, pin 6 and
E27, pin 12. Signal CLK CS 2 HI H is qualified by the HI
BYTE II signal, and CLK CS2 LO H is qualified by the LO
BYTE H signal.
6.11.2 Program Clear Bit
The program clear bit (PG CLR L) is set when the program
loads a 1 in bit 5 of the CS2 register and CLK CS2 LO H is
asserted, indicating that the program is loading the low byte
of the CS2 register. PG CLR L is an input which generates
the CLR portion (see sheet BCTD) of the CLR + GO CLR
L signal and also generates MB INIT (see BCTJ). The CLR
signal initializes the RHll and MB INIT initializes the
drive.

The interrupt facility is enabled by the IE bit. However, the
interrupt occurs as a result of the INTR REQ signal being
asserted. Interrupts can occur as a result of one of the
following conditions:
1.

6.11.3 Bus Address Increment Inhibit
The Bus Address Increment Inhibit (BAI) flip-flop, when
set, prevents the Bus Address register on the BCT module
from incrementing when doing NPR cycles. Consequently,
all memory references are made to or from the same
memory location. The BAI bit can only be changed if the

If SC (special condition) and RDY Hare
asserted, the INTR REQ II signal is generated
to initiate an interrupt. SC occurs as a result of

6-17

The errors are also cleared by loading a 1 in the TRE bi
position in bit 14 of the CSl register. This is accomplishec
by NAND gate E2, pin 3 in zone B-7. Consequently
loading a 1 in the TRE bit position clears out any error il
the RBl1. This is done so the error conditions in the RHl
can be cleared without having to clear the error condition
in the drive.

RHII is in the Ready state. The CLK CS2 LO Hand RDY
Hare ANDed to clock the BAI flip-flop which represents
hit 3 of the CS2 register.
6.11.4 Unit Select Number
The unit numbers are unit 0 through 2 of the CS2 register
and are designated UOO through V02 H. These three bits are
loaded by the program and used on the Massbus to select
one of eight drives, and are generated by data bits D02 IN
H through DOD IN H which are applied to three of four
flip-flops contained on IC E21.

6.11.8 Transfer Error
The TRE (transfer error) flip-flop (zone B-6) is a summa
tion of all the error conditions in the controller and th
drive. These include Data Late Error (DLT)~ Massbus Dat
Parity Error (SYNC PE), Exception (summation of all erro
conditions in the ER register), Write~Check Error (WeE]
Unibus Parity Error (UPE) , Non-Existent Drive (NED)
Non-Existent Memory (NEM), Program Error (PGE)~ ani
Missed Transfer Error (MXF). Anyone of these condition
enables gate E22, pin 8 and clocks the TRE tlip~tlop se1
TRE is bit 14 of the CSl register. TRE (0) H is ORed witl
ATIN and CNTL PE (MCPE) to create SC H, which is bi
15 of the CS 1 register. Bits 14 and 15 are coded to inforn
the programmer of the type of error and where it occurred
Whenever the SC bit is set, this indicates that an error ha
occurred from some drive doing a data transfer comman~
or that a drive has finished some movement command sud
as a Seek. By then examining the TRE bit, the programme
can determine additional information. If TRE is set, thi
indicates that a data transfer error has occurred. If TRE i
not set, this indicates that:

6.11.5 Parity Test Mode
A parity test mode is provided for maintenance purposes.
This is implemented as PAT (bit 4 of the CS2 REG) and
may be set or cleared by the program. When set, the parity
logic associated with the Massbus in the RB11 is switched
from odd parity to even parity generation.
6.11.6 Function Load
The use of the Function Load flip-flop is described on logic
diagram CSRA. The flip-flop is set when a data transfer
command (Read, Write or Write-check) is being loaded in
the CSI register. The C-input to the flip-flop i;'clocked by
GO CLR L which is asserted when a data transfer command
is specified, the clocking signal for the CS1 is asserted, and
the GO bit is set. The flip-flop remains set until the bus
cycle being used to load that command is completed. At
this time, the master drops MSYN and the DEV SEL L
signal goes lU1asserted to clear the Function Load flip~flop.
The Function Load Signal is used to delay the Write signal
from being asserted until the function has been loaded in
the drive (see sheet CSRA), and is also used to clear the
RUN flip-flop when a function command is being loaded
into a non-existent drive (see sheet CSRA).
6.11.7 Non-Existent Drive
The Non-Existent Drive (NED) error is generated at the
output of a latch circuit consisting of gates E9, pin 8 and
E9, pin 11. Signal NED H is asserted when SET NED L is
asserted, and SET NED L is asserted 1.5 J.LS after DEMAND
is asserted on the Massbus and no transfer response
occurred. Thus, if no response was received from a drive
1.5 J.LS after the assertion of DEMAND and the register
being addressed was not the Attention Summary register,
then a non-existent drive has been addressed. Signal NED
H is cleared by CLR ERR L. This CLR ERR L signal clears
all the error conditions, and is generated by CLR + GO
CLR L. Signal CLR occurs as a result of power fail, Unibus
initialize, or program clear. Signal GO CLR L is asserted by
setting the GO bit during a data transfer command.

an error has occurred in some drive not doing:
data transfer command,

the drive has completed some operation whic1
is not a data transfer command, or

a Massbus Control Parity Error was detecte(
when the program read information from :
drive register.

The programmer can then ascertain which drive has cause
the SC H Signal by referring to the Attention Summar
register which shows the ATTN condition of each drive c
if MCPE occurred (bit 13 of CSl). ATTN is raised by
drive when an error occurs or when it has finished som
operation other than a data transfer command. Completio
of data transfer commands are indicated to the programme
by the condition of the RDY bit.

6-18

6.11.9 Program Error Flip-Flop
The Program Error (PGE) flip-flop in zone C-5 is set when
the programmer tries to load a data transfer command
while the RH 11 is in process of doing a data transfer. Signal
GO H is asserted indicating that a data transfer command is
being loaded; if the RH 11 is busy, RDY H is low which
causes the PGE flip-flop to set creating PGE (1) H. This
signal is applied to NAND gate E6, pin 6 and generates a
STOP DEM L signal which is applied to the BCT module
and prevents the DEMAND signal from going out on the
Massbus and actually loading the data transfer command
into a drive. The PGE (1) H signal also creates the TRE
condition (zone B-6). The PGE flip-flop is direct cleared by
CLR L or CLR TRE L.

6.12 LOGIC DIAGRAM DBCA
This diagram contains the logic necessary to transfer data
between the RHl1 and memory over the PDP-II Unibus.
When the RHl1 asserts a DATA REQ, the following events
occur:

6.11.10 End of Sector (EOS) Flip-Flop
An EBL pulse occurs at the end of every record and
indicates that the operation is to be terminated.

The RHll must monitor the RUN line in order to know
when the drive has reached the end of the record.
Otherwise, the RHl1 might return to the Ready state
before the drive has completed the operation. The EOS
flip-flop in the RHII monitors the RUN line at the trailing
edge of EBL. Signal EOS (0) H prevents the BUSY flip-flop
(sheet CSRA) from clearing. At the trailing edge of EBL,
the EOS flip-flop is set, thus allowing the BUSY flip-flop to
clear and pennitting the RHll to return to the Ready state
as long as the last word on the Unibus has been transferred
(DONE is asserted). Remember that the Unibus transfer as
well as the Massbus transfer must be complete to return the
RHll to the Ready state.

6.11.11 Unibus Parity Error (UPE) Flip-Flop
The Unibus Parity Error (UPE) flip-flop is direct set by a
parity error on the Unibus as defined by the states of the
PA (D 16) and PB (D 17) bits (see sheet D BCH). The UPE
flip-flop can be set by the programmer by writing a 1 in bit
poSition 13 of the CS2 and clocking the UPE flip-flop with
CLK CS2 HI H which clocks the high byte of the CS2
register. Signal UPE (1) H causes TRE and the programmer
can ensure proper operation of the UPE flip-flop by writing
a 1 in .bit 13 and checking to see if TRE occurs.

The RHll asserts an NPR request (see sheet
BCTH).

The processor arbitrates the NPR requests and
issues NPG to the RHl1. This indicates that the
RHll is the next device to become bus master.

The RHll acknowledges receipt of the grant by
issuing SACK (selection acknowledge), which
drops the NPG signal.

The RHll waits for BBSY and SSYN to clear,
indicating that the device currently using the
Unibus has finished its cycle.

When BBSY and SSYN clear, the RHll asserts
BBSY and NPC MASTER.

The RHll places address and control information on the Unibus (and data if a Read
command is specified).

After 200 ns, the RHll issues MSYN since it is
now bus master.

If a Read command is specified, the slave device
returns SSYN upon receipt of the data. If a
Write or Write-check command is specified, the
data from the slave is deskewed 125 ns after
SSYN is returned before it is used in the RHl1.

MSYN is cleared which, in turn, causes the slave
device to clear SSYN. If a single NPR cycle is
being performed, BBSY is cleared 100 ns after
MSYN is cleared. If a back-to-back NPR cycle is
being performed, BBSY is cleared 75 ns after
MSYN clears on the second cycle.

10.

When BBSY is cleared, the NPR cycle is
finished until a new DATA REQ is issued to
initiate the next cycle.

The logic to accomplish the above events is contained on
sheets BCTH (previously described) and DBCA. The following description covers sheet DBCA.

6-19

6.12.) NPC MASTER Signal
When NPC MASTER is asserted, ADDR TO BUS H is
asserted. In addition, the NPC MASTER signal enables gates
E84 and E96 (zone D-6). When a Read command is
specified, these gates are qualified to -yield both polarities
of the DATA TO BUS signal used to gate data onto the
Unibus. The gates are connected in parallel to avoid the
delay normally required in going through an inverter.

MSYN Deskew. Cl is asserted low by ADDR
TO BUS H when a Read command is specified.
This designates a DATO operation (data written
into memory). If C1 is unasserted (no Read
command specified), a DATI operation is performed.
NOTE
The CO control line specifies a DATOB or
DA TIP operation. Since the RH 11 does
neither operation, the CO line is not
required and remains unasserted.

6.12.2 ADDR TO BUS Signal
The ADDR TO BUS signal, generated at the output of E89,
pin 10, accomplishes the following functions:
1.

ADDR TO BUS triggers one-shot multivibrator
E92 (zone C-5). In the first memory cycle,
END CYCLE (1) H is unasserted, thus enabling
. gate E89. The assertion of ADDR TO BUS
triggers the one-shot (the function of the
one-shot is described in subsequent paragraphs).
At the end of the first memory cycle, END
CYCLE (1) H is asserted disqualifying E89.
When END CYCLE (1) H goes low, it produces
a positive-going pulse at E89, pin 10 which
triggers the one-shot for the second memory
cycle. Consequently, the one-shot is triggered
by NPC MASTER in the first memory cycle
and by the assertion and subsequent unassertion of END CYCLE (1) H in the second
memory cycle.

ADDR TO BUS H is the enable signal which
gates the address onto the selected Unibus. The
leading edge of END CYCLE (1) H causes the
trailing edge of ADDR TO BUS H which
increments the Bus Address register. During the
width of the END CYCLE pulse, the address in
the address register is stabilized. At the trailing
edge of END CYCLE, one-shot E92 is again
triggered.

ADDR TO BUS is also applied to gate E89 and
gate E90 (zone D-2). The other input to those
gates is SEL BUSA, which selects the appropriate Unibus. If SEL BUSA is asserted, Unibus A
is selected; otherwise Unibus B is selected. E89
and E90 enable the drivers shown in zone Cl
and Dl to generate MSYN and CI signals for
the appropriate Unibus (RUSA or BUSB).
MSYN is asserted by ADDR TO BUS H when
the MSYN flip-flop is set. The setting of this
flip-flop is described in the paragraph entitled

6.12.3 MSYN DESKEW
The ADDR TO BUS H signal triggers one-shot muitivibrator
E92 as previously mentioned. This one-shot provides a
200 ns deskew for MSYN to allow the address and control
lines time to stabilize on the Unibus.
NOTE
Gate E90 (zone C-6) is used during a Read
command to lock the Silo timing to the Unibus
timing and ensures that data will be deskewed
for the proper interval before MSYN is set on
the second cycle of back-to-back NPR
sequences.
The positive-going trailing edge of the 200 ns pulse from
pin 4 of E92 clocks DESK COMPL flip-flop E93 (zone
C-4), indicating that the deskew is completed. This enables
one input to gate E69 (zone C-3). The other inputs to this
gate represent inhibit conditions to prevent MSYN flip-flop
E93 (zone C-3) from setting. These inhibit conditions are
described in the paragraph entitled MSYN Inhibit Conditions. If none of the inhibit conditions are present, and the
Silo and Unibus signals are in the proper state, MSYN is set,
and is ANDed with the appropriate Unibus select signal
(zone D-l) to generate BUSA MSYN Lor BUSB MSYN L.

6.12.4 MSYN Inhibit Conditions
In the second cycle of back-to-back NPRs or in BUS HOG
mode (described in subsequent paragraphs), there are
several conditions used to inhibit MSYN. These conditions
are ORed in gate E69 (zone C-3). The purpose of these
inhibits is to lock the data transfer rate to the Silo data
rate. The inhibit conditions are listed below:

6-20

The RBI1 cannot assert MSYN for the current
cycle until NPC SSYN from the previous cycle
has been cleared.

In a write function, the RH 11 does not assert
MSYN until it is certain that IBUF is empty
and available to receive the data from the
Unibus. If IBUF is full, E69 gate is disabled and
inhibits MSYN until IBUF is cleared.

In a write-check function, the RHl1 does not
fetch a word from memory until it is sure that
the word from the drive is in OBUF. When
OBUF is not full, OBUF FULL (0) H is asserted
which disqualifies gate E69 and prevents MSYN
from setting until OBUF is full.

The fourth inhibit condition occurs during a
Read command when the RHll is doing the
second NPR cycle of back-to-back NPRs or is in
BUS HOG mode. In this instance, the RBll
does not initiate MSYN deskew until it is
assured that a data word is available in OBUF.
At this time, then, the data and address can be
deskewed from MSYN to allow time for the
data and address to stabilize on the Unibus.
This inhibit condition is implemented in AND
gate E90 (zone C-6). If OBUF is full, OBUF
FULL (0) H goes low and allows 200 ns
one-shot E92 to be triggered. If OBUF is not
full, this gate inhibits the one-shot from firing.

are in accordance with Unibus specifications and 50 ns is
the propagation time for the data to be supplied to IBUF
from the Unibus in a write cycle. In a write-check cycle, it
provides the propagation time for this data to be compared
with the device data in 0 BUF. The D AT A WAIT one -shot
is triggered by NPC SSYN, or in its absence, a non-existent
memory error when the RH 11 is bus master (NPC
MASTER H asserted), MSYN has been issued, and a write
or write-check operation has been designated. The
negative-going trailing edge of the DATA WAIT one-shot
triggers the MSYN WAIT one-shot which initiates a 75 ns
pulse. At the end of 75 ns, the positive-going output from
E95, pin 4 triggers 200 ns END CYCLE one-shot (zone
B-2). END CYCLE (1) H inhibits the ADDR TO BUS Signal
and retriggers the NPR control logic if a second cycle is to
be performed or clears BBSY if it is the last cycle of the
NPR sequence. During the 75 ns interval between the firing
of MSYN WAIT and the firing of the END CYCLE
one-shot, the RHll has cleared MSYN and must hold the
address and BBSY asserted.
The MSYN WAIT one-shot accomplishes the following
functions:

6.1 2.s MSYN Timeout
The MSYN (1) H Signal is applied to NEM flip-flop E85
(zone B-6) and to 10 J.lS one-shot multivibrator E83 (zone
8-6). The 10 J.ls one-shot measures the time it takes for
SSYN to respond. If SSYN does not respond within 10 p.s,
the positive-going trailing edge at pin 4 of E83 clocks the
NEM flip-flop set, denoting a non-existent memory. This
sets bit 11 in the CS2 register to flag the programmer and
also raises the TRE bit in the CSI register. If SSYN does
respond within 10 J.lS after MSYN is issued, it direct clears
the 10 J.lS one-shot and the NEM flip-flop via gate E80, pin
3. The CLR ERR signal is used by the programmer to clear
the NEM flip-flop after it has been set by the timeout
circuitry.

Clears the MSYN flip-flop via OR gate E80
(zone C-3).

Is fed to CYCLE COUNT flip-flop E85 (zone
B-3) and NEXT CYCLE flip-flop E36 (zone
B-2). The CYCLE COUNT flip-flop determines
whether the cycle is the first or second cycle of
back-to-back NPRs. The NEXT CYCLE flipflop determines whether a second memory
cycle is to be performed in the NPR sequence.

Generates DATA STR H which is used to clock
data into IBUF or to change data in OBUF.

If a Read command is specified (writing a data word into
memory), the data does not have to be deskewed when
NPC SSYN is received. However, MSYN must be cleared.
Prior to the receipt of NPC SSYN, all inputs to NAND gate
E94 (zone B-4) are high, forcing the output low. Upon
receipt of NPC SSYN, pin 9 of E94 is driven low, forcing
the output high. The positive-going output triggers the
MSYN WAIT one-shot which clears MSYN. Consequently,
in the case of a Write or Write-check command, both the
DATA WAIT and MSYN WAIT one-shots are fired. In the
case of a Read command, the data does not need to be
deskewed and the DATA WAIT one-shot is bypassed.

6.12.6 DATA WAIT and MSYN WAIT One-Shot
Multivibrators
The DATA WAIT one-shot is shown in zone B-5, and the
MSYN WAIT one-shot is shown in zone B-3. The DATA
WAIT one-shot is used during a Write or Write-Check
command (READ L unasserted) and provides a 125 ns
pulse to deskew the data from SSYN. Of the 125ns, 75 ns

6-21

6.12.7 CYCLE COUNT and NEXT CYCLE Flip-Flops
The CYCLE COUNT flip-flop is shown in zone B4 and
determines whether the RHII is doing the first or second
cycle of back-to-back NPRs. Initially, NPC MASTER H is
not asserted which causes CYCLE COUNT to direct set.
Near the end of the first cycle, MSYN WAIT is triggered
which toggles CYCLE COUNT. The low (0) output of the
flip-flop is fed through gates E98 and E97. As a result of
the double inversion, the D-input is low which causes the
flip-flop to reset. Assume that the RHll is not in BUS
HOG mode (pin 10 of E98 asserted high), there is no TRE
error (pin 5 of E97 asserted high), and word count
overflow, exception stop, or non-existent memory is not
holding the flip-flop direct set. The RHII monitors the
flip-flop at END CYCLE time. Since CYCLE COUNT is
reset, it indicates the first NPR cycle is being performed.
The second MSYN WAIT signal toggles the CYCLE COUNT
flip-flop again. Since the flip-flop was reset, the high output
from pin 6 is reflected as a high level at the D-input. This
action causes the flip-flop to set, indicating the second NPR
cycle is being performed.

BBSY to clear. NEM (Non-Existent Memory), if assert
keeps the CYCLE COUNT flip-flop direct set so
flip-flop cannot toggle. A TRE error, if asserted, keeps
data input high to prevent the CYCLE COUNT tlip-f
from toggling.
6.12.9 I-Cycle Jumper
If the RHll is to do single NPR cycles, a jumper designal
"1 CYCLE" and located in zone B-5 is inserted. This pIa
a steady high level at the data input to the CYCLE COUl
flip-flop. causing single memory cycle NPR sequences
always be performed.
The SACK ENB H Signal is always asserted at the output
gate E96, pin 8. This signal allows the SACK flip-flop to
cleared when the RHll becomes bus master and alto
NPR arbitration to occur on the Unibus.
6.12.10 BUS HOG Mode
In BUS HOG mode, the RBIl desires to hold onto tJ
Unibus to transfer the total number of words indicated
the word counter. This feature is only employed on Unib:
B if this bus is dedicated and no other devices a
connected to it. Its purpose is to reduct the NPR latem
time of the Unibus. The RHll enters BUS HOG mode t
doing the first NPR cycle and holding the Unibus b
asserting BBSY until the required number of words ha,
been transferred or an error condition occurs.

Whenever the CYCLE COUNT flip-flop is set, gates E71
(zone A-I) and E97 (zone B-2) are enabled. At END
CYCLE time, therefore, gate E96 (zone B-1) is enabled to
assert CLR BBSY L. This indicates that the RHll has
completed the second cycle of back-to-back NPRs or
desires to tenninate after the first cycle.
If the RHI I is in BUS HOG mode or if a TRE (Transfer
Error) occurs, the CYCLE COUNT is prevented from
toggling because a high level is presented at the data input.

The MSYN inhibit conditions (Paragraph 5.l2.4) locks th
Unibus cycle timing with the Silo buffer word rate.

The NEXT CYCLE flip-flop determines whether a second
memory cycle is to be performed in the NPR sequence. If
the NEXT CYCLE signa] is asserted, a second cycle is
desired, and the reset output of the NEXT CYCLE flip-flop
goes low which inhibits the clearing of BBSY. The NEXT
signal indicates the availability of a data word in the Silo
indicated by Input Ready or Output Ready (depending on
the function performed). If the NEXT Signal is not asserted,
indicating a second cycle is not desired, the reset output of
NEXT CYCLE goes high enabling gates E97 and E96 (zone
B-2). At END CYCLE time, E96 is qualified and BBSY is
cleared terminating the transfer.

To implement BUS HOG mode, the jumper in zone 0-2 i
cut which enables gate E98. If Unibus B is selected, the gat
is qualified, and BUS HOG L is asserted. This signal force
the NEXT CYCLE flip-flop set, indicating another cycle i
to be performed. With this flip-flop set, CLR BBSY L j
inhibited (except if a UPE or WCE error is raised at ENI
CYCLE time). In addition, BUS HOG L is applied to gatl
E98, causing a low input to be applied to the O-input of th~
CYCLE COUNT flip-flop. This overrides the toggling actior
from pin 6 of the CYCLE COUNT flip-flop and prevent:
the flip-flop from counting cycles. However, it still allow!
errors (TRE) or word count overflow to terminate th€
cycle.

6.12.8 ERROR Conditions
The error conditions in the RHII can also cause a cycle to
. terminate. The UPE (Unibus Parity Error) and WCE
(Write-Check Error), if asserted at END CYCLE time, cause

NOTE
The "1 CYCLE" jumper must not be inserted
and BUSB must be selected to implement the
BUS HOG mode of operation.

6-22

6.13 lOGIC DIAGRAM DBCB
This diagram contains the logic used to transfer data into
IBUF and from IBUF into the Silo (Silo input logic). Also,
the diagram contains the logic used to clock data out of the
Silo and into OBUF (Silo output logic).
6.13. t Silo Input logic
Data is supplied to IBUF as a result of one of the following
conditions:
a.

During a Write command - In this case, WRITE
Hand MSYN WAIT (1) H are asserted which
qualifies gate E72, and causes the output of
E72, pin 11 to go high for 75 ns. The effect of
this is described in subsequent paragraphs.
Signal MSYN WAIT ( 1) H is a 75 ns pulse
which occurs during every Unibus cycle. The
positive-going leading edge of this pulse is used
to clock data off the Unibus during a Write
(WRITE H) command. The da ta is transferred
to IBUF, bubbled through the Silo into OBUF,
and is written on the drive.
During a read or write-check operation - In a
read operation, the synchronous data from the
Massbus is clocked into IBUF, bubbled through
the Silo into OBUF, and then to the Unibus. In
a write-check operation, the synchronous
Massbus data is clocked into IBUF, bubbled
through the Silo into OBUF, and then to a
series of Exclusive-OR gates where it is compared to the corresponding memory iocation
from which it was written. The READ + WR
CHK H signal is asserted during a read or
write-check operation and is ANDed with
150 ns pulse in gate E77 to initiate this action.
The 150 ns pulse is p~oduced by one-shot
multivibrator E58 which is triggered by the
positive-going trailing edge of DRIVE CLK H
signal (zone 0-7). Also, when an exception
condition is detected (error condition in the
device), a special stop word is inserted into the
Silo to allow all previous data words in the
buffer to be transferred before signaling the
RDY state. The positive-going trailing edge of
EXCP L, which is an exception condition at
EBL time, will fire the 150 ns one-shot. Either
of these two conditions mentioned above will
cause E72, pin 11 to go high for 150 ns.

When the program is loading data in the
Silo - This function is used during maintenance
and allows the data buffer to be read from or
written into by the program. To accomplish
this, REG STR H and DB IN H are both
asserted. When this occurs, both inputs to the
lower AND gate of E77 are high which cause
the output of gate E72, pin 1] to go high for
125 ns. The REG STR Signal allows the RHll
or one of the device registers to be written into.
In this case, the register specified is the data
buffer as designated by the DB IN H signal.
Consequently, the three situations described
above cause the output of E72, pin 11 to go
high for 75 to 150 ns, depending on the
condition causing the output. This pulse is
designated ClK IBUF H and clocks the data
from the data lines into IBUF. IBUF is shown
on logic diagrams DBCC and DBCD. The
output of E72, pin 11 also direct sets the IBUF
FULL flip-flop via inverter E82, pin 10.
When the trailing edge from E82, pin 10 goes
positive (75 to 150 ns after the negative-going
leading edge), the BUBBLE IN flip-flop is set.
The width of the pulse at the output of E72 is
sufficient to guarantee that the data is clocked
into IBUF and has adequate time to be clocked
into the Silo. In other words, the pulse width
ensures that the data has time to be propagated
through IBUF.

When the BUBBLE IN flip-flop sets and the Input Ready
signals (IRS through IRl) are asserted, a SHIFT IN H signal
is generated which allows the data to be shifted into the
Silo (see gate E78, pin 4). Signals IRS through IRI
originate from the five parallel ICs which comprise the
IS-bit data word. When IRS through IRI is asserted, it
means that the Silo is ready to accept data from IBUF. The
Input Ready signals are guaranteed to have a certain width
to comply with the specification of the Silo.
When the Input Ready signals are no longer asserted, the
output of E62, pin S goes high and clocks the IBUF FULL
flip-flop clear since the data has been accepted by the Silo.
The output of IBUF FULL, in turn, clears the BUBBLE IN
flip-flop. The Input Ready signals, when not asserted,

6-23

indicate that the data need not be stored any longer in
IBUF and sufficient time has ensued to strobe the data into
the Silo. After the data has bubbled out of the first cell in
the Silo, the Input Ready signals once again are asserted.
Consequently, these signals are asserted when an empty
data cell exists at the bottom of the Silo buffer. This timing
sequence of INPUT RDY and the movement of data in the
Silo is all accomplished in the 3341 Silo IC.

issues~n initialize pulse or a power fail occurs
on Unibus B, a CLRB H Signal is asserted and is
applied to gate E79. The other two inputs to
NAND gate E79 are SEL BUS A L (which
indicates BUS B is selected when unasserted)
and RDY L (which indicates that the RH 11 is
busy when unasserted). If all three inputs are
asserted, the DLT IN flip-flop is set, causing a
DLT error to be asserted.

NOTE
The time required for a data word to propagate
from the bottom cell to the top cell in the Silo
is specified from 0 to 32 IlS. For an empty Silo,
the typical time is 16 IlS but may vary between
Silos due to internal characteristics.

The DLT error, in this case, does not mean that
IBUF is full and cannot accept another word
but does mean that additional transfers cannot
be done due to the power fail or initialize
condition.

DLTIN
When inputting data to the Silo, a DLT (data late) error can
be raised in one of the following two instances:

If a word is stored in IBUF [IBUF FULL (1)
H] and a second word is to be loaded from the
Massbus into IBUF during a Read or Writecheck command, the DLT IN flip-flop is set.
The READ + WR CHK Signal is ANDed with a
150 ns pulse derived from DRIVE CLK (or
EXCP for the stop word case) and is applied to
the clock input of DLT IN. The data input
monitors the IBUF FULL flip-flop and, if IBUF
is full, DLT IN is set. The 0 output of DLT IN
causes DLT to be created at the output of E72,
pin 8. This condition would occur if the Unibus
latency time is increased to the point where the
Unibus cannot accept data from the Silo at a
fast enough rate.

A maintenance feature is provided in the DLT
logic. The program can load 66 words in the DB
register, thus filling IBUF, the Silo, and OBUF.
The next word that is loaded in IBUF simulates
a DLT error which is posted in bit 15 of CS2.
This condition is implemented by DB IN Hand
REG STR H signals being asserted which cause
the DLT IN flip-flop to be clocked to a 1 when
IBUF FULL is asserted. As a result, a DLT
error at E72, pin 8 is raised.

6.13.2 Silo Output Logic
The Silo output logic clocks data words out of the Silo and
loads them in OBUF, where they can be transferred to the
Unibus (Read command), to the drive (Write command), or
to the Exclusive-OR gates in the controller (Write-check).
The output ready signals from each of the five parallel Silo
chips are asserted when a data word bubbles to the top cell
in the Silo. The output of gate E59, pin 8 is driven low
when the output ready signals are asserted. This action
causes ORDY H to be asserted at the output of inverter
E61, pin 8, indicating a word has bubbled to the top of the
Silo. In addition, a SHIFT OUT H signal is asserted
proVided BUBBLE OUT flip-flop is set. When OBUF is
empty, the OBUF FULL flip-flop is cleared which sets the
BUBBLE OUT flip-flop which, in turn, qualifies gate E78,
pin 1 to enable SHIFT OUT H to be developed. The SHIFT
OUT H signal is applied to the Silo and causes the word in
the top cell to be transferred out of the Silo. In addition,
the SHIFT OUT Signal fires one-shot multivibrator E58, pin
4 which creates a 45 ns negative-going pulse used to deskew
the data at the output of the Silo before it is loaded into
OBUF. The positive-going trailing edge of the SHIFT OUT
signal fires one-shot multivibrator E70. The negative-going
edge from E70, pin 4 creates a second 45 ns pulse which is
used to generate CLK OBUF H. CLK OBUF H loads the
data word from the Silo into OBUF. The positive-going
pulse from the 1 side of E70 generates SET OFULL L if
EXC STOP has not been asserted. The SET OFULL L Signal
direct sets the OBUF FULL flip-flop, indicating that OBUF
is presently storing a valid data word.
NOTE

A third condition causes the DLT IN flip-flop

If OBUF is full, the OBUF FULL flip-flop is set

to set when performing any of the data transfer
commands over BUSB. If NPR transfers are
being done on Unibus B and the processor

and the BUBBLE OUT flip-flop is cleared. This
condition inhibits the SHIFT OUT signal from
clocking the top cell in the Silo.

6-24

Exclusive-OR gates in the controller. In this
instance, READ + WR CHK Hand DATA
STROBE are applied to gate E76. Signal READ
+ WR CHK H, when asserted, denotes a read or
write-check operation; signal DATA STROBE
H, when asserted, drives the output of E76, pin
6 low. When DATA STROBE H goes unasserted, E76, pin 6 is driven high, clocking the
OBUF FULL flip-flop clear and allowing the
RHl1 to change the data on the Unibus. If
WCE (Write-Check Error) is detected, the data
word in OBUF is frozen by forcing gate E76,
pin 6 low which keeps the clock input to OBUF
FULL low.
.

When the Output Ready signal becomes unasserted due to
one of the five parallel Silo chips responding to the SHIFT
OUT signal, gate E59, pin 8 is driven high. As a result, the
SHIFT OUT signal is terminated and the BUBBLE OUT
signal is cleared because OBUF FULL has been set and has
removed the direct set on the BUBBLE 'OUT flip-flop. The
purpose of the BUBBLE OUT flip-flop is to enable the
completion of the SHIFT OUT signal after data has been
clocked into OBUF and OBUF FULL has been set. When
the next word bubbles to the top of the Silo, the word will
not be clocked into OBUF since the BUBBLE OUT
flip-flop is clear which inhibits the SHIFT OUT signal from
shifting the word out of the Silo ..
Consequently, the OBUF FULL flip-flop must be cleared in
order that the BUBBLE OUT flip-flop becomes set and
allows SHIFT OUT pulses. When this occurs, the data in
OBUF is automatically written over by the next data word
bubbling out of the top of the Silo. The OBUF FULL
flip-flop can be cleared under the following conditions:
a.

When the program is reading the Data Buffer
register. After the program reads the data
buffer, the next data word is allowed to
sequence to the top. This logic is shown in
NAND gate E75, pin 6. The DB OUT H signal
occurs when the data buffer is read, and the DB
OCLK H signal occurs when the RB 11 asserts
SSYN for that register operation. When the
master device removes MSYN and the RBI1 is
deselected, the DB OCLK signal is unasserted,
causing a positive-going edge at the clock input
to OBUF FULL. This indicates that the RBl1
does not have to store the data any longer and
OBUF FULL is clear.
When the RBII is doing a write operation
(memory-to-drive transfer). This condition is
implemented by the WRITE H and DRIVE
CLK H signals at the input to NAND gate E75,
pin 3. Signal WRITE H denotes a write operation. Upon the assertion of DRIVE CLK H,
NAND gate E74, pin 3 goes low and the drive
clocks the data off the Massbus.
On the trailing edge of DRIVE CLK, E75, pin 3
goes high to clock the OBUF FULL flip-flop
clear, and allows the RHII to change the data
on the Massbus.

When the RHII is doing a read (drive-tomemory transfer) or write-check operation
where the output of OBUF is applied to the

DLT OUT Flip-Flop
DLT OUT flip-flop E73 is shown in zone D-2. This flip-flop
is clocked by OUT CLK L which goes positive on the
trailing edge of DRIVE CLK during a write operation (see
gate E75, pin 3 in zone B-6). On the trailing edge of DRIVE
CLK (SYNC eLK from the drive), the RBIl monitors the
top cell in the Silo to determine if a word is there to output
to OBUF. If a word is present, it is indicated on the trailing
edge of DRIVE CLK by ORDY H being asserted, which
inhibits DLT from being generated via gate E7I. If ORDY
is not asserted, indicating the absence of a word available
for OBUF, and it is not the last word (LWRD asserted), the
DLT OUT flip-flop is clocked to the Set state, thus enabling
gate E72, pin 8 to post a DLT error.
The DLT OUT flip-flop can be direct set if DB OC'LK H,
DB OUT H, and OBUF FULL (0) H are asserted. Signal DB
OCLK H is asserted at the time of MSYN; DB OlIT H
denotes a register select function is specified; and OBUF
FULL (0) H indicates OBUF is empty. The setting of DLT
OUT, in this manner, occurs when the program tries to read
the Data Buffer register without a word available in it
(OBUF). It allows the program to simulate the clocking of
non-existent words out of OBUF in order to post DLT
errors. This feature is used as a maintenance aid.
Generation of DRIVE eLK H
The DRIVE CLK H signal is asserted when the drive is
ready to send or receive data. At that time the drive issues
SYNC CLK H, which is DRIVE CLK H if no error
conditions are present (indicated by INH CLK L) and if the
desired number of words have not been transferred as
indicated by DRWC OFLO (0). As previously described,
SYNC CLK signals originate at the drive. On the leading
edge of SYNC CLK, the drive either accepts the data
(Write) or prepares it for transfer to the RHII Controller
(Read or Write-Check).

6-25

sent back to the drive over the Massbus and is used by the
drive to clock data in to its buffer during a write operation.
The purpose of WRITE ClK is to ensure the proper deskew
of data on the Massbus during write operations.

On the trailing edge of SYNC ClK, the controller accepts
the data (Read or Write-Check) or prepares the next word
(Write). If word count overflow has not occurred (indicating more words are to be transferred) and if no error
conditions are present, the SYNC ClK signal becomes
DRIVE ClK in the RH 11. This is accomplished through
gate E68 in zone C-7.

6.13.7 Gating Synchronous Data
The GATE SYNCD signal at the output of gate E63, pin 11
turns on the Massbus drivers, when asserted, and allows the
data from OBUF to be gated on the Massbus synchronous
data lines. This signal is asserted during a write operation if
drive word count overflow has not occurred or an error
condition has not been raised. If an error or dlive word
count overflow occurs before the end of a re~ord. GATE
CYNCD H goes unasserted which disables the data drivers.
causing Os to be written in the remaining words in the
record by presenting all Os on the synchronous Massbus
data lines.

6.13.3 Error Flip-Flop
If an error condition occurs in the controller or the drive, a
TRE (Transfer Error) is posted. TRE (bit 14 of CSI) is
applied to the data input of the ERROR flip-flop (zone
B-7). TIle error condition sets the ERROR flip-flop when
docked by SYNC ClK which then causes an INH eLK
assertion to prevent further DRIVE CLK signals. The
purpose of synchronizing the TRE with SYNC CLK is to
preven t spurious spikes from occurring on DRIVE CLK
during detection of an error. The ERROR flip-flop is
cleared by SILO CLR l which is derived from CLR + GO
CLR.

6.13.8 Data Requests (Write Command)
When requesting words from the Unibus during a write
operation, the DATA REO L signal must be asserted. This
signal is transferred to the BCT module to initiate an NPR
request on the Unibus. Signal OAT A REO L is asserted
when IBUF is empty, provided there is no word count
overflow or no TRE. This is shown in AND gate E68
(output pin 8) which feeds gate E67. The output of E82 is
fed back to AND-OR gate E67 and serves to keep this
circuit latched. The circuit will unlatch as a result of CLR
BBSY L or ROY L. Signal CLR BBSY L occurs when the
RHl1 gives up the Unibus. After the first DATA REQ,
subsequent DATA REO signals are asserted by the SHIFT
IN H signal fed to gate E67. TIle SHIFT IN signal
anticipates the availability of IBUF to accept a data word
from the Unibus.

6.13.4 Generation of INH ClK l
INH CLK L is asserted as a result of a TRE or DLT error.
TIh~se error conditions are ORed in gate E71. INH eLK L
prevents DRIVE CLK H from occurring and thus prevents
the RH I I from accepting any more data words from the
device.
6.13.5 SILO ClR Generation
The SILO CLR l signal is generated by ClR + GO ClR
which triggers 400 ns one-shot multivibrator E92. The
400 ns provides the required pulse width to clear the Silo
chip. TIle CLR signal occurs when the program sets the
CLEAR bit (bit 5 in CS2) when a reset or Unibus initialize
pulse is asserted, or when the power supply is failing which
asserts the DC LO L signal on the Unibus. The GJ CLR
signal is asserted when a data transfer command is loaded
with the GO bit asserted. There are two instances in which
the pulse used to generate CLR + GO CLR L is too narrow
(less than 400 ns) to clear the Silo: I) when the program is
loading the CLEAR bit and 2) when a data transfer
command is loaded in CSI with the GO bit asserted. In
these cases, the CLR + GO ClR is applied to the one-shot
which widens the pulse to 400 ns. The other conditions
used to generate CLR + GO CLR L (reset, Unibus initialize,
and DC lO) are applied to gate E98 to ensure full width of
the clear condition. Signal SILO ClR is used to initialize
the Silo and Silo control signals.

6.13.9 Data Requests (Read or Write-Check)
The RH 11 requests the Unibus by the OAT A REO signal
which is used to initiate the NPR logic on diagram BCTH.
The DATA REO signal is asserted by the Silo output. logic
when OBUF FULL is set (indicating a word has bubbled up
the Silo and into OBUF), there is no TRE (Transfer Error).
and a READ + WR CHI( command is specified. The logic is
implemented in gate E68, pin 6. The output at pin 6 is
applied to gate E67. The output of inverter E82, pin 6
latches gate E67 until unlatched by CLR BBSY L. Signal
CLR BBSY L is generated at the end of the cycle in a
single-cycle NPR or at the end of the second cycle when
doing back-to-back NPR cycles.

6.13.6 Write Clock
1he WRITE elK H signal at the output of AND gate E90,
pin 6 is the SYNC CLK signal from the drive which is
ANDed with the WRITE H signal. Signal WRITE CLK H is

6.13.10 NEXT SIGNAL (Write)
The NEXT signal shown in zone C-I, when asserted. causes
back-to-back NPR cycles to occur. The 0 AT A REO l
signal is keyed when the IBUF is empty or SHIFT IN

6-26

occurs. As soon as the RH 11 gains control of the Unibus, it·
asserts BBSY. prepares to obtain the data word, and
monitors Input Ready (lRDY). This is done at MSYN
WAIT time. If IRDY is asserted, the NEXT signal is
generated by AND-OR gate E76 (as a result of IRDY Hand
WRITE H both being asserted). This means that the bottom
cell of the Silo is empty, and the RH 11 will do a second
NPR cycle before releasing the Unibus. If the NEXT signal
is not asserted, it indicates that the bottom cell of the Silo
is full. In this case, the single NPR cycle is completed, the
bus is released. and the RH 11 waits for SHIFT IN to be
asserted to repeat the cycle.

Silo before returning to the Ready state. This is aCCOlllplished by inserting a stop word in to the Silo upon
detection of exception and waiting for the word to appear
at the output of the Silo before raising the error condition
as TRE and thus producing the return to RDY state.
ll1e above operation is performed hy causing a 150 ns pulse
to be generated by one-shot E58 in zone 07 when the
positive-going trailing edge of EXCP L occurs, which at the
same time sets the EXCP SAVE flip-flop located on
drawing DBCD. The 150 ns pulse creates an input clock to
the Silo as previously described. The EXCP SAVE condition is then inserted in the 20th bit position of the Silo and
begins to bubble to the top as does a normal data word.
When this stop word reaches the top cell of the Silo, the
EXCP STOP signal is asserted, indicating the last word in
the Silo is or has been transferred on the Unibus. TIle Silo
control then attempts to transfer this stop word into
OBUF. However, the EXCP STOP signal diverts the 45 ns
pulse from one-shot E70, pin 13 to cause EXCP ERR Land
prevents the SET OFULL signal from setting OBUF FULL
(an indication that means a valid data word exists in
OBUF). If, however, the WC OFLO (1) condition is
asserted when EXCP SAVE has been set, the EXCP ERR
signal is immediately asserted, causing TRE to set as the
RHII returns to the Ready state.

6.13.11 NEXT SIGNAL (Read or Write-Check)
In order for the RH II to initiate back-to-back NPR cycles,
the NEXT L signal must be asserted. Signal NEXT L is
asserted when OR5 through OR 1 are asserted (indicating a
data word in the top cell of the Silo) and READ + WR CHK
H is asserted. Consequently, the RHl1 monitors the leading
edge of MSYN WAIT in the first memory cycle and
determines whether there is a word in the top cell of the
Silo (ORDY asserted). If there is, the NEXT CYCLE
flip-flop is set on DBCA and back-to-back NPR cycles are
done. If there is no word in the top cell of the Silo, NEXT
L is unasserted to inhibit the next NPR cycle and CLR
BBSY L is asserted which removes the latch keeping the
DATA REQ Signal asserted.

NOTE
If another error occurs causing TRE to set,
operations on the Unibus are halted and the
RHtt will return to the Ready state with data
words remaining in the Silo buffer.

6.13.12 Word Count Increment (Write Command)
111e INC WC gate below NEXT causes the word counter to
be incremented if DESK MSYN is asserted. Consequently,
each memory cycle causes the word counter to increment.

6.14 LOGIC DIAGRAM DBCC
This diagram shows bits 11 through 0 of the DMX, IMX,
IBUF, Silo and OBUF. For a Write command, the data is
gated from the appropriate Unibus (DMX) to IMX, and
then through IBUF, the Silo, and OBUF for transfer to the
drive. For a Read command, the data from the drive is
supplied to IMX from the Massbus and then to IBUF, the
Silo, and OBUF for transfer onto the appropriate Unibus.
For a Write-check command, the output of DMX (from the
Unibus) is compared with the synchronous data at the
output of OBUF (from the drive).

6.13.13 Word Count Increment (Read or Write-Check)
The INC WC L signal at the output of gate E77, pin 6 is
asserted during a read or. write-check operation when the
SHIFT OUT signal is generated. This indicates a word is in
OBUF ready to transfer and the word counter is thus
incremen ted.
6.13.14 EXCEPTION ERROR (Write Command)
The EXCP ERR L signal indicates that an exception
condition in the drive (any error set in the ER register) can
be recognized and may cause TRE to set to end the
operation. When performing a Write command, EXCP
SAVE (1) H immediately causes EXCP ERR L to be
asserted.

When the RHII is bus master (NPC MASTER L asserted),
the CSRA SEL BUSA signal is checked to determine which
Unibus is selected. If CSRA SEL BUS A is asserted, Unibus
A is selected; if the signal is not asserted, Unibus B is
selected. If the RH 11 is not master (NPC MASTER L
unasserted), the DMX is selected to BUSA. If the RH 11 is
not performing a Read or Write-check command, IMX is
selected to accept DMX rather than Massbus synchronous

6.13.15 EXCEPTION ERROR (READ or WRITECHECK)
When performing a read or write-check operation and an
exception condition is raised in the drive, it is desirable to
finish transferring the data words which already exist in the

6-27

1he Unibus B receivers receive the data from the Unibus
(BUSB 000 L through BUSB 017 L) and supply them to
the RH11 where the signals are designated UNIB 000 H
through UNIB 017 H.

data. In this case, the DMX and IMX are set up to only
accept da ta from Unibus A regardless of the setting of the
PORT SEL bit. Consequently. when the program is loading
data into the Data Buffer register, the data originates from
Unibus A. The clocking logic for the IBUF. Silo, and OBUF
is showl1 on sheet DBCB.

Bits 16 and 17 of the Unihus B data which is normally the
Unibus PA and PB lines are employed as data when the EN
DATA BUSB L signal is asserted. This signal is asserted
when Unibus B is selected (SEL I3USA H unasserted) and
the 16 BIT BUSB jumper (W2) shown on sheet DBCH is
cut.

6.15 LOGIC DIAGRAM DBCD
This diagram shows bits 17 through 12 of the DMX, IMX,
IBUF, Silo, and OBUF. The description of these bits is
similar to that described on sheet DBee.
In addition to selecting the 18 data bits from the Unibus or
Massbus, the IMX incorporates a parity bit. During a Write
command, the parity bit is forced to 0 through the Silo and
into OBUF. "nlC parity bit generated by the drive during a
Read or Write-check command is carried through the Silo,
providing a parity check of the Silo logic as well as
transmission over the Massbus. The parity logic associated
with the Massbus is described in more detail on sheet
PACA.

6.17 LOGIC DIAGRAM DBCF
This logic diagram contains the drivers and rccciwrs (8838
transceivers) for the Unibus A data lines. The pull-up
resistors for the internal open-collector bus (BUSI) in the
RH 11 are also shown. This internal open-collector bus is
used when the program is reading infomlation from an
RH 11 register (or a drive register via the Massbus control
lines) and is actually the output of the 8234 open-collector
multiplexers which route information to the Unibus.

-nle EXCP SAVE flip-tlop in zone A-S stores the fact that
an exception condition was received from the drive and is
used as an input to the 20th bit position of the Silo. This
input provides the stop word described previously on
DBC A (EXCP ERR) which will appear as EXCP STOP
when all data words in the Silo have been transmitted.

Data from BUSJ (BUSI 000 OUT L through BUSI 015
OUT L) is supplied to the Unibus A drivers which drive
these signals onto the Unibus where they are designated
BUSA 000 L through BUSA 0 i 5 L.
Data from OBUF is applied to the Unibus via 8881 hus
drivers. The 8881 drivers are enabled if the RH 1 1 is bus
master, if a read operation is specified (OAT A TO BUS H
asserted), and if Unibus A is selected (SEL Bl1SA H
asserted).

TIle top of sheet DBCD shows 18 Exclusive-OR gates used
during a Write-check command. These gates compare the
da ta in OBUF that was taken from the drive to the output
of DMX which represents the corresponding memory word.
TIle outputs of the Exclusive-OR gates are open-collector
ORed such that if corresponding bits fail to compare, an
error will be registered and is indicated by the setting of the
WCE (Write-Check Error) flip-flop. This nip-flop checks the
status of the open-collector Exclusive-OR gates at the time
of the MSYN WAIT signal and is latched if an error is
detected. The flip-flop remains in this state until the CLR
ERR signal is asserted.

Data from Unibus A (BUSA 000 L through BUS A D 17 L)
is supplied to the RHII via the 8838 gates and is designated
000 IN H through 017 IN H in the RH 11.

6.16 LOGIC DIAGRAM DBCE
TIlis diagram contains the drivers and receivers (8838
transceivers) for the Unibus B data lines. The Unibus B
drivers drive the data from OBUF onto the BUSB data
lines. rn order to enable the drivers, the RH 1 ] must be bus
master, Unibus B must be selected (SEL BUSA H not
asserted), and a read function must be specified (DATA TO
BUS L asserted).

6-28

Bits 16 and 17 of Unibus A data which is nonnally the
Unibus PA and PB lines are employed as data when EN
DATA BUSA L is asserted. This signal is asserted when
Unibus A is selected (SEL BUS A H asserted) and the 16
BIT BUSAjumper (WI) shown on sheet DBCH is cut.

6.18 LOGIC DIAGRAM DBCH
This diagram contains the parity jumpers for Unibus A and
Unibus B multiplexer E21 to monitor parity, and four 8234
multiplexers to multiplex the Massbus control lines with
the data buffer output.

6.18.1 Parity Jumpers
The lower portion of the diagram shows a parity jumper
(16 BIT BUSA) for Unibus A and a parity jumper (16 BIT
BUSB) for Unibus B. The operation of each is similar, so
only the Unibus B parity jumper will be described. If the
jumper is left in, gate E27, pin 8 is inhibited from
generating EN DATA BUSB L, indicating that the upper
two bits (D 16 and D 17) are to be used as parity bits (P A
and PB). In addition, AND gate E28, pin 6 is qualified by
the jumper for the selected bus being inserted which causes
EN PAR H (enable parity) to be generated. When the 16 Bit
BUSB jumper is cut, one input to E27, pin 9 is enabled. If
Unibus B is selected, the output goes low, creates EN
DA T A BUSB L, and disables EN PAR which indicates that
the upper two bits are used as data bits. The lower jumper
and gate for Unibus A are the same except that the gate is
qualified by selecting Unibus A and not Unibus B.
6.18.2 74157 Parity Multiplexer
Multiplexer E21 monitors the parity bits for Unibus A and
Unibus B. The multiplexer is enabled by EN PAR H. A
parity error is detected when parity bit PB is asserted and
PA is unasserted. For example, if Unibus A is selected, D16
IN H (PA) is unasserted and D 17 IN H (PB) is asserted,
which causes pins 3 and 4 of gate E79 to be enabled. At
DATA STR time, E79 is qualified generating SET UPE L
(SET Unibus Parity Error).

memory. Every word fetched is accompanied by DATA
STR which clocks the counter and causes it to increment. A
selectable count range may be selected to determine when
the START signal is to be asserted which will cause the
RUN assertion on the Massbus. This is done to prefill the
Silo with data before requesting the drive to start to
perform the write operation. A count of 64 is designated by
the FULL jumper being connected. Other jumper configurations may be inserted. For example, if the HALF jumper
is inserted, the START H signal will be asserted at a count
of 32. If the QTRjumper is connected, the START H signal
will be asserted at a count of 16. Only one jumper may be
inserted at any given time and, with no jumper inserted,
START will always be asserted allowing RUN to be asserted
when the first word reaches OBUF (see CSRA). If a write
operation is designated, the START signal generates RUN
when the Silo is filled to the selected value. 111is connects
the RH 11 to the drive and signals the beginning of the da ta
transfer on the synchronous Massbus.
6.19.2 CSl/CS2 Gating Onto BUSI
The two 8234 open-collector multiplexers select the low
byte of the CSI or CS2 register and gate the contents onto
the internal bus (BUSI). Inputs from the CS 1 register are
gated onto BUSI when CSI OUT is asserted and the inputs
from the CS2 register are gated onto BUSI when CS2 OUT
is asserted.

6.18.3 8234 Control Line/Data Buffer Multiplexing
The 8234 multiplexers select the Massbus control Hnes or
the outputs from OBUF for transfer to the RHil internal
open-collector bus (BUSI). When the program reads a
remote register, the 8234 open-collector multiplexers gate
the Massbus control lines (COO IN H through CIS IN H) to
the in ternal bus (BUSI). In this instance, the multiplexers
are enabled by CNTL OUT L, which is the signal associated
with reading a remote register. When the program is reading
the data buffer for maintenance purposes, the data buffer
outputs (OBUF 00 H through OBUF 15 H) are multiplexed
onto the BUSI lines. The multiplexers are enabled by DB
OUT L, in this case, which is the signal associated with
reading the data buffer.

6.19.3 Voltage Regulator
This diagram shows a regulator circuit which converts
-15 Vdc to -12 Vdc for use on the Silo chips. The 2N5639
FET is connected as a constant current generator to
stabilize the bias current through Zener diode IN759A. The
2N2409A transistor is used as the series pass element
(regulator in series with the load current).
6.20 M7297 PARITY CONTROL MODULE (PACA)
The M7297 Parity Control module contains the parity logic
for parity generation and checking both the synchronous
and the asynchronous sections of the Massbus. Each drive
contains associated parity generation and checking logic.
Sheet PACA shows the Massbus parity logic, consisting of
74180 8-bit parity generator/checkers. The three 74180s on
the left are used for parity on the synchronous Massbus and
the remaining four 74180s are used for parity on the
asynchronous Massbus. Parity on the Massbus is odd.

6.19 LOGIC DIAGRAM DBCJ
The logic diagram shows the START counter, two 8234
open-collector multiplexers which select the low byte of
the CS 1 or CS2 register onto BUSI, and a regulator circuit.

6.20.1 Synchronous Massbus Parity
The 74180 chips serve a dual function. During a write
operation, the 74180 chips in the RH 11 generate parity
while the associated parity logic in the drive check parity.
Conversely, during a read or write-check operation, the
parity logic in the drive generate parity while the 74180s in

6.19.1 Start Counter
The Start Counter consists of two ICs (E64 and E65)
connected in series. Each time a data transfer command is
loaded in the RH 11, the CLR + GO CLR signal resets the
counter to O. For a write operation, words are fetched from

6-29

the RH J I check pari ty. This is possible wi th the same set of
parity chips because in write, read or write-check operanons the parity bit is rippled through the Silo along with
the da ta word. This feature is useful because the parity bit
also checks out the Silo logic as well as the Massbus.
-nle 1S data bits and the parity bit from OBUF are applied
to the 3 741 SO chips. nlis can he considered as a 19-bit
da ta word. Each 74180 also has an 000 and EVEN input
and a ~EVEN and a rOOD output. The EVEN input is
normally low and the anD input is normally high, selecting
the 74180 for odd parity. The 19 data bits and the ODD
input arc summed to yield an asserted :LEVEN or ~O[)D
\lUtpU1. Fm example. if :llJ the data bits (18 data bits plus
thl' parit\ bit) 3rt' asserted, the sum is odd. nlis is summed
with the ODD input to yield an even number of Is.
Consequently. the rEVEN output is asserted and the
disconnected IODD output is unasserted. As another
example. if the 18 data bits are summed to yield an even
number of Is and the parity bit is unasserted, the result is
even. This is summed with the 000 input to yield an odd
number. In this case. the rEVEN output is unasserted.
6 ..20.1 Read or Write-Check Parity
'(lte that the rEVEl\ uutput is applied to the SYNC PE
(Syndlwnous Parity Error) flip-flop and, if ~EVEN is
l"'ierted. this disables thl' SYNC PE flip-flop from setting,
lIldicaring that there is no parity error. The SYNC PE
t1ip-no!, is used when checking parity during a read or
VvTire-ciJcL'k operation. 111e flip-flop is docked during the
trailing edge of OAT A STR .from the Unibus cycle if
WRITE L is unasserted which occurs during a Read or
Write-Check command. A third input to gate E5, which
feeds the SYNC PE clock input, is the 0 output of the
nip-flop which prevents the flip-flop from being clocked
again. In this instance, the flip-flop is direct cleared by the
CLR ERR L signal from sheet CSRB.
6.10.3 Write Parity
For a write operation, the 18 data bits and the parity bit
1fe supplied to the drive to yield an odd number of 1s. To
accomplish this, the 19th bit, designated OBUF PA H, is
forced to a 0 so the 18 data bits (designated OBUF 00
through OBUF 17) determine whether the ~EVEN output
of the 74180 is asserted or unasserted. For example, assume
that the sum of the 18 data bits is odd (the parity bit
OBUF PA can be disregarded since it is a forced 0). These
bits are summed with the 000' input to assert the ~EVEN
output. This inhibits gate E7, pin 8 from generating a sync
parity bit (SYNC PA H), if the second input to this gate is
temporarily disregarded. Since the data is an odd number of
Is, it is not necessary to generate a parity bit. If the data
contains an even number of Is, it yields an odd number

when summed with the ODD input. As a result. the
~EVEN output goes low generating a SYNC PA bit. which
creates odd parity.
In the case where an error condition exists or word count
overflow occurs prior to the end of a rccord. the remaining
words in the record arc filled wi th Os. This is accomplished
by disabling the data drivers on the Massbus with the signal
GATE SYNCD (see sheet DBCB). As a result. the number
of Is is zero which is even. Consequently, a parity bit must
be simulated to generate odd parity. This is accomplished
by the GATE SYNCO input going lInasserted. Thc situation
just described only occurs for a write npt?rarinn and.
consequently, the driver that drives the SYNC P A signal nn
the Massbus is ANDed with the Write signal.

6.20.4 Asynchronous Massbus Parity
TIle two 74180 chips in the center of sheet PACA are
employed for parity generation when writing into a register
in the drive. The 16 data inputs to the chips are from the
Unibus A data lines. Note that odd parity is normally
selected.

Assume the data inputs contain an even numher of I s. This
is summed with the 000 input to assert the LODD output
which generates CNTL PA OUT H. l11is is the parity hit
generation and is supplied to the Masshus Jrivcr for transfer
to the drive. If the data inputs contain an odd number of
Is, .the CNTL PA OUT H signal is not asserted and no
parity bit is generated. When reading from a drive register. a
different set of data lines is used and this necessitates two
additional 74180 chips to check parity. 111e lines are the
"C" IN lines which are the au tputs of the receivers used to
monitor the Massbus control infonnation. 11l(.~ parity bit
generated by the drive is supplied to the ODD input. The
inverted polarity of the parity bit is applied to the EVEN
input. The sum of the bits should be odd which means that
LEVEN should be unasserted. For example. if the 16 data
bits are allIs and the parity bit generated in the drive is a 1.
the sum of all bits is 17, which is odd. This causes ~EVEN
to go low, which inhibits NAND gate E5, pin 5 which, in
turn, places a low at the D-inplIt to the CNTL PE (control
parity error) flip-flop. If the data inputs to the 74180 chips
contain an odd number of 1s and the parity bit from the
drive (CNTL PA IN H) is asserted (indicating a parity
error), the ~EVEN output is forced high which sets the
CNTL PE flip-flop during the trailing edge of CNTL OUT
L. This signal is the gating signal used to gate da ta from the
Massbus control lines to the Unibus. When the CNTL PE
flip-flop is set, it remains latched by the 0 output feeding
the data input via gate E7, pin 3. The flip-flop is cleared in
the same manner as the SYNC PE flip-flop by CLR ERR L.

6-30

NOTE
The second input to gate E5 is the. AS ·REG
signal. This signal inhibits checking parity when
the Attention Summary (AS) register is being
read. The reason that parity cannot be checked
when reading the Attention Summary register is
that the AS register in each drive provides only
one bit of information and a parity check is
meaningless.
The output of the SYNC PE flip-flop causes an MDPE
(Massbus Data Parity Error) which appears in bit 8 of the
CS2 register and also causes TRE (bit 15 of CS 1) to be
raised.
TIle output of the CNTL PE flip-flop causes an MCPE
(Massbus Control Parity Error) which appears in bit 13 of
the CS 1 register and causes SC (bit 15 of CSl).
TIle PAT H signal can be asserted by the program (bit 4 in
CS2) to generate even parity on the Massbus and to check
for even parity on the synchronous data lines when
performing Read or Write-check commands. This maintenance feature' allows verification of the parity logic in the
drive.
The M7297 Parity Control module contains two lightemitting diodes: one for control bus parity error and one
for synchronous bus parity error. TIlis allows the maintenance personnel to quickly detect whether the parity error
occurred on the synchronous section of the Massbus or on
the control (asynchronous) section of the Massbus.
6.2] M5904 MASSBUS TRANSCEIVER MBSA, MBSB,
MBSC
TIle Massbus consists of three Massbus cables and associated
\1assbus transceiver modules. A 40-pin connector on each
M5904 Massbus Transceiver module connects the Transceivers to the Massbus cables. The transceivers plug into
slots C4-D4, CS-D5, and C6-D6 in the RHll to connect the
RH 11 to the Massbus.

Each signal on the Massbus is applied to a differential
circuit which transmits the true signal and an inversion of
the signal along the bus. At the other end of the bus, the
signals are received by differential receivers which output
the true fonn of the signal. The differential circuitry serves
to eliminate noise since any common mode noise will be
cancelled at the differential receivers. For additional description, refer to MS904 Massbus Transceiver module in
Appendix A.

The three Massbus cables are designated: Massbus Cable A
(D-BS-RHI1-0-02, MBSA) Massbus Cable B (D-BS-RBIl0-02, MBSB) Massbus Cable C (D-BS-RHII-0-02, MBSC).
TIle M5904 Massbus Transceiver is functionally shown
within the dotted block on each drawing. The 40-pin
connector is shown in the center of the dotted block. The
differential transmitters which drive signals onto the
Massbus from the RH 11 are shown to the left of the
connector. The differential receivers which receive signals
from the Massbus are shown to the right of the connector.
These signals originate at the drive and are routed to the
RHII via the differential receivers.
To minimize switching of signals on any transceiver module
at a given time, the signals are grouped on different
modules. For example, OBUF 00-05 H is contained on
MBSA, OBUF 06-11 H is contained on MBSB and OBUF
12-17 H is contained on MBSC. The DOO IN H through
DIS IN H signals from BUSA are also divided on the three
modules in similar manner. The RSEL 0 H through RSEL 4
H signals are grouped on MBSA and MBSB.
TIle OBUF signals arc gated by GATE SYNCD H which
enables the output of OBUF to be gated onto the MASS 'D'
lines of the Massbus. The DOO IN H through DIS IN H
signals which form the MASS 'C' lines are enabled by
GATE CNTL H which occurs when the RH 11 is writing a
remote register. GATE CNTL H is the assertion of DEV
SEL and a DATO. TIle RSEL signals select a drive register
and are enabled by the DEV SEL signal. Unit select signals
UOO H througll U02 H are also enabled by DEV SEL and
specify one of eight possible drives. The remaining control
signals which are supplied to the drive are also shown.
These include WRITE CLK, RUN, DIR TRANS, MB INIT,
DEMAND, CNTL PA OUT, SYNC PA, and SUPPLY AC
LO.
The signals sent from the drive to the Massbus are SYNC
DOO through SYNC 017 which represents synchronous
data, and COO H through CIS H which represents the
contents of a drive register. Control signals which include
EXCP, EBL, ATTN, SYNC CLK, CNTL PA IN, OCC and
TRANS are also shown.
6.22 UNIBUS A CABLE DIAGRAM
The Unibus A cable diagram is shown on D-IC-RHII-0-03.
Slots A 1 and A9 are wired together as are slots Bland B9.
The slots are wired to provide UNIBUS A IN and UNIBUS
A OUT signals, except for the GRANT signals. The GRANT
signals are passed through the device before being supplied

6-31

to the Unibus out cable. The cable slots occupy slots AI,
Bl, and A9, B9 as shown in the Module Utilization Chart
D-MU-RHI1-0-01.
'The three small peripheral controller devices are shown on
the lower portion of the cable diagram. If the devices are
inserted in the slots. the GRANT signals are passed from
device to device. G727 Grant Continuity modules are
inserted in any of these slots (D7, D8, or D9) not
containing small peripheral controllers. The designated slots
for the peripheral con trollers are C7 through F7, C8
through F8. and C9 through F9 (see D·MU-RHI1-0-01).

6.24.1 NPR Arbitration and Issuance of NPG
In certain multipart memory configurations, Unibus B will
be employed without a processor. In order for the RH 11 to
acquire bus mastership, it must issue an NPR and must
receive an NPC signal. Since there is no processor to issue
grants, the arbitration logic on the Ml)300 performs this
function. TIle logic is shown on the left-hand side of the
drawing. If the M9300 is connected at the beginning of the
Unibus and no processor is connected to this Unibus,
jumper WI is cut. This enables the arbitration logic as
described below.
TIle NPR requests are arbitrated by the M9300. If an NPR
request is received (and BUS SACK is not present or has
not been on the Unibus for 100 ns), the latch consisting of
E2, pin 3 and E2, pin 6 is enabled. When the NPR request is
received, pin 1 goes low forcing pin 3 high which, in turn,
forces pin 6 low and enables signal BUS NPC H to be
generated.

Also shown on the diagram is the M688 Power Fail driver
which buffers the AC LO and DC LO signals and supplies
them to Unibus A for power fail detection.
6.23

UNIBUS B CABLE DIAGRAM

TIle Unibus B cable diagram is shown in drawing D-ICRH 11-0-04. It is similar to the Unibus A cable diagram with
the following exceptions:

NOTE
I.

lnle signals are prefixed by BUSB to denote
Unibus B.

If a BUS SACK signal and an NPR request are
both received, pins 3 and 6 will both be high
because the arbitration logic recognizes NPRs
while SACK is asserted. In accordance with the
Unibus specification, a GRANT signal cannot
be issued until 100 ns after the SACK signal is
removed. This logic is shown by gates E I, pin
14, E2 pin II, E6 pin 3, 100 ns delay DLI, E5
pin 2, and E2 pin 6. When BUS SACK is
asserted, E2 pin 6 is high and inhibits NPG H
from occurring. After BUS SACK is unasserted
for 100 ns, E2, pin 5 goes high to allow the
grant to be asserted.

In Unibus A. the BUS GRANT signals are
PJssed through the devices and are not directly
wired from the UNIBUS A IN slot to the
lI~IBUS A OUT slot. In Unibus B, the BUS
GRANT signals are directly wired from the
UNIBUS B IN slot to the UNIBUS B OUT slot.
111e reason for this is that the RH 11 cannot
interrupt on Unibus B and, consequently, does
not have to look at the BUS GRANT signals.
Note that the NPG signal is not directly
connected but is passed through the device on
both Unibuses.

TIle NPR request, as previously described. generates the
NPC H signal. In addition, however. it fires 10 MS onc-shot
multivibrator E4, pin 4 via gate E2, pin 6 If the BUS SACK
signal is not returned within 10 MS, the one-shot times out
and the positive-going trailing edge at E4, pin 4 clocks
NO-SACK TIMEOUT flip-flop E3 set. TIle 0 output of this
flip-flop goes low and simulates the BUS SACK signal since
it is ORed with BUS SACK in gate E6, pin 3. The simulated
BUS SACK signal performs two operations: I) it clears the
latch by causing E2, pin 5 to go low, and allows other NPRs
to be arbitrated, and 2) after the 100 ns delay through
DLl, it direct clears the 10!J.s one-shot and the NO-SACK
TIMEOUT flip-flop.

Unibus B has an M688 Power Fail driver simi!ar to that on
Unibus A. TIlis is to assert BUSB AC LO or BUSB DC LO
on Unibus B in the event of a power-fail condition.
6.24

M9300 UNIBUS B TERMINATOR

'Il1C MQ300 Unibus B Terminator is shown in drawing
D·CS-M9300·0-1. Three main functions performed by the
M9300 are:
I.
2.
3.

to properly ternlinate the Unibus cable
to arhitrate NPR'i and issue NPGs

to prevent NO-SACK timeout.

6-32

In addition to arbitrating NPRs, the M9300 must also
simulate a processor when a power-fail condition is asserted. In this case. the device on the Unibus asserts BUS DC
LO L. TIle M9300 receives this signal and returns BUS INIT
L via gates E 1, pin 2 and E8, pin 1. Note that BUS INIT L
is only returned when jumper WI is cut (no processor
connected to Unibus). Consequently, the M9300 simulates
the BUS INIT signal from the processor.
If the :\19300 is connected at the beginning of the Unibus
and there is a processor connected to the Unibus, jumper
WI is not cut. TIlis places a low input at NOR gate E8, pin
5 which causes the output to go high. This output is
open-collector ORed with the processor GRANT signal on
the lTnibus. In this instance, E8, pin 5 diables the
arbitration logic in the M9300 from arbitrating NPRs. E8,
pin 4 is effectively disconnected from the Unibus, and the
processor does the necessary arbitration.

If the M9300 is at the end of the Unibus and there is no
processor connected to the bus, then only jumper W2 is
cut. With jumper W3 in, the gate (E6, pin R) which
normally passes the BUS GRANT signals is inhibited. Since
there is no processor to issue BUS GRANT signals, they
have no meaning. TIlcse signals are open-collector signals
asserted high and since tllere is nothing to assert them low,
they appear as valid BUS GRANT signals 011 the Unibus.
Therefore, jumper W3 is in which disconnects these signals
from the Unibus by opening gate E6, pin 8. TIle BUS NPG
signal can be asserted by a processor or another M9300
terminator at the beginning of the bus, thereby causing the
SACK assertion. This is verified by the fact that NAND gate
E8, pin 13 is enabled to allow the BUS NPG signal to assert
BUS SACK.

If jumpers Wt and W2 are erroneously cut. the M9300
would function abnormally. To prevent this condition from
occurring, both jumpers are applied to NAND gate E8. pin
10. If both jumpers are cut, E8, pin lOis driven low causing
a light-emitting diode to illuminate. This immediately
indicates an illegal jumper configuration for maintenance
purposes.

6.24.2 Prevention of NO-SACK TIMEOUT
TIle logic on the right-hand side of D-CS-M9300-0-01 is
employed when the M9300 is connected at the end of the
l'nibus. TIle purpose of this logic is to monitor the BUS
N'PG and BUS GRANT signals and to issue BUS SACK
which bypasses the 10 I1S timeout logic used in the
processor or in an M9300 module when employed as an
arbi tra tor.

NOTE
If all three jumpers are in, the M9300 logic is
bypassed and only the terminating resistors are
utilized.

If a pwcessor is connected to this Unibus, jumper W3 is
cut. Since the M9300 is at the end of the Unibus, jumper
W2 is also cut. With W3 cut, NAND gate E6, pin 8 is
enabled to pass the BUS GRANT signals, and with jumper
W2 cut, NAND gate E8, pin 13 is enabled to pass the BUS
GRANT or the BUS NPG signal.

6.25 G727 GRANT CONTINUITY MODULE
If there are no small peripheral controllers installed in slots
C7 through F7, C8 through F8, and C9 through F9. G727
Grant Continuity modules must be installed in slot D7, D8,
or D9. These modules merely continue the BUS GRANT
signals to the next device on the Unibus.

Consequently, any grant that reaches the. end of the bus,
and has bypassed the device requesting a grant, causes the
BUS SACK L signal to be asserted. BUS SACK L is sent to
the processor and causes the GRANT signal to drop which,
in turn, causes BUS SACK to become unasserted.
T1~e

6.26 M688 POWER FAIL DRIVER
The M688 Power Fail driver is a single-height module which
receives power fail signals from the power supply and
a.."iserts them on the Unibus. If Unibus B is utilized as a
second bus, an additional M688 is required to assert power
fail signals on this bus. Figure 6-5 is the M688 Power Fail
module schematic. AND-NOR gates E 1. pin 8 and E4, pin X
and the associated inverters are not used in the RH 1 1.

10 I1S timeout logic is overridden as follows. Assume a
device issues a request and then suddenly clears it. The
processor arbitrates the request and issues the grant,
thinking it saw a valid request. The processor then times
out for 10 I1S waiting for BUS SACK. However, the logic
just described causes BUS SACK to be asserted immediately. thus bypassing the timeout feature and improving
interrupt response time of the Unibus.

6-33

10
II

Di
CI

. -----.---- E1

81AI

3.9K

K2-J2

3
4

X)"------.---..- - - - - K 1

rornRENTiAL AMPLiFiER-- -- ---,

fNOiSEFiLTER----ll

I
SUPPLY

AC LO L

R4
lK
R3
100

RI3

+5V

+7 VOLTS

4.7K

R19

~>r----.----I---+____<l PIN

4.7K
12
>--t-t---i

I
II
I
II
-=
L - - - - - - - J L _______ _

BUSA AC LO L

R14
10K

470

P 2 ------'-"-1----...
N2----'-'i..--/
M2-------:.=-r~

L2 ------.:~....J
V2----...:.r~

U2 -----=t.....J

T2----...,-----.,.
RI-----.:...t....~

IoIFFERENnALAMPUFi'ER - -

~~E7tL~----l',

SUPPLY

DC LO L
Nt

R: 5V

II
21 I

II
I

R7
4.7K

I iB~~~R--l
I
I

R20
4.7K

1v~~~~R----

PIN PI

BUS A
DC LO

L ______ .J I
I
L ________ J L _ _ _ -=_.J
10K

I
I
I1
I~

R23
330

L _____._~_J
11-2354

Figure 6-5 UNIBUS Power Fail Drivers Schematic

Vee

"nle schematic shows a noise filter, differential amplifier,
and bus driver for two power fail input sources. Pin HI is
(onnected to the ac power fail line, and pin Nl is
(onnected to the dc power line. When the input at pin HI
or Nl goes low, the output at pin D2 or PI, respectively,
goes low. 111e input power fail signal is applied to a
differential amplifier via the noise filter. The differential
amplifier increases the voltage swing of 3 V (0 to 3 V) to
5 V (0 to 5 V), which is the voltage required to operate the
bus driver. This circuit provides the drive necessary to
supply the signal to the Unibus. The voltage doubler circuit
increases the +5 V input to 8 V. This voltage is necessary to
generate the +5 V required at the input to the bus driver
circuit.

82n

i--:t

.........--1:::120ft. MAXIMUM

.. /

l....f ~5vnom.:I :
DRIVER'

,
:

82n

: TRANSMISSION
,CABLE
~

..rl 2.5V nom. I :
.6

82n
\\- 2348

Figure 6-7 Driver Termination
6.27 M5904 MASSBUS TRANSCEIVER MODULE
111e M5904 Massbus Transceiver module contains nine
differential driver chips (75113) and seven differential
receiver chips (751 07B). Each driver chip and each receiver
dup is capable of carrying two signals. Thus, the chips can
he designated dual drivers and dual differential receivers.
The transmission line connected to the transceivers are
bidirectional in that they can both receive and transmit
information. 111is is illustrated for one signal line in Figure
6-6.

DR IVER
(112 OF 75113)

RECEIVER
(1/2 OF 75107B)
PART OF M5904
"-2341

The M5904 Massbus Transceiver requires input voltages of
+5Vdc and -15Vdc. The dual drivers require +5Vdc
operating voltage while the dual differential receivers
require +5 Vdc and -5 Vdc. 111e -5 Vdc is obtained from
the -15 V dc source via a resistor and Zener diode network.

6.27.1 75113 Dual Differential Driver Chip
The 75113 Tri-state Dual Differential Driver Chips provide
differential outputs with high current capability in order to
drive balanced lines. 11le chips feature a high output
impedance making it possible to connect many drivers on
the same transmission line. A simplii1ed schematic of the
75113 is shown in Figure 6-8.

The inverting output of the driver chip is the transistor
collector, while the non-inverting output is the transistor
emitter shown at point B. When the input is low. neither
transistor conducts and line A is biased to + ~.S V while line
B is biased to 0 V by the tenninator resistors (refer to
diagram). When the input is high, the upper transistor
collector is driven low (0 V) and the lower transistor
emitter is driven high (+2.5 V). The pin connection diagram
for the dual differential driver is shown in Figure 6-9.

Figure ()-6 Typical Differential Driver/Receiver Connection

The advantage of differential circuitry is that any nois(;;
picked up is generally picked up on both the inverted and
non-inverted signal lines. The differential receiver takes the
difference between the signals regardless of the noise level,
and the noise is effectively cancelled out.
Each driver on the M5904 must be terminated since the
M5904 is used to drive transmission lines (Figure 6-7).

6.27.2 75107B Dual Differential Line Receiver Chips
The 75107B Differential Receiver Chips feature dual
independent channels with common voltage supply and
ground terminals. The circuits operate as follows. If the
voltage at pin 1 is positive with respect to the voltage at pin
2, the output at pin 4 goes positive (Figure 6-10).

If the voltage at pin 1 is negative with respect to pin 2, the
output at pin 4 goes negative. 111e pin connection diagram
for the receiver is sh own in Figure 6-1 I .

6-35

r------,

+5V

11/2 OF DRIVER CHIP
82n

I
I SL
I
I
I
I
I
I

r- -

+5V

INVERTING
OUTPUT

I
I
I
I
I

OFF

1/2 OF DRIVER

1CHIP NEAR

I
I

=-....,------+---+----}2n

NON-INVEf3TING
OUTPUT

END OF LINE

+5V

L _,_-.J

OFF

\1\\

-',--F~--- -----------0---1

820

L _ _ _ _ _ _ ..I

II 23')2

Figure 6-8 Driver Chip Simplified Schematic

Vee +5V

INVERTED - - 2--OUTPUT
INVERTED OUTPUT
NON -INVERTED ---- 4
OUT PUT
NON-INVERTED
OUTPUT
LOGIC INPUT
TO +3V
TO +3V
L -_ __

-------------------~

11-2350

Figure 6·9 Dual Differential Driver Pin Connection Diagram

6-36

2
+3V
11·2349

Figure 6-10 Simplified Line Receiver Logic Diagram

INPUTS {

TO +3V
OR
STROBE

TO+3V
OR
STROBE
NC

NC
GROUND

VEE

OUTPUT

TO +3V
OR
STROBE

Vee

11-2351

Figure 6-11

75107B Differential Receiver Pin Connection
Diagram

6.29 M8838 UNIBUS TRANSCEIVER MODULE
The M8838 Unibus Transceiver module drives and receives
signals on the Unibus. The module is a quad chip consisting
of four Unibus drivers with common enables on pins 7 and
9 and four receivers which are always enabled. TIle pin
connection diagram is shown in Figure 6-12.

6.28 H870 TERMINATOR
TIle H870 Bus Terminator provides a simple and reliable
method of terminating the Massbus. The Massbus is
terminated by plugging H870 terminators into each M5903
transceiver module in the last drive.
TIle H870 consists of 38 82[2, 1/4 watt resistors wired
between each Massbus line and a common ground connection.

6.30 UNIBUS TERMINATION
TIle terminating resistors for the Unibus comprise voltage
divider networks necessary to properly terminate the
Unibus. These resistors are similar to the terminating
resistors on the M930 standard Unibus Terminator module.

NOTE
The H870 Terminators are to be installed on
the M5903 transceiver module with the
resistors facing up.

6-37

DRIVER
OUTPUT

DATA
I NPUT

RECEIVER
I NPUT

DRIVER
OUTPUT

DATA
INPUT

RECEIVER
OUTPUT

DISABLE

DRIVER
OUTPUT

DATA
INPUT

RECEIVER
OUTPUT

DRIVER
OUTPUT

RECEIVER
OUTPUT

01 SABLE
B

DATA
INPUT
4

GNO

4
l' - 2 4?'

Figure 6·12 M8838 UNIBUS Transceiver Pin Connection Diagram

6·38

CHAPTER 7
INSTALLATION AND MAINTENANCE

Panel located above the backplane. and quick-disconnect
tabs on the other end, which connect to the printed circuit
backplane. The following chart shows the color codes
associated with the power harness connections.

7.1 INTRODUCTION
This chapter describes the necessary installation information required to install the RH 11 as a Unibus device. The
chapter also describes the preven tive and corrective maintenance procedures that apply to the RH 11 when connected
to a TU16iTM02 tape drive. A major point in the
maintenance philosophy of this manual is that the user
understand the normal operation of the RH 11.

Red
Black
Blue
Gray
Violet
Yellow
Brown

This knowledge, plus the maintenance information contained in the TU 16/T:H02 Tape Drive System Maintenance
Jlanllal. will assist the maintenance personnel in isolating
system malfunctions.

7.2 INSTALLATION
The following paragraphs describe the mechanical and
electrical installation, power checks, jumper configurations,
visual inspection, and diagnostics associated with the RH 11.

+5 Vdc
Gnd
-15 Vdc
+15 Vdc
DC LO (+3 V to +5 V)
AC LO(+3 V to +5 V)
LTC 8 V pk-to-pk ac

CAUTION
When connecting the power cables to the
backplane. ensure that backplane wires are not
damaged. Also, do not cut AC LO and DC LO
wires out of the power harness as they are used
for power fail conditions on the Massbus and
on both Unibus A and Unibus B ports.

7.2.1 Mechanical
The RH 11 uses two hex-height modules and must be
installed in a mounting box that accommodates hex-height
modules. The modules are inserted in a double-system unit
backplane which is installed in the mounting box with four
thumbscrews. The double-system unit is oriented with the
bus cable slots in line with the other options.

After power connections have been made, check for power
shorts with an ohmmeter. Ensure that all modules are
firmly seated in the proper slots (Figure 7-1 ). Power up the
cabinet and measure voltages in accordance with values
listed in color code chart for power connections. After this
is accomplished, tum power off.

7.2.2 Electrical
Electrical installation describes the power cable connections, Unibus cable connections, and Massbus cable connections.

7.2.2.2 Unibus Cable Connections - The RH 11 is a twoport Unibus device capable of accepting two Unibus cable
systems, designated Unibus A and Unibus B.

7.2.2.1 Power Cable Connections - Power is distributed
to the RH 11 modules via two power cables which attach to
the printed circuit backplane assembly by quick-disconnect
tabs (refer to RHll Wired Assembly Drawing D-AD7009397-0-0). The power cables have Mate-N-Lok connectors on one end, which conne.ct to the Power Distribution

Unibus A Connections -- The Unibus A cable slots connect
the RHl1 to the processor controlling it. TI1C Unibus A
cable enters the RH 11 via slot AI, Bland (OIlt1C(tS to the
next device via slot A9, B9 (refer to Module Utilization
Drawing D-MU-RH 11-0-0 1).

7·1

UNIBUS
A IN
(BUSA)
(SEE NOTE 1)

UNI BUS

UNIBUS

0 UT

IN
(BUSB)

OUT
(BUSA)

(BU SB)

UNIBUS

(SEE N OTE 2) (SEE NOTE 2) (SEE NOTE 3)

M7297

PARITY
CONTROL
(PAC)

BUS
CONTROL
(BCT)
MODULE

DATA
BUFFER

CONTROL
(DBC)

MASS BUS
TRANSCEIVER
(MBSA)

MASSBUS
TRANSCEIVER
(MBSB)

MASS BUS
TRANSCEIVER
(MBSC)

MODULE

I
II

SM ALL
P ER.
CON TROL
(DE V. 1)
(OPT! ONAL)

"7296._

UNIBUS
POWER
FAIL
DRIVER
(BUSS)

SMALL
PER.
CONTROL
(DEV.2)

SMALL
PER.
CONTROL
(DEV 3)

(OPTIONAL)

G 727
G727
G727
(SEE NOTE 4) (SEE NOTE 4) (SEE NOTE 4)

I UNIBUS
POWER
FAIL
DRIVER
(BUSA)

CONTROL

STATUS
REGISTERS
(CSR)

____J~_ .~.- .-.- -.- - . - '_ .._
~_J

i
NorES
MAY BE EITHER M920 (CONNECT(ON FROM ADJACENT DEVICE) OR
BCIIA CABLE (CONNECTION FROM ANOTHER BOX OR NON·ADJACENT
DEVICEI

THE SMALL PERIPHERAL CONTROLLER SLOTS MAY CONTAIN A VARIETY
OF PDP·ll OPTIONS. THE OPTION MAY CONSIST OF A SINGLE QUAD
MODULE BOARD (SLOTS C, 0, E, & F) OR A DOUBLE HEIGHT CONTROLLER
BOARD (SLOTS C & D) WITH AN Ml05 ADDRESS SELECTOR MODULE (SLOT
E) AND AN M782l INTERRUPT CONTROL MODULE (SLOT F).

IF NO OPTION IS PRESENT IN THE SMALL PERIPHERAL CONTROLLER SLOTS.
G727 GRANT CONTINUITY MODULE(S) MUST BE INSERTED IN SLOTS D.

MAY BE M9.JOO (TERMINATION AT BEGINNING OR END OF UNIBUS B) OR
BCIIA CABLE (CONNECTION TO OTHER BUS B DEVICES).
MAY BE M920 (CONNECTION TO ADJACENT DEVICE). M930 (TERMINATION
AT END OF UNIBUS AI. OR BCllA CABLE (CONNECTION TO NEXT BOX OR
NONADJACENT DEVICE)

11-2384

Figure 7-1

RHll Module Utilization

7-2

arbitrator. If one RH 11 is connected to Unihus
B, the RH 11 is electrically connected at at the
beginning of the bus with the M9300 selected
to act as an NPR arbitrator. One M9300 Unibus
B Terminator module is placed in slot A8, B8
of the RHI\' Jumper WI on this module Illust
be cut to enable the arhitration Illgic. Connection to other devices on Unibus B. such as
memory, are made via BC I 1A cable connected
to slot A7, B7. The second M9300 Unibus B
Terminator module is installed in the last device
on Unibus B. Jumper W2 is removed for
terminating the Unibus with no processor connected.

Connections to slot ALB 1 arc made via the BC 11 A Unibus
cable if the RH 11 is the first Unibus A device in the
mounting box. Otherwise, connection to AI, B 1 from the
preceding device is made by an M920 Unibus Jumper
module. Connection to the next adjacent device on the
Unibus is made via the M920 Unibus Jumper module, or is
made hy BC 11 A cable if the device is not adjacent.

NOTE
If the RH II is the last device on Unibus A, an
M930 Terminator module is installed in slot
A9,89.

Unibus B Connections - Unibus B connections are generally made in systems with multiport memories. When the
Unibus B port of the RHll is not used, an M9300
Terminator module (with jumper WI cut) should be
installed in slot AS. B8 to temlinate Unibus B signals into
the RI 111. The second M9300 Terminator module should
not be used in order to conserve power consumption. If the
Unibus B port of the RH 11 is used, connections are
determined on the basis of whether a processor is connected to Unibus B. These connections are described below.
J.

NOTE
In this case, an M930 Terminator module
can be substituted for the M9300 Unibus
B Terminator in the last device slot. If
more than one RH 11 is installed, the user
may have extra M9300 modules as a
result of a particular configuration.
Figures 7-2, 7-3, and 7-4 show typical
Unibus configurations.

Processor on Unibus B - If a processor is
connected to Unibus B, it is electrically connected at the beginning of the bus. In this case,
the M930 Terminator modules supplied with
the processor are used for bus termination, and
the two M9300 UnibusB Terminator modules
Sll p plied wi th the RH 11 are not used.

7.2.2.3 Massbus Cables -- Massbus connections to the
RH 11 are made via three 40-conductor ribbon cables. These
cables plug into three M5904 Transceivers in the RH 1 I ~lIld
are designated Massblls Cable A, Massbus Cable B, and
Massblls Cable C. The connec tions arc made as shown
below:

NOTE

Massbus Cable A -- Install in M5904 module in slot C4,

The M9300 Terminator may be used as a
substitute for the M930 Terminator if the
jumpers are selected correctly.

04.
Massbus Cable B ~- Install in MS904 module in slot C5,

05.
11le Unibus B cable connection to the RH 11 is
made via slot AS. B8 with a BCIIA cable.
Connection from the RH 11 to the next device
is made via Be 11 A cable connected to slot A7,
B7. If the RHII is the last device on the bus,
the M930 or M9300 Terminator is installed in
slot A7, B7 instead of the BellA cable.
b.

Massbus Cable C - Install in MS904 module in slot C6,

06.
The Massbus cables are marked and should be inserted with
the edge-marking facing the module handles. To terminate
the Massbus, three HS70 modules (Massbus Transceivers
and Terminators) supplied with the RH II should be
plugged into the MS903 modules located in the last drive
on the Massbus in place of the M5903 modules (Figure
7-5).

No Processor on Unibus B- If no processor is
connected to Unibus B, a M9300 Unibus B
Terminator module must be sele :ted as an NPR

7-3

RH11

PDP-l1
M930

UNIA
IN

UNIB
OUT

UNIB
IN

UNIA
OUT

ABOl

AB07

AB09

M9300
TERM.
MODULE
(AB08l

Wl-0UT

MEMORY
UNIA
OUT

UNIA
IN

T
y

UNIA
OUT

W2-IN
w3-IN

SEE
NOTE 1

UNIBUS A

L-~END OF

---v

UNIBUS A

BEGINNING _~
UNIBUS A

~NiSUS

NOTE r
Install M930

terminator if lost device on UNIBUS A.
1·-2220

Figure 7- 2 Single Port UNIBUS Configuration
UNIBUS B

M9300
WI -IN
W2-0UT
W3-IN

RH11

BEGINNING
UNIBUS
B
UNIA
OUT

UNIA
IN
UNIB
IN

UNIB
OUT

ABOl

AB07

M930

UNIA
OUT

AB09

WI-OUT
W2-IN
W3-IN

MEMORY

PDP-11/45

M9300
AB08

SOLI D STATE MEMORY

UNIA
IN

UNIA
OUT

SEE
NOTE 1
UNIB
OUT

UNIB
IN

UNIBUS A

TO
END OF
UNIBUS
A

NOTE !.
Install

M930 terminator if lost device on UNIBUS A.
U-2Z21

Figure 7-3 Dual Port Configuration -- Memory on UNIBUS B
7-4

MEMORY

PDP-ll

UNIB
OUT

UNIB
IN

UNIBUS B

RH11
UNIA
IN
ABO'

END

UNIA
OUT

C~NIBUS
ABO a

M9300
TERM.
MODULE

AB09

W'-IN
W2-0UT
W3-0UT
SEE
NOTE

SEE
NOTE 2
UNIB
IN

UNIB
OUT

TO
END OF
UNIBUS
A

UNIBUS A

NOTES
1. In lhis conI i9uro1 ion can be replaced by M930.

2. Instoll M930 terminator "

lost deVice on UNIBUS A.

Figure 7-4 Dual Port Configuration - Memory & Processor on UNIBUS B

(BEGINNING OF MASSBUS)

(LAST DRIVE ON MASSBUS)

TM02

RHll

M5904
SLOT
C004

M5904
SLOT
C005

M5904
SLOT
C006

MASSBUS
CABLE A

I
MASSBUS
CABLE B

I
MASSBUS
CABLE C

TM02
M5903
SLOT
AB04

MASSBUS
CABLE A

M5903
SLOT
AB05

MASS BUS
CABLE B

M5903
SLOT
AB06

MASSBUS
CABLE C

M5903YA*
SLOT
AB04

\\----- t-----

II
II

1..

--1\

,...

M5903YA*1
SLOT
AB05

M5903YA
SLOT
AB06

ItM5903YA terminating modules mHy he fp.piM:ed by

M5903 modules wilh H870 1m minalor card, which
plug tIlto the modules,
II· 2771

Figure 7-5 MASSBUS Cable System Configuration

7-5

7.2.2.4 AC LO, DC LO - AC La and DC La signals from
the power supply which supplies RH 11 power must be
connected to the RH 11. The wires supplying these signals
WILL NOT BE CUT from th~ power harness. There will be
only one AC LO and one DC LO pm~'er fail connection to
each Unibus jC)f devices rnounted in the same mounting box
and shan'ng the same power supply. Otherwise, power fail
conditions would latch up due to positive feedback to the
power fail logic. If a power fail connection for AC La and
IX' La is al ready made to a Unibus from a device in the
same Jll~Hmting box, the M688 Power Fail module in the
RIll 1 for that Unibus is removed. TIle M688 module for
Unibus A is located in slot E5 and the M688 module for
Unihus B is located in slot E4. TIle following is a summary
of power fail cont1guration rules.
1.

7.2.4.1 BeT Module - TIle BCT module contains jumpers
for register selection. BR level interrupt. NPR latency.
vector address. and missed transfer error.

Register Selection TIle RH II is capable l)j' responding to
30 possible Unibus addresses. The number of addresses.
however, is dependent on the Massbus device. For the
TU 16/TM02 tape drives, the following jumper configuration should be used (D-CS-M7295-0-J. sheet 2).
Jumper in = binary 0

For each mounting box, there is only one AC
LO and DC La power fail connection to a
Unihus from the power supply.

Jumper

Address
Bit

Jumper In/Jumper Out

WI
W2
W3

12
11
10
9
8
7
6
5

OlJT

W4
W5
Wb

W7
W8

Power supply AC LO and DC La must always
be wired to each RI 111 via the power harness.
J.

Power fail signals may only be disconnected
from a Unibus in an RH II by removing the
appropria te M688 Power Fail Driver module.

-+.

Power supply AC LO and DC La should be
disconnected from all other options mounted in
the same hox as the RH 11 if they do not need
those signals for internal operZltion.

IN
OUT

[N
OUT
IN
IN
OUT

Jumpers WI through W8 select the block of Unibus
addresses that the TUI6/TM02 responds to. The standard
addressing block assigned is 772440 through 772472. If the
jumper is left in, a binary 0 is encoded.
The jumpers in E3 (D-CS-M7295-0-1, sheet 2) are selected
for the appropriate number of registers (14) in the
TU16/TM02 system.

Figures 7-6. 7-7, ~lI1d 7-8 show thre~ typical power fail
configurations which are configured in ac,.:ordance with the
above mentioned rules.
7.2.3 Small Peripheral Controller Slots
nle RH I I provides space for mounting lip to three small
peripheral controllers on Unibus A. These three small
peripheral controller sl(lts may contain a variety ofPDP-J 1
uptions. TIle option may consist of single quad-height
hoards (slots C. 0, E, and F) or double-height control
h()ards (slots C and D) with an MIOS Address Selector
m()dule (slot E) and an M782 I Interrupt Control module
(slot F J. If no option is installed in a small peripheral
controller slot., a G727 Grant Continuity module is installed
in empty slots 07, 08 and/or 09 to jumper the Unibus A
bus grant lines through the unused option space.

Slot

Jumper

Jumper In/J umper Out

1 - 16
2 15
3 - 14
4 - 13
S --- 12 (2)
6 -- J I (4)
7--10(8)

IN
IN

8 -- q (16)

OUT
OUT
OUT
OUT
OUT
IN

BR Level Interrupt - 111(' pnonty jumper plug for the
RHll is normally set for the BR5 level. This plug is located
in E57 (refer to D-CS-M7295-0-1, sheet 7).
NPR Latency - Special circuitry is incorpora ted 011 the
BCT module to improve NPR latency time for devices
connected to the Unibus. This circuitry is enahled via
jumper WI8 (D-CS-M7295-0-1 ,sheet 7). This jumper should
be left in, which enables the NPR latency feature. Not all
PDP-] 1 processors will work with this special feature.

7.2.4 Jumper Configurations
TIle following paragraphs describe the various jumper
configurations on the BCT (M7295), DBC (M7294) and the
CSR (M 7296) modules.

7-6

UNIBUS B

UNIBUS A

RHll
0

c:r

c:r
(/I

...J

(/I

:::>

c:r
c:r
(/I

:::>

l'\

M688
E05

M688
E04

M7295
ABCDEF02

C100

C84

~~~

EXPANDER
MOUNTING
BOX

...J

OPTION
A

OPTION

NO
POWER FAIL
CONNECTIONS
MADE TO
UNIBUS

POWER SUPPLY
AC
LO

DC
LO

SUPPLY AC LO

SUPPLY DC LO
NOTE
One RH11 mounted with other options in
an expander mount i ng box.
11-2218

Figure 7·6 Typica1 Power Fail Configuration for RHll & Options Mounted in Same Expander Box

7·7

.-------------_+----4>-----!f----...- UN I BUS A
~--~----r_----_+----4_---------_r----~.----~----~-----~--_+----.------

RH11

RH11
()

..J

..J
U
0

(])

(f)

::>

::::>

::>

.,J

U
<%

ro
(f)

(f)

::>

en
::>

..J

::>

(f)

::>

9
<%
<%

::>

r
M688
E04

M688
E05

I
I

SEE
NOTE 1

EXPANDER
MOUNTING
BOX

SEE
NOTE 1

M7295
ASCDEF02

M7295
ABCDEF02

C100

C84

C100

C84

+5V

r;1

OPTION
A
NO
POWER FAIL
CONNECTIONS
MADE TO
UNIBUS

POWER SUPPLY

+5V

DC
LO

SUPPLY AC LO
L - _ . _ _..__ .._._. _____... _ _ _ _ .. _ _ _ _ ._ .... _.

._.. __ .___ ... _.. _______.._________-=-S-=-UP:...:P-=L::..:Y--=D.:::..C--=-LO~_ _ _ _ _ _ _ . _ . _ .__ _

NOTE 1
Disconnect power foil signols from SUSA by removing M688 in
slol E05 8 f'om 8USS by removing M688 in slot E04.
11- 2216

Figure 7- 7 Typical Power Fail Configuration for Two RHIIs Mounted in Same Expander Box

UNIBUS B

UNIBUS A

CPU

...J

RH11
0

...J

c:t

...J

c:t

c:t
c:t

C/)

:::l
CD

:::l
CD
l\

C/)

c:t
c:t

C/)

:::l
CD

r'~ - - jl,
I
I
SEE

NOTE 1

--4

M7295
ABCDEF 02

r::q

PROCESSOR
MOUNTING
BOX

C/)

M688
E04
INTERNAL
POWER FAIL
SIGNAL USE

...J

-- J

OPTION

A
NO
POWER FAIL
CONNECTIONS
MADE TO
UNIBUS

M7295
ABCDEF 02

~:~

+5V

POWER SUPPLY
AC

+1v

DC
LO

Lf
SUPPLY AC LO

SUPPLY DC LO
NOTE 1
Disconnect power foil liQnols from BUSA by
removinQ M688 in slot E05.
,,·2217

Figure 7-8 Typical Power Fail Configuration for RHll and CPU Mounted in Processor Box

7-9

Vector Address Jumpers - TIle interrupt vector transferred
to the processor is jumper selectable via jumpers W11
through WI7, representing vector bits 2 through 8, respectively. When a jumper is left in, ~ binary 1 is encoded. The
TJU 16 system has heen assigned a vector address of
000224. The jumper configuration for this address follows:

Start Counter Jumpers - Different Silo fill capacities are
jumper selectable before starting a write operation onto the
disk drive. TIle jumper selections are listed below
(D-CS-M7294-0-1. sheet 9):
Jumper E66, Pins I -- 16
words.

Selects full capadty of (14

Jumper

Vector Bits

Jumper In/Jumper Out

Jumper E66, Pins 5 --- 12 - Selects 32 words.

WIl
WI2
W13
W14
W15
Wl6
W17

V2
V3
V4
VS
V6
V7
V8

IN
OUT
IN
OUT
OUT
IN
OUT

Jumper E66, Pins 7 - 10 --- Selects 16 words.

.MXF Jumper - Jumper Wl9 (D-CS-M729S-0-I, sheet 9) is
used to disable detection of MXF errors and is used during
special main tenance procedures. Normal operation requires
that jumper W19 be left in.
7.2.4.2 DBC Module - TIle DBC module contains jumpers
for NPR cycle selection. Unibus parity, and start counter
capacities.
/VPR C.J'cle Selection Jumpers - There are two jumpers

used to select the type of cycle implemented when doing
NPRs. Jumper E66 (3-14) (D-CS-M7294-0-1, sheet 2)
selects the RH 11 to perform one memory reference for
each NPR request. In the TJU16 system, this jumper is
removed to allow back-to-back memory cycles to occur.

NOTE
Only the jumper representing the desired Silo
capacity should be connected. TIle other
jumpers should be removed. For the TJU 16
system, the 64-word jumper (E66, pins 1 - 16)
should be connected .
7.2.4.3 CSR Module - The CSR module con tains a
jumper to allow for Unibus A selection only. The jumper is
designated WI and is shown on D-CS·M7296-0-J, sheet 2.
The purpose of WI is to override the abili ty of the program
to select Unibus B data transfers; with jumper WI connected, only Unibus A operations are allowed. The jumper is
nonnally left in.
7.3 VISUAL INSPECTION
Before the diagnostics are run, the following visual inspections should be made.

Jumper E66 (2-15) (D-CS-M7294-0-1, sheet 2) takes
advantage of dedicated Unibus B systems by allowing the
RH 11 to transfer complete consecu tive blocks of data
without giving up the Unibus. A dedicated Unibus B system
is one in which the RH 11 is used exclusively as a Unibus B
master. To implement this feature (called BUS HOG mode),
the one-cycle jumper and E66 (2--15) must be cut.

Unibus Parity Jumpers- The RHII option can be selected
for 16 data-bit (plus two parity bits) transfers or 18 data-bit
transfers. Unibus A and Unibus B can each be selected
individually via jum pers WI and W2 (D-CS-M7294-0-1,
sheet g). Jumper WI, if left in, allows parity error code
detection on Unibus A when the RH J 1 is doing DATI
operations. If jumper WI is removed, the Unibus A PA and
PH parity lines are used as data bits 16 and 17, respectively.
Jumper W2 serves the same function for Unibus B as
jumper W I does for Unibus A. The jumpers are normally
left in.
7-10

Verify that all modules have been configured
correctly in accordance with the RH 11 Module
Utilization List D-MU-RHII-O-O I.

Ensure that al1 modules are firmly seated in the
system backplane assembly.

Inspect backplane wiring fur broken wires or
damaged pins. Repair or replace as required.

Ensure that the power cable is ftmlly attached
to the Fast-on tabs on the system backplane
assembly and that the Mate-N-Lok connector is
seated firmly in the power distribution panel on
the chassis.

Clean air filters at top of cabinet.

Ensure that all Unibus and Massbus cables are
properly terminated and arc t1rmly seated.

Check cabinet fans for proper operation.

7.4.2 TM02 and TU16 Installation

7.4 INSTALLATION PROCEDURE FOR A TJU16
ADD-ON
The TJU16 consists of an RHll Massbus Controller, a
TM02 Tape Controller. and a TU 16 Slave Transport.
7.4.1

RH 11 Installation
1.

Unpack the RH 11 and mount it in the processor or expander box.

Remove the M9300 and M5903Y A modules
from the RHlllogic assembly. The M9300 will
be used for jumpering Unibus A to the RBI 1.
The three M5903Y A modules will be used in
the TM02.

Connect the power harness to the RBI 1 logic
assembly in accordance with drawing
UA-RHII-O-O.

Turn on the power for the processor or
expander box and verify that the +5 V, -15 V,
and +15 V power are available at the power
distribution panel of the processor or expander
box.

Turn off the power for the processor or
expander box and plug the three Mate-N-Lok
connectors of the power harness into the power
distribution panel.
(Refer to drawing
UA-RHII-O-O.)

Unpack the TM02/TU16 cabinet and bolt it to
the system cabinet.

Install the cabinet ground strap.

Set the 861 circuit breaker to the off position.

Set the 861 LOCAL/OFF/REMOTE switch to
OFF.

Check the power receptacle to be used for the
861 for correct hot, neutral, and ground connections. Refer to the 861-A,B,C Pmver Controller
Maintenallce
Manllal.
DEC-00-H861A-A-D, for
the
plug and
receptacle diagrams for the particular 861 being
used.

Plug the 861 power cord to the power receptacle.

Set the 861 circuit breaker to the on position.

Set the 861 LOCAL/OFF/REMOTE switch to
LOCAL.

Verify the following:

Turn on the power for the processor or
expander box and check the voltages in the
RH 11 backplane:
Voltage

Harness Wire Color

+5 V
-15 V
+15 V
GND

Red
Blue
Gray
Black

If necessary, adjust the appropriate voltage
regulator in the processor or expander box
power supply.

Turn off the power.

Connect the Massbus cables to the RBI 1 as
described in Paragraphs 7.4.3 and 7.4.5.

Cabinet fan operating

TM02 fan operating

TU16 PWR indicator lit.

TM02 power LED (bottom LED) lit.

10.

Remove the TU16 shipping brackets and slide
the transport out.

11.

Check the power supply voltages listed in
Tables 7-1 and 7-2.
NOTE
The voltage settings are critical. Do not
attempt to adjust the voltages unless a
well-calibrated scope or digital voltmeter
is available.

7-11

Table 7-1
TUl6 Backplane, Regulated Voltages

Designation

Pin No.

Voltage (Vdc)

+5 V
+12 V
-6.4 V
+12 V (NRZ)
+5 V (PE)*
GND

DOIA2
B04S1
C04N2
C02J2
C02J2
DOIC2

+5.25
+12.05
-6.35
+11.875
+5.6

Tolerance (Vdc)
±O . OS
±O.OS
±0.05
±0.125
±O.l

Control
Poten tiometer
R16
R37
R44
R26
R57

---------~.----------- -----~--------.-

-------

*This voltage must be checked out when on-line in the PE mode. (The LED next to the bottom on the TM02 is lit when in
PE mode.)

Table 7-2
P4 Connector, Unregulated Voltages

-----_.-...-_._-_.

12.

._-

_ _--------_._----..

Designation

Wire Color

Minimum Voltage (V dc)

+17 V
-17 V
+18 V
-L8 V
GND

Orange
Yellow
Pale Green
Blue
Black

+17.0
-17.0
+18.0
-18.0

------

Load a scratch tape on the TU16 and check out
all manual functions:
Load
Brake Release
Forward
Reverse
Rewind
Start
Stop

13.

Connect the slave bus cables to the TU16 as
described in Paragraphs 7.4.4 and 7.4.5.

14.

Set the 861 LOCAL/OFF/REMOTE switch to
OFF.

IS.

Slide the TU] 6 back into th~ cabinet.

16.

Remove the shipping brackets from the TM02
and slide it out of the cabinet on its slides.

7-12

17.

Remove the top and side covers of the TM02.

18.

Set the 861 LOCAL/OFF/REMOTE switch to
LOCAL.

19.

Check the power supply voltages listed in Table
7-3 and adjust if necessary.

20.

Set the 861 LOCAL/OFF/REMOTE switch to
OFF.

21.

Connect the Massbus and slave bus cables going
into and out of the TM02 as described in
Paragraphs 7.4.3, 7.4.4, and 7.4.5.

22.

Install the remote power control cable to the
861 power controller.

23.

Set the 861 LOCAL/OFF/REMOTE switch to
REMOTE.

Table 7-3
TM02 Voltage Check

Designation

Pin No.

Wire Color

Voltage (Vdc)

Tolerance (V de)

+5 V
+15 V
-15 V
AC La
DC La

AOlA2, FOlA2
FO! VI
A04B2
A09HI
A09Jl

Red
Orange
Blue
Yellow
Violet

+5.00
+15.0
-15.0
+4.85
+4.85

±O.2S
±1.0
±1.0
±0.I5
±0.I5

2-+.

Apply system power. Verify that the TM02 and
TU16 power indicators are lit.

25.

Attempt to examine locations 772440 through
772472 (standard TJU 16 addresses). If the
processor traps, refer to Figure 7-9 for possible
addressing jumper problems.

26.

Attempt to deposit and examine all Is in
location 772446. If any bits are missing, check
out the Massbus cabling (Paragraphs 7.4.3 and
7.4.5 ).

7.4.3 RH 11 /TM02 Massbus Cable Installation
\1assbus cables must be installed between the RHII and the
T\102 as shown in Figure 7-10. The ribbed surface of the
\lassbus cables must face up at the RHII output, and the
smooth surface of the cables must face up at the input of
the TM02. Refer to Paragraph 7.4.5 for cable identification
markings.

Mid-bus TM02s use M5903 modules.

The end-of-bus TM02 (as in the case of a single
TM02) uses M5903Y A modules.

7.4.4 TM02/TU16 Slave Bus Cable Installation
Slave Bus cable connections between the TM02 and the
TU16 and between daisy-chained TU16s are shown in
Figure 7-11. A half-twist in the slave bus cable is not
required between the TM02 and the first (or single) TU 16,
but if multiple TUI6s are installed, a half-twist of the slave
bus cable must be used between TUI6s. Refer to Paragraph
7.4.5 for cable identification markings.

CAUTION
All slave bus cables must be installed with the
red line toward the module handle. Otherwise,
the +5 V will be applied to a signal line instead
of the shield where it belongs.

CAUTION
All Massbus cables must be installed with the
red line toward the module handle. Otherwise,
a signal line will be grounded.

Mid-bus TU16s use different modules than an end-of-bus
(or single) TU 16.

If more than one TM02 is used:
1.

Control
Potentiometer
,----R50
R35
R26

Cable A
Cable B
Cable C

All TM02s must have the smooth side of the
BC06R Massbus cable up at the input of the
TM02, and the ribbed side up at the output.

7-13

Mid-Bus TUl6

End-of-Bus (or Single) TU16

M900I
M8913
M900IYA

M9001YB
M8913YA
M900I YC

M7295

JUMPERS

ADDRESS SELECTION
(FOR UNIBUS ADDRESS H2440)
JUMPER
JUMPER IN/OUT
ADDRESS BITS
BINARY ADDRESS
OCTAL ADDRESS

VECTOR SELECTION
(FOR UNIBUS VECTOR 224)
JUMPER IN = BINARY 1
WI7 W16 W15 W14 W13 W12 Wl1
OUT IN OUT OUT IN OUT IN

JUMPER
JUMPER IN/our

16\ 1±~iL12111 \10 Iil_8. .1_7. ______6~5---"-1-41iI:-IT]
o g 0log 0 \ 0 ~ 0I 0 ~ 0 0 ~ 0\1 ~ 0 ~~:AR:
-I

1 17 \

VECTOR BITS

MISCELLANEOUS JUMPERS

LEGAL REGISTER SELECT

(SELECTS DECIMAL 14 REGISTERS)
SLOT E3
BINARY
EQUIVALENT

JUMPER

1
2
3
4
5
6

7
8

M7294

TO
TO
TO
TO
TO
TO
TO
TO

64 SILO
BUS HOG DISABLE
ONE CYCLE
32 SILO
16 SILO

2
3
5
7

TO
TO
TO
TO
TO

W18

W19

MXF ENABLE

JUMPER IN/OUT

16
15
14
13
12
11
10
9

JUMPERS
E66
JUMPER

I NPR LATENCY
IN

IN
OUT
OUT
OUT
OUT
OUT

M7296

JUMPERS

USUS.B

DISABLE

NORMALL'f IN

JUMPER IN/OUT
16
15
14
12

IN
IN
OUT
OUT
OUT

MISCELLANEOUS
UBUS A PARITY
UBUS B PARITY

W1
W2

,----"--,,-11-2805

Figure 7-9 Jumper Summary

7-14

RH11
(CABLES MARKED CONTROLLER Al

EACH CABLE
MUST HAVE A
HALF TWIST

MASSBUS CABLE A OUT

M5904 (C/D04)
MASSBUS CABLE BOUT
M5904 (C/D05)

t-----------. . . .

--r-

MASS BUS CABLE C OUT
M5904 (C/D06)

J I

~----------------~~--r-~--<~

RIBBED SURFACE OF CABLE
MUST FACE UP AT THIS END

MID-BUS TM02
(CABLES MARKED CONTROLLER B)

EACH CABLE
MUST HAVE A
HALF TWIST

MASS BUS CABLE A OUT

~ ~M-A-SS-B-U-S-C-A-B-L-E-B--O-UT~

~R-

MASSBUS CABLE A IN

M5903

(A/B04)

M5903

(A/B05)

M5903

(A/B06)

MASSBUS CABLE B IN

MASSBUS CABLE C IN

MASSBUS CABLE C OUT

SMOOTH SURFACE OF CABLE
MUST FACE UP AT THIS END

RIBBED SURFACE OF CABLE
MUST FACE UP AT THIS END

END OF BUS TM02
(CABLES MARKED CONTROLLER B)
MASSBUS CABLE A IN
M5903YA

(A/B04)

MASSBUS CABLE B IN
M5903YA (A/B05)
MASSBUS CABLE C IN
M5903YA (A/B0S)

j
SMOOTH SURFACE OF CABLE
MUST FACE UP AT THIS END
" - 2801

Figure 7-10 RHII/TM02 Massbus Cabling Diagram

7-15

TM02 TO FIRST TU16
CABLE A OUT

TM02

M8907 (AB01) t - - - - - - - - . , /
CABLE BOUT
M8908YA (AB02)t-_ _ _ _ _ _-.,~
CABLE C OUT

TO FIRST TU16
1. SMOOTH SIDE OF CABLE UP

M8908 {AB03)1--_ _ _ _ _~

2. RED LINE TOWARD MODULE HANDLE
3. CONTROLLER DESIGNATION "8"

'-----,----

4. DIRECTION DESIGNATION "OUT"

MID-BUS TU16
( MULTI TRANSPORT SYSTEM)
CABLE A IN

CABLE A OUT

TU16

_ _ _ _--I M9001 (AB01)
CABLE BIN
FROM TM02 OR
PREVIOUS TU16

CABLE BOUT
TO NEXT TU16

- - - - - - - t M8913 (CD01l
CABLE C OUT

CABLE C IN
M9001 YA (EF01l

OUT
1. RIBBED SIDE OF CABLE UP
2. RED LINE TOWARD MODULE HANDLE
3. NO CONTROLLER DESIGNATION
4. DIRECTION DESIGNATION "OUT"
5. HALF TWIST IN CABLE BETWEEN
THIS AND NEXT TU16

1. SMOOTH SIDE OF CABLE UP
2 RED LINE TOWARD MODULE HANDLE
3. NO CONTROLLER DESIGNATION
4, DIRECTION DESIGNATION "IN"

END-OF-BUS TU16
CABLE A IN

-TU16
M9001YB (AB01l

CABLE B IN

FROM TM02 OR
PREVIOUS TU16
1. SMOOTH SIDE OF CABLE UP

2. RED LINE TOWARD MODULE HANDLE
3. NO CONTROLLER DESIGNATION
4. DIRECTION DESIGNATION "IN"

M8913YA (CD01)

CABLE C IN
M9001 YC (EF01)

,,- 2802

Figure 7·11 TM02/RH16 Slave Bus Cabling Diagram

7·16

7.4.5 \1arkup of Massbus and Slave Bus Cables
Both surfaces of each end of the Massbus and slave bus
cables are stamped as shown in Figure 7-12. The stamps are
marked up to indicate cable designations at the time the
cables arc installed. Mark the BC06R Massbus cables as
follows when installing them:

THIS SIDE UP

PART NO.
BC06R-10

Cross out the designation THIS SIDE UP on the
under side of the cable.

Cross out the CONTROLLER designation that
does not apply. Cross out B when plugging into
the RBI 1 and cross out A when plugging into
the TM02.

Cross out the CONNECTOR MODULE designations that do not match the cable letter being
used.

RED LINE MUST BE
ON SIDE CLOSEST
TO MODULE HANDLE

SMOOTH SIDE UP

Cross out IN for the output cables and cross
out OUT for the input cables.
11- 2804

Figure 7-13 Marked-Up Massbus Cable
THIS SIDE UP

\d\ilg\i\tlall\
PART NO.

7.5 DIAGNOSTIC MAINTENANCE
The diagnostic programs described herein are employed
with the TJU16 system. Refer to the applicable diagllostic
operating procedures for detailed information.

7.S.1 Data Reliability Diagnostic DZTUA

~
~

11- 2803

Figure 7-12 Massbus Cable Stamp

This diagnostic provides for evaluation and debugging of
magnetic tape drives. The program is capable of exercising
any tape drive that is compatible with the Massbus and the
TM02. Any number of drives up to eight (single or
multi-drive systems) may be tested by a single execution of
the program. This flexibility is possible because the
program has no t1xed parameters or testing sequence. The
entire test plan, including parameters and operating
sequence, is determined by the operator through responses
to Teletype@ requests and setting of console switches.
The program prOvides for testing of all tape drive functions
such as writing, reading, rewinding, tape positioning,
EOT - BOT sensing, and assumes a properly operating
RHII Massbus controller and TM02 tape controller. During
a test cycle, checks are made for status errors, data errors,
position errors, word count, and memory address errors
wherever applicable.

Figure 7·13 shows an example of a cable that is marked up
to be plugged into the M5903Y A module in slot A/B06 of
an end-of-bus TM02.

The program will attempt to perform any operation.
Therefore, caution should be used to assure that the unit
@Teletype is a registered trademark of Teletype Corporation.

7-17

can perform as requested. For example, an attempt to read
tape that has not been written on, yields unpredictable
data. However. if a tape has been written with this program,
it can be read ::IS often as desired without being rewritten.
This is a good procedure to use for testing tape compatibility.

TM02/TU16 Basic Functions: The following fourtC'C'n tl'sts
will ensure operation of the Magtape bask functions.
FTII:

NOP Test: This test will ensure that the NOP
function executes with no error.

FT 12:

Rewind Test: This test will ensure that the rewind
function will position the tape to BOT with no
error.

FTl3:

Write/Read Test: This test will ensure that the
unit under test can write and read in all densities.

FT14:

RHll Tests: The first ten tests will perform basic RHl1
operations as far as possible without requiring the
T\102jTU16 itself.

Space Test: This test will ensure that proper
positioning is maintained by both space forward
and reverse.

FTlS:

Erase Test: This test will ensure that the erase
function will indeed erase ta pes.

FTI:

RH 11 Addressing: This test will ensure that the
RH 11 will respond without causing a bus trap to
all TM02 register addresses in sequence starting at
the address of CSI entered by the operator.

FTI6:

Tape Mark Write/Read: This test will ensure that
a tape mark can be written and read in both PE
and NRZ.

FT2:

RH 11 Register Bits Read/Write: This test will
ensure that all bits of the RHI1 write/read
registers can be set and reset.

FTI7:

Tape Mark Space Test: This test will ensure that
spacing will be terminated by recognition of tape
mark both in PE and NRZ.

FT20:
FT3:

RHl1 Initialize: This test will ensure that an
RH 11 initialize (bit S of CS2= 1) will indeed clear
the RHll errors.

Write Check Test: This test checks write check
forward and reverse in both PE and NRZ modes.

FT21:

Erase Head Test: This test will ensure that the
erase head itself is operating.

Silo Test l: Tllis test will ensure that a read from
an empty silo will cause DLT to set.

FT22:

Buffered Command: This test will ensure that the
TM02 will accept and execute another command
while its selected slave is rewinding.

FT23:

Read in Preset: This test will ensure that unit 0 is
rewound and set to 800 bpi normal. (only if slave
o is selected.)

FT24:

Rewind: Orf line this test will ensure that the unit
will rewind and go off line. (not if in continuous
cycle.)

7.5.2 TM02/TU16 Basic Function Diagnostic DZTUB
This diagnostic provides for testing all the functional level
operations of the TM02/TU16 Magtape System. The
following is a list of all tests in their proper sequence. A
basic description of each test is provided to aid in
understanding the error messages associated with each one.

FT4:

FTS:

FT6:

Silo Test 2: Tllis test will ensure that both the JR
and OR bits will correctly respond to loading of
the silo with all zeroes followed by a word of all
ones.
Silo Test 3: This test will write and then read the
entire silo to ensure that data can be properly
loaded into and read. From the silo the proper
status of IR and OR are also checked.

FT7:

Silo Test 4: This test will ensure proper RH I 1
response to silo overflow.

FTIO:

Silo Test S: This test will ensure silo reset by
RBI 1 iniiialize.

7.5.3 TM02/TU16 Control Logic Test DZTUC
This diagnostic sequentially tests all control logic and data
formatting within the TM02 formatter. Each test will
attempt to isolate failures to the module level and provide
printout information that will identify the failing module.

7-] 8

There are two major areas of testing -- control logic and
data formatting. The control logic testing will test all error
and status conditions as well as address protocol and
operational logic sequences. On the first line, the printout
will con tain a header which calls out the test number,
function being tested, and the suspected module or
modules. The second line will contain information reo
garding the actual error. Both expected and actual results
will be givcn. Line three will show the contents of the
major registers at the time of the error and line four will
print the iteration number as applicable.
The data formatting section will test all data formats and
transfer paths in all possible combinations. These tests will
print a header containing the test number and a description
of the wraparound function under test. A list of major
registers with expected and actual values will follow the
header. Any bad data will be printed (per character)
following the register information or following the header if
no status errors were encountered.
7.5.4 TM02 Drive Function Timer DZTUD
This diagnostic measures the time required and the gap sizes
produced by the TM02/TU16 Magtape Drive. The program
requires a PDP· 1 I family central processor with 4K
memory and with up to 64 TMll/TM02 Controller/
\1agtape Stations.

Two types of errors are detected by this program hardware errors and incorrect function times.
7.5.5 TU16 Utility Driver DZTUE
This diagnostic uses a brute forcc routine to cOlltinul)llsly
execute an operation or series of operations, regardless of
the results. Because of the complexity of the TUl6 tape
system on the Massbus, it is not always possible to provide
for every contingency in normal programs. Therefore, this
utility driver will allow an operator to execute anything
desired in any order. There are no error checks or printouts
made and. any variation from preset sequences and values
are made by changing the appropriate memory locations:

The program requires the operator to have knowledge of
the TU16 tape system as operated with the RH 11 Massbus
controller. The operator must be able to decide which
sequence of operations is required and values to assign to
the various parameters required to execute them.
7.5.6 Data Tape Create DZTUF
This diagnostic is not a test program but a supplement to
both the TMll/TUlO and TM02/TU16 data reliability
programs. The purpose of this supplement is to allow the
operator to create a paper tape of whatever data pattern is
desired and is used by the data reliability programs when
data pattern zero is selected.

7·19

APPENDIX A
INTEGRATED CIRCUIT DESCRIPTION

When data enters the second cell, the transfer of any data
word from a full cell to the next empty cell is automatic
and is activated by an on-chip control. Consequently. data
stacks up at the output to the memory while empty
locations "bubble" to the input of the memory. The
throughput time from input to output of the Silo is frolll 0
to 32 J.1.s (16 J.1.s typical).

A.I INTRODUCTION
This appendix contains descriptions of some of the integrated circuits used in the RH 11. Where applicable, logic
diagrams, schematics, and pin connection diagrams are
shown.
A.2 3341 64-WORD X 4-BIT SERIAL MEMORY (SILO)
TIle 3341 Silo Memory operates in a first in/first out mode
(FIFO). The output rate is independent of the input rate
and asynchronous or synchronous operation can be
achieved.

When data has transferred to the last cell ill the Silo.
OUTPUT READY (OR) is asserted high. indicating that
valid data is present at the output pins (MO through M3 on
each chip). Data is not shifted out of the Silo. however,
until the OUTPUT READY and SHIFT OUT signals to the
Silo are both asserted high. When the data is shifted out,
OUTPUT READY goes low. The output data is maintained
until both OUTPUT READY and SHIFT OUT go low. At
this point, the contents of the previous memory cell (if it is
full) are transferred to the output cell, causing OUTPUT
READY to be asserted high again. When the Silo memory is
emptied, OUTPUT READY stays low.

The four data inputs (DO through D3) are transferred to the
first memory location if both the Input Ready (lR) and
Shift In (SI) signals are asserted high (see Silo Memory
Block Diagram). After 250 ns to allow the data to stabilize,
IR goes low. However, data remains in the first memory
location until both IR and SI are brought low. At this
point, the data propagates to the next memory location, if
the location is empty. When the data is transferred, IR goes
high, indicating that the device is ready to accept new data.
If the memory is full, the IR signal remains un asserted

Table A-I lists the minimum, typical, and maximum times
for the above mentioned signals at 0° (' and at 70° C.

(low).

Table A-I
Control Signal Timing Specifications
0°
Signal

MIN

TYP

Input Ready High Time
Input Ready Low Time
Data Input Stabilizing Time
Data Output Stabilizing Time
Output Ready High Time
Output Ready Low Time

90
138

300
400
250
250
250
450

90
170

A-I

70°
MAX

MIN

TYP

MAX

300
400
250
250
250
450

450
520
400
400
350
650

155

64 WORD x 4 BIT SILO MEMORY

DATA
INPUT

INPUT 2
READY "'::~i----I
SHIFT ----!::3~_-~
IN

SILO
INPUT
STAGE
(I)

MAIN SILO
REGISTER
(62)

INPUT
CONTROL
LOGIC

MAIN REGISTER
CONTROL
LOGIC

SILO
OUTPUT
STAGE

DATA
OUTPUT

(J)

OUTPUT ...._~~15.:.... _ _ SHIFT OUT
.CONTROL
14
LOGIC
~-~~!..-..... OUTPUT READY
VGG
INPUT
READY
SHIFT IN

9
MASTER
RESET

SHIFT OUT
OUTPUT
READY
MO

JMI

O2
03

VOD

PIN CONFIGURATION FOR EACI-' 3341
SILO CHIP

A·2

Vss

11- 2426

The 7442 BCD-to-decimal decoder features familiar
transistor-transistor-Iogic (TTL) circuits with inputs and
outputs that are compatible for use with other TTL and
DTL circuits.

A.3 7442 4-LINE-TO-lO-LINE DECODERS (I-of-lO)
These monolithic decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are
connected in pairs to make BCD input data available for
decoding by the NAND gates. Full decoding of valid input
logic ensures that all outputs remain off for all invalid input
conditions.

TRUrH TABLES
BCD Input
D
0
0
0
0
0
0
0
0
1
1
1
1
I
1
I
1

C
0
0
0
0

1
1

1
1
0
0
0
0
I
1
1

B
0
0

1
1
0
0
1
I
0
0
1
1
0
0
1
1

Decimal Output

A
0
I
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
I

1
1
1

I
0

I
I
0
1
I
I

1
1

I
1
1
0
1
1
1
1
I
1
1
1
1
1
1

1
I
1
1
1
0

1
1
1
1

1
1
I
1
1
1
1
I
1
I
1

1
I
1
1
I
1
1
I

1
1

1
1
1
1
1
1
1
I
I
1

0
1
1
1
1

1
1
I
1
1
I
I
1

1
1
1
1
1
I
1

1
1
1

6
1

1
1
1
1
1
0

1
1
1
I
1
1
1
1
]

7
1
1
1
1
1

1
1
0
1
1
1
1
1
I
1
I

8
1
1
1

9
1
1
1
1
1
1
1
I
1
0
I
I
1

1
I
1
I
I
0
1
1
I
1
I
I

I
I

INPUT A

OUTPUT 1

OUTPUT 4

OUTPUT

INPUT C

.-t-+++-+ A

.>O---=---t-+-++.~ +·~iD--.-OOUTPUT

OUTPUTS
It-On3

INPUT

D~----~

--oOUTPUT 7

OUTPUT 9

A-3

A.4 7485 4-BfT MAGNITUDE COMPARATORS

The 7485 performs magnitude comparison of straight
binary and straight BCD (8421) codes. TIuee fully decoded
decisions about two 4-bit words (A, B) are made and are
externally available at three outputs.

TRUTH TABLE
CASCADING

INPUTS

~=~3, B3-~~2

,
I

A1,~~=.T~~o. s(-

A3 .... 83

AJ' 83

A3=83

A2<82

A3=B3

A3 = 83

X
X

A2=82!

A1 >81

x
x

A2 = 82

A 1 <.. B 1

x
x

AO' BO
AO<BO

X
X

A3 = B3

A2 = B2

A1 =B1

AO = BO

A3=B3

,A2=B2

A1=Bl

AO=BO

A 1 _~':.1__

AO._-_B_O_-'--._L_---L _ _
L_---L_ _H

_~~-=-.~~ _L_~~_~2
"<OT E

A=~~=~A~. I~~.

A2 = 8 ] 2 1 = B 1
A2-82
A1=Bl

A3 = 83
A3=B3
,

INPUTS

! A3 = 83 I A2 > 82

_ _ _._

- ---_..._--_._-_._----_.,-_._._--_.. •..._..• ...

:--------COMPARING - - - - - - - -

h'gh lellel, L = low level, X = i,.relevant

:;:qr~;:·· ·····-L/l
- ...•. -----.. --.~--

I
!..

iI .. If
I

~·t-

L .r
<>--+. t i-t·~
"~'2'+I~'
--'-'-1
H]

'I",

,~A :::~ ~.
{21

·e· 'N ~~1

·t·--+- . . .-t-!_.

! r

tl -t-..

"J'
AtQ
--_
81

1.1

0----+ .~.

'1\'1 I! :I -

! i :r

-···-t

I
ACe

lit . H~

.,~ . . ·~.~·l.
""~I-·{l21

Pin (16) = Vee. Pin (8) = GND

---.---.-..- ._--.,

..........

A.S 8223 2S6-BIT BIPOLAR FIELD-PROGRAMMABLE
ROM (32 X 8 PROM)
The 8223 is a TTL 2S6-bit read only memory organized as

32 words with 8 bits per word. The words are selected by
five binary address lines; full word decoding is incorporated
on the chip. A chip enable input is provided for additional
decoding flexibility, which causes all eight outputs to go to
the high state when the chip enable input is high.

:32 X 8 ARRAY

Vee • (16)

GND=( 8)
(
) II DENOTES
PI N NUMBERS
11- 23 82

A-S

A.6 8234 2-INPUT 4-BIT DIGITAL MULTIPLEXER
This device is a 2-input, 4-bit digital multiplexer designed
for general purpose, data selection applications. TIle 8234
features inverting data paths. TIle 8234 design has opencollector outputs which permit direct wiring to other
open-collector outputs (collector logic).

(I)

(2)

(6)

(5)

(10)

(11)

(15)

(14)

vee • (16)
GNO·(8)
( ) • DENOTES PIN
NUMBERS
11-2383

A-6

A.7 8242
EXCLUSIVE-NOR
COMPARATOR

4-BIT

DIGITAL

The 8242 digital comparator circ~it consists of four
independent Exclusive-NOR gates with each gate structure
having an open-collector output to permit multiple bit
comparisons. A 4-bit comparator network is formed by
connecting the independent outputs; such a network is
easily expanded by cascading the outputs.

A or F PACKAGE
13 12 11 10 9

a PACKAGE
8

14
13
12
11

1234567

9
8

1\ -04 7 4

I
I
I

I
I
I
I

TRUTH TA8LE

0
0
1
1

1
0
0
1

1
0
1

I
I
I

_-.J
to
11-0472

A-7

A.8 74157
QUADRUPLE 2·LINE TO
I·LINE
MULTIPLEXER
The 74157 quadruple 2·line to I·line multiplexer features
buffered inputs and outputs. All outputs are low when
disabled (enable high). The truth table and logic diagram
are shown below.

INPUTS

OUTPUT V

OUTPUTW

SN54/74157,

ENABLE SELECT A B

SN54Sn4S157

SN54Sn4S158

X X

L- X

H X

X L

X H

'---.

H = high level, L

--'---

= low level, X = irrelevant

'AoE~)--------------~
(3)

lBo-----__~------~~-~

2Bol6-)----~----4_~~
("14)
3AO-------r-----r-~

(13)

3Bo-------r---~~~

(11)

(10)

SELECT
Pin 16 = V ce ' Pin 8'" GND

ENABLEo-------~

Pin (16) = Vee. Pin (8) = GND

A·8

A.9 74174 HEX D-TYPE FLIP-FLOPS
The 74174 contains six flip-flops with single outputs. The
flip-flops contain direct clear inputs and buffered clock
inputs.

INPUT

OUTPUTS

In+ 1

tn = Bit time before clock pulse.
tn+1 ... Bit time after clock pulse.

A 0-;,1.;.;.31_ _ _ _ _ _ _-..1 OA

0-;,1...;41_ _ _ _ _-+--+--.I 08

161
Oc

1111
oo-------__
~~

151

171

1101

1131

O-I-l• ..;,..I-----4-4~OF

CLOCK

CLEAR

Pin (16) = Vee. Pin (8) = GND

A-9

11S1

A.10 74175 QUAD D-lYPE FLIP-FLOPS
The 74175 contains four Ootype flip-flops with dual
outputs. Each flip-flop has direct clear and buffered clock
inputs.

I~I

80--------

i"'Pl;T I

OUTPUTS:
otn+_l0 i

--_~- --l-_-~-.

In ~

tl1l

- - . -~--J

co----.--

Bit time before clock Dulse.

1:n+ 1 = Bit time after clock Dulse.

!131

DO~------·-_+~~

fLOCK

ClEAH

'91

~.4--.--~

Pin (16) = Vee. Pin (8) = GND

A-IO

A.II

74180

PARITY

CONTROL

GENERATOR/

CHEC~R

The 74180 is an 8-bit parity generator/checker featuring
odd and even outputs and control inputs to provide odd or
even parity operation. Word length is expandable by
cascading. The truth· table, pin connection diagram, and
functional block diagram are shown below.

INPUTS - - - . . \

o
TRUTH TABLE
OUTPUTS

INPUTS

IOF1'sAT EVEN ODD
I
o THRU 7
EVEN
EVEN
0

ODD
EVEN
ODD

EVEN ODD
I
INPUT INPUT EVEN

,
,
0
0

ODD

I
ODD
0

,
,

X= IRRELEVANT
~
INPUTS

EVEN ODD I·EVEN I·ODD GND
INPUT INPUT OUTPUT OUTPUT

o
,

IEVEN
OUTPUT

DATA
INPUTS
IODD
OUTPUT
6
7

ODD

INPUT~----------------------------~
EVEN~------------------------------~

INPUT
11-2384

A-II

A.12 74193 4-BfT BINARY COUNTER
The 74193 binary counter has an individual asynchronous
preset to each flip-flop, a fully independent clear input,
internal cascading circuitry, and provides synchronous
counting operations.

COUNT UP

COUNT DOWN

LOAD

MODE

Parallel Load

CLOCK

Count Up

CLOCK

Count Down

H = high level, L = low level, X ., irrelevant

Signal/Pin Designation
Signal Name
DATA INPUT A
DATA INPUT B
DATA INPUTC
DATA INPUT D
CLEAR
LOAD
DOWN COUNT
BORROW OUTPUT
CARRY OUTPUT
UP COUNT
OUTPUTQr\
OUTPUT Q 8
OUTPUT Q c
OUTPUTQD

Pin Designation
15
1
10

9
14
11
4
13
12
5
3
2
6
7

AlJRH{)W
-----~

OUT ru 1

CARRY
OUTPUT

DATA
INPUT A

DOWN
COUNT

OUTPUT Q A

UP
COUNT

DATA
INPUT B

OUTPUT 0B

DATA
INPUT C

OUTPUT 0c

OUTPUT 0D

A·13

A.13 74197 50 MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
This high-speed monolithic counter consists of four dc
coupled, master-slave flip-flops which are internally interconnected to provide a divide-by-two and a divide-by-eight
counter. The counter is fully programmable; i.e., the
outputs may be preset to any state by placing a low on the
count/load input and entering the desired data at the data
inputs. The outputs will change to agree with the data
inputs independent of the state of the clocks.

when the count/load is low, but will remain unchanged
when the count/load is high and the clock inputs are
inactive.
During the count operation. transfer of information to the
outputs occurs on the negative-going edge of the do(k
pulse. It features a direct clear which, when taken low, sets
all outputs low regardless of the states of the clocks.

This counter may also be used as a 4-bit latch by using the
count/load input as the strobe and entering data at the data
inputs. TIle ou tputs will directly follow the data inputs

J OR III DUAL-IIII-LiNE OR
W FLAT PACKAGE
(TOP VIEW)·

DATA INPUTS

Vee

CLEAR

'-C

•

CLOCK
I

CLOCK

GND

DATA INPUTS

ASYNCRONOUS INPUT

LOW INPUT TO CLEAR SETS QA
LOW.
Qs.Qc AND 0

.p," ossionmlnt. for thin circuli. are thl .om. for oil pockoO".
11-0412

SN74197 TRUTH TABLE
(See Note A)
COllnt
0
1

2
3
4
5
6

7
~

9
10
II
12
13
14
15

Output
QD

L
L
L
L
L
L
L
L
II
H
H
H
II
H
H
II

L
L
L
L
H
H
H
H
L
L
L
L
H
H
II
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L

H
L
H

NOTE A: Output Q A connected to clock-2 input.

A-14

DATA A o------------------~

COUNT/LOAD ~-----,.""

CLEAR~

PRESET

CLOCK! o---------------~-+----------4_--------_dT

OAT A 8

o>------------+--_+_~

PRESET

CLOCK 2 0 > - - - - - - - - - - - - - + - 4 _ - - - - - - - 1 1 - - - - - - - . 0

CLEAR

DATA C

DATA 0 0>------------+-4_-1

11-0411

A-IS

I
I

I
I
I
I

I
I
I
Iz

Reader's Comments

TJU16 MAGNETIC
TAPE SUBSYSTEM
MAINTENANCE MANUAL
EK-TJU16-MM-002

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What features are most useful?

I~ What faults do you find with the manual?
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I~ Does this manual satisfy the need you think it was intended to satisfy?
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I~ Does it satisfy your needs?

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Why? ___________________________________

Would you please indicate any factual errors you have found.

Please describe your position.

Name

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Street

Organization
________________________________--____ Department _________________________________

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