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EC-QC4GB-TE

January 1996

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Document:	Alpha 21066 and Alpha 21066A Microprocessors Hardware Reference Manual
Order Number:	EC-QC4GB-TE
Revision:	0
Pages:	314
Original Filename:

OCR Text

Alpha 21066 and Alpha 21066A
Microprocessors
Hardware Reference Manual
Order Number: EC–QC4GB–TE
Revision/Update Information:

Digital Equipment Corporation
Maynard, Massachusetts

This document supersedes the
Alpha 21066, 21066A, and 21068
Microprocessors Hardware Reference
Manual (EC–QC4GA–TE).

January 1996
While Digital believes the information included in this publication is correct as of the date of
publication, it is subject to change without notice.
Digital Equipment Corporation makes no representations that the use of its products in the
manner described in this publication will not infringe on existing or future patent rights, nor do
the descriptions contained in this publication imply the granting of licenses to make, use, or sell
equipment or software in accordance with the description.
© Digital Equipment Corporation 1994, 1995, 1996.
Printed in U.S.A.

AlphaGeneration, Digital, Digital Semiconductor, OpenVMS, VAX, the AlphaGeneration design
mark, and the DIGITAL logo are trademarks of Digital Equipment Corporation.
Digital Semiconductor is a Digital Equipment Corporation business.
IEEE is a registered trademark of The Institute of Electrical and Electronic Engineers, Inc.
Intel is a trademark of Intel Corporation.
Microsoft is registered trademark and Windows NT is a trademark of Microsoft Corporation.
OSF/1 is a registered trademark of Open Software Foundation, Inc.
Prentice Hall is a registered trademark of Prentice-Hall, Inc.
VxWorks is a trademark of Wind River Systems.
All other trademarks and registered trademarks are the property of their respective owners.

This document was prepared using VAX DOCUMENT Version 2.1.

Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvii

1 Introduction
1.1
1.2

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–1
1–2

2 Internal Architecture
2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Instruction Fetch and Decode Unit . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Branch Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Instruction Translation Buffers . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4
Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Integer Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Load and Store Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1
Data Translation Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2
Load Silos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3
Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3.1
Memory Barrier Instruction . . . . . . . . . . . . . . . . . . . . . . .
2.5
Floating-Point Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
IEEE Floating-Point Conformance . . . . . . . . . . . . . . . . . . . . .
2.6
Internal Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1
Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7
Instruction Pipeline Organization . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1
Instruction Pipeline Static and Dynamic Stages . . . . . . . . . .
2.7.2
Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.3
Nonissue Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8
Instruction Scheduling and Issuing Rules . . . . . . . . . . . . . . . . . .
2.8.1
Instruction Class Definition . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2
Producer–Consumer Latency . . . . . . . . . . . . . . . . . . . . . . . . .

2–1
2–3
2–4
2–4
2–5
2–7
2–8
2–8
2–9
2–10
2–11
2–12
2–13
2–14
2–15
2–15
2–15
2–16
2–17
2–18
2–19
2–19
2–19
2–20

iii

2.8.3
2.8.4
2.8.5
2.9
2.9.1
2.9.2
2.10
2.11
2.12
2.13

Producer–Producer Latency . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Issue Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual-Issue Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Required PALcode Instructions . . . . . . . . . . . . . . . . . . . . . . .
Architecturally Reserved PALcode Instructions . . . . . . . . . . .
Physical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–22
2–23
2–24
2–26
2–26
2–26
2–27
2–28
2–29
2–29

3 Privileged Architecture Library Code
3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
PALmode Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Invoking PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
Hardware Dispatch to PALcode . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
CALL_PAL Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Reserved Opcode Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
HW_MFPR and HW_MTPR Instructions . . . . . . . . . . . . . . . .
3.4.2
HW_LD and HW_ST Instructions . . . . . . . . . . . . . . . . . . . . .
3.4.3
HW_REI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
PALcode Entry Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
PALmode Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Translation Buffer Miss Flows . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1.1
Instruction Translation Buffer Miss . . . . . . . . . . . . . . . . .
3.6.1.2
Data Translation Buffer Miss . . . . . . . . . . . . . . . . . . . . . .

3–1
3–2
3–3
3–3
3–4
3–5
3–6
3–9
3–10
3–11
3–14
3–21
3–21
3–22

4 Internal Processor Registers
IDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Translation Buffer Tag Register . . . . . . . . . . . . . . . . . . . . . . .
Instruction Translation Buffer Page Table Entry Register . . .
Instruction Translation Buffer Page Table Entry Temporary
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4
Instruction Translation Buffer ZAP Register . . . . . . . . . . . . .
4.1.5
Instruction Translation Buffer ASM Register . . . . . . . . . . . . .
4.1.6
Instruction Translation Buffer Invalidate Single Register . . .
4.1.7
Instruction Cache Control and Status Register . . . . . . . . . . .
4.1.8
Exception Address Register . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.9
Exception Summary Register . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.10
Clear Serial Line Interrupt Register . . . . . . . . . . . . . . . . . . .
4.1.11
Serial Line Receive Register . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
4.1.1
4.1.2
4.1.3

4–1
4–1
4–3
4–5
4–6
4–6
4–6
4–7
4–11
4–13
4–15
4–15

4.1.12
Serial Line Transmit Register . . . . . . . . . . . . . . . . . . . . . . . .
4.1.13
Interrupt Request and Enable Registers . . . . . . . . . . . . . . . .
4.1.13.1
Hardware Interrupt Request Register . . . . . . . . . . . . . . .
4.1.13.2
Software Interrupt Request Register . . . . . . . . . . . . . . . .
4.1.13.3
Asynchronous Trap Interrupt Request Register . . . . . . . .
4.1.13.4
Hardware Interrupt Enable Register . . . . . . . . . . . . . . . .
4.1.13.5
Software Interrupt Enable Register . . . . . . . . . . . . . . . . .
4.1.13.6
Asynchronous Trap Interrupt Enable Register . . . . . . . . .
4.1.14
Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.15
Processor Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.16
PAL Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
LSU Internal Processor Registers . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
LSU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2
Translation Buffer Control Register . . . . . . . . . . . . . . . . . . . .
4.2.3
Data Translation Buffer Page Table Entry Register . . . . . . . .
4.2.4
Data Translation Buffer Page Table Entry Temporary
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5
Data Translation Buffer ZAP Register . . . . . . . . . . . . . . . . . .
4.2.6
Data Translation Buffer ASM Register . . . . . . . . . . . . . . . . .
4.2.7
Data Translation Buffer Invalidate Single Register . . . . . . . .
4.2.8
Virtual Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.9
Memory Management Control and Status Register . . . . . . . .
4.2.10
Flush Instruction Cache Register . . . . . . . . . . . . . . . . . . . . . .
4.2.11
Flush Instruction Cache ASM Register . . . . . . . . . . . . . . . . .
4.2.12
Alternate Processor Mode Register . . . . . . . . . . . . . . . . . . . .
4.2.13
Cycle Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.14
Cycle Counter Control Register . . . . . . . . . . . . . . . . . . . . . . .
4.3
PALcode Temporary Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Data Cache Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Internal Processor Registers Reset State . . . . . . . . . . . . . . . . . . .

4–16
4–17
4–23
4–23
4–24
4–25
4–26
4–27
4–28
4–30
4–32
4–32
4–33
4–35
4–36
4–38
4–40
4–40
4–40
4–40
4–41
4–42
4–42
4–42
4–43
4–44
4–45
4–45
4–46

5 Memory Controller
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.2.1
5.3
5.3.1
5.3.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Configuration . . . . . . . . . . . . . . . . . . . . . . . . .
Error Correction and Detection . . . . . . . . . . . . . . . . . . . . . . .
Graphics Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
Masked Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1
5–3
5–3
5–3
5–5
5–5
5–6
5–6
5–8
5–9

5.3.3
Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Memory Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1
Correctable Read Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2
Uncorrectable Read Error . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3
Uncorrectable Write Error . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.4
Bcache Tag Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.5
Nonexistent Memory Address Error . . . . . . . . . . . . . . . . . . . .
5.5
Graphics Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1
Simple Frame Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2
Transparent Stipple Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1
Programmable Timing Parameters . . . . . . . . . . . . . . . . . . . .
5.6.2
Bank Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . .
5.6.3
Bank Address Mask Registers . . . . . . . . . . . . . . . . . . . . . . . .
5.6.4
Bank Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.5
Global Timing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.6
Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.7
Error Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.8
Cache Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.9
Video and Graphics Control Register . . . . . . . . . . . . . . . . . . .
5.6.9.1
Video Display Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.10
Plane Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.11
Foreground Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
Idle Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2
RAS Precharge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.3
DRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.4
Full Video Shift-Register Transfer Timing . . . . . . . . . . . . . . .
5.7.5
Split Video Shift-Register Transfer Timing . . . . . . . . . . . . . .
5.7.6
Bcache Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.7
Bcache Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.8
Page-Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.9
Non-Page-Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.10
Page-Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.11
Non-Page-Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . .
5.8
Memory Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.1
mem_data<63:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.2
mem_ecc<7:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.3
mem_addr<11:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.4
mem_write_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.5
mem_rasa_l<3:0> and mem_rasb_l<3:0> . . . . . . . . . . . . . . . .
5.8.6
mem_cas_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.7
mem_dtoe_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9
5–9
5–9
5–10
5–10
5–10
5–11
5–11
5–12
5–12
5–12
5–12
5–14
5–18
5–20
5–22
5–24
5–27
5–29
5–33
5–34
5–35
5–36
5–36
5–40
5–41
5–42
5–43
5–44
5–45
5–46
5–47
5–48
5–49
5–50
5–51
5–51
5–51
5–52
5–52
5–52
5–53
5–53

5.8.8
5.8.9
5.8.10
5.8.11
5.8.12
5.8.13
5.8.14
5.8.15
5.8.16
5.8.17
5.8.18
5.8.19
5.8.20

mem_dsf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
mem_rd_oe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
mem_wr_oe_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bc_tag<7:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bc_dirty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bc_parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bc_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bc_idx_tag<4:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bc_cs_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bc_we_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
bc_oe_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vframe_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vrefresh_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–53
5–54
5–54
5–54
5–54
5–55
5–55
5–55
5–55
5–56
5–56
5–56
5–56

6 I/O Controller
6.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1
Scatter-Gather Mapping Support . . . . . . . . . . . . . . . . . . . . . .
6.1.2
Sparse and Dense Memory Support . . . . . . . . . . . . . . . . . . . .
6.1.3
PCI Parity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.4
PCI Exclusive Access Support . . . . . . . . . . . . . . . . . . . . . . . .
6.1.5
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
CPU-Initiated PCI Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1
CPU Request Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2
Requesting PCI Mastership . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.3
Default Mastership (Bus Parking) . . . . . . . . . . . . . . . . . . . . .
6.2.4
Memory Barrier Instruction Requirements . . . . . . . . . . . . . .
6.2.5
Address Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.6
Sparse Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.6.1
Generating PCI Addresses for Sparse Space . . . . . . . . . .
6.2.6.2
Address Extension for Sparse Space . . . . . . . . . . . . . . . .
6.2.6.3
Burst Order in Sparse Space . . . . . . . . . . . . . . . . . . . . . .
6.2.6.4
Unmasked Longword and Quadword Read Operations to
Sparse Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.6.5
Unmasked Longword Write Operations to Sparse
Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.6.6
Unmasked Quadword Write Operations to Sparse
Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.6.7
Masked Longword Read Operations to Sparse Space . . . .
6.2.6.8
Masked Longword Write Operations to Sparse Space . . .

6–1
6–1
6–2
6–2
6–3
6–3
6–3
6–5
6–5
6–6
6–6
6–7
6–7
6–7
6–9
6–10
6–10
6–11
6–11
6–13
6–13

vii

6.2.7
Dense Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.7.1
Generating PCI Addresses for Dense Space . . . . . . . . . . .
6.2.7.2
Unmasked Read Operations to Dense Space . . . . . . . . . .
6.2.7.3
Unmasked Burst Write Operations to Dense Space . . . . .
6.2.8
I/O Space Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.9
Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.10
Special Cycles and Interrupt Acknowledge Cycles . . . . . . . . .
6.2.10.1
Special Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.10.2
Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . .
6.2.11
Back-to-Back Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.12
PCI Address Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.13
PCI Data Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.13.1
PCI Read Data Parity Errors . . . . . . . . . . . . . . . . . . . . . .
6.2.13.2
PCI Write Data Parity Errors . . . . . . . . . . . . . . . . . . . . .
6.2.14
PCI Master Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.15
PCI Target-Disconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.16
PCI Retry Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.17
PCI Target-Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.18
PCI Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Peripheral-Initiated PCI Cycles . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1
PCI Cycle Command Code Support and Aliasing . . . . . . . . . .
6.3.2
PCI Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2.1
Direct-Mapped Address Translation . . . . . . . . . . . . . . . . .
6.3.2.2
Scatter-Gather Mapped Address Translation . . . . . . . . . .
6.3.3
Scatter-Gather Map Translation Buffer . . . . . . . . . . . . . . . . .
6.3.4
Page Table Read Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5
Invalid Page Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6
Address Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6.1
PCI Address Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6.2
Address Burst Order . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6.3
Page Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6.4
Address Parity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.7
PCI-Initiated Write Data Transfers . . . . . . . . . . . . . . . . . . . .
6.3.7.1
PCI Write-Data Queue . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.7.2
PCI-Initiated Memory Write Data Errors . . . . . . . . . . . .
6.3.8
PCI-Initiated Read Data Transfers . . . . . . . . . . . . . . . . . . . .
6.3.8.1
PCI Read-Data Queue . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.8.2
PCI-Initiated Memory Read Data Errors . . . . . . . . . . . . .
6.3.9
PCI Target Latency Timeout . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.10
PCI-Initiated Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . .
6.3.11
Guaranteed Access Arbitration . . . . . . . . . . . . . . . . . . . . . . .
6.4
I/O Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1
Host Address Extension Register . . . . . . . . . . . . . . . . . . . . . .

viii

6–13
6–13
6–14
6–14
6–15
6–15
6–16
6–16
6–17
6–18
6–18
6–18
6–18
6–19
6–19
6–20
6–20
6–21
6–21
6–22
6–22
6–23
6–25
6–26
6–28
6–29
6–30
6–30
6–30
6–31
6–31
6–31
6–32
6–33
6–33
6–34
6–34
6–35
6–35
6–36
6–36
6–37
6–38

6.4.2
Configuration Cycle Type Register . . . . . . . . . . . . . . . . . . . . .
6.4.3
Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.4
Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.5
Translation Buffer Invalidate All Register . . . . . . . . . . . . . . .
6.4.6
Translation Buffer Enable Register . . . . . . . . . . . . . . . . . . . .
6.4.7
PCI Soft Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.8
PCI Parity Disable Register . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.9
Window Base Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.10
Window Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.11
Translated Base Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.12
Translation Buffer Tag Registers . . . . . . . . . . . . . . . . . . . . . .
6.4.13
Interrupt Vector and Special Cycle Register . . . . . . . . . . . . .
6.4.14
Initialization Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
I/O Controller Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1
req_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2
gnt_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.3
frame_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.4
ad<31:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.5
c_be_l<3:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.6
irdy_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.7
trdy_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.8
devsel_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.9
lock_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.10
stop_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.11
par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.12
perr_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.13
rst_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.14
pci_clk_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.15
memreq_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.16
memack_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–38
6–39
6–41
6–42
6–43
6–43
6–44
6–45
6–46
6–47
6–48
6–49
6–50
6–51
6–51
6–51
6–52
6–52
6–52
6–52
6–52
6–53
6–53
6–53
6–53
6–53
6–53
6–54
6–54
6–54

7 Clocks
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
irq<2:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
pll_bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
pll_clk_in, pll_clk_in_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
pll_filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
pll_i_ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
pll_5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
test_clk_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1
7–1
7–3
7–3
7–3
7–3
7–4
7–4
7–4
7–4

7.3.8

reset_in_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5

8 JTAG Test Port
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.5
8.6
8.6.1
8.6.2
8.7

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Access Port Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
lock_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
instr_ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1
8–1
8–2
8–2
8–4
8–4
8–4
8–5
8–5
8–5
8–7

9 SROM Interface and Icache Initialization
9.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
Instruction Cache Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.1
Icache Load Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.1.1
First Bit Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.1.2
End of Preload Sequence . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.2
Icache Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
Serial Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4
SROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1
sromclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2
sromd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3
sromoe_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–1
9–1
9–3
9–3
9–3
9–4
9–5
9–5
9–5
9–5
9–5

A 21066A Differences
A.1
A.1.1
A.1.2
A.2
A.3
A.4
A.5
A.6
A.6.1
A.6.2
A.6.3

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divider Ramping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Cache Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
New Floating-Point Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Improved Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revised Write-Buffer Unload Logic . . . . . . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . .
Load and Store Unit Control Register . . . . . . . . . . . . . . . . . .
Cache Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–1
A–2
A–3
A–4
A–4
A–5
A–5
A–6
A–6
A–9
A–12

A.6.4

Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–13

B Pin Summary
C Internal Register Summary
D Technical Support and Ordering Information
D.1
D.2
D.3
D.4

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Digital Semiconductor Products . . . . . . . . . . . . . . . . . .
Ordering Associated Literature . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Third-Party Literature . . . . . . . . . . . . . . . . . . . . . . . . .

D–1
D–1
D–2
D–2

Microprocessor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HW_MFPR and HW_MTPR Instructions Format . . . . . . . . . .
HW_LD and HW_ST Instructions Format . . . . . . . . . . . . . . .
HW_REI Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . .
TB_TAG Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITB_PTE Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . .
ICCSR Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXC_ADDR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXC_SUM Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_CLR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_RCV Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_XMIT Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIRR, SIRR, and ASTRR Read Format . . . . . . . . . . . . . . . . .
HIER, SIER, and ASTER Read Format . . . . . . . . . . . . . . . . .
SIRR Write Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASTRR Write Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIER Write Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIER Write Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASTER Write Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2
2–17
3–7
3–9
3–10
4–2
4–4
4–7
4–12
4–14
4–15
4–16
4–17
4–18
4–18
4–23
4–25
4–26
4–27
4–28
4–31

Index
Figures
2–1
2–2
3–1
3–2
3–3
4–1
4–2
4–3
4–4
4–5
4–6
4–7
4–8
4–9
4–10
4–11
4–12
4–13
4–14
4–15
4–16

4–17
4–18
4–19
4–20
4–21
4–22
4–23
4–24
4–25
4–26
4–27
5–1
5–2
5–3
5–4
5–5
5–6
5–7
5–8
5–9
5–10
5–11
5–12
5–13
5–14
5–15
5–16
5–17
5–18
5–19
5–20
5–21
5–22
5–23
6–1
6–2
6–3

xii

PAL_BASE Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
ABOX_CTL Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
TB_CTL Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTB_PTE Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .
DTB_PTE_TEMP Register Format . . . . . . . . . . . . . . . . . . . .
VA Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM_CSR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ALT_MODE Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
CC Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC_CTL Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC_STAT Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Controller Operation . . . . . . . . . . . . . . . . . . . . . . . .
BCR3–BCR0 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BMR3–BMR0 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BTR3–BTR0 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GTR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EAR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bcache Address Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VGR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLM Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FOR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAS Precharge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Video Shift-Register Transfer Timing . . . . . . . . . . . . . . .
Split Video Shift-Register Transfer Timing . . . . . . . . . . . . . .
Bcache Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bcache Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page-Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Page-Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Page-Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Page-Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . .
Scatter-Gather Map Page Table Entry . . . . . . . . . . . . . . . . . .
IOC_HAE Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .
IOC_CONF Register Format . . . . . . . . . . . . . . . . . . . . . . . . .

4–32
4–33
4–35
4–36
4–38
4–41
4–41
4–43
4–44
4–45
4–46
5–2
5–7
5–14
5–19
5–21
5–23
5–25
5–28
5–30
5–32
5–33
5–35
5–36
5–41
5–42
5–43
5–44
5–45
5–46
5–47
5–48
5–49
5–50
6–28
6–38
6–39

6–4
6–5
6–6
6–7
6–8
6–9
6–10
6–11
6–12
6–13
7–1
7–2
9–1
9–2
A–1
A–2
A–3
A–4

IOC_STAT0 Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
IOC_STAT1 Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
IOC_TB_ENA Register Format . . . . . . . . . . . . . . . . . . . . . . .
IOC_SFT_RST Register Format . . . . . . . . . . . . . . . . . . . . . . .
IOC_PAR_DIS Register Format . . . . . . . . . . . . . . . . . . . . . . .
IOC_W_BASE1–0 Registers Format . . . . . . . . . . . . . . . . . . . .
IOC_W_MASK1–0 Registers Format . . . . . . . . . . . . . . . . . . .
IOC_T_BASE1–0 Registers Format . . . . . . . . . . . . . . . . . . . .
IOC_TB_TAG7–0 Registers Format . . . . . . . . . . . . . . . . . . . .
IOC_IACK_SC Register Format . . . . . . . . . . . . . . . . . . . . . . .
PLL Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Reference Current and Filter Circuit . . . . . . . . . . . . . . .
Icache Load Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Icache Load Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABOX_CTL Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
C_STAT Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
production$:[21066a.art.ps_final]ESR Format . . . . . . . . . . . .

6–40
6–42
6–43
6–44
6–44
6–46
6–47
6–48
6–49
6–50
7–2
7–4
9–2
9–4
A–7
A–9
A–12
A–13

Producer–Consumer Classes . . . . . . . . . . . . . . . . . . . . . . . . .
Producer–Consumer Latency Matrix . . . . . . . . . . . . . . . . . . .
Instruction Opcode Summary with Instruction Issue Bus . . .
Required PALcode Instructions . . . . . . . . . . . . . . . . . . . . . . .
Implementation-Specific PALcode Instructions . . . . . . . . . . .
Physical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HW_MFPR and HW_MTPR Format Description . . . . . . . . . .
Internal Processor Register Access . . . . . . . . . . . . . . . . . . . . .
HW_LD and HW_ST Format Description . . . . . . . . . . . . . . .
HW_REI Format Description . . . . . . . . . . . . . . . . . . . . . . . . .
PALcode Entry Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dstream Error PAL Entry Points . . . . . . . . . . . . . . . . . . . . . .
HW_MTPR Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HW_MTPR Cycle Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TB_TAG Register Small-Page Format Field Description . . . .
TB_TAG Register Large-Page Format Field Description . . . .

2–19
2–21
2–25
2–26
2–27
2–28
3–7
3–7
3–9
3–11
3–11
3–13
3–16
3–20
4–2
4–3

Tables
2–1
2–2
2–3
2–4
2–5
2–6
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
4–1
4–2

xiii

4–3
4–4
4–5
4–6
4–7
4–8
4–9
4–10
4–11
4–12
4–13
4–14
4–15
4–16
4–17
4–18
4–19
4–20
4–21
4–22
4–23
4–24
4–25
4–26
4–27
4–28
4–29
4–30
4–31
4–32
4–33
4–34
4–35
4–36
4–37
4–38
5–1

xiv

ITB_PTE Register Write-Format Field Description . . . . . . . .
ITB_PTE Register Read-Format Field Description . . . . . . . . .
ICCSR Write-Format Field Description . . . . . . . . . . . . . . . . .
ICCSR Read-Format Field Description . . . . . . . . . . . . . . . . .
BPE and BHE Branch Prediction Selection . . . . . . . . . . . . . .
EXC_ADDR Field Description . . . . . . . . . . . . . . . . . . . . . . . .
EXC_SUM Register Field Description . . . . . . . . . . . . . . . . . .
SL_CLR Register Field Description . . . . . . . . . . . . . . . . . . . .
SL_RCV Register Field Description . . . . . . . . . . . . . . . . . . . .
SL_XMIT Register Field Description . . . . . . . . . . . . . . . . . . .
Interrupt Request and Enable Registers . . . . . . . . . . . . . . . .
HIRR, SIRR, and ASTRR Read-Format Field Description . . .
HIER, SIER, and ASTER Read-Format Field Description . . .
Interrupt Request and Enable Registers Bit Map . . . . . . . . .
SIRR Write-Format Field Description . . . . . . . . . . . . . . . . . .
ASTRR Write-Format Field Description . . . . . . . . . . . . . . . . .
HIER Write-Format Field Description . . . . . . . . . . . . . . . . . .
SIER Write-Format Field Description . . . . . . . . . . . . . . . . . .
ASTER Write-Format Field Description . . . . . . . . . . . . . . . . .
Counter 0 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter 1 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS Register Write-Format Field Description . . . . . . . . . . . . .
PS Register Read-Format Field Description . . . . . . . . . . . . . .
PAL_BASE Register Field Description . . . . . . . . . . . . . . . . . .
ABOX_CTL Register Field Description . . . . . . . . . . . . . . . . .
TB_CTL Register Field Description . . . . . . . . . . . . . . . . . . . .
DTB_PTE Register Field Description . . . . . . . . . . . . . . . . . . .
DTB_PTE_TEMP Register Field Description . . . . . . . . . . . . .
VA Register Field Description . . . . . . . . . . . . . . . . . . . . . . . .
MM_CSR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . .
ALT_MODE Register Field Description . . . . . . . . . . . . . . . . .
CC Register Write-Format Field Description . . . . . . . . . . . . .
CC Register Read-Format Field Description . . . . . . . . . . . . .
CC_CTL Register Field Description . . . . . . . . . . . . . . . . . . . .
DC_STAT Register Field Description . . . . . . . . . . . . . . . . . . .
Internal Process Register Reset State . . . . . . . . . . . . . . . . . .
Nibble Correction Bit Grouping . . . . . . . . . . . . . . . . . . . . . . .

4–4
4–5
4–8
4–10
4–11
4–13
4–14
4–15
4–16
4–17
4–18
4–19
4–20
4–22
4–24
4–25
4–26
4–27
4–28
4–29
4–30
4–31
4–31
4–32
4–33
4–36
4–37
4–39
4–41
4–42
4–43
4–44
4–44
4–45
4–46
4–46
5–4

5–2
5–3
5–4
5–5
5–6
5–7
5–8
5–9
5–10
5–11
5–12
5–13
5–14
5–15
5–16
5–17
5–18
5–19
5–20
5–21
5–22
5–23
5–24
5–25
5–26
6–1
6–2
6–3
6–4
6–5
6–6
6–7
6–8
6–9
6–10

Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . .
BCR3–BCR0 Field Description . . . . . . . . . . . . . . . . . . . . . . . .
RAS Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Row Address Select Encodings . . . . . . . . . . . . . . . . . . . . . . . .
Row Address Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . .
BMR3–BMR0 Field Description . . . . . . . . . . . . . . . . . . . . . . .
Bank Size Mask Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Bank Address Select . . . . . . . . . . . . . . . . . . . . . . . . . . .
BTR3–BTR0 Field Description . . . . . . . . . . . . . . . . . . . . . . . .
GTR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EAR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Counter Events . . . . . . . . . . . . . . . . . . . . . . . . .
CAR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bcache Size Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VGR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VRAM Address Increment Encodings . . . . . . . . . . . . . . . . . .
PLM Register Field Description . . . . . . . . . . . . . . . . . . . . . . .
FOR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read and Write Options . . . . . . . . . . . . . . . . . . . . . .
VRAM Shift-Register Load Selection . . . . . . . . . . . . . . . . . . .
Use of bc_idx_tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU-to-PCI Address Translation . . . . . . . . . . . . . . . . . . . . . .
CPU Address Windows to PCI Address Spaces . . . . . . . . . . .
Byte Enable Encoding for CPU-Initiated Transfers in Sparse
Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Address Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commands for PCI-Initiated Transactions . . . . . . . . . . . . . . .
PCI Window Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Address Translation—Scatter-Gather Mapping
Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scatter-Gather Map Address . . . . . . . . . . . . . . . . . . . . . . . . .
IOC_HAE Register Field Description . . . . . . . . . . . . . . . . . . .
IOC_CONF Register Field Description . . . . . . . . . . . . . . . . . .

5–4
5–13
5–14
5–16
5–17
5–18
5–19
5–19
5–20
5–21
5–23
5–25
5–28
5–29
5–30
5–32
5–33
5–34
5–35
5–36
5–37
5–38
5–39
5–53
5–55
6–4
6–5
6–8
6–9
6–23
6–24
6–26
6–27
6–38
6–39

6–11
6–12
6–13
6–14
6–15
6–16
6–17
6–18
6–19
6–20
7–1
8–1
8–2
8–3
8–4
9–1
A–1
A–2
A–3
A–4
A–5
A–6
B–1
C–1
C–2
C–3

xvi

IOC_STAT0 Register Field Description . . . . . . . . . . . . . . . . .
IOC_STAT1 Register Field Description . . . . . . . . . . . . . . . . .
IOC_TB_ENA Register Field Description . . . . . . . . . . . . . . . .
IOC_SFT_RST Register Field Description . . . . . . . . . . . . . . .
IOC_PAR_DIS Register Field Description . . . . . . . . . . . . . . .
IOC_W_BASE1–0 Registers Field Description . . . . . . . . . . . .
IOC_W_MASK1–0 Registers Field Description . . . . . . . . . . .
IOC_T_BASE1–0 Registers Field Description . . . . . . . . . . . .
IOC_TB_TAG7–0 Registers Field Description . . . . . . . . . . . .
IOC_IACK_SC Register Field Description . . . . . . . . . . . . . . .
Internal Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG ICMODE Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Chain Order . . . . . . . . . . . . . . . . . . . . . . . . .
Icache Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Divider Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary and Override Divisor Values . . . . . . . . . . . . . . . . . .
ABOX_CTL Register Field Description . . . . . . . . . . . . . . . . .
C_STAT Register Field Description . . . . . . . . . . . . . . . . . . . .
ESR Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Implementation-Specific Internal Processor Registers . . . . . .
Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–40
6–42
6–43
6–44
6–45
6–46
6–47
6–48
6–49
6–50
7–2
8–1
8–3
8–4
8–6
9–2
A–3
A–7
A–8
A–9
A–12
A–14
B–1
C–1
C–3
C–4

Preface
This manual describes the architecture, internal design, and external
interface of the Alpha 21066 and Alpha 21066A microprocessors. The Alpha
21066/21066A Microprocessors Data Sheet describes electrical, mechanical,
and thermal characteristics.

Audience
This manual is for system designers, software developers, and hardware
engineers who use the Alpha 21066 and Alpha 21066A microprocessors.

Manual Organization
This manual contains the following chapters and appendixes:
•

Chapter 1, Introduction, provides an overview of the Alpha architecture. It
also briefly describes the features of the Alpha 21066 and Alpha 21066A
microprocessors.

•

Chapter 2, Internal Architecture, describes the Alpha 21066 and Alpha
21066A microprocessor architecture. It also describes the instruction
pipeline and defines the scheduling and dual-issue rules.

•

Chapter 3, Privileged Architecture Library Code, describes the
microprocessor’s privileged architecture library code (PALcode).

•

Chapter 4, Internal Processor Registers, describes the instruction fetch
and decode unit (IDU) registers, load and store unit (LSU) registers, and
PAL_TEMP registers.

•

Chapter 5, Memory Controller, describes the memory controller, supported
memories, memory operations, error handling, graphics operations,
registers, cycle timing, and interface signals.

•

Chapter 6, I/O Controller, describes the I/O controller (IOC), I/O operations,
and IOC error handling, registers, and interface signals.

xvii

•

Chapter 7, Clocks, describes the clock interface, phase-locked loop (PLL),
clock frequency selection, and noise reduction requirements.

•

Chapter 8, JTAG Test Port, describes the implementation of the joint
testing action group (JTAG) test port.

•

Chapter 9, SROM Interface and Icache Initialization, describes the
instruction cache (Icache) initialization, using the serial ROM (SROM). It
also describes how the SROM port can be used as a serial terminal port
after the Icache is initialized.

•

Appendix A, 21066A Differences, describes how the Alpha 21066A
microprocessor differs from the Alpha 21066 microprocessor.

•

Appendix B, Pin Summary, summarizes the following pins: memory
controller; IOC; clock; JTAG; and instruction reference, interrupt, and
SROM interface.

•

Appendix C, Internal Register Summary, summarizes the Alpha 21066
internal registers.

•

Appendix D, Technical Support and Ordering Information, describes how
to obtain information and technical support, and order products and
associated literature.

Conventions
Unless otherwise noted, the following conventions are extracted from the Alpha
Architecture Reference Manual. The most recent version of that manual is the
authoritative reference for such information and may supersede information in
this document.
Abbreviations
The following abbreviations apply to binary multiples and register access:
•

Binary multiples
The abbreviations K, M, and G (kilo, mega, and giga) represent binary
multiples and have the following values:
K=
M=
G=

210 (1024)
220 (1,048,576)
230 (1,073,741,824)

For example:
2 KB =
4 MB =
8 GB =

xviii

2 kilobytes =
4 megabytes =
8 gigabytes =

2 2 210 bytes
4 2 220 bytes
8 2 230 bytes

•

Register Access
The abbreviations used to indicate the type of access to register fields and
bits have the following definitions:
IGN — Ignore
Bits and fields specified as IGN are ignored when written.
MBZ — Must Be Zero
Software must never place a nonzero value in bits and fields specified
as MBZ. Such fields are reserved for future use. An illegal operand
exception occurs if the processor encounters a nonzero value in a field
specified as MBZ.
RAX — Read As UNDEFINED
Bits and fields specified as RAX are unimplemented bits of registers
that read as UNDEFINED.1
RAZ — Read As Zero
Bits and fields specified as RAZ return a zero when read.
RC — Read Clears
Bits and fields specified as RC are cleared when read. Unless otherwise
specified, such fields cannot be written.1
RES — Reserved
Bits and fields specified as RES are reserved by Digital and should not
be used.1
RO — Read Only
Bits and fields specified as RO can be read and are ignored (not written)
on write operations.1
RW — Read and Write
Bits and fields specified as RW can be read and written. Writing a zero
clears the bits.1

Implementation-specific or typographical convention adapted from or not specified in
the Alpha Architecture Reference Manual.

xix

R/W1C — Read and Write One to Clear
Bits and fields specified as R/W1C can be read. Writing a one clears
the bits.1
WA — Write Always Clears
Bits and fields specified as WA can be read. Any write clears the bits.
WO — Write Only
Bits and fields specified as WO can be written but not read. In the I/O
controller the results of reading such registers are UNPREDICTABLE.
Writing a zero clears the bits.1
X
Bits and fields specified as X return UNPREDICTABLE results when
read and are ignored on write operations.1
Aligned and Unaligned
The terms aligned and naturally aligned are interchangeable and refer to data
objects that are powers of two in size. An aligned datum of size 2n is stored
in memory at a byte address that is a multiple of 2n ; that is, one that has n
low-order zeros. For example, an aligned 64-byte stack frame has a memory
address that is a multiple of 64.
A datum of size 2n is unaligned if it is stored in a byte address that is not a
multiple of 2n .
Bit Notation
Multiple-bit fields can include contiguous and noncontiguous bits contained
in angle brackets ( <> ). Multiple contiguous bits are indicated by a pair of
numbers separated by a colon ( : ). For example, <9:7,5,2:0> specifies bits
9,8,7,5,2,1, and 0. Similarly, single bit positions are frequently indicated with
angle brackets. For example, ‘‘The PAL bit (<0>) indicates PALmode to the
hardware,’’ indicates that the PAL bit is bit 0 in a register.1
Caution
Cautions indicate potential damage to equipment or loss of data.1
Chip
Unless otherwise stated, throughout this manual, the terms microprocessor
and chip mean the Alpha 21066 or the Alpha 21066A microprocessor.

Data Units
The following data unit terminology is used throughout this manual.
Term

Words

Bytes

Bits

Other

Nibble

—

Byte

—

Tribyte

1½

—

Word

—

Longword

—

Quadword

Single read fill—The cache space that can be
filled in a single read access. It takes four
read accesses to fill an onchip (I or D) cache
line.

Octaword

128

—

Hexword

256

Cache block, cache line—The space allocated
to a single Bcache block.

External
Unless otherwise stated, throughout this manual, the term external means not
contained in the Alpha 21066 or Alpha 21066A microprocessor.
Microprocessor
Unless otherwise stated, throughout this manual, the terms microprocessor
and chip mean the Alpha 21066 or the Alpha 21066A microprocessor.
Note
Notes emphasize particularly important information.1
Numbering
All numbers are decimal or hexadecimal unless otherwise indicated. In cases
of ambiguity, a subscript indicates the radix of nondecimal numbers. For
example, 19 is decimal, but 1916 and 19A are hexadecimal.1
Ranges and Extents
Ranges are specified by a pair of numbers separated by two periods ( .. ) and
are inclusive. For example, a range of integers 0..4 includes the integers 0, 1,
2, 3, and 4.
Extents are specified by a pair of numbers in angle brackets ( <> ) separated
by a colon ( : ) and are inclusive. For example, bits <7:3> specifies an extent
including bits 7, 6, 5, 4, and 3.

xxi

Security Holes
A security hole is an error of commission, omission, or oversight in a system
that allows protection mechanisms to be bypassed.
Security holes exist when unprivileged software (that is, software running
outside of kernel mode) can:
•

Affect the operation of another process without authorization from the
operating system.

•

Amplify its privilege without authorization from the operating system.

•

Communicate with another process, overtly or covertly, without
authorization from the operating system.

The Alpha architecture is designed to contain no architectural security holes.
Hardware (processors, buses, controllers, and so on) and software should also
be designed to avoid security holes.
Signal Names
Signal names are printed in lowercase, boldfaced type. The names of lowasserted signals carry the suffix _l. The names of high-asserted signals have
no suffix. For example, pll_clk_in is a high-asserted signal, and pll_clk_in_l
is a low-asserted signal.
UNPREDICTABLE and UNDEFINED
Only privileged software (that is, software running in kernel mode) might
trigger UNDEFINED operations.
Either privileged or unprivileged software might trigger UNPREDICTABLE
results or occurrences.
UNPREDICTABLE results and occurrences do not disrupt the basic operation
of the processor; the processor continues to execute instructions in its normal
way.
UNDEFINED operation might halt the processor or cause it to lose
information.
A result specified as UNPREDICTABLE might acquire an arbitrary value
subject to a few constraints. Such a result might be an arbitrary function of
the input operands or of any state information that is accessible to the process
in its current access mode. UNPREDICTABLE results might be unchanged
from their previous values. Operations that produce UNPREDICTABLE
results might also produce exceptions.
UNPREDICTABLE results must not be security holes.

xxii

Specifically, UNPREDICTABLE results must not depend on or be a function
of the contents of memory locations or registers that are inaccessible to the
current process in the current access mode.
Also, operations that might produce UNPREDICTABLE results must not:
•

Write or modify the contents of memory locations or registers that are
inaccessible to the current process in the current access mode.

•

Halt or hang the system or any of its components.

For example, a security hole would exist if some UNPREDICTABLE result
depended on:
•

The value of a register in another process

•

The contents of processor temporary registers left behind by some
previously running process

•

A sequence of actions of different processes

An occurrence specified as UNPREDICTABLE might happen or not based
on an arbitrary choice function. The choice function is subject to the same
constraints as are UNPREDICTABLE results and, in particular, must not
constitute a security hole.
Results or occurrences specified as UNPREDICTABLE might vary from
moment to moment, implementation to implementation, and instruction to
instruction within implementations. Software can never depend on results
specified as UNPREDICTABLE.
Operations specified as UNDEFINED might vary from moment to moment,
implementation to implementation, and instruction to instruction within
implementations. The operation might vary in effect from nothing to stopping
system operation. UNDEFINED operations must not cause the processor to
hang; that is, reach an unhalted state from which there is no transition to a
normal state in which the machine executes instructions.

xxiii

1
Introduction
This chapter is an overview of the Alpha architecture as it is implemented in
the Alpha 21066 microprocessor (21066) and the Alpha 21066A microprocessor
(21066A). It also lists the major features of the microprocessors.
Note
The 21066–166 and 21066–100 are functionally identical—they differ
only in clock frequency (21066–166 at 166 MHz and 21066–100 at
100 MHz).
The upgraded 21066A versions (21066A–266 at 266 MHz, 21066A–233
at 233 MHz, and 21066A–100 at 100 MHz) are functionally identical
and differ only in clock frequency.
The functionality described for the 21066 is true for the 21066A, except
where the differences are explicitly detailed.

1.1 Architecture
The Alpha architecture is a 64-bit load and store RISC architecture designed
with particular emphasis on speed, multiple instruction issue, multiple
processors, and multiple operating system support.
All registers are 64 bits in length and all operations are performed between
64-bit registers. All instructions are 32 bits in length. Memory operations are
either load instructions or store instructions. All data manipulation is done
between registers.
The Alpha architecture supports the following data types:
•

8-, 16-, 32-, and 64-bit integers

•

IEEE 32-bit and 64-bit floating-point formats

•

VAX 32-bit and 64-bit floating-point formats

Introduction 1–1

In the Alpha architecture, instructions interact with each other only by one
instruction writing to a register or memory location and another instruction
reading from that register or memory location. Using resources in this way
makes it easy to build processors that issue multiple instructions every CPU
cycle.
The microprocessor uses a set of subroutines, called privileged architecture
library code (PALcode), that is specific to a particular Alpha operating system
implementation and hardware platform. These subroutines provide operating
system primitives for context switching, interrupts, exceptions, and memory
management. These subroutines can be invoked by hardware or CALL_PAL
instructions. CALL_PAL instructions use the function field of the instruction
to vector to a specified subroutine. PALcode is written in standard machine
code with some machine-specific extensions to provide direct access to low-level
hardware functions. PALcode supports optimizations for multiple operating
systems, flexible memory management implementations, and multi-instruction
atomic sequences.
The Alpha architecture does byte shifting and masking with normal 64-bit
register-to-register instructions; it does not include single byte load and
store instructions. The software developer must determine the precision of
arithmetic traps.
For more information about the Alpha architecture, see the Alpha Architecture
Reference Manual.

1.2 Microprocessor Features
The 21066 implementation of the Alpha architecture is a 0.65-micron, CMOSbased, superscalar, superpipelined processor using dual-instruction issue. The
21066A is implemented in the same way, with 0.50-micron technology.
The chip incorporates a high level of system integration for best-in-class
system performance in cost-focused (21066–166, 21066A–233, and 21066A–266)
or embedded (21066–100 and 21066A–100) applications. It integrates onchip,
fully pipelined integer and floating-point processors, a high-bandwidth memory
controller, an industry-standard I/O controller (IOC), an embedded graphics
accelerator, internal instruction and data caches, and external cache control.
The microprocessor and associated PALcode implement IEEE single-precision
and double-precision, VAX F_floating and G_floating data types, and support
longword (32-bit) and quadword (64-bit) integers. Byte-manipulation
instructions provide support for byte (8-bit) and word (16-bit) operations.
Limited hardware support is also provided for the VAX D_floating data type.

1–2 Introduction

Microprocessor features include the following:
•

Fully pipelined, 64-bit RISC architecture

•

Supported by multiple operating systems:

•

–

Microsoft Windows NT

–

OSF/1

–

OpenVMS

–

VxWorks for Alpha

Best-in-class performance:
–

266 MHz (21066A–266), 233 MHz (21066A–233), 166 MHz (21066–166),
or 100 MHz (21066–100 and 21066A–100) operation

–

Superscalar, superpipelined (dual issue)

–

Peak instruction execution rate of 532 MIPS (21066A–266), 466 MIPS
(21066A–233), 330 MIPS (21066-166), or 200 MIPS (21066–100 and
21066A–100)

–

0.50-micron (21066A) and 0.65-micron (21066) CMOS technology

•

Pipelined onchip floating-point unit. IEEE single-precision and doubleprecision, VAX F_floating and G_floating, longword and quadword data
types. Limited support for VAX D_floating data type.

•

Onchip demand-paged memory management unit:

•

–

12-entry instruction stream translation buffer (ITB) with eight entries
for 8-KB pages and four entries for 4-MB pages

–

32-entry data stream translation buffer (DTB) with each entry able to
map a single 8-KB, 64-KB, 512-KB, or 4-MB page

–

Superpage mapping

Onchip high-bandwidth memory controller:
–

Full 64-bit memory data path

–

Dynamic RAM (DRAM) controller with fully programmable timing

–

Optional error correction code (ECC)

–

Support for up to four banks of memory with programmable timing for
each bank

–

RAS/CAS memory bus to industry-standard, single inline memory
modules (SIMMs)

Introduction 1–3

•

Embedded graphics accelerator:
–

Onchip support for direct connection to a video RAM (VRAM) frame
buffer

–

High-bandwidth memory data path to VRAM

PCI IOC:
–

32-bit multiplexed address and data

–

Industry-standard interface

–

No glue logic needed to connect PCI-compliant chips

–

Usable bandwidth in excess of 100 MB/s

–

Burst mode read and write operations

–

Asynchronous operation to CPU

–

Multimaster with peer-to-peer access

–

Alpha I/O-compliant

•

Onchip, 8-KB, direct-mapped, write-through data cache (Dcache)

•

Onchip, 8-KB, direct-mapped, instruction cache (Icache)

•

Onchip control for optional, external, write-back backup cache (Bcache):

•

–

Direct connection to external static RAMs (SRAMs) without any
external logic

–

Programmable cache size and speed

Built-in phase-locked loop (PLL):
–

Frequency multiplier for low cost input clock

–

Programmable multiplier values

Serial ROM (SROM) interface:
–

Loads instruction cache after reset

–

Supports software-controlled serial port after initialization

•

Chip- and module-level test support — JTAG (IEEE 1149)

•

3.3-V supply voltage interfaces directly to 5-V logic

1–4 Introduction

In addition, the 21066A features:
•

Software-controllable power management
Programmable clock divider
Programmable override for interrupts, DMA, or both

•

Parity protection on internal caches

Introduction 1–5

2
Internal Architecture
This chapter describes the chip’s microarchitecture. Much of the hardware
design is based on specific PAL functionality. The combination of
microarchitecture and PALcode (described in Chapter 3) defines the
chip’s implementation of the Alpha architecture. This chapter also describes
the instruction pipeline and defines the scheduling and dual-issue rules. This
chapter is an overview of the internal architecture and does not describe the
chip in great detail.

2.1 Overview
The chip consists of a core central processing unit (CPU), a memory controller,
and an I/O controller (IOC). The chip also contains an instruction cache
(Icache), a data cache (Dcache), and a serial read-only memory (SROM)
interface. Figure 2–1 is a block diagram of the chip.
The memory controller interfaces to the system memory and the optional,
external, backup cache (Bcache). It also contains the embedded graphics
accelerator. The memory controller and interface are described in Chapter 5.
The PCI IOC is the interface between peripheral devices, CPU, and system
memory. It is compatible with the PCI Local Bus Specification, Revision 2.0.
The IOC and interface are described in Chapter 6.
The SROM interface provides the initialization data load path from the
SROM to the Icache. Following initialization, this interface can be used as a
diagnostic port through the use of PALcode. The SROM interface and operation
are described in Chapter 9.
The interface unit connects the CPU, memory controller, IOC, and the SROM
interface (Figure 2–1). It consists of a 64-bit bidirectional data bus, address
bus, invalidate address bus, reset logic, and control.

Internal Architecture 2–1

Figure 2–1 Microprocessor Block Diagram

CPU
Instruction Cache (Icache)
Branch
History Table

Tag

Data
Interface
Unit

Instruction
Fetch/Decode
Unit (IDU)

Integer
Execution
Unit (IEU)
Multiplier
Shifter

Prefetcher
Resource
Conflict

Adder
Logic Box

Divider

PC
Calculation
ITB
Pipeline
Control

Integer
Register
File (IRF)

Floating−Point
Execution
Unit (FPU)
Multiplier/
Adder
Pipeline

Floating−Point
Register
File (FRF)

Address
Generator

DTB

Addr/Data
Data Path

Address, RAS, CAS

Backup
Cache
Controller

Backup Cache Tag

ECC

Memory Data/ECC

Graphics
Accelerator
PCI I/O
Controller (IOC)
Addr/Data
Queue
Scatter−Gather
TLB

Load/Store Unit (LSU)
Write
Buffer

Memory
Controller

Control
Address/Data

Load Silo
SROM
Debug Port

SROM Data
SROM Clock
Interrupts

Data Cache (Dcache)
Tag

PLL Clock
Generator

Clock

Data

The IDU is the CPU’s central control unit. It issues instructions, maintains
the pipeline, and performs program counter (PC) calculations. The CPU also
contains four independent execution units:
•

IEU

•

LSU

•

FPU

•

Branch unit

2–2 Internal Architecture

Each unit accepts no more than one instruction per cycle; however, correctly
scheduled code can issue two instructions to two independent units in a single
cycle.

2.2 Instruction Fetch and Decode Unit
The primary function of the IDU is to issue instructions to the IEU, LSU, and
FPU. The IDU includes the following functions:
•

Prefetcher

•

PC pipeline

•

Two instruction translation buffers (ITBs)

•

Abort logic

•

Exception logic

•

Internal processor registers (IPRs)

The IDU decodes two instructions in parallel and checks that the required
resources are available for both instructions, as follows:
•

If resources are available, both instructions are issued.

•

If resources are available only for the second instruction, neither the first
nor the second instruction is issued.

•

If the IDU issues only the first of a pair of instructions, it does not advance
another instruction to attempt a dual issue; dual issue is attempted only
on aligned quadword (8-byte) pairs.

Section 2.8.4 describes instructions that can be dual issued.

Internal Architecture 2–3

2.2.1 Branch Prediction Logic
The branch unit, or prediction logic, is also part of the IDU. The microprocessor
offers a register-selectable choice of branch prediction strategies (Section 4.1.7).
Each instruction location in the Icache includes a single history bit to record
the outcome of branch instructions. This information can be used to predict
the result when the branch instruction is next executed. The prediction for the
first execution of a branch instruction is based on the sign of the displacement
field within the branch instruction, as follows:
•

If the sign is negative, the instruction prefetcher predicts the conditional
branches to be taken.

•

If the sign is positive, the instruction prefetcher predicts that the
conditional branches are not to be taken.

•

Alternatively, if the history table is disabled, all branch prediction can be
based on the sign of the displacement field.

The microprocessor provides a 4-entry subroutine return stack that is
controlled by the hint bits in the BSR, HW_REI, JMP, JSR, RET, and
JSR_COROUTINE instructions. The chip also allows all branch prediction
hardware to be disabled.
Note
The 21066A implements an improved branch prediction scheme. For
details, see Section A.4.

2.2.2 Instruction Translation Buffers
The IDU includes two fully associative instruction translation buffers (ITBs):
•

An 8-entry, small-page ITB for 8-KB pages

•

A 4-entry, large-page ITB for 4-MB (512 2 8 KB) pages

Both translation buffers (TBs) store recently used, instruction stream (Istream)
page-table entries and use a not-last-used replacement algorithm.
In addition, both ITBs support a register-enabled extension called the
superpage. The ITB superpage mappings provide one-to-one translation
from virtual program counter bits <33:13> to physical program counter bits
<33:13> when virtual address bits <42:41> = 2. When translating through the
superpage, the address space match (ASM) bit is always set in the PTE used in
the Icache. Access to the superpage mapping is allowed only while executing
in kernel mode.

2–4 Internal Architecture

PALcode fills and maintains the ITBs. The operating system, through PALcode,
is responsible for ensuring that virtual addresses can be mapped only through
a single ITB entry (in the large page, small page, or superpage) at the same
time.
The IDU presents the 43-bit virtual program counter (VPC) to the ITB each
cycle while not executing in PALmode. If the PTE associated with the VPC is
cached in the ITB, the IDU uses the page frame number (PFN) and protection
bits for the page that contains the VPC to complete the address translation
and access checks.
The ITBs support a single address space number (ASN) through the PTE ASM
bit. Each PTE entry in the ITB contains an ASM bit. Write operations to
the ITBASM register invalidate all entries that do not have the ASM bit set.
This is a simple way to preserve entries that map operating system regions
while invalidating all other entries. (The ITBASM register is described in
Section 4.1.5.)
For more information about TBs and PTEs, see the Alpha Architecture
Reference Manual.

2.2.3 Interrupt Logic
The IDU exception logic supports three sources of interrupts:
•

•

Hardware interrupts
–

Three level-sensitive hardware interrupts are sourced by pins irq<2:0>.

–

Two internally generated interrupts respond to external interface error
conditions. These are sourced by the memory controller error status
register (ESR, Section 5.6.6) and the I/O controller status register 0
(IOC_STAT0, Section 6.4.3).

Software interrupts
The 15 prioritized software interrupts are sourced by the software interrupt
request register (SIRR, Section 4.1.13.2).

•

Asynchronous system traps (ASTs)
Four ASTs are available, one for each processor mode: user, supervisor,
executive, and kernel. These traps are sourced by the asynchronous trap
request register (ASTRR, Section 4.1.13.3).

In addition to the three level-sensitive hardware interrupts from the irq<2:0>
pins, error conditions detected in the memory controller and the IOC can
interrupt the CPU.

Internal Architecture 2–5

The memory controller generates an interrupt if it detects any error condition,
such as a nonexistent memory access, a missed refresh cycle, an uncorrectable
ECC error, and a Bcache parity error. To return the memory subsystem to
correct operation, software must clear these error conditions by writing to the
memory controller ESR.
The I/O controller generates an interrupt to the CPU when it detects certain
error conditions. These errors are logged in the IOC_STAT0 register. To
remove the interrupt, software must write a one to the error bit in the
IOC_STAT0 register.
The memory controller and IOC error conditions and registers are described in
Chapters 5 and 6.
All interrupts can be independently masked using onchip enable registers.
In addition, AST interrupts are qualified by the current processor mode
and the current state of software interrupt enable register bit 2 (SIER,
Section 4.1.13.5). Providing distinct enable bits for each independent interrupt
source allows a flexible, software-controlled interrupt priority scheme to be
implemented in PALcode or the operating system.
For example, the microprocessor can support a 5-level interrupt priority
scheme by defining a distinct state of the hardware interrupt enable register
(HIER, Section 4.1.13.4) for each interrupt priority level (IPL). The state of the
HIER determines the current interrupt priority. The lowest IPL is produced by
enabling all five interrupts, for example bits <5:1>. The next IPL is produced
by enabling bits <5:2> and so on, to the highest IPL that is produced by
enabling only bit 5 and disabling bits <4:1>.
When all interrupt enable bits are cleared, the processor cannot be interrupted
from the hardware interrupt request register (HIRR, Section 4.1.13.1). Each
state (bits <5:1> enabled through only bit 5 enabled) represents an individual
IPL. If these states are the only states allowed in the HIER, a 5-level hardware
interrupt priority scheme can be controlled entirely by PAL software. The
scheme is extensible to provide multiple interrupt sources at the same IPL by
grouping enable bits. Groups of enable bits must be set and cleared together
to support multiple interrupts of equal priority level. This method reduces the
total available number of distinct levels.
Because enable bits are provided for all hardware, software, and AST interrupt
requests, a priority scheme can span all sources of processor interrupts.
Additional restrictions are placed on AST interrupt requests.

2–6 Internal Architecture

Four AST interrupts are provided; one for each processor mode. The AST
interrupt requests are qualified such that AST requests that correspond to a
given mode are blocked when the processor is in a higher mode, regardless of
the state of the AST interrupt enable register (ASTER, Section 4.1.13.6). In
addition, all AST interrupt requests are qualified by SIER bit 2.
When the processor receives an interrupt request and that request is enabled
and the processor is not currently executing PALcode, the hardware reports or
delivers an interrupt to the exception logic. Before vectoring to the interruptservice PAL dispatch address, the pipeline is completely drained and all
outstanding Dcache fills are completed. The restart address is saved in the
exception address register (EXC_ADDR, Section 4.1.8) and the processor enters
PALmode. The cause of the interrupt can be determined by examining the
state of the interrupt request registers.
Usually, the interrupts from the irq<2:0> pins can be grouped as follows:
•

Interval timer interrupts

•

Halt, powerfail, ISA and EISA nonmaskable interrupts, and the PCI serr_l
signal

•

ISA and EISA interrupt requests, and PCI interrupt requests

Hardware interrupt requests are level-sensitive; therefore, they can be removed
before an interrupt is serviced. If they are removed before the interrupt
request register is read, the register will return a zero value.

2.2.4 Performance Counters
An onchip performance recording mechanism counts various hardware events
and causes an interrupt upon counter overflow. Interrupts are triggered six
cycles after the event, and therefore, the exception program counter (PC) might
not reflect the exact instruction causing counter overflow.
Two counters are provided, to allow accurate comparison of two variables
under potentially nonrepeatable, experimental conditions. The events counted
include:
•

Instruction issues and instruction nonissues

•

Total cycles

•

Pipeline dry and pipeline freeze

•

Branch mispredictions and cache misses

•

Counts of various instruction classes

Internal Architecture 2–7

In addition, two external interface events (such as direct memory access [DMA]
transactions, Bcache accesses, and so on), can be counted by programming the
memory controller error address register (EAR, Section 5.6.7).
See Section 4.1.14 for more information about the performance counters.

2.3 Integer Execution Unit
The IEU contains the 64-bit integer execution data path, which includes the
following functions:
•

Adder

•

Logic box

•

Barrel shifter

•

Byte zapper

•

Bypassers

•

Integer multiplier

The integer multiplier retires 4 bits per cycle.
The IEU also contains the 32-entry, 64-bit integer register file (IRF). The IRF
has four read ports and two write ports to simultaneously read operands to
and write operands (results) from the IEU data path and the LSU.

2.4 Load and Store Unit
The LSU contains four major sections:
•

Address translation data path, which includes the data translation buffer

•

Load silo

•

Write buffer

•

Internal processor registers (IPRs)

The address translation data path has a displacement adder that generates
the effective virtual address (VA) for load and store instructions, and a data
translation buffer (DTB) that generates the corresponding physical address.
CPU requests fall into three classes: Dcache fills, Icache fills, and write buffer
requests. Simultaneous internal requests are resolved using a fixed priority
scheme in which Dcache fill requests are given highest priority, followed by
Icache fill requests. Write buffer requests have the lowest priority.

2–8 Internal Architecture

Because the internal cache fill block size is 32 bytes, cache fill operations result
in four data transfers across a 64-bit bus from the memory controller to the
appropriate cache. Also, because each write buffer is 32 bytes wide, write
transactions may result in four data transfers from the write buffer to the
memory controller.
The internal processor registers (IPRs) are described in Chapter 4.

2.4.1 Data Translation Buffer
The 32-entry, fully associative data translation buffer (DTB) stores recently
used, data-stream (Dstream) page table entries (PTEs). The DTB supports
four page-size granularity options (also called granularity hints) that allow an
aligned group of 1, 8, 64, or 512 pages to be treated as a single larger page.
The DTB also supports the register-enabled superpage extension. The DTB
superpage mappings provide virtual-to-physical address translation for two
regions of the virtual address space as follows:
•

In the first region, superpage mapping is enabled when VA bits
<42:41> = 2. In this mode, the entire physical address space is mapped
multiple times to the quadrant of virtual address space defined by VA
<42:41> = 2.

•

In the second region, a 30-bit region of the total physical address (PA)
space defined by PA <33:30> = 0, is mapped into a single corresponding
region of virtual address space defined by VA <42:30> = 1FFE.

Superpage translation is allowed only in kernel mode. The operating system,
through PALcode, is responsible for ensuring that translation buffer entries,
including superpage regions, do not map overlapping virtual address regions at
the same time.
Each PTE in the DTB contains an ASM bit. The DTB supports a single ASN
with the PTE ASM bit. Write operations to the DTBASM register invalidate
all entries that do not have the ASM bit set. This is a simple way to preserve
entries that map operating system regions while invalidating all other entries.
(The DTBASM register is described in Section 4.2.6.)
For load and store instructions, the effective 43-bit virtual address is presented
to the DTBs. If the PTE of the supplied virtual address is cached in the DTB,
the LSU uses the page frame number (PFN) and protection bits for the page
that contains the address to complete the address translation and access
checks.
PALcode fills and maintains the DTB. (The flow for a DTB miss is described
in Chapter 3.) Note that the DTB can be filled in kernel mode by setting the
hardware enable (HWE) bit in the ICCSR (Section 4.1.7).
Internal Architecture 2–9

For more information about translation buffers and page table entries, see the
Alpha Architecture Reference Manual.

2.4.2 Load Silos
The LSU contains a memory reference pipeline that can accept a new load or
store instruction every cycle until a Dcache fill is required. Because the Dcache
lines (blocks) are allocated only on load misses, the load and store unit can
accept a new load instruction every cycle until a load miss occurs. When a load
miss occurs, the IDU stops issuing all instructions that use the load port of the
register file or are otherwise handled by the LSU. These instructions include:
LDx, STx, HW_MTPR, HW_MFPR, FETCH, FETCH_M, RPCC, RS, RC, and
MB. They also include all memory-format branch instructions: JMP, JSR,
JSR_COROUTINE, and RET. (However, a JSR instruction with a destination
of R31 can be issued.)
Instructions are issued in pipeline stage 3 and the result of each Dcache lookup
is not known until pipeline stage 6. Therefore, there can be two instructions in
the LSU pipeline behind a load instruction that misses in the Dcache. These
two instructions are handled as follows:
•

Loads that hit in the Dcache are allowed to complete (hit-under-miss).

•

Loads that miss are placed in a silo and are presented in sequence after
the first load miss completes.

•

Store instructions are presented to the Dcache at their normal time, with
respect to the pipeline. They are placed in a silo and presented to the write
buffer in sequence, with respect to loads that miss.

To improve performance, the IDU can restart the execution of LSU-directed
instructions before the last pending Dcache fill is complete. Dcache fill
transactions result in four data transfers from the memory controller to
the Dcache. These transfers can each be separated by one or more cycles,
depending on the characteristics of the Bcache and memory subsystems.
In the first of these four transfers, the memory controller sends the quadword
of the fill block originally requested by the CPU (it can always do this for read
operations that hit in the Bcache). Therefore, the pending load instruction that
requested the Dcache fill can finish before the Dcache fill finishes.
Dcache fill data accumulates one quadword at a time, into a pending fill
latch, rather than being written into the cache array as it is received from
the memory controller. When the load miss silo is empty and the requested
quadword for the last outstanding load miss is received, the IDU resumes
execution of LSU-directed instructions despite the still-pending Dcache fill.
When the entire cache line has been received from the memory controller, it is

2–10 Internal Architecture

written into the Dcache data array when the array is not busy with a load or a
store instruction.

2.4.3 Write Buffer
The LSU write buffer has two purposes:
•

The CPU can generate store data faster than the Bcache subsystem can
accept the data, which causes CPU stall cycles. The write buffer is a finite,
high-bandwidth resource that receives store data and reduces the number
of possible CPU stall cycles to a minimum.

•

The write buffer also attempts to aggregate store data into aligned, 32-byte
cache blocks to maximize the rate at which the microprocessor can write
data into the Bcache.

The write-merging operation of the write buffer can cause the order of offchip
write operations to be different from the order in which their corresponding
store instructions were executed. In addition, the write buffer can collapse
multiple store instructions to the same location into a single offchip write
transaction. Software that requires strict write ordering or that does multiple
stores to the same location (resulting in multiple offchip write sequences), must
insert a memory barrier (MB) instruction between the store instructions of
interest.
In addition to store instructions, MB, STQ/C, STL/C, FETCH, and FETCH_M
instructions are written into the write buffer and sent offchip. Unlike store
instructions, however, these write-buffer-directed instructions are never
merged into a write buffer entry with other instructions.
Each of the four write buffer entries can store up to 32 bytes (four quadwords).
The buffer has a head pointer and tail pointer. The buffer puts new commands
into empty tail entries and takes commands out of nonempty head entries. The
head pointer increments when an entry is unloaded to the memory controller,
and the tail pointer increments when new data is put into the tail entry. The
head and tail pointers point to the same entry only when either all four entries
are empty or no entries are empty.
For example, suppose that no write operations merge with existing nonempty
entries. In that case, the ordering of write operations with respect to other
write operations will be maintained. The write buffer never reorders write
operations except to merge them into nonempty entries. After a write operation
merges into a nonempty entry, its programmed order is lost with respect to
write operations in the same slot and write operations in other slots.

Internal Architecture 2–11

The write buffer attempts to send its head entry offchip by requesting the
memory controller when one of the following conditions is met:
•

The write buffer contains at least two valid entries.

•

The write buffer contains one valid entry and at least 256 CPU cycles have
elapsed since the execution of the last write-buffer-directed instruction.

•

The write buffer contains an MB instruction.

•

The write buffer contains an STQ/C or STL/C instruction.

•

A load miss that requires the write buffer to be flushed is pending to an
address that is currently valid in the write buffer. The write buffer is
completely flushed regardless of which entry matches the address.
Note
The 21066A implements revised write buffer unload logic. For details,
see Section A.5.

2.4.3.1 Memory Barrier Instruction
The CPU will not execute load or store instructions that occur after an MB
instruction until all preceding load or store instructions have been completed.
The instructions are completed when:
•

A load instruction from a memory address is complete when the memory
controller returns the requested read data to the CPU.

•

A load instruction from a PCI address is complete when the requested read
data has been returned to the CPU.

•

A store instruction to a memory address is complete when the write data
has been written to memory.

•

A store instruction to a PCI address is complete when the write data has
been transferred to the PCI (and is not being retried).

A load or store instruction is considered complete even if error status occurs.
(See Chapter 6 for more information.)

2–12 Internal Architecture

2.5 Floating-Point Unit
The onchip, pipelined FPU can execute both IEEE and VAX floating-point
instructions. The microprocessor supports IEEE S_floating and T_floating
data types, with all rounding modes except round to ± infinity, which can be
provided in software. The microprocessor fully supports VAX F_floating and
G_floating data types and provides limited support for the VAX D_floating
format.
The FPU includes the following functions:
•

A 32-entry, 64-bit floating-point register file (FRF)

•

The user-accessible floating-point control register (FPCR), containing:
Round mode controls
Exception flag information
For a description of the FPCR, see the Alpha Architecture Reference
Manual.

The FPU can accept an instruction every cycle, with the exception of
floating-point divide instructions. The latency for data-dependent, nondivide
instructions is six cycles. (For more information about instruction timing, see
Section 2.7.)
For divide instructions, the FPU does not compute the inexact flag.
Consequently, the INE exception flag in the FPCR is never set for IEEE
floating-point divide using the inexact enable (/INEXACT) modifier. To deliver
IEEE compliant exception behavior, the FPU hardware always traps on
DIVS/SI and DIVT/SI instructions. This allows the arithmetic exception
handler (in either PALcode or the operating system) to identify the source of
the trap, compute the inexact flag, and deliver the appropriate exception. The
exception associated with DIVS/SI and DIVT/SI instructions is imprecise. To
ensure that the trap handler can deliver correct behavior to the user, software
must follow the software completion modifier rules specified by the Alpha
architecture.
Note
The 21066A has new floating-point divide hardware that greatly
reduces average divide latency. For more detailed information, refer to
Section A.3.

For IEEE compliance issues, see Section 2.5.1 and the Alpha Architecture
Reference Manual.
Internal Architecture 2–13

2.5.1 IEEE Floating-Point Conformance
The microprocessor supports IEEE floating-point operations as specified by
the Alpha architecture. Support for a complete implementation of the IEEE
Standard for Binary Floating-Point Arithmetic (754-1985) is provided by a
combination of hardware and software as described in the Alpha Architecture
Reference Manual. Additional information that provides guidelines for
writing code supporting precise exception handling (necessary for complete
conformance to the standard) is in the Alpha Architecture Reference Manual.
The microprocessor implements the following functions:
•

When operating without the /UNDERFLOW modifier, the microprocessor
replaces underflow results with exact zero, whether or not the correct
result would have been negative zero as defined in the IEEE standard.
This Alpha architecture value-added behavior improves performance over
either hardware or software denormal handling.
When strict IEEE compliance is required, the /UNDERFLOW modifier
is necessary and the software must provide the correct result (including
negative zero).

•

The microprocessor supports infinity operands only when used in the
CMPT instruction. Other instructions using infinity operands cause invalid
operation (INV) arithmetic traps.

•

NaN, denormal, or infinity (except when used in CMPT) input operands
produce INV arithmetic traps when used with arithmetic operation
instructions. CPYSE, CPYSN, FCMOV, MF_FPCR, and MT_FPCR are not
arithmetic operations and will pass NaN, denormal, and infinity values
without initiating arithmetic traps. Input operand traps take precedence
over arithmetic result traps.

•

The microprocessor will not produce a NaN, denormal, or infinity result.

•

The microprocessor supports IEEE normal and chopped rounding modes
in hardware. Instructions designating plus infinity and minus infinity
rounding modes cause precise exceptions to the OPCDEC PAL entry point.
This implies that the EXC_ADDR register will be loaded with the address
of the faulting instruction and all following instructions will be aborted.
Table 3–5 describes the PALcode entry points.

•

The DIVS and DIVT instructions with the /INEXACT modifier report
an inexact (INE) arithmetic trap on all results of operations that do not
involve NaN, infinity, or denormal input operands. Operations using NaN,
infinity, and denormal input operands generate INV arithmetic traps.

2–14 Internal Architecture

•

Floating-point exceptions generated by the microprocessor are recorded in
the following places:
Whether or not the corresponding trap is enabled (through the
instruction modifiers), the occurrence of all detected exceptions other
than SWC are recorded in the FPCR (accessible by the MT_FPCR
and MF_FPCR instructions) records. Because this register can be
cleared only with an explicit clear command (MT_FPCR), the exception
information it records is a summary of all exceptions that have occurred
since the last clear operation.
If an exception is detected and the corresponding trap is enabled,
the microprocessor records the condition in the exception summary
register (EXC_SUM, Section 4.1.9) and initiates an arithmetic trap. As
a special case, in order to support inexact exception behavior with the
DIVS/I and DIVT/I instructions, the FPCR does not record an inexact
exception, although the microprocessor always sets the INE bit in the
EXC_SUM register during these instructions. This behavior allows
software to emulate the division instructions with accurate reporting of
potential inexact exceptions.
For more information about the FPCR, see the Alpha Architecture Reference
Manual.

2.6 Internal Cache Organization
All memory cells in the onchip Dcache and Icache are fully static, 6-transistor
CMOS structures.

2.6.1 Data Cache
The 8-KB data cache (Dcache) is a write-through, direct-mapped, read-allocate
physical cache with 32-byte blocks. When a PCI device writes to cacheable
memory, the Dcache block corresponding to the memory address is set invalid
to maintain cache coherency. The 21066A has longword parity protection.

2.6.2 Instruction Cache
The 8-KB instruction cache (Icache) is a physical direct-mapped cache. Each
cache block (line) contains the following:
•

32 bytes of Istream data

•

21-bit associated tag

•

6-bit address space number (ASN) field

•

1-bit address space match (ASM) field

Internal Architecture 2–15

•

8-bit (21066) or 16-bit (21066A) branch history (BHT) field

The 21066A has longword parity protection.
The Icache does not contain hardware for maintaining coherency with memory
and is unaffected by any PCI write operations to the memory.
The chip also contains a single-entry Icache stream buffer and supporting logic
that reduces the performance penalty incurred by Icache misses during inline
instruction processing. Stream buffer prefetch requests never cross physical
page boundaries; instead, they wrap around to the first block of the current
page.
Note
Both the Dcache and the Icache are longword parity protected in the
21066A. Refer to Section A.2 for details.

2.7 Instruction Pipeline Organization
The microprocessor has a 7-stage pipeline for integer operate and memory
reference instructions and a 10-stage pipeline for floating-point operate
instructions. The IDU maintains the state for all pipeline stages, to track
outstanding register write operations, and to determine Icache hits and misses.
Figure 2–2 shows the integer operate, memory reference, and floating-point
operate pipelines for the IDU, IEU, LSU, and FPU. The first four stages of
all the pipelines are the same and are executed in the IDU. The last stages
are unit-specific. All of the units have bypassers that allow the results of one
instruction to be the operand of a following instruction, without writing the
results of the first instruction to a register file.

2–16 Internal Architecture

Figure 2–2 Instruction Pipelines
Instruction Fetch
Swap Dual−Issue Instruction/Branch Prediction
Decode
Register File Access/Issue Check
Integer Operate
Pipeline

IF
0

SW
1

I0
2

I1
3

A1
4

A2
5

WR
6

AC
4

TB
5

HM
6

Computation Cycle 1 − IDU computes new PC
Computation Cycle 2 − ITB Lookup
Integer Register File Write/Icache Hit or Miss

Memory Reference
Pipeline

IF
0

SW
1

I0
2

I1
3

LSU calculates effective Dstream address
DTB Lookup
Dcache Hit or Miss and Load Data Register File Write Pipeline

Floating−Point
Pipeline

IF
0

SW
1

I0
2

I1
3

F1
4

F2
5

F3
6

F4
7

F5
8

FWR
9

Floating−Point Calculate Pipeline
Floating−Point Register File Write Pipeline

2.7.1 Instruction Pipeline Static and Dynamic Stages
The integer pipeline divides instruction processing into four static and three
dynamic stages of execution. The floating-point pipeline maintains the first
four static stages and adds six dynamic stages of execution. The first four
stages are as follows:
•

Instruction fetch

•

Swap

•

Decode

•

Issue logic

These stages are static because instructions can remain valid in the same
pipeline stage for multiple cycles while waiting for a resource or stalling for
other reasons.

Internal Architecture 2–17

Dynamic stages always advance state and are unaffected by any stall in the
pipeline. (Pipeline stalls are also called pipeline freezes.) A pipeline freeze
can occur while either no instructions issue or one instruction of a pair issues
and the second is held at the issue stage. A pipeline freeze implies that valid
instructions are presented to be issued but cannot proceed.
Upon satisfying all issue requirements, instructions can continue through any
pipeline toward completion. Instructions cannot be held in a given pipe stage
after they are issued. The issue stage must ensure that all resource conflicts
are resolved before an instruction is allowed to continue. Only a chip-internal
abort condition can stop instructions after the issue stage.

2.7.2 Aborts
The causes for aborts are grouped into two classes:
•

Exceptions (including interrupts)

•

Nonexceptions

Exceptions require the pipeline to be drained of all outstanding instructions
before restarting the pipeline at a redirected address. In both classes, all
instructions that were fetched after the instruction that caused the abort
condition, must be flushed from the pipeline. This includes stopping one
instruction of a dual-issued pair when an abort condition occurs on the first
instruction of the pair.
Nonexceptions do not require the pipeline to be drained of all outstanding
instructions ahead of the aborting instruction. The pipeline can be immediately
restarted at a redirected address. Examples of nonexception abort conditions
are branch mispredictions, subroutine call or return mispredictions, and Icache
misses. Dcache misses do not produce abort conditions but can cause pipeline
freezes.
If an exception occurs, the processor aborts all instructions issued after the
excepting instruction. Due to the nature of some error conditions, this can
occur as late as the write cycle. The address of the excepting instruction is
then latched in the exception address register (EXC_ADDR, Section 4.1.8).
When the pipeline is fully drained, the processor begins to execute instructions
at the address given by the PALcode dispatch. The pipeline is drained when:
•

All outstanding write operations to both the integer and floating-point
register files have completed, and arithmetic traps have been reported.

•

All outstanding instructions have successfully completed memory
management and access protection traps.

2–18 Internal Architecture

2.7.3 Nonissue Conditions
Nonissue conditions occur for the following reasons:
•

The pipeline freezes when a valid instruction or pair of instructions is
prepared to issue but cannot because of a resource conflict. These types of
nonissue cycles can be minimized through code scheduling.

•

The existence of pipeline bubbles when the pipeline does not contain a valid
instruction to issue.

Pipeline bubbles exist because of the abort conditions described in
Section 2.7.2. In addition, a single pipeline bubble is produced when a
branch-type instruction is predicted to be taken, including subroutine calls and
returns. Pipeline bubbles are reduced directly by the hardware through bubble
squashing but can also be effectively minimized with careful coding. Bubble
squashing is the ability of any of the first four pipeline stages to advance when
a bubble is detected in the pipeline stage immediately ahead of it while the
pipeline is otherwise frozen.

2.8 Instruction Scheduling and Issuing Rules
Sections 2.8.1 through 2.8.5 describe the instruction scheduling and issuing
rules.

2.8.1 Instruction Class Definition
This section describes the performance-related scheduling and dual-issue rules.
There are no functional dependencies related to scheduling or dual issue.
The scheduling and issuing rules are defined in terms of instruction classes.
Table 2–1 specifies all of the instruction classes and the unit that executes the
particular class.
Table 2–1 Producer–Consumer Classes
Class

Unit

Instructions

Load and store

All loads
HW_MFPR, RPCC, RS, RC, and STC producers only
FETCH consumer only

Load and store

All stores and HW_MTPR

IBR

Integer execution

Integer conditional branches
(continued on next page)

Internal Architecture 2–19

Table 2–1 (Cont.) Producer–Consumer Classes
Class

Unit

Instructions

FBR

Floating-point

Floating-point conditional branches

JSR

Integer execution

JMP, JSR, RET, and JSR_COROUTINE
BSR and BR producer only

IADDLOG

Integer execution

ADDL, ADDL/V, ADDQ, and ADDQ/V
LDA and LDAH
SUBL, SUBL/V, SUBQ, SUBQ/V, S4ADDL,
S4ADDQ, S8ADDL, S8ADDQ, S4SUBL, S4SUBQ,
S8SUBL, and S8SUBQ
AND, BIC, BIS, ORNOT, and XOR

SHIFTCM

Integer execution

CMOVEQ, CMOVNE, CMOVLT, CMOVLE,
CMOVGT, CMOVGE, CMOVLBS, and CMOVLBC
EXTQL, EXTLL, EXTWL, EXTBL, EXTQH,
EXTLH, and EXTWH
INSQL, INSLL, INSWL, INSBL, INSQH, INSLH,
and INSWH
MSKQL, MSKLL, MSKWL, MSKBL, MSKQH,
MSKLH, and MSKWH
SLL, SRL, and SRA
ZAP and ZAPNOT

ICMP

Integer execution

CMPEQ, CMPLT, CMPLE, CMPULT, CMPULE, and
CMPBGE

IMULL

Integer execution

MULL and MULL/V

IMULQ

Integer execution

MULQ, MULQ/V, and UMULH

FPOP

Floating-point

Floating-point operates except divide

FDIV

Floating-point

Floating-point divide

2.8.2 Producer–Consumer Latency
The microprocessor enforces scheduling rules regarding producer–consumer
latencies. Table 2–2 shows these rules as a producer–consumer latency matrix.
Each row and column in the matrix is a class of Alpha instructions.

2–20 Internal Architecture

Table 2–2 Producer–Consumer Latency Matrix
IADDLOG

SHIFTCM

ICMP

IMULL

IMULQ

FPOP

FDIV
F/S

FDIV
G/T

2/0

21/20

23/22

X/4

X/32

X/61

JSR

—

IADDLOG

—

Consumer

LD JSR

ST
IBR

SHIFTCM

—

ICMP

—

IMUL

21/19

23/21

FBR

FPOP

FDIV

34/30 63/59

Notes for Table 2–2:
•

The numbers in the matrix represent the cycles of latency. For example,
one cycle of latency is indicated by a 1 in the matrix. One cycle of
latency means that if instruction B uses the results of instruction A,
then instruction B can be issued one cycle after instruction A is issued.

•

LD indicates a Dcache hit is assumed for load instructions. The latency for
Dcache miss depends on the system configuration.

•

X indicates an impossible state or a state not normally encountered. For
example, a floating-point branch would not follow an integer compare.

•

For the ST consumer class, two latencies (for example, 2/0) are given with
some producer classes. The first is the latency for base address of store,
and the second is the latency for store data. Floating-point results cannot
be used as the base address for load or store operations.

•

Two latencies are given for IMUL followed by IMUL (for example, 21/19).
The first is the latency with data dependency; in other words, the second
IMUL uses the result from the first IMUL. The second is the multiply
latency without data dependencies.

Internal Architecture 2–21

•

Two latencies are given for FDIV followed by FDIV (for example, 34/30).
The first is the latency with data dependency; in other words, the second
FDIV uses the result from the first FDIV. The second is the divide latency
without data dependencies.

When determining latency for a given instruction sequence, the classes of each
instruction must first be identified. The following example lists the classes in
the comment field:
ADDQ
SRA
SUBQ
STQ

R1, R2, R3
R3, R4, R5
R5, R6, R7
R7, D(R10)

! IADDLOG class
! SHIFT class
! IADDLOG class
! ST class

The SRA instruction consumes the result (R3) produced by the ADDQ
instruction. The matrix shows a latency of 1 associated with an IADD-SHIFT
producer–consumer pair. In other words, if the ADDQ instruction is issued in
cycle n, the SRA instruction can be issued in cycle n+1.
The SUBQ instruction consumes the result (R5) produced by the SRA
instruction. The matrix shows a latency of 2 associated with a SHIFT-IADD
producer–consumer pair. In other words, if the SRA instruction is issued in
cycle n, the SUBQ instruction can be issued in cycle n+2. The IDU injects one
no-operation (NOP) cycle in the pipeline for this case.
In the final case, the STQ instruction consumes the result (R7) produced by
the SUBQ instruction. The matrix shows a latency of 0 associated with an
IADD-ST producer–consumer pair when the result of the IADD instruction is
the store data. In other words, the SUBQ and STQ instruction pair can be
dual issued.

2.8.3 Producer–Producer Latency
Producer–producer latency (also known as write-after-write conflicts) is
restricted only by the register write order. For most instructions, this is
dictated by issue order; however, IMUL, FDIV, and LD instructions might
require more time to complete than other instructions. Therefore, to preserve
write ordering, IMUL, FDIV, and LD instructions must stall following
instructions that write the same destination register.
In general, only cases involving an intervening producer–consumer conflict are
of interest. They can commonly occur in a dual-issue situation when a register
is reused. In these cases, producer–consumer latencies are equal to or greater

2–22 Internal Architecture

than the required producer–producer latency as determined by write ordering
and, therefore, dictate the overall latency. The following code is an example:
LDQ R2,D(R0)
ADDQ R2,R3,R4
LDQ R2,D(R1)

; R2 destination
; wr-rd conflict stalls execution waiting for R2
; wr-wr conflict may dual issue when addq issues

2.8.4 Instruction Issue Rules
The following conditions prevent instruction issue:
•

No instruction can be issued until all of its source and destination
registers are clean. In other words, all outstanding write operations to
the destination register are guaranteed to complete in issue order, and
either there are no outstanding write operations to the source registers or
those write operations can be bypassed.

•

No LD, ST, FETCH, MB, RPCC, RS, RC, TRAPB, HW_MXPR, BSR, BR, or
JSR (with destination other than R31) instruction can be issued after an
MB instruction until the MB has been acknowledged on the external pin
bus.

•

No IMUL instructions can be issued if the integer multiplier is busy.

•

No SHIFT, IADDLOG, ICMP, or ICMOV instruction can be issued exactly
three cycles before an integer multiplication completes.

•

No integer or floating-point conditional branch instruction can be issued in
the cycle immediately following a JSR, JMP, RET, JSR_COROUTINE, or
HW_REI instruction.

•

No TRAPB instruction can be issued as the second instruction of a
dual-issue pair.

•

No LD instructions can be issued in the two cycles immediately following
an STC instruction.

•

No LD, ST, FETCH, MB, RPCC, RS, RC, TRAPB, HW_MXPR, BSR, BR,
or JSR (with destination other than R31) instruction can be issued when
the LSU is busy due to a load miss or write buffer overflow. (For more
information, see Section 2.4.3.)

•

No FDIV instruction can be issued if the floating-point divider is busy.

•

No floating-point operate instruction can be issued exactly five or six cycles
before a floating-point divide completes.

Internal Architecture 2–23

2.8.5 Dual-Issue Table
Table 2–3 can be used to determine instruction pairs that can issue in a single
cycle. Instructions are dispatched using two internal data paths or buses. In
Table 2–3, the buses are referred to as IB0, IB1, and IBx.
In Table 2–3, any instruction identified with IB0 can be issued in the same
cycle as any instruction identified with IB1. An instruction that is identified as
IBx can be issued with either IB0 or IB1.
Dual issue is attempted if the input operands are available as defined by the
producer–consumer latency matrix in Table 2–2 and the following requirements
are met:
•

Two instructions are contained within an aligned quadword.

•

Both instructions are not in group IB0.

•

Both instructions are not in group IB1.

•

No more than one of the following instructions are to be issued in the same
cycle: JSR, integer conditional branch, BSR, HW_REI, BR, or floating-point
branch.

•

No more than one of the following instructions are to be issued in the same
cycle: load, store, HW_MTPR, HW_MFPR, MISC, TRAPB, HW_REI, BSR,
BR, or JSR.

Producer–consumer latencies of zero indicate that dependent operations
between these two instruction classes can dual-issue. For example, ADDQ R1,
R2, R3; STQ R3, and D(R4).

2–24 Internal Architecture

Table 2–3 Instruction Opcode Summary with Instruction Issue Bus
00

0/8

PAL
IB1

LDA
IB0

INTA
IB0

MISC
IB1

LDF
IBx

LDL
IBx

BR
IB1

BLBC
IB1

1/9

Res
IB1

LDAH
IB0

INTL
IB0

HW_MFPR
IB1

LDG
IBx

LDQ
IBx

FBEQ
IB0

BEQ
IB1

2/A

Res
IB1

INTS
IB0

JSR
IB1

LDS
IBx

LDL_L
IBx

FBLT
IB0

BLT
IB1

3/B

Res
IB1

LDQ_U
IBx

INTM
IB0

HW_LD
IB1

LDT
IBx

LDQ_L
IBx

FBLE
IB0

BLE
IB1

4/C

Res
IB1

STF
IB0

STL
IB1

BSR
IB1

BLBS
IB1

5/D

Res
IB1

FLTV
IB1

HW_MTPR
IB1

STG
IB0

STQ
IB1

FBNE
IB0

BNE
IB1

6/E

Res
IB1

FLTI
IB1

HW_REI
IB1

STS
IB0

STL_C
IB1

FBGE
IB0

BGE
IB1

7/F

Res
IB1

STQ_U
IB1

FLTL
IB1

HW_ST
IB1

STT
IB0

STQ_C
IB1

FBGT
IB0

BGT
IB1

Key to abbreviations
FLTI — IEEE floating-point instruction opcodes
FLTL — Floating-point operate instruction opcodes that are data type independent
FLTV — VAX floating-point instruction opcodes
INTA — Integer arithmetic instruction opcodes
INTL — Integer logical instruction opcodes
INTM — Integer multiply instruction opcodes
INTS — Integer subtract instruction opcodes
JSR — Jump instruction opcodes
MISC — Miscellaneous instruction opcodes
PAL — PALcode instruction (CALL_PAL) opcodes
Res — Reserved for Digital

Table 2–3 lists all Alpha opcodes from 00 (CALL_PAL) through 3F (BGT).
In the table, the column headings appearing over the instructions have a
granularity of 8. The rows beneath the leftmost column supply the individual
hexadecimal number to resolve that granularity.
If an instruction column has a 0 in the right (low) hexadecimal digit, replace
that 0 with the number to the left of the backslash in the leftmost column on
the instruction’s row.
If an instruction column has an 8 in the right (low) hexadecimal digit, replace
that 8 with the number to the right of the backslash in the leftmost column.

Internal Architecture 2–25

For example, the third row (2/A) under the 1016 column contains the symbol
INTS, representing the all-integer shift instructions. The opcode for those
instructions would then be 1216 because the 0 in 10 is replaced by the 2 in the
leftmost column.
Likewise, the third row under the 1816 column contains the symbol JSR,
representing all jump instructions. The opcode for those instructions is 1A
because the 8 in the heading is replaced by the number to the right of the
backslash in the leftmost column.
The instruction format is listed under the instruction symbol.
See the Alpha Architecture Reference Manual for more information about
instructions, their opcodes, and their definitions.

2.9 PALcode
Users and operating system developers require functions to be implemented
consistently in a family of machines. When functions conform to a common
interface, the code that uses those functions can be used on several different
implementations without modification. PALcode allows many different physical
implementations to coexist, each one adhering to the same programming
interface specification.

2.9.1 Required PALcode Instructions
The PALcode instructions listed in Table 2–4 are described in the Alpha
Architecture Reference Manual.
Table 2–4 Required PALcode Instructions
Mnemonic

Type

Operation

HALT

Privileged

Halt processor

IMB

Unprivileged

Istream memory barrier

2.9.2 Architecturally Reserved PALcode Instructions
The Alpha architecture provides five opcodes as implementation-specific
privileged instructions. These instructions are defined independently for each
hardware implementation of the Alpha architecture to give PALcode software
routines access to specific hardware states and functions.

2–26 Internal Architecture

Table 2–5 lists the hardware-specific, privileged instructions that are executed
in PALmode. They produce OPCDEC exceptions if executed while not in the
PALcode environment. (See Section 3.5 for a definition of OPCDEC.) These
instructions are mapped using the architecturally reserved opcodes PAL19,
PAL1B, PAL1D, PAL1E, and PAL1F. They can be used only while executing
chip-specific PALcode.
Table 2–5 Implementation-Specific PALcode Instructions
Mnemonic

Operation

HW_MTPR

Move data to processor register.

HW_MFPR

Move data from processor register.

HW_LD

Load data from memory.

HW_ST

Store data in memory.

HW_REI

Return from PALmode exception.

Programming Note
PALcode uses the HW_LD and HW_ST instructions to access memory
outside the realm of normal Alpha memory management.

2.10 Physical Address Space
Internally, the chip uses a 34-bit address space divided into regions as shown
in Table 2–6. Addresses in the cacheable memory region update the optional
Bcache when referenced by the CPU. The graphics memory region supports
simple graphics operations on data. In the PCI sparse memory region,
addresses are shifted 5 bits to allow access size encodings. Addresses are not
shifted in the PCI dense memory region. PCI peripherals can access only the
cacheable and noncacheable memory regions because the IOC maps the 32-bit
PCI address to the internal address that can access only those memory spaces.
In other words, the PCI cannot access the IOC register, memory controller
register, or graphics memory regions. (The translation mechanism is described
in Chapter 6.)
Instructions cannot be executed from the upper three quadrants of memory;
that is, when address bits <33:32> = 01, 10, or 11. Instructions can be executed
from the cacheable and noncacheable regions of the lowest quadrant, in which
case they will be cached in the Icache but not the Bcache.

Internal Architecture 2–27

Table 2–6 Physical Address Space
Address Region

Address Range (<33:0>)

Size

PCI dense memory

3 FFFF FFFF..3 0000 0000

4.0 GB

PCI sparse memory

2 FFFF FFFF..2 0000 0000

4.0 GB

PCI configuration

1 FFFF FFFF..1 E000 0000

0.5 GB

PCI I/O

1 DFFF FFFF..1 C000 0000

0.5 GB

PCI interrupt acknowledge and special cycle

1 BFFF FFFF..1 A000 0000

0.5 GB

IOC registers

1 9FFF FFFF..1 8000 0000

0.5 GB

Memory controller registers

1 7FFF FFFF..1 2000 0000

1.5 GB

1 1FFF FFFF..1 0000 0000

0.5 GB

Nonexistent memory (NXM)

0 FFFF FFFF..0 4000 0000

3.0 GB

Noncacheable memory

0 3FFF FFFF..0 2000 0000

0.5 GB

Cacheable memory†

0 1FFF FFFF..0 0000 0000

0.5 GB

Graphics memory3

3 Only this region supports graphics functions on write operations.
†All other address regions are noncacheable.

2.11 Memory Controller
The onchip memory controller is the interface between the CPU and the
system memory and optional Bcache. It has several memory-mapped control
and status registers (CSRs) to program organization, timing, and size of
DRAM, VRAM, and Bcache SRAM. It controls CPU requests and DMA
requests (from the IOC) to and from memory and the Bcache. It also controls
VRAM shift register load and memory refresh operations.
The memory controller decodes the address of a CPU request to determine
whether the request is for memory or the IOC. It handles the access to the
memory controller registers, memory, and Bcache. If the request is directed at
the IOC, the memory controller passes control to the IOC.
The memory controller can also perform the following graphics operations:
•

Dumb frame buffer operation

•

Transparent stipple operation

•

Write-per-bit plane masking

•

Byte write operations (with external gating)

•

Full and split VRAM shift-register loads

2–28 Internal Architecture

The memory controller and its registers are described in Chapter 5.

2.12 I/O Controller
The onchip IOC is the interface between peripheral devices and the CPU and
system memory. The IOC interface protocol complies with the PCI Local Bus
Specification, Revision 2.0. All peripheral devices in systems based on the
21066 can communicate with the CPU and system memory through the IOC.
Peripheral chips using the PCI protocol can be connected directly to the chip
without any glue logic. The IOC runs asynchronously to the CPU, using the
PCI clock input.
The IOC incorporates scatter-gather mapping logic to translate 32-bit
addresses generated by PCI bus masters to the 34-bit CPU physical address
space. The IOC implements an 8-entry translation lookaside buffer (TLB)
for fast translations. Two programmable address windows, controlled by
memory-mapped IOC registers, control access from PCI peripherals to system
memory. (The IOC and its registers are described in Chapter 6.)

2.13 Lock Registers
The chip implements two registers associated with the LDQ_L, LDL_L, STQ_C,
and STL_C instructions: the lock_flag register and the locked_physical_address
register. The locked range is 32 bytes.
The lock_flag register is cleared on any of the following conditions:
•

Execution of any STx_C instruction

•

A DMA write operation to the locked range

•

Execution of a CALL_PAL REI instruction

•

The IOC is locked (Section 6.3.10)

The lock flag will not be set by any LDx_L instruction while the IOC is locked.
See the Alpha Architecture Reference Manual for more information about the
lock registers.

Internal Architecture 2–29

3
Privileged Architecture Library Code
This chapter describes the microprocessor’s privileged architecture library code
(PALcode).

3.1 Overview
The Alpha architecture defines an innovative feature called PALcode that
allows many different physical implementations to coexist, each one adhering
to the same programming interface specification. PALcode has characteristics
that make it appear to be a combination of microcode, ROM basic input/output
operating system (BIOS), and system service routines, but it is not exactly
analogous to any of them.
The following examples list the major reasons for using PALcode. In each case,
PALcode routines provide the functions:
•

Some necessary support functions are too complex to implement directly in
a processor chip’s hardware and cannot be handled by a normal operating
system software routine. Such functions include routines to fill the
translation buffer, acknowledge interrupts, and dispatch exceptions. In
some architectures, these functions are handled by microcode, but the
Alpha architecture is careful not to mandate the use of microcode for
reasonable chip implementations.

•

Some functions must run atomically and involve long sequences of
instructions that may need complete access to all of the underlying
computer hardware. An example is the sequence that returns from an
exception or interrupt.

•

Some instructions are necessary for backward compatibility or ease of
programming; however, they are not used often enough to dedicate them
to hardware, or are so complex that they would jeopardize the overall
performance of the computer. For example, an instruction that does
an Intel style interlocked memory access might be familiar to CISC
programmers, but it is not included in the Alpha architecture. Another

Privileged Architecture Library Code 3–1

example is the emulation of an instruction that has no direct hardware
support in a particular chip implementation.
The PALcode routines are simply programs that are invoked at specified times,
and read in as instruction stream (Istream) code in the same way that all other
Alpha code is read. After it is invoked, PALcode runs in a special environment.

3.2 PALmode Environment
PALcode runs in a special environment called PALmode, defined as follows:
•

Istream memory mapping is disabled. Because the PALcode implements
translation buffer fill routines, Istream mapping cannot be enabled.

•

The program has privileged access to all of the computer hardware. Most
PALcode functions are privileged and need to control the lowest levels of
the system.

•

Interrupts are disabled. If a long sequence of instructions needs to be
executed atomically, interrupts cannot be allowed.

One important aspect of PALcode is that it uses normal Alpha instructions for
most of its operations; that is, the same instruction set used by nonprivileged
Alpha programs. In addition, the following instructions are available only in
PALmode:
Mnemonic

Operation

HW_MTPR

Move data to processor register.

HW_MFPR

Move data from processor register.

HW_LD

Load data from memory.

HW_ST

Store data in memory.

HW_REI

Return from PALmode exception.

These instructions will cause an OPCDEC exception if they are attempted
while not in PALmode. The Alpha architecture allows some flexibility in
the functions performed by these special PALmode instructions. In the
microprocessor, the special PALmode instructions perform the following
functions:
•

Read or write internal processor registers (HW_MFPR, HW_MTPR).

•

Perform memory load or store operations without invoking the normal
memory management routines (HW_LD, HW_ST).

•

Return from an exception or interrupt (HW_REI).

3–2 Privileged Architecture Library Code

See Section 3.4 for more information about these special PALmode instructions.
When executing in PALmode, there are certain restrictions on using the
privileged instructions because PALmode gives the programmer complete
access to many of the internal details of the microprocessor.
Caution
It is possible to cause unintended side effects by writing what appears
to be perfectly acceptable PALcode. Digital recommends that most
users do not attempt to change PALcode.

See Section 3.6 for more information about PALmode restrictions.

3.3 Invoking PALcode
PALcode is invoked at specific entry points, under certain well-defined
conditions. PALcode can be thought of as a series of callable routines, with
each routine indexed as an offset from a base address. The base address of
the PALcode is programmable (stored in the PAL base address register—
PAL_BASE, Section 4.1.16) and is normally set by the system reset code. See
Section 3.5 for more information about PALcode entry points.
When an event that invokes PALcode occurs, the microprocessor first drains
the pipeline. The current program counter (PC) is loaded into the exception
address register (EXC_ADDR, Section 4.1.8), and the appropriate PALcode
routine is dispatched. These operations are performed under direct control of
the chip hardware, and place the machine in PALmode. When the HW_REI
instruction is executed at the end of the PALcode routine, the hardware
executes a jump to the address contained in the EXC_ADDR register. Bit 0 in
the EXC_ADDR register indicates PALmode to the hardware. On return from
a PALcode routine, EXC_ADDR register bit 0 is usually clear, and in that case
the hardware loads the new PC, enables interrupts, enables memory mapping,
and dispatches back to the user.

3.3.1 Hardware Dispatch to PALcode
The most basic use of PALcode is to handle complex hardware events, and it is
called automatically when the particular hardware event is sensed. This use
of PALcode is similar to the use of microcode in other architectures. There are
four major categories of hardware-initiated PALcode:
•

When the microprocessor is reset, it enters PALmode and executes the
RESET PALcode. The system remains in PALmode until an HW_REI
instruction is executed and EXC_ADDR register bit 0 is cleared. The

Privileged Architecture Library Code 3–3

system then continues execution in non-PALmode (native mode). While
the initial RESET PALcode is executing, the remaining low-level system
initialization is performed, including any modification to the PALcode base
register.
•

When the microprocessor detects a system hardware error, it invokes one of
several PALcode routines, depending on the type of error. Errors handled
in this way include machine checks, arithmetic exceptions, reserved or
privileged instruction decode, and data fetch errors.

•

When the microprocessor senses an interrupt, it dispatches the interrupt
acknowledgment to a PALcode routine that gathers the necessary
information, then handles the situation appropriately for the particular
interrupt.

•

When a data stream (Dstream) or Istream TB miss occurs, one of
several PALcode routines is called to perform the TB fill. The memorymanagement algorithms or virtual-to-physical page mappings are flexible.
In the simplest case, this can be an automatic one-to-one translation from
virtual-to-physical address. In a typical operating system, these routines
reference page tables and perform the translation and fill based on the
page table contents.

These basic hardware-related functions are difficult to implement efficiently
with typical operating system service routines.

3.3.2 CALL_PAL Instruction
PALcode can also be invoked with the CALL_PAL instruction. This special
instruction dispatches to PALcode at a specific entry point by using the same
steps as hardware-activated PALcode; that is, the pipeline is drained, the
PC is saved, and the appropriate dispatch is made to an offset from the
PALcode base. The difference is that the dispatch is controlled by the program
through an instruction, rather than through a hardware event or error. Also,
CALL_PAL instructions place PC+4 in the EXC_ADDR register.
The CALL_PAL instruction format includes the OPCODE (bits <31:26>) and
the function field (bits <25:0>). The function field specifies the CALL_PAL
routine to be invoked. The microprocessor hardware dispatches support only
a subset of the possible CALL_PAL function values (Section 3.5). CALL_PAL
routines can perform different functions for different operating systems
running on the microprocessor. Unlike the basic hardware-generated PALcode,
the CALL_PAL operations are largely optional and are based on the needs of
the system implementation.

3–4 Privileged Architecture Library Code

A subtle difference exists between hardware-dispatched and CALL_PALdispatched PALcode. Some form of the hardware-invoked PALcode
functions are necessary in most computer systems. For example, when the
microprocessor detects a serious system error, it dispatches to the machine
check (MCHK) PALcode entry point. The exact PALcode that resides at this
entry point can do what is reasonable, based on the needs of the system.
On the other hand, the CALL_PAL instruction dispatch is completely under
control of the executing program. If the program never executes one of the
instructions in the CALL_PAL list, that PALcode will never be run. Any
PALcode that does run, executes in PALmode under the same restrictions as
hardware-activated PALcode.
The microprocessor supports hardware dispatch for both privileged and
nonprivileged CALL_PAL instructions. That is, some of the functions that are
passed to the CALL_PAL instruction are considered special. A CALL_PAL
instruction is privileged or nonprivileged depending on whether the user can
call that particular instruction, not on the mode in which the instruction
eventually runs. Every CALL_PAL instruction dispatches to PALcode that
runs in PALmode.
The difference between privileged and nonprivileged CALL_PAL instructions is
that privileged CALL_PAL instructions can be executed only in kernel mode;
otherwise, they are vectored to 13E0 (OPCDEC, Table 3–5).
Privileged and nonprivileged CALL_PAL instructions are dispatched in
exactly the same way and, when executed, enter PALmode, perform their
function, and return to the user. The user mode is checked before execution.
If a user attempts to execute a privileged CALL_PAL instruction in any
mode other than kernel mode, an OPCDEC PALcode routine, rather than
the CALL_PAL function, is run. An OPCDEC exception is also taken if a
CALL_PAL function code that is not supported by the microprocessor hardware
dispatch is attempted.

3.4 Reserved Opcode Instructions
PALcode uses the Alpha instruction set for most operations. The
microprocessor maps the architecturally reserved opcodes (PALRES0 through
PALRES4) to:
•

Special load and store instructions (HW_LD, HW_ST)

•

Move-to and a move-from processor register instructions (HW_MTPR,
HW_MFPR)

•

Return from a PALmode exception or interrupt instruction (HW_REI)

Privileged Architecture Library Code 3–5

These instructions produce an OPCDEC exception if executed while not in the
PALmode environment. These instructions can be executed in kernel mode if
the hardware enable (HWE) bit is set in the Icache control and status register
(ICCSR, Section 4.1.7).
Register checking and bypassing logic is provided for PALcode instructions and
for non-PALcode instructions, when using general-purpose registers.
Note
Explicit software timing is required for accessing the hardwarespecific internal processor registers (IPRs) and the PALcode temporary
(PAL_TEMP) registers. These constraints are described in Section 3.6
and Chapter 4.

3.4.1 HW_MFPR and HW_MTPR Instructions
PALcode uses the HW_MFPR and HW_MTPR instructions to move data from
and to the IPRs. The IPR specified by the PAL, ABX, IBX, and index field is
written or read with the data from the specified integer register.
Caution
Writing or reading IPRs can have side effects.

Coding restrictions (see Section 3.6) are associated with accessing various
registers. Separate bits are used to access the following registers:
•

LSU registers

•

IDU registers

•

PAL_TEMP registers

It is possible for an HW_MTPR instruction to write multiple registers in
parallel if they both have the same index. (See Table 3–1.)
Figure 3–1 shows the HW_MFPR and HW_MTPR instruction format, and
Table 3–1 describes its fields.

3–6 Privileged Architecture Library Code

Figure 3–1 HW_MFPR and HW_MTPR Instructions Format
31

26 25

OPCODE

21 20

16 15

8 7 6 5 4

P A I
A B B
L X X

IGN

Index

Table 3–1 HW_MFPR and HW_MTPR Format Description
Bits

Field

Description

31:26

OPCODE

The opcode is either 25 (HW_MFPR) or 29 (HW_MTPR).

25:21
20:16

RA
RB

These fields contain the source (HW_MTPR) or destination
(HW_MFPR) register number. RA and RB must be identical.

15:8

IGN

These bits are ignored.

PAL

When this bit is set, the instruction is referencing a PAL
temporary (PAL_TEMP) register.3

ABX

When this bit is set, the instruction is referencing a register in
the LSU.3

IBX

When this bit is set, the instruction is referencing a register in
the IDU.3

4:0

Index

This bit specifies the index within the group.3

3 See Table 3–2.
Table 3–2 indicates how the PAL, ABX, IBX, and INDEX fields are set to access
the registers. Setting the PAL, ABX, and IBX fields to zero generates an NOP.

Table 3–2 Internal Processor Register Access
Mnemonic

PAL

ABX

IBX

Index

Access

Comments

TB_TAG

—

PALmode only

ITB_PTE

—

PALmode only

ICCSR

—

ITB_PTE_TEMP

—

PALmode only
(continued on next page)

Privileged Architecture Library Code 3–7

Table 3–2 (Cont.) Internal Processor Register Access
Mnemonic

PAL

ABX

IBX

Index

Access

Comments

EXC_ADDR

—

SL_RCV

—

ITBZAP

—

PALmode only

ITBASM

—

PALmode only

ITBIS

—

PALmode only

—

EXC_SUM

—

PAL_BASE

—

HIRR

—

SIRR

—

ASTRR

—

HIER

—

SIER

—

ASTER

—

SL_CLR

—

SL_XMIT

—

TB_CTL

—

DTB_PTE

—

DTB_PTE_TEMP

—

MM_CSR

—

DTBZAP

—

DTBASM

—

DTBIS

—

DC_STAT

—

ABOX_CTL

—

ALT_MODE

—

CC_CTL

—

—
(continued on next page)

3–8 Privileged Architecture Library Code

Table 3–2 (Cont.) Internal Processor Register Access
Mnemonic

PAL

ABX

IBX

Index

Access

Comments

FLUSH_IC

—

FLUSH_IC_ASM

—

PAL_TEMP<31:0>

—

31..0

—

3.4.2 HW_LD and HW_ST Instructions
PALcode uses the HW_LD and HW_ST instructions to access memory outside
the realm of normal Alpha memory management. Figure 3–2 shows the
HW_LD and HW_ST instructions format, and Table 3–3 describes its fields.
Figure 3–2 HW_LD and HW_ST Instructions Format
31

26 25

OPCODE

21 20

16 15 14 13 12 11

P A R
Q
H L W
W
Y T C

DISP

The effective address of these instructions is calculated as follows:
addr ( (SEXT(DISP) + RB) AND NOT (QW | 112 )
Table 3–3 HW_LD and HW_ST Format Description
Bits

Field

Description

31:26

OPCODE

The opcode is either 27 (HW_LD) or 31 (HW_ST).

25:21
20:16

RA
RB

These fields specify register numbers, interpreted as is usual for
load and store instructions.

PHY

Physical—When this bit is set, the effective address of the
instruction is a physical address; otherwise, it is a virtual
address.3

3 Physical-mode load-lock (HW_LD/L) and store-conditional (HW_ST/C) variants of the HW_LD and
HW_ST instructions can be created by setting both the PHY and ALT bits.

(continued on next page)

Privileged Architecture Library Code 3–9

Table 3–3 (Cont.) HW_LD and HW_ST Format Description
Bits

Field

Description

ALT

Alternate mode—For virtual-mode HW_LD and HW_ST
instructions, this bit selects the processor mode bits that are
used for memory-management checks. When this bit is set, the
mode bits in the ALT_MODE register are used; otherwise, the
current mode bits of the processor status (PS) register are used.3

RWC

Read-with-write check—When set, this bit enables both read and
write access checks on virtual HW_LD instructions.

Quadword—When set, this bit specifies the data length is
quadword; otherwise, the data length is longword.

11:0

DISP

This field holds a 12-bit, signed, byte displacement.

3 Physical-mode load-lock (HW_LD/L) and store-conditional (HW_ST/C) variants of the HW_LD and
HW_ST instructions can be created by setting both the PHY and ALT bits.

3.4.3 HW_REI Instruction
The HW_REI instruction uses the address in the EXC_ADDR register to
determine the new virtual program counter (VPC). EXC_ADDR register bit
0 indicates the state of the PALmode bit on the completion of the HW_REI
instruction. If EXC_ADDR register bit 0 is set, the processor remains in
PALmode. This allows PALcode to transition from PALmode to non-PALmode.
The HW_REI instruction can also be used to jump from PALmode to PALmode.
This allows PAL instruction flows to take advantage of the Dstream mapping
hardware in the chip, including traps.
Figure 3–3 shows the HW_REI instruction format, and Table 3–4 describes its
fields.
Figure 3–3 HW_REI Instruction Format
31

26 25

OPCODE

21 20

16 15 14 13

1 0

IGN

The next address and PALmode bit are calculated as follows:
VPC ( EXC_ADDR AND {NOT 3}
PALmode ( EXC_ADDR[0]

3–10 Privileged Architecture Library Code

Table 3–4 HW_REI Format Description
Bits

Field

Description

31:26

OPCODE

The opcode is 30.

25:21
20:16

RA
RB

The register numbers contained in these fields should be 1F
(R31); otherwise, a stall may occur.

15:14

These bits contain the branch prediction hint. The microprocessor
pushes the contents of the EXC_ADDR register on the JSR
prediction stack. Bit 15 must be set to pop the stack to avoid
misalignment.

13:0

IGN

These bits are ignored.

3.5 PALcode Entry Points
Table 3–5 lists the PALcode entry points from the highest priority (RESET) to
the lowest priority (FEN). The table defines only the entry point offset, bits
<13:0>. The new PC bits <33:14> come from the PAL_BASE register. At power
up, the PAL_BASE register value is zero.
Note
PALcode at PAL entry points of higher priority than DTB_MISS must
unlock possible locks on the memory-management control and status
register (MM_CSR, Section 4.2.9) and virtual address register (VA,
Section 4.2.8).

Table 3–5 PALcode Entry Points
Entry Name

Time

Offset

Cause

RESET

Anytime

0000

Reset.

MCHK

Anytime

0020

Uncorrected hardware error.

ARITH

Anytime

0060

Arithmetic exception.

INTERRUPT

Anytime

00E0

Interrupt, including corrected hardware
error.

Dstream Errors

Pipe stage 6

01E0, 08E0, 09E0,
11E0

See Table 3–6.
(continued on next page)

Privileged Architecture Library Code 3–11

Table 3–5 (Cont.) PALcode Entry Points
Entry Name

Time

Offset

Cause

ITB_MISS

Pipe stage 5

03E0

ITB miss.

ITB_ACV

Pipe stage 5

07E0

Istream access violation.

CALL_PAL

Pipe stage 5

2000, 2040, 2080,
20C0 through 3FC0

128 locations based on instruction.

OPCDEC

Pipe stage 5

13E0

Reserved or privileged opcode.

FEN

Pipe stage 5

17E0

Floating-point (FP) operation
attempted with:
 FP instructions disabled by the
ICCSR FPE bit
 FP IEEE round to ± infinity
 FP IEEE with data type field other
than S, T, Q

PALcode functions are implemented through the CALL_PAL instruction.
CALL_PAL instructions cause exceptions in the hardware. As with all
exceptions, hardware loads the EXC_ADDR register with a possible return
address.
CALL_PAL exceptions load the EXC_ADDR register with the address of
the instruction following the CALL_PAL instruction, not the address of the
CALL_PAL instruction. PALcode that supports the desired PALmode function
need not increment the EXC_ADDR register before executing an HW_REI
instruction to return to native mode. This feature requires special handling in
the arithmetic trap and machine check PALcode flows. (See Section 4.1.8 for
more information.)
To improve speed of execution, a limited number of CALL_PAL instructions are
directly supported in hardware with dispatches to specific address offsets.
The microprocessor provides the first 64 privileged and 64 unprivileged
CALL_PAL instructions with regions of 64 bytes. This produces hardware PAL
entry points described as follows:
•

Privileged CALL_PAL instructions: 00000000..0000003F
Offset = 200016 + (<5:0> shift left 6)

•

Unprivileged CALL_PAL instructions: 00000080..000000BF
Offset = 300016 + (<5:0> shift left 6)

3–12 Privileged Architecture Library Code

CALL_PAL instructions that fall outside the ranges of 00000000..0000003F and
00000080..000000BF result in an OPCDEC exception. CALL_PAL instructions
that fall within the range of 00000000..0000003F while the microprocessor is
not executing in kernel mode also result in an OPCDEC exception.
The hardware recognizes four classes of Dstream memory management errors:
•

Bad virtual address (VA) (incorrect sign extension)

•

Data translation buffer (DTB) miss (native mode and PALmode)

•

Alignment error

•

Access violation (ACV), fault on read (FOR), fault on write (FOW)

The following errors get mapped into four PAL entry points:
•

UNALIGN

•

DTB_MISS PALmode

•

DTB_MISS native mode

•

D_FAULT

Table 3–6 lists the priority of these entry points as a group. (Also see Dstream
errors, Table 3–5). A particular Dstream memory reference can generate
errors that fall into more than one of the four error classes recognized by the
hardware.
Table 3–6 Dstream Error PAL Entry Points
BAD_VA

DTB_MISS

UNALIGN

PAL

Other3

Offset

11E0 UNALIGN

01E0 D_FAULT

09E0 DTB_MISS PAL

08E0 DTB_MISS NATIVE

11E0 UNALIGN

01E0 D_FAULT

3 ACV, FOR, FOW
1 = error
0 = no error
x = ignored

See Section 3.3 for more information about PALcode entry points.

Privileged Architecture Library Code 3–13

3.6 PALmode Restrictions
Many of the PALmode restrictions involve waiting n cycles before using
the results of a PAL instruction. The typical way to wait for n cycles is
to insert n instructions between two time-sensitive instructions. Because
the microprocessor can dual issue instructions, it is possible to write code
that requires 2 2 n + 1 instructions to wait n cycles. Due to the resource
requirements of individual instructions and the microprocessor’s hardware
design, multiple copies of the same instruction cannot be dual issued.
Following are a few examples of the PALmode restrictions:
•

As a general rule, HW_MTPR instructions require at least four cycles to
update the selected register. At least three cycles of delay must be inserted
before using the result of the register update.
The following instructions will pipeline correctly and do not require
software timing except for accesses to the TB registers:
Multiple read instructions
Multiple write instructions
A read instruction followed by write instruction
These cycles can be guaranteed by either of the following:
Including seven instructions that do not use the register in transition
Proving, through the dual-issue rules or machine state, that at least
three cycles of delay will occur
Multiple copies of an HW_MFPR instruction (used as an NOP instruction)
can be used to pad cycles after the original HW_MTPR instruction.
Multiple copies of the same instruction will never dual-issue; therefore, a
maximum of three instructions are necessary to ensure at least three cycles
of delay.
Example:
HW_MTPR Rx, HIER
HW_MFPR R31, 0
HW_MFPR R31, 0
HW_MFPR R31, 0
HW_MFPR Ry, HIER

; Write to HIER
; NOP mxpr instruction
; NOP mxpr instruction
; NOP mxpr instruction
; Read from HIER

The HW_REI instruction uses the instruction translation buffer (ITB) if
the EXC_ADDR register contains a non-PALmode virtual program counter
(VPC bit 0 = 0). The previous rule implies that at least three cycles of
delay must be included after writing the ITB before executing an HW_REI
instruction to exit PALmode.

3–14 Privileged Architecture Library Code

Exceptions:
HW_MFPR instructions reading a PAL_TEMP register can never
occur exactly two cycles after an HW_MTPR instruction writing a
PAL_TEMP register. The following code solves this problem:
HW_MTPR Rx, PAL_R0
HW_MFPR R31, 0
HW_MFPR R31, 0
HW_MFPR R31, 0
HW_MFPR Ry, PAL_R0

; Write PAL temp [0]
; NOP mxpr instruction
; NOP mxpr instruction
; NOP mxpr instruction
; Read PAL temp [0]

This code guarantees three cycles of delay between the write and the
read instructions. The cycle immediately following an HW_MTPR
instruction can also be used to execute an HW_MFPR instruction to the
same (accomplishing a swap) or a different PAL_TEMP register. The
swap operation only occurs if the HW_MFPR instruction immediately
follows the HW_MTPR instruction. This timing requires great care
and knowledge of the pipeline to ensure that the second instruction
does not stall for one or more cycles. Use of the slot to accomplish a
read from a different PAL_TEMP register requires that the second
instruction will not stall for exactly one cycle. This is much easier
to ensure. An HW_MFPR instruction can stall for a single cycle as a
result of a write-after-write conflict.
The EXC_ADDR register can be read by an HW_REI instruction two
cycles after the HW_MTPR instruction. This is equivalent to one
intervening cycle of delay. Use the following code to perform this
function:
HW_MTPR Rx, EXC_ADDR
HW_MFPR R31, 0
HW_REI
•

; Write EXC_ADDR
; NOP cannot dual issue with
; either Return

An HW_MTPR operation to the data translation buffer invalidate single
register (DTBIS, Section 4.2.7) cannot be sourced from a bypassed path.
All data being moved to the DTBIS register must be sourced directly from
the register file. One way to ensure this is to provide at least three cycles
of delay before using the result of any integer operation (except MUL) as
the source of an HW_MTPR DTBIS instruction.
Note
Do not use an MUL as the source of DTBIS data.

Privileged Architecture Library Code 3–15

Use the following code to perform this function:
ADDQ R1,R2,R3
ADDQ R31,R31,R31
ADDQ R31,R31,R31
ADDQ R31,R31,R31
ADDQ R31,R31,R31
HW_MTPR R3,DTBIS

; source for DTBIS address
; cannot dual issue with above, 1st cycle of delay
; 2nd cycle of delay
; 3rd cycle of delay
; may dual issue with below, else 4th cycle of delay
; R3 must be in register file, no bypass possible

•

At least one cycle of delay must occur after an HW_MTPR TB_CTL
instruction and before an HW_MTPR ITB_PTE or an HW_MFPR ITB_PTE
instruction. This must be done to allow setup of the ITB large page or
small page decode.

•

The first cycle (the first one or two instructions) at all PALcode entry points
cannot execute a conditional branch instruction or any other instruction
that uses the JSR stack hardware, including the following instructions:
JSR
JMP
RET
JSR_COROUTINE
BSR
HW_REI
All Bxx opcodes except BR

•

Table 3–7 lists the number of cycles required after an HW_MTPR
instruction and before an HW_REI instruction for the specified registers.
These cycles can be ensured by inserting one HW_MFPR R31,0 instruction
or other appropriate instructions for each cycle of delay required after the
HW_MTPR instruction.

Table 3–7 HW_MTPR Restrictions
Register

Cycles Between
HW_MTPR and HW_REI

DTBIS, ASM, ZAP

ITBIS, ASM, ZAP

HIER, SIER

HIRR, SIRR

ICCSR (FPE bit)

3–16 Privileged Architecture Library Code

•

When loading the cycle counter register (CC, Section 4.2.13), bits <3:0>
must be loaded with zero. Loading non-zero values in these bits can cause
an inaccurate count.

•

An HW_MTPR DTBIS instruction cannot be combined with an HW_MTPR
ITBIS instruction. The hardware will not clear the ITB if both the
instruction fetch and decode unit registers and the LSU registers are
simultaneously selected. Two instructions are needed to clear each TB
individually. Use the following code to perform this function:
HW_MTPR Rx,ITBIS
HW_MTPR Ry,DTBIS

•

Three cycles of delay are required between the following instructions:
HW_MTPR HIER, SIER
HW_MTPR HIRR, SIRR
HW_MTPR
HW_MTPR
HW_MTPR ALT_MODE

•

and
and
and
and
and

HW_MFPR HIRR, SIRR
HW_MFPR xIRR
HW_LD or HW_ST
HW_MFPR xIRR
HW_LD/HW_ST ALT_MODE

The following operations are disabled in the cycle immediately following an
HW_REI instruction (MxPR = MTPR or MFPR):
— HW_MxPR ITB_TAG
— HW_MxPR ITB_PTE
— HW_MxPR ITB_PTE_TEMP
This rule implies that it is never a good idea to allow exceptions while
updating the ITB. The ITB register will not be written if:
*

An exception interrupts the flow of the ITB miss routine and
attempts to execute an HW_REI instruction. The return address
begins with an HW_MxPR instruction to an ITB register.

The return from the exception interrupt is predicted correctly to
avoid any delay between the two instructions.

The following code demonstrates this situation:
HW_REI
;Return from interrupt
HW_MTPR R1,ITB_TAG ;Attempts to execute very next cycle, instr ignored
•

The following registers can be accessed only in PALmode:
ITB_TAG
ITB_PTE

Privileged Architecture Library Code 3–17

ITB_PTE_TEMP
If the microprocessor is not in PALmode because the hardware enable
(HWE) bit is set in the ICCSR, an HW_MTPR or HW_MFPR instruction to
or from these registers is ignored.
•

When writing the PAL_BASE register, exceptions must not occur. An
exception occurring simultaneously with a write instruction to the
PAL_BASE register can leave the register in a metastable state. All
asynchronous exceptions except reset can be avoided under the following
conditions:
PALmode—Blocks all interrupts
Machine checks disabled—Blocks I/O error exceptions (through the
ABOX_CTL register or MB instruction isolation)
Not under trap shadow—Avoids arithmetic traps
The trap shadow is defined as less than:
*

3 cycles after a non-MUL integer operate that may overflow

22 cycles after an MULL/V instruction

24 cycles after an MULQ/V instruction

6 cycles after a non-DIV floating-point operation that may cause a
trap

34 cycles after a DIVF or DIVS instruction that may cause a trap

63 cycles after a DIVG or DIVT instruction that may cause a trap

•

The sequence HW_MTPR PTE, HW_MTPR TAG is not allowed. At least
two delay cycles must occur between HW_MTPR PTE and HW_MTPR TAG
instructions. This applies to both the ITB and DTB.

•

The MCHK exception service routine must check the EXC_SUM register
for simultaneous arithmetic errors. Arithmetic traps will not trigger
exceptions a second time after returning from exception service for the
machine check.

•

Three cycles of delay must be inserted between HW_MFPR DTB_PTE
and HW_MFPR DTB_PTE_TEMP instructions. Use the following code to
perform this function:

3–18 Privileged Architecture Library Code

HW_MFPR Rx,DTB_PTE
HW_MFPR R31,0
HW_MFPR R31,0
HW_MFPR R31,0
HW_MFPR Ry,DTB_PTE_TEMP
•

; Reads DTB_PTE into DTB_PTE_TEMP register
; First cycle of delay
; Second cycle of delay
; Third cycle of delay
; Read DTB_PTE_TEMP into register file Ry

Three cycles of delay must be inserted between HW_MFPR ITB_PTE
and HW_MFPR ITB_PTE_TEMP instructions. Use the following code to
perform this function:
HW_MFPR Rx,ITB_PTE
HW_MFPR R31,0
HW_MFPR R31,0
HW_MFPR R31,0
HW_MFPR Ry,ITB_PTE_TEMP

; Reads ITB_PTE into ITB_PTE_TEMP register
; First cycle of delay
; Second cycle of delay
; Third cycle of delay
; Read ITB_PTE_TEMP into register file Ry

•

The content of the destination register for HW_MFPR Rx,DTB_PTE and
HW_MFPR Rx,ITB_PTE instructions is UNPREDICTABLE.

•

Two HW_MFPR DTB_PTE instructions cannot be issued in consecutive
cycles. This implies that more than one instruction might be necessary
between the HW_MFPR instructions if dual issue is possible. Similar
restrictions apply to the ITB_PTE register.

•

Reading the EXC_SUM register requires special timing. (See Section 4.1.9
for specific information.)

•

Dstream memory management (DMM) errors occurring one cycle before
HW_MxPR instructions to the ITB_PTE will not stop the TB pointer from
incrementing to the next TB entry even though the HW_MxPR instruction
will be aborted by the DMM error. This behavior affects performance but
not functionality.

•

PALcode that writes multiple ITB entries must write the entry that maps
the address contained in the EXC_ADDR register last.

•

HW_ST instructions cannot be followed for two cycles by any load
instruction that may miss in the Dcache.

•

Updates to the ICCSR ASN field require at least 10 cycles of delay before
entering native mode that can reference the ASN during Icache access. If
the ICCSR HWE bit is used to update the ASN field in kernel mode, it is
sufficient during this time to make all Istream references to pages with the
ASM bit set to avoid use of the ASN field.

•

HW_MTPR instructions that update the TB_CTL register cannot follow
by one cycle an HW_MTPR instruction that updates the DTB_PTE or
ITB_PTE register.

Privileged Architecture Library Code 3–19

•

Table 3–8 shows the delays required for HW_MTPR instructions that
update the ICCSR (ASN field), FLUSH_IC, and FLUSH_IC_ASM
registers.

Table 3–8 HW_MTPR Cycle Delay
Register

Cycles Delay

ICCSR (ASN field only)

FLUSH_IC

FLUSH_IC_ASM

The delay ensures that the update occurs before the first instruction fetch
in native mode, because the pipeline can contain instructions that were
fetched before the update (which would remain valid during a pipeline
stall). At least one instruction must be issued during each cycle of the
delay to ensure that the pipeline is cleared of all instructions fetched prior
to the update.
If the update is performed in kernel mode using the ICCSR HWE bit, it is
sufficient during this time to make all Istream references to pages with the
ASM bit set to avoid use of the ASN field.
•

Machine check exceptions taken while in PALmode can load the
EXC_ADDR register with a restart address one instruction earlier
than the correct restart address. Some HW_MxPR instructions may have
already completed execution although the restart address indicates the
HW_MxPR as the return instruction. Re-execution of some HW_MxPR
instructions can alter the machine state (that is, TB pointers, EXC_ADDR
register mask).
The mechanism that stops instruction flow during machine check
exceptions causes the machine check exception to appear as a Dstream
fault on the following instruction in the hardware pipeline. If the following
instruction is an HW_MxPR instruction, a Dstream fault will not abort
execution in all cases. The EXC_ADDR register will be loaded with
the address of the HW_MxPR instruction as if it were aborted. An
HW_REI instruction to this restart address will incorrectly re-execute this
instruction.
Machine check service routines should check for MxPR instructions at the
return address before continuing.

3–20 Privileged Architecture Library Code

3.6.1 Translation Buffer Miss Flows
Sections 3.6.1.1 and 3.6.1.2 describe hardware-specific details that are helpful
when writing ITB and DTB fill routines. The flows highlight the trade-offs
and restrictions between PALcode and hardware. The PALcode source that is
released with the chip should be referenced before any new flows are written.
The following descriptions assume the reader has a working knowledge of the
Alpha memory-management architecture.
3.6.1.1 Instruction Translation Buffer Miss
When the IDU encounters an ITB miss, it performs the following sequence:
1. Latches the VPC of the target Istream reference in the EXC_ADDR
register.
2. Flushes the pipeline of any instructions that follow the instruction that
caused the ITB miss.
3. Waits for the completion of any other instructions that may be in progress.
4. Enters PALmode.
5. Jumps to the ITB miss PALcode entry point.
The following PALcode sequence is recommended for translating the address
and filling the ITB:
1. Create some scratch area in the integer register file (IRF) by writing the
content of a few integer registers to the PAL_TEMP register file.
2. Read the target virtual address from the EXC_ADDR register.
3. Fetch the page table entry (PTE) (this can take multiple read operations)
using a physical-mode HW_LD instruction. If this PTE valid bit is clear,
either report translation not valid (TNV) or ACV, as appropriate.
4. Check the PTE valid bit because translation buffers cannot contain invalid
PTEs. Also check the ITB PTE RAM to ensure it does not hold the fault
on execute (FOE) bit. If the PTE valid bit is set and the FOE bit is clear,
PALcode can fill an ITB entry.
5. Write the original virtual address to the TB_TAG register, using an
HW_MTPR instruction. This writes the tag into a temporary register
and not into the ITB TAG field.
6. Write the PTE to the TB_CTL register to select either the large-page or
small-page TB regions. Wait at least one cycle before executing the next
step.

Privileged Architecture Library Code 3–21

7. Write the PTE to the ITB_PTE register, using an HW_MTPR instruction.
This HW_MTPR instruction causes the ITB TAG and PTE fields to be
written.
Note
The HW_MTPR instruction to the ITB_PTE register can be issued
without delay after the HW_MTPR instruction to the TB_TAG register
is issued.

8. Restore the contents of any modified integer registers to their original state
using the HW_MFPR instruction.
9. Restart the instruction stream, using the HW_REI instruction.
3.6.1.2 Data Translation Buffer Miss
When the LSU encounters a DTB miss, it performs the following sequence:
1. Latches the referenced virtual address in the virtual address register (VA,
Section 4.2.8) and latches other information about the reference in the
memory management control and status register (MM_CSR, Section 4.2.9).
2. Locks the VA register and MM_CSR against further modifications and
latches the PC of the instruction that generated the reference in the
EXC_ADDR register.
3. Drains the machine (Section 3.6.1.1).
4. Jumps to the DTB miss PALcode entry point.
Unlike ITB misses, DTB misses can occur while the CPU is executing in
PALmode. The recommended PALcode sequence for translating the address
and filling the DTB is as follows:
1. Create some scratch area in the IRF by writing the contents of a few
integer registers to the PAL_TEMP register file.
2. Read the requested virtual address from the VA register. Reading this
register unlocks the VA register and the MM_CSR. The MM_CSR is
updated only when Dstream memory-management errors occur. It retains
information about the instruction that generated the DTB miss for later
use.

3–22 Privileged Architecture Library Code

3. Fetch the PTE. This operation can require multiple read operations. If the
valid bit of the PTE is clear, either a TNV or an ACV must be reported,
unless a FETCH or FETCH_M instruction caused the DTB miss. This
can be checked in the MM_CSR OPCODE field. If the value in this field
is 1816 , a FETCH or FETCH_M instruction caused this DTB miss, and
the subsequent TNV or ACV should not be reported. Therefore, PALcode
should do the following:
a. Read the value in the EXC_ADDR register.
b. Increment the value by four.
c.

Write the value back to the EXC_ADDR register.

d. Execute an HW_REI instruction.
4. Write the register that holds the contents of the PTE to the DTB_CTL
register. This effectively selects one of the four possible granularity hint
sizes.
5. Write the original virtual address to the TB_TAG register. This writes the
tag into a temporary register and not into the DTB TAG field.
6. Write the PTE to the DTB_PTE register. This HW_MTPR instruction
causes the DTB TAG and PTE fields to be written.
Note
It is not necessary to delay issuing the HW_MTPR instruction to the
DTB_PTE register after the HW_MTPR instruction to the TB_TAG
register is issued.

7. Restore the contents of any modified integer registers.
8. Restart the Istream with an HW_REI instruction.

Privileged Architecture Library Code 3–23

4
Internal Processor Registers
This chapter describes the following internal processor registers (IPRs):
•

IDU registers

•

LSU registers

•

PAL_TEMP registers
Note
The abbreviations in the Type column of the register field description
tables indicate field access behavior. The abbreviations are defined in
the Conventions section of the Preface.

The memory controller and I/O controller (IOC) control and status registers
(CSRs) are described in Chapters 5 and 6.

4.1 IDU Registers
Sections 4.1.1 through 4.1.16 describe the IDU registers.

4.1.1 Translation Buffer Tag Register
The write-only translation buffer tag (TB_TAG) register holds the tag for the
next translation buffer update operation in the instruction translation buffer
(ITB) or the data translation buffer (DTB).
The tag is written to a temporary register and not transferred to the ITB
or DTB until the ITB page table entry register (ITB_PTE, Section 4.1.2) or
the DTB page table entry register (DTB_PTE, Section 4.2.3) is written. The
entry to be written is chosen at the time of the ITB_PTE or DTB_PTE write
operation. The DTB replacement algorithm (a not-last-used algorithm or a
round-robin algorithm) is specified by the DTB round-robin enable (DTBRR) bit
in the LSU control register (ABOX_CTL, Section 4.2.1).

Internal Processor Registers 4–1

The page format is determined by the granularity hints (GH) field in the
translation buffer control register (TB_CTL, Section 4.2.2).
Figure 4–1 shows the TB_TAG register formats, and Tables 4–1 and 4–2
describe its fields.
Note
The TB_TAG register is written only while in PALmode, regardless of
the state of the hardware enable (HWE) bit in the instruction cache
control and status register (ICCSR, Section 4.1.7).

Figure 4–1 TB_TAG Register Formats
Small Page Format
63

43 42

13 12

VA
<42:13>

IGN

Large Page Format
63

43 42

22 21

VA
<42:22>

IGN

Table 4–1 TB_TAG Register Small-Page Format Field Description
Bits

Field

Type

Description

63:43

IGN

Ignored when written.

42:13

VA<42:13>

Virtual address bits <42:13>.

12:0

IGN

Ignored when written.

4–2 Internal Processor Registers

IGN

Table 4–2 TB_TAG Register Large-Page Format Field Description
Bits

Field

Type

Description

63:43

IGN

Ignored when written.

42:22

VA<42:22>

Virtual address bits <42:22>.

21:0

IGN

Ignored when written.

4.1.2 Instruction Translation Buffer Page Table Entry Register
The read and write instruction translation buffer page table entry (ITB_PTE)
register represents 12 page table entries split into two distinct arrays. The
first eight page table entries provide small-page (8 KB) translations and
the remaining four provide large-page (4 MB) translations. The entry to be
written is chosen by a not-last-used algorithm (implemented in hardware
independently for each array) and the granularity hints (GH) field in the
translation buffer control register (TB_CTL, Section 4.2.2).
The ITB_PTE register is written using the format described in the Alpha
Architecture Reference Manual, but some fields are ignored.
The ITB tag array is updated from the TB_TAG register (Section 4.1.1) when
the ITB_PTE register is written. Two instructions are required to read the
ITB_PTE register:
1. The first instruction sends the PTE data to the instruction translation
buffer page table entry temporary register (ITB_PTE_TEMP, Section 4.1.3).
2. The second instruction reads the ITB_PTE_TEMP register and returns the
PTE to the register file.
To access the complete set of ITB_PTE register entries, the TB entry pointer
that corresponds to the large- or small-page format (selected by the TB_CTL
register) is incremented when the ITB_PTE register is read or written.
Figure 4–2 shows the ITB_PTE register formats, and Tables 4–3 and 4–4
describe its fields.
Note
The ITB_PTE register is written only while in PALmode, regardless of
the state of the hardware enable (HWE) bit in the instruction cache
control and status register (ICCSR, Section 4.1.7).

Internal Processor Registers 4–3

Figure 4–2 ITB_PTE Register Formats
Write Format
63

53 52

32 31

PFN
<33:13>

IGN

12 11 10 9 8 7 5 4 3 0

IGN

U S E K
A
R R R R IGN S IGN
E E E E
M

Read Format
63

35 34 33

A
S
M

RAZ

13 12 11 10 9 8

U S E K
R R R R
E E E E

PFN
<33:13>

RAZ

Table 4–3 ITB_PTE Register Write-Format Field Description
Bits

Field

Type

Description3

63:53

IGN

Ignored when written.

52:32

PFN<33:13> RW

Page frame number—This field always points to a
page boundary.

31:12

IGN

Ignored when written.

URE

User read-enable—When set, this bit enables user
mode read operations. When this bit is clear, an ACV
occurs if a load or instruction fetch is attempted in
user mode.

SRE

Supervisor read-enable—When set, this bit enables
supervisor mode read operations. When this bit is
clear, an ACV occurs if a load or instruction fetch is
attempted in supervisor mode.

ERE

Executive read-enable—When set, this bit enables
executive mode read operations. When this bit is
clear, an ACV occurs if a load or instruction fetch is
attempted in executive mode.

KRE

Kernel read-enable—When set, this bit enables kernel
mode read operations. When this bit is clear, an ACV
occurs if a load or instruction fetch is attempted in
kernel mode.

3 For more information about the fields, see the Alpha Architecture Reference Manual.
(continued on next page)

4–4 Internal Processor Registers

Table 4–3 (Cont.) ITB_PTE Register Write-Format Field Description
Bits

Field

Type

Description3

7:5

IGN

Ignored when written.

ASM

Address space match—When this bit is set, this PTE
matches all address space numbers (ASNs). For a
given virtual address, this bit must be set consistently
in all processes; otherwise, the address mapping is
UNPREDICTABLE.

3:0

IGN

Ignored when written.

3 For more information about the fields, see the Alpha Architecture Reference Manual.

Table 4–4 ITB_PTE Register Read-Format Field Description
Bits

Field

Type

Description3

63:35

RAZ

Read as zero.

ASM

See the corresponding write-format field description
(Table 4–3).

33:13

PFN<33:13> RW

See the corresponding write-format field description
(Table 4–3).

URE

See the corresponding write-format field description
(Table 4–3).

SRE

See the corresponding write-format field description
(Table 4–3).

ERE

See the corresponding write-format field description
(Table 4–3).

KRE

See the corresponding write-format field description
(Table 4–3).

8:0

RAZ

Read as zero.

3 For more information about the fields, see the Alpha Architecture Reference Manual.

4.1.3 Instruction Translation Buffer Page Table Entry Temporary
Register
The instruction translation buffer page table entry temporary (ITP_PTE_TEMP)
register is a read-only holding register for ITB_PTE read data. Two
instructions are required to read the ITB_PTE register (Section 4.1.2) and
to return data to the integer register file:

Internal Processor Registers 4–5

1. The first instruction reads the ITB_PTE register data to the ITB_PTE_TEMP
register.
2. The second instruction reads the ITB_PTE_TEMP register data to the
integer register file.
The ITB_PTE_TEMP register is updated on all ITB read accesses and write
accesses. A read of the ITB_PTE register to the ITB_PTE_TEMP register
should be followed closely by a read of the ITB_PTE_TEMP register to the
register file.
Note
The ITB_PTE_TEMP register is read only while in PALmode,
regardless of the state of the hardware enable (HWE) bit in the
instruction cache control and status register (ICCSR, Section 4.1.7).

The ITB_PTE_TEMP register format and fields are the same as the ITB_PTE
register read format shown in Figure 4–2 and described in Table 4–4.

4.1.4 Instruction Translation Buffer ZAP Register
A write operation to the instruction translation buffer ZAP (ITBZAP) register
invalidates all 12 ITB entries. It also resets both not-last-used (NLU) pointers
to their initial state. The ITBZAP register is written only in PALmode.

4.1.5 Instruction Translation Buffer ASM Register
A write operation to the instruction translation buffer ASM (ITBASM) register
invalidates all ITB entries in which the address space match (ASM) bit equals
zero. The ITBASM register is written only in PALmode.

4.1.6 Instruction Translation Buffer Invalidate Single Register
A write operation to the instruction translation buffer invalidate single (ITBIS)
register invalidates the ITB entry that maps the virtual address held in
the integer register. The integer register is identified by the Rb field of the
HW_MTPR instruction used to perform the write operation.

4–6 Internal Processor Registers

4.1.7 Instruction Cache Control and Status Register
The instruction cache control and status register (ICCSR) contains various IDU
hardware enable bits and fields.
The only architecturally defined bit in this register is the floating-point enable
(FPE) bit, which enables floating-point instructions. Hardware clears all of the
bits in this register at reset, except for the ASN field and performance counter
interrupt enable bits PC0 and PC1.
The HWE bit allows the special PALcode instructions to execute in kernel
mode. This bit is only for diagnostic routines or operating system alternative
PALcode routines. It does not allow access to the ITB registers while not in
PALmode.
Figure 4–3 shows the ICCSR formats, and Tables 4–5 and 4–6 describe its
fields.
Figure 4–3 ICCSR Formats
Write Format
63 53 52

MBZ

47 46 45 44 43 42 41 40 39 38 37 36 35 34

ASN
<5:0>

R
E
S

P
C
E
N

32 31 12 11

8 7 5 4 3 2 1 0

P
P
B J B
R P
R F M H
I
D
PC
PC
H S P
E P A W
MBZ
MBZ E C MBZ C
P MUX1
I
MUX0
1
E E E
S 0
S E P E
E

Read Format
63

35 34 33

RAZ

R
E
S

28 27 26 25 24 23 22 21 20 19 18 17 16 15

ASN
<5:0>

R
E
S

P
C
E
N

13 12

P
R F M H
B J B
D
I
PC
E P A W
H S P
I
P MUX1
S E P E
E E E
E

9 8

PC
MUX0

3 2 1 0

RAZ

P P R
C C A
1 0 Z

Internal Processor Registers 4–7

Table 4–5 ICCSR Write-Format Field Description
Bits

Field

Type

Description

63:53

MBZ

Must be zero.

52:47

ASN<5:0>

Address space number—This field is used in
conjunction with the Icache to further qualify cache
entries and avoid some cache flushes. The ASN
is written to the Icache during fill operations and
compared with the Istream data on fetch operations.
Mismatches invalidate the fetch without affecting the
Icache.

RES

Reserved by Digital and should not be used.

45:44

PCEN

Performance counter enable—When either bit is set,
both performance counters increment. When both bits
are clear, both performance counters are disabled.

RES

Reserved by Digital and should not be used.

FPE

Floating-point enable—When this bit is set, floatingpoint instructions can be issued. When this bit is
clear, floating-point instructions cause FEN exceptions
(Section 3.5).

MAP

Superpage map enable—When set, this bit enables
superpage Istream memory mapping of VPC<33:13>
directly to physical PC<33:13>, essentially bypassing
the ITB when VPC<42:41> = 2. Superpage mapping
is allowed only in kernel mode. The Icache ASM bit
is always set. When clear, this bit disables superpage
mapping.

HWE

Hardware enable—When this bit is set, the five
PALRES instructions (Section 3.4) can be issued in
kernel mode. When this bit is clear, attempts to
execute PALRES instructions while not in PALmode
result in OPCDEC exceptions (Section 3.5).

Dual issue enable—When set, this bit enables
instruction dual issue. When this bit is clear, only
one instruction can be issued for each CPU cycle.

BHE

Branch history enable—This bit is used in conjunction
with the BPE bit (<36>) (Table 4–7).
(continued on next page)

4–8 Internal Processor Registers

Table 4–5 (Cont.) ICCSR Write-Format Field Description
Bits

Field

Type

Description

JSE

JSR stack enable—When set, this bit enables the JSR
stack to push return addresses. When this bit is clear,
the JSR stack is disabled. See the Alpha Architecture
Reference Manual for more information about the JSR
stack.

BPE

Branch predict enable—This bit is used in conjunction
with the BHE bit (<38>) (Table 4–7).

PIPE

When this bit is set, the pipeline proceeds normally.
When this bit is clear, all hardware-interlocked
instructions drain the machine and wait for the write
buffer to empty before issuing the next instruction.
Instructions that do not cause the pipe to drain
include HW_MTPR, HW_REI, conditional branches,
and instructions that specify R31 as a destination
register.

34:32

PCMUX1

Performance counter 1 multiplexer—See Section 4.1.14
for more information.

31:12

MBZ

Must be zero.

11:8

PCMUX0

Performance counter 0 multiplexer—See Section 4.1.14
for more information.

7:5

MBZ

Must be zero.

RES

Reserved by Digital and should not be used.

PC0

Performance counter 0 interrupt request enable—The
PC0 interrupt request is enabled after 212 events are
counted when this bit is set, and after 216 events are
counted when this bit is clear.

2:1

MBZ

Must be zero.

PC1

Performance counter 1 interrupt request enable—The
PC1 interrupt request is enabled after 28 events are
counted when this bit is set, and after 212 events are
counted when this bit is clear.

Internal Processor Registers 4–9

Table 4–6 ICCSR Read-Format Field Description
Bits

Field

Type

Description

63:35

RAZ

Read as zero.

RES

Reserved by Digital and should not be used.

33:28

ASN<5:0>