Alpha 21066 and Alpha 21066A Microprocessors Hardware Reference Manual

This Hardware Reference Manual provides a comprehensive description of the Alpha 21066 and Alpha 21066A microprocessors, detailing their architecture, internal design, and external interfaces. It is intended for system designers, software developers, and hardware engineers.

Key aspects covered include:

1. Architecture Overview: Both microprocessors implement a 64-bit, load/store RISC architecture, emphasizing speed, multiple instruction issue, and multi-operating system support. The 21066A offers higher clock frequencies and additional features like power management and internal cache parity.
2. Internal Design: The chips integrate a core CPU (with Integer, Floating-Point, Load/Store, and Instruction Fetch/Decode Units), a high-bandwidth memory controller, an industry-standard I/O controller (PCI IOC), an embedded graphics accelerator, and internal instruction and data caches (8KB each, direct-mapped).
3. Instruction Processing: The CPU uses superscalar, superpipelined design with dual-instruction issue capabilities, featuring 7-stage (integer) and 10-stage (floating-point) pipelines, and sophisticated branch prediction logic.
4. Memory Management: On-chip demand-paged memory management units include Instruction and Data Translation Buffers (ITBs and DTBs) supporting various page sizes and superpage mapping. An optional external write-back backup cache (Bcache) is also controlled on-chip.
5. Privileged Architecture Library (PALcode): A unique feature providing operating system primitives for context switching, interrupts, exceptions, and memory management, with direct access to low-level hardware functions.
6. Controllers & Interfaces: Detailed descriptions of the memory controller (DRAM/VRAM support, ECC, graphics operations) and the PCI I/O controller (scatter-gather mapping, parity support, CPU-initiated and peripheral-initiated PCI cycles).
7. Registers and Timing: The manual provides in-depth information on internal processor registers, memory controller registers, and I/O controller registers, along with detailed cycle timing diagrams.
8. Initialization and Testing: It covers Icache initialization via a Serial ROM (SROM) interface (which can also function as a diagnostic port) and JTAG (IEEE 1149.1) test port implementation.

In essence, the document serves as a detailed technical guide for understanding, designing with, and programming the highly integrated Alpha 21066 and 21066A microprocessors.