Digital PDFs

DEC-11-HMELA-B-D

November 1973

102 pages

Original

43MB

view download

OCR Version

22MB

view download

Document:	Me11-L Core Memory System Manual
Order Number:	DEC-11-HMELA-B-D
Revision:	0
Pages:	102
Original Filename:

OCR Text

DEC-11-HMELA-B-D

‘”

ME11-L

core memory

system manual

* digital equipment corporation - maynard, massachusetts

Ist Edition, July 1972
2nd Printing, October 1972

3rd Printing (Rev) December 1972
4th Printing, May 1973
5th Printing, November 1973

The material in this manual is for informational purposes and is subject to change without
notice.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS
Page
CHAPTER 1

GENERAL INFORMATION

1.1

Introduction

1-1

1.2

Functional Description

1-1

1.2.1

Unibus

1-2

1.2.2

Memory

1-2

1.2.3

Power Supply

1.2.4

Mounting Box

1-2

1.3

Physical Description

1-2

1.4

ME11-L Specifications

1-5

1.5

Installation

1-5

1.5.1

Mounting the Computer on Installed Slides

1-7

1.5.2

Installation of Side and Top Cover

1-7

1.5.3

Connection of the AC Power Supply

1-7

1.5.4

Instructions for Connection to Other Than 115V

1-7

1.5.5

Quality of AC Power Source

1-7

1.5.6

ME11-L Power Control

1-8

1.5.7

Installing the Unibus Cable

1-8

CHAPTER 2

POWER SUPPLY

2.1

Introduction

2-1

2.2

General Description

2-1

2.2.1

Physical Description

2-1

2.2.1.1

Power Control

2-1

2.2.1.2

Power Chassis Assembly

2-2

2.2.1.3

DC Regulator Module

2-2

2.2.14

DC Cable

2-5

2.2.1.5

AC Cable

2-5

2.2.2

Specifications

2-5

2.3

Detailed Description

2.3.1

AC Input Circuit

2-10

2.3.2

DC Regulator Module Operation

2-10

2.3.2.1

Generation of * Raw DC

2-10

2.3.2.2

BUS AC LO L and BUS DC LO L Circuits

2-12

2.3.2.3

+5V Regulator Circuit

2-15

2.3.2.4

- 15V Regulator Circuit

2-16

Maintenance

2-16

2.4.1

Adjustments

2-17

2.4.2

Circuit Waveforms

2-17

24.3

Troubleshooting

2-19

2.4.3.1

Troubleshooting Rules

2-19

2.4.3.2

Troubleshooting Hints

2-19

2.4.3.3

Troubleshooting Chart

2-21

244

Parts Identification

2-22

CONTENTS (Cont)
Page

CHAPTER 3

MMI11-L CORE MEMORIES

3.1

Introduction

3-1

3.2

General Description

3-1

3.2.1

Physical Description

3-1

3.2.2

Specifications

3-1

3.2.3

Functional Description

3.2.3.1

Introduction

3-2

3.2.3.2

Control Module (G110)

3-2

3.2.3.3

Drive Module (G231)

3-5

3.2.3.4

Stack Module (H214)

3-7

3.2.4

Basic Memory Operation

3.2.4.1

Data In (DATI) Cycle

3.2.4.2

Data In, Pause (DATIP) Cycle

3-7

3.2.4.3

Data Out (DATO Cycle)

3-7

3.2.4.4

Data Out, Byte (DATOB) Cycle

3-8

3-7

3.3

Detailed Description

3-8

3.3.1

Core Array

3-8

3.3.2

Memory Operation

3-8

3.3.3

Device and Word Selection

3-11

3.3.3.1

Memory Organization and Addressing Conventions

3-11

3.3.3.2

Device Selector

3-15

3.3.3.3

Word Selection

3-18

3.3.4

Read/Write Current Generation and Sensing

3-24

3.3.4.1

Read/Write Operations

3-24

3.3.4.2

X- and Y-Current Generators

3-26

3.3.4.3

Inhibit Driver

3-28

3.3.4.4

Sense Amplifier

3-29

3.3.4.5

Memory Data Register

3-29

3.3.5

Stack Discharge Circuit

3-30

3.3.6

DC LO Circuit

3-31

3.3.7

Operating Mode Selection Logic

3-32

3.3.8

Control Logic

3-33

3.3.8.1

Timing Circuit

3-33

3.3.8.2

Slave Synchronization (SSYN) Circuit

3-39

3.3.8.3

Pause/Write Restart Circuit

3-40

3.3.8.4

Strobe Generating Circuit

3-43

3.3.8.5

Data In (DATI) Operation

3-45

3.3.8.6

Data In Pause (DATIP) Operation

3-47

3.3.8.7

Data Out (DATO) Operation

3-47

3.3.8.8

Data Out Byte (DATOB) Operation

3-48

3.4

Maintenance

3-48

3.4.1

Preventive Maintenance

3-49

3.4.1.1

Initial Procedures

3.4.1.2

Checking Output of Current Generators

3-49

CONTENTS (Cont)
Page

Corrective Maintenance

3-49

3-50

3.4.2.2

Strobe Delay Check and Adjustment
Corrective Maintenance Aids

3.4.3

Programming Tests

3-50

3.4.3.1

Address Test Up (MAINDEC-11-D1A)

3-50

3.4.2

3.4.2.1

3.4.3.2

3.43.3
3434

3.4.3.5

3-50

Address Test Down (MAINDEC-11-D1B)
No Dual Address Test (MAINDEC-11-D1C)

Basic Memory Patterns Test (MAINDEC-11-D1D)
Worst Case Noise Test (MAINDEC-11-D1G)

3-57
3-57

APPENDIX A INTEGRATED CIRCUIT DESCRIPTIONS

A.l

Introduction

A.2

SN74121 Monostable Multivibrator

SN7528 Dual Sense Amplifiers with Preamplifier Test Points

A-1

A-1
A-2

ILLUSTRATIONS
Title

Figure No.

Page

1-1

ME11-L Functional Block Diagram

1-1

1-2

ME11-L Mounting Box

1-3

Rear View of ME11-L

1-3

1-4

ME11-L without Memory Modules

1-4

1-5

Memory Section ME11-L

1-4

1-6

Power Supply Section of ME11-L

1-5

1-7

ME11-L Shipping Carton

1-6

1-8

Unibus Cable Connection

1-8

2-1

Power Chassis Assembly

2-2

DC Regulator Module

2-4

2-3

H740 Output Connector (5409728 Regulator Module)

2-4

AC Interconnection Diagram

2-11

2-5

115V Connections, Simplified Schematic Diagram

2-12

2-6

230V Connection, Simplified Schematic Diagram

2-12

2-7

DC Regulator Module, Block Diagram

2-13

2-8

Rectifier Circuit

2-14

2-9

BUS AC LO and BUS DC LO Circuits

2-14

2-10

+5V Regulator Circuit

2-15

2-11

- 15V Regulator Circuit

2-17

2-12

2-18

2-13

+5V Regulator Circuit Waveforms
- 15V Regulator Circuit Waveforms

3-1

Component Side of Control Module G110

2-9

2-20

3-2

Component Side of Drive Module G231

3-3

Component Side of 8K Stack Module H214

3-4

ILLUSTRATIONS (Cont)

Figure No.

Title

Page

3-4

MM11-L Memory Block Diagram

3-5

Three-Wire Memory Configuration

3-9

3-6

Hysteresis Loop for Core

3-7

Three-Wire 3D Memory, Four Mats Shown for a 16-Word by 4-Bit Memory

3-10

3-8

Device and Word Address Selection Logic, Block Diagram

3-9

Memory Organization for 8K Words

3-6

3-12
3-13

3-14

3-10

Address Assignments for Three Banks of 8K Words Each

3-11

Jumper Configuration for a Specific Memory Address

3-16

3-12

Device Decoding Guide

3-17

3-13

Type 8251 Decoder, Pin Designation and Truth Table

3-14

3-19

Decoding of Read/Write Switches and Drivers Y4—Y7

3-15

3-20

Switch or Driver Base Drive Circuit

3-21

3-16

Y-Line Selection Stack Diode Matrix

3-22

3-17

Typical Y-Line Read/Write Switches and Drivers

3-23

Interconnection of Unibus, Data Register, Sense Amplifier, and Inhibit

3-25

3-18

Driver

3-15

3-19

Y-Current Generator and Reference Voltage Supply

3-20

Sense Amplifier and Inhibit Driver

3-28

3-21

Type 7528 Dual Sense Amplifiers with Preamplifier Test Points

3-30

3-22

Stack Discharge Circuit

3-31

3-23

DC LO Circuit, Schematic Diagram

3-32

3-24

Basic Timing and Control Signal Functions

3-35

3-25

TWID H and TNAR H Control Logic

3-26

Generation of MSEL RESETL

3-27

3-37

3-38

3-27

Slave Synchronization (SSYN) Circuit and Timing Diagrams |

3-28

Pause/Write Restart Circuit

3-43

3-29

Strobe Generating Circuit and Timing Diagram

3-44
3-46

3-41

3-30

Flow Chart for Memory Operation

3-31

Strobe Pulse Waveform

3-50

3-32

Troubleshooting Chart

3-51

3-33

MM11-L Sense/Inhibit Waveforms

3-53

3-34

Drive Waveforms

3-55

TABLES
Table No.

1-1

2-1

Title

Page

ME11-L Basic Specifications

1-5

Power Supply Input Specifications

2-5

2-2

Power Supply Output Specifications

2-6

2-3

Mechanical and Environmental Specifications

2-8

2-4

Power Supply Troubleshooting Chart

2-21

3-1

MM1 1-L Memory Specifications

3-4

TABLES (Cont)
Table No.

Title

Page

Addressing Functions

3-13

3-3

Enabling Signals for Word Register Gating

3-18

3-4

Word Address Decoding Signals

3-24

3-5

Selection of Bus Transactions

3-32

3-6

Generation of Memory Operating Signals

3-34

3-2

vii

INTRODUCTION

The ME11-L Core Memory System is a Unibus-compatible PDP-11 family peripheral. Throughout this manual
the ME11-L Memory System is referred to as the ME1 1-L and core memory is referred to as the memory. The

ME]1 1-L consists of a basic 8K MM11-L Read/Write Core Memory, a Power Supply, and a mounting box. The
memory within the mounting box, powered by the Power Supply, is expandable in 8K (MM11-L) increments to

24K.
This manual provides the user with the theory of operation and maintenance information necessary to understand the ME11-L. The level of discussion assumes that the user is familiar with basic digital computer theory
and basic PDP-11

use.

Signals and data are transferred between the ME1 1-L and the PDP-11 Unibus; however, this manual does not describe the operation of the Unibus. A detailed description of the Unibus is found in the PDP-11 Peripherals and

Interfacing Handbook.
Engineering drawings are referenced by drawing number and may be found in the ME[1-L Engineering Drawing
Manual.

This manual is divided into three chapters. Chapter 1 provides a functional description, a physical description,
ME11-L specifications, and installation information. Chapter 2 contains the general description, detailed description, and maintenance information regarding the Power Supply of the ME11-L. Chapter 3 provides a general de-

scription, a detailed description, and maintenance information regarding the 8K MM11-L Memory used in the
ME11-L. Appendix A contains integrated circuit (IC) descriptions for the ICs used in the ME11-L.

CHAPTER 1

1.1

INTRODUCTION

The ME11-L is a 900-ns memory system for the PDP-11 computer family. The basic system consists of an 8K,

16-bit, read/write memory contained in its own mounting box with a Power Supply. The memory may be expanded in 8K (MM11-L) increments to 24K. All the necessary cables are included with the rack-mountable

5-1/4 X 19 inch mounting box. By containing its own power supply, the memory unit saves up to 8.1A of power

in the processor box.
1.2

FUNCTIONAL DESCRIPTION

Figure 1-1 shows the functional block diagram of the ME11-L unit. The additional memories are the optional
8K increments to the basic ME11-L unit. Two configurations of the ME11-L are possible depending on the

power source to the unit: ME11-LA is for a power source
of 115 Vac, 60 Hz; and the ME11-LB is for a power
source of 230 Vac, 50 Hz. The additional 8K memory increments, optional for the ME11-L, are designated as

the MM11-L Memory. The functional units
of the ME11-L are the Unibus, the memory, the Power Supply, and
the mounting box.

VAN

5 174 X 19 INCH MOUNTING BOX

—l

MM11-L

MEMORY

(8K)

—

1T
9

MEMORY

EXPANSION

EXPANSION
OPTION

“

OPTION

’

+5V

MORY

AC LINE VOLTAGE, JEr'Dower

POWER

SUPPLY

’

- .’AC’LQ aus‘

( ‘

DCLO BUS |

‘

Figure 1-1

MEI11-L Functional Block Diagram

1-1

=172

1.2.1

Unibus

The Unibus is an asynchronous, single high-speed bus. All PDP-11 components and peripherals communicate
through the Unibus on its bi-directional lines. Like all PDP-11 peripherals, the ME11-L has its own bus addresses
which are the memory location addresses. Communications via the Unibus do not require timing pulses; there-

fore, DEC-designed memories of various speeds can be combined in the same PDP-11 System. Because all peripherals share the Unibus, the system includes direct memory accessing (DMA) which is implemented through non-

pmc:esmr’reQuests (NPRs); Data rate on the Unibus is 40 megabits per second or 2.5 million words per second
with a cycle of 400 ns. For detailed information regarding the Unibus, refer to the PDP-11 Peripherals and Interfacing Handbook.
1.2.2

Memory

The basic 8K memory unit for the ME11-L is the MM11-L, a 16-bit read/write core-type memory. It pmvides
8192 (8K) 16-bit words that are word and byte addressable. Unibus address lines 14 through 17 are the ME11-L

device portion of the address. This portion of the address is assigned to the ME11-L according to its use in the
system. The remaining portion of the address (address lines 0 through 13) refers to the specific memory location.
The memory consists of three modules: the G110 Hex Module contains the memory control logic; the G231
Hex Module contains the memory driver logic; and the H214 Quad Module is the memory core stack. The G231

is located between the G110 and the H214. See Chapter 3 for more detailed information on the memory. Paragraph 1.3 describes the memory modules in their ME11-L configuration.

1..2..‘3 | Power Supply
The Power Supply for the ME1 1-L supplies four outputs to the unit. These outputs are: +5V which provides

the memory logic levels; =15V which supplies the memory drive circuits; and BUS AC LO and BUS DC LO
which provide the power fail signals to the Unibus. The Power Supply is discussed in detail in Chapter 2.
1.2.4

Mounting Box

The ME11-L mounting box is a 5-1/4 inch high, 19 inch wide, by 20 inch deep cabinet. It contains all the cabling

necessary to interface the units of the ME11-L and provide power. It also provides for the Unibus connection

-and contains the backplane for interconnection of the memory modules. Details of the mounting box are discussed in Paragraph 1.3.

1.3

PHYSICAL DESCRIPTION

The ME11-L Memory System is shipped in the ME11-L mounting box shown in Figure 1-2. Through the use of
photographs, this paragraph describes the ME11-L components and their location in the mounting box. Engi-

neering drawings in the ME11-L Engineering Drawing Manual are referenced to provide additional physical information.

Figure 1-3 shows the rear of the ME1 1-L mounting box. The Power Supply is behind the vents on the left side

of the box. All connections to the ME11-L unit are made at the rear of the mounting box. Power is supplied
through the line cord to the Power Control unit (115 or 230 Vac). The Unibus enters and is secured to the

ME11-L on the right side of the top rear of the mounting box. The reset button resets the Power Control circuit
breaker, which opens when the line current exceeds 7A for the 115-Vac Power Control option
or 4A for the
230-Vac Power Control option.

1-2

Figure 1-2

PDP-11

ME]11-L Mounting Box

SYSTEM

AC POWER CONTROL

CONNECTORS

LINE CORD

POWER SUPPLY

UNIBUS ENTRANCE

/ POWER CONTROL CIRCUIT

BREAKER RESET BUTTON

Figure 1-3

MEMORY SECTION

Rear View of ME11-L

Figure 1-4 shows the memory side of the mounting box without any modules plugged into the module slots.

When looking at the front of the unit, the memory side is on the left. The backplane divides the memory section
of the unit from the Power Supply. The module slots of the backplane unit and the module guides secure the
modules in the unit. Figure 1-5 shows the memory section again, but with modules for a basic 8K (MM 11-L)

of memory plugged into the unit. (Refer to engineering drawing D-MU-ME11-L-01 for module utilization information.)

Figure 1-6 shows the Power Supply section of the ME11-L mounting box. This includes the Power Supply fan at

the front of the unit, the DC Regulator Module, and the Power Control Mate-N-Lok output connector. (Refer
to engineering drawing E-IA-5409728-0-0 for DC Regulator Module assembly information. The wiring side of

1-3

POWER SUPPLY

BACK PLANE

SECTION

i
o

MODULE GUIDES

MEMORY SECTION

Figure 1-4

MODULE SLOTS

ME11-L without Memory Modules
MODULE SLOTS FOR
UP TO 16K MORE OF MEMORY

"H214 STACK

MODULE

~G231 DRIVER MODULE
"NG110 CONTROL MODULE

Figure 1-5

Memory Section ME11-L

1-4

8K OF BASIC

MM11-L MEMORY

POWER CONTROL
MATE - N~ LOK
CONNECTOR

TRANSFORMER

OC
REGULATOR
MODULE

POWER
SUPPLY
FAN

“

‘

.
-

BACKPLANE

Figure 1-6

Power Supply Section of ME11-L

the backplane and the Power Supply connections to the backplane are also shown in Figure 1-6. The ME11-L
unit is shown on engineering drawing D-UA-ME11-L-0 (2 sheets).

1.4

MEI11-L SPECIFICATIONS

The basic specifications for the ME11-L as a unit are listed in Table 1-1. Detailed specifications for the
Power

Supply and the memory are provided in Paragraphs 2.2.2, and Table 3-1.

1.5

INSTALLATION

Table 1-1

ME11-L Basic Specifications

The ME11-L is shipped, ready to operate, in the protective carton shown in Figure 1-7. There are no special
|

shipping mounts internal to the carton. Additional hardo

ware is included, however, to rack mount the ME1 1-L
'

mounting box.
e

Specifications
)

)

cycled, vibrated, and subjected to mechanical shock

The 5-1/2 by 19 inch by 20 inch ME11-L mounting box

Description
|

Cycle Time

900 ns
350w

)

‘

T?mpm:a ture
Dimensions

with all modules in place.

includes rack mountable slides. The removable top

Power

Voltage

Prior to final electrical testing, each ME1 1-L is thermal
“

115/230V
«-)

,}m

5-1/4 in. (13.3 c¢m) high

19 in. (48.3 cm) wide

20 m* {50“ 8 cm) deep

Weight

3"”"’ m ;i 22 IQ (O to 50, )

45 1b (20.6 kg)

le—— FOAM

€

FOLDED CORRUGATED

LAMINATED CEE

BEZEL PROTECTOR

POLYETHYLENE BAG
20x13x40

OUTER CARTON WITH
INTERIOR PIECES

11-1223

Figure 1-7 MEI11-L Shipping Carton

cover of the mounting box is fastened by four Cam-Loc screws. The removable side panel is fastened by four
Phillips Head screws.

The ME11-L is designed to be mounted in a standard 19 inch wide by 20 inch deep equipment bay. The ME11-L

is mounted on slides for easy service. To mount the unit it is first necessary to attach the fixed portion of the
slides to the cabinet. The fixed portion of the slides can be removed from the ME11-L by actuating the slide

release which is located toward the rear of the mounting box, when the slides are fully extended. Be sure to
mount the slides such that the fixed guides are parallel and level with the ground.
1.5.1

Mounting the Computer on Installed Slides

Once the slide guides have been securely fastened in the cabinet using all eight screws, lift the ME11-L and slide
it c%refully on to the slide guides until the slide release locks. Carefully lift the slide release and push the ME11-L
fully into the rack, being careful not to tear any existing cabling.

The ME11-L should then be fully extended until the slide release locks. The covers on the top and side of the
ME11-L should be removed to permit installation of the Unibus. The covers are removed by loosening four CamLoc and Phillips Head screws, respectively.

1.5.2 Installation of Side and Top Cover

Attached to the side cover is the continuation of the left-hand slide. All four 8-32 screws that hold the cover in
place should be inserted and tightened securely. The top cover can now be installed using the four Cam-Loc
SCTEWS.

1.5.3

Connection of the AC Power Supply

The ME11-L is designed for use on 115-Vac circuits in the United States and is equipped with a 3-pronged connector. This connector, when inserted into a properly wired 115-Vac outlet, grounds the mounting box. It is

dangerous to operate the ME11-L unless the mounting box is grounded because normal leakage current from the
Power Supply flows into metal parts of the chassis.

If there is any question about the integrity of the ground circuit, the user is advised to measure the potential between the ME11-L mounting box and a known ground with an ac voltmeter.
1.5.4

Instructions for Connection to Other Than 115V

The ME11-L operates at voltages ranging from 95V to 135V and from 190V to 270V 47 Hz—63 Hz, providing
the proper power control is connected. The unit is ordered for nominal voltages of 115 or 230. The standard

3-pronged connector for 115V is identical with that found on most household appliances. A different 3-pronged
connector is used for 230V.

On installations outside of the United States or where the National Electrical Code does not govern building wiring, the user is advised to proceed with caution.

1.5.5

Quality of AC Power Source

The ME11-L is a complex electronic device. Computer systems consisting of a processor, memory, and peripherals are often sensitive to interference present on some ac power lines. If a computer system is to be installed in

1-7

an electrically “noisy’” environment, it may be necessary to condition the ac power line. DEC Field Service
engineers can assist in determining if the ac line is satisfactory.

1.5.6

MEI11-L Power Control

The ME11-L contains two standard 3-pin connectr

ss used for ac power control in PDP-11 Systems. These con-

nectors are not used in the ME11-L. They do not affect the power in the ME1 1-L mounting box, nor does

the status of the power in the ME11-L affect the power bus. The ME11-L must be plugged into a source of
switched ac power in order for its power to rise and fall with the rest of the system.

1.5.7

Installing the Unibus Cable

The wide BC11A Unibus Cable should be folded as shown in Figure 1-8 and routed over and through the clamp

attached to the top of the fan. Note that there is a guide extending over the fan from the rear of the mounting

box that prevents the Unibus cable from blocking the air flow of the ME11-L.

UNIBUS

CABLE
CLAMP

Figure 1-8

Unibus Cable Connection

CHAPTER 2

2.1

INTRODUCTION

This chapter is divided into three sections: general description, detailed description, and maintenance. The general description section provides a functional description, physical description, and specifications for the Power
Supply unit. The detailed description section provides a circuit level description of the AC Input Circuit and the
DC Regulator Module of the Power Supply. Finally, the maintenance section provides information necessary for
|
troubleshooting the Power Supply and for parts identification.
2.2

GENERAL DESCRIPTION

The Power Supply is a forced-air-cooled unit which converts single phase 115V or 230V nominal 47 to 63 Hz
line voltage to the two regulated output voltages required by the memories. The output voltages and their prin-

cipal uses and characteristics are: +5V for IC logic (switching regulawd, overvoltage and overcurrent protected),

and - 15V for core memory (switching regulated, overvoltage and overcurrent protected). |
The supply is used in conjunction with two Power Control Assemblies which contain a line cord, circuit breaker,
and RFI capacitors.

The power circuitry also generates BUS AC LO L and DC LO L power fail early warning signals.

A thermal control mounted on the heat sink will interrupt the ac input ahauld, the heat sink tem'pemmmbamme
excessive due to fan failure or other cause.
2.2.1

Physical Description

The Power Supply comprises three major subassemblies and two cables: th& Power Control, Power Chassis As-

sembly, DC Regulator Maule,, DC Cable, and AC Cable.

221.1 Power Control Unit — The Power Control Unit (drawing H400-0-0) i§ mounted on the rear of the
computer by two screws. It contains a line cord, circuit breaker, RFI capacitors, 115V or 230V connections

for the Power Supply transformer and a 6-socket Mate-N-Lok mutput connector. Physically, it consists of a

sheet-metal bracket and a slide-on cover which is locked in place by one screw. A single-pole thermal breaker

and a line cord strain relief grommet are mounted on the flange of the bracket ma.king the line cord and breaker

reset button accessible on the rear of the computer.

A small printed circuit (PC) card is mounted directly to the breaker termimls, This card interconnects and
mounts the RFI dual-disc ceramic capacitor, the Mate-N-Lok output connector, and three fast-tabs for ac input
and ground connections. A dual fast-tab is connected directly to the bracket. The black and white line cord
wires are connected via fast-tab to the PC card; the green (ground) line cord wire is connected to the dual fasttab, which in turn is connected to the third fast-tab on the PC card.

2-1

The 115V and 230V models differ in only two respects: breaker current rating and (printed circuit) jumpers for.

parallel or series connection of the Power Supply transformer primaries.
. Power Control part numbers are: BCOSHXX for the 115V, 7A assembly; and BCO5JXX for the 230V, 4A assem-

bly. Line cord length is variable and is denoted by XX; e.g., BCOSHO6 has a 6-foot line cord.
2.2.1.2

Power Chassis Assembly — The 7008731 Power Chassis Assembly (Figure 2-1) consists of a long

inverted-U-shaped chassis, 7008726 power transformer, and a 5-inch fan. It is secured to the bottom of the

ME11-L by four 8-32 X 3/8 inch Phillips Pan Head bolts.

The chassis is mounted to the right (when viewed from the front) of the connector blocks and airflow is from
front to rear. The fanis held to one end of the chassis by two screws; the transformer may be remaved by loosening four nuts that are accessible through large holes on the bottom of the chassis.

The
DC Regulator Module is mounted to the chassis assembly by six screws and must be removed for cable ac-~ cess. The DC Cable enters a slot on the connector block side of the chassis; the AC Cable enters a slot on the

other side.
Connections to the fan are made by small fast-tabs. Connections to the transformer are made via Mate-—N~L0k
connectors:

2.2.1.3

6-pin for primary, 3-socket for secondary.

DC Regulator Module — The 5409728 DC Regulator Module (Figure 2-2) is a printed circuit assembly

that is mounted to the Power Chassis Assembly by four 6-32 X 9/16 inch and two 6-32 X 1/4 inch Phillips Pan
Head screws. It contains all the circuitry between the transformer secondary winding and the Power Supply
output cable.

ME11-Ls that were shipped during the first three or four months of production of the unit use a DC Regulator
Module designated 5409728-Y A-0; later shipments use a module designated 5409728-0-0, E revision. There
are differences in component values on the two modules. The discussion of the DC Regulator Module circuits
in this manual is directed to the later module, designated 5409728-0-0. Engineering drawings applicable to the

module used are shipped with each equipment. These drawings provide schematics and component values of

the DC Regulator Module used in a specific unit.
The transformer secondary 3-socket Mate-N-Lok connector is plugged into a mating connector which is soldered
directly to the printed circuit board and is accessible underneath it. The 9-pin Mate-N-Lok connector on the dc
output cable to the memory is similarly mated to a connector underneath the other end of the board.

The DC Regulator Module may be probed for troubleshooting purposes from the top; all points on the circuit

are accessible. It may also be removed from the top for cable access and for parts replacement by removing the
siXx mounting screws.

The printed circuit is approximately 5 X 10 inches, with about half of the top surface devoted to the heat sink.

The poWer transistors and power rectifiers are bolted to two shelves on the sides of the heat sink and make contact with the circuit board directly underneath via solder and screw connections. The heat sink is hard anodized

for electrical insulation.

The other half of the top surface is devoted to interconnecting and mounting the balance of the circuit. Three
small output voltage adjustment potentiometers are accessible on this top portion of the board.
Two small Pico fuses are mounted on the top of the PC board on the fan end. These fast-acting fuses will typically only blow when some component is defective or when the +5 or —15 voltage is set too high.

2-2

‘

POWER SUPPLY FAN
»

DC REGULATOR MODULE

———THERMOSTAT MATE -N-LOK CONNECTOR
W

TRANSFORMER

POWER CONTROL

S’MTE -N-LOK

MATE ~N-LOK
CONNECTOR

CONNECTORS

With DC Regulator Module

DC REGULATOR

MODULE

FAST TABS

With DC Regulator Module Removed

Figure 2-1

Power Chassis Assembly

2-3

, +5V

ADJUSTMENT POTENTIOMETER

-5V ADJUSTMENT

POTENTIOMETER

HEAT SINK

+15V ADJUSTMENT

POTENTIOMETER

{NOT USED IN ME1{{-L)

THERMOSTAT
MATE-N~LOK

‘

CONNECTOR

.
w0
D

‘

;

FUSES

Top View

FILTER CAPACITORS

DC OUTPUT

MATE ~N~- L OK

CONNECTOR

AC INPUT

MATE ~N-LOK

CONNECTOR

Bottom me
Figure 2-2

DC Regulator Module

2-4

The two input filter capacitors are held to the under side of the board by a bracket and are connected to the
~

circuit via jumper tabs on the fan end.

The +5V and -15V output filter capacitors and inductors are also mounted under the board, the former by
~
|
screws and the latter by nuts.
Care must be taken to ensure that all electrical and mechanical connections are made securely.
2.2.1.4

DC Cable — This is a simple cable connecting the backplane to the DC Regulator Module via a 9-pin

Mate-N-Lok connector. The latter is made accessible by loosening the six mounting screws and lifting out the
DC Regulator Module.

Cable access is through a slot on the module side of the power chassis.
AC Cable — This cable connects all ac portions of the ME1 1-L chassis, which are as follows:

-0

2.2.1.5

Power supply Fan — two fast-tabs

Power Supply Thermostat — one 2-pin Mate-N-Lok
Memory Section Fan — two fast-tabs

Transformer Primary — one 6-socket Mate-N-Lok
Power Control — one 6-pin Mate-N-Lok

?DPJ 1 System AC Power Control — two 3-pin Mate-N-Lok connectors on rear of mounting box
not used).

The ac cable is located on the right-hand side and rear of the ME11-L mounting box and is inherently shielded
by the Power Supply chassis, and the mounting box.
2.2.2

Specifications

Tables 2-1, 2-2, and 2-3 list all the Power Supply specifications according to input, output, and mechanical and
environmental specifications.
Table 2-1

Power Supply In‘put Specifications
Parameters

~ Specifications

*Input Voltage (1 phase, 2 wires and ground)

95—-135/190-270V

Input Frequency

47—-63 Hz

Input Current

;

5/2.5A RMS

Input Power

Inrush

325W at full load

80/40A peak, 1 cycle

Rise Time of Output Voltages

30 ms max. at full load, low line

Input Overvoltage Transient

180/360V, 1 sec
-360/720V, 1. ms

Storage After Line Failure
Input Breaker (part of BCOS Power Control)

25 ms min., starting at low line, full load
7A/4A single-pole, manually reset, thermal

*Input voltage selection, 115V or 230V, is made by specifying the appropriate AC Input

are with respect to the BCOS input,

Box, DEC Model BCOS (Paragraph 2.2.1.1). All specifications

(continued on next page)

Table 2-1 (Cont)

Power Supply Input Specifications
Parameter

Specification

Thermostat Mounted on Heat Sink (opens

277V 7.2A contacts

transformer and fan power)

Opens 98—105°C
Automatically resets 56—69°C

Line( cord on BCOS Power Control, length

Input Connections

and plug type specified with BC05

(Paragraph 2.2.1.1)

Turn-On/Turn-Off

Application or removal of power

Hipot (input to chassis and output)

2.1 kV/dc, 60 sec

Table 2-2

Power Supply Output Specifications

Parameter

Specification
+5V

Load Range

—

Static

0—-15A

Dynamic #1

+5A (within 0—17A load range)

Dynamic #2

No load — full load

Max. Bypass Capacitance in load for 30-ms

2000 uF

turn-on

Overvoltage Crowbar (blows fuse)

5.7—6.8V actuate (7V abs. max. output)

Current Limit at 25°C

24-29.4A (-0.1A/°C)

Backup Fuse (series with raw dc¢)

15A

Adjustment Range

+5% min.

Regulation
Line

+0.5%

Static Load

Dynamic Load #1

+2%

Dynamic Load #2

+10%

Ripple and Noise

4% peak-to-peak

1000 Hour Drift

+0.25%

Temperature (0—60°)

+1%
-15V

Load Range
Static

0-7A

Dynamic #1

Al = 5A (0.5A/us)

Dynamic #2

No load — full load (0.5A/us)
(continued on next page)

Table 2-2 (Cont)
Power Supply Output Specifications

Parameter

Specification

-15V(Cont)

Max. Bypass Capacitance in load for 30-ms

- 1000 uF

turn-on

Overvoltage Crowbar (blows fuse)

17.4—20.5V (22V abs. max. output)

Current Limit at 25°C

10—13.3A (-0.03 A/°O)

Backup Fuse (series with raw dc)

Adjustment Range

+5% min.

Regulation

Line and Static Load

+1%

Dynamic Load #1

+2.5%

Dynamic Load #2

+3%

“Ripple and Noise

3% peak-to-peak

1000 Hour Drift

+0.25%

Temperature (0—60°C)

+1%
BUSDCLOLand BUSACLOL
Static Performance at Full Load
(for 230V connection, double below voltages)

BUS DC LO L goes to high

74—80 Vac line voltage

BUS AC LO L goes to high

8—11V higher

BUS AC LO L drops to low

80—86 Vac line voltage

BUS DC LO L drops to low

7-10V lower

Hysteresis (contained in

3—4 Vac

above specifications)

Output voltages still good

70Vac’fin¢ ‘v‘”ca‘ltage‘
Dynamic Performance

Worst case on power-up is high

POWER ON

line, full load.

SLOWEST OUTPUT
COMES UP

{
A0ms

k= Max “’":

BUS DC LO L

|
omS

Mm"":

BUS AC LO L

Hma

NOMINAL

H-1094

(continued on next page)

Table 2-2 (Cont)

Power Supply Output Specifications

Parameter

Specification
BUS DC LO L and BUS AC LO L (Cont)

Worst case on power-down is low
]

line, full load,
|

POWER

DOWN

L_:

25ms

MIN

FASTEST OUTPUT

GOES

DOWN

|
I

< MIN

t
‘

;

{

BUS AC LO L

! Sms

:-«-Mm-ww ims

MIN —»

BUS DC LO L

‘

I-10949

Qutput Characteristics
Open Collector

50 mA sinking capability

+0.4V max. offset

Pull-Up Voltage on Unibus

5V nominal, 180§2 impedance

" Rise and Fall Times

1 us max.
Outputs shall remain in O state subsequent to power failure until power is re-

stored despite Unibus pulling voltages
remaining.

Table 2-3
Mechanical and Environmental Specifications

Parameter

Specification

Weight
DC Regulator

7 1b approx.

Power Chassis Assembly including AC

18 Ib approx.

Regula,mr Module
Dimensions

16.50 in. length

5.19 in. width
3.25 in. height

Cooling Means

Integral 5 in. fan

Minimum Cooling Requirements

375 CFM through heat sink

250 CFM over caps, chokes, and transformer
Rated Heat Sink Temperature

95°C max.

(continued on next page)

Table 2-3 (Cont)

Mechamcal and Environmental Spemfmtwm
m

Spemfimtmn

Parameter

Shock, Non-Operating

(duration 30 ms) 1/2 sine in each

of six orientations

1.89G RMS average, 8G peak; varying

Vibration, Non-Operating

from 10 to 50 Hz, 8 dB/octave roll-off
50—200 Hz; aach of six directions

0 to +60°C operating

Ambient Temperature

-40 to +71°C storage
Relative Humidity

95% max. (without condensation)

Altitude

10K ft

Output parameters are specified at the pins of the 9-pin Mate-N-Lok connector (Figure 2-3) which plugs into the
output connector on the 5409728 module. All output voltages are given with respect to the common ground

PIN 3

+5V OUTPUT

PIN 6

BUS
DC LO L

PIN 9

—15V QUTPUT

[® @ @

AC LO L

COMMON

BUS

l® ®

PIN 1
PIN 2

o @ o

Recommended distribution lossis 3 percent maximum.

l,_u
‘

pin on this connector. IR dropsin the distribution wiring are minimized to achieve gmd regulatmn at the load.

NOTE:
The circuit connected to pins 4, 5,7 aond 8 is not used in the ME11
1-1187

Figure 2-3 H740 Output Connector (5409728 Regulator Module)

2.3

DETAILED DESCRIPTION

The following paragraphs discuss the AC Input Circuit and the DC Regul"atm Module. A detailed circuit level

description is provided. The AC Input Circuit description discusses the Power Supply interconnections, Power
Control, tmmfmrmer Pc»wer Control circuit breaker and the Power Supply thermostat. The DC R&gulamr Module description discusses t} e generation at the circuit level of each of the three Power Supply outputs.

2.3.1

AC Input Circuit

A detailed ac interconnection diagram is shown in Figure 2-4. Figures 2-5 and 2-6 illustrate the connections in
schematic form.
The line cord, single-pole breaker, RFI capacitors, and connections for transformer 115V or 230V wiring are

contained in the Power Control Unit. To select 115V input or 230V input, use the BCO5SH or BC05J Power
Control, respectively.

The transformer is rated for 47 to 63 Hz and is equipped with two windings that are connected by the Power
Control in parallel for 115V operation, and in series for 230V. The fans are connected across half of the primary
so that they are always provided with 115V nominal. There is an electrostatic shield between primary and

secondary of the transformers.

The Power Control Unit contains a single-pole thermal circuit breaker which protects against input overload and
is reset by pressing a button on the rearof the computer.

The thermostat is mounted on the Power Supply heat sink. It will open one side of the primary circuit and deenergize the Power Supply if the heat sink temperature rises to about 100°C. It will automatically reset at about

63°C.
2.3.2

|
DC Regulator Module Operation

The discussion of the DC Regulator Module circuits in this manual is directed to the module designated
5409728-0-0, rather than the earlier module designated 5409728-YA-0. A block diagram of this module is
shown in Figure 2-7. The center tapped output of the power transformer is applied to positive and negative
rectifier and filter circuits. The rectifier circuits produce +28V and -28V nominal raw dc voltages which are
unregulated but well filtered by the input storage capacitors.

The +28 Vdc is used by an efficient switching regulator circuit to produce the +5 Vdc output. Provisions for
overcurrent detection are incorporated in the regulator circuit so that excess current is limited when there is a

malfunction in the load. The +5V output is also protected against overvoltage by a crowbar circuit which limits
the output to under 7V; before the output gets to this value, the crowbar circuit blows the fuse in the output

- circuit of the rectifier.
The =28 Vdc is used by the —15V circuit which is similar in operation to the +5V regulator circuit. The =15V
crowbar circuit limits the output to 22V.
The BUS AC LO L and BUS DC LO L signals are used to warn the Unibus of imminent power failure. Circuits

on the regulator module detect the transformer secondéry voltage and generate two timed TTL-compatible
open-collector signals that are used for power fail functions nby devices on the Unibus. Note that this circuit does
not detect the regulated dc output voltages as in some other PDP-11 processors and peripherals.
2.3.2.1

Generation of + Raw DC — As stated in the previous paragraph the center-tapped transformer secondary

voltage is rectified and filtered prior to being fed to the two DC Regulator Module circuits.

The circuitry involved is shown in 'Figure 2-8. The bridge rectifier D14 is mounted on the heat sink and the input

capacitors C1 and C2 are mountedan the bottom of the regulator module. Thflse capacitors filter the dc input
and are large enough to provide at least 25-ms storage when the input power is short circuited or fails.

A fuse is used on each output to protect the regulator and load during faults. The fuses will not normally blow

when a regulator output is shorted since the three outputs are electronically overcurrent protected. However the
appropriate fuse will blow in the case of a +5V or —15V overvoltage crowbar or
a failure in one of the over-current
circuits.

2-10

_| 82.60vS9 70794

2Indig-7DVUOIUODIdIU]wrelgey(J

w “L¥O1LnYoILNnOd3Nv2-aNnowo
OIYWN3HL b 2V101
2 i

L=2o|Y~mbn\*j~Mo“hnIH.4_mH.”u,.er

2-11

Agot+lS| 3¢|2MoAt+O—Wo MAweS-mlh

$9n14d

TA
8F%E".AKE:R

——

Fl"JNE

—

THERMOSTAT

RFI

11sv

SUpPLY

MOUNTED ON

LUG

S—

{

COMPUTER

FAN

|
‘

v DIUD S—

5409728

DC REGULATOR

MODULE

——
ot

—t—

11179

Figure 2-5

4
BREAKER
P

RFI
CAPR

230V
LINE

'
3

PLUG

115V Connections, Simplified Schematic Diagram

;[-

THERMOSTAT

| FAN(iE)

]!il
il

*—=

i
:lfi

o REGULATOR
MODULE

11-1180

Figure 2-6

230V Connection, Simplified Schematic Diagram

The resistor across each fuse provides a slow (100—150 sec) discharge of C1 or C2 after the power is turned off,
should a fuse blow. The capacitors are placed ahead of the fuse to limit the energy in any fault and thus better
protect the outputs.

2.3.2.2

BUS AC LO L and BUS DC LO L Circuits — The circuitry shown in Figure 2-9 generates the timed Uni-

bus power status signals described in Table 2-2.

These are used for power fail functions. The transformer

secondary voltage is rectified by D1 and D2 and filtered by C9 and R1, R14.

Circuit parameters are chosen so that the voltage across C9 will rise slawé:r than the two regulated output voltages on power-up, and will decay faster than the two regulated output voltages on power-down.

Two differential amplifier circuits are used to detect power status: Q17, Q18 is used to "gemmte BUSDCLOL;
and Q15, Q16

is used to generate BUS AC LO L. The differential amplifiers share common mference Zener

diode D3 whichis fed approximately 1 mA by R3.

L ONY3sN4-w3141038| ,IoONINITY e0120|N3dO[*40-1537100Ve—01T
TM 1IN3uHND ¥3A0

umSLygL-TOJ0jemIay‘9MPOWYo[gweselq

A , ‘, p— | i ¥OLIOVdVD||o70a/0v|,|sworsisaw|L SERSROARS,

NOI193130

uNOI10313‘0 TL¥N3IMHAN|0D

"i3AI)Lk|YO3,N

2-13
5

fiwwmmm%&

)

72awsc

47-63Hz2

’
NSS-351

JI-3
/‘"

o
-

FROM{
>—
TRAN&F‘ORMEIR‘
SECONDARY

R45
4.7K
1/2W
ANV

F1,15A

D14

REGULATOR CIRCUIT

N\ p——t—gn TO+5V

\J1-2

c2
24KyF
50V

2aKyF_l1

50VAT~

AY|

Jl+
Y

TO AC LO

ARESiTs®

R4 4.7K

F2,10A
’

TO-15V REGULATOR

® CIRCUIT

-7

Figure 2-8

INGOO4

28VAC, 47-63Hz FROM
v
TRANSFORMER SECON DARY

D2
ND2os

Rectifier Circuit

"*"’

Ri4
1K
1K

20uF

|
»

sR2

sR3

210K 1%

SRS
> 10K 1%
)

10K 1%

)
Qi8

XAS55

AC LO L W21
OUTPUT 7/

$10K 1%

,
Qi7

"y,

\ outpPuT

S Ri

SR10

Liw

Li%

$ 10K

——

Q19

$ 75K

2N1309

—

Ri2
10K
1%

Q1
2N1308

xass ¢ 1K1%

Xsiv

J—
J2-6 pcoL

ae | o

xAfi

‘ :<

SR6

Q20
2N1308

SR7

S1K 1%
H-1176

Figure 2-9 BUS AC LO and BUS DC LO Circuits

As C9 charges subsequent to power-up, first Q17, Q18 and then Q15, Q16 change states; the reverse is true dur-

ing power-down. When C9 starts to charge, Q17 and Q16 are on and Q15 and Q18 are not conducting. As C9
charges further, Q18 starts to conduct into R7 and raises the voltage on the D3 cathode. This acts as a positive

feedback and snaps Q17 off and Q18 on more solidly. A few milliseconds later, the voltage across C9 has risen
sufficiently for the same process to take place in differential amplifier Q15, Q16. The status of each differential
amplifier is followed by the germanium transistor open-collector output stages Q19, Q20 for DC LO L, and Q13,

Q14 for AC LO L. These stages clamp the Unibus at about +0.4V until the differential amplifier circuits

2-14

sequentially signal them across R11 and R12 that power is up. The outputs then rise sequentialltoy about +5V
as dictated by the Unibus loading and pull-up termination resistors. The sequence is as follows:

power-up - then BUS DC LO L= 0~ then ACLOL=0 0= High (+5V)

1=Low(+0.4V)

power-down= then BUS ACLO L = 1 = then DC LO L =1

Thereis sufficient storage in the regulator output capamtors Cl and C2so that when BUS DC LO L and BUS

ACLOL=0, the output mltageis maintained long enough to permit powet fafl mmmts to operate. Note that

the open collector stages are designed to clamp the Unibus to 0.4V maximum, even when thereis no ac input to
the regulator. They are inherently biased by R11 and R12 until the differential amplifiers signal that power is okay.

2.3.2.3 +5V Regulator Circuit — The +5V regulator samples the output voltage and compares it to the voltage
across a reference Zener with a voltage detector transxsmr, whichin turn mmmla the drivers for the main pass
transistor. The +5V mgulamr circuit is shcvwnin Flgum 2-10. An Wfirmrmm mmmt is ampluyed

J2-3 45v,15A

*
'

OuTPUT

_ 6000

IMF,I‘G\I

im@

IN5624
&

D12
INT52A,
5.6V

$R54

+39V FROM

RECTIFIER

__4

l
3

0.0334F

;
;

.T.hul-‘f

XAS5__Q9

SRR

SR47
R46 168K
6 a :»%2‘;@'

s
T1%

Ra3
cs

6.8uF

35V

Qit

= RS3g*"“]_Lcs

R49

& A

C32AX135%

‘

1003

HDK

10V,10%

0.22uF

50V

CWt 2R50

330

‘

c17

e;wm $

6.8
uF I
BuF

3%‘ P.T.C

’“%fir

- 11rs

Figure 2-10 +5V Regulator Circuit

The viewing chain consists of R49, 50, 51; the reference Zeneris D9 whichis fed by R44. QIOis the detector

amplifier. The pass tmnsmtar Q6is turned on by R46. The current is diverted from the base of Q8 by off-driver
Q9 whichis controlled by Q10. The tendency for the output voltage to rise resultsin more conduction through
Q10 and resultant limiting of conduction through Q6.

The +5V circuit is a regulator that operates in the switching mode for increased efficiency. To switch the regulator, positive feedback is applied to the voltage detector input via R47.

2-15

Thus, the whole regulator acts as a Schmitt trigger andis turned either completely on or off, depandmg on
whether the output voltageis too high or too low.
When Q6is on, it supplies current through filter choke L1 to the output

smoothing capacitor C7 and the load.

When Q6 is off, the L1 current decays through commutating diode D10 which becomes forward biased
back emf of L1. The waveform across D10

by the

is a 30V nominal rectangle pulse train. The filtered output across C7

is thus +5V with about a 200 mV peak-to-peak, 10 kHz nominal sawtooth of

of the ripple, Q6 turns off, and at the valley, Q6 turns on.

superimposed ripple. At the crest

This switching mode of operation limits the dissipation in the circuit to the saturated forward

losses of Q6 and

D10 and the switching losses of Q6. The resultant high efficlency allows the
use of a small heat sink and few

semiconductors.

R50is the voltage adjustment potentiometer. R51 is a positive temperature coefficient
wirewound resistor,

which compensates for the negative voltage temperature coefficients

reference dwde D9.

of the Q10 base-emitter junction and the

The overcurrent signalis generated across resistor R41, which is in series

by QS, current limited by R39, 40.

with the Q6 collector, andis detected

Output fault current is limited to a safe value since conduction of Q5 decreases

the reference voltage across D9

to zero. This causes Q10 to conduct and shuts down the regulator.
C5is an averaging ca.pamtor thatis necessary

in the circuit because the current through R41 is pulsating.

High-frequency bypass capacitors are used on input and output of the
regulator, C3 and C6, respectively. C4 is
used to slow down the turn-on of Q6 to allow D10 to recover from the on state without
a large reverse current
spike.

Should a malfunction cause the output voltage to increase beyond about
6.8V nominal, Zener diode D2 will
conduct and fire silicon-controlled rectifier Q11. This will crowbar
the output voltaga to a low value through

D11 and will blow fuse F1 in the rectifier circuit through R52.

2.3.2.4 -15V Regulator Circuit — The- 15V regulator circuit is shown
in Figure 2-11. The -15V output voltage
is adjusted by potentiometer R26. Itis essentially the compleme
nt of the +5V regulator circuit and differs only
in the following minor details:
a.
b.
c.

2.4

The crowbar device is a Triac Q27 instead of an SCR
No temperature compensating resistor is required since Q26 and

The detailed interconnection of the drivers and the circuit values

D4 track each other
are different

MAINTENANCE

This paragraph discusses the adjustments, circuit waveforms, troublesho

oting, and parts identification necessary

to maintain the Power Supply. The adjustments section discusses
the two output potentiometers.

waveforms section provides a guide to proper operation at various

The circuit

placesin the circuit. The troubleshooting sec-

tion provides rules, hints, and a troubleshooting chart as a maintena
nce aidin isolating Power Supply malfunc-

tions. Fmally, the parts identification section provides a directive
to obtmnmg

parts information for the entire

Power Supply unit thmugh a parts location directory to the mechanical engineering drawmgs
in the ME[1-L

Engineering Drawing Manual.

2-16

—28y

€10

WwF

RECWF:%WMHH.-L
FROM

-o—o

]

cio

‘V

‘

T22uf |

R28

B£
*

%/QW

—9

J42-2, GROUND

# 1“1,“

~OUTPUT

Uamiflfr

Q26

35V

CW
| ros
i:*bfigg

R58

v $as2w

$R24

ooy

INT53A

ToK

168K

10K

a2s

;‘:C?E

qos

1HF

$383

T1%

“

FW%&%O}.&F

25V

g
D5, 20A

Feast

RECOVERY

Q27

MACH1-3°T

<40

c12
2 2uF
35V

& 52488

Qe2
2N5302

mma
N

15V, 7A
OUTPUT
11-0970

Figure 2-11

2.4.1

-15V Regulator Circuit

Adjustments

There are only two adjustments to the Power Supply for the +5V and —15V dc output voltages. (A small screw-

driveris all thatis required for adjustment.) Clockwise adjustment of anyof the potentiometers increases voltage. The
p otentiometers are located onthe: top side of the DC Ragulamr deum and are dmgnawd as R50 for
+5V and R26 for —=15V. A +15V admmmmt potentiometer and mmmtry are also Emate:d on the DC Regulator

Module, but this supply voltageis not usedin the ME11-L and it is not necessary to ad_mst the +15V potentiometer.
CAUTION

Do not adjust voltages beyond their 105percent rating.
slowlyin order to avoid overvoltage crowbar blowil;:gdc matput

fuses. Do use a calibrated voltmeter; preferablya digital volt-

meter. Voltages should be adjusted to their center mlm
+5.0, and
- 15.0; all under load at the m: Cahlw terr
tl:w sys;wm umt
2.4.2

m@mm
|

Circuit Waveforms

The two basic regulator circuits used on the DC Regulator Module generate +5V and - 15V. Figure 2-12 shows
six waveforms of the +5V regulator circuit taken at two points (A and B) in the circuit (Figure 2-10). Waveforms

a, b, and c are taken at point A, which is the +5V circuit, Q6 transistor output. Waveforms d, e, and f are taken

at point B, which is the +5V Power Supply output (J2-3). Figure 2-12 also indicates the load conditions and time

2-17

a) Point A, No load,

d) Point B, No load,

2 ms/div, and

10V/div.

50 mV/div.

b) Point A, No load,

e) Point B, No load,

20 us/div, and

20 ps/div, and

10V/div.

50 mV/div.

¢) Point A, 20A load.

f) Point B, 20A load,

20 us/div, and

10V/div.

50 mV/div.

Figure 2-12

+5V Regulator Circuit Waveforms

2-18

scalw for each waveform. Fxguw 2-13 shows six waveforms of the-ISV mgulatm circuit taken at two points

(C and D)in tlw circuit (F’'f‘~§'~‘~ifi‘re 2-1 1). Waveforms a, b, and c are tak,en at mmt C, whichis the- 15V mrcmt Q22
transistor output. Wammms d, e, and f are taken at point D, whichis the- 15V Power Supply mmput (J2-9).
The load conditions and time scales of the mspectwe waveforms are also indicated in Figure 2-13. ‘These waveforms were taken on a Tektronix Model 453 oscilloscope.

243 meblefihwmmg

Tmubleshmtmg mfmmafim for themeer Supply consists of mm,hmts anda tmubleshmtmg chart Thwinformation pmvzdes a maintenance aid for isolating Power Supplymalfumtwm

2.4.3.1

Troubleshooting Rules — Troubleshooting rules for the Power Supply are as follows:

‘a.

Be sure that power is turned off and unplugged before servicing the Power Supply.

Be sure that input capacitors C1 and C?2 are discharged before servicing the Power Supply. A 10 to
10052, IOW resistor can be used to speed up discharge of the capammm (Be sure pmwer is off.)

c. ~ The DC Ragulatur Moduleis not mtemally grounded to th@ chmm Shmts m gmund can be lmcated
; aft@r dzscomammg thez dc c}utput cable from the system umt

d. | The dc output fusm F1 and F2 can be replaced without mmmmg m@ DC Regu}amr Mmm Befam
unsoldering the fuses, obsewe the cautions describedin a andb above.

e Fm proper opemtmn all hardware: must be secured txghflywzth abmut 12meh*pwunds mmufi: (1

capaczmm, chokes, semmunducmrs) All hardware shoulf‘*‘f be mpmmfiwith memwal hardware mplaac«
ment pa:rts

TheDC R@gulamr Modulemay be removed from the top of the: me&r Chasm Asmmbiy wmmthe: latter is still boltedto the ME11-L chassis.

When replacing power semiconductor components that are secured to the heat sink, apply a thin coat

of Wakefield #128 compound or Dow Silicone Grease to heat sink contact side (bottom) of the semiconductor.

2.4.3.2

Troubleshooting Hints
CAUTION

Unplug ME11-L before servicing.

The most likely source of Power Supply malfumtmnis the DC Regulamr Mmdulfiz A quwk mmedy for a malfunction may be to replace the entire module. The problem, how&wr,muld bfi: a shmtin the system unit,a
defective mmpment or a problemin the ac mput circuit.

The +5V and- 15V regulatnm contain mvewmltage detection czrcmtry If RSO or Rzé are adguflmdtoo fm’ clmk~
wise, the corresponding cmwbar circuit trips and blows a fuse. To correct thm condition, adwm the p@tmtmm-»

eter fully emumemmckm% replace thfsa blown fuse, and re-adjust accm'dmg, w Pamgmph 2.4.1.
Make a wsual examination of the c:zrcmtry. Check for burned remsmm, CMCkfid transistors, burned printed circuit

board etch, oil leaking from capacitors, and loose connections. If a malfunction is caused by something of this
nature, a visual check can quickly locate it.

2-19

a) Point C, No load,

d) Point D, No load,

5 ms/div, and

10V/div.

50 mV/div.

‘

b) Point C, No load,

e} Point D, No load,

50 us/div, and

10V/div.

50 mV/div.

c) Point C, bA load,

f) Point D, BA load,

50 us/div, and
10V /div.

50 us/div, and
fi

50 mV/div.

Figure 2-13

- 15V Regulator Circuit Waveforms

2-20

2.4.3.,3 Troubleshooting Chart — In checking the various areas of the Power Supply, the rules listed in Paragraph

2.4.3.1 should be followed. The wamfams referenced in Paragraph 2.4.2 provide a comparison for the troubleshooting readings. Table 2-4 provides a chart of problems and causes for troubleshooting the Power Supply.
Table 2-4

Power Supply Troubleshooting Chart

Cause

Problem

F1 opened

No +5V Output

D14 or transformer opened
+5V adjusted too high*

Q5,D9,Q10,Q9,Q11,D2, or D10 shorted

+5V Output Too Low

C5 or C7 shorted

R49, R50, R51, R46, or R44 opened

Q6,Q7, Q8, or D11 shorted

Q9, Q10, or D9 opened
F2 opened

No =15V Output

D14 or transformer opened

~15V adjusted too high*

Q25, D4, Q26,Q21,Q27, D7, or DS shorted

~15V Output Too Low

C14 or C12 shorted
R22, R26, R25, R27, or R29 opened

Q22, Q23, Q24, or D6 shorted
Q25, Q26, or D4 opened

Q13,Q14, or Q15 shorted
Q16 or D3 opened
R7, R3, R6, or R8 opened

BUS AC LO L Will Not Go High

C9 shorted

BUS AC LO L Will Not Go Low and/or Acts
Erratically on Power-On/Power-Off

Q13,Q14, or Q16 opened
Q15 or D3 shorted
R12, R13, R7, or R10 opened

BUS DC LO L Will Not Go High

Q19, Q20, or Q18 shorted
Q17 or D3 opened
R7, R3, or R6 opened
C9 shorted

Q19, Q20, or Q17 opened

BUS DC LO L Will Not Go Low and/or Acts

Q18 or D3 shorted
R9, R10, R11, or R8 opened

Erratically on Power-On/Power-Off

* These causes make the crowbar fire, which in turn blows the appropriate fuse.

2-21

' 2.4.4 Parts Identification
Parts identification for the Power Supply is provided in the ME11-L Eflgmearmg Drawing Manual. The assembly
drawings and associated parts lists provide the respective unit parts, their part des:&gnatmns and DEC part
bers. These drawings and their numbers are as follows:

Module Utilization

D-MU-ME11-L-01

15-Bit 18-Mil Memory

B-DD-MM11-L

Regulator Board

E-1A-5409728-0-0

Circuit Schematic

D-CS-5409728-0-1

Circuit Schematic

‘,

C-CS-5409959-0-1

Line Set BCOSH

B-DD-BCO5H-0

AC Input Harness .

E-IA-7008889-0-0

DC Harness Assembly

D-IA-7008857-0-0

Unit Assembly ME11-L

D-UA-ME11-L-0

Power Supply H740

D-AD-7008731-0-0

Power Supply Assembly (Parts List)

A-PL-7008731-0-0

Software List

A-SL-ME11-L-4

Accessory List

A-AL-ME11-L-3

2-22

num-

CHAPTER 3

3.1 Imrnovumom

This chapter provides the user with the theory of aparatian and logic diagmmé ‘nmes&ary to understand and maintain the MM1 1-L Read/Write Core Memories. Thela%l of discussion a&sumes that the maderis familiar with
basic digital computer thmry Both general and de:tmled dfiscmptmm of the core memories are included.
Although memory control signals and data pass through the Umbusfi it m beyond the scope of this manual to describe the operation of the Unibus itself. A detailed d%cnpucm 0f the.r Umbusis pmsmtedin the PDP-11
Peripherals and Interfacing Handbamk

A complete set of engineering logic drawings is shipped with each core memory. These drawings are bound in a
separate volume entitled MM 11-L Core Memories, Engineering Drawings. The drawings reflect the latest print revisions and correspond to the specific memory shipped to the user.

This chapter of the manual is divided into three sections: General Description, Detailed Description, and Maintenance.

3.2

GENERAL DESCRIPTION

This paragraph provides a physical description and specifications for the memory. The major functional units of
each memory are briefly described and the basic memory operations are discussed.
3.2.1

Physical Description

The MM11-L provides 8192 (8K) 16-bit words. This requires three standard 8-1/2 inch wide modules: two are
hex-height and one is quad-height. The quad-height module contains the memory stack: module H214 for 8K.

One hex-height module (G110) contains the control logic, inhibit drivers, sense amplifiers, and 16-bit data register; the other hex-height module (G231) contains the address selection logic, current generator, and switches and
drivers. Pin-to-pin compatibility exists between the C, D, E, and F connectors on both these modules and the

stack module connectors. The pins on the A and B connectors of both these modules are also compatible with
the standard Unibus pin assignments.

The modules are installed in the ME11-L mounting box. It is recommended that the Driver Module (G231) be installed between the Control Module (G110) and the Stack Module (H214). Photographs of the component side
of the modules are shown in Figures 3-1, 3-2, and 3-3.

3.2.2

Specifications

The general memory specifications are listed in Table 3-1.

HANDLE (2

STROBE ADJUSTMENT

RI20

i
o

dl
i

o
o

(',

oy
Do
.

Figure 3-1

3.2.3

Component Side of Control Module G110

Functional Description

3.2.3.1

Introduction — The memory is a read/write, random access coincident current, magnetic core type with

a cycle time of 900 ns and an access time of 400 ns. It is organized in a 3D, 3-wire planar configuration. Word
length is 16 bits: MM11-L contains 8192 (8K) words.

The major functional units of the memory (Figure 3-4) are briefly described in the following paragraphs.

3.2.3.2

Control Module (G110) — The Control Module (G110) contains the memory control circuits, inhibit

drivers, sense amplifiers, data register, threshold circuit, - 5V supply, and device selector.

Memory Control Circuits — Control circuits are provided to acknowledge the request of the master device; determine which of the four basic operations (DATI, DATIP, DATO or DATOB) is to be per-

formed; and set up the appropriate timing and control logic to perform the desired read or write operation.

If a byte operation has been selected, address line AOO L determines the byte to be selected.

The actual read or write operation is selected by control lines (CO0 and C01). The memory control

logic also transfers data to and from the Unibus.
b.

Inhib.: Drivers — Each bit mat contains a single inhibit/sense line that passes through all cores on the
mat. To write a 0 into a selected bit, an inhibit current is passed through the inhibit/sense line that
cancels the write current in the Y line. The core does not switch so it remains in the 0 state. With no

inhibit current, the currents in the X and Y lines switch the core to the 1 state.

3-2

Sense Amplifiers — During a read operation, the sense amplifier picks up a voltage induced in the sense
inhibit winding when a core is switched from a 1 to a 0. This signal is detected and amplified by the
sense amplifier whose output sets a data register flip-flop to store a 1. In effect, a 1 is read but the
core is switched to the 0 state. Cores which were previously set to 0 are not affected.

Data Register — The data register is a 16-bit flip-flop register used to store the contents of a word after
it is destructively read out of the memory; the same word can then be written back into memory (restored) when in the DATI mode. The register is also used to accept data from the Unibus lines to accommodate the loading of incoming data into the core memory during the DATO or DATOB cycles.
"

Device Selector — The device address (bus lines A 14 through A17) is decoded in the device selector
to determine if the memory bank has been addressed.

Threshold Circuit and -5V Supply — The threshold circuit provides a reference threshold voltage to
the sense amplifiers. During a read operation, if the threshold voltage (£20 mV) is exceeded, the sense
amplifier produces an output. The -5V supply provides a negative voltage for the sense amplifiers.

HANDLE(2)

Component Side of Driver Module G

Figure 3-2

HANDLE (4)

Figure 3-3

Component Side of 8K Stack Module H214

Table 3-1
MM11-L Memory Specifications
Type:

Magnetic core, read/write, coincident current, random access
Organization:

Planar, 3D, 3-wire
Capacity:

8192 (8K) words for MM11-L
Access Time and Cycle Time:

‘
Bus Mode

Cycle Time
Non-Interleaved

.
Access Time

DATI

900 ns

400 ns

DATIP

450 ns

400 ns

DATO-DATOB
(PAUSE L)

900 ns

200 ns

DATO-DATOB
(PAUSE H)

450 ns

200 ns

(continued on next page)

Table 3-1 (Cont)

MM11-L Memory Specifications
X-Y Current Margins:

+6% @ 0°C, +7% @ 25°C, +6% @ 50°C
Strobe Pulse Margins:

+30 ns @ 0°C, +40 ns @ 25°C, +30 ns @ 50°C
Voltage Requirements:

+5V +£5% with less than 0.05V ripple

-15V 5% with less than 0.05V ripple
Average Current Requirements:

Stand by
+5V:

1.7A

-15V: 0.5A
Memory Active

+5V: 3.4A
-15V: 6.0A

Power Dissipation (worst case):

Control Module (G110): = 60W
Drive Module (G231): =40W

Stack Module (H214): = 20W
Total at maximum repetition rate: 120W
Environment:

Ambient temperature: 0°C to 50°C (32°F to 122°F)
Relative Humidity: 0-90% (non-condensing)

3.2.3.3 Driver Module ((}231) — The Driver Module (G231) contains the address selection logic, switches and

drivers, current generator, stack discharge circuit, gmd DC LO protection circuit.
a.\

Address Selection Logic — The core memory receives an 18-bit address from the master device. The

address is latched and decoded to determine if the memory is the selected device and to determine the
core location specifically addressed. If the operation is a byte operation, bus line AOQO L indicates the

byte to be used. The X and Y portion of the address is decoded through selection switches and a diode
matrix to enable passage of read/write current through the selected X and Y drive lines of the memory.
The coincidence of these currents selects the specific 16-bit core memory location desired.

Switches and Drivers — The switches and drivers direct the flow of current through the magnetic cores
to ensure the proper polarity for the desired function. This action is necessary because a single read/
write line is used, and the current for a write operation is opposite in polarity to the current required
for a read operation. There are separate switches and drivers for the read and write circuits in the selection matrix.

Current Generators — X and Y current generators provide the current necessary to change the state of
the magnetic cores. The linear rise time and amplitude of the output-current waveform have been selected to provide optimum switching of the core states and maximum signal-to-noise ratio for a wide
range of temperatures.

(continued on page 3-7)

LI—m.m-w1.NSVm—Hw.YIwH4.mLmw.1—3..mAlw3:.—.m7..3.:0.l—A.L¥.91.aW°3.l.00bA..f[(4..eTeH3—..“4oe..VL.r=¢I:..NmII.JS.lI¥.aHL.ImlN4D.In.-_.a0HlQ—.I.¥olAid.I.AH.M.Ai_|¥OA-0O;gWEM,NMObP96N0eYXAS,-—tIH¢3ON0DNA141M0I47LSNNLI3¥S0vI1W¥H1fiIVHIdLW3d18
1i¥.OSSLnl33gxi¥I!ASA|lHIQ.3SlVAe“13_>SA35.Ia3G03Hnm5H3yIzOoN-48i=L[J=1v.oaYye34nIvTL—1Di9a18H.y880vMqifv[—*a~|S|mL9'Y3oG8>6i'awbrm8qygYvmQm|&¥S|df,mAXisliaL4iv-7m.0o0L|¥axL-0 v e7XTM>LBYG7LT\M7Nx1\S7\LI7sN:7L7ImT7[77
IND LNIN¥YNDoTlOHLNOD8 B3 bodtOLSIS3Y
—oNOT+SW1IR9L31TG3AORi8Hv0SLH4ODNe1OISTMMDSH0VTAYHNINI1VL8vivfIoa—._S9diT0viTvIa3TSNTdA0ROW7eo !I%$I1E2°€I}22H6I4A8MO4tySWI3NW"ODMIiMOOVdL4SivM8tYOt£M8iX9i11"8ii

sng SINSYE veiVLT TT
TI

. 1 7777

TM /7 / /

j0a¥odt

4§

[+Ss3u‘av

eo—

3-6

+€29 H3AIHA 3TINAOW

MOVLS

9} SLINDYID

SS €

2SS

sng 0704 7 — —

cizi'ti'or'se's

sn80 712°71 3AVITHILNIT0HLINOD |
sng ‘2'9'G'p'e'2y i , o
_JHNLIVYIdWILNOO.IM.LYNSNXIdWLO-D0 iy T LTLLL
InSiyg- TNT-1AIOWoWyoigWeIsel(

Ssng.N80vIN7ssn\g visnSvnaNQggng(N0SL7A1I1-SN00I) 7777

> HEBHE

N7SANTS8W

0S§S

geli-il

|
7

Stack Discharge Circuit — The stack discharge circuit maintains the proper stack charge voltage during

DC LO Protection Circuit — If the ac input voltage is out of tolerance, DC LO L is asserted on the Unibus. Itis sensed by the DC LO protection circuit which inhibits the memory operation by opening the

operation: approximately OV during a read operation and approximately - 14V during a write operation.

~15V line to the current source. This prevents spurious memory operation.

3.2.3.4 Stack Module (H214) — The Stack Module contains the ferrite core array and the X-Y diode matrices.
16 core mats, each wired in a 128 X 64 matrix are used for the 8K memory (H214). The stack also contains the

resistor-thermistor combination to control the G231 X-Y current generator temperature compensation.
Basic Memory Operations

3.2.4

The core memory has four basic modes of operation. The main function of the memory is simply to read and
write data. Additional modes are provided, however, to allow for byte operation and to eliminate the restore
cycle when it is not needed, thereby increasing overall system efficiency. The four basic memory operations are:
a.

Read/restore (DATI)

Read pause (DATIP)

Write (DATO)

Write byte (DATOB)

These four modes are discussed briefly in the following paragraphs.
NOTE

In the following discussions, all operations refer to the master
(controlling) device. For example, the term “data outTM indicates data flowing out of the master and into the memory.

3.2.4.1 Data In (DATI) Cycle — The DATI cycle is a read/restore memory cycle. During this operation, the
memory reads the information from the selected core location, transfers it to the Unibus, and then writes the information back into the memory location. This last step is necessary because the core memory is a destructive
readout device. During the first part of the cycle, the memory loads the data into a register; at the same time,
the memory applies the data to the Unibus. Then, during the second part of the cycle, the memory takes the
data from the register and writes it back into the memory location.

3.2.4.2 Data In, Pause (DATIP) Cycle — Normally in reading memory, the information is destroyed in the particular location accessed, and the data must be restored. However, sometimes it is not actually necessary to restore the information after reading because the location is to have new data written into it. In this instance,

eliminating the restore crpemtion decreases the memory cycle time by approximately 50 percent. The DATIP

operation is used for this purpose. The data is read from memory and the restore cycle is inhibited. Because no

restore cycle is used, a DATIP must always be followed by a write cycle (either DATO or DATOB) on the same

address or data in both addresses will be destroyed, the memory controller will be unable to control the bus, and

other devices will be unable to access the bus (this is known as hanging the bus).

3.2.4.3 Data Out (DATO) Cycle — The DATO cycle is a write memory cycle used by the master device to transfer data into core memory. To ensure that proper data is stored, the memory unit must first be cleared by reading the cores (thereby setting them all to 0) before writing in the new data. During a normal DATO, the memory
first performs the read operation to clear the cores and then performs a write cycle to transfer data from the bus
into the selected core location. If a DATO follows a DATIP (rather than a DATI), the sequence is not the same.
The DATIP clears core and generates a pause flag; the DATO skips the read cycle and immediately begins the
write cycle. This process reduces DATO cycle time by approximately 50 percent.

3-7

3.2.4.4

Data Out, Byte (DATOB) Cycle — The DATOB cycle is similar in function to the DATO cycle except

that during DATOB, data is transferred into the core memory from the bus in byte form rather than as a full
word. During the read cycle, the non-selected byte is saved by reading it into the data register while the selected

byte is transferred into the register from the bus. During the write cycle, only the selected byte portion of the

word is loaded into the memory location from the bus. At the same time, the non-selected byte is restored from
the data register into the memory location. In effect, the memory is first cleared and then simultaneously per-

forms a restore cycle for the non-selected byte and a write cycle for the selected byte. This mode can follow a
DATIP as described above.

3.3

DETAILED DESCRIPTION

This paragraph provides a detailed description of the MM1 1-L memories. The detailed description covers the
core array, device and word selection, switches and drivers, current generation, stack discharge circuit, DC LO

circuit, sense/inhibit circuitry, control and timing logic, and memory operating cycles.

3.3.1

Core Array

The ferrite-core array for the 8K memory consists of 16 mats arranged in a planar configuration. Each mat contains 8192 ferrite cores arranged in a 128-by-64 array. Each mat represents a single bit position of a word. This
planar configuration provides a total of 8192 16-bit word locations. Each ferrite core can assume a stable magnetic state corresponding to either a binary 1 or a binary 0. Even if power is removed from the core, the core re-

tains its state until changed by appropriate control signals. The outside diameter of each core is 18 mil; the inside diameter is approximately 11 mil. Each core is 4.5 mil thick.

Selection and switching of the cores is provided by three wires traversing each core in a special selection tech-

nique. An X-axis read/write winding passes through all cores in each horizontal row for all 16 mats. A Y-axis

read/write winding passes through all cores in each vertical row for all 16 mats. Through the use of selection circuits which control the current applied to specific X-Y windings, any one of the 8192 word locations can be
addressed for writing data into memory or reading data out of memory. A third line passes through each core on

a mat to provide the sense/inhibit functions. There is one sense/inhibit line per mat. This single sense/inhibit
line, as well as the selection circuits, are discussed in subsequent paragraphs.

3.3.2

Memory Operation

Figure 3-5 illustrates a typical portion of the core memory. An X and Y winding pass through each core in the
mat. The current passing through any one winding is such that no single winding produces a magnetic field

strong enough to cause a core to change its magnetic state. Only the reinforcing magnetic field caused by the
coincident current of both an X and a Y winding can cause the core located at the point of intersection to change
states. It is this principle that allows the relatively simple winding arrangement to select one and only one mem-

ory core out of the total contained on each mat. The current passing through either an X or Y winding is referred to as the half-select current.

A half-select current passing through the X3 winding (Figure 3-5) from left to right produces a magnetic field
that tends to change all cores in that horizontal row from the O to 1 state. The flux produced by the current is,
however, insufficient to complete the state transition in any core. Simultaneously passing a half-select current

through the Y2 winding from top to bottom produces the same effect on all cores in that particular vertical row.
Note, however, that both currents pass through only one core which is located at the intersection of the X3 and
Y2 windings. This is the selected core and the combined current values are sufficient to change the state of the
core. The arrows in Figure 3-5 show current direction for the write cycle.

3-8

INHIBIT
CURRENT DRIVER
-

FERRITE

‘/\/ CORES

— f§

X7 -

—|

]

)

wfi

X4 =

=4
—

SELECTED

N\~

CORE

Ims2 X3 =

X2 =

SENSE/INHIBIT
LINES

TO SENSE AMPLIFIER
TERMINATION

Figure 3-5

1-0079

Three-Wire Memory Configuration

All X and Y windings are arranged in such a manner that whenever a half-select current is passed through each,
the resultant magnetic fields combine in the core at the point of intersection. This combined, full-select current
ensures that the selected core is left in the binary 1 state. The currents used to select the core are referred to as
write currents. A typical hysteresis loop for a core is shown in Figure 3-6.

In the MM11-L Core Memory, the X3 windings in all 16 mats are connected in series as are the Y2 windings.
Therefore, whenever a full-select current flows through a selected core on one mat, it also flows through an

identical core on the other 15 mats. The X3-Y?2 cores on all mats switch to a binary
1, causing each of the 16
cores to become one bit of a 16-bit storage cell.

HYSTERESIS

LOOP FOR CORE

INHIBIT OR

FLUX STORED OR SWITCHED

READ HALF SELECT

= ""UNDISTURBED

p-— — "I"DISTURBED

I
[

1
|

i
WRITE
FULL

SELECT
FLUX
CHANGE

FOR 1 AT
<
READ

ODRIVE CURRENT

TIME

READ
FuLL

SELECT

t
|
|
|

{

"O" DISTURBED
-~ ¢
"0" UNDISTURBED-=

;

mmmmm FLUX CHANGE AT READ{

HALF SELECT WRITE

TIME FOR A "O"

NOTE NO SWITCHING
TAKES PLACE.

18]

OUTPUT SWITCHES AT THE

CORE TIME CONSTANT AND IS
o

OUTPUT COMES DURING I RISE TIME

PRIMARILY

AMPLITUDE.
oo

DEPENDENT

CURRENT AMgLiTUUEE. IT WILL

AND IS A FUNCTION OF IT AND CURRENT

SWITCH FASTER AND GROW AS

RISE TIME IS DECREASED.

OUTPUTwCE.fM?Ing 0 T

DOTTED LINES SHOW HOW
OUTPUTS WOULD BEHAVE
WITH DIFFERENT CURRENTS

11-00888

Figure 3-6

Hysteresis Loop for Core

Because of the serial nature of the X-Y windings a method is used that allows cores to rémain in the

ing a write operation; otherwise, every 16-bit word selected would be all 1s.

The method used in the MM11-L

Core Memories is to first clear all cores to the 0 state by reading and then, by using

3-10

O state dur-

an inhibit winding during the

write operation, to inhibit cores on particular mats. The inhibited cores remain Os even when identical cores on
“other mats are set to Is.

The half-select current for the inhibit lines is applied from an inhibit current driver, which is a switch and a resistor between the inhibit line and - 15V. The current in the inhibit line flows in the opposite direction from the
write current in all Y-lines and cancels out the write current in any Y-line. There is a separate inhibit driver for
each memory mat, and each mat represents one bit position of a word; thus, selected bits can be inhibited to produce any combination of binary 1s and Os desired in the 16-bit word. It must be remembered that the inhibit

function is active only during write tiime..

The sense/inhibit lines are also used to read out information in a selected 16-bit memcry cell. The specific core
is selected at read time in the same manner as during the write cycle with one notable exception: the X and Y
currents are in the opposite direction. These opposite half-select currents cause all cores previously set to 1 to
change to 0; cores previously set to 0 are not affected. Whenever the core changes from 1 to 0, the flux change
induces a current in the sense winding of that mat. This current is detected and amplified by a sense amplifier.
The amplifier output is strobed into the data register for eventual transfer to the Unibus.

Figure 3-7 shows a 16-word by 4-bit planar memory. The MM11-L Core Memory (8K) functions in the same
manner, except that it has 128 X-lines, 64 Y-lines, and 16 core mats. The core stringing is identical, and the
sense windings are strung through all 8192 cores with the interchange between X63 and X64 instead of between
X1 and X2.

3.3.3

Device and Word Selection

When the processor or a peripheral device is to perform a transaction with the memory, the processor asserts an

18-bit address on Unibus address lines A{17:00). Four of the 18 bits (A{17:14)) indicate the address of the memory as a device. Thirteen of the 14 remaining bits (A(13:01)) indicate the address of a specific word within the
memory. Address bit AQO is used to select the byte (8 bits) transactions when in the DATOB mode.

The memory address is decoded by the device selection circuit on the Control Module (G110). The word ad- dress is stored in a register on the Driver Module (G23 1) whose output is decoded to activate the X-Y line
switches and drivers which select the addressed word. These circuits contain jumpers which are included or excluded to configure the memory to establish a specific device address.

Table 3-2 lists the function of each address bit. Figure 3-8 is a simplified block diagram of the device and word
address selection circuits.

3.3.3.1 Memory Organization and Addressing Conventions — Prior to a detailed discussion of the address selection logic, it is important to understand memory organization and addressing conventions.

The memory is organized in 16-bit words each consisting of two 8-bit bytes. The bytes are identified as low and
high as shown below.

MSB

l
i
i
HIGH BYTE
1

}

DATA BITS DLI5: 00>

i
i
i
LOW BYTE
i

{

LSB
=174

Each byte is addressable and has its own address location: low bytes are even numbered and high bytes are odd
numbered. Words are addressed at even-numbered locations only; the high (odd) byte is automatically included.

3-11

ARROWS SHOW CURRENT
DURING WRITE TIME

TOP VIEW OF CORE MATS

/
XSW

r‘"’

»t

J
¢

_ X2

M
-

‘

B S

<«
X0

AN
N

T~ INTERCHANGE
IS FOR NOISE

¢
P

XDR

CANCELLATION

SA SB

THERE

INH

r»-

YSW

\ J

Y §

WR
YDR

SENSE

INHIBIT

WINDING PER MAT

—

y 3

WR
YDR

CORE

SENSE-INH LINE

NE
Y

De—xvLine

LINE

BONDING MEDIUM

fe— GROUND PLANE

BOARD

DETAILS OF CORE STRINGING

11-00884

Figure 3-7 Three-Wire 3D Memory, Four Mats
Shown for a 16-Word by 4-Bit Memory

For example, an 8K word memory has 8192 words or 16,384
bytes; therefore, 16,384 locations are assigned.
The address locations are specified as 6-digit octal numbers. The
16,384 locations for the 8K memory are designated 000000 through 037777. Figure 3-9 shows the organizat
ion for an 8K memory.

3-12

Table 3-2

Addressing Functions

Function

Bus Address

Controls byte mode

AQ00

Decode Y-Drivers
Decode Y-Switches
Decode X-Drivers
Decode X-Switches
Decodes X-Switches
Go to device selector

A02, AO03, A0l
A04, A0S, AO6
A07, A0S, AQO9
Al10, All, Al12
Al3
Al4, AlS5, Al6, Al7

DCLOL

|CONTROL MODULE G110

1
A<17:14>

>
y

400,01 |

DRIVER

DEVICE

SELECTOR

MODULE G231

U
N

-» TO CONTROL LOGIC

DSEL H

AO1 H

[
'

A13 I

‘

AO3H & L

AOSH 8 L

NAND

GATES

TDR H |

A<I2:02>
‘
|

VL
N/
l

>
v

WORD

ADDRESS

AOTH,AO2H,AO4H,AO5H,AOTH, AOBH, ATOH, A11H

‘ R

TO DECODERS

AND DRIVERS

A13 (1) &(0)

A12 (1) &(0)
AO6(1) 8(0)

)

ADDRESS

TsSH I

GATING

(AT2H-A13H) L
(AM12L-A13H) L
(A12H-A13L)L
(A12L-A13L)L

> g g%r’éfiés

1-1090

Figure 3-8 Device and Word Address Selection Logic, Block Diagram

3-13

tal‘r

I
!
e
16 Bl
T

WORD ——eip

HIGH BYTE

LOW BYTE

000001

000000

000003

000002

000005

000004

037773

037772

037775

037774

037777

037776

11-1091

Figure 3-9

Memory Organization for 8K Words

The address selection logic responds to the binary equivalent of the octal address.

The binary equivalent of

017772 is shown below as an example.

ADDRESS

17116

OjJ

115114

|13

00|00
0

BITS

A<17:00>

[12 |

|10

[0o9|

08|07

1
7

|06

|05 | 04|03

1
,

|02

BIT POSITION

BINARY

OCTAL
=173

Each memory bank requires its own unique device address. For example, assume
that a system contains three

8K memory banks (Figure 3-10). The device selector for the 8K memory decodes
four address lines (A{17:14)).

Examination of the binary states of bits

A14 and A15 allow the selection of a unique combination for each bank.
The combination, which is the device address, is hardware selected by jumpers
in the device selector.
During system operation, the processor asserts the binary equivalent of the

octal address on Unibus address lines

A(17:00). The processor uses positive logic and the Unibus uses negative logic.
Processor (Positive Logic)

Signal Asserted: High = Logical 1 = +3V

Signal at Rest: Low = Logical 0 = 0V
Unibus (Negative Logic)

Signal Asserted: Low = Logical 1 =0V
Signal at Rest: High = Logical 0 = +3V

3-14

000000

037777

040000
077777

100000

137777

1
BANK
8K WORDS

2
BANK

8K WORDS

3
BANK
8K WORDS

17
(

| LAST ADDRESS

0 ] 0 [ ol
o}

{

o i

| BINARY

OCTAL

{st ADDRESS

BANK 1«

116 | 15 | 14 | 13 | 12 | BIT POSITION
| o

|
-

olo|lo]l1t[o]o
*
2 <
BANK

_ LAST ADDRESS

{st ADDRESS

0 { 0 { 0

}

0 | 0 { 1

0 } 0 t 0

ist ADDRESS
3 <
BANK

0 } 0 ]
| LAST ADDRESS

0 }

{

1-1082

Figure 3-10 Address Assignments for Three Banks of 8K Words Each

3.3.3.2 Device Selector — The device selector is located on the Control Module (drawing G110-0-1, sheet 2).
Address bits A(17:14) are decoded in the device selector to provide the device selection signal D SEL H that is
used in the control logic.

Each memory bank must have its own unique device address. Four jumpers (W2, W3, W4, and W6) in the device
selector provide this capability. On drawing G110-0-1, sheet 2, all the jumpers are shown in place and the device
selector responds only when high signals appear on the Unibus address lines A(17:14). Some jumpers can be removed to allow the device selector to respond to a particular combination of high and low signals on these address lines.

All highs at the inputs of the 7380 Unibus receivers (E12 and E23) give lows at their outputs. Each receiver output goes to one input of a type 8242 exclusive-NOR gate. Because of jumpers W7 and W8, bit A14 is decoded.
An additional receiver is used to sense BUS DC LO L and its output (E23 pin 14) is sent to an 8242 gate (E24

pin 5). BUS DC LO L is asserted only when the ac input voltage to the Power Supply drops below the specified
limit.

3-15

The other input of the 8242 gates associated with bits Al4, A15, A16,
ground depending on whether or not jumpers W2 through W4 and

and A17 can be connected to +5V or

W6 are installed. The input is low (ground)

with the jumper in; with the jumper removed, the input is high (+5V).
parator:

Each 8242 gate is used as a digital comits output is high only when both inputs are identical. The 8242
gates have open collectors and they

are connected in common; therefore, the comparator output

D SEL H is high only when all gates detect matched

inputs (both lows or both highs).

An installed jumper requires a low signal at the output of the 7380 Unibus

receiver. The 7380 is connected as

an inverter so this signal is reflected as a high on the Unibus (logical O or asserted

figure the jumpers for a specific device address, find the binary equivalent

state for the Unibus). To con-

of the assigned octal address and insert
a jumper in each bit position that containsa 0. A specific jumper configurati
on is shown in Figure 3-11.

PROCESSOR STATE (POSITIVE LOGIC)
ASSERTED: H=1=+3V

BUS STATE (NEGATIVE LOGIC)
ASSERTED: L=1:0V
REST: H=0=+3V

REST L=0:0V

+3Vv

R108
AN

R122
w6

BUS A14 L ——Q

TM~

s |

—Q

COMMON

E23

RESISTOR

COLLECTOR

ASSERTED
ONLY

R199

D SELH _ TIF ALL

GATE

OUTPUTS

‘

BUS A15 L ———1(3

I
ONLY

\
E12

) |

/_J_,

E13

ARE

HIGH

[r—

A14 AND A1I5

A<17:46>HAVE

SHOWN.

JUMPERS

ALSO.

TRUTH TABLE
AlB|C

)

8242 EXCLUSIVE

| USED AS

|OUTPUT

1101901
NOR ELEMENT

DIGITAL

COMPARATOR.

ONLY

IS HIGH

WHEN

BOTH

INPUTS MATCH.

ASSIGNED ADDRESS 040004
17116

115

114

|13 [ 12

Oj0}1O0

Oj1ojojojolo
4

BITS A <17:14> ARE DECODED FOR DEVICE

|11

|10]

9 | 8

0]
0

{

0
4

BIT POSITION
BINARY OCTAL

OCTAL

SELECTION

17116 | 15 | 14

O0O]O |1

INSTALL JUMPERS IN THESE BIT POSITIONS
11-1093

Figure 3-11

Jumper Configuration for a Specific Memory Address

In the 8K memory configuration, jumper W9 is removed and W10 is installed.
The input of Unibus receiver E12
on G110 is +5V via resistor R107. This receiver output (pin 14) always
remains low so that jumper W5 must re-

main installed to ensure a match on pins 12 and 13 of gate E13. The
jumper configurations for memory systems

up to 128K words are shown in Figure 3-12.

3-16

Device Address Jumpers
Memory Bank

Machine Address

(words)
|

(words)

W6
Al4 or AO1

w4
AlS

W3
Al6

w2
Al17L

0—8K

000000-037776

. In

8—16K

040000-077776

Out

- 16—24K

100000—-137776

Out

24—-32K

140000—-177776

Out

32—-40K

200000-237776

Out

40—48K

240000277776

Out

48—-56K
56—-64K

300000-—-337776

340000-377776

Out

Out
Out

Out

In
In

64—72K

400000—-437776

Out

72—80K

440000-477776

Out

80—88K

500000537776

Out

640000-677776

Out

112—-120K

700000-737776

Out

120—-128K

740000-777776

Out

88—96K

540000-577776

96—104K

600000—-637776

104—112K

CONTROL MODULE G110

o W8 o

o w10 o

Out

o
wa
o

o wz Do

o
we
o
o
ws
Mo

O WieRO

o
wia
0

CONNECTOR EDGE -/

*J umper W1 is for test purposes only. It must be installed for normal operation.
**Jumpm W11 should be removed for normal operation. When installed the memory
responds to DATI only,regardiess of state of control lines COO and CO1.

NOTE:
TE

Jumpers

o
*
N

W5 W7, and W8 must remain in the factory installed positions.

Figure 3-12 Device Deéoding Guide

3-17

H-1149

3.3.3.3

Word Selection — Word selection requires two levels of decoding. The word address bits are placed in

the 13-bit word address register; some bits from the register output are combined in a gating network. The out-

puts from the gating network and some outputs directly from the register are used as inputs to a group of decoders (Figure 3-8). The outputs of the decoders select the proper X and Y read/write switches and drivers. The

word selection logic is discussed in four parts as follows:
d.

Word Address Register and Gating Logic — The word address register and gating logic are contained on

the Driver Module (G231). The circuit schematic is shown in drawing G231-0-1, sheet 2. The register
is composed of thirteen 74H74 dual D-type edge-triggered flip-flops. They are identified as E11, E12,

E13,E14, E18, E19, and E20. The output (pin 3) of gate E9 provides a high signal on the preset input (pin 4 or pin 10) of each flip-flop which prevents direct presetting of the flip-flop. Direct clearing
of each flip-flop is prevented by a high signal on the clear input (pin 1 or pin 13) via the output (pin 2)

of gate E9. The register cannot be directly cleared or preset because its output responds only to the
signal at its data (D) input. Address bits A(13:01) are picked off the Unibus via type 7380 receivers

(E15, E16, and E17). The receiver outputs are sent to the corresponding flip-flop D-inputs. The 8K
memory requires J4 in and J3 out. The flip-flop (E11) associated with bit AO1 receives its input from

the device selector (drawing G110-0-1, sheet 2). The input signal is AO1H which is obtained from bit
AO0O1 Unibus receiver for an 8K memory.

The register flip-flops are clocked synchronously by CLK 1 H from the control logic (drawing
G110-0-1, sheet 2). Clocking occurs on the positive-going edge of CLK 1 H. The generation and tim-

ing of this clock signal is discussed in Paragraph 3.3.7. When the register is clocked, the outputs of
flip-flops AO1, A02, A04, A0S, A07, A08, A10, and A11 are sent to the type 8251 X-Y line decoders
on the Driver Module (drawing G231-0-1, sheets 3 and 4). The outputs of flip-flops A06, A12 and

A13 are combined in a group of six type 74H10 NAND gates (three E22s and three E25s) which are
enabled by the signal TSS H. Table 3-3 lists the states of flip-flops A06, A12, and A13 that are required to enable th=se gates. The outputs of flip-flops A0O3 and A09 are gated with the TDR H in high-

speed, 2-input NAND gates and then applied to the decoders for the drivers only.

Table 3-3
Enabling Signals for Word Register Gating

Output Signals
Gate

Asserted Signal

E22 pin 12

(AO6H) L

E22 pin 8

AO6L

E22 pin6

Enabling Signals
FF A06

FF A12

FF A13
X

Set

Reset

(A12H - AI3H)L

Set

E25 pin 12

(A12L . AI3H)L

Reset

Set

E2S pin 8

(A12H - A13L) L

Set

Reset

E25 pin 6

(AI2L . AI13L)L

Reset

The six signals listed in Table 3-3 are sent only to the X-Y line read/write switch decoders on the
Driver Module.

TSS H is generated at the output (pin 3) of negative input OR gate E4 during a read or write operation.
During a read operation, the enabling signal is produced at NAND gate E4, pin 8 by ANDing READ H
and TNAR H. During a write operation, the enabling signal is produced at NAND gate E4, pin 6 by

ANDing WRITE H and TWID H. READ, TNAR, and TWID are generated by the control logic on the
Control Module. WRITE is the complement of READ (produced by inverter E6). READ H comes

from the 1 output of read/write flip-flop E13 (drawing G110-0-1, sheet 2): READ H is produced
when the flip-flop is set. When the read/write flip-flop is cleared, READ H is low and it is inverted by

E6 to produce WRITE H.

3-18

X- and Y-Line Decoding — The basic decoding unit is a type 8251 BCD-to-decimal decoder. It converts
a 4-bit BCD input code to a one-of-ten output; however, only eight outputs are used. Figure 3-13
shows an 8251 decoder and an associated truth table. The inputs are DO, D1, D2, and D3; they are
weighted 1, 2, 4, and 8 with DO being the least significant bit. The outputs are 0—7 and are mutually
exclusive. The selected output is low and all others are high.

7 o..fi.._._....

BCD IN

BUT 4

6 p~—— | TO WRITE

—Bg o
14

3
SWITCHES
/
5 O~ | DRIVERS

a2l

P
D3

+5V

3 p———

2 D—————-—-mfi

TO READ

SWITCHES/

D———— | DRIVERS
13

i A
TRUTH TABLE

INPUTS

OUTPUTS

p3[ozlp1]oojof{1]|2]|3]a|s]|6|7
ololofololt

a1l

ofofofritjolt{tivit1]t1in

lojoltjolr

1ot

1;1

11l rfolv]r]ti1
olol1lv
oltlolol1ltl1lriol1 1]

olt1lolr

1111

oltlt1]lolt

]1]ofl1]1

1111

]1]0]1

CIEREREREEREEERERERER

vixixixitlboebv

X=1RREVELANT
111095

Figure 3-13

Type 8251 Decoder, Pin Designation and Truth Table

For the 8K memory, ten decoders are used: six for the X-axis and four for the Y-axis. Each decoder
controls four read/write switch-pairs. Each pair is associated with a specific switch or driver. This
switch matrix is combined with the stack X-Y diode matrix to allow selection of any location out of
the total 8192 locations (see stack drawing DCS-H214-0-1 for interconnections). The X- and Y-line
switches are first differentiated as switches and drivers. The drivers are those switches that are connected to the diode end of the stack. Drivers and switches are further differentiated by function:

either read or write. Another differentiation is made by polarity: negative or positive, depending on

the physical connection. Read drivers and write switches are connected to the current generator outputs and are considered positive; write drivers and read switches are connected to-15V and are considered negative.

Figure 3-14 shows the decoders associated with Y-line read and write switches 4—7 and Y-line read and
write drivers 4—7. (Refer also to the truth table in Figure 3-13.) In both decoders (E28 for switches
and E8 for drivers), the signal to input D3 selects the block of switch pairs. This signal must be low
for any output to be selected. The signal to input D2, which is READ L for all decoders, controls the

selection of read or write switches/drivers. When READ L is low, outputs 0—3 can be selected; these

are read switches and read drivers. When READ L is high, outputs 4—7 can be selected; these are
write switches and write drivers. The four combinations of the states of inputs DO and D1 select the
particular switch/driver.

3-19

AO6

READ L

AOS H

AO4

QD3

E28
D1

AO3

YS6

WRITE SW

YS6 READ SW

“

5 o >

YS5 WRITE SW

YSS5 READ

YS4 WRITE

FOR READ AND

WRITE

YS4 READ SW

SWITCHES

]

WRITE SW

YS7 READ SW

a
6

0 b

TOR

YS7

3 :::m

DECODER

YS4 -YS7

YP READ

DR7

YN WRITE

DR7

READ L

AO2

AOt H

DECODER

20—

4
60—

D2
£8
Di

12
{ O—————
5o————-1

YP READ DR6
YN

WRITE

DRS6

YP READ

DRS

WRITE

DR5

FOR READ AND

OP——

YPREAD

DR4

40—

YN WRITE

DR4

WRITE

DRIVERS Y4-Y7
11-1096

Figure 3-14

(contj

Decoding of Read/Write Switches and Drivers Y4—Y7

The four driver decoders (E3, E8, E43, and E46 on drawing G231-0-1, sheets 3 and 4) have a NAND |
gate connected to input D3. Signal TDR H is an input to each gate; therefore, the driver decoders cannot be enabled unless TDR H is high. This signal is generated on the Driver Module (drawing

G231-0-1, sheet 2, coordinates A-B) by ANDing TWID H and READ H or TNAR H and WRITE H.

Each switch/driver is connected to the decoder output by means of a transformer-coupled base drive
circuit. When the decoder output is at ground (low), the switch/driver is turned on; it is turned off
when the decoder output is at +3.5V (high). The base drive circuit for write switch YS7 shown in

Figure 3-15

is typical.

In this example, the decoder inputs have selected output 7 which is at ground. Current i, flows into
this decoder output circuit from the +5V supply via resistor R11 and the primary winding (terminals
4 and 3) of transformer T8. The value of i, is determined by the value of R11 and the voltage reflected into the transformer primary (approximately 1.0V). An equal current, i,, is induced in baseemitter circuit of write switch E29 which is connected to the transformer secondary winding (termi-

nals 13 and 14). This current turns on E29. All the base current for E29 is provided by this circuit;
i, is the collector current. When the decoder is turned off, its output pull-up transistor tries to drive
the turn-off current i 4 in the opposite direction. This reverse current removes the forward bias from
the base of E29 and turns it off. Capacitor C30 allows the decoder to pump reverse current i4 into the
transformer primary; it also speeds up turn-on current i,. Diode D1 prevents reverse breakdown of

the base-emitter junction of E29; it also protects the decoder output.

3-20

+5V

8251
DECODER
E28

‘b

ZD1

==C30 § R11
FROM

CURRENT
GENERATOR

¥
715

E29

WRITE

SWITCH

3
PORTION OF
OUTPUT 7

gt
-

Figure 3-15

H-1097

Switch or Driver Base Drive Circuit

Drivers and Switches — Drivers and switches direct the current through the X- and Y-lines in the
proper direction as selected by the read and write operations.

For an 8K memory, sixteen pairs of read/write switches and eight pairs of read/write drivers are provided in the X-axis; eight pairs of read/write switches and eight pairs of read/write drivers are provided
in the Y-axis. In conjunction with the stack diode matrix (drawing H214-0-1, sheet 2), one driver and
any one of sixteen switches select sixteen lines in the X-axis; one driver and any one of eight switches
select eight lines in the Y-axis. This allows selection of 128 lines in the X-axis and 64 lines in the Y-axis.

This provides a 128 X 64 matrix that selects any location out of 8192 locations.
Figure 3-16 is one-fourth of a Y-selection matrix showing the interconnection of the diodes and the

lines from the switches and drivers. It shows how four pairs of switches and drivers are connected to
select sixteen locations. (Refer to drawing H213-0-1, sheet 2 for an extension of this method that uses
eight pairs of switches and drivers to select 64 locations.)

Figure 3-16 shows four pairs of drivers and four pairs of switches for the Y-axis only; polarities are
shown for convenience.
The diodes are identified to assist in associating them with the drivers and switches. Each line from a

twin diode interconnection to a read/write switch pair passes through 64 cores and represents one line
on each bit mat. Assume that a write operation is to be performed and the word address decoders
have selected write switch WYSO00 and write driver YNWD1. The Y-current generator sends current

through write switch WYS0O0 (conventional flow) which puts a positive voltage on the anodes of

diodes 03W, 02W, 01W, and OOW. The non-selected write drivers (YNWD3, YNWD2, and YNWDO0)
provide a positive voltage on the cathodes of their associated diodes (03W, 02W, and 00W respectively)
which reverse biases them and prevents conduction. Write driver

YNWD1, which has been selected,

turns on and makes the cathode of diode 01W negative with respect to the anode which forward biases
it. The diode conducts and allows current to flow to write driver YNWD1. A half-select current now

flows through this line that links 64 cores per bit mat (1024 total for 16 mats).
Figure 3-17 is a simplified schematic of two pairs of switches and drivers interconnected with the core

stack and current generator. Read/write switches YSO7 and read/write drivers YD7 are used as examples. These switches and drivers are chosen for convenience. For a read or write operation, there

are 64 switch/driver combinations available on the Y axis and 128 on the X axis. For a read operation,

decoder ES8 selects positive read driver E7 via transformer T3, and decoder E28 selects negative read

3-21

switch E26 via transformer T7. Both E7 and E26 are turned on when they are selected. E7 conducts

(cont)

and removes the reverse bias on diode D67 which allows current from the Y-current generator to flow
through D67, E7, the associated matrix diode, and the cores on the selected line. After passing through
the cores, the current flows through E26 and R27 to the —15V line. For a write operation, decoder
E28 selects positive write switch E29 via transformer T8, and decoder E8 selects negative write drivers
E10 via transformer T4. Both E29 and E10 are turned on. E29 conducts and removes the reverse bias
on diode D17 which allows current from the Y-current generator to flow in the opposite direction

through D17, E29, and the cores. After passing through the cores, the current flows through the as.

sociated matrix diode, E10, and R140 to the —~15V line. Read current flow is shown as a solid line; a
broken line shows write current flow.

SWITCHES

*IRYSQO
+ !WYSOO |

- lwsm

_[mvsos

2 33R

A 23R

+ [wrsoe

I2W

& 22w

B
!
-

- lmsm

& 32R

A 22R

A 12R

33W &

‘

31R

I/72wW

O3R

% O2R

21w | & 1w | & 01w
21R

YPro3 | +

ozw | [Ywoz] -

12w

E 3w

13R

pee

Mfl

& OiIR

I YPRD1 l—{-

A 20w

4 10w

+ lwvgoa |

]

+[wvso1

[

DRIVERS

& 33w | & 23w | & 13w | & osw | LYNWO3|-

YNWDO

& 20R

4 OOR

r‘—"l

64 CORES/MAT
L

33RE

OR 1024 TOTAL

FOR EACH LINE

& 30w

Eme—

I/2R

A 30R

TYPICAL JUNCTION

Y-AX1S

4x4

10R

SECTION

YPRDO | +

(16 LOCATIONS)
H"-1088

Figure 3-16

Y-Line Selection Stack Diode Matrix

Word Address Decoding and Selection Sequence — This paragraph takes a specific word address
through the decoding and X- and Y-line selection sequence.

The word address is 017772 and it is assumed that a specific 8K memory bank has been selected. The
binary equivalent of the address is shown below. A read operation is to be performed.

ADDRESS BITS

A<17:00>

17116115114

113

112 | 11

|10

|09|0B

10}

010}

|07
1
7

3-22

|06|05|04|
1

1
7

|02|

|OO0]

]

O | BINARY

BIT POSITION

OCTAL

+5V

WRITE
CURRENT

; D60

De7 ¥

i D61
e

-15v

R141

+5 MN—
POS

READ DRIVER

N’

YPRD7

TO DECODER

T
8

3133
Bpccammn

DIODE

PAIRS

9
V¥

1024 CORES

R150

(64/MAT)

NEG WRITE DRIVER
|

Y'Y

YNWD7

E10

TO DECODER

——

b
I
B

READ
CURRENT

Y-CURRENT

GENERATOR

¥ 017
R9

@——ANAA- + 5V
POS WRITE SWITCH

()YSO7%

TO DECODER
E28
n

Rt
CIRCUIT

-15V

NEG READ SWITCH

E26

YSO7

‘

R140

om———

TO DECODER

£28

R27

‘

-5V
11-1089

‘Figure 3-17

(canti

Typical Y-Line Read/Write Switches and Drivers

Bits A(13:01) are used to decode the word address. Bit AO1 is sent to the device selector (drawing
G110-0-1, sheet 2) and appears at word address flip-flop E11 pin 2 as A01 H (drawing G231-0-1 ,
sheet 2). Bits A{13:01) are sent to the Unibus receivers which are inputs to the associated word address flip-flops. J3 is out and J4 is in. Table 3-4 shows the state of bits A{13:01) and the decoding signals generated by the word address flip-flops after they are clocked.
The output signals from flip-flops A06, A12, and A13 are not used directly from the flip-flops. They
are sent to gating logic (E22 and E25) and are ANDed with signal TSS H. In this case, only two out of
a possible six signals are generated: AO6H is low from E22 pin 12 and (A12H - A13L) L is low from

E2S5 pin 8. These signals and the outputs from the other word address flip-flops are sent to the inputs
of the type 8251 decoders to select the appropriate switches and drivers. READ L is an input to each
8251 decoder. A read operation is to be performed; therefore, READ L is low.
The decoders, switches, and drivers are shown in drawing G231-0-1, sheets 3 and 4. Using the decoding signals in Table 3-4 and the operating characteristics of the decoders, it is possible to determine
which decoders have been selected for word address 017772. A decoder is selected only when its D3
input is low. In this case, the selected decoders are E34 and E46 for the X-line (drawing G231-0-1,
sheet 3), and E23 and E8 for the Y-line (drawing G231-0-1, sheet 4). READ L is low and is sent to input D2 of each decoder; it selects read drivers and switches in this case. To verify this point, refer to
the truth table and diagram in Figure 3-13. Decoder inputs DO and D1 select the particular switch or

driver as shown below.

3-23

Decoder E34

(cont)

D1 is high, DO is high:

Selects output 3 (pin 10) which is read switch XS07

Decoder E46

D1 is high, DO is high:

Selects output 3 (pin 10) which is read driver XPRD7

Decoder E23

D1 is high, DO is high:

Selects output 3 (pin 10) which is read switch YS03

Decoder E8

D1 is low, DO is high:

Selects output 1 (pin 12) which is read driver YPRDS
Table 3-4

Word Address Decoding Signals

Address Bit

Unibus

‘

Flip-Flop

Receiver Input

Receiver Qutput

Flip-Flop State

Output Signals

AQl

set

AOlH=H

A02

reset

AO2H =L

AQ3

set

AO3H=H, AO3L=L

AQ4

set

AO4H =H

AQ5

set

AO5SH=H

AQ6

set

AQ7

set

AQO7H=H

AQ8

set

AO8H =H

AQ9

set

AQ9H =H, AO9L =L

Al0

set

AlOH=H

All

set

AllH=H

Al2

set

Al12H=H,
A12L =L

Al3

reset

Al3H=L, A13L=H

AO6H =H, AO6L=L

The last step is to follow the outputs of the drivers and switches to the stack diode matrix (drawing
H213-0-1, sheet 2). For the X-line, the circuit is from driver XPRD7 to diode junction E7-11, across
termination 35 to switch XS07. For the Y-line, the circuit is from driver YPRDS to diode junction
E4-9, across termination 15 to switch YS03. The terminations indicate the point on the stack printedcircuit board where the X- or Y-line is soldered. Physically, the wire that is connected across the ter-

mination is strung through 64 cores per bit mat (total of 1024 cores in series for 16-bit memory).

3.34 Read/ Write Current Generation and Sensing
Aside from the addressing and control logic, four functional units are involved in generating current to switch
the cores and detect their state. The X- and Y-line current generators supply the drive current (via switches and

drivers); the inhibit drivers allow Os to be written during a write operation; the sense amplifiers detect 1s during
a read operation; and the memory data register (MDR) temporarily stores data to be written or data that has

been read from the memory. This paragraph describes each functional unit and discusses their interrelation.
3.3.4.1

Read/Write Operations — The discussion of the read/write operations shows the interrelation of the cur-

rent generator, inhibit drivers, sense amplifiers, and memory data register. Details of the operation of each func-

tional unit are discussed in subsequent paragraphs. Several control signals are mentioned; however, details of
their generation and timing are described in Paragraph 3.3.7.

3-24

For clarity, one data bit (D07) of the selected word is discussed and the text is referenced to Figure 3-18, which
is a simplified block diagram. Detailed logic for the MDR, Unibus receivers and drivers, sense amplifiers, and inhibit drivers for all 16 data bits is shown on drawings G110-0-1, sheets 3 and 4.

STROBE O H

TINHOH

SENSE
AMP

INHIBIT
DRIVER

ES3

INPUT
NETWORK

INVERTER

—=0 E10 \2

PRE

1 .

E21

6 | REC

[—0, ___/

» |DRIVER |
=

E54

BIT DO7

|
LOAD O H

CLK

CLR

DATA OUT H

DO7

DO7
RESET O L

UNIBUS DATA LINES D<I5:00>

THRESHOLD

VOLTAGE

_ SENSE AMP INPUT
FROM

STACK

SENSE LINE
OUTPUT E52 (6-T)
RESET O L

STROBE H

SENSE _AMP
QUTPUT

E56 OUTPUT

J
E54
OUTPUTS

DATA OUT H
.

E21 OUTPUT
TO UNIBUS

o——

Figure 3-18 Interconnection of Unibus, Data Register,
Sense Amplifier, and Inhibit Driver

3-25

During a read operation, half-select currents flow in the X- and Y-lines for the selected word in

each bit mat.
These currents flow opposite to the write currents; therefore, cores in the 1 state are switched to the O state

and

cores in the O state are unchanged. Switching the core from the 1 state to the O state induces a voltage
pulse in

the sense winding. This pulse is detected by sense amplifier E52 as a differential voltage on input pins 6 and
7 |
that exceeds the threshold reference voltage. This pulse is amplified and when STROBE 0H is generated at pin
11 the output of sense amplifier E52 goes high. Just prior to the strobe signal, the control logic generates
RESET
0 which clears (resets) flip-flop E54. The sense amplifier output is inverted by E56 and sent to
the preset input
(pin 10) of MDR flip-flop E54. A low on the preset input sets the flip-flop; its 1 output (pin
9) is a high and its

0 output (pin 8) is a low. The high from pin 9 of the flip-flop is sent to input pin 1 of the Unibus driver E21.
The other input to this gate is the data out signal. When the control logic generates DATA OUT H, the output
of E21 is low (logical O for memory logic and logical 1 for Unibus logic). This is the read-out of
bit DO7 and it
is sent to the requesting device via the Unibus. Timing diagrams for the sense operation are also shown in Figure
3-18.
The read operation is destructive: all cores at the specified location
are now 0. The data that was read must be
restored by a write operation which immediately follows the read operation. Flip-flop E54 is still in
the set state;

therefore, its 0 output (pin 8), which is low, is sent to input pin 9 of NAND gate E53. The control
logic generates the inhibit driver control signal TINHO H which is the other input to gate E53. The gate
is not asserted (pin

8 is high) and the inhibit driver is not turned on. With no inhibit current in the inhibit line to oppose the
half-

select Y-line current, a 1 is written back into the appropriate cores. In this example, if bit DO7
is a 0 in core, it

does not switch during the read operation and the output of sense amplifier E52 does not go high. Flip-flop
E54
remains cleared (reset); its 1 output (pin 9) is low and its O output (pin 8) is high. When the control logic
generates DATA OUT H, the output of Unibus driver E21 is high (logical 1 for memory logic and
logical O for Unibus
logic). The O output of flip-flop E54, which is high, is sent to NAND gate E53. During the subsequent
write operation, TINHO H is generated. This produces a low output signal at E53 pin 8 to activate
the inhibit driver

which produces a current that opposes the Y-line current and prevents a 1 from being written into
selected word.

this bit of the

The read/write operation which has been discussed is a read/restore operation (DATI). The requesting device
wants to read a word from memory and, as an internal requirement, the memory must

restore the word by writ-

ing it back in core. In this case, the MDR flip-flops are preset by the sense amplifier outputs
when 1s are read

from the core. The flip-flop outputs are used in the subsequent write (restore) operation to control
the inhibit
drivers. If the requesting device wants to write a word into. memory (DATO), it must load the
data into

the

MDR flip-flops. The device asserts the data on the Unibus from which it is picked off via Unibus
receivers.
In this example, bit DO7 is sent to pin 7 of Unibus receiver E10. The bit is inverted by the receiver

and sent to
the D-input (pin 12) of flip-flop E54. At the start of the DATO cycle, the control logic generates
LOAD 0 H
which clocks the flip-flop. If the D-input is high, E54 is set and its O output is low. Control
gate E53 is not asserted by TINHO H and the inhibit driver is not turned on. A 1 is written into the selected
core. If the D-input

is low, E54 is reset and its O output is high. Control gate ES3 is asserted by TINHO H and the
inhibit driver is
turned on. A 0 is written into the selected core. Because RESET and STROBE are inactive
in this mode, the

read is used only to magnetically clear the cores to the zero state.

3.3.4.2 X-and Y-Current Generators — Two identical current generators are provided: one each
for the X- and
Y-drive lines. They generate the current pulses that are used during read and write operations to
switch the cores.
The current generators and associated reference voltage supply are shown in drawing G231-0-1,

sheet 2. This

discussion refers to Figure 3-19 which shows the Y-current generator and reference voltage supply.

3-26

+5V

$R83

T Sa—

b s

TWID H

‘

T;MP COMP 4

DS8'X

=xC48

RC52

C514

i€

MOUNTED ON STACK
AN

R84

0 Y AXIS

$R94
)

R90

—9 ‘3“;“"%%5 AND
IVE

A o062

/ P>°4

R91

R92

Jy2

v REF

*—MN——df O——@

g
SV,

Y063

3R95

2R93

TO X CURRENT

GENERATOR

I
—15V

11-1101

Figure 3-19

Y-Current Generator and Reference Voltage Supply

Optimum core switching requires repeatable current pulses of constant amplitude with a linear rise time. The
current generator and reference voltage circuit provide current pulses that meet these requirements. The ampli-

tude of the output current pulse is determined by the reference voltage circuit; the rise time is determined by an
RC circuit in the current generator; and pulse duration is determined by the length of the triggering pulse
TWID H.

During the quiescent state of the current generator, input transistor Q8 is on; its collector voltage is 4.7V and is
connected to the cathode of diode D62 which reverse biases it. The anode of D62 is connected to the emitter of

transistor Q4 which is the output of the reference voltage circuit. In this state, D62 blocks the output from the
reference voltage circuit to the current generator. With Q8 on, both output transistors Q9 and Q10 are turned
off’; the current generator is off.

Operation of the current generator is mggered by a high TWID H mwal from the control logic. TWID His
double inverted by two E6 inverters and sent to the base of Q8 which turns it off. When Q8is cut off, capacitor
C52 starts charging. This provides base drive to output transistors Q9 and QI 0 and they start to conduct. With

Q8 off, its collector goes negative until it reaches the forward bias level of D62 which is the value of the reference
voltage minus the voltage drop across D62. The rise time of the current pulse is determined by the time constant

of C52, R87, and R88. The amplitude of the pulse is determined by the value of the reference voltage. When
TWID H goes low again, the current generator is turned off and the output pulse is terminated.

A resistor network in the base circuit of Q4 in the reference supply is used “:m set the amplitude of the current

generator to approximately 410 mA. The total resistance of parallel network R90, R91, and R92 is changed by

3-27

the configuration of jumpers J1 and J2. The amplitude of the current generator output pulse is factory set as

close as possible to 410 mA at 25°C. It should not be changed in the field.
The base circuit of Q4 is temperature compensated by a resistor and thermistor that are mounted on the stack.
This ensures that the amplitude of the current generator output pulse remains within specified tolerances

over

the temperature range of 0°C to S0°C. This temperature compensation is approximately - 0.8 mA/°C
3.3.4.3

Inhibit Driver — A detailed schematic of the inhibit driver for bit DO7 is shown in Figure 3-20; it is typi-

cal of all 16 inhibit drivers (drawing G110-0-1, sheets 3 and 4).

//"‘)

+Sv

STROBE

——

3 Rss

v TH=22mV
=

0758

X Di4

S R4

N AAASTTT

X1
y

.
"INH

{

)

m
'INH

R43S

Y YN

S
Y013

6 N

R57 3

%l SeNsE o
S]awe

—

=
|

10 E34

MDR DO7

SENSE AMP

|
SRI3

1. C430

C8 X

OUTPUT

-5V
07SA

O7IN

-15V
i

————>
INH

R72

INH

BELLE|
Q7

C55

TINHO H ——
9|

DO7 (0) H ——

E53

8 e

NW\__.....q

yDs9

R87 3 ’TNC?Q

f1-1102

Figure 3-20

Sense Amplifier and Inhibit Driver

| When the inhibit driveriis off, none of the currents shownin the schematic are flowmg Transistor Q7 is held off

by the negative voltage on its base. The output of NAND gate E53 goes low (ground) when thxs inhibit driveris

selected Current ii flows into the output circuit of E53 from the +5V supply via resistor R87 and the primary
winding (terminals 15 and 16) of transformer T8. An equal current is inducedin the base-emitter circuit
of Q7

whichis connected to the transformer secondary winding (terminals 1 and 2). This base current overcomes the
reverse bias voltage and turns on Q7. Current
ii, and therefore induced current 12 , is determined by resistor R87

and the reflected base-emitter voltage Vie of Q7. When Q7is turned on, current flows from gmund thmugh

Balun trzmsfanner T’7 isolation dwdes Dl 3 :md D14, and the &ense/mhxblt winding to the common inhibit

3-28

terminal (07IN). The Balun transformer balances the two inhibit half currents. At terminal O7IN, the full inhibit
current flows through resistor R72 and Q7 to —15V. The value for inhibit current is calculated as follows:
linhm

15V - Ve sat Q7 V’be diodes
R72 + Rcore mat

_15-08-12

13 + 4.5

"’”175

= 740 mA

Each leg of the sense/inhibit sees half the inhibit current appmmmately 370 mA. Capacxtor C55 decreases the
rise time of the current.

The inhibit driver is turned off when the output (pin 8) of gate E53 goes from low to high. At turn-off time, the
back emf caused by the stack inductive reactance tries to drive the collector of Q7 highly positive; however,
diode D43 clamps this voltage to ground. When the output of E53 goes high (approximately +3.2V), its output
pull-up transistor (an integral part of the gate circuit) tries to drive the turn-off current i, in the opposite direction through the transformer primary winding. An equal currem inducedin the secondary winding removes the
forward bias from the base of Q7 and turns it off. With Q7 mff, all dynamic current flow ceases in the circuit
and the negative voltage on the base of Q7 keeps it turned off until the output of gate E53 goes low again.

i, into the transformer primary; it also helps to decrease
Capacitor C74 allows the gate to pump reverse current
the turn-on time of Q7. Diode D59 prevents reverse breakdown of the base-emitter junction of Q7.
3.3.4.4 Sense Amplifier — A detailed schematic of the sense amplifier circuit for bit D07 is shown in Figure
3-20; it is typical of all 16 sense amplifier circuits (drawing G110-0-1, sheets 3 and 4). It consists of the sense

amplifier, terminating network for the sense/inhibit winding, and threshold vc»ltage mtwork

The sense amplifier input (E52 pins 6 and 7)is across the sense/inhibit winding (points 07SB and 07SA). Resistors R13 and R14 are matched to terminate the smae/ inhibit linein the desired impedance. Practically speaking,

during the sense operation, the inhibit driver connection is an open circuit through the driver transistor Q7. The
effect of the inhibit driver circuit, Balun transformer T7, and isolation diodes D13 and D14 can be ignored during the sense operation, because the diodes are reverse biased.

Sense amplifier E52 is one-half of a dual IC package (type 7528). A mmphfiad block diagram of the package is
shownin Figure 3-21. The two identical circuits are marked 1 and 2. Each one consists of a preamplifier and
sense amplifier. The output of the preamplifieris available asa test point to observe the amplified core signal

and to facilitate accurate strobe timing. Both circuits share a reference voltage (or threshold voltage) amplifier
(pins 4 and 5). In this application, pin 4 is grounded and a positive threshold voltage of approximately 20 mV is
supplied to pin 5. This voltage is obtained from the +5V supply through resistor voltage divider R57 and R58;
C40 is a bypass capacitor. Operation of the sense amplifier is discussed in Paragraph 3.3.4.1.

3.3.4.5 Memory Data Register — The memory data register (MDR) is a 16-bit flip-flop register that is used to
store a word after it is read out of the memory, or to store a word from the Unibus prior to its being written
into the memory. Itis composed of eight 74H74 dual hlgh«apeed D-type flxpflmm Bits DO0O—DO7 are shownin
drawing G110-0-1, sheet 3 and are identified as E54, E57, E60, and E63; bits DO8—-D15 are shownin drawing

‘G110-0-1, sheet 4 and are identified as E42, E45, E48, and E51.

3-29

VeeTM

Vect

[¢]

[1e]
CIRCUIT 1

15| TEST POINT 1

INPUT 1{
DIFF
- INPUT
THRESHOLD
VOLTAGE

}—{13] outPUT 1

|tV

B
SAz2

INPUT 2

>—<»

— E

STROBE H

D—-—m OUTPUT 2

sB2
10] TEST POINT 2

CIRCUIT 2

CexT

GND

11-1103

Figure 3-21

Type 7528 Dual Sense Amplifiers with
Preamplifier Test Points

At the start of a memory operation, the MDR is cleared directly via the CLEAR input (pin 1 or pin 13) of each
flip-flop; the clear signal is RESET 0 L for bits DO0—D07 and RESET 1 L for bits DO8—D15.

The operation of the MDR during a read/restore operation (DATI) and a write operation (DATO) is discussed in
Paragraph 3.3.4.1.
3.3.5

Stack Discharge Circuit

The stack discharge circuit assists the stack capacitance in recovering and shortens the rise time of the stack current. It also reduces unwanted currents in the seven unselected lines associated with the selected driver.

Figure 3-22 shows the stack discharge circuit. Its output is taken from the emitter of transistor Q2 and goes to
the junction of each X and Y read/write switch pair via a resistor. This common interconnection is labeled VO..

It is desired that Vo( = 0V (ground) during a read operation, and V, = - 15V during a write operation. The ef-

fective stack capacitance associated with each line is shown as Cotack During a write operation, READ H is low; it is inverted and ANDed with TWID H at NAND gate E4. The low
output (pin 11) of E4 is inverted by E6 and sent to the cathode of diode D51 which reverse biases it. The emit-

ter of Q1 becomes more positive, overcomes the constant positive base bias, and turns on transistor Q1. When
Q1 conducts, it provides base drive for Q3 which also turns on. When Q3 conducts, it reduces the base drive on

Q2 and it turns off. The emitter voltage of Q2 goes to approximately —14V which is V, on the switch node for
the stack. Diode D57 prevents hard saturation of Q3. Diode D55 holds Q2 off. During a wme opemtmn Vo =
- 14V and the stack dmcharge circuit is considered to be turned on (input transistor Q1 is on).

During a read opemtmn READ H is high; it is inverted and ANDed with TWID H at NAND gate E4. The gate is
not asserted and its output (pin 11)is high. This signalis inverted by E6 and sent to the cathode of dwde D51

which forward biases it. The voltage on the emitter of Q1 produced by the current through R77 and D51 is not
enough to overcome the constant positive bias and Q1 is turned off. With Q1 off, Q3 loses its base drive and

turns off. Now, D55 cannot hold Q2 off. Aslong as the stack capacitance is charged negatively, base current
exists for Q2 and it remains on. The stack capacitance now charges in the positive direction until it reaches

3-30

ground potential. During a read operation, V, = 0V and the stack discharge circuit is considered to be off (input transistor Q1 is off).

+5V

READ H

TWID HW

n o1

R783

R77%

D51

3R79

WRITE SWITCH

Q1 |

R803

READ SWITCH

C STACK M

I
-

R813

-15V

OTHER READ/WRITE
TO ALL
, S‘a’WWflN WMRL“»
3&“ X AND
#-1104

Figure 3-22

Stack Discharge Circuit

To see how the stack discharge c'ircuit reduces unwanted currents on the seven unselected lines associated with
the selected driver, see Figure 3-17.

During a read operation, the stack discharge circuit is off and V, = OV. The current generator drives the read

driver node of the stack towards ground; the current generator output is clamped to ground by diode D61

(Figure 3-19). The anodes of the eight read diodes are at ground. The stack discharge circuit is on and the

cathodes of the seven unselected diodes are also at ground which back biases them; therefore, they are off. The
read switch pulls the cathode of the selected line mwards -14V which forward biases it and allows conduction

through the diode. Current flows only thmugh the selected Imr:':: Reverse biasing of the diodesin the unselected
lines prevents current fmm flowing between the m%lectedmd@a and the selected read dmver.

The stack discharge circuit performs the same task during the write opemtwn by back biasing the anodes of the
- 14V,
dmdesin the unselected lines with
3.3.6

DC LO Circuit

A circuit on the Driver Module (drawing G231-0-1, sheet 2) opens the - 15V supply line to the current generators
when power is interrupted to the Power Supply. When power is interrupted, the +5V supply is lost and the operation of all logicis indeterminate. In this state, it is necessary to cut off the- 15V supply to the X- and Y-line

current generators to prevent them from destmymg stored data. The circuit that performs the- 15V cut offis
called the DC LO circuit (Figure 3- 23).

The - 15V supply for the X- and Y-line current generators passes through transistor Q7 in the DC LO circuit. Q7
must be turned on for the - 15V to reach the current generators.

3-31

+5V

BUS DC LO L

FROM UNIBUS

"%fl 0.4V
ARGy

~15V TO CURRENT GENERATORS
=15V FROM SUPPLY
1n-10s

Figure 3-23

DC LO Circuit, Schematic Diagram

The circuit monitors BUS DC LO L from the Power Supply via the Unibus. This signal is sent to the base of
transistor Q5. When power is on, BUS DC LO L is high (not asserted). The voltage across R96 forward biases

Q5 and it turns on, which turns on Q6. The conduction through Q5 and Q6 forward biases Q7, which turns it
on. The - 15V flows through Q7 to the X- and Y-line current generators.

When power is interrupted, BUS DC LO L goes low (asserted). Q5 is now reverse biased and it turns off, which

turns off Q6. With Q5 and Q6 off, Q7 is also turned off which opens the - 15V line to the current generators.
This circuit still functions when BUS DC LO L is asserted even if the +5 supply drops to O.

3.3.7

Operating Mode Selection Logic

When the memory is addressed by the master device, one of four bus transactions is selected. The transaction
(or operation) selected is determined by the states of control bits CO1 and CO0 and address bit A0O as placed on
the Unibus by the master device. Table 3-5 shows the states of these bits for each transaction.

Table 3-5
Selecficm of Bus Transactions
Mode Control
Transaction

Data In

| Mnemonic

DATI

'
‘
C01:00 | Octal

Control A0 |

Function

Data from memory to master. Memory
performs read and restore operations.

Data In,

DATIP

Data from memory
to master. Restore

Pause

|
|

operation is inhibited. Must be followed
by DATO or DATOB Read Gperatmn

is inhibited.

Data Out

DATO

Data Out,

DATOB

Data from master to memory (words)

Data fmm master to mamory ngh

High Byte

Data Out,

byte on data lines D{15:08).

DATOB

Low Byte

3-32

Data from master tomemory Low byte
on data lines D{07:00).

The logic that decodes the mode and byte control bits is shown in drawing G1 10-0-1, sheet 2; it appears at the
bottom of the sheet andis identified as the byte masking logic. Bits BUS C01, BUS C00, and BUS AQO are
taken from the Unibus to three E29 receivers. One input of each gate associated with CO1 and CO0Ois connected
to the output of the PROTECT LOW gate (E29 pin 3). Bmh inputs to this gate are tied to +5V so that its output is always low. For tmubleshmotmg purposes, a jumper (W11) can be installed that makes the gate output

high, which allows only DATI ope:ratmns to be performed regardlas& of the states of bits CO1 and C00. This

jumper hardwires the memory as a read-only device.

The outputs of the three E29 receivers (CO1 , C00, and A0Q) are sent to the byte masking logic to generate
LOAD 0 H and LOAD 1 H and to qualify a group of gates, which are enabled by control signals to generate

RESET 0 L, RESET 1 L, STROBE 0 H, STROBE 1 H, and DATA OUT H. The logic also conditions the D-input
of the PAUSE flip-flop (E4 pin 12) to allow it to be set or reset. It also applies conditioning signals to the wiredAND that provides the clocking signal to the Slave Sync (SSYN) fhp~fl0p The PAUSE fllp-flop and the SSYN
flip-flop are part of the control logic.

The signals generated for each bus transaction are slmwn in Table. 3-6. The memory operational sequences are
discussedin subsequent paragraphs. To avoid wnfmmnin mterpretmg th@ transactions listedin Table 3-6, the
purpose of the PAUSE flip-flopis discussed briefly.

During DATIP, the PAUSE flip-flop is set during the read operatian which inhibits the restore (write) operation.

The DATIP must be followed by a DATO or DATOB on the same address. The DATO or DATOB that follows a

DATIP is shorter than a standard DATO or DATOB because the initial read operation is eliminated. In Table 3-6,
the suffix PAUSE H identi:fie:fl the DATO and DATOB
the suffix PAUSE L identifies the standard transactions;

transactions that must follow a DATIP.
3.3.8

Control Logic

ns are reThe control logic generates the precisely timed signals that initiate and stop the memory operatiothat
quested as a result of the decoding of the bus transaction. The heart of the control logicis the delay line timing
circuit. For better understanding, the timing am;mt slave sync circuit, pausfi/wme restart circuit, and strobe
generating circuit are described separately. Then, mch bus transaction is discussedin detafl The discussion is to

the detailed logic level but the signals are not traced through each component. The text is referenced to logic
drawing G110-0-1, sheet 2, and the timing diagrams in drawing MM 11-L-3.

3.3.8.1 Timing Circuit — The heart of the memory control logic is the timing circuit. When activated, it gener-

ates a series of precisely timed signals that control memory operation. The major component of the tjimirtg cir-

cuit is a delay line (DL1) with multiple 25-ns taps (drawing G110-0-1, sheet 2). The delay line outputs are gated
to produce the control s;gnals Figure 3-24 shows the timing of the delay line outputs and the timing for the
control signals obtained by gating these outputs. A brief statement of the function of each control mgnalis included. Absolute timin g is abtamed from the engme:ermg timing diagram (dmwmg MM11-L-3).

The discussion is referenced to Figure 3*24 and the control logic drawing G110-0-1.

When the system is turned on, the processor asserts BUS INIT L on the Umbus This mttmlwmg signalis sent to

pins 6 and 7 of bus receiver E7. It is inverted by E'? to produce a high whwhis sent to pins 9 and 10 of the mem-

ory select reset (MSEL RESET) gate E16. The output (pin 8) of E16is a low whichis used to clear (reset)

MSEL flxp~fl0p E2 via the 100-ns delay DL3. The autput of E7iis also inverted by E18 to pmvxde a low which

clears read/write (R/W) flip-flop E3. The output of E7is also inverted by E15 to provide a low which clears

PAUSE flip-flop E4. The low output of E15 is double inverted by two E38 gates to clear the DEL flip-flop E28.
The master places the address, mode control state, and data (if required) on the Unibus. The device address is
decoded and DSEL H is generated and sent to pin 13 of E1 which is one of four input signals (pins 10, 11, 12,

3-33

and 13). Pin 11 is high via thew()-autp}xt of MSEL flip-flop E2. SSYN flip-flop E4 is preset and it makes pin 10
of E1 high via its l1-output (pin 5). When the master asserts BUS MSYN L to bus receiver E23, pin 12 of El is
high also. The output of E1 (pin 8) goes low which is sent to pin 13 of ES, pins 4 and 5 of E14, and pin 1 of delay line DL2. E14 inverts the low from E1 to start the positive CLK 1 H pulse. DL2 provides a 30-ns delay for
the low signal from E1 which is inverted by E15 to start the positive CLK 2 H pulse. The output (pin 3) of DL2

is sent to the preset input (pin 4) of MSEL flip-flop E2. This low signal directly sets E2 and pin 6 goes low

which is fed back to pin 10 of E1 to disable it. The output (pin 8) of El is now high and this signal terminates
both clock pulses (CLK 1 H and CLK 2 H) via gates E14 and E15. These clock pulses are approximately 50-ns
wide.

Table 3-6

Generation of Memory Operating Signals
Signals Generated

Mode

Byte | Control | Stateof

Mode | Control
A00

=|lo|=|o|

~|m

|m|wm|=|=|a|al=

PAUSE | 8|8

~ | Flip-Flop | &2 | e | 5 | 33 | 3
| Co1 | CO0
==

§ =2

Operational Sequence
|

§
a

DATI

0 | Reset

XI1XIX1X

X | Read-restore.

DATIP

X | X|X|X

X | Read-pause. Restore inhibited by

JReset-Set|

PAUSE flip-flop.

DATO

0 | Reset

Clear-write.

0 | Set

Write. Must follow DATIP.

| 1 | Reset

PAUSE L

DATO

PAUSE H |

DATOB

X|X

Clear-write selected byte 0. Clear-

PAUSE L

DATOB

restore nonselected byte 1.

| Set

Write selected byte 0. Restore

PAUSE H

nonselected byte 1. Must follow
DATIP.

DATOB

Reset

PAUSE L
DATOB
PAUSE H

|
1

| Set

Clear-write selected byte 1. Clear-

restore nonselected byte O.
X

Write selected byte 1. Restore
nonselected byte 0. Must follow

DATIP.

Gate ES also inverts the low from E1 because pin 12 (WRITE RESTART L) of ES is high. The positive transi-

tion at the output (pin 11) of ES5 clocks delay (DEL) flip-flop E28 which sets it. Pin 5 of E28 is high and it is
‘connected to pins 1 and 2 of DL1 driver gate E34. The low from the output (pin 3) of E34 is the input to delay line DL1. This signal remains low for approximately 225 ns until DEL flip-flop E28is cleared by DELAY
FF RESET. This provides a negative pulse that propagates through the delay line and
can be pmked off at 25~ns
intervals.

3-34

100

BUS MSYN L -]

150

200

300

350

4?0

450ns

{&m’nmm MEMORY CYCLE, RESETS SSYN FF E4

“‘

[

DLY DELAY

250

DEL fg f?g*h E27-P6
RESET H

(2L+4H-READ H) E7-P3

’

{nwfim DELAY FF E28 BOTH IN READ AND WRITE.

USED ONLY DURING READ.

{cm‘rma SWITCH TIMING DURING READ AND DRIVER TIMING DURING WRITE,

‘

[

]

{g{"i@r L"; E14-P8 I

{ RESETS DATA FF's (BITS 0-15) AND STARTS STROBE DELAY.

(1 ffi%fi E14-P11 l

‘

fCONTROLS TDRH DURING READ AND TSSH DURING WRITE. CONTROLS

{ CURRENT GENERATOR AND STACK DISCHARGE TIMING. USED AS TINH DURING
-

MSEL RESET H

- (6H-8L) E26-P13

{mm AT END OF WRITE CYCLE IN ALL OTHER MODES.

‘

{nmwm R/W (READ/WRITE) FF E3 AT END OF READ CYCLE.

{mflmwm GIVE PROFER DELAY FROM

* .

STROBE DEL L E36-P1
,

STROBE H EI7-P3

~
|

LTRAILING EDGE SETS SSYN FF E4 DURING DAT} - DATIP MODES.

WRITE

CLK1 H

El4-P6

LOAD L

WRITE

UNLESS IN DATIP MODE.

r‘ CLOCKS DELAY FF E28 TO START WRITE TIMING CHAIN.

DOES
NOT OCCUR IN DATIP.

CLOCKS (R/W, AD, €O, CI FFI ON m*m {A1-A3 FFLON G231 1N ALL MODES.

IN DATO AND DATOB MODES, IT BECOMES LOADO, 1H.

CLOCKS MSEL FF E2 1N ALL MODES.

LeLocks ssvn eF

| pATO, DATO B

\DATI,

E34-P11

’

ouT

DMQMN : Eg z:
¥

LSTROBE DELAY.

SETS AT START OF CYCLE UNLESS PAUSE £F E4.P9 1S SET. AS IT RESETS, IT

CLK2 H EI3-P4
CLK SSYN H E4-P3

[ GENERATES NARROW WIDTH (35 s} STROBE PULSE FROM TRAILING EDGE OF

READ H ...J E3-P9

GATES SENSE AMPS TO DATA LATCHES DURING READ CYCLE.

STROBE 0s E28-P9

RESTART L E23-P3

LwaiTe cveLE.

RESETS MSEL (MEMORY SELECTED) FF EZ AT END OF READ CYCLE IN DATIP

R/W l}gfifi;g £26-P10

w GATED TOGETHER AS SHOWN BELDW

LINE TAP‘S

{mm FF E4 AS SHOWN.

DATIP

DATA FROM BUS TO DATA FF |0-15 IN DATO AND DATOB MODES.
{W
|

DATA FF 0-15 TO UNIBUS IN DATI AND DATIP
H STROBBUSESSSYNDATAL.FROM
[DATAHOUTBECOMES
WHICH KEEPS MSEL FF FROM SETTING.

\ | —y

{mm
4

TIMING CHAIN READ OR WRITE
r

;

N-1os

Figure 3-24

Basic Timing and Control Signal Functions

DL1 taps 2,4, 5, 6,7, 8, and 9 are used to generate control signals. Using Figure 3-24 as a guide, each control
signal discussed is related to the logic drawing (G110-0-1, sheet 2).

DELAY FF RESET
Tap 6L is inverted by E15 and sent to pins 3 and 5 of 3-input NAND gate E27; the third input (pin 4) is tap 8H.
The output (pin 6) of E27 is the signal that clears DEL flip-flop E28; however, it is ORed with INIT L in gate
E38 (pins 9 and 10) and inverted by E38 pin 11 so that either (6L - 8H) or BUS INIT L can produce DELAY FF

RESET which clears E28 via its clear input (pin 1). This signal is generated in both read and write operations.
RESET H

Tap 2L, tap 4H, and READ H are gated to generate RESET H which triggers the strobe delay circuit and generates RESET O L and RESET 1 L during the read operation only. Tap 4H and READ H (high during read operation) are ANDed at pins 10 and 9 of E17. The low output of E17 is ANDed with tap 2L in gate E7. The high
output (pin 3) is RESET H.

TWID H and TNAR H
The O-output of DEL flip-flop E28 is ORed with tap 5L and tap 7L in separate gates (E14) to produce TWID H

and TNAR H. Tap 5L is sent to pin 13 of E14; the other input to this gate (pin 12) is from the O-output of DEL
flip-flop E28. Tap 7L is sent to pin 10 of another E14 gate; pin 9 of this gate also is connected to the 0-output

of DEL flip-flop E28. These gates are 2-input NAND gates (type 7437); however, they are shown as lc)gicafly
equivalent negated-input OR gates because it is desired to have them asserted high (logical 1) when TWID H or

TNAR H is asserted.

At the start of a read or write cycle, just before E28 is set, TNAR and TWID are low because both inputs to each
gate are high. E28 is set and pins 23 and 9 of E14 go low; TNAR and TWID are both high, which starts the posi-

tive TNAR and TWID pulses simultaneously. When taps 5 and 7 go low (E28 is still set), TNAR and TWID remain high. At the end of the read or write cycle, E28 is cleared (taps 5 and 7 are still low) and TNAR and TWID
still remain high. When tap 5 is high again, TNAR goes low because both inputs (pins 12 and 13) of E14 are

high. This terminates the positive TNAR pulse. Approximately 50-ns later, tap 7 is high again and TWID goes
low which terminates the positive TWID pulse. To summarize TNAR H and

TWID H are started together by the

setting of DEL flip-flop E28 before taps 5 and 7 are low; they are not affected when taps 5 and 7 go low.

TNAR H and TWID H are terminated when taps 5 and 7 return high. The intervening clearing of E28 does not
affect TNAR H or TWID H.

TNAR H and TWID H provide various control functions related to the operation of the switches, drivers, current

generators, inhibit drivers, and stack discharge circuit. At this point, the discussion digresses to follow TNAR H
and TWID H through some additional logic to understand their functions. The logic is spread throughout several
engineering drawings. To simplify the discussion, all the logic is shown in Figure 3-25.

TWID H is ANDed with the O-output (pin 8) of R/W flip-flop E3 at pins 9 and 10 of gate E25. With TWID H
high, E25 is asserted only when E3 pin 8 is high; this occurs only during a write operation. The output (pin 8)

of E25 is inverted by E14 to produce TINH O H and TINH 1 H. The output of E14 is physically divided into

two paths: TINH O H activates the inhibit drivers for bits D(07:00) and TINH 1 H activates the inhibit drivers
for bits D{15:08). These signals do not leave the Control Module because the inhibit drivers are on this module

also.

‘

3-36

READ H

TWID H

W"‘
WRITE H

READ H|

READ L

pryrpufiirpnunyiibese
Sbrmi e g ""']
G110-0-1SH2

GENERATORS

ot |
,

w—-—-—-—ch
Cion

10 ALL SWITCH AND

DRIVER DECODERS

TO X-AND Y CURRENT

510

13}

P I
'

DISCHARGE
CIRCUIT |
1—e ON
TO STACK

O—=0QFF

N
s FOR
TO DECODING
LOGIC
+
)2
SWITCH DECODERS
TSS H ONLY

G231-0-1SH3 &8 4

G231-0-1 SH2

R/WFF

E3 PIN 8

O0— READ
1—=WRITE
[T

‘

‘
R

|
B

| |

BN
¥

TO DRIVER

DECODERS ONLY

TO INHIBIT DRIVERS

lmm BITS D<D7:00>

70 INHIBIT DRIVERS
FOR BITS D<15:08>

i ae

Figure 3-25 TWID H and TNAR H Control Logic

TWID H and TNAR H leave the Control Module (G110) and are sent to the Driver Module (G231). TWID H is

sent to pin 4 of E2R and TNAR H is sent to pin 2 of E2W. Gates E2 and E4 are marked W and R in Figure 3-25
to show their association with write or read operations. READ H is sent from the 1-output (pin 9) of R/W flip-

flop E3 on the Control Module to pin 9 of inverter E6 on the Driver Module. READ H is high during a read op-

eration and low during a write operation. Assume that a read operation is selected. READ H is high at pin 9 of

E6 and is sent to pin 5 of E2R to be ANDed with TWID H. This gate is asserted and its low output is sent to

pin 12 of negative-input NOR gate E2 which inverts it to pmdmfi TDR H. This signal is a decoding input for

the memory read/write drivers only. Gate E2W is not asserted because WRITE H, which is the inversion of
READ H, is low. Therefore, TWID H controls decoding signal TDR H dwing a read operation. During a write
c}pemuon READ H is low and WRITE H is high. TDR H

is asserted via the output of gate E2ZW using the AND-

ing of WRITE H and TNAR H. Decodmg signal TDR H is controlled by TNAR H during a write operation.
A similar logic network is used to control signal TSS H which enables six decoding signals that are used to con-

trol memory read/write switches only. Gates E4W, E4R, and E4 are used: TSSH s generated at the output (pin

3) of E4. During a read operation, TNAR H controls enabling signal TSS
H; TWID H controls TSS H during a
write operation. TWID H controls the mpemmon of the X- and Y-current gammmm During read and write operations, when TWID H is high, it is double inverted by two E6 inverters to turn on both current generators.

TWID H also controls the operation
of the stack discharge circuit. It is ANDed with WRITE H at pins 13 and 12
of NAND gate E4. The output (pin 11) of E4 is inverted by E6
to control the stack discharge circuit. This circuit is considered to be turned on when the output (pin 2) of E6 is high. This occurs during a write operation;

TWID H and WRITE H both high.

3-37

Although not part of the timing circuit, Figure 3-25 shows READ H inverted by two E6 inverters to become
READ L which is a decoding input to all type 8251 decoders for the memory switches and drivers. During a
read operation, READ H is high and READ L is low which selects only read switches and drivers; conversely,

READ L is high during a write operation which selects only write switches and drivers.

MSEL RESET

The memory select (MSEL) flip-flop E2 is cleared (reset) at the end of a read operation in DATIP mode and at

the end of a write operation in all other modes (DATI, DATO, and DATOB) by MSEL RESET. This signal is

generated at the output (pin 8) of gate E16. This gate is a type 74H53 2-2-2-3 input AND-OR-invert gate. Three
of its four AND inputs are used to facilitate the various methods used to generate MSEL RESET (Figure 3-26).

IN DATIP

R/W FF E3 PIN 9

1-0UTPUT

DL1 TAP 8B

DL1 TAP 6

012 |

, 0212

BUS INIT
L

+—O

l..,

E26

MSEL RESET L
TO CLEAR INPUT

OF MSEL FF E2

R/W FF E3 PIN 8

O-0QUTPUT

PAUSE FF E4 PIN 8
0-0UTPUT
-114%

Figure 3-26

Generation of MSEL RESET L

When the system is turned on, the processor asserts BUS INIT L on the Unibus. The output of bus receiver E7

is a high which is sent to pins 9 and 10 of E16 to generate MSEL RESET L at its output (pin 8). MSEL RESET L
is passed through a 100-ns delay line (DL3) to the clear input (pin 1) of MSEL flip-flop E2 which directly clears

(resets) it. All memory operations start with E2 cleared; however, it is set shortly (approximately 75 ns) after
the processor asserts BUS MSYN L. It remains set until it is cleared by one of the following operations.

In the DATIP mode, pin 12 of AND

gate E6 is high; in all other modes it is low, which disqualifies
E6. A read

operation is performed in DATIP so R/W flip-flop E3 is set. The 1-output of E3 is sent to pin 13 of E6. At this
time pin 13 is high and a high is asserted at the output (pin 11) of E6. This signal is sent to pin 13 of E16. This

AND input is qualified when pin 1 is also high. This occurs when DL1 tap 6 is high and DL1 tap 8 is low. Tap
6H is inverted by E35 and sent to pin 12 of E26. Tap 8L is sent directly to the other input (pin 11) and the
gate is asserted, which sends a high to pin 1 of E16. This asserts MSEL RESET L at the output (pin 8) of E16.

This low signal clears MSEL flip-flop E2 at the end of the read operation (timed by 6H and 8L).
In all other modes (DATI, DATO, and DATOB), MSEL RESET L is asserted at the end of the write operation.
Each of the three modes starts with a read operation (except DATO or DATOB following a DATIP). The R/W

flip-flop is set so its 0-output (pin 8) is low which disqualifies the 3-input (pins 4, 5, and 6) AND gate in E16.
Taps 6H and 8L cannot qualify this AND input nor can they qualify the other AND input (pins 1 and 13) be-

cause the memory is not in the DATIP mode. Therefore, the read operation is completed and MSEL RESET L

3-38

is not generated. The write operation is now started and the R/W flip-flop is cleared. This puts a high on input 5
of E16; input 6 is high because the PAUSE flip-flop is reset (pin 8 isa 1). Now, when tap 6 is high and tap 8 is

low, input 4 of E16 is high. This generates MSEL RESET L to clear MSEL flip-flop E2 at the end of the write
- operation. This circuit performs the function of a memory bus flip-flop.
R/W RESET

The timing for the generation of the signal
to clear (reset) R/W flip-flop E3 is obtained from taps 8 and 9 of DL1
(drawing G110-0-1, sheet 2). Tap 9 is sent directly to pin 8 of E26. Tap 8 is inverted by E35 and sent to pin 9

of E26. When tap 9 is low and tap 8 is high, E26
is asserted (output pin 10 is high). This signal is sometimes
called R/W RESET H. It is ANDed with READ H at pins 2 and 1 of NAND gate E18 to generate R/W RESET L.
When this signal is a low, it directly resets R/W flip-flop E3 via its clear input (pin 13). READ H is high when

the R/W flip-flop is set because it comes from the 1-output (pin 9). The remainder of the control signals shown
in Figure 3-24 are discussed in the circuit descriptions contained in Paragraph 3.3.8.2, Slave Synchronization

Circuit; Paragraph 3.3.8.3, Pause/Write Restart Circuit; and Paragraph 3.3.8.4, Strobe Generating Circuit.

3.3.8.2 Slave Synchronization (SSYN) Circuit — Slave synchronization (SSYN) is the slave device’s response to
the master: usually a response to master synchronization (MSYN). The master places address information, mode

control information, and data (if a DATO or DATOB is selected) on the Unibus. It then asserts MSYN only if

SSYN from the slave is cleared, which indicates that the slave can participate in a bus transaction. The slave asserts SSYN when it has data to send (DATI or DATIP) or when it has received data (DATO or DATOB). The
master receives SSYN in both cases and clears MSYN. When the slave receives the cleared MSYN it clears SSYN

which frees the bus. This brief statement of the SSYN/MSYN interaction
is necessary to understand the opera-

tion of the memory SSYN circuit. Details of the SSYN/MSYN interaction during all bus transactions can be
found in the PDP-11 Peripherals and Interfacing Handbook.

The SSYN circuit is shown in drawing G110-0-1, sheet 2; however, for clarity, only the SSYN circuit is shown in
Figure 3-27 along with appropriate timing diagrams.

During a DATI or DATIP transaction, BUS SSYN L is asserted by the memory when the data is placed on the
Unibus by the memory data register. During a DATO
or DATOB transaction, BUS SSYN L is asserted by the

memory when it takes in the data from the Unibus.

At the start of each transaction, the master first places the memory address (device and word) and mode control

information on the Unibus. (Data is included if the transaction is DATO or DATOB.) For a DATI or DATIP,
BUS COI1L is high at pin 10 of bus receiver E29. The output (pin 14)
of E29 is low and it is sent to the D-input

(pin 6) of CO1 latch E30 and to pin 5 of the E5 WRITE gate. BUS MSYN L has not been asserted yet so the
output (pin 13) of bus receiver E23 is low. This signal is sent to pin 2 of NOR gate E26; the other input (pin 3)
of this gate is always low because MSYNA L is normally not connected. The output (pin 1) of E26 is inverted

by E15 to produce SSYN RESET L which sets the SSYN flip-flop E4 via its preset input (pin 4). The O-output
(pin 6) is low and is sent to both inputs of bus driver E5. The output of this gate is the slave synchronization signal (BUS SSYN L) and, at this point, it is not asserted. Aslong as BUS MSYN L is not asserted, the SSYN flipflop is preset. Now, the master asserts BUS MSYN L which disables the preset signal to the SSYN flip-flop

(SSYN RESET L is high). Clock signal CLK 1 His generated and clocks CO1 latch E30. The latch is reset and
its O-output (pin 11) is a high which is sent to pin 10 of the ES READ gate. The wired-AND output is CLK SSYN
which is high. It remains high as long as both ES NAND gate outputs are high; this occurs when at least one input

of each gate is low. The output of E5 WRITE remains high because input pm 5 is held low by the output of COl1
receiver E29. The output of this gate is not changed when the CLK 2 H pulse appears at pin 4. The output of
E5 READ remains high until STROBE H goes high, at which point its output goes low.

- 3-39

When STROBE H goes low again, the wired-AND output is high again.

This positive transition clocks the

SSYN flip-flop which now resets because its D-input is tied to ground (low).

The O-output (pin 6) of the

SSYN flip-flop is high which asserts BUS SSYN L at the output (pin 3) of bus driver 5.

The master receives

the asserted BUS SSYN L signal and clears BUS MSYN L. The memory receives the cleared BUS MSYN Lat bus
receiver E23 and generates SSYN RESET L via gates E26 and E15 to set the SSYN flip-flop. The memory is
now ready for the next transaction.

For a DATO or DATOB, the sequence is the same except that BUS CO1 L is low at pin 10 of bus receiver E29.
This conditions the wired-AND so that the output of ES READ remains a 1. In this case, the CLK 2 H pulse generates the CLK SSYN pulse that clocks the SSYN flip-flop via ES WRITE.

3.3.8.3

Pause/Write Restart Circuit — The PAUSE flip-flop (E4) is used to inhibit the restore (write) operation

during a DATIP. This transaction is used to advantage when it is not necessary to restore the data after reading
because the location is to have new data written into it. Eliminating the restore operation decreases the memory
cycle time by approximately 50 percent. A DATIP must always be followed by a DATO or DATOB. In this
case, the DATO or DATOB is shortened by eliminating the normal clear (read) operation that is performed prior

to the write operation. The location has been cleared previously by the DATIP so the DATO or DATOB performs only the write operation.

The pause/write restart circuit is shown in drawing G110-0-1, sheet 2; however, for clarity, only the pause/write
restart circuit is shown in Figure 3-28.

At the start of all bus transactions, the PAUSE flip-flop is reset and it remains in this state during the whole trans‘action except for a DATIP during which it is set after the read operation. The PAUSE flip-flop is clocked by the

O-output (pin 6) of the SSYN flip-flop when it is reset. The state (set or reset) of the PAUSE flip-flop is determined by its D-input (pin 12): D is high to set and D is low to reset. The D-input state is controlled by the Unibus mode control bits CO1 and COOQ; only the mode control representing a DATIP provides a high to the D-input

of the PAUSE flip-flop. During a DATIP, CO1 is high and COO is low at bus receivers E29 pin 10 and E29 pin 7.
These signals are inverted by the receivers and applied to the D-inputs of the CO1 and COO latches: CO00 latch
E30 pin 3 is high and CO1 latch E30 pin 6 is low. When the latches are clocked by CLK 1 H, latch CO1 is reset

and COO is set. This puts a low on each input of negative input AND gate E26 which generates a high output.

This is the D-input to the PAUSE flip-flop. The PAUSE flip-flop is now conditioned to set when it is clocked.
Going back to the start of the DATIP, the PAUSE flip-flop is reset. Its D-input is conditioned (D is high) but it
has not been clocked so its O-output (pin 8) is high. This output goes to the D-input of the read/write flip-flop

(R/W E3). It is clocked early in the sequence by CLK 1 H so it is set, which permits a read operation. The
O-output (pin 8) of the R/W flip-flop is low and is sent to pin 4 of E17. The other input (pin 5) of E17 comes
from the O-output (pin 8) of the PAUSE flip-flop
and it is a high at this time. The output of E17 is a high and is
inverted by E15 which puts a low on the clear input of the write restart flip-flop (WR RS E2). The output of

E15 also goes to input 2 of E25. The WR RS flip-flop is cleared (reset) and its O-output (pin 8) is a high which is
sent to the other input (pin 1) of E25. The output of E25 is the WRITE RESTART L signal which is produced

to trigger the timing circuit and produce a write operation. It is high now, which is proper, because a read operation is being performed.

At the end of the read operation, the SSYN flip-flop is clocked, which resets it. The positive tranSitiOn at its
O-output (pin 6) clocks the PAUSE flip-flop which sets
it and puts a low on pin 5 of E17. The timing circuit
clears (resets) the R/W flip-flop which puts a high on pin 4 of E17. The output of E17 remains high which inhibits the WRITE RESTART L signal and prevents the initiation of a write operation.

3-40

BUS MSYN L

CLK1 H E14 PIN 6

CO1 LATCH
O-OUTPUT E30 PIN 11,

STROBE H

E17 PIN 3

CLOCK SSYN ES
PINS 6/8 WIRED-AND

SSYN FF
O0-QUTPUT E4 PING

SSYN RESET L
BUS SSYN L ES PIN 3

CLKZ2H

11-1140

SRE
TO E1 PIN 10

WRITE

OF PAUSE FF

SSYN

{:{}1
.

3 CLK O

STROBE H—
o]

€5

+ 3V

During DATI and DATIP

WIRED-AND L _CLR

saFtEJl{}

LATCH

CLKt H—CLK

}

fTimifig Diagram for SSYN Circuit

. TO CLOCK INPUT

‘r

-2
1|

BUS SSYN L

b3
+5V
11-1139

Slave Synchronization (SSYN) Circuit

BUS MSYN L

CO1 RECEIVER
E29 PIN 14

CLK2 H E15 PIN1

CLOCK SSYN ES
PINS 6/8 WIRED-AND

SSYN FF

O-OUTPUT E4 PIN &

BUS SSYN L
ES5 PIN 3
11-1141

Timing Diagram for SSYN Circuit
During DATO and DATOB

Figure 3-27

Slave Synchronization (SSYN) Circuit
and Timing Diagrams

3-41

—WRITE RESTART L

CLK1H

BUS CO1 L
9 | £29
ALWAYS O-8—f

1
£30
co1

. LATCH

READ=SET=0

WRITE=RESET=1

INIT L

SSYN RESET L
2

R/W RESET L

11-1144

Figure 3-28

Pause/Write Restart Circuit

For any other transaction (DATI, DATO, or DATOB) the PAUSE flip-flop is not set when it is clocked because

its D-input is low. It remains reset which keeps a high on pin 5 of E17. When the R/W flip-flop is cleared it puts
a high on pin 4 of E17. Now, the output of E17 is a low which is inverted by E15 and sent to pin 2 of E25. The

WR RS flip-flop is reset so pin 1 of E25 is also high. The output (pin 3) of E25 goes low which generates
WRITE RESTART L. This starts the formation of a low WRITE RESTART pulse. This output is inverted by
E25 pin 6 and clocks the WR RS flip-flop which sets it because its input is connected to +3V. Pin 8 of the
WR RS now goes low and is fed to pin 1 of E25. This makes the output of E25 high again which terminates the
low WRITE RESTART L pulse. This pulse triggers the timing circuit and initiates a write operation.

For a DATO or DATOB following a DATIP, the PAUSE flip-flop is reset by the SSYN flip-flop because the
DATO or DATOB transaction started with the PAUSE flip-flop set previously by the DATIP.

3.3.8.4 Strobe Generating Circuit — The strobe gengmting circuit produces a narrow positive pulse (’STROBE H)

during the read operation to enable the STROBE 0 H and STROBE 1 H

signals for the sense amplifiers.

The strobe generating circuit is shown in drawing G110-0-1, sheet 2; however, for clarity, only the strobe generating circuit is shown in Figure 3-29 along with an appropriate timing dia

During the read operation, the timing circuit generates RESET H which is a positive pulse. It is sent to pin 5 of
the strobe delay one-shot (ST DEL E36). This type 74121 one-shot provides complementary outputs but only
the Q (negative pulse) output (pin 1) is used. Pins 3 and 4 of the ST DEL one-shot are connected to ground so
that only a positive-going edge at pin 5 triggers it.

3-43

STROBE
0S

E28

”LgLR

it3

+3V

STROBE H
E36

RESET H

ST DEL|

lfi :

P
TRIGGERS ONLY
ON POSITIVE
TRANSITION

NEGATIVE PULSE
WHEN TRIGGERED

l-1142

RESET H

E36 PIN 5
_—TIMES OUT

STROBE DELAY

ONE-SHOT
E36 PIN 1

STROBE H

E17 PIN 3

)
~—PRESET

STROBE 0S FF
E28 PIN 9

CLOCKED TO RESET

" STATE

Li-t143

Figure 3-29

Strobe Generating Circuit and Timing Diagram

Prior to receiving the triggering signal (RESET H), the strobe generating circuit is in the quiescent state. The

STROBE O0S flip-flop E28 is in the reset state. (When the memory is powered up, E28 is driven to the reset state
by E36 if it did not come up reset mndmmly ) The l-output (pin 9) of E28 is low and is sent to pin 13 of E17.

The ST DEL one-shotis inhibited, so its Q output (pin 1)is a high whichis sent to pin 12 of E17. The output

(pin 11) of E17is high andis inverted by the next E17 gate (pin 3). Thisis the STROBE H signal and it is low
at this time.
The timing circuit generates a positive RESET H pulse that is sent to pin 5 of E36. The positive edge of RESET H

triggers E36 and its 6 output (pin 1) goes to low. This is the start of a single negative pulse whose duration is determined by an external RC circuit connected to pins 10 and 11 of E36. The output of E36 directly sets

STROBE 0S flip-flop E28 via its preset input (pin 10). The 1-output (pin 9) of E28 goes high and is sent to pin
13 of E17. The other input to this gate (pin 12) is now low. E17 pin 11 is high and is inverted so E17 pin 3 is
still low (no strobe pulse yet). When E36 times out, its output (pin 1) goes high again. Pins 12 and 13 of E17 are
now both high and the output (pin 11) of E17 is low. This signal is inverted and E17 pin 3 is high. This is the

beginning of the STROBE H pulse. The positive transition at E17 pin 3 also clocks fl1p~fl<3p E28. It is reset because its D-mputis connected to ground (low). Pin 9 of E28is now low. It is fed baak to pin 13 of E17 which

makes E17 pin 3 low again. This terminates the positive STROBE H pulse. The circuit is back to its quiescent
state where it remains until another RESET H pulse triggers ST DEL one-shot E36.

3-44

3.3.8.5 Data In (DATI) Operation — The discussion of the DATI operation, as well as the DATIP, DATO, and
DATOB operation, is descriptive. Signals are not traced through circuit components; rather, various events are

integrated to describe a complete memory operating cycle. All the circuits involved have been discussed in de-

tail in the preceding paragraphs of this chapter. Refer to engineering logic drawings G110-0-1, sheets 2, 3, and 4;
G231-0-1, sheets 2, 3, and 4; MM11-L3 (timing dxagram), and Figure 3-30, which is a flow chart for memory operation.

In a DATI operation, the master requests that a selected memory location be read and the information trans-

ferred to the master via the Unibus. The readout is de&tructive because the read operation forces all cores in the
selected location to 0. However, during readout, the informationis temporarily storedin the memory data reg~ister (MDR) andis automatically resmmfi to the aelected location by a write opemtmn that immediately follows
|

the read operation.

At the start of the DATI, the MSEL, DEL, R/W, and PAUSE flip-flops are reset, and SSYN flxp-flcapis set. The
address lines and mode control lines (CO1 and C0Q)are decoded. The master asserts BUS MSYN L and the cycle
begins. CLK 1 H is generated, the DEL flip-flopis set, and the R/W flip-flop m set. Setting the DEL flip-flop
~ initiates the timing chain via delay line DL1. The timing chain generates TWID H and TNAR H. CLK 2 H is

generated at the same time and it presets the MSEL flip-flop, which prevents the start of another cycle until it is
reset. Signal READ H from the R/W flm—flmp and signals TNAR H and TWID H go to the driver module to select

the appropriate read drivers and switches, turn on the X- and Y-current gemmmm, and control the stack dis-

charge circuit. As a result of these signals, the X- and Ywha}f currents are¢d:lrecwd to the selected memory loca-

tion and all 16 cores (one per bit plane) are set to 0. J ust prior to this event, the timing chain generates RESET

0 L and RESET 1 L which clear the memory data register. The timing chain generates STROBE H which asserts
STROBE 0 H and STROBE 1 H which are sent to the sense amplifiers. The strobe pulses are timed to arrive at
the same time as the pulses induced in the sense/inhibit line. If a selected core was a 1, a pulse is induced in the
sense/inhibit line that exceeds the sense amplifier threshold and it produces an amplified positive pulse. This

output is inverted, presets its associated MDR flip-flop, and a 1 is stored in the flip-flop. STROBE H also clocks

the SSYN flip-flop which resets. The SSYN flip-flop output asserts DATA OUT H and BUS SSYN L. Signal
DATA OUT H gates the output of the memory data register to the Unibus. BUS SSYN L is a Unibus signal that
informs the master that the memory has read the selected location and placed the data on the Unibus. The mas-

ter takes the data and clears BUS MSYN L which generates. SSYN RESET L to set the SSYN flip-flop. BUS

SSYN L is cleared to indicate that the Unibusis free; however, another bus transaction cannot be initiated even

if the master asserts BUS MSYN L because of the lockout feature of the MSEL flip-flop, which is zstill‘ set. Prior
to the assertion of BUS SSYN L, the timing chain gemmws DELA‘{ FF RESET L which resets the DEL flipflop and allows the TNAR H and TWID H pulsm to terminate as a function of taps 5 and 7 of the d&lay line.
The timing chain also generates R/W RESET L which resets the R/W flxpwflop

The memory now enters the write (or restore) cycle. With the R/W fixwflwp and PAUSE fllp—fl@p both reset, the
pause/write restart circuit generates WRITE RESTART L wlfnah mmatefi moth&r mmmg cymfi by s&ttmg tha
|

DEL flip-flop.

The timing chain generates TWID H and TNAR H. These signals plus a low READ H signal from the R[W flip-

flop go to the driver module to select the appropriate write drivers and switches, turn on the X- and Y-current
generators, and control the stack discharge circuit. In addition, TWID H and an output from the R/W flip-flop
are ANDed to generate TINH O H and TINH 1 H. These signals control the operation of the inhibit drivers.
TINH O H and TINH 1 H are ANDed with the outputs of the MDR flip-flops. If a 1 is stored in the MDR flipflop, the associated inhibit driver is not turned on and a 1 is written into this bit of the selected memory location. If a O is stored in the MDR flip-flop, the associated inhibit driver is turned on and produces a current that
opposes the Y-line current and prevents a 1 from being written into this bit. The timing chain generates

3-45

AMOW3W S| 1ON

LIVM TINN

I
z»mfiTAWIL*
37T2AD

1383y sng

S3A

3-46

i~ LP

31L3I8E3my 37T30SAWD4 s1n383NyASsWneH
4

3ATH0OAWDIW%)A(QSYU3OIGYH

3NIL

37040

138 38Nvd 4 1V 138341YviS3yM/¥13044 4
13V8O3Ny31430SWQv43y ANV LHVIS JLI4M
sNSAnSs NASW7 HLHIM
404suQSOlvad
(AHOW3W
H=)3AIQTV03AYD 804ANOW3WLX3NAQV3Y

NAS 1 1V ON3

{

LY3SSVY SN8
131V3LIsHON33My 0407340ISW 4 - s1383yNnAsS NA7TSsSWHNL8IHM

%WO¥d0070 SN8Ni Viva

313s8nvMd7yd037144T-3dI0N443 NAS 711V A1J @

%WOoudd2010 NSNgI JOHLNOD

A1HOONWO3NNOd1MS3Y

>
=
7
1
L
V
a
M
m
d
i
l
v
a
3
0
0
W
~
L
1
M
3
S
Y
S
N
1
l
¥
3
s
s
v
S
N
E
:
N
A
S
7
1
L
Y
0
2M
ONVS3¥AQV T 1VwaOoNm3zf4lw0fiaa NASS7THLIM
ANVLHVISQv3y 31040(sU0062)
Ind1g(Qf-€MO[WBYD10]AIOWIuoneradQ
Sng NASW T

1¥X034N

DELAY FF RESET L which resets the DEL flip-flop and allows TNAR H, TWID H, and the inhibit pulses

(TINH O H and TINH 1 H) to terminate. The timing chain also generates MSEL RESET L which resets the
MSEL flip-flop.

3.3.8.6 Data In Pause (DATIP) Operation— In a DATIP operation, the master requests that a selected memory
location be read and the information transferred to the master via the Unibus. However, unlike the DATI, this

information is not to be restored after reading; this location is to have new information written into it. The
DATIP performs only a read operation, the write operanon is mhibxted A
DATIP must always be followed by

a write transaction (either DATO or DATOB).

The read operation of a DATIPis 1demwal to that of a DATI (Pm"agmph 3.3.8.5) until the time the SSYN flipflopis reset (clocked by STROBE H). At thm time, the SSYN flip-flop mutput clmks the PAUSE fllp-flz)p which
sets it because its D-inputis a 1 (only dumng DATIP due to the state of mode control bits CO1 and C00). The
timing chain generates R/W RESET L which resets the R/W flip-flop. The outputs of the PAUSE flip-flop and

R/W flip-flop prevent the pause/write restart circuit from generating WRITE RESTART L. With this signal inhibited, the write operation is not produced. The timing chain generates DELAY FF RESET L which resets the

DEL flip-flop and terminates TNAR H and TWID H. The timing chain also generates MSEL RESET L which resets the MSEL flip-flop. The memory is now ready to accept another request from the master. The next cycle

is required to be a DATO or DATOB. Normally, a DATO or DATOB starts with a read operation to set all selected cores to O (clear) before writing new information into them. A DATO or DATOB following a DATIP has
this initial clear operation eliminated because the cores have been cleared by the previous DATIP operation.

The DATO or DATOB following a DATIP starts when the master asserts BUS MSYN L. Pulse CLK 1 is generated but it does not set the R/W flip-flop because the PAUSE flip-flop is set. The master places the information
to be written on the Unibus where it is picked off by bus receivers and sent to the D-input of the memory ad-

dress register flip-flops. Decoding the mode control bits (CO1 and C00) for a DATO or DATOB generates
LOAD 0 H and LOAD 1 H which clock the MDR flip-flops. The outputs of the MDR flip-flops are gated with
TINH 0 H and TINH 1 H to control the associated inhibit drivers to write 1s or Os into the selected memory lo-

cation. As in the write operation of a DATI, the timing chain generates TWID H and TNAR H which select the
appropriate write drivers and switches, turn on the XA and Y-current gen’eratms@ :md control the stack discharge

circuit. They also generate inhibit driver wntml fignals TINH 0 H and TINH 1 H. Signal CLK 2 H clocks the
SSYN flip-flop (resets it) which asserts BUS SSYNL to tell the master that the data has befm taken from the
Unibus. When the master clears BUS MSYN, the SSYN fl1p~flopis mset whmhin turn resets the PAUSE flip-

flop. At the end of the write operation, the nmmg chain genemms DELAY FF RESET L and MSEL RESET L
to restore the control sxmal’s to their c»rxgmal states.

3.3.8.7 Data Out (DATO) Operation — In a DA’I’O operation, the maflter sends a word of 16 bits to be written
into the selected memory location. The transaction starts with a read (clear) cspfzmnmn to set the selected cores
to 0 before writing new data into them. The standard DATO consists of a read operation followed by a write
operation. (As described in Paragraph 3.3.8.6, a DATO following a DATIP does not perform the read operation.)

The read operation of a DATO is similar to a read operation of a DATI except that no RESETOL, RESET 1 L,

STROBE 0 H, and STROBE 1 H pulses are generated. The memory data register is not cleared and the sense amplifiers are not strobed. This read operation is required only to clear the memory location by setting all the se-

lected cores to 0; it is not necessary to readout and store the information in the MDR.

The information on the Unibus data lines is sent to the inputs of the MDR flip-flops. Decoding the mode control bits (CO1 and C0O0) generates LOAD O H and LOAD 1 H which clock the MDR flip-flops. The MDR outputs

(16 bits) are gated with TINH O H and TINH 1 H to control the associated inhibit drivers. The timing chain

3-47

generates the other control signals that provide the selection of the appropriate write drivers and switches and a
write operation is initiated. This write operation is the same as that described in Paragraph 3.3.8.6 for a DATO
’\
fi

following a DATIP.

3.3.8.8 Data Out Byte (DATOB) Operation — In a DATOB operation, the master sends a byte (8 bits) to be

written into the selected memory location. A high byte (bits D{15:08)) or a low byte (bits D{07:00)) can be selected. Byte selection is made by the state of address bit A0O.

A DATOB is the é;:ame as a DATO except that the selected and non-selected bits are handled differently.
Assume that the low byte (bits D{07:00)) is selected (A0O = 0). Neither RESET O L or STROBE O H are generated for the selected byte because new data is to be written into bits D{07:00 (low byte). LOADO H is generated so that the data on Unibus bits D{07:00) can be written “inm the selected byte location.

The non-selected byte (bits D(15:08)) is to be restored so RESET 1 L and STROBE 1 H are generated. These
signals strobe the byte into the MDR for restoration during the write operation. Restoration is necessary because this byte does not receive new data. LOAD 1 H is not generated; therefore, any data on Unibus bits
|

D{(15:08) has no effect on the non-selected byte.

When the DATOB is complete, the selected byte contains new data and the non-selected byte remains unchanged.

A DATOB c)pemt:ion following a DATIP is the same, except that the read portion is eliminated.
3.4

MAINTENANCE

This section discusses the preventive and corrective maintenance procedures that apply to the MM11-L memories. A major point in the maintenance philosophy of this manual is that the user understand the normal opera3.3 provides this understanding. This knowledge, plus the maintenance information of the memory. Paragraph
tion, aids the user in isolating and correcting malfunctions.

For maintenance purposes, the backplane unit is wired in such a way that an MM 11-L can be plugged into, and

run, in any one of three groups of module slots. These groups consist of slots 1, 2, and 3; slots 4, 5, and 6; or
slots 7, 8, and 9. Therefore, an MM1 1-L, which consists of the G110, G231, and H214 modules, can be plugged

into any of the three groups of slots described. The individual MM 11-L modules work in any slot in either of the
three slot groups. This allows a module to be plugged into slot 1 for easy troubleshooting or adjustment of the
strobe. As an example, suppose it is necessary to adjust the strobe on the MM11-L plugged into slots 7, 8, and 9.

Slot 7 contains the H214, slot 8 contains the G231, and slot 9 contains the G110. The G110 module contains

the test point and strobe adjustment; therefore, it is necessary to move the G110 to slot 1 for easy access from
the top of the ME11-L unit. To test the G110 in slot 1, the entire MM 11-L must be moved from slots 7, 8, and

9 toslots 1, 2, and 3. Any MM11-L in slots 1, 2, and 3 is plugged into t}ie slot group vacated.

With the modules in the proper slots (G110 in slot 1 and the H214 and G231 in opposite slots 2 or 3), the G110

is easily accessed from the top of the ME11-L unit and any adjustment can be made easily. When maintenance
is complete, be sure each MM11-L has the G231 module between the G110 and H214 modules. This is the rec-

ommended operating configuration.

3-48

Preventive Maintenance

3.4.1

Preventive maintenance consists of specific tasks performed at intervals to detect conditions that could lead to
subsequent performance deterioration or malfunction. The following tasks are considered preventive maintenance items:

a.
b.

Visual inspection of modules for broken wires, connectors, or other obvious defects
+5V and - 15V checks; both must be within +3 percent

X-and Y-current generator check (Paragraph 3.4.1.2)

Two pieces of test equipment are recommended for checking and troubleshooting the memory. They are:
Tektronix 453 Dual Trace Oscilloscope or equivalent, and Honeywell 33R Digital Voltmeter or equivalent with
0.5 percent accuracy.

3.4.1.1

Initial Procedures — Before attempting to check, adjust, or troubleshoot the memory, perform the fol-

lowing steps.

NOTE

All tests and adjustments must be performed in an ambi-

ent temperature range of 20°C to 30°C (68°F to 86°F).
1.

Verify that all modules are properly and securely installed.
CAUTION

Make sure all power is off before installing or removing
modules.

Visually check modules and backplane for broken wires, connectors, or other obvious defects.
Verify that power buses are not shorted together.

Turn on primary power and check that both the - 15V and +5V power are present and within tolerances
(£3 percent).

Start the system. The memory should operate without errors. If not, check the output of the current
generator (Paragraph 3.4.1.2). If the memory still does not operate properly, a malfunction has occurred. Proceed with corrective maintenance (Paragraph 3.4.2).

3.4.1.2 Checking Output of Current Generators — The amplitude of the current pulse from each current generator (X and Y) is factory set at 410 £5 mA. It is not adjustable in the field.

The X- and Y-current generators are located on the Driver Module (G231). Each output has a current loop on
its output line for attaching a test probe. Loop J5 is for the Y-generator and loop J6 is for the X-generator

(drawing G231-0-1, sheet 2). The amplitude of each read current pulse should be 410 £5 mA. At the time of
measurement, - 15V and +5V power must be within the specified tolerance of +3 percent.
3.4.2

Corrective Maintenance

This paragraph includes the strobe delay adjustment which is a specific corrective maintenance procedure. It

also includes aids for performing corrective maintenance: a troubleshooting chart, and waveforms for the drive
circuits and the sense/inhibit circuits.

3-49

3.4.2.1

Strobe Delay Check and Adjustment

CAUTION
Strobe delay is factory adjusted and should be adjusted
only when one of the three modules is replaced. It is a
critical adjustment and must be done carefully.
The strobe must be set while cycling the Worst Case Noise Test (MAINDEC-11-D1GA). The proper setting is

mid-way between the two end points where the memory starts to error as strobe time is moved from earliest to
latest. As the strobe time is varied, allow adequate time to cycle completely through the Worst Case Noise Test
at each strobe position. Figure 3-31 shows the strobe pulse waveform and the READ pulse waveform and the
points at which they are picked off for display. The potentiometer (R120) for adjusting the strobe is on the

G110 module next to the large delay line (DL1) and is accessible without putting the module on an extender.

READ H

G110 OR G231
PIN

Cu2

je———— T

STROBE ———=

STROBE H
G110 TEST POINT 1
INPUT TO E5 PIN 9
11-1138

Figure 3-31

3.4.2.2

Strobe Pulse Waveform

Corrective Maintenance Aids — Figure 3-32 is a troubleshooting chart arranged as a 2-axis grid that iden-

tifies faults versus cause location. Figure 3-33 illustrates the sense/inhibit waveforms and Figure 3-34 illustrates
the drive waveforms. Both figures include schematics to indicate the points in the circuit where the waveforms
occur. In addition to nominal waveforms, dotted lines are used to indicate waveforms that appear if specific
components are faulty.

3.4.3

Programming Tests

Certain DEC programs can be used to test various memory operations as an aid to troubleshooting. The purpose

of each of these memory-related test programs, as well as the program abstract, is given in the following paragraphs. Each program contains instructions for its use.

3.4.3.1

Address Test Up (MAINDEC-11-D1A) — The purpose of the Address Test Up program is to demon-

strate that the selected memory area is capable of basic read and write operations when address propagation is
upward through memory.

This test program writes the address of each memory location (within the test limits) into itself and then increments through memory until the address corresponding to the high limit is reached. After this location has been
written, the memory enters the read cycle. The read cycle starts with the high limit location and reads and compares each word location, decrementing down to the low limit location. The program halts on an error.

This program checks that all addresses are selectable and can also be used to isolate bad switches, wiring errors,
or address selection errors. It will also find double selection errors when two bus addresses select the same core
address.

3-50

Loc.

Possible

Circuit

.§s

@
£ )
&
|ddle |

Seleg=|
& | o&
§S§>_<§;

> |8S El=d]|
3|S5 H| A
(521283
“w 1&slas]| =

Flur
Symptom

Memory Does Not

Respond to MSYNL

e | o

§|%l=E
=

&S|o & %
=
@

|5A

|5o
|2e

51
o

2|
o

é’* =

s5ls

|ES

g2
518

|BE8|s5|
Eé*“

o
la|Z|<|2|52gs|SEl2]|
T
21 o9 d| o

|3-

|E=

|5a |5Z |38|52(2c
la=|l@ad|ds8] 2
a
X

2|
Q

2|22
£
| E 8
2|58
Sl aE

(%)

S1alsg|g.

ol
)

RSe
A

B
2B

%
3
S |8 gE
|2|3|2|82
)
A | A |A

~§§ .

g 5

| €|

_zl2 | §=
s gla.l|

|8&

o
-

z | S

2|
4

o |~ &

>8lxs|
8|S =3 w 3 2 B4;| 2%
o9 o
»
, &
E
1R3l38|2|2|8|g|8|g|B|x|«5|
X g|n O | X
>
>
<
<
=
Al

=
&g

2n
=
|3]|z|¢
@
+
:
X

Memory Hangs Bus

DATO Fails

C00-

DATIP Fails

€00

Co1

Many Bits Fail

Picks Bits

Drops Bits

FA2

Byte Failures

4 Bits Fail

2 Bits Fail
1 Bit Fails

Fails All Addresses

Al—A3 Common
A4—-A6 Common

A7-A9 Common
Al10—-A13 Common

READ Waveforms
- Wrong

WRITE Waveforms
Wrong

No Inhibit

Location

C = G110 Sense Control

X = Indicates Circuit Not Operable

S = Stack

Lo = Measured Parameter Too Low or Early

D= G231 Driver

Hi = Measured Parameter Too High or Late

Figure 3-32 Troubleshooting Chart

|
G110 MODULE

IP-FLO

TINH H B —

7437

BASE DRIVER

MEMORY

|
I
%

FROM MDA

‘G??G MODULE

’

'62?4 MODULE

‘

TERMINATION

’

*"'—1_

; d

! o
|58

oK CORE MAT

;

WINDING

Gosecores
sensesinn

SENSE AMP

P A

INHIBIT DRIVER

—————————— T
15Y

——

REC.

DATAIN

LOAD
A

RESET L

ol—TO 7437 INHIBIT
I

" BASE DRIVER

7anor o2
__|orivER

MOR FLIP-FLOP

e e e e T T 2

OPEN
INR R S

1 sv
;

;

+50mV

_L-Q

Lono

{}R TN

evy

1
J

}

I
-5V

;

‘T $

|
|
|

| sa

WRITE

READ

- somv

DATOUT H

{

~ UNIBUS

19-118¢

‘ !

STROBE

l DATA ON BUS FROM OTHER UNITS WILL ALSO APPEAR HERE

ti-1152

Figure 3-33 MM1 1-L Sense/Inhibit Waveforms

3-53

+5V
°

TfiiD H

216.90

—\

WRITE

+5V

OPEN LINE

~___OR RPDR ;

—15V

-15V Y~ SHORTED LINE

/
-20V

OPEN LINE

+5V

s =

< “OR WPS f

|
INOP RNS

OPEN LINE

<_OR WNDR |

-25V
|

LOOP
URRENT
CURRE

O
+5v

+5V

GND

%, ¢ > %

-15

CURRENT GENERATOR

) 67>

GND

/-———\4,?\\1 OR 450::3&/———

READ

(E— TO DECODER
®

INOP RPDR

*—AAA—o0 —{5V
A 2

INOP WNDR __ _

MEMORY
CORES

TopEN LINE y

POV

T ey

----Dotted line show possible

failure waveforms.

1i-1154

¥TDR H—

8251

DECODER

+5V

reap L— (SN
ax —| ouTPUT |
AX — SHOWN)

v Ve
'

+5V

15|

NEG

D
DRIVER

READ
SWITCH

;";5‘13

DECODER
|

STACK

DISCHARGE

519

‘%Indicctes module conn pin.
¥ TDR H and NAND

gate are used on

driver decoders only.

(Vg— Vp) follows waveform
shown

=15V

below

+1V

(VB-VA}

~
Ti=1153

Figure 3-34 Drive Waveforms

3-55

3.4.3.2 Address Test Down (MAINDEC-11-D1B) — The purpose of the Address Test Down program is to demonstrate that the selected memory area is capable of basic read and write operations when address propagation is
downward through memory. It is a companion test to the Address Test Up program (Paragraph 3.4.3.1).
This test program writes the address of each location into itself, downward through memory. After writing
down, the program reads and checks back up through the memory test area. The program halts on an error.
The Address Test Down program resides in the high portion of core memory. It does not check memory below
address 100, as these locations are reserved for trap and vector locations. The program verifies that all modules
can perform their basic functions, checks that all addresses are selectable, and can also be used to isolate faulty
switches, wiring errors, or address selection errors.

3.4.3.3 No Dual Address Test (MAINDEC-11-D1C) — The purpose of the No Dual Address Test program is to
check the unique selection of each memory address tested.

This test is divided into two parts. The first portion of the test fills the test field with 1s and writes Os into the
first test location. This is followed by a read check from this location. The program then checks each field location to ensure that there are no variations from the 1s configuration. Upon completion of this test, the test location pointer is incremented. The next location is then write-read exercised with Os and the test field rechecked
for any change in content. When the selected test field has been tested in this mode, the program sets a flag and

the second portion of the test is begun. The program fills the test field with Os and the field is then tested with a
write-read exercised with 1s.

This program checks for faulty switches or wiring errors, checks the complete address selection scheme, and
checks all 16 bits in the data field for 1s and Os operation.

3.4.3.4 Basic Memory Patterns Test (MAINDEC-11-D1D) — The Basic Memory Patterns Test program has two
main purposes:

a.
b.

Verify that the selected memory test field is capable of writing and reading fixed data patterns.

Verify that the memory plane is properly strung.

This test program writes a specific pattern throughout a given memory zone, then reads the pattern back and

compares it with the original for correctness. If the pattern read fails to compare correctly with the original, the
program initiates a call to the error subroutine. After completely checking the pattern, the program continues
on to the next pattern test.

3.4.3.5 Worst Case Noise Test (MAINDEC-11-D1G) — The purpose of the Worst Case Noise Test program is to
generate the maximum possible amount of plane noise during execution of memory reference instructions to
check system operation under worst case conditions.

This test program is designed to produce the greatest amount of plane noise possible during memory read and
write cycles. The noise parameters are effected by a number of factors: the noise generated is distributed across

the core plane algebraically and adds to the normal dynamic noise present on the sense lines. This can cause misreading of data (within the plane) that is in the low (1) or high (0) category. The sense windings of most memories are such that worst case patterns can be caused by alternately writing -1 and O data configurations throughout memory. Under these conditions, worst case noise is generated by performing a read, write, complement,

read, write, complement, operation at each location. The test is repeated after complementing all of the pattern

data stored in the memory test zone, so that all cores are worst case tested as both 1s and Os. The pattern, or its
complement, is written into the memory test zone as determined by the exclusive-OR between address bits 3
and 9.

3-57

The Worst Case Noise Test program is divided into two parts. Part 1 is run first and, during this part of the program, a - 1 configuration is written into all locations having an address with an exclusive-OR state between bits
3and 9. All other locations are loaded with the O configuration. After the test zone has been loaded, the memory is rescanned. This time, each location is read, complemented, read, and complemented (RCRC). Any loca-

tion detected as being disturbed by a previous RCRC operation is flagged as an error. Upon conclusion of the

read scan loop, the program automatically switches to Part 2.

During Part 2 of the program, the data patterns stored in memory are complemented. In other words, O patterns
are stored in locations having addresses with an exclusive-OR between bits 3 and 9. All other locations are

loaded with the - 1 configuration.
The exclusive-OR pattern distribution for Parts 1 and 2 is summarized for reference as follows:

Part 1

Exclusive-OR (3 and 9) = -1 pattern
No Exclusive-OR (3 and 9) = 0 pattern
Part 2

Exclusive-OR (3 and 9) = 0 pattern

No Exclusive-OR (3 and 9) = -1 pattern

After memory is loaded, it is scanned again with a read, complement, read, complement (RCRC) loop as described
previously. Any location detected as being disturbed by a previous RCRC operation is flagged as an error.
Before writing or reading any location (in either part of the program), the program issues a call to subroutine
XORCK (exclusive-OR check) which tests bits 3 and 9 and sets the XORFLG if the exclusive-OR condition is
present.

Subroutine ERRORA is called for any location disturbed from the - 1 configuration; subroutine ERRORB is
called for any location disturbed from the O configuration.
The program prints out errors and repeats when complete without interruption. Upon completion, the program

rings the Teletype® bell and then halts if switch 12 is present. A continue from the halt initiates another pass.
If the program indicates an error, use the troubleshooting chart as a guide to locating the fault.

® Teletype is a registered

trademark of Teletype Corporation.

3-58

APPENDIX A

INTEGRATED CIRCUIT DESCRIPTIONS

A.1

INTRODUCTION

In the ME11-L, two integrated circuits (ICs) are shown as boxes in the engineering drawings. All other compo-

nents are shown in the engineering drawings in logic symbology (gates, inverters, flip-flops). The two ME11-L
ICs are the SN74121 Monostable Multivibrator (DEC No. 19-10230) and the SN7528 Dual Sense Amplifier

(DEC No. 19-10687). These ICs are described in the following paragraphs, which include an IC package drawing
with number designations, an IC circuit equivalent logic diagram, and for the SN74121, a brief description.

These descriptions provide lower level logic description as a maintenance aid for troubleshooting the unit to the
IC level.

A.2

SN74121 MONOSTABLE MULTIVIBRATOR

This monolithic TTL monostable multivibrator features dc triggering from positive or gated negative-going inputs
with inhibit facility. Both positive and negative-going output pulses are provided with full fanout to 10 normalized loads.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input

pulse. Schmitt trigger input circuitry (TTL-compatible and featuring temperature-independent backlash) for the

B-input allows jitter-free triggering from inputs with transition times as slow as 1V/second, providing the circuit
with an excellent noise immunity of typically 1.2V. A high immunity to V. noise of typically 1.5V is also provided by internal latching circuitry.

Once fired, the outputs are independent of further transitions on the inputs and are a function only of the timing components. Input pulses may be of any duration relative to the output pulse. Output pulse lengths may
be varied from 40 ns to 40 sec by choosing appropriate timing components. With no external timing compo-

nents (i.e., pin 9 connected to pin 14, pins 10, 11 open), an output pulse of typically 30 ns is achieved which

may be used as a dc triggered reset signal. Output rise and fall times are TTL compatible and independent of

pulse length.

TRUTH TABLE
;

n INPUT ft; .

A1|AZ|

INPUT

OUTPUT

‘

|a1]A2]|

tfefoltft]t]

INHIBIT

X|0O]

INHIBIT

X]0|0]

INHIBIT

X110

X101t}

O|X]|0]O]

X]|41|ONE SHOT
X1OJO]X]O
|t
]ONE SHOT
111111

X]0/|

ONE SHOT

111110}

X | 1|

X{O0JO|X]

10|

ONE SHOT
INHIBIT

X]O]1|X|O]|

INHIBIT

X{oft

11|

INHIBIT

Ofx

]t]1]4]

INHIBIT

11110

X010 |

11110101

X0 |

INHIBIT

1*Vin(1) =2V
0=Vin (0)

£0.8V

t1-1119

A.3

SN7528 DUAL SENSE AMPLIFIERS WITH PREAMPLIFIER TEST POINTS

QUTPUTS

Vee+

STROBE
1S

V STROBE
23

GND

10
e

Cext

1Al

-VREF +VREr

2A1

2A2

Vee-

POSITIVE LOGIC: W=AS

DEFINITION OF LOGIC LEVEL
INPUT

TRUTH TABLE

INPUTS | QUTPUT

IVID2VT MAX[VIDS VT MIN|IRRELEVANT

VIZ2VIH MIN

[VISVIL Max|IRRELEVANT

'A is a differential voltage (V|p) between Al and A2, For

which terminal is positive with respect to the other.

these circuits Vip is considered positive regardless of

=122

DEC-11-HMELA-B-D

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of
our publications.

What is ydur general reaction to this manual? In your judgment is it complete, accurate, well organized, well
- written, etc.? Is it easy to use?

What features are most useful?

What faults do you find with the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Does it satisfy your needs?

Why?

Would you please indicate any factual errors you have found.

Please describe your position.
2

Name

Street
City

ARSI

Organization

Department
| V| (-

Zip or Country

—

— —

——

- ——

—— Do Not Tear - Fold Here and Staple

—

— —

—

FIRST CLASS

PERMIT NO. 33
MAYNARD, MASS.

BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
146 Main Street

Maynard, Massachusetts 01754