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XX-E9B37-96

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Document:	pdp11 ocr module
Order Number:	XX-E9B37-96
Revision:
Pages:	88
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OCR Text

E K-ADVI 1 -OP-O02

ADVl 1 -A, KWVl 1 -A,
AAVl 1 -A, D RVl 1
user’s manual

digital equipment corporation

maynard, massachusetts

1st Edition, July 1976
2nd Printing (Rev) November 1976
3rd Printing (Rev) April 1977

The material in this manual is for informational
purposes and is subject to Change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This document was set on DIGITAL% DECset-8000
computerized typesetting System.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts.
DEC
DECCOMM
DECsystem-10
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

PDP
RSTS
TYPESETTYPESET- 1
UNIBUS

CONTENTS
Page
CHAPTER 1
1 .l
1.2

INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REFERENCES

CHAPTER 2

ADVl 1 -A ANALOG-TO-DIGITAL CONVERTER

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
2.4.1
2.4.1 .l
2.4.1.2
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.4.4
2.5
2.51
2.5.2
2.5.3

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . .
F1 JNCTIONAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . .
Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USER INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
Quasi-Differential Mode
. . . . . . . . . . . . . . . . . . . . . . . .
Avoiding Spurious Signals
. . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Input Lines
. . . . . . . . . . . . . . . . . . . . . . . .
Shielded Input Lines
. . . . .
Allowing for Input Settling with High Source Impedance
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . .
Connections
. . . . . . . . . . . . . . . . . . . . . . . . .
Distribution Panel
External and Glock Starts . . . . . . . . . . . . . . . . . . . . . .
Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
Vector and Address Selection
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROGRAMMING
Control/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
Data Buffer Register (DBR)
.
.
.
. . . . . . . . . . . . . . . . . . . . . . .
Programming Example

CHAPTER 3

KWVl 1 -A PROGRAMMABLE REAL-TIME CLOCK

3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECIFICATIONS
.
.
.
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glock
. . . . . . . . . . . . . . . . . . . . . . . .
Input and Output Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Signals
Power Requirements (from LSI-11 Bus Power Supply) . . . . . . .
...

111

l-l
l-l

2-l
2-l
2-l
2-2
2-2
2-3
2-3
2-3
2-3
2-4
2-4
2-6
2-6
2-6
2-6
2-6
2-7
2-9
2-9
2-l 1
2-l 1
2-l 1
2-l 1
2-l 1
2-l 2
2-l 2
2-l 4
2-l 4
2-l 6
2- 17

3-l
3-l
3-l
3-l
3-2
3-3
3-3

CONTENTS (Cont )
Page
3.3
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.3.4
3.3.3.5
3.3.4
3.3.5
3.3.6
3.4
3.4.1
3.4.2
3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.5
3.5.1
3.5.2
3.5.3
3.5.3.1
3.5.3.2
3.5.3.3
3.5.3.4
3.5.4

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Control
Control/Status Register
. . . . . . . . . . . . . . . . . . . . . . . . .
Mode Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 0 (Single Interval)
. . . . . . . . . . . . . . . . . . . . . .
Mode 1 (Repeated Interval) . . . . . . . . . . . . . . . . . . . . .
Mode 2 (External Event Timing) . . . . . . . . . . . . . . . . . .
Mode 3 (External Event Timing from Zero Base) . . . . . . . . . .
Flag Overrun
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator, Divider, Rate Control Chain
. . . . . . . . . . . . . . . . .
Buffer/Preset and Counter Registers . . . . . . . . . . . . . . . . . . .
Schmitt Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONNECTORS, SWITCHES, AND CONTROLS
. . . . . . . . . . . . . . .
40-Pin Connector
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
FAST ON Connectors (Glock Overflow and ST1 Outputs) . . . . . . . .
Selector Switches (Address, Vector, and Slope/Reference Level)
. . . .
Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . .
Vector Selection
. . . . . . . . . . . . . . . . . . . . . . . . . .
Slope and Reference Level Selector Switches and Controls . . . . .
PROGRAMMING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer/Preset Register (BPR) . . . . . . . . . . . . . . . . . . . . . . .
Normal Control Sequences . . . . . . . . . . . . . . . . . . . . . . . .
Mode 0 (Single Interval)
. . . . . . . . . . . . . . . . . . . . . .
Mode 1 (Repeated Interval) . . . . . . . . . . . . . . . . . . . . .
Mode 2 (External Event Timing) . . . . . . . . . . . . . . . . . .
Mode 3 (External Event Timing from Zero Base) . . . . . . . . . .
Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 4

AAVl 1 -A DIGITAL-TO-ANALOG CONVERTER

4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.4.1
4.4.2
4.4.3
4.5
4.5.1
4.5.2

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECIFICATIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .
Bus Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DACsO,l,and2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONNECTORS, SWITCHES, AND CONTROLS
. . . . . . . . . . . . . . .
40-Pin Connector
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode/Level Selector Jumpers
. . . . . . . . . . . . . .
INTERFACING TO OUTPUT DEVICES . : : : : : . . . . . . . . . . . . . .
Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisting
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3
3-3
3-3
3-4
3-4
3-4
3-5
3-5
3-5
3-5
3-5
3-5
3-6,
3-6
3-6
3-6
3-7
3-8
3-8
3-8
3-8
3-9
3-9
3-9
3-13
3-13
3-l 7
3-l 7

4-l
4-l
4-2
4-2
4-2
4-2
4-2
44
4-4
4-5
4-6
4-6
4-6
4-7

.
.

CONTENTS (Cont )
Page

4.53
4.5.4
4.6

Shielding
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drive Capability
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROGRAMMING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 5

DRVll PARALLEL LINE UNIT

5.1
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5 -3.5
5.3.6
5.4
5.4.1
5.4.2
5.4.3
5.4.4

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . .
JUMPER-SELECTED ADDRESSING AND VECTORS . . . . . . . . . . . .
Locations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERFACING TO THE USER’S DEVICE . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
Request Flags
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NEW DATA READY and DATA TRANSMITTED Pulse
Width Modification
. . . . . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . .
PROGRAMMING
Addressing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vectors
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word Formats
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 6

ADVl l-A, KWVI l-A, and AAVll-A MAINTENANCE

6.1
6.2
6.2.1
6.2.1 .l
6.2.1.2
6.2.1.3
6.2.1.4
6.2.1.5
6.2.1.6
6.2.1.7
6.2.2
6.2.2.1
6.2.2.2
6.2.2.3
6.2.3
6.2.4
6.2.5
6.3
6.3.1
6.3.1 .l

MAINTENANCE PHILOSOPHY
. . . . . . . . . .
ADVl 1 -A ANALOG-TO-DIGITAL C&‘&E*RTER . : : : : . . . . . . . . . .
Installation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address and Vector Selection . . . . . . . . . . . . . . . . . . . .
Board Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Connector . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shields
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acceptance
Final Connections
. . . . . . . . . . . . . . . . . . . . . . . . .
ADVll-A Circuitry
. . . . . . . . . . . . . . . . . . . . . . . . . . .
ADVll-A Analog Power Supply
. . . . . . . . . . . . . . . . . .
ADVl l-AA/D Conversion Circuit
. . . . . . . . . . . . . . . . .
The Vemier DAC . . . . . . . . . . . . . . . . . . . . . . . . . .
ADV 11 -A Performance Test (MAINDEC-1 l-DVADA-A)
. . . . . . . .
Maintenance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration
. . . . . . . . . . . . . . . . . . . . . . .
KWVll-AREAL TIME CL&K’ : . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Installation
Location
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V

4-7
4-7
4-7

5-1
5-1
5-l
5-2
5-2
5-3
5-3
5-3
5-5
5-5
5-6
5-6
5-6
5-6
5-7
5-7
5-7

6-1
6-l
6-l
6-l
6-l
6-l
6-l
6-l
6-2
6-2
6-2
6-2
6-4
6-8
6-8
6-l 0
6-l 0
6-10
6-l 0
6-10

CONTENTS (Cont )
Page
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.1 .l
6.4.1.2
6.4.1.3
6.4.1.4
6.4.1.5
6.4.2
6.4.3
6.4.4
6.4.4.1
6.4.4.2
6.4.5
6.4.6
6.4.7

Address and Vector Selection . . . . . . . . . . . . . . . . . . . .
Board Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Connections . . . . . . . . . . . . . . . . . . . . . . . . . .
Acceptance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Final Connections
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .
KWVll-A Circuitry
KWVl l-A Diagnostic (MAINDEC-1 l-DVKWA-A-D) . . . . . . . . . . .
Maintenance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . .
AAV 11 -A DIGITAL-TO-ANALOG CONVERTER
Installation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Selection. . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Insertion . . . . . . . . . .
Test Connectors
. . . . . . . . .
Acceptance Test
. . . . . . . . . . . . . . . . . . . . . . . . . .
Final Connections
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode/Level Selection
. . . . . . . . . . . . . . . . . . . . . . . . . .
AAVll-A Circuitry
. . . . . . . . . . . . . . . . . . . . . . . . . . .
AAVll-A Analog Power Supply
. . . . . . . . . . . . . . . . . .
Digital-to-Analog Circuits . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . .
AAVl l-A Diagnostic Test (MAINDEC-1 l-DVAAA-A)
Maintenance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-10
6-l 0
6-l 0
6-l 0
6-10
6-l 1
6-l 1
6-l 1
6-l 1
6-l 1
6-l 1
6-11
6-l 1
6-l 1
6-l 1
6-l 1
6-l 2
6-12
6-12
6- 14
6-14
6-l 4
6-l 6

ILLUSTRATIONS
Figure No.

Title

Page
!

2-l
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-l 1
2-12
3-l
3-2

ADVl 1-A Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . 2-5
Single-Ended Input Referenced to User’s Ground . . . . . . . . . . . . . . . 2-7
2-8
Floating ADV 11 -A Input Signals . . . . . . . . . . . . . . . . . . . . . . . .
2-9
Single-Ended Versus True Differential Input Modes . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 2-l 0
ADVl 1 -A Quasi-Differential Mode
ADVl 1-A Connectors and Switches . . . . . . . . . . . . . . . . . . . . . . 2-l 2
ADV 11 -A 40-Pin Connector Pin Assignments . . . . . . . . . . . . . . . . . 2-l 3
H322 Distribution Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-l 3
Module Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
ADV 11 -A Address and Vector Switches
. . . . . . . . . . . . . . . . . . . . . . . . . . 2-l 5
(Rocker or Slide Switches)
ADVl l-AControl/Status Register (CSR) . . . . . . . . . . . . . . . . . . . 2-l 6
. . . . . . . . . . . . . . . . . . . . 2-16
ADVl l-AData Buffer Register (DBR)
. . . . . . . . . . . . . . . . 3-2
KWVl l-A Connectors, Switches, and Controls
.
.
. . . . . . . . . . . . . . . . 3-4
KWVl 1 -A Real-Time Glock Block Diagram

ILLUSTRATIONS ( Gon t )
Figure No.
3-3
3-4
3-5
3-6
3-7
3-8
3-9
4-l
4-2
4-3
4-4
4-5
4-6
5-l
5-2
5-3
5-4
5-5
5-6
5-7
6-l
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-l 0
6-l 1

Title
Connecting External User-Supplied Slope and Level Controls . . . . . . . . .
40-Pin Connector Pin Assignments
. . . . . . . . . . . . . . . . . . . . . .
KWVl 1 -A CSR Address Switches (Set for 170420) . . . . . . . . . . . . . .
KWVl l-A Vector Address Switches (Set for 000440) . . . . . . . . . . . . .
KWVl l-A Slope/Reference Level Selector Switches and Controls
. . . . . .
KWVll-ASlope Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR Bit Assignments
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AAVl 1 -A Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . .
AAV 11 -A Connectors, Switches, and Cont rols
. . . . . . . . . . . . . . . .
40-Pin Connector Pin Assignments
. . . . . . . . . . . . . . . . . . . . . .
AAV 11 -A Address Decoding
. . . . . . . . . . . . . . . . . . . . . . . . .
AAV 11 -A Address Switches (Set for 17044n) . . . . . . . . . . . . . . . . .
Connection to Oscilloscope with Differential Input . . . . . . . . . . . . . .
DRVl 1 Parallel Line Unit . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRVll Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRVll Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRVl 1 Vector Address . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jl or J2 Connector Pin Locations . . . . . . . . . . . . . . . . . . . . . . .
DRVll Word Formats
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRV 11 Interface Signal Sequence . . . . . . . . . . . . . . . . . . . . . . .
Battery-Operated Potentiometer Box for ADVl 1-A A/D Converter . . . . . .
Analog Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . .
DC-DC Converter Signals
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Positive Voltage Doubler
. . . . . . . . . . . . . . . . . . . . . . . .
ADVl 1-A A/D Conversion Circuit Block Diagram
. . . . . . . . . . . . . .
A/D During Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D During Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C Node During Conversion
. . . . . . . . . . . . . . . . . . . . . . . . . .
ADVl 1 -A Troubleshooting Procedure . . . . . . . . . . . . . . . . . . . . .
AAV 11 -A Troubleshooting Procedure . . . . . . . . . . . . . . . . . . . . .
Floating the DVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page
3-6
3-7
3-7
3-8
3-9
3-10
3-13
4-3
4-4
4-5
4-6
4-6
4-7
5-1
5-2
5-3
5-3
5-4
5-7
5-l 0
6-3
6-3
6-4
6-4
6-5
6-5
6-6
6-7
6-9
6- 15
6-16

TABLES
Table No.
3-l
3-2
3-3
3-4
4-l
5-l
5-2

Title
KWVll-A CSR Bit Definitions
. . . . . . . . . . . . . . . . . . . . . . . .
CSR Bit Settings for Mode 0, Single Interval
. . . . . . . . . . . . . . . . .
CSR Bit Settings for Mode 1, Repeated Interval . . . . . . . . . . . . . . . .
CSR Bit Settings for Mode 2, External Event Timing . . . . . . . . . . . . .
AAV 11 -A Digital-to-Analog Conversions
. . . . . . . . . . . . . . . . . . .
DRVl 1 Input and Output Signal Pins . . . . . . . . . . . . . . . . . . . . .
Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

Page
3-l 1
3-14
3-15
3-l 6
4-8
5-5
5-8

TABLES (Cont)
Table No.
6-l
6-2
6-3
6-4

Title

Page

ADV 11 -A Voltage/Current/Bit
Relationships . . . . . . . . . . . . . . . . . 6-8
Jumper Configurations for Bipolar Operation . . . . . . . . . . . . . . . . . 6- 12
Jumper Configurations for Unipolar Operation . . . . . . . . . . . . . . . . 6-l 3
. . . . . . . . . . . . . 6-l 3
AAVl 1 -A Input Code/Output Voltage Relationships

CHAPTER 1
INTRODUCTION

1.1 GENERAL

This manual contains information necessary for the Operation, installation, and maintenance of the
family of real-time analog and digital I/O devices which DEC provides as Options for the LSI-11
Processor, i.e., the ADV 11 -A Analog-to-Digital Converter, the KWVll-A Real-Time Glock, the
AAVI I-A Digital-to-Analog Converter, and the DRVl 1 Parallel Line Interface. Operating information for each device is provided in a chapter specific to that device which includes functional description, specifications, theory of Operation, and programming background. Installation and maintenance
information is provided for all units in Chapter 6.
All members of the LSI-11 real-time I/O family are designed to interface between the processor and
analog or digital Signals in the world external to the processor. All devices are configured on one quad
or double-height board designed to mount in an LSI-11 backplane or expander box and to receive
power from LSI-11 supplies. All communicate with the LSI-11 bus and receive interrupt priority as a
function of their location in the backplane. Finally, all have facilities to permit users to assign device
addresses, and where appropriate, interrupt vector locations.
A number of recommendations are made in this text regarding specific interfacing configurations and
general good practice. However, no specific interfacing Claims are made over and above those
expressed in the general specifications for each module. The responsibility for connecting DEC modules to external equipment rests ultimately with the User.
1.2 REFERENCES
l
l

Microcornputer Handbook (EB-06583 76 09/53)
LS/- 11 Bus SpeciJca tion

l-l

CHAPTER 2
ADVll-A

ANALOG-TO-DIGITAL

CONVERTER

2.1 GENERAL DESCRIPTION
The ADVl I-A is a 12-bit successive-approximation analog-to-digital converter with built-in multiplexer and Sample-and-hold for use on the LSI-11 bus. The multiplexer section accommodates 16
Single-ended or 8 quasi-differential inputs, and the converter section utilizes a patented auto-zeroing
design that measures the sampled Signal with respect to the offset of its own internal circuitry and thus
effectively cancels out its own offset error contributions to the measurement.
A/D conversions are initiated either by program command, clock Overflow, or external events as
determined by program control of the ADVl1-A’s Control/Status Register (CSR). The clock Overflow
command is supplied by the KWVll-A clock Option. External event inputs may originate directly
from user equipment or from the Schmitt trigger output on the KWVl l-A clock. Digital A/D conVersion data is routed through a buffer register to the LSI-11 for programmed transfer into memory.
This buffering optimizes the throughput rate of the converter by allowing data from one conversion to
be transferred to the processor after a subsequent conversion begins.
A vernier offset digital-to-analog converter is included in the ADVl l.-A’s analog circuitry to facilitate
very accurate program-controlled trimming of the A/D’s offset. Three test Signals - two dc levels and
one bipolar triangular waveform - are available for use on any channel input. The triangular wave tan
be used in conjunction with diagnostic Software and the vernier DAC to produce extremely thorough
and precise analog testing.
2.2 SPECIFICATIONS
2.2.1

Electrical (@ 25” C unless otherwise specified)

Inputs
Analog Input Protection

Fusible resistor guaranteed to open at h-85 V within 6.25 seconds. Guaranteed not to open from -20 V to +15 V at the
input. Overload affects no components other than the fusible
resistor on the overloaded channel; no other channels are
affected.

Logic Input Protection

Fusible resistor guaranteed to open at f 25 V within 6.25 seconds. Guaranteed not to open from -3 V to +8 V at the input.

Analog Input
Full Scale Range (FSR)

10.24 V bipolar (-5.12 V to +5.12 V)

2-l

Inputs (Cont)

Analog Input
Dynamit Resistance
(/Vin/ < 5.12 V)
Analog Input Bias Current
(/Vin/ < 5.12 V)

100 MQ, minimum
50 nA, maximum

Logic Input Voltages

Low = 0.0 to +0.7 V; high = +2 V to +5 V

Logic Input Currents

Low = -6.8 mA at 0 V in.; high = +1.3 mA at i-5 V in

Logic Input Rise/Fall Time

400 ns, maximum

2.2.2 Coding
A/D Converter

Resolution

12 bits, binary weighted

Format

Parallel offset binary, right justitied
Input Voltage

Output Code

+FS-1 LSB
0
-FS

7777
4000
0
(FS = 5.12 V; 1 LSB = 2.5 mV)

Vernier D /A

2.2.3

Resolution

8 bits, binary weighted

Format

Offset binary encoded
Input Code

Approximate Offset Voltage

377
200
0

+2.5 A/D LSB (+6.4 mV)
0
-2.5 A/D LSB (-6.4 mV)

Performance

Gain Error

Adjustable to zero

Offset Error

Adjustable to zero

Differential

Linearity

1 ntegral Linearity

No skipped states; no states wider than 2 LSB. 99% of statewidths f 1/2 LSB
f 1 LSB, maximum non-linearity (referenced to end Points)

2-2

Performance (Cont)
Temperature

Coefficients

Gain = 6 ppm per degree C
Linearity = 2 ppm of full-scale range per degree C
Offset = 7.5 ppm of full-scale range per degree C

Noise

Module = 0.4 LSB rms; 2 LSB peak
System = 1/2 LSB rms; 2 LSB peak

Warm-Up Time

5 minutes, maximum

2.2.4

Timing
External

Start

Low level pulse, 50 ns minimum to 10 ps maximum; conversion
Starts on leading edge

Synchronization

0 to T

Conversion

Time

16T
(T = clock period = 2.14 ps f 6%)

Transition

Interval’

9PSf 12%

Sample and Hold

Aperture Delay = 200 ns
Aperture Uncertainty = 2 ns

2.2.5 Test Signals
The ADVl 1-A provides three output voltages for test purposes:
1.

Positive dc level, +4.4 V (=t 15%)

2,.

Negative dc level, -4.4 V (f 15%)

Triangular wave, 15 Hz nominal (& 15%)

2.2.6 Environmental (Ref: DEC STD 102, class B)
2.2.7 Power Requirements
+5 Vdt *5% @2.0 A, maximum
+12 Vdt &3% @450 mA, maximum
2.3 FUNCTIONAL
DESCRIPTION
The ADV l l-A performs its function in seven successive Steps:
1.

It enables the specified channel.

It samples 1 of 16 Single-ended (or 1 of 8 differential) analog input channels specified by the
control program long enough to acquire a reliable internal reference equivalent.

It accepts a command to perform an A/D conversion.

It holds the sampled reference equivalent during

12 successive interrogation intervals.

*Reacquisition interval between end of conversion or channel Change and start of new conversion.
2-3

_5 .

When the least significant bit has been resolved in the Successive Approximation Register
(SAR), the ADVll-Atransfers the contents of the now-filled SAR to the DATA Buffer
Register (DBR) where that data tan be accessed by the processor.

It informs the processor that conversion data is available.

It reacquires and tracks the programmed channel.

These Steps are implemented in the ADVll-Aby components that tan be grouped together in four
functional categories:
1.

C hannel selection

A/D conversion

Processor/ADVl1-A interface

Control logic that coordinates the above Steps with respect to one another and to the needs
of the processor.

These categories are discussed below.
2.3.1 Channel Selection

Channel selection is accomplished under program control by two 8-channel multiplexers and is a
function of the data asserted in bits 8 through 11 of the Control/StatusRegister (CSR). Esch of the 16
analog input channels is routed to the Single output channel through a MOS field-effect transistor
which acts as a normally-open switch. During the Sample interval, the data Pattern in CSR bits 8
through 1 1 selects one of these transistors and Causes it to Change from a condition of nearly infinite
resistance (1 GQ or more) to one of very low resistance (1000 52 or less). Since in the selected state the
transistor conducts current within the k5.12 V limits equally well in both directions, it now functions
as a closed switch, effectively routing to the output line whatever analog Signal is connected to its
input.
2.3.2 A/ D Conversion

A/D conversions tan be initiated in three ways: under program control, on Overflow from the
KWVl I-A Real-Time Glock, or on external input. When a conversion is completed or the control
program writes a multiplexer address into the CSR, the control logic initiates the Transition Intervala delay of about 9 ps to allow the multiplexer adequate selection and settling time and to permit a valid
representation of the Signal level to be established in the Sample circuit. If no A/D Start Signal has
occurred by the time the Transition Interval has elapsed, the Sample circuit merely follows the Signal
transmitted to it through the selected multiplexer channel and waits for an A/D Start Signal. When an
A/D Start Signal occurs - or at the end of the Transition Interval if A/D Start was previously generated by the writing of the CSR GO bit - the Sample and hold circuits are switched to hold, sustaining
the sampled level for the next Step. The multiplexer output is then set to its hold condition, i.e., to
ground if the Single-ended (SE.) input is set low for Single-ended measurement, to the second differental input (return line) if the S.E. input is not set low. Note that if an external or clock Start Signal occurs
during the Transition Interval, conversion Starts immediately without waiting for the Transition Interval to be completed. Bit 15 of the CSR (AD ERROR) is set, however, and an interrupt is generated if
bit 14 (error interrupt enable) is set - alerting the program that conversions are occurring too fast and
are consequently liable to be in error.

2-4

’ CHANNEL

SELECTION

’ A-D CONVERSION
COMP H

LOW CHANNEL
SELECT

T-l

r-l
SAMPLE 8 HOLD
COM PARATOR
.

INTERFACE

HIGH CHANNEL
SELECT
---B----w
,

----m
-C ONTEL-

v4
/

FUNCTIONS

LOW
CHANNEL
^.--< -^-

>tLtL I
-

-I

”

1 (READ) L-,,
IBD 0 8 111
I

DBR
(WRITE)

EXT ST.

EOC

HIGH
CHANNEL
SF1 FI-T
-----.
LOW ENABLE
..<^.<
HlbH
ENABLE

MISC
CONTROL
LOGIC

ADZC L
HOLD

TRANSCEIVER
CNTL
VECTOR H
’ SINGLE
ENDFD

L
11-4165

Figure 2- 1

ADV l l-A Functional Block Diagram

Under normal conditions, it is not until the Transition Interval is complete that the measurement
process is begun. The Successive Approximation Register (SAR) is cycled through 13 states by the
clock. In the first state its output code involves only the most significant bit (MSB) of the 12-bit SAR
werd. This output code Causes the feedback digital-to-analog converter (DAC) to generate an output
equivalent to that produced by the hold circuits in response to a Sample voltage of 0. The DAC output
is summed with that produced by the hold circuits and with that coming from the grounded multiplexer output (Single-ended mode) or from the second differential input (quasi-differential mode). If
the current from the summing node is negative, the first approximation was too low, and the comparator Signals the SAR to maintain the state of bit 11 and repeat the process with bit 10. If the current
from the summing node is positive, the first approximation was too high and the SAR changes the
state of bit 1 1 before cycling into the second approximation. This process continues until all 12 bits in
the werd have been set, tested, and if necessary, changed. The 13th state (end of conversion, or EOC)
indicates that the measurement is complete and that the SAR now contains an offset binary equivalent
of the sampled voltage and may therefore be transfered to the processor. EOC Causes the Sample and
hold circuits to return to the Sample mode and to reset the SAR, preventing further SAR activity until
the occurrence of the next hold condition.
Note that because the reference Point against which the Sample voltage is compared is at the output of
the multiplexer itself rather than internal to the Sample and hold circuits, all offset voltages generated
by the intervening circuits are common to both Sample and hold conditions and are therefore cancelled
out of any measurement. In Single-ended mode, grounding the multiplexer output (and thereby establishing this reference Point) is identified as auto-zeroing the converter.
2.3.3 Interface Functions
In addition to stopping the SAR clock and reestablishing the Sample mode, the end-of-conversion
Signal also initiates the process that Causes the SAR data to be transferred to the processor. Since this
Operation takes a finite amount of time which would interfere with subsequent measuring operations,
the SAR data is first transferred to a holding device, the Data Buffer Register (DBR), where it will
remain until the processor tan be notified to read the conversion data for processing. In the meantime,
the channel selection and A/D conversion circuits tan begin the next measurement as dictated by
Control/Status Register (CSR) bit conditions controlled by the processor.
Included in the ADVl l-Ainterface is an extension of the DBR designed to accept 8-bit write information from the BUS DATA/ADDRESS lines. This buffer permits programmed setting of the Vernier
DAC (see Paragraph 6.2.2.3). Also included are transceivers that connect the bi-directional BUS
DATA lines to the LW1 1 Bus DATA/ADDRESS lines. Associated with these transceivers are switches that permit assigning device and vector addresses to any given A DVl 1-A.
i

2.3.4 Control
As the above discussion suggests, a large number of Signals must be precisely orchestrated each time
the ADV 1 I-A executes a conversion. The control logic contains an assortment of gates, latches, readonly memories, and timing circuits designed to assure that multiplexer channels are properly selected,
Sample durations are of adequate length, conversions are not initiated during uncompleted previous
conversions, etc. In general, this logic precludes the need for the user to attend to any but the mostelementary details of the conversion process, e.g., making necessary connections to the System and
writing control programs that make appropriate use of the CSR.
2.4 USER INTERFACING
2.4.1 Analog Inputs
2.4.1.1 Single-Ended Mode* - Single-ended analog input Signals for the ADVVl l-Amay be of two
types. grounded and floating. A grounded input is one whose level is referenced to the ground of the
instrument that is producing it, as illustrated in Figure 2-2. Since the instrument may be located at a
*The ADV I I-A is factory-set for differential mode. Single-ended mode must be selected as described in Paragraph 2.4.3.3.

2-6

distance from the Computer, there may be some voltage differente between the instrument ground and
the Computer ground. The voltage seen by the ADVll-Awill be the sum of the undesired ground
differente voltage and the desired instrument Signal voltage. In cases where such differentes are
encountered, they tan be minimized by plugging the instrument into an ac outlet as close as possible to
that providing power to the Computer. DO not run a wire from user’s ground to the ADVl 1-A analog
ground. Such a wire tan Cause ground loop currents which affect results not only on the input channel
in question, but also on other channels.

~----SER’S

SOURCE VOLTAG

I
I
I
I
I

L
L --s-s

USER’S
GROUND

COMPUTER
GROUND
It-4166

Figure 2-2

Single-Ended Input Referenced to User’s Ground

A floating input is one whose Signal voltage is developed with respect to a Point not connected to
ground, as illustrated in Figure 2-3. The identifying characteristic of a floating Source is that connecting the Signal return to the ADVll-Aground does not result in a current path between the
ADVl I-A ground and the instrument ground.
Note that the return of a floating input must be connected to one of the ADW 1-A’s analog ground
terminals (see Figure 2-3). Ground Points may be shared among channels, as illustrated by the batterypowered sources in Figure 2-3.
2.4.1.2 Quasi-Differential Mode - The “quasi” prefix in “quasi-differential” tan best be explained in
the context of a preliminary review of true differential Operation. A true differential input involves two
Signal lines connected to a differential amplifier in such a way that the output of the device is a function
of the instantaneous differente between the voltages on the two Signal lines. One advantage of such a
configuration is illustrated in Figure 2-4.
Figure 2-4(a) assumes a Single-ended generating device that produces a Signal, V,, with respect to its
ground and is situated sufficiently far from the receiving device for a significant noise voltage, Vn, to be
developed in the power distribution ground lines. The result is that, at any given instant, the differential amplifier in the receiving device sees both the Signal voltage and the noise voltage. Its output, Vo, is
a function of VS + V, and is in error with respect to V, alone.
2-7

FLOATING

SOURCE

1
SIGNAL ,-.
RETURN $,
\ I

CHAN 00
I
’ CHAN 01
I

BATTERY
SOURCE

CHAN 02

POWERED

INSTRUMENT WITH
ISOLATION TRANS FORMER AND
FLOATING SECONDARY

;lGNAL ,,/
?ETURN ,‘\
HO GROUND
I

11-4167

Figure 2-3

Floating ADVl l-A Input Signals

Figure 2-4(b) illustrates the same device connected in true differential mode. The same noise voltage
exists in the power distribution ground System, but this time the generating device ground is connected
directly to the negative input of the receiving differential amplifier. Since the instantaneous noise
voltage is common to both the + and the - inputs, it is cancelled out of the final amplifier output. VO
now provides a valid representation of VS alone.
Figure 2-5 illustrates the ADVl 1-A operating in the quasi-differential mode.
The major contrast between true differential Operation as described above and the Operation of the
ADVl 1-A in differential mode is that in the latter, the two sides of the Signal are not simultaneously
input to a differential amplifier. Rather, their differente is established by a sequential Operation that
first samples the voltage at one of the two inputs and then, holding this value fixed, in effect subtracts
from it the voltage at the second input. For near dc conditions, this procedure produces a result like
that of true differential Operation - that is, the output is a function of the differente between the two
input voltages, and common mode voltages are cancelled out. But, since there is a significant time
lapse between taking the Sample and completing the final approximation, a possibility for error is
introduced by the ADV l l-A that increases as a function of common mode Signal frequency. The result

2-8

is that the common mode rejection ratio, while essentially infinite at dc, rolls off for ac Signals, and is
about 40 dB at 60 Hz line frequency. In addition, since the holding action of the Sample-and-hold
circuit is only in effect on the first (non-inverting, Signal) input but not on the second (inverting,
return) input, the voltage rate of Change on the second input should be kept below 25 mV/ms. This is
the slope that results in a quarter-LSB Change during the conversion interval. Such a rate of Change
corresponds to 125 mV peak-to-peak at 60 Hz line frequency. This dynamic response differente
between the two inputs requires us to distinguish the ADV1 1-A’s differential mode from true differential Operation. Hence the term “quasi-differential.”

r ---- 1

r- - - -

GENERATING DEVICE

I
I

I
I
L

RECEIVING

-----

-Pm-

o. S I N G L E - E N D E D M O D E

DEVICE

----

(VO=Vl+V,)

GENERATING DEVICE

-i-

-L
1

b. TRUE DIFFERENTIAL MODE

(V, =V, +:,-Vn)
11-4168

Figure 2-4

Single-Ended Versus True Differential Input Modes

2.4.2 Avoiding Spurious Signals

As a preliminary Step, tonfirm that the Computer power supply ground is connected to power line
(earth) ground. If continuity Checks reveal no such connection, attach a length of 12-gauge wire
between the power supply ground and a convenient Point associated with earth ground. (All DECLAB
11/03 Systems are provided with this connection at the factory.)
2.4.2.1 Twisted Pair Input Lines - The effects of magnetic coupling on the input Signals may be
reduced for floating Single-ended or differential inputs by twisting the Signal and return lines in the
input cable. If the inductive pickup voltages of the two leads match, the net effect seen at the ADVl 1-A
input is Zero. Use of twisted pairs has no effect with a Single-ended non-floating Signal (referenced to
ground at the instrument end).

2-9

I
I
I
l
I
I
I
I
I
I

I
I

1
I
I
1
I
I
I
I

2-10

I
I

2.4.2.2 Shielded Input Lines - The effects of electrostatic coupling on the input Signals may be reduced blr shielding the Signal wires. This is especially important if the instrument or transducer has high
Source impedance. To prevent the shield from carrying current and thus developing ground loop
voltages within the ADVl I-A, connect it to ground at the instrument end only.
2.4.2.3 Allowing for Input Settling with High Source Impedance - All solid-state multiplexers inject a
small amount of Charge into their input lines when changing channels, causing a transient error voltage
that is discharged by the input signal’s Source impedance. The ADVl l-A shares this characteristic, and
also injects a small Charge into the selected input line at the end of each conversion when the auto-zero
switch is turned off (see Paragraph 2.3.2). After any channel Change and after any conversion, the
ADV 1 1-A’s control logic allows a 9 ps interval (identified as the Transition Interval) during which
conversions cannot Start without generating error conditions. Normally, this is sufficient time for the
input transient to settle out. However, more time may be needed when the multiplexer is switching into
an input channel with high Source impedance, particularly when large amounts of Shunt capacitance
exist in the interconnecting cables. Source impedance/cable
Shunt capacitance products greater than 1
11s should be avoided whenever conversions are to be made at maximum rate with less than 1/2 LSB
error. This means that cable Shunt capacitance for a 1000 12 Source should not exceed 1000 pF (103 X
10m9 = 10m6), that Shunt capacitance for a 100 52 Source should not exceed 0.01 pF ( 102 X lO’* = 10m6),
etc. Assuming twisted pair cable capacitance of 50 pF/foot, these constraints translate into a maximum run of 20 feet from a lOOO-R Source, 200 feet from a lOO-Q Source, etc. Note that these values are
consistent with good practice for avoiding noise pickup in long cable runs. Note also that settling
errors tan be eliminated by increasing the time between conversions or incorporating a Software delay
between channel changes and program Start commands.
2.4.3 Connections
Figure 2-6 illustrates the location of user connectors and switches on the component side of the
ADVll-Aboard.
Analog input Signals are input to the ADVl 1-A through the 40-pin connector. Pin assignments for the
connector are shown in Figure 2-7. The proper Berg-to-Berg cable is the BC08R; the proper Berg to
prepared open-ended cable is the BC04Z. (See Maintenance chapter for further information.)
2.4.3.1 Distribution Panel - Figure 2-8 Shows an H322 Distribution Panel that is connected on the
rear to the ADVl 1-A Berg connector and on the front provides easily identifiable and conveniently
accessible barrier Strip connections for user apparatus. Esch H322 accommodates two ADVl l-As or
one ADVl l-A and one other Single-connector device. The ADVl l-A is shipped with decal sets that
specifically identify ADVl l-A inputs and Outputs. Note that the H323-B Potentiometer Box may not
be used with the ADVl 1-A. (See Maintenance chapter for appropriate Potentiometer box circuit.)
2.4.3.2 Extemal and Glock Starts - The external Start Signal line, pin B of the Berg connector or TAB
S (see Figures 2-6 and 2-7), is a TTL-compatible input that presents five unit loads (8.0 mA) to any
driving output. Conversions Start on the high-to-low transitions of this Signal.
In most cases, the external Start Signal will be produced by a grounded (non-floating) pulse generator
or logic circuitry located in a grounded instrument. The return path for the External Start Signal will be
through the power line ground System. For this reason, ground differentes between Source and comPuter should be minimized to prevent spurious Start pulses due to ground noise. In no case should a
separate return line be run between grounded Source and the Computer ground. Only with floating
devices should return lines be run between Source logic ground and logic ground pins on the ADVl l-A
Berg connector. External devices that require buffering tan be interfaced to the ADV l l-A through
Schmitt Trigger 1 of the KWVll-A clock (STl). Connection is made by means of a DEC 7010771 type
jumper (Figure 2-9) to TAB S (Figure 2-6) of the ADVll-A.

2-l 1

SI NGLE-ENDED
JUMPER LUGS

j
(EXTERNAL
OFFSET
ADJ-

Figure 2-6

START 1

GAIN
ADJ

ADV l l-A Connectors and Switches

Conversions that must be initiated in consequence of time intervals or on every nth external event may
be triggered from the KWVll-A through a DEC 7010771 type jumper connected from the clock
output tab (CLK) to the ADVll-Aclock Overflow tab (C).
2.4.3.3 Mode Control - The ADVll-Ais equipped with jumper lugs (see Figure 2-6) that permit
changing operating mode from quasi-differential (no connection) to Single-ended (jumper installed).
The Single-ended mode tan also be selected by connecting Berg connector pin C to logic ground. This
alternative is provided to permit convenient external mode selection in installations that require frequent alternation between one mode and the other.
2.4.4 Vector and Address Selection - Device and vector addresses are assigned to the ADV l l-A by
means of two switch Packs (S2 and S 1, Figure 2-6). S2 is a pack containing 10 Single-pole/single-throw
switches, numbered 1- 10, that communicate with data lines BDAL 2-l 1. Assuming BDAL lines 12-15
to be set by the processor to 1, SI permits assigning any address between 170000 and 177774. The
recommended address for the ADVl 1-A Status Register is 170400, set as illustrated in Figure 2-IO(a).
The Data Buffer Register automatically receives the next even address following that assigned to the
CSR.

2-12

LOGIC GND &

!
A

SINGLE

START L
o---&/EXT

ENDE0 L -Li+
RAMP

ANALOG GND

-4.5v

ANALOG

C H 17

-CH 07

CH x7

C H 16

-CH 06

CH X6

CH 15

-CH 05

CH x5

CH 14

-CH 04

CH x4

CH 0 7

+Cti

CH 0 7

CH 0 6

+CH 0 6

CH 0 6

CH 0 5

+ct?

CH 0 5

CH 0 4

+CH 0 4

CH 0 4

CH 13

-CH 03

CH x3

C H 12

-CH 02

CH X2

C H 11

- C H 01

CH X1

C H 10

-CH 00

CH XO

CH 0 3

+CH

CH 0 3

CH 0 2

+cti 0 2

CH 0 2

+CH

CH 01

CH 0 0

+CH

CH 0 0

SINGLE
ENDED

DIFFERENTIAL

H322
NOMENCLATURE

BOARD S I D E

Figure 2-7

ADVl 1-A 40-Pin Connector Pin Assignments

8201

Figure

2-8

H322

Distribution

Panel

The A/D done interrupt vector address is set by means of Sl, an 8-switch pack of which only six
switches are utilized. These switches communicate with BDAL lines 3 through 8 and tan be set in
increments of 10~. The error interrupt vector automatically receives an address that is four locations
higher than the A/D done interrupt vector whose recommended address is 000400 [see Figure 2-lO(b)].

2-13

M-O599

Figure 2-9 Module Jumpers
2.5

PROGRAMMING

2.5.1 Control/Status Register (CSR)

The significance of the CSR bits is defined below:
Bit 15: A/D ERROR (Read/ Write) - The A/D ERROR may be program set or cleared and is cleared

by the processor INITIALIZE. It is set by any of the following conditions:
1.

Attempting an external or clock Start during the transition interval (see Paragraph 2.3.2)

Attempting any Start during a conversion in progress

Failing to read the result of a previous conversion before the end of the current conversion.

Bit 14: ERROR INTERRUPT ENABLE (Read/ Write) - When set, enables a program interrupt upon

an error condition (A/D ERROR). Interrupt is generated whenever bits 14 and 15 are set, regardless
of which was set fn-st.
Bits 13-12: Not used.
Bits 11-8: MULTIPLEXER ADDRESS (Re&/ Write) - Contain the number of the current analog
input channel being addressed.
Bit 07: A/ D DONE (Read) - Set at the completion of a conversion when the data buffer is updated.

Cleared when the data buffer is read and by the processor INITIALIZE. If enabled interrupts are
requested simultaneously by both bits 07 and 15, bit 07 has the higher priority.
2-14

Bit 06: DONE INTERRUPT ENABLE (Readl Write) - When set, enables a program interrupt at the
completion of a conversion (A/D DONE). Interrupt is generated when bit 07 and bit 06 are both set,
regardless of sequence.
Bit 0.5: CLOCK STAR T ENA BLE (Read/ Write) - When set, enables conversions to be initiated by an
Overflow from the clock Option.
Bit 04: EXTERNAL STA RT ENABLE (Read/ Write) - When set, enables conversions to be initiated
by an external Signal or through a Schmitt trigger from the clock Option.
Bit 03: ID ENABLE (Read/ Write) - When set, Causes bit 12 of the Data Buffer Register to be loaded
to a 1 at the end of any conversion.
Bit 02: MAINTENA NCE (Read/ Write) - Loads, when set, all bits of the converted data output equal
to Multiplexer Address LSB (bit 08) at the completion of the next conversion. Cleared by the processor
INITIALIZE. Used for “all Os” and “all 1s” tests of A/D conversion logic.
Bit 01: Not used.
Bit 00: A/ D STA R T (Read/ Write) - Initiates a conversion when set. Cleared at the completion of the
conversion and by the processor INITIALIZE.

OCTAL

EOUIVALENT

LOGICAL
BIT VALUE

CSR ADDRESS
S W I T C H (S2)

BDAL BIT
POSITION
BOARD
FINGERS

BOARD
- H A N D L E
a CSR

ADDRESS

SWITCH

(SET

FOR

170400)

OCTAL

EQUIVALENT

----L
0-A
LOGICAL
BIT VALUE

BDAL BIT
POSITION

*SWITCHESN O T

CONNECTED
b

Figure 2- 10

VECTOR

ADDRESS

SWITCH

(SET

FOR

000400)

ADV l l-A Address and Vector Switches (Rocker or Slide Switches)
2-15

READ/WRITE
ERR
INT ENA

AD
DONE

CLK
START
ENA

ID
ENA

NOT USED

!l-4311

Figure 2- 11

ADV l l-A Control/Status Register (CSR)

V E R N I E R D/A (WRITE)
c

MS8

CONVERTED

LSB

DATA

(READ)
11-4312

Figure 2- 12

ADVl 1-A Data Buffer Register (DBR)

2.5.2 Data Buffer Register @BR)

The DBR is actually two separate registers - one read only, the other write only.
Read Only (Cleared at processor initialize)

Bits 25-23: Not used. Should read as 0.
Bit 22: ID (Read) - When ID ENABLE (bit 03) of the CSR has been set, DBR bit 12 will be

loaded to a 1 at the end of conversion.
Bits 1 1-00: CON VERTED DA TA (Read) - These bits contain the results of the last A/D

conversion.

Write Only (Set to 2008 at processor initialize)
Bits 25-08: Not used.
Bits 07-00: VERNIER DIA ( Write) - These bits provide a programmed offset to the converted

value (scaled 1 D/A LSB = 1/50 A/D LSB). The hardware initializes this value to 2008 (midrange). Values greater than 200~ make the input voltage appear more positive.

2-16

2.5.3 Programming Example

Read 1008 A/D conversions from channel 0 into locations 4000&176s and halt.
START:

LOOPI

CLR

QADSR

?!QV
INC

#4OOO,RO

TSTEY
BPL
IW
M0v

CW
0NE
HALT
Aw3P:

ADEIßt

170400
170402
,ENP

tCLEAF A/D S T A T U S R E G I S T E R
jSFT U P F I R S T ADRFESS
tSTART
A/U CONVERS‘ION
jCHECK D O N E F L A G
jwAIT UNTIL FLAG S E : ?
ISTART
%EXT CONVEFSXONw
;PLACE C O N V E P T E G VALUE
tFFQM AIP RUFF’EP IF!TO MEMOFY
;LOCATION Ar:D S E T UP ?JEXT
:L@CATXON F O R TRANSFER*

@Al?SR
QADSF
LOOP

@ADSP
@ADBP,(PO)+

RO,#4200

ICHECK I

1c)O CQNVENWXJS

;HAVE BEEti DnNE
IfJO# G E ? NEXT CONVE’RSION
; DI7NE
tA/P S T A T U S RFGISTFR ADDPFSS
tA/D BUFFER
RE’GISTEP AUl2RESS

LOOP

START

*Starting a subsequent conversion before moving data from a previous conversion is to be recommended only
with Systems equipped with non-processor memory refresh, as provided in the REVll Options. Without this
capability, data will be lost occasionally by CPU memory refresh intervening between the INC and MOV commands. In general, non-processor memory refresh is essential to realizing the full potential of the ADVl l-A.

2-17

CHAPTER 3
KWVll-A PROGRAMMABLE REAL-TIME CLOCK

3.1 GENERAL DESCRIPTION
The KWV l l-A is a programmable clock/counter combination that provides a variety of means for
determining time intervals or counting events. It tan be used to generate interrupts to the LSI-11
processor at predetermined intervals, to synchronize the processor to external events, or to measure
time intervals or establish programmed ratios between input and output events. It tan also be used to
Start the ADVl 1-A Analog-to-Digital Converter either by clock counter Overflow or by the Fixring of a
Schmitt trigger.
The clock counter has a resolution of 16 bits and tan be driven from any of Eve internal crystalcontrolled frequencies (100 Hz to 1 MHz), from a line frequency input or from a Schmitt trigger fit-ed
by an external input. The KWVl 1-A tan be operated in any of four programmable modes: Single
interval, repeated interval, external event timing, and external event timing from zero base.
The KWV l l-A includes two Schmitt triggers, each with integral slope and level controls. The Schmitt
triggers permit the user to Start the clock, initiate A/D conversions, or generate program interrupts in
response to external events.
The physical structure of the KWVl 1-A is illustrated in Figure 3-l. The unit is contained on one quad
size module whose fingers interface to the LSI-11 Bus. User interfacing for the Schmitt triggers and
clock Overflow Signals is accomplished by means of a multi-pin connector (Jl). FAST ON connectors
(CLK, STl) are provided to permit direct and simple connections of clock Overflow and Schmitt
trigger Outputs to corresponding terminals on the ADVl l-A A/D Converter. Switch Packs permit
selecting CSR (Control/Status Register) address, interrupt vector address, and Schmitt trigger slope
and level conditions. Screwdriver controls (R 18 and R19) permit setting Schmitt trigger levels. Provision is also made via the multi-pin connector Jl for external user-provided slope switches and Level
controls.
3.2
3.2.1

SPECIFICATIONS (@ 25” C unless otherwise specified)
Glock

Oscillator

Accuracy

Range

3.2.2 Input and Output Signals
All inputs and Outputs are TTL compatible

0.01%
Base frequency (10 MHz) divided into five selectable rates
(1 M Hz, 100 kHz, 10 kHz, 1 kHz, 100 Hz); line frequency;
Schmitt trigger 1 input
unless otherwise specified.

3-l

BIT 11

BIT 2

rl
ADDRESS
SWITCHES

BIT 8

BIT 3

n
VECTOR
SWITCHES

Figure 3- 1
3.2.2.1
1.

KWVl 1-A Connectors, Switches, and Contrals

1 npu t Signals

ST1 IN (Schmitt Trigger 1 Input)
Input Range
(maximum limits)
Assertion Level

-30 v to +30 v

Origin

User device

Response Time

Depends upon input waveform and amplitude; typically
600 ns with TTL logic input

Hysteresis

Approximately 0.5 V, positive and negative

Characteristics

Single-ended input; 100 kS2 impedance to ground

Depends upon Position of slope reference selector switch
and level control; triggering range, -12 V to + 12 V

ST2 IN (Schmitt Trigger 2 Input)
Same description as ST1 IN
3-2

3.2.2.2
1.

Output

Signals

CLK OV (Glock Overflow)
Asserted Level

Low

Destination

User device or ADVl 1-A

Duration

Approximately 500 ns

Characteristics

TTL open-collector driver with 470 12 pull-up to +5 V
Maximum Source current from output through load to
ground when output is high (2 2.4 V): 5 mA
Maximum sink current from external Source voltage
through load to output when output is low (GO.8 V): 8 mA

ST1 Out (Schmitt Trigger 1 Output)
Same description as CLK OV

ST2 OUT (Schmitt Trigger 2 Output)
Same description as CLK OV

3.2.2.3 Environmental (refi DEC STD 102, class C)
3.2.2.4

Power Requirements (from LSI-11 Bus Power Supply )
+5 v
1.75 A typical
+12 v
10 mA typical

3.3 FUNCTIONAL DESCRIPTION
3.3.1 Bus Control
Figure 3-2 illustrates the KWVll-A in block diagram form.
The logic associated with the bus control block maintains proper communications protocol between
the processor bus and the KWVll-A. This logic generates and monitors the bus Signals involved
during interrupts and data transfers between the processor and the KWVl1-A. It permits the KWVl lA to recognize when it is being addressed by the processor (address defined by the Address Switch
Pack), to prescribe the location in memory pointing to the starting addresses of interrupt Service
routines (by means of the Vector Address Switch Pack), to input control data from the processor, and
to output data to the processor.
Interrupts tan be enabled for both counter Overflow and Operation of ST2. Since each of these conditions raises a flag bit in the Control/Status Register, and since separate interrupt vectors exist for each
condition, the conditions may be distinguished either by vectors or by testing flag bits.
3.3.2 Control/Status Register
The Control/Status Register (CSR) provides a means for the processor to control the Operation of the
KWVl 1-A and to derive information about its operating condition. Bits are provided for enabling
interrupts, mode selection, maintenance operations, starting the counter, and Overflow and Schmitt
trigger event monitoring. (See Figure 3-9 and Table 3-l .)
3-3

BUS

CONTROL

RR
o v L
-~_-4
(Jl)
VECTOR H

----i

CLK

SWITCH
PACK

UVECTOk
ADDRESS

A
CSR

15-0

v
ST2 FLAG
NTERRUPT

BEVNT

L ,z

CONTROL

x
VVSTl I N

SCHMITT

TRIGGERS

ST1

ST LEV 1

(Jl)

(Jl)
ST2 OUT L HH
a
(J 1)
ST1 H
S

Figure 3-2

*
I

MISCELLANEOUS
INTERNAL
CONTROL
SIGNALS

KWV l l-A Real-Time Glock Block Diagram

3.3.3 Mode Control
Logic circuitry associated with the mode control block permits KWVl 1-A Operation in four different
modes as specified by bits 2-l of the CSR.
3.3.3.1 Mode 0 (Single Interval)
When the GO bit is set in this mode either by the processor or by a Schmitt Trigger 2 event, the counter
is loaded from the Buffer/Preset Register (which has previously been loaded with the 2’s complement
of the number of counts desired before Overflow). Once loaded, the counter will increment at the
selected rate until it Overflows. Overflow clears the GO bit, sets the Overflow Flag, and interrupts the
processor if that function has been enabled. If interrupt has not been enabled, the KWVl 1-A waits for
processor
intervention.
3.3.3.2 Mode 1 (Repeated Interval)
When the GO bit is set in this mode, the counter is loaded from the Buffer/Preset Register (BPR) and
is then incremented to Overflow as for Mode 0. In Mode 1, however, Overflow does not clear the GO
bit; instead, it Causes the counter to be reloaded from the BPR, raises the Overflow Flag, initiates an
interrupt sequence if the CSR Interrupt on Overflow bit is set, and Causes the count to be continued
with no loss of data.

3-4

3.3.3.3 IUode 2 (Extemal Event Timing)

M’hen the GO bit is set in this mode, the counter is set to 0 and then incremented at the selected rate as
long as the GO bit remains set. An external Signal to Schmitt Trigger 2 (ST2) Causes the current
contents of the counter to be loaded into the BPR while the counter continues to run. At the same time
the ST2 Flag is set and, if Interrupt 2 is enabled, an interrupt is generated, thus permitting the program
to read the value held in the BPR.
The counter continues to run after the ST2 event and also continues to run after Overflow. Interrupt on
Overflow mal’ be enabled to alert the program to the Overflow condition.
3.3.3.4

hlode 3 ( External Event Timing from Zero Base)

Operation in Mode 3 is identical to that in Mode 2 except that the counter is zeroed each time an ST2
event loads its contents into the BPR.
3.3.3.5 Flag Overrun

In all modes, if a second Overflow occurs before the Overflow Flag is reset (i.e., before a Prior event is
serviced by the processor), or if ST 2 fires when the ST 2 flag is already set, the Flag Overrun bit is set.
3.3.4

Oscillator,

Divider,

Rate

Control

Chain

The circuitry associated with these blocks provides the time base that is fed to the counter. The
KWV l l-A permits eight clock conditions to be specified by bits 5-3 of the CSR: STOP, 1 MHz,
100 kHz, 10 kHz, 1 kHz, 100 Hz, an external time base applied to STl, and line frequency (50 or 60
Hz) picked up from bus line BEVNT. External periodic or aperiodic pulses may be applied to ST1 and
counted, provided they meet the criteria in Paragraphs 3.2 and 3.3.6.
3.3.5

Buffer/Preset

and

Counter

Registers

The Buffer/Preset Register is a word-oriented, 16-bit read/write register that tan be loaded either
under program control or from the counter. In Modes 2 and 3, the firing of ST2 Causes the BPR to be
loaded with the contents of the counter. The BPR cannot be loaded by the program in these modes as
long as the GO bit is set.
The counter is a 16-bit internal register accessible only by way of the BPR; in Modes 2 and 3 it tan be
read indirectly through the BPR.
3.3.6 Schmitt Triggers

Both Schmitt triggers are equipped with switches to permit selecting slope direction (+ or -) and
threshold reference level (TTL or -12V to +12V continuously variable). Esch Schmitt trigger is also
equipped with a screwdriver-operated Potentiometer to permit setting the variable threshold level.
Switch-pack and Potentiometer terminals are all brought to multiple connector Jl to permit attachment of external user-provided slope and level controls. (See Figure 3-3.)
The two Schmitt triggers are used in somewhat different ways:
STI - Performs as an external time base input or external input for aperiodic Signals to be
counted. Outputs both to ST1 FAST ON connector to provide external Start Signals to ADVl l-A
and, through rate control circuitry, to permit selection as input to the counter. Maximum frequency varies as a function of input waveform.
ST? - When the ST2 GO ENABLE bit is set, Iiring ST2 in any mode sets the GO bit and initiates
counter action, Causes the ST2 Flag to be asserted, and generates an interrupt if that function is
enabled. When the GO bit is set in Modes 2 and 3, firing ST2 Causes the Buffer/Preset Register to
be loaded from the counter, the ST2 Flag to be set, and an interrupt to be generated if enabled.

3-5

EXT ST1
LEVEL POT
(5- 20K)

BOARD
HANDLE

OFF
rON
OFF
OFF
OFF
UNUSED

BOARD
FINGERS

NOTE
For proper Operation of external level controls. both RlB and Rl9
on KWVIl- A board must be sel to approximate mid - polnt af
rotation. and the S2 switches must be set as shawn.

Figure 3-3

ll-

4337

Connecting External User-Supplied Slope and Level Controls

3.4 CONNECTORS, SWITCHES, AND CONTROLS
Figure 3- 1 illustrates the location of user connectors, switches, and controls on the component side of
the KWVl I-A board.
3.4.1 40-Pin Connector
Figure 3-4 illustrates the 40-pin connector pin assignments for user inputs and Outputs. These pins may
be connected to the optional H322 Distribution Panel* (see Paragraph 2.4.3.1) for convenient external
user access. The proper Berg-to-Berg cable is the BC08R. The proper Berg to prepared open-ended
cable is the BC042.
3.4.2 FAST ON Connectors (Glock Overflow and ST1 Outputs)
Two FAST ON connector tabs labeled CLK and ST1 are situated in the upper-right corner of the
K WV 1 I-A board (see Figure 3-l). These tabs are electrically in parallel with pins RR (CLK OV L) and
UU (ST 1 OUT L) on the 40-pin connector and are intended to facilitate connections by means of
module jumpers (shown in Figure 2-9) to the clock Overflow and external Start inputs on the ADVl l-A
(see Paragrapgh 2.4.3).
3.4.3 Selector Switches ( Address, Vector, and Slope/Reference Level)
Figure 3-1 identifies three switch Packs (Sl, S2, and S3) that the KWVl 1-A provides to facilitate the
selection of CSR address, vector address, and slope/reference level conditions for Schmitt Triggers
1
-and 2.
1

*T he KWV 11 -A is shipped with decals which permit permanent identification of Signal lines associated with H322 terminals.

3-6

ii
I

POT 2
POT 1
SLOPE 2
SLOPE 1

INN
CLK OV L

&-----ST 2 OUT

ST 2 IN

S T 1 OUT

ST 1 IN

t
BOARD

11-4175

SIDE

Figure 3-4 40-Pin Connector Pin Assignments
3.4.3.1 Address Selection - Switch Pack SI contains 10 Single-pole/single-throw switches that com-

municate with data lines BDAL 1 l-2. The KWVll-A reads the BDAL lines only in response to BBS7
which the processor asserts only for an address of 160000 or higher. For this reason, and because the
KWV 1 1-A transceivers are hard wired to respond only when BDAL bit 12 is set to 1, Si permits
assigning the CSR any address ending in 0 or 4 between 1700008 and 1777748. The recommended
address for the KWVl 1-A CSR is 170420, set as illustrated in Figure 3-5. The BPR automatically
receives the next even address following that assigned to the CSR.
OCTAL

EQUIVALENT

LOGICAL
BIT VALUE

BDAL B I T
POSITION
c-- BOARD HANDLE

BOARD F I N G E R S ------+

NOTE
t

Figure 3-5

Switches may be of either
rocker or slide variety.

11-4176

KWVll-A CSR Address Switches (Set for 170420)
3-7

3.4.3.2 \‘ector Selection - The clock overflow interrupt vector address is set by means of S3, a 7switch pack of which oniy six switches are utilized. These switches communicate with BDAL lines 8-3
and tan be set in increments of 108. The ST2 interrupt vector automatically receives an address that is
four locations higher than the clock Overflow interrupt vector whose recommended address is 0000440
(see Figure 3-6).

LOGICAL
BIT VALUE

BDAL BIT
POSITION
- BOARD HANDLE

BOARD FINGERS NOTE
1. Switches moy be of either
rocker or slide varrety

Figure 3-6

11-4177

KWV l l-A Vector Address Switches (Set for 000440)

Slope and Reference Level Selector Switches and Controls (See Figure 3-7) - Slope and reference level selection for ST1 and ST2 are accomplished by means of S2, a 7-switch pack of which only
switches l-6 are used. Two reference modes are selectable for each Schmitt trigger - one that Picks a
fixed level appropriate to TTL logic, and one that Picks a variable level that permits setting the ST
threshold to any Point between -12 and +12 V.
NOTE
User should take care that both TTL and variable
switches for either Schmitt trigger are not on simultaneously. This condition will do no darnage to components, but produces unpredictable reference levels.
Note also that if no Signal is connected to a Schmitt
trigger input, both threshold switches for that ST
should be open for noise immunity. Alternatively,
ST1 IN and ST2 IN tan be grounded externally.
3.4.3.3

Slope selection is accomplished by separate switches for ST1 and ST2, respectively. When the related
switch is on, the firing Point effectively occurs on the positive slope of the input waveform. When the
switch is Off, the firing Point occurs on the negative slope. (See Figure 3-8.)
3.5

PROGRAMMING

3.51 CSR Bit Assignments
CSR bit assignments are identified in Figure 3-9 and defined in Table 3-l.

3-8

OFF -

/,ON
l

t
BOARD

HANDLE

ST SLOPE 1 (Jl-T)
S T

Figure 3-7

3.5.2

Buffer/Preset

KWVl 1 -A Slope/Reference

SLOPE ZiJI-R)

BOARD FINGERS

Level Selector Switches and Controls

(BPR)

The BPR is a Io-bit, word-oriented, read/write register. Any attempt to write a byte into this register
will result in a whole word being written. In Modes 0 and 1 the program may load it with the 2’s
complement of the number of counts desired before overflow. In Modes 2 and 3 it permits indirect
reading of the clock counter.
3.5.3

Normal

3.5.3.1

Control

Sequences

Mode G (Single Interval) - Control code for Operation in Mode 0 must support the following

sequence:
1.

Control program

Program writes control code into Control/Status Register as indicated in Table 3-2.

If GO bit is set high, KWVll-A responds by loading the Io-bit counter (see Paragraph 3.3.5)
from the BPR and enabling the counter; if GO bit is set low and ST2 GO ENABLE bit is set
high, KWVl 1-A waits for ST2 event, then sets the GO bit and loads and enables the
counter.

Counter increments untif Overflow, then halts (GO bit is cleared)

KWV 1 1-A raises Overflow Flag and issues interrupt if the CSR INT OV bit is set; if interrupt is not enabled, KWVI 1-A waits for program intervention.

Program responds to interrupt or intervenes in consequence of other criteria (e.g., testing the
Overflow Flag or the A/D Done Flag if overflow was used to Start an A/D conversion).
Program reads the CSR, clears the Overflow Flag, and if no counting or mode changes are
required, sets the GO bit or the ST2 GO ENABLE bit to reenter the sequence at step 3.

writes desired count (2’s complement) into BPR (see Paragraph 3.3.5).

3-9

INPUT WAVEFORM
POSITIVE-GOING

NEGATIVE-GOING

THRESHOLD

THRESHOLO

I
I
I
I
OUTPUT

500 ns

--AI- 500 ns

NOTE.
ST is retriggered only after Input woveform
has moved beyond oppaslte threshold and
then again passed selected threshold
( a ) SLOPE SELECTION : SLOPE swltch ON

( Positive Slope)

INPUT WAVEFORM

POSITIVE-GOING

THRESHOLD

SELECTED TRIGGER
LEVEL

NEGATIVE

-GOING

THRESHOLD

ST IS retrlggered only ofter Input waveform
has maved beyond opposite threshald and
then again passed selected threshold.
(b)

SLOPE SELECTION: SLOPE switch OFF (Negative Slope)
11-4549

Figure 3-8 KWVl l-A Slope Selection

Table 3-l
Bit
15 ST2 Flag
Read/Write to 0

14 INT 2
(INTERR UPT
ON ST2)

KWVl 1-A CSR Bit Definitions

Set By/Cleared By
Set by the Fixring of Schmitt Trigger
2 or the setting of the MAINT ST2
bit in any mode while the GO bit or
the ST2 GO ENABLE bit is set.
Cleared under program control.
Also cleared at the “1’‘-going transition of the GO bit unless the ST2
GO ENABLE bit has previously
been set.

Must be cleared after servicing an
ST2 interrupt to enable further
interrupts. When cleared, any
pending ST2 interrupt request will
be cancelled. If enabled interrupts
are requested at the same time by
bits 07 and 15, bit 07 has the higher
priority.

S e t a n d c l e a r e d under program
control.

When set, the assertion of ST2 Flag
will Cause an interrupt. If set while
ST2 Flag is set, an interrupt is
initiated. When cleared, any pending ST2 interrupt request will be
cancelled.

Set and cleared under program control. Also cleared at the “ 1”-going
transition of the GO bit.

When set, the assertion of ST2 Flag
will set the GO bit and clear the
ST2 GO ENABLE bit.

Set when an Overflow occurs and
the Overflow Flag is still set from a
previous occurrence, or when ST2
fires and the ST2 Flag is already
set. Cleared under program control
and at the “1”-going transition of
the GO bit.

This bit provides the programmer
with an indication that the hardware is being asked to operate at a
Speed higher t h a n i s compatible
with the Software.

S e t a n d c l e a r e d under program
control.

For maintenance purposes, this bit
inhibits the internal crystal
oscillator from incrementing the
clock counter. Used in conjunction
with bit 10 below.

Set under program control. Clearing is not required. Always read as
a “0.”

For maintenance purposes, setting
this bit high simulates one cycle of
the internal 10 MHz crystal
oscillator used to increment the
clock counter.

Set under program control. Clearing is not required. Always read as
a “0.”

Setting this bit simulates the firing
of Schmitt Trigger 2. All functions
initiated by ST2 tan be exercised
under program control by using
this bit.

Read/W rite
13 ST2 GO
ENABLE

Remarks

Read/W rite
12 FOR
(FLAG OVERRUN)
Read/W rite

11 DIO
(DISABLE
INTERNAL
OSCILLATOR)
Read/W rite
10 MAINT OSC
Write Only

9 MAINT ST2
Write Only

3-11

Table 3-1
Bit
8 MAINT ST1

KWVl 1-A CSR Bit Definitions (Cont)
- ~~-- Set By/Cleared BI
Remarks

~---

Set under program control. Clearing is not required. Always read as
a “0.”

Setting this bit simulates the Fixring
of STl. All functions initiated by
ST1 tan be exercised under program control by using this bit.

Read/Write to 0

Set each time the counter overflows. Cleared under program control and at the “1”going transition
of the GO bit.

If bit 6 is set, bit 7 set will initiate an
interrupt. Bit 7 must be cleared
after the interrupt has been serviced
to enable further Overflow interrupts. If cleared while an Overflow
interrupt request to the processor is
pending, the request is cancelled. If
enabled interrupts are requested at
the same time by bits 07 and 15, bit
07 has the higher priority.

6 INTOV
(INTERRUPT ON
OVERFLOW)

S e t a n d c l e a r e d under program
control.

When this bit is set, the assertion of
OVFLO Flag will generate an interrupt. Interrupt is also generated if
bit 6 is set while OVFLO Flag is set.
If cleared while an Overflow interrupt request to the processor is
pending the request is cancelled.

S e t a n d c l e a r e d under program
control.

These bits select clock counting rate
or Source.

Write Onlj
7 OVFLO FLAG

Read/Write

5:3 R A T E
Read/Write

Rate

0 0 0 STOP
0 0 1 1MHz
0 1 0 100 kHz
0 1 1 10 kHz
1 0 0 1 kHz
1 0 1 100 Hz
1 1 0 ST1
1 1 1 Line (50/60
2:l M O D E

Set and cleared under
control.

program

Read/Write

OGO
Read/Write

Hz)

2 1
ModeO: 0
0
Mode 1: 0 1
Mode 2: 1 0
Mode 3: 1 1

Set and cleared under program control. Also cleared when the counter
Overflows in Mode 0.

3-12

Setting this bit initiates counter
action as determined by the rate
and mode bits. In Modes 1,2, and 3
it remains set until cleared. In
Mode 0 it clears itself when counter
Overflow occurs. Clearing bit 0
zeroes and inhibits the counter.

INT 2

FOR

MAINT
osc

MAINT
ST1

INT OV

RATE
1

MODE
1

GO
ll-431c

Figure 3-9 CSR Bit Assignments
3.5.3.2 Mode 1 (Repeated Interbal) - Control code for Operation in Mode 1 must support the following sequence:
1.

Control program writes desired count (2’s complement)

into the BPR.

Program writes control code into CSR as indicated in Table 3-3.

If GO bit is set high, KWVI 1-A responds by loading the Io-bit counter from the BPR and
enabling the counter; if GO bit is set low and ST2 GO ENABLE bit is set high, KWVl 1-A
waits for ST2 event, then sets the GO bit and loads and enables the counter.

Counter increments until Overflow.

KWV 11 -A reloads counter from the BPR, reenables the counter, raises the Overflow Flag in
the CSR, and issues interrupt to the processor if interrupt is enabled.

If second Overflow occurs before first is serviced (i.e., if Overflow Flag is still high when next
Overflow occurs), KWVll-A Flag Overrun (FOR) bit in the CSR is set high to alert program that data has been lost.

Program responds to interrupt or intervenes in consequence of other criteria. Program reads
CSR, clears the Overflow Flag, and if no counting or mode changes are required, sets the
GO bit or the ST2 GO ENABLE bit to reenter the sequence at step 3.

3.5.3.3 Mode 2 (External Event Timing) - Control Code for Operation in Mode 2 must support the
following sequence:
1.

Program writes control code into CSR as indicated in Table 3-4.

KWV 1 1-A responds by incrementing the counter (zeroed when the GO bit was cleared) at
the selected rate until the GO bit is set to 0.

ST2 pulse loads current counter contents into BPR, sets the ST2 Flag, and generates interrupt if INT 2 is enabled.

Overflow sets OVFLO FLG high and, if INT OV bit is high, generates interrupt.

Counter continues to increment until processor sets GO bit to 0.

Normally, program enables INT 2 and/or INT OV bits, permitting the processor to synchronize its
operations with the external ST2 events and prevent loss of data by reinitializing the process after step
4.

3-13

Table 3-2

CSR Bit Settings for Mode 0, Single Interlal
Bit Condition
as Written by
Processor

Bit No.

CSR
Name

ST2 FLG

INT 2

Set to 1 by program
ST2 event is desired.

ST2 GO ENA

Set to 1 by program if GO is to be set
by external Signal to ST2. Cleared by
leading edge of GO bit assertion.

FOR

(0)

DIO

MAINT OSC

MAINT ST2

MAINTSTl

OVFLO FLG

(0)

Will be set to 1 by counter Overflow.
Always cleared by leading edge of GO
bit assertion.

INT OV

Set to 1 by program for interrupt on
counter Overflow.

RATE 2

RATE 1

RATE 0

MODE 1

Set by program to 0.

MODE 0

Set by program to 0.

Set by program to 1 unless ST2 GO
ENA is set; remains 1 until written to
0 by program. Cleared when counter
Overflows.

Remarks
Will be set to 1 on ST2 event. Cleared
by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.
if interrupt on

See Table 3- 1.

x = 0 or 1, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.

3-14

Table 3-3

Bit No.

CSR
Name

CSR Bit Settings for Mode 1, Repeated Interval
Bit Condition
as Written by
Processor

Remarks

ST2 FLG

Will be set to 1 on ST2 event. Cleared
by leading edge of GO bit assertion
except when ST2 GO ENA has previously been set.

INT 2

Set to 1 by program
ST2 event is desired.

ST2 GO ENA

Set to 1 by program if GO is to be set
by external Signal to ST2. Cleared by
leading edge of GO bit assertion.

FOR

(0)

DIO

MAINT OSC

MAINT ST2

MAINT ST1

OVFLO FLG

(0)

INT OV

if interrupt on

Will be set to 1 by counter Overflow.
Always cleared by leading edge of GO
bit assertion.
Set to 1 by program for interrupt on
counter Overflow.

RATE 2
RATE 1

See Table 3-l.

RATE 0
MODE 1
Set by program to lg.
MODE 0
GO

Same as for Mode 0, except that bit is
not cleared when counter Overflows.

= 0 or 1, depending on user requirements.
(0; = Automatically cleared by GO bit assertion.

3-15

Table 3-4

CSR Bit Settings for Mode 2, External Event Timing

CSR
Name

Bit Condition
as Written by
Processor

ST2 FLG

Will be set to 1 on ST2 event. Cleared
by leading edge of GO bit assertion
except when ST2 GO ENA has previously been Set.

[NT 2

Set to 1 by program
ST2 event is desired.

ST2 GO ENA

Set to 1 by program if GO is to be set
by external Signal to ST2. Cleared by
leading edge of GO bit assertion.

FOR

(0)

DIO

l-0

MAINT OSC

MAINT ST2

MAINT ST1

OVFLO FLG

(0)

Will be set to 1 by counter Overflow.
Always cleared by leading edge of GO
bit assertion.

INT OV

Set to 1 by program for interrupt on
counter Overflow.

RATE 2

RATE 1

RATE 0

MODE 1

MODE 0

Bit No.

Remarks

if interrupt on

See Table 3-l.

Set by program to 28.
Set by program to 1 unless ST2 GO
ENA is set; remains 1 until written to
0 by program. Cleared when counter
Overflows.

= 0 or 1, depending on user requirements.
(0; = Automatically cleared by GO bit assertion.

3-16

3.5.3.4 Mode 3 (External Event Timing from Zero Base) - Operation is identical to that in Mode 2
except that counter is zeroed after ST2 pulse. Counter continues to increment until GO bit is set to 0.
Note that the interval between two ST2 events may be measured directly in Mode 2 or 3 with processor
assistance if the CSR ST2 GO ENABLE and Interrupt 2 bits are set before the first event and the GO
bit is left clear. Under these conditions, the first ST2 event will set the GO bit (and thus Start the
counting process) and simultaneously issue an interrupt. If the interrupt Service routine now clears the
ST2 Flag bit, the next ST2 event will Cause the BPR to be loaded from the counter in the normal Mode
2 fashion. The choice of Mode 2 or Mode 3 for such measurements will depend on whether or not an
ongoing accumulation of time after the second event is required by the application. If such an accumulation is necessary, Mode 2 is appropriate since the counter is not zeroed after ST2 events.
3.5.4 Programming Example
Record Point in double-precision timeframe for each ST2 event following GO. Program makes use of a
32-bit counter, the low Order bits of which are taken directly from the KWVl 1-A (KWBPR) and the
high Order bits of which are taken from a Software counter (HICNT) that is incremented with each
KWBPR Overflow.
JCLEA~ PSW

MTPS
MOV

wo
IISTZSRV,

MOV

rZOO,@STZPSW

@ST2VEC

ILOÄD ST2 VECTOP
jADDP

#SET UP PSW FOR bT2
ffNTERRUPT (DI8ABLE
MALL

MOV

XOVSRV, @uVVEC

BUBSEQUENT

1INTERRUPTS)
jtOAD O V VECTOR
J ADDR

MOV

@ET UP PSW FOR OV
jINTEPPlJPT (DISABLE
jALL SUBSEQÜENT
flNThPRUPTS1

M;v

CIJKGU:

UBUFFEH, P O

ISET UP POINTER TLI
~6ECINNING OF
#BWFER AREA
@iYOSIT lMH2, MOUE 2 ,

MOV

JLNT OV ENr

INT ST2 EN,
GO INTO KWCSH
jPOtc INTERRUPT
JAND

CMNT:

WAlT

JU OVFLO OR ST2
JIS CCR BIT SET?
JN~-I, CONTINUE
J XES, SERVICE F‘LAc;

Pl’1
EEQ

JMP
OVSPV:

#UVEkRUrd CONDITIOtU

E3f-r
BEQ
TST
BPL

;fS S't2 FLAG SET?
JbO? COt*TIhUE
JDiü ST2
OCCUP PEboHE U V ?
Jido,

BHAtvCH

POV
MOV
BfC

Jx&S,

SERVICE

; ACKNCJWLEDGE
JOCC~~+RE~CE

ST2

FIRST

STZ

(example continued on next Page)
3-17

25:

IbC

HlCr,T

RT1
ST2SRV:

FOHSHV:

$32 @IT oVEHFL~~
;uCCUPPLD

KwCSl?:

KkJBPtJ:
OLFVEC:
s1’2vt%cr
fiIcrLT:
dUFF’EP t

;xxxXaLFhGTH
8 Rur F-EH

3-18

OP ROSULT

CHAPTER 4
AAVll-A

DIGITAL-TO-ANALOG

CONVERTER

4.1 GENERAL DESCRIPTION

The AAV l l-A is a 4-channel digital-to-analog converter module for use on the bus of the LSI- 11
processor. The unit is made up of control and interfacing circuitry, four D/A converters, a dc-dc
converter to provide power to the analog circuits, and a voltage reference. Esch channel provides 12
bits of resolution. Esch has its own holding register which tan be separately addressed and tan be
written and read in either word or byte format. In addition, bits O-3 of the fourth holding register are
brought to the I/O connector for use as a 4-bit digital output register.
Jumpers permit manual selection of voltage range and operating mode (bipolar or unipolar).
4.2

SPECIFICATIONS (@ 25” C unless otherwise specified)

Number of D/A Converters

Digital

Input

12 bits (binary encoded for unipolar mode, offset binary
encoded for bipolar mode)

Digital

Storage

Read-write, word or byte operable, Single buffered

Analog Output Voltage Range
(j umper selected)
Digital Output Characteristics
(DAC 3 Holding Register
Bits 3:0)

~l~2.56 V, f5.12 V, f 10.24 V bipolar; 0 V to +5.12 V, 0 V to
+ 10.24 V unipolar
Source: 5.2 mA @ 2.4 V
Sink: 16 mA @ 0.4 V

Resolution

1 part in 4096

Warm-Up Time

5 minutes minimum

Gain

Accuracy

Adjustable (factory-set for bipolar k5.12 V; selection of other
ranges may require recalibration)

Gain

Temperature

Coefficient

10 ppm per degree C, maximum

Offset

Temperature

Coefficient

20 ppm of full scale range per degree C, maximum

Linearity

f 1/2 LSB maximum non-linearity

Differential
Output

Linearity

Impedance

f 1/2 LSB, monotonic
1 Q maximum at DAC output; 4 62 maximum at end of BCOSR
8 ft cable
4-l

Drive Capability

f 5 mA maximum per converter

Slewing Speed

5 VIP

Rise and Settling Time
(to 0.1% of final value)

4 ps: 8 ps with 5000 pF load in parallel with lk fl

Power Consumption
(from LSI-1 1 bus power supply)

5 V &5% @ 1.5 A, 12 V @ 0.4 A

Environmental

Ref: DEC STD 102, class C

Packaging

One quad module

Bus

1 bus load

4.3 FUNCTIONAL DESCRIPTION
Figure 4-l illustrates the AAVl 1-A in block diagram form.
4.3.1 Bus Control
The logic associated with the bus control section maintains proper communications protocol between
the processor LST- 11 bus and the AAVl 1-A. This logic generates and monitors the bus Signals
involved during data transfers between the processor and the AAVl l-A, permitting the AAVl l-A to
recognize when it is being addressed by the processor (address defined by setting on the Address
Switch Pack), to accept input data from the processor, and to output data to the processor.
4.3.2 Control Logic
The AAVl 1-A has no Control/Status Register. The four digital-to-analog converters continually generate voltages at their Outputs that reflect whatever digital values have most recently been written into
their respective holding registers. The role of the control logic is to make the necessary discriminations
between requests to Change the state of the holding registers (i.e., to write into the holding registers),
and requests to put the holding register contents onto the BD lines where they tan be picked up
through the transceivers by the processor.
4.3.3 DACs 0, 1, and 2
Digital-to-analog conversion functions are performed in each of the four AAVl l-Achannels by identical circuits:

A holding register which stores the digital value output by the processor
0

A digital-to-analog converter (DAC) proper which generates a current that is a function of
the holding register value and of the mode/level jumper conditions

An amplifier that translates the current into a proportional voltage, provides a low output
impedance for the channel, and permits adjustment of Signal offset.

4.3.4 DAC 3
DAC 3 is identical to DACs 0, 1, and 2 except that Holding Register bits O-3 are routed to the I/O
connector as well as to the DAC. This arrangement permits these bits to be routed to external equipment that requires binary control Signals at programmable intervals. Control data in these bit positions affects any 12-bit D/A conversion that they coincide with, but since they involve the least
significant bits of the word, the worst-case error is less than 0.5%. Consequently, DAC 3 tan be used as
a 12-bit DAC or as an g-bit DAC plus four output bits for CRT Intensify, Store, Non-Store, Erase,
etc.
4-2

rI
I
I
I

r
I
I

I
I I

- - 11

G,\
a
I Cuds I
2

1I
I I

11;
l -v - I I
L2 - - J I
I*

k
cc
= k-- -z=

B-B--

1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
J

-----

I
I
I
I
I
I
I
I
I
I
I 0E
I 50
I
,s
sne

4-3

II-ISl

I
I
- -J

4.4 CONNECTORS, SWITCHES, AND CONTROLS

Figure 4-2 illustrates the location of user connectors, switches, and controls located on the component
side of the AAV l l-A board.

DACO

DACZ

DAC 1

DAC3

/\ /\/\\

R46
(OFFFET)

R34
(GAIN)

R47
(OfFSET)

R35 R36
R48
R37 (GAIN)
\
(GAIN)(GAIN) (OFFSET)
R49 (OFFSET)

w5
w3
w7
WlO
wi2
Wil
o----o--- W6
Wl3
w14
w4
wa
w9
L
Y
MODE /LEVEL STRAPS

W18

w15

w17

W16

BIT 11

BIT 3
Si

‘u
(ADDRESS)

Figure 4-2
4.4.1

40-Pin

AAVl 1-A Connectors, Switches, and Controls

Connector

Figure 4-3 illustrates the 40-pin connector pin assignments for user Outputs. These pins may be connected to the optional H322 Distribution Panel* (see Paragraph 2.4.3.1) for convenient external User
access. The proper cable for this purpose is the BC08R. Also available is a Berg to prepared openended cable, the BC04Z.
Either a VR14 or VR17 CRT may be interfaced to the H322 via a user-created cable terminating in a
24-pin Amphenol, or equivalent, male plug (DEC #12-03466-00). A user-created cable may be connected to other types of CRT Systems using a 25pin connector such as a male DB25P type plug (DK
# 12-05886-00).

* The AAVI 1-A is shipped with decals which permit permanent identification of Signal lines associated with H322 terminals.

4-4

BIT 3 OUT
BIT 2 OUT
DAC 1

HQ GND

BIT 1 O U T

DAC 2

HO GND

B I T 0 OUT

DAC 3 H Q G N D

DAC

3 OUT

-15V T E S T

DAC 2 OUT

+15V T E S T

DAC 1 OUT

DAC 0 H O G N D

DAC 0 OUT

B O A R D SIDE
lt-43t4

Figure 4-3

40-Pin

Connector Pin Assignments

The BCO4Z Signal lines may be connected to user-selected pins on a male or female connector. A
female 25 pin connector of the DB25S type (DEC #12-09326-00) may be used for general purposes. A
male 25pin connector of the DB25P type (DEC #12-05886-00) will interface several popular CRT
Systems to the AAVl1. Either a VR14 or VR17 CRT may be interfaced by means of a 24-pin Amphenol, or equivalent, male plug (DEC #12-03466-00) to the BCO4Z. Both the AAVl 1 and selected CRT
must be set up and adjusted for electrical compatibility. The CRT manual should define appropriate
connector pins for each AAVl1 Signal line. Appropriate Software will be necessary to control a CRT.
4.4.2 Address Switches

Figure 4-2 identifies the location of S 1, a switch pack containing 10 Single-pole Single-throw switches (1
unused) which, when set, transmit 0 logic levels to the compare inputs of the transceivers. Whenever
the AAVl 1-A sees BBS7 transmit a logical 1 (indicating that the processor has placed an I/O device
address on the bus), the transceivers compare the Pattern created by the switches with that appearing
on Bus Data/Address (BDAL) lines 3-l 1. If the Patterns match, the processor is addressing the
AAV 11 -A, and the latter prepares to load the DAC holding register identified by decoding bits 1 and 2
of the address word as defined in Figure 4-4.
Since the AAVll-Amakes the comparison only in response to BBS7 (which the processor sets to 1
only in response to an address of 160000 or higher) when address line BD 12 = 1, SI permits assigning
the four DACs any contiguous set of four even word addresses between 170000 and 177770. The
recommended setting for SI on the first AAVl 1-A is 170440, illustrated in Figure 4-5. Since LSI-11 bus
address assignments for the AAVl 1-A extend from 170440 to 170476, up to four AAVl l-As tan be
accommodated on the same processor.

4-5

AAVll-AA D D R E S S W O R D

= 0: WORD OR LOW BYTE
“ 0 = 1 : HIGH BYTE
“ 0

“2

DAC

0
0
1
1

0
1
0
1

0
1
2
3

ADDRESS

DAC

MODE

170440
170441
170442
170443
170444
170445
170446
170447

0
0
1
1
2
2
3
3

WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE
WORD OR LOW BYTE
HIGH BYTE
11-4313

Figure 4-4

AAV l l-A Address Decoding
OCTAL EQUIVALENT

t
LOGICAL
BIT VALUE
BOARD

HANDLE

BOARD

FINGERS

BDAL BIT
POSITION
11-4172

Figure 4-5

AAVl 1-A Address Switches (set for 17044n)

4.4.3 Mode/Level Selector Jumpers
As shipped from the factory, the AAVll-Ais set for bipolar Operation between -5.12 and +5.12 V.
Unipolar Operation and Operation with other voltage ranges tan be achieved by proper changes in the
mode/level jumpers (illustrated in Figure 4-2). See AAVll-AInstallation and Service chapter for
details.
4.5 INTERFACING TO OUTPUT DEVICES
4.5.1 Ground Connections
Analog output devices such as oscilloscopes may be either grounded or floating. If the oscilloscope is
grounded, either through its power plug or through contact between its Chassis and a grounded cabinet, the oscilloscope ground should not be connected to any of the AAVl l-A ground Pins. Doing so
may result in a ground loop which will adversely affect scope control results as well as any ADVl l-A
operations. If the oscilloscope is floating, its ground should be connected to the AAVll-Alogic
ground, pins L, N, R, or T of the Berg connector. Note that the foregoing assumes that the Computer
power supply ground is connected to power line (earth) ground. If continuity Checks reveal no such
connection, attach a length of 12-gauge wire between the power supply ground and a convenient Point
associated with earth ground.

4-6

(

Oscilloscope X and Y inputs may be either differential or Single-ended. Differential inputs should be
driven as in Figure 4-6.

Figure 4-6

Connection to Oscilloscope with Differential Input

When oscilloscopes with Single-ended inputs are involved, the AAVl l-A analog grounds (Pins UU
and HH) are not used. Return path for X and Y Signal currents is through ground for a grounded
oscilloscope or through logic ground (Pins L, N, R, or T) for a floating oscilloscope. Since the
grounded, Single-ended oscilloscope sees an input voltage which is the sum of the AAVll-Aoutput
and the ground differente voltage between the oscilloscope and the AAVl l-A, noise and line frequency errors may be minimized by plugging the scope into an ac socket as close as possible to the comPuter. Running Single-ended scopes in a floating configuration will eliminate noise and line frequency
errors which are due to ground voltage differentes.
, 4.5.2 Twisting
The effect of magnetic coupling into the scope input lines tan be minimized for a differential-input
scope by running the AAV 11 -A output and its return line in a twisted pair. No benefit is derived fror-n
a twisted pair with a Single-ended scope input.
4.5.3 Shielding
The effect of electrostatic coupling into the scope input lines tan be minimized by shielding the input
lines from AAVl 1-A to the scope. The shield should be connected to ground at one end only. Ground
ing the shield at both ends may result in a ground loop which will adversely affect scope control results
and any ADVl l-A A/D operations.
4.5.4 Drive Capability
Careful selection of cabling is essential. The D/A Outputs are capable of driving a maximum of 5000
pF. Output impedance is 1 ohm. Output current limit is 5 mA.
4.6 PROCRAMMING
All four DAC holding registers are automatically set to zero on System initialization. This produces
-5.12 V at the DAC Outputs when the mode/level jumpers are connected as delivered from the factory.
Any holding register value remains in effect until changed by the processor in response to a program
instruction. Coding to the D/A converters is offset binary for bipolar Operation and straight binary for
unipolar Operation. Offset binary defines 0 as maximum negative voltage, mid-Point (i.e., 40008 for the
12-bit AAV 1 1-A) as 0 V, and all 1s (7777*) as maximum positive voltage. These relationships are
illustrated in Table 4- 1.
4-7

Table 4-l AAVll-A

Digital-to-Analog Conversions*

Bipolar
1 nput Code
(octal)
-2.56
-2.55875
-0.00125
0.0
+0.00125
+2.55875
*

Unipolar

zks.12 v
(Volts)

f 10.24 V
(Volts)

0 v to +5.12 v
(Volts)

0 V to +10.24 V
(Volts)

-5.12
-5.1175
-0.0025

-10.24
-10.235
-0.005

+o.o

0.0

+0.0025
+5.1175

0.0

+0.005
+10.235

+0.00125
+2.55875
+2.56
+2.56125
+5.11875

+0.025
+5.1175
+5.12
+5.1225
+10.2375

Offset binary for bipolar, straight binary for unipolar operating modes. Conversions may be made between 2’s
complement signed binary and offset binary numbers by subtracting 40008 from the 2’s complement number
(or adding 40008 to the offset binary number) and using only the low Order 12 bits of the result.

? Note that in all ranges, actual maximum positive voltage output is 1 LSB less than nominal maximum positive
output.

4-8

CHAPTER 5
DRVll PARALLEL LINE UNIT

5.1 GENERAL DESCRIPTION

The DRVl 1 is a general-purpose interface unit used for connecting parallel-line TTL or DTL devices
to the LSI- 11 bus over up to 25 feet of cable. It permits program-controlled data transfers at rates up to
44K words per second (with optimized programming) and provides LSI-11 bus interface and control
logic for interrupt processing and vector generation. Data is handled by 16 diode-clamped input lines
and 16 latched output lines. Device address is user-assigned and Control/Status Registers (CSR) and
Data Registers are compatible with ‘PDP-11 Software routines.

BDALO - 15L

)

OUT

DROUTBUF

0-15

BIAKO L

L-

tOs: AFROM

- DEVICE
LOG IC

BSYNC L

5 L
EYBTOL
BDIN L
BDOUT L
BRPLY L
BINIT L
BDAL 0-15 L

t
/

DRINBUF
1

Figure 5- 1

IN 0-15
L

DRVl 1 Parallel Line Unit

5.2 JUMPER-SELECTED ADDRESSING AND VECTORS
5.2.1

Locations

Jumpers for device address and vector selection are provided on the DRVl 1 as shown in Figure 5-2.
Jumpers are installed at the factory for address 167770 (DRCSR) and vectors 300 (interrupt A) and
304 (interrupt B). These tan be tut or removed by the user to program the module for his System
application, as described in the following Paragraphs.

5-1

r VECTOR
- - -JUMPERS
- --l
v 4 1 v5-

---z”lJ

r
- - - - - - - i
, ADDRESS JUMPERS ,
I
I
1

A 3 A4A5A6A7-

-A9
’
-Al0
1
A
l
l
A
l
2

v 3

SLl .si SL2
C-J----+c---Cl
,’ :
OPTIONAL EXTERNAL
CAPACITOR
’ (SEE
PARA.5.3.6)

LA2YrL----_1

M7941 ETCH REV C

CP-f809

Figure 5-2 DRVll Jumper Locations
5.2.2 Addressing
Jumpers involved with addressing include A3 through A12. Only address bits 03 through 12 are programmed by jumpers for DRVl 1 addressing, producing the M-bit address word shown in Figure 5-3.
The appropriate jumpers are removed to produce logical 1 bits; jumpers are installed to produce
logical 0 bits.
5 . 2 . 3 Vectors
Jumpers involved with vector addressing include V3 through V7. Only vector bits 03 through 07 are
programmed by the jumpers for DRVl 1 vector addressing, producing the 16-bit word shown in Figure
5-4. The appropriate jumpers are removed to produce logical 1 bits; jumpers are installed to produce
logical 0 bits.
5-2

YTE SELECT
- h i q h byte(B-15)
O=lowbyte(O-7)

BBS7 L

OOX = DRCSR
01 X = DROUTBUF
1OX = D R I N B U F
11 X = NO RESPONSE
CP 18lL

ADDRESS JUMPERS.
INSTA LLED =0
REMOVED = 1

Figure 5-3 DRVl1 Device Address

1
b
>
L

u)
>

In
>

1
rf
>

VECTOR
JUMPERS:
INSTALLED=O
REMOVED = 1

Figure 5-4

L
cr)
>
/

;;;%l%
O=REQ A
1 =REQ B

DEVICE

CP-1745

DRVl 1 Vector Address

5.3 INTERFACING TO THE USER’S DEVICE
5.3.1 General
Interfacing the DRVl 1 to the user’s device is via the two board-mounted HS54 40-pin male connectors. Pins are located as shown in Figure 5-5. Signal pin assignments for input interface 52 (connector no. 2) and output interface Jl (connector no. 1) are listed in Table 5-l. The proper Berg-to-Berg
cable is a BC08R. The proper Berg to open-ended cable is a BCO4Z. Connection to the DRVlltan be
made through the H322 Distribution Panel (see Figure 2-8). This unit is provided with decals, which
when applied according to instructions on the decal sheet, identify the H322 screw terminals with
respect to the associated pins on the DRVl 1 Berg connectors (A, B, UU, VV, etc.). Spate is provided
on the decal for specific user identification. Note that DRVl l/H322 terminal relationships assumed
by the decal sheet rest on connection of the BCOSR cable so that stamped labels on female cable ends
match embossed labels on male connectors - A/B to A/B, UU/VV to UU/VV. This normally means
that any “this side up” labels face away from the board on which the male connector is mounted.
Esch BCO4Z cable from a DRVl 1 may be terminated in a female 25-pin connector such as a DB25S
type (DEC #12-09326-00) socket. The user may assign the Signal and ground lines from the BC04Z to
specific connector Pins. User apparatus may be connected into the socket by means of a male 25-pin
connector such as a DB25P type plug (DEC #12-05886-00).
5.3.2 Output Data Interface
The output interface is the 16-bit buffer DROUTBUF. It tan be either loaded or read under program
control. When DROUTBUF is loaded by the CPU, the NEW DATA READY H 300 ns pulse is
generated to inform the user’s device of the data transfer. In Order to allow data to settle on the
interface cable, the trailing edge of this positive-going pulse should be used to strobe the data into the
user’s device. The System initialize Signal (BINIT L) clears DROUTBUF. When an output line is set to
logical 1, the TTL output is high (2 2.7 V); when an output is set to logical 0, the TTL output is low
(< 0.5 V).
5-3

Hf354
CON NECTOR

Figure 5-5

Jl or 52 Connector Pin Locations

All output Signals are TTL levels capable of driving five unit loads (8 mA sink** @ 0.5 V, 400 PA
Source*** @ 2.7 V) except for the following:
NEW DATA READY = 10 unit loads

= 16 mA sink** @I 0.4 V, 400 PA
Source*** @ 2.4 V

INIT (Initialize)* = 10 unit loads/connector
DATA TRANSMITTED = 30 unit loads

= 48 mA sink** @ 0.4 V, 5 mA
Source*** @ 2.7 V

*Common sig na1 on both connectors.
** Sink refers to current from external +5 V supply through load to output line when output is low.
***Source refers to current from output line through load to ground when output is high.

5-4

Tabie 5-l

DRVll Input and Output Signal Pins*

Inputs
Signal

Connectoi

IN00
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
REQ A
REQ B

52
52
J3
52
52
32
52
52
52
52
52
52
52
52
52
52
Jl
J2

TT
LL
l-1. 1‘
BB
KK
HH
EE
cc
Z
Y
w
V
U
P
N
M
LL
S

OUTOO
OUT01
OUT02
OUT03
OUT04
OUT05
OUT06
OUT07
OUT08
OUT09
OUT10
OUT1 1
OUT12
OUT13
OUT14
OUT15
NEW DATA RDY*
DATA TRANS*
CSRO
CSRl
INIT
INIT

Connector

Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
Jl
52
52
Jl
Jl
52

K
NN
U
L
N
R
T
W
X
Z
AA
BB
FF
HH
JJ
vv
C
K
DD
P
RR, NN

*Pulse Signals, approximately 300-ns wide. Width tan be changed by User.
53.3 Input Data Interface
The input interface is the 16-bit DRINBUF read-only register, comprising gated bus drivers that
transfer data from the user’s device onto the LSI-11 bus under program control. DRINBUF is not
capable of storing data; hence the user must keep input data on the IN lines until read by the LSI- 11
microprocessor. When it has read the data, the DRVll generates a positive-going 300-ns DATA
TRANSMITTED H pulse which informs the user’s device that the data has been accepted. The trailing edge of the pulse indicates that the input transfer has been completed.
All input and request Signals are one Standard TTL unit load; inputs are protected by diode clamps to
ground and +5 V. A +2.7 V to +5 V input is read as logical 1; 0 V to 0.5 V as logical 0.
5.3.4 Request Flags
Two Signal lines (REQ A H and REQ B H) tan be asserted by the user’s device as flags in the DRCSR
werd. REQ B is available via connector no. 2 and tan be read in DRCSR bit 15. REQ A is available
via connector no. 1; it tan be read in DRCSR bit 7. Two DRCSR interrupt enable bits, INT ENB A
(bit 6) and INT ENB B (bit 5), allow automatic generation of an interrupt request when their respective REQ A or REQ B Signals are asserted. Once the user’s request Signal has been asserted (logical0to
logical 1 transition), it must remain asserted until the CPU completes interrupt processing. At this
time, DATA TRANSMITTED or NEW DATA READY Signals (see Paragraphs 5.3.2 and 5.3.3) tan
be used to cancel the request. Note that Request A has a higher priority than Request B, and that each
of the interrupt enable bits tan be set or reset under program control.
* Ground pins for connector Jl: J, M, S, V, Y, CC, EE, KK, MM, PP, SS, UU. Connector 52: J, L, R, T, X, AA, DD, JJ,
MM, PP, SS, UU.

5-5

5.3.5

Initialkation

The BINIT L processor-generated initialize Signal is applied to DRVl 1 circuits for interface logic
initialization. It is also available to the user’s circuits via connectors Jl and 52 as follows:
Connector/Pin

Signal

Jl/P
J2/RR
JZ/NN

AINIT H
BINIT H
BINIT H

An active BINIT L Signal will clear the following: DROUTBUF data; DRCSR bits 6, 5, 1, 0; bits 16
and 7 (when the maintenance cable is connected); and Interrupt Request and Interrupt Acknowledge
flip-flops.
5.3.6

NEW DATA READY and DATA TRANSMITTED Pulse Width Modification

An optional capacitor tan be added by the user to the DRVll module to extend the pulse width of
both the NEW DATA READY and DATA TRANSMITTED pulses. The module without external
capacitance (as shipped) will produce 300 ns pulses. The capacitor tan be added in the location shown
in Figure 5-2 to produce the approximate pulse widths listed below.
Optional External
Capacitance (pF)

Approximate
Pulse Width (ns)

None
1200
1800
6000
5.4
5.4.1

300
500
600
1200

PROGRAMMING
Addressing

Addresses for the DRVl 1 tan range from 16oooO
address the desired DRVl 1 register as follows:
Address*

Device

1 xxxxo
1 xxxx2
1xxxx4

DRCSR
DROUTBUF
DRINBUF

through 17777Xs. The least significant three bits

Addresses 177560- 177566 are reserved for the console device and should not be used for DRVl 1
addressing. The following address assignments are normally used:
First DRVll
DRCSR = 167770
DROUTBUF = 167772
DRINBUF = 167774
Second DRVl 1
167760 to 167764
Third DRVll
167750 to 167754

*Address IXXXXO

will not produce a response from the DRVl 1.

5-6

Second DRVl1
167760 to 167764
Third DRVl 1
167750 to 167754
5.4.2 Interrupt Vectors
Two interrupt vectors are jumper-selected in the range of 0 through 37Xs. The least significant
bits identify the interrupting function.

oooxxo

three

Interrupt A
Interrupt B

oooxx4

Vectors 60 and 64 are reserved for the console device and should not be used for DRVllvectors.
5.4.3 Word Formats
The three word formats associated with the DRVl 1 are shown in Figure 5-6 and are described in Table
5-2.
5.4.4 I/O Timing
I/O transfers through the DRVll occur as illustrated in Figure 5-7.

DRCSR

REOUEST B
(READ ONLY)

REQUEST A
INT EN8 A
(READ 1 WRITE)

CSRO
(READ/ WR ITE)
0

DROUT BUF

DATA OUT
(R EAO/WRITE)
15

DRINBUF
V

DATA IN
(READ ONLY)
CP-1746

Figure 5-6

DRVl 1 Word Formats

5-7

Table 5-2 Werd Formats

Bit(s)

Function

REQUEST B - This bit is under control of the user’s
device and may be used to initiate an interrupt sequence or to generate a flag that may be tested by the
program.
When used as an interrupt request, it is asserted by
the external device and initiates an interrupt provided
the INT ENB B bit (bit 05) is also set. When used as a
flag, this bit tan be read by the program to monitor external device Status.
When the maintenance cable is used, the state of this
bit is dependent on the state of CSRl (bit 01). This
permits checking interface Operation by loading a 0 or
1 into CSRl and then verifying that REQUEST B is
the Same value.
Read-Only bit. Cleared by INIT when in maintenance
mode.

14-08
07

Not used . Read as 0.
REQUEST A - Performs the Same function as REQUEST B (bit 15) except that an interrupt is generated
only if INT ENB A (bit 06) is also Set.
When the maintenance cable is used, the state of REQUEST A is identical to that of CSRO (bit 00).
Read-Only bit. Cleared by INIT when in maintenance
mode.

INT ENB A - Interrupt enable bit. When set, allows
an interrupt request to be generated, provided REQUEST A (bit 07) becomes set.
Can be loaded or read by the program (read/write
bit). Cleared by BINIT.

04-02

INT ENB B - Interrupt enable bit. When set, allows
an interrupt sequence to be initiated, provided REQUEST B (bit 15) becomes Set.
Not used. Read as 0.
Can be loaded or read by the program (read/write
bit). Cleared by INIT.

5-8

Table 5-2

Word Formats (Cont)

Word

Bit(s)

Function

DRCSR

CSRl - This bit tan be loaded or read (under program control) and tan be used for a user-defined command to the device (appears only on Connector No. 1).
When themaintenancecable is used, setting or Clearing
this bit Causes an identical state in bit 15 (REQUEST
B). This permits checking Operation of bit 15 which
cannot be loaded by the program.
Can be loaded or read by the program (read/write
bit). Cleared by INIT.

CSRO- Performs the same functions as CSRl (bit 01)
but appears only on Connector No. 2.
When the maintenance cable is used, the state of this
bit controls the state of bit 07 (REQUEST A).
Read/write bit. Cleared by INIT.

DROUTBUF

15-00

Output Data Buffer - Contains a full 16-bit word or
one or two 8-bit bytes: High Byte = 15-8; Low Byte
= 7-o.
Loading is accomplished under a program-controlled
DATO or DATOB bus cycle. It tan be read under a
program-controlled DATI cycle.

DRINBUF

15-00

Input Data Buffer - Contains a full 16-bit word or
one or two 8-bit bytes. The entire 16bit word is read
under a program-controlled DATI bus cycle.

5-9

- <dato
- = I>-

DRINBUF

<dato=l>

<IN00:I N 1 5 > a r e s e t /reset by the
User; the dato must remain stable untrl
trailrnq e d g e a f D A T A TRANSMITTED

L - - - - - - - - - - - - - - - - - s . = . . - - - - - -

<dato
- -=0>
-

2 300 ns

DATA TRANSMITTE0
Pulsed by DRV 11 when the
lt /O3 reads dato fram the DRVll

READ

DATA

FROM

L TvAILING
I
EDGE

BUFFER -l

REQUEST

Set by user when ready ta transmit new
dato to the 11/03, reset by user upon
trarlrng edge of DATA TRANSM ITTED

THE INTERRUPT

REQUEST

I
DRCSR
<bit 5 > Interrupt Enable B
Set by user to allow Interrupt-driven
dato transfer

I
l

DRCSR
< brt 15>Request B flog
Indrcates state of REQUEST A Iine
11-4588

<dota = 1 >
--es----------

DROUTBUF
<OUT00. OUT 15> are set /reset
by the DRV 11 under control of
t h e lt/03

<dato = 0>
l

<dato = 0>
_--------m-s

NEW DATA READY
Pulsed by DRVll when the
lt/ 03 writes dato ta the DRV 11

I
REQUEST

Set by user when ready for new dato
fram 11 /03,reset by user upan
trarlrng edge of NEW DATA READY

DRCSR
< bit 6> Interrupt Enable A
Set by user ta ollow Interrupt-driven
dota transfer

I
I

l
I

DRCSR
< bit 7 > Request A flog
Indicotes state of REQUEST A Irne

Figure 5-7

DRVl 1 Interface Signal Sequence

5-10

CHAPTER 6
ADVll-A, KWVll-A, and AAVll-A MAINTENANCE

6.1 MAINTENANCE PHILOSOPHY
Digital logic circuitry in the ADVl I-A, KWVI l-A, AAVl I-A, and DRVll is to be repaired in the
normal manner. Analog circuitry, however, is to be repaired only at the factory. If any analog failures
occur in the field, modules are to be board-swapped and returned to the factory for repair. Installations performed by DEC include installation of DEC-supplied equipment only. The customer is
responsible for wiring from his equipment to the H322 Distribution Panel or to the end of the DECsupplied cable.
6.2
6.2.1

ADVll-A

ANALOG-TO-DIGITAL

CONVERTER

Installation

6.2.1.1 Location - The ADV l l-A is a Single-module Option which interfacesio an LSI-11 or PDP1 1/03 through one of the quad locations in the LSI-11 backplane or in an expander box. Within the
constraints imposed by the LSI-11 bus structure (refer to the LSZ-11, Microcomputer Handbook - EB06583 76 09/53) the unit may be mounted in any available location and will operate within specifications, regardless of proximity to the processor, memory, or other DEC Options. Where circumstances
permit, however, analog Performance may be improved beyond specification levels by installing the
unit away from the processor, memory modules, or other noise-producing Options. Note that priority
transfer requires that no empty unstrapped locations exist in the backplane between the processor and
any device that communicates with it.

6.2.1.2 Address and Vector Selection - Select and set CSR and Vector addresses as indicated in Paragraph 2.4.3.4. Note that where more than one ADVl l-A is involved, CSR addresses must be four
locations apart (e.g., 170400, 170404, 170410, etc.). Vector addresses must be 108 locations apart (e.g.,
000400, 000410,000420, etc.). Remember to reinstall any covers removed from switch Packs Sl and S2.
6.2.1.3 Board Insertion - Select a quad location, and making sure that the keyed edge connector
matches the physical configuration of the terminal block, apply firm pressure alternately to the extractor handles near the opposite corners of the board until it is squarely and fully seated in the connector.
6.2.1.4 Test Connector - DO not insert I/O cables into the Berg connector at this Point. Instead,
insert the 7012894 test connector, which establishes the conditions required by the ADVl 1
Wraparound Test - that is, all channel inputs are grounded except 1, 2, 3, and 17, with internallygenerated +4.5 V Signal on channel 1, -4.5 V Signal on channel 2, ramp Signal on channel 3, and
Provision for external reference voltage on channel 17.
6.2.1.5 Shields - Install the 1700021-02 electromagnetic
shields on both sides of the ADVl l-A.
Shields are insulated on both sides and physically separate the ADVl l-Afrom adjacent modules but
are not electrically connected to the System.

6-l

6.2.1.6

Acceptance - Conduct an acceptance test as specified in A-SP-ADVl 1A.

6.2.1.7 Final Connections
Cables
Remove the 7012894 test connector and install the BCOSR cable (ADVll-A to H322 Distribution
Panel) or the BC04Z cable (ADVl 1 -A to user devices) in the ADVl 1-A Berg connector. Connect
BC08R at both ends so that the stamped labels on the female cable ends match the embossed labels on
the male connectors - A/B to A/B, UU/VV to UU/VV. This normally means that any “this side up”
labels face away from the board on which the male connector is mounted.
KOTE
The BC08R cable is symmetrically wired but for several reasons is unsymmetrically
labeled. That is,
wires identified as A and B on one end are identified
as UU and VV on the other end.

To simplify System relationships, the H322 PC
board compensates for this inversion on the PC
board that distributes Berg connector Signals to front
Panel screw terminals. For this reason, the user tan
connect both ends of the BCOSR according to the
labels, A/B to A/B and UU/VV to UU/VV. So connected, Signals from the ADVll-A will properly
appear at front Panel terminals which have been
labeled according to the instructions on the ADVl lA decal sheet. Esch BCO4Z cable from an ADVll-A
may be terminated in a female 25pin connector such
as a DB25S type (DEC 12-09326-00) socket. The
user may assign the Signal and ground lines from the
BC04Z to specific connector Pins. User apparatus
may be connected to the socket by means of a male
25pin connector such as a DB25P type plug (DEC
12-05886-00).

If KWVI 1-A is present, connect Faston terminals, as described in Paragraph 2.4.3.2.
Manual Voltage Control
Applications which require variable dc voltages to be applied to one or more channels of the ADVl lA tan be implemented by the circuit illustrated in Figure 6- 1. Note that the H323-B Potentiometer Box
may no2 be used with the ADVll-A.
6.2.2 ADV l l-A Circuitry
The digital interface and control logic of the ADVl 1-A conforms in general to Standard DEC practices
and should be understandable to qualified technicians who have access to ADVl 1-A print sets and are
familiar with Overall ADVl 1-A functions as described in Chapter 2. Since the analog power supply
and the A/D conversion sections involve some nonstandard circuits, they are discussed below.
6.2.2.1 ADVl l-A

Analog Power Supply

General
The f 15 V power for the analog circuits is derived from a dc-dc converter which consists of three basic
sections: a 12 V power switch, positive and negative voltage doubler diode-capacitor banks, and a dual
tracking voltage regulator. Output jumpers (W 1 and W2) are provided to permit removing the load for
troubleshooting
purposes.
6-2

CH RET
NOTE
I

Value of R In kilohms tan be calculated as follows
R=

VB - 6
Kfi
2 . 5 (N+2)

(1)

Where N = Number of channel pots
Current drain from battery in milliamps when R IS
selected wtth equation ( 1 ) tan be calculated as
follaws :
1 bo+ = 2 5

(N +2) mA

(2)
11-4487

Figure 6- 1

Battery-Operated Potentiometer Box for ADVl l-A A/D Converter

TP3
p,,
+ 15v
WI
SW A
POWER
SWITCH

REGULATOR

SW B
-

TP2

.--Y..-r-15v

. <

w2
!l-

Figure 6-2

4478

Analog Power Supply Block Diagram

Power Switch
Transistors Q15 and Q 16 constitute the output Stage of the 12 V power switch and provide a 0 V to
+ 12 V switching Signal, which is derived from the SW A and SW B Signals, and which drives the
voltage doubler diode-capacitor banks. Since saturated transistor switches turn on faster than they
turn Off, an idle is included (see Figure 6-3) to ensure that Q15 and Q16 are never on at the same time.
Voltage Doublers
The basic voltage doubler consists of a Charge transfer Stage (DA and CA in Figure 6-4) and a Charge
storage Stage (DB and CB in Figure 6-3). When the power switch output is at 0 V, CA charges to VI, VD, (+11.3 V). Wh en the power switch output goes to + 12 V, DA is reverse-biased and Charge is
transferred from CA to CB. The power switch output then returns to 0 V, reverse-biasing DB and
recharging CA - DA. The voltage on CB builds up to approximately + 12 V - VDA + 12 V - VDB.

6-3

CLOCK I-i

POWER
SWITCH
OUTPUT

i
‘1 = IDLE-TIME
t2 = SWITCH ON TIME
11-4479

Figure 6-3

V IN= +12V

DC-DC Converter Signals

1
POWER
SWITCH
OUTPUT

+tz;

VOUT

1 CB

TcA

11-4480

Figure 6-4 Basic Positive Voltage Doubler
The negative voltage doubler operates in a similar manner and consists of two basic doubler circuits in
cascade with an additional input negative voltage generating Stage (D26 and C47).
Dual Voltage Regulator

The dual voltage regulator comprises an LM325N (E50) tracking regulator and power boosters (417
and Q18). Output current limit sensing is provided by R60 and R61. This Stage regulates the Outputs
from the doubler circuits to provide the f 15 V of analog power required by the various analog circuits.
6.2.2.2

ADVI 1-A A/D Conversion Circuit - The ADVl l-A A/D converter circuit utilizes a patented
auto-zeroing, successive approximation technique. The basic components of this circuit are illustrated
in Figure 6-5.
Analog Multiplexer

The analog multiplexer consists of two 8-channel, Single-ended multiplexer ICs (E47 and E48) whose
Outputs are connected together, thus forming a 16-channel multiplexer. During Sample, when no conversion is in process, the addressed multiplexer channel is on. During hold, two conditions are possible. If Single-ended (SE) mode is picked, all channels of the multiplexer are off and the auto-zero
switch is on. If SE mode is not picked, the negative side of the selected quasi-differential pair is
selected.
6-4

ESH
SAMPLE

NODE

-AND-HOLD

FEEDBACK
DIA
FEEDBACK
SIGNAL
SWITCH

AUTO - ZERO
SWITCH

ADZC

”
HOLD
B-BIT
VERNIER
D/A

SUCCESSIVE
APPROXIMATION
REGISTER
(SAR)

COMPARATOR

11-4481

Figure 6-5

ADVl 1-A A/D Conversion Circuit Block Diagram

Auto-Zero
During Sample, the feedback Signal switch (QS, Q6, 48, Q9, QlO, and Ql 1) connects the output of the
feedback preamplifier (Q2 - Q4) to the input of the Sample-and-hold (413, E5 1, C67), thus completing
the amplifier feedback path and allowing the Sample-and-hold to track the analog input (see Figure 66).

Eos1

ESH

F E E D B A C K DIA

V E R N I E R DIA

ic PREAMP, SIGNAL SWITCH
AND SAMPLE-AND- HOLD

Figure 6-6 A/D During

6-5

Sample

Summing

currents into the 2 node:

1, = EI + Eos, - %x7L + ESH - EOS2 _ 1,
R,
RIl

(1)

Eos1 is the offset of the input buffer amplifier (E49) and Q s2 is the offset of the feedback
preamplifier.
When a conversion is initiated, the feedback Signal switch disconnects the output of the feedback
preamplifier from the input of the Sample-and-hold, thus storing the Signal, and connects the preamplifier output to the comparator (Q7 and 412) input. Next, the A/D input, El, is either switched to
the negative channel or is grounded through the auto-zero switch, E44, depending upon whether or not
Single-ended Operation was selected.
At the completion of the conversion, the C node is ideally equal to bs2’ (see Figure 6-7).

‘-D
FEEWACK

DIA

COMP

V E R N I E R D/A
11-4483

Figure 6-7 A/D During

Conversion

Again summing currents into the C node:
1,’ =

E, ’ + E,,,, ‘- E.,,’

E,,’ - EOS7c

- 1,’

(2)

R,,

Where 1 D ’ is the feedback D/A cwrent at the completion of the LSB interrogation.
Subtracting equation (2) from equation (1):

I,,- I,‘=

E, - E , ’
RD

- (I,- 1,‘) + Eosl - Eosl’
RIl

6-6

_ EOS* - EO& + E,, - kJ{ ’
R,; //RD

(3)

Note that since the offset due to the input buffer is the same in both cases,
E OS1 - E OS1 ‘=E,,, -Eo,, =0
RD

EOS2 - Eos2, is controlled by R 15 by forcing an offset shift in the feedback preamplifier and is used to
null the offset caused by the Sample-and-hold pedestal (ESH - EsH,). Note also that the conversion is
not dependent upon the magnitude of Eos~, but upon the forced shift. Therefore:
F - E, ’
1 11 - 1,’ = ‘1
- UV- IJ
RL3
If no vernier offset is programmed, Iv = IV’,
and:
1, - 1, ’ =

E,- E,’

(4)

A / D Conversion
The 12-bit feedback D/A (E46) is initialized to 40008.

During conversion, each bit of the feedback D/A is interrogated in sequence by the SAR (E39),
starting with the MSB. At the end of each interrogation interval, the decision of the comparator to
accept or reject that bit is clocked into the SAR where this decision is held. A positive voltage on the x
node will Cause the comparator to reject a bit. Because of the Overall negative feedback, this process
will Cause the C node to work its way toward null (Figure 6-8j. After the LSB interrogation, the
contents of the SAR are transferred to the Data Buffer register.

CLOCK

+ CLAMP

- CLAM P

1
LSB

MSB

11-4484

Figure 6-8

C Node During
6-7

Conversion

Since
1, ’ min = 0 (@ code = 7777)
and
1, ’ max = 1 ,:sR - ILsIi ((a\ code = 0000),
equations (4) and (5) permit voltage/current conversions
Table 6-1

$3 ’

to be derived as illustrated in Table 6-l.

AI)V 1 1 -A Voltage/Current/Bit

Relationships

Code

1, -1, ’

7777

1 P FSR
(1 - 1 LSH)

1/2 (Er:SK - E Lsu 1

crFSR >

3777

- 1 LSB

- E

1 FSR - 1 LSB

0000

-’ /2 &:,,)

-1/‘2 (Er;SR)

0
’ /2

LSB

6.2.2.3 The Vernier DAC - The Vernier DAC is a digital-to-analog converter packaged in a Single
chip serving to provide programmable small increment offsets to the summing node of the A/D converter. It has been included in the ADVl 1-A circuit primarily to facilitate automatic testing of the
module and is used by the diagnostic routines in the measurement of noise, offset error, and interchannel settling error. The Vernier DAC is controlled through bits 07:OO of the Data Buffer register
(write-only), accepting g-bit offset binary code to produce positive and negative full scale offsets of 2.5
A/D LSBs.
6.2.3 ADVll-A Performance Test (MAINDEC-1 l-DVADA-A)
This diagnostic package permits complete testing of all functional aspects of the ADVll-A. It is
divided into four major routines which are described below. Refer to diagnostic listing MAINDEC-1 lDVADA-A for run instructions.
1.

Wraparound Routine - consists of four subtests which tan be run individually or
consecutively:
a.

Analog Test - Checks all channels and their Outputs to ascertain whether or not multiplexing and gross conversion functions are working.

Noise Test - determines whether or not the amount and distribution
noise within the A/D converter is within limits.

Interchannel Settling Test - Determines whether or not the 4/D converter tan recover
from measurements at opposite extremes within specified times (switches alternately
between channels 1 and 2 - i.e., between +4.5 V and -4.5 VI.

Differential Linearity and Relative Accuracy Test - makes multiple randomized measurements of ramp Signal on channel 2 to determine, within 0.01 LSB, the width of the
voltage band corresponding to each of the 4094 finite width states.

short-term

Calibration Routine - works interactively with Operator to facilitate precise calibration of
A/D. Requires precision voltage Source.

6-8

rC H E C K +5V
84 +12v
POWER

Calibration routine

this polnt
Source
ts

tf precision

(EDC VS-1 1 N

SUPPLY

tan be run at
voltage
or equlvalentl

available.
11

Figure 6-9

ADVl 1-A Troubleshooting Procedure

6-9

4485

Print Values routine - works interactively with Operator to execute, and if desired, print out
results of conversions on selected channels.

Logic Test Routine - consists of 23 subtests that run sequentially without Operator intervention and check Status register read/write Operation, initialize conditions, A/D done flag
setting and Clearing, error flag setting, interrupt functions, etc.

6.2.4 Maintenance
In general, both routine maintenance and specific troubleshooting efforts will follow the flow defined
in Figure 6-9. Preventive maintenance will consist of removing airborne dust accumulations, checking
the power supply levels whenever new devices are added to the System, and running diagnostics whenever Performance confirmation is desired.
6.2.5 Calibration (Requires Precision Voltage Source - EDC VS-l 1N or Equivalent)
With test connector installed in ADVI 1-A Berg socket, connect thefloating reference voltage to the
two Clip-terminated leads (channel 17). Then, run the Calibration Routine and follow the step-by-step
instructions it issues. The program will specify reference voltage settings and indicate when offset and
gain potentiometers (identified in Figure 2-6) should be adjusted.
6.3 KWVll-A
6.3.1

REAL TIME CLOCK

Installation

6.3.1.1 Location - The K WV1 1-A is a Single-module Option which interfaces to an LSI-11 through
one of the quad locations in the LSI-11 backplane or in an expander box. Within the constraints
imposed by the LSI-11 bus structure (refer to the Microcomputer Handbook - EB-06.583 76 09/53), the
unit may be mounted in any available location. Note that LSI-11 priority transfer requires that no
empty unstrapped locations exist between the processor and the last device connected to the LSI-11
bus.

6.3.1.2 Address and Vector Selection - Select and set CSR and Vector Addresses as indicated in
Paragraphs 3.4.3.1 and 3.4.3.2. Note that where more than one KWVl l-Ais connected to the same
bus, CSR addresses must be four locations apart (e.g., 170420, 170424, 170430, etc.). Vector addresses
for multiple KWVl l-As must be los locations apart (e.g., 000440,000450,000460,
etc.). Remember to
reinstall any covers on switch Packs Sl and S3.
i

6.3.1.3 Board Insertion - Select a quad location, and making sure that the KWVl 1-A board is oriented so that the keyed edge connector matches the physical configuration of the terminal block, apply
firm pressure alternately to the extractor handles near the opposite corners of the board until it is
squarely and fully seated in the connector.
6.3.1.4
nostic

Test Connections - DO not connect User eq uipment to Berg connector Jl at this time. Diag0 Signal tests will requ ire jumpers between specified p ins on Jl .

6.3.1.5

Acceptance - Conduct an acceptance test as specified in A-SP-KWVl l-A-3.

6.3.2 Final Connections
Install FAST ON connectors between CLK/STl tabs and ADVl l-A tabs as required. Install the
BC08R cable (KWVI 1-A to H322 Distribution Panel) or BC04Z cable (KWVll-A to user devices)
between the Berg connector (Jl) and the appropriate terminus. Connect the BC08R at both ends so
that the stamped labels on the female cable ends match the embossed labels on the male connectors A/B to A/B, UU/VV to UU/VV.This normally means that any “this side up” labels face away from
the board on which the male connector is mounted. (See Note in Paragraph 6.2.1.7.)

6-10

“F
7
p

6.3.3 K’M’V l l-A Circuitr‘
The digital logic of the KWVl 1-A conforms in general to Standard DEC practices and should be
understandable to qualified technicians who have access to KWVl 1-A print sets and are familiar with
KWV 1 1-A functions as described in Chapter 3.
6.3.4 KWVl l-A Diagnostic (MAINDEC-1 l-DVKWA-A-D)
The KWVl I-A diagnostic is divided into two main routines, the first designed to test logic functions
on up to four KWVI 1-A modules, the second to test selected module I/O functions, STl, ST2, and
clock Overflow. Refer to diagnostic listing MAINDEC- 11 -DVKWA-A-D for run instructions.
6.3.5 Maintenance
Preventive maintenance consists of removing airborne dust accumulations, checking that power supply levels remain within specifications whenever new devices are added to a System, and running
diagnostics whenever Performance confirmation is desired.
6.4
6.4.1

AAVll-A

DIGITAL-TO-ANALOG CONVERTER

Installation

6.4.1.1 Location - The AAV l l-A is a Single-module Option which interfaces to an LSI-11 or PDP1 1/03 through one of the quad locations in the LSI-11 backplane or in an expander box. Within the
constraints imposed by the LSI-11 bus structure (refer to the Microcomputer Handbook - EB-06.583 76
09/53) the unit may be mounted in any available location and will operate within specifications,
regardless of proximity to the processor, memory, or other DEC Options. Where circumstances permit,
however, analog Performance may be improved beyond specification levels by installing the unit away
from the processor, memory modules, or other noise-producing Options. Note that priority transfer
requires that no empty unstrapped locations exist in the backplane between the processor and any
device that communicates with it.
6.4.1.2 Address Selection - Select and set address as indicated in Paragraph 4.4.2. Note that the least
significant three bits of the address word are reserved for Software addressing of the four digital-toanalog converters (DACs) and are therefore not selectable on the switch pack. For this reason, if
several AAV 1 1 -As are installed on a System, they must be assigned addresses that are 108 locations
apart.
“X

6.4.1.3 Board Insertion - Select a quad location on the connector block, and making sure that the
AAV 1 I-A board is oriented so that the keyed edge connector matches the physical configuration of the
connector block, apply firm pressure alternately to the extractor handles near the opposite corners of
the board until it is squarely and fully seated in the connector block.
6.4.1.4 Test Connectors - If AAV l l-A Signals are to be routed to the H322 Distribution Panel,
connection may be made to that unit at this time (see Paragraph 6.4.2). Otherwise, leave the Berg
connector empty to allow for monitoring AAVl 1-A output Signals in the next Step.
6.4.1.5 Acceptance Test - Conduct an acceptance test as described in the AAVl 1-A Manufacturing
and Field Acceptance Procedure (A-SP-AAV 1 l-A-3).
6.4.2 Final Connections
Install the BC08R cable (AAV l l-A to H322 Distribution Panel) or BCO4Z cable (AAV l l-A to user
devices) between Berg connector (Jl) and the appropriate terminus. Connect BC08R at both ends SO
that the stamped labels on the female connectors match the embossed labels on the male connectors A/B to A/B, UU/VV to UU/VV. This normally means that any “this side up” labels face away from
the board on which the male connector is mounted. (See Note in Paragraph 6.2.1.7.)

6-l 1

6 . 4 . 3 Mode/Level Selection
As shipped from the factory, the AAVl l-Ais set for bipolar Operation between -5.12 V and +5.12 V.
Unipolar Operation and Operation in other voltage ranges tan be achieved by proper changes in
mode/level jumpers (illustrated in Figure 4-2). Table 6-2 indicates jumper configurations for all bipolar voltage ranges; Table 6-3 indicates those for all unipolar ranges. Note that each of the four DACs
on any given AAVl l-Amay be set for a different mode/levelcondition. Note also that any Change
from the factory settings may require recalibration of the DAC involved (see Paragraph 6.4.7).

Table 6-2

Jumper Configurations for Bipolar Operation
f2.56 V

f5.12 V

f 10.24 V

DAC 1
w3
w4
W5
W6

IN
OUT
IN
IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

DAC 2
w7
W8
w9
WlO

IN
OUT
IN
IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

DAC 3
Wll
w12
w13
w14

IN
OUT
IN
IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

DAC4
w15
W16
w17
W18

IN
OUT
IN
IN

IN
OUT
OUT
IN

OUT
IN
OUT
IN

6.4.4 AAV l l-A Circuitry
The digital interface and control logic of the AAVl l-Aconforms in general to Standard DEC practices
and should be understandable to qualified technicians who have access to AAVl l-A print sets and are
familiar with Overall AAVl 1-A functions as described in Chapter 4. The analog power supply and the
digital-to-analog circuitry, however, make use of techniques and components with which DEC technicians may not be familiar. Since the analog power supply and the D/A conversion sections involve
some non-Standard circuits, they are discussed below.
6.4.4.1

AAVl 1-A Analog Power Supply

General (see Figure 6-l )
The f 15 V power for the analog circuits is derived from a dc-dc converter which consists of three basic
sections: a 12 V power switch, positive and negative voltage doubler diode-capacitor banks, and a dual
tracking voltage regulator-

6-12

!
!

Table 6-3

Jumper Configurations for Unipolar Operation
0 V - +10.24 V

DAC 1

w3
W4
W5
W6

IN
OUT
IN
OUT

OUT
OUT
OUT

IN
OUT
IN
OUT

IN
OUT
OUT
OUT

OUT
IN
OUT

IN
OUT
OUT
OUT

IN
OUT
IN
OUT

OUT
OUT
OUT

DAC 2

W7
W8
w9
WlO
DAC 3

Wll
w12
w13
W14
DAC 4

w15
WM
w17
W18

Table 6-4

AAVll-A Input Code/Output Voltage Relationships

Input Code

Unipolar

ov
1/2 FS
+FS - 1/2 LSB

Bipolar

- FS
ov
+FS - 1/2 LSB

Power Switch

Transistors Q2 and 43 constitute the output Stage of the 12 V power switch and provide a 0 V to + 12
V switching Signal, which is derived from the SW A and SW B Signals, and which drives the voltage
doubler diode-capacitor banks. Since saturated transistor switches turn on faster than they turn Off, an
idle time is included (see Figure 6-2) to ensure that 42 and Q3 are never on at the same time.
Voltage Doublers

The basic voltage doubler consists of a Charge transfer Stage (DA and CA in Figure 6-3) and a Charge
storage Stage (DB and CB in Figure 6-3). When the power switch output is at 0 V, CA charges to VIN VD, (+ 11.3 V) through DA. When the power switch output goes to + 12 V, DA is reverse-biased and
Charge is transferred from CA to CB through Dg. The power switch output then returns to 0 V, reversebiasing DB and recharging CA through DA. The voltage on CB builds up to approximately + 12 V VD, +12 V - VD, (+22 V).

6-13

The negative voltage doubler operates in a similar manner and consists of two basic doubler circuits in
cascade v+rith an additional input negative voltage generating Stage (D21/22 and C42/43).
Dual Voltage Regulator
The dual voltage regulator comprises an LM325N (E38) tracking regulator and power boosters (Q4
and Q5). Output current limit sensing is provided by R57 and R58. This Stage regulates the Outputs
from the doubler circuits to provide the f 15V of analog power required by the various analog circuits.
6.4.4.2 Digital-to-Analog Circuits - The analog sections of the AAVl l-Aconsist of four 12-bit D/A
converters (each contained on one 24-pin Chip), four 2505 operational amplifiers. and a + 10 V precision reference Source.
Esch D/A converter (DAC) contains the necesary circuits to generate a O-2 mA output current and to
modify that current as a function of the 12 input data bits. A 1-LSB Change in the data register
corresponds to a Change of 1 part in 4096 of the full scale output, approximately 1/2 PA.
The output of the DAC is fed into a 2505 operational amplifier which converts the drive current into a
voltage output. The feedback from the output of the amplifier is passed through the selected feedback
resistors. The interconnections between these resistors, determined by the mode/range Straps illustrated in Figure 4-2, determine the operating mode (unipolar or bipolar) and voltage range of the DAC
in question.
Gain and offset of each DAC are controlled
Figure 4-2).

through the externally-adjustable potentiometers (see

6.4.5 AAVll-A Diagnostic Test (MAINDEC-ll-DVAAA-A)

The AAVI 1-A Diagnostic

Test is divided into four routines. Esch is briefiy described below.

Logic Tests (starting address: 200) - exercises and monitors behavior of interface and control logic of all DACs on all AAVl l-As in a System. Checks that DAC holding registers tan
be loaded, cleared, and modified without error.

Ramp Loop (starting address: 204) - reiteratively increments the holding register for each
DAC to produce full-scale ramp voltages successively at the output of each DAC. Permits
confirmation by oscilloscope of DAC Linearity, settlmg time, and channel isolation.

Static Calibration Loop (starting address: 210) - permits Operator to input control data to
all DACs and monitor resulting output conditions. Run with a precision DVM as output
monitor-, the Static Calibration Loop permits calibration of gain and offset of each DAC.

Dynamit Calibration Loop (starting address: 214) - reiteratively switches each DAC
between maximum and minimum output conditions. Facilitates checking DAC response
and recovery characteristics as well as amplifier slew rates.

.
.

6.4.6 Maintenance

In general, both routine maintenance and specific troubleshooting efforts will follow the flow defined
in Figure 6- 10. Since the diagnostic program has no way of evaluating AAV 11 -A analog Performance,
pass or failure of all but the logic tests depends on the judgment of the Operator. Refer to the AAVl lA Manufacturing and Field Acceptance Procedure (A-SP-AAVll-A-3) for applicable criteria.
Preventive maintenance consists of removing airborne dust accumulations, checking that power supply levels remain within specifications whenever new devices are added to a System, and running
diagnositics whenever Performance confirmation is desired.

6-14

AND

REPAIR

ANALOG

“ S e e AAVll-A
Procedure

for

PS.

Fgeld A c c e p t a n c e
appltcable

criteria.
11

Figure 6- 10 AAV 11 -A Troubleshooting Procedure
6-15

4486

6.4.7 Calibration
Prepare the System to permit access to Signal line(s) and calibration potentiometers of DAC(s) to be

calibrated. Connect DVM of appropriate precision (note that 1 LSB on k2.56 V bipolar or 0 -5.12 V
unipolar = 1.25 mV) to output of DAC to be measured. Float the DVM as illustrated in Figure 6-l 1.
Take care to connect DVM common lead to HQ ground associated with the DAC in question. Then
proceed as follows:
1.

Load DAC holding register with 0000.

Adjust offset Potentiometer (see Figure 4-2) for DVM reading appropriate to selected
mode/level condition (see Table 4-l).

Load DAC holding register with 7777.

Adjust gain Potentiometer for DVM reading appropriate to selected mode/level condition
(see Table 4-l).

Load DAC holding register with 4000.

Check DVM for reading appropriate to selected mode/level condition (see Table 4-l).

Step 6 should produce a reading accurate to l-l/2 LSB.

Figure 6- 11

Floating the DVM
i

6.5 DRVll PARALLEL LINE INTERFACE
Refer to the Microcomputer Handbook (EB-06583 76 091.53).

6-16

GLOSSARY OF A/D TERMS

The analog error. expressed as a percentage
‘4 cayui\itiorl

of full scale,

referenced to the National Bureau of Standards Volt.

Tirlle

The time duration betueen the gi\,ing

of the Sample

specified

error

band

value.

Aper-tut-e

De1a.l.

Tir?lu

around

the

input

command and the point when the output remains within a

The time elapsed between the hold command and the Point
ilperture

at which

the sampling switch is completely open.

C~ncrrtuint~k*

The variation

in aperture

delay

time for a particular

Sample-and-hold.

C‘onwlon M o d e R e j e c t i o n (C’MR)
The ability o f a d i f f e r e n t i a l a m p l i f i e r t o r e j e c t n o i s e c o m m o n t o b o t h i n p u t s . C o m m o n m o d e r e j e c t i o n
expressed as a ratio, the Common Mode Rejection Ratio (CMRR). A differential amplifier with
dB (10,000: 1) would have an output voltage of 0.5 mV if both inputs were 5 V (5 V/80 dB).

CMRR

of 80

Crosstalk
The amount of Signal coupled to the output as a percentage of input Signal

applied to all off channels.

Differential lnpu t.s l Tt-ue)
TNO external Signals applied to the input circuitry of an A/D System whereby the first is subtracted from the
second. The differente is applied to the A/D System. This is generally used with twisted pair wiring to reduce
noise pickup.
Example

= (v+) - (V-)
= [VI + V(, ) noise] - [V2 + V(,) noise
=

[V, - V, ] + [V(, ) noise - V(, ) noise

“(11,

NOISE

For twisted pair wiring:
-+ VG

V(, ) noise A V(, ) noise
. * . v() A v, - v *
Vc2jNOISE

GLOSSARY-1

06-1236

ßifft~rt~rlrir~l lriprri.~
This

method

is common

The

I Psltr~tio I
inputting is similar

to the other

maximum dev,iation

to true differen tial

inputting elcept

that the negativre

input to the A D slstem

inputs.

of an actual

stated ~idth

t h e c o n v e r t e r . .A d i f f e r e n t i a l linear-it> o f

from its theoretical value

f 1, 2 LSB means

for any

code

ov’er the full

that the vbidth of each code

range

ov’er the range

01‘

of the

converter is 1 LSB f 1 2 LSB. Missing
Codes in an A, D converter occur vvhen the output code skips a digit.
happens v5 h e n t h e d i f f e r e n t i a l lincartt> i s vvorse t h a n f 1 L S B .

This

/) rifi
D r i f t 13 a f u n c t i o n of t h e t e m p e r a t u r e c o e f f i c i e nts of the components.

l t ic t h e maJor

c o n t r i b u t o r to gain a n d

o f f s e t error.

The error, expressed as ;r percentage,
b>
range. This error is adjustable t o zero.

hich

the actual

full

scale range

differs from

the theoretical fuil

scale

Gcriu Ttwtpt~rci t ure Cw fficitw t
This is the arnount
C/LSB
will

of gain

that

changes

at full scale. If an A/D

he off bq

1 LSB at full

with a Change

in temperature. This mat

has a gain temperature coefficient of 20” C/LSB

scale if the temperature rises 20” C above 25”

be expressed in p p m

at F.S., the A/D

C or O

converted vjalue

/rlput Bia 5 C‘urretl t
The amount of current

that fiow~s

into the selected

The resistance seen at the input to an A/D

A /D

channel

from

the Source.

system.

Linearit-y
is defined as the maximum deviation from a straight line drawn between the end Points of the converter
transfer function. Linearity
m a q he expressed as a percentage of full scale or as a fraction
of an LSB.

The multiplexer is a set of

suitches that

the

Sample-and-hold

M~rlliplt~.~

(or

permits

converter)

analog data

from

different sources

(channels) to he supplied

individually.

er Sctllitig Tittie

T h e m a x i m u m time r e q u i r e d to resch

T h e e r r o r by which

Qwnti~utic~tr

;t s p e c i f i e d e r r o r b a n d around

t h e i n p u t v a l u e w h e n switching

t h e t r a n s f e r f u n c t i o n fails t o pass t h r o u g h t h e o r i g i n . T h i s i s usually

channels.

a d j u s t a b l e t o zero

Error

Quantization error is defined as the basic

uncertainty associated with digitizing

an analog S i g n a l ,

due to the finite

r e s o l u t i o n o f a n A/D c o n v e r t e r . A n i d e a l c o n v e r t e r h a s a m a x i m u m q u a n t i r a t i o n e r r o r o f f 1 /2 L S B .

Like true differential Operation

(see Differential Inputs) in that measurement is made of the differente between
that measurement is not made at one instant in

an input and a return line. Unlike true differential, however, in
time. but rather throughout the Variation of the conversion.

This is defined us the input to output error as a fraction
Relative

accuracl

dependent

of full

Iinearity.
CLOSSARY-2

scale with gain and offset errors adjusted to Zero.

Resolution
The resolution of an A/D converter is defined as the smallest analog Change
tion is the analog value of the least significant bit.

Resolution =

that tan be dis tinguished. Resolu-

Full scale
Least significan t bit

For example. if a System requires a w.eight measurement range of _-3540 Ib, measured to the nearest 3 Ib,
2540
Resolution = -=--z-- = 847 code combinations
The closest Standard A/D converter resolution available is IO-bits binary. A binary resolution of IO-bits selected.
The new resolution for this channel is recalculated for 10 bits.
1 LSB (least significant bit) =

Full scale range _ 2540 = 2.5 lb
1024
3n

Sample-and- Hold
In Order to ensure that input voltage does not Change during a conversion, a Sample-and-hold is required. If the
Change during a conversion cycle is less than 1/2 LSB, then a Sample-and-hold circuit is not required.
Example
Conversion Speed = 20 ps
Full Scale Input Range (FSR), where arnax = 2 7~ (BW)
Converter Resolution = 10 bits
LSB Value = .Ol V/bit
1/2 LSB = 0.005 V
Maximum slew = 0.005 V/20 psec = 250 pV/psec =250 V/sec
(Rate required for no Sample-and-hold)
for ein = 1/2 (FSR) sin c3 t
then de/dt = (1/2)w (FSR) cos w t
:. lde/dt 1max = (1/2)w,,,,, (FSR) = (BW) (FSR), where wmax = 2 71 (BW)
or 250 V/sec = 71 (BW) (FSR)
BW = 250 V/sec /rr (10.24 V) G 7.77 Hz

Slew Rate
The capability of the output of an analog circuit to Change its voltage in a given period of time. If the slew rate is
7 V/psec, the analog circuit output will Change seven Volts in one psec.

GLOSSARY-3

A method that is used to transform the analog Signal to a digital number.

ANALOG, , INPUT POMPARATOR

OB-1238

An analog Signal is compared to a logic generated Signal. The logic always supplies a half range Signal initiall),.
For example, the full scale input to an A/D converter System is 10 V and the input to the System is 7 V.

Try*

5V
2.5 v
1.25 v
.625 v
.3125 v
.15625 V
.078125 v

New Logic Voltage

1s the Input
Greater Than
New Voitage

5v
5 + 2.5 V
5 + 1.25 v
6.25 + .625 V
6.875 + .3125 V
6.875 + .1562 V
6.875 + .078125 V

Yes
NO
Yes
Yes
NO
NO
Yes

*This I\ ;i 7-bit A/D
1011001 2 7 V in 10 V full wale range.

10
9
8
F

GLOSSARY-4

Decision

ND
Register
Value

Buffer
Bits

Add +5 = +S
Do nothing
Add 1.25 = 6.25
Add .625 = 6.875
D O nothing
Do nothing
Add .078175

1000000
1000000

1010000
1011000
1011000
1011000
1011001

The N>quist sampling theorem states that a minimum of tuo samples per c>,cle are required to completel‘
recover continuous Signals in ü noiseless environment. In tvpical instrumentation Systems noise does exist and
from 5-10 samples per cycle at-e required.
For appiications with dc and ver) low frequency Signals, Sample rate is usually a sub-multiple of the poL%erline
frequency to provide essentiall) infinite rejection of these frequencies.
The minimum sampling Speed required is the number of samples per cjfcle multiplied by the highest frequencj
component of the data. For time multiplesed Systems. the Speed requirement of the A/D converter is dependent
on s>stem throughput Speed. Svstem conversion Speed is determined from data bandwidth, the number ofchanneis. and the sampling factor b‘:
System throughput = (TV) (n) (B.W.) samplesisecond
n = number of channels
where N = number of samples,/c~~cle
(sampling fdctor)
B.W. = largest bandwidth of anq channel
Example
Channel 1 bandwidth 100 Hz
Channel 2 bandwidth 200 Hz
Channel 3 bandwidth ‘250 Hz
throughput = 10 X 3 (250) = 7500 sample/second
N = IO
n=3
BW = 250 Hz
The A/D throughput is comprised of the following:
Multiplexer settling time
Sample & Hold settling time
A /D conversion Speed
A/D recovery time
Computer acquisition time (Software)

GLOSSARY-5

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