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MAINDEC-8E-D1AB-D

December 1971

34 pages

Original

3.0MB

Document:	maindec-8e-d1ab-d
Order Number:	MAINDEC-8E-D1AB-D
Revision:
Pages:	34
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/maindec-8e-d1a/maindec-8e-d1ab-d.pdf

OCR Text

'CIDENTIFICATION'
”MAINDECw8E~DlAB—D
PRODUCT CODE:
‘ PRODUCT NAME:*' ' - MMBE 4K MEMORY CHECKERBOARD.
DATE CREATEDfiK
JUNE 7,‘1971'
-7»
MAINTAINERE
DIAGNOSTIC GROUP
'

‘

AUTHORz'

-VERNON'FREy.

EQUIPMENT CORPORATION

‘

'ABS

‘,ThiS pragram.is designed

detect Core failures on ha1f~selocted

lineS under wbrst CaSe noiSe canditions. (It' s
’the PUP—8E W1th

ba81c 4K memory

use

intended for

system.

i) A PDPSQE fidfiputer with 4K of m: ”ry.bI

storggei

:Initially the program is in ooré locatidns Zflfi-777 and in
1"

locations

7fi¢fl~7577.

VIDADING PROCEDURE

",:Load the program With thé

binary

loader

(BIN).

core

OPERATING PRQCEDURE
There

two

are

entries

the_pr0gramg

These

entries allow

start by testing upper core (lflQfl-7777),
start by testing lowercore
(fiflfifiw6777); To start the
the

user

program:
A.

Load Address

with flesired entry address.

gLOAD ADDRESS 3 fiZfifl i

',EEOAD ADDRESS ] 7fi¢¢§
Bw

Set
to

upper

Test

lower core

follOwing

(lflflfi-7777).

(fiflfifi—6777)

table.
'

SWITCH

core

switch
the

Test

(down)

_1(up)

SRfifi
SRg7

NOTE

.Continue

testing

Halt after test.

Relocate

program

Inhibit

Press

INOTE 2:

key

relocation

start.

RIM

and

not

BIN are saved during this test and will
lest

This

program

lower

core

the program is halted using-SRflfiu

will alternate testing

upper

and

relocation
no

uhleSs SR¢7 is set.

During

program.

a comparison check is made to insure

program loss.-

'ERRQRS

The contents of given memory test location should always be
[WSW
7777 therefore anything other than IWW 7777 will
1.
result in a-test error halt. A relocation error halt will occur
a

-:-‘if the relocation carparison check fails. .4

TeSt

Error Halts

teSt error halt is indicated by halt address WX’X

the link is set, the errOr occurred

lst

halt

The

75XX.

corrplemenhed data.

displays the contents cf

the

location in error

Record the C(AC) and press key continue.
2nd halt The AC diSplays the address of the location in errori
-

‘
7

Record

the C(AC)

and press key continue to resume testing

with the next sequential memory address.

Relocation Error Halts

.
I

I, A relOcation error halt is indicated by halt address fl3XX
let

712m

halt The AC displays the contents of the location transferring
I

Record the C (AC)

from.

2nd halt

—

Record

fr'cm'.

73rd halt

key

continue.
.

the

C (AC)

and press

key continue

displays the contents of the location transferring
Record the C(AC) and press key continue.

The AC

to.

4th halt

and press

The AC displays the address of the location transferring

The AC displays the. address of the location transferring

to.

Record the C(AC)

core

[location if possible; Load Address =7 C (MA) and

press key;

continue to

and C(MA.)

”Manually correct bad

continue relocationa

REsTRiCrIONs
Starting Restrictions
The

program may be restarted at 532% if the program is in lower core,

at 7am if the progran is in upper

oore.

It Can easily be den-

termined where the progran is by manuakly looking at

few core
.

locations

Opeung Betrtrons

None

The time to write and

test the worst

in upper and lower core

case patterh
is
approximately second
1.

and its
.

During program execution a 5 will be typed on the ‘ITY
of program
run

run

time.

Carp-lament

every

This allows the operator to determine

time before a failure

occurred.

5 minutes

approximate

LOOPS

SCOPE

TWO

special scope loops have been provided

Before

_
V

in this

entering

a scope

loop

program.

the cheokerboard.program‘wrfln

run

the halt switch up This willwrite

WOIS-‘E

case pattern thru Core

'flfis mxme hxp reads the address in the sWitches 6 timee before

oomplementing.

ADDRESS-'«flSBGif program is-in

LOAD

.A.

It,

7336

lower

core;

program is in upper core

"B.. Set switChes=addrees to he

looped

on.

Press key start.

1C.

This scope loop_exeCUted a Simple read, complement, write.

LOAD-ADDRESS-‘ISSGl if program is in lower core i
i. 7361 if program is in upper core.

.A.

Set

Switdhes S address to he looped

I'Cai'PresS key Start‘
‘

The address being

WNOTE:

looped

on can

on,

changed

simply by

the

sWitdh settings.

The

with 1ts Original centent

previous addreSS'will be left

changing

PROGRAM DESCRIPTION
A

given core is Selected when the cdnbined currents of theyX— and

Y—

the

produce a magneto netive force which exceeds

selection" lines

‘

threshold for reversing

the flux direction of the core

This;

intersection of, the activated selection lines.

occurs at the

All

other cores which are threaded onto. the activated lines will be

slightly dis'tnrbed ,Under marginal current conditions

Such

half~3elected cores might also reverse polarity when their states
are properly estainShed by the pattern which the Checkerboard Test:
writes into netmry

When a selected core isin the
it to

state. the read current'will. canse

reverse polarity and beccme [3.

When the core is in the {3

state, the write current will canse it to become 1.

Thus, the.

possibility of a reading error is greatest when all half-selected
cores

are

the 1 state;

writing error is most probable when all

the halfvselected cores are in the g state.
If a

half-selected core, changes polarity, the error will be de—

tected when the memory

the program.
appear

For a

location containing that core is tested by

reading errOr

$3 in a field of 1's,

the contents of that core will

and vice ”versa for

Test pattern consists

is reversed every

491}? octal locations

writing error.

of alternating 4 nerrory cells

containing Vilma and 4 wary cells containing 7777.
_

This. pattern

(This test pattern is

generated according to the stringing of the stack and the wiring
of the memory

SYSW.

It is the

same pattern for all 8E stacks).

0000
.

Xmaxis
».

0000
0000
0000-

0000‘ 1111
0000
1111

1111

0000 _1111
0000
1111

1111

;1111

0000

1111

0000

1111

0000
0000

.1111
1111‘

1111
«0000
0000
0000

1111

0000

1111-

1111
1111

waxy-Ls

0000

0000.
1111= 0000

1111; 0000 ._
0000-.1111*
0000 .1111 f.

.0000* 1111

0000 1111'
(1416-11)

\v!._

0., The abové array is interpreted as follows:
1A1
7‘

Positions on the

y-axis repIESent obnschtiveoctal loCations

lin.memory from.¢fi thru 77..
.B,‘

Positions On the X—axis represent consecutivac octal locations
in.memory from ya hundred thru 77 hundred,

Program Relocation

PrOgram relocatiefi is governed by the status of switch register bit 7."
“With this Switch dam ([5 peeition) program relocation occurs each time
'

the test pattern and it's ocmglement have been Completely tested._ During
the relocatiOn a oonparison check is made to inSuxe no program loss
.

.
.

Test: Freedfire
e.

The worst

ease pattern iS Written, then each location is treated as follows:
I

Read ,

(Implement, Write the location.

locetziofiw

f Read and test the

Read, (implement, Write the {loCatio ,;

‘

’

D...

Read

and

test the

Go on to neXt

After the

location,

location repeating Ann.-

pattern‘ is empletew tested, the cmtplerent pattern is
V
’

mitten and

tested.

For further

understanding of how the test is performed, refer to the

listing

26 E

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