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DEC-LB-HRZA-D

December 1971

43 pages

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Document:	Lab-8E Preliminary Users Handbook
Order Number:	DEC-LB-HRZA-D
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Pages:	43
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user‘og handbcmk

DEC-LB -HRZA-D

@— $9.7

user'g mm

DIGITAL EQUIPMENT CORPORATION

MAYNARD, MASSACHUSETTS

1st Printing November 1971

The material in this manual is for informational pquOSes and is
without notice.

subject

change

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS

Page
CHAPTER 1

SYSTEM INTRODUCTION

CHAPTER 2

ANALOG INPUT PANELS
2—1

Description
Analog Panel Pin Connections
DR8-EB Panel Assembly Connections

2-2

DK8-EF Panel Assembly Connections

2-2

CHAPTER 3

ANALOG-TO-DIGITAL CONVERTER SYSTEM

General Description

3-1

AD8-EA Analog-To-Digital Converter

3-2

Operation of the AD8-EA ConVerter

3-2

AD8-EA Specifications

3-2
3-2

AM8-EA 8-Channel Analog Multiplexer

Operation of the AM8-EA 8-Channel Analog Multiplexer
3-3

AM8—EA Specifications

3-3

Programming

3-4

Programming Examples
CHAPTER 4

DISPLAY SYSTEM

General Description

VC8-E Point-Plot Display Control

44
4—2

Operation of the Display System
Type VR14 Oscilloscope Display

VM03 Mounting Hardware

4—2

Display Times

4-2

Specifications

4—2

Digital—to-Analog Converter Specifications

4—3

4-3

Programming

4—4

Programming Examples
CHAPTER 5

REAL-TIME CLOCK

General Description

iii

Page
Operation of the DK8—ES Real-Time Clock

5-1

Clock Counter Register

5-1

Buffer-Preset Register
Clock Enable Register

5-2

Schmitt Triggers

5-4

Clock Status Register

5-4

Programming

5-5

Programming Examples
CHAPTER 6

5-6

BUFFERED DIGITAL I/O

General Description

6- l

Output Transfers

6- 1

Input Transfers

6-1

Specifications

6-2

Jumper Descriptions

6-2

Programming

6-2

Programming Examples

6-3

Interface

6-3

Cable Descriptions

6-3

Pin Connections

CHAPTER 7

6-4

LABORATORY MOUNTING PANEL

ILLUSTRATION S
Figure No.

Title

Art No.

Page

1-1

LAB-8/E System

5629-1

1-1

2-1

Analog Input Panel

5681-5 8

2~1

3-1

A/D Converter and Multiplexer
Block Diagram

8E-0157

3-1

3-2

—

Simplified

Status, Enable, and Multiplexer Register Word
Format

8E-0152

3-3

4—1

X or Y Buffer

8E-Ol47

4-2

Operation of the Point-Plot Display System

8E-0153

4—2

4—3

Display Enable/ Status Register

8E-0151

4—3

5-1

12-Bit Clock Counter Register

8E-0150

5-1

5-2

Operation of Buffer-Preset Register

8E-0155

5-2

5-3

Clock Enable Register Word Format

8E-0149

5-2

5-4

Partial Diagram Showing Major Components
of Real-Time Clock

8E—0156

5-2

5-5

Schmitt Trigger Definition

8E~0154

5—4

5-6

Clock Status Register

8E—0148

5-5

12-Channel Buffered Digital I/O-Block Diagram

8E-0158

6-1

TABLES
Title

Table No.

Page

2-1

Pin Connections

2-2

DR8-EB Panel Connections

2-2

2—3

DK8-EF Panel Connections

2-3

5-1

Rate Selection

5-3

FOREWORD
The LAB-8/ E User’s Handbook is intended to familiarize
the user with the LAB-8 / E Laboratory System

which

contains the newest low cost PDP-8/ E Computer.
,

A separate chapter of this handbook is devoted to the use

of each of the following PDP-8/ E options:
Front Panels

b. Analog-to-Digital Converter

Point-Plot Display Control

d. Real-Time Clock
e.

Buffered Digital No

It is beyond the scope of this manual to cover the use of
the PDP-8/ E or the other options mentioned.

REFERENCE DOCUMENTS

The following reference documents are available from

Digital Equipment Corporation:
LAB-8/ E Maintenance Manual DEC-LB-HXZA-D
PDP-8/E Small Computer Handbook
PDP-8/ E Maintenance Manual DEC-BE-HRIB-D
VRI 4 Display Maintenance Manual

DEC-IZ-HRZA-D
Introduction to Programming-

Programming Languages

1
SYSTEM INTRODUCTION

LAB-8/E SYSTEM

The LAB-8/E (see Figure 1—1) is a PDP-8/E computer

d. An 8-channel

analog multiplexer

(ex-

pandable to 16 channels)

with numerous options designed to provide the scientific

and engineering communities withalow-cost, modular,

VM03 mounting hardware and cable for
Tektronix Model 602 Oscilloscope

easy-to-use laboratory instrument computer. The basic

system comprises:
a.

A PDP-8/E General-Purpose, 12-bit Digital

Computer with basic 4096 word memory and
1.2 us cycle time.
b. A Teletype ® Model 33 ASR 10-bit
Input / Output device with paper-tape reader
and punch.
c. A laboratory mounting panel with precision
power supply for use with LAB-8/ E per-

ipherals.
d. A 10-bit

Analog-to-Digital Converter with
sample and hold circuitry and optional multiplexer.
e. A 10-bit Point-Plot Display Control for the
graphic diSplay of data on an oscilloscope.
f. A Real-Time Clock with five programmable

E
E
E

ranges from 1 us per count to 10 ms per
count plus three Schmitt triggers.

E
E

More advanced LAB—8/ E Systems make use of standard

PDP-8/ E options. The options most commonly used with
the LAB-8/ E are:
a.

Extra core memory

b. High—speed paper-tape reader and punch
c.

Figure 1-1 LAB-8/ E System

VR14 large-screen display oscilloscope

®Teletype is

registered trademark of Teletype Corporation.

1-1

2
ANALOG INPUT PANELS

Analog Multiplexer (AM8-E)

ANALOG PANELS

panel is supplied with an ADS-ES option, where a single
input is wired to channel 0 of the panel. Field expansion
with AM8-EA options (2 maximum) can utilize the AM8ED panel for signal inputs. Two DB-25P connectors
(DEC Part No. 12-05886) are also supplied to connect
with the Analog Panel.

DESCRIPTION

Four front panels are available with the LAB-8/ E. The
AM8-ED and AM8-EC analog panels are available with

the AD8-E AM8-E options. A DK8-EF panel is available
for the Real-Time Clock option, and a DR8-EB panel is

available for the Buffered Digital I/O option (see Figure
2-1).

The AM8-EC

analog panel is similar to the AM8-ED
panel; however, parameter potentiometers are supplied for channels 0 through 3. These variable potentiometers have i 1.3 Vdc applied to them, and they can

The AM8-ED panel furnishes the user with two DB-ZSS

receptacles, which provide inputs for a maximum configuration, 16—channel system. In addition, the AM8-ED

Figure 2-1 Analog Input Panel
2-1

be used to vary thresholds, to move pointers across dis-

Channels 10 through 17 on each panel are identical to the

to edit text, and to perform other functions.

wiring of channels 0 through 7 on the AM8-ED panel,
except that channel 0 corresponds to channel 10 1 to 11

play tubes

The

i 1

etc.

Vdc Inputs to these four channels can be re-

moved from the potentiometers by installing a 3—con-

1/4-in. telephone plug in the telephone jack on

ductor

The DR8—EB panel has 2 module connectors for 12 digital
inputs and 12 digital outputs. This panel is used to connect the DR8E Buffered Digital I/O modules with
various outside devices. Two M904 Modules are provided
with this panel that enable the user to connect his cables.
One diagnostic jumper cable to connect Input and Output
connectors is provided for troubleshooting and running
I/O diagnostic tests.

the selected channel. Four telephone jacks are supplied

with each AM8-EC panel.
The DK8—EF

Real-Time Clock panel assembly is used

to connect the Schmitt triggers and external clock inputs
to the Real-Time Clock. There are + and -slope switches

that enable each Schmitt trigger channel to select the direction of the slope of the input. A potentiometer associ-

ated with each channel adjusts the trigger amplitude.

Inputs to the Schmitt trigger channels can be supplied by
3-conductor 1/4-in. telephone jacks one for each channel and BNC connectors for all inputs. BNC connectors

DR8-EB Panel Assembly Connections

and telephone jacks are supplied with the panel.

The DR8—EB Buffered Digital I/O panel connections are
shown in Table 2-2. The M904 Module is used to connect
to the front panel block.

ANALOG PANEL PIN CONNECTIONS

The pin connections for each optional analog panel are
presented in Table 2-1.

Table 2-2
DR8-EB Panel Connections

Table 2-1
Pin Connections
Bit No.

Input Pin

Channel

Input

AMS-ED

AM8-EC
0

Pin 1

Phone Plug

Gnd

Phone Plug

Gnd

Phone Plug

Grid

Phone Plug

Gnd

Phone Plug

Gnd

Ground connected to A1
N1 F1 K1 N1 R1 T1
02

U2.

Gnd

22.

The DK8—EF Real-Time Clock Input Connections are

Gnd

shown in Table 2-3.

DKS-EF Panel Assembly Connections

2-2

Table 2-3

D’K8-EF Panel Connections

Cable or

Channel No.

Pin No.

Channel No.

Cable No.1

C
D
2

L
J
H

R
N
M

Cable No. 2

Cable No. 3

Gnd

+6.2V

Gnd

-6.2V

Gnd

Ext. Clock In

Gnd

Overflow

Schmitt common

Gnd

Chl (L)

STl

Gnd

Ch2(L)

ST2

Gnd

CH4(L)

ST4

Gnd

BNC 1

STI (out)

ENC 2

ST2 (out)

BNC 3

ST4 (out)

BNC 4

Overflow

BNC 5

Ext. Clock In

IN 1

IN 2

IN 4

BNC connector shield tied to Schmitt common.

3
ANALOG-TO-DIGITAL
CONVERTER SYSTEM

Analog-to-Digital Converter (AD8-E)

A/D CONVERTER

the voltage at the input constant until the conversion

GENERAL DESCRIPTION

process is complete.

The

LAB-8/E Analog-to-Digital Converter System

enables the user to sample analog data at specified rates

When used with two 8-channel multiplexer and expander

and to store the equivalent digital value in the memory

boards, the analog-to-digital converter can select up to

of the PDP-8/E for subsequent processing. Sample and

16 analog channels for sampling (refer to Figure 3-1).

hold circuitry in the converter ensures an accurate con—

Connectors on a panel mounted on the front of the LAB-

version of even the fastest changing signals by holding

8/ E laboratory mounting panel provide the inputs to the

—

AMS-EA—__——I
ANALOG

|(8

MULTIPLEXER

|
!

CHANNELS)

DIFFERENTIAL
PRE—AMPS 11V

AME—EC
ANALOG
INPUT
PANEL

GE-ET__
A/D

_Am

CONVERTER

I
JVBUFFER
PE,— 1050” —-l—OAC
ANALOG

15v.

AMPLIFIER

|____,___J

IAMS'EA

ANALOG MULTIPLEXER

'(8

CHANNELS)

MUX

|
l_______l
CHIS

———’7

F‘

DIGITAL
CONTROL INPUTS
CONTROL

BOARD

A231
8E-OI57

Figure 3-1 A/D Converter and Multiplexer---Simplified Block Diagram

3-1

LAB-8/E Analog-to-Digital Converter System. When
only the AD8-EA Analog-to-Digital Converter is used,
the input is differential and in the range of 1 5V. With the
AM8—EA multiplexer the input range is i1V differ—
ential which is amplified to i5V for input to the Analogto-Digital Converter.

The converter also contains circuits for detection of

timing errors. A timing error is defined as the receipt of
a conversion request, attempting to read the AD Buffer
or an attempt to change the multiplexer channel while a
,

conversion is in progress. If one of these conditions

Timing Error Flag is set. The Timing Error
Flag is sensed by an ADSE instruction and cleared by an

occurs , the

Four continuously variable parameter knobs are also

ADCL or ADST instruction.

available with the multiplexer. These knobs control the

position of potentiometers, which tap a voltage from a
standard power supply and feed that voltage to the converter system. These variable knobs are useful to programmers for establishing parameters setting threshold levels, or moving parts of the display. The output
of each of these potentiometers is physically connected
to a multiplexer channel; knob 0 connects to channel 0
knob 1 to channel 1 etc. To prevent monopolizing the
multiplexer channels in the eVent that they are required
for external use, a phone jack is associated with each
parameter knob. When used externally, the corresponding potentiometer output is disabled and the multiplexer input is available at one common connector input.

AD8-EA Specifications

Input Voltage Range:
Input Impedance:

3: 5V

Differential

+ input greater

than 10 M 9.

negative input

(with jumper) greater than
10 k9. Common mode rejec-

tion at least 35 dB at 60 Hz

(common mode voltage less
than 5V to ground)

Parallel: 10 bits right-justi-

Output Format:

fied and sign extended

2’s

complement
AD8-EA ANALOG-TO-DIGITAL CONVERTER

Resolution :

.1%(1 bit in 1024)
i .1%lFS /C

The AD8—EA is a 10-bit successive-approximation con-

Temperature Stability:
Accuracy :
Repeatability :

verter with sample and hold circuits

cuits

conversion cir-

input buffer, and control logic contained on two

.1%

99.7%repeatable (3 standard
deviations on a normal dis-

PDP-8/E modules (A231 and A841). The converter can

tribution function)

be used singularly with one channel input having an input

Conversion Rate:

50 kHz maximum

range of i5V, or it can be used with the AM8—EA multiplexer boards (A232) to perform conversions for up to
AM8—EA 8-CHANNEL ANALOG MULTIPLEXER

16 channels having full-scale inputs of 1“ 1V. Analog
inputs are connected to the module by H851 Edge connectors from the multiplexer or by a shielded twisted
pair from an external device.

The AM8-EA is an 8-channel multiplexer

designed to

expand the capability of the AD8-EA A/D Converter.
The multiplexer accepts bipolar analog inputs having a

Operation of the ADS-EA Converter

full-scale range of

i 1V and converts these

inputs into a

full-scale t 5V output supplied to the AD8-EA Converter.

The operation of the AD8-EA converter is controlled by
IOT instructions. A conversion is initiated by an ADST

Operation of the AM8-EA 8-Channel Analog Multiplexer

instruction or from the DK8-ES Real-Time Clock. An
starts the conversion and clears the

A/D Done

input
Flag. When the conversion is complete the converter
sets its A/ D Done Flag. This flag is sensed by an ADSK

The AM8-EA consists of multiplexer switches and scal-

instruction

ing amplifiers for eight analog channels. The AM8-EA
can be expanded up to 16 channels in 8-channe1 groups by
adding an additional AM8-EA 8-channel Multiplexer Expander Module. Multiplexer operation is controlled by
the AD8—EA. Programmed instructions and the associated multiplexer control provide the capabilities for
random or sequential selection of a multiplexer channel
and for reading the active channel address to the computer. Two programmable address modes are provided:

and if set, it causes the next instruction to

be skipped; thus, the 10-bit digital word can be trans-

ferred to ACZ-ll by an ADRB instruction. Because the
10-bit word is in 2’s complement form, AC00 and AC01

(sign-extended format). In other words, a
negative voltage results in a negative signed number.
The converter contains an INTERRUPT ENABLE flipflop that is controlled by program instructions. When
this flip-flop is enabled, the converter can generate interrupt requests to the program interrupt facility on
completion of a conversion.
copy AC02

auto-increment or non-auto-increment. The AD8-EA is
set to the non-auto-increment mode when the ADCL

command is given.
3-2

In the auto-increment mode

channel addresses are in-

LOAD MULTIPLEXER (ADLM)

cremented automatically at the completion of a con-

Octal Code:

version by an A/ D Done output from the converter. The

Operation:

computer specifies the first channel requested by the
user by issuing an ADLM instruction, then issues A/ D
converter instructions to start an A/ D conversion. On
completion, the A/D Done Flag increments the multiplexer channel address for the next sample. This

6531

Load Multiplexer Register with contents of AC8-11 and clear AC.

START CONVERSION (ADST)

Octal Code:

6532

Operation:

Clear A/D Done and Timing Error

process continues until the AUTO MODE flip-flop is
reset. Incrementing beyond channel 17
causes an auto8

Flags and start A/D Converter.

matic reset to channel 0.

mined by MUX Register.

Channel to be converted is deter-

READ A/ D BUFFER (ADRB)

AM8-EA Specifications

Octal Code:

Output :

Clear A/D Done Flag and load the

Operation:

Bipolar 1 1V
Non-inverting input is 70
k9 i2% in parallel with 300
pF. Inverting input is 35
kg :2% in parallel with 300
pF
Bipolar 1 5V full scale

Input Voltage:
Input Impedance:

6533

contents of the A/ D Buffer into ACO11.

SKIP ON A/D DONE (ADSK)

Octal Code:

6534

Operation:

Skip the next instruction if A / D Done
1. Do not clear flag.
=

Common Mode Rejection: Greater than 25 dB, 35 dB

(typical)

SKIP ON TIMING ERROR (ADSE)

i67V from fault line (in-

OverloadProtection:

definitely)
Overload Recovery Time: 8 us

Octal Code:

6535

Operation:

Skip the next instruction if Timing
Error Flag
1. Do not clear flag.
=

Flat from 0 to 30 kHz, -3 dB at

Frequency Response:

60 kHz

Leakage Current:

LOAD ENABLE REGISTER (ADLE)

Negligible at 7052 impedance

Octal Code:

Long Term Stability (one hour) :
Not more than 0.1% for

6536

Load Enable Register with contents

Operation:

i 300°

of AC2-5 and clear AC Register.

change

READ STATUS REGISTER (ADRS)

PROGRAMMING

Eight instructions are used to program the A/ D Converter and Multiplexer. Each instruction is completed in
1.2 us. The instructions are as follows (see Figure 3—2 for
word format):

Octal Code:

6537

Operation:

Read A/D Status

Enable Register

and MUX Register contents into
ACO-11.

The Status

Enable

and Multiplexer bits indicate the

following conditions :

CLEAR ALL (ADCL)

Octal Code:

6530

Operation:

Clears the A/D Done Flag and

0— A/D Done Flag Status (Done

Status Register

Timing Error Flags to ready the con-

verter for another conversion. This

instruction also clears the MUX and

1—Timing

Enable Register.

Error

(Error

STxfrus

ENE

NOT USED

MUL‘PIrPLEX
REGISTER
8E-0152

Figure 3-2

Status , Enable , and Multiplexer

3-3

Flag Status

read the value of the converter’s buffer into the PDP-

2—Enable Interrupt on A/D Done

Enable Register

8/ E accumulator. The program is as follows:

3—Enable Interrupt on Timing
Error

1 (Note 1)

ADST

ICLEAR

ADSK

ISKIP

THE

JMP-l

/JUMP

BACK

ONE

ADRB

/READ

THE

DONE

ADC

FLAG

START

AND

INSTRUCTION
INSTRUCTION
BUFFER

THE

INTO

CONVERSION

WHEN

DONE

(e.g., clock)

4—Enable External

A/D start

If the ADC has been enabled to accept start pulses from
an external device (such as a clock), then a

5—Auto-Increment Mode (Note 2)

timing error

could occur. To check for this possibility, the following
code should be added after the ADRB command:

Multiplex Register

——

11— Indicates current channel

(0-178 ) to be sampled by
A/ D.
ISKIP

SKP

IUNCONDITIONAL

JMS

NOTE

THE

ADSE
ERROR

/GO

ERROR

INSTRUCTION

ERROR

SKIP

ROUTINE

1. The Timing Error Flag indicates that

either an ADRB , ADLM, ADST, or external A/D start was attempted while a

When the ADC is equipped with the multiplexer option ,

conversion was in progress. ADLM or

the channel to be sampled is selected prior to starting

ADRB will cause an erroneous result to

appear in the

using the ADLM command. For
simple program to continuously read the
value of one of the parameter knobs and display the digital value in the PDP-8/ E accumulator is as follows:

the conversion process

A/D buffer, while ex-

ternal A/D start

example

ADST will be ig-

nored.
2. When this bit is set , the occurrence of

START:

CLA

/CLEAR

1 will increment the MultiA/ D Done
plex Register by 1. Incrementing past
channel 17 8 will cause the MUX Regis-

ADSK

ISKIP

ter to reset to channel 0.

JMPO‘I

ADRB

IREAD

TAD

ADST

THE

/LOAD

AGAIN:

Programming Examples
Normal Mode

/GET

ADLM

JMP

--—

CHN

PDP-8/E

CHANNEL

ACCUMULATOR
(O-B

MULTIPLEXER

FROM

FOR

KNOBS)

ISTART
WHEN
ADC

FINISHED
VALUE

AGAIN

Clock Mode

—

In this special mode

samples are taken

at regular intervals as defined by the clock rate. A con-

To program the analog-to-digital concom-

version is initiated with every clock overflow. The fol-

mand; loop on the Done Flag until the conversion
process is complete and the Done Flag is set to a 1; then

lowing example takes 100010 samples at the specified

verter (ADC), the program must issue

INITIALIZE

START:

CLOCK

AND

start

ADC

clock rate and stores them in memory.

ENABLE

CLA

ADLOOP:

TAD

NUMBER

/-IOOO#

DCA

COUNTER

ISTORE

TAD

ADDRESS

/ADDRESS

AID

DCA

POINTER

/POINTER

ADSK

COUNTER

CONVERSION
AUTO-INDEX

CONVERSION

/WAIT

FOR

/READ

CONVERSION

STORAGE

AREA

DONE

JMP-l
ADRB

/STORE

COUNTER

/HAVE

THE

ADLOOP

INO:

DCA

ISZ
JMP

POINTER

NUMBER:

-175@#

COUNTER:

ADDRESS:

n-l

POINTER:

GET

AWAY
#

SAMPLES

(IOOO#

THIS

REQUIRED

BEEN

ANOTHER

SAMPLES

/BEGINNING

TABLE-l

CASE)

TAKEN

4
DISPLAY SYSTEM

Point-Plot Display Control (VC8-E)

VCB-E DISPLAY CONTROL

GENERAL DESCRIPTION

d. Z-axis control, which consists of provisions

for the intensity

signal necessary for the
Tektronix Model 602 Oscilloscope and in-

The VC8—E Display control can control a Tektronix 602 or

VR14 Display in the form of a 102410 by 102410 dot array.

tensity and channel select signals necessary
for the VR14 oscilloscope.

Under program control, a bright spot can be momenta-

rily produced at any point in this array. A series of these
intensified dots can be programmed to produce graphic
output.

The VC8-E interfaces with the Tektronix Model 602 or

the VR14 through two different connector assemblies.

VC8-E POINT-PLOT DISPLAY CONTROL

Note the relationship between the signed octal numbers
The VC8-E consists of a two-axis, digital-to-analog con-

shown below and their corresponding 2’s complement

verter and intensifying circuit (Module M885) that pro-

form.

vide deflection and intensity signals. The output of the

D/A converters is -5V to +5V in steps of ~10 mV per

step. The signals from the VC8-E are applied to the input
amplifier circuitry of such display units as the Tektronix
Model 602 or the type VR14 Oscilloscope. The control circuit for the VC8-E is located on a PDP-8/ E module
(M869). Both modules plug into the OMNIBUS @

Signed Values

2’s Complement

(used in programming example)

(10 Bit) (12 Bit)

+777

0777

The basic VC8—E system consists of the following cir-

cuitry:
a. OMNIBUS

interface

IOT decoding, skip,

clear AC and interrupt control.
,

b. X-axis

0001

0000

-1

1777

7777

-777

1001

7001

buffer, D/A converter, summing

amplifier, and bipolar line driver.
c.

Y-axis buffer, D/A converter,

summing

amplifier, and bipolar line driver.

@ OMNIBUS

is a trademark of Digital Equipment Corporation.

the oscilloscope (provided by the user) in the H945 LAB-

OPERATION OF THE DISPLAY SYSTEM

The VC8-E is a two-axis (X and Y),

8/ E Mounting Cabinet. A modification kit for the oscilloscope and a BC01L-10 cable are provided to properly
interface the Model 602 oscilloscope to the VCB—E. Cable
lengths other than 10 ft are available at extra cost.

digital-to-analog

converter and intensifying circuit (Z-axis) that provides

defection and intensity information to the display os-

cilloscope. In Figure 4-1 the position of the oscilloscope
beam will be determined by the contents of the X-and Ybuffer registers. Coordinate (0 0) is located in the center
of the screen. Coordinate data (see Figure 4-2) is transferred to the X-and Y-axis from bits 2 through 11 of the
PDP-8/E accumulator. This data must be in the range
,

Display Times

i- 0777

diSplay times of instructions that include in-

The

tensification depend on the type of oscilloscope used.

VR14:

21 us

Tektronix Model 602:

6 us

SIGN

J
r

UNUSED

DATA

(IN

2's COMPLEMENT)
85-0147

Figure 4-1

*(1001.o777)

X or Y Buffer

*(oooo,o777)

(0,0)

(1001,0000)

"(1001,1001)

”(0777.0777)

(0777,0000)

*(o777,1001)

*(oooo,1oon

6E-0153

Figure 4-2 Operation of the Point-Plot Display System

NOTE

These times are necessary for the electron gun to reach

Octal 1000 is a point on the oscilloscope
below 1001; however, it is undefined in 2’s

specified position before intensification can take
place. A switch is provided on the M869 Module to select

complement arithmetic.

the proper interval. The switch is marked DELAY with

the

settings L for long and S for short.
Type VR14 Oscilloscope Display

Specifications

The VR14 is a compact solid-state CRT display with self-

contained power supplies and a viewing area of 6-3/ 4 in.
by 9 in. The VR14 can plot 1500 random points and up to 75

Z-Axis

in. of vector with no flicker. A maximum deflection step

The Z-axis polarity is con-

For the Tektronix 602, the switch must be in the positive

VC8-E is through connector assembly BC01K-10 (10 ft)
,

—

either positive or negative, depending on the setting.

in any direction requires only 21 us. Interface with the
BCOlK-25 (25 ft)

(intensity pulse)

trolled by a switch in the M869 Module. The pulse will be

position; for the VR14 the switch must be in the nega-

BC01K-50 (50 ft). The standard

tive position.

length is 10 ft.

Pulse Width:

VM03 Mounting Hardware

1 us

Pulse Size :

+4V to -2V

Mounting Hardware kit for the Tektronix

Rise Time:

100 ns

Model 602 Oscilloscope provides‘brackets for inserting

Fall Time:

200 ns

The VM03

4-2

NOTE

Skip On Done Flag (DISD)
con-

Octal Code:

6052

trolling a Tektronix Model RM503 Oscilloscope. However the settling time for
this unit is somewhat longer than the
VR14 settling time (21 ,us). A software
time delay before intensification must be
provided by the user for proper operation.
A jumper wire must be removed on the
M885 Module, and another wire must be
installed on two split lugs. This modi-

Operation:

Skip if Done Flag (1). Do not clear
Done Flag.

Provisions have been made for

fication will create

Load X-Register (DILX)

Octal Code:

wait for settle. Set Done Flag. Do not

clear AC.
Load Y-Register (DILY)

+4V to -10V in-

the RM503, the

intensity
cilloscope functions properly.
on

Clear Done Flag; load X-Register,

Operation:

Octal Code:

tensity pulse. With adjustments of the Zaxis

6053

6054

Clear Done Flag; load Y-Register,

Operation:

os-

wait for settle. Set Done Flag. Do not
clear AC.

Digital-to-Analog Converter Specifications

Intensify (DIXY)
Octal Code:

6055

Clear Done Flag; intensify; set Done

Operation:

Output Voltage:

+5.12V to -5.12V

Resolution:

10 mV i 2.5 mV

Slewing Speed:
Drive Capability:

Capable of driving loads

Load Enable (DILE)

greater than 1 k9 (min) in
parallel with 5000 pF; i.e.,
100 ft, 50 pF/ ft cable.

Octal Code:

6056

Operation:

Transfers contents of AC to Enable

i .01V

Flag.

<2.5 V/ us

Clears

AC.
Offset and gain adjustments provide a 10%decrease in

range and step sizes, and a variation of

Read Enable/ Status Register (DIRE)

i.5V from

Octal Code:

ground.

6057

Transfer the contents of the Display

Operation:

Enable/Status Register to the AC as
PROGRAMMING

defined below:

To output data on the oscilloscope display use the in-

The Done Flag (bit 0) can be read using a DIRE (trans-

structions defined as follows (refer to Figure 4-3 for Dis-

fer enable to AC) command; however, the Done Flag

play Enable/Status Register) :

may not be set under program control using the DILE

(load enable, clear AC) command.

Clear All Logic (DILC)

Octal Code:

6050

Operation:

Clears, enables, flags and delays.

The channel number selects the VR14 display channel.
Bit 10

0, channel 0; bit 10

1, channel 1.

Both channel number and interrupt can be loaded from

Clear Done Flag (DICD)

Octal Code:

6051

and read into the AC using the DILE and DIRE com-

Operation:

Clears Done Flag.

mands, respectively.

DONE FLAG

INTERRUPT
ENABLE

l 1

DONE

NOTYJSED

CHANNEL
NUMBER
BE-Otst

Figure 4-3 Display Enable/Status Register

serted prior to an intensify instruction and after the load

Programming Examples

sequence:

Display Control is extremely fast; thus,
many display oscilloscopes cannot position their beam
before an intensify command is performed. For this
reason, a Done Flag has been incorporated into the control and should be used whenever random points are
plotted sequentially.
The VCS—E

The Tektronix 602 requires only 6 ,us to display clear in-

formation on the oscilloscope. In applications where the
program overhead time is of sufficient length to consume 5 cycles of processor time, there is no need to wait
for

display Done Flag indications. This time saving

factor is indicated by the following example :

DISD

/SKIP

DILX

IGET

X-COORDINATE

/LOAD

X-REGISTER

DILY

IGET

Y-COORDINATE

ILOAD

Y-REGISTER

TAD

TABLE

DCA

TAD

TABLE

DCA

START:

CLA

ISET
SAMPLE

DIX

CYCLE

TIME

INTENSIFY

/LOAD

AC=0

IPOSITION

KNOB

/LOAD

CLA

IAC

/SET

JMS

SAMPLE

IPOSITION

DILY

/LOAD

DISD

/SKIP

AC=l

DISPLAY

DONE

FLAG

JMP-l

/INTENSIFY

DIXY

JUMP START
0

SAMPLE:

FLAG

and 1 of the ADC:

JMS

CLA
TAD

DONE

coordinates are set by the position of parameter knobs 0

CLA
X

DISPLAY

The following example displays a dot on the screen; the

DILX

TAD

JMPc-l

ADLM

/LOAD

MULTIPLEXER

ADST

ISTART

CONVERSION

ADSK

lwAIT

JMPI-l

USED

ADRB

IREAD

JMPI

POINT

When using the VC8—E with slower oscilloscopes, such as

SAMPLE

The kaleidoscope program for the V08-E vividly shows
the versatility of the VC8-E DiSplay System. The pic-

the VR14, or if there is some doubt concerning the pro-

tures on the screen are varied by manipulating switch

gram overhead time, the following code should be in-

/KALEIDOSCOPE
START:

TAD

JMS

PROGRAM
Y

/GET

SCALE

ISCALE
/2’s

CMA
TAD

DCA

TAD

/LOAD

JNS

COMPLEMENT

/CONFUSE

DILX

TAD

SCALE

WITH

ISCALE
/CONFUSE

/LOAD

DILY

WITH

DISD

JMP.-l
DIXY
DCA
SCALE:

CHANGE:

/INTENSIFY
Y

JMP

START

DCA

TEM

/D0

AGAIN

ITEMP

STORE

OSR

IREAD

SWITCHES

CIA

INEGATE

DCA

TAD

TEM

CLL

SPA
CML
RAR

ISZ

JMP

CHANGE
I

X:2222
Yallll

SCALE

/STORE
IGET VALUE

CHANGE

5
REAL-TIME CLOCK

Real-Time Programmable Clock (DK8-E)

DK8—ES REAL-TIME CLOCK

77778 and then overflows on the next pulse, causing
the Overflow Flag to be set to 1. The program detects the
Overflow Flag; the flag is also sensed by a program interrupt, a skip instruction, and/or a read status instruction. The contents of the clock counter at any given point
can be determined by an instruction that puts the con-

GENERAL DESCRIPTION

The LAB-8/ E DK8-ES Real-Time Clock option offers the
PDP-8/E user a method of accurately measuring and

counting intervals or events in a number of ways. The
real-time clock can be used to synchronize the central
processor to external events, count external events,
measure intervals of time between events, or provide

tents of the clock counter into the AC via the Buffer-

program interrupts at programmable intervals. Some of

ister can also be set by the user via the Buffer-Preset

these operations can be performed concurrently.

OPERATION OF THE DK8-ES REAL-TIME CLOCK

Buffer-Preset Register

Preset Register. The contents of the Clock Counter Reg-

The 12-bit Buffer-Preset Register is the link between the

Logically, the DK8—ES contains the features described in
the following paragraphs.

processor, accumulator (AC), and the clock counter
(see Figure 5-2). The Buffer-Preset Register is used to

read the contents of the Clock Counter Register into the

AC; it is also used to buffer the current count in the clock

Clock Counter Register

counter when this value is to be saved. The Buffer-

Preset Register is then made available to the program

The Clock Counter Register (see Figure 5-1) is one of the

four registers in the DK8—ES that are accessible to the

by an instruction that reads the contents of the Buffer-

program. Each generated pulse causes the clock count-

Preset Register into the AC. This register is also used to

by 1. The clock counter increments

hold the number to be transferred into the clock counter

er to be incremented

12-BIT

l1|2J3

CLOCK COUNTER

OVERFLOW

FLAG
PULSES FROM CLOCK
SE-0l50

Figure 5-1

12—Bit Clock Counter Register

each time the counter overflows. This number is then

Counting goes from Oto 77778 overflows,
and then starts counting from 0 again.
Overflow, therefore, occurs every 409610
,

procedure allows the counter to be reset to some desired
starting value each time the counter overflows; thus, the
program has a highly flexible control over the apparent
clock frequency.

PDP -8/E

l
FLAG

CLOCK

counts (or every 4096

The overflow flag remains set until

cleared by programming.

C—> GOO-V7777 +OVERFLOW——)
01

COUNTER

counting rate

cycles).

BUFFER—PRESET

I
|

Eff}

ACCUMULATOR

Function

AC Bit

loaded into the Buffer-Preset Register from the AC. This

Present Time -as in mode 00, the counter
.

IS incremented at the

specxfied rate.

Each time overflow occurs, however, the

Figure 5-2 Operation of Buffer-Preset Register

contents of the Buffer-PI-eset

are
.

CIOCk Enable Register

transferred

up from that value. The Buffer—Preset
Register is usually set to the negative (2’s

The Clock Enable Register (see Figure 5-3) is the 12-bit
register that enables the operation of the entireclock
option.

value 0f the number 0f
complement)
counts deSIred before overflow. In this

mode, the user has not only determined

This Clock Enable Register controls the rate of the time

the rate of counting but also the number

base and the mode of counting and selectively enables

of counts before overflow, thus allowing

each of the three input channels and the interrupt line.

him two dimensions in selecting the time

Other bits in the 12-bit register determine interrupt and

intervals between overflow (see Figure 5-

enable conditions. The Clock Enable Register is loaded

4).

from the PDP—8/ E accumulator under program control.
The conditions enabled for any channel determine the

In this mode, as in mode 00, the overflow

action that must be taken to detect an event.

remains set until cleared by the program.

L_W_J\

0.F.

MODE

r
RATE

SCHMITT
TRIGGER
INPUTS

CONTROL
FUNCTIONS

850149

Figure 5-3 Clock Enable Register Word Format
Mode Selection

—

Bits 1 and 2 of the Clock Enable Regis-

ter can be considered the Mode Control Register; this

USER

DETERMINED

INITIAL COUNT

7777

OVERFLOW

clock operates.
ON

EACH

BUFFER-PRESET

OVER FLOW

AC Bit

Function

Enables clock overflow to set correspond-

ing bit in the Status Register.
00

Free Run -the counter is incremented at
the specified rate.

ISSUING

INSTRUCTION

PDP-8/E
ACCUMULATOR

850156

Figure 5-4 Partial Diagram Showing Major
Components of Real-Time Clock

Time Base from Initial Event -as modes

NEURON FIRING
T1

00 and

01, the clock counter is incremented at the specified rate, but on

NEURON FIRING

STIMULUS

each occurrance of an input event on a se-

lected input channel (Schmitt trigger),
the contents of the clock counter are auto-

matically transferred to the BufferPreset Register, and the counter contin-

ues to count.

NEURON FIRING

Time Base between Two Events

-as

modes 00, 01, and 10, the clock counter is
incremented at the specified rate.

COUNTER TO

START
COUNTER

EVENT

On each occurrence of an input event on a

BUFFER

INITIAL I

————————

selected input channel (Schmitt trigger),
the contents of the clock counter are auto-

matically transferred to the BufferPreset Register. This procedure is identi-

EVENT

cal to mode 10 thus far. However, mode 10

This mode is useful for determining the

and mode 11 differ as follows: in mode 10,

total elapsed time between some initial

the clock counter continues to count after

(e.g., a stimulus) and subsequent

the transfer, regardless of which of the

events that might be caused by the initial

three enabled input channels the event oc-

(e.g., muscle reaction). In using
mode 10, the Clock Status Register is used
in conjunction with the Clock Enable Register to detect the occurance of the input

curred on. In mode 11, the clock counter is

events. Each time such an event is recog-

(refer to Table 5-1).

event
event

cleared after being transferred to the
Buffer-Preset Register; counting then
continues from 0 at the

specified rate

nized, the contents of the Buffer-Preset
Register can be picked up by the program
and stored away, or processed as the user

Function

AC Bit

wishes.

Enable external start (of ADS-E).
A Post Stimulus Histogram (PST) can be

generated as follows: 0 a stimulus can be
issued to a subject, and the clock started.
Then, the elapsed time to succeeding
neuron firings (i.e., input events) can be
determined by saving the time counts

Inhibits the clock from counting when set
to a 1. Bit 7 is cleared by firing any en-

abled Schmitt trigger.

that are transferred from the counter to

the Buffer-Preset Register on each firing.

Causes an interrupt request when any bits
in the Status Register are set to a 1.

Table 5-1
Rate Selection
*

Contents of Bits

Octal

Interval Between

3-5

Value

Pulses (seconds)

000

Stop

001

010

011

1 kHz

100

10 kHz

101

100 kHz

110

1 kHz

111

Stop

Frequency

External Input
100 Hz

Hysteresis :

Function

AC Bit

0.3V

Common Mode Rejection: 35 dB
9, 10, & 11

or 4 to set

600 ns

Propagation :
OutputVoltage:

Enabled the firing of Schmitt triggers 1, 2,

corresponding bits in the Status

0 to

+5V

(falling edge

denotes firing and resets on

recrossing the threshold voltage).

Schmitt trigger 4
Schmitt trigger 2

NOTE

Schmitt trigger 1

A Schmitt trigger need not be enabled to

make use of its signal conditioning properties. An analog signal can be used to

NOTE

The program interrupt facility must be

drive the external clock input by connecting the analog signal to the Schmitt
trigger input, and then connecting the
output to the external clock input.

enabled by issuing an ION (6001) before
an actual program
an

interrupt can occur. If
enabling inter-

ION has been issued,

rupt on an input channel or on overflow
still causes the Clock Flag to be set to 1;

however, the program will JUMP to a
subroutine at 0. The Clock Flag can be

The Schmitt trigger firing (see Figure 5-5) is governed

checked, like any other device flag, with a

between +5V and -5V is coarsely selected by setting the

Skip on Flag

by setting the source and threshold controls. A voltage

1 instruction CLSK.

threshold knob to the far right for +5V, far left for -5V,

point in between. The slope, either positivegoing
negative-going, is then chosen by setting the
slope switch to either + or At this point, each time the
external signal crosses the preset voltage in the indicated direction, the Schmitt trigger fires, causing a
pulse to be generated. This pulse is referred to as an
or at some

Any or all of the Schmitt triggers can be enabled to set

the Clock Status Registers, and depending on other bits
set in the Enable Register, an interrupt or a transfer of

clock counter information to the Buffer-Preset Register
may occur.

event.

Schmitt Triggers

Access to the Schmitt triggers is gained through the

Input Control Panel, which is mounted on the Laboratory Mounting Panel. The Input Control Panel has three
groups of outlined boxes, each designated Schmitt trig-

85-0l54

gers and each with an identical set of controls. Each box
represents one input channel to which an external signal

Figure 5-5 Schmitt Trigger Definition

may be connected. Within each box, there is a phone jack
(Differential Input) marked input, and a BNC marked

Other Enable bit functions are discussed in the next sec-

output; also within each box, there is a switch marked
slope, and a control knob marked threshold. The input
jacks have the following specifications:

tion on clock programming.
If threshold was set to +1V and slope to +, then the as-

terisks indicate a pulse generated, whereas the X does
not. Even though the threshold was crossed, the second

Input Threshold:

Variable between 1- 5V

Source:

Positive, Negative,
Voltage

Input Type:
Input Resistance:

Differential

Minimum Duration

2 us

Clock Status Register

1 50V

The Clock Status

condition of slope was not satisfied; thus, a pulse was not

Line

produced.

50 k

Input Pulse:
Maximum Permissible

Input Voltage

events 1, 2, 4, and the overflow bit.

5-4

EV4

EV2

EV1

OVERFLOW

NOT

USED

SCHMITT
TRIGGERS
SE-OMS

Figure 5-6 Clock Status Register

status information is

PROGRAMMING

inclusively

ORed into the AC, then all status bits
The following IOT instructions control the DK8-ES Real-

are cleared.

Time Clock:

that only one occurrence of an event

This procedure ensures

will be transferred to the program.

Clear Clock Enable Register per AC (CLZE)

Octal Code:

6130

Operation:

Clears the bits in the Clock Enable

The status condition is established as

follows:

Status

AC Bit

Condition

Skip on Clock Interrupt (CLSK)
Octal Code:

6131

Operation:

Causes the next instruction to be

skipped if an interrupt condition

Overflow

Event 4

Event 2

Event 1

exists.
a.

An enabled Schmitt

trigger has

fired.

Clock Buffer to AC (CLBA)

Octal Code:

6136

Operation:

Clears the

b. The clock counter has overflowed.

AC, then transfers the

contents of the Clock Buffer into the
AC.

Set Clock Enable Register per AC (CLOE)

Octal Code:

Operation:

6132

Clock Counter to AC (CLCA)

Sets the bits in the Clock Enable

Octal Code:

Operation:

6137

Clears the AC, transfers the contents
of the clock counter to the Clock

Buffer, then transfers the contents
of the Clock Buffer into the AC.

AC to Clock Buffer-Preset (CLAB)

Octal Code:

Operation:

6133

Causes the contents of the AC to be

transferred into the Clock Buffer-

Preset; then causes the contents of
the Clock Buffer-Preset to be transferred into the clock counter. The AC
is not changed.
Load Clock Enable Register (CLEN)

NOTE
The clock counter can be read while it is

counting. Gating in the clock control section prevents data from being strobed out
of the counter before a specified time following a clock pulse. This time, approximately 300 ns, allows the data to be settled in the counter.

Octal Code:

6134

Operation:

Causes the contents of the Clock

This feature allows the counter to be read

any number of times without introducing
timing errors in counting; it allows the

Enable

into the AC.

counter to read the amount of time be-

Clock Status to AC (CLSA)

Octal Code:

6135

Operation:

Interrogates the Clock

tween intervals, and it also eliminates

false counts that are the result of reading

Input

and

Overflow Status flip-flops. The clock

the counter

one or

bits

are

transition from one state to another.

Programming Examples
*1
JMP

IPOINTER

SERVC

SERVICE

INTERRUPT

ROUTINE

*200
START:

CLA

CLL

ORDER

/ZERO

HIGH

CLOE

/LOAD

ENABLE

CMA

ICLEAR

DCA

HIGH

TAD

ENABLE

WORD

UNUSED

CLZE

ION

TURN

PROGRAM

/WAS

INTERRUPT

CLSK

SERVC:

JMP

RETURN:

HIGH:

Example Subroutine#1

—

CLOCK

FLAG

AND

CAUSED

/WAS

IGNORE

STATUS:

/READ
CLA

FLAG?

INCREMENT

ISZ

HIGH

/YE$:

RETURN

IAND

JMP

SOMEWHERE

/AFTER

RETURN

THE

HIGH

DID

4096*4096

CLEAR

NEGATIVE?

STATUS

JMP

COUNTS:

ORDER

WORD

NOT

OVERFLOW

SOMETHING

ION
JMP

ENABLE:

INO

RETURN

CLSA
SPA

INTERRUPT

IAND
MAIN

4210

MODE

/OVERFLOW:

/INTERRUPT

ENABLE

108

RATE

This example illustrates how

just over 16 seconds; with the clock set to its slowest
rate, it can mark time for over 100 days.

the DK8—ES Real-Time Clock can be used as a double-

precision (24-bit) free-running clock, using the clock

A simple routine can be written to interrogate elapsed

counter as the low-order 12 bits and a memory location

time by using the CLCA (Clock Counter to AC) com-

high-order 12 bits. Because all the registers of the
clock have been set to 0 initially by the clear key, it is
necessary that the program only zero the high-order
words, set the Enable Register, and turn on the interrupt. After 4096 counts, the clock counter overflows, signalling an interrupt. The service routine simply increments the highbrder word, then returns to the main
as the

mand.

EXample Subroutine #2

The DK8-ES can also easily

be programmed to function as an alarm clock, counting
off a period of time, giving an alarm, automatically re-

setting itself, and continuing. The alarm could be used to
ring a bell, as indicated in the example; however, a more
practical use might be to start an analog-to-digital converter to take a number of samples from an external

program.
With this program, time can be kept during program execution. With the clock set to its fastest rate (1 us per

source.

In this example, the bell will ring every second:

tick), this double-precision counter can mark time for
START:

——

CLA

TAD

COUNTER

/SET

COUNTER

ENABLE

ISET

ENABLE

-1@Efl

DECIMAL

CLAB
CLA
TAD

CLOE
AGAIN:

CLSK

SKIP?

ICLOCK

Mpv'l
CLSA
/YE$:

READ

IRING

BELL

STATUS

CLA
TAD

BELL

TLS
TSF
JMP.-l

JMP
COUNTER:

AGAIN

-1750

ENABLE:

OVERFLOW

BELL:

207

MODE

5360

AND

CLEAR

6
BUFFERED DIGITAL 'I/O

Buffered Digital 10 (DR8 E)

DR8-EA 12-CHANNEL

BUFFERED DIGITAL 1/0

GENERAL DESCRIPTION

The DR8—EA is contained entirely on one 8-1/2 in. Quad-

12-Channel Buffered Digital I /0 (see
can
be
used to control 12 discrete digital
Figure 6-1)

type board (M863). The module can be used in the PDP8/E OMNIBUS, BE8 expanded OMNIBUS, or BA8 expander.

The DR8-EA

switching circuits (externally located) and can also be
used to accept 12 discrete inputs from external sources.
The unit consists of IOT control logic, a 12-bit input buffer, a 12 bit output buffer, and 3 multiplexer 108 that control the flow of data for input and output operations. All
circuits are transistor-to-transistor (TTL) logic and are
mounted on a single PDP-8/ E module that plugs into the
OMNIBUS. Standard TTL outputs are connected to the
external load via two H854 connectors on the module. In-

puts from external sources are also connected to the
DR8—EA, using H854 connectors.

INTERRUPT
8 SmP

PDP-B/E

ACCUMULATOR

Output Transfers
Data outputs are updated under program control. Stan-

dard output drivers have a TTL 30-unit load capability.
For an output function, the computer issues a DBRO,

DBSO, or DBCO instruction. For DBSO instructions, only
logical ls in the AC are loaded into the output register;
AC bits containing logical 0s do not affect output register
bits. For DBCO instructions, logical 1s in the AC result in
logical Os in corresponding bits of the output register.
For DBRO instructions, the contents of the output register are transferred into the AC register.

l
Input Transfers

INPUT

BUFFER

OUTPUT

BUFFER
8E-0158

Figure 6-1 12-Channel Buffered Digital I/O -Block Diagram

Data

inputs must be TTL compatible, have negative

transition to 0.8V or less for a logical 1, and have a pulse

duration of greater than 50 ns. Pulse rise and fall time
should be less than 150 ns for maximum noise immunity.
In one mode of operation, the input register bits, after

A maximum of eight DR8—EA options can be used. Each

device selector code is determined by the user through
various jumpers. Device codes 50 to 57 are legal; however, the DR8-EA normally comes with device code 50

installed.

being set by the data inputs, remain set until read by a
DBRI instruction and cleared by a DBCI instruction. In
the second mode of operation, the input can be placed directly through gating on the bus and remains as long as
the input remains. The DBRI instruction is also used to

read the input data. When this IOT is issued, the contents

The normal configuration will be factory installed with

of the input register are gated to the AC via the

device selector code 50. The input will have Jumper A

OMNIBUS. A DBCI instruction, used with DBRI instruction, enables inputs that occurred too late to be read by
the next DBRI instruction, provided that the frequency
of input data is greater than the time elapsed between
the issuing of the DBRI instruction and the DBCI instruc-

(edge triggered flip-flop) installed at the factory. To
change to level Enables, use jumper B. The A and B lugs
are on all 12 bits. Jumpers will also be provided to isolate
the inputs from the interrupt and skip circuitry.

tion. Correct usage of this feature results in
time

”

“

zero dead

PROGRAMMING

for events. Any of the input lines can cause an in-

terrupt if the proper jumpers are selected. The interrupt
facility can be enabled by the DBEI instruction and disabled by the DBDI instruction.

The following instructions are used for DR8—EA oper-

ation. The X refers to a jumper selectable code; however, the DR8-EA normally comes with code 50 in-

stalled.
SPECIFICATIONS
Disable Interrupt (DBDI)

Parallel, 12 bits
TTL-compatible levels. Input
lines are clamped at +5V for
positive input protection.

Input Format:
Input Levels:

cause

Environmental:

0° C to 55

are

Octal Code:

65X1

Operation:

Set Interrupt Enable Flip-Flop. This

terrupt Request if In Flag equals 1.

the

Skip on Flag (DBSK)
Octal Code:

Operation:

65X2
Tests the In Flag. If the flag is a 1,
the next sequential memory location

is skipped.
Clear Selective Input Register (DBCI)

Octal Code:

Operation:

65X3
Ones in the AC clear the respective

bits in the Input Register.

10%to 90%relative humidity

(non-condensing)
Power Requirements:

interrupts that

tests the In Flag and causes the In-

input to become a logical 1.
Optional inputs bypass the
flip-flop for direct interrogation of input line status.
Parallel, 12 bits
TTL-compatible levels capable of driving 30 unit loads.
Output lines are protected
from short circuits to ground.

Output Format:
Output Levels:

Operation:

Enable Interrupts (DBEI)

Inputs to Inverter buffers are
normally held high by resistors. A negative transition of
0.8V or less will

65X0
Disable all

caused by logical 1 on input.

Input Connections
and Pulse Width:

Octal Code:

Transfer Input to the AC (DBRI)

+5.0V, 2.25A (worst case)

Octal Code:

65X4

Operation:

Transfers the complete 12-bit Input

Jumper Descriptions
The following chart will enable the user to change the

Clear Selective Output Register (DBCO)

IOT device code by changing the jumper across the spec-

Octal Code:

ified split lug.

Operation:

65X5
Ones in the AC clear the respective

bits in the Output Register.
Device Selector

Jumper

50 (normal conf )

6H 7H 8H

Octal Code:

6H 7H 8L

Operation:

6H 7L 8H

Set Selective Output Register (DBSO)

65X6
Ones in the AC set the respective bits

in the Output Register.

SH 7L BL

GL 7H 8H

Transfer Output to AC (DBRO)

GL 7H 8L

Octal Code:

65X7

BL 7L 8H

Operation:

Transfer the complete 12-bit Output

6L 7L 8L

6-2

Solution: Define the same corresponding input and

Programming Examples

output bits; i.e., bit 0 input event

——

bit 0 output function.

Example 1: Assume that 10 bits of digital information
are to be transferred to the PDP-8/ E. When the data is

SET

UP:

ready, the occurrence of one of two possible pulses
defines this information.

CLA:

/CLEAR

CLL

/ALL

DBCI

/CLEAR

THE

INPUT

DBCO

/CLEAR

THE

OUTPUT

DBSK

/SKIP
.-1

/GO

INPUT:

CLA:

CLL

/CLEARS

UP:

CLA:

/CLEAR

CLL

AND

THE

CMA

/ALL

ONES

DBCI

/CLEAR

THE

INPUT

DBCO

/CLEAR

THE

OUTPUT

DBEI

/ENABLE

ION

/TURN

THE

AND

DBSO

/SET

CORRESPONDING

DECO

/CLEAR

JMP

PULSE
/CLEAR

PROGRAM/DO

BACK

THE

OUTPUT

LINK

/GET

(AN

LINK

FLAG

THE
AC

DBRI

DBCI
SET

THE

JMP

Solution: Define input bits 2-11 as data and remove the

interrupt jumpers. Define input bit 0 as process one; this
causes an interrupt. Define input bit 1 as process two,
and this also causes an interrupt. Define output 0 as the
data accepted pulse.

AND

THE

ONES

CMA

LINK

INFORMATION

CORRESPONDING
HAS

BEEN

INPUT

(TO

OUTPUT

AC)
BIT

OUTPUT

BIT

CREATED.)

BIT

SOMETHING

HITH

DATA

THE INTERRUPTS

CONTINUE

IN DR8-EA

(DETECT

OTHER

EVENT)

INTERRUPTS

JMPPROGRAM/JUMPTOPROGRAMTHAThmITSEORDATA

INTERFACE

When an interrupt occurs, the program goes to the loca-

The DR8-EA interfaces to the PDP-8/E OMNIBUS by
plugging directly into the bus. Two edge connectors on
the M863 Module provide the interface to the outside
world. Signals leaving the board (12 bits parallel) are
high (+3V) for a logical false and ground (0V) for a logical true. Each output line has approximately 20 mA of
drive (high level) and 20 mA of sink (low level). Output
levels remain fixed except when changed by the proces-

tion specified and jumps to the interrupt handling routine.

INPUT

DESK

ISKIP

SKP

ISKIP

JMP

INPUT

/GO

FLAG
CHAIN

ROUTINE

PROCESSING

DATA

sor.

Data processing routine will define and accept the data.

INPUT:

CLL

CLA:

THE

ICLEAR

DBRI

/TRANSFER

DBCI

/CLEAR

DCA

TEMP
4060

IBIT

ICREATE

DECO

IEND

CLL
TEMP

WERE

SET

DBSO

TAD

“

THAT

BITS

INTERRUPT

IDISABLE

CLA:

THE

Signals entering from the outside world must be in TTL
format. The input represents approximately two unit
loads. When jumpered for
edge detection ”, a negative-going edge (3V to 0V) is sensed. The signal must
remain low (0V) for at least 50 ns. When sensing for an
external level (jumpered to bypass the flip-flop) ground
(0V) represents a logical true, and a high (+3V) represents a logical false. With all bits jumpered in this
manner, the option represents a 12-bit parallel input reg-

LINK

ISTORE

DBDI
TAD

AND

ICLEAR
/ADD

SNA

START

THE

PULSE

(1.2

PULSE)

LINK

THE

FOR

BIT

ICHECK

PULSE

JMP

/JUMP

PROCESS

TWO

JMP

/JUMP

PROCESS

ONE

THEN

PROCESS

ister rather than an event decoder.

An optional method for interfacing to the DR8-EA is as
THE
P2:

DATA

follows: two BC08J-X cables are provided. Each cable

(ribbon-type) is terminated by a Berg-type connector on
(for interfacing to the DR8-EA module) and a
standard DEC Flip-Chip on the other. One cable is used
for the input and the other for output.

CLA
TAD

TENP

IADD

TOTAL

AND

K1777

/MASK

FOR

DCA

DATA

ISTORE

one end

DATA

Cable Descriptions

Example 2: Twelve random events may occur at any
time; the object of this exercise is to control their corresponding output functions.

The 7008418 cable is used to jumper the input to the

output for diagnostic purposes. The cable is part of the

6-3

DR8-EA option. If the user desires interface cables, the

The input and output pins corresponding to the AC bits

BCOBJ cables can be purchased. The BCOSJ cable in—

enabled on the M863 Module (DR8—EA) are as follows:

cludes the 1210073-0 Berg connector, a cable, and the
M953 Module.

Input and Output
End Pins (BC08J )

PIN CONNECTIONS

Input

Grounds

Output

A1 C2

D—Bito

D—BitO

Bitl—D2

C1F2

F—Bitl

BitZ—Dl

F1J2

J—Bit2

Bit3—E2

K1L2

Bit 0

L—Bit3

Bit4—E1

N1N2

N—Bit4

Bit5—H2

R1R2

R—Bit5

Bite—H1

T1U2

T—Bit6

Bit7—K2

V—Bit7

Bits—J1

Z—Bit9

Bit9——M2

——

Bit 10

DD—Bit 11

——

Bit 10

DD—Bit 11

—

Bit 11—P2

6-4

7
LABORATORY MOUNTING PANEL

H945 MOUNTING PANEL

The laboratory mounting panel is designed for compact,

phone jacks, four 10-turn vernier controls, and two connectors. Panel requires

versatile packaging of modular accessory equipment for

laboratory environments. The panel is a 19-in. rackmounted unit with H945 Mounting Panel frame and housing that accepts plug-in type modules or module panels.
Modules can be single-width, double-width, or other multiples of single-width, and may contain a printed circuit

three single-panel unit widths.
AM8-ED

16-channel
Simple analog input Panel
A D panel used for AM8-EA multiplexer
inputs. Panel contains two connectors
and requires a single-panel unit width.

VM03

Tektronix Model 602 Oscilloscope Mount-

card mounted on the vertical dimensions. Controls and

input/output connectors for peripheral equipment are
mounted on the module front panel. Modules or module
panels are attached to the panel frame, using one fastener at the top and bottom of the module panel.
The following options are available:
H945

H945-BA

Housing (rack-mountable chassis) for
mounting laboratory peripherals, including space for mounting 11 panel
units; 5 single-panel units; 3 double-panel
units, and a single 1-1/2 panel, unit filler
panel.
115V Table-Top version with super cover.

——

ing Hardware
VR14

115 Vac CRT Display with mounting hardware for Rack-Mounted version.

VR14-A

230 Vac CRT Display with mounting hardware for Rack-Mounted version.

VR14-B

100 Vac CRT Display with mounting hardware for Rack-Mounted version.

VR14-C

115 Vac CRT Display with mounting hardware for

VR14-D

230 Vac CRT Display with mounting hardware for

H945-BB

230V Table-Top version with super cover.

H945-CA

115V Rack-Mounted version

H945-CB

230V Rack-Mounted version

AM8-EC

Analog input Panel ~16-channel A/ D
panel used for AM8-EA multiplexer
inputs. Panel contains four 3—conductor

VR14-E

Table-Top version.

100 Vac CRT Display with mounting hardware for

DK8—EF

Table-Top version.

Real-Time Clock Input Panel

—

3 ex-

ternal Schmitt trigger inputs, 3 outputs,
external clock in, and external overflow.
DR8—EC

12-bit output and 12Digital I/O Panel
bit input, including two M904 Modules.
—

digital equipment corporation