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DEC-8I-HR1A-D

December 1970

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DEC-8I-HR1A-D

PDP-8/1

MAINTENANCE MANUAL

VOLUME

DIGITAL

EQUIPMENT

CORPORATION

•

MAYNARD, MASSACHUSETTS

1st

Printing October 1968

2nci Printing March

1968

Printing May 1969
4th Printing July 1969
3rci

5th Printing March 1970

The material in this manual is for information purposes and is subject to change without notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS
Page

CHAPTER

INTRODUCTION AND DESCRIPTION
1-1

1.1

Introduction

1.2

Description

1-1

1.3

Pertinent Documents

1-2

1.4

Abbreviations

1-2

CHAPTER 2
INSTALLATION
2.1

Space Requirements

2-1

2.2

Environmental Requirements

2-2

2.3

Power Requirements

2-2

2.4

Cable Requirements

2-6

2.5

Installation Procedure

2.6

Internal

2.7

System Configurations

2-8

2.8

I/O Interface

2-8

2-6
2-8

Option Installation

2.8.1

I/O Bus Signal

2-8

2.8.2

I/O Cables

2-8

2.8.3

Logic Levels and Level Converters

2-8

2.8.4

Interface Signal Connections

2-9

CHAPTER 3

OPERATION
3.1

3-1

Controls and Indicators

3.1.1

Computer

3~'

3.1.2

Teletype

3-6

3.2

3-6

Operating Procedures

3.2.1

Common Procedures

3-6

3.2.2

Manual Loading Procedures

3-6

3.2.3

Teletype Loading Procedures

3-6

3.2.4

Off- Line Teletype Procedures

3-8

III

CONTENTS (Cont)
Page

CHAPTER 4

THEORY
SECTION I: BLOCK DIAGRAM DISCUSSION
4.1

Registers

4_]

4.1.1

Accumulator (AC)

4_]

4.1.2

Link (L)

4_1

4.1.3

Program Counter (PC)

4-1

4.1.4

Memory Address Register (MA)

4-1

4.1.5

Memory Buffer Register (MB)

4-1

4. 1 .6

Sense Register (SENSE or MEM)

4-1

4.1.7

Instruction Register (IR)

4-1

4.1.8

Switch Register (SR)

4-3

4.2

Major Register Gating Network

4-3

4.3

Timing and Control Elements

4-3

4.3.1

Timing Elements

4-3

4.3.2

Control Elements

4-3

4.4

Input/Output

4_3

4.5

Memory

4_4

4.5.1

Core Array

4-4

4.5.2

Memory Control

4-4

4.5.3

Address Selection

4-4

4.5.4

Inhibit Drivers

4-4

4.5.5

Sense Amplifiers

4-4

SECTION II: GENERAL THEORY
4.6

Time States/Time Pulses

4-4

4.7

Major States

4-5

4.8

Internal Data Flow

4-5

4.9

Instructions

4-5

4.9.1

Memory Reference Instructions

4-5

4.9.2

Augmented Instructions

4-7

4.10
4,10.1

Program Interrupt

4-12

Instructions

4-13

CONTENTS (Cont)
Page

SECTION III: DETAILED MEMORY THEORY
4.11

Overall Memory Theory

4-13

4.12

Memory Operation

4-13

4.12.1

Memory Control

4-13

4.12.2

ReadA^rite

4-15

4.12.3

Address Selection

4-18

SECTION IV: DETAILED PROCESSOR THEORY
4.13

Flow Diagram Interpretation

4-19

4.14

Timing

4-21

4.14.1

Manual Function Timing Generator

4-21

4.14.2

Manual Operations

4-21

4.14.3

Time States

4-24

4.15

Major States

4-26

4.16

Internal Data Flow

4-29

4.16.1

Source

4-29

4.16.2

Route

4-29

4.16.3

Destination

4-29

4.17

Operating Instructions

4-31

4.17.1

Instructions

4-31

4.17.2

Memory Reference Instructions

4-31

4.17.3

Direct/Indirect Addressing

4-38

4.17.4

Augmented Instructions

4-39

CHAPTER 5

MAINTENANCE
5.1

Equipment

5-1

5.2

Programs

^"^

5.3

Preventive Maintenance

5-3

5.3.1

Weekly Checks

5-3

5.3.2

Preventive Maintenance Tasks

5-3

5.4

Corrective Maintenance

5-4

5.4.1

Preliminary Investigation

5-4

5.4.2

System Troubleshooting

5-4

5.4.3

Logical Troubleshooting

^~^

CONTENTS (Cont)
Page

5.4.4

Circuit Troubleshooting

5-5

5.4.5

Repairs and Replacement

5.4.6

Validation Tests

5-7

5.4.7

Recording

5-7

5.5

Adjustments

5-6

5-8

5.5.1

Power-Up Threshold Adjustment

5-8

5.5.2

Memory Alignment Procedure

5-8

5.6

ASR33 Teleprinter and Control Maintenance

5-12

5.6.1

Equipment

5-14

5.6.2

Programs

5-14

5.6.3

Preventive Maintenance

5-14

5.6.4

Corrective Maintenance

5-15

5.7

Spare Parts

5-17

5.8

Mechanization Charts

5-19

ILLUSTRATIONS
2-1

PDP-8/I Pedestal Dimensions

2-1

2-2

Rack Mounted PDP-8/I Dimensions

2-2

2-3

PDP-8/I Installation in Standard DEC Cabinet

2-3

2-4

PDP-8/I Installation in Bud Cabinet

2-4

2-5

PDP-8/I Installation in Emcor Cabinet

2-5

2-6

System Configurations

2-7

I/O Bus Configuration

2-8

I/O Signal Connections

2-9

3-1

PDP-8/I Front Panel

3-1

3-2

Teletype Model ASR33 Console

3-5

4-1

System Block Diagram

4-2

Memory Reference Instruction Bit Assignments

4-6

4-3

lOT Instructions Bit Assignments

4-8

4-4

Group

Operate Instruction Bit Assignments

4-8

4-5

Group 2 Operate Instruction Bit Assignments

4-1

4-6

Memory System, Block Diagram

4-14

4-7

Memory Operations Timing Diagram

4-16

4-8

Simple Core Memory Plane

4-16

ILLUSTRATIONS (Cont)
Page

4-9

Memory Address Selector and ReadA^rite Current Control

4-18

4-10

Manual Function Timing Diagram

4-22

4-11

System Timing Diagram

4-25

4-12

Data Flow

4-13

Direct and Indirect Address Selection, Simplified Flow Chart

4-14

lOT Generation

5-1

IC Location

5-2

IC Pin Location

5-3

Memory Control Waveforms

5-4

Representative ReadA/rite Current Waveforms

5-10

5-5

Representative Inhibit Current Waveforms

5-13

5-6

Representative Sense Amplifier Waveforms

5-13

5-7

Teletype Connections

5-8

Teletype Signal Waveform and Bit Relationship
for the Character "U"

^-30
4-40
^~^^

^"^
^"^

^~"

5-16

5-17

TABLES
3-1

Computer Controls and Indicators

3-2

Teletype Controls and Indicators

3-7

3-3

Readin Mode Loader Program

3-8

4-1

Example of Register Contents During JMS Instruction

4-35

5-1

Maintenance Equipment

5-1

5-2

Maintenance Programs

5-3

Type H704 Power Supply Outputs

5-4

Teletype Maintenance Tools

5-5

Teleprinter Maintenance Programs

5-6

Spare Parts for Keyboard-Model ASR33 Teletype

5-7

Spare Module List

5-8

Recommended Spare Diodes

5-9

Recommended Spare Transistors

5-10

Recommended Spare Integrated Circuits

5-19

5-11

Spare Miscellaneous Components and Parts

5-19

5-12

Sample Mechanization Chart

5-13

Fetch Cycle, AND, TAD, ISZ,

-''^

5-4

5-14
5-14
5-18

^'^^
5-18
5-18

5-20

DCA, and

JMS Instruction Mechanization Chart
VII

5-20

TABLES (Cont)
Page

5-14

Fetch Cycle,

OPR Instruction Mechanization Chart

5-22

5-15

Fetch Cycle, JMP Instruction, Mechanization Chart

5-29

5-16

Fetch Cycle, lOT Instructions, Mechanization Chart

5-30

5-17

Execute Cycle, AND Instruction, Mechanization Chart

5-30

5-18

Execute Cycle, TAD Instruction, Mechanization Chart

5-33

5-19

Execute Cycle, ISZ Instruction, Mechanization Chart

5-34

5-20

Execute Cycle,

DCA Instruction, Mechanization Chart

5-35

5-21

Execute Cycle, JMS Instruction, Mechanization Chart

5-36

5-22

Defer Cycle, JMP Instruction, Mechanization Chart

5-37

5-23

Defer Cycle, JMP Instruction, Mechanization Chart

5-38

5-24

Word Count Cycle, Mechanization Chart

5-41

5-25

Current Address Cycle, Mechanization Chart

5-42

5-26

Break Cycle Mechanization Chart

5_43

5-27

Signal Origins

5-45

VIII

PDP-8/I Pedestal and Cabinet- Configuration

CHAPTER 1
INTRODUCTION

AND DESCRIPTION
1

In terms of operating characteristics, speed,

INTRODUCTION

programming and available peripheral devices,
the PDP-8/1 is completely compatible with the

This manual covers Installation, operation,

PDP-8.

theory, and maintenance of the Programmed
Data Processor - 8/1 (PDP-8/l) . It is the intent
of this manual to provide the field service en-

gineer or maintenance technician who is familiar
with digital logic circuitry with the information
he needs to install and maintain a PDP-8/1
system. This manual is largely written under the

assumption that the reader is conversant with
digital's system of logic notation . If this is
not the case, the reader should refer to appli-

The PDP-8/1 performs one addition in 3.0 \is
(with one number in the accumulator), permitting a computation rate of 333,333 additions per
second to be achieved. It performs subtraction
in 6.0 |js (with the minuend in the accumulator)
using two's complement addition.

cable sections in the appendix for a description.

The PDP-8/1 is a one-address, 12-bit, fixedword-length, parallel computer using two's
complement arithmetic. Normal cycle time of
the 4096-word (referred to as 4K), randomaccess, magnetic-core memory is 1 .5 jjs. An
additional 4K of memory with extended memory
control may also be added to the system by plug-

Multiplica-

tion takes approximately 360 \xs , using a subroutine that operates on two signed 12-bit numbers to produce a 24-bit product, leaving the
12 most significant bits in the accumulator.
Division of two signed 12-bit numbers takes
approximately 460 |js, using a subroutine that
produces a 12-bit quotient in the accumulator,
and a 12-bit remainder in core memory. The
optional Extended Arithmetic Element (KE8I)
performs similar multiplication and division
operations in 6.0 and 6.5 |js, respectively.

ging the memory modules directly into the system in spaces provided. As much as 32K of
memory is available as well as other options,

Flexible, high-capacity, input/output capabilities of the computer allow it to operate a variety

with their control logic internal to the basic
machine. Standard features of the system in-

of peripheral equipment. In addition to the
Teletype keyboard/printer and perforated -tape
reader/punch, equipment supplied with a basic

clude indirect addressing, facilities for instruction skipping and program interruption as functions of input/output-device conditions, and
high-speed information transfers with massmemory devices via a cycle-stealing data break.

1.2

DESCRIPTION

The integrated-circuit (PDP-8/1) is a smallscale general -purpose computer that functions
as an independent information -handling facility in a large computer system, or as the
control element in a complex processing
system.

1-1

PDP-8/1, the system can operate a number of
optional devices. These options include highspeed perforated-tape reader and punch, card
reader, line printer, ana log -to-digital converters, cathode-ray-tube displays, magnetic drum
systems, magnetic disk-file systems, and magnetic tape equipment. Instruments or equipment of
special design can also be connected into the
PDP-8/l system. The computer itself needs no
modification for the addition of peripheral devices.

The PDP-8/1 is completely self-contained and,
under normal conditions, requires neither spec-

iai power sources

nor rigidly controlled environ-

mental conditions.

A single source of

for the Program Assembler Language (PAL III),

15 VAC,

FORTRAN, FOCAL, utility subroutines, and
the maintenance programs (MAINDEC) pre-

60 Hz, single-phase power permits internal
power supplies to produce all required operating
voltages. M-series modules, using TTL-type
integrated circuit packs, ensure reliable operation in ambient temperatures between +32 and
+130°F.

pared by Digital are available to PDP-8/I users.
The 1st of programs currently In the library and
available is provided In Appendix D.
1

1.4

ABBREVIATIONS

PERTINENT DOCUMENTS

1.3

Listed below are the most-common ly used ab-

The following documents serve as source material
and complement the Information in this manual:

Logic Handbook , C-105 (1970 edition),

breviations of registers, key operations,

ponents, instructions and signal names.

Accumulator

A/D

Analog-to-dlgltal (converter or
converted signal)
Address

printed by DIGITAL, which notes the function

ADD or ADDR

and specifications of the M-series modules
and module accessories for the PDP-8/l.

Break state

BD
BRK RQST

Bus driver

printed by DIGITAL, which contains program-

Current address state

ming and operational data and the PDP-8/l
Users Handbook.

CLA

Small Computer Handbook , (1970 edition),

and II).

This manual covers operation and

maintenance of the Teletype unit.
4. Parts, Model 33 Page Printer Set , Bulletin
1 184B, contains an illustrated parts break-

down to serve as a guide to disassembly, reassembly, and ordering replacement parts for
the Teletype unit.

Clear accumulator (instruction or

CLR

Clear

CMorCOMP
CO NT

Complement

CP
D

Central processor
Defer state

DCA

Deposit and clear accumulator

DEP
DF
DIV

Deposit

DLI

Instruction List F-8I6 , printed by DIGITAL. E

This is a shirt-pocket

list of all memory
reference instructions, all augmented instruc-

Continue

(instruction)

DP
5.

Break request

signal)

3. Technical Manual, Automatic Send and
Receive Sets (ASR) , Bulletin 273B (Volumes
I

EAE
EX or EXAM
,

Data Field Register
Divide
Data line interface
Deposit
Execute state
Extended arithmetic element

Examine

tions, the most common lOT instructions, and

Fetch state

the ASCII code used with many l/O devices.

FLG
HLT

Flag

Halt

Instruction field

IFR

Instruction field register

com-

Instruction manuals and MAINDEC pro-

grams for appropriate input/output devices
are prepared by DIGITAL.
7. Digital Program Library Documents. Perforated program tapes and descriptive matter

1-2

INH

Inhibit

INST
INT

Instruction (key)

INTACK

Interrupt acknowledge

Interrupt

I/O

ION
lOP
lOT

PROG
PWRCLR

Input/Output
Interrupf on
Input/Output pulse
Input/Oufput (informaHon)
transfer

Program
Power clear
Reader
Sense amplifier
Step counter (EAE)
Solenoid driver

RDR
SA
SC
SD
SENSE

Memory register (also MEM)

Instruction register

ISZ

Increment and skip if zero

MP
J MS

Jump (Instruction)
Jump to subroutine (instruction)

Start field

SING

Single (key)

KBD

Keyboard (Teletype)

SKP

Skip

Link

Start

MEM

Memory address register
Memory buffer register
Memory register (also SENSE)

ST
SR

SYNC
TAD

Switch register
Synchronize
Two's complement add (instruction)

Multiplier quotient register

MUL

Multiply

OP
OPR

Operate
Operate (class of instruction)

Parity

PA
PC

Pulse amplifier

TTO

Teletype out (Teletype teleprinter/

Program counter
Program interrupt

punch buffer)
Word count state

TP
TS
TT
TTI

Time pulse
Time state
Teletype

Teletype in (Teletype keyboard/
reader buffer)

1-3

CHAPTER 2
INSTALLATION

This chapter contains installation Information

be purchased unmounted for installation in a

and physical specifications of the PDP-8/I and

customer cabinet.

its

2.1

Figure 2-1 gives dimensions

mounted PDP-8/1. Figures 2-2
through 2-5 show detailed mounting information
for installing the PDP-8/1 into standard DEC,
BUD, and EMCOR racks.

options.

for the pedestal

SPACE REQUIREMENTS

Access space must be provided at the installation
site to accommodate the PDP-8/l and peripheral
equipment, and to allow access to all doors and
panels for maintenance.

Minimum service clearance on all standard DEC
computer cabinets is 8-3/4 in. at the front and
14-7/8 in. at the back.

The standard Teletype automatic send receive
set requires a floor space of approximately 22The PDP-8/1 is available in either the pedestal
or rack mounted configuration. The rack mount- 1/4 in. wide by 18-1/2 in. deep. The Teletype
ed configuration and peripherals may be purchas- signal cable requires the Teletype to be placed
near the computer.
ed completely installed in DEC cabinets or may

Figure 2-1

PDP-8/l Pedestal Dimensions

2-1

2.2

ENVIRONMENTAL REQUIREMENTS

15A must be provided to operate a standard PDPTo allow connection of the computer to the
power cable, this source should be provided with
8/1 .

Ambient temperature at the installation site can
vary between 32° and 130°F (0°and 55*C). To
extend the life expectancy of the system, however, it is recommended that the temperature at
the installation site be maintained at between
70° and 85°F (between 20° and 30°C)
During shipping or storing of the system, the

a Hubbell 3-terminal connector plug.

A rack

mounted PDP-B/I has a 20A twist-lock plug;
systems that draw more than 20A use a 30A twistlock plug. All free-standing cabinets require
independent 115V receptacles. However , these
units may be turned on or off, or controlled from
the PDP-8/1 operator console .

ambient temperature may vary between 32° and
130°F (between 0°and 55°C). All exposed
surfaces of all DEC cabinets and hardware are
treated to prevent corrosion, but exposure of
systems to extreme humidity for long periods of
time should be avoided.

2.3

Upon special request, a PDP-8/1 can be
constructed to operate from a 220V (±33V),
60 Hz (±0.5 Hz), single-phase power source
or from a lOOV (±15V), 50 Hz (±0.5 Hz),

POWER REQUIREMENTS

single-phase power source.

A source of 115V (±17V), 60 Hz (±0.5 Hz),
single-phase power capable of supplying at least

•19" REF-

23 5/16" REF

1 3/4"

REF.

o o

PDP-8/I

CONSOLE

30-11/16"

PDP-e/i

PROCESSOR

25 1/8"

POWER
SUPPLY
(704A)

3/4"
REF.

^
FRONT VIEW

Figure 2-2

SIDE VIEW

Rack Mounted PDP-8/l Dimensions

2-2

VIEW SHOWN WITHOUT FRONT DOOR (SUPPLIED BY DEC IF DESIRED)
AND WITHOUT LOWER COVER PANEL (SUPPLIED BY DEC IF DESIRED)

27" REF.

21-1/4 REF.

67-7/8"

O O

REF

POP- 8/1
PROCESSOR

POWER
SUPPLY
(704A)

I
T^i

IZL
33-13/16" REF.

Figure 2-3

PDP-S/l Installation in Standard
DEC Cabinet

2-3

VIEW SHOWN WITHOUT FRONT DOOR (SUPPLIED BY BUD IF DESIRED)
AND WITHOUT LOWER COVER PANEL (SUPPLIED BY DEC)

BUD RADIO INC DOOR
PT #60-2344

24 1/8 REF

25 t/2" REF

—

69 7/8"

POP- 8/1
CONTROL
PANEL

1/8"

REF

o o

REF

I
i

23 5/16" REF

PDP-8/1

POWER
SUPPLY

PROCESSOR

704A

h tJ

Figure 2-4

PDP-8/1 Installation in Bud Cabinet

2-4

VIEW SHOWN WITHOUT FRONT DOOR (SUPPLIED BY EMCOR IF DESIRED)

AND WITHOUT LOWER COVER PANEL (SUPPLIED BY DEC)

23 9/16

REF

PDP-8/I

CONSOLE

68 3/8

POWER
SUPPLY
704A

3/8" REF
T

Figure 2-5

PDP-8/1 Installation in Emcor Cabinet

2-5

REF,

2.4 CABLE REQUIREMENTS

from the shipping carton. Remove the Teletype
console from the carton, holding it by means of

Signal conducfor cables with Type WOll Cable
Connectors provide signal connections between

the wooden pallet attached to the bottom. Snap

the computer and the optional equipment in free-

side of the Teletype stand. Remove the Teletype console from the pallet, and mount it on
the stand. Connect the Teletype console to

standing cabinets.

the power pack in place at the top of the rear

These cables are connected

by plugging the WOll connectors into standard
module receptacles. Cables connect to cabinets
through a drop panel in the bottom of cabinets.
Subflooring is not necessary because casters elevate the cabinets high enough from the floor to
provide sufficient cable clearance. Cable details are Included in the I/O Interface

paragraph.

the power pack (a six-lead cable attached at
the console is connected to the power pack by

means of a white plastic Molex 1375 Female
Connector which mates with a male output plug
on the power pack)
Pass the three-wire power
cable, and the seven -conductor signal cable
(which is terminated in a type W076 Cable
Connector Module) through the opening at the
.

2.5 INSTALLATION PROCEDURE

lower left-hand corner of the Teletype stand;
then replace the back cover of the stand by

Installation of a PDP-8/1 system requires no
special tools or equipment. A fork-lift truck,

means of the two mounting screws.

or other pallet-handling equipment, and normal

4. Dress the Teletype cable under the PDP-B/l
cabinet, through the large opening and into

hand tools should be available for receiving and
installing the equipment. To install the computer
observe the following procedure:
1

Place the computer package near the final

logic frame slot J12. It is necessary that this
cable be dressed through the cable clamp at the
lower rear corner of the logic frame where the
power cables are secured. A second clamp

installation location.

Pry the top, and side
sections of the wooden shipping crate apart

may be desirable at the bottom of the PDP-B/l
cabinet to assure that sufficient slack exists

with a hammer, and wedge at the staple joints.

irrespective of the Teletype position,

Unfasten the four bolts holding the computer

frame to the pallet. Using a ramp, slide the
computer off the pallet to the final location.

of the Teletype power cable to the connector

When a cabinet mounted PDP-8/1 is installed,

at the rear of the computer power supply chassis.

a similar procedure is used.

First,

shipping straps with cutting shears.

remove the
Remove

the packing material, and the cardboard crate

Connect the three-prong male connector

6o Set the PANEL LOCK switch to the full
counterclock wise position (OFF). Set the

to disassemble the wooden corner supports.

POWER LOCK switch to the full counterclockwise position (OFF). Set the main powerswitch

Remove the plastic cover. Remove the two
machine screws in the rear of the computer

(circuit breaker at rear of computer power

logic frame that hold it firm.

supply chassis) to ON.

This allows the

logic frame to be serviced pulling it out on the

Turn the POWER switch on.

tracks

3, Open the Teletype carton, and remove the
packing material. Remove the back cover from
the stand. Remove and unwrap the copyholder,

8. Install a roll of printed paper into the Teletype keyboard/printer, and install a tape In the

chad box, and power pack .

Remove the stand

2-6

punch as described in the Teletype technical
manual

Set the LINE/OFF/LOCAL switch to LINE.

ON pushbutton

10.

Turn the power OFF.

Strike several

This completes the installation of a standard

keys, and note whether or not the printer and
punch operate. Check the operation of the
printer with the LINE/OFF/LOCAL switch set

verify the operating capability of the system.

Press the punch

LOCAL.

PDP-8/I system. Before normal operating use,
Perform the power supply checks, and run the

complete set of diagnostic programs (MAINDECs) as described in Chapter 5.

After completion of these checks,

set the switch to OFF,

(FRONT)

PRIORITIES!

priorities;

AFOt

PT08

AFOI 2
D/A CONVERTER 3

D/A CONVERTER 2
DF32 3

priorities:

PRIORITIES:

vc8/i scope

0F32
DS32 2
1

PTOe 2
DF32 3

AF04A

CABINET,
CABINET,
TC58 CABINET,
TU20 CABINET,

DECTAPE

DRUM CABINET,
COMMUNICATION SYSTEM
CABINET,

SHOULD ALL BE MOUNTED
TO THE LEFT OF THE
OPTION

ALWAYS RESERVED
FOR PC 8/1

OS 32 OR MM -8/1
DS32 EXPANDS DOWN
MM 8/1 EXPANDS UP

READER/PUNCH

CABINET.

DS32 OR MM-8/I
DS32 EXPANDS DOWN
MM 8/1 EXPANDS UP

PDP-8/I

CONSOLE

PROCESSOR

MM 8/1
MEMORY EXPANSION

MC8/I
MP8/I
KE8/I
KP8/I
PC8/I
VC8/I

704 A

POWER
SUPPLY

VP8/I

KW8/I
KA8/I
DM01

CAB-8/I^
OPTION

Figure 2-6

CABINET

System Configurations

2-7

CAB-8/I
BASIC

CABINET

2.6 INTERNAL OPTION INSTALLATION

vice, as shown in Figure 2-7.

Where physical

location of equipment makes series connections

The instal lation of the infernal opHons involves
the addition of the logic modules in the proper
locations. Turn off the computer before inserting
or removing any modules in the logic frame. Refer to both sheets of the modu le uti ization drawingsMU-8I-0-17for the locations of each moduleof all internal options. If an option involves
an external device, dress connecting cables
through the large opening from the logic frame to
theoption. Proper adequately ventilated mount-

impractical, or when cable length become excessive, additional interface connectors are

usually installed near the computer.

10 CABLES

TO
ADOmorjAL DEVICES

ing facilities are necessary to insure protection

and safety of the equipment. Refer to the system
configurations drawing (Figure 2-6) for proper
Figure 2-7

location of options.

I/O Bus Configuration

2.7 SYSTEM CONFIGURATIONS

2.8.2 I/O Cables

PDP-8/1 systems are mounted in standard DEC
cabinets. The basic cabinet contains the processor and the power supply. The other cabinets
and spaces in Figure 2-6 show the position priority assignments and the top priority when a
choice exists. The priorities are assigned with
considerations of ease of control, and cable

The standard PDP-8/1 I/O bus uses 18-conductor
93Qribbon cable that terminates into WOll
Cable Connectors. Terminals C,F,J,L,N,R,
and Uof receptacles JO 1 through J 10 are groundedwithinthe computer, and terminals D,E,H,J,
M,P,S,T, and V carry signals.
All PDP-8/1 I/O cable connections are made at
the assigned module receptacle connectors JOl
through JIO in the mounting frame, with the ex-

lengths.

2.8 I/O INTERFACE

ception of the Address Extend l,2,3inputs, and

The following paragraphs describe the PDP-8/1
I/O bus, the I/O cables, the logic level converters and their driving capabilities, and the
processor location terminals of each l/O bus

at location HOI

Data Field 0,1, and 2 outputs which terminate

signal

2,8.3 Logic Levels and Level Converters
2.8.1

I/O Bus Signal

The PDP-8/1 internal logic levels are positive
levels of +3Vand OV. The present DEC ex-

The PDP-8/1 employs a series I/O bus system
which allows interface connections to be made
between all of the external devices without
modifying the computer wiring. In a series I/O
bus, the computer sends all I/O signals to the
first devicewhich makes use of pertinent signals
and sends all of the I/O signals to the next de-

ternal peripherals function with negative

DEC

standard levels or pulses. The standard levels
are either ground potential (O.OV to -0.3V)

designated by an open diamond (O), or -3V

(-3Vto -4V) designated by a solid diamond ().
To provide compatibility between the internal
PDP-8/l levels and the external negative logic

2-8

levels, the computer inputs and outputs are con-

the M650 Negative Output Converter and Bus

verted by the M506 and M650 Level Converters

Driver modules which shift the PDP-8/I levels

(Drawing BS-8I-0-10).

of +3V and OV to DEC levels of OV and -3V.

Input interface signals to the computer use the

An M506 input voltage level of +3V is converted to OV as an I/O signal, and a OV input
signal converts to -3V. The M650 can drive

M506 Negative Input Converters which shift the
DEC standard negative levels of -3V and OV to'
PDP-8/I positive levelsof 0Vand+3V. A -3V
input produces an M506 output of OV, and a OV
input generates a +3V output. Inaddition, the
M506 contains positive-logic internal bus input-

20 mA at OV or sink 20 mA at -3V.

gating that allows the outputs from the Teletype

2.8.4 Interface Signal Connections

logic, extended memory internally generated

skip and interrupt, and AC CLEAR from the internal options to input to the major register

Figure 2-8 shows the I/O bus interface signals

gating network.

as well as the cable and signal locations.

The

signal direction is also shown by the logic levels
which are shownwith the functions in the active

I/O bus output signals to the external options except theMMSI, are first converted by

All

states

won
JOI

-O BAC 00(11
-O 8AC OKI)

—O
—O
-O
—
—

02(1)
03(11

0410
05(11

06(0
07(0

—

won

08(1)

J09
DATA
DATA
DATA
DATA
DATA
DATA

DATA
DATA

won
J02
02 •EZ •H2 •-

DATA

-O BAC 09(11

—O BAC 10(1)
-^O BAC 11(1)
BIOPKO)

ADD
ADD
ADD
ADD

D2 •-

01
02
03

E2
H2
K2

ADD
ADD
ADD
ADO
ADO

04
05
06
07
OB

MTO

DATA
DATA
DATA
DATA
DATA

INPUT BUS 00
INPUT BUS 01

INPUT BUS 04

INPUT
INPUT
INPUT
INPUT

B INITIALIZE

BUS 05
BUS 06
BUS 07

won

BUS OS

JOS
02

won
J10

ADO 09
DATA ADD 10
DATA ADO 11
BRK RQST
- DATA
IN
B BREAK
B ADD ACCEPTED
MEMORY INCREMENT
(5ATA

02 •-

•

M2 •-

won

K2 •M2 •-

P2 •S2 •T2 •-

won

~0 6MB 00(1)
-O 3MB 01(1)
—O BMB 02(1)

INPUT BUS 09
INPUT BUS 10
INPUT BUS 1
I

10 SKIP

-O BMB 03(11
BMB 04(0)

•

-O BM8 04(0

•

-O
—

BMB 05(0)
BMB 05(1)

INT HOST
AC CLEAR
B RUN
BTT INST
LINE (0)

Figure 2-8

I/O Signal Connections
2-9

H2
K2

••-

DATA 0!
DATA
1C
1 1
DATA
3 CYCLE
CA INCREMENT

BWC OVERFLOW

V2 •

JOS
D2 •-

—* BMB 03(01
—

02
03
04
05
06
07
OS

INPUT BUS 02
INPUT BUS 03

—
— BI0P2(0)
—» BlOPiKOl
— BTS3
— BTS
—
1

J03
02 •-

DATA
DATA

S2 •
T2 •
V2 •

CHAPTER 3
OPERATION
counter (PC) is identified as PCOO, and the least

This chapter contains operating information for

(rightmost) significant bit is identified as

the PDP-8/I and the ASR33 Teletypewriter.
Operating information for the peripheral input/

output devices is contained in their respective

manuals.

lock switches) are of two types:

3.1

CONTROLS AND INDICATORS

butterfly switch-

es, and momentary-contact switches.

The butter-

fly switches are considered to be in their

The following subparagraphs contain detailed
information regarding the controls and indicators
of the PDP-8/I and the AS R33 Teletypewriter.
3.1 .1

Computer

Figure 3-1 shows the location of the PDP-8/l
controls and indicators. Although not marked

on the front panel, register bits are numbered
from left to right starting with zero.

Therefore

the most significant (leftmost) bit in the program

fully depressed, and are considered to be in their

one or on state when the bottom ha If of the
butterfly is depressed. The momentary-contact
switches include the Start, Exam, Load Add,
Cont, Dep and Stop switches. These switches
(except Dep) are actuated when the bottom half
The Dep switch is the reverse
is fully depressed.
of the above. Indicators are considered to be in
their on or one state when they are lit, and in
their off or zero state when not lit.

PDP-8/l Front Panel

3-1

zero or

off-state when the top half of the butterfly is

ili

Figure 3-1

PCll .

Table 3-1 contains a listing of the PDP-8/1 controls and indicators within their functions. The
PDP-8/l controls (except the power and panel

Table 3-1

Computer Controls And Indicators

Control or Indicator

Panel Lock key switch

Function

When turned clockwise, this key-operated switch disables all
controls except the Switch Register switches on the operator

console.

In this condition, inadvertent key operation cannot

disturb the program.

The program can, however, monitor the
content of SR by execution of the OSR instruction.
Power key switch

This key-operated switch controls application of primary power

When this switch is turned clockwise, primary

to the computer.

power is applied.
Start key

Starts the. program by turning off the program interrupt circuits
clearing the AC and L, setting the Fetch state, and starts the

central processor.

Load Add key

This key transfers the content of SR into PC, the content of

INST FIELD * switches into IF, the content of the DATA FIELD *
switches into DF, and clears the major state flip-flops.

Dep key

This key transfers the content of SR into MB and core memory
at the address specified by the current content of PC. The

ma|or state flip-flops are cleared. The contents of PC is then
incremented by one to allow storing of information in sequential
core memory addresses by repeated operation of the Dep key.

Exam key

This key transfers the content of core memory at the address
specified by the content of PC, into the MB. The content

of the PC is then incremented by one to allow examination
of the contents of sequential core memory addresses by repeated
operation of the Exam key. The major state flip-flop register
cleared. The
indicates the address of the data in the MB.

Cont key

This key sets the

RUN flip-flop to continue the program in the

state and instruction designated by the lighted console indicators,

at the address currently specified by the PC if key SS is not on.

Stop key

Causes the RUN flip-flop to be cleared at the end of the
instruction in progress at the time the key is pressed.

Sing Step key

This key causes the RUN flip-flop to be cleared to disable the
timing circuits at the end of one cycle of operation . Thereafter,
repeated operation of the Cont key steps the program one cycle
at a time so that the operator can observe the contents of registers
in each major state.

Activated only on systems containing the MC8/I, Memory Extension Control option,

3-2

Table 3-1
Operator Console Controls And Indicators (Cont)
Function

Control or Indicator

This i<ey allows execution of one instruction.

Sing Inst key

When the computer

started by pressing the Start or Cont key, the Sing Inst key

causes the RUN flip-flop to be cleared at the end of the last
cycle of the current instruction. Thereafter, repeated operation
of the Cont key steps the program one instruction at a time.

Switch Register switches

Provide a means of manually setting a 12-bit word into the
machine. Load the content of this register into PC by pressing
the Load Add key or load the content into the MB and core

memory by the Dep key. Under program control, the OSR
and LAS instructions can set the content of SR into AC.
Data Field indicators
and switches *

The indicators denote the content of the data field register
(DF), and the switches serve as an extension of SR to load DF
by means of the Load Add key. DF determines the core memory
field of data storage and retrieval.

Inst Field indicators

The indicators denote the content of the instruction field register
(IF), and the switches serve as an extension of SR to load the
IF by means of the Load Add key. IF determines the core memory
field from which instructions are to be taken.

and switches

Program Counter

The PC contains the location of the next instruction to be performed.

indicators

Memory Address
indicators

Usually, the contents of MA denote
the core memory address of the word currently or previously read
Indicate the content of MA.

After operation either the Dep or Exam key, the
indicate the core memory address |ust examined
contents of
or written.

or deposited into.

Usually, the contents of MB designate

Memory Buffer

Indicates the content of MB.

indicators

the word just written at the core memory address in MA.

Accumulator

Indicates the content of AC.

Link

Indicates the content of L,

Multiplier Quotient

Indicates the content of the multiplier quotient (MQ).
holds the multiplier at the beginning of a multiplication and

holds the least-significant half of the product at the conclusion
It holds the least-significant half of the dividend at the start

of division and holds the quotient at the conclusion.

Activated only on systems containing the MC8/1, Memory Extension Control option.

3-3

Table 3-1
Operator Console Controls And Indicators (Cont)
Control or Indicator

Function

Major State Indicators
Fetch

Indicates that the processor is currently performing or has

performed a Fetch cycle.

Execute

Indicates that the processor Is currently performing or has

performed an Execute cycle.
Defer

Indicates that the processor is currently performing or has

performed a Defer cycle.

Word Count

Indicates that the processor is currently performing or has

performed a Word Count cycle.
Current Address

Indicates that the processor is currently performing or has

performed a Current Address cycle.
Break

Indicates that the processor is currently performing or has

performed a Break cycle.

Miscellaneous Indicators
Ion

Indicates the
status of the INT. ENABLE flip-flop.
When lit, the interrupt control is enabled for information
1

exchange with an l/O device.
Pause

Indicates the

status of the PAUSE flip-flop when lit.

The PAUSE flip-flop is set for 2.75 ps by any lOT
instruction that requires generation of lOP pulses or by

any EAE instruction ** that require shifting of information.
Run

1
status of the RUN flip-flop. When lit, the
internal timing circuits are enabled and the machine performs

Indicates the
instructions.

Instruction Indicators

And

Indicates that the processor is currently performing or has

performed an And instruction.

Tad

Indicates that the processor is currently performing or has

performed a Tad instruction

Activated only on systems containing the KE8I, Extended Arithmetic Element option.

3-4

Table 3-1

Operator Console Controls. And Indicators (Cont)
Function

Control or Indicator
Instruction Indicators

Isz

Indicates that the processor is currently performing or has
performed an Isz instruction.

Dca

Indicates that the processor is currently performing or has

performed a Dca instruction.
Indicates that the processor is currently performing or has

Jms

performed a Jms instruction
Indicates that the processor is currently performing or has

Jmp

performed a Jmp instruction.
lot

Indicates that the processor is currently performing or has
performed an lot instruction.

Opr

Indicates that the processor is currently performing or has

performed an Opr instruction.

rm.
[

!??<yB*»«aHirSP':.'''.f-*.

& ^.
f^

•S-.

'^•'i^

'•^'

^ ;•;
; t
4
/,/ /.y li
/ J J J J .- ^

hi J J

)

Figure 3-2

Teletype Model ASR33 Console

3-5

3.1 .2

Teletype

Set the bit switches of the Switch Register

(SR) to correspond with the address bits of the

Figure 3-2 shows the location of the ASR33

Teletypewriter controls and indicators .

to be stored. Press the Load Add
key and observe that the address specified by
the SR is held in the PC, as designated by
lighted Program Counter indicators corresponding to switches in the 1 position and un lighted indicators corresponding to switches in the
first word

Table

3-2 contains a listing of the ASR33 controls and
indicators with a description of their functions.

3.2

OPERATING PROCEDURES

position.

Many means are available for loading and unloading PDP-8/I information. The means used
depend upon the form of the information, time
limitations, and the peripheral equipment connected to the computer. The following procedures are basic to any use of the PDP-8/I. Al-

Just set into the PC. Press the Dep key and
observe that the MB, and hence the core
memory, hold the word set by the SR.

though these procedures are used infrequently as
the programming and use of the computer become
more sophisticated, they are valuable in preparing the initial programs and learning the func-

Observe that the contents of the PC have
been incremented by 1 so that additional data
can be stored at sequentia addresses by repeated SR setting and Dep key operation .
3,

tion of machine Input and output transfers.

3.2.1

To check the contents of an address in core

Common Procedures

All of the following procedures require that the

PANEL LOCK switch be rotated fully counter-

3 .2 .2

memory, set the address into the PC as in step 2;
then press the Exam key. The Memory Buffer
indicates the contents of the Address.

The

contents of the PC are incremented by 1 with the
operation of the Exam key, so that the contents

and that the Power switch be
rotated fully clockwise (on).
clockwise

Set the SR to correspond with the data or

instruction word to be stored at the address

(off),

of consecutive addresses can be examined by

repeated operation of the Exam key after the

Manual Loading Procedures

original (or starting) address is loaded.

Any

address can be modified by repeating steps 2 and

Programs and data can be stored or modified

manually by means of the facilities on the operator console. The chief use of the manual data

3.2.3 Teletype Loading Procedures

storage facility is to load the Readin Mode Loader

program into the computer core memory. The
Readin Mode Loader (RIM) is a program used for
loading into the PDP-8/l other programs that
have been assembled on perforated tape In RIM
format. This program and the RIM tape format
are described in the PDP-8/l Users Handbook
(see Small Computer Handbook, C-800, 1968
edition) and in Digital Program Library descriptions. The RIM program is also listed in Table
3-3 for rapid reference and can be used as an
exercise in manual data storage. To store data
manually In the PDP-8/l core memory proceed as
follows:

3-6

Information can be stored or modified in the
computer under program control . For example,
having the RIM Loader stored In core memory
allows RIM format tapes to be loaded as follows.

1 .

Set the Teletype LINE/OFFAOCAL

switch to the LINE POSITION.

Load the tape in the Teletype reader by

setting the START/S TOP/FREE switch to the

FREE position, releasing the cover guard by
means of the latch at the right, loading the
tape so that the sprocket wheel teeth engage

the BIN Loader stored in core memory, program

the feed holes in the tape, closing the cover
guard, and setting the switch to the STOP

tapes assembled in Program Assembly Language
(PAL III) binary format can be stored as de-

position. Load the tape in the back of the
reader so that it moves toward the front as it

scribed in the previous procedure, except that
the starting address of the BIN Loader (J777q)

read. Proper positioningof the tape in the
reader finds three channeisbeing sensed to
the left of the sprocket wheel and five channels being sensed to the right of the sprocket
is

used in step 4. After storing a program in
this manner, the computer stops; the AC should
contain all O'sif the program is stored properly.
is

wheel
3. Load the starting address of the RIM
Loader program (7756g) into the PC using the
SR and the Load Add key.
4. Press the computer Start key and set the

Ifthe computer stops with a number other than
in the AC, a checksum error has been detect-

3-position Teletype reader switch to the
START position. The tape is read into

correctly, initiate it by loading the program
starting address (usually designated on the leader

memory by program control

of the tape) into the PC using the SR and Load
Add key. Then press the Start key.

ed; therefore, the program has been stored incorrectly, and the storage procedure should be
repeated. When the program has been stored

The RIM Loader program loads the Binary Loader
(BIN) program as previously described. With
Table 3-2 Teletype Controls and Indicators
Function

Control or Indicator

REL. pushbutton

Disengages the tape in the punch to allow tape removal or tape
loading.

B. SP. pushbutton

Backspaces the tape in the punch by one space, allowing manual
correction or rubout of the character just punched.

OFF and ON pushbuttons

Control use of the tape punch with operation of the Teletype

keyboard/pri nter

START/STOP/FREE switch

Controls use of the tape reader with operation of the Teletype.
In the lower FREE position, the reader is disengaged and can be
loaded or unloaded. In the center STOP position, the reader

mechanism is engaged but de-energized. In the upper START
position, the reader is engaged and operated under program
control

Keyboard

Provides a means of printing on paper in use as a typewriter and
pushbutton.
punching tape when the operator presses the punch
The keyboard also supplies input data to the computer when the

LINE/OFF/LOCAL switch is in the LINE position.
LINE/OFF/LOCAL switch

Controls application of primary power in the Teletype and controls
data connection to the processor. In the LINE position, the Teletype is energized and connected as an I/O device of the computer.
In the OFF position, the Teletype is de-energized.

In the

LOCAL

position, the Teletype is energized for off-line operation, and
signal connections to the processor are broken. Only line use of
the Teletype requires that the computer be energized through the

POWER switch if primary power for the Teletype is supplied from
a source other than the outlet at the back of the computer.

3-7

Table 3-3
Readin Mode Loader Program

Address

7756,
7757,
7760,
7761,
7762,
7763,
7764,
7765,
7766,
7767,
7770
777\,
7772,
7773,

777A,
7775,
7776,

Octal
Content

Mnemonic

Tag

KCC

/CLEAR AC AND FLAG

6031

KSF

/SKIP IF FLAG =

5357
6036
7106
7006
7510
5357
7006

JMP

6032

BEG,

KRB

SPA

JMP BEG+1
RTL

6031

KSF

5367
6034
7420
3776
3376
5356

JMP .-1
KRS

SNL

DCA TEMP
DCA TEMP
I

JMP BEG
TEMP,

/CHANNEL 8 IN ACO
/CHECKING FOR LEADER
/FOUND LEADER
/OK,CHANNEL7IN LINK
/READ, DO NOT CLEAR
/CHECKING FOR ADDRESS
/STORE CONTENTS
/STORE ADDRESS

/NEXT WORD
/TEMP STORAGE

Assure that primary Teletype power is

ON.
2.

/LOOKING FOR CHARACTER
/READ BUFFER

RTL

The Teletype can operate separately from the
PDP-8/I for typing, punching tape, or duplicating tapes. To use the Teletype in this manner
follow the procedure described below.
.

.-1

CLL RTL

3.2.4 Off-Line Teletype Procejdures

Comments

Set the Teletype LINE/OFF/LOCAL

SHIFT keys with the left hand; press and hold
the REFT key; press and release the P key.
When the required amount of leader has been
punched, release the REFT key, then CTRL and
SHIFT keys. To produce the 3378 code leader,
simultaneously press and hold both the REFT
and RUB OUT keys until a sufficient amount
of leader has been punched.

If an incorrect key is struck while punching a
tape, the tape can be corrected as follows. If

switch to the LOCAL position.

the error is noticed after typing and punching

Load the punch as follows. Raise the
cover and manually feed the tape from the
3.

top of the roll into the guide at the back of
the punch .

N characters, press the punch B.SF. (backspace) pushbutton N +
times and strike the
keyboard RUB OUT key N +
times. Then

Advance the tape through the

punch by manually turning the friction wheel;

continue typing and punching with the character which was In error.

then close the cover.

4. Energize the punch by pressing the
pushbutton, and produce about 2 ft of leader.
The leader-trailer can be either 200s or
377 code. To produce the 200 code leader,
simultaneously press and hold the CTRL and

To duplicate and obtain a listing of an existing
tape; load the tape to be duplicated In the paper

LOCAL/LINE switch to
LOCAL, turn the punch on, and turn the paper

tape reader. Set the
tape reader on

3-8

CHAPTER 4
THEORY

This chapter is divided into four sections and
covers the theory of operation of the PDP-8/l

4.1.4 Memory Address Register (MA)

Computer. Section I contains a discussion of
the theory at a block diagram level; Section II

This 12-bit register contains the address in core

contains a discussion in terms of general theo-

writing. This address is decoded by the memory
selection matrix to permit addressing of all

ry of operation; Sections

III

and IV cover de-

memory that is currently selected for reading or

4096 words of core memory

tailed memory theory and detailed processor

theory, respectively.

4. 1 .5

Memory Buffer Register (MB)

SECTION
BLOCK DIAGRAM DISCUSSION

All data to be written into core memory is loaded

The following paragraphs discuss the major

provided by the major-register gating network,
the MB accepts data from any of the major registers in the processor and, during a high-speed

first into the 12-bit

e lements of the PDP-8/l as shown on
the simplified system block diagram (Figure 4-1).

f unctiona

MB. Through the facilities

data-break transfer, from mass-memory devices.
Its only output capability,

4.1

access to core memory, is through the processor
interface to optional peripheral equipment.

REGISTERS

4.1.1

other thanits direct

4.1.6 Sense Register (SENSE or MEM)

Accumulator (AC)

This 12-bIt ACservesasan Input/output register

All data read from core memory is strobed first

for programmed Information transfers between

accepts data only
from the core memory and transfers data directly
to the Instruction Register (IR) and, through the
major register gating network, to other reginto this 12-bit register.

core memory and peripheral equipment , and as
a transfer register through which arithmetic and
logic operations are performed.

isters In the processor.

4.1.2
This

Link

(L)

-bit register extends the arithmetic facili-

4.1.7 Instruction Register (IR)

ties of the accumulator and serves as the carry

This 3-bit register contains the operation code of
the Instruction currently being performed by the

This 12-bit register contains the address of the
core-memory location from which the next in-

computer. The three most-significant bitsof
the current instruction load Into the IRfrom
SENSE during a Fetch cycle. The contents of
the IR are decoded to produce logic signals

struction will be taken.

for each of the eight basic instructions.

4.1.3

Program Counter (PC)

4-1

)

REGtSTER INPUT BUS

r'
r

CONTROL '

AZ.

AZ_

ACCUMULATOR

PROGRAM

MEMORY

MEMORY
ADDRESS
REGISTER (MAI

[AC!
(12 BITS)

COUNTER
112

(

-¥

BUFFER

BITSI

(12

(MB)

BITSI

(12

BITS]

MB Dfl

AC DATA 4

EXTERNAL
NEGATIVE 8US

INFHJT /OUTPUT

-J

LEVEL
CONVERTERS

r~f

CONTROL M
CONTROL iNPUT BUS -

t ft*

4^_

MEMORY ~1

I/O BUS

4036 12-BlT
WORD

NPUT
GATING
I

CORE -PLANE

MEMORY

iNT INPUT BUS -

iNTERNAL '

POSITIVE BUS

MB DATA 4—

CONTROL ^-

MEMORY EXT

SENSE
REGISTER
(12

TELETYPE /-^
SIGNALS "V4I

ii iA
SWITCH
REGISTER

INDICATORS

ISR]

Figure 4-1

OPERATOR'S CONSOLE

System Block Diagram

SITSl

FH
S

INSTRUCTION
REGISTER
13

SlTSt

4.1.8 Switch Register (SR)

operate In response to conditions established
in eitherthe processor or peripheral equipment,

The 12-bit SR performs a dual function in that it
permits the manual loading of eithera discrete
core-memory address into the PC or a 12-bit
data or control word into core memory The SR

control the flow of information between registers.
In addition, they initiate program interrupt op-

by 1 2 togg le switches located on the
operator's console. Actuation ofeitherthe
Load Address or Deposit keys then causes the
stored information to be loaded into the PC

erations during which subroutines enable the

servicing of peripheral equipment.

is loaded

The PDP-8/I has two bus systems to Input/output (I/O) equipment: an internal positive bus;

or MB, respectively.

4.2

4.4 INPUT/OUTPUT

MAJOR REGISTER GATING NETWORK

All internal data transfers occuring in the

PDP-8/I, except those performed through
hardwired facilities, such as MEM-*IR and MB-*
MEMORY, are implemented through the majorregister gating network. The network contains
a separate gate structure and a common register
input bus for the 12 bits. Transfers between registers and into and out of memory, as wel as the
implementing of logical and two's complement
arithmetic functions occur through the network.

and an external negative bus.
Typical of the available internal bus peripherals
are paper-tape reader and punch, punched-card
reader, incremental plotter, and CRT display

equipment. The control logic elements for these
options are located in the PDP-8/I processor logic
rack. The control logicinterfaces with the internal portion of the I/O bus and does not

operate through the I/O level converters.

The data-break peripherals , also optional ly
aval lable , are represented by mass -memory devices such as magnetic tape, magnetic drum,
and disk file systems These peripherals employ
the negative external l/O but to communlcdte
with the PDP-8/I All of the signals to and from
these options pass through the I/O level con-

Data and address information received through
the I/O interface also pass through this network
4.3

TIMING AND CONTROL ELEMENTS

4.3.1

Timing Elements

verters .

The processor and memory control circuits in the
standard PDP-B/I used fixed and variable delay
lines in place of timing clocks. Interleaving of

ATeletypeASR33AutomaticSend-ReceiveSet
is provided as standard equipment with the PDP-

fixed delay sequences provide asynchronous
control between the processor and the memory.
The overall cycle time of approximately 1.5 |js
For apis determined by the memory timing.

8/1

In addition to a manual keyboard and hard-

copy printout facilities, the ASR33 contains an
8-level paper-tape punch and a paper-tape
reader, all of which are interfaced with the

plications involving real time, the KWB/l Real
Time Clock option is added to the system.

processor through the Teletype control logic
This logic interfaces with the processor in a
similar manner as the Internal options.

4.3.2 Control Elements
The PDP-8/I integrated circuits operate on logic
levels of and +3V. At the present time, most
peripherals contain discrete-component control

Circuits in the PDP-B/l control program advance

and instruction skipping. These circuits, which

4-3

elemenfs operating on logic levels of

and -3V.
To permit proper interfacing with these peripherals, the PDP-8/I contains I/O level converters
which produce appropriate changes in the levels
of both Input and output signals. The output circuits, in addition, provide the necessary line-

memory location.

This address is decoded
through the selection switches and the diode

matrix to enable passage of read/write currents

through specific X and Y drive lines of the mem-

The coincidence of these currents select
the specific 12-blt core-memory location desired.
ory.

drive capability to operate over interconnecting

cables of reasonable lengths.

Refer to the Logic
Level and Level Converter discussions In Chap-

4.5.4

Inhibit Drivers

ter 2, Section 2.8.3.

The PDP-8/I memory Is so configured that, unless

MEMORY

4.5

prohibited, all bit locations of the addressed

memory cell would be switched to a logical
during the write portion of the memory cycle.
1

The standard memory supplied with the PDP-S/l
Is a random access, coincident current, magnetic

levels stored In the MB will be
The core planes and diode matrices retained In the corresponding bit locations of the

core memory with a storage capacity of 4096
12-bIt words.

Inhibit drivers, therefore, are used to ensure

that the logic

that make up the core array are mounted on print-

addressed memory cell.

ed circuit cards. These cards plug directly into
the PDP-8/I logic rack receptacles. The Extended Memory Control (MC8I) allows an addi-

4.5.5 Sense Amplifiers

tional 4K of memory with control for 32K of

memory to be installed directly into the logic
rack as an option. The additional memory fields
above 8K are external as the MM8I option. The
major functional elements of the core memory are

During the read portion of the memory cycle,
sense amplifiers detect analog signals induced In
the sense windings of the core array.

These signals are amplified and used in conjunction with

STROBE to set corresponding bits of the SENSE

described In the following paragraphs.

4.5.

Core Ar ra z.

The ferrite-core array consists of 12 64 x 64 core

SECTION

planes.

GENERAL THEORY

This provides a total of 4096 12-bit

words of data and program storage. A thirteenth
core plane is optionally available to permit a
parity bit for each word In memory.

4.5.2 Memory Control

The following paragraphs discuss the major
functional elements of the PDP-8/I in terms of
their operational dynamics. These dynamics
will be discussed in greater detail In Sections III
and IV.

Memory control circuits determine the sequence
of operations of the complete read/write memory
cycle, starting and stopping each function as re-

4.6 TIME STATES/TIME PULSES

quired.

4.5.3 Address Selection
The Memory Address register (MA) contains the
12-bIf address of the currently selected core-

4-4

Each computer cycle consists of four basic time
divisions, Tl, T2, T3, and T4, as denoted on
the system flow diagrams. Each time division
consists of a time state (TS) and Its associated
time pulse (TP). The time states each extend

throughoutthelr particular time division (TSl,
TS2, TS3, TS4) and end with a time pulse (TPI,
TP2, TP3, TP4).

This permits incoming data to be strobed into any

desired major register, or the contents of any register to be complemented, incremented, or transferred intoany other major register. The comple-

In general, the time states generate enabling

Time

levels associated with register outputs .

pulses are used to strobe data into registers.

4.7

MAJOR STATES

menting function is implemented by transferring
the output of the desired reg ister through the
gating network and back into the same register
The incrementing function is performed by transferring the 1 output of the register through the
gating network whi e inserting a carry into the
low-order bit of the word. The data is then transI

The PDP-8/I contai nssix major-state f ip-f lops
These are: Fetch, Defer, Execute, Word Count,
Current Address, and Break The outputs of these
flip-flops generate enabling levels used within
the control elements of the processor to impleI

ferred back into the desired register.

4.9 INSTRUCTIONS

ment particular machine functions.

Instruction words are of two types

The first three major states (Fetch, Defer, and
Execute) are sufficient to perform most machine

ence and augmented

memory refer-

Memory reference instruc-

tionsstore or retrieve data from core memory,

while augmented instructions do not. All instructhrough 2 to specify the operationsutilizebits
Operation codes of Og through 5q
tion code
specify memory reference instructions, and codes

functions in the areas of logical operations,

arithmetic functions, memory read/write operations, and data transfers through the processor

I/O bus. The last three major states (Word

of 6gand 7g specify augmented instructions.

Count, Current Address, and Break) are used
only for high-speed data transfers through the

Memory reference instruction execution times
are multiples of the 1 .5 ps memory cycle. Indirect addressing increases the execution time of a

Data-Break facility.

memory reference instruction by 1 .5 jos. The
augmented instructions, input-output transfer,

The processor determines, near the end of each
computer cycle, which major state will be needed for the activities to be performed in the next
computer cycle. At the very end of the cycle
(TP4)the new major-state will be entered by the

and operate, are performed In 4.25 and 1 .5 |js
respectively. (All computer times are ±20%.)

setting of that particular flip-flop.

4.9.1

Memory Reference Instructions

Since the PDP-S/l system contains a 4096-word
core memory, 12 bits are required to address all
locations. To simplify addressing, the core memory Is divided Into blocks, or pages, of 128 words

4.8 INTERNAL DATA FLOW
The simplified system block diagram shown in
Figure 4-1 depicts the flowof data through the
major elements of the PDP-B/l. Note that all
data transfers into the four major reg isters (AC,
PC, MB, and MA) occur through a register gatThe
ing network and a common register bus

(200o addresses) . Pages are numbered O3 through
core memory
37c,; each field of 4096-words of
uses 32 pages.

The seven address bits (bits 5

through 1 1 )of a memory reference Instruction can
address any location in the page on which the

outputs of these four registers, plus the SENSE
and SR, and the data input from the interface
are all connected to the input gates of the

current Instruction Is located by placing a 1 in
n bit 4
By placing a
bit 4 of the Instruction

major-register gating network.

of the Instruction, any location InpageOcanbe

4-5

Two's Comp lement Add (TAD Y)

addressed directly from any page of core memory.
Al other core memory locations can be addressed
I

indirectly by placinga 1 inbitSandplacinga

Octal Code:

7-bit effective address in bits 5 through 11 of the

Indicators:

instruction to specify the location in the current

Execution Time: 3. 0|.is with direct addressing,
4.5 |js with indirect addressing.

page or page Owhich contains the full 12-bit
absolute address of the operand.

TAD, FETCH, EXECUTE

Operation: The content of memory location Y is
added tothecontentof the AC in two's complement arithmetic. The resu It of this addition is
held in the AC, the original contentof the AC is
lost, and the contentof Y is restored. If there is
a carry from ACO, the link is complemented.

Word format of memory reference instructions is
shown in Figure 4.2 and the instructions perform
as follows:

Logical

AND (ANDY)

This feature is useful in multiple precision arith-

metic.
Symbol:

Octal Code:

ACO -

+ YO - 1 1 - > ACO - 11

1 1

AND, FETCH, EXECUTE

Indicators:

Execution Time:

3. 0|js with direct addressing,

4.5 [jswith indirect addressing.
Operation: The AND operation is performed between the content of memory location Y and the
content of the AC. The result is left in the AC,
the origina content of the AC is lost, and the

Increment and Skip if Zero (ISZ Y)

content of Y is restored. Corresponding bits of
the AC and Y are operated upon Independently.
This instruction, often cal led extract or mask,
can be considered as a bit-by-bit multiplication.

Octal Code: 2
Indicators:

ISZ, FETCH,

Execution Time:

EXECUTE

3. 0|js with direct addressing,

4.5 |js with indirect addressing
Operation: The contentof memory location Y is
incremented by one If the resultant content of
Y equa Is zero, the content bf the PC Is incremented by one and the next instruction isskipped.

Example:

Original

Final

ACj

If the resultant content of

Y does not equal zero,

the program proceeds to the next instruction.

The incremented content of Y is restored to memory. The content of the AC is not affected by this

1
1

instruction.

Symbol:
Symbol: AC| A Yj =

> ACj

= >Y

resultant YO -

1 1

= 0, then PC + 1 = >MA

MEMORY

OPERATION
COOES 0-5

Y+

PAGE

ADDRESS

INDIRECT

ADDRESSING
Figure 4-2

Memory Reference Instruction Bit Assignments
4-6

Deposit and Clear AC

(DCA Y)

function as an extension of the operation code

and can be microprogrammed to perform severe
operations within one instruction. Augmented
instruct ions a re one-cycle (Fetch) instructions

Octal Code: 3

DCA, FETCH, EXECUTE

Indicators:

Execution Time: 3. Ojjswithdirect addressing,

4.5 |js with indirect addressing.
Operation: The content of the AC is deposited In
core memory at address Y and the AC is cleared
The previous content of memory locdtion Y is lost
Symbol: AC = >Y
= > AC
then

Jump to Subroutine (JMS Y)
Octal Code: 4

JMS, FETCH, EXECUTE

Indicators:

Execution Time: 3. Ojjswithdirect addressing,
4.5 |js with indirect addressing.
Operation: The content of the PC is deposited
in core memory location Y and the next instruction is taken from core memory location Y + 1
The content of the AC is not affected by this

that initiate various operations as a function of
bit microprogramming

4.9.2.1

Microinstructions of the input-output transfer
(lOT) initiate operation of peripheral equipment

and effect information transfers between the
processorandan l/Odevice. Specifically, upon
recognition of the operation code 6 as an lOT
instruction, the computerentersa 4.25 ps expanded computer FETCH cycle by setting the
PAUSE flip-flop and enabling the lOP generator
to produce lOP 1, lOP 2 and lOP 4 pulses as a
function of the three leastsignificantbitsof the
instruction (bits 9 through 11). These pulses

occur at 1 jjs Intervals designated as event
times 3, 2 and 1 as follows.

instruction.

Symbol:

Input/Output Transfer Instruction -

PC = >Y

MA+1=>PC

Instruction

lOP

lOT

Event

Bit

Pulse

Time

lOP 1

lOT

IOP2
IOP4

IOT2
IOT4

Jump to Y (JMP Y)

Octal Code: 5

JMP, FETCH

Indicators:

The lOP pulses are gated in the device selector
of the program-selected equipment to produce

Execution Time: 1 .5 ps with direct addressing,
3.0 |js with indirect addressing
Operation Address Y is set into the PC so that
the next instruction is taken from core memory
.

address Y. The original content of the PC is lost.
The content of the AC is not affected by this

lOT pulses that enact a data transferor initiate
a control operation. Selection of an equipment
isaccomplishedby bits 3 through 8 of an lOT
Instruction. These bits form a 6-bit code that

instruction.

enablesthe device selector In a given device.

Symbol:

Y = >PC
The format of the lOT instruction is shown in
Figure 4-3.

4.9.2 Augmented Instructions
There are two augmented instructions which do
They are the Inputnot reference core memory
output transfer, which has an operation code of
6, and the operate which has an operation code

4.9.2.2 Operate Instruction - With operate
Instructions, the programmer can consider logica sequences occurring during one computer

of 7. Bits 3 through 1 1 within these instructions

logical

FETCH cycle. These sequences provide a

4-7

method of forming microinstructions.

Symbol: ACj = >ACi + 1
AC11 = >L

by one in two's complement arithmetic.
Symbol: AC + 1 = >AC

>ACO

L =

Rotate Accumulator Left (RAL)

Rotate Two Right (RTR)

Octal Code: 7004
Sequence: 4

Octal Code: 7012
Sequence: 4

Indicators:

OPR, FETCH

Indicators:

Execution Time: 1 .5 ps
Operation: The content of the AC is rotated two
binary positions to the right with the content of
the link. This instruction is logically equal to

Execution Time: 1 ,5 fjs
Operation: The content of the AC is rotated one
binary position to the left with the content of the
link.

The content of bits AC! - 11 areshifted to

two successive RAR operations
Symbol: ACj = >ACi + 2

the next greater significant bit, the content of
ACO is shifted into the L, and the content of the

AC 11
ACj =>ACj ACO = > L

L is shifted into

Symbol:

OPR, FETCH

AC10=L
ACll =ACO

>AC1

L =

L = >AC11

Rotate Two Left (RTL)

Complement Link (CML)

Octal Code: 7006
Sequence:

Octal Code: 7020
Sequence: 2

Indicators:

OPR, FETCH

Indicators:

OPR, FETCH

Execution Time: 1 .5 jos
Operation: The content of the AC is rotated two
binary positions to the left with the content of
the link. This instruction is logically equal to

Execution Time: 1 .5 ^s
Operation: The content of the L is complemented.

two successive RAL operations.
Symbol: ACj = >ACj - 2

Complement Accumulator (CMA)

Symbol:

L = > L

ACl =>L
AC0 = >AC11

Octal Code: 7040
Sequence: 2

L=>AC10

Indicators:

OPR, FETCH

Execution Time: 1 .5 ps
Operation: The content of the AC is set to the
one's complement of the current content of the

Rotate Accumulator Right (RAR)

AC. The content of each bit of the AC iscomplemente d ind ividually.
Symbol: ACj = >ACj

Octal Code: 7010
Sequence: 4
Indicators:

OPR, FETCH

Complement and Increment Accumulator (CIA)

Execution Time: 1 .5|as
Operation: The contentof the AC is rotated one
binary position to the right with the content of
the link. Thecontentof bits ACO - lOareshift-

Octal Code: 7041
Sequence: 2, 3

ed to the next less significant bit, the content of
AC 11 is shifted into the L, and the contentof the

Execution Time: 1 .5 ps
Operations: The content of the

L is shifted into ACO.

converted

4-9

Indicators:

OPR, FETCH

AC is

froma binary value to its equivalenf two's complement number. This conversion is accomp ished
by combining the CMA and lAC commands, thus
the content of the AC is complemented during
sequence 2 and is incremented by one during
sequence 3.
Symbol: A^j = > AC|,
then AC + 1 = > AC

Indicators:

OPR, FETCH

Execution Time: 1 .5 |js
Operation: Each bit of the AC is set to contain
a binary 1 . This operation is logically equal to

combining the CLA and CMA commands.
Symbol: 1 = > ACj

Clear Link (CLL)

Group 2 Microinstruction

Octal Code: 7100
Sequence: 1

The Group 2 operate microinstruction format is
shown in Figure 4-5 and the primary microinstructions are explained in the following paragraphs. Any logical combination of bits within
this group can be composed into one microin-

Indicators:

OPR, FETCH

Execution Time:

.5 ps

Operation: The content of the L is cleared to
contain a 0.
Symbol:
= > L

struction.

If skipsare combined in

a single instruction, the

Inclusive OR of the condition determines the

Set Link (STL)

AND

skip when bit 8

is a 0; and the
of the inverse of the conditions determi nes the skip when

Octal Code: 7120
Sequence: 1 , 2
Indicators:

bits isa 1 . For example, if ones are designated

OPR, FETCH

in bits 6 and 7 (SZA and SNL), the next instruction is skipped if either the contents of the AC=0,

Execution Time: 1 .5 |js
Operation: The L is set to contain a binary 1

or the content of L = 1,

This instruction is logically equal to combining

bits 5, 7, and 8, the next instruction

the CLL and CML commands

if the AC contains a positive number and the L
contains a 0.

Symbol:

= > L.

If ones are

contained in
is skipped

Clear Accumulator (CLA)
Halt (HLT)

Octal Code: 7200
Sequence: 1
Indicators:

Octal Code: 7402
Sequence: 3

OPR, FETCH

Execution Time: 1 .5 |js
Operation: The content of each bit of the AC is
cleared to contain a binary 0.
Symbol:
= > AC
Set Accumulators (ST A)

Indicators:

OPR, not RUN

Execution Time: 1 ,5 |as
Operation: Clears the RUN flip-flop at Se-

quences, so that the program stops at the conclusionofthecurrentmachine cycle. This command can be combined with others in the OPR 2
group that are executed during either sequence 1,

Octal Code: 7240
Sequence: 1 , 2

2, and so are performed before the program stops

Symbol:

4-10

= > RUN

REVERSE
SKIP

SENSING OF

OPERATION
CODE 7

SZA
A

CLA

E IT S

—SNL

SMA

CONTAINS A
TO SPECIFY
GROUP 2

OSR

GROUP 2

Figure 4-5

__y

CONTAINS A
TO SPECIFY

HUT

5,6 7

Group 2 Operate Instruction Bit Assignments

OR with Switch Register (OSR)

if it

contains a

the content of the PC is incre-

mented by one so that the next sequential instrucOctal Code: 7404
Sequence: 3
Indicators:

tion

If the L

skipped.

contains a 0, no operation

occurs and the next sequential instruction is ini-

OPR, FETCH

tiated.

Symbol:

Execution Time: 1 .5 [js
Operation: The inclusive OR operation is performed between the content of the AC and the
content of the SR. The result is left in the AC,
the original content of the AC is lost, and the

If L =

then PC +

= > MA

Skip on Zero Link (SZL)

Octal Code: 7430
Sequence: 1
command.
this
by
content of SR is unaffected
When combined with the CLA command, the OSR Indicators: OPR, FETCH
Execution Time: 1 .5 ps
performs a transfer of the content of the SR into
The content of the L is sampled, and
Operation:
the AC.
the content of the PC is increif it contains a
Symbol: ACj V SRj = > AC]

mented by one so that the next sequential instruction

Skip, unconditional (SKP)

skipped.

If the L

contains a

1 ,

no operation

occurs and the next sequential instruction is initiated.

Octal Code: 7410
Sequence: 1
Indicators:

Symbol:

skipped.

Skip on

PC + 1 = > MA

= > MA

Skip on Zero Accumulator (SZA)

Octal Code: 7440
Sequence: 1
Indicators:

OPR, FETCH

Execution Time: 1 .5 |js
Operation: The content of each bit of the AC is
the content
sampled, and if any bit contains a
of the PC is incremented by one so that the next

Non-Zero Link (SNL)

Octal Code: 7420
Sequence: 1
Indicators:

0, then PC +

OPR, FETCH

Execution Time: 1 .5 |js
Operation: The content of the PC is incremented
by one so that the next sequential instruction is

Symbol:

If L =

sequential instruction is skipped. If all bits of
the AC contain a 0, no operation occurs and the

OPR, FETCH

Execution Time: 1 .5 |js
Operation: The content of the L is sampled, and

next sequential instruction is initiated.
Symbol: If ACQ -11=0, then PC + 1 = >

4-n

Skip on

Clear Accumulator (CLA)

Non-Zero Accumulator (SNA)

Octal Code: 7600
Sequence: 2

Octal Code: 7450
Sequence: 1
Indicators:

OPR, FETCH

Indicators:

Execution Time: 1 .5 ps
Operation: The content of each bit of the AC is
sampled, and if any bit contains a
the content
of the PC is incremented by one so that the next
sequential instruction is skipped. If all bits of
the AC contain a 0, no operation occurs and the
next sequential instruction is initiated.
Symbol: If ACO - 11 7^ 0, then PC + 1 = >
1

AC is sampled, and if it contains a 1
Indicating the AC contains a negative two's com-

bit of the

plement number, the content of the PC is incremented by one so that the next sequential Intive

4.10

PROGRAM INTERRUPT

that it would consume a prohibitive amount of

OPR, FETCH

Execution Time: 1 .5 ps
Operation: The content of the most significant

.5 ps

transfer or perform a specified operation. Others
are so slow in operation, relative to the computer,

Octal Code: 7500
Sequence: 1

struction

Operation: Each bit of the AC is cleared to contain a binary 0.
Symbol:
= > AC

Some of the I/O devices used with the PDP-8/I
require several instructions to complete a data

Skip on Minus Accumulator (SMA)

Indicators:

OPR, FETCH

Execution Time:

skipped.

the AC contains a posi-

number no operation occurs and program

control advances to the next sequential instruc-

time to have the computer wait In a skip loop for
their operation to be completed.

These devices,
therefore, employ the program interrupt facility.

When the program enables the program interrupt
facility, the computer senses interrupt requests

The interrupt may also
be initiated In response to a programmed lOT Infrom peripheral devices.

struction.

tion.

Symbol:

ACO =

then PC + 1 = >

An interrupt is allowed to occur only on comple-

tion of the instruction currently in process and

takes effect at the beginning of the following

Skip on Positive Accumulator (SPA )

fetch cycle.

Octal Code: 7510
Sequence: 1

A program interrupt is similar, in effect, to a
JMS to memory address 0000. The content of PC

Indicators:

OPR, FETCH

saved in location 0000 and the next instruction
Is taken from location 0001 3.
The instruction
is

Execution Time: 1 .5 |js
Operation: The content of the most significant
bit of the

stored at this location is usually a JMP to a per-

AC Is sampled, and if it contains a 0,

ipheral-servicing subroutine.

indicating a positive (or zero) two's complement

number, the content of the PC is Incremented by
one so that the next sequential Instruction Is

After identifying the interrupting device and servicing It, the program enables the interrupt sys-

AC contains a negative number,

tem and then performs a JMP I 0000 (jump to perform the address specified by the content of lo-

skipped.

If the

no operation occurs and program control ad-

vances to the next sequential instruction.
Symbol: If ACO = 0, then PC + 1 = > MA

cation 0000) to return to the point at which the

program was interrupted.

4-12

4.10.1

necessary control elements for the memory are
contained within the basic PDP-8/I.

Instructions

The two instructions associated with the program
interrupt synchronization element are lOT microinstructions that do not use the lOP generator.
These instructions are as follows.

The memory capacity of the computer can be Increased, In Increments of 4096 words, to a maximum of 32,768 wordswith or without parity. If

Interrupt Turn On (ION)

the parity option is selected, the parity bit is
carried as the thirteenth bit in each word. Any

Increase in the size of the memory from the basic
4K configuration, however, necessitates the ad-

Octal Code: 6001
Event Time: Not applicable
Indicators:

dition of the Type MC8I Memory Extension Con-

lOT, FETCH, ION

trol

1.5 ps

Execution Time:
Operation: This command enables the computer
to respond to a program interrupt request. If the
interrupt is disabled when this instruction is given,

the computer executes the next instruction, then
enables the interrupt. Theadditional instruction
allows exit from the interrupt subroutine before

allowing another interrupt to occur. This instruction has no effect upon the condition of the interrupt circuits if it isgiven when the interrupt

with the first 4K of extended memory.

The first 4K of extended memory is plugged directly into the processor main frame in reserved

connector locations . The ba lance of the extended memory (MM8I options) must be located externa

Figure 4-6 is a block diagram showing the interrelationship of the mapr elements of the PDP8/l memory and its control elements.

4.12

enabled.
Symbol: 1 => INT. ENABLE

to the processor.

MEMORY OPERATION

PDP-8/I memory operation involves five major
functions:

Octal Code: 6002
Event Time: Not applicable
Indicators:

lOT, FETCH

Execution Time:

.5 |js

Operation: This command disables the program
interrupt synchronization element to prevent interruption of the current program.

Symbol:

address selection, read, inhibit, write,

and sense. The memory control provides the
timing and initiation of the read, Inhibit, write
and sense functions. Address selection is performed by the contents of the MA register, applied through the address selection switches and
the X and Y diode selection matrices.

Interrupt Turn Off (lOF)

= > INT. ENABLE, INT. DELAY

SECTION III
DETAILED MEMORY THEORY

4.12.1

Memory Control

The memory control consists of several seriesconnected delay lines with associated logic gates
and control flip-flops (Drawing BS-8I-0-13).
An Initiating signal, MEM START, from the central processor proceeds through the delay lines

The following paragraphs discuss memory theory

alternately setting, and clearing the various control fl ip-flops, and r eturns to the central processor

at a detailed level.

as the

4.11

MEM DONE signal. The timing for this

cycle is fixed by prewired taps on the delay lines.
The control flip-flops enable the read/write and

OVERALL MEMORY THEORY

Inhibit currents In the selected memory field.

The basic PDP-8/I containsasingle4096-word,
12-bit core memory which performs all normal
functions of data storage and retrieval. All

4-13

variable delay is provided for the STRO BE FIELD
signal to the sense amplifiers, and for the STROBE
signal to the central processor.

CURRENT
LIMITING
RESISTOR

(G624)

A38,A39

SENSE AMPLIFIERS
AND MEM REGISTER

TO INSTRUCTION REGISTER

T*- MEM 00
» MEM 02
-» MEM 03

(G020 OR G021)

A3I-A33/B31-B33

MEM SUPPLrt »

TO MAJOR
REGISTER
GATING

NETWORK

MEM SUPPLY

%
MEM ENABLE
MEM BEGIN

INHIB IT

FROM

4096
12-BIT WORD
CORE MEMORY

DRIVERS

MEMORY -i

(G228'S)

BUFFER

A36,B36,B37

FIELD STROBE

FT
OOg

MAOO (0)
MAOO (1)
MA01 ID

778

OOg

(

MEMORY CONTROL

ADDRESS
DECODING
AND
SELECTION
SWITCHES

X-AXIS
DIODE SELECTION
MATRIX
(G610,G61 1)
CD34/CD36

IG221'S)

C37/C38

MA02 (111

MA06I0)

Y-AXIS
DIODE SELECTION
MATRIX
(G610,G611)
CD34/C036

MAOGdl

ADDRESS
DECODING
AND
SELECTION
SWITCHES
(G22rs)
C32/C33

MA07(1)

B21

TO /FROM
C.P TIMING

B22
A21.A22.A23
B23.824
B30

MA08(1)
FIELD CONTROL
(EA0,EA1,EA2)

FIELD »X R/W

M113
M246
M310
M360
M617

SOURCE

Y R/W SOURCE

INHIBIT

ADDRESS DECODING
AND SELECTION

R/W

YR/W

RETURN

SWITCHES
(G22rs) D32/D33

NEG

CLAMP

MA04(1)

POWER CLEAR

SWITCHES
(G2Zrs) D37/D38

rrTTT

MA03(0)

ADDRESS DECODING
AND SELECTION

rrTTT

FIELD

MA09(0I

MAIO(I)

NEG
CLAMP

FIELD

MA03(n

MA0S11)

MA09(n

MAIKII

MEM
MEMORY VOLTAGE
POWER CLEAR
SHUT DOWN

REGULATION AND
DETECTION
•

(6805, G826)

AB1/AB2

STOP OK

SUPPLY+
MEM,

SUPPLY-

CURRENT
LIMITING
RESISTORS

R/W RETURN

RW/SOURCE

SELECTION
SWITCHES

(G624'S)

(6228)

(G228)

B3e/A39/B39

D39

C39
READ (t)

THERMISTOR
(IN MEMORY

STACK)

Figure 4-6

Memory System, Block Diagram

The MEM START signal to the memory control
delay ines is gated by the field selection signa Is
EAO and EAI (for the internal memory fields).

processor control . This permits the processor/

MEM START also sets the MEM ENABLE flip-flop

The waveshapes of the memory control signals are
shown in Figure 4-7. The transition and duration
timesare approximate due to the delays through
pulse amplifiers (about 50 ns), and gates (about
20 ns).

memory cycle to be reinitiated

when the field selection levels specify either
FIELD OorFIELD 1. The buffered MEM ENABLE
output enables the contents of the appropriate

SENSE registertothemajorregisterbus.

MEM

START clocks the FIELD flip-flop which sets when
EA2(l)isactive (select FIELD 1). TheFIELD
flip-flop iscleared for FIELD

(basic memory)

operation.

Each memory control can service two 4K memory stacks. The FIELD flip-flop selects the specific one fora given cycle.

The buffered outputs
of the FIELD flip-flop enable the address selection current drivers, the Inhibit Drivers, and the
variable strobe delay associated with the selected field . After passing through a delay line
MEM START, now a pulse, sets the READflipflop. This flip-flop enables the read/write se-

INHIBIT flip-flop. The buffered INHIBIT output
gatesall the Inhibit drivers associated with the
memory control . Further enabling is effected by
the buffered FIELD flip-flopsandthespecific
MB output for a given bit. The WRITE f ip-flop is
I

set approximate ly 50 ns after the setting of the

INHIBIT flip-flop. Both ofthese control fl ipflops are cleared by the MEM FINISH signal,
which inverts to MEM DONE. Whileset,the

by four windings traversing each core In the memory In a standard 3D selection technique An Xaxis read/write winding passes through al cores
in each of 64 horizonta rows; a Y-axis read/
write winding passes through all cores in each of
64 vertical rows; and a sense and an inhibit winding pass through all coresof eachof 12 (or 13)
.

provides the inputto the variable delay line enabled by the FIELD flip-flop. The occurrence of
both the STROBE FIELD signal to the sense amplifiers and the STROBE signa to the central processor are control led by this selected adjustable
delay.

line chain clears the READ flip-flop, and sets the

The ferrite core memory consists of 1 2 planes (13
if the parity option isselected), each containing
4096 ferrite cores arranged in a 64 x 64-core
array . Each core assumes a stable magnetic
state corresponding either too binary 1 or a

Selection and switching of the cores is provided

the memory stack. Anothertapof the delay line

Further progression of the pulse along the delay

4.12.2 Read^Vrite

binary 0.

lection switches to provide the read currents to

planes . Through the use of selection circuits
control ling the input of the X and Y read/write
windings, any one of the 4096 12-bitword locations can be addressed for writing data Into, or

reading data out of memory

The level of the read, write, and inhibit currents
passing through these windings Is such that no
single winding producesa magnetic field strong
enough to cause a core to change Its magnetic
state. This current level Isknownas the halfselect value. Only the reinforcing magnetic
field caused by the coincident current of both an
X and Y read/write winding can cause the core
located at the point of coincidence to change
state.

It is,this principle that a I

lows the relative-

ly simple winding arrangement to select one and

WRITE flip-flop enables the proper read/write

only one memory word out of a possible 4096 in

switches to provide the write currents to the
memory stack

each array

MEM DONE indicates the end of thememory
cycle by setting the MEM IDLE flip-flop in the

Figure 4-8 shows a slmple4x 4core array. The
winding scheme shown on this array is identical
to that used in the planes of the P DP- 8/1 memory

4-15

MEMORY CYCLE ENDS —H

MEM DONE

r
I

(^— MEMORY CYCLE BEGINS
MEM START

MEM BEGIN

READ

IT
INHIBIT

Figure 4-7

Memory Operations Timing Diagram

READ

INHIBIT

WRITE
WRITE ^
INHIBIT

WINDING

Figure 4-8

Simple Core Memory Plane

4-16

READ

The magnetic field generated by the
inhibit current is of a value and polarity which
effectively cancels the field generated by the

A half-select current passing through the X2

direction.

winding from right to left (write direction) produces a magnetic field that tends to change all
Y-axis half-select write current. This prevents
to the
the cores in that horizontal row from the
the setting to the 1 state of any core through
state. The flux produced by this current is,
1
however, insufficient to complete the state tran- which inhibit current is flowing.
Simultaneously passing a halfsition in any core.
Each of the 12 inhibit windings is connected to
select current through the Y3 winding from top to the output of an Inhibit driver circuit. Each
bottom (write direction) tends to produce the
in turn, is controlled by the output of one
driver,

same effect on all cores in that particular vertical row. Note, however, that both currents pass
through one core, located at the intersection of
the X2 and Y3 windings. This then becomes the
selected core.

bit of the memory buffer register,

which contains

the data to be stored in memory.

When the write

operation commences, each inhibit driver conis activated.
nected to an MB bit containing a
The resulting half-current value output of the
driver then prevents the writing of a logic

The X and Y windings are so configured that,
when half-select value write currents are passed
through each, their resultant magnetic fields add
in the core at their point of intersection.

Their

its

assigned core plane.

The MB bits containing

logic I's disable their respective inhibit drivers.
This allows the cores pertaining to these bits to

have I's written Into them.

The content of the

combined (full-select) current then ensures that

MB is therefore written intact Into the selected

the selected core is left in the

core-memory storage cell.

state.

PDP-8/I core memory, the X2 windings of
12 planes are connected in series, as are the

In the
all

Y3 windings. When X2Y3 half-select write currents flow, therefore, the X2Y3 core on each

To read out information contained in the 12-bit
X2Y3 memory cell, half-select read currents are
passed through both the X2 and Y3 windings.

plane changes to or remains in, the 1 state. This
makes each of these cores equivalent to one bit

Since read current flows In the opposite direction
of write current, all cores in the X2Y3 cell previously set to the 1 state are switched to the

of a 12-bit storage cell.

state.

should be noted that passing a half-select value write current through a particular pair of X
and Y windings produces the 1 state in all 12-bit

A sense amplifier circuit is provided for each of

Cores already in the
unaffected.

state are, of course,

positions of the selected core-memory storage

To store usable information, however, it is
state during this
also necessary to produce the
write cycle in any or all bit location of the selected storage cell. This is performed by the inhibit windings, and the prior occurrence of a
cell.

read cycle which puts all the cores in the

state.

the 12 core planes In the memory. The input to
each amplifier is a sense winding which passes
through every core on the associated plane. If,

during the read operation, the addressed core in
state transition, the flux
a plane makes the 1 to
change Induces a current in the sense winding of

amplified, shaped, and after threshold detection, is used to set a SENSE flip-flop
connected to the output of the sense amplifier
This input

Each inhibit winding, shown as a broken line on
Figure 4-8, passes through all cores on a particular plane. Unlike the X and Y windings, in
which the read and write currents flow In opposite directions, the half-select value current in
the inhibit windings always flows In the same

This current develops a 40-50
voltage pulse at the input to the sense amplifier.
that plane.

when STROBE is generated.
Addressed cores which were already In the

state,

when saturated by the full-select read flux, will

4-17

induce a limited amount of noise into their sense

transferred to the MB for restoration to its origi-

winding. The voltage level produced by this
noise (intheorder ofSmV) will be insufficient

nal location during the write portion of the

memory eye le

to activate the sense amplifier associated with

that plane. The SENSEflip-flopforthatbitwill

therefore remain clear, indicating a logic
that location.

4.12.3 Address Selection

The memory selector switches decode the address
MA and se lect the proper source
and return lines for both the X- and Y-axes.
These selection circuits are shown on engineering drawings BS-8I -0-1 5 (X-axis selection) and
specifi ed by the

Since this type of readout destroys the content
of the addressed eel

(by switchingallcoresto

O's) , the data stored in the SENSE register wi

TO AXES Y 10-Y70

TO AXES

MEMORY SUPPLY

(

MEMORY SUPPLY (-)

Figure 4-9

Memory Address Selector and

Read/Write Current' Control

4-18

diodes within the matrix and on theiraddress selection switch (BS-8I-0-16).

BS-8I-0-1 6 (Y-axis selection) in Chapter 8 of
this document. The polarity of the magnetic
fieldapplied to the cores ofthe addressed eel is
determi ned by the di recti on of c urrent f low

In a write operation , Q4and

Q5 would be turned

on by gates 4and 5, reversing the direction of
current flow. Theaddress selection path now
becomes D4, Q2, D5, the cores ofthe YOOaxis,
D6,Qland D2. This new current direction attempts to set the cores to the 1 state . As has
been previously stated , each core through which
write current passes wi II be set to the 1 state unless the inhibit driver associated with that core
has been activated by the sensing of a logic

through the core read/write windings. It differs
between the read and write cycles. The read/
write current selection circuitsare shown on

engineering drawing BS-8I-0-13 (Memory
Control) in Chapter 7 of this document.
Figure 4-9 provides a combined and simplified
version of these two drawings showing the selection of a Y-axis memory cell,andthe method of

in that particularbit position of the MB.

determination of read/write current direction.
The drawing assumes a content of in bits 6
through 1 1 of the MA, addressing axis 00 on

DETAILED PROCESSOR

BS-8I-0-16.

THEORY

SECTION

The functiona operation ofthe PDP-8/l Processor is summari zed on the flow diagram FD-8I -0-1.
The information on the flow diagram is not deI

NOTE

tai led enough , however, to faci litate trouble

The component designation numbers
used In Figure 4-9 have beenarbitraand
i ly assigned to assist this discussion

isolation to the level of a module. The object

of this section, therefore, is to educate the
service technicianand to provide him with a
means of transition from the flow diagram to the

do not re late to actual designations.

block schematic.

With a read operation in process, the READ (1)
line will be affirmed enabling gates 3and6o
The outputs of these gates turn on both Q3 and
Q6. This establishesa positive source and neg-

4,13

FLOW DIAGRAM INTERPRETATION

Y-axis cores
serviced by address-selection gates! and 2.

The flow diagram 81 -0-1 , lustrates the sequence
of events that occur during the manua , storedprogram, and automatic operations ofthe PDP-

This Isthe proper polarity and current direction

8/1

ative return for the windi ngs of a

for a

read operation .

Sheet 1 ofthe f low diagram, which describesa
stored-programandautomatic functions, contains
six vertical columns, each of which isassociated
with a particular major state of the computer.
The first three columns. Fetch, Defer, and Execute, correspond to the three major states in
programmed operation requiring access to the
1

With MA06- 11=0 gates 1 and2 have been en
abled, and both Ql and Q2 will conduct. Current then flows through Dl and Ql to D8. The
read current then passes through D8 and the
winding ofcoreson the Y-axis of OOattempting
to switch the cores to the

state .

There are

12x64cores along this Y-axis; one for each bit
and each X-axis. It then passes through D7,Q2,
and returns to the Memory Supply (-) through Q6

memory or execution of certain logic functions.

The current does not pass through the cores on the
01-07, and 10-77Y-axis because of back biased

operations during the transfer of information to
or from a mass-memory device (data break).

The lastthreecolumns,titledWord Count, Current Address , and Break , correspond to automatic

4-19

Sheet 2 defines the events that occur during man-

ditional.

ual operation of the computer . It contains three

mation-transfer statements with no indication of

verticalcoJumns,each of which contains a
single key, or group of i<ey operations and their

Unconditional events appear as Infor-

For example, LA, ST, EX, and
DP key operations begin with the event 0-^MAJOR STATES , which occurs In tl me state MFTSO,
and during a load -address operation, SR transfers
to the PC In MFTS2 (SR-PC).

resultant functions.

Horizontal rows on the flow diagram represent
time states, with time progressing from top to

bottom. The upper row represents time one (Tl)

Conditional eventsappear as information-tran-

during programmed and automatic operation

sfer statements, accompanied by one or more In-

and, on Sheet 2, Manual Function Time State

dications of the contents of a register which are a
condition to the occurrence of the event. For

(MFTSO) during manual operation.

example, during an OPRI instruction, several
Eventsappear on the diagramas rectangular
boxes joined by vertica flow lines . Operations
n a sequence not speci fica ly designated by a
key name or instruction mnemonic are assumed

conditional events may occur. These appear in
the Fetch cycle In the leftmost sequence occur-

to be comm on to all sequ ences (e .g . , STROBE

contains a 0. When following thesequence of
events many given instruction, conditional

The first event, AC -AC, occurs
onlyif MB bit 04contalnsa Oand MBbIt 06
ring during T3,

in Tl , and

MEM DONE, in T4)

events for which the required conditionsare not

Branching of a common sequence into several

met should be Ignored.

operation chains , each associated with a speci fie instruction or key operation, appears as a
vertical line terminated by an arrowhead on a

To determine the method by which the processor
executes an event specified in the flow diagram,

MEM

horizontal line. Thus, in the Fetch cycle,
-*IR (contents of the currently addressed memory
location - bits 0-2- transferred to bits 0-2of the

When tracing a transfer operation, first examine

refer to the appropriate engineering logic dia-

gram and the corresponding mechanization chart.

Instruction Register) is common to a II operations,

the control gating of the register to which the

after which a branch occurs.

transfer is being made. Thus, to trace the operation PC -* MA, examine the Major Register

In this branch, the decoded output of the I R de-

(Drawing BS -81 -0-8). Notethatan MA LOAD
pulse Is required to transfer data from the register
bus into the MA. An examination of the Register
Input Control and Skip (Drawing BS-8I-0-9)
shows the gating levels required to complete the

termines which of the eight basic Instructions Is
In process, permitting selection of the proper

branch for the next operation.

The convergence of severe sequences into a
further common sequence appears as a number

transfer of the data through the gating network
and onto the register bus. Twolevelsare required . These are
SHIFT and PC ENABLE.

of vertica

lines with arrowheads that meet a

common horizontal line. A single vertica

line,

descending from the horizontal line to a rectangle, specifies the next common event.

The method of generation of the PC ENABLE level
Is shown on the Register Output Gate Control
(Drawing BS-8I-0-4) . The PC ENABLE level

Thus, the

common sequenceassoclated with manual examine and deposit operations concludes with the

activates the Input gates of the major -register

branchedsequenceMEM— MB (examine) and
SR- MB (deposit).

gating networkassoclated with the logic 1 output

Note that some events specified In the recta ng les

of the PC. Theappearance of this signal Initiates
a data transfer from the PC onto the major-register

of the flowchart are conditional, others uncon-

gating network bus. The data then passes through

4-20

fhe adder circuit to be transferred to the desired
register (in this case the MA).

The method of generation of the NO SHIFT level
is shown on the Shift and Carry Gate Control
SHIFT levels en(Drawing BS-8I-0-5). The
circuit is transadder
of
the
output
that
the
sure

manual time levels and pulses from occurring if a
key is pressed when the computer is running.
MFTSO is inverted to produce MFTSO which sets
the MFTSl flip-flop. MFTSO also combines with
KEY EX + DEP to enable clearing of the RUN
flip-flop during T3 of the processor cycle.

Timing level MFTSO generates an MFTPO pulse.
That is, the output of PCOO will be This pulse is delayed 2 |js to produce MFTPl . The

ferred directly into its corresponding output gating network.

transferred into MAOO.

The

NO SHIFT level

generated during each data transfer when left or
right data shifting or rotation is not desired.

MFTPl pulse sets the MFTS2 flip-flop which clears
the MFTSl flip-flop ending that time state. MFTPl
fs

delayed 2 ps to generate MFTP2 which clears

the MFTS2 flip-flop.

cleared, the MFTS2 (0) level generates the MFTS3
gate.
timing level through a

NAND

4.14 TIMING

The applications of the manual function timing
levels and pulses are shown on the MAN FUNCTIONS flow diagram (Drawing FD-8I-0-1) and
described with the key function.

The following paragraphs discuss the internal
timing of the processor.

4.14.1

When this flip-flop is

Manual Function Timing Generator

4.14.2 Manual Operations

When the computer is initially started, or when
data is manually deposited, examined, or con-

The following keys and switches are provided on
the operators console: START, STOP, LOADADD,
CONT, EXAM, DEP, SING STEP, SING INST,

tinued, or the memoryaddressed, the processor
and/or memory eye les are entered by application of the Manual Function Time signals. These

and the switch register (SR).

AM are single keys

signals include the time-state levels MFTSO,

with the exception of the SR which consists of a

MFTSl , MFTS2, and MFTS3, and timing pulses
MFTPO, MFTPl, and MFTP2 (Drawing BS-8I-0-2).

bank of 12 switches.

The levels and pulsesare independent from, and
not to be confused with, the process or time
generator signa Is The generator and the manua

These switches, used singly or in combination,
permit manual intervention to start the program,
stop the program, load data into a selected memory location, and run the program step-by-step,

timing signa Is are described in the following

or instruction-by-instruction for troubleshooting

paragraphs. Figure 4-10 shows the timing relationship between the manua timing signals.

the system, or debugging new programs.

When any of the levels K EY LA, KEY ST,
EX +DEPor KEY CONTare activated by pressing

The MAN FUNCTIONS flowchart (Drawing FD81-0-1 ; sheet 2) describes the operation of each
of the five active manua control keys (Start
Load Add, Exam, Dep, Cont).
I

oneof the associated keys, a low-to-high level
transition occurs . The transition is smoothed by

Load Add -The memory location to be addressed
and Load Add
(Drawing
diagram
keyed. As shown in the flow
FD-8I -0-1), this clears the major state register.
AAANUALPRESEt, which performs this operation

anintegrating filter which eliminates the noise
generated by the closure of the switch (key). To
perform this function, a 100ms delay isincorpo-

is toggled intotheswitch register,

rated as part of the fi Iter . The f i ter output acti votes the ST (Schmitt Tri gger) wh ich combines
I

with RUN(0) togenerateMFTSO. The RUN (0)
level controls the timing generator by preventing

isgeneratedbythe MFTPO pulse when LoadAdd
is

4-21

pressed.

No further operations occur unti MFTS2 when

the MB LOAD pulse (Drawing BS-8I-0-6), per-

theaddresstoggled into the switches is loaded
into the PC. This occurs through the generation
ofanSR ENABLE signal (Drawing BS-8I-0-4)and
a PC LOAD signal at MFTP2 (Drawing BS-8I-0-6).

mits MB to accept the SR data present on the

major register bus. During the write portion of

thememorycycle, this data is written into the
memory location specified by the contents of

MA. This completes the deposit cycle.
Deposit (DEP) - If data is to be manually loaded
into memory, thestarting location is placed in

the PC, as described with LoadAdd, and the data
is loaded word-by-word through the SR (Switch
Register) by the action of Dep.

Subsequent data is loaded in sequential memory
locations by toggling the data into the SR and
actuating Dep. The PC is incremented for each
deposit, making further addressing unnecessary
unti such time as access to a non -sequential
I

As shown in the flow diagram (Drawing FD-8I-01), pressing KEY DEP clears the major state registers during MFTO by generating the MANUAL

memory address is required.

contents (starting address) of the PC are transferred to the MA. Thegeneration of the PC EN-

Examine (Exam) -Theactuation of Exam permits
examination of the wordin thecurrentlyaddressed memory location As shown on the flow diagram (Drawing FD-8I-0-1), this sequence is

ABLE signal (Drawing BS-8l-0-4)by MFTSl

identical to the previously discussed deposit

KEY ST-+£X+DEP, and the MA LOAD signal
(Drawing BS-8I-0-6) byMFTPl •KEYST+EX+

operation up to the start of the memory eye le

DEP perform this transfer operation.

Duri ng the Read portion of the memory eye le , the

PRBET level with MFTPO. During MFT

the

contents ofthe address specified, when the Load

During MFT2, theaddress in MA is incremented
and transferred back to PC, leaving the current
address in MA and placing the next consecutive
memory address in PC. This transfer is accomplished by an MA ENABLE level (at MFTS2),
and a PC LOAD pulse (at MFTP2) . The address
is incremented bythe insertion of a CARRY into
the adder of the least-significantbitduring the
transferof theaddress into PC. This occurs; by

Add key was pressed, are transferred from core
me mory to th e SENSE register T he memor y signal STROBEa lows this transfer. STROBE also

generating a CARRY INSERT level (Drawing
BS-8I-0-5) during MFTS2.

permits the operator to exami ne the contents of

ends processor time-stateTSl ,andinitiatesTS2.
At the end of T2, time-pulse TP2 generates an
MB LOAD pulse which completes the examine
operation by transferring the contents of the
SENSE register to the MB. Upon completion of
this transfer cycle, the processor stops .

This

the locationaddressed by observing the MB indicator lights located on the console panel

During this transfer operation the memory cycle
is

During theWriteportionof thememorycycle,

started to permit loading of theSRdata into

the currently addressed memory location .

the contents ofthe MB containing the read word

The

actuation of any manual key, except LOAD
START pulse at MFTP2
ADD, generates a

are restored to the original memory location.
Thus, the contents of the examined address remain

(Drawing BS-8I-0-2), initiating the memory
cycle.

intheMBandin the memory location The contents of theaddress examined maybe modified
through the use of the Switch Register and Key

During MFTP3, the actuation of Dep generates
SR ENABLE (Drawing BS-8I-0-4) . Thisgates

be noted, however, that as part
ofthe cycle which extracted the data from memory, the PC was incremented by one to set up the
address ofthe nextinstruction . The next word.

MEM

Dep.

the data, as signified by the switch positions, onto the major register bus.

At TP2 ofeachcycle.

4-23

It should

therefore, would be loaded into the core-memory

Step key inhibits the RUN flip-flop from being

address next in 'sequence to the address of the

set.

presentlydisplayedword. The 12-bit SRand Key
Load Add must therefore be used to set the PC
back to the address of the displayed word prior to
insertion of the new word.

erates a single

Subsequent actuation of the Cont key gen-

MEM START pulse, but prevents

the processor from automatic execution of the

Eachactuationof the Cont key therefore permits a single processor and memory cycle
to be executed.
program.

Start - Pressing key Start initiates execution of

Placing the Sing Inst key in the up position per-

a program previously loaded into core memory.

mits setting of the RUN flip-flop but stops the

When this key is pressed, MFTPO is combined
with the KEY ST evel to generate the INITIALIZE

processor, by clearing the RUN flip-flop upon

and INITIALIZE signals (Drawing BS-8I-0-2)
which clears se veral circuits. The MFTPO pulse
also generates

generation of an F SET level , indicating that the
next machine cycle is to be Fetch.

Under Sing
Inst an instruction consisting of more than one
processor and memory eye les is completed before

MANUAL PRESET.

a halt.

During MFTl

the contents of the PC transfer

4.14.3 Time States

through the major reg ister gating network to the
MA, and INITIALIZE clears the lOP flip-flops.

During MFT2, the AC, Link, and INT ENABLE
(Drawing BS-8I-0-7) flip-flops are cleared, and
the FETCH flip-flop is set. The memory cycle is
also Initiated at this time by the generation of
MEM START (Drawing BS-8I-0-2).

The memory signal STROBE is activated during
the memory cycle. STROBE continues the automatic sequences of the processor by clearing
TS1 and loading TS2 to one. The RUN flip-flop
is set by processor time-pulse TP3, and the program instructions are executed until either a
halt command is encountered, or the computer
is manually stopped.

Four time-state levels (TSl , TS2, TS3, and TS4)
and associated time pulses (TPl , TP2, TP3, and
TP4)are generated during each computer cycle.
This trainof levels and pulses is initiated at the
start of each memory cycle and terminated upon
its completion. The generation of the time state
and time pulses and their relationships are discussed below and are shown in Figure 4-11.
TSl, the first time-state produced (Drawing BS81-0-2), is entered at the end of the previous processor cycle by TP4.

The memory cycle is also

initiated at this time by generating

(Drawing BS-8I-0-2).

MEM START

The duration of TSl and

generatio n of time pulse TPl depends on the memory signal STROBE which is produced during the

READ portion of the memory cycle.

Therefore,

Stop - Pressing key Stop can halt a program at

the dura tion of T Sl depends on the memory used,

the end of an instruction.

and the STROBE delay adjustment.

generates a

Operation of this key

KEY + SI STOP level which clears

the RUNflip-flopduringTPS. Clearing the RUN

During processor time TSl ,

MEM START initiates

MEM

the memory cycle by progressing through a delay

START pulse preventing another memory cycle.

chain (Drawing BS-8I-0-13). MEM START is delayed to generate MEM BEGIN which starts the
read function by setting the READ flip-flop. The
memory signal STROBE (Drawing BS-8I-0-13) is
generated by an adjustable delay toward the end
of the read portion of the memory cycle by MEM

flip-flop Inhibits generation of the next

Sing Step and Sing Inst Keys - Pressing the Sing
Step (single step) or Sing Inst (single instruction)

keys steps the program one cycle or one instruction respectively at a time.

Operating the Sing

4-24

MEM DONE

MEMORY CYCLE ENDS—•<

r
I

L_J

MEMORY CYCLE BEGINS

MEM START
)

MEM BEGIN

1
1

STROBE

WRITE

J
i
TPl

DETERMINED BY STROBE

SOOns

PROCESSOR
TS2

TP2

250ns

TS3

TP3

TS4

250n5

500ns

DETERMINED BY MEM DONE
I

(T) NORMAL

CYCLE

Tl ME

,5 jl

Figure 4-11

S«c.

@ TOLERANCES

± 20 %

System Timing Diagram

4-25

START (delayed). STROBEallows thetransition
from processor time state TSl toTS2,and generotes time pulse TPl (Drawing BS-8I-0-2).

STROBE also clears the MEM IDLE flip-flop disabling MEM START and TP4.

When STROBE generates TPl

the processor-

timing-progression continues. TPl is delayed by
0.15 |js to generate TP2 which clears the TS2
flip-flop and sets the TS3 flip-flop. TPl is also
delayed0.4|jstogenerateTP3. Thethird timepulse (TP3) clears TS3, and if the instruction
performed is neither an inp ut/outpu t inst ruction
nor an EAE function (both EAE SET and SLOW
CYCLE inactive), TP3 sets the TS4 flip-flop.

flop, and simult aneously clears the TS2, TS3,

and
TS4 f ip-f lops. MANUAL PRESET is generated by
pressing any of the keys mentioned above except
for Cont. When this key Is pressed, a TP4 pulse
is forced, setting the TSl flip-flop. The clearing
characteristic of MANUAL PRESET is avoided.
By pressing any of the keys mentioned above with
the exception of Load Add, MEM START is generated initiating a memory cycle.
Although normal computer operation is through
I

the use of continuously running stored program,

proceeding from instruction to instruction, in
sequence, this process must be started manually
may be stopped manual ly, or may be incremented
manually either instruction-at-a-tlme or stepat-a-timefor program debugging and mainten-

During processor time-state TS3 the INHIBIT and

WRITE control flip-flops (Drawing BS-8I-0-13)
are set by the delayed MEM START signal. At
•the end of the memory cycle MEM START (delayed) generates MEM FINISH which clears the
INHIBIT and WRITE flip-flops, and generates

ance purposes.
4.15

MAJOR STATES

A tota of six major states are provided to perform
I

cycle.

computer operations. These states are Fetch
Defer (D), Execute (E), Word Count (WC)
Current Address (CA), and Break (B). The major
state occurs in one complete 1 .5 |js computer
cycle except for Fetch when there isan input/
output instruction or an EAE function. The execution of a computer instruction consumes one
or more major states, depending upon the operations to be performed. The following paragraphs
describe the relationship between the states,
their functions and their generation.

The paragraphs above describe the re lationships
between PDP-B/l processor, and memory timing

Fetch - During this state, an instruction is read
into the sense register and the memory buffer at

cycles when the previous cycle initiates the next

the address specified by the content of the program counter. The instruction is restored in core
memory and retained in the memory buffer. The
operation code of the instruction is transferred to
the Instruction register for decoding, and the
contentof the program counter is incremented by

MEM DONE
MEM DONE sets the MEM IDLE flip-flop (Draw.

ing BS-8I-0-2)

The setting of this flip-flop allows the generation of MEM START (initiating
another memory cycle) and TP4, if the RUN flipflop is sti set and the PAUSE flip-flop is cleared
Time pulse TP4 clears the TS4 flip-flop and sets
the TSl flip-flop, initiating another processor
1

cycle bygeneratingTP4and MEM START. This
assumes that the PDP-B/l is running . When the
computer is initially started (by pressing ST, Load
ADD*, DEP, EXAM, or CONT) the processor
and memory cycles are entered in the following
manner.

The p rocessor timing cyc le is initiated by generating MANUAL PRESET which sets the TSl flip-

MEM

*When Load Add is pressed,
START Is inhibited, therefore, there is no memory cycle.

all

(F),

one.

The Fetch state is entered by pressing KEY ST
(Drawing BS-8I-0-3). When this key is pressed
the Manual Function Time Generated is activated,
and MFTP2 (Drawing BS-8I-0-2) Is produced.
This pulse, combined with a level produced by

KEY ST, sets the FETCH flip-flop.

4-26

The Fetch state can a Iso be entered during T4
time, by TP4of a fetch cycle oran Execute cycle.

the instruction is completed and the Fetch state
is

entered.

Entry occurs from a single cycle Fetch cycle in-

Execute -This state is enteredforall memory
reference instructions except JMP. During an
And, TAD, or Isz instruction the content of the
core memory location specified by the address

cluding all of the OPRand lOTcommandsand
the JMP command when directly addressed.
Entry into th e Fetch st ate occurs from the Exe-

cute cycle if BRK REQ occurs. When these conditionsare met, F SET (Drawing BS-8I-0-3) is

portion of the instruction is read first into the

active, enabling the FETCH flip-flop. F SET is

SENSE register and subsequently into the memory

produced when the fol low ing si gnals are inactive;
DSET, FSET, BREAK OK, and SPECIALGYCLE.

buffer and the operation specified by bits Oand 2

fetched, the
following major state will be either Defer or Ex-

of the accumulator is transferred into the memory

of the instruction (instruction operation code) is

performed. During a Dca instruction, the content
If a multiple-cycle instruction

buffer and is stored in core memory at the address
specified by the instruction. During a Jms inThe multiple-cycle instructions include
struction the content of the program counter is
the
indirectlythe And, Tad, Isz, Dca, Jms, and
written into the core memory address and the adaddressed Jmp instruction. When the above indress specified by the instruction is written into
structions are directly addressed, the EXECUTE
the program counter to change program control
flip-flop is set; when the instructions are indiThe Executestate can be entered at the conclurectly addressed the DEFER flip-flop is set. The

ecute.

sion of the Fetch, Defer, Execute, or Break state

following major state entry is executed by TP4
in

if there is a

both cases.

PROGRAM BRK REQ

In this event

the EXECUTE flip-flop is enabled by the E SET

Defer - When a

present in bit 3 of a, memory

reference instruction, the Defer state is entered
to obtain the full 12-bit address of the operand
from the address in the current page or page 0,
specified by bits 4 through 1 1 of the Instruction.
The process of address deferring is called indirect
addressing because access to the operand is addressed in'directly, or deferred, to another memory location.

The Defer state can be entered only from the
Fetch state when one of the multiple-cycle instructions And, Tad, Isz, Dca, Jms, or Jmp is
indirectly addressed (MB03=1). Under these conditions, entry is made during T4 time by TP4 in
the Fetch cycle. D SET (Drawing BS-8I-0-3)
enables the DEFER flip-flop. It is generated by
the active levels MB03=1 , an d B FETCH (1), and
the inactive level lOT + OPR.

With a PROGRAM
BRK REQ, E SET is generated by INT OK (Drawlevel (Drawing BS-8I-0-3).

ing BS-8I-(>-7).

Entry into the Execute state can also occur from
One of these occurs at the
two other methods
.

conclusion of the Fetch state when the instruction being performed is a directly-addressed

multiple-cycle command . When the signa Is
MB03 (0) and B FETCH (1) are active and JMP is
inactive, E SET is generated enabling the Execute flip-flop.

The other Execute-state entry method is from the
Defer state when any instruction except JMP is
performed . In this event, E SET is produced by
the DEFER (1) level and the JMP level inactive

If the

Regard less of the source of the Execute-state
entry , the EXECUTE f ip-f lop is set in the previous major state during T4 by time-pulse TP4.

When the
is made from the Defer state.
JMP instruction is performed with no BRK REQ,

The Executestate is the last state thata multiplecycle instruction enters. At the conclusion of

multiple-cycle instruction being performed
is not a JMP command, entry into the Execute

state

4-27

this state the Fetch state is entered again ex-

nal device suppliessignalsrequestinga data

eye le is not incremented . Incrementation , if it
occurs, occurs on the transfer to the memory
buffer from core memory . This word is rewritten
into core memory at the same location. The
Break state immediately follows the Current
Address state

break and the break is a 3-cyc le break . When
this state occurs, a transfer word count in a core
memory location designated by the device is read

stateis by progressing through the Word Count

ceptwhen the PDP-8/1 acknowledges a device
request! ng any type of break request at thi s time

Word Count - This state is entered when an exter-

Since the only entry path to the Current Address

into the memory buffer, incremented by 1 ,and

sWtewitha 3-cycle data break, the CURRENT

rewritten in the same location. Ifthe word count

ADDRESS flip-flop is set during T4 time byTP4

overflows , indicating that the desired number of
data break transfers wi be enacted at the com-

when the WORD COUNT flip-flop is set (Draw-

ing BS-8I-0-3).

pletion of the current break , the computer transmits a signal to the device. The Current Address
state I mmediate ly fo lows the Word Count state
I

Break - This state is entered to enact a data transfer between computer core memoryand an external device, eitherastheonlystateofa 1-cycle

data break or as the fina state of a 3-cyc le data
I

The Word Count state is entered at the end of
each major state excepting the Current Address

break When a break request signal arrives and
the cycle select signal specifies a 1-cycle break,
the computer enters the Break state at the com.

or the Word Count states when there is a request

3-cyc le data break. The request is acknowledged during T4 time.
for a

pletion of the current instruction. Information
transfers occur between the externa device and
I

The WORD COUNT flip-flop is enabled in the
SET level (Drawprevious major state by the
ing BS-8I-0-3) . This level is generated by the
active 3-CYCLEand BREAK OK levels. The
WORD COUNT flip-flop is set by time-pulse
TP4 in the previous major state.

At the conclusion of theWord Count state, the
combination of WORD COUNT (1) and timepulse TP4 sets the CURRENT ADDRESS flip-flop

ed by one to establish sequential addresses for
the transfers, and also transferred to the memory address register to determine the address
selected for the next cycle.

An inhibit signal

(from the data break device) can be supplied to

the computer so that the word read during the

The Break state is entered by the active B SET
level and time pulse TP4 in the fina major state
of the current instruction. In this event, B SET
(Drawing BS-8I-0-3) is generated by WC SET
and BREAK OK level Synchronization of the
asynchronous Break signal (from the device) is
done with the BREAK SYNC flip-flop (which is
set during TPI of either a one- or three-cycle
I

to the one state enacting Current Address entry.

Current Address -As the second cycle of a 3cycledata break, this cycle establishes the address for the transfer that takesplace in the following cycle (Break state) . Normally the location fol lowing the word count is read from core
memoryinto the memory buffer and increment-

a device-specified core memory location,
through the memory buffer . When this transfer
is complete, the program sequence resumes from
the point of the break. The data break (one- or
three-cyc le) does not affect the contents of the
accumulator, the link, or the program counter.

break)
Entryirito the Break state also occurs when there

a 3-cycle data break. This is the last cycle
ofthistypeof break and Break state entry isentered direct ly from the Current Address state . When
this occurs, B SET, generated by CURRENT ADDRESS (0) (Drawing BS-8I-0-3), enables the
BREAK flip-flop. This flip-flop is set by timepulse TP4 in the Current Address state.
is

4-28

At t-he conclusion of fhe Break state; the Word
Count state is entered if there is still a 3-cycle
break, the Execute state is entered if there is a
program break, and the Fetch state is reinstated
if there is no longer a break request.

The lower-level gating network includes the
adder circuitry, and logic gates for shifting operations. The adder circuits permit propagation
of carries, and provide a method of incrementing
data as the ISZ, lAC, and MA+l-PC functions
require. The data In the upper gating levels
passes through the adders to the lower level gates

4.16 INTERNAL DATA FLOW

(Drawing BS-SI-0-9; all sheets) whether or not
the operation requires a carry or addition.

When the content of one of the major registers
(MB, MA, AC, PC) is transferred or modified,

When any inter-register transfer within the

the data flow proceeds as illustrated by Figure

4-12.

For ease in understanding the data flow,

the sequence of events is described in three steps:
(1) source, (2)

route, and (3) destination.

PDP-8/I Is performed, excepting rotate, shift
operations, and the And instruction, a NO SHIFT
(Drawing BS-8I-0-5) is generated. NO SHIFT
allows data to pass from the adders directly
through the lower level gates to the REGister BUS
lines.

4.16.1

Source

When a shift or rotate instruction is per-

formed, specific upper and lower gating levels
direct AC data to the adder and through a par-

As Figure 4-12 illustrates, the 12-bit inter-regis-

ticular lower-level gate to the bus.

ter transfers are gated into the major register net-

when the RTR instruction (rotate every AC and

work by enable gates.

Link bit right two places) is performed,

include:

The basic gating levels

MA ENABLE, SR ENABLE, PC ENABLE,

MEM ENABLE, and AC ENABLE.

All enable

gates are partially conditioned by processor or

manual function time-state levels such as TS2(1),
MFTS(l), TS3(1). The enable levels allow the
data from one register to enter the major register
gating network (Drawing BS-8I-0-9) in a parallel
transfer

For example,

AC EN-

ABLE and DOUBLE RIGHT ROTATE levels are
generated (Drawing BS-8I-0-5). AC ENABLE
allows the AC data Into the adders. DOUBLE
RIGHT ROTATE directs each adder output two
places to the right. For the RTR command, the
content of the Link shifts to ACOl , ACOO shifts
two places to the right (AC02), ACOl shifts to
AC03 etc. Identical data shifting into the REG
BUS lines to the AC bits occurs with each bit.

4.16.2 Route

When the AND instruction is performed, the
After the contents of a register(s) are enabled,

the data enters the major register gating network

including the adders, and input to the REGister

BUS lines (Drawing BS-8I-0-9 all sheets). The

complement of the MB Is gated In on the lower
level by AND ENABLE bypassing the adders.
The AC ENABLE signal gates the AC onto the
upper network with NO SHIFT gating the con-

BUS lines. A zero appears here
MB or AC had a bit at zero.

tents to the REG

major register gating network consists of an upper
and lower gating network and adder for each of

if either the

12 bits.

The upper-level gating permits the register data
to enter the adders by combining major register
levels such as ACOO(O), DATAOO, and MEM03,
and other data inputs with an enable level, or
levels, depending on the operation performed.

4.16.3

Destination

All 12-bit inter-register data transfers enter onto

the REG BUS lines 00 through 11 after passing

through the major register gating network.

4-29

These

the enable levels, and time pulses partially con-

and the data on these
lines is loaded into the specified register by a
lines are the data input,

dition the load pulses.

if the AC is the destination,
generated. There are
pulse
is
AC
LOAD
the

clocking pulse, i.e. ,

As Figure 4-12 illustrates, data can enter the
major register gating network from the MB (AND

They are:
Each

three other major register load pulses.

MB LOAD, MA LOAD, and PC LOAD.

MA, PC, AC, SR, the INPUT BUS,
DATA BUS, DATA ADDR BUS, or from the SENSE

Instruction),

load pulse occurs at the end of a processor or

Data transfers from the REGister
BUS, however, can flow only to the MB, MA,
PC, or AC.

(MEM) register.

manual function time period by time pulses such
It should be rememas TP3, TP4, and MFTPl
.

bered that time-state levels partially condition

CORE
ogrpuT
INHIBIT

DRIVERS

CORE

MEMORY

STROBE

X AND Y
SELECT
INHIBIT

MEMORY TIMING
AND

ADDER

CARRY OUT

SENSE

CONTROL

CARRY

(2)

INSERT

(1)

t
L

ENABLE GATES

t
INPUT

BUS

DATA

MEM

ADDR

LOAD

MEM
MAJOR REGISTERS

(3)

Z^
AND

SHIFT

—

CP CONTROL
1

BUS (21

REG.

INTERNAL
OPTIONS

CENTRAL
PROCESSOR

TELETYPE
CONTROL

'—Nnfrn—
I

BREAK

FACILITY

OPTIONS

i/l SHIFT

DATA

EXTERNAL

INST
rsj

—I

TIMING AND

MAJOR

CONTROL

GENERATOR

STATE

LOGIC

NOTES
THREE STEP OPERATION
1. SOURCE
2. ROUTE
I

TO OPTIONS

Figure 4-12

4-30

Data Flow

DESTINATION

RES.

Data flow into core memory always occurs through
the MB under MA addressing control. For example,
when data in the AC is transferred to core memory

(DCA instruction), the AC data transfers to the
MB through the major-register gating network.
The contents of the MB are sampled, inhibited if
necessary, and written into memory.
tents of the

in the

MA and a memory read operation

initiated.

memory reference instructions or augmented instructions. A memory reference instruction con-

The con-

tains an operation code (in bits

which the write operation occurs. When the contents of a memory location are transferred to the

MB, the data flow occurs through the sense ampliSENSE register. The data then trans-

fers to the IR for decoding,

Each explanation begins at the start of the

fetch cycle, when the address of the Instruction is

Instructions performed by the PDP-8/1 are either

MA determine the address location in

fiers into the

gram.

and through the major

The data flow from outside the major registers to
one of them occurs through the INPUT BUS for
devices such as the Teletype and through the
DATA, and DATA ADDR lines for DATA BREAK

through 2) and

core memory at which the operation
An augmented
is to occur (in bits 3 through 11).
Instruction Is used when the operand is already In

an address in

no memory
through 2 of an augaddress Is required. Bits
mented instruction contain the operation code
which determines the general class of the instruction. Bits 3 through 11 of the Instruction contain
a register such as the AC;

in this case,

Information which permits the required operations
to occur during the two or three execution time

Operations performed in this manner are said to be "microprogrammed," since several such operations may take
states of a single (Fetch) cycle.

devices.

place during a single Instruction.

4.17 OPERATING INSTRUCTIONS
4.17.2 Memory Reference Instructions

The following paragraphs describe in detail, the
dynamics of the converter operation.

The format of a memory reference instruction appears in Figure 4-2. With the exception of Jmp
Instructions which reference a memory address in
or the current page, instructions occur
page
in two cycles: fetch and execute. Instructions
which reference any other page require three
cycles: a fetch cycle in which the Instruction
word is brought out of memory and contains the
effective address of the operand in the current
page or page 0; a defer cycle (refer to Direct/
Indirect Addressing In this chapter) in which the
absolute address of the operand is brought out of
memory and enters the MA; and the execute
cycle, in which the operand Is brought out of
core memory and operated on.

The normal mode of PDP-8/1 operation Is execution
of a prestored programmed instruction sequence. A
program interrupt can modify programmed operation,
or a data break can temporarily suspend programmed operation. A program interrupt transfers program control from the main program to a subroutine
to effect an information transfer with an l/O device or peripheral equipment. A data break Is an
automatic operation suspending the main program
for one or three cycles to permit a high-speed
I/O device to exchange information with the core
memory.

4.17.1

Instructions

The following explanations of the functions performed during the execution of each instruction
assumes that the PDP-8/1 Is energized and is operating normally under control of the main pro-

The following explanations of memory reference
instructions assume that the Instruction Is directly
addressed; however, the JMP Instruction Is described with direct and indirect addressing as an
example. It is also assumed that no break cycle
has been Initiated.

4-31

AND - The logical And operation occurs between

the contents of the addressed memory cell and the

are enabled to the corresponding

contents of the AC.

during time pulse TP4 these bits are gated into

The result is stored in the
AC. In effect, each AC bit is compared with the
corresponding memory-cell bit. Only when the

AC bits corresponding to the addressed memorycell bits are both a
will the particular AC bit
1

remain a

AND

at the end of the operation.

The logi-

therefore a transfer of binary O's. The
original contents of the AC are lost.
cal

The sequence of events listed below describe the
order in which the And instruction Is enacted.
The events described In paragraphs a through
and k are common to all memory-reference ini

During TS4, sense register bits 5 through

MA bits, and

the MA.

The same enabling and gating signals
affect sense register bits
through 4 and MA
bits
through 4 depending on the status of MB04.
This memory buffer bit determines whether the
addressed cell Is on the current page (MB04=1),
or on page zero (MB04=0). If it is on page zero,
zeros are transferred into MAOO through MA04.

g.
is

Also, during T4, the next major state entry

determined by the status of MB03.

contains a

1 ,

If this bit

indirect addressing is indicated

and the DEFER flip-flop is set byTP4.

structions.

If this bit

contains a 0, direct addressing occurs and TP4
sets the

The Fetch state is always entered with all
instructions at the completion of the last in-

struction performed.

In all cases, the

EXECUTE flip-flop. Only one major

state can be entered at any time. The state
entered depends on the input gating of each
major state controlling flip-flop during TS4.

FETCH

flip-flop Is set during T4 by time-pulse TP4.
h.

With all instructions, the functions that occur during Tl and T2 times are the same.
b.

During TSl of the Fetch cycle, the MA is
incremented and its contents transferred to the
PC by TP1
This will provide the address of the

next Instruction.

Towards the end of the processor cycle, the

memory write function occurs and the instruction
is written back into core memory.
When this Is
done, MEM DONE is generated, and TP4 Is generated to start another processor cycle and clear
TS4. MEM DONE also enables another memory
cycle to be initiated.

The word In the currently ad-

dressed location is also read into the sense register at this time.

During the strobe portion of the Execute

cycle, the operand stored at the address cur-

MA reads into the sense regAt TP2 the operand transfers to the MB,

rently held by the
d.

During TS2 the word in the sense register is

ister.

ready to transfer into the MB. The sense bits
through 2 are also enabled to the IR. Time pulse

TP2 loads the sense bits
through 2 into the IR
and the complete word in the sense register Into

AND instruction, the IR will
be loaded with O's because the AND operation

the MB.

For the

code is 03.

The contents of the IR (Os) produce
the AND level. This level is used by the processor for input-gating control functions for this

During TS3 the AND ENABLE level permits

the AND-combining of the AC and MB through
the major register gating network.

Time pulse
TP3 sets the AC bits whose register inputs are
active (high), and clears the other AC bits.

No operations occur for the And, Tad, Isz,
Dca, Jms and indirectly-addressed Jmp instruc-

Towards the end of the Execute cycle the
operand, which is unaltered in the AND process,
is rewritten Into memory during the Write portion
of the memory cycle. The operand of other instructions such as the Dca, Jms, and Isz is al-

tions during T3.

tered before

instruction.

4-32

rewritten.

questandSKIP=0,the contents of the PC are
loadedintothe MAatthistime by TP4. This

If there is no break request and SKIP=0, the

durcontents of the PC are loaded into the
pulse
time
ing Execute T4 time byTP4. This

time pulse also clears the I Rand sets the FETCH
flip-flop.

alsoclears the IRand sets the FETCH flip-flop.

This concludes the TAD instruction; the program

This concludes the logical And operation; the
program is ready to fetch the next instruction from

the location specified by the contents of the MA.

readytofeteh the next instruction from the
location specified by the contents of the MA.

Two's Complement Add (Tad) - The contents of the
addressed memory ce add to the contents of the
AC in 2's complement arithmetic. The result of^
the addition is stored in the AC, and the operand

Increment and Skip if Zero 0sz) -The Isz instructi on reads the contents of the addressed
memory ce into the sense register , and transfers
the contents of this register through the major

(addend) is restored to memory. The original
contents of the AC are lost.

-register gating network with a carry insert to the

MB. If the incremented contents ofthe MB are
not

During the Fetch cycle, the TAD instruction opD nstr uction .
erates n the same manner as the
Refer to events a through h for these operations.

The operation code Ig is decoded by the IR to
generate the TAD gating levelwhlch is used by
the processor to mplement the TAD operations
The actual two's complement add is performed in
the Execute cycle in the following sequence:

the program proceeds to the next I nstruc -

tion. Iftheincrementedeontentsofthe MBare
, the contents ofthe PC Increment by
and the program ski ps the next nstructi on
The events that occur in performing the Isz instructlonare listed in sequence below.

equal to
1 ,

Operations during the Fetch cycle of an
ISZ instruction are similar to those during the
Fetch cycle of an AND Instruction. Refer to
events a through h of the AND Instruction. The
only difference between these two instructions
during the Fetch cycle Is the operation code 2g

a .

During the memory strobe portion (Tl) of the
Execute eye ie, the addend reads nto the sense

decoded by the IR for the ISZ instruction
During T2 the operand in the sense register
istransferrredto the MB for rewriting into

memory

at the memory location signi fled by the contents

During Tl of the Execute cycle, the word

ofthe

MA is transferred into the Sense register,

During T3 the MB and AC outputs are enabled andapplied to the major register input
gating network. Carries are generated and

c During T2 of

propagated in the adders as required. Time
pulse TP3al lows generation of an AC LOAD
pulse during the Execute eye Ie of the TAD inAC LOAD transfers the sum of the
struction

major register gating network. The incrementation occurs through the application of a carry
Insert level to the adder ofthe least significant
bit during the transfer operation. If this carry
insert level produces a carry out from the most

the Execute cycle the Sense
register Istransferred to the MB through the

AC and MB Into the AC.

signi ficantbit, indlcatinganall

In T4 of the Execute state, the memory

cycle performs the write function. During this
portion ofthe memory cycle the original oper-

and held in the MB is restored to memory at the
original address eel I. If there is no break re-

4-33

Oeondition in

the register, the SKIP flip-flop is set byTP2.
TP2 also loads the MB register for rewriting
into memory.

d . No event occurs during T3 of the Execute

At the end of T2, time-pulse TP2 generates an

cycle,however,theSKIPflip-flopisset.This
allows incrementation of the program counter
register through a carry insert into the major

MB LOAD pulse that al lows the contents from
the AC to be loaded into the MB.

registers during T4.

The next sequential in-

struction will therefore be skipped.

e. During the memory write portion of the mem-

ory cycle the incremented contents of the MB

are written into the address eel from which
they were removed

LOAD pulse, however, no enable levels are
generated. This lack of enable levels places
the equivalent of all O'sonthe input to the
major register gating network. The AC LOAD
pulse therefore, loads these O's into the AC,

d . During T3, time-pulse TP3 generates an AC

effectively clearing the register.

Time pulse TP4(attheend of TS4) sets the

FETCH flip-flop if there is no break request.

e. During the write portion of the memory cycle

the contents of the MB are written into the core
location specified by the MA. During T4if
neither a break request nor a skip = 1 level is
present, the contents of the PC are transferred

Deposit and C lear Accumu ator (Peg) - The Dca
I

instruction deposits the contents of the

AC into

to the

MA to specify the next desired core lo-

theaddressed memory cell and theACcIears. The

cation. Time pulse TP4sets the FETCH flip-

original contents of the addressed cell are de-

flop allowing entry into the Fetch cycle.

stroyed. The sequence of events that occur in

J ump to Subroutine (JMS) - The Jms instruction

performing the Dca instruction are listed be low.

provides an exit.from the main program into a

a . Operations during the Fetch cycle of a Dca

subroutine. The contents of the PC (current pro-

instruction are similar to those occurring during

gram count) incremented by 1 ,are written into
the core memory address specified by the Jms instruction. That address transfers to the PC and
increments by 1 ; this incremented address fetches

the Fetch cycleof theAnd instruction. Refer
to events a through h of the And instruction.

The operation code for the two instructions differs. The operation code 3gdecoded by the IR
for the

Dca command generates a Dca level

the first subroutine instruction during the next instruction cycle.

When the subroutine ends, the

which isused as a gate-enable signal forthis

main program is reentered by a jump indirect to

instruction.

theaddressspecifiedbytheoriginal Jms instruc-

b. During T4ofthe Fetch cycle the EXECUTE

The contents of that address are now the
incremented main-program count, and transfer-

flip-flop is set to allow entry into this state.

ring this count into the PC causes the main pro-

tion.

gram sequence to continue.
c. During T2 of the Execute cycle, the Dca
level combined with B EXECUTE (1) inhibits

MEM ENABLE 0-4/5-1

This prevents the
1 .
contents of the Sense register from transferring

totheMB. Therefore, the contents of the ad-

The sequence of events in performing the Jms instruction are listed below. In addition, to further
clarify the Jms operation, a sample program with
this instruction

given in Table 4-1.

a. Operations during the Fetch cycle of a Jms

dressed cell are lost.

instruction are similar to those occurring during

the Fetch cycle ofthe And instruction. Refer

The levels TS 1 (1 ), Dca, and B EX ECUTE (1
combine to generate AC ENABLE during T2.

to events a through h ofthe And instruction.

This al lows the contents of the AC to transfer

through the major register gating bus to the MB.

4-34

The operation code for the two instructions differ . The operation code 4g decoded by the IR

Table 4-1

Example of Register Contents During JMS Instruction

Cycle

Fetch or

Time

TS4

PC Contents
0-4
5-11

MEM Contents
Address

(Page)

(Location)

D/20

Contents

Unknown

MB Contents

MA Contents

0-4

5-11

Unknown

PC-MA
1-F

Execute
Fetch

Command

TSl

D/21

JMS/0/100

Unknown

MA+l-'PC
Memory -MEM

TS2

D/21

JMS/0/100

MEM-MB
MEM-IR

TS3

No operations

TS4

D/21

JMS/0/100

MB -Memory

MEM-MA
1-E
Execute

TSl

0/100

xxx/x/xxx

TS2

0/100

xxx/x/xxx

TS3

0/101

TS4

0/101

100

Memory-MEM

100

PC -MB

0/100

100

MA+l-PC

0/100

100

MB -Memory
PC -MA
1-F

Fetch

TSl

102

0/101

1st

Subroutine

Instruction

101

MA+l-PC
Memory -MEM

Jms command generates a Jms level which

for the
is

used as a gate-enable level for this instruc-

tion.

(1) During T4 of instruction 208 '" *^^ "1°'"
program, the PC contains the address of the
next instruction, location 2l8 In page D (cur-

rent page).

During Tl of the Execute cycle no operations

This address Is transferred into the

MA.

occur.

During TSl of the Fetch cycle for Instruction 2l8, the contents of cell D2l8 reads into
(2)

During T2 of the Execute cycle the contents

of the

PC are transferred to the MB if there is

no skip condition (SKIP=0). In order to perform
this operation, PC ENABLE and MB LOAD are
generated. PC ENABLE allows the contents of
the PC to enter the ma|or register bus.
tents of the bus are loaded by MB

The con-

LOAD into

the MB.

the sense register.

Upon completion of the
read operation the sense register contains Jms/
0/100 (41008). The Jms operation code (48)
is in bits 00 through 02; page
is specified by
bit 03 =
(denoting a direct address) and bit
04 =
(denoting page 0). Bits 05 through 1
specify location lOOs (of page 0). Also during
TSl the contents of the
increments as it

During T3, the current address is incremented

by one and transfe rred to the PC.

PC.

To do this,

MA ENABLE, CARRY INSERT, and PC LOAD
signals are generated. MA ENABLE allows the
contents of th e MA to enter th e major register
the

network bus.

transfers into the

CARRY INSERT adds one to the

Finally, PC LOAD loads
the PC with the incremented contents of the bus.

contents of the bus.

(3)

MB.

Bits

00 through 02 transfer into the IR

where they are decoded to produce the Jms
level.

(4)

During the write portion of the memory cycle,
the contents of the MB (described in event c of

During T2, the contents of the SENSE

No operations occur during TS3.

this instruction)

are written into memory at the

location specified by the Jms instruction.
f.

During T4 of the Jms Fetch cycle, the
contents of the MB (the Jms Instruction) is
(5)

written back Into its original core location
(D2l8).

During T4 the FETCH flip-flop is set by TP4

if there is

neither a break request nor a SKIP=1

level.

(6)

At TP4, the contents of MB05 through

transferred to the corresponding bits of the

and, because bit MB04 = 0, bits MAOO
through 04 are cleared to indicate page 0.
The events above describe the Jms operation.
These events are easier to understand, however,
if a concrete example is given.
The following
events describe the sample program of Table 4-1
The program sequence assumes that the main pro-

The MA now contains (0/1008), ^^^ address

specified by the Jms instruction.

NOTE

gram is in page D of memory (current page), and
that the 21st instruction

is Jms directly, page 0,
location lOOg. The following conditions are also

MB03 or MB04 control page and whether
instruction

deferred or executed.

assumed for this example: memory pages are designated 0, A, B, C, D, E; each page contains
locations designated

routine

page

through 177g; and the substarting at location lOlg.

4-36

During Tl of the Jms Execute cycle, the
contents of core location (O/lOOg), as speci(7)

fied by the address portion of the Jms instruction (which is now in the MA), reads into the

The Jmp instruction contains either the absolute
core-memory address of the next operand (direct

sense register and is lost,

addressing) or the address of a location containing the absolute core-memory address of the next

During T2 of the Jms Execute cycle, the

operand (indirect addressing). When the next
contents of the PC, which is D/223, (address
operand is located either in the current page or
of the next sequential main-program instruction)
page zero of memory, dir'ect addressing is used
transfers into the MB. The SKIP flip-flop is
requiring only a single fetch cycle to extract the
assumed as clear.
operand and prepare for its execution. If, however, the next operand is located in any other
(O/l OOs)
(9) Duri ng T3 , the contents of the
page in memory, its 12-bit absolute address must
which is the current subroutine address, is inbe stored in either the current page or page zero
cremented by one as It is transferred to the PC.
at a location specified by bits 05-11 of the Jmp
instruction. This Is known as indirect addressing,
(10) During T4, the contents of the MB (D/228>
and requires both a fetch cycle and a defer cycle
writes into memory location (O/IOOq). At TP4,
to extract the operand for processing.
the contents of the PC (0/1 01 3) transfer to the
(8)

MA to select the core memory location con-

The events that occur in performing the Jmp instruction are listed in sequence below.

taining the first active instruction of the subroutine. At this time, the Jms Execute cycle
is terminated and the Fetch cycle of the first
instruction of the subroutine

Operations occurring during Tl and T2of the
Jmp Fetch cycle are Identical to those events of
the And instruction in the same time periods except for the operation code 58 decoded by the

entered.

During Tl of the Fetch cycle, the first
instruction of the subroutine reads from core
(11)

IR for the Jmp Instruction.

location (0/1 01 3) Into sense register. The
program then proceeds to execute the sub-

Refer to events a

through d of the And instruction.

routine.

(12)

Operations during T3 of the Fetch cycle depends upon whether the Jmp specifies direct
(MB03=0) or indirect (MB03=1) addressing. If
Indirect addressing is indicated no operations

(0/1 OOs) contains the address in core memory
of the next sequential main-program instruction

By this means the subroutine Is terminated and the main program reentered at the

occur during T3. If direct addressing Is indicated, the specified address (SENSE 05 through
11) Is loaded into the corresponding bits of the
PC. If the instruction specifies that the operand
(MBO^O), bits 00 through
is located on page

point at which it was interrupted.

04 of the PC are cleared.

The last Instruction of the subroutine must
be a jump indirect to the location originally
specified by the Jms Instruction, in this case
(O/lOOs). As noted in step 10 above, location

(D/228).

however, the instruction specifies that the operand is In the current page (MB04=1), bits 00 through 04 of the

Jump (Jmp) - The Jmp Instruction links two pro-

If,

gram instructions that are executed consecutively

MA are transferred to the corresponding bits of

when the instructions are not in sequential loca-

the PC.

tions.

This instruction

commonly used to link

a program together when the program length extends over more than one page (1778 locations) of

core memory.

Jmp is also extensively used in

program loops such as counting and comparing in
conjunction with the Skip instructions.

4-37

The following events occur during T4 of the

Fetch cycle of a direct address Jmp (if neither

a Break request nor a Skip is specified: PC transfers to the MA, the Jmp instruction is restored
Intact to Its original core-memory location, and

the FETCH flip-flop is set.

The operand is re-

MA.

Also during T4 the contents of the MB are

moved from core-memory during the next ma-

written bock into memory at the original loca-

chine cycle (Fetch) and implemented.

tion (intact

For an indirectly addressed Jmp during 14,

bits 05 through

of the sense register transfer

1 1

to the corresponding bits of the

of the MB is examined.

address of operand on page 0) ,

MA04 are cleared.

MA and bit 04

MB04=0 (absolute

MAOO through

Auto Index was not performed, or
incremented by 1 if Auto Index was performed).
At the end of T4 the FETCH flip-flop is set alif

lowing Fetch cycle entry for the next Instruction performed.

During the ensuing Fetch cycle

the operand is read from memory and its operations begun.

MB04=1 (absolute address

of operand on current page), bits 00 through 04

MA (current page address) are circulated
out of, and back into, the same MA bits. Also

4. 17.3. Direct/Indirect Addressing

of the

during T4, the Jmp instruction is restored intact

Six of the eight basic instructions in the PDP-8/l
repertoire are designated as memory-reference

to its original core-memory location. At the
end of T4 the DEFER flip-flop is set, allowing

instructions.

entry into the Defer state.

either write into or read from memory.

The following events relate to the Jmp instruction when the Defer state

entered.

This state

These instructions (And, Tad, Isz,
Dca, Jmp, and Jms), as part of their function

The first three bits (0-2) of these 12-bit instructions contain the operation code designating the

can be entered with any of the memory reference specific function to be performed.
instructions and

not restricted to the Jmp in-

struction exclusively.

The remaining

nine bits (3-11) are therefore available to specify
the memory location involved in the required op-

A complete specification of any one of
the 4096 locations in the basic PDP-8/I memory,
eration.

During Tl of the Defer cycle, the absolute

12-bit address of the operand Is read from the

however, requires the use of 12 address bits

memory location specified by the Jmp instruction (2 ^=4096). To minimize the number of instruc(or any of the memory reference Instructions) in- tions required to access memory,
therefore, both
to the sense register.

direct and indirect addressing

used In the

PDP-8/I.
f.
During T2, the contents of the sense register
are transferred to the MB if an Auto Index Is not

required.

When there is an Auto Index, the

contents of sense are incremented by 1 In the
major register gating network before loading into the MB. An Auto Index occurs when a memory reference instruction such as the Jmp com-

mand is indirectly addressed in one of the locations lOg through

The memory is organized into 32 pages (or blocks),
each containing 128 consecutive memory locations. These pages are numbered
through 3/3.
The specification of any of the 128 locations on a
particular page requires only seven bits (2^=128).
Bits 5

through

11 of the memory

reference in-

structions are used for this purpose.

Uq on page zero of memory. eration code carried in bits

With the op-

through 2, bits 3

and 4 remain to specify the direct/indirect adg. During T3, the contents of the sense register dressing mode of operation.
are transferred to the PC (intact if an Auto Index
Is

not specified, and incremented by one If an

Auto Index is specified).
h.

During T4,

no break request Is specified,
the contents of the PC are transferred to the
If

4-38

The status of bit 3 of the instruction specifies
whether direct or indirect addressing Is to be
performed. When bit 3=0 direct addressing is
specified. I.e.; the location specified in bits 5

through

contains the operand upon which the

Input/Output Transfer (lOT) - The
lOT class of augmented instructions generate

function described inbits through 2 is to be
performed. Ifbit3=l, indirectaddressing is
specified; i.e., the location specified in bits 5
through 1 1 contains the absolute 12-bit address
of theoperand.

4.17.4.1

pulses lOP pulses) thatallows the PDP-8/I processor to communicate with both the internal and

externa devices . The lOP pulses generated by
performing this instruction are used for timing

An additional computer cycle

(Defer) is therefore required to extract the 12-bit
address of the operand from the specified address

control applications, synchronizations, and

data transfer functions.

The status of bit 4 determines whether the location specified by bits 5 through 11 is on the currently addressed page of memory, or on page
(l=current page, 0=page 0). Through the use of

The format of the lOT instructions differ from
that of the memory reference instructions as
Bits 00 through 02
code
contain the operation
(6g) , bits 03 through
08 form a code that enables the device selector
in a given I/O device, and bits 09 through 11
enable the generation of lOP pulses which

illustrated in Figure 4-2.

bit 4, therefore, a memory reference instruction

can address 256 locations; 128 in the current
page, and 128 in page 0.

control the data-transfer operation

Itshould be noted that the full, 12-bitabsolute
address of the desired location must be present in
the

Two processor lOT instructions ION (60018)

MA to permit access to that location. The

and lOF (6002q) do not permit generation of

1 2-bit starti ng address of the program is entered

into the

lOP pulses when they are performed. These in-

MA through the switch register and the

structionsare used to enable the program interrupt facility (ION) or, disable it (lOF).

LOAD ADD key when programmed operation
commences.

In normal operation, the PC is in-

cremented during each FETCH cycle to step the
address to the next sequential memory location
When a memory reference instruction is extracted
from memory, only bits 5 through 11 are transferred to the MA.

The following events described the operation of
the lOT instruction (refer to the lOT timing

diagram Figure 4-14).

If bit 4of the instruction isa

Operations during T 1 and T2 of the lOT
Fetch eye le are identical to the events a
through d ofthe AND instruction, except for
the operation code 6g decoded by the IR for the
lOT instruction during T2 The IRgenerates

are left unchanged
through 4 of the
1, bits
and the next location addressed is on the current
page. If, however, bit 4 is a 0, bits through 4
ofthe MA are cleared. This addresses the bit 5

through 1 1 location on page

of the memory

the lOT level used in the lOT operations

Figure 4-13 isa simplified flow chart showing
the sequence of operation of both the direct and

Atthe end of T3 of the Fetch cycle, TP3
and SLOW CYCLE (produced by the lOT level
during T2 if not a processor lOT) generate
lO START which sets the PAUSE flip-flop preb.

indirect addressing functions.

4.17.4 Augmented Instructions

venting the generation of another MEM START
pulseand resetting ofthe major-state generator.

The two classes of augmented instructions used
in the PDP-8/lare: The input/output transfer
(lOT) which has the operation code 6gand the
operate instruction (OPR), which has the opera-

c. Approximately 150 ns after the generation
of lO START, an lOP 1 pulse is generated for
700 ns(±20%) if MB 1 1=1 . After a delay of

Augmented instructions are
single-cycle (Fetch) instructions which initiate
tion code 7q.

200 ns IOP2 is generated for 700 ns (±20%)

various operations asa function of bit micropro-

gramming.

4-39

MB10=1.

LOaO STARTING
ADDRESS Y
(SRO-M
PCO-111

—

SET y INTO MA
(PCO-II

—MAO-11)

SET FETCH
STATE

INCREMENT PC
(NOW HOLDS V + t)

RETRIEVE FIRST
INSTRUCTION FROM

INSTRUCTION
RETRIEVAL

y AND SET INTO MB

SET OP CODE
INTO IR

(SENSE 0-2-»-mO-2l

SET EFFECTIVE
ADDRESS OF OPERAND

EFFECTIVE
ADDRESS OF

(Zl INTO

OPERAND

MA (SENSE

5-l1-»MA5-1t)

MB4 A

\oV,,-^
|no

SELECT CURRENT
PAGE (MAO-5
NOT CHANGEDI

SELECT PAGE

(0-»MA0-41

;

SET DEFER

STATE

RETRIEVE ABSOLUTE
ADDRESS (X) OF OPERAND
FROM LOCATION Z IN PAGED
OR CURRENT PAGE

ABSOLUTE
ADDRESS
RETRIEVAL

SET ADDRESS OF
OPERAND (XI INTO MA
(SENSE0-I1-»MA0-111

SET

EXECUTE
STATE
RETRIEVE OPERAND
FROM LOCATION Z
IN PAGE
OR
CURRENT PAGE

OPERAND
RETRIEVAL

RETRIEVE OPERAND
FROM LOCATION X
(MAy BE IN
ANY PAGE)

-^'
EXECUTE THE
INSTRUCTION

ON OPERAND

SET ADDRESS OF
INSTRUCTION
INTO MA

(y + 1)

IPCO-ll

—* MAO-11)

SET FETCH
STATE

INCREMENT PC
(NOW HOLDS y +Z)

RETRIEVE SECOND
INSTRUCTION FROM
LOCATION y + i

Figure 4-13

Direct and Indirect Address
Selection, Simplified Flow Chart

4-40

After 200 ns lOP 4 pu Ise is generated for 700 ns
(±20%) if MB09=1 . After an additional 350 ns
delay, the lO END isgenerated. This pulse,

Certain lOT instructions are normally combined
toclearthe AC and transfer data to the accumulator in one computer cycle. This is perform-

MEM

ed by generating AC LOAD as described above,
and disablin g AC ENABLE (Drawing BS-8I-0-4).
AC CLEAR (Drawing BS-8I-0-4), gated by I/O

d . The lOP pulses are gated in the device selector of the addressed I/O device to produce

STROBE, disables AC ENABLE, thus O's are
loaded into each AC bit when l/O STROBE occurs (norma ly during lOP 2). During IOP4
time, data is loaded into the AC by I/O STROBE.

delayedand additional 300 ns (±20%), clears
the PAUSE flip-flop to permit another

START level

lOT pulses. The lOT pulses control the operation of the device, effect a transfer of information between the device and the processor, or
initiate action in the processor, such as clear-

ing the AC, or incrementing the PC .

In addi-

tion, with each lOP pulse generated, l/Q

STROBE is produced allowing AC LOAD (Drawing BS-8I-0-6) to clock data from extended

memory or other options into the AC.

TP3

4.17.4.2 Operate (OPR) - The OPR class of
augmented instructions consist of two categories
of microinstructions Group 1 and Group 2. The
format of these groups appear in Figures 4-4and
4-5, respectively. In each case, bits 00 through

02 contain the operation code 7g. Group 1, de-

I/O START - TP3. SLOM( CYCLE
I/O START

L
1

700 nj

K.-Z00n»-« .

I0P1

I/O STROBE

—

-400 n.

•

(IF

—

lOP 4

—

I/O STROBE

—

MBll- II

I/O STFIOBE

(IF

MB11 -1)

—

I0P2

•

(IF

l«-200n.-*

MBia- 11

IIFMB1 «-l)

(IF

U-aoOns-.

1/0

(IF

END -

TS1 -

NOTE: TIMING TOLERANCE t 20 %

Figure 4-14

lOT Generation

4-41

MB «9- 1)

MB 59- 11

signated by a
structions.

03, are called Opr
inOpr 1 instructions perform AC and
in

h'\f

Link operations such as clearing, complementing,
rotating, and incrementing. Group 2, designated

by a 1

in bit 03 and a

in bit 11

Time pulse TP3 generates the load signals

such as AC LOAD, that perform the transfer of
data from the major register gating network to
the indicated register.

are called Opr 2

instructions. These commands check the contents
of the AC and Link, and on the basis of the results,

determine whether the next sequential instruction
is to be performed or skipped.

The major state B FETCH (1) time-state TS3

levels are used as enabling levels.

Except for the rotate OPR 1 instructions, the
is generated to allow all transfers from the adder of the major register gating
network onto the network bus.
f.

NO SHIFT signal

The Opr 1 operations may occur either singularly
or in logical combinations.

Care must be exercised, however, to ensure that contradictory or
conflicting operations are not specified within the

same instruction.

For example, bit 08 of the Opr 1

microinstruction, when set to

1 specifies an RAR
(rotate AC and L to the right one place) operation.

Bit 09 similarly specifies an

RAL (rotate AC and L

to the left one place) operation. It is physically
possible, by setting both bit 09 and 08 to the 1

state, to request an impossible, conflicting operation, i.e. , rotate AC and L both right and left

one place simultaneously.

NOP

instruction
(70008),- however, to conform with the flow

chart (Drawing BS-8I-0-1) each bit is discussed
in order; therefore, several
this instruction

events occur when
performed.

The Opr instructions and their operations are described below.
During Tl and T2 of the Fetch cycle, the
operations that occur are identical to events a
through d of the And instruction.

The following se-

quence of events describes the operations of this
class of instructions.

There is only one OPR 1

Both groups of Opr microinstructions are single-

cycle (Fetch) instructions.

The instruction descriptions

contain the primary signals necessary to perform

During T3, bit 03 of the Opr instruction is

examined to determine whether the instruction
is an Opr 1 (MB03=0) or an Opr 2 (MB03=1).

the specified«operations.

Appropriate levels are generated in the control

primary signals are generated.

group.

Reference to the mechanization charts indicates where and how the

For ease of explanation, the signals and conditions common to most of the Opr instructions are
listed below.

implement the requirements of each
The descriptions of the instructions that
follow should be carefully traced in the flow
chart (Drawing BS-8I-0-1) to facilitate undercircuits to

standing of the system operation. The order of
appearance of the Instruction descriptions parallels the order shown in the flow diagram. It
should be noted that, through microprogramming,
operations may be combined during the same
For instance; AC-AC (CMA)and L-L
(CML) may occur in the same instruction to
complement both the AC and the Link.

cycle.

The operations code is 7q.

Actual AC and L operations occur during T3

of the Fetch cycle.
c. The Opr level decoded by the IR serves as
an enabling level, and also combines with MB03

to form

OPl and OP2 levels.

c. During T3, when the Opr 1 instructions are
specified (MB03=0), the following Instructions

can be performed.

4-42

They are:

(1)

NOP (no operation). When fhe 7000q

(6)

CML (complement the Link). When the

instrucHon is performed, MB04=0, MB06=0,
and no other opei'ond exists. The contents of

70208 Instruction is performed, MB05=0,
MB07=1 , and no other operand exists. The

the AC are circulated through the major register and adder network, and returned unaltered
to the AC (AC-AC). This transfer occurs when

side of the Link bit (L) transfers through the

AC ENABLE, AC LOAD, and NO SHIFT are
generated.
the Opr

The events described in 5 and 9of
instructions also occur simultaneously

ated.

CLL (clear the Link). When the 71008
Instruction Is performed, MB05=1, and no

with the AC circulation.

(2)

major register gating network intojhe Link
(I-L). This transfer occurs when L ENABLE,
SHIFT levels are generAC LOAD, and

(7)

level is transother operand exists, and logic
is performed
operation
ferred to the Link. The

CMA (complement the AC). When the

70408 instruction is performed, MB04=0,
MB06=1 , and no other operand exists. The

NO SHIFT signals

by generating AC LOAD and
with no enable levels existing.

AC bits (AC) is transferred through
AC
AC
the
(AC-AC). This transfer occurs when
ENABLE, NO SHIFT and AC LOAD signals

side of all

the m ajor register gating network to the

STL (set the Link). When the 71208 instruction is performed, MB05=1 , MB07=1, and
no other operand exists, the combined operations of the CML and CLL instructions described in 6 and 7 above occur (L + L - L).
The Link is set to the 1 state by clearing it,
(8)

are generated.

(3)

CLA (clear the AC). When the 72008 in-

struction is performed, MB04=1 , MB06=0, and
levels are
no other operand exists, logic

then complementing it.

transferredto allACbits. This transfer occurs
SHIFT levels,
by producing AC LOAD and

(9)

instruction Is performed,

with no enable levels existing. Thlsoperation
clears (sets al

bits to 0) the

NOP (no operation). When the 70008
MB08=0, MB09=0,

and no other operand exists.

AC register (0-AC)

In addition to

the events described for this instruction in 1
SHIFT level is generated. This
and 5, the
level controls transfers of all data from the

(4)

CLA/CMA (clear and complement the AC).

When the 72408 instruction is performed,
MB04=1 , MB06=1 , and no other operand exists.
The AC is cleared then complemented (AC+

AC-AC, set AC=-1). This effectively sets
state. This_ operaall of the AC bits to the
tion occurs when the AC ENABLE, AC ENABLE,
NO SHIFT and AC LOAD signals are generated.
1

(5)

NOP (no operation). When the 70008 in-

adder onto the major register bus. This signal
and Is
Is generated for all OPR 1 instructions,
gated by MB08=0, and MB09=0. It should be
SHIFT signal is also genernoted that the
ated for all instructions except for the EAE
shift group, but there is a different path ac-

tivated.

(10)

struction is performed, MB05=0, MB07=0, and
no other operand exists (refer to instruction

RAR (rotate the AC and Link right one

place).

When the 70108 instruction is per-

formed, MB08=l,and no other operand exists.

The contents of the AC and L are shifted one
bit to the right. The Link status is transferred
into ACOO, while ACll status transfers into
the Link. The RAR operation occurs when the
L ENABLE, AC ENABLE, RIGHT SHIFT and

description 1). The L-L circulation occurs
and the contents of the Link are circulated

through the major register gating network and
returned unaltered to the Link. This transfer
occurs when the L ENABLE, AC LOAD, and
SHIFT signals are generated.

AC LOAD signals are generated.

4-43

(11)

RAL (rotate AC and the Link left one

place).

4.17.4.3

When the 70048 instruction Is per-

formed, MB09=1 , and no other operand exists.
The contents of the AC and Link are shifted

one bit to the left.

The content of ACOO is

OPR2 -WhenMB03=l, and MBIT =0.

the OPR 2 group of microinstructions is specified.
These microinstructions may be performed singly
or in useful logical combinations. Theavailable
commands include: CLA, HLT, OSR, and seven

transferred to the Link, and the content of the

skip instruct ions dependent upon the status of the

Link bit is transferred to ACl 1 .

AC and/or Link.
The operations performed during Tl and T2 of the
Fetch cycle of the Opr 2 class of instructions are

The RAL operation is performed when LEFT SHIFT, L ENABLE, AC ENABLE, and AC LOAD signals are
generated.

identical to those previously described for those
time states in the
Instruction. The following

AND

(12)

RTR and RTL (double rotate, right or left).

When the 70128 instruction (RTR) or the 70068
instruction (RTL) is performed, MB10=1, and
the operand for either the RAR or RAL instruc-

instruction descriptions therefore, describe the

Opr 2 Instructions during T3 of the Fetch cycle.

SZA (skip on zero AC). When the 74408

(1)

instruction is performed MB06=1

However, to avoid conflicting
operations, only one of these operands should
exist at one time. The RTR command rotates
the contents of the AC and Link two places to
tion exists.

operand exists.

and no other

The contents of the AC regis-

ter are checked and if the AC=0, the next se-

quential program instruction is skipped.

When

the AC=0, the SKIP flip-flop is set to the one

Similarly, the RTL command rotates
the contents of the AC and Link two places to

state by TP3, B

the left.

enable level generated by And-comblnation of

the right.

Both the RTR and RTL Instructions occur when

ENABLE, AC ENABLE, DOUBLE RIGHT
ROTATE or DOUBLE LEFT ROTATE, and AC
L

FETCH (1), Opr, and a, skip-

all

AC 0-side outputs.

(2)

SMA (skip on minus AC). When the 75008

is performed MB05=1 and no other
operand exists. The content of ACOO Is sensed
to determine its status. If AC00=1 , a minus

instruction

LOAD are generated.

AC Is specified, the SKIP flip-flop Is set, and
lAC (increment the AC). When the 70018
Instruction is performed, MB11=1 and no other
(13)

operand exists. The AC is incremented by 1
by transferring the contents of the AC to the
major register gating network, adding a logic 1
through the network adder, and transferring
the incremented contents into the AC. The

AC ENABLE, AC LOAD, and CARRY INSERT
signals are generated to perform this instruction.

The lAC command can be combined with either
the CLA or

CMA commands to perform the

functions of both during one cycle.

When the

CLVIAC Instruction or the CIA (lAC/CMA)
instruction

performed, the operations of both

separate Instructions are performed simulta-

neously, during T3.

4-44

the next sequential program instruction Is skip-

ped. This flip-flop is set by a load pulse generated by the TP3, B FETCH (1) and Opr signals.

The skip-enable level Is produced by

MB05 (1) combined with ACOO (1).
(3) SNL (skip on non-zero Link). When the
74208 Instruction is performed, MB07=1 and
no other operand exists. The Link bit is sensed
to determine whether it is in the 1 state, and
If It is, the next sequential program instruction
is skipped.
The SKIP flip-flop is enabled by
LINK (1), and MB07 (1), and set by the combination of TP3, B FETCH (1), and Opr signals.
(4) SKP (skip unconditionally). When the
74108 instruction is performed, MB08=1, and
no other operand exists. The next sequential

instruction is skipped regardless of the contents

operand exists.

of the AC and Link.

(0-»AC).

The SKIP flip-flop is enabled by MB08 (1), MBIT (0), and OP2; it is
set by the combination of TP3, B FETCH (1),
and Opr.

When one of the SZA, SMA, or SNL operands
is combined with MB08 (1), reverse sense skipping occurs, i.e. SZA becomes SNA (skip on
,

non-zero AC;7450g), SMA becomes SPA (skip
on plus AC;75108), and SNL becomes SZL
(skip on zero Link;74308).

Opr 1

exists.

This operation clears the RUN flip-

flop, inhibiting the generation of a

the Opr 2 microinstructions.

ter T4 time.

OSR (inclusive OR between the SR and
AC). When the 74048 instruction is performed
(6)

As a result the

AC can be cleared after it is sensed by one of
the skip instructions, or combination between
the OSR and the CLA may be made resulting
in the

LAS (load the AC with the contents of

the SR).

NOP (No Operation). When the 74008
MB03=1 , and no other
The same events described for

instruction is performed,

operand exists.

NOP conditions of the Opr

descriptions

START level which prevents the start of another machine cycle. The computer stops af-

identical to the

The CLA instructo
combine with
exists
order
in
2)
(Opr
tion

the

MEM

CLA instruction with the exception of

the OP 2 and MB04 levels.

(8)

HLT (halt operation). When the 74028 is
performed, MB10=1 , and no other operand
(5)

The AC is loaded to all O's

This instruction

instruction

1,5, and 9 occur.

The Opr 2 instructions listed above may be logically combined to perform more than one operation in a single Fetch cycle. Examples of the
combined microinstructions are listed below; however,

MB09=1 , and no other operand exists. The result of the inclusive OR remains in the AC.
The OSR operation occurs when the AC ENABLE, AC LOAD, SR ENABLE, and NO SHIFT

many other useful combinations exist.

SZA CLA (76408). When this instruction
the content of the AC is sensed.
performed,
is
If each AC bit is a binary 0, the next instruction is skipped and the AC is cleared.
(1)

signals are generated.
(2)

(7)

CLA (clear the AC).

When the 76008 in-

struction is performed MB09=1 and no other

4-45

SNA SZL (74708). When this instruction

performed the next sequential instruction is
and the Link = 0.
skipped if both the AC 7^
is

CHAPTER 5
MAINTENANCE
alent equipment used by Digital Equipment Corp.

This chapter contains Information pertinent to

preventive maintenance, corrective maintenance, field service personnel,

and troubleshooting techniques, of the PDP-8/I.

5.1

EQUIPMENT

5.2

Table 5-1

lists

ifications

needed for maintenance of the basic
Also Included in the list is the equiv-

PDP-8/I.

the equipment and relevant spec-

PROGRAMS

Table 5-2 lists the Maintenance Programs supsplied by DEC for ascertaining proper operation
of the

PDP-8/I

Table 5-1

Maintenance Equipment

Equipment

Specifications

Equivalent

310

Multimeter

lOK ohms/volt-20K ohms/volt

Triplett Model

Oscilloscope

dc to 50 mc with calibrated deflection factors from
5 mV to lOV/div. Maximum horizontal sweep rate
of 0.1 |js/div. Delaying sweep is desirable and
dual trace is a necessity.

Tektronix Type 453

Probes

XIO with response characteristics matched to

Tektronix Type P6010

oscilloscope

Clip-on

2 mA/mVor 10 mA/mV

Tektronix Type P6019

current probe

with passive terminator

Recessed Probe

Tektronix

Tip

Unwrapping tool

Gardner-Denver
505-244-475

Wire-Wrap Tool

Gardner-Denver
A-20557-29

30 gauge bit for
wrap tool

Gardner-Denver
504221

Sleeve for 30

Gardner-Denver
500350

gauge bit

5-1

Table 5-1

Maintenance Equiprrfent (Cont)

Equipment

Specifications

Equivalent

Spray paint

Krylon 1501
Glossy white

Spray paint

DEC black

Module Extender (2)

DEC No. W982

Jumper Wires

Assorted lengths
affixed with 30 gauge

termi-ppint connectors

Table 5-2

Maintenance Programs*

Program Name

DEC No.

Use

Mcindec 8I-D01B

Tests And, Tad, and operate Instructions only

Instruction Test 2

Maindec 8I-D02B

Extensive test of Auto index, indirect address
and the DC A instruction

Instruction Test 2B

Maindec 08-D02A

Tests 2's add and rotate logic

Random Jmp Test

Maindec 08-D04B

Extensive test of Jmp instruction

Random Jmp-Jms Test

Maindec 08-D05B

Extensive test of Jms instruction

Random ISZ Test

Maindec 08-D07B

Extensive test of ISZ instruction

Memory Checkerboard

Maindec 08- DUO

Tests memory circuits susceptibility to noise

Memory Address Test

Maindec 08-D1B0

Tests address selection logic

Memory Power
On/Off Test

Maindec 08-DlAB

Test ability to retain memory information during

Instruction Test

loss of power

^'Programs are subject to change

5-2

5.3

PREVENTIVE MAINTENANCE

5,3.2 Preventive Maintenance Tasks

A systematic preventive maintenance program
can be a useful deterrant against system failures.
Proper application of such a program is an aid to
both serviceman and user, since detection and
prevention of probable failures can reduce main-

The following tasks should be performed on at
least a three month's schedule.

tenance and downtime to a minimum.

Clean the exterior and interior of the equipment cabinet using a vacuum cleaner and/or
cloths moistened in nonflammable solvent.

Clean the air filter by removing the retaining bar and machine screw. Use a vacuum
cleaner to remove accumulated dirt and dust.
Replace filter in the PDP-8/I.

Scheduling of computer usage should always include time set aside for maintenance purposes.
Careful diagnostic testing can make evident

problems which may only occur intermittently
during on-line operation.

Lubricate hinges, slide mechanisms, and

We suggest weekly program checks and thorough

casters, with a light machine oil.

preventive maintenance on the following criteria:

excess oil,
Visually inspect equipment for general
Repaint any scratched areas with

1000-hours - electrical

d .

500-hours - mechanical

condition.

DEC black paint or Krylon glossy white
No. 1501.

or at least every three months

5.3.1

Wipe off

e. Inspect all wiring and cables for cuts,
breaks, fraying, wear, deterioration, kinks,

Weekly Checks

Time should be scheduled each week to operate
the MAIN DEC programs. Run each program
listed in Table 5-2 for at least five minutes. Take
any corrective action necessary at this time and
record the results in the log book.

strains,

and mechanical security.

Tape, solder,

or replace any defective wiring or cable cover-

ing.

Inspect the following for mechanical secu-

maintained on a weekly basis.

keys, switches, control knobs, lamps,
connectors, transformers, fans, capacitors, etc.
Tighten or replace as required.

Many hours of computer downtime can be avoided

by rigid adherence to a schedule based on the
condition of the air filter. A dirty filter can
cause machine failure through overheating which

sure that each module is securely seated in its

has a number of bad effects.

improper air filter servicing.

The frequency of this practice depends upon system environment and usage. The condition of the
air filter should be checked every week. After
several weeks the frequency of cleansing for the
particular environment will be determined. The
procedure for filter cleansing is described under

rity:

External cleanliness of the system should also be

Preventive Maintenance Tasks.

5-3

Inspect all module mounting panels to en-

connector. Reropve and clean any module
which may have collected dirt or dust due to

Inspect power supply components for leaky

capacitors, overheated resistors, etc.

Replace

any defective components.
i

Check the output voltage and ripple content

of the H704 power supply as specified in Table
5-3. Use a multimeter to make these measure-

ments without disconnecting the load.

Use an

are not adjustable; therefore,

and a multimeter. The best corrective maintenance tool is a thorough understanding of the
physical and electrical characteristics of the
equipment. Persons responsible for maintenance

maintenance should be performed.

of specific module circuits, and the location of

oscilloscope to measure p-p ripple on all dc
outputs of the supply. The outputs of the supply

if any output voltage or ripple content is not within specifications should become thoroughly familiar with the systhe supply is considered defective and corrective tem concept, the logic drawings, the operation

mechanical and electrical components.
Table 5-3
Type H704 Power Supply Outputs

It is

virtually impossible to outline any specific

procedures for locating faults within complex
digital systems such as the

PDP-8/l.

However,

diagnosis and remedial action for a fault condi-

Nominal
Output dc

Output

Maximum

Max P-P

tion can be undertaken logically, and system-

Voltage

Output

atically in the following phases:

Voltage

Range

Current

Ripple

+5V

±5%

10 amp

50 mV

a.
b.

System Troubleshooting

+ 15V

± 10%
± 15%

5 amp
5 amp
6 amp

unfiltered

Logic Troubleshooting

350 mV
700 mV

Circuit Troubleshooting

-15V
-30V

Run all

±10%

Repairs and Replacement

Validation Tests

Recording

MAIN DEC programs to verify pro-

per equipment operation. Each program should
be allowed to run for at least 10 minutes.
k.

Preliminary Investigation

Perform all preventive maintenance opera-

tions for each peripheral device included in

the system

5.4.1

Preliminary Investigation

Before commencing troubleshooting procedures,
explore every possible source of information.

Think over the problem before attempting to
troubleshoot the system.

Enter preventive maintenance results in the

log book

Gather all available
information from those users who have encount-

ered the problem and check the System log book
for any previous references to the problem.

5.4 CORRECTIVE MAINTENANCE
The PDP-8/I is constructed of highly reliable
TTL M-series modules. Use of these circuits

Do not attempt to troubleshoot by use of complex
system programs alone. Run the MAINDEC programs and select the shortest, simplest program
available which exhibits the error conditions.

with faithful performance of the preventive main-

MAINDEC programs are carefully written to

tenance tasks ensures relatively little equipment

include program loops for assistance in system
downtime due to failure. Should a malfunction
and logic troubleshooting.
occur, maintenance personnel should analyze
the condition and correct it as indicated in the
following procedures. Neither special test equip- 5.4.2 System
Troubleshoot "9
~
"
ment nor special tools are required for corrective
maintenance other than a broad-bandwidth oscil- Once the problem is understood
and the proper
loscope, a Tektronix Type P6019 current probe.
program is selected, the logical section of the

5-4

system at fault should be determined. Obviously, There ore several terminals which must be tied
to either ground or +3V when prewired options
the program which has been selected gives a
are not installed. Refer to engineering specifireasonable Idea of what section of the system is
cations (Drawing A-SP-8I-0-23) for the locations
failing. However, faults in equipment which
of these temporary jumpers.

transmit or receive information, or improper
connection of the system, frequently give indi-

cations similar to those caused by computer mal-

functions.

5.4.4 Circuit Troubleshooting

Disconnect any peripheral devices which are not
necessary to operate the failing program.

Engineering schematic diagrams of each module
are supplied with each PDP-8/l system and
should be referred to for detailed circuit information. Copies of engineering schematic dia-

At this time, reduce the program to its simplest
scope loop and duplicate this loop in a dissimilar
grams are contained In Volume II.
portion of memory to verify, for instance, thaJ- an
operation failure is not dependent upon memory
Visually Inspect the module on both the compolocation. This process can aid in distinguishing
of
failures.
Use
nent side and the printed wiring side to check for
processor
from
failures
memory
overheated or broken components or etch. If this
the techniques described above often pinpoints
inspection fails to reveal the cause of trouble or
the problem to a few modules.
to confirm a fault condition observed, use the
multimeter to measure resistances.

5.4.3

Logic Troubleshooting

CAUTION
Before attempting to troubleshoot the logic, make
sure that proper and calibrated test equipment is
available. Always calibrate the vertical preamp

and probes of an oscilloscope before using. Make
sure the oscilloscope has a good ac ground and
keep the dc ground from the probe as short as

Do not use the lowest or highest resistance
ranges of the multimeter when checking
semiconductor devices. The XlO range Is
suggested.

Failure to heed this warning

may result in damage to components.

possible.

Measure the forward and reverse resistances of
diodes. Diodes should measure approximately
Use the oscilloscope to trace signal flow through
20 Q forward and more than lOOOQ reverse. If
sweep
Oscilloscope
element.
the suspected logic
can be synchronized by control pulses or by level readings in each direction are the same and no
parallel paths exist, replace the diode.
transitions which are available on individual
logic.
side
of
the
module terminals at the wiring
Care should be exercised when probing the logic, Measure the emitter-collector, collector-base,
and emitter-base resistances of transistors In both
to prevent shorting between pins. Shorting of
result
in
directions. Short circuits between collector and
can
signal pins to power supply pins
emitter or an open circuit In the base-emitter
damaged components.
path cause most failures. A good transistor indiheld
at
are
cates an open circuit In both directions between
Within modules, unused gate inputs
collector and emitter. Normally 50 to lOOQ
+3V. This voltage Is introduced from pin Ul or
numThe
or
M617.
exist between the emitter and the base, or beMl
Mils,
17,
VI of modules
tween the collector and the base in the forward
ber in parenthesis beside each +3V input repredirection, and an open circuit condition exists
sents the wiring run number for that +3V line.
loads.
of
15
maximum
in the reverse direction. To determine forward
Each line can handle a

5-5

and reverse directions, consider a fransisfor as
two diodes connected back to back . In this
analogy, PNP transistors would have both cathodes connected together to form the base, and
both the emitter and collector would assume the
function of an anode. In NPN transistors the
base would be a common-anode connection; and
both the emitter and collector, the cathode.

Use a heat sink, such as a pair of pliers, to

grip the lead between the joint and device being

soldered.

Multimeter polarity must be checked before measuring resistance, since many meters apply a posE3

itive voltage to the common lead when in the

resistance

mode.

Since IC's contain complex integrated circuits
with only the input, output, and power terminals

available, static multimeter testing is limited to
continuity checks for shorts between terminals.
E6

IC checking is best done under dynamic conditions

using a module extender to make terminals readily

Using PDP-8/I logic diagrams and
M-series module schematics, you may locate an

accessible.

-1

IC on a circuit board as follows.
E2

Hold the module with the handle in your

left hand;

component side facing you.
E3

IC's are

The numbers increase toward the handle.

numbered starting af the contact
side of the board; upper right hand corner.

Figure 5-1

IC Location

d. When a row is complete, the next IC is
located in the next row at the contact end
of the board. (See Figure 5-1)
e.

The pins on each IC are located as Figure

5-2 illustrates.
14

n n n n n n n
5.4,5

Repairs and Replacement

When soldering semiconductor devices (transistor,
diodes, rectifiers or Integrated circuits) which

may be damaged by heat, physical shock, or

o
u1.2345
u u u u u67u

excessive electrical current, take the following
Figure 5-2

special precautions.

5-6

IC Pin Location

Use a 6V iron with an isolation transformer.
Use the smallest iron adequate for the work.

ful not to expose

painted or plastic surfaces to

this solvent.

Use of an iron without an isolation transformer

may result In excessive voltages presented at
the iron tip.

5.4.6 Validation Tests

Perform the soldering operation in the
shortest possible time to prevent damage to the

Always return repaired modules to the location
from which they were taken. If a defective module is replaced by a new one while repairs are
being made; tag the defective module noting the
location from which it was taken, and the nature
of the failure. When repairs are completed, return the repaired module to its original location
and ascertain that the repairs have resolved the

component and delamination of the module
etched wiring
d. IC's may be easily removed by using a solder puller to remove all excessive solder from
contacts and then by straightening the leads,
the IC from Its terminal points. If it is not
desirable to save the defective IC for test pur-

problem.

poses, then the terminals may be cut at the
IC body and each terminal removed from the

To confirm that repairs have been completed, run
all tests which originally exhibited the problem.
If modules have been moved during the troubleshooting period, return all modules to their orig-

lift

board individually.

inal positions before running the validation tests.

CAUTION
5.4.7 Recording

Never attempt to remove solder from terminal points by heating and rapping module against another surface.

A log book is supplied with each PDP-8/I system.

This practice

Corrective maintenance is not complete until all
activities are recorded in the log book. Record
all data indicating the symptoms given by the

can result In module or component damage.
Always remove solder by the use of a solder-sucking tool

compowould
be
nent at fault, and any comments which
helpful in maintaining the equipment in the future

fault, the method of fault detection, the

When removing any part of the equipment for
repair and replacement, make sure that all leads
or wires which are unsoldered, or otherwise dis-

The log should be maintained on a daily basis,
recording all operator usage and preventive

maintenance results.

connected, are legibly tagged or marked for
identification with their respective terminals.

Replace defective component only with parts of
equal or better quality and equal tolerance.

and unsoldering operations in the
repair and replacement of parts, avoid placing
excessive solder or flux on adjacent parts or
service lines. When repair has been completed,
remove all excess flux by washing junctions with
In all soldering

a solvent such as trichlorethylene.

Be very care-

5-7

NOTE
The measurements and adjustments made in
the following paragraphs are analog in nature, and are not of the QN-OFF, HI-LO
nature .

These represent tuned sections of

the machine that must be properly aligned

by qualified personnel

5.5

ADJUSTMENTS

5.5.2 Memory Alignment Procedure

Adjustments of the PDP-8/I should never be underit has been confirmed that a failure is
due to circuit aging or misalignment rather than
a component failure. Replacement of certain
components or removal of an excessive environment may eliminate the need for adjustment.

taken until

5.5.1

To adjust or check the memory currents, the
PDP-8/I should be a lowed to warm up for approximately one hour before measurements are
made. In addition, the measurements should be
performed at an ambient temperature of 25°C.
I

The G826 negative regulator control module at
location AB2 and the G805 negative regulator
moduleat location API control the memory voltage regulation, and therefore control the mem-

Power-Up Threshold Adjustment

This adjustment is preset at the factory and should

ory currents.

only be attempted in the field by personnel train-

ed in this skill

The voltage difference between MEMORY
SUPPLY + and MEMORY SUPPLY -provides the
read/write, and inhibit current through the

The G826 Negative Regulator Control module
contains a difference amplifier that compares the
+5V supply voltage with an adjustable reference
threshold voltage. The threshold reference is

memory stack.

properly set when the voltage at test point A2U2

changes from a low voltage (-6V]I to a higher
voltage (-2V) as the +5V supply voltage passes
through4. 75V after turn-on. Thethreshold voltage is adjusted by the G826 variable resistor
R2, 1000 Q and performs several functions.

When the +5V supply voltage is less than this
threshold, the regulated memory supply voltage
is

held off. This threshold also controls various

logic signals to the central processor by initiat ing

POWER OK and a power failure level SHUT

The negative regulator control (G826) serves to
vary the G805 regu lator for temperature variations

by a thermistor and difference amplifier tracking
circuit which compares the regulated memory
voltage to an adjustable reference. A trimpot
(R28, 2000 Q) located on theG826 module varies
this reference voltage, and therefore, varies
the memory currents.

Adjustment of the trimpot varies the MEMORY
SUPPLY + voltage between approximately -IV
and -12V; the subsequent variation of the regulated memory supply voltage should be between
-18V and -29V. Normally, the regulated memory voltage should be set to approximately -22.5V,
measured with a multimeter across MEMORY

DOWN; a STOP OK level from the processor
allows a shut down of the memory supply voltage

SUPPLY + and MEMORY SUPPLY-.

when the +5V supply voltage fai ls. Asthethres -

If the voltage can be adjusted but not to the
above value, thethermistoracross the regulator
control (pins B2R2 and B2S2) should be investigated The thermistor is located within the memory stack and outputs on the inhibit connector
card (pins B35S2 andB35T2); its resistance should
be 330 Q ± 10% at 25''C. Shunting resistance
in the regulator control would reduce this value
if a measurement is made with the modules con-

hold is reached during turn-on , POWER CLEAR

produces a pulse to ground and then retu rns to a
high level
Also, with these c onditions, POW ER
OK is a low logic level , and SHUT
is a
.

DOWN

The inverse of these levels
should exist before the threshold is reached. The
high logic level.

STOP OK level originates from the central processorand its undriven input should remain high,
having no effect during alignment.
5-8

nected.

no voltage adjustment Is possible, either the
Negative Regulator (G805) or the Regulator
Control (G826) can be at fault.

The absence of such a variation in-

justing R28.

dicates a falling regulator control and the need
for replacement.

Variation suggests a failed

Negative Regulator (G805).
In alignment of the memory, the actual outputs

Removal of the Negative Regulator allows a
separate test of the Regulator Control and, there- of the various memory control flip-flops should
fore, a determination of which module has failed, be checked against those of Figure 5-3.

With the Negative Regulator (G805 at 81) removed and a stack with Its associated thermistor
present, the regulator control output (pin B2R2)

can be varied between ground and -13V by ad-

approximate initial STROBE adjustment can be
such that its leading edge occurs 500 ns after the
leading edge of MEM START. The width of the
strobe signal should be less than or equal to 80ns

POWER CLEAR
MEM START

SIGNAL FROM PROCESSOR, RESET BY STROBE

MEM ENABLE

EAO (0) AND EAt (0) ARE HIGH FOR ENABLING
OF THE INTERNAL MEMORY

(!) IS LOW FOR SELECTION OF FIELD 0,
AND HIGH FOR SELECTION OF FIELD

EA2

FIELD

OZjls

7jjLS

•- LESS THAN 0.08ms

EITHER STROBE FIELD
OR STROBE FIELD
SIGNAL, OTHER SIGNAL LOW

STROBE FIELD

MEM BEGIN

^O.Sms
CORE

(1)

CLEARED BY MEM BEGIN AND SET BY STROBE

SENSE FF'S

FIELD TO CORE OUTPUT DATA

CORE

STROBE

(TP

(0)

SIGNAL TO CENTRAL PROCESSOR

)

l_
0,9>is

1.4 5J1S

WRITE

SIGNAL OCCURS 0.05^.5 AFTER INHIBIT

0.95m

I.45J1S

MEM DONE

SIGN AL TO CENTRAL PROCESSOR

OOms

NOTE

0.5>is

1.0p.s

1.5ms

TRANSITION TIMES ARE MEASURED FROM THE POSITIVE TRANSITION OF MEM START
AND ARE APPROXIMATE.

Figure 5-3

Memory Control Waveforms
5-9

and have an approximate adjustment range for its
leading edge from MEM START from 350 ns to
650 ns. A clockwise rotation of the adjustment
on the variable delay line (M360 at B23) increases this delay. The final adjustment of
strobe must be made in relation to the analog
data signal from core memory.

loops at the SOURCE and RETURN signals. The

current waveforms are similarto those of Figure

5-4 which represents the equal amplitude read/
write currents measured on the memory stack in-

When running a multiple-selection program,
such as MEMORY CHECKERBOARD, the waveput.

forms differ in the amplitudes of the read/write
currents due to the contribution of the base cur-

The R/W selector switches are examined by inspecting the current waveforms on the current

rents to the emitter currents of the address de-

coding and selection switches.

MEM START
0.7;lt

O.iixt

r
320 ma

READ
O.SSjis

•

-J—

ZOma

O.Ziis

NORMAL READ/WRITE
CURRENT WAVEFORM

JZOma

t.l5M>

45m«

OPEN DIODE, BAD R/W SWITCH

SHORTED DIODE

ABNORMAL READ/WRITE
CURRENT WAVEFORMS

Figure 5-4

(BOTH WAVEFORMS MAY ALSO BE NEGATIVE)

Representative Read/Write Current

Waveforms

5-10

The additional current (approximately 30 mA)
appears on the retur n current through th e R/W
selection switches to

MEMORY SUPPLY-

analyze the read/write currents for individual
addresses, the following program may be used:

De-

pending upon the loop examined, it is sometimes
additional read current and sometimes additional

0000
0001

DCA Temp

write current.

0002
0003
0004

TAD I Temp
J MP Beg

This difference in current should

not be confused with amplitude variations within

the read/write current due to bad address decod-

Beg,

7604
3004

LAS

1404

5000
0000

Temp,

ing selection switches; these differences are also

apparent at the memory stack inputs and vary with The read/write currents for individual addresses
may be examined by setting the desired address
different addresses. The current loops, provided
for use with a Tektronix type P6019 current probe, into the switch register. Of course, since the
currents for all memory addresses pass through
are as follows.
the common test point, you will also be examining the currents for those locations which the
X Source
C38T2 to C39K1
test program occupies. You must first ascertain
Y Source
C33T2 to C39S1
that the currents are proper for those addresses
X Return
D33T2 to D39K1
within
the program; if not, relocate the program
Y Return
D38T2 to D39S1
to some other area of memory. By selecting individual
addresses via the switch register, waveloops
has
the
at
these
Examination of the current
form deformities may be traced to defective asadvantage that the currents for all memory adsociated R/W switches.
dresses pass through these common points The
.

waveshape should be inspected on each of the
four loops to check that no leakage to ground
exists between the voltages, MEMORY SUPPLY
+ and MEMORY SUPPLY -.

If the

improper waveform remains fixed to a spe-

cific address and replacement of the associated

R//7 switch does not correct the problem; then,
the logic signal inputs from the memory address

The regulated memory voltage was previously
adjusted in a static condition for -22.5V; there
should be no change although the memory Is now
cycling. The resultant stack current should be
approximately 320 mA (this value varies with
stack vendors, and is best determined by adequate core output with minimum noise). The
lower read/write current amplitudes on the current amplitudes on the current loops equal the
current amplitudes in the stack windings; the
current measurements can conveniently be made
here. Correlation between the voltage and
current should exist. Variations in current amplitude at successive addresses should be less than

20 mA.

Failure of the R/W selection switches is

indicated by the lack of proper read/write currents of any address.

If all

of the

R/W selection

switches appear to have failed, inspection should

be made at the Input logic signals, READ (1) and
WRITE (1), and the input supply voltages. To

(MA) register should be inspected.

those sig-

nals are correct and vary according to the selec-

ted address, attention should be turned to the

memory stack with its attendant Diode Selection
Matrices

The Diode Selection Matrices (G611 and G610)
sandwich the memory planes of ferrite cores between them. Also connected to this unit are two
W025 cable connectors, one for the inhibit inputs,
the other for the SENSE outputs.

The X-axis Diode Selection Matrix (D-BS-8I-0-15)
has half its diodes on the G610 board and half on
the G611 board; the same is true of the Y-axis
Diode Selection Matrix (D-BS-8I-0-16). The
inductor symbol connecting the centers of the two
sets of diodes represents the stack winding traversing the 12 core planes. The windings are identified on the Diode Matrix Selection boards as X,
0-64 and X. 0-64 for the X-axis windings and Y,

5-n

0-64 and Y. 0-64 for the Y-axis windings. Sus-

is used in machines which have a basic 4K mempected opens and shorts in the windings, detected ory; when an additional 4K memory is added,
during dynamic tests, should be verified by meas- this module is replaced with a G021 which prourements across these points with an ohmmeter.
vides an additional amplifier input (Drawing BSThe resistance of the read/write winding is 3.5 Q 81-0-14). The sense windings for each bit enter
±10%. The forward and reverse resistance of the a differential amplifier with a threshold voltage
diodes in the matrix should also be checked when established as a function of the fixed SLICE voladdress selection failures are attributed to stack
tage. The test points (pins El and K2) after the
failures. Drawing D-CS-3005256-D-3 correlates amplifiers allow observation of the waveforms
for comparison with those of Figure 5-6. The
the memory diode location and function.
preliminary setting of STROBE should now be
modified as a function of the data output from
CAUTION
core memory
The memory stack is expensive and fragile;
it is easily damaged and must be handled
The strobe leading edge is set approximately at
with care.
the center or Just past the midpoint of the amplifier "one" output. This adjustment should be
Twelve inhibit drivers are associated with each
late enough to sense all "one" data with normal
memory stack. To inspect the Inhibit currents,
variations in delay, and yet centered in the
you will need two module extender boards (W998) "zero" data output. Each sense amplifier test
at AB35. These extender boards provide current
point should be examined and the final adjustloops for each of the 12 inhibit lines.
Inhibit
ment of the strobe signal should be made using
current should be inspected and compared with
the most sensitive sense amplifier as a criteria.
the waveform in Figure 5-5. Inhibit current
amplitude Is approximately 290 mA as noted;
The lack of proper waveforms at all addresses
more important, however, is the ratio of Inhibit
indicates that the sense amplifier or the core
to read/write currents. This ratio is 0.85 of
winding Is in error. The sense amplifier may be
the read/write current and should exist regardchecked by exchanging a known good amplifier
less of the read/write current amplitude. Failure
with the suspected one
The absence of an input
signal indicates the stack sense winding should
of a specific inhibit driver can be determined by
movement of the syspected driver to another lobe checked or the sense connector (W025 at
.

cation.

Movement of the failure indicated that

the module should be repaired or replaced.

movement of the failure indicates that either the
input signals or output load is causing the failure.

34AB) for a resistance of 21 Q ±10%.
Testing and adjustment of the memory section of
the PDP-8/I is now completed by running the

memory address test and memory checkerboard
test (worst pattern).

Final adjustment of the read/

The logic inputs, B INHIBIT and B FIELD (0),
from the memory control; the connection through
the current limiting resistor; and the memory buffer signals should be checked. If the stack is
suspected, the specific winding should be meas-

write current

ured for a resistance of 14Q

5.6 ASR33 TELEPRINTER AND CONTROL

±10%.

may be necessary to Increase or

decrease the amplitude of the core input and
corresponding noistf.

MAINTENANCE
Twelve sense amplifiers (G020 or G021) are
associated with each memory stack; each amplifier transforms the analog pulse output of ferrite

core to a usable logic level.

The G020 module

This section contains information pertinent to the

maintenance of the ASR33 and its associated
control logic.

5-12

MEM START
0.0m«
1.45;i5

290ma

BAD TRANSFORMER, OPEN DIODE

OPEN WINDING

0.90M8

NORMAL INHIBIT
CURRENT WAVEFORM

Figure 5-5

ABNORMAL INHIBIT
CURRENT WAVEFORM

Representative Inhibit Current

Waveforms

READ (I

)

J
0.0>i8

< 6mV

CORE OUTPUT
(PINS D2,E2 a LI, Ml)

0.26ms

O.S6>is

0.38 >LS

AMPLIFIER
OUTPUTS

'JWVm''^'''^

(PINS El a K2I

0.26>iS

< 80ns

<80r)8

STROBE FIELD
(PIN 01

SENSE FLIP-FLOP
(PINS Al a U2)

CLEARED BY

MEM BEGIN

NOTE

CORE OUTPUTS ARE OBSERVED DIFFERENTIALLY AT THE PINS NOTED.

Figure 5-6

Representative Sense Amplifier

Waveforms
5-13

5.6.1

5.6.2

Equipment

Programs

Table 5-4 lists the special tools needed for main- Table 5-5 lists the maintenance programs supplied
tenance of the ASR33 teleprinter. All of these
by DEC for aid in maintaining the ASR33 and
items can be obtained from Digital Equipment
associated control logic.
Corporation or from the Teletype Corporation.

Table 5-4

5.6.3

Preventive Maintenance

Teletype Maintenance Tools

Teletype preventive maintenance is scheduled on
Item

8 oz. scale
32 oz. scale
64 oz. scale
Set of gauges
Offset screwdriver
Offset screwdriver

Handwheel
Handwheel adaptor
Contact adjustment tool

Gauge
Gauge
Gauge
Bending Tool
Extractor

Tweezer
Spring hook (push)
Spring hook (pull)

Screw holder

Part No.

the same frequency as discussed in Section 5.4.

110443
110444
82711
117781

CAUTION
Do not use alcohol , mineral spirits, or
other solvents to clean plastic parts with

94644
94645
161430
181465
172060
180587
180588
183103
180993
182697
151392
142555
142554
151384

protective decorative finishes.

Normally,

a soft, dry cloth should be used to remove
dust, oil, grease, or otherwise clean parts
or subassemblies.

To clean plastic surfaces, we recommend using
any of several household cleaner-waxer liquids
such as "Jubilee" or "Jato". To clean the
printer platen, we recommend using a lacquer

thinner.

During a overhaul, subassemblies and metal parts
can be cleaned in a bath of trichlorethylene.
Proper lubrication should be performed often.

Table 5-5
Teleprinter Maintenance Programs
Program Name

DEC No.

Use

Reader Test

Maindec-8I-D2PB

Function test and exerciser for ASR33/35
Teletype paper tape reader

Punch Test

Mamdec-8I-D2QB

Function test and exerciser for ASR33/35

Teletype paper tape punch

Keyboard Test

Maindec-8I-D2RB

Combination Test

Maindec-8I-D2TB

Function test and exerciser for ASR33/35
Teletype keyboard
Exerciser program used to test ASR33/35
printer and punch simultaneously

5-14

Brush Holder

Weekly Tasks

574-122- 700 Page 15

(Distributor)

a. Inspect platen and paper guides.
clean, using a soft, dry cloth.

Wipe

Carriage Drive Bail
Print Trip Lever

574-122- 700 Pages 16-24
574-122- 700 Pages 30-34
574-122- 700 Page 35
574-122- 700 Page 37
574-122- 700 Page 43
574-122- 700 Page 44
574-122- 700 Pages 61-62

Dashpot

574-122- 700 Page 78

Final Printing

574-122-700 Page 85

Clutches

Code Bar Reset
Print Suppression

Clean external areas of paper tape punch

Blocking Levers
Print Suppression

and reader, using a soft brush or cloth.
c.

Remove and empty paper tape punch chad

box.
Run teleprinter combination test (Maindec8I-D2TB) for approximately 15 min.

Alignment
Line Feed
Keyboard Trip

574-122-700 Page 89-95
574-122-700 Page 141

Lever

Reader Trip Lever
Detent Lever

574-124-700 Pages 6-9

Inspect platen and paper guides. Clean
platen, using a lacquer thinner to remove shiny

Sensing Pin
Tape Lid Latch

574-124-700 Page 15

snjrface

Handle
Feed Pawl

Preventive Maintenance Tasks

Clean ribbon guides and replace ribbon, if

Registration

574-12^700 Page 10
574-124-700 Page 18
574-125-700 Page 11
574-125-700 Page 12

necessary.

fects; loose nuts, screws, retaining clips, etc.

Run each of the teletype Maindec Programs
for at least two passes each

Remove distributor rotor and clean disk surface, using cotton swab moistened in "freon"

cleanly.

Remove cover and check for vibration ef-

Check that tape holes are being punched

or "trichlorethylene."

e. Check selector magnet coil for signs of
overheating.

Clean between selector magnet pole piece
and armature with bond paper to remove any

lubricant or dirt.

5.6.4 Corrective Maintenance
Figure 5-7 is a simplified drawing of the control
circuits for the ASR33 Teleprinter. Details of
the cable connector are included to show how a
teleprinter is modified to operate with the PDP-

8/1.

g. Clean and lubricate teletype as per Teletype Bulletin 273B. Follow instructions literally so as not to over lubricate.

During off-line operation, the keyboard

distributor effectively drives the printer selector

magnet. This means that any character received
from the keyboard or paper tape reader is automatical ly reproduced on the printer and paper
.tape punch. During on-line operation, this conh. The following adjustments should be checked
receiver (M706)
Bulletin 273B, Volume 2. tinuity is broken and a teletype
Pages indicated are in

Trip Shaft
Trip Lever

574-122-700 Page 13
574-122-700 Page 14

is used to accept the input from the reader or
keyboard while a teletype transmitter (M707) is
used to drive the printer and paper tape punch

5-15

TTY TRANSMITTER
M707

TTY RECEIVER

TTI CLOCK

CLOCK
M4S2

M706

EV2

FM2

EU2

~:^
TTO CLOCK

TTY OUTPUT

rASR33

TTY

TELETYPE CONNECTOR
^ -' W07S

KEYBOARD
DISTRIBUTOR

SELECTOR
MAGNET
DRIVER
"1
_^

i
1*

(
I-

-o~\

R4
•

^A/V-

—

^e^

311

5« 6n

MAGNET

TTY INPUT
B

n I

-^
B

SELECTOI

—M-

-15V O-

I
~°

CABLE

H
J
}%'.'

Figure 5-7

Teletype Connections

POWER
LI
SWITCH LZ
a RVR SOLENOID

I
—

/„>
I

4915
READER CONTROL

The clock (M452) develops a TTI clock (880 HZ)
and a
clock (220 HZ).

Printer/punch problems can sometimes be isolated
by comparing the printed character with the out-

put of the paper tape punch . If the printed character agrees with the punch output, and both are

These clocks are used to shift the bits through
Adjustment

the transmitter and receiver buffers.

incorrect then, the problem lies in the selector

made by viewing the TTO clock output with
the oscilloscope probe on F3K2 and adjusting the
Most teletype problems can be traced to one of

mechanism or in the TTY transmitter module
(M707). If the printed character and the paper
tape punch output disagree, and the paper tape
punch output is correct then, the problem lies

four areas:

within the printer assembly.

trimpot for a 4.5 ms to 4.6 ms repetition rate.

Figure 5-8 shows the teletype signal produced at

ASR33 keyboard or reader
b. ASR33 printer or punch

c.
d.

pin EV2 while transmitting from the computer and

M706 receiver

also at FM2 when recelvjng information from the

M707 transmitter

teletype.

POP 8/1 ACC^UMULATOR
2

5-6

- '-"•' :^ ^ ^ /
3" ^ '4^ -^ 5/

_ 2

\
6

START

\"--^
"^7 "-,-.

+ 2.5 V

GND
I

UNIT

UNITUNIT

)

UNIT

UNITS

Figure 5-8

UN ITS OF TIME

Teletype Signal Waveform and Bit
Relationship for the Character "U"

Isolation of bit related problems is fairly simple.

Off-line duplication can usually determine
whether the problem is in the teleprinter or the
control logic. Steps may also be taken to isolate
the problem to subassemblies within the teleprinter. Picking up bits during a read operation
can be caused by a defect in any of three sets of
contacts which are tied in parallel. Reader,
keyboard, and answer-back contacts provide

5,7 SPARE PARTS
Each user of the PDP-8/I system should establish
a spare parts stock in accordance with the extent
of the available repair facilities. The following
considerations are helpful in determining what
spare parts should be stocked.
Teletype - Users who do not have maintenance

parallel inputs to the distributor contact disk.

personnel trained in the maintenance and repair

pick-up problems can be isolated to one of
these three areas by disengaging the related contact from the suspected contact set

of Teletype units should keep a complete Model

Bit

33 Automatic Send Receive Teletype near the
computer. If the on-line unit becomes defective.

5-17

subsHtute the spare to avoid computer down-time

Table 5-7 (Cont)

However, many users have facilities for the maintenance of Teletype units, in which case it is

Spore Module List

Name

suggested that spore parts be stocked as listed in

Table 5-6, and that one of each Teletype mainte-

Resistor Board

nance tool listed in Table 5-4 be stocked. All
of these items can be obtained from the Digital
Equipment Corporation, or from the Teletype

Negative Regulator
Regulator Control

Ten, 2- Input Nand

Corporation.

Eight, 3-Input Nand

Six, 4- Input Nand

Table 5-6
Spare Parts for Keyboard- Mode

Three, And/Nor
Expanders

ASR33 Teletype

Item

Part

Circuit Board

Tape Feed Sprocket

Lever, universal

Fuse (3.2 amp)

Distributor Brush

Beit Driven Gear

Drive Gear

Belt

Shaft

Bearing

No.

181821
183071

182240
120167
180979
181420
181411
181409
181007
181002

G624
G805
G826
Ml 13
Ml 15
Ml 17
Ml 60

Six Flip-Flops

Quantity

Type

Major Registers
Delay Line
Variable Delay
Variable Clock
Negative Input Converter
Six, 4- Input Power Nand
Negative Output Converter
Manual Timing Generator
Teletype Receiver
Teletype Transmitter

M216
M220
M310
M360
M452
M506
M617
M650
M700
M706
M707

Table 5-8

Recommended Spare Diodes
Modules And Components - All of the module

Code Number

Description

Quantity

11-00113
11-00114
11-02451
11-03183
11-03309
11-05275

D662
D664
1N753

MR2064

D671

2
10

types in the basic PDP-8/I are listed in Table 5-7
It is suggested that one module of each type be
stocked as a spare part, except for the Type

Ml 13, and Type M310 modules for which the suggested quantity is two each.

modules are to be
repaired at the installation site, reduce this list
of spare modules, and stock the components listed
in Tables 5-8 through 5-11.
If

10
2

D672
Table 5-9

Recommended Spare Transistors
Table 5-7
Spare Module

Name

List

Code Number

Description

Quantity

15-02155
15-02937
15-03100
15-03399
15-03409

DEC 1008-S
2N3568
DEC 3009B-S

5
10

DEC 3790-S

6534 D

Type

Sense Amplifier

G020

Memory Selector

G221

Inhibit Driver

G228

5-18

Table 5-10

The charts contain, reading left to right, the de-

Recommended Spare Integrated Circuits

sired function, the time period (per flow-diagram

notation) during which it occurs, the time state

Code Number

Description

19-05521
19-05547
19-05575
19-05576
19-05577
19-05578
19-05579
19-05580
19-05581
19-05582
19-05584

MC 1540G

signals which generate the primary signals,

SN7474
SN7400N
SN7410N
SN7420N
SN7430N
SN7440N
SN7450N
SN7460N
SN7453N
SN7482N

5
5

the engineering drawings upon which all signals

5.8

Quantity

(or pulse) during which it is implemented, the
primary signal(s) which perform the function, the

and

previously described are generated

The portion of the chart shown Table 5-12 repre-

2
5

sents the Tl portion of the FETCH cycle of a

typical memory reference instruction.

2
5

Function column, the notation MA+1 -PC

In the

indicates that during Tl the content of

MECHANIZATION CHARTS

This paragraph contains function mechanization

be incremented and transferred to the PC. This
is to be initiated during TSl and completed at
TPl . The sig nals required du ring TSl are MA
ENABLE and CARRY INSERT. MA EN ABLE is
generated on Drawing BS-8I-0-4, and CARRY
INSERT on Drawing BS-8I-0-5.

charts intended to serve both as a quick reference

table for the experienced technician and as a

MA ENABLE

troubleshooting analysis guide for less experienced

logic

maintenance personnel.

bined with the PC INCREMENT signal .
two signals are generated on Drawings BS-8I0-2 and -3 respectively.

generated by the output of the

side of the TSl flip-flop [TSl(l)]

comThese

The charts are designed to serve as a bridge between the functions specified on the flow diagrams
and those logic elements in the block schematics
CARRY INSERT is generated by the combination
by which the functions are implemented.
of TSl(l) and FETCH=0. These two signals are
Table 5-11

Spare Miscellaneous Components and Parts

Component
Delay Line
Pulse Transformer

Pulse Transformer

Rocker Switch
Rocker Switch
Rocker Handles
Indicator Bulbs

Power Lock Switch

*Must specify color

Code Number
16-05530
52-00672
52-02123
12-5375 (RS-9-3-FB)
12-5941 (RS-50-FB-PC)
12-5317*
12-5550 (2313)
34-4235

. . .

gray or orange

5-19

Description

L501

2037
2052

D501A

Quantity
1

5
5

4
4
4
6
1

The charts are so structured that the events of a
particular time state are fully explained before
spectively.
the description of the events governed by the
associated
time pulse is begun. The user, therecompleted
is
function
The implementation of this
fore, after examining all the time state events of
at TPl by the signal PC LOAD, generated on
Drawing BS-8I-0-6. PC LOAD is, in turn, gen- a particular function, should examine the time
erated by the combination of TPl and PC INCRE- pulse activities of that same function.
MENT. These two signals are generated on
Drawings BS-8I-0-2 and -5, respectively.
generated on Drawings BS-8I-0-2 and -3, re-

Table 5-12

Sample Mechanization Chart
State

Function

Time

Signal Required

Generated By

Drawing
Reference

Pulse

MA+1 -f C

TSl

MA ENABLE
TSl(l)

PC INCREMENT

CARRY INSERT
TSl(l)

FETCH=0

MA+1 -PC

TPl

PC LOAD
TPl

PC INCREMENT

BS-8I-0-4
BS-8I-0-2
BS-8I-0-5
BS-8I-0-5
BS-8I-0-2
BS-8I-0-3
BS-8I-&-6
BS-8I-0-2
BS-8I-0-5

Table 5-13
Fetch Cycle, AND, TAD, ISZ,

DC A, and JMS Instruction Mechanization Chart

State

Function

Time

Signal Required

Generated By

Drawing
Reference

Pulse

MA+1 -PC

TSl

MA ENABLE
TSl(l)

PC INCREMENT

CARRY INSERT
TSl(l)

FETCH=0

MA+1 -PC

TPl

PC INCREMENT

5-20

BS-8I-0-4
BS-8I-0-2
BS-8I-&-5
BS-8I-0-5
BS-8I-0-2
BS-8I-0-3
BS-8I-0-6
BS-8I-0-2
BS-8I-&-5

Table 5- 13 (Cont)
Fetch Cycle, AND, TAD, ISZ, DCA, and JMS Instruction Mechanization Chart

State

Function

Time

Generated By

Signal Required

Drawing
Reference

Pulse

MEM -MB

TS2

MEM ENABLE 0-4/S-n
TS2(1)

BS-8I-0-4
BS-8I-0-2

All of the following

NOT true:
KEY DP, DCA, JMS,
BREAK, EXECUTE

MEM -MB
MEM -IR

TP2

MB LOAD
TP2

BS-8I-0-2,3
BS-8I-a-6
BS-8I-0-2

Load Instruction
Register

TP2
B

TS3/

FETCH=1

BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

No Operations

TP3

MEMS- 11 -MAS- 11

TS4

MEM ENABLE S-11

INT OK

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-4
BS-8I-0-7

MEM ENABLE 0-4
MEM ENABLE 5-11

BS-8I-0-4
BS-8I-0-4
BS-8I-0-4

TS4(1)

ESET
PC ENABLE
MB04=1 then:

Address Current Page

MAO-4 -MAO-4

MA ENABLE 0-4

Address Page Zero

MB04=0 then:

MA ENABLE 0-4

-.MAa-4

not generated

Defer State entry

TS4

(cont'

(cont)

If
1

MB03=1 then:

-DEFER (enable)
B

FETCH (1)

lR0=0or IR1-0
MB03=1
Execute State entry

If
1

MB03=0 then:
-EXECUTE (enable)

JMP
B

FETCH=1

IR0=0or IR1=1

MBO=0

5-21

BS-8I-0-4
BS-8I-0-3
BS-8I-0-3
BS-8I-0-8
BS-8I-0-3
BS-8I-0-3
BS-8I-0-3
BS-8I-0-3
BS-8I-0-8

Table 5-13 (Cont)
Fetch Cycle, AND,

TAD, ISZ, DCA, and JMS InstrucHon Mechanization Chart
State

Function

Time

Signal Required

Generated By

Pulse

MEMS- 11 -MAS- 11

TP4

Drawing
Reference

MA LOAD
TP4
1

-DEFER (Set)

-EXECUTE (Set)

BS-8I-0-6
BS-8I-0-2
BS-8I-0-2

TP4

BS-8I-0-2
BS-8I-0-2

Table 5-14
Fetch Cycle, OPR Instruction Mechanization Chart
State

Function

Time

Signal Required

Generated By

MA+1 -PC

TSl/
TP1

MEM -MB
MEM -IR
No operation"
AC -AC

TS2/
TP2

TS3

Drawing
Reference

Pulse

Same as AND Instruction

Same as AND instruction

MBQ3=0 (OP1)

NOP
(MB04-0-MB06=0)

AC ENABLE
MB04:::MB06=0

BS-8I-0-4
BS-8I-0-5
BS-8I-0-8

OPl
MB06=1/MB04=0

BS-8I-0-4
BS-8I-0-5
BS-8I-0-3

OPl

Com plement AC

AC -AC

CMA
^B04=0-MB06=1)
AC ENABLE

-AC

CLA
(MB04=l-MB06-0)

NO OPERATION
5-22

Table 5-14 (Cont)
Fetch Cycle, OPR Instruction Mechanization Chart

State

Time

Function

Signal Required

Generated By

Drawing
Reference

Pulse

CLA/CMA

Set AC=-1

AC+AC -AC

(MB04=1-MB06=1)

AC ENABLE
OPl
MB04=MB06=1

BS-8I-0-4
BS-8I-0-5
BS-8I-0-8

OPl
MB06=1

BS-8I-0-4
BS-8I-0-4
BS-8I-0-8

MB05=MB07

BS-8I-0-4
BS-8I-0-8

AC ENABLE

AC+AC -AC

NOP

No operation
L -L

(MB05=0.MB07=O)
L ENABLE

CML

Complement the Link
L

(MB05-0.MB07=1)

-L

L ENABLE

Clear the Link

-L

T3
(cont)

TS3
(cont)

BS-8I-(>-4

OPl
MB07=1

BS-8I-0-5
BS-8I-0-8

OPl
MB05=MB07-1

BS-8I-0-4
BS-8I-0-5
BS-8I-0-8

OPl
MB07=1

BS-8I-0-4
BS-8I-0-5
BS-8I-0-8

CLL
(MB05=1-MB07=0)

No operation
Set Link to
+1

-L

CLL/CML
(MB05=1-MB07-1)
L ENABLE

CLLand STL

No Operation
AC -AC

I ENABLE

(MB08=0-MB09=0)

NO SHIFT
MB08=0
MB09-0

OPR
TS3 (1)

MB03=0
B FETCH (1)

5-23

BS-8I-0-5
BS-8I-&-8
BS-8I-0-8
BS-81-0-3
BS-8I-0-2
BS-8I-0-8
B$-9I-0-3

Table 5-14 (Cont)
Fetch Cycle, OPR Instruction Mechanization Gharf

State

Function

Time

Signal Required

Generated By

Reference

Pulse

RAR

•

Drawing

MB 10=0

Rotate AC and Link one

(MB08=1)

right

RIGHT SHIFT
MB08=1

MB 10=0
OPR
TS3

(1)

MB03=0
B FETCH (1)
RAL

(MB09=1)
LEFT SHIFT

Rotate AC and Link one

BS-8I-0-5
BS-8I-0-8
BS-8I-0-8
BS-8I-0-3
BS-8I-0-2
BS-8I-0-8
BS-8I-0-3

BS-8I-0-5

left

MB09=1

MB 10=0
OPR
TS3

(1)

MB03=0
B FETCH (1)
Rotate AC and Link
right two

T3
(cont)

TS3
(cont)

MB10=1
(MB08=1)

DOUBLE RIGHT ROTATE

BS-8I-0-5

MB08=1

BS-8I-(>-8

MB 10=1

BS-8I-0-8
BS-8I-0-5

OPRl
Rotate AC and Link

(MB09=1)

left tvyo

DOUBLE LEFT ROTATE
MB09=1

MB 10=1
OPR
TS3 (1)

MB08=0
B FETCH (1)
+1

-AC

MB04=MB06

-AC

BS-8I-0-5
BS-8I-0-8
BS-8I-0-8
BS-8I-0-3
BS-8I-0-2
BS-8I-0-8
BS-8I-0-3

(MB11=1)

AC ENABLE
+1

BS-8I-0-8
BS-8I-0-8
BS-8I-0-3
BS-8I-0-2
BS-8I-0-8
BS-8I-&-3

CARRY INSERT
OPl

MBn=l
5-24

BS-8I-0-4
BS-8I-0-8
BS-8I-0-5
BS-8I-0-5
BS-8I-0-8

Table 5-14 (Cont)
Fetch Cycle, OPR Instruction Mechanization Chart

State

Time

Function

Drawing
Signal Required

Generated By

Reference

Pulse

Skip on a zero AC

MB03=1 (OP2)

SZA
(MB06=1-AC=0)
-SKIP (Enable)

AC00=1
MB05=1

BS-8I-0-6
BS-8I-0-8
BS-8I-0-8
BS-8I-0-4
BS-8I-0-8
BS-8I-0-8

MB08=0
MB11=0
OP2
AC00=1
MB05=1

BS-8I-0-6
BS-8I-0-8
BS-8I-0-8
BS-8I-0-4
BS-8I-0-8
BS-8I-0-8

MB08=1
MB11=0

OP2

Si<ip on a

SNL

non-zero

(MB07=1-L=1)

Link

Skip unconditionally
1

-SKIP

T3
(cont)

-SKIP (Enable)

TS3

Reverse SKIP Sens

(cont)

(MB08=1)
1

-SKIP (Enable)

If combined with SMA,
SZA and SNL instructions.

MB11=1
MB08=1

the inverse occurs

OP2
AC/L Sense Out

.e .

SPA, SNA, and SZL
Halt operation

-RUN

HLT
(MB10=1)

-RUN (Enable)
MB 10=1
MB 11=0
OP2

No operation
AC -AC

BS-8I-0-6
BS-8I-0-8
BS-8I-0-8
BS-8I-0-4
BS-8I-0-6

BS-8I-0-2
BS-8I-0-8
BS-8I-0-8
BS-8I-0-4

NOP
(MB04==0-MB09=0)

AC ENABLE
MB04=0

AC -MQ ENABLE
MB03=1

OPR
TS3

(1)

B FETCH (1)

5-25

BS-8I-0-4
BS-8I-0-8
BS-KE8I-0-2
BS-8I-0-8
BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

Table 5-14 (Cont)
Fetch Cycle, OPR Instruction Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

AC+SR -AC

Drawing
Reference

OSR
(MB04=0.MB09=1)

AC ENABLE

BS-8I-0-4
(Same as NOP above)

AC+SR -AC

SR ENABLE

BS-8I-(>-4

OP2
MB09-1

MBn=0
-AC

BS-8I-0-4
BS-8I-0-8
BS-8I-0-8

CLA
(MB04=1-MB09=0)

No Operation
SR -AC

CLA/OSR
(MB04=1-MB09=1)
SR ENABLE

OP2
MB09=1

MB 11=0

NOP (MB04=0-MB06=0)
CMA (MB04=0-MB06=1)

TP3

BS-8I-0-4
BS-8I-0-4
BS-8I-0-8
BS-8I-0-8

MB03=0 (OPl)

AC LOAD

BS-8I-0-6

CLA (MB04=1 •MB06=0)
^J;^Y('^B04=1.MB06=1)

TP3

OPR

BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

AC LOAD

BS-8I-(>-6

B FETCH (1)

NOTE: No operations occur at TP3 of an Of 1
FETCH cycle for any combination of MB08,
MB09, or MBIO. These bits generate levels
which extend throughout T3.
+1

-AC

lAC

(MBn=l)

AC LOAD
TP3
B FETCH (1)

OPR
5-26

BS-8I-0-6
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

Table 5-14 (Cont)
Fetch Cycle, OPR InstrucHon MechanizaHon Chart

State

Function

Time

Signal Required

Generated By

Pulse

Reverse SKIP sens (MB08=0)

SZA(MB06=1 •AC=0)
SNA(MB05=1-AC00=1)
SNL(MB07=1-L=1)

-SKIP (strobe)

OPR

BS-8I-0-6
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

TP3

BS-8I-0-2
BS-8I-0-2

TP3
B FETCH (1)

HLT (MB10=1)

Halt Operation

-RUN (strobe)

-RUN

AC LOAD

NOP(MB04=0'MB09=0)
OSR(MB04-0-MB09=1)
CLA(MB04-1 •MB09=0)
5^':yMB04=1-MB09=l)

PC ->MA

Drawing
Reference

BS-8I-0-6

TP3

TS4

BS-8I-0-2

B FETCH (1)

BS-8I-(>-3

OPR

BS-8I-(>-3

TS4(1)
F SET

BS-8I-0-4
BS-8I-0-2
BS-8I-&-3

BRK REQ and

(SKIP=0) then:

PC ENABLE

PC+1

-MA

(SKIP=1)

PC ENABLE
TS4 (1)

FSET
PC +1

-MA

CARRY INSERT
SKIP=1

PC ENABLE
Fetch State entry

-F

SET (Enable)

DSET
E

SET

BREAK OK
SPECIAL CYCLE

5-27

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-5
BS-8I-&-6
BS-8I-0-4

BS-8I-0-3
BS-8I-0-3
BS-8I-0-3
BS-8I-&-3
BS-8I-0-3

Table 5-14 (Cont)
Fetch Cycle, OPR Instruction Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

PC -MA
PC+1

TP4

-MA

BRK REQ and
SKIP = or
SKIP = 1 then:

MA LOAD
TP4

DATA ADD -MA

Drawing
Reference

TS4

there is a

DATA BRK

REQ then:
DATA ENABLE
TS4 (1)

BREAK OK
TP4

Break State entry

BS-8I-&-6
BS-8I-0-2

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

cycle DATA BREAK

then:
1

-B
TP4

BSET
Word Count State
entry

T4
(cont)

TP4

(cont)

then:
1

3 cycle

DATA BREAK

-WC

WC SET

BS-8I-0-3
BS-8I-0-2
BS-8I-0-2

TP4

BS-8I-0-6
BS-8I-0-2

TP4

BS-8I-0-6
BS-8I-0-2

TP4

DATA ADD -MA

-MA

MA LOAD
If

the BRK

BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

REQ is a

PROGRAM BREAK
REQUEST then:

MA LOAD
JMS -IR

JMS (forced) -IR
INT OK

BS-8I-0-3
BS-8I-0-2
BS-8I-0-7

TP4
E SET

BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

TP4

Execute State entry

-EXECUTE

5-28

Table 5-15
Fetch Cycle, JMP

Instruction, Mechanization Chart

State

Function

Time

Drawing

Generated By

Signal Required

Reference

Pulse

MA+1 -PC

TSl/

Some as AND instruction

TPl

MEM -MB
MEM -IR

MEM5-n -PCS- 11

TS2/
TP2

TS3

Same as AND instruction

MB03=0 then:
MEM ENABLE 5-11
If

TS3 (1)

JMP
B FETCH (1)
MB03 (0)
-PCO-4

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3
BS-8I-0-8

MB04=0 then:

PC ENABLE not generated

MAO-4 - PCO-4

MB04=1 then:

MA ENABLE 0-4

MAO-4 - PCO-4
MEMS- 11 -PCS- 11

TP3

TS4/
TP4

BS-8I-0-4

MEM ENABLE 5-11

BS-8I-C>-4

MB04 (1)
(MEM ENABLE 0-4

BS-8I-0-8

not generated)

BS-8I-0-4

TP3

BS-8I-(>-2

JMP
MB03 (0)
B FETCH (1)

BS-8I-0-3
BS-8I-a-8
BS-8I-0-3

PC LOAD

Same as OPR instruction

5-29

BS-8I-0-6

Table 5-16
Fetch Cycle, lOT Instructions, Mechanization Chart

State

Function

Time

Signol Required

Generated By

Pulse

MA+1 -PC

TSl/
TPl

MEM -MB
MEM -IR

-PAUSE

TS2/
TP2

TS3
TP3

Generate lOPl

Same as AND instruction

-PAUSE

lOPl

lO START

BS-8I-0-2
BS-8I-0-2

lO START

BS-8I-0-2
BS-8I-0-2
BS-8I-&-8

(1)

MBll(l)
Generate IOP2

IOP2 (1)
10 START

MBIO (1)
Generate IOP4

Drawing
Reference

IOP4 (1)
lO START

MB09 (1)

BS-8I-0-2
BS-8I-0-2
BS-8I-0-8
BS-8I-0-2
BS-8I-0-2
BS-8I-0-8

Table 5-17
Execute Cycle, AND Instruction, Mechanization Chart
State

Function

Time

Signal Required

Generated By

MEM -SENSE

MEM -MB

TSl/

NONE

TPl

Operand to Sense

TS2

Drawing
Reference

Pulse

STROBE

BS-8I-0-14
BS-8I-0-13

TS2 (1)

BS-8I-0-4
BS-8I-0-2

MEM ENABLEO-4/5-11
All of the following

NOT true:
KEY DEP, DCA, JMS
and EXECUTE BREAK

5-30

Table 5-17 (Cont)

Execute Cycle, AND Instruction, Mechanization Chart

State

Function

Time

Generated By

Signal Required

Drawing
Reference

Pulse

MEM -MB

TP2

MB LOAD
TP2

AC -MB -^AC

TS3

AC ENABLE

AND ENABLE
AND ENABLE
AND
TS3 (1)
B EXECUTE (1)

AND ENABLE
AND ENABLE
AC -MB -AC

TP3

AC LOAD

B EXECUTE (1)

TS4(1)
F SET

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

AND

-MA

TS4

BRK REQ and
SKIP=0 then:

PC ENABLE

PC+1

-MA

(SKIP=1)

PC ENABLE
TS4 (1)
F SET

PC+1

-MA

CARRY INSERT
SKIP=1

PC ENABLE
Fetch State entry

BS-8I-0-4
BS-8I-0-5
BS-8I-0-5
BS-8I-0-3
BS-8I-0-2
BS-8I-0-3
BS-8I-0-5
BS-8I-0-5
BS-8I-0-6
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

TP3

BS-8I-0-6
BS-8I-0-2

T4
(cent)

TS4

-F

(cont)

SET (Enable)

D SET
E

SET

BREAK OK
SPECIAL CYCLE

5-31

BS-8I-0-4
BS-8I-0-2
BS-8I-(>-3

BS-8I-0-5
BS-8I-0-6
BS-8I-0-4

BS-8I-0-3
BS-8I-0-3
BS-8I-0-3
BS-8I-0-3
BS-8I-(>-3

Table 5-17 (Cont)

Execute Cycle, AND Instruction, Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

PC -MA
PC+1 -*MA

TP4

Drawing
Reference

BRK REQ and
(SKIP=0) then:
(SKIP=1)

MA LOAD

DATA ADD -MA

Break State entry

TS4

TP4

BS-8I-0-6

TP4

BS-8I-(>-2

TS4 (1)

BREAK OK

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

TP4
B SET

BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

If there is a DATA BRK
REQ then:
DATA ENABLE

DATA

cycle

BREAK then:
-B
1

Word Count State
entry

TP4

3 cycle

DATA

BREAK then:
1

-WC
TP4

WC SET
DATA ADD -MA

-MA

MA LOAD
If

the BRK

BS-8I-0-3
BS-8I-0-2
BS-8I-0-2

BS-8I-0-6

TP4

BS-8I-(>-2

TP4

BS-8I-0-6
BS-8I-0-2

REQ is a

PROGRAM BREAK
REQUEST then:

MA LOAD
JMS - IR

JMS (forced) -IR

BS-8I-(>-3

TP4
INT
Execute State entry

BS-8I-(>-2

-EXECUTE
TP4
E SET

5-32

BS-8I-0-7
85-81-0-3
BS-8I-0-2
BS-8I-0-3

Table 5-18

Execute Cycle, TAD Instruction, Mechanization Chart

State

Function

Time

Drawing
Signal Required

Generated By

Reference

Pulse

MEM -SENSE

MEM -MB

TSl

NONE

TP1

Operand to SENSE

TS2

STROBE

BS-8I-0-14
BS-8I-0-13

TS2 (1)

BS-8I-0-4
BS-8I-0-2

MEMENABLEO-4/5-n
All of the following

NOT true:
KEY DP, (DCA V JMS),
EXECUTE, BREAK

MEM -MB
MEM -IR

TP2

MB LOAD

BS-8I-0-6
TP2

AC+MEM -AC

TS3

AC ENABLE
TAD
B EXECUTE (1)

TS3 (1)

MEM ENABLEO-4/5-11
ADD

AC+MEM -AC

TP3

AC LOAD
TAD
TP3

TS4/
TP4

Same as AND instruction
during T4 of EXECUTE

Cycle.

5-33

BS-8I-0-4
BS-8I-0-3
BS-8I-0-3
BS-8I-0-2
BS-8I-&-4
BS-8I-0-4
BS-8I-(>-6

B EXECUTE (1)

BS-8I-0-2

BS-8I-0-3
BS-8I-0-3
BS-8I-0-2

Table 5-19

Execute Cycle, ISZ Instruction, Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

MEM -SENSE

MEM+1 -MB

TSl/

NONE

TPl

Operand to SENSE

TS2

MEM+1 -MB

Drawing
Reference

STROBE

BS- 81- 0-1
BS-8I-0-13

TS2 (1)

BS-8I-0-4
BS-8I-0-2

MEMENABLEO-4/5-11

CARRY INSERT

BS-8I-(>-5

TS2 (1)
ISZ
B EXECUTE (1)

BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

MB=0 after
MEM+1 -MB then:
If

TP2

-SKIP

BS-8I-0-6
TP2

BS-8I-(>-2

B EXECUTE (1)
B EXECUTE (1)

BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

CARRY OUT

BS-8I-(>-8

ISZ

BS-8I-0-2

TP2

BS-8I-0-6
BS-8I-0-2

TS2 (1)

MEM+1 -MB

MB LOAD

TS3/
TP3

TS4/
TP4

NONE

Same as AND instruction
during T4 of EXECUTE

Cycle.

5-34

Table 5-20

Execute Cycle, DCA Instruction, Mechanization Chart

State

Function

Time

Drawing
Signal Required

Generated By

Reference

Pulse

MEM -SENSE

TSl
TP1

No Operations
Operand from memory

BS-SI-O-U

to SENSE

STROBE

AC -MB

TS2

AC ENABLE
TS2 (1)
B EXECUTE (1)

DCA
AC -MB

-AC

TP2

TS3
TP3

MB LOAD

TS4/
TP4

BS-8I-0-6
BS-8I-0-2-

TP3

BS-8I-(>-2

DCA

BS-8I-0-3
BS-8I-0-3

No Operations
AC LOAD

Same as AND instruction
during T4 of EXECUTE
Cycle.

5-35

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

TP2

BS-8I-0-6

B EXECUTE (1)

BS-8I-0-13

Table 5-21
Execute Cycle, JMS Instruction, Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

MEM -SENSE

TSl/

NONE

TPl

Operand to SENSE

STROBE

-MB

TS2

When SKIP=0
PC ENABLE
INT SKIP ENABLE

JMS
When SKIP=1
PC ENABLE

MA+1 -PC

TS3

SKIP (1)
INT SKIP ENABLE

BS-8I-0-5
BS-8I-0-6
BS-8I-0-5

TP2

BS-8I-0-6
BS-8I-0-2

MB LOAD

MA EN ABLE 0-4/5TS3 (1)

JMS
B EXECUTE (1)

CARRY INSERT
TS3 (1)
B

EXECUTE (1)

JMS
MA+1 -PC

TP3

JMS
B EXECUTE (1)

TS4/
TP4

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3
BS-8I-0-5
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

PC LOAD
TP3

Fetch State entry

BS-8I-0-4
BS-8I-0-4
BS-8I-0-3

above)

When SKIP=1
CARRY INSERT

TP2

BS-8I-0-14
BS-8I-0-13

BS-8I-0-4
(as

PC -MB

Drawing
Reference

Same as AND instructic>n
during T4 EXECUTE Cy cle.
1

5-36

BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

Table 5-22
Defer Cycle, JMP Inslruction, Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

MEM -SENSE

TSl

None

TPl

Address from memory
to SENSE

MEM+1 -MB

TS2

STROBE

BS-8I-0-14
BS-8I-0-13

TS2 (1)

BS-8I-0-4
BS-8I-0-2

MEM ENABLEO-4/5-11

[Auto Index]

Drawing
Reference

MEM+1 -MB
CARRY INSERT

[Auto Index]

TS2 (1)

BS-8I-0-5
BS-8I-0-5
BS-8I-0-4
BS-8I-0-2

TP2

BS-8I-0-2
BS-8I-0-2

AUTO INDEX

MEM ENABLEO-4/5-11

MEM -MB
[Auto Index]

TP2

MB LOAD

MEM+1 -MB
[Auto Index]

MEM -IR
T3

TS3/
TP3

MEM+1 -MA
[Auto Index]

TS4

No Operations

(Auto Index)

MEM ENABLEO-4/5-11
TS4(1)

DEFER (1)

JMP

MEM+1 -MA
[AUTO INDEX]

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

CARRY INSERT
BS-8I-0-5

AUTO INDEX

MEM -MA

(AUTO INDEX)

[Auto Index]

MEM ENABLEO-4/5-11
TS4(1)

DEFER (1)

JMP

5-37

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

Table 5-22 (Cont)
Defer Cycle, JMP Instruction, Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

Execute State entry

TS4

-EXECUTE (Enable)

JMP
DEFER (1)

MEM+1 -MA

TP4

Drawing
Reference

BS-8I-0-3
BS-8I-0-3
BS-8I-0-3

(AUTO INDEX/AUTO
INDEX)

MA LOAD

BS-8I-0-6

TP4
Execute State entry

BS-8I-(>-2

-EXECUTE (Set)

BS-8I-0-3

TP4

BS-8I-(>-2

Table 5-23
Defer Cycle, JMP Instruction, Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

MEM -SENSE

TS1/
TPl

Address from memory
to SENSE

STROBE

MEM+1 -MB
[AUTO INDEX]

MEM -MB

Drawing
Reference

TS2

BS-8I-0-14
BS-8I-0-13

Same as JMP instruction

TP2

[AUTO INDEX]

MEM+1 -PC

TS3

[Auto Index]

MEMENABLEO-4/5-11
TS3

(1)

DEFER (1)

JMP

5-38

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-3

Table 5-23 (Cont)
Defer Cycle, JMP Instruction, Mechanization Chart

State

Function

Time

Generated By

Signal Required

Drawing
Reference

Pulse

CARRY INSERT

MEM+1 -PC

AUTO INDEX

MEM -PC

[AUTO INDEX]

MEM ENABLEO-4/5-11
TS3 (1)

DEFER (1)

JMP

MEM+1 -PC

TP3

MEM -PC

PC LOAD

JMP

TS4

DEFER (1)

BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

TS4(1 )
F SET

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

BRK REQ and
SKIP=0 then:
If

PC ENABLE

PC+1 -

(SKIP-1)

PC ENABLE
TS
F

PC+1

-MA

(1)

SET

CARRY INSERT
SKIP==1

PC ENABLE

Fetch State entry

T4
(cont)

TS4

-F

(cont)

SET (Enable)

TP4

BS-8I-0-5
BS-8I-0-6
BS-8I-0-4

BREAK OK
SPECIAL CYCLE

TP4

BS-8I-0-2

-MA
PC+1 -MA

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

BS-8I-0-3
BS-8I-0-3
BS-8I-0-3
BS-8I-0-3
BS-8I-0-3

D SET

BS-8I-&-4
BS-8I-0-2
BS-8I-a-3
BS-8I-0-3

BS-8I-0-6

TP3

PC -MA

BS-8I-0-5
BS-8I-0-5

SET

BRK REQ and
(SKIP=0) then
(SKIP=1)

MA LOAD

5-39

BS-8I--0-6

Table 5-23 (Cont)
Defer Cycle, JMP InstrucHon, Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

DATA ADD -MA

If there is a DATA BRK
REQ then:
DATA ENABLE

TS4

BREAK OK

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

TP4

BS-8I-0-3
BS-8I-0-2

BSET

BS-8I-(>-3

TP4

WC SET

BS-8I-0-3
BS-8I-a-2
BS-8I-0-2

TP4

BS-8I-0-6
BS-8I-0-2

TP4

BS-8I-0-6
BS-8I-0-2

TS4 (1)

Break State entry

Drawing
Reference

TP4

cycle DATA

BREAK then:
1

-B

Word Count State

Entry

BREAK then:
1

DATA ADD -*MA

-MA

3 cycle

DATA

-WC

MA LOAD
If

the BRK REQ is a

PROGRAM BREAK
REQUEST then:

MA LOAD
JMS -IR

JMS (forced) -IR
INT OK

BS-8I-0-3
BS-8I-0-2
BS-8I-0-7

TP4
E SET

BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

TP4

Execute State entry

-EXECUTE

5-40

Table 5-24
Mechanization Chart
Count
Cycle,
Word

State

Time

Function

Signal Required

Generated By

Drawing
Reference

Pulse

TSl/
TPl

MEM -MB

TS2

NONE

If CA INCREMENT then:
MEMENABLEO-4/5-11

TS2 (1)

MEM+1 -MB

TS2

If CA INCREMENT then
MEMENABLEO-4/5-11

BS-8I-0-4
BS-8I-0-2

BS-8I-0-4
As above

CARRY INSERT

MEM+1 -MB

BS-8I-0-5

CURRENT ADDRESS (1) BS-8I-0-3
BS-8I-0-5
CA INCREMENT

MEM -MB

TP2

MB LOAD

MEM+1 -MB
TP2

TS3/

TP3

MEM+1 -MA

TS4

NONE
If

CA INCREMENT then:

MEM ENABLEO-4/5-11
TS4 (1)

CURRENT ADDRESS (1)

MEM+1 -MA

BS-8I-0-6
BS-8I-0-2

CARRY INSERT

BS-8I-0-4
BS-8I-a-2
BS-8I-0-3
BS-8I-0-5

CURRENT ADDRESS (1) BS-8I-0-3
BS-8I-0-5
CA INCREMENT
If CA INCREMENT then:
MEMENABLEO-4/5-11

MEM -MA

BS-8I-0-4
As above

MEM+1 -MA

TP4

MA LOAD

MEM -MA
TP4

TP4

Break State entry

-B
TP4

BSET

±
NOTE

ALL instructions suspended.

(The first cycle of the 3-cycle Break)

5-41

BS-8I-0-6
65-81-0-2
BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

Table 5-25
Current Address Cycle, Mechanization Chart

State

Function

Time

Signal Required

Generated By

TSl/

NONE

TPl

MEM -MB

TS2

CA INCREMENT then:

MEM ENABLEO-4/5-11
TS2 (1)

MEM+1 -MB

Drawing
Reference

Pulse

TS2

BS-8I-0-4
BS-8I-0-2

CA INCREMENT then

MEM ENABLEO-4/5-11

BS-8I-0-4
As above

MEM+1 -MB

CARRY INSERT

BS-8I-0-5

CURRENT ADDRESS (1) BS-8I-0-3
CA INCREMENT
BS-8I-0-5

MEM -MB

MB LOAD

TP2

MEM+1 -MB

BS-8I-0-6
BS-8I-0-2

TS3/

NONE

TP3

MEM+1 -MA

TS4

CA INCREMENT then:

MEM ENABLEO-4/5-11
TS4(1)

CURRENT ADDRESS (1)

MEM+1 -MA

CARRY INSERT

CURRENT ADDRESS (1)

CA INCREAv\ENT

MEM -MA

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3
BS-8I-0-5
BS-8I-0-3
BS-8I-0-5

CA INCREMENT then:

MEM ENABLEO-4/5-11

BS-8I-0-4
As above

MEM+1 -MA

TP4

MEM -MA

MA LOAD
TP4

Break State entry

TP4

-B
TP4

BSET

NOTE

ALL Instructions (2nd cycle of 3-cycle Break)

5-42

BS-8I-0-6
BS-8I-0-2
BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

Table 5-26
Break Cycle Mechanization Chart

State

Time

Function

Generated By

Signal Required

Drawing
Reference

Pulse

TSl/
TPl

DATA -MB

TS2

NONE

DATA IN then:
DATA ENABLE

BS-8I-0-4
TS2(1)

BS-8I-(>-2

DATA IN

BS-8I-0-4

BREAK (1)

BS-8I-(>-3

TS2 (1)

BS-8I-0-4
BS-8I-0-2

If DATA OUT then:
MEMENABLEO-4/5-11

MEM -MB

MEM+1 -MB

MEM INCREMENT

then:

MEMENABLEO-4/5-11

BS-8I-0-4
As above

MEM+1 -MB

CARRY INSERT

BREAK (1)

BS-8I-0-5
BS-8I-0-2
BS-8I-0-10
BS-8I-0-3

TP2

BS-8I-0-6
BS-8I-0-2

TS4 (1 )
F SET

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

TS4 (1)
F SET

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

TS2 (1)

MEMORY INCREMENT
DATA -MB

TP2

MB LOAD

MEM -MB
MEM+1 -MB

PC -MA

TS4

If BRK REG and
SKIP=0 then:

PC ENABLE

PC+1

-MA

(SKIP-1)

PC ENABLE

NOTE

ALL Instructions suspended (Third cycle of 3-cycle Break)

5-43

Table 5-26 (Cont)
Break Cycle Mechanization Chart

State

Function

Time

Signal Required

Generated By

Pulse

PC+1 -MA

FETCH STATE entry

CARRY INSERT

-F

SET (Enable)

TS4

SKIP-1

BS-8I-0-5
B5-8I-0-6

PC ENABLE

BS-8I-(>-4

DSET

BS-8I-C>-3

SET

BREAK OK
SPECIAL CYCLE

BS-8I-0-3
BS-8I-0-3
BS-8I-0-3

TP4

BS-8I-C>-2

TS4(1)

BREAK OK

BS-8I-0-4
BS-8I-0-2
BS-8I-0-3

TP4
B SET

BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

BS-8I-0-3
E

PC -MA

TP4

PC+1 -MA

Drawing
Reference

BRK REQ and

(SKIP=0) then:
(SKIP=1)

MA LOAD

DATA ADD -MA

TS4

BS-8I-0-6

there is a DATA

BRK REQ then:

DATA ENABLE

BREAK STATE entry

TP4

cycle DATA

BREAK then:
1

WORD COUNT STATE
entry

-B

3 cycle DATA

BREAK then:
1

-WC

WC SET

BS-8I-0-3
BS-8I-0-2
BS-8I-0-2

TP4

BS-8I-0-6
BS-8I-0-2

TP4

DATA ADD -MA

NOTE

MA LOAD

ALL Instructions suspended (Third cycle of 3-cycle Break)

5-44

Table 5-26 (Cont)
Break Cycle Mechanization Chart

State

Time

Function

Generated By

Signal Required

Drawing
Reference

Pulse

-MA

the BRK

REQ is a

PROGRAM BREAK
REQUEST then:

MA LOAD

BS-8I-0-6
BS-8I-0-2

TP4

JMS (forced) -IR

JMS -IR

TP4

INT OK

EXECUTE STATE entry

-EXECUTE
TP4
E SET

NOTE

BS-8I-0-3
BS-8I-0-2
BS-8I-0-7
BS-8I-0-3
BS-8I-0-2
BS-8I-0-3

ALL Instructions suspended (Third cycle of 3-cycle Break)

5.9 Table 5-27 provides maintenance personnel
with a reference to the origin of selected signals
generated within the PDP-8/l. The signal name
appears in the left column, exactly as it is shown
on the engineering drawings. The specific drawing upon which that signal is generated appears

AND
AND
AND ENABLE
ASR ENAB LE
ASR L SET

AUTO INDEX
B EAE

in the right column.

D-BS- 81-0-3
D-BS- •81-0-3
D-BS- •81-0-5
D-BS- KE8I-0-2
D-BS- KE8I-0-2
D-BS- 81-0-5
D-BS- KE8I-0-2
D-BS- 81-0-3
D-BS- 81-0-3
D-BS- 81-0-13
D-BS- 81-0-13
D-BS- 81-0-13
D-BS- •81-0-13

B EXECUTE (1)
B FETCH (1)

Table 5-27

B FIELD (0)

Signal Origins

B FIELD (1)

B INHIBIT
Signal

AC CLEAR
AC ENABLE
AC ENABLE
AC LOAD
AC -MQ ENABLE
AC - MQ ENABLE
ADD
ADD ACCEPTED
ADDER L
ADDER L

Drawing No.

MEM ENABLE
BSET
BREAK
BREAK OK
BREAK OK

D-BS-8I-0-4
D-BS-8I-0-4
D-BS-8I-0-4
D-BS-8I-0-6
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-8I-0-4
D-BS-8I-0-7
D-BS-8I-0-8
D-BS-KE8I-0-3

5-45

D-BS- 81-0-3
D-BS- 81-0-3

CARRY INSERT
CURRENT ADDRESS
D SET
D SET

DATA ADD ENABLE
DATA ENABLE
DCA

D-BS- 81-0-3
D-BS- -81-0-3
D-BS- -81-0-5
D-BS- 81-0-3
D-BS- -81-0-3
D-BS' -81-0-3
D-BS' -81-0-4
D-BS -81-0-4

D-BS -81-0-3

Signal

DCA
DEFER
DIV LAST
DIV LAST

DOUBLE LEFT ROTATE
DOUBLE RIGHT ROTATE
DVI
DVI
EA£ AC ENABLE
EAE AC ENABLE
EAE BEGIN
EAE COMPLETE
EAE E SET
EAE END
EAE EXECUTE
EAE INST
EAE IRO
EAE IR1
EAE IR2
EAE L DISABLE
EAE LEFT SHIFT ENABLE
EAE MEM ENABLE
EAE MQ
ENABLE
EAE MQ
ENABLE
EAE NO SHIFT ENABLE
EAE ON (0)
EAE ON (1)
EAE RIGHT SHIFT ENABLE
EAE RUN (1)
EAE SET
EAE START

EAETG(l)
EAETP
EAE TP
E SET

EXECUTE
F

SET

FSET
FETCH
FIELD (0)
FIELD (1)

I/O ENABLE
I/O END
I/O END
I/O START

Drawing No.

Signal

D-BS-8I-0-3
D-BS- 81-0-3
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-8I-0-5
D-BS-8I-0-5
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-13
D-BS-8I-0-13
D-B5-8I-0-4
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2

I/O STROBE
INHIBIT
INITIALIZE
INITIALIZE

INT DELAY
INIT ENABLE

INT OK
INT OK
INT SKIP ENABLE
INT STROBE
INT SYNC
lOP
1

IOP2
IOP4
lOT
lOT
ISZ
ISZ
J

JMP
J

JMS
KEY CONT
KEY DP
KEY EX + DP
KEY LA
KEY SI + STOP
KEY ST
KEYSS
L ENABLE
L ENABLE
LEFT SHIFT
LEFT SHIFT

MA ENABLE 0-4
MA ENABLE 5-11
MA LOAD
MANUAL PRESET
MB LOAD
MB -SC ENABLE

MEM BEGIN
MEM DONE
MEM ENABLE 0-4
MEM ENABLE 5-11
MEM ENABLE
MEM FINISH

5-46

Drawing No.

D-BS-8I-0-2
D-BS-8I-0-13
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-7
D-BS-8I-0-7
L)-BS-8I-0-7

D-BS-8I-0-7
D-BS-8I-0-4
D-BS-8I-0-2
D-BS-8I-0-7
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-4
D-BS-8I-0-4
D-BS-8I-0-5
D-BS-KE8I-0-3
D-BS-8I-0-4
D-BS-8I-0-4
D-BS-8I-0-6
D-BS-8I-0-2
D-BS-8I-0-6
D-BS-KE8I-0-2
D-BS-8I-0-13
D-BS-8I-0-13
D-BS-8I-0-4
D-BS-8I-0-4
D-BS-8I-0-13
D-BS-8I-0-13

Signal

MEM START
MFTPO
MFTP1
MFTP2

MFTSO
MFTSO
MFTS1

MFTS3

MQOO-MQll

MQ ENABLE
MQ LOAD
MQ and LOW AC =
MUY
MUY
MUY + DVI
NMI
NMI

NORM
NORM
NO SHIFT
OPl
OP2

OPR
OPR
PAUSE
PC ENABLE
PC ENABLE
PC LOAD

POWER CLEAR
POWER OK
PROCESSOR lOT
PC INCREMENT
READ
RIGHT SHIFT

Drawing No.

D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-KE8I-0-3
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-8I-0-5
D-BS- 81-0-5
D-BS-8I-0-4
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-2
D-BS-8I-0-4
D-BS-8I-0-4
D-BS-8I-0-6
D-BS-8I-0-13
D-BS-8I-0-13
D-BS-8I-0-7
D-BS-8I-0-5
D-BS-8I-0-13
D-BS-8I-0-5

Drawing No

Signal

RUN
SC 0-3 =
SC 0-3 SCO - SC4

SC-0
SC ENABLE
SC FULL
SCL
SC LOAD

SHUTDOWN
SKIP

SLOW CYCLE
SLOW CYCLE
SPECIAL CYCLE
SR ENABLE

STOP OK
STROBE
STROBE FIELD
STROBE FIELD

TAD
TAD
TPl

TP2
TP3
TP4
TSl

TS2
TS3
TS4

WC OVERFLOW
WC SET
WORD COUNT
WRITE

5-47

D-BS-8I-0-2
D-BS-KE8I-0-3
D-BS-KE8I-0-3
D-BS-KE8I-0-3
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-KE8I-0-3
D-BS-KE8I-0-2
D-BS-KE8I-0-2
D-BS-8I-0-13
D-BS-8I-0-6
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-3
D-BS-8I-0-4
D-BS-8I-0-13
D-BS-8I-0-13
D-BS-8I-0-13
D-BS-8I-0-13
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-2
D-BS-8I-0-7
D-BS-8I-0-3
D-BS-8I-0-3
D-BS-8I-0-13